From 702723b9f9c6db9e579f10001abd86ad1283e312 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 28 Sep 2020 11:34:44 +0000 Subject: [PATCH] cut out core for now to focus on ioring --- experiments9/non_generated/ls180.il | 497802 +++++++------------------ 1 file changed, 130727 insertions(+), 367075 deletions(-) diff --git a/experiments9/non_generated/ls180.il b/experiments9/non_generated/ls180.il index 5eea29a..107e41d 100644 --- a/experiments9/non_generated/ls180.il +++ b/experiments9/non_generated/ls180.il @@ -1,3032 +1,4290 @@ -# Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 3.8.1-24 -fPIC -Os) -autoidx 13726 -attribute \src "issuer_ls180.v:5.1-330.10" +# Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 9.0.1-12 -fPIC -Os) +autoidx 3705 +attribute \src "libresoc.v:5.1-277.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec19" +attribute \nmigen.hierarchy "test_issuer.jtag._fsm" attribute \generator "nMigen" -module \ALU_dec19 - attribute \src "issuer_ls180.v:279.3-288.6" - wire width 3 $0\ALU_dec19_cr_in[2:0] - attribute \src "issuer_ls180.v:289.3-298.6" - wire width 3 $0\ALU_dec19_cr_out[2:0] - attribute \src "issuer_ls180.v:319.3-328.6" - wire width 2 $0\ALU_dec19_cry_in[1:0] - attribute \src "issuer_ls180.v:219.3-228.6" - wire $0\ALU_dec19_cry_out[0:0] - attribute \src "issuer_ls180.v:189.3-198.6" - wire width 12 $0\ALU_dec19_function_unit[11:0] - attribute \src "issuer_ls180.v:259.3-268.6" - wire width 3 $0\ALU_dec19_in1_sel[2:0] - attribute \src "issuer_ls180.v:269.3-278.6" - wire width 4 $0\ALU_dec19_in2_sel[3:0] - attribute \src "issuer_ls180.v:249.3-258.6" - wire width 7 $0\ALU_dec19_internal_op[6:0] - attribute \src "issuer_ls180.v:199.3-208.6" - wire $0\ALU_dec19_inv_a[0:0] - attribute \src "issuer_ls180.v:209.3-218.6" - wire $0\ALU_dec19_inv_out[0:0] - attribute \src "issuer_ls180.v:229.3-238.6" - wire $0\ALU_dec19_is_32b[0:0] - attribute \src "issuer_ls180.v:299.3-308.6" - wire width 4 $0\ALU_dec19_ldst_len[3:0] - attribute \src "issuer_ls180.v:309.3-318.6" - wire width 2 $0\ALU_dec19_rc_sel[1:0] - attribute \src "issuer_ls180.v:239.3-248.6" - wire $0\ALU_dec19_sgn[0:0] - attribute \src "issuer_ls180.v:6.7-6.20" +module \_fsm + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $0\fsm_state$next[3:0]$25 + attribute \src "libresoc.v:91.3-92.35" + wire width 4 $0\fsm_state[3:0] + attribute \src "libresoc.v:6.7-6.20" wire $0\initial[0:0] - attribute \src "issuer_ls180.v:279.3-288.6" - wire width 3 $1\ALU_dec19_cr_in[2:0] - attribute \src "issuer_ls180.v:289.3-298.6" - wire width 3 $1\ALU_dec19_cr_out[2:0] - attribute \src "issuer_ls180.v:319.3-328.6" - wire width 2 $1\ALU_dec19_cry_in[1:0] - attribute \src "issuer_ls180.v:219.3-228.6" - wire $1\ALU_dec19_cry_out[0:0] - attribute \src "issuer_ls180.v:189.3-198.6" - wire width 12 $1\ALU_dec19_function_unit[11:0] - attribute \src "issuer_ls180.v:259.3-268.6" - wire width 3 $1\ALU_dec19_in1_sel[2:0] - attribute \src "issuer_ls180.v:269.3-278.6" - wire width 4 $1\ALU_dec19_in2_sel[3:0] - attribute \src "issuer_ls180.v:249.3-258.6" - wire width 7 $1\ALU_dec19_internal_op[6:0] - attribute \src "issuer_ls180.v:199.3-208.6" - wire $1\ALU_dec19_inv_a[0:0] - attribute \src "issuer_ls180.v:209.3-218.6" - wire $1\ALU_dec19_inv_out[0:0] - attribute \src "issuer_ls180.v:229.3-238.6" - wire $1\ALU_dec19_is_32b[0:0] - attribute \src "issuer_ls180.v:299.3-308.6" - wire width 4 $1\ALU_dec19_ldst_len[3:0] - attribute \src "issuer_ls180.v:309.3-318.6" - wire width 2 $1\ALU_dec19_rc_sel[1:0] - attribute \src "issuer_ls180.v:239.3-248.6" - wire $1\ALU_dec19_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \ALU_dec19_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 6 \ALU_dec19_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 9 \ALU_dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 12 \ALU_dec19_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \ALU_dec19_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \ALU_dec19_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 4 \ALU_dec19_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \ALU_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \ALU_dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 11 \ALU_dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 13 \ALU_dec19_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 7 \ALU_dec19_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \ALU_dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 14 \ALU_dec19_sgn - attribute \src "issuer_ls180.v:6.7-6.15" + attribute \src "libresoc.v:97.3-124.6" + wire $0\isdr$next[0:0]$21 + attribute \src "libresoc.v:93.3-94.25" + wire $0\isdr[0:0] + attribute \src "libresoc.v:240.3-267.6" + wire $0\isir$next[0:0]$38 + attribute \src "libresoc.v:95.3-96.25" + wire $0\isir[0:0] + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $10\fsm_state$next[3:0]$35 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $11\fsm_state$next[3:0]$36 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $1\fsm_state$next[3:0]$26 + attribute \src "libresoc.v:46.13-46.29" + wire width 4 $1\fsm_state[3:0] + attribute \src "libresoc.v:97.3-124.6" + wire $1\isdr$next[0:0]$22 + attribute \src "libresoc.v:51.7-51.18" + wire $1\isdr[0:0] + attribute \src "libresoc.v:240.3-267.6" + wire $1\isir$next[0:0]$39 + attribute \src "libresoc.v:56.7-56.18" + wire $1\isir[0:0] + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $2\fsm_state$next[3:0]$27 + attribute \src "libresoc.v:97.3-124.6" + wire $2\isdr$next[0:0]$23 + attribute \src "libresoc.v:240.3-267.6" + wire $2\isir$next[0:0]$40 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $3\fsm_state$next[3:0]$28 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $4\fsm_state$next[3:0]$29 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $5\fsm_state$next[3:0]$30 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $6\fsm_state$next[3:0]$31 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $7\fsm_state$next[3:0]$32 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $8\fsm_state$next[3:0]$33 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $9\fsm_state$next[3:0]$34 + attribute \src "libresoc.v:75.17-75.110" + wire $eq$libresoc.v:75$1_Y + attribute \src "libresoc.v:76.18-76.111" + wire $eq$libresoc.v:76$2_Y + attribute \src "libresoc.v:77.18-77.111" + wire $eq$libresoc.v:77$3_Y + attribute \src "libresoc.v:78.18-78.111" + wire $eq$libresoc.v:78$4_Y + attribute \src "libresoc.v:79.18-79.111" + wire $eq$libresoc.v:79$5_Y + attribute \src "libresoc.v:80.17-80.108" + wire $eq$libresoc.v:80$6_Y + attribute \src "libresoc.v:81.18-81.111" + wire $eq$libresoc.v:81$7_Y + attribute \src "libresoc.v:82.18-82.111" + wire $eq$libresoc.v:82$8_Y + attribute \src "libresoc.v:83.18-83.111" + wire $eq$libresoc.v:83$9_Y + attribute \src "libresoc.v:84.18-84.111" + wire $eq$libresoc.v:84$10_Y + attribute \src "libresoc.v:85.18-85.111" + wire $eq$libresoc.v:85$11_Y + attribute \src "libresoc.v:86.18-86.111" + wire $eq$libresoc.v:86$12_Y + attribute \src "libresoc.v:87.18-87.112" + wire $eq$libresoc.v:87$13_Y + attribute \src "libresoc.v:88.17-88.108" + wire $eq$libresoc.v:88$14_Y + attribute \src "libresoc.v:89.17-89.108" + wire $eq$libresoc.v:89$15_Y + attribute \src "libresoc.v:90.17-90.108" + wire $eq$libresoc.v:90$16_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:60" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:83" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:88" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:91" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:96" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:99" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:108" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:117" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 9 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 10 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire output 11 \capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" + wire width 4 \fsm_state + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" + wire width 4 \fsm_state$next + attribute \src "libresoc.v:6.7-6.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 10 \opcode_switch - attribute \src "issuer_ls180.v:189.3-198.6" - process $proc$issuer_ls180.v:189$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire output 1 \isdr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire \isdr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire output 4 \isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire \isir$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:50" + wire \local_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" + wire output 8 \negjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" + wire output 6 \negjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire output 7 \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire output 5 \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:37" + wire \rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire output 2 \shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:27" + wire output 3 \update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" + cell $eq $eq$libresoc.v:75$1 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:75$1_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" + cell $eq $eq$libresoc.v:76$2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:76$2_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:60" + cell $eq $eq$libresoc.v:77$3 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:77$3_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:68" + cell $eq $eq$libresoc.v:78$4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'1 + connect \Y $eq$libresoc.v:78$4_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" + cell $eq $eq$libresoc.v:79$5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:79$5_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" + cell $eq $eq$libresoc.v:80$6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 1'0 + connect \Y $eq$libresoc.v:80$6_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" + cell $eq $eq$libresoc.v:81$7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:81$7_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:83" + cell $eq $eq$libresoc.v:82$8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:82$8_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:88" + cell $eq $eq$libresoc.v:83$9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'1 + connect \Y $eq$libresoc.v:83$9_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:91" + cell $eq $eq$libresoc.v:84$10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:84$10_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:96" + cell $eq $eq$libresoc.v:85$11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'1 + connect \Y $eq$libresoc.v:85$11_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:99" + cell $eq $eq$libresoc.v:86$12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:86$12_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:108" + cell $eq $eq$libresoc.v:87$13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:87$13_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" + cell $eq $eq$libresoc.v:88$14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 2'11 + connect \Y $eq$libresoc.v:88$14_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" + cell $eq $eq$libresoc.v:89$15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 3'101 + connect \Y $eq$libresoc.v:89$15_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:117" + cell $eq $eq$libresoc.v:90$16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 4'1000 + connect \Y $eq$libresoc.v:90$16_Y + end + attribute \src "libresoc.v:125.3-239.6" + process $proc$libresoc.v:125$24 assign { } { } assign { } { } - assign $0\ALU_dec19_function_unit[11:0] $1\ALU_dec19_function_unit[11:0] - attribute \src "issuer_ls180.v:190.5-190.29" + assign $0\fsm_state$next[3:0]$25 $1\fsm_state$next[3:0]$26 + attribute \src "libresoc.v:126.5-126.29" switch \initial - attribute \src "issuer_ls180.v:190.9-190.17" + attribute \src "libresoc.v:126.9-126.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $2\fsm_state$next[3:0]$27 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:60" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$next[3:0]$27 4'0001 + case + assign $2\fsm_state$next[3:0]$27 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $3\fsm_state$next[3:0]$28 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:68" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$next[3:0]$28 4'0010 + case + assign $3\fsm_state$next[3:0]$28 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $4\fsm_state$next[3:0]$29 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[3:0]$29 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\fsm_state$next[3:0]$29 4'0100 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $5\fsm_state$next[3:0]$30 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[3:0]$30 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $5\fsm_state$next[3:0]$30 4'0000 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $6\fsm_state$next[3:0]$31 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:83" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\fsm_state$next[3:0]$31 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $6\fsm_state$next[3:0]$31 4'0110 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $7\fsm_state$next[3:0]$32 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:88" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\fsm_state$next[3:0]$32 4'0110 + case + assign $7\fsm_state$next[3:0]$32 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $8\fsm_state$next[3:0]$33 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:91" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\fsm_state$next[3:0]$33 4'0111 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $8\fsm_state$next[3:0]$33 4'1000 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $9\fsm_state$next[3:0]$34 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:96" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\fsm_state$next[3:0]$34 4'1001 + case + assign $9\fsm_state$next[3:0]$34 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $10\fsm_state$next[3:0]$35 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:99" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\fsm_state$next[3:0]$35 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $10\fsm_state$next[3:0]$35 4'1000 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 assign { } { } - assign $1\ALU_dec19_function_unit[11:0] 12'000000000010 + assign $1\fsm_state$next[3:0]$26 $11\fsm_state$next[3:0]$36 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:108" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\fsm_state$next[3:0]$36 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $11\fsm_state$next[3:0]$36 4'0010 + end case - assign $1\ALU_dec19_function_unit[11:0] 12'000000000000 + assign $1\fsm_state$next[3:0]$26 \fsm_state end sync always - update \ALU_dec19_function_unit $0\ALU_dec19_function_unit[11:0] + update \fsm_state$next $0\fsm_state$next[3:0]$25 end - attribute \src "issuer_ls180.v:199.3-208.6" - process $proc$issuer_ls180.v:199$2 + attribute \src "libresoc.v:240.3-267.6" + process $proc$libresoc.v:240$37 assign { } { } assign { } { } - assign $0\ALU_dec19_inv_a[0:0] $1\ALU_dec19_inv_a[0:0] - attribute \src "issuer_ls180.v:200.5-200.29" + assign $0\isir$next[0:0]$38 $1\isir$next[0:0]$39 + attribute \src "libresoc.v:241.5-241.29" switch \initial - attribute \src "issuer_ls180.v:200.9-200.17" + attribute \src "libresoc.v:241.9-241.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\isir$next[0:0]$39 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\isir$next[0:0]$39 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\isir$next[0:0]$39 $2\isir$next[0:0]$40 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\isir$next[0:0]$40 1'1 + case + assign $2\isir$next[0:0]$40 \isir + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 assign { } { } - assign $1\ALU_dec19_inv_a[0:0] 1'0 + assign $1\isir$next[0:0]$39 1'0 case - assign $1\ALU_dec19_inv_a[0:0] 1'0 + assign $1\isir$next[0:0]$39 \isir end sync always - update \ALU_dec19_inv_a $0\ALU_dec19_inv_a[0:0] + update \isir$next $0\isir$next[0:0]$38 end - attribute \src "issuer_ls180.v:209.3-218.6" - process $proc$issuer_ls180.v:209$3 - assign { } { } + attribute \src "libresoc.v:46.13-46.29" + process $proc$libresoc.v:46$42 assign { } { } - assign $0\ALU_dec19_inv_out[0:0] $1\ALU_dec19_inv_out[0:0] - attribute \src "issuer_ls180.v:210.5-210.29" - switch \initial - attribute \src "issuer_ls180.v:210.9-210.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\ALU_dec19_inv_out[0:0] 1'0 - case - assign $1\ALU_dec19_inv_out[0:0] 1'0 - end + assign $1\fsm_state[3:0] 4'0000 sync always - update \ALU_dec19_inv_out $0\ALU_dec19_inv_out[0:0] + sync init + update \fsm_state $1\fsm_state[3:0] end - attribute \src "issuer_ls180.v:219.3-228.6" - process $proc$issuer_ls180.v:219$4 - assign { } { } + attribute \src "libresoc.v:51.7-51.18" + process $proc$libresoc.v:51$43 assign { } { } - assign $0\ALU_dec19_cry_out[0:0] $1\ALU_dec19_cry_out[0:0] - attribute \src "issuer_ls180.v:220.5-220.29" - switch \initial - attribute \src "issuer_ls180.v:220.9-220.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\ALU_dec19_cry_out[0:0] 1'0 - case - assign $1\ALU_dec19_cry_out[0:0] 1'0 - end + assign $1\isdr[0:0] 1'0 sync always - update \ALU_dec19_cry_out $0\ALU_dec19_cry_out[0:0] + sync init + update \isdr $1\isdr[0:0] end - attribute \src "issuer_ls180.v:229.3-238.6" - process $proc$issuer_ls180.v:229$5 + attribute \src "libresoc.v:56.7-56.18" + process $proc$libresoc.v:56$44 assign { } { } + assign $1\isir[0:0] 1'0 + sync always + sync init + update \isir $1\isir[0:0] + end + attribute \src "libresoc.v:6.7-6.20" + process $proc$libresoc.v:6$41 assign { } { } - assign $0\ALU_dec19_is_32b[0:0] $1\ALU_dec19_is_32b[0:0] - attribute \src "issuer_ls180.v:230.5-230.29" - switch \initial - attribute \src "issuer_ls180.v:230.9-230.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\ALU_dec19_is_32b[0:0] 1'0 - case - assign $1\ALU_dec19_is_32b[0:0] 1'0 - end + assign $0\initial[0:0] 1'0 sync always - update \ALU_dec19_is_32b $0\ALU_dec19_is_32b[0:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "issuer_ls180.v:239.3-248.6" - process $proc$issuer_ls180.v:239$6 + attribute \src "libresoc.v:91.3-92.35" + process $proc$libresoc.v:91$17 assign { } { } + assign $0\fsm_state[3:0] \fsm_state$next + sync posedge \local_clk + update \fsm_state $0\fsm_state[3:0] + end + attribute \src "libresoc.v:93.3-94.25" + process $proc$libresoc.v:93$18 assign { } { } - assign $0\ALU_dec19_sgn[0:0] $1\ALU_dec19_sgn[0:0] - attribute \src "issuer_ls180.v:240.5-240.29" - switch \initial - attribute \src "issuer_ls180.v:240.9-240.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\ALU_dec19_sgn[0:0] 1'0 - case - assign $1\ALU_dec19_sgn[0:0] 1'0 - end - sync always - update \ALU_dec19_sgn $0\ALU_dec19_sgn[0:0] + assign $0\isdr[0:0] \isdr$next + sync posedge \local_clk + update \isdr $0\isdr[0:0] + end + attribute \src "libresoc.v:95.3-96.25" + process $proc$libresoc.v:95$19 + assign { } { } + assign $0\isir[0:0] \isir$next + sync posedge \local_clk + update \isir $0\isir[0:0] end - attribute \src "issuer_ls180.v:249.3-258.6" - process $proc$issuer_ls180.v:249$7 + attribute \src "libresoc.v:97.3-124.6" + process $proc$libresoc.v:97$20 assign { } { } assign { } { } - assign $0\ALU_dec19_internal_op[6:0] $1\ALU_dec19_internal_op[6:0] - attribute \src "issuer_ls180.v:250.5-250.29" + assign $0\isdr$next[0:0]$21 $1\isdr$next[0:0]$22 + attribute \src "libresoc.v:98.5-98.29" switch \initial - attribute \src "issuer_ls180.v:250.9-250.17" + attribute \src "libresoc.v:98.9-98.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 assign { } { } - assign $1\ALU_dec19_internal_op[6:0] 7'0100100 - case - assign $1\ALU_dec19_internal_op[6:0] 7'0000000 - end - sync always - update \ALU_dec19_internal_op $0\ALU_dec19_internal_op[6:0] + assign $1\isdr$next[0:0]$22 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\isdr$next[0:0]$22 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\isdr$next[0:0]$22 $2\isdr$next[0:0]$23 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\isdr$next[0:0]$23 1'1 + case + assign $2\isdr$next[0:0]$23 \isdr + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\isdr$next[0:0]$22 1'0 + case + assign $1\isdr$next[0:0]$22 \isdr + end + sync always + update \isdr$next $0\isdr$next[0:0]$21 + end + connect \$9 $eq$libresoc.v:75$1_Y + connect \$11 $eq$libresoc.v:76$2_Y + connect \$13 $eq$libresoc.v:77$3_Y + connect \$15 $eq$libresoc.v:78$4_Y + connect \$17 $eq$libresoc.v:79$5_Y + connect \$1 $eq$libresoc.v:80$6_Y + connect \$19 $eq$libresoc.v:81$7_Y + connect \$21 $eq$libresoc.v:82$8_Y + connect \$23 $eq$libresoc.v:83$9_Y + connect \$25 $eq$libresoc.v:84$10_Y + connect \$27 $eq$libresoc.v:85$11_Y + connect \$29 $eq$libresoc.v:86$12_Y + connect \$31 $eq$libresoc.v:87$13_Y + connect \$3 $eq$libresoc.v:88$14_Y + connect \$5 $eq$libresoc.v:89$15_Y + connect \$7 $eq$libresoc.v:90$16_Y + connect \update \$7 + connect \shift \$5 + connect \capture \$3 + connect \rst \$1 + connect \local_clk \TAP_bus__tck + connect \negjtag_rst \rst + connect \negjtag_clk \TAP_bus__tck + connect \posjtag_rst \rst + connect \posjtag_clk \TAP_bus__tck +end +attribute \src "libresoc.v:281.1-392.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.jtag._idblock" +attribute \generator "nMigen" +module \_idblock + attribute \src "libresoc.v:365.3-385.6" + wire width 32 $0\TAP_id_sr$next[31:0]$63 + attribute \src "libresoc.v:363.3-364.35" + wire width 32 $0\TAP_id_sr[31:0] + attribute \src "libresoc.v:282.7-282.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:365.3-385.6" + wire width 32 $1\TAP_id_sr$next[31:0]$64 + attribute \src "libresoc.v:318.14-318.31" + wire width 32 $1\TAP_id_sr[31:0] + attribute \src "libresoc.v:365.3-385.6" + wire width 32 $2\TAP_id_sr$next[31:0]$65 + attribute \src "libresoc.v:347.17-347.105" + wire $and$libresoc.v:347$45_Y + attribute \src "libresoc.v:351.18-351.103" + wire $and$libresoc.v:351$49_Y + attribute \src "libresoc.v:353.18-353.105" + wire $and$libresoc.v:353$51_Y + attribute \src "libresoc.v:357.18-357.103" + wire $and$libresoc.v:357$55_Y + attribute \src "libresoc.v:358.18-358.106" + wire $and$libresoc.v:358$56_Y + attribute \src "libresoc.v:362.17-362.101" + wire $and$libresoc.v:362$60_Y + attribute \src "libresoc.v:348.18-348.102" + wire $eq$libresoc.v:348$46_Y + attribute \src "libresoc.v:349.18-349.102" + wire $eq$libresoc.v:349$47_Y + attribute \src "libresoc.v:352.17-352.101" + wire $eq$libresoc.v:352$50_Y + attribute \src "libresoc.v:354.18-354.102" + wire $eq$libresoc.v:354$52_Y + attribute \src "libresoc.v:355.18-355.102" + wire $eq$libresoc.v:355$53_Y + attribute \src "libresoc.v:359.18-359.102" + wire $eq$libresoc.v:359$57_Y + attribute \src "libresoc.v:360.17-360.101" + wire $eq$libresoc.v:360$58_Y + attribute \src "libresoc.v:350.18-350.104" + wire $or$libresoc.v:350$48_Y + attribute \src "libresoc.v:356.18-356.104" + wire $or$libresoc.v:356$54_Y + attribute \src "libresoc.v:361.17-361.101" + wire $or$libresoc.v:361$59_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:369" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 5 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:226" + wire width 32 \TAP_id_sr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:226" + wire width 32 \TAP_id_sr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:215" + wire output 6 \TAP_id_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:233" + wire \_bypass + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:230" + wire \_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:231" + wire \_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:229" + wire \_tdi + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:232" + wire \_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire input 1 \capture + attribute \src "libresoc.v:282.7-282.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + wire width 4 input 9 \ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire input 2 \isdr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire input 8 \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire input 7 \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire input 3 \shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:27" + wire input 4 \update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + cell $and $and$libresoc.v:347$45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$7 + connect \B \capture + connect \Y $and$libresoc.v:347$45_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $and $and$libresoc.v:351$49 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isdr + connect \B \$15 + connect \Y $and$libresoc.v:351$49_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + cell $and $and$libresoc.v:353$51 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$17 + connect \B \shift + connect \Y $and$libresoc.v:353$51_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $and $and$libresoc.v:357$55 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isdr + connect \B \$25 + connect \Y $and$libresoc.v:357$55_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + cell $and $and$libresoc.v:358$56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \B \update + connect \Y $and$libresoc.v:358$56_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $and $and$libresoc.v:362$60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isdr + connect \B \$5 + connect \Y $and$libresoc.v:362$60_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $eq $eq$libresoc.v:348$46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ir + connect \B 1'1 + connect \Y $eq$libresoc.v:348$46_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $eq $eq$libresoc.v:349$47 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \ir + connect \B 4'1111 + connect \Y $eq$libresoc.v:349$47_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $eq $eq$libresoc.v:352$50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ir + connect \B 1'1 + connect \Y $eq$libresoc.v:352$50_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $eq $eq$libresoc.v:354$52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ir + connect \B 1'1 + connect \Y $eq$libresoc.v:354$52_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $eq $eq$libresoc.v:355$53 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \ir + connect \B 4'1111 + connect \Y $eq$libresoc.v:355$53_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:369" + cell $eq $eq$libresoc.v:359$57 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \ir + connect \B 4'1111 + connect \Y $eq$libresoc.v:359$57_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $eq $eq$libresoc.v:360$58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \ir + connect \B 4'1111 + connect \Y $eq$libresoc.v:360$58_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $or $or$libresoc.v:350$48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$11 + connect \B \$13 + connect \Y $or$libresoc.v:350$48_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $or $or$libresoc.v:356$54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$21 + connect \B \$23 + connect \Y $or$libresoc.v:356$54_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $or $or$libresoc.v:361$59 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$3 + connect \Y $or$libresoc.v:361$59_Y end - attribute \src "issuer_ls180.v:259.3-268.6" - process $proc$issuer_ls180.v:259$8 + attribute \src "libresoc.v:282.7-282.20" + process $proc$libresoc.v:282$66 assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:318.14-318.31" + process $proc$libresoc.v:318$67 assign { } { } - assign $0\ALU_dec19_in1_sel[2:0] $1\ALU_dec19_in1_sel[2:0] - attribute \src "issuer_ls180.v:260.5-260.29" - switch \initial - attribute \src "issuer_ls180.v:260.9-260.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\ALU_dec19_in1_sel[2:0] 3'000 - case - assign $1\ALU_dec19_in1_sel[2:0] 3'000 - end + assign $1\TAP_id_sr[31:0] 0 sync always - update \ALU_dec19_in1_sel $0\ALU_dec19_in1_sel[2:0] + sync init + update \TAP_id_sr $1\TAP_id_sr[31:0] end - attribute \src "issuer_ls180.v:269.3-278.6" - process $proc$issuer_ls180.v:269$9 + attribute \src "libresoc.v:363.3-364.35" + process $proc$libresoc.v:363$61 + assign { } { } + assign $0\TAP_id_sr[31:0] \TAP_id_sr$next + sync posedge \posjtag_clk + update \TAP_id_sr $0\TAP_id_sr[31:0] + end + attribute \src "libresoc.v:365.3-385.6" + process $proc$libresoc.v:365$62 assign { } { } assign { } { } - assign $0\ALU_dec19_in2_sel[3:0] $1\ALU_dec19_in2_sel[3:0] - attribute \src "issuer_ls180.v:270.5-270.29" + assign $0\TAP_id_sr$next[31:0]$63 $1\TAP_id_sr$next[31:0]$64 + attribute \src "libresoc.v:366.5-366.29" switch \initial - attribute \src "issuer_ls180.v:270.9-270.17" + attribute \src "libresoc.v:366.9-366.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:244" + switch { \_shift \_capture } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 assign { } { } - assign $1\ALU_dec19_in2_sel[3:0] 4'0000 - case - assign $1\ALU_dec19_in2_sel[3:0] 4'0000 - end + assign $1\TAP_id_sr$next[31:0]$64 6399 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\TAP_id_sr$next[31:0]$64 $2\TAP_id_sr$next[31:0]$65 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:247" + switch \_bypass + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\TAP_id_sr$next[31:0]$65 [31:1] \TAP_id_sr [31:1] + assign $2\TAP_id_sr$next[31:0]$65 [0] \_tdi + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\TAP_id_sr$next[31:0]$65 { \_tdi \TAP_id_sr [31:1] } + end + case + assign $1\TAP_id_sr$next[31:0]$64 \TAP_id_sr + end + sync always + update \TAP_id_sr$next $0\TAP_id_sr$next[31:0]$63 + end + connect \$9 $and$libresoc.v:347$45_Y + connect \$11 $eq$libresoc.v:348$46_Y + connect \$13 $eq$libresoc.v:349$47_Y + connect \$15 $or$libresoc.v:350$48_Y + connect \$17 $and$libresoc.v:351$49_Y + connect \$1 $eq$libresoc.v:352$50_Y + connect \$19 $and$libresoc.v:353$51_Y + connect \$21 $eq$libresoc.v:354$52_Y + connect \$23 $eq$libresoc.v:355$53_Y + connect \$25 $or$libresoc.v:356$54_Y + connect \$27 $and$libresoc.v:357$55_Y + connect \$29 $and$libresoc.v:358$56_Y + connect \$31 $eq$libresoc.v:359$57_Y + connect \$3 $eq$libresoc.v:360$58_Y + connect \$5 $or$libresoc.v:361$59_Y + connect \$7 $and$libresoc.v:362$60_Y + connect \TAP_id_tdo \TAP_id_sr [0] + connect \_bypass \$31 + connect \_update \$29 + connect \_shift \$19 + connect \_capture \$9 + connect \_tdi \TAP_bus__tdi +end +attribute \src "libresoc.v:396.1-480.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.jtag._irblock" +attribute \generator "nMigen" +module \_irblock + attribute \src "libresoc.v:397.7-397.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:458.3-478.6" + wire width 4 $0\ir$next[3:0]$80 + attribute \src "libresoc.v:441.3-442.21" + wire width 4 $0\ir[3:0] + attribute \src "libresoc.v:445.3-457.6" + wire width 4 $0\shift_ir$next[3:0]$77 + attribute \src "libresoc.v:443.3-444.33" + wire width 4 $0\shift_ir[3:0] + attribute \src "libresoc.v:458.3-478.6" + wire width 4 $1\ir$next[3:0]$81 + attribute \src "libresoc.v:416.13-416.22" + wire width 4 $1\ir[3:0] + attribute \src "libresoc.v:445.3-457.6" + wire width 4 $1\shift_ir$next[3:0]$78 + attribute \src "libresoc.v:428.13-428.28" + wire width 4 $1\shift_ir[3:0] + attribute \src "libresoc.v:458.3-478.6" + wire width 4 $2\ir$next[3:0]$82 + attribute \src "libresoc.v:435.17-435.103" + wire $and$libresoc.v:435$68_Y + attribute \src "libresoc.v:436.18-436.105" + wire $and$libresoc.v:436$69_Y + attribute \src "libresoc.v:437.17-437.105" + wire $and$libresoc.v:437$70_Y + attribute \src "libresoc.v:438.17-438.103" + wire $and$libresoc.v:438$71_Y + attribute \src "libresoc.v:439.17-439.104" + wire $and$libresoc.v:439$72_Y + attribute \src "libresoc.v:440.17-440.105" + wire $and$libresoc.v:440$73_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:355" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:357" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:356" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:357" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:355" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:356" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 4 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire input 1 \capture + attribute \src "libresoc.v:397.7-397.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + wire width 4 output 9 \ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + wire width 4 \ir$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire input 5 \isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire input 8 \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire input 7 \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire input 2 \shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:139" + wire width 4 \shift_ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:139" + wire width 4 \shift_ir$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:129" + wire output 6 \tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:27" + wire input 3 \update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:356" + cell $and $and$libresoc.v:435$68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \shift + connect \Y $and$libresoc.v:435$68_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:357" + cell $and $and$libresoc.v:436$69 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \update + connect \Y $and$libresoc.v:436$69_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:355" + cell $and $and$libresoc.v:437$70 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \capture + connect \Y $and$libresoc.v:437$70_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:356" + cell $and $and$libresoc.v:438$71 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \shift + connect \Y $and$libresoc.v:438$71_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:357" + cell $and $and$libresoc.v:439$72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \update + connect \Y $and$libresoc.v:439$72_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:355" + cell $and $and$libresoc.v:440$73 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \capture + connect \Y $and$libresoc.v:440$73_Y + end + attribute \src "libresoc.v:397.7-397.20" + process $proc$libresoc.v:397$83 + assign { } { } + assign $0\initial[0:0] 1'0 sync always - update \ALU_dec19_in2_sel $0\ALU_dec19_in2_sel[3:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "issuer_ls180.v:279.3-288.6" - process $proc$issuer_ls180.v:279$10 + attribute \src "libresoc.v:416.13-416.22" + process $proc$libresoc.v:416$84 assign { } { } + assign $1\ir[3:0] 4'0001 + sync always + sync init + update \ir $1\ir[3:0] + end + attribute \src "libresoc.v:428.13-428.28" + process $proc$libresoc.v:428$85 assign { } { } - assign $0\ALU_dec19_cr_in[2:0] $1\ALU_dec19_cr_in[2:0] - attribute \src "issuer_ls180.v:280.5-280.29" - switch \initial - attribute \src "issuer_ls180.v:280.9-280.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\ALU_dec19_cr_in[2:0] 3'000 - case - assign $1\ALU_dec19_cr_in[2:0] 3'000 - end + assign $1\shift_ir[3:0] 4'0000 sync always - update \ALU_dec19_cr_in $0\ALU_dec19_cr_in[2:0] + sync init + update \shift_ir $1\shift_ir[3:0] end - attribute \src "issuer_ls180.v:289.3-298.6" - process $proc$issuer_ls180.v:289$11 + attribute \src "libresoc.v:441.3-442.21" + process $proc$libresoc.v:441$74 assign { } { } + assign $0\ir[3:0] \ir$next + sync posedge \posjtag_clk + update \ir $0\ir[3:0] + end + attribute \src "libresoc.v:443.3-444.33" + process $proc$libresoc.v:443$75 assign { } { } - assign $0\ALU_dec19_cr_out[2:0] $1\ALU_dec19_cr_out[2:0] - attribute \src "issuer_ls180.v:290.5-290.29" - switch \initial - attribute \src "issuer_ls180.v:290.9-290.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\ALU_dec19_cr_out[2:0] 3'000 - case - assign $1\ALU_dec19_cr_out[2:0] 3'000 - end - sync always - update \ALU_dec19_cr_out $0\ALU_dec19_cr_out[2:0] + assign $0\shift_ir[3:0] \shift_ir$next + sync posedge \posjtag_clk + update \shift_ir $0\shift_ir[3:0] end - attribute \src "issuer_ls180.v:299.3-308.6" - process $proc$issuer_ls180.v:299$12 + attribute \src "libresoc.v:445.3-457.6" + process $proc$libresoc.v:445$76 assign { } { } assign { } { } - assign $0\ALU_dec19_ldst_len[3:0] $1\ALU_dec19_ldst_len[3:0] - attribute \src "issuer_ls180.v:300.5-300.29" + assign $0\shift_ir$next[3:0]$77 $1\shift_ir$next[3:0]$78 + attribute \src "libresoc.v:446.5-446.29" switch \initial - attribute \src "issuer_ls180.v:300.9-300.17" + attribute \src "libresoc.v:446.9-446.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:142" + switch { \$5 \$3 \$1 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\shift_ir$next[3:0]$78 \ir + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- assign { } { } - assign $1\ALU_dec19_ldst_len[3:0] 4'0000 + assign $1\shift_ir$next[3:0]$78 { \TAP_bus__tdi \shift_ir [3:1] } case - assign $1\ALU_dec19_ldst_len[3:0] 4'0000 + assign $1\shift_ir$next[3:0]$78 \shift_ir end sync always - update \ALU_dec19_ldst_len $0\ALU_dec19_ldst_len[3:0] + update \shift_ir$next $0\shift_ir$next[3:0]$77 end - attribute \src "issuer_ls180.v:309.3-318.6" - process $proc$issuer_ls180.v:309$13 + attribute \src "libresoc.v:458.3-478.6" + process $proc$libresoc.v:458$79 + assign { } { } assign { } { } assign { } { } - assign $0\ALU_dec19_rc_sel[1:0] $1\ALU_dec19_rc_sel[1:0] - attribute \src "issuer_ls180.v:310.5-310.29" + assign $0\ir$next[3:0]$80 $2\ir$next[3:0]$82 + attribute \src "libresoc.v:459.5-459.29" switch \initial - attribute \src "issuer_ls180.v:310.9-310.17" + attribute \src "libresoc.v:459.9-459.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:142" + switch { \$11 \$9 \$7 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $1\ir$next[3:0]$81 \ir + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $1\ir$next[3:0]$81 \ir + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- assign { } { } - assign $1\ALU_dec19_rc_sel[1:0] 2'00 + assign $1\ir$next[3:0]$81 \shift_ir case - assign $1\ALU_dec19_rc_sel[1:0] 2'00 + assign $1\ir$next[3:0]$81 \ir end - sync always - update \ALU_dec19_rc_sel $0\ALU_dec19_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:319.3-328.6" - process $proc$issuer_ls180.v:319$14 - assign { } { } - assign { } { } - assign $0\ALU_dec19_cry_in[1:0] $1\ALU_dec19_cry_in[1:0] - attribute \src "issuer_ls180.v:320.5-320.29" - switch \initial - attribute \src "issuer_ls180.v:320.9-320.17" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 assign { } { } - assign $1\ALU_dec19_cry_in[1:0] 2'00 + assign $2\ir$next[3:0]$82 4'0001 case - assign $1\ALU_dec19_cry_in[1:0] 2'00 + assign $2\ir$next[3:0]$82 $1\ir$next[3:0]$81 end sync always - update \ALU_dec19_cry_in $0\ALU_dec19_cry_in[1:0] - end - attribute \src "issuer_ls180.v:6.7-6.20" - process $proc$issuer_ls180.v:6$15 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + update \ir$next $0\ir$next[3:0]$80 end - connect \opcode_switch \opcode_in [10:1] + connect \$9 $and$libresoc.v:435$68_Y + connect \$11 $and$libresoc.v:436$69_Y + connect \$1 $and$libresoc.v:437$70_Y + connect \$3 $and$libresoc.v:438$71_Y + connect \$5 $and$libresoc.v:439$72_Y + connect \$7 $and$libresoc.v:440$73_Y + connect \tdo \ir [0] end -attribute \src "issuer_ls180.v:334.1-1750.10" +attribute \src "libresoc.v:484.1-1198.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31" +attribute \nmigen.hierarchy "test_issuer.dbg" attribute \generator "nMigen" -module \ALU_dec31 - attribute \src "issuer_ls180.v:1457.3-1478.6" - wire width 3 $0\ALU_dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:1479.3-1500.6" - wire width 3 $0\ALU_dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:1545.3-1566.6" - wire width 2 $0\ALU_dec31_cry_in[1:0] - attribute \src "issuer_ls180.v:1611.3-1632.6" - wire $0\ALU_dec31_cry_out[0:0] - attribute \src "issuer_ls180.v:1677.3-1698.6" - wire width 12 $0\ALU_dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:1721.3-1742.6" - wire width 3 $0\ALU_dec31_in1_sel[2:0] - attribute \src "issuer_ls180.v:1435.3-1456.6" - wire width 4 $0\ALU_dec31_in2_sel[3:0] - attribute \src "issuer_ls180.v:1699.3-1720.6" - wire width 7 $0\ALU_dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:1567.3-1588.6" - wire $0\ALU_dec31_inv_a[0:0] - attribute \src "issuer_ls180.v:1589.3-1610.6" - wire $0\ALU_dec31_inv_out[0:0] - attribute \src "issuer_ls180.v:1633.3-1654.6" - wire $0\ALU_dec31_is_32b[0:0] - attribute \src "issuer_ls180.v:1501.3-1522.6" - wire width 4 $0\ALU_dec31_ldst_len[3:0] - attribute \src "issuer_ls180.v:1523.3-1544.6" - wire width 2 $0\ALU_dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:1655.3-1676.6" - wire $0\ALU_dec31_sgn[0:0] - attribute \src "issuer_ls180.v:335.7-335.20" +module \dbg + attribute \src "libresoc.v:1014.3-1023.6" + wire $0\d_cr_req[0:0] + attribute \src "libresoc.v:821.3-830.6" + wire $0\d_gpr_req[0:0] + attribute \src "libresoc.v:1024.3-1033.6" + wire $0\d_xer_req[0:0] + attribute \src "libresoc.v:803.3-820.6" + wire $0\dmi_ack_o[0:0] + attribute \src "libresoc.v:1034.3-1064.6" + wire width 64 $0\dmi_dout[63:0] + attribute \src "libresoc.v:1005.3-1013.6" + wire $0\dmi_read_log_data$next[0:0]$199 + attribute \src "libresoc.v:781.3-782.51" + wire $0\dmi_read_log_data[0:0] + attribute \src "libresoc.v:996.3-1004.6" + wire $0\dmi_read_log_data_1$next[0:0]$196 + attribute \src "libresoc.v:783.3-784.55" + wire $0\dmi_read_log_data_1[0:0] + attribute \src "libresoc.v:831.3-839.6" + wire $0\dmi_req_i_1$next[0:0]$162 + attribute \src "libresoc.v:793.3-794.39" + wire $0\dmi_req_i_1[0:0] + attribute \src "libresoc.v:1155.3-1188.6" + wire $0\do_dmi_log_rd$next[0:0]$226 + attribute \src "libresoc.v:795.3-796.43" + wire $0\do_dmi_log_rd[0:0] + attribute \src "libresoc.v:1125.3-1154.6" + wire $0\do_icreset$next[0:0]$219 + attribute \src "libresoc.v:797.3-798.37" + wire $0\do_icreset[0:0] + attribute \src "libresoc.v:1095.3-1124.6" + wire $0\do_reset$next[0:0]$212 + attribute \src "libresoc.v:799.3-800.33" + wire $0\do_reset[0:0] + attribute \src "libresoc.v:1065.3-1094.6" + wire $0\do_step$next[0:0]$205 + attribute \src "libresoc.v:801.3-802.31" + wire $0\do_step[0:0] + attribute \src "libresoc.v:934.3-961.6" + wire width 7 $0\gspr_index$next[6:0]$184 + attribute \src "libresoc.v:787.3-788.37" + wire width 7 $0\gspr_index[6:0] + attribute \src "libresoc.v:485.7-485.20" wire $0\initial[0:0] - attribute \src "issuer_ls180.v:1457.3-1478.6" - wire width 3 $1\ALU_dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:1479.3-1500.6" - wire width 3 $1\ALU_dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:1545.3-1566.6" - wire width 2 $1\ALU_dec31_cry_in[1:0] - attribute \src "issuer_ls180.v:1611.3-1632.6" - wire $1\ALU_dec31_cry_out[0:0] - attribute \src "issuer_ls180.v:1677.3-1698.6" - wire width 12 $1\ALU_dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:1721.3-1742.6" - wire width 3 $1\ALU_dec31_in1_sel[2:0] - attribute \src "issuer_ls180.v:1435.3-1456.6" - wire width 4 $1\ALU_dec31_in2_sel[3:0] - attribute \src "issuer_ls180.v:1699.3-1720.6" - wire width 7 $1\ALU_dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:1567.3-1588.6" - wire $1\ALU_dec31_inv_a[0:0] - attribute \src "issuer_ls180.v:1589.3-1610.6" - wire $1\ALU_dec31_inv_out[0:0] - attribute \src "issuer_ls180.v:1633.3-1654.6" - wire $1\ALU_dec31_is_32b[0:0] - attribute \src "issuer_ls180.v:1501.3-1522.6" - wire width 4 $1\ALU_dec31_ldst_len[3:0] - attribute \src "issuer_ls180.v:1523.3-1544.6" - wire width 2 $1\ALU_dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:1655.3-1676.6" - wire $1\ALU_dec31_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \ALU_dec31_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 6 \ALU_dec31_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 9 \ALU_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 12 \ALU_dec31_cry_out - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 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\enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \ALU_dec31_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 4 \ALU_dec31_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \ALU_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \ALU_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 11 \ALU_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 13 \ALU_dec31_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 7 \ALU_dec31_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \ALU_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 14 \ALU_dec31_sgn - attribute \src "issuer_ls180.v:335.7-335.15" + attribute \src "libresoc.v:962.3-995.6" + wire width 32 $0\log_dmi_addr$next[31:0]$190 + attribute \src "libresoc.v:785.3-786.41" + wire width 32 $0\log_dmi_addr[31:0] + attribute \src "libresoc.v:890.3-933.6" + wire $0\stopping$next[0:0]$175 + attribute \src "libresoc.v:789.3-790.33" + wire $0\stopping[0:0] + attribute \src "libresoc.v:840.3-889.6" + wire $0\terminated$next[0:0]$165 + attribute \src "libresoc.v:791.3-792.37" + wire $0\terminated[0:0] + attribute \src "libresoc.v:1014.3-1023.6" + wire $1\d_cr_req[0:0] + attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + wire 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"/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" + wire input 6 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 input 10 \core_dbg_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 input 9 \core_dbg_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" + wire output 7 \core_rst_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:97" + wire output 11 \core_stop_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103" + wire input 12 \core_stopped_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire input 19 \d_cr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 input 18 \d_cr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire output 17 \d_cr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire input 16 \d_gpr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" + wire width 7 output 14 \d_gpr_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 input 15 \d_gpr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire output 13 \d_gpr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire input 22 \d_xer_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 input 21 \d_xer_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire output 20 \d_xer_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" + wire output 4 \dmi_ack_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 4 input 24 \dmi_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 input 3 \dmi_din + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 64 output 5 \dmi_dout + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" + wire \dmi_read_log_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" + wire \dmi_read_log_data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" + wire \dmi_read_log_data_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" + wire \dmi_read_log_data_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire input 1 \dmi_req_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" + wire \dmi_req_i_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" + wire \dmi_req_i_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + wire input 2 \dmi_we_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" + wire \do_dmi_log_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" + wire \do_dmi_log_rd$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" + wire \do_icreset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" + wire \do_icreset$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" + wire \do_reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" + wire \do_reset$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" + wire \do_step + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" + wire \do_step$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:143" + wire width 7 \gspr_index + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:143" + wire width 7 \gspr_index$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99" + wire \icache_rst_o + attribute \src "libresoc.v:485.7-485.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" - wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 10 \opcode_switch - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:1350.22-1366.4" - cell \ALU_dec31_dec_sub0 \ALU_dec31_dec_sub0 - connect \ALU_dec31_dec_sub0_cr_in \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in - connect \ALU_dec31_dec_sub0_cr_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out - connect \ALU_dec31_dec_sub0_cry_in \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in - connect \ALU_dec31_dec_sub0_cry_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out - connect \ALU_dec31_dec_sub0_function_unit \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit - connect \ALU_dec31_dec_sub0_in1_sel \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel - connect \ALU_dec31_dec_sub0_in2_sel \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel - connect \ALU_dec31_dec_sub0_internal_op \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op - connect \ALU_dec31_dec_sub0_inv_a \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a - connect \ALU_dec31_dec_sub0_inv_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out - connect \ALU_dec31_dec_sub0_is_32b \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b - connect \ALU_dec31_dec_sub0_ldst_len \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len - connect \ALU_dec31_dec_sub0_rc_sel \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel - connect \ALU_dec31_dec_sub0_sgn \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn - connect \opcode_in \ALU_dec31_dec_sub0_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145" + wire width 32 \log_dmi_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145" + wire width 32 \log_dmi_addr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" + wire width 64 \log_dmi_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:119" + wire width 32 \log_write_addr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" + wire input 23 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:134" + wire width 64 \stat_reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" + wire \stopping + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" + wire \stopping$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:102" + wire input 8 \terminate_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" + wire \terminated + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" + wire \terminated$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:122" + wire \terminated_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $add $add$libresoc.v:728$95 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \log_dmi_addr [1:0] + connect \B 1'1 + connect \Y $add$libresoc.v:728$95_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:1367.23-1383.4" - cell \ALU_dec31_dec_sub10 \ALU_dec31_dec_sub10 - connect \ALU_dec31_dec_sub10_cr_in \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in - connect \ALU_dec31_dec_sub10_cr_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out - connect \ALU_dec31_dec_sub10_cry_in \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in - connect \ALU_dec31_dec_sub10_cry_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out - connect \ALU_dec31_dec_sub10_function_unit \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit - connect \ALU_dec31_dec_sub10_in1_sel \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel - connect \ALU_dec31_dec_sub10_in2_sel \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel - connect \ALU_dec31_dec_sub10_internal_op \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op - connect \ALU_dec31_dec_sub10_inv_a \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a - connect \ALU_dec31_dec_sub10_inv_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out - connect \ALU_dec31_dec_sub10_is_32b \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b - connect \ALU_dec31_dec_sub10_ldst_len \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len - connect \ALU_dec31_dec_sub10_rc_sel \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel - connect \ALU_dec31_dec_sub10_sgn \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn - connect \opcode_in \ALU_dec31_dec_sub10_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:719$86 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$7 + connect \Y $and$libresoc.v:719$86_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:1384.23-1400.4" - cell \ALU_dec31_dec_sub22 \ALU_dec31_dec_sub22 - connect \ALU_dec31_dec_sub22_cr_in \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in - connect \ALU_dec31_dec_sub22_cr_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out - connect \ALU_dec31_dec_sub22_cry_in \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in - connect \ALU_dec31_dec_sub22_cry_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out - connect \ALU_dec31_dec_sub22_function_unit \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit - connect \ALU_dec31_dec_sub22_in1_sel \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel - connect \ALU_dec31_dec_sub22_in2_sel \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel - connect \ALU_dec31_dec_sub22_internal_op \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op - connect \ALU_dec31_dec_sub22_inv_a \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a - connect \ALU_dec31_dec_sub22_inv_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out - connect \ALU_dec31_dec_sub22_is_32b \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b - connect \ALU_dec31_dec_sub22_ldst_len \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len - connect \ALU_dec31_dec_sub22_rc_sel \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel - connect \ALU_dec31_dec_sub22_sgn \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn - connect \opcode_in \ALU_dec31_dec_sub22_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:722$89 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$101 + connect \Y $and$libresoc.v:722$89_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:1401.23-1417.4" - cell \ALU_dec31_dec_sub26 \ALU_dec31_dec_sub26 - connect \ALU_dec31_dec_sub26_cr_in \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in - connect \ALU_dec31_dec_sub26_cr_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out - connect \ALU_dec31_dec_sub26_cry_in \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in - connect \ALU_dec31_dec_sub26_cry_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out - connect \ALU_dec31_dec_sub26_function_unit \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit - connect \ALU_dec31_dec_sub26_in1_sel \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel - connect \ALU_dec31_dec_sub26_in2_sel \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel - connect \ALU_dec31_dec_sub26_internal_op \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op - connect \ALU_dec31_dec_sub26_inv_a \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a - connect \ALU_dec31_dec_sub26_inv_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out - connect \ALU_dec31_dec_sub26_is_32b \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b - connect \ALU_dec31_dec_sub26_ldst_len \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len - connect \ALU_dec31_dec_sub26_rc_sel \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel - connect \ALU_dec31_dec_sub26_sgn \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn - connect \opcode_in \ALU_dec31_dec_sub26_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:724$91 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$105 + connect \Y $and$libresoc.v:724$91_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:1418.22-1434.4" - cell \ALU_dec31_dec_sub8 \ALU_dec31_dec_sub8 - connect \ALU_dec31_dec_sub8_cr_in \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in - connect \ALU_dec31_dec_sub8_cr_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out - connect \ALU_dec31_dec_sub8_cry_in \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in - connect \ALU_dec31_dec_sub8_cry_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out - connect \ALU_dec31_dec_sub8_function_unit \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit - connect \ALU_dec31_dec_sub8_in1_sel \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel - connect \ALU_dec31_dec_sub8_in2_sel \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel - connect \ALU_dec31_dec_sub8_internal_op \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op - connect \ALU_dec31_dec_sub8_inv_a \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a - connect \ALU_dec31_dec_sub8_inv_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out - connect \ALU_dec31_dec_sub8_is_32b \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b - connect \ALU_dec31_dec_sub8_ldst_len \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len - connect \ALU_dec31_dec_sub8_rc_sel \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel - connect \ALU_dec31_dec_sub8_sgn \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn - connect \opcode_in \ALU_dec31_dec_sub8_opcode_in - end - attribute \src "issuer_ls180.v:1435.3-1456.6" - process $proc$issuer_ls180.v:1435$16 - assign { } { } - assign { } { } - assign $0\ALU_dec31_in2_sel[3:0] $1\ALU_dec31_in2_sel[3:0] - attribute \src "issuer_ls180.v:1436.5-1436.29" - switch \initial - attribute \src "issuer_ls180.v:1436.9-1436.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel - case - assign $1\ALU_dec31_in2_sel[3:0] 4'0000 - end - sync always - update \ALU_dec31_in2_sel $0\ALU_dec31_in2_sel[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" + cell $and $and$libresoc.v:731$98 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$118 + connect \Y $and$libresoc.v:731$98_Y end - attribute \src "issuer_ls180.v:1457.3-1478.6" - process $proc$issuer_ls180.v:1457$17 - assign { } { } - assign { } { } - assign $0\ALU_dec31_cr_in[2:0] $1\ALU_dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:1458.5-1458.29" - switch \initial - attribute \src "issuer_ls180.v:1458.9-1458.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in - case - assign $1\ALU_dec31_cr_in[2:0] 3'000 - end - sync always - update \ALU_dec31_cr_in $0\ALU_dec31_cr_in[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" + cell $and $and$libresoc.v:733$100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \stopping + connect \B \$122 + connect \Y $and$libresoc.v:733$100_Y end - attribute \src "issuer_ls180.v:1479.3-1500.6" - process $proc$issuer_ls180.v:1479$18 - assign { } { } - assign { } { } - assign $0\ALU_dec31_cr_out[2:0] $1\ALU_dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:1480.5-1480.29" - switch \initial - attribute \src "issuer_ls180.v:1480.9-1480.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out - case - assign $1\ALU_dec31_cr_out[2:0] 3'000 - end - sync always - update \ALU_dec31_cr_out $0\ALU_dec31_cr_out[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:738$105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$17 + connect \Y $and$libresoc.v:738$105_Y end - attribute \src "issuer_ls180.v:1501.3-1522.6" - process $proc$issuer_ls180.v:1501$19 - assign { } { } - assign { } { } - assign $0\ALU_dec31_ldst_len[3:0] $1\ALU_dec31_ldst_len[3:0] - attribute \src "issuer_ls180.v:1502.5-1502.29" - switch \initial - attribute \src "issuer_ls180.v:1502.9-1502.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len - case - assign $1\ALU_dec31_ldst_len[3:0] 4'0000 - end - sync always - update \ALU_dec31_ldst_len $0\ALU_dec31_ldst_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:740$107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$21 + connect \Y $and$libresoc.v:740$107_Y end - attribute \src "issuer_ls180.v:1523.3-1544.6" - process $proc$issuer_ls180.v:1523$20 - assign { } { } - assign { } { } - assign $0\ALU_dec31_rc_sel[1:0] $1\ALU_dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:1524.5-1524.29" - switch \initial - attribute \src "issuer_ls180.v:1524.9-1524.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel - case - assign $1\ALU_dec31_rc_sel[1:0] 2'00 - end - sync always - update \ALU_dec31_rc_sel $0\ALU_dec31_rc_sel[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:745$112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$31 + connect \Y $and$libresoc.v:745$112_Y end - attribute \src "issuer_ls180.v:1545.3-1566.6" - process $proc$issuer_ls180.v:1545$21 - assign { } { } - assign { } { } - assign $0\ALU_dec31_cry_in[1:0] $1\ALU_dec31_cry_in[1:0] - attribute \src "issuer_ls180.v:1546.5-1546.29" - switch \initial - attribute \src "issuer_ls180.v:1546.9-1546.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in - case - assign $1\ALU_dec31_cry_in[1:0] 2'00 - end - sync always - update \ALU_dec31_cry_in $0\ALU_dec31_cry_in[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:747$114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$35 + connect \Y $and$libresoc.v:747$114_Y end - attribute \src "issuer_ls180.v:1567.3-1588.6" - process $proc$issuer_ls180.v:1567$22 - assign { } { } - assign { } { } - assign $0\ALU_dec31_inv_a[0:0] $1\ALU_dec31_inv_a[0:0] - attribute \src "issuer_ls180.v:1568.5-1568.29" - switch \initial - attribute \src "issuer_ls180.v:1568.9-1568.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a - case - assign $1\ALU_dec31_inv_a[0:0] 1'0 - end - sync always - update \ALU_dec31_inv_a $0\ALU_dec31_inv_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:753$120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$45 + connect \Y $and$libresoc.v:753$120_Y end - attribute \src "issuer_ls180.v:1589.3-1610.6" - process $proc$issuer_ls180.v:1589$23 - assign { } { } - assign { } { } - assign $0\ALU_dec31_inv_out[0:0] $1\ALU_dec31_inv_out[0:0] - attribute \src "issuer_ls180.v:1590.5-1590.29" - switch \initial - attribute \src "issuer_ls180.v:1590.9-1590.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out - case - assign $1\ALU_dec31_inv_out[0:0] 1'0 - end - sync always - update \ALU_dec31_inv_out $0\ALU_dec31_inv_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:755$122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$49 + connect \Y $and$libresoc.v:755$122_Y end - attribute \src "issuer_ls180.v:1611.3-1632.6" - process $proc$issuer_ls180.v:1611$24 - assign { } { } - assign { } { } - assign $0\ALU_dec31_cry_out[0:0] $1\ALU_dec31_cry_out[0:0] - attribute \src "issuer_ls180.v:1612.5-1612.29" - switch \initial - attribute \src "issuer_ls180.v:1612.9-1612.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out - case - assign $1\ALU_dec31_cry_out[0:0] 1'0 - end - sync always - update \ALU_dec31_cry_out $0\ALU_dec31_cry_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:759$126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$3 + connect \Y $and$libresoc.v:759$126_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:761$128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$59 + connect \Y $and$libresoc.v:761$128_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:763$130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$63 + connect \Y $and$libresoc.v:763$130_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:768$135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$73 + connect \Y $and$libresoc.v:768$135_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:771$138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$77 + connect \Y $and$libresoc.v:771$138_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:776$143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$87 + connect \Y $and$libresoc.v:776$143_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:778$145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$91 + connect \Y $and$libresoc.v:778$145_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:720$87 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:720$87_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:725$92 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:725$92_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:726$93 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:726$93_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:727$94 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:727$94_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" + cell $eq $eq$libresoc.v:729$96 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'111 + connect \Y $eq$libresoc.v:729$96_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:730$97 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:730$97_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:734$101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:734$101_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:735$102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:735$102_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:741$108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:741$108_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:742$109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:742$109_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:743$110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:743$110_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:749$116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:749$116_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:750$117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:750$117_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:751$118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:751$118_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:756$123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:756$123_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:757$124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:757$124_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:758$125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:758$125_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:764$131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:764$131_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:765$132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:765$132_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:766$133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:766$133_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:772$139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:772$139_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:773$140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:773$140_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:774$141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:774$141_Y end - attribute \src "issuer_ls180.v:1633.3-1654.6" - process $proc$issuer_ls180.v:1633$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:779$146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:779$146_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:780$147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:780$147_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:721$88 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:721$88_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:723$90 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:723$90_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" + cell $not $not$libresoc.v:732$99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \do_step + connect \Y $not$libresoc.v:732$99_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:736$103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:736$103_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:739$106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:739$106_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:744$111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:744$111_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:746$113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:746$113_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:748$115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:748$115_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:752$119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:752$119_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:754$121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:754$121_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:760$127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:760$127_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:762$129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:762$129_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:767$134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:767$134_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:769$136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:769$136_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:770$137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:770$137_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:775$142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:775$142_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:777$144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:777$144_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170" + cell $pos $pos$libresoc.v:737$104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping } + connect \Y $pos$libresoc.v:737$104_Y + end + attribute \src "libresoc.v:1005.3-1013.6" + process $proc$libresoc.v:1005$198 assign { } { } assign { } { } - assign $0\ALU_dec31_is_32b[0:0] $1\ALU_dec31_is_32b[0:0] - attribute \src "issuer_ls180.v:1634.5-1634.29" + assign $0\dmi_read_log_data$next[0:0]$199 $1\dmi_read_log_data$next[0:0]$200 + attribute \src "libresoc.v:1006.5-1006.29" switch \initial - attribute \src "issuer_ls180.v:1634.9-1634.17" + attribute \src "libresoc.v:1006.9-1006.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b + assign $1\dmi_read_log_data$next[0:0]$200 1'0 case - assign $1\ALU_dec31_is_32b[0:0] 1'0 + assign $1\dmi_read_log_data$next[0:0]$200 \$120 end sync always - update \ALU_dec31_is_32b $0\ALU_dec31_is_32b[0:0] + update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$199 end - attribute \src "issuer_ls180.v:1655.3-1676.6" - process $proc$issuer_ls180.v:1655$26 + attribute \src "libresoc.v:1014.3-1023.6" + process $proc$libresoc.v:1014$201 assign { } { } assign { } { } - assign $0\ALU_dec31_sgn[0:0] $1\ALU_dec31_sgn[0:0] - attribute \src "issuer_ls180.v:1656.5-1656.29" + assign $0\d_cr_req[0:0] $1\d_cr_req[0:0] + attribute \src "libresoc.v:1015.5-1015.29" switch \initial - attribute \src "issuer_ls180.v:1656.9-1656.17" + attribute \src "libresoc.v:1015.9-1015.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 assign { } { } - assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn + assign $1\d_cr_req[0:0] \dmi_req_i case - assign $1\ALU_dec31_sgn[0:0] 1'0 + assign $1\d_cr_req[0:0] 1'0 end sync always - update \ALU_dec31_sgn $0\ALU_dec31_sgn[0:0] + update \d_cr_req $0\d_cr_req[0:0] end - attribute \src "issuer_ls180.v:1677.3-1698.6" - process $proc$issuer_ls180.v:1677$27 + attribute \src "libresoc.v:1024.3-1033.6" + process $proc$libresoc.v:1024$202 assign { } { } assign { } { } - assign $0\ALU_dec31_function_unit[11:0] $1\ALU_dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:1678.5-1678.29" + assign $0\d_xer_req[0:0] $1\d_xer_req[0:0] + attribute \src "libresoc.v:1025.5-1025.29" switch \initial - attribute \src "issuer_ls180.v:1678.9-1678.17" + attribute \src "libresoc.v:1025.9-1025.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 assign { } { } - assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit + assign $1\d_xer_req[0:0] \dmi_req_i case - assign $1\ALU_dec31_function_unit[11:0] 12'000000000000 + assign $1\d_xer_req[0:0] 1'0 end sync always - update \ALU_dec31_function_unit $0\ALU_dec31_function_unit[11:0] + update \d_xer_req $0\d_xer_req[0:0] end - attribute \src "issuer_ls180.v:1699.3-1720.6" - process $proc$issuer_ls180.v:1699$28 + attribute \src "libresoc.v:1034.3-1064.6" + process $proc$libresoc.v:1034$203 assign { } { } assign { } { } - assign $0\ALU_dec31_internal_op[6:0] $1\ALU_dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:1700.5-1700.29" + assign $0\dmi_dout[63:0] $1\dmi_dout[63:0] + attribute \src "libresoc.v:1035.5-1035.29" switch \initial - attribute \src "issuer_ls180.v:1700.9-1700.17" + attribute \src "libresoc.v:1035.9-1035.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:173" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 assign { } { } - assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\dmi_dout[63:0] \stat_reg + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 assign { } { } - assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 + assign $1\dmi_dout[63:0] \core_dbg_pc + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 assign { } { } - assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 + assign $1\dmi_dout[63:0] \core_dbg_msr + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 assign { } { } - assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\dmi_dout[63:0] \d_gpr_data + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dmi_dout[63:0] { \log_write_addr_o \log_dmi_addr } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dmi_dout[63:0] \log_dmi_data + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dmi_dout[63:0] \d_cr_data + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 assign { } { } - assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op + assign $1\dmi_dout[63:0] \d_xer_data case - assign $1\ALU_dec31_internal_op[6:0] 7'0000000 + assign $1\dmi_dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \ALU_dec31_internal_op $0\ALU_dec31_internal_op[6:0] + update \dmi_dout $0\dmi_dout[63:0] end - attribute \src "issuer_ls180.v:1721.3-1742.6" - process $proc$issuer_ls180.v:1721$29 + attribute \src "libresoc.v:1065.3-1094.6" + process $proc$libresoc.v:1065$204 assign { } { } assign { } { } - assign $0\ALU_dec31_in1_sel[2:0] $1\ALU_dec31_in1_sel[2:0] - attribute \src "issuer_ls180.v:1722.5-1722.29" + assign { } { } + assign $0\do_step$next[0:0]$205 $5\do_step$next[0:0]$210 + attribute \src "libresoc.v:1066.5-1066.29" switch \initial - attribute \src "issuer_ls180.v:1722.9-1722.17" + attribute \src "libresoc.v:1066.9-1066.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$9 \$5 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 assign { } { } - assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\do_step$next[0:0]$206 $2\do_step$next[0:0]$207 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_step$next[0:0]$207 $3\do_step$next[0:0]$208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$15 \$13 \$11 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_step$next[0:0]$208 $4\do_step$next[0:0]$209 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" + switch \dmi_din [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_step$next[0:0]$209 1'1 + case + assign $4\do_step$next[0:0]$209 1'0 + end + case + assign $3\do_step$next[0:0]$208 1'0 + end + case + assign $2\do_step$next[0:0]$207 1'0 + end + case + assign $1\do_step$next[0:0]$206 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel + assign $5\do_step$next[0:0]$210 1'0 case - assign $1\ALU_dec31_in1_sel[2:0] 3'000 + assign $5\do_step$next[0:0]$210 $1\do_step$next[0:0]$206 end sync always - update \ALU_dec31_in1_sel $0\ALU_dec31_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:335.7-335.20" - process $proc$issuer_ls180.v:335$30 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + update \do_step$next $0\do_step$next[0:0]$205 end - connect \ALU_dec31_dec_sub8_opcode_in \opcode_in - connect \ALU_dec31_dec_sub22_opcode_in \opcode_in - connect \ALU_dec31_dec_sub26_opcode_in \opcode_in - connect \ALU_dec31_dec_sub0_opcode_in \opcode_in - connect \ALU_dec31_dec_sub10_opcode_in \opcode_in - connect \opc_in \opcode_switch [4:0] - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "issuer_ls180.v:1754.1-2163.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub0" -attribute \generator "nMigen" -module \ALU_dec31_dec_sub0 - attribute \src "issuer_ls180.v:2082.3-2097.6" - wire width 3 $0\ALU_dec31_dec_sub0_cr_in[2:0] - attribute \src "issuer_ls180.v:2098.3-2113.6" - wire width 3 $0\ALU_dec31_dec_sub0_cr_out[2:0] - attribute \src "issuer_ls180.v:2146.3-2161.6" - wire width 2 $0\ALU_dec31_dec_sub0_cry_in[1:0] - attribute \src "issuer_ls180.v:1986.3-2001.6" - wire $0\ALU_dec31_dec_sub0_cry_out[0:0] - attribute \src "issuer_ls180.v:1938.3-1953.6" - wire width 12 $0\ALU_dec31_dec_sub0_function_unit[11:0] - attribute \src "issuer_ls180.v:2050.3-2065.6" - wire width 3 $0\ALU_dec31_dec_sub0_in1_sel[2:0] - attribute \src "issuer_ls180.v:2066.3-2081.6" - wire width 4 $0\ALU_dec31_dec_sub0_in2_sel[3:0] - attribute \src "issuer_ls180.v:2034.3-2049.6" - wire width 7 $0\ALU_dec31_dec_sub0_internal_op[6:0] - attribute \src "issuer_ls180.v:1954.3-1969.6" - wire $0\ALU_dec31_dec_sub0_inv_a[0:0] - attribute \src "issuer_ls180.v:1970.3-1985.6" - wire $0\ALU_dec31_dec_sub0_inv_out[0:0] - attribute \src "issuer_ls180.v:2002.3-2017.6" - wire $0\ALU_dec31_dec_sub0_is_32b[0:0] - attribute \src "issuer_ls180.v:2114.3-2129.6" - wire width 4 $0\ALU_dec31_dec_sub0_ldst_len[3:0] - attribute \src "issuer_ls180.v:2130.3-2145.6" - wire width 2 $0\ALU_dec31_dec_sub0_rc_sel[1:0] - attribute \src "issuer_ls180.v:2018.3-2033.6" - wire $0\ALU_dec31_dec_sub0_sgn[0:0] - attribute \src "issuer_ls180.v:1755.7-1755.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:2082.3-2097.6" - wire width 3 $1\ALU_dec31_dec_sub0_cr_in[2:0] - attribute \src "issuer_ls180.v:2098.3-2113.6" - wire width 3 $1\ALU_dec31_dec_sub0_cr_out[2:0] - attribute \src "issuer_ls180.v:2146.3-2161.6" - wire width 2 $1\ALU_dec31_dec_sub0_cry_in[1:0] - attribute \src "issuer_ls180.v:1986.3-2001.6" - wire $1\ALU_dec31_dec_sub0_cry_out[0:0] - attribute \src "issuer_ls180.v:1938.3-1953.6" - wire width 12 $1\ALU_dec31_dec_sub0_function_unit[11:0] - attribute \src "issuer_ls180.v:2050.3-2065.6" - wire width 3 $1\ALU_dec31_dec_sub0_in1_sel[2:0] - attribute \src "issuer_ls180.v:2066.3-2081.6" - wire width 4 $1\ALU_dec31_dec_sub0_in2_sel[3:0] - attribute \src "issuer_ls180.v:2034.3-2049.6" - wire width 7 $1\ALU_dec31_dec_sub0_internal_op[6:0] - attribute \src "issuer_ls180.v:1954.3-1969.6" - wire $1\ALU_dec31_dec_sub0_inv_a[0:0] - attribute \src "issuer_ls180.v:1970.3-1985.6" - wire $1\ALU_dec31_dec_sub0_inv_out[0:0] - attribute \src "issuer_ls180.v:2002.3-2017.6" - wire $1\ALU_dec31_dec_sub0_is_32b[0:0] - attribute \src "issuer_ls180.v:2114.3-2129.6" - wire width 4 $1\ALU_dec31_dec_sub0_ldst_len[3:0] - attribute \src "issuer_ls180.v:2130.3-2145.6" - wire width 2 $1\ALU_dec31_dec_sub0_rc_sel[1:0] - attribute \src "issuer_ls180.v:2018.3-2033.6" - wire $1\ALU_dec31_dec_sub0_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \ALU_dec31_dec_sub0_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 6 \ALU_dec31_dec_sub0_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 9 \ALU_dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 12 \ALU_dec31_dec_sub0_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \ALU_dec31_dec_sub0_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \ALU_dec31_dec_sub0_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 4 \ALU_dec31_dec_sub0_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \ALU_dec31_dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \ALU_dec31_dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 11 \ALU_dec31_dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 13 \ALU_dec31_dec_sub0_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 7 \ALU_dec31_dec_sub0_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \ALU_dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 14 \ALU_dec31_dec_sub0_sgn - attribute \src "issuer_ls180.v:1755.7-1755.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:1755.7-1755.20" - process $proc$issuer_ls180.v:1755$45 + attribute \src "libresoc.v:1095.3-1124.6" + process $proc$libresoc.v:1095$211 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:1938.3-1953.6" - process $proc$issuer_ls180.v:1938$31 assign { } { } assign { } { } - assign $0\ALU_dec31_dec_sub0_function_unit[11:0] $1\ALU_dec31_dec_sub0_function_unit[11:0] - attribute \src "issuer_ls180.v:1939.5-1939.29" + assign $0\do_reset$next[0:0]$212 $5\do_reset$next[0:0]$217 + attribute \src "libresoc.v:1096.5-1096.29" switch \initial - attribute \src "issuer_ls180.v:1939.9-1939.17" + attribute \src "libresoc.v:1096.9-1096.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub0_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$23 \$19 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 assign { } { } - assign $1\ALU_dec31_dec_sub0_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $1\do_reset$next[0:0]$213 $2\do_reset$next[0:0]$214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_reset$next[0:0]$214 $3\do_reset$next[0:0]$215 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$29 \$27 \$25 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_reset$next[0:0]$215 $4\do_reset$next[0:0]$216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" + switch \dmi_din [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_reset$next[0:0]$216 1'1 + case + assign $4\do_reset$next[0:0]$216 1'0 + end + case + assign $3\do_reset$next[0:0]$215 1'0 + end + case + assign $2\do_reset$next[0:0]$214 1'0 + end + case + assign $1\do_reset$next[0:0]$213 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\ALU_dec31_dec_sub0_function_unit[11:0] 12'000000000010 + assign $5\do_reset$next[0:0]$217 1'0 case - assign $1\ALU_dec31_dec_sub0_function_unit[11:0] 12'000000000000 + assign $5\do_reset$next[0:0]$217 $1\do_reset$next[0:0]$213 end sync always - update \ALU_dec31_dec_sub0_function_unit $0\ALU_dec31_dec_sub0_function_unit[11:0] + update \do_reset$next $0\do_reset$next[0:0]$212 end - attribute \src "issuer_ls180.v:1954.3-1969.6" - process $proc$issuer_ls180.v:1954$32 + attribute \src "libresoc.v:1125.3-1154.6" + process $proc$libresoc.v:1125$218 + assign { } { } assign { } { } assign { } { } - assign $0\ALU_dec31_dec_sub0_inv_a[0:0] $1\ALU_dec31_dec_sub0_inv_a[0:0] - attribute \src "issuer_ls180.v:1955.5-1955.29" + assign $0\do_icreset$next[0:0]$219 $5\do_icreset$next[0:0]$224 + attribute \src "libresoc.v:1126.5-1126.29" switch \initial - attribute \src "issuer_ls180.v:1955.9-1955.17" + attribute \src "libresoc.v:1126.9-1126.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$37 \$33 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 assign { } { } - assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $1\do_icreset$next[0:0]$220 $2\do_icreset$next[0:0]$221 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_icreset$next[0:0]$221 $3\do_icreset$next[0:0]$222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$43 \$41 \$39 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_icreset$next[0:0]$222 $4\do_icreset$next[0:0]$223 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" + switch \dmi_din [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_icreset$next[0:0]$223 1'1 + case + assign $4\do_icreset$next[0:0]$223 1'0 + end + case + assign $3\do_icreset$next[0:0]$222 1'0 + end + case + assign $2\do_icreset$next[0:0]$221 1'0 + end + case + assign $1\do_icreset$next[0:0]$220 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'1 + assign $5\do_icreset$next[0:0]$224 1'0 case - assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'0 + assign $5\do_icreset$next[0:0]$224 $1\do_icreset$next[0:0]$220 end sync always - update \ALU_dec31_dec_sub0_inv_a $0\ALU_dec31_dec_sub0_inv_a[0:0] + update \do_icreset$next $0\do_icreset$next[0:0]$219 end - attribute \src "issuer_ls180.v:1970.3-1985.6" - process $proc$issuer_ls180.v:1970$33 + attribute \src "libresoc.v:1155.3-1188.6" + process $proc$libresoc.v:1155$225 assign { } { } assign { } { } - assign $0\ALU_dec31_dec_sub0_inv_out[0:0] $1\ALU_dec31_dec_sub0_inv_out[0:0] - attribute \src "issuer_ls180.v:1971.5-1971.29" + assign { } { } + assign $0\do_dmi_log_rd$next[0:0]$226 $4\do_dmi_log_rd$next[0:0]$230 + attribute \src "libresoc.v:1156.5-1156.29" switch \initial - attribute \src "issuer_ls180.v:1971.9-1971.17" + attribute \src "libresoc.v:1156.9-1156.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$51 \$47 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 assign { } { } - assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 + assign $1\do_dmi_log_rd$next[0:0]$227 $2\do_dmi_log_rd$next[0:0]$228 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_dmi_log_rd$next[0:0]$228 $3\do_dmi_log_rd$next[0:0]$229 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$57 \$55 \$53 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $3\do_dmi_log_rd$next[0:0]$229 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $3\do_dmi_log_rd$next[0:0]$229 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $3\do_dmi_log_rd$next[0:0]$229 1'1 + case + assign $3\do_dmi_log_rd$next[0:0]$229 1'0 + end + case + assign $2\do_dmi_log_rd$next[0:0]$228 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- assign { } { } - assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $1\do_dmi_log_rd$next[0:0]$227 1'1 + case + assign $1\do_dmi_log_rd$next[0:0]$227 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 + assign $4\do_dmi_log_rd$next[0:0]$230 1'0 case - assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 + assign $4\do_dmi_log_rd$next[0:0]$230 $1\do_dmi_log_rd$next[0:0]$227 end sync always - update \ALU_dec31_dec_sub0_inv_out $0\ALU_dec31_dec_sub0_inv_out[0:0] + update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$226 end - attribute \src "issuer_ls180.v:1986.3-2001.6" - process $proc$issuer_ls180.v:1986$34 + attribute \src "libresoc.v:485.7-485.20" + process $proc$libresoc.v:485$231 assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:658.7-658.31" + process $proc$libresoc.v:658$232 assign { } { } - assign $0\ALU_dec31_dec_sub0_cry_out[0:0] $1\ALU_dec31_dec_sub0_cry_out[0:0] - attribute \src "issuer_ls180.v:1987.5-1987.29" - switch \initial - attribute \src "issuer_ls180.v:1987.9-1987.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 - end + assign $1\dmi_read_log_data[0:0] 1'0 + sync always + sync init + update \dmi_read_log_data $1\dmi_read_log_data[0:0] + end + attribute \src "libresoc.v:662.7-662.33" + process $proc$libresoc.v:662$233 + assign { } { } + assign $1\dmi_read_log_data_1[0:0] 1'0 + sync always + sync init + update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0] + end + attribute \src "libresoc.v:668.7-668.25" + process $proc$libresoc.v:668$234 + assign { } { } + assign $1\dmi_req_i_1[0:0] 1'0 sync always - update \ALU_dec31_dec_sub0_cry_out $0\ALU_dec31_dec_sub0_cry_out[0:0] + sync init + update \dmi_req_i_1 $1\dmi_req_i_1[0:0] + end + attribute \src "libresoc.v:674.7-674.27" + process $proc$libresoc.v:674$235 + assign { } { } + assign $1\do_dmi_log_rd[0:0] 1'0 + sync always + sync init + update \do_dmi_log_rd $1\do_dmi_log_rd[0:0] + end + attribute \src "libresoc.v:678.7-678.24" + process $proc$libresoc.v:678$236 + assign { } { } + assign $1\do_icreset[0:0] 1'0 + sync always + sync init + update \do_icreset $1\do_icreset[0:0] + end + attribute \src "libresoc.v:682.7-682.22" + process $proc$libresoc.v:682$237 + assign { } { } + assign $1\do_reset[0:0] 1'0 + sync always + sync init + update \do_reset $1\do_reset[0:0] + end + attribute \src "libresoc.v:686.7-686.21" + process $proc$libresoc.v:686$238 + assign { } { } + assign $1\do_step[0:0] 1'0 + sync always + sync init + update \do_step $1\do_step[0:0] + end + attribute \src "libresoc.v:690.13-690.31" + process $proc$libresoc.v:690$239 + assign { } { } + assign $1\gspr_index[6:0] 7'0000000 + sync always + sync init + update \gspr_index $1\gspr_index[6:0] + end + attribute \src "libresoc.v:696.14-696.34" + process $proc$libresoc.v:696$240 + assign { } { } + assign $1\log_dmi_addr[31:0] 0 + sync always + sync init + update \log_dmi_addr $1\log_dmi_addr[31:0] + end + attribute \src "libresoc.v:708.7-708.22" + process $proc$libresoc.v:708$241 + assign { } { } + assign $1\stopping[0:0] 1'0 + sync always + sync init + update \stopping $1\stopping[0:0] + end + attribute \src "libresoc.v:714.7-714.24" + process $proc$libresoc.v:714$242 + assign { } { } + assign $1\terminated[0:0] 1'0 + sync always + sync init + update \terminated $1\terminated[0:0] + end + attribute \src "libresoc.v:781.3-782.51" + process $proc$libresoc.v:781$148 + assign { } { } + assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next + sync posedge \clk + update \dmi_read_log_data $0\dmi_read_log_data[0:0] + end + attribute \src "libresoc.v:783.3-784.55" + process $proc$libresoc.v:783$149 + assign { } { } + assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next + sync posedge \clk + update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0] + end + attribute \src "libresoc.v:785.3-786.41" + process $proc$libresoc.v:785$150 + assign { } { } + assign $0\log_dmi_addr[31:0] \log_dmi_addr$next + sync posedge \clk + update \log_dmi_addr $0\log_dmi_addr[31:0] + end + attribute \src "libresoc.v:787.3-788.37" + process $proc$libresoc.v:787$151 + assign { } { } + assign $0\gspr_index[6:0] \gspr_index$next + sync posedge \clk + update \gspr_index $0\gspr_index[6:0] + end + attribute \src "libresoc.v:789.3-790.33" + process $proc$libresoc.v:789$152 + assign { } { } + assign $0\stopping[0:0] \stopping$next + sync posedge \clk + update \stopping $0\stopping[0:0] + end + attribute \src "libresoc.v:791.3-792.37" + process $proc$libresoc.v:791$153 + assign { } { } + assign $0\terminated[0:0] \terminated$next + sync posedge \clk + update \terminated $0\terminated[0:0] + end + attribute \src "libresoc.v:793.3-794.39" + process $proc$libresoc.v:793$154 + assign { } { } + assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next + sync posedge \clk + update \dmi_req_i_1 $0\dmi_req_i_1[0:0] + end + attribute \src "libresoc.v:795.3-796.43" + process $proc$libresoc.v:795$155 + assign { } { } + assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next + sync posedge \clk + update \do_dmi_log_rd $0\do_dmi_log_rd[0:0] + end + attribute \src "libresoc.v:797.3-798.37" + process $proc$libresoc.v:797$156 + assign { } { } + assign $0\do_icreset[0:0] \do_icreset$next + sync posedge \clk + update \do_icreset $0\do_icreset[0:0] + end + attribute \src "libresoc.v:799.3-800.33" + process $proc$libresoc.v:799$157 + assign { } { } + assign $0\do_reset[0:0] \do_reset$next + sync posedge \clk + update \do_reset $0\do_reset[0:0] end - attribute \src "issuer_ls180.v:2002.3-2017.6" - process $proc$issuer_ls180.v:2002$35 + attribute \src "libresoc.v:801.3-802.31" + process $proc$libresoc.v:801$158 assign { } { } + assign $0\do_step[0:0] \do_step$next + sync posedge \clk + update \do_step $0\do_step[0:0] + end + attribute \src "libresoc.v:803.3-820.6" + process $proc$libresoc.v:803$159 assign { } { } - assign $0\ALU_dec31_dec_sub0_is_32b[0:0] $1\ALU_dec31_dec_sub0_is_32b[0:0] - attribute \src "issuer_ls180.v:2003.5-2003.29" + assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0] + attribute \src "libresoc.v:804.5-804.29" switch \initial - attribute \src "issuer_ls180.v:2003.9-2003.17" + attribute \src "libresoc.v:804.9-804.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 assign { } { } - assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 + assign $1\dmi_ack_o[0:0] \d_gpr_ack + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 assign { } { } - assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $1\dmi_ack_o[0:0] \d_cr_ack + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 assign { } { } - assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 + assign $1\dmi_ack_o[0:0] \d_xer_ack + attribute \src "libresoc.v:0.0-0.0" case - assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 + assign { } { } + assign $1\dmi_ack_o[0:0] \dmi_req_i end sync always - update \ALU_dec31_dec_sub0_is_32b $0\ALU_dec31_dec_sub0_is_32b[0:0] + update \dmi_ack_o $0\dmi_ack_o[0:0] end - attribute \src "issuer_ls180.v:2018.3-2033.6" - process $proc$issuer_ls180.v:2018$36 + attribute \src "libresoc.v:821.3-830.6" + process $proc$libresoc.v:821$160 assign { } { } assign { } { } - assign $0\ALU_dec31_dec_sub0_sgn[0:0] $1\ALU_dec31_dec_sub0_sgn[0:0] - attribute \src "issuer_ls180.v:2019.5-2019.29" + assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0] + attribute \src "libresoc.v:822.5-822.29" switch \initial - attribute \src "issuer_ls180.v:2019.9-2019.17" + attribute \src "libresoc.v:822.9-822.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 assign { } { } - assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'0 + assign $1\d_gpr_req[0:0] \dmi_req_i case - assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'0 + assign $1\d_gpr_req[0:0] 1'0 end sync always - update \ALU_dec31_dec_sub0_sgn $0\ALU_dec31_dec_sub0_sgn[0:0] + update \d_gpr_req $0\d_gpr_req[0:0] end - attribute \src "issuer_ls180.v:2034.3-2049.6" - process $proc$issuer_ls180.v:2034$37 + attribute \src "libresoc.v:831.3-839.6" + process $proc$libresoc.v:831$161 assign { } { } assign { } { } - assign $0\ALU_dec31_dec_sub0_internal_op[6:0] $1\ALU_dec31_dec_sub0_internal_op[6:0] - attribute \src "issuer_ls180.v:2035.5-2035.29" + assign $0\dmi_req_i_1$next[0:0]$162 $1\dmi_req_i_1$next[0:0]$163 + attribute \src "libresoc.v:832.5-832.29" switch \initial - attribute \src "issuer_ls180.v:2035.9-2035.17" + attribute \src "libresoc.v:832.9-832.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0001010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0001100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0001010 + assign $1\dmi_req_i_1$next[0:0]$163 1'0 case - assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0000000 + assign $1\dmi_req_i_1$next[0:0]$163 \dmi_req_i end sync always - update \ALU_dec31_dec_sub0_internal_op $0\ALU_dec31_dec_sub0_internal_op[6:0] + update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$162 end - attribute \src "issuer_ls180.v:2050.3-2065.6" - process $proc$issuer_ls180.v:2050$38 + attribute \src "libresoc.v:840.3-889.6" + process $proc$libresoc.v:840$164 + assign { } { } assign { } { } assign { } { } - assign $0\ALU_dec31_dec_sub0_in1_sel[2:0] $1\ALU_dec31_dec_sub0_in1_sel[2:0] - attribute \src "issuer_ls180.v:2051.5-2051.29" + assign { } { } + assign $0\terminated$next[0:0]$165 $8\terminated$next[0:0]$173 + attribute \src "libresoc.v:841.5-841.29" switch \initial - attribute \src "issuer_ls180.v:2051.9-2051.17" + attribute \src "libresoc.v:841.9-841.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$65 \$61 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 assign { } { } - assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 + assign $1\terminated$next[0:0]$166 $2\terminated$next[0:0]$167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\terminated$next[0:0]$167 $3\terminated$next[0:0]$168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$71 \$69 \$67 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign { } { } + assign { } { } + assign $3\terminated$next[0:0]$168 $6\terminated$next[0:0]$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" + switch \dmi_din [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\terminated$next[0:0]$169 1'0 + case + assign $4\terminated$next[0:0]$169 \terminated + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" + switch \dmi_din [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\terminated$next[0:0]$170 1'0 + case + assign $5\terminated$next[0:0]$170 $4\terminated$next[0:0]$169 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" + switch \dmi_din [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\terminated$next[0:0]$171 1'0 + case + assign $6\terminated$next[0:0]$171 $5\terminated$next[0:0]$170 + end + case + assign $3\terminated$next[0:0]$168 \terminated + end + case + assign $2\terminated$next[0:0]$167 \terminated + end + case + assign $1\terminated$next[0:0]$166 \terminated + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" + switch \terminate_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $7\terminated$next[0:0]$172 1'1 + case + assign $7\terminated$next[0:0]$172 $1\terminated$next[0:0]$166 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'001 + assign $8\terminated$next[0:0]$173 1'0 case - assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'000 + assign $8\terminated$next[0:0]$173 $7\terminated$next[0:0]$172 end sync always - update \ALU_dec31_dec_sub0_in1_sel $0\ALU_dec31_dec_sub0_in1_sel[2:0] + update \terminated$next $0\terminated$next[0:0]$165 end - attribute \src "issuer_ls180.v:2066.3-2081.6" - process $proc$issuer_ls180.v:2066$39 + attribute \src "libresoc.v:890.3-933.6" + process $proc$libresoc.v:890$174 + assign { } { } assign { } { } assign { } { } - assign $0\ALU_dec31_dec_sub0_in2_sel[3:0] $1\ALU_dec31_dec_sub0_in2_sel[3:0] - attribute \src "issuer_ls180.v:2067.5-2067.29" + assign { } { } + assign $0\stopping$next[0:0]$175 $7\stopping$next[0:0]$182 + attribute \src "libresoc.v:891.5-891.29" switch \initial - attribute \src "issuer_ls180.v:2067.9-2067.17" + attribute \src "libresoc.v:891.9-891.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$79 \$75 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 assign { } { } - assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 + assign $1\stopping$next[0:0]$176 $2\stopping$next[0:0]$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\stopping$next[0:0]$177 $3\stopping$next[0:0]$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$85 \$83 \$81 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign { } { } + assign $3\stopping$next[0:0]$178 $5\stopping$next[0:0]$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" + switch \dmi_din [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\stopping$next[0:0]$179 1'1 + case + assign $4\stopping$next[0:0]$179 \stopping + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" + switch \dmi_din [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\stopping$next[0:0]$180 1'0 + case + assign $5\stopping$next[0:0]$180 $4\stopping$next[0:0]$179 + end + case + assign $3\stopping$next[0:0]$178 \stopping + end + case + assign $2\stopping$next[0:0]$177 \stopping + end + case + assign $1\stopping$next[0:0]$176 \stopping + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" + switch \terminate_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $6\stopping$next[0:0]$181 1'1 + case + assign $6\stopping$next[0:0]$181 $1\stopping$next[0:0]$176 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0001 + assign $7\stopping$next[0:0]$182 1'0 case - assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0000 + assign $7\stopping$next[0:0]$182 $6\stopping$next[0:0]$181 end sync always - update \ALU_dec31_dec_sub0_in2_sel $0\ALU_dec31_dec_sub0_in2_sel[3:0] + update \stopping$next $0\stopping$next[0:0]$175 end - attribute \src "issuer_ls180.v:2082.3-2097.6" - process $proc$issuer_ls180.v:2082$40 + attribute \src "libresoc.v:934.3-961.6" + process $proc$libresoc.v:934$183 assign { } { } assign { } { } - assign $0\ALU_dec31_dec_sub0_cr_in[2:0] $1\ALU_dec31_dec_sub0_cr_in[2:0] - attribute \src "issuer_ls180.v:2083.5-2083.29" + assign { } { } + assign $0\gspr_index$next[6:0]$184 $4\gspr_index$next[6:0]$188 + attribute \src "libresoc.v:935.5-935.29" switch \initial - attribute \src "issuer_ls180.v:2083.9-2083.17" + attribute \src "libresoc.v:935.9-935.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$93 \$89 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 assign { } { } - assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $1\gspr_index$next[6:0]$185 $2\gspr_index$next[6:0]$186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\gspr_index$next[6:0]$186 $3\gspr_index$next[6:0]$187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$99 \$97 \$95 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $3\gspr_index$next[6:0]$187 \gspr_index + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $3\gspr_index$next[6:0]$187 \dmi_din [6:0] + case + assign $3\gspr_index$next[6:0]$187 \gspr_index + end + case + assign $2\gspr_index$next[6:0]$186 \gspr_index + end + case + assign $1\gspr_index$next[6:0]$185 \gspr_index + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 + assign $4\gspr_index$next[6:0]$188 7'0000000 case - assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 + assign $4\gspr_index$next[6:0]$188 $1\gspr_index$next[6:0]$185 end sync always - update \ALU_dec31_dec_sub0_cr_in $0\ALU_dec31_dec_sub0_cr_in[2:0] + update \gspr_index$next $0\gspr_index$next[6:0]$184 end - attribute \src "issuer_ls180.v:2098.3-2113.6" - process $proc$issuer_ls180.v:2098$41 + attribute \src "libresoc.v:962.3-995.6" + process $proc$libresoc.v:962$189 + assign { } { } assign { } { } assign { } { } - assign $0\ALU_dec31_dec_sub0_cr_out[2:0] $1\ALU_dec31_dec_sub0_cr_out[2:0] - attribute \src "issuer_ls180.v:2099.5-2099.29" + assign $0\log_dmi_addr$next[31:0]$190 $4\log_dmi_addr$next[31:0]$194 + attribute \src "libresoc.v:963.5-963.29" switch \initial - attribute \src "issuer_ls180.v:2099.9-2099.17" + attribute \src "libresoc.v:963.9-963.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'010 - case - assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub0_cr_out $0\ALU_dec31_dec_sub0_cr_out[2:0] - end - attribute \src "issuer_ls180.v:2114.3-2129.6" - process $proc$issuer_ls180.v:2114$42 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub0_ldst_len[3:0] $1\ALU_dec31_dec_sub0_ldst_len[3:0] - attribute \src "issuer_ls180.v:2115.5-2115.29" - switch \initial - attribute \src "issuer_ls180.v:2115.9-2115.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$107 \$103 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 assign { } { } - assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 + assign $1\log_dmi_addr$next[31:0]$191 $2\log_dmi_addr$next[31:0]$192 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\log_dmi_addr$next[31:0]$192 $3\log_dmi_addr$next[31:0]$193 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$113 \$111 \$109 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $3\log_dmi_addr$next[31:0]$193 \log_dmi_addr + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $3\log_dmi_addr$next[31:0]$193 \log_dmi_addr + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $3\log_dmi_addr$next[31:0]$193 \dmi_din [31:0] + case + assign $3\log_dmi_addr$next[31:0]$193 \log_dmi_addr + end + case + assign $2\log_dmi_addr$next[31:0]$192 \log_dmi_addr + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign $1\log_dmi_addr$next[31:0]$191 [31:2] \log_dmi_addr [31:2] + assign $1\log_dmi_addr$next[31:0]$191 [1:0] \$115 [1:0] case - assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 + assign $1\log_dmi_addr$next[31:0]$191 \log_dmi_addr end - sync always - update \ALU_dec31_dec_sub0_ldst_len $0\ALU_dec31_dec_sub0_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:2130.3-2145.6" - process $proc$issuer_ls180.v:2130$43 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub0_rc_sel[1:0] $1\ALU_dec31_dec_sub0_rc_sel[1:0] - attribute \src "issuer_ls180.v:2131.5-2131.29" - switch \initial - attribute \src "issuer_ls180.v:2131.9-2131.17" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 assign { } { } - assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 + assign $4\log_dmi_addr$next[31:0]$194 0 case - assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 + assign $4\log_dmi_addr$next[31:0]$194 $1\log_dmi_addr$next[31:0]$191 end sync always - update \ALU_dec31_dec_sub0_rc_sel $0\ALU_dec31_dec_sub0_rc_sel[1:0] + update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$190 end - attribute \src "issuer_ls180.v:2146.3-2161.6" - process $proc$issuer_ls180.v:2146$44 + attribute \src "libresoc.v:996.3-1004.6" + process $proc$libresoc.v:996$195 assign { } { } assign { } { } - assign $0\ALU_dec31_dec_sub0_cry_in[1:0] $1\ALU_dec31_dec_sub0_cry_in[1:0] - attribute \src "issuer_ls180.v:2147.5-2147.29" + assign $0\dmi_read_log_data_1$next[0:0]$196 $1\dmi_read_log_data_1$next[0:0]$197 + attribute \src "libresoc.v:997.5-997.29" switch \initial - attribute \src "issuer_ls180.v:2147.9-2147.17" + attribute \src "libresoc.v:997.9-997.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'01 - case - assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'00 - end - sync always - update \ALU_dec31_dec_sub0_cry_in $0\ALU_dec31_dec_sub0_cry_in[1:0] - end - connect \opcode_switch \opcode_in [10:6] + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi_read_log_data_1$next[0:0]$197 1'0 + case + assign $1\dmi_read_log_data_1$next[0:0]$197 \dmi_read_log_data + end + sync always + update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$196 + end + connect \$9 $and$libresoc.v:719$86_Y + connect \$99 $eq$libresoc.v:720$87_Y + connect \$101 $not$libresoc.v:721$88_Y + connect \$103 $and$libresoc.v:722$89_Y + connect \$105 $not$libresoc.v:723$90_Y + connect \$107 $and$libresoc.v:724$91_Y + connect \$109 $eq$libresoc.v:725$92_Y + connect \$111 $eq$libresoc.v:726$93_Y + connect \$113 $eq$libresoc.v:727$94_Y + connect \$116 $add$libresoc.v:728$95_Y + connect \$118 $eq$libresoc.v:729$96_Y + connect \$11 $eq$libresoc.v:730$97_Y + connect \$120 $and$libresoc.v:731$98_Y + connect \$122 $not$libresoc.v:732$99_Y + connect \$124 $and$libresoc.v:733$100_Y + connect \$13 $eq$libresoc.v:734$101_Y + connect \$15 $eq$libresoc.v:735$102_Y + connect \$17 $not$libresoc.v:736$103_Y + connect \$1 $pos$libresoc.v:737$104_Y + connect \$19 $and$libresoc.v:738$105_Y + connect \$21 $not$libresoc.v:739$106_Y + connect \$23 $and$libresoc.v:740$107_Y + connect \$25 $eq$libresoc.v:741$108_Y + connect \$27 $eq$libresoc.v:742$109_Y + connect \$29 $eq$libresoc.v:743$110_Y + connect \$31 $not$libresoc.v:744$111_Y + connect \$33 $and$libresoc.v:745$112_Y + connect \$35 $not$libresoc.v:746$113_Y + connect \$37 $and$libresoc.v:747$114_Y + connect \$3 $not$libresoc.v:748$115_Y + connect \$39 $eq$libresoc.v:749$116_Y + connect \$41 $eq$libresoc.v:750$117_Y + connect \$43 $eq$libresoc.v:751$118_Y + connect \$45 $not$libresoc.v:752$119_Y + connect \$47 $and$libresoc.v:753$120_Y + connect \$49 $not$libresoc.v:754$121_Y + connect \$51 $and$libresoc.v:755$122_Y + connect \$53 $eq$libresoc.v:756$123_Y + connect \$55 $eq$libresoc.v:757$124_Y + connect \$57 $eq$libresoc.v:758$125_Y + connect \$5 $and$libresoc.v:759$126_Y + connect \$59 $not$libresoc.v:760$127_Y + connect \$61 $and$libresoc.v:761$128_Y + connect \$63 $not$libresoc.v:762$129_Y + connect \$65 $and$libresoc.v:763$130_Y + connect \$67 $eq$libresoc.v:764$131_Y + connect \$69 $eq$libresoc.v:765$132_Y + connect \$71 $eq$libresoc.v:766$133_Y + connect \$73 $not$libresoc.v:767$134_Y + connect \$75 $and$libresoc.v:768$135_Y + connect \$77 $not$libresoc.v:769$136_Y + connect \$7 $not$libresoc.v:770$137_Y + connect \$79 $and$libresoc.v:771$138_Y + connect \$81 $eq$libresoc.v:772$139_Y + connect \$83 $eq$libresoc.v:773$140_Y + connect \$85 $eq$libresoc.v:774$141_Y + connect \$87 $not$libresoc.v:775$142_Y + connect \$89 $and$libresoc.v:776$143_Y + connect \$91 $not$libresoc.v:777$144_Y + connect \$93 $and$libresoc.v:778$145_Y + connect \$95 $eq$libresoc.v:779$146_Y + connect \$97 $eq$libresoc.v:780$147_Y + connect \$115 \$116 + connect \log_write_addr_o 0 + connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \terminated_o \terminated + connect \icache_rst_o \do_icreset + connect \core_rst_o \do_reset + connect \core_stop_o \$124 + connect \d_gpr_addr \gspr_index + connect \stat_reg \$1 end -attribute \src "issuer_ls180.v:2167.1-2870.10" +attribute \src "libresoc.v:1202.1-7135.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub10" +attribute \nmigen.hierarchy "test_issuer.dec2.dec" attribute \generator "nMigen" -module \ALU_dec31_dec_sub10 - attribute \src "issuer_ls180.v:2684.3-2720.6" - wire width 3 $0\ALU_dec31_dec_sub10_cr_in[2:0] - attribute \src "issuer_ls180.v:2721.3-2757.6" - wire width 3 $0\ALU_dec31_dec_sub10_cr_out[2:0] - attribute \src "issuer_ls180.v:2832.3-2868.6" - wire width 2 $0\ALU_dec31_dec_sub10_cry_in[1:0] - attribute \src "issuer_ls180.v:2462.3-2498.6" - wire $0\ALU_dec31_dec_sub10_cry_out[0:0] - attribute \src "issuer_ls180.v:2351.3-2387.6" - wire width 12 $0\ALU_dec31_dec_sub10_function_unit[11:0] - attribute \src "issuer_ls180.v:2610.3-2646.6" - wire width 3 $0\ALU_dec31_dec_sub10_in1_sel[2:0] - attribute \src "issuer_ls180.v:2647.3-2683.6" - wire width 4 $0\ALU_dec31_dec_sub10_in2_sel[3:0] - attribute \src "issuer_ls180.v:2573.3-2609.6" - wire width 7 $0\ALU_dec31_dec_sub10_internal_op[6:0] - attribute \src "issuer_ls180.v:2388.3-2424.6" - wire $0\ALU_dec31_dec_sub10_inv_a[0:0] - attribute \src "issuer_ls180.v:2425.3-2461.6" - wire $0\ALU_dec31_dec_sub10_inv_out[0:0] - attribute \src "issuer_ls180.v:2499.3-2535.6" - wire $0\ALU_dec31_dec_sub10_is_32b[0:0] - attribute \src "issuer_ls180.v:2758.3-2794.6" - wire width 4 $0\ALU_dec31_dec_sub10_ldst_len[3:0] - attribute \src "issuer_ls180.v:2795.3-2831.6" - wire width 2 $0\ALU_dec31_dec_sub10_rc_sel[1:0] - attribute \src "issuer_ls180.v:2536.3-2572.6" - wire $0\ALU_dec31_dec_sub10_sgn[0:0] - attribute \src "issuer_ls180.v:2168.7-2168.20" +module \dec + attribute \src "libresoc.v:3396.3-3534.6" + wire width 8 $0\asmcode[7:0] + attribute \src "libresoc.v:5381.3-5522.6" + wire $0\br[0:0] + attribute \src "libresoc.v:4103.3-4244.6" + wire width 3 $0\cr_in[2:0] + attribute \src "libresoc.v:4245.3-4386.6" + wire width 3 $0\cr_out[2:0] + attribute \src "libresoc.v:4813.3-4954.6" + wire width 2 $0\cry_in[1:0] + attribute \src "libresoc.v:5239.3-5380.6" + wire $0\cry_out[0:0] + attribute \src "libresoc.v:6659.3-6800.6" + wire width 5 $0\form[4:0] + attribute \src "libresoc.v:6375.3-6516.6" + wire width 12 $0\function_unit[11:0] + attribute \src "libresoc.v:3535.3-3676.6" + wire width 3 $0\in1_sel[2:0] + attribute \src "libresoc.v:3677.3-3818.6" + wire width 4 $0\in2_sel[3:0] + attribute \src "libresoc.v:3819.3-3960.6" + wire width 2 $0\in3_sel[1:0] + attribute \src "libresoc.v:1203.7-1203.20" wire $0\initial[0:0] - attribute \src "issuer_ls180.v:2684.3-2720.6" - wire width 3 $1\ALU_dec31_dec_sub10_cr_in[2:0] - attribute \src "issuer_ls180.v:2721.3-2757.6" - wire width 3 $1\ALU_dec31_dec_sub10_cr_out[2:0] - attribute \src "issuer_ls180.v:2832.3-2868.6" - wire width 2 $1\ALU_dec31_dec_sub10_cry_in[1:0] - attribute \src "issuer_ls180.v:2462.3-2498.6" - wire $1\ALU_dec31_dec_sub10_cry_out[0:0] - attribute \src "issuer_ls180.v:2351.3-2387.6" - wire width 12 $1\ALU_dec31_dec_sub10_function_unit[11:0] - attribute \src "issuer_ls180.v:2610.3-2646.6" - wire width 3 $1\ALU_dec31_dec_sub10_in1_sel[2:0] - attribute \src "issuer_ls180.v:2647.3-2683.6" - wire width 4 $1\ALU_dec31_dec_sub10_in2_sel[3:0] - attribute \src "issuer_ls180.v:2573.3-2609.6" - wire width 7 $1\ALU_dec31_dec_sub10_internal_op[6:0] - attribute \src "issuer_ls180.v:2388.3-2424.6" - wire $1\ALU_dec31_dec_sub10_inv_a[0:0] - attribute \src "issuer_ls180.v:2425.3-2461.6" - wire $1\ALU_dec31_dec_sub10_inv_out[0:0] - attribute \src "issuer_ls180.v:2499.3-2535.6" - wire $1\ALU_dec31_dec_sub10_is_32b[0:0] - attribute \src "issuer_ls180.v:2758.3-2794.6" - wire width 4 $1\ALU_dec31_dec_sub10_ldst_len[3:0] - attribute \src "issuer_ls180.v:2795.3-2831.6" - wire width 2 $1\ALU_dec31_dec_sub10_rc_sel[1:0] - attribute \src "issuer_ls180.v:2536.3-2572.6" - wire $1\ALU_dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:6517.3-6658.6" + wire width 7 $0\internal_op[6:0] + attribute \src "libresoc.v:4955.3-5096.6" + wire $0\inv_a[0:0] + attribute \src "libresoc.v:5097.3-5238.6" + wire $0\inv_out[0:0] + attribute \src "libresoc.v:5807.3-5948.6" + wire $0\is_32b[0:0] + attribute \src "libresoc.v:4387.3-4528.6" + wire width 4 $0\ldst_len[3:0] + attribute \src "libresoc.v:6091.3-6232.6" + wire $0\lk[0:0] + attribute \src "libresoc.v:3961.3-4102.6" + wire width 2 $0\out_sel[1:0] + attribute \src "libresoc.v:4671.3-4812.6" + wire width 2 $0\rc_sel[1:0] + attribute \src "libresoc.v:5665.3-5806.6" + wire $0\rsrv[0:0] + attribute \src "libresoc.v:6233.3-6374.6" + wire $0\sgl_pipe[0:0] + attribute \src "libresoc.v:5949.3-6090.6" + wire $0\sgn[0:0] + attribute \src "libresoc.v:5523.3-5664.6" + wire $0\sgn_ext[0:0] + attribute \src "libresoc.v:4529.3-4670.6" + wire width 2 $0\upd[1:0] + attribute \src "libresoc.v:3396.3-3534.6" + wire width 8 $1\asmcode[7:0] + attribute \src "libresoc.v:5381.3-5522.6" + wire $1\br[0:0] + attribute \src "libresoc.v:4103.3-4244.6" + wire width 3 $1\cr_in[2:0] + attribute \src "libresoc.v:4245.3-4386.6" + wire width 3 $1\cr_out[2:0] + attribute \src "libresoc.v:4813.3-4954.6" + wire width 2 $1\cry_in[1:0] + attribute \src "libresoc.v:5239.3-5380.6" + wire $1\cry_out[0:0] + attribute \src "libresoc.v:6659.3-6800.6" + wire width 5 $1\form[4:0] + attribute \src "libresoc.v:6375.3-6516.6" + wire width 12 $1\function_unit[11:0] + attribute \src "libresoc.v:3535.3-3676.6" + wire width 3 $1\in1_sel[2:0] + attribute \src "libresoc.v:3677.3-3818.6" + wire width 4 $1\in2_sel[3:0] + attribute \src "libresoc.v:3819.3-3960.6" + wire width 2 $1\in3_sel[1:0] + attribute \src "libresoc.v:6517.3-6658.6" + wire width 7 $1\internal_op[6:0] + attribute \src "libresoc.v:4955.3-5096.6" + wire $1\inv_a[0:0] + attribute \src "libresoc.v:5097.3-5238.6" + wire $1\inv_out[0:0] + attribute \src "libresoc.v:5807.3-5948.6" + wire $1\is_32b[0:0] + attribute \src "libresoc.v:4387.3-4528.6" + wire width 4 $1\ldst_len[3:0] + attribute \src "libresoc.v:6091.3-6232.6" + wire $1\lk[0:0] + attribute \src "libresoc.v:3961.3-4102.6" + wire width 2 $1\out_sel[1:0] + attribute \src "libresoc.v:4671.3-4812.6" + wire width 2 $1\rc_sel[1:0] + attribute \src "libresoc.v:5665.3-5806.6" + wire $1\rsrv[0:0] + attribute \src "libresoc.v:6233.3-6374.6" + wire $1\sgl_pipe[0:0] + attribute \src "libresoc.v:5949.3-6090.6" + wire $1\sgn[0:0] + attribute \src "libresoc.v:5523.3-5664.6" + wire $1\sgn_ext[0:0] + attribute \src "libresoc.v:4529.3-4670.6" + wire width 2 $1\upd[1:0] + attribute \src "libresoc.v:3396.3-3534.6" + wire width 8 $2\asmcode[7:0] + attribute \src "libresoc.v:5381.3-5522.6" + wire $2\br[0:0] + attribute \src "libresoc.v:4103.3-4244.6" + wire width 3 $2\cr_in[2:0] + attribute \src "libresoc.v:4245.3-4386.6" + wire width 3 $2\cr_out[2:0] + attribute \src "libresoc.v:4813.3-4954.6" + wire width 2 $2\cry_in[1:0] + attribute \src "libresoc.v:5239.3-5380.6" + wire $2\cry_out[0:0] + attribute \src "libresoc.v:6659.3-6800.6" + wire width 5 $2\form[4:0] + attribute \src "libresoc.v:6375.3-6516.6" + wire width 12 $2\function_unit[11:0] + attribute \src "libresoc.v:3535.3-3676.6" + wire width 3 $2\in1_sel[2:0] + attribute \src "libresoc.v:3677.3-3818.6" + wire width 4 $2\in2_sel[3:0] + attribute \src "libresoc.v:3819.3-3960.6" + wire width 2 $2\in3_sel[1:0] + attribute \src "libresoc.v:6517.3-6658.6" + wire width 7 $2\internal_op[6:0] + attribute \src "libresoc.v:4955.3-5096.6" + wire $2\inv_a[0:0] + attribute \src "libresoc.v:5097.3-5238.6" + wire $2\inv_out[0:0] + attribute \src "libresoc.v:5807.3-5948.6" + wire $2\is_32b[0:0] + attribute \src "libresoc.v:4387.3-4528.6" + wire width 4 $2\ldst_len[3:0] + attribute \src "libresoc.v:6091.3-6232.6" + wire $2\lk[0:0] + attribute \src "libresoc.v:3961.3-4102.6" + wire width 2 $2\out_sel[1:0] + attribute \src "libresoc.v:4671.3-4812.6" + wire width 2 $2\rc_sel[1:0] + attribute \src "libresoc.v:5665.3-5806.6" + wire $2\rsrv[0:0] + attribute \src "libresoc.v:6233.3-6374.6" + wire $2\sgl_pipe[0:0] + attribute \src "libresoc.v:5949.3-6090.6" + wire $2\sgn[0:0] + attribute \src "libresoc.v:5523.3-5664.6" + wire $2\sgn_ext[0:0] + attribute \src "libresoc.v:4529.3-4670.6" + wire width 2 $2\upd[1:0] + attribute \src "libresoc.v:3260.17-3260.211" + wire width 32 $ternary$libresoc.v:3260$243_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + wire width 32 \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 25 \BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 24 \BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 30 \BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 3 \BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 2 \BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 29 \BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 28 \BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 26 \BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 output 27 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 \LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 11 \LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 23 \OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 20 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 21 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 18 \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 19 \RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 22 \Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 output 31 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 output 34 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 output 35 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 32 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 33 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 16 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 36 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec19_dec19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -3036,7 +4294,7 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \ALU_dec31_dec_sub10_cr_in + wire width 3 \dec19_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -3044,15 +4302,47 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 6 \ALU_dec31_dec_sub10_cr_out + wire width 3 \dec19_dec19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 9 \ALU_dec31_dec_sub10_cry_in + wire width 2 \dec19_dec19_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 12 \ALU_dec31_dec_sub10_cry_out + wire \dec19_dec19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec19_dec19_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -3067,7 +4357,7 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \ALU_dec31_dec_sub10_function_unit + wire width 12 \dec19_dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -3075,7 +4365,7 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \ALU_dec31_dec_sub10_in1_sel + wire width 3 \dec19_dec19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -3092,7 +4382,13 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 4 \ALU_dec31_dec_sub10_in2_sel + wire width 4 \dec19_dec19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec19_dec19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -3168,13 +4464,13 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \ALU_dec31_dec_sub10_internal_op + wire width 7 \dec19_dec19_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \ALU_dec31_dec_sub10_inv_a + wire \dec19_dec19_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 11 \ALU_dec31_dec_sub10_inv_out + wire \dec19_dec19_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 13 \ALU_dec31_dec_sub10_is_32b + wire \dec19_dec19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -3182,920 +4478,43 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 7 \ALU_dec31_dec_sub10_ldst_len + wire width 4 \dec19_dec19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec19_dec19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \ALU_dec31_dec_sub10_rc_sel + wire width 2 \dec19_dec19_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 14 \ALU_dec31_dec_sub10_sgn - attribute \src "issuer_ls180.v:2168.7-2168.15" - wire \initial + wire \dec19_dec19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec19_dec19_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:2168.7-2168.20" - process $proc$issuer_ls180.v:2168$60 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:2351.3-2387.6" - process $proc$issuer_ls180.v:2351$46 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_function_unit[11:0] $1\ALU_dec31_dec_sub10_function_unit[11:0] - attribute \src "issuer_ls180.v:2352.5-2352.29" - switch \initial - attribute \src "issuer_ls180.v:2352.9-2352.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 - case - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000000 - end - sync always - update \ALU_dec31_dec_sub10_function_unit $0\ALU_dec31_dec_sub10_function_unit[11:0] - end - attribute \src "issuer_ls180.v:2388.3-2424.6" - process $proc$issuer_ls180.v:2388$47 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_inv_a[0:0] $1\ALU_dec31_dec_sub10_inv_a[0:0] - attribute \src "issuer_ls180.v:2389.5-2389.29" - switch \initial - attribute \src "issuer_ls180.v:2389.9-2389.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub10_inv_a $0\ALU_dec31_dec_sub10_inv_a[0:0] - end - attribute \src "issuer_ls180.v:2425.3-2461.6" - process $proc$issuer_ls180.v:2425$48 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_inv_out[0:0] $1\ALU_dec31_dec_sub10_inv_out[0:0] - attribute \src "issuer_ls180.v:2426.5-2426.29" - switch \initial - attribute \src "issuer_ls180.v:2426.9-2426.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub10_inv_out $0\ALU_dec31_dec_sub10_inv_out[0:0] - end - attribute \src "issuer_ls180.v:2462.3-2498.6" - process $proc$issuer_ls180.v:2462$49 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_cry_out[0:0] $1\ALU_dec31_dec_sub10_cry_out[0:0] - attribute \src "issuer_ls180.v:2463.5-2463.29" - switch \initial - attribute \src "issuer_ls180.v:2463.9-2463.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 - case - assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub10_cry_out $0\ALU_dec31_dec_sub10_cry_out[0:0] - end - attribute \src "issuer_ls180.v:2499.3-2535.6" - process $proc$issuer_ls180.v:2499$50 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_is_32b[0:0] $1\ALU_dec31_dec_sub10_is_32b[0:0] - attribute \src "issuer_ls180.v:2500.5-2500.29" - switch \initial - attribute \src "issuer_ls180.v:2500.9-2500.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub10_is_32b $0\ALU_dec31_dec_sub10_is_32b[0:0] - end - attribute \src "issuer_ls180.v:2536.3-2572.6" - process $proc$issuer_ls180.v:2536$51 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_sgn[0:0] $1\ALU_dec31_dec_sub10_sgn[0:0] - attribute \src "issuer_ls180.v:2537.5-2537.29" - switch \initial - attribute \src "issuer_ls180.v:2537.9-2537.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub10_sgn $0\ALU_dec31_dec_sub10_sgn[0:0] - end - attribute \src "issuer_ls180.v:2573.3-2609.6" - process $proc$issuer_ls180.v:2573$52 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_internal_op[6:0] $1\ALU_dec31_dec_sub10_internal_op[6:0] - attribute \src "issuer_ls180.v:2574.5-2574.29" - switch \initial - attribute \src "issuer_ls180.v:2574.9-2574.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 - case - assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000000 - end - sync always - update \ALU_dec31_dec_sub10_internal_op $0\ALU_dec31_dec_sub10_internal_op[6:0] - end - attribute \src "issuer_ls180.v:2610.3-2646.6" - process $proc$issuer_ls180.v:2610$53 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_in1_sel[2:0] $1\ALU_dec31_dec_sub10_in1_sel[2:0] - attribute \src "issuer_ls180.v:2611.5-2611.29" - switch \initial - attribute \src "issuer_ls180.v:2611.9-2611.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 - case - assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub10_in1_sel $0\ALU_dec31_dec_sub10_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:2647.3-2683.6" - process $proc$issuer_ls180.v:2647$54 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_in2_sel[3:0] $1\ALU_dec31_dec_sub10_in2_sel[3:0] - attribute \src "issuer_ls180.v:2648.5-2648.29" - switch \initial - attribute \src "issuer_ls180.v:2648.9-2648.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'1001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'1001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0000 - case - assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0000 - end - sync always - update \ALU_dec31_dec_sub10_in2_sel $0\ALU_dec31_dec_sub10_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:2684.3-2720.6" - process $proc$issuer_ls180.v:2684$55 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_cr_in[2:0] $1\ALU_dec31_dec_sub10_cr_in[2:0] - attribute \src "issuer_ls180.v:2685.5-2685.29" - switch \initial - attribute \src "issuer_ls180.v:2685.9-2685.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 - case - assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub10_cr_in $0\ALU_dec31_dec_sub10_cr_in[2:0] - end - attribute \src "issuer_ls180.v:2721.3-2757.6" - process $proc$issuer_ls180.v:2721$56 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_cr_out[2:0] $1\ALU_dec31_dec_sub10_cr_out[2:0] - attribute \src "issuer_ls180.v:2722.5-2722.29" - switch \initial - attribute \src "issuer_ls180.v:2722.9-2722.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 - case - assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub10_cr_out $0\ALU_dec31_dec_sub10_cr_out[2:0] - end - attribute \src "issuer_ls180.v:2758.3-2794.6" - process $proc$issuer_ls180.v:2758$57 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_ldst_len[3:0] $1\ALU_dec31_dec_sub10_ldst_len[3:0] - attribute \src "issuer_ls180.v:2759.5-2759.29" - switch \initial - attribute \src "issuer_ls180.v:2759.9-2759.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 - case - assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 - end - sync always - update \ALU_dec31_dec_sub10_ldst_len $0\ALU_dec31_dec_sub10_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:2795.3-2831.6" - process $proc$issuer_ls180.v:2795$58 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_rc_sel[1:0] $1\ALU_dec31_dec_sub10_rc_sel[1:0] - attribute \src "issuer_ls180.v:2796.5-2796.29" - switch \initial - attribute \src "issuer_ls180.v:2796.9-2796.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 - case - assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'00 - end - sync always - update \ALU_dec31_dec_sub10_rc_sel $0\ALU_dec31_dec_sub10_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:2832.3-2868.6" - process $proc$issuer_ls180.v:2832$59 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_cry_in[1:0] $1\ALU_dec31_dec_sub10_cry_in[1:0] - attribute \src "issuer_ls180.v:2833.5-2833.29" - switch \initial - attribute \src "issuer_ls180.v:2833.9-2833.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 - case - assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 - end - sync always - update \ALU_dec31_dec_sub10_cry_in $0\ALU_dec31_dec_sub10_cry_in[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:2874.1-3451.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub22" -attribute \generator "nMigen" -module \ALU_dec31_dec_sub22 - attribute \src "issuer_ls180.v:3310.3-3337.6" - wire width 3 $0\ALU_dec31_dec_sub22_cr_in[2:0] - attribute \src "issuer_ls180.v:3338.3-3365.6" - wire width 3 $0\ALU_dec31_dec_sub22_cr_out[2:0] - attribute \src "issuer_ls180.v:3422.3-3449.6" - wire width 2 $0\ALU_dec31_dec_sub22_cry_in[1:0] - attribute \src "issuer_ls180.v:3142.3-3169.6" - wire $0\ALU_dec31_dec_sub22_cry_out[0:0] - attribute \src "issuer_ls180.v:3058.3-3085.6" - wire width 12 $0\ALU_dec31_dec_sub22_function_unit[11:0] - attribute \src "issuer_ls180.v:3254.3-3281.6" - wire width 3 $0\ALU_dec31_dec_sub22_in1_sel[2:0] - attribute \src "issuer_ls180.v:3282.3-3309.6" - wire width 4 $0\ALU_dec31_dec_sub22_in2_sel[3:0] - attribute \src "issuer_ls180.v:3226.3-3253.6" - wire width 7 $0\ALU_dec31_dec_sub22_internal_op[6:0] - attribute \src "issuer_ls180.v:3086.3-3113.6" - wire $0\ALU_dec31_dec_sub22_inv_a[0:0] - attribute \src "issuer_ls180.v:3114.3-3141.6" - wire $0\ALU_dec31_dec_sub22_inv_out[0:0] - attribute \src "issuer_ls180.v:3170.3-3197.6" - wire $0\ALU_dec31_dec_sub22_is_32b[0:0] - attribute \src "issuer_ls180.v:3366.3-3393.6" - wire width 4 $0\ALU_dec31_dec_sub22_ldst_len[3:0] - attribute \src "issuer_ls180.v:3394.3-3421.6" - wire width 2 $0\ALU_dec31_dec_sub22_rc_sel[1:0] - attribute \src "issuer_ls180.v:3198.3-3225.6" - wire $0\ALU_dec31_dec_sub22_sgn[0:0] - attribute \src "issuer_ls180.v:2875.7-2875.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:3310.3-3337.6" - wire width 3 $1\ALU_dec31_dec_sub22_cr_in[2:0] - attribute \src "issuer_ls180.v:3338.3-3365.6" - wire width 3 $1\ALU_dec31_dec_sub22_cr_out[2:0] - attribute \src "issuer_ls180.v:3422.3-3449.6" - wire width 2 $1\ALU_dec31_dec_sub22_cry_in[1:0] - attribute \src "issuer_ls180.v:3142.3-3169.6" - wire $1\ALU_dec31_dec_sub22_cry_out[0:0] - attribute \src "issuer_ls180.v:3058.3-3085.6" - wire width 12 $1\ALU_dec31_dec_sub22_function_unit[11:0] - attribute \src "issuer_ls180.v:3254.3-3281.6" - wire width 3 $1\ALU_dec31_dec_sub22_in1_sel[2:0] - attribute \src "issuer_ls180.v:3282.3-3309.6" - wire width 4 $1\ALU_dec31_dec_sub22_in2_sel[3:0] - attribute \src "issuer_ls180.v:3226.3-3253.6" - wire width 7 $1\ALU_dec31_dec_sub22_internal_op[6:0] - attribute \src "issuer_ls180.v:3086.3-3113.6" - wire $1\ALU_dec31_dec_sub22_inv_a[0:0] - attribute \src "issuer_ls180.v:3114.3-3141.6" - wire $1\ALU_dec31_dec_sub22_inv_out[0:0] - attribute \src "issuer_ls180.v:3170.3-3197.6" - wire $1\ALU_dec31_dec_sub22_is_32b[0:0] - attribute \src "issuer_ls180.v:3366.3-3393.6" - wire width 4 $1\ALU_dec31_dec_sub22_ldst_len[3:0] - attribute \src "issuer_ls180.v:3394.3-3421.6" - wire width 2 $1\ALU_dec31_dec_sub22_rc_sel[1:0] - attribute \src "issuer_ls180.v:3198.3-3225.6" - wire $1\ALU_dec31_dec_sub22_sgn[0:0] + wire width 32 \dec19_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec30_dec30_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -4105,7 +4524,7 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \ALU_dec31_dec_sub22_cr_in + wire width 3 \dec30_dec30_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -4113,15 +4532,47 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 6 \ALU_dec31_dec_sub22_cr_out + wire width 3 \dec30_dec30_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 9 \ALU_dec31_dec_sub22_cry_in + wire width 2 \dec30_dec30_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 12 \ALU_dec31_dec_sub22_cry_out + wire \dec30_dec30_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec30_dec30_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -4136,7 +4587,7 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \ALU_dec31_dec_sub22_function_unit + wire width 12 \dec30_dec30_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -4144,7 +4595,7 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \ALU_dec31_dec_sub22_in1_sel + wire width 3 \dec30_dec30_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -4161,7 +4612,13 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 4 \ALU_dec31_dec_sub22_in2_sel + wire width 4 \dec30_dec30_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec30_dec30_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -4237,13 +4694,13 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \ALU_dec31_dec_sub22_internal_op + wire width 7 \dec30_dec30_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \ALU_dec31_dec_sub22_inv_a + wire \dec30_dec30_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 11 \ALU_dec31_dec_sub22_inv_out + wire \dec30_dec30_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 13 \ALU_dec31_dec_sub22_is_32b + wire \dec30_dec30_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -4251,752 +4708,43 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 7 \ALU_dec31_dec_sub22_ldst_len + wire width 4 \dec30_dec30_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec30_dec30_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \ALU_dec31_dec_sub22_rc_sel + wire width 2 \dec30_dec30_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 14 \ALU_dec31_dec_sub22_sgn - attribute \src "issuer_ls180.v:2875.7-2875.15" - wire \initial + wire \dec30_dec30_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec30_dec30_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:2875.7-2875.20" - process $proc$issuer_ls180.v:2875$75 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:3058.3-3085.6" - process $proc$issuer_ls180.v:3058$61 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_function_unit[11:0] $1\ALU_dec31_dec_sub22_function_unit[11:0] - attribute \src "issuer_ls180.v:3059.5-3059.29" - switch \initial - attribute \src "issuer_ls180.v:3059.9-3059.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 - case - assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000000 - end - sync always - update \ALU_dec31_dec_sub22_function_unit $0\ALU_dec31_dec_sub22_function_unit[11:0] - end - attribute \src "issuer_ls180.v:3086.3-3113.6" - process $proc$issuer_ls180.v:3086$62 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_inv_a[0:0] $1\ALU_dec31_dec_sub22_inv_a[0:0] - attribute \src "issuer_ls180.v:3087.5-3087.29" - switch \initial - attribute \src "issuer_ls180.v:3087.9-3087.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub22_inv_a $0\ALU_dec31_dec_sub22_inv_a[0:0] - end - attribute \src "issuer_ls180.v:3114.3-3141.6" - process $proc$issuer_ls180.v:3114$63 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_inv_out[0:0] $1\ALU_dec31_dec_sub22_inv_out[0:0] - attribute \src "issuer_ls180.v:3115.5-3115.29" - switch \initial - attribute \src "issuer_ls180.v:3115.9-3115.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub22_inv_out $0\ALU_dec31_dec_sub22_inv_out[0:0] - end - attribute \src "issuer_ls180.v:3142.3-3169.6" - process $proc$issuer_ls180.v:3142$64 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_cry_out[0:0] $1\ALU_dec31_dec_sub22_cry_out[0:0] - attribute \src "issuer_ls180.v:3143.5-3143.29" - switch \initial - attribute \src "issuer_ls180.v:3143.9-3143.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub22_cry_out $0\ALU_dec31_dec_sub22_cry_out[0:0] - end - attribute \src "issuer_ls180.v:3170.3-3197.6" - process $proc$issuer_ls180.v:3170$65 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_is_32b[0:0] $1\ALU_dec31_dec_sub22_is_32b[0:0] - attribute \src "issuer_ls180.v:3171.5-3171.29" - switch \initial - attribute \src "issuer_ls180.v:3171.9-3171.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub22_is_32b $0\ALU_dec31_dec_sub22_is_32b[0:0] - end - attribute \src "issuer_ls180.v:3198.3-3225.6" - process $proc$issuer_ls180.v:3198$66 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_sgn[0:0] $1\ALU_dec31_dec_sub22_sgn[0:0] - attribute \src "issuer_ls180.v:3199.5-3199.29" - switch \initial - attribute \src "issuer_ls180.v:3199.9-3199.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub22_sgn $0\ALU_dec31_dec_sub22_sgn[0:0] - end - attribute \src "issuer_ls180.v:3226.3-3253.6" - process $proc$issuer_ls180.v:3226$67 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_internal_op[6:0] $1\ALU_dec31_dec_sub22_internal_op[6:0] - attribute \src "issuer_ls180.v:3227.5-3227.29" - switch \initial - attribute \src "issuer_ls180.v:3227.9-3227.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0100001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 - case - assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000000 - end - sync always - update \ALU_dec31_dec_sub22_internal_op $0\ALU_dec31_dec_sub22_internal_op[6:0] - end - attribute \src "issuer_ls180.v:3254.3-3281.6" - process $proc$issuer_ls180.v:3254$68 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_in1_sel[2:0] $1\ALU_dec31_dec_sub22_in1_sel[2:0] - attribute \src "issuer_ls180.v:3255.5-3255.29" - switch \initial - attribute \src "issuer_ls180.v:3255.9-3255.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 - case - assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub22_in1_sel $0\ALU_dec31_dec_sub22_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:3282.3-3309.6" - process $proc$issuer_ls180.v:3282$69 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_in2_sel[3:0] $1\ALU_dec31_dec_sub22_in2_sel[3:0] - attribute \src "issuer_ls180.v:3283.5-3283.29" - switch \initial - attribute \src "issuer_ls180.v:3283.9-3283.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 - case - assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 - end - sync always - update \ALU_dec31_dec_sub22_in2_sel $0\ALU_dec31_dec_sub22_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:3310.3-3337.6" - process $proc$issuer_ls180.v:3310$70 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_cr_in[2:0] $1\ALU_dec31_dec_sub22_cr_in[2:0] - attribute \src "issuer_ls180.v:3311.5-3311.29" - switch \initial - attribute \src "issuer_ls180.v:3311.9-3311.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 - case - assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub22_cr_in $0\ALU_dec31_dec_sub22_cr_in[2:0] - end - attribute \src "issuer_ls180.v:3338.3-3365.6" - process $proc$issuer_ls180.v:3338$71 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_cr_out[2:0] $1\ALU_dec31_dec_sub22_cr_out[2:0] - attribute \src "issuer_ls180.v:3339.5-3339.29" - switch \initial - attribute \src "issuer_ls180.v:3339.9-3339.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 - case - assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub22_cr_out $0\ALU_dec31_dec_sub22_cr_out[2:0] - end - attribute \src "issuer_ls180.v:3366.3-3393.6" - process $proc$issuer_ls180.v:3366$72 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_ldst_len[3:0] $1\ALU_dec31_dec_sub22_ldst_len[3:0] - attribute \src "issuer_ls180.v:3367.5-3367.29" - switch \initial - attribute \src "issuer_ls180.v:3367.9-3367.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 - case - assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 - end - sync always - update \ALU_dec31_dec_sub22_ldst_len $0\ALU_dec31_dec_sub22_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:3394.3-3421.6" - process $proc$issuer_ls180.v:3394$73 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_rc_sel[1:0] $1\ALU_dec31_dec_sub22_rc_sel[1:0] - attribute \src "issuer_ls180.v:3395.5-3395.29" - switch \initial - attribute \src "issuer_ls180.v:3395.9-3395.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 - case - assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 - end - sync always - update \ALU_dec31_dec_sub22_rc_sel $0\ALU_dec31_dec_sub22_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:3422.3-3449.6" - process $proc$issuer_ls180.v:3422$74 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_cry_in[1:0] $1\ALU_dec31_dec_sub22_cry_in[1:0] - attribute \src "issuer_ls180.v:3423.5-3423.29" - switch \initial - attribute \src "issuer_ls180.v:3423.9-3423.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 - case - assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 - end - sync always - update \ALU_dec31_dec_sub22_cry_in $0\ALU_dec31_dec_sub22_cry_in[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:3455.1-3864.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub26" -attribute \generator "nMigen" -module \ALU_dec31_dec_sub26 - attribute \src "issuer_ls180.v:3783.3-3798.6" - wire width 3 $0\ALU_dec31_dec_sub26_cr_in[2:0] - attribute \src "issuer_ls180.v:3799.3-3814.6" - wire width 3 $0\ALU_dec31_dec_sub26_cr_out[2:0] - attribute \src "issuer_ls180.v:3847.3-3862.6" - wire width 2 $0\ALU_dec31_dec_sub26_cry_in[1:0] - attribute \src "issuer_ls180.v:3687.3-3702.6" - wire $0\ALU_dec31_dec_sub26_cry_out[0:0] - attribute \src "issuer_ls180.v:3639.3-3654.6" - wire width 12 $0\ALU_dec31_dec_sub26_function_unit[11:0] - attribute \src "issuer_ls180.v:3751.3-3766.6" - wire width 3 $0\ALU_dec31_dec_sub26_in1_sel[2:0] - attribute \src "issuer_ls180.v:3767.3-3782.6" - wire width 4 $0\ALU_dec31_dec_sub26_in2_sel[3:0] - attribute \src "issuer_ls180.v:3735.3-3750.6" - wire width 7 $0\ALU_dec31_dec_sub26_internal_op[6:0] - attribute \src "issuer_ls180.v:3655.3-3670.6" - wire $0\ALU_dec31_dec_sub26_inv_a[0:0] - attribute \src "issuer_ls180.v:3671.3-3686.6" - wire $0\ALU_dec31_dec_sub26_inv_out[0:0] - attribute \src "issuer_ls180.v:3703.3-3718.6" - wire $0\ALU_dec31_dec_sub26_is_32b[0:0] - attribute \src "issuer_ls180.v:3815.3-3830.6" - wire width 4 $0\ALU_dec31_dec_sub26_ldst_len[3:0] - attribute \src "issuer_ls180.v:3831.3-3846.6" - wire width 2 $0\ALU_dec31_dec_sub26_rc_sel[1:0] - attribute \src "issuer_ls180.v:3719.3-3734.6" - wire $0\ALU_dec31_dec_sub26_sgn[0:0] - attribute \src "issuer_ls180.v:3456.7-3456.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:3783.3-3798.6" - wire width 3 $1\ALU_dec31_dec_sub26_cr_in[2:0] - attribute \src "issuer_ls180.v:3799.3-3814.6" - wire width 3 $1\ALU_dec31_dec_sub26_cr_out[2:0] - attribute \src "issuer_ls180.v:3847.3-3862.6" - wire width 2 $1\ALU_dec31_dec_sub26_cry_in[1:0] - attribute \src "issuer_ls180.v:3687.3-3702.6" - wire $1\ALU_dec31_dec_sub26_cry_out[0:0] - attribute \src "issuer_ls180.v:3639.3-3654.6" - wire width 12 $1\ALU_dec31_dec_sub26_function_unit[11:0] - attribute \src "issuer_ls180.v:3751.3-3766.6" - wire width 3 $1\ALU_dec31_dec_sub26_in1_sel[2:0] - attribute \src "issuer_ls180.v:3767.3-3782.6" - wire width 4 $1\ALU_dec31_dec_sub26_in2_sel[3:0] - attribute \src "issuer_ls180.v:3735.3-3750.6" - wire width 7 $1\ALU_dec31_dec_sub26_internal_op[6:0] - attribute \src "issuer_ls180.v:3655.3-3670.6" - wire $1\ALU_dec31_dec_sub26_inv_a[0:0] - attribute \src "issuer_ls180.v:3671.3-3686.6" - wire $1\ALU_dec31_dec_sub26_inv_out[0:0] - attribute \src "issuer_ls180.v:3703.3-3718.6" - wire $1\ALU_dec31_dec_sub26_is_32b[0:0] - attribute \src "issuer_ls180.v:3815.3-3830.6" - wire width 4 $1\ALU_dec31_dec_sub26_ldst_len[3:0] - attribute \src "issuer_ls180.v:3831.3-3846.6" - wire width 2 $1\ALU_dec31_dec_sub26_rc_sel[1:0] - attribute \src "issuer_ls180.v:3719.3-3734.6" - wire $1\ALU_dec31_dec_sub26_sgn[0:0] + wire width 32 \dec30_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec31_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -5006,7 +4754,7 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \ALU_dec31_dec_sub26_cr_in + wire width 3 \dec31_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -5014,15 +4762,47 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 6 \ALU_dec31_dec_sub26_cr_out + wire width 3 \dec31_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 9 \ALU_dec31_dec_sub26_cry_in + wire width 2 \dec31_dec31_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 12 \ALU_dec31_dec_sub26_cry_out + wire \dec31_dec31_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec31_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -5037,7 +4817,7 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \ALU_dec31_dec_sub26_function_unit + wire width 12 \dec31_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -5045,7 +4825,7 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \ALU_dec31_dec_sub26_in1_sel + wire width 3 \dec31_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -5062,7 +4842,13 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 4 \ALU_dec31_dec_sub26_in2_sel + wire width 4 \dec31_dec31_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec31_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -5138,13 +4924,13 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \ALU_dec31_dec_sub26_internal_op + wire width 7 \dec31_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \ALU_dec31_dec_sub26_inv_a + wire \dec31_dec31_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 11 \ALU_dec31_dec_sub26_inv_out + wire \dec31_dec31_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 13 \ALU_dec31_dec_sub26_is_32b + wire \dec31_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -5152,528 +4938,43 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 7 \ALU_dec31_dec_sub26_ldst_len + wire width 4 \dec31_dec31_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec31_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \ALU_dec31_dec_sub26_rc_sel + wire width 2 \dec31_dec31_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 14 \ALU_dec31_dec_sub26_sgn - attribute \src "issuer_ls180.v:3456.7-3456.15" - wire \initial + wire \dec31_dec31_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec31_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:3456.7-3456.20" - process $proc$issuer_ls180.v:3456$90 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:3639.3-3654.6" - process $proc$issuer_ls180.v:3639$76 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_function_unit[11:0] $1\ALU_dec31_dec_sub26_function_unit[11:0] - attribute \src "issuer_ls180.v:3640.5-3640.29" - switch \initial - attribute \src "issuer_ls180.v:3640.9-3640.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_function_unit[11:0] 12'000000000010 - case - assign $1\ALU_dec31_dec_sub26_function_unit[11:0] 12'000000000000 - end - sync always - update \ALU_dec31_dec_sub26_function_unit $0\ALU_dec31_dec_sub26_function_unit[11:0] - end - attribute \src "issuer_ls180.v:3655.3-3670.6" - process $proc$issuer_ls180.v:3655$77 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_inv_a[0:0] $1\ALU_dec31_dec_sub26_inv_a[0:0] - attribute \src "issuer_ls180.v:3656.5-3656.29" - switch \initial - attribute \src "issuer_ls180.v:3656.9-3656.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub26_inv_a $0\ALU_dec31_dec_sub26_inv_a[0:0] - end - attribute \src "issuer_ls180.v:3671.3-3686.6" - process $proc$issuer_ls180.v:3671$78 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_inv_out[0:0] $1\ALU_dec31_dec_sub26_inv_out[0:0] - attribute \src "issuer_ls180.v:3672.5-3672.29" - switch \initial - attribute \src "issuer_ls180.v:3672.9-3672.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub26_inv_out $0\ALU_dec31_dec_sub26_inv_out[0:0] - end - attribute \src "issuer_ls180.v:3687.3-3702.6" - process $proc$issuer_ls180.v:3687$79 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_cry_out[0:0] $1\ALU_dec31_dec_sub26_cry_out[0:0] - attribute \src "issuer_ls180.v:3688.5-3688.29" - switch \initial - attribute \src "issuer_ls180.v:3688.9-3688.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub26_cry_out $0\ALU_dec31_dec_sub26_cry_out[0:0] - end - attribute \src "issuer_ls180.v:3703.3-3718.6" - process $proc$issuer_ls180.v:3703$80 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_is_32b[0:0] $1\ALU_dec31_dec_sub26_is_32b[0:0] - attribute \src "issuer_ls180.v:3704.5-3704.29" - switch \initial - attribute \src "issuer_ls180.v:3704.9-3704.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub26_is_32b $0\ALU_dec31_dec_sub26_is_32b[0:0] - end - attribute \src "issuer_ls180.v:3719.3-3734.6" - process $proc$issuer_ls180.v:3719$81 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_sgn[0:0] $1\ALU_dec31_dec_sub26_sgn[0:0] - attribute \src "issuer_ls180.v:3720.5-3720.29" - switch \initial - attribute \src "issuer_ls180.v:3720.9-3720.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub26_sgn $0\ALU_dec31_dec_sub26_sgn[0:0] - end - attribute \src "issuer_ls180.v:3735.3-3750.6" - process $proc$issuer_ls180.v:3735$82 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_internal_op[6:0] $1\ALU_dec31_dec_sub26_internal_op[6:0] - attribute \src "issuer_ls180.v:3736.5-3736.29" - switch \initial - attribute \src "issuer_ls180.v:3736.9-3736.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0011111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0011111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0011111 - case - assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0000000 - end - sync always - update \ALU_dec31_dec_sub26_internal_op $0\ALU_dec31_dec_sub26_internal_op[6:0] - end - attribute \src "issuer_ls180.v:3751.3-3766.6" - process $proc$issuer_ls180.v:3751$83 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_in1_sel[2:0] $1\ALU_dec31_dec_sub26_in1_sel[2:0] - attribute \src "issuer_ls180.v:3752.5-3752.29" - switch \initial - attribute \src "issuer_ls180.v:3752.9-3752.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'100 - case - assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub26_in1_sel $0\ALU_dec31_dec_sub26_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:3767.3-3782.6" - process $proc$issuer_ls180.v:3767$84 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_in2_sel[3:0] $1\ALU_dec31_dec_sub26_in2_sel[3:0] - attribute \src "issuer_ls180.v:3768.5-3768.29" - switch \initial - attribute \src "issuer_ls180.v:3768.9-3768.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 - case - assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 - end - sync always - update \ALU_dec31_dec_sub26_in2_sel $0\ALU_dec31_dec_sub26_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:3783.3-3798.6" - process $proc$issuer_ls180.v:3783$85 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_cr_in[2:0] $1\ALU_dec31_dec_sub26_cr_in[2:0] - attribute \src "issuer_ls180.v:3784.5-3784.29" - switch \initial - attribute \src "issuer_ls180.v:3784.9-3784.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 - case - assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub26_cr_in $0\ALU_dec31_dec_sub26_cr_in[2:0] - end - attribute \src "issuer_ls180.v:3799.3-3814.6" - process $proc$issuer_ls180.v:3799$86 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_cr_out[2:0] $1\ALU_dec31_dec_sub26_cr_out[2:0] - attribute \src "issuer_ls180.v:3800.5-3800.29" - switch \initial - attribute \src "issuer_ls180.v:3800.9-3800.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'001 - case - assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub26_cr_out $0\ALU_dec31_dec_sub26_cr_out[2:0] - end - attribute \src "issuer_ls180.v:3815.3-3830.6" - process $proc$issuer_ls180.v:3815$87 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_ldst_len[3:0] $1\ALU_dec31_dec_sub26_ldst_len[3:0] - attribute \src "issuer_ls180.v:3816.5-3816.29" - switch \initial - attribute \src "issuer_ls180.v:3816.9-3816.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0100 - case - assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0000 - end - sync always - update \ALU_dec31_dec_sub26_ldst_len $0\ALU_dec31_dec_sub26_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:3831.3-3846.6" - process $proc$issuer_ls180.v:3831$88 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_rc_sel[1:0] $1\ALU_dec31_dec_sub26_rc_sel[1:0] - attribute \src "issuer_ls180.v:3832.5-3832.29" - switch \initial - attribute \src "issuer_ls180.v:3832.9-3832.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'10 - case - assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'00 - end - sync always - update \ALU_dec31_dec_sub26_rc_sel $0\ALU_dec31_dec_sub26_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:3847.3-3862.6" - process $proc$issuer_ls180.v:3847$89 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_cry_in[1:0] $1\ALU_dec31_dec_sub26_cry_in[1:0] - attribute \src "issuer_ls180.v:3848.5-3848.29" - switch \initial - attribute \src "issuer_ls180.v:3848.9-3848.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 - case - assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 - end - sync always - update \ALU_dec31_dec_sub26_cry_in $0\ALU_dec31_dec_sub26_cry_in[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:3868.1-4655.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub8" -attribute \generator "nMigen" -module \ALU_dec31_dec_sub8 - attribute \src "issuer_ls180.v:4439.3-4481.6" - wire width 3 $0\ALU_dec31_dec_sub8_cr_in[2:0] - attribute \src "issuer_ls180.v:4482.3-4524.6" - wire width 3 $0\ALU_dec31_dec_sub8_cr_out[2:0] - attribute \src "issuer_ls180.v:4611.3-4653.6" - wire width 2 $0\ALU_dec31_dec_sub8_cry_in[1:0] - attribute \src "issuer_ls180.v:4181.3-4223.6" - wire $0\ALU_dec31_dec_sub8_cry_out[0:0] - attribute \src "issuer_ls180.v:4052.3-4094.6" - wire width 12 $0\ALU_dec31_dec_sub8_function_unit[11:0] - attribute \src "issuer_ls180.v:4353.3-4395.6" - wire width 3 $0\ALU_dec31_dec_sub8_in1_sel[2:0] - attribute \src "issuer_ls180.v:4396.3-4438.6" - wire width 4 $0\ALU_dec31_dec_sub8_in2_sel[3:0] - attribute \src "issuer_ls180.v:4310.3-4352.6" - wire width 7 $0\ALU_dec31_dec_sub8_internal_op[6:0] - attribute \src "issuer_ls180.v:4095.3-4137.6" - wire $0\ALU_dec31_dec_sub8_inv_a[0:0] - attribute \src "issuer_ls180.v:4138.3-4180.6" - wire $0\ALU_dec31_dec_sub8_inv_out[0:0] - attribute \src "issuer_ls180.v:4224.3-4266.6" - wire $0\ALU_dec31_dec_sub8_is_32b[0:0] - attribute \src "issuer_ls180.v:4525.3-4567.6" - wire width 4 $0\ALU_dec31_dec_sub8_ldst_len[3:0] - attribute \src "issuer_ls180.v:4568.3-4610.6" - wire width 2 $0\ALU_dec31_dec_sub8_rc_sel[1:0] - attribute \src "issuer_ls180.v:4267.3-4309.6" - wire $0\ALU_dec31_dec_sub8_sgn[0:0] - attribute \src "issuer_ls180.v:3869.7-3869.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:4439.3-4481.6" - wire width 3 $1\ALU_dec31_dec_sub8_cr_in[2:0] - attribute \src "issuer_ls180.v:4482.3-4524.6" - wire width 3 $1\ALU_dec31_dec_sub8_cr_out[2:0] - attribute \src "issuer_ls180.v:4611.3-4653.6" - wire width 2 $1\ALU_dec31_dec_sub8_cry_in[1:0] - attribute \src "issuer_ls180.v:4181.3-4223.6" - wire $1\ALU_dec31_dec_sub8_cry_out[0:0] - attribute \src "issuer_ls180.v:4052.3-4094.6" - wire width 12 $1\ALU_dec31_dec_sub8_function_unit[11:0] - attribute \src "issuer_ls180.v:4353.3-4395.6" - wire width 3 $1\ALU_dec31_dec_sub8_in1_sel[2:0] - attribute \src "issuer_ls180.v:4396.3-4438.6" - wire width 4 $1\ALU_dec31_dec_sub8_in2_sel[3:0] - attribute \src "issuer_ls180.v:4310.3-4352.6" - wire width 7 $1\ALU_dec31_dec_sub8_internal_op[6:0] - attribute \src "issuer_ls180.v:4095.3-4137.6" - wire $1\ALU_dec31_dec_sub8_inv_a[0:0] - attribute \src "issuer_ls180.v:4138.3-4180.6" - wire $1\ALU_dec31_dec_sub8_inv_out[0:0] - attribute \src "issuer_ls180.v:4224.3-4266.6" - wire $1\ALU_dec31_dec_sub8_is_32b[0:0] - attribute \src "issuer_ls180.v:4525.3-4567.6" - wire width 4 $1\ALU_dec31_dec_sub8_ldst_len[3:0] - attribute \src "issuer_ls180.v:4568.3-4610.6" - wire width 2 $1\ALU_dec31_dec_sub8_rc_sel[1:0] - attribute \src "issuer_ls180.v:4267.3-4309.6" - wire $1\ALU_dec31_dec_sub8_sgn[0:0] + wire width 32 \dec31_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec58_dec58_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -5683,7 +4984,7 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \ALU_dec31_dec_sub8_cr_in + wire width 3 \dec58_dec58_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -5691,15 +4992,47 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 6 \ALU_dec31_dec_sub8_cr_out + wire width 3 \dec58_dec58_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 9 \ALU_dec31_dec_sub8_cry_in + wire width 2 \dec58_dec58_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 12 \ALU_dec31_dec_sub8_cry_out + wire \dec58_dec58_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec58_dec58_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -5714,7 +5047,7 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \ALU_dec31_dec_sub8_function_unit + wire width 12 \dec58_dec58_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -5722,7 +5055,7 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \ALU_dec31_dec_sub8_in1_sel + wire width 3 \dec58_dec58_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -5739,7 +5072,13 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 4 \ALU_dec31_dec_sub8_in2_sel + wire width 4 \dec58_dec58_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec58_dec58_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -5815,13 +5154,13 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \ALU_dec31_dec_sub8_internal_op + wire width 7 \dec58_dec58_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \ALU_dec31_dec_sub8_inv_a + wire \dec58_dec58_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 11 \ALU_dec31_dec_sub8_inv_out + wire \dec58_dec58_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 13 \ALU_dec31_dec_sub8_is_32b + wire \dec58_dec58_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -5829,1008 +5168,43 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 7 \ALU_dec31_dec_sub8_ldst_len + wire width 4 \dec58_dec58_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec58_dec58_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \ALU_dec31_dec_sub8_rc_sel + wire width 2 \dec58_dec58_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 14 \ALU_dec31_dec_sub8_sgn - attribute \src "issuer_ls180.v:3869.7-3869.15" - wire \initial + wire \dec58_dec58_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec58_dec58_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:3869.7-3869.20" - process $proc$issuer_ls180.v:3869$105 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:4052.3-4094.6" - process $proc$issuer_ls180.v:4052$91 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_function_unit[11:0] $1\ALU_dec31_dec_sub8_function_unit[11:0] - attribute \src "issuer_ls180.v:4053.5-4053.29" - switch \initial - attribute \src "issuer_ls180.v:4053.9-4053.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 - case - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000000 - end - sync always - update \ALU_dec31_dec_sub8_function_unit $0\ALU_dec31_dec_sub8_function_unit[11:0] - end - attribute \src "issuer_ls180.v:4095.3-4137.6" - process $proc$issuer_ls180.v:4095$92 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_inv_a[0:0] $1\ALU_dec31_dec_sub8_inv_a[0:0] - attribute \src "issuer_ls180.v:4096.5-4096.29" - switch \initial - attribute \src "issuer_ls180.v:4096.9-4096.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 - case - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub8_inv_a $0\ALU_dec31_dec_sub8_inv_a[0:0] - end - attribute \src "issuer_ls180.v:4138.3-4180.6" - process $proc$issuer_ls180.v:4138$93 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_inv_out[0:0] $1\ALU_dec31_dec_sub8_inv_out[0:0] - attribute \src "issuer_ls180.v:4139.5-4139.29" - switch \initial - attribute \src "issuer_ls180.v:4139.9-4139.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub8_inv_out $0\ALU_dec31_dec_sub8_inv_out[0:0] - end - attribute \src "issuer_ls180.v:4181.3-4223.6" - process $proc$issuer_ls180.v:4181$94 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_cry_out[0:0] $1\ALU_dec31_dec_sub8_cry_out[0:0] - attribute \src "issuer_ls180.v:4182.5-4182.29" - switch \initial - attribute \src "issuer_ls180.v:4182.9-4182.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 - case - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub8_cry_out $0\ALU_dec31_dec_sub8_cry_out[0:0] - end - attribute \src "issuer_ls180.v:4224.3-4266.6" - process $proc$issuer_ls180.v:4224$95 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_is_32b[0:0] $1\ALU_dec31_dec_sub8_is_32b[0:0] - attribute \src "issuer_ls180.v:4225.5-4225.29" - switch \initial - attribute \src "issuer_ls180.v:4225.9-4225.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub8_is_32b $0\ALU_dec31_dec_sub8_is_32b[0:0] - end - attribute \src "issuer_ls180.v:4267.3-4309.6" - process $proc$issuer_ls180.v:4267$96 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_sgn[0:0] $1\ALU_dec31_dec_sub8_sgn[0:0] - attribute \src "issuer_ls180.v:4268.5-4268.29" - switch \initial - attribute \src "issuer_ls180.v:4268.9-4268.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub8_sgn $0\ALU_dec31_dec_sub8_sgn[0:0] - end - attribute \src "issuer_ls180.v:4310.3-4352.6" - process $proc$issuer_ls180.v:4310$97 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_internal_op[6:0] $1\ALU_dec31_dec_sub8_internal_op[6:0] - attribute \src "issuer_ls180.v:4311.5-4311.29" - switch \initial - attribute \src "issuer_ls180.v:4311.9-4311.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 - case - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000000 - end - sync always - update \ALU_dec31_dec_sub8_internal_op $0\ALU_dec31_dec_sub8_internal_op[6:0] - end - attribute \src "issuer_ls180.v:4353.3-4395.6" - process $proc$issuer_ls180.v:4353$98 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_in1_sel[2:0] $1\ALU_dec31_dec_sub8_in1_sel[2:0] - attribute \src "issuer_ls180.v:4354.5-4354.29" - switch \initial - attribute \src "issuer_ls180.v:4354.9-4354.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 - case - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub8_in1_sel $0\ALU_dec31_dec_sub8_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:4396.3-4438.6" - process $proc$issuer_ls180.v:4396$99 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_in2_sel[3:0] $1\ALU_dec31_dec_sub8_in2_sel[3:0] - attribute \src "issuer_ls180.v:4397.5-4397.29" - switch \initial - attribute \src "issuer_ls180.v:4397.9-4397.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'1001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'1001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 - case - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 - end - sync always - update \ALU_dec31_dec_sub8_in2_sel $0\ALU_dec31_dec_sub8_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:4439.3-4481.6" - process $proc$issuer_ls180.v:4439$100 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_cr_in[2:0] $1\ALU_dec31_dec_sub8_cr_in[2:0] - attribute \src "issuer_ls180.v:4440.5-4440.29" - switch \initial - attribute \src "issuer_ls180.v:4440.9-4440.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - case - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub8_cr_in $0\ALU_dec31_dec_sub8_cr_in[2:0] - end - attribute \src "issuer_ls180.v:4482.3-4524.6" - process $proc$issuer_ls180.v:4482$101 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_cr_out[2:0] $1\ALU_dec31_dec_sub8_cr_out[2:0] - attribute \src "issuer_ls180.v:4483.5-4483.29" - switch \initial - attribute \src "issuer_ls180.v:4483.9-4483.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 - case - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub8_cr_out $0\ALU_dec31_dec_sub8_cr_out[2:0] - end - attribute \src "issuer_ls180.v:4525.3-4567.6" - process $proc$issuer_ls180.v:4525$102 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_ldst_len[3:0] $1\ALU_dec31_dec_sub8_ldst_len[3:0] - attribute \src "issuer_ls180.v:4526.5-4526.29" - switch \initial - attribute \src "issuer_ls180.v:4526.9-4526.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - case - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - end - sync always - update \ALU_dec31_dec_sub8_ldst_len $0\ALU_dec31_dec_sub8_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:4568.3-4610.6" - process $proc$issuer_ls180.v:4568$103 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_rc_sel[1:0] $1\ALU_dec31_dec_sub8_rc_sel[1:0] - attribute \src "issuer_ls180.v:4569.5-4569.29" - switch \initial - attribute \src "issuer_ls180.v:4569.9-4569.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 - case - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'00 - end - sync always - update \ALU_dec31_dec_sub8_rc_sel $0\ALU_dec31_dec_sub8_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:4611.3-4653.6" - process $proc$issuer_ls180.v:4611$104 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_cry_in[1:0] $1\ALU_dec31_dec_sub8_cry_in[1:0] - attribute \src "issuer_ls180.v:4612.5-4612.29" - switch \initial - attribute \src "issuer_ls180.v:4612.9-4612.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 - case - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'00 - end - sync always - update \ALU_dec31_dec_sub8_cry_in $0\ALU_dec31_dec_sub8_cry_in[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:4659.1-4938.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec19" -attribute \generator "nMigen" -module \BRANCH_dec19 - attribute \src "issuer_ls180.v:4857.3-4872.6" - wire width 3 $0\BRANCH_dec19_cr_in[2:0] - attribute \src "issuer_ls180.v:4873.3-4888.6" - wire width 3 $0\BRANCH_dec19_cr_out[2:0] - attribute \src "issuer_ls180.v:4809.3-4824.6" - wire width 12 $0\BRANCH_dec19_function_unit[11:0] - attribute \src "issuer_ls180.v:4841.3-4856.6" - wire width 4 $0\BRANCH_dec19_in2_sel[3:0] - attribute \src "issuer_ls180.v:4825.3-4840.6" - wire width 7 $0\BRANCH_dec19_internal_op[6:0] - attribute \src "issuer_ls180.v:4905.3-4920.6" - wire $0\BRANCH_dec19_is_32b[0:0] - attribute \src "issuer_ls180.v:4921.3-4936.6" - wire $0\BRANCH_dec19_lk[0:0] - attribute \src "issuer_ls180.v:4889.3-4904.6" - wire width 2 $0\BRANCH_dec19_rc_sel[1:0] - attribute \src "issuer_ls180.v:4660.7-4660.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:4857.3-4872.6" - wire width 3 $1\BRANCH_dec19_cr_in[2:0] - attribute \src "issuer_ls180.v:4873.3-4888.6" - wire width 3 $1\BRANCH_dec19_cr_out[2:0] - attribute \src "issuer_ls180.v:4809.3-4824.6" - wire width 12 $1\BRANCH_dec19_function_unit[11:0] - attribute \src "issuer_ls180.v:4841.3-4856.6" - wire width 4 $1\BRANCH_dec19_in2_sel[3:0] - attribute \src "issuer_ls180.v:4825.3-4840.6" - wire width 7 $1\BRANCH_dec19_internal_op[6:0] - attribute \src "issuer_ls180.v:4905.3-4920.6" - wire $1\BRANCH_dec19_is_32b[0:0] - attribute \src "issuer_ls180.v:4921.3-4936.6" - wire $1\BRANCH_dec19_lk[0:0] - attribute \src "issuer_ls180.v:4889.3-4904.6" - wire width 2 $1\BRANCH_dec19_rc_sel[1:0] + wire width 32 \dec58_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec62_dec62_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -6840,7 +5214,7 @@ module \BRANCH_dec19 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 4 \BRANCH_dec19_cr_in + wire width 3 \dec62_dec62_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -6848,7 +5222,47 @@ module \BRANCH_dec19 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \BRANCH_dec19_cr_out + wire width 3 \dec62_dec62_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec62_dec62_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec62_dec62_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -6863,7 +5277,15 @@ module \BRANCH_dec19 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \BRANCH_dec19_function_unit + wire width 12 \dec62_dec62_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec62_dec62_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -6880,7 +5302,13 @@ module \BRANCH_dec19 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 3 \BRANCH_dec19_in2_sel + wire width 4 \dec62_dec62_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec62_dec62_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -6956,326 +5384,85 @@ module \BRANCH_dec19 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \BRANCH_dec19_internal_op + wire width 7 \dec62_dec62_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 7 \BRANCH_dec19_is_32b + wire \dec62_dec62_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec62_dec62_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 8 \BRANCH_dec19_lk + wire \dec62_dec62_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec62_dec62_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 6 \BRANCH_dec19_rc_sel - attribute \src "issuer_ls180.v:4660.7-4660.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 9 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 10 \opcode_switch - attribute \src "issuer_ls180.v:4660.7-4660.20" - process $proc$issuer_ls180.v:4660$114 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:4809.3-4824.6" - process $proc$issuer_ls180.v:4809$106 - assign { } { } - assign { } { } - assign $0\BRANCH_dec19_function_unit[11:0] $1\BRANCH_dec19_function_unit[11:0] - attribute \src "issuer_ls180.v:4810.5-4810.29" - switch \initial - attribute \src "issuer_ls180.v:4810.9-4810.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\BRANCH_dec19_function_unit[11:0] 12'000000100000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\BRANCH_dec19_function_unit[11:0] 12'000000100000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\BRANCH_dec19_function_unit[11:0] 12'000000100000 - case - assign $1\BRANCH_dec19_function_unit[11:0] 12'000000000000 - end - sync always - update \BRANCH_dec19_function_unit $0\BRANCH_dec19_function_unit[11:0] - end - attribute \src "issuer_ls180.v:4825.3-4840.6" - process $proc$issuer_ls180.v:4825$107 - assign { } { } - assign { } { } - assign $0\BRANCH_dec19_internal_op[6:0] $1\BRANCH_dec19_internal_op[6:0] - attribute \src "issuer_ls180.v:4826.5-4826.29" - switch \initial - attribute \src "issuer_ls180.v:4826.9-4826.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\BRANCH_dec19_internal_op[6:0] 7'0001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\BRANCH_dec19_internal_op[6:0] 7'0001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\BRANCH_dec19_internal_op[6:0] 7'0001000 - case - assign $1\BRANCH_dec19_internal_op[6:0] 7'0000000 - end - sync always - update \BRANCH_dec19_internal_op $0\BRANCH_dec19_internal_op[6:0] - end - attribute \src "issuer_ls180.v:4841.3-4856.6" - process $proc$issuer_ls180.v:4841$108 - assign { } { } - assign { } { } - assign $0\BRANCH_dec19_in2_sel[3:0] $1\BRANCH_dec19_in2_sel[3:0] - attribute \src "issuer_ls180.v:4842.5-4842.29" - switch \initial - attribute \src "issuer_ls180.v:4842.9-4842.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\BRANCH_dec19_in2_sel[3:0] 4'1100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\BRANCH_dec19_in2_sel[3:0] 4'1100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\BRANCH_dec19_in2_sel[3:0] 4'1100 - case - assign $1\BRANCH_dec19_in2_sel[3:0] 4'0000 - end - sync always - update \BRANCH_dec19_in2_sel $0\BRANCH_dec19_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:4857.3-4872.6" - process $proc$issuer_ls180.v:4857$109 - assign { } { } - assign { } { } - assign $0\BRANCH_dec19_cr_in[2:0] $1\BRANCH_dec19_cr_in[2:0] - attribute \src "issuer_ls180.v:4858.5-4858.29" - switch \initial - attribute \src "issuer_ls180.v:4858.9-4858.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\BRANCH_dec19_cr_in[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\BRANCH_dec19_cr_in[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\BRANCH_dec19_cr_in[2:0] 3'010 - case - assign $1\BRANCH_dec19_cr_in[2:0] 3'000 - end - sync always - update \BRANCH_dec19_cr_in $0\BRANCH_dec19_cr_in[2:0] - end - attribute \src "issuer_ls180.v:4873.3-4888.6" - process $proc$issuer_ls180.v:4873$110 - assign { } { } - assign { } { } - assign $0\BRANCH_dec19_cr_out[2:0] $1\BRANCH_dec19_cr_out[2:0] - attribute \src "issuer_ls180.v:4874.5-4874.29" - switch \initial - attribute \src "issuer_ls180.v:4874.9-4874.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\BRANCH_dec19_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\BRANCH_dec19_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\BRANCH_dec19_cr_out[2:0] 3'000 - case - assign $1\BRANCH_dec19_cr_out[2:0] 3'000 - end - sync always - update \BRANCH_dec19_cr_out $0\BRANCH_dec19_cr_out[2:0] - end - attribute \src "issuer_ls180.v:4889.3-4904.6" - process $proc$issuer_ls180.v:4889$111 - assign { } { } - assign { } { } - assign $0\BRANCH_dec19_rc_sel[1:0] $1\BRANCH_dec19_rc_sel[1:0] - attribute \src "issuer_ls180.v:4890.5-4890.29" - switch \initial - attribute \src "issuer_ls180.v:4890.9-4890.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 - case - assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 - end - sync always - update \BRANCH_dec19_rc_sel $0\BRANCH_dec19_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:4905.3-4920.6" - process $proc$issuer_ls180.v:4905$112 - assign { } { } - assign { } { } - assign $0\BRANCH_dec19_is_32b[0:0] $1\BRANCH_dec19_is_32b[0:0] - attribute \src "issuer_ls180.v:4906.5-4906.29" - switch \initial - attribute \src "issuer_ls180.v:4906.9-4906.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\BRANCH_dec19_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\BRANCH_dec19_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\BRANCH_dec19_is_32b[0:0] 1'0 - case - assign $1\BRANCH_dec19_is_32b[0:0] 1'0 - end - sync always - update \BRANCH_dec19_is_32b $0\BRANCH_dec19_is_32b[0:0] - end - attribute \src "issuer_ls180.v:4921.3-4936.6" - process $proc$issuer_ls180.v:4921$113 - assign { } { } - assign { } { } - assign $0\BRANCH_dec19_lk[0:0] $1\BRANCH_dec19_lk[0:0] - attribute \src "issuer_ls180.v:4922.5-4922.29" - switch \initial - attribute \src "issuer_ls180.v:4922.9-4922.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\BRANCH_dec19_lk[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\BRANCH_dec19_lk[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\BRANCH_dec19_lk[0:0] 1'1 - case - assign $1\BRANCH_dec19_lk[0:0] 1'0 - end - sync always - update \BRANCH_dec19_lk $0\BRANCH_dec19_lk[0:0] - end - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "issuer_ls180.v:4942.1-5239.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec19" -attribute \generator "nMigen" -module \CR_dec19 - attribute \src "issuer_ls180.v:5136.3-5169.6" - wire width 3 $0\CR_dec19_cr_in[2:0] - attribute \src "issuer_ls180.v:5170.3-5203.6" - wire width 3 $0\CR_dec19_cr_out[2:0] - attribute \src "issuer_ls180.v:5068.3-5101.6" - wire width 12 $0\CR_dec19_function_unit[11:0] - attribute \src "issuer_ls180.v:5102.3-5135.6" - wire width 7 $0\CR_dec19_internal_op[6:0] - attribute \src "issuer_ls180.v:5204.3-5237.6" - wire width 2 $0\CR_dec19_rc_sel[1:0] - attribute \src "issuer_ls180.v:4943.7-4943.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:5136.3-5169.6" - wire width 3 $1\CR_dec19_cr_in[2:0] - attribute \src "issuer_ls180.v:5170.3-5203.6" - wire width 3 $1\CR_dec19_cr_out[2:0] - attribute \src "issuer_ls180.v:5068.3-5101.6" - wire width 12 $1\CR_dec19_function_unit[11:0] - attribute \src "issuer_ls180.v:5102.3-5135.6" - wire width 7 $1\CR_dec19_internal_op[6:0] - attribute \src "issuer_ls180.v:5204.3-5237.6" - wire width 2 $1\CR_dec19_rc_sel[1:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" + wire width 2 \dec62_dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \CR_dec19_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" + wire width 2 \dec62_dec62_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec62_opcode_in + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 4 \CR_dec19_cr_out + wire width 5 \form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -7290,15 +5477,48 @@ module \CR_dec19 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \CR_dec19_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" + wire width 12 output 7 \function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 12 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 13 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \in3_sel + attribute \src "libresoc.v:1203.7-1203.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" @@ -7366,6079 +5586,5485 @@ module \CR_dec19 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \CR_dec19_internal_op + wire width 7 output 6 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 9 \is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 32 \opcode_switch$1 + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 15 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 1 \raw_opcode_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 5 \CR_dec19_rc_sel - attribute \src "issuer_ls180.v:4943.7-4943.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 10 \opcode_switch - attribute \src "issuer_ls180.v:4943.7-4943.20" - process $proc$issuer_ls180.v:4943$120 + wire width 2 output 3 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \sh + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 17 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + cell $mux $ternary$libresoc.v:3260$243 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:3260$243_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:3261.9-3287.4" + cell \dec19 \dec19 + connect \dec19_asmcode \dec19_dec19_asmcode + connect \dec19_br \dec19_dec19_br + connect \dec19_cr_in \dec19_dec19_cr_in + connect \dec19_cr_out \dec19_dec19_cr_out + connect \dec19_cry_in \dec19_dec19_cry_in + connect \dec19_cry_out \dec19_dec19_cry_out + connect \dec19_form \dec19_dec19_form + connect \dec19_function_unit \dec19_dec19_function_unit + connect \dec19_in1_sel \dec19_dec19_in1_sel + connect \dec19_in2_sel \dec19_dec19_in2_sel + connect \dec19_in3_sel \dec19_dec19_in3_sel + connect \dec19_internal_op \dec19_dec19_internal_op + connect \dec19_inv_a \dec19_dec19_inv_a + connect \dec19_inv_out \dec19_dec19_inv_out + connect \dec19_is_32b \dec19_dec19_is_32b + connect \dec19_ldst_len \dec19_dec19_ldst_len + connect \dec19_lk \dec19_dec19_lk + connect \dec19_out_sel \dec19_dec19_out_sel + connect \dec19_rc_sel \dec19_dec19_rc_sel + connect \dec19_rsrv \dec19_dec19_rsrv + connect \dec19_sgl_pipe \dec19_dec19_sgl_pipe + connect \dec19_sgn \dec19_dec19_sgn + connect \dec19_sgn_ext \dec19_dec19_sgn_ext + connect \dec19_upd \dec19_dec19_upd + connect \opcode_in \dec19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:3288.9-3314.4" + cell \dec30 \dec30 + connect \dec30_asmcode \dec30_dec30_asmcode + connect \dec30_br \dec30_dec30_br + connect \dec30_cr_in \dec30_dec30_cr_in + connect \dec30_cr_out \dec30_dec30_cr_out + connect \dec30_cry_in \dec30_dec30_cry_in + connect \dec30_cry_out \dec30_dec30_cry_out + connect \dec30_form \dec30_dec30_form + connect \dec30_function_unit \dec30_dec30_function_unit + connect \dec30_in1_sel \dec30_dec30_in1_sel + connect \dec30_in2_sel \dec30_dec30_in2_sel + connect \dec30_in3_sel \dec30_dec30_in3_sel + connect \dec30_internal_op \dec30_dec30_internal_op + connect \dec30_inv_a \dec30_dec30_inv_a + connect \dec30_inv_out \dec30_dec30_inv_out + connect \dec30_is_32b \dec30_dec30_is_32b + connect \dec30_ldst_len \dec30_dec30_ldst_len + connect \dec30_lk \dec30_dec30_lk + connect \dec30_out_sel \dec30_dec30_out_sel + connect \dec30_rc_sel \dec30_dec30_rc_sel + connect \dec30_rsrv \dec30_dec30_rsrv + connect \dec30_sgl_pipe \dec30_dec30_sgl_pipe + connect \dec30_sgn \dec30_dec30_sgn + connect \dec30_sgn_ext \dec30_dec30_sgn_ext + connect \dec30_upd \dec30_dec30_upd + connect \opcode_in \dec30_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:3315.9-3341.4" + cell \dec31 \dec31 + connect \dec31_asmcode \dec31_dec31_asmcode + connect \dec31_br \dec31_dec31_br + connect \dec31_cr_in \dec31_dec31_cr_in + connect \dec31_cr_out \dec31_dec31_cr_out + connect \dec31_cry_in \dec31_dec31_cry_in + connect \dec31_cry_out \dec31_dec31_cry_out + connect \dec31_form \dec31_dec31_form + connect \dec31_function_unit \dec31_dec31_function_unit + connect \dec31_in1_sel \dec31_dec31_in1_sel + connect \dec31_in2_sel \dec31_dec31_in2_sel + connect \dec31_in3_sel \dec31_dec31_in3_sel + connect \dec31_internal_op \dec31_dec31_internal_op + connect \dec31_inv_a \dec31_dec31_inv_a + connect \dec31_inv_out \dec31_dec31_inv_out + connect \dec31_is_32b \dec31_dec31_is_32b + connect \dec31_ldst_len \dec31_dec31_ldst_len + connect \dec31_lk \dec31_dec31_lk + connect \dec31_out_sel \dec31_dec31_out_sel + connect \dec31_rc_sel \dec31_dec31_rc_sel + connect \dec31_rsrv \dec31_dec31_rsrv + connect \dec31_sgl_pipe \dec31_dec31_sgl_pipe + connect \dec31_sgn \dec31_dec31_sgn + connect \dec31_sgn_ext \dec31_dec31_sgn_ext + connect \dec31_upd \dec31_dec31_upd + connect \opcode_in \dec31_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:3342.9-3368.4" + cell \dec58 \dec58 + connect \dec58_asmcode \dec58_dec58_asmcode + connect \dec58_br \dec58_dec58_br + connect \dec58_cr_in \dec58_dec58_cr_in + connect \dec58_cr_out \dec58_dec58_cr_out + connect \dec58_cry_in \dec58_dec58_cry_in + connect \dec58_cry_out \dec58_dec58_cry_out + connect \dec58_form \dec58_dec58_form + connect \dec58_function_unit \dec58_dec58_function_unit + connect \dec58_in1_sel \dec58_dec58_in1_sel + connect \dec58_in2_sel \dec58_dec58_in2_sel + connect \dec58_in3_sel \dec58_dec58_in3_sel + connect \dec58_internal_op \dec58_dec58_internal_op + connect \dec58_inv_a \dec58_dec58_inv_a + connect \dec58_inv_out \dec58_dec58_inv_out + connect \dec58_is_32b \dec58_dec58_is_32b + connect \dec58_ldst_len \dec58_dec58_ldst_len + connect \dec58_lk \dec58_dec58_lk + connect \dec58_out_sel \dec58_dec58_out_sel + connect \dec58_rc_sel \dec58_dec58_rc_sel + connect \dec58_rsrv \dec58_dec58_rsrv + connect \dec58_sgl_pipe \dec58_dec58_sgl_pipe + connect \dec58_sgn \dec58_dec58_sgn + connect \dec58_sgn_ext \dec58_dec58_sgn_ext + connect \dec58_upd \dec58_dec58_upd + connect \opcode_in \dec58_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:3369.9-3395.4" + cell \dec62 \dec62 + connect \dec62_asmcode \dec62_dec62_asmcode + connect \dec62_br \dec62_dec62_br + connect \dec62_cr_in \dec62_dec62_cr_in + connect \dec62_cr_out \dec62_dec62_cr_out + connect \dec62_cry_in \dec62_dec62_cry_in + connect \dec62_cry_out \dec62_dec62_cry_out + connect \dec62_form \dec62_dec62_form + connect \dec62_function_unit \dec62_dec62_function_unit + connect \dec62_in1_sel \dec62_dec62_in1_sel + connect \dec62_in2_sel \dec62_dec62_in2_sel + connect \dec62_in3_sel \dec62_dec62_in3_sel + connect \dec62_internal_op \dec62_dec62_internal_op + connect \dec62_inv_a \dec62_dec62_inv_a + connect \dec62_inv_out \dec62_dec62_inv_out + connect \dec62_is_32b \dec62_dec62_is_32b + connect \dec62_ldst_len \dec62_dec62_ldst_len + connect \dec62_lk \dec62_dec62_lk + connect \dec62_out_sel \dec62_dec62_out_sel + connect \dec62_rc_sel \dec62_dec62_rc_sel + connect \dec62_rsrv \dec62_dec62_rsrv + connect \dec62_sgl_pipe \dec62_dec62_sgl_pipe + connect \dec62_sgn \dec62_dec62_sgn + connect \dec62_sgn_ext \dec62_dec62_sgn_ext + connect \dec62_upd \dec62_dec62_upd + connect \opcode_in \dec62_opcode_in + end + attribute \src "libresoc.v:1203.7-1203.20" + process $proc$libresoc.v:1203$268 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "issuer_ls180.v:5068.3-5101.6" - process $proc$issuer_ls180.v:5068$115 + attribute \src "libresoc.v:3396.3-3534.6" + process $proc$libresoc.v:3396$244 assign { } { } assign { } { } - assign $0\CR_dec19_function_unit[11:0] $1\CR_dec19_function_unit[11:0] - attribute \src "issuer_ls180.v:5069.5-5069.29" + assign { } { } + assign $0\asmcode[7:0] $2\asmcode[7:0] + attribute \src "libresoc.v:3397.5-3397.29" switch \initial - attribute \src "issuer_ls180.v:5069.9-5069.17" + attribute \src "libresoc.v:3397.9-3397.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 + assign $1\asmcode[7:0] \dec19_dec19_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 + assign $1\asmcode[7:0] \dec30_dec30_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 + assign $1\asmcode[7:0] \dec31_dec31_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 + assign $1\asmcode[7:0] \dec58_dec58_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 + assign $1\asmcode[7:0] \dec62_dec62_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 + assign $1\asmcode[7:0] 8'00000111 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 + assign $1\asmcode[7:0] 8'00001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 + assign $1\asmcode[7:0] 8'00000110 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\asmcode[7:0] 8'00001001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\asmcode[7:0] 8'00010001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\asmcode[7:0] 8'00010010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\asmcode[7:0] 8'00010100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\asmcode[7:0] 8'00010101 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\asmcode[7:0] 8'00011101 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\asmcode[7:0] 8'00011111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\asmcode[7:0] 8'01001110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\asmcode[7:0] 8'01001111 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\asmcode[7:0] 8'01011000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\asmcode[7:0] 8'01011010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\asmcode[7:0] 8'01011110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\asmcode[7:0] 8'01011111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\asmcode[7:0] 8'01100111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\asmcode[7:0] 8'01101001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\asmcode[7:0] 8'10000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\asmcode[7:0] 8'10001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\asmcode[7:0] 8'10001011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\asmcode[7:0] 8'10011000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\asmcode[7:0] 8'10011001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\asmcode[7:0] 8'10011010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\asmcode[7:0] 8'10100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\asmcode[7:0] 8'10101001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\asmcode[7:0] 8'10110010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\asmcode[7:0] 8'10110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\asmcode[7:0] 8'10111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\asmcode[7:0] 8'10111011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\asmcode[7:0] 8'11000011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + assign $1\asmcode[7:0] 8'11001011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\asmcode[7:0] 8'11001111 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\asmcode[7:0] 8'11010001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\asmcode[7:0] 8'11010010 + case + assign $1\asmcode[7:0] 8'00000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\asmcode[7:0] 8'00010011 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\asmcode[7:0] 8'10000110 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\asmcode[7:0] 8'10011100 case - assign $1\CR_dec19_function_unit[11:0] 12'000000000000 + assign $2\asmcode[7:0] $1\asmcode[7:0] end sync always - update \CR_dec19_function_unit $0\CR_dec19_function_unit[11:0] + update \asmcode $0\asmcode[7:0] end - attribute \src "issuer_ls180.v:5102.3-5135.6" - process $proc$issuer_ls180.v:5102$116 + attribute \src "libresoc.v:3535.3-3676.6" + process $proc$libresoc.v:3535$245 assign { } { } assign { } { } - assign $0\CR_dec19_internal_op[6:0] $1\CR_dec19_internal_op[6:0] - attribute \src "issuer_ls180.v:5103.5-5103.29" + assign { } { } + assign $0\in1_sel[2:0] $2\in1_sel[2:0] + attribute \src "libresoc.v:3536.5-3536.29" switch \initial - attribute \src "issuer_ls180.v:5103.9-5103.17" + attribute \src "libresoc.v:3536.9-3536.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 assign { } { } - assign $1\CR_dec19_internal_op[6:0] 7'0101010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 + assign $1\in1_sel[2:0] \dec19_dec19_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } - assign $1\CR_dec19_internal_op[6:0] 7'1000101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 + assign $1\in1_sel[2:0] \dec30_dec30_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 assign { } { } - assign $1\CR_dec19_internal_op[6:0] 7'1000101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 + assign $1\in1_sel[2:0] \dec31_dec31_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } - assign $1\CR_dec19_internal_op[6:0] 7'1000101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 + assign $1\in1_sel[2:0] \dec58_dec58_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 assign { } { } - assign $1\CR_dec19_internal_op[6:0] 7'1000101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 + assign $1\in1_sel[2:0] \dec62_dec62_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 assign { } { } - assign $1\CR_dec19_internal_op[6:0] 7'1000101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } - assign $1\CR_dec19_internal_op[6:0] 7'1000101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } - assign $1\CR_dec19_internal_op[6:0] 7'1000101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + case + assign $1\in1_sel[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- assign { } { } - assign $1\CR_dec19_internal_op[6:0] 7'1000101 + assign $2\in1_sel[2:0] 3'000 case - assign $1\CR_dec19_internal_op[6:0] 7'0000000 + assign $2\in1_sel[2:0] $1\in1_sel[2:0] end sync always - update \CR_dec19_internal_op $0\CR_dec19_internal_op[6:0] + update \in1_sel $0\in1_sel[2:0] end - attribute \src "issuer_ls180.v:5136.3-5169.6" - process $proc$issuer_ls180.v:5136$117 + attribute \src "libresoc.v:3677.3-3818.6" + process $proc$libresoc.v:3677$246 + assign { } { } assign { } { } assign { } { } - assign $0\CR_dec19_cr_in[2:0] $1\CR_dec19_cr_in[2:0] - attribute \src "issuer_ls180.v:5137.5-5137.29" + assign $0\in2_sel[3:0] $2\in2_sel[3:0] + attribute \src "libresoc.v:3678.5-3678.29" switch \initial - attribute \src "issuer_ls180.v:5137.9-5137.17" + attribute \src "libresoc.v:3678.9-3678.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 assign { } { } - assign $1\CR_dec19_cr_in[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 + assign $1\in2_sel[3:0] \dec19_dec19_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } - assign $1\CR_dec19_cr_in[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 + assign $1\in2_sel[3:0] \dec30_dec30_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 assign { } { } - assign $1\CR_dec19_cr_in[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 + assign $1\in2_sel[3:0] \dec31_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } - assign $1\CR_dec19_cr_in[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 + assign $1\in2_sel[3:0] \dec58_dec58_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 assign { } { } - assign $1\CR_dec19_cr_in[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 + assign $1\in2_sel[3:0] \dec62_dec62_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 assign { } { } - assign $1\CR_dec19_cr_in[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } - assign $1\CR_dec19_cr_in[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } - assign $1\CR_dec19_cr_in[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in2_sel[3:0] 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in2_sel[3:0] 4'0110 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in2_sel[3:0] 4'0111 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 assign { } { } - assign $1\CR_dec19_cr_in[2:0] 3'100 + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + case + assign $1\in2_sel[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in2_sel[3:0] 4'0000 case - assign $1\CR_dec19_cr_in[2:0] 3'000 + assign $2\in2_sel[3:0] $1\in2_sel[3:0] end sync always - update \CR_dec19_cr_in $0\CR_dec19_cr_in[2:0] + update \in2_sel $0\in2_sel[3:0] end - attribute \src "issuer_ls180.v:5170.3-5203.6" - process $proc$issuer_ls180.v:5170$118 + attribute \src "libresoc.v:3819.3-3960.6" + process $proc$libresoc.v:3819$247 assign { } { } assign { } { } - assign $0\CR_dec19_cr_out[2:0] $1\CR_dec19_cr_out[2:0] - attribute \src "issuer_ls180.v:5171.5-5171.29" + assign { } { } + assign $0\in3_sel[1:0] $2\in3_sel[1:0] + attribute \src "libresoc.v:3820.5-3820.29" switch \initial - attribute \src "issuer_ls180.v:5171.9-5171.17" + attribute \src "libresoc.v:3820.9-3820.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 assign { } { } - assign $1\CR_dec19_cr_out[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 + assign $1\in3_sel[1:0] \dec19_dec19_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } - assign $1\CR_dec19_cr_out[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 + assign $1\in3_sel[1:0] \dec30_dec30_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 assign { } { } - assign $1\CR_dec19_cr_out[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 + assign $1\in3_sel[1:0] \dec31_dec31_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } - assign $1\CR_dec19_cr_out[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 + assign $1\in3_sel[1:0] \dec58_dec58_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 assign { } { } - assign $1\CR_dec19_cr_out[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 + assign $1\in3_sel[1:0] \dec62_dec62_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 assign { } { } - assign $1\CR_dec19_cr_out[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } - assign $1\CR_dec19_cr_out[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } - assign $1\CR_dec19_cr_out[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 assign { } { } - assign $1\CR_dec19_cr_out[2:0] 3'011 + assign $1\in3_sel[1:0] 2'00 + case + assign $1\in3_sel[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in3_sel[1:0] 2'00 case - assign $1\CR_dec19_cr_out[2:0] 3'000 + assign $2\in3_sel[1:0] $1\in3_sel[1:0] end sync always - update \CR_dec19_cr_out $0\CR_dec19_cr_out[2:0] + update \in3_sel $0\in3_sel[1:0] end - attribute \src "issuer_ls180.v:5204.3-5237.6" - process $proc$issuer_ls180.v:5204$119 + attribute \src "libresoc.v:3961.3-4102.6" + process $proc$libresoc.v:3961$248 + assign { } { } assign { } { } assign { } { } - assign $0\CR_dec19_rc_sel[1:0] $1\CR_dec19_rc_sel[1:0] - attribute \src "issuer_ls180.v:5205.5-5205.29" + assign $0\out_sel[1:0] $2\out_sel[1:0] + attribute \src "libresoc.v:3962.5-3962.29" switch \initial - attribute \src "issuer_ls180.v:5205.9-5205.17" + attribute \src "libresoc.v:3962.9-3962.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 assign { } { } - assign $1\CR_dec19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 + assign $1\out_sel[1:0] \dec19_dec19_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } - assign $1\CR_dec19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 + assign $1\out_sel[1:0] \dec30_dec30_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 assign { } { } - assign $1\CR_dec19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 + assign $1\out_sel[1:0] \dec31_dec31_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } - assign $1\CR_dec19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 + assign $1\out_sel[1:0] \dec58_dec58_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 assign { } { } - assign $1\CR_dec19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 + assign $1\out_sel[1:0] \dec62_dec62_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 assign { } { } - assign $1\CR_dec19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } - assign $1\CR_dec19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } - assign $1\CR_dec19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\out_sel[1:0] 2'10 + case + assign $1\out_sel[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 assign { } { } - assign $1\CR_dec19_rc_sel[1:0] 2'00 + assign $2\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\out_sel[1:0] 2'01 case - assign $1\CR_dec19_rc_sel[1:0] 2'00 + assign $2\out_sel[1:0] $1\out_sel[1:0] end sync always - update \CR_dec19_rc_sel $0\CR_dec19_rc_sel[1:0] + update \out_sel $0\out_sel[1:0] end - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "issuer_ls180.v:5243.1-5972.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31" -attribute \generator "nMigen" -module \CR_dec31 - attribute \src "issuer_ls180.v:5928.3-5946.6" - wire width 3 $0\CR_dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:5947.3-5965.6" - wire width 3 $0\CR_dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:5890.3-5908.6" - wire width 12 $0\CR_dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:5909.3-5927.6" - wire width 7 $0\CR_dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:5871.3-5889.6" - wire width 2 $0\CR_dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:5244.7-5244.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:5928.3-5946.6" - wire width 3 $1\CR_dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:5947.3-5965.6" - wire width 3 $1\CR_dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:5890.3-5908.6" - wire width 12 $1\CR_dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:5909.3-5927.6" - wire width 7 $1\CR_dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:5871.3-5889.6" - wire width 2 $1\CR_dec31_rc_sel[1:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \CR_dec31_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 4 \CR_dec31_cr_out - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \CR_dec31_dec_sub0_opcode_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \CR_dec31_dec_sub15_opcode_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute 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attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \CR_dec31_dec_sub16_opcode_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 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\enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \CR_dec31_dec_sub19_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \CR_dec31_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \CR_dec31_internal_op - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 5 \CR_dec31_rc_sel - attribute \src "issuer_ls180.v:5244.7-5244.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" - wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 10 \opcode_switch - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:5839.21-5846.4" - cell \CR_dec31_dec_sub0 \CR_dec31_dec_sub0 - connect \CR_dec31_dec_sub0_cr_in \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in - connect \CR_dec31_dec_sub0_cr_out \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out - connect \CR_dec31_dec_sub0_function_unit \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit - connect \CR_dec31_dec_sub0_internal_op \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op - connect \CR_dec31_dec_sub0_rc_sel \CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel - connect \opcode_in \CR_dec31_dec_sub0_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:5847.22-5854.4" - cell \CR_dec31_dec_sub15 \CR_dec31_dec_sub15 - connect \CR_dec31_dec_sub15_cr_in \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in - connect \CR_dec31_dec_sub15_cr_out \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out - connect \CR_dec31_dec_sub15_function_unit \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit - connect \CR_dec31_dec_sub15_internal_op \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op - connect \CR_dec31_dec_sub15_rc_sel \CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel - connect \opcode_in \CR_dec31_dec_sub15_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:5855.22-5862.4" - cell \CR_dec31_dec_sub16 \CR_dec31_dec_sub16 - connect \CR_dec31_dec_sub16_cr_in \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in - connect \CR_dec31_dec_sub16_cr_out \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out - connect \CR_dec31_dec_sub16_function_unit \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit - connect \CR_dec31_dec_sub16_internal_op \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op - connect \CR_dec31_dec_sub16_rc_sel \CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel - connect \opcode_in \CR_dec31_dec_sub16_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:5863.22-5870.4" - cell \CR_dec31_dec_sub19 \CR_dec31_dec_sub19 - connect \CR_dec31_dec_sub19_cr_in \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in - connect \CR_dec31_dec_sub19_cr_out \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out - connect \CR_dec31_dec_sub19_function_unit \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit - connect \CR_dec31_dec_sub19_internal_op \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op - connect \CR_dec31_dec_sub19_rc_sel \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel - connect \opcode_in \CR_dec31_dec_sub19_opcode_in - end - attribute \src "issuer_ls180.v:5244.7-5244.20" - process $proc$issuer_ls180.v:5244$126 + attribute \src "libresoc.v:4103.3-4244.6" + process $proc$libresoc.v:4103$249 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:5871.3-5889.6" - process $proc$issuer_ls180.v:5871$121 assign { } { } assign { } { } - assign $0\CR_dec31_rc_sel[1:0] $1\CR_dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:5872.5-5872.29" + assign $0\cr_in[2:0] $2\cr_in[2:0] + attribute \src "libresoc.v:4104.5-4104.29" switch \initial - attribute \src "issuer_ls180.v:5872.9-5872.17" + attribute \src "libresoc.v:4104.9-4104.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 assign { } { } - assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 + assign $1\cr_in[2:0] \dec19_dec19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } - assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\cr_in[2:0] \dec30_dec30_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 assign { } { } - assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 + assign $1\cr_in[2:0] \dec31_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } - assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel - case - assign $1\CR_dec31_rc_sel[1:0] 2'00 - end - sync always - update \CR_dec31_rc_sel $0\CR_dec31_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:5890.3-5908.6" - process $proc$issuer_ls180.v:5890$122 - assign { } { } - assign { } { } - assign $0\CR_dec31_function_unit[11:0] $1\CR_dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:5891.5-5891.29" - switch \initial - attribute \src "issuer_ls180.v:5891.9-5891.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\cr_in[2:0] \dec58_dec58_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 assign { } { } - assign $1\CR_dec31_function_unit[11:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 + assign $1\cr_in[2:0] \dec62_dec62_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 assign { } { } - assign $1\CR_dec31_function_unit[11:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } - assign $1\CR_dec31_function_unit[11:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } - assign $1\CR_dec31_function_unit[11:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit - case - assign $1\CR_dec31_function_unit[11:0] 12'000000000000 - end - sync always - update \CR_dec31_function_unit $0\CR_dec31_function_unit[11:0] - end - attribute \src "issuer_ls180.v:5909.3-5927.6" - process $proc$issuer_ls180.v:5909$123 - assign { } { } - assign { } { } - assign $0\CR_dec31_internal_op[6:0] $1\CR_dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:5910.5-5910.29" - switch \initial - attribute \src "issuer_ls180.v:5910.9-5910.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 assign { } { } - assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 assign { } { } - assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 assign { } { } - assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 assign { } { } - assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op - case - assign $1\CR_dec31_internal_op[6:0] 7'0000000 - end - sync always - update \CR_dec31_internal_op $0\CR_dec31_internal_op[6:0] - end - attribute \src "issuer_ls180.v:5928.3-5946.6" - process $proc$issuer_ls180.v:5928$124 - assign { } { } - assign { } { } - assign $0\CR_dec31_cr_in[2:0] $1\CR_dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:5929.5-5929.29" - switch \initial - attribute \src "issuer_ls180.v:5929.9-5929.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 assign { } { } - assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 assign { } { } - assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 assign { } { } - assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 assign { } { } - assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in - case - assign $1\CR_dec31_cr_in[2:0] 3'000 - end - sync always - update \CR_dec31_cr_in $0\CR_dec31_cr_in[2:0] - end - attribute \src "issuer_ls180.v:5947.3-5965.6" - process $proc$issuer_ls180.v:5947$125 - assign { } { } - assign { } { } - assign $0\CR_dec31_cr_out[2:0] $1\CR_dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:5948.5-5948.29" - switch \initial - attribute \src "issuer_ls180.v:5948.9-5948.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 assign { } { } - assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 assign { } { } - assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 assign { } { } - assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 assign { } { } - assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out - case - assign $1\CR_dec31_cr_out[2:0] 3'000 - end - sync always - update \CR_dec31_cr_out $0\CR_dec31_cr_out[2:0] - end - connect \CR_dec31_dec_sub16_opcode_in \opcode_in - connect \CR_dec31_dec_sub15_opcode_in \opcode_in - connect \CR_dec31_dec_sub19_opcode_in \opcode_in - connect \CR_dec31_dec_sub0_opcode_in \opcode_in - connect \opc_in \opcode_switch [4:0] - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "issuer_ls180.v:5976.1-6153.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub0" -attribute \generator "nMigen" -module \CR_dec31_dec_sub0 - attribute \src "issuer_ls180.v:6122.3-6131.6" - wire width 3 $0\CR_dec31_dec_sub0_cr_in[2:0] - attribute \src "issuer_ls180.v:6132.3-6141.6" - wire width 3 $0\CR_dec31_dec_sub0_cr_out[2:0] - attribute \src "issuer_ls180.v:6102.3-6111.6" - wire width 12 $0\CR_dec31_dec_sub0_function_unit[11:0] - attribute \src "issuer_ls180.v:6112.3-6121.6" - wire width 7 $0\CR_dec31_dec_sub0_internal_op[6:0] - attribute \src "issuer_ls180.v:6142.3-6151.6" - wire width 2 $0\CR_dec31_dec_sub0_rc_sel[1:0] - attribute \src "issuer_ls180.v:5977.7-5977.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:6122.3-6131.6" - wire width 3 $1\CR_dec31_dec_sub0_cr_in[2:0] - attribute \src "issuer_ls180.v:6132.3-6141.6" - wire width 3 $1\CR_dec31_dec_sub0_cr_out[2:0] - attribute \src "issuer_ls180.v:6102.3-6111.6" - wire width 12 $1\CR_dec31_dec_sub0_function_unit[11:0] - attribute \src "issuer_ls180.v:6112.3-6121.6" - wire width 7 $1\CR_dec31_dec_sub0_internal_op[6:0] - attribute \src "issuer_ls180.v:6142.3-6151.6" - wire width 2 $1\CR_dec31_dec_sub0_rc_sel[1:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \CR_dec31_dec_sub0_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 4 \CR_dec31_dec_sub0_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \CR_dec31_dec_sub0_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \CR_dec31_dec_sub0_internal_op - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 5 \CR_dec31_dec_sub0_rc_sel - attribute \src "issuer_ls180.v:5977.7-5977.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:5977.7-5977.20" - process $proc$issuer_ls180.v:5977$132 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:6102.3-6111.6" - process $proc$issuer_ls180.v:6102$127 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub0_function_unit[11:0] $1\CR_dec31_dec_sub0_function_unit[11:0] - attribute \src "issuer_ls180.v:6103.5-6103.29" - switch \initial - attribute \src "issuer_ls180.v:6103.9-6103.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 assign { } { } - assign $1\CR_dec31_dec_sub0_function_unit[11:0] 12'000001000000 - case - assign $1\CR_dec31_dec_sub0_function_unit[11:0] 12'000000000000 - end - sync always - update \CR_dec31_dec_sub0_function_unit $0\CR_dec31_dec_sub0_function_unit[11:0] - end - attribute \src "issuer_ls180.v:6112.3-6121.6" - process $proc$issuer_ls180.v:6112$128 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub0_internal_op[6:0] $1\CR_dec31_dec_sub0_internal_op[6:0] - attribute \src "issuer_ls180.v:6113.5-6113.29" - switch \initial - attribute \src "issuer_ls180.v:6113.9-6113.17" - case 1'1 + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cr_in[2:0] 3'000 case + assign $1\cr_in[2:0] 3'000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- assign { } { } - assign $1\CR_dec31_dec_sub0_internal_op[6:0] 7'0111011 + assign $2\cr_in[2:0] 3'000 case - assign $1\CR_dec31_dec_sub0_internal_op[6:0] 7'0000000 + assign $2\cr_in[2:0] $1\cr_in[2:0] end sync always - update \CR_dec31_dec_sub0_internal_op $0\CR_dec31_dec_sub0_internal_op[6:0] + update \cr_in $0\cr_in[2:0] end - attribute \src "issuer_ls180.v:6122.3-6131.6" - process $proc$issuer_ls180.v:6122$129 + attribute \src "libresoc.v:4245.3-4386.6" + process $proc$libresoc.v:4245$250 + assign { } { } assign { } { } assign { } { } - assign $0\CR_dec31_dec_sub0_cr_in[2:0] $1\CR_dec31_dec_sub0_cr_in[2:0] - attribute \src "issuer_ls180.v:6123.5-6123.29" + assign $0\cr_out[2:0] $2\cr_out[2:0] + attribute \src "libresoc.v:4246.5-4246.29" switch \initial - attribute \src "issuer_ls180.v:6123.9-6123.17" + attribute \src "libresoc.v:4246.9-4246.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 assign { } { } - assign $1\CR_dec31_dec_sub0_cr_in[2:0] 3'011 - case - assign $1\CR_dec31_dec_sub0_cr_in[2:0] 3'000 - end - sync always - update \CR_dec31_dec_sub0_cr_in $0\CR_dec31_dec_sub0_cr_in[2:0] - end - attribute \src "issuer_ls180.v:6132.3-6141.6" - process $proc$issuer_ls180.v:6132$130 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub0_cr_out[2:0] $1\CR_dec31_dec_sub0_cr_out[2:0] - attribute \src "issuer_ls180.v:6133.5-6133.29" - switch \initial - attribute \src "issuer_ls180.v:6133.9-6133.17" - case 1'1 + assign $1\cr_out[2:0] \dec19_dec19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cr_out[2:0] \dec30_dec30_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cr_out[2:0] \dec31_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cr_out[2:0] \dec58_dec58_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cr_out[2:0] \dec62_dec62_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cr_out[2:0] 3'000 case + assign $1\cr_out[2:0] 3'000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- assign { } { } - assign $1\CR_dec31_dec_sub0_cr_out[2:0] 3'000 + assign $2\cr_out[2:0] 3'000 case - assign $1\CR_dec31_dec_sub0_cr_out[2:0] 3'000 + assign $2\cr_out[2:0] $1\cr_out[2:0] end sync always - update \CR_dec31_dec_sub0_cr_out $0\CR_dec31_dec_sub0_cr_out[2:0] + update \cr_out $0\cr_out[2:0] end - attribute \src "issuer_ls180.v:6142.3-6151.6" - process $proc$issuer_ls180.v:6142$131 + attribute \src "libresoc.v:4387.3-4528.6" + process $proc$libresoc.v:4387$251 assign { } { } assign { } { } - assign $0\CR_dec31_dec_sub0_rc_sel[1:0] $1\CR_dec31_dec_sub0_rc_sel[1:0] - attribute \src "issuer_ls180.v:6143.5-6143.29" + assign { } { } + assign $0\ldst_len[3:0] $2\ldst_len[3:0] + attribute \src "libresoc.v:4388.5-4388.29" switch \initial - attribute \src "issuer_ls180.v:6143.9-6143.17" + attribute \src "libresoc.v:4388.9-4388.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 assign { } { } - assign $1\CR_dec31_dec_sub0_rc_sel[1:0] 2'00 - case - assign $1\CR_dec31_dec_sub0_rc_sel[1:0] 2'00 - end - sync always - update \CR_dec31_dec_sub0_rc_sel $0\CR_dec31_dec_sub0_rc_sel[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:6157.1-6799.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub15" -attribute \generator "nMigen" -module \CR_dec31_dec_sub15 - attribute \src "issuer_ls180.v:6489.3-6591.6" - wire width 3 $0\CR_dec31_dec_sub15_cr_in[2:0] - attribute \src "issuer_ls180.v:6592.3-6694.6" - wire width 3 $0\CR_dec31_dec_sub15_cr_out[2:0] - attribute \src "issuer_ls180.v:6283.3-6385.6" - wire width 12 $0\CR_dec31_dec_sub15_function_unit[11:0] - attribute \src "issuer_ls180.v:6386.3-6488.6" - wire width 7 $0\CR_dec31_dec_sub15_internal_op[6:0] - attribute \src "issuer_ls180.v:6695.3-6797.6" - wire width 2 $0\CR_dec31_dec_sub15_rc_sel[1:0] - attribute \src "issuer_ls180.v:6158.7-6158.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:6489.3-6591.6" - wire width 3 $1\CR_dec31_dec_sub15_cr_in[2:0] - attribute \src "issuer_ls180.v:6592.3-6694.6" - wire width 3 $1\CR_dec31_dec_sub15_cr_out[2:0] - attribute \src "issuer_ls180.v:6283.3-6385.6" - wire width 12 $1\CR_dec31_dec_sub15_function_unit[11:0] - attribute \src "issuer_ls180.v:6386.3-6488.6" - wire width 7 $1\CR_dec31_dec_sub15_internal_op[6:0] - attribute \src "issuer_ls180.v:6695.3-6797.6" - wire width 2 $1\CR_dec31_dec_sub15_rc_sel[1:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \CR_dec31_dec_sub15_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 4 \CR_dec31_dec_sub15_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \CR_dec31_dec_sub15_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \CR_dec31_dec_sub15_internal_op - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 5 \CR_dec31_dec_sub15_rc_sel - attribute \src "issuer_ls180.v:6158.7-6158.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:6158.7-6158.20" - process $proc$issuer_ls180.v:6158$138 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:6283.3-6385.6" - process $proc$issuer_ls180.v:6283$133 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub15_function_unit[11:0] $1\CR_dec31_dec_sub15_function_unit[11:0] - attribute \src "issuer_ls180.v:6284.5-6284.29" - switch \initial - attribute \src "issuer_ls180.v:6284.9-6284.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\ldst_len[3:0] \dec19_dec19_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $1\ldst_len[3:0] \dec30_dec30_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 + assign $1\ldst_len[3:0] \dec31_dec31_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 + assign $1\ldst_len[3:0] \dec58_dec58_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + assign $1\ldst_len[3:0] \dec62_dec62_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + case + assign $1\ldst_len[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\ldst_len[3:0] 4'0000 case - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000000000000 + assign $2\ldst_len[3:0] $1\ldst_len[3:0] end sync always - update \CR_dec31_dec_sub15_function_unit $0\CR_dec31_dec_sub15_function_unit[11:0] + update \ldst_len $0\ldst_len[3:0] end - attribute \src "issuer_ls180.v:6386.3-6488.6" - process $proc$issuer_ls180.v:6386$134 + attribute \src "libresoc.v:4529.3-4670.6" + process $proc$libresoc.v:4529$252 assign { } { } assign { } { } - assign $0\CR_dec31_dec_sub15_internal_op[6:0] $1\CR_dec31_dec_sub15_internal_op[6:0] - attribute \src "issuer_ls180.v:6387.5-6387.29" + assign { } { } + assign $0\upd[1:0] $2\upd[1:0] + attribute \src "libresoc.v:4530.5-4530.29" switch \initial - attribute \src "issuer_ls180.v:6387.9-6387.17" + attribute \src "libresoc.v:4530.9-4530.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $1\upd[1:0] \dec19_dec19_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 + assign $1\upd[1:0] \dec30_dec30_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 + assign $1\upd[1:0] \dec31_dec31_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + assign $1\upd[1:0] \dec58_dec58_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 + assign $1\upd[1:0] \dec62_dec62_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\upd[1:0] 2'00 + case + assign $1\upd[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + assign $2\upd[1:0] 2'00 case - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0000000 + assign $2\upd[1:0] $1\upd[1:0] end sync always - update \CR_dec31_dec_sub15_internal_op $0\CR_dec31_dec_sub15_internal_op[6:0] + update \upd $0\upd[1:0] end - attribute \src "issuer_ls180.v:6489.3-6591.6" - process $proc$issuer_ls180.v:6489$135 + attribute \src "libresoc.v:4671.3-4812.6" + process $proc$libresoc.v:4671$253 + assign { } { } assign { } { } assign { } { } - assign $0\CR_dec31_dec_sub15_cr_in[2:0] $1\CR_dec31_dec_sub15_cr_in[2:0] - attribute \src "issuer_ls180.v:6490.5-6490.29" + assign $0\rc_sel[1:0] $2\rc_sel[1:0] + attribute \src "libresoc.v:4672.5-4672.29" switch \initial - attribute \src "issuer_ls180.v:6490.9-6490.17" + attribute \src "libresoc.v:4672.9-4672.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $1\rc_sel[1:0] \dec19_dec19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 + assign $1\rc_sel[1:0] \dec30_dec30_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 + assign $1\rc_sel[1:0] \dec31_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + assign $1\rc_sel[1:0] \dec58_dec58_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 + assign $1\rc_sel[1:0] \dec62_dec62_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 + assign $1\rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + assign $1\rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 case - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'000 + assign $1\rc_sel[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\rc_sel[1:0] 2'00 + case + assign $2\rc_sel[1:0] $1\rc_sel[1:0] end sync always - update \CR_dec31_dec_sub15_cr_in $0\CR_dec31_dec_sub15_cr_in[2:0] + update \rc_sel $0\rc_sel[1:0] end - attribute \src "issuer_ls180.v:6592.3-6694.6" - process $proc$issuer_ls180.v:6592$136 + attribute \src "libresoc.v:4813.3-4954.6" + process $proc$libresoc.v:4813$254 assign { } { } assign { } { } - assign $0\CR_dec31_dec_sub15_cr_out[2:0] $1\CR_dec31_dec_sub15_cr_out[2:0] - attribute \src "issuer_ls180.v:6593.5-6593.29" + assign { } { } + assign $0\cry_in[1:0] $2\cry_in[1:0] + attribute \src "libresoc.v:4814.5-4814.29" switch \initial - attribute \src "issuer_ls180.v:6593.9-6593.17" + attribute \src "libresoc.v:4814.9-4814.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $1\cry_in[1:0] \dec19_dec19_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 + assign $1\cry_in[1:0] \dec30_dec30_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 + assign $1\cry_in[1:0] \dec31_dec31_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + assign $1\cry_in[1:0] \dec58_dec58_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 + assign $1\cry_in[1:0] \dec62_dec62_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 + assign $1\cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + case + assign $1\cry_in[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + assign $2\cry_in[1:0] 2'00 case - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + assign $2\cry_in[1:0] $1\cry_in[1:0] end sync always - update \CR_dec31_dec_sub15_cr_out $0\CR_dec31_dec_sub15_cr_out[2:0] + update \cry_in $0\cry_in[1:0] end - attribute \src "issuer_ls180.v:6695.3-6797.6" - process $proc$issuer_ls180.v:6695$137 + attribute \src "libresoc.v:4955.3-5096.6" + process $proc$libresoc.v:4955$255 + assign { } { } assign { } { } assign { } { } - assign $0\CR_dec31_dec_sub15_rc_sel[1:0] $1\CR_dec31_dec_sub15_rc_sel[1:0] - attribute \src "issuer_ls180.v:6696.5-6696.29" + assign $0\inv_a[0:0] $2\inv_a[0:0] + attribute \src "libresoc.v:4956.5-4956.29" switch \initial - attribute \src "issuer_ls180.v:6696.9-6696.17" + attribute \src "libresoc.v:4956.9-4956.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $1\inv_a[0:0] \dec19_dec19_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 + assign $1\inv_a[0:0] \dec30_dec30_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 + assign $1\inv_a[0:0] \dec31_dec31_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + assign $1\inv_a[0:0] \dec58_dec58_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 + assign $1\inv_a[0:0] \dec62_dec62_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 + assign $1\inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - case - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - end - sync always - update \CR_dec31_dec_sub15_rc_sel $0\CR_dec31_dec_sub15_rc_sel[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:6803.1-6980.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub16" -attribute \generator "nMigen" -module \CR_dec31_dec_sub16 - attribute \src "issuer_ls180.v:6949.3-6958.6" - wire width 3 $0\CR_dec31_dec_sub16_cr_in[2:0] - attribute \src "issuer_ls180.v:6959.3-6968.6" - wire width 3 $0\CR_dec31_dec_sub16_cr_out[2:0] - attribute \src "issuer_ls180.v:6929.3-6938.6" - wire width 12 $0\CR_dec31_dec_sub16_function_unit[11:0] - attribute \src "issuer_ls180.v:6939.3-6948.6" - wire width 7 $0\CR_dec31_dec_sub16_internal_op[6:0] - attribute \src "issuer_ls180.v:6969.3-6978.6" - wire width 2 $0\CR_dec31_dec_sub16_rc_sel[1:0] - attribute \src "issuer_ls180.v:6804.7-6804.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:6949.3-6958.6" - wire width 3 $1\CR_dec31_dec_sub16_cr_in[2:0] - attribute \src "issuer_ls180.v:6959.3-6968.6" - wire width 3 $1\CR_dec31_dec_sub16_cr_out[2:0] - attribute \src "issuer_ls180.v:6929.3-6938.6" - wire width 12 $1\CR_dec31_dec_sub16_function_unit[11:0] - attribute \src "issuer_ls180.v:6939.3-6948.6" - wire width 7 $1\CR_dec31_dec_sub16_internal_op[6:0] - attribute \src "issuer_ls180.v:6969.3-6978.6" - wire width 2 $1\CR_dec31_dec_sub16_rc_sel[1:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \CR_dec31_dec_sub16_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 4 \CR_dec31_dec_sub16_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \CR_dec31_dec_sub16_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \CR_dec31_dec_sub16_internal_op - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 5 \CR_dec31_dec_sub16_rc_sel - attribute \src "issuer_ls180.v:6804.7-6804.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:6804.7-6804.20" - process $proc$issuer_ls180.v:6804$144 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:6929.3-6938.6" - process $proc$issuer_ls180.v:6929$139 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub16_function_unit[11:0] $1\CR_dec31_dec_sub16_function_unit[11:0] - attribute \src "issuer_ls180.v:6930.5-6930.29" - switch \initial - attribute \src "issuer_ls180.v:6930.9-6930.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 assign { } { } - assign $1\CR_dec31_dec_sub16_function_unit[11:0] 12'000001000000 - case - assign $1\CR_dec31_dec_sub16_function_unit[11:0] 12'000000000000 - end - sync always - update \CR_dec31_dec_sub16_function_unit $0\CR_dec31_dec_sub16_function_unit[11:0] - end - attribute \src "issuer_ls180.v:6939.3-6948.6" - process $proc$issuer_ls180.v:6939$140 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub16_internal_op[6:0] $1\CR_dec31_dec_sub16_internal_op[6:0] - attribute \src "issuer_ls180.v:6940.5-6940.29" - switch \initial - attribute \src "issuer_ls180.v:6940.9-6940.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 assign { } { } - assign $1\CR_dec31_dec_sub16_internal_op[6:0] 7'0110000 - case - assign $1\CR_dec31_dec_sub16_internal_op[6:0] 7'0000000 - end - sync always - update \CR_dec31_dec_sub16_internal_op $0\CR_dec31_dec_sub16_internal_op[6:0] - end - attribute \src "issuer_ls180.v:6949.3-6958.6" - process $proc$issuer_ls180.v:6949$141 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub16_cr_in[2:0] $1\CR_dec31_dec_sub16_cr_in[2:0] - attribute \src "issuer_ls180.v:6950.5-6950.29" - switch \initial - attribute \src "issuer_ls180.v:6950.9-6950.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 assign { } { } - assign $1\CR_dec31_dec_sub16_cr_in[2:0] 3'110 - case - assign $1\CR_dec31_dec_sub16_cr_in[2:0] 3'000 - end - sync always - update \CR_dec31_dec_sub16_cr_in $0\CR_dec31_dec_sub16_cr_in[2:0] - end - attribute \src "issuer_ls180.v:6959.3-6968.6" - process $proc$issuer_ls180.v:6959$142 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub16_cr_out[2:0] $1\CR_dec31_dec_sub16_cr_out[2:0] - attribute \src "issuer_ls180.v:6960.5-6960.29" - switch \initial - attribute \src "issuer_ls180.v:6960.9-6960.17" - case 1'1 + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\inv_a[0:0] 1'0 case + assign $1\inv_a[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- assign { } { } - assign $1\CR_dec31_dec_sub16_cr_out[2:0] 3'100 + assign $2\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\inv_a[0:0] 1'0 case - assign $1\CR_dec31_dec_sub16_cr_out[2:0] 3'000 + assign $2\inv_a[0:0] $1\inv_a[0:0] end sync always - update \CR_dec31_dec_sub16_cr_out $0\CR_dec31_dec_sub16_cr_out[2:0] + update \inv_a $0\inv_a[0:0] end - attribute \src "issuer_ls180.v:6969.3-6978.6" - process $proc$issuer_ls180.v:6969$143 + attribute \src "libresoc.v:5097.3-5238.6" + process $proc$libresoc.v:5097$256 + assign { } { } assign { } { } assign { } { } - assign $0\CR_dec31_dec_sub16_rc_sel[1:0] $1\CR_dec31_dec_sub16_rc_sel[1:0] - attribute \src "issuer_ls180.v:6970.5-6970.29" + assign $0\inv_out[0:0] $2\inv_out[0:0] + attribute \src "libresoc.v:5098.5-5098.29" switch \initial - attribute \src "issuer_ls180.v:6970.9-6970.17" + attribute \src "libresoc.v:5098.9-5098.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 assign { } { } - assign $1\CR_dec31_dec_sub16_rc_sel[1:0] 2'00 - case - assign $1\CR_dec31_dec_sub16_rc_sel[1:0] 2'00 - end - sync always - update \CR_dec31_dec_sub16_rc_sel $0\CR_dec31_dec_sub16_rc_sel[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:6984.1-7161.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub19" -attribute \generator "nMigen" -module \CR_dec31_dec_sub19 - attribute \src "issuer_ls180.v:7130.3-7139.6" - wire width 3 $0\CR_dec31_dec_sub19_cr_in[2:0] - attribute \src "issuer_ls180.v:7140.3-7149.6" - wire width 3 $0\CR_dec31_dec_sub19_cr_out[2:0] - attribute \src "issuer_ls180.v:7110.3-7119.6" - wire width 12 $0\CR_dec31_dec_sub19_function_unit[11:0] - attribute \src "issuer_ls180.v:7120.3-7129.6" - wire width 7 $0\CR_dec31_dec_sub19_internal_op[6:0] - attribute \src "issuer_ls180.v:7150.3-7159.6" - wire width 2 $0\CR_dec31_dec_sub19_rc_sel[1:0] - attribute \src "issuer_ls180.v:6985.7-6985.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:7130.3-7139.6" - wire width 3 $1\CR_dec31_dec_sub19_cr_in[2:0] - attribute \src "issuer_ls180.v:7140.3-7149.6" - wire width 3 $1\CR_dec31_dec_sub19_cr_out[2:0] - attribute \src "issuer_ls180.v:7110.3-7119.6" - wire width 12 $1\CR_dec31_dec_sub19_function_unit[11:0] - attribute \src "issuer_ls180.v:7120.3-7129.6" - wire width 7 $1\CR_dec31_dec_sub19_internal_op[6:0] - attribute \src "issuer_ls180.v:7150.3-7159.6" - wire width 2 $1\CR_dec31_dec_sub19_rc_sel[1:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \CR_dec31_dec_sub19_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 4 \CR_dec31_dec_sub19_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \CR_dec31_dec_sub19_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \CR_dec31_dec_sub19_internal_op - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 5 \CR_dec31_dec_sub19_rc_sel - attribute \src "issuer_ls180.v:6985.7-6985.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:6985.7-6985.20" - process $proc$issuer_ls180.v:6985$150 - assign { } { } - assign $0\initial[0:0] 1'0 + assign $1\inv_out[0:0] \dec19_dec19_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\inv_out[0:0] \dec30_dec30_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\inv_out[0:0] \dec31_dec31_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\inv_out[0:0] \dec58_dec58_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\inv_out[0:0] \dec62_dec62_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + case + assign $1\inv_out[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\inv_out[0:0] 1'0 + case + assign $2\inv_out[0:0] $1\inv_out[0:0] + end sync always - update \initial $0\initial[0:0] - sync init + update \inv_out $0\inv_out[0:0] end - attribute \src "issuer_ls180.v:7110.3-7119.6" - process $proc$issuer_ls180.v:7110$145 + attribute \src "libresoc.v:5239.3-5380.6" + process $proc$libresoc.v:5239$257 + assign { } { } assign { } { } assign { } { } - assign $0\CR_dec31_dec_sub19_function_unit[11:0] $1\CR_dec31_dec_sub19_function_unit[11:0] - attribute \src "issuer_ls180.v:7111.5-7111.29" + assign $0\cry_out[0:0] $2\cry_out[0:0] + attribute \src "libresoc.v:5240.5-5240.29" switch \initial - attribute \src "issuer_ls180.v:7111.9-7111.17" + attribute \src "libresoc.v:5240.9-5240.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cry_out[0:0] \dec19_dec19_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cry_out[0:0] \dec30_dec30_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cry_out[0:0] \dec31_dec31_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cry_out[0:0] \dec58_dec58_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cry_out[0:0] \dec62_dec62_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 assign { } { } - assign $1\CR_dec31_dec_sub19_function_unit[11:0] 12'000001000000 + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + case + assign $1\cry_out[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cry_out[0:0] 1'0 case - assign $1\CR_dec31_dec_sub19_function_unit[11:0] 12'000000000000 + assign $2\cry_out[0:0] $1\cry_out[0:0] end sync always - update \CR_dec31_dec_sub19_function_unit $0\CR_dec31_dec_sub19_function_unit[11:0] + update \cry_out $0\cry_out[0:0] end - attribute \src "issuer_ls180.v:7120.3-7129.6" - process $proc$issuer_ls180.v:7120$146 + attribute \src "libresoc.v:5381.3-5522.6" + process $proc$libresoc.v:5381$258 assign { } { } assign { } { } - assign $0\CR_dec31_dec_sub19_internal_op[6:0] $1\CR_dec31_dec_sub19_internal_op[6:0] - attribute \src "issuer_ls180.v:7121.5-7121.29" + assign { } { } + assign $0\br[0:0] $2\br[0:0] + attribute \src "libresoc.v:5382.5-5382.29" switch \initial - attribute \src "issuer_ls180.v:7121.9-7121.17" + attribute \src "libresoc.v:5382.9-5382.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\br[0:0] \dec19_dec19_br + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\br[0:0] \dec30_dec30_br + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\br[0:0] \dec31_dec31_br + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\br[0:0] \dec58_dec58_br + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\br[0:0] \dec62_dec62_br + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 assign { } { } - assign $1\CR_dec31_dec_sub19_internal_op[6:0] 7'0101101 + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\br[0:0] 1'0 + case + assign $1\br[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\br[0:0] 1'0 case - assign $1\CR_dec31_dec_sub19_internal_op[6:0] 7'0000000 + assign $2\br[0:0] $1\br[0:0] end sync always - update \CR_dec31_dec_sub19_internal_op $0\CR_dec31_dec_sub19_internal_op[6:0] + update \br $0\br[0:0] end - attribute \src "issuer_ls180.v:7130.3-7139.6" - process $proc$issuer_ls180.v:7130$147 + attribute \src "libresoc.v:5523.3-5664.6" + process $proc$libresoc.v:5523$259 + assign { } { } assign { } { } assign { } { } - assign $0\CR_dec31_dec_sub19_cr_in[2:0] $1\CR_dec31_dec_sub19_cr_in[2:0] - attribute \src "issuer_ls180.v:7131.5-7131.29" + assign $0\sgn_ext[0:0] $2\sgn_ext[0:0] + attribute \src "libresoc.v:5524.5-5524.29" switch \initial - attribute \src "issuer_ls180.v:7131.9-7131.17" + attribute \src "libresoc.v:5524.9-5524.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sgn_ext[0:0] \dec19_dec19_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sgn_ext[0:0] \dec30_dec30_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sgn_ext[0:0] \dec31_dec31_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sgn_ext[0:0] \dec58_dec58_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sgn_ext[0:0] \dec62_dec62_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + case + assign $1\sgn_ext[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 assign { } { } - assign $1\CR_dec31_dec_sub19_cr_in[2:0] 3'110 + assign $2\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sgn_ext[0:0] 1'0 case - assign $1\CR_dec31_dec_sub19_cr_in[2:0] 3'000 + assign $2\sgn_ext[0:0] $1\sgn_ext[0:0] end sync always - update \CR_dec31_dec_sub19_cr_in $0\CR_dec31_dec_sub19_cr_in[2:0] + update \sgn_ext $0\sgn_ext[0:0] end - attribute \src "issuer_ls180.v:7140.3-7149.6" - process $proc$issuer_ls180.v:7140$148 + attribute \src "libresoc.v:5665.3-5806.6" + process $proc$libresoc.v:5665$260 assign { } { } assign { } { } - assign $0\CR_dec31_dec_sub19_cr_out[2:0] $1\CR_dec31_dec_sub19_cr_out[2:0] - attribute \src "issuer_ls180.v:7141.5-7141.29" + assign { } { } + assign $0\rsrv[0:0] $2\rsrv[0:0] + attribute \src "libresoc.v:5666.5-5666.29" switch \initial - attribute \src "issuer_ls180.v:7141.9-7141.17" + attribute \src "libresoc.v:5666.9-5666.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\rsrv[0:0] \dec19_dec19_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\rsrv[0:0] \dec30_dec30_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\rsrv[0:0] \dec31_dec31_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\rsrv[0:0] \dec58_dec58_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\rsrv[0:0] \dec62_dec62_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + case + assign $1\rsrv[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- assign { } { } - assign $1\CR_dec31_dec_sub19_cr_out[2:0] 3'000 + assign $2\rsrv[0:0] 1'0 case - assign $1\CR_dec31_dec_sub19_cr_out[2:0] 3'000 + assign $2\rsrv[0:0] $1\rsrv[0:0] end sync always - update \CR_dec31_dec_sub19_cr_out $0\CR_dec31_dec_sub19_cr_out[2:0] + update \rsrv $0\rsrv[0:0] end - attribute \src "issuer_ls180.v:7150.3-7159.6" - process $proc$issuer_ls180.v:7150$149 + attribute \src "libresoc.v:5807.3-5948.6" + process $proc$libresoc.v:5807$261 + assign { } { } assign { } { } assign { } { } - assign $0\CR_dec31_dec_sub19_rc_sel[1:0] $1\CR_dec31_dec_sub19_rc_sel[1:0] - attribute \src "issuer_ls180.v:7151.5-7151.29" + assign $0\is_32b[0:0] $2\is_32b[0:0] + attribute \src "libresoc.v:5808.5-5808.29" switch \initial - attribute \src "issuer_ls180.v:7151.9-7151.17" + attribute \src "libresoc.v:5808.9-5808.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\is_32b[0:0] \dec19_dec19_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\is_32b[0:0] \dec30_dec30_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\is_32b[0:0] \dec31_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\is_32b[0:0] \dec58_dec58_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\is_32b[0:0] \dec62_dec62_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + case + assign $1\is_32b[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- assign { } { } - assign $1\CR_dec31_dec_sub19_rc_sel[1:0] 2'00 + assign $2\is_32b[0:0] 1'0 case - assign $1\CR_dec31_dec_sub19_rc_sel[1:0] 2'00 + assign $2\is_32b[0:0] $1\is_32b[0:0] end sync always - update \CR_dec31_dec_sub19_rc_sel $0\CR_dec31_dec_sub19_rc_sel[1:0] + update \is_32b $0\is_32b[0:0] end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:7165.1-7903.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31" -attribute \generator "nMigen" -module \DIV_dec31 - attribute \src "issuer_ls180.v:7873.3-7885.6" - wire width 3 $0\DIV_dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:7886.3-7898.6" - wire width 3 $0\DIV_dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:7743.3-7755.6" - wire width 2 $0\DIV_dec31_cry_in[1:0] - attribute \src "issuer_ls180.v:7782.3-7794.6" - wire $0\DIV_dec31_cry_out[0:0] - attribute \src "issuer_ls180.v:7821.3-7833.6" - wire width 12 $0\DIV_dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:7847.3-7859.6" - wire width 3 $0\DIV_dec31_in1_sel[2:0] - attribute \src "issuer_ls180.v:7860.3-7872.6" - wire width 4 $0\DIV_dec31_in2_sel[3:0] - attribute \src "issuer_ls180.v:7834.3-7846.6" - wire width 7 $0\DIV_dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:7756.3-7768.6" - wire $0\DIV_dec31_inv_a[0:0] - attribute \src "issuer_ls180.v:7769.3-7781.6" - wire $0\DIV_dec31_inv_out[0:0] - attribute \src "issuer_ls180.v:7795.3-7807.6" - wire $0\DIV_dec31_is_32b[0:0] - attribute \src "issuer_ls180.v:7717.3-7729.6" - wire width 4 $0\DIV_dec31_ldst_len[3:0] - attribute \src "issuer_ls180.v:7730.3-7742.6" - wire width 2 $0\DIV_dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:7808.3-7820.6" - wire $0\DIV_dec31_sgn[0:0] - attribute \src "issuer_ls180.v:7166.7-7166.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:7873.3-7885.6" - wire width 3 $1\DIV_dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:7886.3-7898.6" - wire width 3 $1\DIV_dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:7743.3-7755.6" - wire width 2 $1\DIV_dec31_cry_in[1:0] - attribute \src "issuer_ls180.v:7782.3-7794.6" - wire $1\DIV_dec31_cry_out[0:0] - attribute \src "issuer_ls180.v:7821.3-7833.6" - wire width 12 $1\DIV_dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:7847.3-7859.6" - wire width 3 $1\DIV_dec31_in1_sel[2:0] - attribute \src "issuer_ls180.v:7860.3-7872.6" - wire width 4 $1\DIV_dec31_in2_sel[3:0] - attribute \src "issuer_ls180.v:7834.3-7846.6" - wire width 7 $1\DIV_dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:7756.3-7768.6" - wire $1\DIV_dec31_inv_a[0:0] - attribute \src "issuer_ls180.v:7769.3-7781.6" - wire $1\DIV_dec31_inv_out[0:0] - attribute \src "issuer_ls180.v:7795.3-7807.6" - wire $1\DIV_dec31_is_32b[0:0] - attribute \src "issuer_ls180.v:7717.3-7729.6" - wire width 4 $1\DIV_dec31_ldst_len[3:0] - attribute \src "issuer_ls180.v:7730.3-7742.6" - wire width 2 $1\DIV_dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:7808.3-7820.6" - wire $1\DIV_dec31_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \DIV_dec31_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 6 \DIV_dec31_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 9 \DIV_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 12 \DIV_dec31_cry_out - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \DIV_dec31_dec_sub11_opcode_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \DIV_dec31_dec_sub9_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \DIV_dec31_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \DIV_dec31_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 4 \DIV_dec31_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \DIV_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \DIV_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 11 \DIV_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 13 \DIV_dec31_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 7 \DIV_dec31_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \DIV_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 14 \DIV_dec31_sgn - attribute \src "issuer_ls180.v:7166.7-7166.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" - wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 10 \opcode_switch - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:7683.23-7699.4" - cell \DIV_dec31_dec_sub11 \DIV_dec31_dec_sub11 - connect \DIV_dec31_dec_sub11_cr_in \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in - connect \DIV_dec31_dec_sub11_cr_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out - connect \DIV_dec31_dec_sub11_cry_in \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in - connect \DIV_dec31_dec_sub11_cry_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out - connect \DIV_dec31_dec_sub11_function_unit \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit - connect \DIV_dec31_dec_sub11_in1_sel \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel - connect \DIV_dec31_dec_sub11_in2_sel \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel - connect \DIV_dec31_dec_sub11_internal_op \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op - connect \DIV_dec31_dec_sub11_inv_a \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a - connect \DIV_dec31_dec_sub11_inv_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out - connect \DIV_dec31_dec_sub11_is_32b \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b - connect \DIV_dec31_dec_sub11_ldst_len \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len - connect \DIV_dec31_dec_sub11_rc_sel \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel - connect \DIV_dec31_dec_sub11_sgn \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn - connect \opcode_in \DIV_dec31_dec_sub11_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:7700.22-7716.4" - cell \DIV_dec31_dec_sub9 \DIV_dec31_dec_sub9 - connect \DIV_dec31_dec_sub9_cr_in \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in - connect \DIV_dec31_dec_sub9_cr_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out - connect \DIV_dec31_dec_sub9_cry_in \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in - connect \DIV_dec31_dec_sub9_cry_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out - connect \DIV_dec31_dec_sub9_function_unit \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit - connect \DIV_dec31_dec_sub9_in1_sel \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel - connect \DIV_dec31_dec_sub9_in2_sel \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel - connect \DIV_dec31_dec_sub9_internal_op \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op - connect \DIV_dec31_dec_sub9_inv_a \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a - connect \DIV_dec31_dec_sub9_inv_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out - connect \DIV_dec31_dec_sub9_is_32b \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b - connect \DIV_dec31_dec_sub9_ldst_len \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len - connect \DIV_dec31_dec_sub9_rc_sel \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel - connect \DIV_dec31_dec_sub9_sgn \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn - connect \opcode_in \DIV_dec31_dec_sub9_opcode_in - end - attribute \src "issuer_ls180.v:7166.7-7166.20" - process $proc$issuer_ls180.v:7166$165 + attribute \src "libresoc.v:5949.3-6090.6" + process $proc$libresoc.v:5949$262 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:7717.3-7729.6" - process $proc$issuer_ls180.v:7717$151 assign { } { } assign { } { } - assign $0\DIV_dec31_ldst_len[3:0] $1\DIV_dec31_ldst_len[3:0] - attribute \src "issuer_ls180.v:7718.5-7718.29" + assign $0\sgn[0:0] $2\sgn[0:0] + attribute \src "libresoc.v:5950.5-5950.29" switch \initial - attribute \src "issuer_ls180.v:7718.9-7718.17" + attribute \src "libresoc.v:5950.9-5950.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 assign { } { } - assign $1\DIV_dec31_ldst_len[3:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\sgn[0:0] \dec19_dec19_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } - assign $1\DIV_dec31_ldst_len[3:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len - case - assign $1\DIV_dec31_ldst_len[3:0] 4'0000 - end - sync always - update \DIV_dec31_ldst_len $0\DIV_dec31_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:7730.3-7742.6" - process $proc$issuer_ls180.v:7730$152 - assign { } { } - assign { } { } - assign $0\DIV_dec31_rc_sel[1:0] $1\DIV_dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:7731.5-7731.29" - switch \initial - attribute \src "issuer_ls180.v:7731.9-7731.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 + assign $1\sgn[0:0] \dec30_dec30_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 assign { } { } - assign $1\DIV_dec31_rc_sel[1:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\sgn[0:0] \dec31_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } - assign $1\DIV_dec31_rc_sel[1:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel - case - assign $1\DIV_dec31_rc_sel[1:0] 2'00 - end - sync always - update \DIV_dec31_rc_sel $0\DIV_dec31_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:7743.3-7755.6" - process $proc$issuer_ls180.v:7743$153 - assign { } { } - assign { } { } - assign $0\DIV_dec31_cry_in[1:0] $1\DIV_dec31_cry_in[1:0] - attribute \src "issuer_ls180.v:7744.5-7744.29" - switch \initial - attribute \src "issuer_ls180.v:7744.9-7744.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 + assign $1\sgn[0:0] \dec58_dec58_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 assign { } { } - assign $1\DIV_dec31_cry_in[1:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\sgn[0:0] \dec62_dec62_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 assign { } { } - assign $1\DIV_dec31_cry_in[1:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in - case - assign $1\DIV_dec31_cry_in[1:0] 2'00 - end - sync always - update \DIV_dec31_cry_in $0\DIV_dec31_cry_in[1:0] - end - attribute \src "issuer_ls180.v:7756.3-7768.6" - process $proc$issuer_ls180.v:7756$154 - assign { } { } - assign { } { } - assign $0\DIV_dec31_inv_a[0:0] $1\DIV_dec31_inv_a[0:0] - attribute \src "issuer_ls180.v:7757.5-7757.29" - switch \initial - attribute \src "issuer_ls180.v:7757.9-7757.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } - assign $1\DIV_dec31_inv_a[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } - assign $1\DIV_dec31_inv_a[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a - case - assign $1\DIV_dec31_inv_a[0:0] 1'0 - end - sync always - update \DIV_dec31_inv_a $0\DIV_dec31_inv_a[0:0] - end - attribute \src "issuer_ls180.v:7769.3-7781.6" - process $proc$issuer_ls180.v:7769$155 - assign { } { } - assign { } { } - assign $0\DIV_dec31_inv_out[0:0] $1\DIV_dec31_inv_out[0:0] - attribute \src "issuer_ls180.v:7770.5-7770.29" - switch \initial - attribute \src "issuer_ls180.v:7770.9-7770.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 assign { } { } - assign $1\DIV_dec31_inv_out[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 assign { } { } - assign $1\DIV_dec31_inv_out[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out - case - assign $1\DIV_dec31_inv_out[0:0] 1'0 - end - sync always - update \DIV_dec31_inv_out $0\DIV_dec31_inv_out[0:0] - end - attribute \src "issuer_ls180.v:7782.3-7794.6" - process $proc$issuer_ls180.v:7782$156 - assign { } { } - assign { } { } - assign $0\DIV_dec31_cry_out[0:0] $1\DIV_dec31_cry_out[0:0] - attribute \src "issuer_ls180.v:7783.5-7783.29" - switch \initial - attribute \src "issuer_ls180.v:7783.9-7783.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 assign { } { } - assign $1\DIV_dec31_cry_out[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 assign { } { } - assign $1\DIV_dec31_cry_out[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out - case - assign $1\DIV_dec31_cry_out[0:0] 1'0 - end - sync always - update \DIV_dec31_cry_out $0\DIV_dec31_cry_out[0:0] - end - attribute \src "issuer_ls180.v:7795.3-7807.6" - process $proc$issuer_ls180.v:7795$157 - assign { } { } - assign { } { } - assign $0\DIV_dec31_is_32b[0:0] $1\DIV_dec31_is_32b[0:0] - attribute \src "issuer_ls180.v:7796.5-7796.29" - switch \initial - attribute \src "issuer_ls180.v:7796.9-7796.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 assign { } { } - assign $1\DIV_dec31_is_32b[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 assign { } { } - assign $1\DIV_dec31_is_32b[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b - case - assign $1\DIV_dec31_is_32b[0:0] 1'0 - end - sync always - update \DIV_dec31_is_32b $0\DIV_dec31_is_32b[0:0] - end - attribute \src "issuer_ls180.v:7808.3-7820.6" - process $proc$issuer_ls180.v:7808$158 - assign { } { } - assign { } { } - assign $0\DIV_dec31_sgn[0:0] $1\DIV_dec31_sgn[0:0] - attribute \src "issuer_ls180.v:7809.5-7809.29" - switch \initial - attribute \src "issuer_ls180.v:7809.9-7809.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 assign { } { } - assign $1\DIV_dec31_sgn[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 assign { } { } - assign $1\DIV_dec31_sgn[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn - case - assign $1\DIV_dec31_sgn[0:0] 1'0 - end - sync always - update \DIV_dec31_sgn $0\DIV_dec31_sgn[0:0] - end - attribute \src "issuer_ls180.v:7821.3-7833.6" - process $proc$issuer_ls180.v:7821$159 - assign { } { } - assign { } { } - assign $0\DIV_dec31_function_unit[11:0] $1\DIV_dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:7822.5-7822.29" - switch \initial - attribute \src "issuer_ls180.v:7822.9-7822.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 assign { } { } - assign $1\DIV_dec31_function_unit[11:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 assign { } { } - assign $1\DIV_dec31_function_unit[11:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit - case - assign $1\DIV_dec31_function_unit[11:0] 12'000000000000 - end - sync always - update \DIV_dec31_function_unit $0\DIV_dec31_function_unit[11:0] - end - attribute \src "issuer_ls180.v:7834.3-7846.6" - process $proc$issuer_ls180.v:7834$160 - assign { } { } - assign { } { } - assign $0\DIV_dec31_internal_op[6:0] $1\DIV_dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:7835.5-7835.29" - switch \initial - attribute \src "issuer_ls180.v:7835.9-7835.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 assign { } { } - assign $1\DIV_dec31_internal_op[6:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 assign { } { } - assign $1\DIV_dec31_internal_op[6:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op - case - assign $1\DIV_dec31_internal_op[6:0] 7'0000000 - end - sync always - update \DIV_dec31_internal_op $0\DIV_dec31_internal_op[6:0] - end - attribute \src "issuer_ls180.v:7847.3-7859.6" - process $proc$issuer_ls180.v:7847$161 - assign { } { } - assign { } { } - assign $0\DIV_dec31_in1_sel[2:0] $1\DIV_dec31_in1_sel[2:0] - attribute \src "issuer_ls180.v:7848.5-7848.29" - switch \initial - attribute \src "issuer_ls180.v:7848.9-7848.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 assign { } { } - assign $1\DIV_dec31_in1_sel[2:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 assign { } { } - assign $1\DIV_dec31_in1_sel[2:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel - case - assign $1\DIV_dec31_in1_sel[2:0] 3'000 - end - sync always - update \DIV_dec31_in1_sel $0\DIV_dec31_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:7860.3-7872.6" - process $proc$issuer_ls180.v:7860$162 - assign { } { } - assign { } { } - assign $0\DIV_dec31_in2_sel[3:0] $1\DIV_dec31_in2_sel[3:0] - attribute \src "issuer_ls180.v:7861.5-7861.29" - switch \initial - attribute \src "issuer_ls180.v:7861.9-7861.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 assign { } { } - assign $1\DIV_dec31_in2_sel[3:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 assign { } { } - assign $1\DIV_dec31_in2_sel[3:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel - case - assign $1\DIV_dec31_in2_sel[3:0] 4'0000 - end - sync always - update \DIV_dec31_in2_sel $0\DIV_dec31_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:7873.3-7885.6" - process $proc$issuer_ls180.v:7873$163 - assign { } { } - assign { } { } - assign $0\DIV_dec31_cr_in[2:0] $1\DIV_dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:7874.5-7874.29" - switch \initial - attribute \src "issuer_ls180.v:7874.9-7874.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 assign { } { } - assign $1\DIV_dec31_cr_in[2:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 assign { } { } - assign $1\DIV_dec31_cr_in[2:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in - case - assign $1\DIV_dec31_cr_in[2:0] 3'000 - end - sync always - update \DIV_dec31_cr_in $0\DIV_dec31_cr_in[2:0] - end - attribute \src "issuer_ls180.v:7886.3-7898.6" - process $proc$issuer_ls180.v:7886$164 - assign { } { } - assign { } { } - assign $0\DIV_dec31_cr_out[2:0] $1\DIV_dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:7887.5-7887.29" - switch \initial - attribute \src "issuer_ls180.v:7887.9-7887.17" - case 1'1 + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgn[0:0] 1'0 case + assign $1\sgn[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- assign { } { } - assign $1\DIV_dec31_cr_out[2:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $2\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- assign { } { } - assign $1\DIV_dec31_cr_out[2:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out + assign $2\sgn[0:0] 1'0 case - assign $1\DIV_dec31_cr_out[2:0] 3'000 + assign $2\sgn[0:0] $1\sgn[0:0] end sync always - update \DIV_dec31_cr_out $0\DIV_dec31_cr_out[2:0] + update \sgn $0\sgn[0:0] end - connect \DIV_dec31_dec_sub11_opcode_in \opcode_in - connect \DIV_dec31_dec_sub9_opcode_in \opcode_in - connect \opc_in \opcode_switch [4:0] - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "issuer_ls180.v:7907.1-8610.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub11" -attribute \generator "nMigen" -module \DIV_dec31_dec_sub11 - attribute \src "issuer_ls180.v:8424.3-8460.6" - wire width 3 $0\DIV_dec31_dec_sub11_cr_in[2:0] - attribute \src "issuer_ls180.v:8461.3-8497.6" - wire width 3 $0\DIV_dec31_dec_sub11_cr_out[2:0] - attribute \src "issuer_ls180.v:8572.3-8608.6" - wire width 2 $0\DIV_dec31_dec_sub11_cry_in[1:0] - attribute \src "issuer_ls180.v:8202.3-8238.6" - wire $0\DIV_dec31_dec_sub11_cry_out[0:0] - attribute \src "issuer_ls180.v:8091.3-8127.6" - wire width 12 $0\DIV_dec31_dec_sub11_function_unit[11:0] - attribute \src "issuer_ls180.v:8350.3-8386.6" - wire width 3 $0\DIV_dec31_dec_sub11_in1_sel[2:0] - attribute \src "issuer_ls180.v:8387.3-8423.6" - wire width 4 $0\DIV_dec31_dec_sub11_in2_sel[3:0] - attribute \src "issuer_ls180.v:8313.3-8349.6" - wire width 7 $0\DIV_dec31_dec_sub11_internal_op[6:0] - attribute \src "issuer_ls180.v:8128.3-8164.6" - wire $0\DIV_dec31_dec_sub11_inv_a[0:0] - attribute \src "issuer_ls180.v:8165.3-8201.6" - wire $0\DIV_dec31_dec_sub11_inv_out[0:0] - attribute \src "issuer_ls180.v:8239.3-8275.6" - wire $0\DIV_dec31_dec_sub11_is_32b[0:0] - attribute \src "issuer_ls180.v:8498.3-8534.6" - wire width 4 $0\DIV_dec31_dec_sub11_ldst_len[3:0] - attribute \src "issuer_ls180.v:8535.3-8571.6" - wire width 2 $0\DIV_dec31_dec_sub11_rc_sel[1:0] - attribute \src "issuer_ls180.v:8276.3-8312.6" - wire $0\DIV_dec31_dec_sub11_sgn[0:0] - attribute \src "issuer_ls180.v:7908.7-7908.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:8424.3-8460.6" - wire width 3 $1\DIV_dec31_dec_sub11_cr_in[2:0] - attribute \src "issuer_ls180.v:8461.3-8497.6" - wire width 3 $1\DIV_dec31_dec_sub11_cr_out[2:0] - attribute \src "issuer_ls180.v:8572.3-8608.6" - wire width 2 $1\DIV_dec31_dec_sub11_cry_in[1:0] - attribute \src "issuer_ls180.v:8202.3-8238.6" - wire $1\DIV_dec31_dec_sub11_cry_out[0:0] - attribute \src "issuer_ls180.v:8091.3-8127.6" - wire width 12 $1\DIV_dec31_dec_sub11_function_unit[11:0] - attribute \src "issuer_ls180.v:8350.3-8386.6" - wire width 3 $1\DIV_dec31_dec_sub11_in1_sel[2:0] - attribute \src "issuer_ls180.v:8387.3-8423.6" - wire width 4 $1\DIV_dec31_dec_sub11_in2_sel[3:0] - attribute \src "issuer_ls180.v:8313.3-8349.6" - wire width 7 $1\DIV_dec31_dec_sub11_internal_op[6:0] - attribute \src "issuer_ls180.v:8128.3-8164.6" - wire $1\DIV_dec31_dec_sub11_inv_a[0:0] - attribute \src "issuer_ls180.v:8165.3-8201.6" - wire $1\DIV_dec31_dec_sub11_inv_out[0:0] - attribute \src "issuer_ls180.v:8239.3-8275.6" - wire $1\DIV_dec31_dec_sub11_is_32b[0:0] - attribute \src "issuer_ls180.v:8498.3-8534.6" - wire width 4 $1\DIV_dec31_dec_sub11_ldst_len[3:0] - attribute \src "issuer_ls180.v:8535.3-8571.6" - wire width 2 $1\DIV_dec31_dec_sub11_rc_sel[1:0] - attribute \src "issuer_ls180.v:8276.3-8312.6" - wire $1\DIV_dec31_dec_sub11_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \DIV_dec31_dec_sub11_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 6 \DIV_dec31_dec_sub11_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 9 \DIV_dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 12 \DIV_dec31_dec_sub11_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \DIV_dec31_dec_sub11_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \DIV_dec31_dec_sub11_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 4 \DIV_dec31_dec_sub11_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \DIV_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \DIV_dec31_dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 11 \DIV_dec31_dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 13 \DIV_dec31_dec_sub11_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 7 \DIV_dec31_dec_sub11_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \DIV_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 14 \DIV_dec31_dec_sub11_sgn - attribute \src "issuer_ls180.v:7908.7-7908.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:7908.7-7908.20" - process $proc$issuer_ls180.v:7908$180 + attribute \src "libresoc.v:6091.3-6232.6" + process $proc$libresoc.v:6091$263 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:8091.3-8127.6" - process $proc$issuer_ls180.v:8091$166 assign { } { } assign { } { } - assign $0\DIV_dec31_dec_sub11_function_unit[11:0] $1\DIV_dec31_dec_sub11_function_unit[11:0] - attribute \src "issuer_ls180.v:8092.5-8092.29" + assign $0\lk[0:0] $2\lk[0:0] + attribute \src "libresoc.v:6092.5-6092.29" switch \initial - attribute \src "issuer_ls180.v:8092.9-8092.17" + attribute \src "libresoc.v:6092.9-6092.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\lk[0:0] \dec19_dec19_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\lk[0:0] \dec30_dec30_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\lk[0:0] \dec31_dec31_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\lk[0:0] \dec58_dec58_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\lk[0:0] \dec62_dec62_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 - case - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'000000000000 - end - sync always - update \DIV_dec31_dec_sub11_function_unit $0\DIV_dec31_dec_sub11_function_unit[11:0] - end - attribute \src "issuer_ls180.v:8128.3-8164.6" - process $proc$issuer_ls180.v:8128$167 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_inv_a[0:0] $1\DIV_dec31_dec_sub11_inv_a[0:0] - attribute \src "issuer_ls180.v:8129.5-8129.29" - switch \initial - attribute \src "issuer_ls180.v:8129.9-8129.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 - case - assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 - end - sync always - update \DIV_dec31_dec_sub11_inv_a $0\DIV_dec31_dec_sub11_inv_a[0:0] - end - attribute \src "issuer_ls180.v:8165.3-8201.6" - process $proc$issuer_ls180.v:8165$168 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_inv_out[0:0] $1\DIV_dec31_dec_sub11_inv_out[0:0] - attribute \src "issuer_ls180.v:8166.5-8166.29" - switch \initial - attribute \src "issuer_ls180.v:8166.9-8166.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 - case - assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 - end - sync always - update \DIV_dec31_dec_sub11_inv_out $0\DIV_dec31_dec_sub11_inv_out[0:0] - end - attribute \src "issuer_ls180.v:8202.3-8238.6" - process $proc$issuer_ls180.v:8202$169 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_cry_out[0:0] $1\DIV_dec31_dec_sub11_cry_out[0:0] - attribute \src "issuer_ls180.v:8203.5-8203.29" - switch \initial - attribute \src "issuer_ls180.v:8203.9-8203.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\lk[0:0] 1'0 + case + assign $1\lk[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + assign $2\lk[0:0] 1'0 case - assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + assign $2\lk[0:0] $1\lk[0:0] end sync always - update \DIV_dec31_dec_sub11_cry_out $0\DIV_dec31_dec_sub11_cry_out[0:0] + update \lk $0\lk[0:0] end - attribute \src "issuer_ls180.v:8239.3-8275.6" - process $proc$issuer_ls180.v:8239$170 + attribute \src "libresoc.v:6233.3-6374.6" + process $proc$libresoc.v:6233$264 assign { } { } assign { } { } - assign $0\DIV_dec31_dec_sub11_is_32b[0:0] $1\DIV_dec31_dec_sub11_is_32b[0:0] - attribute \src "issuer_ls180.v:8240.5-8240.29" + assign { } { } + assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0] + attribute \src "libresoc.v:6234.5-6234.29" switch \initial - attribute \src "issuer_ls180.v:8240.9-8240.17" + attribute \src "libresoc.v:6234.9-6234.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 assign { } { } - assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\sgl_pipe[0:0] \dec19_dec19_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } - assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\sgl_pipe[0:0] \dec30_dec30_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 assign { } { } - assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\sgl_pipe[0:0] \dec31_dec31_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } - assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\sgl_pipe[0:0] \dec58_dec58_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 assign { } { } - assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\sgl_pipe[0:0] \dec62_dec62_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 assign { } { } - assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } - assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } - assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 assign { } { } - assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 assign { } { } - assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 - case - assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'0 - end - sync always - update \DIV_dec31_dec_sub11_is_32b $0\DIV_dec31_dec_sub11_is_32b[0:0] - end - attribute \src "issuer_ls180.v:8276.3-8312.6" - process $proc$issuer_ls180.v:8276$171 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_sgn[0:0] $1\DIV_dec31_dec_sub11_sgn[0:0] - attribute \src "issuer_ls180.v:8277.5-8277.29" - switch \initial - attribute \src "issuer_ls180.v:8277.9-8277.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 assign { } { } - assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 assign { } { } - assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 assign { } { } - assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 assign { } { } - assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 assign { } { } - assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 assign { } { } - assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 assign { } { } - assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 assign { } { } - assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 assign { } { } - assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 assign { } { } - assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 - case - assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 - end - sync always - update \DIV_dec31_dec_sub11_sgn $0\DIV_dec31_dec_sub11_sgn[0:0] - end - attribute \src "issuer_ls180.v:8313.3-8349.6" - process $proc$issuer_ls180.v:8313$172 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_internal_op[6:0] $1\DIV_dec31_dec_sub11_internal_op[6:0] - attribute \src "issuer_ls180.v:8314.5-8314.29" - switch \initial - attribute \src "issuer_ls180.v:8314.9-8314.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 assign { } { } - assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 assign { } { } - assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 assign { } { } - assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 assign { } { } - assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 assign { } { } - assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 assign { } { } - assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 assign { } { } - assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 assign { } { } - assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 assign { } { } - assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0101111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 assign { } { } - assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0101111 - case - assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0000000 - end - sync always - update \DIV_dec31_dec_sub11_internal_op $0\DIV_dec31_dec_sub11_internal_op[6:0] - end - attribute \src "issuer_ls180.v:8350.3-8386.6" - process $proc$issuer_ls180.v:8350$173 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_in1_sel[2:0] $1\DIV_dec31_dec_sub11_in1_sel[2:0] - attribute \src "issuer_ls180.v:8351.5-8351.29" - switch \initial - attribute \src "issuer_ls180.v:8351.9-8351.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 assign { } { } - assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 assign { } { } - assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 assign { } { } - assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 assign { } { } - assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 assign { } { } - assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 assign { } { } - assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 assign { } { } - assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 assign { } { } - assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 assign { } { } - assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 assign { } { } - assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 - case - assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'000 - end - sync always - update \DIV_dec31_dec_sub11_in1_sel $0\DIV_dec31_dec_sub11_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:8387.3-8423.6" - process $proc$issuer_ls180.v:8387$174 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_in2_sel[3:0] $1\DIV_dec31_dec_sub11_in2_sel[3:0] - attribute \src "issuer_ls180.v:8388.5-8388.29" - switch \initial - attribute \src "issuer_ls180.v:8388.9-8388.17" - case 1'1 + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 case + assign $1\sgl_pipe[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- assign { } { } - assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $2\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 assign { } { } - assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $2\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- assign { } { } - assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + assign $2\sgl_pipe[0:0] 1'1 case - assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0000 + assign $2\sgl_pipe[0:0] $1\sgl_pipe[0:0] end sync always - update \DIV_dec31_dec_sub11_in2_sel $0\DIV_dec31_dec_sub11_in2_sel[3:0] + update \sgl_pipe $0\sgl_pipe[0:0] end - attribute \src "issuer_ls180.v:8424.3-8460.6" - process $proc$issuer_ls180.v:8424$175 + attribute \src "libresoc.v:6375.3-6516.6" + process $proc$libresoc.v:6375$265 + assign { } { } assign { } { } assign { } { } - assign $0\DIV_dec31_dec_sub11_cr_in[2:0] $1\DIV_dec31_dec_sub11_cr_in[2:0] - attribute \src "issuer_ls180.v:8425.5-8425.29" + assign $0\function_unit[11:0] $2\function_unit[11:0] + attribute \src "libresoc.v:6376.5-6376.29" switch \initial - attribute \src "issuer_ls180.v:8425.9-8425.17" + attribute \src "libresoc.v:6376.9-6376.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\function_unit[11:0] \dec19_dec19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\function_unit[11:0] \dec30_dec30_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\function_unit[11:0] \dec31_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\function_unit[11:0] \dec58_dec58_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\function_unit[11:0] \dec62_dec62_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 - case - assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 - end - sync always - update \DIV_dec31_dec_sub11_cr_in $0\DIV_dec31_dec_sub11_cr_in[2:0] - end - attribute \src "issuer_ls180.v:8461.3-8497.6" - process $proc$issuer_ls180.v:8461$176 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_cr_out[2:0] $1\DIV_dec31_dec_sub11_cr_out[2:0] - attribute \src "issuer_ls180.v:8462.5-8462.29" - switch \initial - attribute \src "issuer_ls180.v:8462.9-8462.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + assign $1\function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'000 - case - assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'000 - end - sync always - update \DIV_dec31_dec_sub11_cr_out $0\DIV_dec31_dec_sub11_cr_out[2:0] - end - attribute \src "issuer_ls180.v:8498.3-8534.6" - process $proc$issuer_ls180.v:8498$177 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_ldst_len[3:0] $1\DIV_dec31_dec_sub11_ldst_len[3:0] - attribute \src "issuer_ls180.v:8499.5-8499.29" - switch \initial - attribute \src "issuer_ls180.v:8499.9-8499.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 assign { } { } - assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 assign { } { } - assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 assign { } { } - assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 assign { } { } - assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 assign { } { } - assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 assign { } { } - assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 assign { } { } - assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 assign { } { } - assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 assign { } { } - assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 assign { } { } - assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 - case - assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 - end - sync always - update \DIV_dec31_dec_sub11_ldst_len $0\DIV_dec31_dec_sub11_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:8535.3-8571.6" - process $proc$issuer_ls180.v:8535$178 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_rc_sel[1:0] $1\DIV_dec31_dec_sub11_rc_sel[1:0] - attribute \src "issuer_ls180.v:8536.5-8536.29" - switch \initial - attribute \src "issuer_ls180.v:8536.9-8536.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + assign $1\function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 assign { } { } - assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 assign { } { } - assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 assign { } { } - assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 assign { } { } - assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 assign { } { } - assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 assign { } { } - assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 assign { } { } - assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 assign { } { } - assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 assign { } { } - assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 assign { } { } - assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'00 - case - assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'00 - end - sync always - update \DIV_dec31_dec_sub11_rc_sel $0\DIV_dec31_dec_sub11_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:8572.3-8608.6" - process $proc$issuer_ls180.v:8572$179 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_cry_in[1:0] $1\DIV_dec31_dec_sub11_cry_in[1:0] - attribute \src "issuer_ls180.v:8573.5-8573.29" - switch \initial - attribute \src "issuer_ls180.v:8573.9-8573.17" - case 1'1 + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 case + assign $1\function_unit[11:0] 12'000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $2\function_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $2\function_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + assign $2\function_unit[11:0] 12'000000000000 case - assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + assign $2\function_unit[11:0] $1\function_unit[11:0] end sync always - update \DIV_dec31_dec_sub11_cry_in $0\DIV_dec31_dec_sub11_cry_in[1:0] + update \function_unit $0\function_unit[11:0] end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:8614.1-9317.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub9" -attribute \generator "nMigen" -module \DIV_dec31_dec_sub9 - attribute \src "issuer_ls180.v:9131.3-9167.6" - wire width 3 $0\DIV_dec31_dec_sub9_cr_in[2:0] - attribute \src "issuer_ls180.v:9168.3-9204.6" - wire width 3 $0\DIV_dec31_dec_sub9_cr_out[2:0] - attribute \src "issuer_ls180.v:9279.3-9315.6" - wire width 2 $0\DIV_dec31_dec_sub9_cry_in[1:0] - attribute \src "issuer_ls180.v:8909.3-8945.6" - wire $0\DIV_dec31_dec_sub9_cry_out[0:0] - attribute \src "issuer_ls180.v:8798.3-8834.6" - wire width 12 $0\DIV_dec31_dec_sub9_function_unit[11:0] - attribute \src "issuer_ls180.v:9057.3-9093.6" - wire width 3 $0\DIV_dec31_dec_sub9_in1_sel[2:0] - attribute \src "issuer_ls180.v:9094.3-9130.6" - wire width 4 $0\DIV_dec31_dec_sub9_in2_sel[3:0] - attribute \src "issuer_ls180.v:9020.3-9056.6" - wire width 7 $0\DIV_dec31_dec_sub9_internal_op[6:0] - attribute \src "issuer_ls180.v:8835.3-8871.6" - wire $0\DIV_dec31_dec_sub9_inv_a[0:0] - attribute \src "issuer_ls180.v:8872.3-8908.6" - wire $0\DIV_dec31_dec_sub9_inv_out[0:0] - attribute \src "issuer_ls180.v:8946.3-8982.6" - wire $0\DIV_dec31_dec_sub9_is_32b[0:0] - attribute \src "issuer_ls180.v:9205.3-9241.6" - wire width 4 $0\DIV_dec31_dec_sub9_ldst_len[3:0] - attribute \src "issuer_ls180.v:9242.3-9278.6" - wire width 2 $0\DIV_dec31_dec_sub9_rc_sel[1:0] - attribute \src "issuer_ls180.v:8983.3-9019.6" - wire $0\DIV_dec31_dec_sub9_sgn[0:0] - attribute \src "issuer_ls180.v:8615.7-8615.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:9131.3-9167.6" - wire width 3 $1\DIV_dec31_dec_sub9_cr_in[2:0] - attribute \src "issuer_ls180.v:9168.3-9204.6" - wire width 3 $1\DIV_dec31_dec_sub9_cr_out[2:0] - attribute \src "issuer_ls180.v:9279.3-9315.6" - wire width 2 $1\DIV_dec31_dec_sub9_cry_in[1:0] - attribute \src "issuer_ls180.v:8909.3-8945.6" - wire $1\DIV_dec31_dec_sub9_cry_out[0:0] - attribute \src "issuer_ls180.v:8798.3-8834.6" - wire width 12 $1\DIV_dec31_dec_sub9_function_unit[11:0] - attribute \src "issuer_ls180.v:9057.3-9093.6" - wire width 3 $1\DIV_dec31_dec_sub9_in1_sel[2:0] - attribute \src "issuer_ls180.v:9094.3-9130.6" - wire width 4 $1\DIV_dec31_dec_sub9_in2_sel[3:0] - attribute \src "issuer_ls180.v:9020.3-9056.6" - wire width 7 $1\DIV_dec31_dec_sub9_internal_op[6:0] - attribute \src "issuer_ls180.v:8835.3-8871.6" - wire $1\DIV_dec31_dec_sub9_inv_a[0:0] - attribute \src "issuer_ls180.v:8872.3-8908.6" - wire $1\DIV_dec31_dec_sub9_inv_out[0:0] - attribute \src "issuer_ls180.v:8946.3-8982.6" - wire $1\DIV_dec31_dec_sub9_is_32b[0:0] - attribute \src "issuer_ls180.v:9205.3-9241.6" - wire width 4 $1\DIV_dec31_dec_sub9_ldst_len[3:0] - attribute \src "issuer_ls180.v:9242.3-9278.6" - wire width 2 $1\DIV_dec31_dec_sub9_rc_sel[1:0] - attribute \src "issuer_ls180.v:8983.3-9019.6" - wire $1\DIV_dec31_dec_sub9_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \DIV_dec31_dec_sub9_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 6 \DIV_dec31_dec_sub9_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 9 \DIV_dec31_dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 12 \DIV_dec31_dec_sub9_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \DIV_dec31_dec_sub9_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \DIV_dec31_dec_sub9_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 4 \DIV_dec31_dec_sub9_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \DIV_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \DIV_dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 11 \DIV_dec31_dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 13 \DIV_dec31_dec_sub9_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 7 \DIV_dec31_dec_sub9_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \DIV_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 14 \DIV_dec31_dec_sub9_sgn - attribute \src "issuer_ls180.v:8615.7-8615.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:8615.7-8615.20" - process $proc$issuer_ls180.v:8615$195 + attribute \src "libresoc.v:6517.3-6658.6" + process $proc$libresoc.v:6517$266 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:8798.3-8834.6" - process $proc$issuer_ls180.v:8798$181 assign { } { } assign { } { } - assign $0\DIV_dec31_dec_sub9_function_unit[11:0] $1\DIV_dec31_dec_sub9_function_unit[11:0] - attribute \src "issuer_ls180.v:8799.5-8799.29" + assign $0\internal_op[6:0] $2\internal_op[6:0] + attribute \src "libresoc.v:6518.5-6518.29" switch \initial - attribute \src "issuer_ls180.v:8799.9-8799.17" + attribute \src "libresoc.v:6518.9-6518.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 - case - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'000000000000 - end - sync always - update \DIV_dec31_dec_sub9_function_unit $0\DIV_dec31_dec_sub9_function_unit[11:0] - end - attribute \src "issuer_ls180.v:8835.3-8871.6" - process $proc$issuer_ls180.v:8835$182 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_inv_a[0:0] $1\DIV_dec31_dec_sub9_inv_a[0:0] - attribute \src "issuer_ls180.v:8836.5-8836.29" - switch \initial - attribute \src "issuer_ls180.v:8836.9-8836.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + assign $1\internal_op[6:0] \dec19_dec19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\internal_op[6:0] \dec30_dec30_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\internal_op[6:0] \dec31_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\internal_op[6:0] \dec58_dec58_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\internal_op[6:0] \dec62_dec62_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\internal_op[6:0] 7'1001001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 - case - assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 - end - sync always - update \DIV_dec31_dec_sub9_inv_a $0\DIV_dec31_dec_sub9_inv_a[0:0] - end - attribute \src "issuer_ls180.v:8872.3-8908.6" - process $proc$issuer_ls180.v:8872$183 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_inv_out[0:0] $1\DIV_dec31_dec_sub9_inv_out[0:0] - attribute \src "issuer_ls180.v:8873.5-8873.29" - switch \initial - attribute \src "issuer_ls180.v:8873.9-8873.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + assign $1\internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\internal_op[6:0] 7'0000110 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\internal_op[6:0] 7'0000111 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 - case - assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 - end - sync always - update \DIV_dec31_dec_sub9_inv_out $0\DIV_dec31_dec_sub9_inv_out[0:0] - end - attribute \src "issuer_ls180.v:8909.3-8945.6" - process $proc$issuer_ls180.v:8909$184 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_cry_out[0:0] $1\DIV_dec31_dec_sub9_cry_out[0:0] - attribute \src "issuer_ls180.v:8910.5-8910.29" - switch \initial - attribute \src "issuer_ls180.v:8910.9-8910.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 - case - assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 - end - sync always - update \DIV_dec31_dec_sub9_cry_out $0\DIV_dec31_dec_sub9_cry_out[0:0] - end - attribute \src "issuer_ls180.v:8946.3-8982.6" - process $proc$issuer_ls180.v:8946$185 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_is_32b[0:0] $1\DIV_dec31_dec_sub9_is_32b[0:0] - attribute \src "issuer_ls180.v:8947.5-8947.29" - switch \initial - attribute \src "issuer_ls180.v:8947.9-8947.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 assign { } { } - assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 assign { } { } - assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 assign { } { } - assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 assign { } { } - assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 assign { } { } - assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 assign { } { } - assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 assign { } { } - assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\internal_op[6:0] 7'0111111 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 assign { } { } - assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\internal_op[6:0] 7'0111111 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 assign { } { } - assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\internal_op[6:0] 7'1000011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 assign { } { } - assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 - case - assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 - end - sync always - update \DIV_dec31_dec_sub9_is_32b $0\DIV_dec31_dec_sub9_is_32b[0:0] - end - attribute \src "issuer_ls180.v:8983.3-9019.6" - process $proc$issuer_ls180.v:8983$186 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_sgn[0:0] $1\DIV_dec31_dec_sub9_sgn[0:0] - attribute \src "issuer_ls180.v:8984.5-8984.29" - switch \initial - attribute \src "issuer_ls180.v:8984.9-8984.17" - case 1'1 + assign $1\internal_op[6:0] 7'1000011 case + assign $1\internal_op[6:0] 7'0000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- assign { } { } - assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $2\internal_op[6:0] 7'0000101 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 assign { } { } - assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $2\internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- assign { } { } - assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + assign $2\internal_op[6:0] 7'1000100 case - assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + assign $2\internal_op[6:0] $1\internal_op[6:0] end sync always - update \DIV_dec31_dec_sub9_sgn $0\DIV_dec31_dec_sub9_sgn[0:0] + update \internal_op $0\internal_op[6:0] end - attribute \src "issuer_ls180.v:9020.3-9056.6" - process $proc$issuer_ls180.v:9020$187 + attribute \src "libresoc.v:6659.3-6800.6" + process $proc$libresoc.v:6659$267 assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_internal_op[6:0] $1\DIV_dec31_dec_sub9_internal_op[6:0] - attribute \src "issuer_ls180.v:9021.5-9021.29" - switch \initial - attribute \src "issuer_ls180.v:9021.9-9021.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0101111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0101111 - case - assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0000000 - end - sync always - update \DIV_dec31_dec_sub9_internal_op $0\DIV_dec31_dec_sub9_internal_op[6:0] - end - attribute \src "issuer_ls180.v:9057.3-9093.6" - process $proc$issuer_ls180.v:9057$188 assign { } { } assign { } { } - assign $0\DIV_dec31_dec_sub9_in1_sel[2:0] $1\DIV_dec31_dec_sub9_in1_sel[2:0] - attribute \src "issuer_ls180.v:9058.5-9058.29" + assign $0\form[4:0] $2\form[4:0] + attribute \src "libresoc.v:6660.5-6660.29" switch \initial - attribute \src "issuer_ls180.v:9058.9-9058.17" + attribute \src "libresoc.v:6660.9-6660.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 assign { } { } - assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 - case - assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'000 - end - sync always - update \DIV_dec31_dec_sub9_in1_sel $0\DIV_dec31_dec_sub9_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:9094.3-9130.6" - process $proc$issuer_ls180.v:9094$189 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_in2_sel[3:0] $1\DIV_dec31_dec_sub9_in2_sel[3:0] - attribute \src "issuer_ls180.v:9095.5-9095.29" - switch \initial - attribute \src "issuer_ls180.v:9095.9-9095.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + assign $1\form[4:0] \dec19_dec19_form + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } - assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\form[4:0] \dec30_dec30_form + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 assign { } { } - assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\form[4:0] \dec31_dec31_form + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } - assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\form[4:0] \dec58_dec58_form + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 assign { } { } - assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\form[4:0] \dec62_dec62_form + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 assign { } { } - assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } - assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } - assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 assign { } { } - assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 assign { } { } - assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\form[4:0] 5'00011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 assign { } { } - assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 - case - assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0000 - end - sync always - update \DIV_dec31_dec_sub9_in2_sel $0\DIV_dec31_dec_sub9_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:9131.3-9167.6" - process $proc$issuer_ls180.v:9131$190 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_cr_in[2:0] $1\DIV_dec31_dec_sub9_cr_in[2:0] - attribute \src "issuer_ls180.v:9132.5-9132.29" - switch \initial - attribute \src "issuer_ls180.v:9132.9-9132.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\form[4:0] 5'00001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 - case - assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 - end - sync always - update \DIV_dec31_dec_sub9_cr_in $0\DIV_dec31_dec_sub9_cr_in[2:0] - end - attribute \src "issuer_ls180.v:9168.3-9204.6" - process $proc$issuer_ls180.v:9168$191 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_cr_out[2:0] $1\DIV_dec31_dec_sub9_cr_out[2:0] - attribute \src "issuer_ls180.v:9169.5-9169.29" - switch \initial - attribute \src "issuer_ls180.v:9169.9-9169.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'000 - case - assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'000 - end - sync always - update \DIV_dec31_dec_sub9_cr_out $0\DIV_dec31_dec_sub9_cr_out[2:0] - end - attribute \src "issuer_ls180.v:9205.3-9241.6" - process $proc$issuer_ls180.v:9205$192 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_ldst_len[3:0] $1\DIV_dec31_dec_sub9_ldst_len[3:0] - attribute \src "issuer_ls180.v:9206.5-9206.29" - switch \initial - attribute \src "issuer_ls180.v:9206.9-9206.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 assign { } { } - assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 assign { } { } - assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 assign { } { } - assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 assign { } { } - assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 assign { } { } - assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 assign { } { } - assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 assign { } { } - assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 assign { } { } - assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 assign { } { } - assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 assign { } { } - assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 - case - assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 - end - sync always - update \DIV_dec31_dec_sub9_ldst_len $0\DIV_dec31_dec_sub9_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:9242.3-9278.6" - process $proc$issuer_ls180.v:9242$193 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_rc_sel[1:0] $1\DIV_dec31_dec_sub9_rc_sel[1:0] - attribute \src "issuer_ls180.v:9243.5-9243.29" - switch \initial - attribute \src "issuer_ls180.v:9243.9-9243.17" - case 1'1 + assign $1\form[4:0] 5'00100 case + assign $1\form[4:0] 5'00000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- assign { } { } - assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 + assign $2\form[4:0] 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 assign { } { } - assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $2\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- assign { } { } - assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'00 + assign $2\form[4:0] 5'00000 case - assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'00 + assign $2\form[4:0] $1\form[4:0] end sync always - update \DIV_dec31_dec_sub9_rc_sel $0\DIV_dec31_dec_sub9_rc_sel[1:0] + update \form $0\form[4:0] end - attribute \src "issuer_ls180.v:9279.3-9315.6" - process $proc$issuer_ls180.v:9279$194 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_cry_in[1:0] $1\DIV_dec31_dec_sub9_cry_in[1:0] - attribute \src "issuer_ls180.v:9280.5-9280.29" - switch \initial - attribute \src "issuer_ls180.v:9280.9-9280.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 - case - assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 - end - sync always - update \DIV_dec31_dec_sub9_cry_in $0\DIV_dec31_dec_sub9_cry_in[1:0] - end - connect \opcode_switch \opcode_in [10:6] + connect \$2 $ternary$libresoc.v:3260$243_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \SPR \opcode_in [20:11] + connect \MB \opcode_in [10:6] + connect \ME \opcode_in [5:1] + connect \SH \opcode_in [15:11] + connect \BC \opcode_in [10:6] + connect \TO \opcode_in [25:21] + connect \DS \opcode_in [15:2] + connect \D \opcode_in [15:0] + connect \BH \opcode_in [12:11] + connect \BI \opcode_in [20:16] + connect \BO \opcode_in [25:21] + connect \FXM \opcode_in [19:12] + connect \BT \opcode_in [25:21] + connect \BA \opcode_in [20:16] + connect \BB \opcode_in [15:11] + connect \CR \opcode_in [10:1] + connect \BF \opcode_in [25:23] + connect \BD \opcode_in [15:2] + connect \OE \opcode_in [10] + connect \Rc \opcode_in [0] + connect \AA \opcode_in [1] + connect \LK \opcode_in [0] + connect \LI \opcode_in [25:2] + connect \ME32 \opcode_in [5:1] + connect \MB32 \opcode_in [10:6] + connect \sh { \opcode_in [1] \opcode_in [15:11] } + connect \SH32 \opcode_in [15:11] + connect \L \opcode_in [21] + connect \UI \opcode_in [15:0] + connect \SI \opcode_in [15:0] + connect \RB \opcode_in [15:11] + connect \RA \opcode_in [20:16] + connect \RT \opcode_in [25:21] + connect \RS \opcode_in [25:21] + connect \opcode_in \$2 + connect \opcode_switch$1 \opcode_in + connect \dec62_opcode_in \opcode_in + connect \dec58_opcode_in \opcode_in + connect \dec31_opcode_in \opcode_in + connect \dec30_opcode_in \opcode_in + connect \dec19_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] end -attribute \src "issuer_ls180.v:9321.1-10482.10" +attribute \src "libresoc.v:7139.1-8646.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec19" attribute \generator "nMigen" -module \LDST_dec31 - attribute \src "issuer_ls180.v:10324.3-10342.6" - wire $0\LDST_dec31_br[0:0] - attribute \src "issuer_ls180.v:10229.3-10247.6" - wire width 3 $0\LDST_dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:10248.3-10266.6" - wire width 3 $0\LDST_dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:10400.3-10418.6" - wire width 12 $0\LDST_dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:10438.3-10456.6" - wire width 3 $0\LDST_dec31_in1_sel[2:0] - attribute \src "issuer_ls180.v:10457.3-10475.6" - wire width 4 $0\LDST_dec31_in2_sel[3:0] - attribute \src "issuer_ls180.v:10419.3-10437.6" - wire width 7 $0\LDST_dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:10362.3-10380.6" - wire $0\LDST_dec31_is_32b[0:0] - attribute \src "issuer_ls180.v:10267.3-10285.6" - wire width 4 $0\LDST_dec31_ldst_len[3:0] - attribute \src "issuer_ls180.v:10305.3-10323.6" - wire width 2 $0\LDST_dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:10381.3-10399.6" - wire $0\LDST_dec31_sgn[0:0] - attribute \src "issuer_ls180.v:10343.3-10361.6" - wire $0\LDST_dec31_sgn_ext[0:0] - attribute \src "issuer_ls180.v:10286.3-10304.6" - wire width 2 $0\LDST_dec31_upd[1:0] - attribute \src "issuer_ls180.v:9322.7-9322.20" +module \dec19 + attribute \src "libresoc.v:7657.3-7708.6" + wire width 8 $0\dec19_asmcode[7:0] + attribute \src "libresoc.v:7865.3-7916.6" + wire $0\dec19_br[0:0] + attribute \src "libresoc.v:8541.3-8592.6" + wire width 3 $0\dec19_cr_in[2:0] + attribute \src "libresoc.v:8593.3-8644.6" + wire width 3 $0\dec19_cr_out[2:0] + attribute \src "libresoc.v:7605.3-7656.6" + wire width 2 $0\dec19_cry_in[1:0] + attribute \src "libresoc.v:7813.3-7864.6" + wire $0\dec19_cry_out[0:0] + attribute \src "libresoc.v:8281.3-8332.6" + wire width 5 $0\dec19_form[4:0] + attribute \src "libresoc.v:7397.3-7448.6" + wire width 12 $0\dec19_function_unit[11:0] + attribute \src "libresoc.v:8333.3-8384.6" + wire width 3 $0\dec19_in1_sel[2:0] + attribute \src "libresoc.v:8385.3-8436.6" + wire width 4 $0\dec19_in2_sel[3:0] + attribute \src "libresoc.v:8437.3-8488.6" + wire width 2 $0\dec19_in3_sel[1:0] + attribute \src "libresoc.v:7969.3-8020.6" + wire width 7 $0\dec19_internal_op[6:0] + attribute \src "libresoc.v:7709.3-7760.6" + wire $0\dec19_inv_a[0:0] + attribute \src "libresoc.v:7761.3-7812.6" + wire $0\dec19_inv_out[0:0] + attribute \src "libresoc.v:8073.3-8124.6" + wire $0\dec19_is_32b[0:0] + attribute \src "libresoc.v:7449.3-7500.6" + wire width 4 $0\dec19_ldst_len[3:0] + attribute \src "libresoc.v:8177.3-8228.6" + wire $0\dec19_lk[0:0] + attribute \src "libresoc.v:8489.3-8540.6" + wire width 2 $0\dec19_out_sel[1:0] + attribute \src "libresoc.v:7553.3-7604.6" + wire width 2 $0\dec19_rc_sel[1:0] + attribute \src "libresoc.v:8021.3-8072.6" + wire $0\dec19_rsrv[0:0] + attribute \src "libresoc.v:8229.3-8280.6" + wire $0\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:8125.3-8176.6" + wire $0\dec19_sgn[0:0] + attribute \src "libresoc.v:7917.3-7968.6" + wire $0\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:7501.3-7552.6" + wire width 2 $0\dec19_upd[1:0] + attribute \src "libresoc.v:7140.7-7140.20" wire $0\initial[0:0] - attribute \src "issuer_ls180.v:10324.3-10342.6" - wire $1\LDST_dec31_br[0:0] - attribute \src "issuer_ls180.v:10229.3-10247.6" - wire width 3 $1\LDST_dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:10248.3-10266.6" - wire width 3 $1\LDST_dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:10400.3-10418.6" - wire width 12 $1\LDST_dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:10438.3-10456.6" - wire width 3 $1\LDST_dec31_in1_sel[2:0] - attribute \src "issuer_ls180.v:10457.3-10475.6" - wire width 4 $1\LDST_dec31_in2_sel[3:0] - attribute \src "issuer_ls180.v:10419.3-10437.6" - wire width 7 $1\LDST_dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:10362.3-10380.6" - wire $1\LDST_dec31_is_32b[0:0] - attribute \src "issuer_ls180.v:10267.3-10285.6" - wire width 4 $1\LDST_dec31_ldst_len[3:0] - attribute \src "issuer_ls180.v:10305.3-10323.6" - wire width 2 $1\LDST_dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:10381.3-10399.6" - wire $1\LDST_dec31_sgn[0:0] - attribute \src "issuer_ls180.v:10343.3-10361.6" - wire $1\LDST_dec31_sgn_ext[0:0] - attribute \src "issuer_ls180.v:10286.3-10304.6" - wire width 2 $1\LDST_dec31_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \LDST_dec31_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \LDST_dec31_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" + attribute \src "libresoc.v:7657.3-7708.6" + wire width 8 $1\dec19_asmcode[7:0] + attribute \src "libresoc.v:7865.3-7916.6" + wire $1\dec19_br[0:0] + attribute \src "libresoc.v:8541.3-8592.6" + wire width 3 $1\dec19_cr_in[2:0] + attribute \src "libresoc.v:8593.3-8644.6" + wire width 3 $1\dec19_cr_out[2:0] + attribute \src "libresoc.v:7605.3-7656.6" + wire width 2 $1\dec19_cry_in[1:0] + attribute \src "libresoc.v:7813.3-7864.6" + wire $1\dec19_cry_out[0:0] + attribute \src "libresoc.v:8281.3-8332.6" + wire width 5 $1\dec19_form[4:0] + attribute \src "libresoc.v:7397.3-7448.6" + wire width 12 $1\dec19_function_unit[11:0] + attribute \src "libresoc.v:8333.3-8384.6" + wire width 3 $1\dec19_in1_sel[2:0] + attribute \src "libresoc.v:8385.3-8436.6" + wire width 4 $1\dec19_in2_sel[3:0] + attribute \src "libresoc.v:8437.3-8488.6" + wire width 2 $1\dec19_in3_sel[1:0] + attribute \src "libresoc.v:7969.3-8020.6" + wire width 7 $1\dec19_internal_op[6:0] + attribute \src "libresoc.v:7709.3-7760.6" + wire $1\dec19_inv_a[0:0] + attribute \src "libresoc.v:7761.3-7812.6" + wire $1\dec19_inv_out[0:0] + attribute \src "libresoc.v:8073.3-8124.6" + wire $1\dec19_is_32b[0:0] + attribute \src "libresoc.v:7449.3-7500.6" + wire width 4 $1\dec19_ldst_len[3:0] + attribute \src "libresoc.v:8177.3-8228.6" + wire $1\dec19_lk[0:0] + attribute \src "libresoc.v:8489.3-8540.6" + wire width 2 $1\dec19_out_sel[1:0] + attribute \src "libresoc.v:7553.3-7604.6" + wire width 2 $1\dec19_rc_sel[1:0] + attribute \src "libresoc.v:8021.3-8072.6" + wire $1\dec19_rsrv[0:0] + attribute \src "libresoc.v:8229.3-8280.6" + wire $1\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:8125.3-8176.6" + wire $1\dec19_sgn[0:0] + attribute \src "libresoc.v:7917.3-7968.6" + wire $1\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:7501.3-7552.6" + wire width 2 $1\dec19_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 6 \LDST_dec31_cr_out + wire width 8 output 4 \dec19_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br + wire output 18 \dec19_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -13448,7 +11074,7 @@ module \LDST_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in + wire width 3 output 9 \dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -13456,172 +11082,47 @@ module \LDST_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" + wire width 3 output 10 \dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \LDST_dec31_dec_sub20_opcode_in + wire width 2 output 14 \dec19_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" + wire output 17 \dec19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out + wire width 5 output 3 \dec19_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -13636,7 +11137,7 @@ module \LDST_dec31 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit + wire width 12 output 1 \dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -13644,7 +11145,7 @@ module \LDST_dec31 attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel + wire width 3 output 5 \dec19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -13661,172 +11162,13 @@ module \LDST_dec31 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext - attribute \enum_base_type "LDSTMode" + wire width 4 output 6 \dec19_in2_sel + attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \LDST_dec31_dec_sub21_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel + wire width 2 output 7 \dec19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -13902,9 +11244,13 @@ module \LDST_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op + wire width 7 output 2 \dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec19_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b + wire output 16 \dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -13912,2988 +11258,2579 @@ module \LDST_dec31 attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn + wire width 4 output 11 \dec19_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext - attribute \enum_base_type "LDSTMode" + wire output 23 \dec19_lk + attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \LDST_dec31_dec_sub22_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 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\LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in - connect \LDST_dec31_dec_sub22_cr_out \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out - connect \LDST_dec31_dec_sub22_function_unit \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit - connect \LDST_dec31_dec_sub22_in1_sel \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel - connect \LDST_dec31_dec_sub22_in2_sel \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel - connect \LDST_dec31_dec_sub22_internal_op \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op - connect \LDST_dec31_dec_sub22_is_32b \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b - connect \LDST_dec31_dec_sub22_ldst_len \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len - connect \LDST_dec31_dec_sub22_rc_sel \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel - connect \LDST_dec31_dec_sub22_sgn \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn - connect \LDST_dec31_dec_sub22_sgn_ext \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext - connect \LDST_dec31_dec_sub22_upd \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd - connect \opcode_in \LDST_dec31_dec_sub22_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:10213.24-10228.4" - cell \LDST_dec31_dec_sub23 \LDST_dec31_dec_sub23 - connect \LDST_dec31_dec_sub23_br \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br - connect \LDST_dec31_dec_sub23_cr_in \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in - connect \LDST_dec31_dec_sub23_cr_out \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out - connect \LDST_dec31_dec_sub23_function_unit \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit - connect \LDST_dec31_dec_sub23_in1_sel \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel - connect \LDST_dec31_dec_sub23_in2_sel \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel - connect \LDST_dec31_dec_sub23_internal_op \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op - connect \LDST_dec31_dec_sub23_is_32b \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b - connect \LDST_dec31_dec_sub23_ldst_len \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len - connect \LDST_dec31_dec_sub23_rc_sel \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel - connect \LDST_dec31_dec_sub23_sgn \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn - connect \LDST_dec31_dec_sub23_sgn_ext \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext - connect \LDST_dec31_dec_sub23_upd \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd - connect \opcode_in \LDST_dec31_dec_sub23_opcode_in - end - attribute \src "issuer_ls180.v:10229.3-10247.6" - process $proc$issuer_ls180.v:10229$196 - assign { } { } - assign { } { } - assign $0\LDST_dec31_cr_in[2:0] $1\LDST_dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:10230.5-10230.29" - switch \initial - attribute \src "issuer_ls180.v:10230.9-10230.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in - case - assign $1\LDST_dec31_cr_in[2:0] 3'000 - end + attribute \src "libresoc.v:7140.7-7140.20" + process $proc$libresoc.v:7140$293 + assign { } { } + assign $0\initial[0:0] 1'0 sync always - update \LDST_dec31_cr_in $0\LDST_dec31_cr_in[2:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "issuer_ls180.v:10248.3-10266.6" - process $proc$issuer_ls180.v:10248$197 + attribute \src "libresoc.v:7397.3-7448.6" + process $proc$libresoc.v:7397$269 assign { } { } assign { } { } - assign $0\LDST_dec31_cr_out[2:0] $1\LDST_dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:10249.5-10249.29" + assign $0\dec19_function_unit[11:0] $1\dec19_function_unit[11:0] + attribute \src "libresoc.v:7398.5-7398.29" switch \initial - attribute \src "issuer_ls180.v:10249.9-10249.17" + attribute \src "libresoc.v:7398.9-7398.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } - assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out - case - assign $1\LDST_dec31_cr_out[2:0] 3'000 - end - sync always - update \LDST_dec31_cr_out $0\LDST_dec31_cr_out[2:0] - end - attribute \src "issuer_ls180.v:10267.3-10285.6" - process $proc$issuer_ls180.v:10267$198 - assign { } { } - assign { } { } - assign $0\LDST_dec31_ldst_len[3:0] $1\LDST_dec31_ldst_len[3:0] - attribute \src "issuer_ls180.v:10268.5-10268.29" - switch \initial - attribute \src "issuer_ls180.v:10268.9-10268.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 assign { } { } - assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 assign { } { } - assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 assign { } { } - assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len - case - assign $1\LDST_dec31_ldst_len[3:0] 4'0000 - end - sync always - update \LDST_dec31_ldst_len $0\LDST_dec31_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:10286.3-10304.6" - process $proc$issuer_ls180.v:10286$199 - assign { } { } - assign { } { } - assign $0\LDST_dec31_upd[1:0] $1\LDST_dec31_upd[1:0] - attribute \src "issuer_ls180.v:10287.5-10287.29" - switch \initial - attribute \src "issuer_ls180.v:10287.9-10287.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 assign { } { } - assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 assign { } { } - assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 + assign $1\dec19_function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 assign { } { } - assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 + assign $1\dec19_function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 assign { } { } - assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd + assign $1\dec19_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000010000000 case - assign $1\LDST_dec31_upd[1:0] 2'00 + assign $1\dec19_function_unit[11:0] 12'000000000000 end sync always - update \LDST_dec31_upd $0\LDST_dec31_upd[1:0] + update \dec19_function_unit $0\dec19_function_unit[11:0] end - attribute \src "issuer_ls180.v:10305.3-10323.6" - process $proc$issuer_ls180.v:10305$200 + attribute \src "libresoc.v:7449.3-7500.6" + process $proc$libresoc.v:7449$270 assign { } { } assign { } { } - assign $0\LDST_dec31_rc_sel[1:0] $1\LDST_dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:10306.5-10306.29" + assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0] + attribute \src "libresoc.v:7450.5-7450.29" switch \initial - attribute \src "issuer_ls180.v:10306.9-10306.17" + attribute \src "libresoc.v:7450.9-7450.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } - assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel - case - assign $1\LDST_dec31_rc_sel[1:0] 2'00 - end - sync always - update \LDST_dec31_rc_sel $0\LDST_dec31_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:10324.3-10342.6" - process $proc$issuer_ls180.v:10324$201 - assign { } { } - assign { } { } - assign $0\LDST_dec31_br[0:0] $1\LDST_dec31_br[0:0] - attribute \src "issuer_ls180.v:10325.5-10325.29" - switch \initial - attribute \src "issuer_ls180.v:10325.9-10325.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 assign { } { } - assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 assign { } { } - assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 assign { } { } - assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br - case - assign $1\LDST_dec31_br[0:0] 1'0 - end - sync always - update \LDST_dec31_br $0\LDST_dec31_br[0:0] - end - attribute \src "issuer_ls180.v:10343.3-10361.6" - process $proc$issuer_ls180.v:10343$202 - assign { } { } - assign { } { } - assign $0\LDST_dec31_sgn_ext[0:0] $1\LDST_dec31_sgn_ext[0:0] - attribute \src "issuer_ls180.v:10344.5-10344.29" - switch \initial - attribute \src "issuer_ls180.v:10344.9-10344.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 assign { } { } - assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 assign { } { } - assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 assign { } { } - assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 assign { } { } - assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 case - assign $1\LDST_dec31_sgn_ext[0:0] 1'0 + assign $1\dec19_ldst_len[3:0] 4'0000 end sync always - update \LDST_dec31_sgn_ext $0\LDST_dec31_sgn_ext[0:0] + update \dec19_ldst_len $0\dec19_ldst_len[3:0] end - attribute \src "issuer_ls180.v:10362.3-10380.6" - process $proc$issuer_ls180.v:10362$203 + attribute \src "libresoc.v:7501.3-7552.6" + process $proc$libresoc.v:7501$271 assign { } { } assign { } { } - assign $0\LDST_dec31_is_32b[0:0] $1\LDST_dec31_is_32b[0:0] - attribute \src "issuer_ls180.v:10363.5-10363.29" + assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] + attribute \src "libresoc.v:7502.5-7502.29" switch \initial - attribute \src "issuer_ls180.v:10363.9-10363.17" + attribute \src "libresoc.v:7502.9-7502.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } - assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b - case - assign $1\LDST_dec31_is_32b[0:0] 1'0 - end - sync always - update \LDST_dec31_is_32b $0\LDST_dec31_is_32b[0:0] - end - attribute \src "issuer_ls180.v:10381.3-10399.6" - process $proc$issuer_ls180.v:10381$204 - assign { } { } - assign { } { } - assign $0\LDST_dec31_sgn[0:0] $1\LDST_dec31_sgn[0:0] - attribute \src "issuer_ls180.v:10382.5-10382.29" - switch \initial - attribute \src "issuer_ls180.v:10382.9-10382.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 assign { } { } - assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 assign { } { } - assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 assign { } { } - assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn - case - assign $1\LDST_dec31_sgn[0:0] 1'0 - end - sync always - update \LDST_dec31_sgn $0\LDST_dec31_sgn[0:0] - end - attribute \src "issuer_ls180.v:10400.3-10418.6" - process $proc$issuer_ls180.v:10400$205 - assign { } { } - assign { } { } - assign $0\LDST_dec31_function_unit[11:0] $1\LDST_dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:10401.5-10401.29" - switch \initial - attribute \src "issuer_ls180.v:10401.9-10401.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 assign { } { } - assign $1\LDST_dec31_function_unit[11:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 assign { } { } - assign $1\LDST_dec31_function_unit[11:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 assign { } { } - assign $1\LDST_dec31_function_unit[11:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 assign { } { } - assign $1\LDST_dec31_function_unit[11:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 case - assign $1\LDST_dec31_function_unit[11:0] 12'000000000000 + assign $1\dec19_upd[1:0] 2'00 end sync always - update \LDST_dec31_function_unit $0\LDST_dec31_function_unit[11:0] + update \dec19_upd $0\dec19_upd[1:0] end - attribute \src "issuer_ls180.v:10419.3-10437.6" - process $proc$issuer_ls180.v:10419$206 + attribute \src "libresoc.v:7553.3-7604.6" + process $proc$libresoc.v:7553$272 assign { } { } assign { } { } - assign $0\LDST_dec31_internal_op[6:0] $1\LDST_dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:10420.5-10420.29" + assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0] + attribute \src "libresoc.v:7554.5-7554.29" switch \initial - attribute \src "issuer_ls180.v:10420.9-10420.17" + attribute \src "libresoc.v:7554.9-7554.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } - assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op - case - assign $1\LDST_dec31_internal_op[6:0] 7'0000000 - end - sync always - update \LDST_dec31_internal_op $0\LDST_dec31_internal_op[6:0] - end - attribute \src "issuer_ls180.v:10438.3-10456.6" - process $proc$issuer_ls180.v:10438$207 - assign { } { } - assign { } { } - assign $0\LDST_dec31_in1_sel[2:0] $1\LDST_dec31_in1_sel[2:0] - attribute \src "issuer_ls180.v:10439.5-10439.29" - switch \initial - attribute \src "issuer_ls180.v:10439.9-10439.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 assign { } { } - assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 assign { } { } - assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 assign { } { } - assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel - case - assign $1\LDST_dec31_in1_sel[2:0] 3'000 - end - sync always - update \LDST_dec31_in1_sel $0\LDST_dec31_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:10457.3-10475.6" - process $proc$issuer_ls180.v:10457$208 - assign { } { } - assign { } { } - assign $0\LDST_dec31_in2_sel[3:0] $1\LDST_dec31_in2_sel[3:0] - attribute \src "issuer_ls180.v:10458.5-10458.29" - switch \initial - attribute \src "issuer_ls180.v:10458.9-10458.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 assign { } { } - assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 assign { } { } - assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 assign { } { } - assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel + assign $1\dec19_rc_sel[1:0] 2'00 case - assign $1\LDST_dec31_in2_sel[3:0] 4'0000 + assign $1\dec19_rc_sel[1:0] 2'00 end sync always - update \LDST_dec31_in2_sel $0\LDST_dec31_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:9322.7-9322.20" - process $proc$issuer_ls180.v:9322$209 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - connect \LDST_dec31_dec_sub23_opcode_in \opcode_in - connect \LDST_dec31_dec_sub21_opcode_in \opcode_in - connect \LDST_dec31_dec_sub20_opcode_in \opcode_in - connect \LDST_dec31_dec_sub22_opcode_in \opcode_in - connect \opc_in \opcode_switch [4:0] - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "issuer_ls180.v:10486.1-10994.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub20" -attribute \generator "nMigen" -module \LDST_dec31_dec_sub20 - attribute \src "issuer_ls180.v:10693.3-10717.6" - wire $0\LDST_dec31_dec_sub20_br[0:0] - attribute \src "issuer_ls180.v:10868.3-10892.6" - wire width 3 $0\LDST_dec31_dec_sub20_cr_in[2:0] - attribute \src "issuer_ls180.v:10893.3-10917.6" - wire width 3 $0\LDST_dec31_dec_sub20_cr_out[2:0] - attribute \src "issuer_ls180.v:10668.3-10692.6" - wire width 12 $0\LDST_dec31_dec_sub20_function_unit[11:0] - attribute \src "issuer_ls180.v:10818.3-10842.6" - wire width 3 $0\LDST_dec31_dec_sub20_in1_sel[2:0] - attribute \src "issuer_ls180.v:10843.3-10867.6" - wire width 4 $0\LDST_dec31_dec_sub20_in2_sel[3:0] - attribute \src "issuer_ls180.v:10793.3-10817.6" - wire width 7 $0\LDST_dec31_dec_sub20_internal_op[6:0] - attribute \src "issuer_ls180.v:10743.3-10767.6" - wire $0\LDST_dec31_dec_sub20_is_32b[0:0] - attribute \src "issuer_ls180.v:10918.3-10942.6" - wire width 4 $0\LDST_dec31_dec_sub20_ldst_len[3:0] - attribute \src "issuer_ls180.v:10968.3-10992.6" - wire width 2 $0\LDST_dec31_dec_sub20_rc_sel[1:0] - attribute \src "issuer_ls180.v:10768.3-10792.6" - wire $0\LDST_dec31_dec_sub20_sgn[0:0] - attribute \src "issuer_ls180.v:10718.3-10742.6" - wire $0\LDST_dec31_dec_sub20_sgn_ext[0:0] - attribute \src "issuer_ls180.v:10943.3-10967.6" - wire width 2 $0\LDST_dec31_dec_sub20_upd[1:0] - attribute \src "issuer_ls180.v:10487.7-10487.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:10693.3-10717.6" - wire $1\LDST_dec31_dec_sub20_br[0:0] - attribute \src "issuer_ls180.v:10868.3-10892.6" - wire width 3 $1\LDST_dec31_dec_sub20_cr_in[2:0] - attribute \src "issuer_ls180.v:10893.3-10917.6" - wire width 3 $1\LDST_dec31_dec_sub20_cr_out[2:0] - attribute \src "issuer_ls180.v:10668.3-10692.6" - wire width 12 $1\LDST_dec31_dec_sub20_function_unit[11:0] - attribute \src "issuer_ls180.v:10818.3-10842.6" - wire width 3 $1\LDST_dec31_dec_sub20_in1_sel[2:0] - attribute \src "issuer_ls180.v:10843.3-10867.6" - wire width 4 $1\LDST_dec31_dec_sub20_in2_sel[3:0] - attribute \src "issuer_ls180.v:10793.3-10817.6" - wire width 7 $1\LDST_dec31_dec_sub20_internal_op[6:0] - attribute \src "issuer_ls180.v:10743.3-10767.6" - wire $1\LDST_dec31_dec_sub20_is_32b[0:0] - attribute \src "issuer_ls180.v:10918.3-10942.6" - wire width 4 $1\LDST_dec31_dec_sub20_ldst_len[3:0] - attribute \src "issuer_ls180.v:10968.3-10992.6" - wire width 2 $1\LDST_dec31_dec_sub20_rc_sel[1:0] - attribute \src "issuer_ls180.v:10768.3-10792.6" - wire $1\LDST_dec31_dec_sub20_sgn[0:0] - attribute \src "issuer_ls180.v:10718.3-10742.6" - wire $1\LDST_dec31_dec_sub20_sgn_ext[0:0] - attribute \src "issuer_ls180.v:10943.3-10967.6" - wire width 2 $1\LDST_dec31_dec_sub20_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \LDST_dec31_dec_sub20_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \LDST_dec31_dec_sub20_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 6 \LDST_dec31_dec_sub20_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \LDST_dec31_dec_sub20_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \LDST_dec31_dec_sub20_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 4 \LDST_dec31_dec_sub20_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \LDST_dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 12 \LDST_dec31_dec_sub20_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 7 \LDST_dec31_dec_sub20_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 9 \LDST_dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 13 \LDST_dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 11 \LDST_dec31_dec_sub20_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \LDST_dec31_dec_sub20_upd - attribute \src "issuer_ls180.v:10487.7-10487.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:10487.7-10487.20" - process $proc$issuer_ls180.v:10487$223 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + update \dec19_rc_sel $0\dec19_rc_sel[1:0] end - attribute \src "issuer_ls180.v:10668.3-10692.6" - process $proc$issuer_ls180.v:10668$210 + attribute \src "libresoc.v:7605.3-7656.6" + process $proc$libresoc.v:7605$273 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub20_function_unit[11:0] $1\LDST_dec31_dec_sub20_function_unit[11:0] - attribute \src "issuer_ls180.v:10669.5-10669.29" + assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0] + attribute \src "libresoc.v:7606.5-7606.29" switch \initial - attribute \src "issuer_ls180.v:10669.9-10669.17" + attribute \src "libresoc.v:7606.9-7606.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } - assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 - case - assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000000 - end - sync always - update \LDST_dec31_dec_sub20_function_unit $0\LDST_dec31_dec_sub20_function_unit[11:0] - end - attribute \src "issuer_ls180.v:10693.3-10717.6" - process $proc$issuer_ls180.v:10693$211 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub20_br[0:0] $1\LDST_dec31_dec_sub20_br[0:0] - attribute \src "issuer_ls180.v:10694.5-10694.29" - switch \initial - attribute \src "issuer_ls180.v:10694.9-10694.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_br[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 assign { } { } - assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 assign { } { } - assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $1\LDST_dec31_dec_sub20_br[0:0] 1'1 + assign $1\dec19_cry_in[1:0] 2'00 case - assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + assign $1\dec19_cry_in[1:0] 2'00 end sync always - update \LDST_dec31_dec_sub20_br $0\LDST_dec31_dec_sub20_br[0:0] + update \dec19_cry_in $0\dec19_cry_in[1:0] end - attribute \src "issuer_ls180.v:10718.3-10742.6" - process $proc$issuer_ls180.v:10718$212 + attribute \src "libresoc.v:7657.3-7708.6" + process $proc$libresoc.v:7657$274 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub20_sgn_ext[0:0] $1\LDST_dec31_dec_sub20_sgn_ext[0:0] - attribute \src "issuer_ls180.v:10719.5-10719.29" + assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0] + attribute \src "libresoc.v:7658.5-7658.29" switch \initial - attribute \src "issuer_ls180.v:10719.9-10719.17" + attribute \src "libresoc.v:7658.9-7658.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } - assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 + assign $1\dec19_asmcode[7:0] 8'01101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 + assign $1\dec19_asmcode[7:0] 8'00100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 + assign $1\dec19_asmcode[7:0] 8'00100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\dec19_asmcode[7:0] 8'00100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\dec19_asmcode[7:0] 8'00101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 - case - assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub20_sgn_ext $0\LDST_dec31_dec_sub20_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:10743.3-10767.6" - process $proc$issuer_ls180.v:10743$213 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub20_is_32b[0:0] $1\LDST_dec31_dec_sub20_is_32b[0:0] - attribute \src "issuer_ls180.v:10744.5-10744.29" - switch \initial - attribute \src "issuer_ls180.v:10744.9-10744.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $1\dec19_asmcode[7:0] 8'00101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 + assign $1\dec19_asmcode[7:0] 8'00101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 + assign $1\dec19_asmcode[7:0] 8'00101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 + assign $1\dec19_asmcode[7:0] 8'00101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 assign { } { } - assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\dec19_asmcode[7:0] 8'00010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 assign { } { } - assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\dec19_asmcode[7:0] 8'00010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'10010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\dec19_asmcode[7:0] 8'01001000 case - assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + assign $1\dec19_asmcode[7:0] 8'00000000 end sync always - update \LDST_dec31_dec_sub20_is_32b $0\LDST_dec31_dec_sub20_is_32b[0:0] + update \dec19_asmcode $0\dec19_asmcode[7:0] end - attribute \src "issuer_ls180.v:10768.3-10792.6" - process $proc$issuer_ls180.v:10768$214 + attribute \src "libresoc.v:7709.3-7760.6" + process $proc$libresoc.v:7709$275 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub20_sgn[0:0] $1\LDST_dec31_dec_sub20_sgn[0:0] - attribute \src "issuer_ls180.v:10769.5-10769.29" + assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0] + attribute \src "libresoc.v:7710.5-7710.29" switch \initial - attribute \src "issuer_ls180.v:10769.9-10769.17" + attribute \src "libresoc.v:7710.9-7710.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } - assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 - case - assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub20_sgn $0\LDST_dec31_dec_sub20_sgn[0:0] - end - attribute \src "issuer_ls180.v:10793.3-10817.6" - process $proc$issuer_ls180.v:10793$215 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub20_internal_op[6:0] $1\LDST_dec31_dec_sub20_internal_op[6:0] - attribute \src "issuer_ls180.v:10794.5-10794.29" - switch \initial - attribute \src "issuer_ls180.v:10794.9-10794.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 assign { } { } - assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 assign { } { } - assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100110 + assign $1\dec19_inv_a[0:0] 1'0 case - assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0000000 + assign $1\dec19_inv_a[0:0] 1'0 end sync always - update \LDST_dec31_dec_sub20_internal_op $0\LDST_dec31_dec_sub20_internal_op[6:0] + update \dec19_inv_a $0\dec19_inv_a[0:0] end - attribute \src "issuer_ls180.v:10818.3-10842.6" - process $proc$issuer_ls180.v:10818$216 + attribute \src "libresoc.v:7761.3-7812.6" + process $proc$libresoc.v:7761$276 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub20_in1_sel[2:0] $1\LDST_dec31_dec_sub20_in1_sel[2:0] - attribute \src "issuer_ls180.v:10819.5-10819.29" + assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0] + attribute \src "libresoc.v:7762.5-7762.29" switch \initial - attribute \src "issuer_ls180.v:10819.9-10819.17" + attribute \src "libresoc.v:7762.9-7762.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } - assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + assign $1\dec19_inv_out[0:0] 1'0 case - assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'000 + assign $1\dec19_inv_out[0:0] 1'0 end sync always - update \LDST_dec31_dec_sub20_in1_sel $0\LDST_dec31_dec_sub20_in1_sel[2:0] + update \dec19_inv_out $0\dec19_inv_out[0:0] end - attribute \src "issuer_ls180.v:10843.3-10867.6" - process $proc$issuer_ls180.v:10843$217 + attribute \src "libresoc.v:7813.3-7864.6" + process $proc$libresoc.v:7813$277 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub20_in2_sel[3:0] $1\LDST_dec31_dec_sub20_in2_sel[3:0] - attribute \src "issuer_ls180.v:10844.5-10844.29" + assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0] + attribute \src "libresoc.v:7814.5-7814.29" switch \initial - attribute \src "issuer_ls180.v:10844.9-10844.17" + attribute \src "libresoc.v:7814.9-7814.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } - assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + assign $1\dec19_cry_out[0:0] 1'0 case - assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0000 + assign $1\dec19_cry_out[0:0] 1'0 end sync always - update \LDST_dec31_dec_sub20_in2_sel $0\LDST_dec31_dec_sub20_in2_sel[3:0] + update \dec19_cry_out $0\dec19_cry_out[0:0] end - attribute \src "issuer_ls180.v:10868.3-10892.6" - process $proc$issuer_ls180.v:10868$218 + attribute \src "libresoc.v:7865.3-7916.6" + process $proc$libresoc.v:7865$278 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub20_cr_in[2:0] $1\LDST_dec31_dec_sub20_cr_in[2:0] - attribute \src "issuer_ls180.v:10869.5-10869.29" + assign $0\dec19_br[0:0] $1\dec19_br[0:0] + attribute \src "libresoc.v:7866.5-7866.29" switch \initial - attribute \src "issuer_ls180.v:10869.9-10869.17" + attribute \src "libresoc.v:7866.9-7866.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } - assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + assign $1\dec19_br[0:0] 1'0 case - assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + assign $1\dec19_br[0:0] 1'0 end sync always - update \LDST_dec31_dec_sub20_cr_in $0\LDST_dec31_dec_sub20_cr_in[2:0] + update \dec19_br $0\dec19_br[0:0] end - attribute \src "issuer_ls180.v:10893.3-10917.6" - process $proc$issuer_ls180.v:10893$219 + attribute \src "libresoc.v:7917.3-7968.6" + process $proc$libresoc.v:7917$279 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub20_cr_out[2:0] $1\LDST_dec31_dec_sub20_cr_out[2:0] - attribute \src "issuer_ls180.v:10894.5-10894.29" + assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:7918.5-7918.29" switch \initial - attribute \src "issuer_ls180.v:10894.9-10894.17" + attribute \src "libresoc.v:7918.9-7918.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } - assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + assign $1\dec19_sgn_ext[0:0] 1'0 case - assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + assign $1\dec19_sgn_ext[0:0] 1'0 end sync always - update \LDST_dec31_dec_sub20_cr_out $0\LDST_dec31_dec_sub20_cr_out[2:0] + update \dec19_sgn_ext $0\dec19_sgn_ext[0:0] end - attribute \src "issuer_ls180.v:10918.3-10942.6" - process $proc$issuer_ls180.v:10918$220 + attribute \src "libresoc.v:7969.3-8020.6" + process $proc$libresoc.v:7969$280 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub20_ldst_len[3:0] $1\LDST_dec31_dec_sub20_ldst_len[3:0] - attribute \src "issuer_ls180.v:10919.5-10919.29" + assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] + attribute \src "libresoc.v:7970.5-7970.29" switch \initial - attribute \src "issuer_ls180.v:10919.9-10919.17" + attribute \src "libresoc.v:7970.9-7970.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } - assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 + assign $1\dec19_internal_op[6:0] 7'0101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'1000 + assign $1\dec19_internal_op[6:0] 7'1000110 case - assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0000 + assign $1\dec19_internal_op[6:0] 7'0000000 end sync always - update \LDST_dec31_dec_sub20_ldst_len $0\LDST_dec31_dec_sub20_ldst_len[3:0] + update \dec19_internal_op $0\dec19_internal_op[6:0] end - attribute \src "issuer_ls180.v:10943.3-10967.6" - process $proc$issuer_ls180.v:10943$221 + attribute \src "libresoc.v:8021.3-8072.6" + process $proc$libresoc.v:8021$281 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub20_upd[1:0] $1\LDST_dec31_dec_sub20_upd[1:0] - attribute \src "issuer_ls180.v:10944.5-10944.29" + assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0] + attribute \src "libresoc.v:8022.5-8022.29" switch \initial - attribute \src "issuer_ls180.v:10944.9-10944.17" + attribute \src "libresoc.v:8022.9-8022.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } - assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + assign $1\dec19_rsrv[0:0] 1'0 case - assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + assign $1\dec19_rsrv[0:0] 1'0 end sync always - update \LDST_dec31_dec_sub20_upd $0\LDST_dec31_dec_sub20_upd[1:0] + update \dec19_rsrv $0\dec19_rsrv[0:0] end - attribute \src "issuer_ls180.v:10968.3-10992.6" - process $proc$issuer_ls180.v:10968$222 + attribute \src "libresoc.v:8073.3-8124.6" + process $proc$libresoc.v:8073$282 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub20_rc_sel[1:0] $1\LDST_dec31_dec_sub20_rc_sel[1:0] - attribute \src "issuer_ls180.v:10969.5-10969.29" + assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] + attribute \src "libresoc.v:8074.5-8074.29" switch \initial - attribute \src "issuer_ls180.v:10969.9-10969.17" + attribute \src "libresoc.v:8074.9-8074.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } - assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 - case - assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 - end - sync always - update \LDST_dec31_dec_sub20_rc_sel $0\LDST_dec31_dec_sub20_rc_sel[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:10998.1-11818.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub21" -attribute \generator "nMigen" -module \LDST_dec31_dec_sub21 - attribute \src "issuer_ls180.v:11229.3-11277.6" - wire $0\LDST_dec31_dec_sub21_br[0:0] - attribute \src "issuer_ls180.v:11572.3-11620.6" - wire width 3 $0\LDST_dec31_dec_sub21_cr_in[2:0] - attribute \src "issuer_ls180.v:11621.3-11669.6" - wire width 3 $0\LDST_dec31_dec_sub21_cr_out[2:0] - attribute \src "issuer_ls180.v:11180.3-11228.6" - wire width 12 $0\LDST_dec31_dec_sub21_function_unit[11:0] - attribute \src "issuer_ls180.v:11474.3-11522.6" - wire width 3 $0\LDST_dec31_dec_sub21_in1_sel[2:0] - attribute \src "issuer_ls180.v:11523.3-11571.6" - wire width 4 $0\LDST_dec31_dec_sub21_in2_sel[3:0] - attribute \src "issuer_ls180.v:11425.3-11473.6" - wire width 7 $0\LDST_dec31_dec_sub21_internal_op[6:0] - attribute \src "issuer_ls180.v:11327.3-11375.6" - wire $0\LDST_dec31_dec_sub21_is_32b[0:0] - attribute \src "issuer_ls180.v:11670.3-11718.6" - wire width 4 $0\LDST_dec31_dec_sub21_ldst_len[3:0] - attribute \src "issuer_ls180.v:11768.3-11816.6" - wire width 2 $0\LDST_dec31_dec_sub21_rc_sel[1:0] - attribute \src "issuer_ls180.v:11376.3-11424.6" - wire $0\LDST_dec31_dec_sub21_sgn[0:0] - attribute \src "issuer_ls180.v:11278.3-11326.6" - wire $0\LDST_dec31_dec_sub21_sgn_ext[0:0] - attribute \src "issuer_ls180.v:11719.3-11767.6" - wire width 2 $0\LDST_dec31_dec_sub21_upd[1:0] - attribute \src "issuer_ls180.v:10999.7-10999.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:11229.3-11277.6" - wire $1\LDST_dec31_dec_sub21_br[0:0] - attribute \src "issuer_ls180.v:11572.3-11620.6" - wire width 3 $1\LDST_dec31_dec_sub21_cr_in[2:0] - attribute \src "issuer_ls180.v:11621.3-11669.6" - wire width 3 $1\LDST_dec31_dec_sub21_cr_out[2:0] - attribute \src "issuer_ls180.v:11180.3-11228.6" - wire width 12 $1\LDST_dec31_dec_sub21_function_unit[11:0] - attribute \src "issuer_ls180.v:11474.3-11522.6" - wire width 3 $1\LDST_dec31_dec_sub21_in1_sel[2:0] - attribute \src "issuer_ls180.v:11523.3-11571.6" - wire width 4 $1\LDST_dec31_dec_sub21_in2_sel[3:0] - attribute \src "issuer_ls180.v:11425.3-11473.6" - wire width 7 $1\LDST_dec31_dec_sub21_internal_op[6:0] - attribute \src "issuer_ls180.v:11327.3-11375.6" - wire $1\LDST_dec31_dec_sub21_is_32b[0:0] - attribute \src "issuer_ls180.v:11670.3-11718.6" - wire width 4 $1\LDST_dec31_dec_sub21_ldst_len[3:0] - attribute \src "issuer_ls180.v:11768.3-11816.6" - wire width 2 $1\LDST_dec31_dec_sub21_rc_sel[1:0] - attribute \src "issuer_ls180.v:11376.3-11424.6" - wire $1\LDST_dec31_dec_sub21_sgn[0:0] - attribute \src "issuer_ls180.v:11278.3-11326.6" - wire $1\LDST_dec31_dec_sub21_sgn_ext[0:0] - attribute \src "issuer_ls180.v:11719.3-11767.6" - wire width 2 $1\LDST_dec31_dec_sub21_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \LDST_dec31_dec_sub21_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \LDST_dec31_dec_sub21_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 6 \LDST_dec31_dec_sub21_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \LDST_dec31_dec_sub21_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \LDST_dec31_dec_sub21_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 4 \LDST_dec31_dec_sub21_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \LDST_dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 12 \LDST_dec31_dec_sub21_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 7 \LDST_dec31_dec_sub21_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 9 \LDST_dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 13 \LDST_dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 11 \LDST_dec31_dec_sub21_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \LDST_dec31_dec_sub21_upd - attribute \src "issuer_ls180.v:10999.7-10999.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:10999.7-10999.20" - process $proc$issuer_ls180.v:10999$237 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:11180.3-11228.6" - process $proc$issuer_ls180.v:11180$224 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub21_function_unit[11:0] $1\LDST_dec31_dec_sub21_function_unit[11:0] - attribute \src "issuer_ls180.v:11181.5-11181.29" - switch \initial - attribute \src "issuer_ls180.v:11181.9-11181.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + assign $1\dec19_is_32b[0:0] 1'0 case - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000000 + assign $1\dec19_is_32b[0:0] 1'0 end sync always - update \LDST_dec31_dec_sub21_function_unit $0\LDST_dec31_dec_sub21_function_unit[11:0] + update \dec19_is_32b $0\dec19_is_32b[0:0] end - attribute \src "issuer_ls180.v:11229.3-11277.6" - process $proc$issuer_ls180.v:11229$225 + attribute \src "libresoc.v:8125.3-8176.6" + process $proc$libresoc.v:8125$283 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub21_br[0:0] $1\LDST_dec31_dec_sub21_br[0:0] - attribute \src "issuer_ls180.v:11230.5-11230.29" + assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0] + attribute \src "libresoc.v:8126.5-8126.29" switch \initial - attribute \src "issuer_ls180.v:11230.9-11230.17" + attribute \src "libresoc.v:8126.9-8126.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - case - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub21_br $0\LDST_dec31_dec_sub21_br[0:0] - end - attribute \src "issuer_ls180.v:11278.3-11326.6" - process $proc$issuer_ls180.v:11278$226 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub21_sgn_ext[0:0] $1\LDST_dec31_dec_sub21_sgn_ext[0:0] - attribute \src "issuer_ls180.v:11279.5-11279.29" - switch \initial - attribute \src "issuer_ls180.v:11279.9-11279.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + assign $1\dec19_sgn[0:0] 1'0 case - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + assign $1\dec19_sgn[0:0] 1'0 end sync always - update \LDST_dec31_dec_sub21_sgn_ext $0\LDST_dec31_dec_sub21_sgn_ext[0:0] + update \dec19_sgn $0\dec19_sgn[0:0] end - attribute \src "issuer_ls180.v:11327.3-11375.6" - process $proc$issuer_ls180.v:11327$227 + attribute \src "libresoc.v:8177.3-8228.6" + process $proc$libresoc.v:8177$284 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub21_is_32b[0:0] $1\LDST_dec31_dec_sub21_is_32b[0:0] - attribute \src "issuer_ls180.v:11328.5-11328.29" + assign $0\dec19_lk[0:0] $1\dec19_lk[0:0] + attribute \src "libresoc.v:8178.5-8178.29" switch \initial - attribute \src "issuer_ls180.v:11328.9-11328.17" + attribute \src "libresoc.v:8178.9-8178.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - case - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub21_is_32b $0\LDST_dec31_dec_sub21_is_32b[0:0] - end - attribute \src "issuer_ls180.v:11376.3-11424.6" - process $proc$issuer_ls180.v:11376$228 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub21_sgn[0:0] $1\LDST_dec31_dec_sub21_sgn[0:0] - attribute \src "issuer_ls180.v:11377.5-11377.29" - switch \initial - attribute \src "issuer_ls180.v:11377.9-11377.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 + assign $1\dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + assign $1\dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec19_lk[0:0] 1'0 case - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + assign $1\dec19_lk[0:0] 1'0 end sync always - update \LDST_dec31_dec_sub21_sgn $0\LDST_dec31_dec_sub21_sgn[0:0] + update \dec19_lk $0\dec19_lk[0:0] end - attribute \src "issuer_ls180.v:11425.3-11473.6" - process $proc$issuer_ls180.v:11425$229 + attribute \src "libresoc.v:8229.3-8280.6" + process $proc$libresoc.v:8229$285 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub21_internal_op[6:0] $1\LDST_dec31_dec_sub21_internal_op[6:0] - attribute \src "issuer_ls180.v:11426.5-11426.29" + assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:8230.5-8230.29" switch \initial - attribute \src "issuer_ls180.v:11426.9-11426.17" + attribute \src "libresoc.v:8230.9-8230.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\dec19_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + assign $1\dec19_sgl_pipe[0:0] 1'0 case - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0000000 + assign $1\dec19_sgl_pipe[0:0] 1'0 end sync always - update \LDST_dec31_dec_sub21_internal_op $0\LDST_dec31_dec_sub21_internal_op[6:0] + update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0] end - attribute \src "issuer_ls180.v:11474.3-11522.6" - process $proc$issuer_ls180.v:11474$230 + attribute \src "libresoc.v:8281.3-8332.6" + process $proc$libresoc.v:8281$286 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub21_in1_sel[2:0] $1\LDST_dec31_dec_sub21_in1_sel[2:0] - attribute \src "issuer_ls180.v:11475.5-11475.29" + assign $0\dec19_form[4:0] $1\dec19_form[4:0] + attribute \src "libresoc.v:8282.5-8282.29" switch \initial - attribute \src "issuer_ls180.v:11475.9-11475.17" + attribute \src "libresoc.v:8282.9-8282.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + assign $1\dec19_form[4:0] 5'01001 case - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'000 + assign $1\dec19_form[4:0] 5'00000 end sync always - update \LDST_dec31_dec_sub21_in1_sel $0\LDST_dec31_dec_sub21_in1_sel[2:0] + update \dec19_form $0\dec19_form[4:0] end - attribute \src "issuer_ls180.v:11523.3-11571.6" - process $proc$issuer_ls180.v:11523$231 + attribute \src "libresoc.v:8333.3-8384.6" + process $proc$libresoc.v:8333$287 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub21_in2_sel[3:0] $1\LDST_dec31_dec_sub21_in2_sel[3:0] - attribute \src "issuer_ls180.v:11524.5-11524.29" + assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0] + attribute \src "libresoc.v:8334.5-8334.29" switch \initial - attribute \src "issuer_ls180.v:11524.9-11524.17" + attribute \src "libresoc.v:8334.9-8334.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + assign $1\dec19_in1_sel[2:0] 3'011 case - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0000 + assign $1\dec19_in1_sel[2:0] 3'000 end sync always - update \LDST_dec31_dec_sub21_in2_sel $0\LDST_dec31_dec_sub21_in2_sel[3:0] + update \dec19_in1_sel $0\dec19_in1_sel[2:0] end - attribute \src "issuer_ls180.v:11572.3-11620.6" - process $proc$issuer_ls180.v:11572$232 + attribute \src "libresoc.v:8385.3-8436.6" + process $proc$libresoc.v:8385$288 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub21_cr_in[2:0] $1\LDST_dec31_dec_sub21_cr_in[2:0] - attribute \src "issuer_ls180.v:11573.5-11573.29" + assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0] + attribute \src "libresoc.v:8386.5-8386.29" switch \initial - attribute \src "issuer_ls180.v:11573.9-11573.17" + attribute \src "libresoc.v:8386.9-8386.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + assign $1\dec19_in2_sel[3:0] 4'1100 case - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + assign $1\dec19_in2_sel[3:0] 4'0000 end sync always - update \LDST_dec31_dec_sub21_cr_in $0\LDST_dec31_dec_sub21_cr_in[2:0] + update \dec19_in2_sel $0\dec19_in2_sel[3:0] end - attribute \src "issuer_ls180.v:11621.3-11669.6" - process $proc$issuer_ls180.v:11621$233 + attribute \src "libresoc.v:8437.3-8488.6" + process $proc$libresoc.v:8437$289 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub21_cr_out[2:0] $1\LDST_dec31_dec_sub21_cr_out[2:0] - attribute \src "issuer_ls180.v:11622.5-11622.29" + assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0] + attribute \src "libresoc.v:8438.5-8438.29" switch \initial - attribute \src "issuer_ls180.v:11622.9-11622.17" + attribute \src "libresoc.v:8438.9-8438.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + assign $1\dec19_in3_sel[1:0] 2'00 case - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + assign $1\dec19_in3_sel[1:0] 2'00 end sync always - update \LDST_dec31_dec_sub21_cr_out $0\LDST_dec31_dec_sub21_cr_out[2:0] + update \dec19_in3_sel $0\dec19_in3_sel[1:0] end - attribute \src "issuer_ls180.v:11670.3-11718.6" - process $proc$issuer_ls180.v:11670$234 + attribute \src "libresoc.v:8489.3-8540.6" + process $proc$libresoc.v:8489$290 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub21_ldst_len[3:0] $1\LDST_dec31_dec_sub21_ldst_len[3:0] - attribute \src "issuer_ls180.v:11671.5-11671.29" + assign $0\dec19_out_sel[1:0] $1\dec19_out_sel[1:0] + attribute \src "libresoc.v:8490.5-8490.29" switch \initial - attribute \src "issuer_ls180.v:11671.9-11671.17" + attribute \src "libresoc.v:8490.9-8490.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 + assign $1\dec19_out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + assign $1\dec19_out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\dec19_out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 + assign $1\dec19_out_sel[1:0] 2'00 case - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0000 + assign $1\dec19_out_sel[1:0] 2'00 end sync always - update \LDST_dec31_dec_sub21_ldst_len $0\LDST_dec31_dec_sub21_ldst_len[3:0] + update \dec19_out_sel $0\dec19_out_sel[1:0] end - attribute \src "issuer_ls180.v:11719.3-11767.6" - process $proc$issuer_ls180.v:11719$235 + attribute \src "libresoc.v:8541.3-8592.6" + process $proc$libresoc.v:8541$291 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub21_upd[1:0] $1\LDST_dec31_dec_sub21_upd[1:0] - attribute \src "issuer_ls180.v:11720.5-11720.29" + assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0] + attribute \src "libresoc.v:8542.5-8542.29" switch \initial - attribute \src "issuer_ls180.v:11720.9-11720.17" + attribute \src "libresoc.v:8542.9-8542.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 + assign $1\dec19_cr_in[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\dec19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + assign $1\dec19_cr_in[2:0] 3'000 case - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 + assign $1\dec19_cr_in[2:0] 3'000 end sync always - update \LDST_dec31_dec_sub21_upd $0\LDST_dec31_dec_sub21_upd[1:0] + update \dec19_cr_in $0\dec19_cr_in[2:0] end - attribute \src "issuer_ls180.v:11768.3-11816.6" - process $proc$issuer_ls180.v:11768$236 + attribute \src "libresoc.v:8593.3-8644.6" + process $proc$libresoc.v:8593$292 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub21_rc_sel[1:0] $1\LDST_dec31_dec_sub21_rc_sel[1:0] - attribute \src "issuer_ls180.v:11769.5-11769.29" + assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0] + attribute \src "libresoc.v:8594.5-8594.29" switch \initial - attribute \src "issuer_ls180.v:11769.9-11769.17" + attribute \src "libresoc.v:8594.9-8594.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 + assign $1\dec19_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + assign $1\dec19_cr_out[2:0] 3'000 case - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + assign $1\dec19_cr_out[2:0] 3'000 end sync always - update \LDST_dec31_dec_sub21_rc_sel $0\LDST_dec31_dec_sub21_rc_sel[1:0] + update \dec19_cr_out $0\dec19_cr_out[2:0] end - connect \opcode_switch \opcode_in [10:6] + connect \opcode_switch \opcode_in [10:1] end -attribute \src "issuer_ls180.v:11822.1-12447.10" +attribute \src "libresoc.v:8650.1-10539.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub22" +attribute \nmigen.hierarchy "test_issuer.dec2" attribute \generator "nMigen" -module \LDST_dec31_dec_sub22 - attribute \src "issuer_ls180.v:12038.3-12071.6" - wire $0\LDST_dec31_dec_sub22_br[0:0] - attribute \src "issuer_ls180.v:12276.3-12309.6" - wire width 3 $0\LDST_dec31_dec_sub22_cr_in[2:0] - attribute \src "issuer_ls180.v:12310.3-12343.6" - wire width 3 $0\LDST_dec31_dec_sub22_cr_out[2:0] - attribute \src "issuer_ls180.v:12004.3-12037.6" - wire width 12 $0\LDST_dec31_dec_sub22_function_unit[11:0] - attribute \src "issuer_ls180.v:12208.3-12241.6" - wire width 3 $0\LDST_dec31_dec_sub22_in1_sel[2:0] - attribute \src "issuer_ls180.v:12242.3-12275.6" - wire width 4 $0\LDST_dec31_dec_sub22_in2_sel[3:0] - attribute \src "issuer_ls180.v:12174.3-12207.6" - wire width 7 $0\LDST_dec31_dec_sub22_internal_op[6:0] - attribute \src "issuer_ls180.v:12106.3-12139.6" - wire $0\LDST_dec31_dec_sub22_is_32b[0:0] - attribute \src "issuer_ls180.v:12344.3-12377.6" - wire width 4 $0\LDST_dec31_dec_sub22_ldst_len[3:0] - attribute \src "issuer_ls180.v:12412.3-12445.6" - wire width 2 $0\LDST_dec31_dec_sub22_rc_sel[1:0] - attribute \src "issuer_ls180.v:12140.3-12173.6" - wire $0\LDST_dec31_dec_sub22_sgn[0:0] - attribute \src "issuer_ls180.v:12072.3-12105.6" - wire $0\LDST_dec31_dec_sub22_sgn_ext[0:0] - attribute \src "issuer_ls180.v:12378.3-12411.6" - wire width 2 $0\LDST_dec31_dec_sub22_upd[1:0] - attribute \src "issuer_ls180.v:11823.7-11823.20" +module \dec2 + attribute \src "libresoc.v:10405.3-10486.6" + wire width 8 $0\asmcode[7:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 64 $0\cia[63:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 3 $0\cr_in1[2:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $0\cr_in1_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 3 $0\cr_in2$1[2:0]$312 + attribute \src "libresoc.v:10405.3-10486.6" + wire width 3 $0\cr_in2[2:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $0\cr_in2_ok$2[0:0]$313 + attribute \src "libresoc.v:10405.3-10486.6" + wire $0\cr_in2_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 3 $0\cr_out[2:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $0\cr_out_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 8 $0\cr_rd[7:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $0\cr_rd_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 8 $0\cr_wr[7:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $0\cr_wr_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 5 $0\ea[4:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $0\ea_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 3 $0\fast1[2:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 3 $0\fast2[2:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 3 $0\fasto1[2:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $0\fasto1_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 3 $0\fasto2[2:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $0\fasto2_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 12 $0\fn_unit[11:0] + attribute \src "libresoc.v:8651.7-8651.20" wire $0\initial[0:0] - attribute \src "issuer_ls180.v:12038.3-12071.6" - wire $1\LDST_dec31_dec_sub22_br[0:0] - attribute \src "issuer_ls180.v:12276.3-12309.6" - wire width 3 $1\LDST_dec31_dec_sub22_cr_in[2:0] - attribute \src "issuer_ls180.v:12310.3-12343.6" - wire width 3 $1\LDST_dec31_dec_sub22_cr_out[2:0] - attribute \src "issuer_ls180.v:12004.3-12037.6" - wire width 12 $1\LDST_dec31_dec_sub22_function_unit[11:0] - attribute \src "issuer_ls180.v:12208.3-12241.6" - wire width 3 $1\LDST_dec31_dec_sub22_in1_sel[2:0] - attribute \src "issuer_ls180.v:12242.3-12275.6" - wire width 4 $1\LDST_dec31_dec_sub22_in2_sel[3:0] - attribute \src "issuer_ls180.v:12174.3-12207.6" - wire width 7 $1\LDST_dec31_dec_sub22_internal_op[6:0] - attribute \src "issuer_ls180.v:12106.3-12139.6" - wire $1\LDST_dec31_dec_sub22_is_32b[0:0] - attribute \src "issuer_ls180.v:12344.3-12377.6" - wire width 4 $1\LDST_dec31_dec_sub22_ldst_len[3:0] - attribute \src "issuer_ls180.v:12412.3-12445.6" - wire width 2 $1\LDST_dec31_dec_sub22_rc_sel[1:0] - attribute \src "issuer_ls180.v:12140.3-12173.6" - wire $1\LDST_dec31_dec_sub22_sgn[0:0] - attribute \src "issuer_ls180.v:12072.3-12105.6" - wire $1\LDST_dec31_dec_sub22_sgn_ext[0:0] - attribute \src "issuer_ls180.v:12378.3-12411.6" - wire width 2 $1\LDST_dec31_dec_sub22_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \LDST_dec31_dec_sub22_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \LDST_dec31_dec_sub22_cr_in - attribute \enum_base_type "CROutSel" + attribute \src "libresoc.v:10405.3-10486.6" + wire width 2 $0\input_carry[1:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 32 $0\insn[31:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 7 $0\insn_type[6:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $0\is_32bit[0:0] + attribute \src "libresoc.v:10385.3-10404.6" + wire $0\is_priv_insn[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $0\lk[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 64 $0\msr[63:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 5 $0\reg1[4:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $0\reg1_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 5 $0\reg2[4:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $0\reg2_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 5 $0\reg3[4:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $0\reg3_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 5 $0\rego[4:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $0\rego_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 10 $0\spr1[9:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $0\spr1_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 10 $0\spro[9:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $0\spro_ok[0:0] + attribute \src "libresoc.v:10339.3-10348.6" + wire $0\tmp_tmp_lk[0:0] + attribute \src "libresoc.v:10375.3-10384.6" + wire width 13 $0\tmp_tmp_trapaddr[12:0] + attribute \src "libresoc.v:10349.3-10364.6" + wire width 3 $0\tmp_xer_in[2:0] + attribute \src "libresoc.v:10365.3-10374.6" + wire $0\tmp_xer_out[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 13 $0\trapaddr[12:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 7 $0\traptype[6:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 3 $0\xer_in[2:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $0\xer_out[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 8 $1\asmcode[7:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 64 $1\cia[63:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 3 $1\cr_in1[2:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $1\cr_in1_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 3 $1\cr_in2$1[2:0]$314 + attribute \src "libresoc.v:10405.3-10486.6" + wire width 3 $1\cr_in2[2:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $1\cr_in2_ok$2[0:0]$315 + attribute \src "libresoc.v:10405.3-10486.6" + wire $1\cr_in2_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 3 $1\cr_out[2:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $1\cr_out_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 8 $1\cr_rd[7:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $1\cr_rd_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 8 $1\cr_wr[7:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $1\cr_wr_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 5 $1\ea[4:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $1\ea_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 3 $1\fast1[2:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 3 $1\fast2[2:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $1\fast2_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 3 $1\fasto1[2:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $1\fasto1_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 3 $1\fasto2[2:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $1\fasto2_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 12 $1\fn_unit[11:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 2 $1\input_carry[1:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 32 $1\insn[31:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 7 $1\insn_type[6:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $1\is_32bit[0:0] + attribute \src "libresoc.v:10385.3-10404.6" + wire $1\is_priv_insn[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $1\lk[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 64 $1\msr[63:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $1\rc_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 5 $1\reg1[4:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $1\reg1_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 5 $1\reg2[4:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $1\reg2_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 5 $1\reg3[4:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $1\reg3_ok[0:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire width 5 $1\rego[4:0] + attribute \src "libresoc.v:10405.3-10486.6" + wire $1\rego_ok[0:0] + attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_cr_in_cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_cr_in_cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_in_cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_cr_in_cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_in_cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_in_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \dec_cr_in_cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_in_cr_fxm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 3 \dec_cr_in_sel_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_cr_out_cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \dec_cr_out_cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_out_cr_fxm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 3 \dec_cr_out_sel_in + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_cry_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \LDST_dec31_dec_sub22_function_unit + wire width 12 \dec_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -16901,7 +13838,7 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \LDST_dec31_dec_sub22_in1_sel + wire width 3 \dec_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -16918,7 +13855,13 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 4 \LDST_dec31_dec_sub22_in2_sel + wire width 4 \dec_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -16994,844 +13937,217 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \LDST_dec31_dec_sub22_internal_op + wire width 7 \dec_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:885" + wire \dec_irq_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 12 \LDST_dec31_dec_sub22_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" + wire \dec_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_o2_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_o2_fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363" + wire \dec_o2_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec_o2_reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_o2_reg_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_o_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_o_fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec_o_reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_o_reg_o_ok + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308" + wire width 2 \dec_o_sel_in + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \dec_o_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_o_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec_opcode_in + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 7 \LDST_dec31_dec_sub22_ldst_len + wire width 2 \dec_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 9 \LDST_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 13 \LDST_dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 11 \LDST_dec31_dec_sub22_sgn_ext + wire width 2 \dec_rc_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 2 \dec_rc_sel_in attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \LDST_dec31_dec_sub22_upd - attribute \src "issuer_ls180.v:11823.7-11823.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:11823.7-11823.20" - process $proc$issuer_ls180.v:11823$251 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:12004.3-12037.6" - process $proc$issuer_ls180.v:12004$238 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_function_unit[11:0] $1\LDST_dec31_dec_sub22_function_unit[11:0] - attribute \src "issuer_ls180.v:12005.5-12005.29" - switch \initial - attribute \src "issuer_ls180.v:12005.9-12005.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 - case - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000000 - end - sync always - update \LDST_dec31_dec_sub22_function_unit $0\LDST_dec31_dec_sub22_function_unit[11:0] - end - attribute \src "issuer_ls180.v:12038.3-12071.6" - process $proc$issuer_ls180.v:12038$239 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_br[0:0] $1\LDST_dec31_dec_sub22_br[0:0] - attribute \src "issuer_ls180.v:12039.5-12039.29" - switch \initial - attribute \src "issuer_ls180.v:12039.9-12039.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 - case - assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub22_br $0\LDST_dec31_dec_sub22_br[0:0] - end - attribute \src "issuer_ls180.v:12072.3-12105.6" - process $proc$issuer_ls180.v:12072$240 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_sgn_ext[0:0] $1\LDST_dec31_dec_sub22_sgn_ext[0:0] - attribute \src "issuer_ls180.v:12073.5-12073.29" - switch \initial - attribute \src "issuer_ls180.v:12073.9-12073.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 - case - assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub22_sgn_ext $0\LDST_dec31_dec_sub22_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:12106.3-12139.6" - process $proc$issuer_ls180.v:12106$241 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_is_32b[0:0] $1\LDST_dec31_dec_sub22_is_32b[0:0] - attribute \src "issuer_ls180.v:12107.5-12107.29" - switch \initial - attribute \src "issuer_ls180.v:12107.9-12107.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 - case - assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub22_is_32b $0\LDST_dec31_dec_sub22_is_32b[0:0] - end - attribute \src "issuer_ls180.v:12140.3-12173.6" - process $proc$issuer_ls180.v:12140$242 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_sgn[0:0] $1\LDST_dec31_dec_sub22_sgn[0:0] - attribute \src "issuer_ls180.v:12141.5-12141.29" - switch \initial - attribute \src "issuer_ls180.v:12141.9-12141.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 - case - assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub22_sgn $0\LDST_dec31_dec_sub22_sgn[0:0] - end - attribute \src "issuer_ls180.v:12174.3-12207.6" - process $proc$issuer_ls180.v:12174$243 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_internal_op[6:0] $1\LDST_dec31_dec_sub22_internal_op[6:0] - attribute \src "issuer_ls180.v:12175.5-12175.29" - switch \initial - attribute \src "issuer_ls180.v:12175.9-12175.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0011100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 - case - assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0000000 - end - sync always - update \LDST_dec31_dec_sub22_internal_op $0\LDST_dec31_dec_sub22_internal_op[6:0] - end - attribute \src "issuer_ls180.v:12208.3-12241.6" - process $proc$issuer_ls180.v:12208$244 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_in1_sel[2:0] $1\LDST_dec31_dec_sub22_in1_sel[2:0] - attribute \src "issuer_ls180.v:12209.5-12209.29" - switch \initial - attribute \src "issuer_ls180.v:12209.9-12209.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 - case - assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'000 - end - sync always - update \LDST_dec31_dec_sub22_in1_sel $0\LDST_dec31_dec_sub22_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:12242.3-12275.6" - process $proc$issuer_ls180.v:12242$245 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_in2_sel[3:0] $1\LDST_dec31_dec_sub22_in2_sel[3:0] - attribute \src "issuer_ls180.v:12243.5-12243.29" - switch \initial - attribute \src "issuer_ls180.v:12243.9-12243.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 - case - assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0000 - end - sync always - update \LDST_dec31_dec_sub22_in2_sel $0\LDST_dec31_dec_sub22_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:12276.3-12309.6" - process $proc$issuer_ls180.v:12276$246 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_cr_in[2:0] $1\LDST_dec31_dec_sub22_cr_in[2:0] - attribute \src "issuer_ls180.v:12277.5-12277.29" - switch \initial - attribute \src "issuer_ls180.v:12277.9-12277.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 - case - assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 - end - sync always - update \LDST_dec31_dec_sub22_cr_in $0\LDST_dec31_dec_sub22_cr_in[2:0] - end - attribute \src "issuer_ls180.v:12310.3-12343.6" - process $proc$issuer_ls180.v:12310$247 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_cr_out[2:0] $1\LDST_dec31_dec_sub22_cr_out[2:0] - attribute \src "issuer_ls180.v:12311.5-12311.29" - switch \initial - attribute \src "issuer_ls180.v:12311.9-12311.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 - case - assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 - end - sync always - update \LDST_dec31_dec_sub22_cr_out $0\LDST_dec31_dec_sub22_cr_out[2:0] - end - attribute \src "issuer_ls180.v:12344.3-12377.6" - process $proc$issuer_ls180.v:12344$248 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_ldst_len[3:0] $1\LDST_dec31_dec_sub22_ldst_len[3:0] - attribute \src "issuer_ls180.v:12345.5-12345.29" - switch \initial - attribute \src "issuer_ls180.v:12345.9-12345.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0100 - case - assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0000 - end - sync always - update \LDST_dec31_dec_sub22_ldst_len $0\LDST_dec31_dec_sub22_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:12378.3-12411.6" - process $proc$issuer_ls180.v:12378$249 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_upd[1:0] $1\LDST_dec31_dec_sub22_upd[1:0] - attribute \src "issuer_ls180.v:12379.5-12379.29" - switch \initial - attribute \src "issuer_ls180.v:12379.9-12379.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 - case - assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 - end - sync always - update \LDST_dec31_dec_sub22_upd $0\LDST_dec31_dec_sub22_upd[1:0] - end - attribute \src "issuer_ls180.v:12412.3-12445.6" - process $proc$issuer_ls180.v:12412$250 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_rc_sel[1:0] $1\LDST_dec31_dec_sub22_rc_sel[1:0] - attribute \src "issuer_ls180.v:12413.5-12413.29" - switch \initial - attribute \src "issuer_ls180.v:12413.9-12413.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 - case - assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 - end - sync always - update \LDST_dec31_dec_sub22_rc_sel $0\LDST_dec31_dec_sub22_rc_sel[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:12451.1-13271.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub23" -attribute \generator "nMigen" -module \LDST_dec31_dec_sub23 - attribute \src "issuer_ls180.v:12682.3-12730.6" - wire $0\LDST_dec31_dec_sub23_br[0:0] - attribute \src "issuer_ls180.v:13025.3-13073.6" - wire width 3 $0\LDST_dec31_dec_sub23_cr_in[2:0] - attribute \src "issuer_ls180.v:13074.3-13122.6" - wire width 3 $0\LDST_dec31_dec_sub23_cr_out[2:0] - attribute \src "issuer_ls180.v:12633.3-12681.6" - wire width 12 $0\LDST_dec31_dec_sub23_function_unit[11:0] - attribute \src "issuer_ls180.v:12927.3-12975.6" - wire width 3 $0\LDST_dec31_dec_sub23_in1_sel[2:0] - attribute \src "issuer_ls180.v:12976.3-13024.6" - wire width 4 $0\LDST_dec31_dec_sub23_in2_sel[3:0] - attribute \src "issuer_ls180.v:12878.3-12926.6" - wire width 7 $0\LDST_dec31_dec_sub23_internal_op[6:0] - attribute \src "issuer_ls180.v:12780.3-12828.6" - wire $0\LDST_dec31_dec_sub23_is_32b[0:0] - attribute \src "issuer_ls180.v:13123.3-13171.6" - wire width 4 $0\LDST_dec31_dec_sub23_ldst_len[3:0] - attribute \src "issuer_ls180.v:13221.3-13269.6" - wire width 2 $0\LDST_dec31_dec_sub23_rc_sel[1:0] - attribute \src "issuer_ls180.v:12829.3-12877.6" - wire $0\LDST_dec31_dec_sub23_sgn[0:0] - attribute \src "issuer_ls180.v:12731.3-12779.6" - wire $0\LDST_dec31_dec_sub23_sgn_ext[0:0] - attribute \src "issuer_ls180.v:13172.3-13220.6" - wire width 2 $0\LDST_dec31_dec_sub23_upd[1:0] - attribute \src "issuer_ls180.v:12452.7-12452.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:12682.3-12730.6" - wire $1\LDST_dec31_dec_sub23_br[0:0] - attribute \src "issuer_ls180.v:13025.3-13073.6" - wire width 3 $1\LDST_dec31_dec_sub23_cr_in[2:0] - attribute \src "issuer_ls180.v:13074.3-13122.6" - wire width 3 $1\LDST_dec31_dec_sub23_cr_out[2:0] - attribute \src "issuer_ls180.v:12633.3-12681.6" - wire width 12 $1\LDST_dec31_dec_sub23_function_unit[11:0] - attribute \src "issuer_ls180.v:12927.3-12975.6" - wire width 3 $1\LDST_dec31_dec_sub23_in1_sel[2:0] - attribute \src "issuer_ls180.v:12976.3-13024.6" - wire width 4 $1\LDST_dec31_dec_sub23_in2_sel[3:0] - attribute \src "issuer_ls180.v:12878.3-12926.6" - wire width 7 $1\LDST_dec31_dec_sub23_internal_op[6:0] - attribute \src "issuer_ls180.v:12780.3-12828.6" - wire $1\LDST_dec31_dec_sub23_is_32b[0:0] - attribute \src "issuer_ls180.v:13123.3-13171.6" - wire width 4 $1\LDST_dec31_dec_sub23_ldst_len[3:0] - attribute \src "issuer_ls180.v:13221.3-13269.6" - wire width 2 $1\LDST_dec31_dec_sub23_rc_sel[1:0] - attribute \src "issuer_ls180.v:12829.3-12877.6" - wire $1\LDST_dec31_dec_sub23_sgn[0:0] - attribute \src "issuer_ls180.v:12731.3-12779.6" - wire $1\LDST_dec31_dec_sub23_sgn_ext[0:0] - attribute \src "issuer_ls180.v:13172.3-13220.6" - wire width 2 $1\LDST_dec31_dec_sub23_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \LDST_dec31_dec_sub23_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \LDST_dec31_dec_sub23_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 6 \LDST_dec31_dec_sub23_cr_out + wire width 2 \dec_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 8 \ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 9 \ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:884" + wire \ext_irq_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 22 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 23 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 24 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 25 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 26 \fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 27 \fasto1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 28 \fasto2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 29 \fasto2_ok attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -17845,33 +14161,34 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \LDST_dec31_dec_sub23_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \LDST_dec31_dec_sub23_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 4 \LDST_dec31_dec_sub23_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 12 output 42 \fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:887" + wire \illeg_ok + attribute \src "libresoc.v:8651.7-8651.15" + wire \initial + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + wire width 2 output 48 \input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + wire width 32 output 40 \insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364" + wire width 32 \insn_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443" + wire width 32 \insn_in$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" + wire width 32 \insn_in$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + wire width 32 \insn_in$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" + wire width 32 \insn_in$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" + wire width 32 \insn_in$9 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -17946,1087 +14263,1824 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \LDST_dec31_dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 12 \LDST_dec31_dec_sub23_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 7 \LDST_dec31_dec_sub23_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 9 \LDST_dec31_dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 13 \LDST_dec31_dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 11 \LDST_dec31_dec_sub23_sgn_ext - attribute \enum_base_type "LDSTMode" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 7 output 41 \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire output 55 \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:41" + wire \is_priv_insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire output 43 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + wire width 64 output 38 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 46 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 47 \oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" + wire \priv_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 4 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 44 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 45 \rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 10 \reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 11 \reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 12 \reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 13 \reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 14 \reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 15 \reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 6 \rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 7 \rego_ok + attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \LDST_dec31_dec_sub23_upd - attribute \src "issuer_ls180.v:12452.7-12452.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:12452.7-12452.20" - process $proc$issuer_ls180.v:12452$265 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:12633.3-12681.6" - process $proc$issuer_ls180.v:12633$252 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub23_function_unit[11:0] $1\LDST_dec31_dec_sub23_function_unit[11:0] - attribute \src "issuer_ls180.v:12634.5-12634.29" - switch \initial - attribute \src "issuer_ls180.v:12634.9-12634.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - case - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000000 - end - sync always - update \LDST_dec31_dec_sub23_function_unit $0\LDST_dec31_dec_sub23_function_unit[11:0] + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:362" + wire width 2 \sel_in + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 output 18 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 19 \spr1_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 output 16 \spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 17 \spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" + wire width 8 \tmp_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_cr_in1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_cr_in1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_cr_in2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_cr_in2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_cr_in2_ok$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_cr_out_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \tmp_ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_fasto1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_fasto2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_fasto2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \tmp_reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \tmp_reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \tmp_reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \tmp_rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_rego_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \tmp_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_spr1_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \tmp_spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 \tmp_tmp_cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \tmp_tmp_cr_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_tmp_cr_rd_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \tmp_tmp_cr_wr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_tmp_cr_wr_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 12 \tmp_tmp_fn_unit + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + wire width 2 \tmp_tmp_input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + wire width 32 \tmp_tmp_insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 7 \tmp_tmp_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire \tmp_tmp_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire \tmp_tmp_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + wire width 64 \tmp_tmp_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_tmp_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_tmp_oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_tmp_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_tmp_rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 13 \tmp_tmp_trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 7 \tmp_tmp_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + wire width 3 \tmp_xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" + wire \tmp_xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 13 output 50 \trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 7 output 49 \traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + wire width 3 output 20 \xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" + wire output 21 \xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:889" + cell $and $and$libresoc.v:10190$298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cur_eint + connect \B \cur_msr [15] + connect \Y $and$libresoc.v:10190$298_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:890" + cell $and $and$libresoc.v:10191$299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cur_dec [63] + connect \B \cur_msr [15] + connect \Y $and$libresoc.v:10191$299_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:891" + cell $and $and$libresoc.v:10192$300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_priv_insn + connect \B \cur_msr [14] + connect \Y $and$libresoc.v:10192$300_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:859" + cell $eq $eq$libresoc.v:10186$294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:10186$294_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:861" + cell $eq $eq$libresoc.v:10187$295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0001010 + connect \Y $eq$libresoc.v:10187$295_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:863" + cell $eq $eq$libresoc.v:10188$296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:10188$296_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:867" + cell $eq $eq$libresoc.v:10189$297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0111111 + connect \Y $eq$libresoc.v:10189$297_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:892" + cell $eq $eq$libresoc.v:10193$301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0000000 + connect \Y $eq$libresoc.v:10193$301_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:923" + cell $eq $eq$libresoc.v:10194$302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'0111111 + connect \Y $eq$libresoc.v:10194$302_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:924" + cell $eq $eq$libresoc.v:10195$303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1001001 + connect \Y $eq$libresoc.v:10195$303_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:933" + cell $eq $eq$libresoc.v:10197$305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1000110 + connect \Y $eq$libresoc.v:10197$305_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:924" + cell $or $or$libresoc.v:10196$304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$29 + connect \B \$31 + connect \Y $or$libresoc.v:10196$304_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10198.7-10235.4" + cell \dec \dec + connect \BA \dec_BA + connect \BB \dec_BB + connect \BC \dec_BC + connect \BI \dec_BI + connect \BO \dec_BO + connect \BT \dec_BT + connect \FXM \dec_FXM + connect \LK \dec_LK + connect \OE \dec_OE + connect \RA \dec_RA + connect \RB \dec_RB + connect \RS \dec_RS + connect \RT \dec_RT + connect \Rc \dec_Rc + connect \SPR \dec_SPR + connect \XL_BT \dec_XL_BT + connect \XL_XO \dec_XL_XO + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \asmcode \dec_asmcode + connect \bigendian \bigendian + connect \cr_in \dec_cr_in + connect \cr_out \dec_cr_out + connect \cry_in \dec_cry_in + connect \function_unit \dec_function_unit + connect \in1_sel \dec_in1_sel + connect \in2_sel \dec_in2_sel + connect \in3_sel \dec_in3_sel + connect \internal_op \dec_internal_op + connect \is_32b \dec_is_32b + connect \lk \dec_lk + connect \opcode_in \dec_opcode_in + connect \out_sel \dec_out_sel + connect \raw_opcode_in \raw_opcode_in + connect \rc_sel \dec_rc_sel + connect \upd \dec_upd + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10236.9-10250.4" + cell \dec_a \dec_a + connect \BO \dec_BO + connect \RA \dec_RA + connect \RS \dec_RS + connect \SPR \dec_SPR + connect \XL_XO \dec_XL_XO + connect \fast_a \dec_a_fast_a + connect \fast_a_ok \dec_a_fast_a_ok + connect \internal_op \dec_internal_op + connect \reg_a \dec_a_reg_a + connect \reg_a_ok \dec_a_reg_a_ok + connect \sel_in \dec_a_sel_in + connect \spr_a \dec_a_spr_a + connect \spr_a_ok \dec_a_spr_a_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10251.9-10261.4" + cell \dec_b \dec_b + connect \RB \dec_RB + connect \RS \dec_RS + connect \XL_XO \dec_XL_XO + connect \fast_b \dec_b_fast_b + connect \fast_b_ok \dec_b_fast_b_ok + connect \internal_op \dec_internal_op + connect \reg_b \dec_b_reg_b + connect \reg_b_ok \dec_b_reg_b_ok + connect \sel_in \dec_b_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10262.9-10268.4" + cell \dec_c \dec_c + connect \RB \dec_RB + connect \RS \dec_RS + connect \reg_c \dec_c_reg_c + connect \reg_c_ok \dec_c_reg_c_ok + connect \sel_in \dec_c_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10269.13-10288.4" + cell \dec_cr_in \dec_cr_in$3 + connect \BA \dec_BA + connect \BB \dec_BB + connect \BC \dec_BC + connect \BI \dec_BI + connect \BT \dec_BT + connect \FXM \dec_FXM + connect \X_BFA \dec_X_BFA + connect \cr_bitfield \dec_cr_in_cr_bitfield + connect \cr_bitfield_b \dec_cr_in_cr_bitfield_b + connect \cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b_ok + connect \cr_bitfield_o \dec_cr_in_cr_bitfield_o + connect \cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o_ok + connect \cr_bitfield_ok \dec_cr_in_cr_bitfield_ok + connect \cr_fxm \dec_cr_in_cr_fxm + connect \cr_fxm_ok \dec_cr_in_cr_fxm_ok + connect \insn_in \dec_cr_in_insn_in + connect \internal_op \dec_internal_op + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10289.14-10301.4" + cell \dec_cr_out \dec_cr_out$4 + connect \FXM \dec_FXM + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield \dec_cr_out_cr_bitfield + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \cr_fxm \dec_cr_out_cr_fxm + connect \cr_fxm_ok \dec_cr_out_cr_fxm_ok + connect \insn_in \dec_cr_out_insn_in + connect \internal_op \dec_internal_op + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10302.9-10315.4" + cell \dec_o \dec_o + connect \BO \dec_BO + connect \RA \dec_RA + connect \RT \dec_RT + connect \SPR \dec_SPR + connect \fast_o \dec_o_fast_o + connect \fast_o_ok \dec_o_fast_o_ok + connect \internal_op \dec_internal_op + connect \reg_o \dec_o_reg_o + connect \reg_o_ok \dec_o_reg_o_ok + connect \sel_in \dec_o_sel_in + connect \spr_o \dec_o_spr_o + connect \spr_o_ok \dec_o_spr_o_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10316.10-10325.4" + cell \dec_o2 \dec_o2 + connect \RA \dec_RA + connect \fast_o \dec_o2_fast_o + connect \fast_o_ok \dec_o2_fast_o_ok + connect \internal_op \dec_internal_op + connect \lk \dec_o2_lk + connect \reg_o \dec_o2_reg_o + connect \reg_o_ok \dec_o2_reg_o_ok + connect \upd \dec_upd + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10326.10-10332.4" + cell \dec_oe \dec_oe + connect \OE \dec_OE + connect \internal_op \dec_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10333.10-10338.4" + cell \dec_rc \dec_rc + connect \Rc \dec_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in end - attribute \src "issuer_ls180.v:12682.3-12730.6" - process $proc$issuer_ls180.v:12682$253 + attribute \src "libresoc.v:10339.3-10348.6" + process $proc$libresoc.v:10339$306 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub23_br[0:0] $1\LDST_dec31_dec_sub23_br[0:0] - attribute \src "issuer_ls180.v:12683.5-12683.29" + assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0] + attribute \src "libresoc.v:10340.5-10340.29" switch \initial - attribute \src "issuer_ls180.v:12683.9-12683.17" + attribute \src "libresoc.v:10340.9-10340.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:758" + switch \dec_lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + assign $1\tmp_tmp_lk[0:0] \dec_LK case - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + assign $1\tmp_tmp_lk[0:0] 1'0 end sync always - update \LDST_dec31_dec_sub23_br $0\LDST_dec31_dec_sub23_br[0:0] + update \tmp_tmp_lk $0\tmp_tmp_lk[0:0] end - attribute \src "issuer_ls180.v:12731.3-12779.6" - process $proc$issuer_ls180.v:12731$254 + attribute \src "libresoc.v:10349.3-10364.6" + process $proc$libresoc.v:10349$307 + assign { } { } assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub23_sgn_ext[0:0] $1\LDST_dec31_dec_sub23_sgn_ext[0:0] - attribute \src "issuer_ls180.v:12732.5-12732.29" + assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0] + attribute \src "libresoc.v:10350.5-10350.29" switch \initial - attribute \src "issuer_ls180.v:12732.9-12732.17" + attribute \src "libresoc.v:10350.9-10350.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:859" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + assign $1\tmp_xer_in[2:0] 3'111 + case + assign $1\tmp_xer_in[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:861" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + assign $2\tmp_xer_in[2:0] 3'001 case - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + assign $2\tmp_xer_in[2:0] $1\tmp_xer_in[2:0] end sync always - update \LDST_dec31_dec_sub23_sgn_ext $0\LDST_dec31_dec_sub23_sgn_ext[0:0] + update \tmp_xer_in $0\tmp_xer_in[2:0] end - attribute \src "issuer_ls180.v:12780.3-12828.6" - process $proc$issuer_ls180.v:12780$255 + attribute \src "libresoc.v:10365.3-10374.6" + process $proc$libresoc.v:10365$308 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub23_is_32b[0:0] $1\LDST_dec31_dec_sub23_is_32b[0:0] - attribute \src "issuer_ls180.v:12781.5-12781.29" + assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0] + attribute \src "libresoc.v:10366.5-10366.29" switch \initial - attribute \src "issuer_ls180.v:12781.9-12781.17" + attribute \src "libresoc.v:10366.9-10366.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:863" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\tmp_xer_out[0:0] 1'1 case - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + assign $1\tmp_xer_out[0:0] 1'0 end sync always - update \LDST_dec31_dec_sub23_is_32b $0\LDST_dec31_dec_sub23_is_32b[0:0] + update \tmp_xer_out $0\tmp_xer_out[0:0] end - attribute \src "issuer_ls180.v:12829.3-12877.6" - process $proc$issuer_ls180.v:12829$256 + attribute \src "libresoc.v:10375.3-10384.6" + process $proc$libresoc.v:10375$309 assign { } { } assign { } { } - assign $0\LDST_dec31_dec_sub23_sgn[0:0] $1\LDST_dec31_dec_sub23_sgn[0:0] - attribute \src "issuer_ls180.v:12830.5-12830.29" + assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0] + attribute \src "libresoc.v:10376.5-10376.29" switch \initial - attribute \src "issuer_ls180.v:12830.9-12830.17" + attribute \src "libresoc.v:10376.9-10376.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:867" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 + assign $1\tmp_tmp_trapaddr[12:0] 13'0000001110000 + case + assign $1\tmp_tmp_trapaddr[12:0] 13'0000000000000 + end + sync always + update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0] + end + attribute \src "libresoc.v:10385.3-10404.6" + process $proc$libresoc.v:10385$310 + assign { } { } + assign { } { } + assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0] + attribute \src "libresoc.v:10386.5-10386.29" + switch \initial + attribute \src "libresoc.v:10386.9-10386.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:42" + switch \dec_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 , 7'1000111 , 7'1001000 , 7'1001010 , 7'1000110 assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 + assign $1\is_priv_insn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 , 7'0110001 assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 + assign $1\is_priv_insn[0:0] $2\is_priv_insn[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:49" + switch \tmp_tmp_insn [20] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\is_priv_insn[0:0] 1'1 + case + assign $2\is_priv_insn[0:0] 1'0 + end + case + assign $1\is_priv_insn[0:0] 1'0 + end + sync always + update \is_priv_insn $0\is_priv_insn[0:0] + end + attribute \src "libresoc.v:10405.3-10486.6" + process $proc$libresoc.v:10405$311 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_out[2:0] $1\cr_out[2:0] + assign $0\lk[0:0] $1\lk[0:0] + assign $0\cia[63:0] $1\cia[63:0] + assign $0\cr_in1[2:0] $1\cr_in1[2:0] + assign $0\cr_in1_ok[0:0] $1\cr_in1_ok[0:0] + assign $0\cr_in2[2:0] $1\cr_in2[2:0] + assign $0\cr_in2$1[2:0]$312 $1\cr_in2$1[2:0]$314 + assign $0\cr_in2_ok[0:0] $1\cr_in2_ok[0:0] + assign $0\cr_in2_ok$2[0:0]$313 $1\cr_in2_ok$2[0:0]$315 + assign $0\cr_out_ok[0:0] $1\cr_out_ok[0:0] + assign $0\cr_rd[7:0] $1\cr_rd[7:0] + assign $0\cr_rd_ok[0:0] $1\cr_rd_ok[0:0] + assign $0\cr_wr[7:0] $1\cr_wr[7:0] + assign $0\cr_wr_ok[0:0] $1\cr_wr_ok[0:0] + assign $0\ea[4:0] $1\ea[4:0] + assign $0\ea_ok[0:0] $1\ea_ok[0:0] + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fn_unit[11:0] $1\fn_unit[11:0] + assign $0\input_carry[1:0] $1\input_carry[1:0] + assign $0\insn[31:0] $1\insn[31:0] + assign $0\insn_type[6:0] $1\insn_type[6:0] + assign $0\is_32bit[0:0] $1\is_32bit[0:0] + assign $0\msr[63:0] $1\msr[63:0] + assign $0\oe[0:0] $1\oe[0:0] + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + assign $0\rc[0:0] $1\rc[0:0] + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + assign $0\reg1[4:0] $1\reg1[4:0] + assign $0\reg1_ok[0:0] $1\reg1_ok[0:0] + assign $0\reg2[4:0] $1\reg2[4:0] + assign $0\reg2_ok[0:0] $1\reg2_ok[0:0] + assign $0\reg3[4:0] $1\reg3[4:0] + assign $0\reg3_ok[0:0] $1\reg3_ok[0:0] + assign $0\rego[4:0] $1\rego[4:0] + assign $0\rego_ok[0:0] $1\rego_ok[0:0] + assign $0\spr1[9:0] $1\spr1[9:0] + assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] + assign $0\spro[9:0] $1\spro[9:0] + assign $0\spro_ok[0:0] $1\spro_ok[0:0] + assign $0\trapaddr[12:0] $1\trapaddr[12:0] + assign $0\traptype[6:0] $1\traptype[6:0] + assign $0\xer_in[2:0] $1\xer_in[2:0] + assign $0\xer_out[0:0] $1\xer_out[0:0] + assign $0\fasto1[2:0] $2\fasto1[2:0] + assign $0\fasto1_ok[0:0] $2\fasto1_ok[0:0] + assign $0\fasto2[2:0] $2\fasto2[2:0] + assign $0\fasto2_ok[0:0] $2\fasto2_ok[0:0] + assign $0\fast1[2:0] $2\fast1[2:0] + assign $0\fast1_ok[0:0] $2\fast1_ok[0:0] + assign $0\fast2[2:0] $2\fast2[2:0] + assign $0\fast2_ok[0:0] $2\fast2_ok[0:0] + assign $0\asmcode[7:0] \dec_asmcode + attribute \src "libresoc.v:10406.5-10406.29" + switch \initial + attribute \src "libresoc.v:10406.9-10406.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:895" + switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok } + attribute \src "libresoc.v:0.0-0.0" + case 4'---1 assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - case - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub23_sgn $0\LDST_dec31_dec_sub23_sgn[0:0] - end - attribute \src "issuer_ls180.v:12878.3-12926.6" - process $proc$issuer_ls180.v:12878$257 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub23_internal_op[6:0] $1\LDST_dec31_dec_sub23_internal_op[6:0] - attribute \src "issuer_ls180.v:12879.5-12879.29" - switch \initial - attribute \src "issuer_ls180.v:12879.9-12879.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 - case - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0000000 - end - sync always - update \LDST_dec31_dec_sub23_internal_op $0\LDST_dec31_dec_sub23_internal_op[6:0] - end - attribute \src "issuer_ls180.v:12927.3-12975.6" - process $proc$issuer_ls180.v:12927$258 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub23_in1_sel[2:0] $1\LDST_dec31_dec_sub23_in1_sel[2:0] - attribute \src "issuer_ls180.v:12928.5-12928.29" - switch \initial - attribute \src "issuer_ls180.v:12928.9-12928.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - case - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'000 - end - sync always - update \LDST_dec31_dec_sub23_in1_sel $0\LDST_dec31_dec_sub23_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:12976.3-13024.6" - process $proc$issuer_ls180.v:12976$259 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub23_in2_sel[3:0] $1\LDST_dec31_dec_sub23_in2_sel[3:0] - attribute \src "issuer_ls180.v:12977.5-12977.29" - switch \initial - attribute \src "issuer_ls180.v:12977.9-12977.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$315 $1\cr_in2$1[2:0]$314 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000010010000 + assign $1\traptype[6:0] 7'0100000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 4'--1- assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - case - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0000 - end - sync always - update \LDST_dec31_dec_sub23_in2_sel $0\LDST_dec31_dec_sub23_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:13025.3-13073.6" - process $proc$issuer_ls180.v:13025$260 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub23_cr_in[2:0] $1\LDST_dec31_dec_sub23_cr_in[2:0] - attribute \src "issuer_ls180.v:13026.5-13026.29" - switch \initial - attribute \src "issuer_ls180.v:13026.9-13026.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - case - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - end - sync always - update \LDST_dec31_dec_sub23_cr_in $0\LDST_dec31_dec_sub23_cr_in[2:0] - end - attribute \src "issuer_ls180.v:13074.3-13122.6" - process $proc$issuer_ls180.v:13074$261 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub23_cr_out[2:0] $1\LDST_dec31_dec_sub23_cr_out[2:0] - attribute \src "issuer_ls180.v:13075.5-13075.29" - switch \initial - attribute \src "issuer_ls180.v:13075.9-13075.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - case - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - end - sync always - update \LDST_dec31_dec_sub23_cr_out $0\LDST_dec31_dec_sub23_cr_out[2:0] - end - attribute \src "issuer_ls180.v:13123.3-13171.6" - process $proc$issuer_ls180.v:13123$262 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub23_ldst_len[3:0] $1\LDST_dec31_dec_sub23_ldst_len[3:0] - attribute \src "issuer_ls180.v:13124.5-13124.29" - switch \initial - attribute \src "issuer_ls180.v:13124.9-13124.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 - case - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0000 - end - sync always - update \LDST_dec31_dec_sub23_ldst_len $0\LDST_dec31_dec_sub23_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:13172.3-13220.6" - process $proc$issuer_ls180.v:13172$263 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub23_upd[1:0] $1\LDST_dec31_dec_sub23_upd[1:0] - attribute \src "issuer_ls180.v:13173.5-13173.29" - switch \initial - attribute \src "issuer_ls180.v:13173.9-13173.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$315 $1\cr_in2$1[2:0]$314 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000001010000 + assign $1\traptype[6:0] 7'0010000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 4'-1-- assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 - case - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 - end - sync always - update \LDST_dec31_dec_sub23_upd $0\LDST_dec31_dec_sub23_upd[1:0] - end - attribute \src "issuer_ls180.v:13221.3-13269.6" - process $proc$issuer_ls180.v:13221$264 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub23_rc_sel[1:0] $1\LDST_dec31_dec_sub23_rc_sel[1:0] - attribute \src "issuer_ls180.v:13222.5-13222.29" - switch \initial - attribute \src "issuer_ls180.v:13222.9-13222.17" - case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$315 $1\cr_in2$1[2:0]$314 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000001110000 + assign $1\traptype[6:0] 7'0000010 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 4'1--- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$315 $1\cr_in2$1[2:0]$314 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000001110000 + assign $1\traptype[6:0] 7'1000000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\traptype[6:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[11:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$315 $1\cr_in2$1[2:0]$314 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$12 \tmp_cr_in2$11 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:924" + switch \$33 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\fasto1[2:0] 3'011 + assign $2\fasto1_ok[0:0] 1'1 + assign $2\fasto2[2:0] 3'100 + assign $2\fasto2_ok[0:0] 1'1 + case + assign $2\fasto1[2:0] $1\fasto1[2:0] + assign $2\fasto1_ok[0:0] $1\fasto1_ok[0:0] + assign $2\fasto2[2:0] $1\fasto2[2:0] + assign $2\fasto2_ok[0:0] $1\fasto2_ok[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:933" + switch \$35 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\fast1[2:0] 3'011 + assign $2\fast1_ok[0:0] 1'1 + assign $2\fast2[2:0] 3'100 + assign $2\fast2_ok[0:0] 1'1 case - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + assign $2\fast1[2:0] $1\fast1[2:0] + assign $2\fast1_ok[0:0] $1\fast1_ok[0:0] + assign $2\fast2[2:0] $1\fast2[2:0] + assign $2\fast2_ok[0:0] $1\fast2_ok[0:0] end sync always - update \LDST_dec31_dec_sub23_rc_sel $0\LDST_dec31_dec_sub23_rc_sel[1:0] + update \asmcode $0\asmcode[7:0] + update \cr_out $0\cr_out[2:0] + update \lk $0\lk[0:0] + update \cia $0\cia[63:0] + update \cr_in1 $0\cr_in1[2:0] + update \cr_in1_ok $0\cr_in1_ok[0:0] + update \cr_in2 $0\cr_in2[2:0] + update \cr_in2$1 $0\cr_in2$1[2:0]$312 + update \cr_in2_ok $0\cr_in2_ok[0:0] + update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$313 + update \cr_out_ok $0\cr_out_ok[0:0] + update \cr_rd $0\cr_rd[7:0] + update \cr_rd_ok $0\cr_rd_ok[0:0] + update \cr_wr $0\cr_wr[7:0] + update \cr_wr_ok $0\cr_wr_ok[0:0] + update \ea $0\ea[4:0] + update \ea_ok $0\ea_ok[0:0] + update \fast1 $0\fast1[2:0] + update \fast1_ok $0\fast1_ok[0:0] + update \fast2 $0\fast2[2:0] + update \fast2_ok $0\fast2_ok[0:0] + update \fasto1 $0\fasto1[2:0] + update \fasto1_ok $0\fasto1_ok[0:0] + update \fasto2 $0\fasto2[2:0] + update \fasto2_ok $0\fasto2_ok[0:0] + update \fn_unit $0\fn_unit[11:0] + update \input_carry $0\input_carry[1:0] + update \insn $0\insn[31:0] + update \insn_type $0\insn_type[6:0] + update \is_32bit $0\is_32bit[0:0] + update \msr $0\msr[63:0] + update \oe $0\oe[0:0] + update \oe_ok $0\oe_ok[0:0] + update \rc $0\rc[0:0] + update \rc_ok $0\rc_ok[0:0] + update \reg1 $0\reg1[4:0] + update \reg1_ok $0\reg1_ok[0:0] + update \reg2 $0\reg2[4:0] + update \reg2_ok $0\reg2_ok[0:0] + update \reg3 $0\reg3[4:0] + update \reg3_ok $0\reg3_ok[0:0] + update \rego $0\rego[4:0] + update \rego_ok $0\rego_ok[0:0] + update \spr1 $0\spr1[9:0] + update \spr1_ok $0\spr1_ok[0:0] + update \spro $0\spro[9:0] + update \spro_ok $0\spro_ok[0:0] + update \trapaddr $0\trapaddr[12:0] + update \traptype $0\traptype[6:0] + update \xer_in $0\xer_in[2:0] + update \xer_out $0\xer_out[0:0] + end + attribute \src "libresoc.v:8651.7-8651.20" + process $proc$libresoc.v:8651$316 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - connect \opcode_switch \opcode_in [10:6] + connect \$13 $eq$libresoc.v:10186$294_Y + connect \$15 $eq$libresoc.v:10187$295_Y + connect \$17 $eq$libresoc.v:10188$296_Y + connect \$19 $eq$libresoc.v:10189$297_Y + connect \$21 $and$libresoc.v:10190$298_Y + connect \$23 $and$libresoc.v:10191$299_Y + connect \$25 $and$libresoc.v:10192$300_Y + connect \$27 $eq$libresoc.v:10193$301_Y + connect \$29 $eq$libresoc.v:10194$302_Y + connect \$31 $eq$libresoc.v:10195$303_Y + connect \$33 $or$libresoc.v:10196$304_Y + connect \$35 $eq$libresoc.v:10197$305_Y + connect \tmp_asmcode 8'00000000 + connect \tmp_tmp_traptype 7'0000000 + connect \illeg_ok \$27 + connect \priv_ok \$25 + connect \dec_irq_ok \$23 + connect \ext_irq_ok \$21 + connect { \tmp_cr_out_ok \tmp_cr_out } { \dec_cr_out_cr_bitfield_ok \dec_cr_out_cr_bitfield } + connect { \tmp_cr_in2_ok$12 \tmp_cr_in2$11 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o } + connect { \tmp_cr_in2_ok \tmp_cr_in2 } { \dec_cr_in_cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b } + connect { \tmp_cr_in1_ok \tmp_cr_in1 } { \dec_cr_in_cr_bitfield_ok \dec_cr_in_cr_bitfield } + connect { \tmp_fasto2_ok \tmp_fasto2 } { \dec_o2_fast_o_ok \dec_o2_fast_o } + connect { \tmp_fasto1_ok \tmp_fasto1 } { \dec_o_fast_o_ok \dec_o_fast_o } + connect { \tmp_fast2_ok \tmp_fast2 } { \dec_b_fast_b_ok \dec_b_fast_b } + connect { \tmp_fast1_ok \tmp_fast1 } { \dec_a_fast_a_ok \dec_a_fast_a } + connect { \tmp_spro_ok \tmp_spro } { \dec_o_spr_o_ok \dec_o_spr_o } + connect { \tmp_spr1_ok \tmp_spr1 } { \dec_a_spr_a_ok \dec_a_spr_a } + connect { \tmp_ea_ok \tmp_ea } { \dec_o2_reg_o_ok \dec_o2_reg_o } + connect { \tmp_rego_ok \tmp_rego } { \dec_o_reg_o_ok \dec_o_reg_o } + connect { \tmp_reg3_ok \tmp_reg3 } { \dec_c_reg_c_ok \dec_c_reg_c } + connect { \tmp_reg2_ok \tmp_reg2 } { \dec_b_reg_b_ok \dec_b_reg_b } + connect { \tmp_reg1_ok \tmp_reg1 } { \dec_a_reg_a_ok \dec_a_reg_a } + connect \dec_o2_lk \tmp_tmp_lk + connect \sel_in \dec_out_sel + connect \dec_o_sel_in \dec_out_sel + connect \dec_c_sel_in \dec_in3_sel + connect \dec_b_sel_in \dec_in2_sel + connect \dec_a_sel_in \dec_in1_sel + connect \insn_in$10 \dec_opcode_in + connect \insn_in$9 \dec_opcode_in + connect \insn_in$8 \dec_opcode_in + connect \insn_in$7 \dec_opcode_in + connect \insn_in$6 \dec_opcode_in + connect \tmp_tmp_is_32bit \dec_is_32b + connect \tmp_tmp_input_carry \dec_cry_in + connect { \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr } { \dec_cr_out_cr_fxm_ok \dec_cr_out_cr_fxm } + connect { \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd } { \dec_cr_in_cr_fxm_ok \dec_cr_in_cr_fxm } + connect { \tmp_tmp_oe_ok \tmp_tmp_oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \tmp_tmp_rc_ok \tmp_tmp_rc } { \dec_rc_rc_ok \dec_rc_rc } + connect \tmp_tmp_fn_unit \dec_function_unit + connect \tmp_tmp_insn_type \dec_internal_op + connect \tmp_tmp_cia \cur_pc + connect \tmp_tmp_msr \cur_msr + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_cr_out + connect \dec_cr_in_sel_in \dec_cr_in + connect \dec_oe_sel_in \dec_rc_sel + connect \dec_rc_sel_in \dec_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$5 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \tmp_tmp_insn \dec_opcode_in end -attribute \src "issuer_ls180.v:13275.1-13666.10" +attribute \src "libresoc.v:10543.1-11690.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec58" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec30" attribute \generator "nMigen" -module \LDST_dec58 - attribute \src "issuer_ls180.v:13473.3-13488.6" - wire $0\LDST_dec58_br[0:0] - attribute \src "issuer_ls180.v:13585.3-13600.6" - wire width 3 $0\LDST_dec58_cr_in[2:0] - attribute \src "issuer_ls180.v:13601.3-13616.6" - wire width 3 $0\LDST_dec58_cr_out[2:0] - attribute \src "issuer_ls180.v:13457.3-13472.6" - wire width 12 $0\LDST_dec58_function_unit[11:0] - attribute \src "issuer_ls180.v:13553.3-13568.6" - wire width 3 $0\LDST_dec58_in1_sel[2:0] - attribute \src "issuer_ls180.v:13569.3-13584.6" - wire width 4 $0\LDST_dec58_in2_sel[3:0] - attribute \src "issuer_ls180.v:13537.3-13552.6" - wire width 7 $0\LDST_dec58_internal_op[6:0] - attribute \src "issuer_ls180.v:13505.3-13520.6" - wire $0\LDST_dec58_is_32b[0:0] - attribute \src "issuer_ls180.v:13617.3-13632.6" - wire width 4 $0\LDST_dec58_ldst_len[3:0] - attribute \src "issuer_ls180.v:13649.3-13664.6" - wire width 2 $0\LDST_dec58_rc_sel[1:0] - attribute \src "issuer_ls180.v:13521.3-13536.6" - wire $0\LDST_dec58_sgn[0:0] - attribute \src "issuer_ls180.v:13489.3-13504.6" - wire $0\LDST_dec58_sgn_ext[0:0] - attribute \src "issuer_ls180.v:13633.3-13648.6" - wire width 2 $0\LDST_dec58_upd[1:0] - attribute \src "issuer_ls180.v:13276.7-13276.20" +module \dec30 + attribute \src "libresoc.v:10986.3-11022.6" + wire width 8 $0\dec30_asmcode[7:0] + attribute \src "libresoc.v:11134.3-11170.6" + wire $0\dec30_br[0:0] + attribute \src "libresoc.v:11615.3-11651.6" + wire width 3 $0\dec30_cr_in[2:0] + attribute \src "libresoc.v:11652.3-11688.6" + wire width 3 $0\dec30_cr_out[2:0] + attribute \src "libresoc.v:10949.3-10985.6" + wire width 2 $0\dec30_cry_in[1:0] + attribute \src "libresoc.v:11097.3-11133.6" + wire $0\dec30_cry_out[0:0] + attribute \src "libresoc.v:11430.3-11466.6" + wire width 5 $0\dec30_form[4:0] + attribute \src "libresoc.v:10801.3-10837.6" + wire width 12 $0\dec30_function_unit[11:0] + attribute \src "libresoc.v:11467.3-11503.6" + wire width 3 $0\dec30_in1_sel[2:0] + attribute \src "libresoc.v:11504.3-11540.6" + wire width 4 $0\dec30_in2_sel[3:0] + attribute \src "libresoc.v:11541.3-11577.6" + wire width 2 $0\dec30_in3_sel[1:0] + attribute \src "libresoc.v:11208.3-11244.6" + wire width 7 $0\dec30_internal_op[6:0] + attribute \src "libresoc.v:11023.3-11059.6" + wire $0\dec30_inv_a[0:0] + attribute \src "libresoc.v:11060.3-11096.6" + wire $0\dec30_inv_out[0:0] + attribute \src "libresoc.v:11282.3-11318.6" + wire $0\dec30_is_32b[0:0] + attribute \src "libresoc.v:10838.3-10874.6" + wire width 4 $0\dec30_ldst_len[3:0] + attribute \src "libresoc.v:11356.3-11392.6" + wire $0\dec30_lk[0:0] + attribute \src "libresoc.v:11578.3-11614.6" + wire width 2 $0\dec30_out_sel[1:0] + attribute \src "libresoc.v:10912.3-10948.6" + wire width 2 $0\dec30_rc_sel[1:0] + attribute \src "libresoc.v:11245.3-11281.6" + wire $0\dec30_rsrv[0:0] + attribute \src "libresoc.v:11393.3-11429.6" + wire $0\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:11319.3-11355.6" + wire $0\dec30_sgn[0:0] + attribute \src "libresoc.v:11171.3-11207.6" + wire $0\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:10875.3-10911.6" + wire width 2 $0\dec30_upd[1:0] + attribute \src "libresoc.v:10544.7-10544.20" wire $0\initial[0:0] - attribute \src "issuer_ls180.v:13473.3-13488.6" - wire $1\LDST_dec58_br[0:0] - attribute \src "issuer_ls180.v:13585.3-13600.6" - wire width 3 $1\LDST_dec58_cr_in[2:0] - attribute \src "issuer_ls180.v:13601.3-13616.6" - wire width 3 $1\LDST_dec58_cr_out[2:0] - attribute \src "issuer_ls180.v:13457.3-13472.6" - wire width 12 $1\LDST_dec58_function_unit[11:0] - attribute \src "issuer_ls180.v:13553.3-13568.6" - wire width 3 $1\LDST_dec58_in1_sel[2:0] - attribute \src "issuer_ls180.v:13569.3-13584.6" - wire width 4 $1\LDST_dec58_in2_sel[3:0] - attribute \src "issuer_ls180.v:13537.3-13552.6" - wire width 7 $1\LDST_dec58_internal_op[6:0] - attribute \src "issuer_ls180.v:13505.3-13520.6" - wire $1\LDST_dec58_is_32b[0:0] - attribute \src "issuer_ls180.v:13617.3-13632.6" - wire width 4 $1\LDST_dec58_ldst_len[3:0] - attribute \src "issuer_ls180.v:13649.3-13664.6" - wire width 2 $1\LDST_dec58_rc_sel[1:0] - attribute \src "issuer_ls180.v:13521.3-13536.6" - wire $1\LDST_dec58_sgn[0:0] - attribute \src "issuer_ls180.v:13489.3-13504.6" - wire $1\LDST_dec58_sgn_ext[0:0] - attribute \src "issuer_ls180.v:13633.3-13648.6" - wire width 2 $1\LDST_dec58_upd[1:0] + attribute \src "libresoc.v:10986.3-11022.6" + wire width 8 $1\dec30_asmcode[7:0] + attribute \src "libresoc.v:11134.3-11170.6" + wire $1\dec30_br[0:0] + attribute \src "libresoc.v:11615.3-11651.6" + wire width 3 $1\dec30_cr_in[2:0] + attribute \src "libresoc.v:11652.3-11688.6" + wire width 3 $1\dec30_cr_out[2:0] + attribute \src "libresoc.v:10949.3-10985.6" + wire width 2 $1\dec30_cry_in[1:0] + attribute \src "libresoc.v:11097.3-11133.6" + wire $1\dec30_cry_out[0:0] + attribute \src "libresoc.v:11430.3-11466.6" + wire width 5 $1\dec30_form[4:0] + attribute \src "libresoc.v:10801.3-10837.6" + wire width 12 $1\dec30_function_unit[11:0] + attribute \src "libresoc.v:11467.3-11503.6" + wire width 3 $1\dec30_in1_sel[2:0] + attribute \src "libresoc.v:11504.3-11540.6" + wire width 4 $1\dec30_in2_sel[3:0] + attribute \src "libresoc.v:11541.3-11577.6" + wire width 2 $1\dec30_in3_sel[1:0] + attribute \src "libresoc.v:11208.3-11244.6" + wire width 7 $1\dec30_internal_op[6:0] + attribute \src "libresoc.v:11023.3-11059.6" + wire $1\dec30_inv_a[0:0] + attribute \src "libresoc.v:11060.3-11096.6" + wire $1\dec30_inv_out[0:0] + attribute \src "libresoc.v:11282.3-11318.6" + wire $1\dec30_is_32b[0:0] + attribute \src "libresoc.v:10838.3-10874.6" + wire width 4 $1\dec30_ldst_len[3:0] + attribute \src "libresoc.v:11356.3-11392.6" + wire $1\dec30_lk[0:0] + attribute \src "libresoc.v:11578.3-11614.6" + wire width 2 $1\dec30_out_sel[1:0] + attribute \src "libresoc.v:10912.3-10948.6" + wire width 2 $1\dec30_rc_sel[1:0] + attribute \src "libresoc.v:11245.3-11281.6" + wire $1\dec30_rsrv[0:0] + attribute \src "libresoc.v:11393.3-11429.6" + wire $1\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:11319.3-11355.6" + wire $1\dec30_sgn[0:0] + attribute \src "libresoc.v:11171.3-11207.6" + wire $1\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:10875.3-10911.6" + wire width 2 $1\dec30_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec30_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \LDST_dec58_br + wire output 18 \dec30_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -19036,7 +16090,7 @@ module \LDST_dec58 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \LDST_dec58_cr_in + wire width 3 output 9 \dec30_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -19044,7 +16098,47 @@ module \LDST_dec58 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 6 \LDST_dec58_cr_out + wire width 3 output 10 \dec30_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec30_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec30_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -19059,7 +16153,7 @@ module \LDST_dec58 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \LDST_dec58_function_unit + wire width 12 output 1 \dec30_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -19067,7 +16161,7 @@ module \LDST_dec58 attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \LDST_dec58_in1_sel + wire width 3 output 5 \dec30_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -19084,7 +16178,13 @@ module \LDST_dec58 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 4 \LDST_dec58_in2_sel + wire width 4 output 6 \dec30_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec30_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -19160,9 +16260,13 @@ module \LDST_dec58 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \LDST_dec58_internal_op + wire width 7 output 2 \dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec30_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 12 \LDST_dec58_is_32b + wire output 21 \dec30_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -19170,1095 +16274,1576 @@ module \LDST_dec58 attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 7 \LDST_dec58_ldst_len + wire width 4 output 11 \dec30_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec30_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec30_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 9 \LDST_dec58_rc_sel + wire width 2 output 13 \dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec30_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec30_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 13 \LDST_dec58_sgn + wire output 22 \dec30_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 11 \LDST_dec58_sgn_ext + wire output 19 \dec30_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \LDST_dec58_upd - attribute \src "issuer_ls180.v:13276.7-13276.15" + wire width 2 output 12 \dec30_upd + attribute \src "libresoc.v:10544.7-10544.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 14 \opcode_in + wire width 32 input 25 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 2 \opcode_switch - attribute \src "issuer_ls180.v:13276.7-13276.20" - process $proc$issuer_ls180.v:13276$279 + wire width 4 \opcode_switch + attribute \src "libresoc.v:10544.7-10544.20" + process $proc$libresoc.v:10544$341 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "issuer_ls180.v:13457.3-13472.6" - process $proc$issuer_ls180.v:13457$266 + attribute \src "libresoc.v:10801.3-10837.6" + process $proc$libresoc.v:10801$317 assign { } { } assign { } { } - assign $0\LDST_dec58_function_unit[11:0] $1\LDST_dec58_function_unit[11:0] - attribute \src "issuer_ls180.v:13458.5-13458.29" + assign $0\dec30_function_unit[11:0] $1\dec30_function_unit[11:0] + attribute \src "libresoc.v:10802.5-10802.29" switch \initial - attribute \src "issuer_ls180.v:13458.9-13458.17" + attribute \src "libresoc.v:10802.9-10802.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } - assign $1\LDST_dec58_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 assign { } { } - assign $1\LDST_dec58_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 assign { } { } - assign $1\LDST_dec58_function_unit[11:0] 12'000000000100 - case - assign $1\LDST_dec58_function_unit[11:0] 12'000000000000 - end - sync always - update \LDST_dec58_function_unit $0\LDST_dec58_function_unit[11:0] - end - attribute \src "issuer_ls180.v:13473.3-13488.6" - process $proc$issuer_ls180.v:13473$267 - assign { } { } - assign { } { } - assign $0\LDST_dec58_br[0:0] $1\LDST_dec58_br[0:0] - attribute \src "issuer_ls180.v:13474.5-13474.29" - switch \initial - attribute \src "issuer_ls180.v:13474.9-13474.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 assign { } { } - assign $1\LDST_dec58_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 assign { } { } - assign $1\LDST_dec58_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 assign { } { } - assign $1\LDST_dec58_br[0:0] 1'0 + assign $1\dec30_function_unit[11:0] 12'000000001000 case - assign $1\LDST_dec58_br[0:0] 1'0 + assign $1\dec30_function_unit[11:0] 12'000000000000 end sync always - update \LDST_dec58_br $0\LDST_dec58_br[0:0] + update \dec30_function_unit $0\dec30_function_unit[11:0] end - attribute \src "issuer_ls180.v:13489.3-13504.6" - process $proc$issuer_ls180.v:13489$268 + attribute \src "libresoc.v:10838.3-10874.6" + process $proc$libresoc.v:10838$318 assign { } { } assign { } { } - assign $0\LDST_dec58_sgn_ext[0:0] $1\LDST_dec58_sgn_ext[0:0] - attribute \src "issuer_ls180.v:13490.5-13490.29" + assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0] + attribute \src "libresoc.v:10839.5-10839.29" switch \initial - attribute \src "issuer_ls180.v:13490.9-13490.17" + attribute \src "libresoc.v:10839.9-10839.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } - assign $1\LDST_dec58_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 assign { } { } - assign $1\LDST_dec58_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 assign { } { } - assign $1\LDST_dec58_sgn_ext[0:0] 1'1 + assign $1\dec30_ldst_len[3:0] 4'0000 case - assign $1\LDST_dec58_sgn_ext[0:0] 1'0 + assign $1\dec30_ldst_len[3:0] 4'0000 end sync always - update \LDST_dec58_sgn_ext $0\LDST_dec58_sgn_ext[0:0] + update \dec30_ldst_len $0\dec30_ldst_len[3:0] end - attribute \src "issuer_ls180.v:13505.3-13520.6" - process $proc$issuer_ls180.v:13505$269 + attribute \src "libresoc.v:10875.3-10911.6" + process $proc$libresoc.v:10875$319 assign { } { } assign { } { } - assign $0\LDST_dec58_is_32b[0:0] $1\LDST_dec58_is_32b[0:0] - attribute \src "issuer_ls180.v:13506.5-13506.29" + assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] + attribute \src "libresoc.v:10876.5-10876.29" switch \initial - attribute \src "issuer_ls180.v:13506.9-13506.17" + attribute \src "libresoc.v:10876.9-10876.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } - assign $1\LDST_dec58_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 assign { } { } - assign $1\LDST_dec58_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 assign { } { } - assign $1\LDST_dec58_is_32b[0:0] 1'0 + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 case - assign $1\LDST_dec58_is_32b[0:0] 1'0 + assign $1\dec30_upd[1:0] 2'00 end sync always - update \LDST_dec58_is_32b $0\LDST_dec58_is_32b[0:0] + update \dec30_upd $0\dec30_upd[1:0] end - attribute \src "issuer_ls180.v:13521.3-13536.6" - process $proc$issuer_ls180.v:13521$270 + attribute \src "libresoc.v:10912.3-10948.6" + process $proc$libresoc.v:10912$320 assign { } { } assign { } { } - assign $0\LDST_dec58_sgn[0:0] $1\LDST_dec58_sgn[0:0] - attribute \src "issuer_ls180.v:13522.5-13522.29" + assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0] + attribute \src "libresoc.v:10913.5-10913.29" switch \initial - attribute \src "issuer_ls180.v:13522.9-13522.17" + attribute \src "libresoc.v:10913.9-10913.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } - assign $1\LDST_dec58_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 assign { } { } - assign $1\LDST_dec58_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 assign { } { } - assign $1\LDST_dec58_sgn[0:0] 1'0 + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 case - assign $1\LDST_dec58_sgn[0:0] 1'0 + assign $1\dec30_rc_sel[1:0] 2'00 end sync always - update \LDST_dec58_sgn $0\LDST_dec58_sgn[0:0] + update \dec30_rc_sel $0\dec30_rc_sel[1:0] end - attribute \src "issuer_ls180.v:13537.3-13552.6" - process $proc$issuer_ls180.v:13537$271 + attribute \src "libresoc.v:10949.3-10985.6" + process $proc$libresoc.v:10949$321 assign { } { } assign { } { } - assign $0\LDST_dec58_internal_op[6:0] $1\LDST_dec58_internal_op[6:0] - attribute \src "issuer_ls180.v:13538.5-13538.29" + assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0] + attribute \src "libresoc.v:10950.5-10950.29" switch \initial - attribute \src "issuer_ls180.v:13538.9-13538.17" + attribute \src "libresoc.v:10950.9-10950.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } - assign $1\LDST_dec58_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 assign { } { } - assign $1\LDST_dec58_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 assign { } { } - assign $1\LDST_dec58_internal_op[6:0] 7'0100101 + assign $1\dec30_cry_in[1:0] 2'00 case - assign $1\LDST_dec58_internal_op[6:0] 7'0000000 + assign $1\dec30_cry_in[1:0] 2'00 end sync always - update \LDST_dec58_internal_op $0\LDST_dec58_internal_op[6:0] + update \dec30_cry_in $0\dec30_cry_in[1:0] end - attribute \src "issuer_ls180.v:13553.3-13568.6" - process $proc$issuer_ls180.v:13553$272 + attribute \src "libresoc.v:10986.3-11022.6" + process $proc$libresoc.v:10986$322 assign { } { } assign { } { } - assign $0\LDST_dec58_in1_sel[2:0] $1\LDST_dec58_in1_sel[2:0] - attribute \src "issuer_ls180.v:13554.5-13554.29" + assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0] + attribute \src "libresoc.v:10987.5-10987.29" switch \initial - attribute \src "issuer_ls180.v:13554.9-13554.17" + attribute \src "libresoc.v:10987.9-10987.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } - assign $1\LDST_dec58_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_asmcode[7:0] 8'10010100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 assign { } { } - assign $1\LDST_dec58_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 + assign $1\dec30_asmcode[7:0] 8'10010100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 assign { } { } - assign $1\LDST_dec58_in1_sel[2:0] 3'010 + assign $1\dec30_asmcode[7:0] 8'10010101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010110 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010110 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010111 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010111 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010011 case - assign $1\LDST_dec58_in1_sel[2:0] 3'000 + assign $1\dec30_asmcode[7:0] 8'00000000 end sync always - update \LDST_dec58_in1_sel $0\LDST_dec58_in1_sel[2:0] + update \dec30_asmcode $0\dec30_asmcode[7:0] end - attribute \src "issuer_ls180.v:13569.3-13584.6" - process $proc$issuer_ls180.v:13569$273 + attribute \src "libresoc.v:11023.3-11059.6" + process $proc$libresoc.v:11023$323 assign { } { } assign { } { } - assign $0\LDST_dec58_in2_sel[3:0] $1\LDST_dec58_in2_sel[3:0] - attribute \src "issuer_ls180.v:13570.5-13570.29" + assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0] + attribute \src "libresoc.v:11024.5-11024.29" switch \initial - attribute \src "issuer_ls180.v:13570.9-13570.17" + attribute \src "libresoc.v:11024.9-11024.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec58_in2_sel[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } - assign $1\LDST_dec58_in2_sel[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 assign { } { } - assign $1\LDST_dec58_in2_sel[3:0] 4'1000 - case - assign $1\LDST_dec58_in2_sel[3:0] 4'0000 - end - sync always - update \LDST_dec58_in2_sel $0\LDST_dec58_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:13585.3-13600.6" - process $proc$issuer_ls180.v:13585$274 - assign { } { } - assign { } { } - assign $0\LDST_dec58_cr_in[2:0] $1\LDST_dec58_cr_in[2:0] - attribute \src "issuer_ls180.v:13586.5-13586.29" - switch \initial - attribute \src "issuer_ls180.v:13586.9-13586.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 assign { } { } - assign $1\LDST_dec58_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 assign { } { } - assign $1\LDST_dec58_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 assign { } { } - assign $1\LDST_dec58_cr_in[2:0] 3'000 + assign $1\dec30_inv_a[0:0] 1'0 case - assign $1\LDST_dec58_cr_in[2:0] 3'000 + assign $1\dec30_inv_a[0:0] 1'0 end sync always - update \LDST_dec58_cr_in $0\LDST_dec58_cr_in[2:0] + update \dec30_inv_a $0\dec30_inv_a[0:0] end - attribute \src "issuer_ls180.v:13601.3-13616.6" - process $proc$issuer_ls180.v:13601$275 + attribute \src "libresoc.v:11060.3-11096.6" + process $proc$libresoc.v:11060$324 assign { } { } assign { } { } - assign $0\LDST_dec58_cr_out[2:0] $1\LDST_dec58_cr_out[2:0] - attribute \src "issuer_ls180.v:13602.5-13602.29" + assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0] + attribute \src "libresoc.v:11061.5-11061.29" switch \initial - attribute \src "issuer_ls180.v:13602.9-13602.17" + attribute \src "libresoc.v:11061.9-11061.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } - assign $1\LDST_dec58_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 assign { } { } - assign $1\LDST_dec58_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 assign { } { } - assign $1\LDST_dec58_cr_out[2:0] 3'000 + assign $1\dec30_inv_out[0:0] 1'0 case - assign $1\LDST_dec58_cr_out[2:0] 3'000 + assign $1\dec30_inv_out[0:0] 1'0 end sync always - update \LDST_dec58_cr_out $0\LDST_dec58_cr_out[2:0] + update \dec30_inv_out $0\dec30_inv_out[0:0] end - attribute \src "issuer_ls180.v:13617.3-13632.6" - process $proc$issuer_ls180.v:13617$276 + attribute \src "libresoc.v:11097.3-11133.6" + process $proc$libresoc.v:11097$325 assign { } { } assign { } { } - assign $0\LDST_dec58_ldst_len[3:0] $1\LDST_dec58_ldst_len[3:0] - attribute \src "issuer_ls180.v:13618.5-13618.29" + assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0] + attribute \src "libresoc.v:11098.5-11098.29" switch \initial - attribute \src "issuer_ls180.v:13618.9-13618.17" + attribute \src "libresoc.v:11098.9-11098.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } - assign $1\LDST_dec58_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 assign { } { } - assign $1\LDST_dec58_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 assign { } { } - assign $1\LDST_dec58_ldst_len[3:0] 4'0100 + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 case - assign $1\LDST_dec58_ldst_len[3:0] 4'0000 + assign $1\dec30_cry_out[0:0] 1'0 end sync always - update \LDST_dec58_ldst_len $0\LDST_dec58_ldst_len[3:0] + update \dec30_cry_out $0\dec30_cry_out[0:0] end - attribute \src "issuer_ls180.v:13633.3-13648.6" - process $proc$issuer_ls180.v:13633$277 + attribute \src "libresoc.v:11134.3-11170.6" + process $proc$libresoc.v:11134$326 assign { } { } assign { } { } - assign $0\LDST_dec58_upd[1:0] $1\LDST_dec58_upd[1:0] - attribute \src "issuer_ls180.v:13634.5-13634.29" + assign $0\dec30_br[0:0] $1\dec30_br[0:0] + attribute \src "libresoc.v:11135.5-11135.29" switch \initial - attribute \src "issuer_ls180.v:13634.9-13634.17" + attribute \src "libresoc.v:11135.9-11135.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } - assign $1\LDST_dec58_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 assign { } { } - assign $1\LDST_dec58_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 assign { } { } - assign $1\LDST_dec58_upd[1:0] 2'00 + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_br[0:0] 1'0 case - assign $1\LDST_dec58_upd[1:0] 2'00 + assign $1\dec30_br[0:0] 1'0 end sync always - update \LDST_dec58_upd $0\LDST_dec58_upd[1:0] + update \dec30_br $0\dec30_br[0:0] end - attribute \src "issuer_ls180.v:13649.3-13664.6" - process $proc$issuer_ls180.v:13649$278 + attribute \src "libresoc.v:11171.3-11207.6" + process $proc$libresoc.v:11171$327 assign { } { } assign { } { } - assign $0\LDST_dec58_rc_sel[1:0] $1\LDST_dec58_rc_sel[1:0] - attribute \src "issuer_ls180.v:13650.5-13650.29" + assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:11172.5-11172.29" switch \initial - attribute \src "issuer_ls180.v:13650.9-13650.17" + attribute \src "libresoc.v:11172.9-11172.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } - assign $1\LDST_dec58_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 assign { } { } - assign $1\LDST_dec58_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 assign { } { } - assign $1\LDST_dec58_rc_sel[1:0] 2'00 + assign $1\dec30_sgn_ext[0:0] 1'0 case - assign $1\LDST_dec58_rc_sel[1:0] 2'00 + assign $1\dec30_sgn_ext[0:0] 1'0 end sync always - update \LDST_dec58_rc_sel $0\LDST_dec58_rc_sel[1:0] - end - connect \opcode_switch \opcode_in [1:0] -end -attribute \src "issuer_ls180.v:13670.1-14022.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec62" -attribute \generator "nMigen" -module \LDST_dec62 - attribute \src "issuer_ls180.v:13865.3-13877.6" - wire $0\LDST_dec62_br[0:0] - attribute \src "issuer_ls180.v:13956.3-13968.6" - wire width 3 $0\LDST_dec62_cr_in[2:0] - attribute \src "issuer_ls180.v:13969.3-13981.6" - wire width 3 $0\LDST_dec62_cr_out[2:0] - attribute \src "issuer_ls180.v:13852.3-13864.6" - wire width 12 $0\LDST_dec62_function_unit[11:0] - attribute \src "issuer_ls180.v:13930.3-13942.6" - wire width 3 $0\LDST_dec62_in1_sel[2:0] - attribute \src "issuer_ls180.v:13943.3-13955.6" - wire width 4 $0\LDST_dec62_in2_sel[3:0] - attribute \src "issuer_ls180.v:13917.3-13929.6" - wire width 7 $0\LDST_dec62_internal_op[6:0] - attribute \src "issuer_ls180.v:13891.3-13903.6" - wire $0\LDST_dec62_is_32b[0:0] - attribute \src "issuer_ls180.v:13982.3-13994.6" - wire width 4 $0\LDST_dec62_ldst_len[3:0] - attribute \src "issuer_ls180.v:14008.3-14020.6" - wire width 2 $0\LDST_dec62_rc_sel[1:0] - attribute \src "issuer_ls180.v:13904.3-13916.6" - wire $0\LDST_dec62_sgn[0:0] - attribute \src "issuer_ls180.v:13878.3-13890.6" - wire $0\LDST_dec62_sgn_ext[0:0] - attribute \src "issuer_ls180.v:13995.3-14007.6" - wire width 2 $0\LDST_dec62_upd[1:0] - attribute \src "issuer_ls180.v:13671.7-13671.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:13865.3-13877.6" - wire $1\LDST_dec62_br[0:0] - attribute \src "issuer_ls180.v:13956.3-13968.6" - wire width 3 $1\LDST_dec62_cr_in[2:0] - attribute \src "issuer_ls180.v:13969.3-13981.6" - wire width 3 $1\LDST_dec62_cr_out[2:0] - attribute \src "issuer_ls180.v:13852.3-13864.6" - wire width 12 $1\LDST_dec62_function_unit[11:0] - attribute \src "issuer_ls180.v:13930.3-13942.6" - wire width 3 $1\LDST_dec62_in1_sel[2:0] - attribute \src "issuer_ls180.v:13943.3-13955.6" - wire width 4 $1\LDST_dec62_in2_sel[3:0] - attribute \src "issuer_ls180.v:13917.3-13929.6" - wire width 7 $1\LDST_dec62_internal_op[6:0] - attribute \src "issuer_ls180.v:13891.3-13903.6" - wire $1\LDST_dec62_is_32b[0:0] - attribute \src "issuer_ls180.v:13982.3-13994.6" - wire width 4 $1\LDST_dec62_ldst_len[3:0] - attribute \src "issuer_ls180.v:14008.3-14020.6" - wire width 2 $1\LDST_dec62_rc_sel[1:0] - attribute \src "issuer_ls180.v:13904.3-13916.6" - wire $1\LDST_dec62_sgn[0:0] - attribute \src "issuer_ls180.v:13878.3-13890.6" - wire $1\LDST_dec62_sgn_ext[0:0] - attribute \src "issuer_ls180.v:13995.3-14007.6" - wire width 2 $1\LDST_dec62_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \LDST_dec62_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \LDST_dec62_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 6 \LDST_dec62_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \LDST_dec62_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \LDST_dec62_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 4 \LDST_dec62_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \LDST_dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 12 \LDST_dec62_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 7 \LDST_dec62_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 9 \LDST_dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 13 \LDST_dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 11 \LDST_dec62_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \LDST_dec62_upd - attribute \src "issuer_ls180.v:13671.7-13671.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 2 \opcode_switch - attribute \src "issuer_ls180.v:13671.7-13671.20" - process $proc$issuer_ls180.v:13671$293 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + update \dec30_sgn_ext $0\dec30_sgn_ext[0:0] end - attribute \src "issuer_ls180.v:13852.3-13864.6" - process $proc$issuer_ls180.v:13852$280 + attribute \src "libresoc.v:11208.3-11244.6" + process $proc$libresoc.v:11208$328 assign { } { } assign { } { } - assign $0\LDST_dec62_function_unit[11:0] $1\LDST_dec62_function_unit[11:0] - attribute \src "issuer_ls180.v:13853.5-13853.29" + assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] + attribute \src "libresoc.v:11209.5-11209.29" switch \initial - attribute \src "issuer_ls180.v:13853.9-13853.17" + attribute \src "libresoc.v:11209.9-11209.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } - assign $1\LDST_dec62_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 assign { } { } - assign $1\LDST_dec62_function_unit[11:0] 12'000000000100 + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 case - assign $1\LDST_dec62_function_unit[11:0] 12'000000000000 + assign $1\dec30_internal_op[6:0] 7'0000000 end sync always - update \LDST_dec62_function_unit $0\LDST_dec62_function_unit[11:0] + update \dec30_internal_op $0\dec30_internal_op[6:0] end - attribute \src "issuer_ls180.v:13865.3-13877.6" - process $proc$issuer_ls180.v:13865$281 + attribute \src "libresoc.v:11245.3-11281.6" + process $proc$libresoc.v:11245$329 assign { } { } assign { } { } - assign $0\LDST_dec62_br[0:0] $1\LDST_dec62_br[0:0] - attribute \src "issuer_ls180.v:13866.5-13866.29" + assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0] + attribute \src "libresoc.v:11246.5-11246.29" switch \initial - attribute \src "issuer_ls180.v:13866.9-13866.17" + attribute \src "libresoc.v:11246.9-11246.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } - assign $1\LDST_dec62_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 assign { } { } - assign $1\LDST_dec62_br[0:0] 1'0 + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 case - assign $1\LDST_dec62_br[0:0] 1'0 + assign $1\dec30_rsrv[0:0] 1'0 end sync always - update \LDST_dec62_br $0\LDST_dec62_br[0:0] + update \dec30_rsrv $0\dec30_rsrv[0:0] end - attribute \src "issuer_ls180.v:13878.3-13890.6" - process $proc$issuer_ls180.v:13878$282 + attribute \src "libresoc.v:11282.3-11318.6" + process $proc$libresoc.v:11282$330 assign { } { } assign { } { } - assign $0\LDST_dec62_sgn_ext[0:0] $1\LDST_dec62_sgn_ext[0:0] - attribute \src "issuer_ls180.v:13879.5-13879.29" + assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] + attribute \src "libresoc.v:11283.5-11283.29" switch \initial - attribute \src "issuer_ls180.v:13879.9-13879.17" + attribute \src "libresoc.v:11283.9-11283.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } - assign $1\LDST_dec62_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 assign { } { } - assign $1\LDST_dec62_sgn_ext[0:0] 1'0 + assign $1\dec30_is_32b[0:0] 1'0 case - assign $1\LDST_dec62_sgn_ext[0:0] 1'0 + assign $1\dec30_is_32b[0:0] 1'0 end sync always - update \LDST_dec62_sgn_ext $0\LDST_dec62_sgn_ext[0:0] + update \dec30_is_32b $0\dec30_is_32b[0:0] end - attribute \src "issuer_ls180.v:13891.3-13903.6" - process $proc$issuer_ls180.v:13891$283 + attribute \src "libresoc.v:11319.3-11355.6" + process $proc$libresoc.v:11319$331 assign { } { } assign { } { } - assign $0\LDST_dec62_is_32b[0:0] $1\LDST_dec62_is_32b[0:0] - attribute \src "issuer_ls180.v:13892.5-13892.29" + assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0] + attribute \src "libresoc.v:11320.5-11320.29" switch \initial - attribute \src "issuer_ls180.v:13892.9-13892.17" + attribute \src "libresoc.v:11320.9-11320.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } - assign $1\LDST_dec62_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 assign { } { } - assign $1\LDST_dec62_is_32b[0:0] 1'0 + assign $1\dec30_sgn[0:0] 1'0 case - assign $1\LDST_dec62_is_32b[0:0] 1'0 + assign $1\dec30_sgn[0:0] 1'0 end sync always - update \LDST_dec62_is_32b $0\LDST_dec62_is_32b[0:0] + update \dec30_sgn $0\dec30_sgn[0:0] end - attribute \src "issuer_ls180.v:13904.3-13916.6" - process $proc$issuer_ls180.v:13904$284 + attribute \src "libresoc.v:11356.3-11392.6" + process $proc$libresoc.v:11356$332 assign { } { } assign { } { } - assign $0\LDST_dec62_sgn[0:0] $1\LDST_dec62_sgn[0:0] - attribute \src "issuer_ls180.v:13905.5-13905.29" + assign $0\dec30_lk[0:0] $1\dec30_lk[0:0] + attribute \src "libresoc.v:11357.5-11357.29" switch \initial - attribute \src "issuer_ls180.v:13905.9-13905.17" + attribute \src "libresoc.v:11357.9-11357.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } - assign $1\LDST_dec62_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 assign { } { } - assign $1\LDST_dec62_sgn[0:0] 1'0 + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 case - assign $1\LDST_dec62_sgn[0:0] 1'0 + assign $1\dec30_lk[0:0] 1'0 end sync always - update \LDST_dec62_sgn $0\LDST_dec62_sgn[0:0] + update \dec30_lk $0\dec30_lk[0:0] end - attribute \src "issuer_ls180.v:13917.3-13929.6" - process $proc$issuer_ls180.v:13917$285 + attribute \src "libresoc.v:11393.3-11429.6" + process $proc$libresoc.v:11393$333 assign { } { } assign { } { } - assign $0\LDST_dec62_internal_op[6:0] $1\LDST_dec62_internal_op[6:0] - attribute \src "issuer_ls180.v:13918.5-13918.29" + assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:11394.5-11394.29" switch \initial - attribute \src "issuer_ls180.v:13918.9-13918.17" + attribute \src "libresoc.v:11394.9-11394.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } - assign $1\LDST_dec62_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 assign { } { } - assign $1\LDST_dec62_internal_op[6:0] 7'0100110 + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 case - assign $1\LDST_dec62_internal_op[6:0] 7'0000000 + assign $1\dec30_sgl_pipe[0:0] 1'0 end sync always - update \LDST_dec62_internal_op $0\LDST_dec62_internal_op[6:0] + update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0] end - attribute \src "issuer_ls180.v:13930.3-13942.6" - process $proc$issuer_ls180.v:13930$286 + attribute \src "libresoc.v:11430.3-11466.6" + process $proc$libresoc.v:11430$334 assign { } { } assign { } { } - assign $0\LDST_dec62_in1_sel[2:0] $1\LDST_dec62_in1_sel[2:0] - attribute \src "issuer_ls180.v:13931.5-13931.29" + assign $0\dec30_form[4:0] $1\dec30_form[4:0] + attribute \src "libresoc.v:11431.5-11431.29" switch \initial - attribute \src "issuer_ls180.v:13931.9-13931.17" + attribute \src "libresoc.v:11431.9-11431.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } - assign $1\LDST_dec62_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_form[4:0] 5'10101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_form[4:0] 5'10101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 assign { } { } - assign $1\LDST_dec62_in1_sel[2:0] 3'010 + assign $1\dec30_form[4:0] 5'10100 case - assign $1\LDST_dec62_in1_sel[2:0] 3'000 + assign $1\dec30_form[4:0] 5'00000 end sync always - update \LDST_dec62_in1_sel $0\LDST_dec62_in1_sel[2:0] + update \dec30_form $0\dec30_form[4:0] end - attribute \src "issuer_ls180.v:13943.3-13955.6" - process $proc$issuer_ls180.v:13943$287 + attribute \src "libresoc.v:11467.3-11503.6" + process $proc$libresoc.v:11467$335 assign { } { } assign { } { } - assign $0\LDST_dec62_in2_sel[3:0] $1\LDST_dec62_in2_sel[3:0] - attribute \src "issuer_ls180.v:13944.5-13944.29" + assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0] + attribute \src "libresoc.v:11468.5-11468.29" switch \initial - attribute \src "issuer_ls180.v:13944.9-13944.17" + attribute \src "libresoc.v:11468.9-11468.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } - assign $1\LDST_dec62_in2_sel[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 assign { } { } - assign $1\LDST_dec62_in2_sel[3:0] 4'1000 + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 case - assign $1\LDST_dec62_in2_sel[3:0] 4'0000 + assign $1\dec30_in1_sel[2:0] 3'000 end sync always - update \LDST_dec62_in2_sel $0\LDST_dec62_in2_sel[3:0] + update \dec30_in1_sel $0\dec30_in1_sel[2:0] end - attribute \src "issuer_ls180.v:13956.3-13968.6" - process $proc$issuer_ls180.v:13956$288 + attribute \src "libresoc.v:11504.3-11540.6" + process $proc$libresoc.v:11504$336 assign { } { } assign { } { } - assign $0\LDST_dec62_cr_in[2:0] $1\LDST_dec62_cr_in[2:0] - attribute \src "issuer_ls180.v:13957.5-13957.29" + assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0] + attribute \src "libresoc.v:11505.5-11505.29" switch \initial - attribute \src "issuer_ls180.v:13957.9-13957.17" + attribute \src "libresoc.v:11505.9-11505.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } - assign $1\LDST_dec62_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 assign { } { } - assign $1\LDST_dec62_cr_in[2:0] 3'000 + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'0001 case - assign $1\LDST_dec62_cr_in[2:0] 3'000 + assign $1\dec30_in2_sel[3:0] 4'0000 end sync always - update \LDST_dec62_cr_in $0\LDST_dec62_cr_in[2:0] + update \dec30_in2_sel $0\dec30_in2_sel[3:0] end - attribute \src "issuer_ls180.v:13969.3-13981.6" - process $proc$issuer_ls180.v:13969$289 + attribute \src "libresoc.v:11541.3-11577.6" + process $proc$libresoc.v:11541$337 assign { } { } assign { } { } - assign $0\LDST_dec62_cr_out[2:0] $1\LDST_dec62_cr_out[2:0] - attribute \src "issuer_ls180.v:13970.5-13970.29" + assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0] + attribute \src "libresoc.v:11542.5-11542.29" switch \initial - attribute \src "issuer_ls180.v:13970.9-13970.17" + attribute \src "libresoc.v:11542.9-11542.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } - assign $1\LDST_dec62_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 assign { } { } - assign $1\LDST_dec62_cr_out[2:0] 3'000 + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 case - assign $1\LDST_dec62_cr_out[2:0] 3'000 + assign $1\dec30_in3_sel[1:0] 2'00 end sync always - update \LDST_dec62_cr_out $0\LDST_dec62_cr_out[2:0] + update \dec30_in3_sel $0\dec30_in3_sel[1:0] end - attribute \src "issuer_ls180.v:13982.3-13994.6" - process $proc$issuer_ls180.v:13982$290 + attribute \src "libresoc.v:11578.3-11614.6" + process $proc$libresoc.v:11578$338 assign { } { } assign { } { } - assign $0\LDST_dec62_ldst_len[3:0] $1\LDST_dec62_ldst_len[3:0] - attribute \src "issuer_ls180.v:13983.5-13983.29" + assign $0\dec30_out_sel[1:0] $1\dec30_out_sel[1:0] + attribute \src "libresoc.v:11579.5-11579.29" switch \initial - attribute \src "issuer_ls180.v:13983.9-13983.17" + attribute \src "libresoc.v:11579.9-11579.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } - assign $1\LDST_dec62_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 assign { } { } - assign $1\LDST_dec62_ldst_len[3:0] 4'1000 + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 case - assign $1\LDST_dec62_ldst_len[3:0] 4'0000 + assign $1\dec30_out_sel[1:0] 2'00 end sync always - update \LDST_dec62_ldst_len $0\LDST_dec62_ldst_len[3:0] + update \dec30_out_sel $0\dec30_out_sel[1:0] end - attribute \src "issuer_ls180.v:13995.3-14007.6" - process $proc$issuer_ls180.v:13995$291 + attribute \src "libresoc.v:11615.3-11651.6" + process $proc$libresoc.v:11615$339 assign { } { } assign { } { } - assign $0\LDST_dec62_upd[1:0] $1\LDST_dec62_upd[1:0] - attribute \src "issuer_ls180.v:13996.5-13996.29" + assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0] + attribute \src "libresoc.v:11616.5-11616.29" switch \initial - attribute \src "issuer_ls180.v:13996.9-13996.17" + attribute \src "libresoc.v:11616.9-11616.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } - assign $1\LDST_dec62_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 assign { } { } - assign $1\LDST_dec62_upd[1:0] 2'01 + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 case - assign $1\LDST_dec62_upd[1:0] 2'00 + assign $1\dec30_cr_in[2:0] 3'000 end sync always - update \LDST_dec62_upd $0\LDST_dec62_upd[1:0] + update \dec30_cr_in $0\dec30_cr_in[2:0] end - attribute \src "issuer_ls180.v:14008.3-14020.6" - process $proc$issuer_ls180.v:14008$292 + attribute \src "libresoc.v:11652.3-11688.6" + process $proc$libresoc.v:11652$340 assign { } { } assign { } { } - assign $0\LDST_dec62_rc_sel[1:0] $1\LDST_dec62_rc_sel[1:0] - attribute \src "issuer_ls180.v:14009.5-14009.29" + assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0] + attribute \src "libresoc.v:11653.5-11653.29" switch \initial - attribute \src "issuer_ls180.v:14009.9-14009.17" + attribute \src "libresoc.v:11653.9-11653.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } - assign $1\LDST_dec62_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 assign { } { } - assign $1\LDST_dec62_rc_sel[1:0] 2'00 + assign $1\dec30_cr_out[2:0] 3'001 case - assign $1\LDST_dec62_rc_sel[1:0] 2'00 + assign $1\dec30_cr_out[2:0] 3'000 end sync always - update \LDST_dec62_rc_sel $0\LDST_dec62_rc_sel[1:0] + update \dec30_cr_out $0\dec30_cr_out[2:0] end - connect \opcode_switch \opcode_in [1:0] + connect \opcode_switch \opcode_in [4:1] end -attribute \src "issuer_ls180.v:14026.1-14764.10" +attribute \src "libresoc.v:11694.1-18064.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31" attribute \generator "nMigen" -module \LOGICAL_dec31 - attribute \src "issuer_ls180.v:14734.3-14746.6" - wire width 3 $0\LOGICAL_dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:14747.3-14759.6" - wire width 3 $0\LOGICAL_dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:14604.3-14616.6" - wire width 2 $0\LOGICAL_dec31_cry_in[1:0] - attribute \src "issuer_ls180.v:14643.3-14655.6" - wire $0\LOGICAL_dec31_cry_out[0:0] - attribute \src "issuer_ls180.v:14682.3-14694.6" - wire width 12 $0\LOGICAL_dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:14708.3-14720.6" - wire width 3 $0\LOGICAL_dec31_in1_sel[2:0] - attribute \src "issuer_ls180.v:14721.3-14733.6" - wire width 4 $0\LOGICAL_dec31_in2_sel[3:0] - attribute \src "issuer_ls180.v:14695.3-14707.6" - wire width 7 $0\LOGICAL_dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:14617.3-14629.6" - wire $0\LOGICAL_dec31_inv_a[0:0] - attribute \src "issuer_ls180.v:14630.3-14642.6" - wire $0\LOGICAL_dec31_inv_out[0:0] - attribute \src "issuer_ls180.v:14656.3-14668.6" - wire $0\LOGICAL_dec31_is_32b[0:0] - attribute \src "issuer_ls180.v:14578.3-14590.6" - wire width 4 $0\LOGICAL_dec31_ldst_len[3:0] - attribute \src "issuer_ls180.v:14591.3-14603.6" - wire width 2 $0\LOGICAL_dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:14669.3-14681.6" - wire $0\LOGICAL_dec31_sgn[0:0] - attribute \src "issuer_ls180.v:14027.7-14027.20" +module \dec31 + attribute \src "libresoc.v:16763.3-16823.6" + wire width 8 $0\dec31_asmcode[7:0] + attribute \src "libresoc.v:17617.3-17677.6" + wire $0\dec31_br[0:0] + attribute \src "libresoc.v:17068.3-17128.6" + wire width 3 $0\dec31_cr_in[2:0] + attribute \src "libresoc.v:17129.3-17189.6" + wire width 3 $0\dec31_cr_out[2:0] + attribute \src "libresoc.v:17373.3-17433.6" + wire width 2 $0\dec31_cry_in[1:0] + attribute \src "libresoc.v:17556.3-17616.6" + wire $0\dec31_cry_out[0:0] + attribute \src "libresoc.v:16702.3-16762.6" + wire width 5 $0\dec31_form[4:0] + attribute \src "libresoc.v:16580.3-16640.6" + wire width 12 $0\dec31_function_unit[11:0] + attribute \src "libresoc.v:16824.3-16884.6" + wire width 3 $0\dec31_in1_sel[2:0] + attribute \src "libresoc.v:16885.3-16945.6" + wire width 4 $0\dec31_in2_sel[3:0] + attribute \src "libresoc.v:16946.3-17006.6" + wire width 2 $0\dec31_in3_sel[1:0] + attribute \src "libresoc.v:16641.3-16701.6" + wire width 7 $0\dec31_internal_op[6:0] + attribute \src "libresoc.v:17434.3-17494.6" + wire $0\dec31_inv_a[0:0] + attribute \src "libresoc.v:17495.3-17555.6" + wire $0\dec31_inv_out[0:0] + attribute \src "libresoc.v:17800.3-17860.6" + wire $0\dec31_is_32b[0:0] + attribute \src "libresoc.v:17190.3-17250.6" + wire width 4 $0\dec31_ldst_len[3:0] + attribute \src "libresoc.v:17922.3-17982.6" + wire $0\dec31_lk[0:0] + attribute \src "libresoc.v:17007.3-17067.6" + wire width 2 $0\dec31_out_sel[1:0] + attribute \src "libresoc.v:17312.3-17372.6" + wire width 2 $0\dec31_rc_sel[1:0] + attribute \src "libresoc.v:17739.3-17799.6" + wire $0\dec31_rsrv[0:0] + attribute \src "libresoc.v:17983.3-18043.6" + wire $0\dec31_sgl_pipe[0:0] + attribute \src "libresoc.v:17861.3-17921.6" + wire $0\dec31_sgn[0:0] + attribute \src "libresoc.v:17678.3-17738.6" + wire $0\dec31_sgn_ext[0:0] + attribute \src "libresoc.v:17251.3-17311.6" + wire width 2 $0\dec31_upd[1:0] + attribute \src "libresoc.v:11695.7-11695.20" wire $0\initial[0:0] - attribute \src "issuer_ls180.v:14734.3-14746.6" - wire width 3 $1\LOGICAL_dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:14747.3-14759.6" - wire width 3 $1\LOGICAL_dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:14604.3-14616.6" - wire width 2 $1\LOGICAL_dec31_cry_in[1:0] - attribute \src "issuer_ls180.v:14643.3-14655.6" - wire $1\LOGICAL_dec31_cry_out[0:0] - attribute \src "issuer_ls180.v:14682.3-14694.6" - wire width 12 $1\LOGICAL_dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:14708.3-14720.6" - wire width 3 $1\LOGICAL_dec31_in1_sel[2:0] - attribute \src "issuer_ls180.v:14721.3-14733.6" - wire width 4 $1\LOGICAL_dec31_in2_sel[3:0] - attribute \src "issuer_ls180.v:14695.3-14707.6" - wire width 7 $1\LOGICAL_dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:14617.3-14629.6" - wire $1\LOGICAL_dec31_inv_a[0:0] - attribute \src "issuer_ls180.v:14630.3-14642.6" - wire $1\LOGICAL_dec31_inv_out[0:0] - attribute \src "issuer_ls180.v:14656.3-14668.6" - wire $1\LOGICAL_dec31_is_32b[0:0] - attribute \src "issuer_ls180.v:14578.3-14590.6" - wire width 4 $1\LOGICAL_dec31_ldst_len[3:0] - attribute \src "issuer_ls180.v:14591.3-14603.6" - wire width 2 $1\LOGICAL_dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:14669.3-14681.6" - wire $1\LOGICAL_dec31_sgn[0:0] + attribute \src "libresoc.v:16763.3-16823.6" + wire width 8 $1\dec31_asmcode[7:0] + attribute \src "libresoc.v:17617.3-17677.6" + wire $1\dec31_br[0:0] + attribute \src "libresoc.v:17068.3-17128.6" + wire width 3 $1\dec31_cr_in[2:0] + attribute \src "libresoc.v:17129.3-17189.6" + wire width 3 $1\dec31_cr_out[2:0] + attribute \src "libresoc.v:17373.3-17433.6" + wire width 2 $1\dec31_cry_in[1:0] + attribute \src "libresoc.v:17556.3-17616.6" + wire $1\dec31_cry_out[0:0] + attribute \src "libresoc.v:16702.3-16762.6" + wire width 5 $1\dec31_form[4:0] + attribute \src "libresoc.v:16580.3-16640.6" + wire width 12 $1\dec31_function_unit[11:0] + attribute \src "libresoc.v:16824.3-16884.6" + wire width 3 $1\dec31_in1_sel[2:0] + attribute \src "libresoc.v:16885.3-16945.6" + wire width 4 $1\dec31_in2_sel[3:0] + attribute \src "libresoc.v:16946.3-17006.6" + wire width 2 $1\dec31_in3_sel[1:0] + attribute \src "libresoc.v:16641.3-16701.6" + wire width 7 $1\dec31_internal_op[6:0] + attribute \src "libresoc.v:17434.3-17494.6" + wire $1\dec31_inv_a[0:0] + attribute \src "libresoc.v:17495.3-17555.6" + wire $1\dec31_inv_out[0:0] + attribute \src "libresoc.v:17800.3-17860.6" + wire $1\dec31_is_32b[0:0] + attribute \src "libresoc.v:17190.3-17250.6" + wire width 4 $1\dec31_ldst_len[3:0] + attribute \src "libresoc.v:17922.3-17982.6" + wire $1\dec31_lk[0:0] + attribute \src "libresoc.v:17007.3-17067.6" + wire width 2 $1\dec31_out_sel[1:0] + attribute \src "libresoc.v:17312.3-17372.6" + wire width 2 $1\dec31_rc_sel[1:0] + attribute \src "libresoc.v:17739.3-17799.6" + wire $1\dec31_rsrv[0:0] + attribute \src "libresoc.v:17983.3-18043.6" + wire $1\dec31_sgl_pipe[0:0] + attribute \src "libresoc.v:17861.3-17921.6" + wire $1\dec31_sgn[0:0] + attribute \src "libresoc.v:17678.3-17738.6" + wire $1\dec31_sgn_ext[0:0] + attribute \src "libresoc.v:17251.3-17311.6" + wire width 2 $1\dec31_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -20268,7 +17853,7 @@ module \LOGICAL_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \LOGICAL_dec31_cr_in + wire width 3 output 9 \dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -20276,15 +17861,19 @@ module \LOGICAL_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 6 \LOGICAL_dec31_cr_out + wire width 3 output 10 \dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 9 \LOGICAL_dec31_cry_in + wire width 2 output 14 \dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub0_dec31_dec_sub0_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 12 \LOGICAL_dec31_cry_out + wire \dec31_dec_sub0_dec31_dec_sub0_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -20294,7 +17883,7 @@ module \LOGICAL_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -20302,15 +17891,47 @@ module \LOGICAL_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out + wire \dec31_dec_sub0_dec31_dec_sub0_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub0_dec31_dec_sub0_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -20325,7 +17946,7 @@ module \LOGICAL_dec31 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit + wire width 12 \dec31_dec_sub0_dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -20333,7 +17954,7 @@ module \LOGICAL_dec31 attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -20350,7 +17971,13 @@ module \LOGICAL_dec31 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel + wire width 4 \dec31_dec_sub0_dec31_dec_sub0_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -20426,13 +18053,13 @@ module \LOGICAL_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op + wire width 7 \dec31_dec_sub0_dec31_dec_sub0_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a + wire \dec31_dec_sub0_dec31_dec_sub0_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out + wire \dec31_dec_sub0_dec31_dec_sub0_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b + wire \dec31_dec_sub0_dec31_dec_sub0_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -20440,17 +18067,43 @@ module \LOGICAL_dec31 attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len + wire width 4 \dec31_dec_sub0_dec31_dec_sub0_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn + wire \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \LOGICAL_dec31_dec_sub26_opcode_in + wire width 32 \dec31_dec_sub0_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub10_dec31_dec_sub10_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -20460,7 +18113,7 @@ module \LOGICAL_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in + wire width 3 \dec31_dec_sub10_dec31_dec_sub10_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -20468,15 +18121,47 @@ module \LOGICAL_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out + wire width 3 \dec31_dec_sub10_dec31_dec_sub10_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in + wire width 2 \dec31_dec_sub10_dec31_dec_sub10_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out + wire \dec31_dec_sub10_dec31_dec_sub10_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub10_dec31_dec_sub10_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -20491,7 +18176,7 @@ module \LOGICAL_dec31 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit + wire width 12 \dec31_dec_sub10_dec31_dec_sub10_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -20499,7 +18184,7 @@ module \LOGICAL_dec31 attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel + wire width 3 \dec31_dec_sub10_dec31_dec_sub10_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -20516,7 +18201,13 @@ module \LOGICAL_dec31 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel + wire width 4 \dec31_dec_sub10_dec31_dec_sub10_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub10_dec31_dec_sub10_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -20592,13 +18283,13 @@ module \LOGICAL_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op + wire width 7 \dec31_dec_sub10_dec31_dec_sub10_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a + wire \dec31_dec_sub10_dec31_dec_sub10_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out + wire \dec31_dec_sub10_dec31_dec_sub10_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b + wire \dec31_dec_sub10_dec31_dec_sub10_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -20606,57 +18297,147 @@ module \LOGICAL_dec31 attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len + wire width 4 \dec31_dec_sub10_dec31_dec_sub10_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub10_dec31_dec_sub10_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel + wire width 2 \dec31_dec_sub10_dec31_dec_sub10_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn + wire \dec31_dec_sub10_dec31_dec_sub10_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub10_dec31_dec_sub10_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \LOGICAL_dec31_dec_sub28_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" + wire width 32 \dec31_dec_sub10_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \LOGICAL_dec31_function_unit - attribute \enum_base_type "In1Sel" + wire width 8 \dec31_dec_sub11_dec31_dec_sub11_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_br + attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \LOGICAL_dec31_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" + wire width 3 \dec31_dec_sub11_dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub11_dec31_dec_sub11_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub11_dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub11_dec31_dec_sub11_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub11_dec31_dec_sub11_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub11_dec31_dec_sub11_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 4 \LOGICAL_dec31_in2_sel + wire width 4 \dec31_dec_sub11_dec31_dec_sub11_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub11_dec31_dec_sub11_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -20732,13 +18513,13 @@ module \LOGICAL_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \LOGICAL_dec31_internal_op + wire width 7 \dec31_dec_sub11_dec31_dec_sub11_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \LOGICAL_dec31_inv_a + wire \dec31_dec_sub11_dec31_dec_sub11_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 11 \LOGICAL_dec31_inv_out + wire \dec31_dec_sub11_dec31_dec_sub11_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 13 \LOGICAL_dec31_is_32b + wire \dec31_dec_sub11_dec31_dec_sub11_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -20746,515 +18527,43 @@ module \LOGICAL_dec31 attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 7 \LOGICAL_dec31_ldst_len + wire width 4 \dec31_dec_sub11_dec31_dec_sub11_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub11_dec31_dec_sub11_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \LOGICAL_dec31_rc_sel + wire width 2 \dec31_dec_sub11_dec31_dec_sub11_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 14 \LOGICAL_dec31_sgn - attribute \src "issuer_ls180.v:14027.7-14027.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" - wire width 5 \opc_in + wire \dec31_dec_sub11_dec31_dec_sub11_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub11_dec31_dec_sub11_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 10 \opcode_switch - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:14544.27-14560.4" - cell \LOGICAL_dec31_dec_sub26 \LOGICAL_dec31_dec_sub26 - connect \LOGICAL_dec31_dec_sub26_cr_in \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in - connect \LOGICAL_dec31_dec_sub26_cr_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out - connect \LOGICAL_dec31_dec_sub26_cry_in \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in - connect \LOGICAL_dec31_dec_sub26_cry_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out - connect \LOGICAL_dec31_dec_sub26_function_unit \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit - connect \LOGICAL_dec31_dec_sub26_in1_sel \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel - connect \LOGICAL_dec31_dec_sub26_in2_sel \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel - connect \LOGICAL_dec31_dec_sub26_internal_op \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op - connect \LOGICAL_dec31_dec_sub26_inv_a \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a - connect \LOGICAL_dec31_dec_sub26_inv_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out - connect \LOGICAL_dec31_dec_sub26_is_32b \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b - connect \LOGICAL_dec31_dec_sub26_ldst_len \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len - connect \LOGICAL_dec31_dec_sub26_rc_sel \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel - connect \LOGICAL_dec31_dec_sub26_sgn \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn - connect \opcode_in \LOGICAL_dec31_dec_sub26_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:14561.27-14577.4" - cell \LOGICAL_dec31_dec_sub28 \LOGICAL_dec31_dec_sub28 - connect \LOGICAL_dec31_dec_sub28_cr_in \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in - connect \LOGICAL_dec31_dec_sub28_cr_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out - connect \LOGICAL_dec31_dec_sub28_cry_in \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in - connect \LOGICAL_dec31_dec_sub28_cry_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out - connect \LOGICAL_dec31_dec_sub28_function_unit \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit - connect \LOGICAL_dec31_dec_sub28_in1_sel \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel - connect \LOGICAL_dec31_dec_sub28_in2_sel \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel - connect \LOGICAL_dec31_dec_sub28_internal_op \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op - connect \LOGICAL_dec31_dec_sub28_inv_a \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a - connect \LOGICAL_dec31_dec_sub28_inv_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out - connect \LOGICAL_dec31_dec_sub28_is_32b \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b - connect \LOGICAL_dec31_dec_sub28_ldst_len \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len - connect \LOGICAL_dec31_dec_sub28_rc_sel \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel - connect \LOGICAL_dec31_dec_sub28_sgn \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn - connect \opcode_in \LOGICAL_dec31_dec_sub28_opcode_in - end - attribute \src "issuer_ls180.v:14027.7-14027.20" - process $proc$issuer_ls180.v:14027$308 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:14578.3-14590.6" - process $proc$issuer_ls180.v:14578$294 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_ldst_len[3:0] $1\LOGICAL_dec31_ldst_len[3:0] - attribute \src "issuer_ls180.v:14579.5-14579.29" - switch \initial - attribute \src "issuer_ls180.v:14579.9-14579.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_ldst_len[3:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_ldst_len[3:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len - case - assign $1\LOGICAL_dec31_ldst_len[3:0] 4'0000 - end - sync always - update \LOGICAL_dec31_ldst_len $0\LOGICAL_dec31_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:14591.3-14603.6" - process $proc$issuer_ls180.v:14591$295 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_rc_sel[1:0] $1\LOGICAL_dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:14592.5-14592.29" - switch \initial - attribute \src "issuer_ls180.v:14592.9-14592.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_rc_sel[1:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_rc_sel[1:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel - case - assign $1\LOGICAL_dec31_rc_sel[1:0] 2'00 - end - sync always - update \LOGICAL_dec31_rc_sel $0\LOGICAL_dec31_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:14604.3-14616.6" - process $proc$issuer_ls180.v:14604$296 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_cry_in[1:0] $1\LOGICAL_dec31_cry_in[1:0] - attribute \src "issuer_ls180.v:14605.5-14605.29" - switch \initial - attribute \src "issuer_ls180.v:14605.9-14605.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_cry_in[1:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_cry_in[1:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in - case - assign $1\LOGICAL_dec31_cry_in[1:0] 2'00 - end - sync always - update \LOGICAL_dec31_cry_in $0\LOGICAL_dec31_cry_in[1:0] - end - attribute \src "issuer_ls180.v:14617.3-14629.6" - process $proc$issuer_ls180.v:14617$297 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_inv_a[0:0] $1\LOGICAL_dec31_inv_a[0:0] - attribute \src "issuer_ls180.v:14618.5-14618.29" - switch \initial - attribute \src "issuer_ls180.v:14618.9-14618.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_inv_a[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_inv_a[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a - case - assign $1\LOGICAL_dec31_inv_a[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_inv_a $0\LOGICAL_dec31_inv_a[0:0] - end - attribute \src "issuer_ls180.v:14630.3-14642.6" - process $proc$issuer_ls180.v:14630$298 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_inv_out[0:0] $1\LOGICAL_dec31_inv_out[0:0] - attribute \src "issuer_ls180.v:14631.5-14631.29" - switch \initial - attribute \src "issuer_ls180.v:14631.9-14631.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_inv_out[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_inv_out[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out - case - assign $1\LOGICAL_dec31_inv_out[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_inv_out $0\LOGICAL_dec31_inv_out[0:0] - end - attribute \src "issuer_ls180.v:14643.3-14655.6" - process $proc$issuer_ls180.v:14643$299 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_cry_out[0:0] $1\LOGICAL_dec31_cry_out[0:0] - attribute \src "issuer_ls180.v:14644.5-14644.29" - switch \initial - attribute \src "issuer_ls180.v:14644.9-14644.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_cry_out[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_cry_out[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out - case - assign $1\LOGICAL_dec31_cry_out[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_cry_out $0\LOGICAL_dec31_cry_out[0:0] - end - attribute \src "issuer_ls180.v:14656.3-14668.6" - process $proc$issuer_ls180.v:14656$300 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_is_32b[0:0] $1\LOGICAL_dec31_is_32b[0:0] - attribute \src "issuer_ls180.v:14657.5-14657.29" - switch \initial - attribute \src "issuer_ls180.v:14657.9-14657.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_is_32b[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_is_32b[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b - case - assign $1\LOGICAL_dec31_is_32b[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_is_32b $0\LOGICAL_dec31_is_32b[0:0] - end - attribute \src "issuer_ls180.v:14669.3-14681.6" - process $proc$issuer_ls180.v:14669$301 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_sgn[0:0] $1\LOGICAL_dec31_sgn[0:0] - attribute \src "issuer_ls180.v:14670.5-14670.29" - switch \initial - attribute \src "issuer_ls180.v:14670.9-14670.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_sgn[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_sgn[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn - case - assign $1\LOGICAL_dec31_sgn[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_sgn $0\LOGICAL_dec31_sgn[0:0] - end - attribute \src "issuer_ls180.v:14682.3-14694.6" - process $proc$issuer_ls180.v:14682$302 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_function_unit[11:0] $1\LOGICAL_dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:14683.5-14683.29" - switch \initial - attribute \src "issuer_ls180.v:14683.9-14683.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_function_unit[11:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_function_unit[11:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit - case - assign $1\LOGICAL_dec31_function_unit[11:0] 12'000000000000 - end - sync always - update \LOGICAL_dec31_function_unit $0\LOGICAL_dec31_function_unit[11:0] - end - attribute \src "issuer_ls180.v:14695.3-14707.6" - process $proc$issuer_ls180.v:14695$303 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_internal_op[6:0] $1\LOGICAL_dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:14696.5-14696.29" - switch \initial - attribute \src "issuer_ls180.v:14696.9-14696.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_internal_op[6:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_internal_op[6:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op - case - assign $1\LOGICAL_dec31_internal_op[6:0] 7'0000000 - end - sync always - update \LOGICAL_dec31_internal_op $0\LOGICAL_dec31_internal_op[6:0] - end - attribute \src "issuer_ls180.v:14708.3-14720.6" - process $proc$issuer_ls180.v:14708$304 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_in1_sel[2:0] $1\LOGICAL_dec31_in1_sel[2:0] - attribute \src "issuer_ls180.v:14709.5-14709.29" - switch \initial - attribute \src "issuer_ls180.v:14709.9-14709.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_in1_sel[2:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_in1_sel[2:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel - case - assign $1\LOGICAL_dec31_in1_sel[2:0] 3'000 - end - sync always - update \LOGICAL_dec31_in1_sel $0\LOGICAL_dec31_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:14721.3-14733.6" - process $proc$issuer_ls180.v:14721$305 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_in2_sel[3:0] $1\LOGICAL_dec31_in2_sel[3:0] - attribute \src "issuer_ls180.v:14722.5-14722.29" - switch \initial - attribute \src "issuer_ls180.v:14722.9-14722.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_in2_sel[3:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_in2_sel[3:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel - case - assign $1\LOGICAL_dec31_in2_sel[3:0] 4'0000 - end - sync always - update \LOGICAL_dec31_in2_sel $0\LOGICAL_dec31_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:14734.3-14746.6" - process $proc$issuer_ls180.v:14734$306 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_cr_in[2:0] $1\LOGICAL_dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:14735.5-14735.29" - switch \initial - attribute \src "issuer_ls180.v:14735.9-14735.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_cr_in[2:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_cr_in[2:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in - case - assign $1\LOGICAL_dec31_cr_in[2:0] 3'000 - end - sync always - update \LOGICAL_dec31_cr_in $0\LOGICAL_dec31_cr_in[2:0] - end - attribute \src "issuer_ls180.v:14747.3-14759.6" - process $proc$issuer_ls180.v:14747$307 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_cr_out[2:0] $1\LOGICAL_dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:14748.5-14748.29" - switch \initial - attribute \src "issuer_ls180.v:14748.9-14748.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_cr_out[2:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_cr_out[2:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out - case - assign $1\LOGICAL_dec31_cr_out[2:0] 3'000 - end - sync always - update \LOGICAL_dec31_cr_out $0\LOGICAL_dec31_cr_out[2:0] - end - connect \LOGICAL_dec31_dec_sub26_opcode_in \opcode_in - connect \LOGICAL_dec31_dec_sub28_opcode_in \opcode_in - connect \opc_in \opcode_switch [4:0] - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "issuer_ls180.v:14768.1-15429.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub26" -attribute \generator "nMigen" -module \LOGICAL_dec31_dec_sub26 - attribute \src "issuer_ls180.v:15258.3-15291.6" - wire width 3 $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] - attribute \src "issuer_ls180.v:15292.3-15325.6" - wire width 3 $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] - attribute \src "issuer_ls180.v:15394.3-15427.6" - wire width 2 $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] - attribute \src "issuer_ls180.v:15054.3-15087.6" - wire $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] - attribute \src "issuer_ls180.v:14952.3-14985.6" - wire width 12 $0\LOGICAL_dec31_dec_sub26_function_unit[11:0] - attribute \src "issuer_ls180.v:15190.3-15223.6" - wire width 3 $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] - attribute \src "issuer_ls180.v:15224.3-15257.6" - wire width 4 $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] - attribute \src "issuer_ls180.v:15156.3-15189.6" - wire width 7 $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] - attribute \src "issuer_ls180.v:14986.3-15019.6" - wire $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] - attribute \src "issuer_ls180.v:15020.3-15053.6" - wire $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] - attribute \src "issuer_ls180.v:15088.3-15121.6" - wire $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] - attribute \src "issuer_ls180.v:15326.3-15359.6" - wire width 4 $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] - attribute \src "issuer_ls180.v:15360.3-15393.6" - wire width 2 $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] - attribute \src "issuer_ls180.v:15122.3-15155.6" - wire $0\LOGICAL_dec31_dec_sub26_sgn[0:0] - attribute \src "issuer_ls180.v:14769.7-14769.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:15258.3-15291.6" - wire width 3 $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] - attribute \src "issuer_ls180.v:15292.3-15325.6" - wire width 3 $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] - attribute \src "issuer_ls180.v:15394.3-15427.6" - wire width 2 $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] - attribute \src "issuer_ls180.v:15054.3-15087.6" - wire $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] - attribute \src "issuer_ls180.v:14952.3-14985.6" - wire width 12 $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] - attribute \src "issuer_ls180.v:15190.3-15223.6" - wire width 3 $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] - attribute \src "issuer_ls180.v:15224.3-15257.6" - wire width 4 $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] - attribute \src "issuer_ls180.v:15156.3-15189.6" - wire width 7 $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] - attribute \src "issuer_ls180.v:14986.3-15019.6" - wire $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] - attribute \src "issuer_ls180.v:15020.3-15053.6" - wire $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] - attribute \src "issuer_ls180.v:15088.3-15121.6" - wire $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] - attribute \src "issuer_ls180.v:15326.3-15359.6" - wire width 4 $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] - attribute \src "issuer_ls180.v:15360.3-15393.6" - wire width 2 $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] - attribute \src "issuer_ls180.v:15122.3-15155.6" - wire $1\LOGICAL_dec31_dec_sub26_sgn[0:0] + wire width 32 \dec31_dec_sub11_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub15_dec31_dec_sub15_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -21264,7 +18573,7 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \LOGICAL_dec31_dec_sub26_cr_in + wire width 3 \dec31_dec_sub15_dec31_dec_sub15_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -21272,15 +18581,47 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 6 \LOGICAL_dec31_dec_sub26_cr_out + wire width 3 \dec31_dec_sub15_dec31_dec_sub15_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 9 \LOGICAL_dec31_dec_sub26_cry_in + wire width 2 \dec31_dec_sub15_dec31_dec_sub15_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 12 \LOGICAL_dec31_dec_sub26_cry_out + wire \dec31_dec_sub15_dec31_dec_sub15_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub15_dec31_dec_sub15_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -21295,7 +18636,7 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \LOGICAL_dec31_dec_sub26_function_unit + wire width 12 \dec31_dec_sub15_dec31_dec_sub15_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -21303,7 +18644,7 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \LOGICAL_dec31_dec_sub26_in1_sel + wire width 3 \dec31_dec_sub15_dec31_dec_sub15_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -21320,7 +18661,13 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 4 \LOGICAL_dec31_dec_sub26_in2_sel + wire width 4 \dec31_dec_sub15_dec31_dec_sub15_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub15_dec31_dec_sub15_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -21396,13 +18743,13 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \LOGICAL_dec31_dec_sub26_internal_op + wire width 7 \dec31_dec_sub15_dec31_dec_sub15_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \LOGICAL_dec31_dec_sub26_inv_a + wire \dec31_dec_sub15_dec31_dec_sub15_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 11 \LOGICAL_dec31_dec_sub26_inv_out + wire \dec31_dec_sub15_dec31_dec_sub15_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 13 \LOGICAL_dec31_dec_sub26_is_32b + wire \dec31_dec_sub15_dec31_dec_sub15_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -21410,864 +18757,43 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 7 \LOGICAL_dec31_dec_sub26_ldst_len + wire width 4 \dec31_dec_sub15_dec31_dec_sub15_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub15_dec31_dec_sub15_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \LOGICAL_dec31_dec_sub26_rc_sel + wire width 2 \dec31_dec_sub15_dec31_dec_sub15_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 14 \LOGICAL_dec31_dec_sub26_sgn - attribute \src "issuer_ls180.v:14769.7-14769.15" - wire \initial + wire \dec31_dec_sub15_dec31_dec_sub15_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub15_dec31_dec_sub15_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:14769.7-14769.20" - process $proc$issuer_ls180.v:14769$323 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:14952.3-14985.6" - process $proc$issuer_ls180.v:14952$309 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_function_unit[11:0] $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] - attribute \src "issuer_ls180.v:14953.5-14953.29" - switch \initial - attribute \src "issuer_ls180.v:14953.9-14953.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 - case - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000000000 - end - sync always - update \LOGICAL_dec31_dec_sub26_function_unit $0\LOGICAL_dec31_dec_sub26_function_unit[11:0] - end - attribute \src "issuer_ls180.v:14986.3-15019.6" - process $proc$issuer_ls180.v:14986$310 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] - attribute \src "issuer_ls180.v:14987.5-14987.29" - switch \initial - attribute \src "issuer_ls180.v:14987.9-14987.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 - case - assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_dec_sub26_inv_a $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] - end - attribute \src "issuer_ls180.v:15020.3-15053.6" - process $proc$issuer_ls180.v:15020$311 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] - attribute \src "issuer_ls180.v:15021.5-15021.29" - switch \initial - attribute \src "issuer_ls180.v:15021.9-15021.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 - case - assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_dec_sub26_inv_out $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] - end - attribute \src "issuer_ls180.v:15054.3-15087.6" - process $proc$issuer_ls180.v:15054$312 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] - attribute \src "issuer_ls180.v:15055.5-15055.29" - switch \initial - attribute \src "issuer_ls180.v:15055.9-15055.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 - case - assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_dec_sub26_cry_out $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] - end - attribute \src "issuer_ls180.v:15088.3-15121.6" - process $proc$issuer_ls180.v:15088$313 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] - attribute \src "issuer_ls180.v:15089.5-15089.29" - switch \initial - attribute \src "issuer_ls180.v:15089.9-15089.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 - case - assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_dec_sub26_is_32b $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] - end - attribute \src "issuer_ls180.v:15122.3-15155.6" - process $proc$issuer_ls180.v:15122$314 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_sgn[0:0] $1\LOGICAL_dec31_dec_sub26_sgn[0:0] - attribute \src "issuer_ls180.v:15123.5-15123.29" - switch \initial - attribute \src "issuer_ls180.v:15123.9-15123.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 - case - assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_dec_sub26_sgn $0\LOGICAL_dec31_dec_sub26_sgn[0:0] - end - attribute \src "issuer_ls180.v:15156.3-15189.6" - process $proc$issuer_ls180.v:15156$315 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] - attribute \src "issuer_ls180.v:15157.5-15157.29" - switch \initial - attribute \src "issuer_ls180.v:15157.9-15157.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110111 - case - assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0000000 - end - sync always - update \LOGICAL_dec31_dec_sub26_internal_op $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] - end - attribute \src "issuer_ls180.v:15190.3-15223.6" - process $proc$issuer_ls180.v:15190$316 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] - attribute \src "issuer_ls180.v:15191.5-15191.29" - switch \initial - attribute \src "issuer_ls180.v:15191.9-15191.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 - case - assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'000 - end - sync always - update \LOGICAL_dec31_dec_sub26_in1_sel $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:15224.3-15257.6" - process $proc$issuer_ls180.v:15224$317 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] - attribute \src "issuer_ls180.v:15225.5-15225.29" - switch \initial - attribute \src "issuer_ls180.v:15225.9-15225.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 - case - assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 - end - sync always - update \LOGICAL_dec31_dec_sub26_in2_sel $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:15258.3-15291.6" - process $proc$issuer_ls180.v:15258$318 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] - attribute \src "issuer_ls180.v:15259.5-15259.29" - switch \initial - attribute \src "issuer_ls180.v:15259.9-15259.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 - case - assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 - end - sync always - update \LOGICAL_dec31_dec_sub26_cr_in $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] - end - attribute \src "issuer_ls180.v:15292.3-15325.6" - process $proc$issuer_ls180.v:15292$319 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] - attribute \src "issuer_ls180.v:15293.5-15293.29" - switch \initial - attribute \src "issuer_ls180.v:15293.9-15293.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 - case - assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 - end - sync always - update \LOGICAL_dec31_dec_sub26_cr_out $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] - end - attribute \src "issuer_ls180.v:15326.3-15359.6" - process $proc$issuer_ls180.v:15326$320 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] - attribute \src "issuer_ls180.v:15327.5-15327.29" - switch \initial - attribute \src "issuer_ls180.v:15327.9-15327.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0100 - case - assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 - end - sync always - update \LOGICAL_dec31_dec_sub26_ldst_len $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:15360.3-15393.6" - process $proc$issuer_ls180.v:15360$321 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] - attribute \src "issuer_ls180.v:15361.5-15361.29" - switch \initial - attribute \src "issuer_ls180.v:15361.9-15361.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 - case - assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 - end - sync always - update \LOGICAL_dec31_dec_sub26_rc_sel $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:15394.3-15427.6" - process $proc$issuer_ls180.v:15394$322 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] - attribute \src "issuer_ls180.v:15395.5-15395.29" - switch \initial - attribute \src "issuer_ls180.v:15395.9-15395.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 - case - assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 - end - sync always - update \LOGICAL_dec31_dec_sub26_cry_in $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:15433.1-16136.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub28" -attribute \generator "nMigen" -module \LOGICAL_dec31_dec_sub28 - attribute \src "issuer_ls180.v:15950.3-15986.6" - wire width 3 $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] - attribute \src "issuer_ls180.v:15987.3-16023.6" - wire width 3 $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] - attribute \src "issuer_ls180.v:16098.3-16134.6" - wire width 2 $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] - attribute \src "issuer_ls180.v:15728.3-15764.6" - wire $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] - attribute \src "issuer_ls180.v:15617.3-15653.6" - wire width 12 $0\LOGICAL_dec31_dec_sub28_function_unit[11:0] - attribute \src "issuer_ls180.v:15876.3-15912.6" - wire width 3 $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] - attribute \src "issuer_ls180.v:15913.3-15949.6" - wire width 4 $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] - attribute \src "issuer_ls180.v:15839.3-15875.6" - wire width 7 $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] - attribute \src "issuer_ls180.v:15654.3-15690.6" - wire $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] - attribute \src "issuer_ls180.v:15691.3-15727.6" - wire $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] - attribute \src "issuer_ls180.v:15765.3-15801.6" - wire $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] - attribute \src "issuer_ls180.v:16024.3-16060.6" - wire width 4 $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] - attribute \src "issuer_ls180.v:16061.3-16097.6" - wire width 2 $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] - attribute \src "issuer_ls180.v:15802.3-15838.6" - wire $0\LOGICAL_dec31_dec_sub28_sgn[0:0] - attribute \src "issuer_ls180.v:15434.7-15434.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:15950.3-15986.6" - wire width 3 $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] - attribute \src "issuer_ls180.v:15987.3-16023.6" - wire width 3 $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] - attribute \src "issuer_ls180.v:16098.3-16134.6" - wire width 2 $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] - attribute \src "issuer_ls180.v:15728.3-15764.6" - wire $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] - attribute \src "issuer_ls180.v:15617.3-15653.6" - wire width 12 $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] - attribute \src "issuer_ls180.v:15876.3-15912.6" - wire width 3 $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] - attribute \src "issuer_ls180.v:15913.3-15949.6" - wire width 4 $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] - attribute \src "issuer_ls180.v:15839.3-15875.6" - wire width 7 $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] - attribute \src "issuer_ls180.v:15654.3-15690.6" - wire $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] - attribute \src "issuer_ls180.v:15691.3-15727.6" - wire $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] - attribute \src "issuer_ls180.v:15765.3-15801.6" - wire $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] - attribute \src "issuer_ls180.v:16024.3-16060.6" - wire width 4 $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] - attribute \src "issuer_ls180.v:16061.3-16097.6" - wire width 2 $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] - attribute \src "issuer_ls180.v:15802.3-15838.6" - wire $1\LOGICAL_dec31_dec_sub28_sgn[0:0] + wire width 32 \dec31_dec_sub15_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub16_dec31_dec_sub16_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -22277,7 +18803,7 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \LOGICAL_dec31_dec_sub28_cr_in + wire width 3 \dec31_dec_sub16_dec31_dec_sub16_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -22285,15 +18811,47 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 6 \LOGICAL_dec31_dec_sub28_cr_out + wire width 3 \dec31_dec_sub16_dec31_dec_sub16_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 9 \LOGICAL_dec31_dec_sub28_cry_in + wire width 2 \dec31_dec_sub16_dec31_dec_sub16_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 12 \LOGICAL_dec31_dec_sub28_cry_out + wire \dec31_dec_sub16_dec31_dec_sub16_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub16_dec31_dec_sub16_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -22308,7 +18866,7 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \LOGICAL_dec31_dec_sub28_function_unit + wire width 12 \dec31_dec_sub16_dec31_dec_sub16_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -22316,7 +18874,7 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \LOGICAL_dec31_dec_sub28_in1_sel + wire width 3 \dec31_dec_sub16_dec31_dec_sub16_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -22333,7 +18891,13 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 4 \LOGICAL_dec31_dec_sub28_in2_sel + wire width 4 \dec31_dec_sub16_dec31_dec_sub16_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub16_dec31_dec_sub16_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -22409,13 +18973,13 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \LOGICAL_dec31_dec_sub28_internal_op + wire width 7 \dec31_dec_sub16_dec31_dec_sub16_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \LOGICAL_dec31_dec_sub28_inv_a + wire \dec31_dec_sub16_dec31_dec_sub16_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 11 \LOGICAL_dec31_dec_sub28_inv_out + wire \dec31_dec_sub16_dec31_dec_sub16_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 13 \LOGICAL_dec31_dec_sub28_is_32b + wire \dec31_dec_sub16_dec31_dec_sub16_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -22423,896 +18987,43 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 7 \LOGICAL_dec31_dec_sub28_ldst_len + wire width 4 \dec31_dec_sub16_dec31_dec_sub16_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub16_dec31_dec_sub16_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \LOGICAL_dec31_dec_sub28_rc_sel + wire width 2 \dec31_dec_sub16_dec31_dec_sub16_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 14 \LOGICAL_dec31_dec_sub28_sgn - attribute \src "issuer_ls180.v:15434.7-15434.15" - wire \initial + wire \dec31_dec_sub16_dec31_dec_sub16_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub16_dec31_dec_sub16_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:15434.7-15434.20" - process $proc$issuer_ls180.v:15434$338 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:15617.3-15653.6" - process $proc$issuer_ls180.v:15617$324 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_function_unit[11:0] $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] - attribute \src "issuer_ls180.v:15618.5-15618.29" - switch \initial - attribute \src "issuer_ls180.v:15618.9-15618.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 - case - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000000000 - end - sync always - update \LOGICAL_dec31_dec_sub28_function_unit $0\LOGICAL_dec31_dec_sub28_function_unit[11:0] - end - attribute \src "issuer_ls180.v:15654.3-15690.6" - process $proc$issuer_ls180.v:15654$325 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] - attribute \src "issuer_ls180.v:15655.5-15655.29" - switch \initial - attribute \src "issuer_ls180.v:15655.9-15655.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 - case - assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_dec_sub28_inv_a $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] - end - attribute \src "issuer_ls180.v:15691.3-15727.6" - process $proc$issuer_ls180.v:15691$326 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] - attribute \src "issuer_ls180.v:15692.5-15692.29" - switch \initial - attribute \src "issuer_ls180.v:15692.9-15692.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 - case - assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_dec_sub28_inv_out $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] - end - attribute \src "issuer_ls180.v:15728.3-15764.6" - process $proc$issuer_ls180.v:15728$327 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] - attribute \src "issuer_ls180.v:15729.5-15729.29" - switch \initial - attribute \src "issuer_ls180.v:15729.9-15729.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 - case - assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_dec_sub28_cry_out $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] - end - attribute \src "issuer_ls180.v:15765.3-15801.6" - process $proc$issuer_ls180.v:15765$328 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] - attribute \src "issuer_ls180.v:15766.5-15766.29" - switch \initial - attribute \src "issuer_ls180.v:15766.9-15766.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 - case - assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_dec_sub28_is_32b $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] - end - attribute \src "issuer_ls180.v:15802.3-15838.6" - process $proc$issuer_ls180.v:15802$329 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_sgn[0:0] $1\LOGICAL_dec31_dec_sub28_sgn[0:0] - attribute \src "issuer_ls180.v:15803.5-15803.29" - switch \initial - attribute \src "issuer_ls180.v:15803.9-15803.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 - case - assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_dec_sub28_sgn $0\LOGICAL_dec31_dec_sub28_sgn[0:0] - end - attribute \src "issuer_ls180.v:15839.3-15875.6" - process $proc$issuer_ls180.v:15839$330 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] - attribute \src "issuer_ls180.v:15840.5-15840.29" - switch \initial - attribute \src "issuer_ls180.v:15840.9-15840.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0001001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'1000011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0110101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0110101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0110101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'1000011 - case - assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000000 - end - sync always - update \LOGICAL_dec31_dec_sub28_internal_op $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] - end - attribute \src "issuer_ls180.v:15876.3-15912.6" - process $proc$issuer_ls180.v:15876$331 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] - attribute \src "issuer_ls180.v:15877.5-15877.29" - switch \initial - attribute \src "issuer_ls180.v:15877.9-15877.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 - case - assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'000 - end - sync always - update \LOGICAL_dec31_dec_sub28_in1_sel $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:15913.3-15949.6" - process $proc$issuer_ls180.v:15913$332 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] - attribute \src "issuer_ls180.v:15914.5-15914.29" - switch \initial - attribute \src "issuer_ls180.v:15914.9-15914.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 - case - assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0000 - end - sync always - update \LOGICAL_dec31_dec_sub28_in2_sel $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:15950.3-15986.6" - process $proc$issuer_ls180.v:15950$333 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] - attribute \src "issuer_ls180.v:15951.5-15951.29" - switch \initial - attribute \src "issuer_ls180.v:15951.9-15951.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 - case - assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 - end - sync always - update \LOGICAL_dec31_dec_sub28_cr_in $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] - end - attribute \src "issuer_ls180.v:15987.3-16023.6" - process $proc$issuer_ls180.v:15987$334 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] - attribute \src "issuer_ls180.v:15988.5-15988.29" - switch \initial - attribute \src "issuer_ls180.v:15988.9-15988.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 - case - assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'000 - end - sync always - update \LOGICAL_dec31_dec_sub28_cr_out $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] - end - attribute \src "issuer_ls180.v:16024.3-16060.6" - process $proc$issuer_ls180.v:16024$335 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] - attribute \src "issuer_ls180.v:16025.5-16025.29" - switch \initial - attribute \src "issuer_ls180.v:16025.9-16025.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 - case - assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 - end - sync always - update \LOGICAL_dec31_dec_sub28_ldst_len $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:16061.3-16097.6" - process $proc$issuer_ls180.v:16061$336 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] - attribute \src "issuer_ls180.v:16062.5-16062.29" - switch \initial - attribute \src "issuer_ls180.v:16062.9-16062.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 - case - assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'00 - end - sync always - update \LOGICAL_dec31_dec_sub28_rc_sel $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:16098.3-16134.6" - process $proc$issuer_ls180.v:16098$337 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] - attribute \src "issuer_ls180.v:16099.5-16099.29" - switch \initial - attribute \src "issuer_ls180.v:16099.9-16099.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 - case - assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 - end - sync always - update \LOGICAL_dec31_dec_sub28_cry_in $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:16140.1-16698.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31" -attribute \generator "nMigen" -module \MUL_dec31 - attribute \src "issuer_ls180.v:16655.3-16667.6" - wire width 3 $0\MUL_dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:16668.3-16680.6" - wire width 3 $0\MUL_dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:16616.3-16628.6" - wire width 12 $0\MUL_dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:16642.3-16654.6" - wire width 4 $0\MUL_dec31_in2_sel[3:0] - attribute \src "issuer_ls180.v:16629.3-16641.6" - wire width 7 $0\MUL_dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:16590.3-16602.6" - wire $0\MUL_dec31_is_32b[0:0] - attribute \src "issuer_ls180.v:16681.3-16693.6" - wire width 2 $0\MUL_dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:16603.3-16615.6" - wire $0\MUL_dec31_sgn[0:0] - attribute \src "issuer_ls180.v:16141.7-16141.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:16655.3-16667.6" - wire width 3 $1\MUL_dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:16668.3-16680.6" - wire width 3 $1\MUL_dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:16616.3-16628.6" - wire width 12 $1\MUL_dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:16642.3-16654.6" - wire width 4 $1\MUL_dec31_in2_sel[3:0] - attribute \src "issuer_ls180.v:16629.3-16641.6" - wire width 7 $1\MUL_dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:16590.3-16602.6" - wire $1\MUL_dec31_is_32b[0:0] - attribute \src "issuer_ls180.v:16681.3-16693.6" - wire width 2 $1\MUL_dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:16603.3-16615.6" - wire $1\MUL_dec31_sgn[0:0] + wire width 32 \dec31_dec_sub16_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub18_dec31_dec_sub18_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -23322,7 +19033,7 @@ module \MUL_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 4 \MUL_dec31_cr_in + wire width 3 \dec31_dec_sub18_dec31_dec_sub18_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -23330,25 +19041,47 @@ module \MUL_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \MUL_dec31_cr_out - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" + wire width 3 \dec31_dec_sub18_dec31_dec_sub18_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" + wire width 2 \dec31_dec_sub18_dec31_dec_sub18_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out + wire width 5 \dec31_dec_sub18_dec31_dec_sub18_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -23363,7 +19096,15 @@ module \MUL_dec31 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit + wire width 12 \dec31_dec_sub18_dec31_dec_sub18_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub18_dec31_dec_sub18_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -23380,7 +19121,13 @@ module \MUL_dec31 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel + wire width 4 \dec31_dec_sub18_dec31_dec_sub18_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub18_dec31_dec_sub18_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -23456,19 +19203,57 @@ module \MUL_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op + wire width 7 \dec31_dec_sub18_dec31_dec_sub18_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub18_dec31_dec_sub18_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b + wire \dec31_dec_sub18_dec31_dec_sub18_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub18_dec31_dec_sub18_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel + wire width 2 \dec31_dec_sub18_dec31_dec_sub18_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn + wire \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub18_dec31_dec_sub18_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \MUL_dec31_dec_sub11_opcode_in + wire width 32 \dec31_dec_sub18_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub19_dec31_dec_sub19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -23478,7 +19263,7 @@ module \MUL_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in + wire width 3 \dec31_dec_sub19_dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -23486,7 +19271,47 @@ module \MUL_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out + wire width 3 \dec31_dec_sub19_dec31_dec_sub19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub19_dec31_dec_sub19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub19_dec31_dec_sub19_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -23501,7 +19326,15 @@ module \MUL_dec31 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit + wire width 12 \dec31_dec_sub19_dec31_dec_sub19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub19_dec31_dec_sub19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -23518,7 +19351,13 @@ module \MUL_dec31 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel + wire width 4 \dec31_dec_sub19_dec31_dec_sub19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub19_dec31_dec_sub19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -23594,19 +19433,115 @@ module \MUL_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op + wire width 7 \dec31_dec_sub19_dec31_dec_sub19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub19_dec31_dec_sub19_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b + wire \dec31_dec_sub19_dec31_dec_sub19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub19_dec31_dec_sub19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel + wire width 2 \dec31_dec_sub19_dec31_dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn + wire \dec31_dec_sub19_dec31_dec_sub19_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub19_dec31_dec_sub19_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \MUL_dec31_dec_sub9_opcode_in + wire width 32 \dec31_dec_sub19_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub20_dec31_dec_sub20_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub20_dec31_dec_sub20_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub20_dec31_dec_sub20_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub20_dec31_dec_sub20_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub20_dec31_dec_sub20_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -23621,7 +19556,15 @@ module \MUL_dec31 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \MUL_dec31_function_unit + wire width 12 \dec31_dec_sub20_dec31_dec_sub20_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub20_dec31_dec_sub20_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -23638,7 +19581,13 @@ module \MUL_dec31 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 3 \MUL_dec31_in2_sel + wire width 4 \dec31_dec_sub20_dec31_dec_sub20_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub20_dec31_dec_sub20_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -23714,319 +19663,57 @@ module \MUL_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \MUL_dec31_internal_op + wire width 7 \dec31_dec_sub20_dec31_dec_sub20_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub20_dec31_dec_sub20_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 7 \MUL_dec31_is_32b + wire \dec31_dec_sub20_dec31_dec_sub20_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub20_dec31_dec_sub20_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 6 \MUL_dec31_rc_sel + wire width 2 \dec31_dec_sub20_dec31_dec_sub20_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 8 \MUL_dec31_sgn - attribute \src "issuer_ls180.v:16141.7-16141.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" - wire width 5 \opc_in + wire \dec31_dec_sub20_dec31_dec_sub20_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub20_dec31_dec_sub20_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 9 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 10 \opcode_switch - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:16568.23-16578.4" - cell \MUL_dec31_dec_sub11 \MUL_dec31_dec_sub11 - connect \MUL_dec31_dec_sub11_cr_in \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in - connect \MUL_dec31_dec_sub11_cr_out \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out - connect \MUL_dec31_dec_sub11_function_unit \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit - connect \MUL_dec31_dec_sub11_in2_sel \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel - connect \MUL_dec31_dec_sub11_internal_op \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op - connect \MUL_dec31_dec_sub11_is_32b \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b - connect \MUL_dec31_dec_sub11_rc_sel \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel - connect \MUL_dec31_dec_sub11_sgn \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn - connect \opcode_in \MUL_dec31_dec_sub11_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:16579.22-16589.4" - cell \MUL_dec31_dec_sub9 \MUL_dec31_dec_sub9 - connect \MUL_dec31_dec_sub9_cr_in \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in - connect \MUL_dec31_dec_sub9_cr_out \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out - connect \MUL_dec31_dec_sub9_function_unit \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit - connect \MUL_dec31_dec_sub9_in2_sel \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel - connect \MUL_dec31_dec_sub9_internal_op \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op - connect \MUL_dec31_dec_sub9_is_32b \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b - connect \MUL_dec31_dec_sub9_rc_sel \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel - connect \MUL_dec31_dec_sub9_sgn \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn - connect \opcode_in \MUL_dec31_dec_sub9_opcode_in - end - attribute \src "issuer_ls180.v:16141.7-16141.20" - process $proc$issuer_ls180.v:16141$347 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:16590.3-16602.6" - process $proc$issuer_ls180.v:16590$339 - assign { } { } - assign { } { } - assign $0\MUL_dec31_is_32b[0:0] $1\MUL_dec31_is_32b[0:0] - attribute \src "issuer_ls180.v:16591.5-16591.29" - switch \initial - attribute \src "issuer_ls180.v:16591.9-16591.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\MUL_dec31_is_32b[0:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\MUL_dec31_is_32b[0:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b - case - assign $1\MUL_dec31_is_32b[0:0] 1'0 - end - sync always - update \MUL_dec31_is_32b $0\MUL_dec31_is_32b[0:0] - end - attribute \src "issuer_ls180.v:16603.3-16615.6" - process $proc$issuer_ls180.v:16603$340 - assign { } { } - assign { } { } - assign $0\MUL_dec31_sgn[0:0] $1\MUL_dec31_sgn[0:0] - attribute \src "issuer_ls180.v:16604.5-16604.29" - switch \initial - attribute \src "issuer_ls180.v:16604.9-16604.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\MUL_dec31_sgn[0:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\MUL_dec31_sgn[0:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn - case - assign $1\MUL_dec31_sgn[0:0] 1'0 - end - sync always - update \MUL_dec31_sgn $0\MUL_dec31_sgn[0:0] - end - attribute \src "issuer_ls180.v:16616.3-16628.6" - process $proc$issuer_ls180.v:16616$341 - assign { } { } - assign { } { } - assign $0\MUL_dec31_function_unit[11:0] $1\MUL_dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:16617.5-16617.29" - switch \initial - attribute \src "issuer_ls180.v:16617.9-16617.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\MUL_dec31_function_unit[11:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\MUL_dec31_function_unit[11:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit - case - assign $1\MUL_dec31_function_unit[11:0] 12'000000000000 - end - sync always - update \MUL_dec31_function_unit $0\MUL_dec31_function_unit[11:0] - end - attribute \src "issuer_ls180.v:16629.3-16641.6" - process $proc$issuer_ls180.v:16629$342 - assign { } { } - assign { } { } - assign $0\MUL_dec31_internal_op[6:0] $1\MUL_dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:16630.5-16630.29" - switch \initial - attribute \src "issuer_ls180.v:16630.9-16630.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\MUL_dec31_internal_op[6:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\MUL_dec31_internal_op[6:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op - case - assign $1\MUL_dec31_internal_op[6:0] 7'0000000 - end - sync always - update \MUL_dec31_internal_op $0\MUL_dec31_internal_op[6:0] - end - attribute \src "issuer_ls180.v:16642.3-16654.6" - process $proc$issuer_ls180.v:16642$343 - assign { } { } - assign { } { } - assign $0\MUL_dec31_in2_sel[3:0] $1\MUL_dec31_in2_sel[3:0] - attribute \src "issuer_ls180.v:16643.5-16643.29" - switch \initial - attribute \src "issuer_ls180.v:16643.9-16643.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\MUL_dec31_in2_sel[3:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\MUL_dec31_in2_sel[3:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel - case - assign $1\MUL_dec31_in2_sel[3:0] 4'0000 - end - sync always - update \MUL_dec31_in2_sel $0\MUL_dec31_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:16655.3-16667.6" - process $proc$issuer_ls180.v:16655$344 - assign { } { } - assign { } { } - assign $0\MUL_dec31_cr_in[2:0] $1\MUL_dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:16656.5-16656.29" - switch \initial - attribute \src "issuer_ls180.v:16656.9-16656.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\MUL_dec31_cr_in[2:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\MUL_dec31_cr_in[2:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in - case - assign $1\MUL_dec31_cr_in[2:0] 3'000 - end - sync always - update \MUL_dec31_cr_in $0\MUL_dec31_cr_in[2:0] - end - attribute \src "issuer_ls180.v:16668.3-16680.6" - process $proc$issuer_ls180.v:16668$345 - assign { } { } - assign { } { } - assign $0\MUL_dec31_cr_out[2:0] $1\MUL_dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:16669.5-16669.29" - switch \initial - attribute \src "issuer_ls180.v:16669.9-16669.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\MUL_dec31_cr_out[2:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\MUL_dec31_cr_out[2:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out - case - assign $1\MUL_dec31_cr_out[2:0] 3'000 - end - sync always - update \MUL_dec31_cr_out $0\MUL_dec31_cr_out[2:0] - end - attribute \src "issuer_ls180.v:16681.3-16693.6" - process $proc$issuer_ls180.v:16681$346 - assign { } { } - assign { } { } - assign $0\MUL_dec31_rc_sel[1:0] $1\MUL_dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:16682.5-16682.29" - switch \initial - attribute \src "issuer_ls180.v:16682.9-16682.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\MUL_dec31_rc_sel[1:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\MUL_dec31_rc_sel[1:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel - case - assign $1\MUL_dec31_rc_sel[1:0] 2'00 - end - sync always - update \MUL_dec31_rc_sel $0\MUL_dec31_rc_sel[1:0] - end - connect \MUL_dec31_dec_sub11_opcode_in \opcode_in - connect \MUL_dec31_dec_sub9_opcode_in \opcode_in - connect \opc_in \opcode_switch [4:0] - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "issuer_ls180.v:16702.1-17053.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub11" -attribute \generator "nMigen" -module \MUL_dec31_dec_sub11 - attribute \src "issuer_ls180.v:16927.3-16951.6" - wire width 3 $0\MUL_dec31_dec_sub11_cr_in[2:0] - attribute \src "issuer_ls180.v:16952.3-16976.6" - wire width 3 $0\MUL_dec31_dec_sub11_cr_out[2:0] - attribute \src "issuer_ls180.v:16852.3-16876.6" - wire width 12 $0\MUL_dec31_dec_sub11_function_unit[11:0] - attribute \src "issuer_ls180.v:16902.3-16926.6" - wire width 4 $0\MUL_dec31_dec_sub11_in2_sel[3:0] - attribute \src "issuer_ls180.v:16877.3-16901.6" - wire width 7 $0\MUL_dec31_dec_sub11_internal_op[6:0] - attribute \src "issuer_ls180.v:17002.3-17026.6" - wire $0\MUL_dec31_dec_sub11_is_32b[0:0] - attribute \src "issuer_ls180.v:16977.3-17001.6" - wire width 2 $0\MUL_dec31_dec_sub11_rc_sel[1:0] - attribute \src "issuer_ls180.v:17027.3-17051.6" - wire $0\MUL_dec31_dec_sub11_sgn[0:0] - attribute \src "issuer_ls180.v:16703.7-16703.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:16927.3-16951.6" - wire width 3 $1\MUL_dec31_dec_sub11_cr_in[2:0] - attribute \src "issuer_ls180.v:16952.3-16976.6" - wire width 3 $1\MUL_dec31_dec_sub11_cr_out[2:0] - attribute \src "issuer_ls180.v:16852.3-16876.6" - wire width 12 $1\MUL_dec31_dec_sub11_function_unit[11:0] - attribute \src "issuer_ls180.v:16902.3-16926.6" - wire width 4 $1\MUL_dec31_dec_sub11_in2_sel[3:0] - attribute \src "issuer_ls180.v:16877.3-16901.6" - wire width 7 $1\MUL_dec31_dec_sub11_internal_op[6:0] - attribute \src "issuer_ls180.v:17002.3-17026.6" - wire $1\MUL_dec31_dec_sub11_is_32b[0:0] - attribute \src "issuer_ls180.v:16977.3-17001.6" - wire width 2 $1\MUL_dec31_dec_sub11_rc_sel[1:0] - attribute \src "issuer_ls180.v:17027.3-17051.6" - wire $1\MUL_dec31_dec_sub11_sgn[0:0] + wire width 32 \dec31_dec_sub20_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub21_dec31_dec_sub21_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -24036,7 +19723,7 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 4 \MUL_dec31_dec_sub11_cr_in + wire width 3 \dec31_dec_sub21_dec31_dec_sub21_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -24044,7 +19731,47 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \MUL_dec31_dec_sub11_cr_out + wire width 3 \dec31_dec_sub21_dec31_dec_sub21_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub21_dec31_dec_sub21_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub21_dec31_dec_sub21_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -24059,7 +19786,15 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \MUL_dec31_dec_sub11_function_unit + wire width 12 \dec31_dec_sub21_dec31_dec_sub21_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub21_dec31_dec_sub21_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -24076,7 +19811,13 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 3 \MUL_dec31_dec_sub11_in2_sel + wire width 4 \dec31_dec_sub21_dec31_dec_sub21_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub21_dec31_dec_sub21_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -24152,416 +19893,57 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \MUL_dec31_dec_sub11_internal_op + wire width 7 \dec31_dec_sub21_dec31_dec_sub21_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub21_dec31_dec_sub21_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 7 \MUL_dec31_dec_sub11_is_32b + wire \dec31_dec_sub21_dec31_dec_sub21_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub21_dec31_dec_sub21_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 6 \MUL_dec31_dec_sub11_rc_sel + wire width 2 \dec31_dec_sub21_dec31_dec_sub21_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 8 \MUL_dec31_dec_sub11_sgn - attribute \src "issuer_ls180.v:16703.7-16703.15" - wire \initial + wire \dec31_dec_sub21_dec31_dec_sub21_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub21_dec31_dec_sub21_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 9 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:16703.7-16703.20" - process $proc$issuer_ls180.v:16703$356 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:16852.3-16876.6" - process $proc$issuer_ls180.v:16852$348 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub11_function_unit[11:0] $1\MUL_dec31_dec_sub11_function_unit[11:0] - attribute \src "issuer_ls180.v:16853.5-16853.29" - switch \initial - attribute \src "issuer_ls180.v:16853.9-16853.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 - case - assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000000000000 - end - sync always - update \MUL_dec31_dec_sub11_function_unit $0\MUL_dec31_dec_sub11_function_unit[11:0] - end - attribute \src "issuer_ls180.v:16877.3-16901.6" - process $proc$issuer_ls180.v:16877$349 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub11_internal_op[6:0] $1\MUL_dec31_dec_sub11_internal_op[6:0] - attribute \src "issuer_ls180.v:16878.5-16878.29" - switch \initial - attribute \src "issuer_ls180.v:16878.9-16878.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110010 - case - assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0000000 - end - sync always - update \MUL_dec31_dec_sub11_internal_op $0\MUL_dec31_dec_sub11_internal_op[6:0] - end - attribute \src "issuer_ls180.v:16902.3-16926.6" - process $proc$issuer_ls180.v:16902$350 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub11_in2_sel[3:0] $1\MUL_dec31_dec_sub11_in2_sel[3:0] - attribute \src "issuer_ls180.v:16903.5-16903.29" - switch \initial - attribute \src "issuer_ls180.v:16903.9-16903.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 - case - assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0000 - end - sync always - update \MUL_dec31_dec_sub11_in2_sel $0\MUL_dec31_dec_sub11_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:16927.3-16951.6" - process $proc$issuer_ls180.v:16927$351 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub11_cr_in[2:0] $1\MUL_dec31_dec_sub11_cr_in[2:0] - attribute \src "issuer_ls180.v:16928.5-16928.29" - switch \initial - attribute \src "issuer_ls180.v:16928.9-16928.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 - case - assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 - end - sync always - update \MUL_dec31_dec_sub11_cr_in $0\MUL_dec31_dec_sub11_cr_in[2:0] - end - attribute \src "issuer_ls180.v:16952.3-16976.6" - process $proc$issuer_ls180.v:16952$352 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub11_cr_out[2:0] $1\MUL_dec31_dec_sub11_cr_out[2:0] - attribute \src "issuer_ls180.v:16953.5-16953.29" - switch \initial - attribute \src "issuer_ls180.v:16953.9-16953.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 - case - assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'000 - end - sync always - update \MUL_dec31_dec_sub11_cr_out $0\MUL_dec31_dec_sub11_cr_out[2:0] - end - attribute \src "issuer_ls180.v:16977.3-17001.6" - process $proc$issuer_ls180.v:16977$353 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub11_rc_sel[1:0] $1\MUL_dec31_dec_sub11_rc_sel[1:0] - attribute \src "issuer_ls180.v:16978.5-16978.29" - switch \initial - attribute \src "issuer_ls180.v:16978.9-16978.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 - case - assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'00 - end - sync always - update \MUL_dec31_dec_sub11_rc_sel $0\MUL_dec31_dec_sub11_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:17002.3-17026.6" - process $proc$issuer_ls180.v:17002$354 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub11_is_32b[0:0] $1\MUL_dec31_dec_sub11_is_32b[0:0] - attribute \src "issuer_ls180.v:17003.5-17003.29" - switch \initial - attribute \src "issuer_ls180.v:17003.9-17003.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 - case - assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'0 - end - sync always - update \MUL_dec31_dec_sub11_is_32b $0\MUL_dec31_dec_sub11_is_32b[0:0] - end - attribute \src "issuer_ls180.v:17027.3-17051.6" - process $proc$issuer_ls180.v:17027$355 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub11_sgn[0:0] $1\MUL_dec31_dec_sub11_sgn[0:0] - attribute \src "issuer_ls180.v:17028.5-17028.29" - switch \initial - attribute \src "issuer_ls180.v:17028.9-17028.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 - case - assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'0 - end - sync always - update \MUL_dec31_dec_sub11_sgn $0\MUL_dec31_dec_sub11_sgn[0:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:17057.1-17408.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub9" -attribute \generator "nMigen" -module \MUL_dec31_dec_sub9 - attribute \src "issuer_ls180.v:17282.3-17306.6" - wire width 3 $0\MUL_dec31_dec_sub9_cr_in[2:0] - attribute \src "issuer_ls180.v:17307.3-17331.6" - wire width 3 $0\MUL_dec31_dec_sub9_cr_out[2:0] - attribute \src "issuer_ls180.v:17207.3-17231.6" - wire width 12 $0\MUL_dec31_dec_sub9_function_unit[11:0] - attribute \src "issuer_ls180.v:17257.3-17281.6" - wire width 4 $0\MUL_dec31_dec_sub9_in2_sel[3:0] - attribute \src "issuer_ls180.v:17232.3-17256.6" - wire width 7 $0\MUL_dec31_dec_sub9_internal_op[6:0] - attribute \src "issuer_ls180.v:17357.3-17381.6" - wire $0\MUL_dec31_dec_sub9_is_32b[0:0] - attribute \src "issuer_ls180.v:17332.3-17356.6" - wire width 2 $0\MUL_dec31_dec_sub9_rc_sel[1:0] - attribute \src "issuer_ls180.v:17382.3-17406.6" - wire $0\MUL_dec31_dec_sub9_sgn[0:0] - attribute \src "issuer_ls180.v:17058.7-17058.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:17282.3-17306.6" - wire width 3 $1\MUL_dec31_dec_sub9_cr_in[2:0] - attribute \src "issuer_ls180.v:17307.3-17331.6" - wire width 3 $1\MUL_dec31_dec_sub9_cr_out[2:0] - attribute \src "issuer_ls180.v:17207.3-17231.6" - wire width 12 $1\MUL_dec31_dec_sub9_function_unit[11:0] - attribute \src "issuer_ls180.v:17257.3-17281.6" - wire width 4 $1\MUL_dec31_dec_sub9_in2_sel[3:0] - attribute \src "issuer_ls180.v:17232.3-17256.6" - wire width 7 $1\MUL_dec31_dec_sub9_internal_op[6:0] - attribute \src "issuer_ls180.v:17357.3-17381.6" - wire $1\MUL_dec31_dec_sub9_is_32b[0:0] - attribute \src "issuer_ls180.v:17332.3-17356.6" - wire width 2 $1\MUL_dec31_dec_sub9_rc_sel[1:0] - attribute \src "issuer_ls180.v:17382.3-17406.6" - wire $1\MUL_dec31_dec_sub9_sgn[0:0] + wire width 32 \dec31_dec_sub21_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub22_dec31_dec_sub22_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -24571,7 +19953,7 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 4 \MUL_dec31_dec_sub9_cr_in + wire width 3 \dec31_dec_sub22_dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -24579,7 +19961,47 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \MUL_dec31_dec_sub9_cr_out + wire width 3 \dec31_dec_sub22_dec31_dec_sub22_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub22_dec31_dec_sub22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub22_dec31_dec_sub22_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -24594,7 +20016,15 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \MUL_dec31_dec_sub9_function_unit + wire width 12 \dec31_dec_sub22_dec31_dec_sub22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub22_dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -24611,7 +20041,13 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 3 \MUL_dec31_dec_sub9_in2_sel + wire width 4 \dec31_dec_sub22_dec31_dec_sub22_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub22_dec31_dec_sub22_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -24687,424 +20123,57 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \MUL_dec31_dec_sub9_internal_op + wire width 7 \dec31_dec_sub22_dec31_dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub22_dec31_dec_sub22_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 7 \MUL_dec31_dec_sub9_is_32b + wire \dec31_dec_sub22_dec31_dec_sub22_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub22_dec31_dec_sub22_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 6 \MUL_dec31_dec_sub9_rc_sel + wire width 2 \dec31_dec_sub22_dec31_dec_sub22_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 8 \MUL_dec31_dec_sub9_sgn - attribute \src "issuer_ls180.v:17058.7-17058.15" - wire \initial + wire \dec31_dec_sub22_dec31_dec_sub22_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub22_dec31_dec_sub22_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 9 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:17058.7-17058.20" - process $proc$issuer_ls180.v:17058$365 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:17207.3-17231.6" - process $proc$issuer_ls180.v:17207$357 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub9_function_unit[11:0] $1\MUL_dec31_dec_sub9_function_unit[11:0] - attribute \src "issuer_ls180.v:17208.5-17208.29" - switch \initial - attribute \src "issuer_ls180.v:17208.9-17208.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 - case - assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000000000000 - end - sync always - update \MUL_dec31_dec_sub9_function_unit $0\MUL_dec31_dec_sub9_function_unit[11:0] - end - attribute \src "issuer_ls180.v:17232.3-17256.6" - process $proc$issuer_ls180.v:17232$358 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub9_internal_op[6:0] $1\MUL_dec31_dec_sub9_internal_op[6:0] - attribute \src "issuer_ls180.v:17233.5-17233.29" - switch \initial - attribute \src "issuer_ls180.v:17233.9-17233.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110010 - case - assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0000000 - end - sync always - update \MUL_dec31_dec_sub9_internal_op $0\MUL_dec31_dec_sub9_internal_op[6:0] - end - attribute \src "issuer_ls180.v:17257.3-17281.6" - process $proc$issuer_ls180.v:17257$359 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub9_in2_sel[3:0] $1\MUL_dec31_dec_sub9_in2_sel[3:0] - attribute \src "issuer_ls180.v:17258.5-17258.29" - switch \initial - attribute \src "issuer_ls180.v:17258.9-17258.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 - case - assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0000 - end - sync always - update \MUL_dec31_dec_sub9_in2_sel $0\MUL_dec31_dec_sub9_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:17282.3-17306.6" - process $proc$issuer_ls180.v:17282$360 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub9_cr_in[2:0] $1\MUL_dec31_dec_sub9_cr_in[2:0] - attribute \src "issuer_ls180.v:17283.5-17283.29" - switch \initial - attribute \src "issuer_ls180.v:17283.9-17283.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 - case - assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 - end - sync always - update \MUL_dec31_dec_sub9_cr_in $0\MUL_dec31_dec_sub9_cr_in[2:0] - end - attribute \src "issuer_ls180.v:17307.3-17331.6" - process $proc$issuer_ls180.v:17307$361 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub9_cr_out[2:0] $1\MUL_dec31_dec_sub9_cr_out[2:0] - attribute \src "issuer_ls180.v:17308.5-17308.29" - switch \initial - attribute \src "issuer_ls180.v:17308.9-17308.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 - case - assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'000 - end - sync always - update \MUL_dec31_dec_sub9_cr_out $0\MUL_dec31_dec_sub9_cr_out[2:0] - end - attribute \src "issuer_ls180.v:17332.3-17356.6" - process $proc$issuer_ls180.v:17332$362 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub9_rc_sel[1:0] $1\MUL_dec31_dec_sub9_rc_sel[1:0] - attribute \src "issuer_ls180.v:17333.5-17333.29" - switch \initial - attribute \src "issuer_ls180.v:17333.9-17333.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 - case - assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'00 - end - sync always - update \MUL_dec31_dec_sub9_rc_sel $0\MUL_dec31_dec_sub9_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:17357.3-17381.6" - process $proc$issuer_ls180.v:17357$363 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub9_is_32b[0:0] $1\MUL_dec31_dec_sub9_is_32b[0:0] - attribute \src "issuer_ls180.v:17358.5-17358.29" - switch \initial - attribute \src "issuer_ls180.v:17358.9-17358.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 - case - assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 - end - sync always - update \MUL_dec31_dec_sub9_is_32b $0\MUL_dec31_dec_sub9_is_32b[0:0] - end - attribute \src "issuer_ls180.v:17382.3-17406.6" - process $proc$issuer_ls180.v:17382$364 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub9_sgn[0:0] $1\MUL_dec31_dec_sub9_sgn[0:0] - attribute \src "issuer_ls180.v:17383.5-17383.29" - switch \initial - attribute \src "issuer_ls180.v:17383.9-17383.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 - case - assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'0 - end - sync always - update \MUL_dec31_dec_sub9_sgn $0\MUL_dec31_dec_sub9_sgn[0:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:17412.1-17943.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec30" -attribute \generator "nMigen" -module \SHIFT_ROT_dec30 - attribute \src "issuer_ls180.v:17720.3-17756.6" - wire width 3 $0\SHIFT_ROT_dec30_cr_in[2:0] - attribute \src "issuer_ls180.v:17757.3-17793.6" - wire width 3 $0\SHIFT_ROT_dec30_cr_out[2:0] - attribute \src "issuer_ls180.v:17831.3-17867.6" - wire width 2 $0\SHIFT_ROT_dec30_cry_in[1:0] - attribute \src "issuer_ls180.v:17868.3-17904.6" - wire $0\SHIFT_ROT_dec30_cry_out[0:0] - attribute \src "issuer_ls180.v:17572.3-17608.6" - wire width 12 $0\SHIFT_ROT_dec30_function_unit[11:0] - attribute \src "issuer_ls180.v:17683.3-17719.6" - wire width 4 $0\SHIFT_ROT_dec30_in2_sel[3:0] - attribute \src "issuer_ls180.v:17646.3-17682.6" - wire width 7 $0\SHIFT_ROT_dec30_internal_op[6:0] - attribute \src "issuer_ls180.v:17905.3-17941.6" - wire $0\SHIFT_ROT_dec30_is_32b[0:0] - attribute \src "issuer_ls180.v:17794.3-17830.6" - wire width 2 $0\SHIFT_ROT_dec30_rc_sel[1:0] - attribute \src "issuer_ls180.v:17609.3-17645.6" - wire $0\SHIFT_ROT_dec30_sgn[0:0] - attribute \src "issuer_ls180.v:17413.7-17413.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:17720.3-17756.6" - wire width 3 $1\SHIFT_ROT_dec30_cr_in[2:0] - attribute \src "issuer_ls180.v:17757.3-17793.6" - wire width 3 $1\SHIFT_ROT_dec30_cr_out[2:0] - attribute \src "issuer_ls180.v:17831.3-17867.6" - wire width 2 $1\SHIFT_ROT_dec30_cry_in[1:0] - attribute \src "issuer_ls180.v:17868.3-17904.6" - wire $1\SHIFT_ROT_dec30_cry_out[0:0] - attribute \src "issuer_ls180.v:17572.3-17608.6" - wire width 12 $1\SHIFT_ROT_dec30_function_unit[11:0] - attribute \src "issuer_ls180.v:17683.3-17719.6" - wire width 4 $1\SHIFT_ROT_dec30_in2_sel[3:0] - attribute \src "issuer_ls180.v:17646.3-17682.6" - wire width 7 $1\SHIFT_ROT_dec30_internal_op[6:0] - attribute \src "issuer_ls180.v:17905.3-17941.6" - wire $1\SHIFT_ROT_dec30_is_32b[0:0] - attribute \src "issuer_ls180.v:17794.3-17830.6" - wire width 2 $1\SHIFT_ROT_dec30_rc_sel[1:0] - attribute \src "issuer_ls180.v:17609.3-17645.6" - wire $1\SHIFT_ROT_dec30_sgn[0:0] + wire width 32 \dec31_dec_sub22_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub23_dec31_dec_sub23_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -25114,7 +20183,7 @@ module \SHIFT_ROT_dec30 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 4 \SHIFT_ROT_dec30_cr_in + wire width 3 \dec31_dec_sub23_dec31_dec_sub23_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -25122,15 +20191,47 @@ module \SHIFT_ROT_dec30 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \SHIFT_ROT_dec30_cr_out + wire width 3 \dec31_dec_sub23_dec31_dec_sub23_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \SHIFT_ROT_dec30_cry_in + wire width 2 \dec31_dec_sub23_dec31_dec_sub23_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 8 \SHIFT_ROT_dec30_cry_out + wire \dec31_dec_sub23_dec31_dec_sub23_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub23_dec31_dec_sub23_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -25145,7 +20246,15 @@ module \SHIFT_ROT_dec30 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \SHIFT_ROT_dec30_function_unit + wire width 12 \dec31_dec_sub23_dec31_dec_sub23_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub23_dec31_dec_sub23_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -25162,7 +20271,13 @@ module \SHIFT_ROT_dec30 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 3 \SHIFT_ROT_dec30_in2_sel + wire width 4 \dec31_dec_sub23_dec31_dec_sub23_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub23_dec31_dec_sub23_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -25238,696 +20353,57 @@ module \SHIFT_ROT_dec30 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \SHIFT_ROT_dec30_internal_op + wire width 7 \dec31_dec_sub23_dec31_dec_sub23_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub23_dec31_dec_sub23_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 9 \SHIFT_ROT_dec30_is_32b + wire \dec31_dec_sub23_dec31_dec_sub23_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub23_dec31_dec_sub23_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 6 \SHIFT_ROT_dec30_rc_sel + wire width 2 \dec31_dec_sub23_dec31_dec_sub23_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \SHIFT_ROT_dec30_sgn - attribute \src "issuer_ls180.v:17413.7-17413.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 11 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 4 \opcode_switch - attribute \src "issuer_ls180.v:17413.7-17413.20" - process $proc$issuer_ls180.v:17413$376 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:17572.3-17608.6" - process $proc$issuer_ls180.v:17572$366 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec30_function_unit[11:0] $1\SHIFT_ROT_dec30_function_unit[11:0] - attribute \src "issuer_ls180.v:17573.5-17573.29" - switch \initial - attribute \src "issuer_ls180.v:17573.9-17573.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 - case - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000000000 - end - sync always - update \SHIFT_ROT_dec30_function_unit $0\SHIFT_ROT_dec30_function_unit[11:0] - end - attribute \src "issuer_ls180.v:17609.3-17645.6" - process $proc$issuer_ls180.v:17609$367 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec30_sgn[0:0] $1\SHIFT_ROT_dec30_sgn[0:0] - attribute \src "issuer_ls180.v:17610.5-17610.29" - switch \initial - attribute \src "issuer_ls180.v:17610.9-17610.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 - case - assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec30_sgn $0\SHIFT_ROT_dec30_sgn[0:0] - end - attribute \src "issuer_ls180.v:17646.3-17682.6" - process $proc$issuer_ls180.v:17646$368 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec30_internal_op[6:0] $1\SHIFT_ROT_dec30_internal_op[6:0] - attribute \src "issuer_ls180.v:17647.5-17647.29" - switch \initial - attribute \src "issuer_ls180.v:17647.9-17647.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111010 - case - assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0000000 - end - sync always - update \SHIFT_ROT_dec30_internal_op $0\SHIFT_ROT_dec30_internal_op[6:0] - end - attribute \src "issuer_ls180.v:17683.3-17719.6" - process $proc$issuer_ls180.v:17683$369 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec30_in2_sel[3:0] $1\SHIFT_ROT_dec30_in2_sel[3:0] - attribute \src "issuer_ls180.v:17684.5-17684.29" - switch \initial - attribute \src "issuer_ls180.v:17684.9-17684.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'0001 - case - assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'0000 - end - sync always - update \SHIFT_ROT_dec30_in2_sel $0\SHIFT_ROT_dec30_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:17720.3-17756.6" - process $proc$issuer_ls180.v:17720$370 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec30_cr_in[2:0] $1\SHIFT_ROT_dec30_cr_in[2:0] - attribute \src "issuer_ls180.v:17721.5-17721.29" - switch \initial - attribute \src "issuer_ls180.v:17721.9-17721.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 - case - assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 - end - sync always - update \SHIFT_ROT_dec30_cr_in $0\SHIFT_ROT_dec30_cr_in[2:0] - end - attribute \src "issuer_ls180.v:17757.3-17793.6" - process $proc$issuer_ls180.v:17757$371 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec30_cr_out[2:0] $1\SHIFT_ROT_dec30_cr_out[2:0] - attribute \src "issuer_ls180.v:17758.5-17758.29" - switch \initial - attribute \src "issuer_ls180.v:17758.9-17758.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 - case - assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'000 - end - sync always - update \SHIFT_ROT_dec30_cr_out $0\SHIFT_ROT_dec30_cr_out[2:0] - end - attribute \src "issuer_ls180.v:17794.3-17830.6" - process $proc$issuer_ls180.v:17794$372 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec30_rc_sel[1:0] $1\SHIFT_ROT_dec30_rc_sel[1:0] - attribute \src "issuer_ls180.v:17795.5-17795.29" - switch \initial - attribute \src "issuer_ls180.v:17795.9-17795.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 - case - assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'00 - end - sync always - update \SHIFT_ROT_dec30_rc_sel $0\SHIFT_ROT_dec30_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:17831.3-17867.6" - process $proc$issuer_ls180.v:17831$373 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec30_cry_in[1:0] $1\SHIFT_ROT_dec30_cry_in[1:0] - attribute \src "issuer_ls180.v:17832.5-17832.29" - switch \initial - attribute \src "issuer_ls180.v:17832.9-17832.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 - case - assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 - end - sync always - update \SHIFT_ROT_dec30_cry_in $0\SHIFT_ROT_dec30_cry_in[1:0] - end - attribute \src "issuer_ls180.v:17868.3-17904.6" - process $proc$issuer_ls180.v:17868$374 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec30_cry_out[0:0] $1\SHIFT_ROT_dec30_cry_out[0:0] - attribute \src "issuer_ls180.v:17869.5-17869.29" - switch \initial - attribute \src "issuer_ls180.v:17869.9-17869.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 - case - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec30_cry_out $0\SHIFT_ROT_dec30_cry_out[0:0] - end - attribute \src "issuer_ls180.v:17905.3-17941.6" - process $proc$issuer_ls180.v:17905$375 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec30_is_32b[0:0] $1\SHIFT_ROT_dec30_is_32b[0:0] - attribute \src "issuer_ls180.v:17906.5-17906.29" - switch \initial - attribute \src "issuer_ls180.v:17906.9-17906.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 - case - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec30_is_32b $0\SHIFT_ROT_dec30_is_32b[0:0] - end - connect \opcode_switch \opcode_in [4:1] -end -attribute \src "issuer_ls180.v:17947.1-18751.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31" -attribute \generator "nMigen" -module \SHIFT_ROT_dec31 - attribute \src "issuer_ls180.v:18714.3-18729.6" - wire width 3 $0\SHIFT_ROT_dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:18730.3-18745.6" - wire width 3 $0\SHIFT_ROT_dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:18602.3-18617.6" - wire width 2 $0\SHIFT_ROT_dec31_cry_in[1:0] - attribute \src "issuer_ls180.v:18618.3-18633.6" - wire $0\SHIFT_ROT_dec31_cry_out[0:0] - attribute \src "issuer_ls180.v:18666.3-18681.6" - wire width 12 $0\SHIFT_ROT_dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:18698.3-18713.6" - wire width 4 $0\SHIFT_ROT_dec31_in2_sel[3:0] - attribute \src "issuer_ls180.v:18682.3-18697.6" - wire width 7 $0\SHIFT_ROT_dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:18634.3-18649.6" - wire $0\SHIFT_ROT_dec31_is_32b[0:0] - attribute \src "issuer_ls180.v:18586.3-18601.6" - wire width 2 $0\SHIFT_ROT_dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:18650.3-18665.6" - wire $0\SHIFT_ROT_dec31_sgn[0:0] - attribute \src "issuer_ls180.v:17948.7-17948.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:18714.3-18729.6" - wire width 3 $1\SHIFT_ROT_dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:18730.3-18745.6" - wire width 3 $1\SHIFT_ROT_dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:18602.3-18617.6" - wire width 2 $1\SHIFT_ROT_dec31_cry_in[1:0] - attribute \src "issuer_ls180.v:18618.3-18633.6" - wire $1\SHIFT_ROT_dec31_cry_out[0:0] - attribute \src "issuer_ls180.v:18666.3-18681.6" - wire width 12 $1\SHIFT_ROT_dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:18698.3-18713.6" - wire width 4 $1\SHIFT_ROT_dec31_in2_sel[3:0] - attribute \src "issuer_ls180.v:18682.3-18697.6" - wire width 7 $1\SHIFT_ROT_dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:18634.3-18649.6" - wire $1\SHIFT_ROT_dec31_is_32b[0:0] - attribute \src "issuer_ls180.v:18586.3-18601.6" - wire width 2 $1\SHIFT_ROT_dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:18650.3-18665.6" - wire $1\SHIFT_ROT_dec31_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 4 \SHIFT_ROT_dec31_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" + wire \dec31_dec_sub23_dec31_dec_sub23_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \SHIFT_ROT_dec31_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire width 2 \dec31_dec_sub23_dec31_dec_sub23_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub23_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \SHIFT_ROT_dec31_cry_in + wire width 8 \dec31_dec_sub24_dec31_dec_sub24_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 8 \SHIFT_ROT_dec31_cry_out + wire \dec31_dec_sub24_dec31_dec_sub24_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -25937,7 +20413,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in + wire width 3 \dec31_dec_sub24_dec31_dec_sub24_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -25945,15 +20421,47 @@ module \SHIFT_ROT_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out + wire width 3 \dec31_dec_sub24_dec31_dec_sub24_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in + wire width 2 \dec31_dec_sub24_dec31_dec_sub24_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out + wire \dec31_dec_sub24_dec31_dec_sub24_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub24_dec31_dec_sub24_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -25968,7 +20476,15 @@ module \SHIFT_ROT_dec31 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit + wire width 12 \dec31_dec_sub24_dec31_dec_sub24_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub24_dec31_dec_sub24_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -25985,7 +20501,13 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel + wire width 4 \dec31_dec_sub24_dec31_dec_sub24_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub24_dec31_dec_sub24_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -26061,19 +20583,57 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op + wire width 7 \dec31_dec_sub24_dec31_dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub24_dec31_dec_sub24_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b + wire \dec31_dec_sub24_dec31_dec_sub24_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub24_dec31_dec_sub24_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel + wire width 2 \dec31_dec_sub24_dec31_dec_sub24_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn + wire \dec31_dec_sub24_dec31_dec_sub24_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub24_dec31_dec_sub24_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \SHIFT_ROT_dec31_dec_sub24_opcode_in + wire width 32 \dec31_dec_sub24_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub26_dec31_dec_sub26_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -26083,7 +20643,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in + wire width 3 \dec31_dec_sub26_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -26091,30 +20651,70 @@ module \SHIFT_ROT_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out + wire width 3 \dec31_dec_sub26_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in + wire width 2 \dec31_dec_sub26_dec31_dec_sub26_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" + wire \dec31_dec_sub26_dec31_dec_sub26_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub26_dec31_dec_sub26_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit + wire width 12 \dec31_dec_sub26_dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub26_dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -26131,7 +20731,13 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel + wire width 4 \dec31_dec_sub26_dec31_dec_sub26_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub26_dec31_dec_sub26_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -26207,19 +20813,57 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op + wire width 7 \dec31_dec_sub26_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub26_dec31_dec_sub26_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b + wire \dec31_dec_sub26_dec31_dec_sub26_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub26_dec31_dec_sub26_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel + wire width 2 \dec31_dec_sub26_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn + wire \dec31_dec_sub26_dec31_dec_sub26_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub26_dec31_dec_sub26_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \SHIFT_ROT_dec31_dec_sub26_opcode_in + wire width 32 \dec31_dec_sub26_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub27_dec31_dec_sub27_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -26229,7 +20873,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in + wire width 3 \dec31_dec_sub27_dec31_dec_sub27_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -26237,15 +20881,47 @@ module \SHIFT_ROT_dec31 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out + wire width 3 \dec31_dec_sub27_dec31_dec_sub27_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in + wire width 2 \dec31_dec_sub27_dec31_dec_sub27_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out + wire \dec31_dec_sub27_dec31_dec_sub27_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub27_dec31_dec_sub27_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -26260,7 +20936,15 @@ module \SHIFT_ROT_dec31 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit + wire width 12 \dec31_dec_sub27_dec31_dec_sub27_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub27_dec31_dec_sub27_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -26277,7 +20961,13 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel + wire width 4 \dec31_dec_sub27_dec31_dec_sub27_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub27_dec31_dec_sub27_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -26353,19 +21043,115 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op + wire width 7 \dec31_dec_sub27_dec31_dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub27_dec31_dec_sub27_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b + wire \dec31_dec_sub27_dec31_dec_sub27_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub27_dec31_dec_sub27_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel + wire width 2 \dec31_dec_sub27_dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn + wire \dec31_dec_sub27_dec31_dec_sub27_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub27_dec31_dec_sub27_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \SHIFT_ROT_dec31_dec_sub27_opcode_in + wire width 32 \dec31_dec_sub27_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub28_dec31_dec_sub28_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub28_dec31_dec_sub28_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub28_dec31_dec_sub28_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub28_dec31_dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub28_dec31_dec_sub28_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -26380,7 +21166,15 @@ module \SHIFT_ROT_dec31 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \SHIFT_ROT_dec31_function_unit + wire width 12 \dec31_dec_sub28_dec31_dec_sub28_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub28_dec31_dec_sub28_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -26397,7 +21191,13 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 3 \SHIFT_ROT_dec31_in2_sel + wire width 4 \dec31_dec_sub28_dec31_dec_sub28_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub28_dec31_dec_sub28_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -26473,441 +21273,57 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \SHIFT_ROT_dec31_internal_op + wire width 7 \dec31_dec_sub28_dec31_dec_sub28_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub28_dec31_dec_sub28_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 9 \SHIFT_ROT_dec31_is_32b + wire \dec31_dec_sub28_dec31_dec_sub28_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub28_dec31_dec_sub28_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 6 \SHIFT_ROT_dec31_rc_sel + wire width 2 \dec31_dec_sub28_dec31_dec_sub28_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \SHIFT_ROT_dec31_sgn - attribute \src "issuer_ls180.v:17948.7-17948.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" - wire width 5 \opc_in + wire \dec31_dec_sub28_dec31_dec_sub28_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub28_dec31_dec_sub28_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 11 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 10 \opcode_switch - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:18547.29-18559.4" - cell \SHIFT_ROT_dec31_dec_sub24 \SHIFT_ROT_dec31_dec_sub24 - connect \SHIFT_ROT_dec31_dec_sub24_cr_in \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in - connect \SHIFT_ROT_dec31_dec_sub24_cr_out \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out - connect \SHIFT_ROT_dec31_dec_sub24_cry_in \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in - connect \SHIFT_ROT_dec31_dec_sub24_cry_out \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out - connect \SHIFT_ROT_dec31_dec_sub24_function_unit \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit - connect \SHIFT_ROT_dec31_dec_sub24_in2_sel \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel - connect \SHIFT_ROT_dec31_dec_sub24_internal_op \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op - connect \SHIFT_ROT_dec31_dec_sub24_is_32b \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b - connect \SHIFT_ROT_dec31_dec_sub24_rc_sel \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel - connect \SHIFT_ROT_dec31_dec_sub24_sgn \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn - connect \opcode_in \SHIFT_ROT_dec31_dec_sub24_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:18560.29-18572.4" - cell \SHIFT_ROT_dec31_dec_sub26 \SHIFT_ROT_dec31_dec_sub26 - connect \SHIFT_ROT_dec31_dec_sub26_cr_in \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in - connect \SHIFT_ROT_dec31_dec_sub26_cr_out \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out - connect \SHIFT_ROT_dec31_dec_sub26_cry_in \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in - connect \SHIFT_ROT_dec31_dec_sub26_cry_out \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out - connect \SHIFT_ROT_dec31_dec_sub26_function_unit \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit - connect \SHIFT_ROT_dec31_dec_sub26_in2_sel \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel - connect \SHIFT_ROT_dec31_dec_sub26_internal_op \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op - connect \SHIFT_ROT_dec31_dec_sub26_is_32b \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b - connect \SHIFT_ROT_dec31_dec_sub26_rc_sel \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel - connect \SHIFT_ROT_dec31_dec_sub26_sgn \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn - connect \opcode_in \SHIFT_ROT_dec31_dec_sub26_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:18573.29-18585.4" - cell \SHIFT_ROT_dec31_dec_sub27 \SHIFT_ROT_dec31_dec_sub27 - connect \SHIFT_ROT_dec31_dec_sub27_cr_in \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in - connect \SHIFT_ROT_dec31_dec_sub27_cr_out \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out - connect \SHIFT_ROT_dec31_dec_sub27_cry_in \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in - connect \SHIFT_ROT_dec31_dec_sub27_cry_out \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out - connect \SHIFT_ROT_dec31_dec_sub27_function_unit \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit - connect \SHIFT_ROT_dec31_dec_sub27_in2_sel \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel - connect \SHIFT_ROT_dec31_dec_sub27_internal_op \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op - connect \SHIFT_ROT_dec31_dec_sub27_is_32b \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b - connect \SHIFT_ROT_dec31_dec_sub27_rc_sel \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel - connect \SHIFT_ROT_dec31_dec_sub27_sgn \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn - connect \opcode_in \SHIFT_ROT_dec31_dec_sub27_opcode_in - end - attribute \src "issuer_ls180.v:17948.7-17948.20" - process $proc$issuer_ls180.v:17948$387 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:18586.3-18601.6" - process $proc$issuer_ls180.v:18586$377 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_rc_sel[1:0] $1\SHIFT_ROT_dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:18587.5-18587.29" - switch \initial - attribute \src "issuer_ls180.v:18587.9-18587.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\SHIFT_ROT_dec31_rc_sel[1:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_rc_sel[1:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_rc_sel[1:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel - case - assign $1\SHIFT_ROT_dec31_rc_sel[1:0] 2'00 - end - sync always - update \SHIFT_ROT_dec31_rc_sel $0\SHIFT_ROT_dec31_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:18602.3-18617.6" - process $proc$issuer_ls180.v:18602$378 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_cry_in[1:0] $1\SHIFT_ROT_dec31_cry_in[1:0] - attribute \src "issuer_ls180.v:18603.5-18603.29" - switch \initial - attribute \src "issuer_ls180.v:18603.9-18603.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\SHIFT_ROT_dec31_cry_in[1:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_cry_in[1:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_cry_in[1:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in - case - assign $1\SHIFT_ROT_dec31_cry_in[1:0] 2'00 - end - sync always - update \SHIFT_ROT_dec31_cry_in $0\SHIFT_ROT_dec31_cry_in[1:0] - end - attribute \src "issuer_ls180.v:18618.3-18633.6" - process $proc$issuer_ls180.v:18618$379 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_cry_out[0:0] $1\SHIFT_ROT_dec31_cry_out[0:0] - attribute \src "issuer_ls180.v:18619.5-18619.29" - switch \initial - attribute \src "issuer_ls180.v:18619.9-18619.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\SHIFT_ROT_dec31_cry_out[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_cry_out[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_cry_out[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out - case - assign $1\SHIFT_ROT_dec31_cry_out[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_cry_out $0\SHIFT_ROT_dec31_cry_out[0:0] - end - attribute \src "issuer_ls180.v:18634.3-18649.6" - process $proc$issuer_ls180.v:18634$380 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_is_32b[0:0] $1\SHIFT_ROT_dec31_is_32b[0:0] - attribute \src "issuer_ls180.v:18635.5-18635.29" - switch \initial - attribute \src "issuer_ls180.v:18635.9-18635.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\SHIFT_ROT_dec31_is_32b[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_is_32b[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_is_32b[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b - case - assign $1\SHIFT_ROT_dec31_is_32b[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_is_32b $0\SHIFT_ROT_dec31_is_32b[0:0] - end - attribute \src "issuer_ls180.v:18650.3-18665.6" - process $proc$issuer_ls180.v:18650$381 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_sgn[0:0] $1\SHIFT_ROT_dec31_sgn[0:0] - attribute \src "issuer_ls180.v:18651.5-18651.29" - switch \initial - attribute \src "issuer_ls180.v:18651.9-18651.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\SHIFT_ROT_dec31_sgn[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_sgn[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_sgn[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn - case - assign $1\SHIFT_ROT_dec31_sgn[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_sgn $0\SHIFT_ROT_dec31_sgn[0:0] - end - attribute \src "issuer_ls180.v:18666.3-18681.6" - process $proc$issuer_ls180.v:18666$382 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_function_unit[11:0] $1\SHIFT_ROT_dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:18667.5-18667.29" - switch \initial - attribute \src "issuer_ls180.v:18667.9-18667.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\SHIFT_ROT_dec31_function_unit[11:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_function_unit[11:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_function_unit[11:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit - case - assign $1\SHIFT_ROT_dec31_function_unit[11:0] 12'000000000000 - end - sync always - update \SHIFT_ROT_dec31_function_unit $0\SHIFT_ROT_dec31_function_unit[11:0] - end - attribute \src "issuer_ls180.v:18682.3-18697.6" - process $proc$issuer_ls180.v:18682$383 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_internal_op[6:0] $1\SHIFT_ROT_dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:18683.5-18683.29" - switch \initial - attribute \src "issuer_ls180.v:18683.9-18683.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\SHIFT_ROT_dec31_internal_op[6:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_internal_op[6:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_internal_op[6:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op - case - assign $1\SHIFT_ROT_dec31_internal_op[6:0] 7'0000000 - end - sync always - update \SHIFT_ROT_dec31_internal_op $0\SHIFT_ROT_dec31_internal_op[6:0] - end - attribute \src "issuer_ls180.v:18698.3-18713.6" - process $proc$issuer_ls180.v:18698$384 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_in2_sel[3:0] $1\SHIFT_ROT_dec31_in2_sel[3:0] - attribute \src "issuer_ls180.v:18699.5-18699.29" - switch \initial - attribute \src "issuer_ls180.v:18699.9-18699.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\SHIFT_ROT_dec31_in2_sel[3:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_in2_sel[3:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_in2_sel[3:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel - case - assign $1\SHIFT_ROT_dec31_in2_sel[3:0] 4'0000 - end - sync always - update \SHIFT_ROT_dec31_in2_sel $0\SHIFT_ROT_dec31_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:18714.3-18729.6" - process $proc$issuer_ls180.v:18714$385 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_cr_in[2:0] $1\SHIFT_ROT_dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:18715.5-18715.29" - switch \initial - attribute \src "issuer_ls180.v:18715.9-18715.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\SHIFT_ROT_dec31_cr_in[2:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_cr_in[2:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_cr_in[2:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in - case - assign $1\SHIFT_ROT_dec31_cr_in[2:0] 3'000 - end - sync always - update \SHIFT_ROT_dec31_cr_in $0\SHIFT_ROT_dec31_cr_in[2:0] - end - attribute \src "issuer_ls180.v:18730.3-18745.6" - process $proc$issuer_ls180.v:18730$386 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_cr_out[2:0] $1\SHIFT_ROT_dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:18731.5-18731.29" - switch \initial - attribute \src "issuer_ls180.v:18731.9-18731.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\SHIFT_ROT_dec31_cr_out[2:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_cr_out[2:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_cr_out[2:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out - case - assign $1\SHIFT_ROT_dec31_cr_out[2:0] 3'000 - end - sync always - update \SHIFT_ROT_dec31_cr_out $0\SHIFT_ROT_dec31_cr_out[2:0] - end - connect \SHIFT_ROT_dec31_dec_sub24_opcode_in \opcode_in - connect \SHIFT_ROT_dec31_dec_sub27_opcode_in \opcode_in - connect \SHIFT_ROT_dec31_dec_sub26_opcode_in \opcode_in - connect \opc_in \opcode_switch [4:0] - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "issuer_ls180.v:18755.1-19106.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub24" -attribute \generator "nMigen" -module \SHIFT_ROT_dec31_dec_sub24 - attribute \src "issuer_ls180.v:18991.3-19009.6" - wire width 3 $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] - attribute \src "issuer_ls180.v:19010.3-19028.6" - wire width 3 $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] - attribute \src "issuer_ls180.v:19048.3-19066.6" - wire width 2 $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] - attribute \src "issuer_ls180.v:19067.3-19085.6" - wire $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] - attribute \src "issuer_ls180.v:18915.3-18933.6" - wire width 12 $0\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] - attribute \src "issuer_ls180.v:18972.3-18990.6" - wire width 4 $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] - attribute \src "issuer_ls180.v:18953.3-18971.6" - wire width 7 $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] - attribute \src "issuer_ls180.v:19086.3-19104.6" - wire $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] - attribute \src "issuer_ls180.v:19029.3-19047.6" - wire width 2 $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] - attribute \src "issuer_ls180.v:18934.3-18952.6" - wire $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] - attribute \src "issuer_ls180.v:18756.7-18756.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:18991.3-19009.6" - wire width 3 $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] - attribute \src "issuer_ls180.v:19010.3-19028.6" - wire width 3 $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] - attribute \src "issuer_ls180.v:19048.3-19066.6" - wire width 2 $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] - attribute \src "issuer_ls180.v:19067.3-19085.6" - wire $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] - attribute \src "issuer_ls180.v:18915.3-18933.6" - wire width 12 $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] - attribute \src "issuer_ls180.v:18972.3-18990.6" - wire width 4 $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] - attribute \src "issuer_ls180.v:18953.3-18971.6" - wire width 7 $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] - attribute \src "issuer_ls180.v:19086.3-19104.6" - wire $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] - attribute \src "issuer_ls180.v:19029.3-19047.6" - wire width 2 $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] - attribute \src "issuer_ls180.v:18934.3-18952.6" - wire $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] + wire width 32 \dec31_dec_sub28_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub4_dec31_dec_sub4_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -26917,7 +21333,7 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub24_cr_in + wire width 3 \dec31_dec_sub4_dec31_dec_sub4_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -26925,15 +21341,47 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub24_cr_out + wire width 3 \dec31_dec_sub4_dec31_dec_sub4_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub24_cry_in + wire width 2 \dec31_dec_sub4_dec31_dec_sub4_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 8 \SHIFT_ROT_dec31_dec_sub24_cry_out + wire \dec31_dec_sub4_dec31_dec_sub4_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub4_dec31_dec_sub4_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -26948,7 +21396,15 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \SHIFT_ROT_dec31_dec_sub24_function_unit + wire width 12 \dec31_dec_sub4_dec31_dec_sub4_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub4_dec31_dec_sub4_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -26965,7 +21421,13 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub24_in2_sel + wire width 4 \dec31_dec_sub4_dec31_dec_sub4_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub4_dec31_dec_sub4_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -27041,430 +21503,57 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub24_internal_op + wire width 7 \dec31_dec_sub4_dec31_dec_sub4_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub4_dec31_dec_sub4_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 9 \SHIFT_ROT_dec31_dec_sub24_is_32b + wire \dec31_dec_sub4_dec31_dec_sub4_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub4_dec31_dec_sub4_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub24_rc_sel + wire width 2 \dec31_dec_sub4_dec31_dec_sub4_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \SHIFT_ROT_dec31_dec_sub24_sgn - attribute \src "issuer_ls180.v:18756.7-18756.15" - wire \initial + wire \dec31_dec_sub4_dec31_dec_sub4_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub4_dec31_dec_sub4_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 11 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:18756.7-18756.20" - process $proc$issuer_ls180.v:18756$398 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:18915.3-18933.6" - process $proc$issuer_ls180.v:18915$388 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] - attribute \src "issuer_ls180.v:18916.5-18916.29" - switch \initial - attribute \src "issuer_ls180.v:18916.9-18916.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000001000 - case - assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000000000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub24_function_unit $0\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] - end - attribute \src "issuer_ls180.v:18934.3-18952.6" - process $proc$issuer_ls180.v:18934$389 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] - attribute \src "issuer_ls180.v:18935.5-18935.29" - switch \initial - attribute \src "issuer_ls180.v:18935.9-18935.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'0 - case - assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_dec_sub24_sgn $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] - end - attribute \src "issuer_ls180.v:18953.3-18971.6" - process $proc$issuer_ls180.v:18953$390 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] - attribute \src "issuer_ls180.v:18954.5-18954.29" - switch \initial - attribute \src "issuer_ls180.v:18954.9-18954.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111101 - case - assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0000000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub24_internal_op $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] - end - attribute \src "issuer_ls180.v:18972.3-18990.6" - process $proc$issuer_ls180.v:18972$391 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] - attribute \src "issuer_ls180.v:18973.5-18973.29" - switch \initial - attribute \src "issuer_ls180.v:18973.9-18973.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'1011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0001 - case - assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub24_in2_sel $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:18991.3-19009.6" - process $proc$issuer_ls180.v:18991$392 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] - attribute \src "issuer_ls180.v:18992.5-18992.29" - switch \initial - attribute \src "issuer_ls180.v:18992.9-18992.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 - case - assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub24_cr_in $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] - end - attribute \src "issuer_ls180.v:19010.3-19028.6" - process $proc$issuer_ls180.v:19010$393 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] - attribute \src "issuer_ls180.v:19011.5-19011.29" - switch \initial - attribute \src "issuer_ls180.v:19011.9-19011.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 - case - assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub24_cr_out $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] - end - attribute \src "issuer_ls180.v:19029.3-19047.6" - process $proc$issuer_ls180.v:19029$394 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] - attribute \src "issuer_ls180.v:19030.5-19030.29" - switch \initial - attribute \src "issuer_ls180.v:19030.9-19030.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 - case - assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'00 - end - sync always - update \SHIFT_ROT_dec31_dec_sub24_rc_sel $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:19048.3-19066.6" - process $proc$issuer_ls180.v:19048$395 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] - attribute \src "issuer_ls180.v:19049.5-19049.29" - switch \initial - attribute \src "issuer_ls180.v:19049.9-19049.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 - case - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 - end - sync always - update \SHIFT_ROT_dec31_dec_sub24_cry_in $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] - end - attribute \src "issuer_ls180.v:19067.3-19085.6" - process $proc$issuer_ls180.v:19067$396 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] - attribute \src "issuer_ls180.v:19068.5-19068.29" - switch \initial - attribute \src "issuer_ls180.v:19068.9-19068.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 - case - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_dec_sub24_cry_out $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] - end - attribute \src "issuer_ls180.v:19086.3-19104.6" - process $proc$issuer_ls180.v:19086$397 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] - attribute \src "issuer_ls180.v:19087.5-19087.29" - switch \initial - attribute \src "issuer_ls180.v:19087.9-19087.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 - case - assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_dec_sub24_is_32b $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:19110.1-19431.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub26" -attribute \generator "nMigen" -module \SHIFT_ROT_dec31_dec_sub26 - attribute \src "issuer_ls180.v:19334.3-19349.6" - wire width 3 $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] - attribute \src "issuer_ls180.v:19350.3-19365.6" - wire width 3 $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] - attribute \src "issuer_ls180.v:19382.3-19397.6" - wire width 2 $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] - attribute \src "issuer_ls180.v:19398.3-19413.6" - wire $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] - attribute \src "issuer_ls180.v:19270.3-19285.6" - wire width 12 $0\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] - attribute \src "issuer_ls180.v:19318.3-19333.6" - wire width 4 $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] - attribute \src "issuer_ls180.v:19302.3-19317.6" - wire width 7 $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] - attribute \src "issuer_ls180.v:19414.3-19429.6" - wire $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] - attribute \src "issuer_ls180.v:19366.3-19381.6" - wire width 2 $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] - attribute \src "issuer_ls180.v:19286.3-19301.6" - wire $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] - attribute \src "issuer_ls180.v:19111.7-19111.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:19334.3-19349.6" - wire width 3 $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] - attribute \src "issuer_ls180.v:19350.3-19365.6" - wire width 3 $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] - attribute \src "issuer_ls180.v:19382.3-19397.6" - wire width 2 $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] - attribute \src "issuer_ls180.v:19398.3-19413.6" - wire $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] - attribute \src "issuer_ls180.v:19270.3-19285.6" - wire width 12 $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] - attribute \src "issuer_ls180.v:19318.3-19333.6" - wire width 4 $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] - attribute \src "issuer_ls180.v:19302.3-19317.6" - wire width 7 $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] - attribute \src "issuer_ls180.v:19414.3-19429.6" - wire $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] - attribute \src "issuer_ls180.v:19366.3-19381.6" - wire width 2 $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] - attribute \src "issuer_ls180.v:19286.3-19301.6" - wire $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] + wire width 32 \dec31_dec_sub4_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub8_dec31_dec_sub8_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -27474,7 +21563,7 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub26_cr_in + wire width 3 \dec31_dec_sub8_dec31_dec_sub8_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -27482,15 +21571,47 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub26_cr_out + wire width 3 \dec31_dec_sub8_dec31_dec_sub8_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub26_cry_in + wire width 2 \dec31_dec_sub8_dec31_dec_sub8_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 8 \SHIFT_ROT_dec31_dec_sub26_cry_out + wire \dec31_dec_sub8_dec31_dec_sub8_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub8_dec31_dec_sub8_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -27505,7 +21626,15 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \SHIFT_ROT_dec31_dec_sub26_function_unit + wire width 12 \dec31_dec_sub8_dec31_dec_sub8_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub8_dec31_dec_sub8_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -27522,7 +21651,13 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub26_in2_sel + wire width 4 \dec31_dec_sub8_dec31_dec_sub8_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub8_dec31_dec_sub8_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -27598,390 +21733,57 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub26_internal_op + wire width 7 \dec31_dec_sub8_dec31_dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub8_dec31_dec_sub8_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 9 \SHIFT_ROT_dec31_dec_sub26_is_32b + wire \dec31_dec_sub8_dec31_dec_sub8_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub8_dec31_dec_sub8_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub26_rc_sel + wire width 2 \dec31_dec_sub8_dec31_dec_sub8_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \SHIFT_ROT_dec31_dec_sub26_sgn - attribute \src "issuer_ls180.v:19111.7-19111.15" - wire \initial + wire \dec31_dec_sub8_dec31_dec_sub8_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub8_dec31_dec_sub8_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 11 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:19111.7-19111.20" - process $proc$issuer_ls180.v:19111$409 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:19270.3-19285.6" - process $proc$issuer_ls180.v:19270$399 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] - attribute \src "issuer_ls180.v:19271.5-19271.29" - switch \initial - attribute \src "issuer_ls180.v:19271.9-19271.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] 12'000000001000 - case - assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] 12'000000000000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub26_function_unit $0\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] - end - attribute \src "issuer_ls180.v:19286.3-19301.6" - process $proc$issuer_ls180.v:19286$400 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] - attribute \src "issuer_ls180.v:19287.5-19287.29" - switch \initial - attribute \src "issuer_ls180.v:19287.9-19287.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'1 - case - assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_dec_sub26_sgn $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] - end - attribute \src "issuer_ls180.v:19302.3-19317.6" - process $proc$issuer_ls180.v:19302$401 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] - attribute \src "issuer_ls180.v:19303.5-19303.29" - switch \initial - attribute \src "issuer_ls180.v:19303.9-19303.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0100000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0111101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0111101 - case - assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0000000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub26_internal_op $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] - end - attribute \src "issuer_ls180.v:19318.3-19333.6" - process $proc$issuer_ls180.v:19318$402 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] - attribute \src "issuer_ls180.v:19319.5-19319.29" - switch \initial - attribute \src "issuer_ls180.v:19319.9-19319.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'1010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'1010 - case - assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'0000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub26_in2_sel $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:19334.3-19349.6" - process $proc$issuer_ls180.v:19334$403 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] - attribute \src "issuer_ls180.v:19335.5-19335.29" - switch \initial - attribute \src "issuer_ls180.v:19335.9-19335.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 - case - assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub26_cr_in $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] - end - attribute \src "issuer_ls180.v:19350.3-19365.6" - process $proc$issuer_ls180.v:19350$404 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] - attribute \src "issuer_ls180.v:19351.5-19351.29" - switch \initial - attribute \src "issuer_ls180.v:19351.9-19351.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'001 - case - assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub26_cr_out $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] - end - attribute \src "issuer_ls180.v:19366.3-19381.6" - process $proc$issuer_ls180.v:19366$405 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] - attribute \src "issuer_ls180.v:19367.5-19367.29" - switch \initial - attribute \src "issuer_ls180.v:19367.9-19367.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'10 - case - assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'00 - end - sync always - update \SHIFT_ROT_dec31_dec_sub26_rc_sel $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:19382.3-19397.6" - process $proc$issuer_ls180.v:19382$406 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] - attribute \src "issuer_ls180.v:19383.5-19383.29" - switch \initial - attribute \src "issuer_ls180.v:19383.9-19383.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 - case - assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 - end - sync always - update \SHIFT_ROT_dec31_dec_sub26_cry_in $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] - end - attribute \src "issuer_ls180.v:19398.3-19413.6" - process $proc$issuer_ls180.v:19398$407 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] - attribute \src "issuer_ls180.v:19399.5-19399.29" - switch \initial - attribute \src "issuer_ls180.v:19399.9-19399.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'1 - case - assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_dec_sub26_cry_out $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] - end - attribute \src "issuer_ls180.v:19414.3-19429.6" - process $proc$issuer_ls180.v:19414$408 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] - attribute \src "issuer_ls180.v:19415.5-19415.29" - switch \initial - attribute \src "issuer_ls180.v:19415.9-19415.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 - case - assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_dec_sub26_is_32b $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:19435.1-19786.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub27" -attribute \generator "nMigen" -module \SHIFT_ROT_dec31_dec_sub27 - attribute \src "issuer_ls180.v:19671.3-19689.6" - wire width 3 $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] - attribute \src "issuer_ls180.v:19690.3-19708.6" - wire width 3 $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] - attribute \src "issuer_ls180.v:19728.3-19746.6" - wire width 2 $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] - attribute \src "issuer_ls180.v:19747.3-19765.6" - wire $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] - attribute \src "issuer_ls180.v:19595.3-19613.6" - wire width 12 $0\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] - attribute \src "issuer_ls180.v:19652.3-19670.6" - wire width 4 $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] - attribute \src "issuer_ls180.v:19633.3-19651.6" - wire width 7 $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] - attribute \src "issuer_ls180.v:19766.3-19784.6" - wire $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] - attribute \src "issuer_ls180.v:19709.3-19727.6" - wire width 2 $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] - attribute \src "issuer_ls180.v:19614.3-19632.6" - wire $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] - attribute \src "issuer_ls180.v:19436.7-19436.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:19671.3-19689.6" - wire width 3 $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] - attribute \src "issuer_ls180.v:19690.3-19708.6" - wire width 3 $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] - attribute \src "issuer_ls180.v:19728.3-19746.6" - wire width 2 $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] - attribute \src "issuer_ls180.v:19747.3-19765.6" - wire $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] - attribute \src "issuer_ls180.v:19595.3-19613.6" - wire width 12 $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] - attribute \src "issuer_ls180.v:19652.3-19670.6" - wire width 4 $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] - attribute \src "issuer_ls180.v:19633.3-19651.6" - wire width 7 $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] - attribute \src "issuer_ls180.v:19766.3-19784.6" - wire $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] - attribute \src "issuer_ls180.v:19709.3-19727.6" - wire width 2 $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] - attribute \src "issuer_ls180.v:19614.3-19632.6" - wire $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] + wire width 32 \dec31_dec_sub8_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub9_dec31_dec_sub9_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -27991,7 +21793,7 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub27_cr_in + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -27999,15 +21801,47 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub27_cr_out + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub27_cry_in + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 8 \SHIFT_ROT_dec31_dec_sub27_cry_out + wire \dec31_dec_sub9_dec31_dec_sub9_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub9_dec31_dec_sub9_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -28022,7 +21856,15 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \SHIFT_ROT_dec31_dec_sub27_function_unit + wire width 12 \dec31_dec_sub9_dec31_dec_sub9_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -28039,7 +21881,13 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub27_in2_sel + wire width 4 \dec31_dec_sub9_dec31_dec_sub9_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -28115,450 +21963,85 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub27_internal_op + wire width 7 \dec31_dec_sub9_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub9_dec31_dec_sub9_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 9 \SHIFT_ROT_dec31_dec_sub27_is_32b + wire \dec31_dec_sub9_dec31_dec_sub9_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub27_rc_sel + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \SHIFT_ROT_dec31_dec_sub27_sgn - attribute \src "issuer_ls180.v:19436.7-19436.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 11 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:19436.7-19436.20" - process $proc$issuer_ls180.v:19436$420 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:19595.3-19613.6" - process $proc$issuer_ls180.v:19595$410 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] - attribute \src "issuer_ls180.v:19596.5-19596.29" - switch \initial - attribute \src "issuer_ls180.v:19596.9-19596.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000001000 - case - assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000000000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub27_function_unit $0\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] - end - attribute \src "issuer_ls180.v:19614.3-19632.6" - process $proc$issuer_ls180.v:19614$411 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] - attribute \src "issuer_ls180.v:19615.5-19615.29" - switch \initial - attribute \src "issuer_ls180.v:19615.9-19615.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 - case - assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_dec_sub27_sgn $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] - end - attribute \src "issuer_ls180.v:19633.3-19651.6" - process $proc$issuer_ls180.v:19633$412 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] - attribute \src "issuer_ls180.v:19634.5-19634.29" - switch \initial - attribute \src "issuer_ls180.v:19634.9-19634.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0100000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0111100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0111101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0111101 - case - assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0000000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub27_internal_op $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] - end - attribute \src "issuer_ls180.v:19652.3-19670.6" - process $proc$issuer_ls180.v:19652$413 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] - attribute \src "issuer_ls180.v:19653.5-19653.29" - switch \initial - attribute \src "issuer_ls180.v:19653.9-19653.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'1010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'1010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'0001 - case - assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'0000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub27_in2_sel $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:19671.3-19689.6" - process $proc$issuer_ls180.v:19671$414 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] - attribute \src "issuer_ls180.v:19672.5-19672.29" - switch \initial - attribute \src "issuer_ls180.v:19672.9-19672.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 - case - assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub27_cr_in $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] - end - attribute \src "issuer_ls180.v:19690.3-19708.6" - process $proc$issuer_ls180.v:19690$415 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] - attribute \src "issuer_ls180.v:19691.5-19691.29" - switch \initial - attribute \src "issuer_ls180.v:19691.9-19691.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 - case - assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub27_cr_out $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] - end - attribute \src "issuer_ls180.v:19709.3-19727.6" - process $proc$issuer_ls180.v:19709$416 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] - attribute \src "issuer_ls180.v:19710.5-19710.29" - switch \initial - attribute \src "issuer_ls180.v:19710.9-19710.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 - case - assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'00 - end - sync always - update \SHIFT_ROT_dec31_dec_sub27_rc_sel $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:19728.3-19746.6" - process $proc$issuer_ls180.v:19728$417 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] - attribute \src "issuer_ls180.v:19729.5-19729.29" - switch \initial - attribute \src "issuer_ls180.v:19729.9-19729.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 - case - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 - end - sync always - update \SHIFT_ROT_dec31_dec_sub27_cry_in $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] - end - attribute \src "issuer_ls180.v:19747.3-19765.6" - process $proc$issuer_ls180.v:19747$418 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] - attribute \src "issuer_ls180.v:19748.5-19748.29" - switch \initial - attribute \src "issuer_ls180.v:19748.9-19748.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 - case - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_dec_sub27_cry_out $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] - end - attribute \src "issuer_ls180.v:19766.3-19784.6" - process $proc$issuer_ls180.v:19766$419 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] - attribute \src "issuer_ls180.v:19767.5-19767.29" - switch \initial - attribute \src "issuer_ls180.v:19767.9-19767.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 - case - assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_dec_sub27_is_32b $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:19790.1-20112.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31" -attribute \generator "nMigen" -module \SPR_dec31 - attribute \src "issuer_ls180.v:20069.3-20078.6" - wire width 3 $0\SPR_dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:20079.3-20088.6" - wire width 3 $0\SPR_dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:20049.3-20058.6" - wire width 12 $0\SPR_dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:20059.3-20068.6" - wire width 7 $0\SPR_dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:20099.3-20108.6" - wire $0\SPR_dec31_is_32b[0:0] - attribute \src "issuer_ls180.v:20089.3-20098.6" - wire width 2 $0\SPR_dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:19791.7-19791.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:20069.3-20078.6" - wire width 3 $1\SPR_dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:20079.3-20088.6" - wire width 3 $1\SPR_dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:20049.3-20058.6" - wire width 12 $1\SPR_dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:20059.3-20068.6" - wire width 7 $1\SPR_dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:20099.3-20108.6" - wire $1\SPR_dec31_is_32b[0:0] - attribute \src "issuer_ls180.v:20089.3-20098.6" - wire width 2 $1\SPR_dec31_rc_sel[1:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \SPR_dec31_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 4 \SPR_dec31_cr_out - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" + wire \dec31_dec_sub9_dec31_dec_sub9_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub9_opcode_in + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out + wire width 5 output 3 \dec31_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -28573,108 +22056,38 @@ module \SPR_dec31 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" + wire width 12 output 1 \dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" + wire width 3 output 5 \dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \SPR_dec31_dec_sub19_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" + wire width 4 output 6 \dec31_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \SPR_dec31_function_unit + wire width 2 output 7 \dec31_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -28750,5297 +22163,2959 @@ module \SPR_dec31 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \SPR_dec31_internal_op + wire width 7 output 2 \dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 6 \SPR_dec31_is_32b + wire output 23 \dec31_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 5 \SPR_dec31_rc_sel - attribute \src "issuer_ls180.v:19791.7-19791.15" + wire width 2 output 13 \dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_upd + attribute \src "libresoc.v:11695.7-11695.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" wire width 5 \opc_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 7 \opcode_in + wire width 32 input 25 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:20040.23-20048.4" - cell \SPR_dec31_dec_sub19 \SPR_dec31_dec_sub19 - connect \SPR_dec31_dec_sub19_cr_in \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in - connect \SPR_dec31_dec_sub19_cr_out \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out - connect \SPR_dec31_dec_sub19_function_unit \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit - connect \SPR_dec31_dec_sub19_internal_op \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op - connect \SPR_dec31_dec_sub19_is_32b \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b - connect \SPR_dec31_dec_sub19_rc_sel \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel - connect \opcode_in \SPR_dec31_dec_sub19_opcode_in - end - attribute \src "issuer_ls180.v:19791.7-19791.20" - process $proc$issuer_ls180.v:19791$427 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:20049.3-20058.6" - process $proc$issuer_ls180.v:20049$421 - assign { } { } - assign { } { } - assign $0\SPR_dec31_function_unit[11:0] $1\SPR_dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:20050.5-20050.29" - switch \initial - attribute \src "issuer_ls180.v:20050.9-20050.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\SPR_dec31_function_unit[11:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit - case - assign $1\SPR_dec31_function_unit[11:0] 12'000000000000 - end - sync always - update \SPR_dec31_function_unit $0\SPR_dec31_function_unit[11:0] + attribute \src "libresoc.v:16094.18-16120.4" + cell \dec31_dec_sub0 \dec31_dec_sub0 + connect \dec31_dec_sub0_asmcode \dec31_dec_sub0_dec31_dec_sub0_asmcode + connect \dec31_dec_sub0_br \dec31_dec_sub0_dec31_dec_sub0_br + connect \dec31_dec_sub0_cr_in \dec31_dec_sub0_dec31_dec_sub0_cr_in + connect \dec31_dec_sub0_cr_out \dec31_dec_sub0_dec31_dec_sub0_cr_out + connect \dec31_dec_sub0_cry_in \dec31_dec_sub0_dec31_dec_sub0_cry_in + connect \dec31_dec_sub0_cry_out \dec31_dec_sub0_dec31_dec_sub0_cry_out + connect \dec31_dec_sub0_form \dec31_dec_sub0_dec31_dec_sub0_form + connect \dec31_dec_sub0_function_unit \dec31_dec_sub0_dec31_dec_sub0_function_unit + connect \dec31_dec_sub0_in1_sel \dec31_dec_sub0_dec31_dec_sub0_in1_sel + connect \dec31_dec_sub0_in2_sel \dec31_dec_sub0_dec31_dec_sub0_in2_sel + connect \dec31_dec_sub0_in3_sel \dec31_dec_sub0_dec31_dec_sub0_in3_sel + connect \dec31_dec_sub0_internal_op \dec31_dec_sub0_dec31_dec_sub0_internal_op + connect \dec31_dec_sub0_inv_a \dec31_dec_sub0_dec31_dec_sub0_inv_a + connect \dec31_dec_sub0_inv_out \dec31_dec_sub0_dec31_dec_sub0_inv_out + connect \dec31_dec_sub0_is_32b \dec31_dec_sub0_dec31_dec_sub0_is_32b + connect \dec31_dec_sub0_ldst_len \dec31_dec_sub0_dec31_dec_sub0_ldst_len + connect \dec31_dec_sub0_lk \dec31_dec_sub0_dec31_dec_sub0_lk + connect \dec31_dec_sub0_out_sel \dec31_dec_sub0_dec31_dec_sub0_out_sel + connect \dec31_dec_sub0_rc_sel \dec31_dec_sub0_dec31_dec_sub0_rc_sel + connect \dec31_dec_sub0_rsrv \dec31_dec_sub0_dec31_dec_sub0_rsrv + connect \dec31_dec_sub0_sgl_pipe \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe + connect \dec31_dec_sub0_sgn \dec31_dec_sub0_dec31_dec_sub0_sgn + connect \dec31_dec_sub0_sgn_ext \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + connect \dec31_dec_sub0_upd \dec31_dec_sub0_dec31_dec_sub0_upd + connect \opcode_in \dec31_dec_sub0_opcode_in end - attribute \src "issuer_ls180.v:20059.3-20068.6" - process $proc$issuer_ls180.v:20059$422 - assign { } { } - assign { } { } - assign $0\SPR_dec31_internal_op[6:0] $1\SPR_dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:20060.5-20060.29" - switch \initial - attribute \src "issuer_ls180.v:20060.9-20060.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\SPR_dec31_internal_op[6:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op - case - assign $1\SPR_dec31_internal_op[6:0] 7'0000000 - end - sync always - update \SPR_dec31_internal_op $0\SPR_dec31_internal_op[6:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:16121.19-16147.4" + cell \dec31_dec_sub10 \dec31_dec_sub10 + connect \dec31_dec_sub10_asmcode \dec31_dec_sub10_dec31_dec_sub10_asmcode + connect \dec31_dec_sub10_br \dec31_dec_sub10_dec31_dec_sub10_br + connect \dec31_dec_sub10_cr_in \dec31_dec_sub10_dec31_dec_sub10_cr_in + connect \dec31_dec_sub10_cr_out \dec31_dec_sub10_dec31_dec_sub10_cr_out + connect \dec31_dec_sub10_cry_in \dec31_dec_sub10_dec31_dec_sub10_cry_in + connect \dec31_dec_sub10_cry_out \dec31_dec_sub10_dec31_dec_sub10_cry_out + connect \dec31_dec_sub10_form \dec31_dec_sub10_dec31_dec_sub10_form + connect \dec31_dec_sub10_function_unit \dec31_dec_sub10_dec31_dec_sub10_function_unit + connect \dec31_dec_sub10_in1_sel \dec31_dec_sub10_dec31_dec_sub10_in1_sel + connect \dec31_dec_sub10_in2_sel \dec31_dec_sub10_dec31_dec_sub10_in2_sel + connect \dec31_dec_sub10_in3_sel \dec31_dec_sub10_dec31_dec_sub10_in3_sel + connect \dec31_dec_sub10_internal_op \dec31_dec_sub10_dec31_dec_sub10_internal_op + connect \dec31_dec_sub10_inv_a \dec31_dec_sub10_dec31_dec_sub10_inv_a + connect \dec31_dec_sub10_inv_out \dec31_dec_sub10_dec31_dec_sub10_inv_out + connect \dec31_dec_sub10_is_32b \dec31_dec_sub10_dec31_dec_sub10_is_32b + connect \dec31_dec_sub10_ldst_len \dec31_dec_sub10_dec31_dec_sub10_ldst_len + connect \dec31_dec_sub10_lk \dec31_dec_sub10_dec31_dec_sub10_lk + connect \dec31_dec_sub10_out_sel \dec31_dec_sub10_dec31_dec_sub10_out_sel + connect \dec31_dec_sub10_rc_sel \dec31_dec_sub10_dec31_dec_sub10_rc_sel + connect \dec31_dec_sub10_rsrv \dec31_dec_sub10_dec31_dec_sub10_rsrv + connect \dec31_dec_sub10_sgl_pipe \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe + connect \dec31_dec_sub10_sgn \dec31_dec_sub10_dec31_dec_sub10_sgn + connect \dec31_dec_sub10_sgn_ext \dec31_dec_sub10_dec31_dec_sub10_sgn_ext + connect \dec31_dec_sub10_upd \dec31_dec_sub10_dec31_dec_sub10_upd + connect \opcode_in \dec31_dec_sub10_opcode_in end - attribute \src "issuer_ls180.v:20069.3-20078.6" - process $proc$issuer_ls180.v:20069$423 - assign { } { } - assign { } { } - assign $0\SPR_dec31_cr_in[2:0] $1\SPR_dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:20070.5-20070.29" - switch \initial - attribute \src "issuer_ls180.v:20070.9-20070.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\SPR_dec31_cr_in[2:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in - case - assign $1\SPR_dec31_cr_in[2:0] 3'000 - end - sync always - update \SPR_dec31_cr_in $0\SPR_dec31_cr_in[2:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:16148.19-16174.4" + cell \dec31_dec_sub11 \dec31_dec_sub11 + connect \dec31_dec_sub11_asmcode \dec31_dec_sub11_dec31_dec_sub11_asmcode + connect \dec31_dec_sub11_br \dec31_dec_sub11_dec31_dec_sub11_br + connect \dec31_dec_sub11_cr_in \dec31_dec_sub11_dec31_dec_sub11_cr_in + connect \dec31_dec_sub11_cr_out \dec31_dec_sub11_dec31_dec_sub11_cr_out + connect \dec31_dec_sub11_cry_in \dec31_dec_sub11_dec31_dec_sub11_cry_in + connect \dec31_dec_sub11_cry_out \dec31_dec_sub11_dec31_dec_sub11_cry_out + connect \dec31_dec_sub11_form \dec31_dec_sub11_dec31_dec_sub11_form + connect \dec31_dec_sub11_function_unit \dec31_dec_sub11_dec31_dec_sub11_function_unit + connect \dec31_dec_sub11_in1_sel \dec31_dec_sub11_dec31_dec_sub11_in1_sel + connect \dec31_dec_sub11_in2_sel \dec31_dec_sub11_dec31_dec_sub11_in2_sel + connect \dec31_dec_sub11_in3_sel \dec31_dec_sub11_dec31_dec_sub11_in3_sel + connect \dec31_dec_sub11_internal_op \dec31_dec_sub11_dec31_dec_sub11_internal_op + connect \dec31_dec_sub11_inv_a \dec31_dec_sub11_dec31_dec_sub11_inv_a + connect \dec31_dec_sub11_inv_out \dec31_dec_sub11_dec31_dec_sub11_inv_out + connect \dec31_dec_sub11_is_32b \dec31_dec_sub11_dec31_dec_sub11_is_32b + connect \dec31_dec_sub11_ldst_len \dec31_dec_sub11_dec31_dec_sub11_ldst_len + connect \dec31_dec_sub11_lk \dec31_dec_sub11_dec31_dec_sub11_lk + connect \dec31_dec_sub11_out_sel \dec31_dec_sub11_dec31_dec_sub11_out_sel + connect \dec31_dec_sub11_rc_sel \dec31_dec_sub11_dec31_dec_sub11_rc_sel + connect \dec31_dec_sub11_rsrv \dec31_dec_sub11_dec31_dec_sub11_rsrv + connect \dec31_dec_sub11_sgl_pipe \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe + connect \dec31_dec_sub11_sgn \dec31_dec_sub11_dec31_dec_sub11_sgn + connect \dec31_dec_sub11_sgn_ext \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + connect \dec31_dec_sub11_upd \dec31_dec_sub11_dec31_dec_sub11_upd + connect \opcode_in \dec31_dec_sub11_opcode_in end - attribute \src "issuer_ls180.v:20079.3-20088.6" - process $proc$issuer_ls180.v:20079$424 - assign { } { } - assign { } { } - assign $0\SPR_dec31_cr_out[2:0] $1\SPR_dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:20080.5-20080.29" - switch \initial - attribute \src "issuer_ls180.v:20080.9-20080.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\SPR_dec31_cr_out[2:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out - case - assign $1\SPR_dec31_cr_out[2:0] 3'000 - end - sync always - update \SPR_dec31_cr_out $0\SPR_dec31_cr_out[2:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:16175.19-16201.4" + cell \dec31_dec_sub15 \dec31_dec_sub15 + connect \dec31_dec_sub15_asmcode \dec31_dec_sub15_dec31_dec_sub15_asmcode + connect \dec31_dec_sub15_br \dec31_dec_sub15_dec31_dec_sub15_br + connect \dec31_dec_sub15_cr_in \dec31_dec_sub15_dec31_dec_sub15_cr_in + connect \dec31_dec_sub15_cr_out \dec31_dec_sub15_dec31_dec_sub15_cr_out + connect \dec31_dec_sub15_cry_in \dec31_dec_sub15_dec31_dec_sub15_cry_in + connect \dec31_dec_sub15_cry_out \dec31_dec_sub15_dec31_dec_sub15_cry_out + connect \dec31_dec_sub15_form \dec31_dec_sub15_dec31_dec_sub15_form + connect \dec31_dec_sub15_function_unit \dec31_dec_sub15_dec31_dec_sub15_function_unit + connect \dec31_dec_sub15_in1_sel \dec31_dec_sub15_dec31_dec_sub15_in1_sel + connect \dec31_dec_sub15_in2_sel \dec31_dec_sub15_dec31_dec_sub15_in2_sel + connect \dec31_dec_sub15_in3_sel \dec31_dec_sub15_dec31_dec_sub15_in3_sel + connect \dec31_dec_sub15_internal_op \dec31_dec_sub15_dec31_dec_sub15_internal_op + connect \dec31_dec_sub15_inv_a \dec31_dec_sub15_dec31_dec_sub15_inv_a + connect \dec31_dec_sub15_inv_out \dec31_dec_sub15_dec31_dec_sub15_inv_out + connect \dec31_dec_sub15_is_32b \dec31_dec_sub15_dec31_dec_sub15_is_32b + connect \dec31_dec_sub15_ldst_len \dec31_dec_sub15_dec31_dec_sub15_ldst_len + connect \dec31_dec_sub15_lk \dec31_dec_sub15_dec31_dec_sub15_lk + connect \dec31_dec_sub15_out_sel \dec31_dec_sub15_dec31_dec_sub15_out_sel + connect \dec31_dec_sub15_rc_sel \dec31_dec_sub15_dec31_dec_sub15_rc_sel + connect \dec31_dec_sub15_rsrv \dec31_dec_sub15_dec31_dec_sub15_rsrv + connect \dec31_dec_sub15_sgl_pipe \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe + connect \dec31_dec_sub15_sgn \dec31_dec_sub15_dec31_dec_sub15_sgn + connect \dec31_dec_sub15_sgn_ext \dec31_dec_sub15_dec31_dec_sub15_sgn_ext + connect \dec31_dec_sub15_upd \dec31_dec_sub15_dec31_dec_sub15_upd + connect \opcode_in \dec31_dec_sub15_opcode_in end - attribute \src "issuer_ls180.v:20089.3-20098.6" - process $proc$issuer_ls180.v:20089$425 - assign { } { } - assign { } { } - assign $0\SPR_dec31_rc_sel[1:0] $1\SPR_dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:20090.5-20090.29" - switch \initial - attribute \src "issuer_ls180.v:20090.9-20090.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\SPR_dec31_rc_sel[1:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel - case - assign $1\SPR_dec31_rc_sel[1:0] 2'00 - end - sync always - update \SPR_dec31_rc_sel $0\SPR_dec31_rc_sel[1:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:16202.19-16228.4" + cell \dec31_dec_sub16 \dec31_dec_sub16 + connect \dec31_dec_sub16_asmcode \dec31_dec_sub16_dec31_dec_sub16_asmcode + connect \dec31_dec_sub16_br \dec31_dec_sub16_dec31_dec_sub16_br + connect \dec31_dec_sub16_cr_in \dec31_dec_sub16_dec31_dec_sub16_cr_in + connect \dec31_dec_sub16_cr_out \dec31_dec_sub16_dec31_dec_sub16_cr_out + connect \dec31_dec_sub16_cry_in \dec31_dec_sub16_dec31_dec_sub16_cry_in + connect \dec31_dec_sub16_cry_out \dec31_dec_sub16_dec31_dec_sub16_cry_out + connect \dec31_dec_sub16_form \dec31_dec_sub16_dec31_dec_sub16_form + connect \dec31_dec_sub16_function_unit \dec31_dec_sub16_dec31_dec_sub16_function_unit + connect \dec31_dec_sub16_in1_sel \dec31_dec_sub16_dec31_dec_sub16_in1_sel + connect \dec31_dec_sub16_in2_sel \dec31_dec_sub16_dec31_dec_sub16_in2_sel + connect \dec31_dec_sub16_in3_sel \dec31_dec_sub16_dec31_dec_sub16_in3_sel + connect \dec31_dec_sub16_internal_op \dec31_dec_sub16_dec31_dec_sub16_internal_op + connect \dec31_dec_sub16_inv_a \dec31_dec_sub16_dec31_dec_sub16_inv_a + connect \dec31_dec_sub16_inv_out \dec31_dec_sub16_dec31_dec_sub16_inv_out + connect \dec31_dec_sub16_is_32b \dec31_dec_sub16_dec31_dec_sub16_is_32b + connect \dec31_dec_sub16_ldst_len \dec31_dec_sub16_dec31_dec_sub16_ldst_len + connect \dec31_dec_sub16_lk \dec31_dec_sub16_dec31_dec_sub16_lk + connect \dec31_dec_sub16_out_sel \dec31_dec_sub16_dec31_dec_sub16_out_sel + connect \dec31_dec_sub16_rc_sel \dec31_dec_sub16_dec31_dec_sub16_rc_sel + connect \dec31_dec_sub16_rsrv \dec31_dec_sub16_dec31_dec_sub16_rsrv + connect \dec31_dec_sub16_sgl_pipe \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe + connect \dec31_dec_sub16_sgn \dec31_dec_sub16_dec31_dec_sub16_sgn + connect \dec31_dec_sub16_sgn_ext \dec31_dec_sub16_dec31_dec_sub16_sgn_ext + connect \dec31_dec_sub16_upd \dec31_dec_sub16_dec31_dec_sub16_upd + connect \opcode_in \dec31_dec_sub16_opcode_in end - attribute \src "issuer_ls180.v:20099.3-20108.6" - process $proc$issuer_ls180.v:20099$426 - assign { } { } - assign { } { } - assign $0\SPR_dec31_is_32b[0:0] $1\SPR_dec31_is_32b[0:0] - attribute \src "issuer_ls180.v:20100.5-20100.29" - switch \initial - attribute \src "issuer_ls180.v:20100.9-20100.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\SPR_dec31_is_32b[0:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b - case - assign $1\SPR_dec31_is_32b[0:0] 1'0 - end - sync always - update \SPR_dec31_is_32b $0\SPR_dec31_is_32b[0:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:16229.19-16255.4" + cell \dec31_dec_sub18 \dec31_dec_sub18 + connect \dec31_dec_sub18_asmcode \dec31_dec_sub18_dec31_dec_sub18_asmcode + connect \dec31_dec_sub18_br \dec31_dec_sub18_dec31_dec_sub18_br + connect \dec31_dec_sub18_cr_in \dec31_dec_sub18_dec31_dec_sub18_cr_in + connect \dec31_dec_sub18_cr_out \dec31_dec_sub18_dec31_dec_sub18_cr_out + connect \dec31_dec_sub18_cry_in \dec31_dec_sub18_dec31_dec_sub18_cry_in + connect \dec31_dec_sub18_cry_out \dec31_dec_sub18_dec31_dec_sub18_cry_out + connect \dec31_dec_sub18_form \dec31_dec_sub18_dec31_dec_sub18_form + connect \dec31_dec_sub18_function_unit \dec31_dec_sub18_dec31_dec_sub18_function_unit + connect \dec31_dec_sub18_in1_sel \dec31_dec_sub18_dec31_dec_sub18_in1_sel + connect \dec31_dec_sub18_in2_sel \dec31_dec_sub18_dec31_dec_sub18_in2_sel + connect \dec31_dec_sub18_in3_sel \dec31_dec_sub18_dec31_dec_sub18_in3_sel + connect \dec31_dec_sub18_internal_op \dec31_dec_sub18_dec31_dec_sub18_internal_op + connect \dec31_dec_sub18_inv_a \dec31_dec_sub18_dec31_dec_sub18_inv_a + connect \dec31_dec_sub18_inv_out \dec31_dec_sub18_dec31_dec_sub18_inv_out + connect \dec31_dec_sub18_is_32b \dec31_dec_sub18_dec31_dec_sub18_is_32b + connect \dec31_dec_sub18_ldst_len \dec31_dec_sub18_dec31_dec_sub18_ldst_len + connect \dec31_dec_sub18_lk \dec31_dec_sub18_dec31_dec_sub18_lk + connect \dec31_dec_sub18_out_sel \dec31_dec_sub18_dec31_dec_sub18_out_sel + connect \dec31_dec_sub18_rc_sel \dec31_dec_sub18_dec31_dec_sub18_rc_sel + connect \dec31_dec_sub18_rsrv \dec31_dec_sub18_dec31_dec_sub18_rsrv + connect \dec31_dec_sub18_sgl_pipe \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe + connect \dec31_dec_sub18_sgn \dec31_dec_sub18_dec31_dec_sub18_sgn + connect \dec31_dec_sub18_sgn_ext \dec31_dec_sub18_dec31_dec_sub18_sgn_ext + connect \dec31_dec_sub18_upd \dec31_dec_sub18_dec31_dec_sub18_upd + connect \opcode_in \dec31_dec_sub18_opcode_in end - connect \SPR_dec31_dec_sub19_opcode_in \opcode_in - connect \opc_in \opcode_switch [4:0] - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "issuer_ls180.v:20116.1-20324.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31.SPR_dec31_dec_sub19" -attribute \generator "nMigen" -module \SPR_dec31_dec_sub19 - attribute \src "issuer_ls180.v:20271.3-20283.6" - wire width 3 $0\SPR_dec31_dec_sub19_cr_in[2:0] - attribute \src "issuer_ls180.v:20284.3-20296.6" - wire width 3 $0\SPR_dec31_dec_sub19_cr_out[2:0] - attribute \src "issuer_ls180.v:20245.3-20257.6" - wire width 12 $0\SPR_dec31_dec_sub19_function_unit[11:0] - attribute \src "issuer_ls180.v:20258.3-20270.6" - wire width 7 $0\SPR_dec31_dec_sub19_internal_op[6:0] - attribute \src "issuer_ls180.v:20310.3-20322.6" - wire $0\SPR_dec31_dec_sub19_is_32b[0:0] - attribute \src "issuer_ls180.v:20297.3-20309.6" - wire width 2 $0\SPR_dec31_dec_sub19_rc_sel[1:0] - attribute \src "issuer_ls180.v:20117.7-20117.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:20271.3-20283.6" - wire width 3 $1\SPR_dec31_dec_sub19_cr_in[2:0] - attribute \src "issuer_ls180.v:20284.3-20296.6" - wire width 3 $1\SPR_dec31_dec_sub19_cr_out[2:0] - attribute \src "issuer_ls180.v:20245.3-20257.6" - wire width 12 $1\SPR_dec31_dec_sub19_function_unit[11:0] - attribute \src "issuer_ls180.v:20258.3-20270.6" - wire width 7 $1\SPR_dec31_dec_sub19_internal_op[6:0] - attribute \src "issuer_ls180.v:20310.3-20322.6" - wire $1\SPR_dec31_dec_sub19_is_32b[0:0] - attribute \src "issuer_ls180.v:20297.3-20309.6" - wire width 2 $1\SPR_dec31_dec_sub19_rc_sel[1:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 3 \SPR_dec31_dec_sub19_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 4 \SPR_dec31_dec_sub19_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \SPR_dec31_dec_sub19_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \SPR_dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 6 \SPR_dec31_dec_sub19_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 5 \SPR_dec31_dec_sub19_rc_sel - attribute \src "issuer_ls180.v:20117.7-20117.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 7 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:20117.7-20117.20" - process $proc$issuer_ls180.v:20117$434 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \module_not_derived 1 + attribute \src "libresoc.v:16256.19-16282.4" + cell \dec31_dec_sub19 \dec31_dec_sub19 + connect \dec31_dec_sub19_asmcode \dec31_dec_sub19_dec31_dec_sub19_asmcode + connect \dec31_dec_sub19_br \dec31_dec_sub19_dec31_dec_sub19_br + connect \dec31_dec_sub19_cr_in \dec31_dec_sub19_dec31_dec_sub19_cr_in + connect \dec31_dec_sub19_cr_out \dec31_dec_sub19_dec31_dec_sub19_cr_out + connect \dec31_dec_sub19_cry_in \dec31_dec_sub19_dec31_dec_sub19_cry_in + connect \dec31_dec_sub19_cry_out \dec31_dec_sub19_dec31_dec_sub19_cry_out + connect \dec31_dec_sub19_form \dec31_dec_sub19_dec31_dec_sub19_form + connect \dec31_dec_sub19_function_unit \dec31_dec_sub19_dec31_dec_sub19_function_unit + connect \dec31_dec_sub19_in1_sel \dec31_dec_sub19_dec31_dec_sub19_in1_sel + connect \dec31_dec_sub19_in2_sel \dec31_dec_sub19_dec31_dec_sub19_in2_sel + connect \dec31_dec_sub19_in3_sel \dec31_dec_sub19_dec31_dec_sub19_in3_sel + connect \dec31_dec_sub19_internal_op \dec31_dec_sub19_dec31_dec_sub19_internal_op + connect \dec31_dec_sub19_inv_a \dec31_dec_sub19_dec31_dec_sub19_inv_a + connect \dec31_dec_sub19_inv_out \dec31_dec_sub19_dec31_dec_sub19_inv_out + connect \dec31_dec_sub19_is_32b \dec31_dec_sub19_dec31_dec_sub19_is_32b + connect \dec31_dec_sub19_ldst_len \dec31_dec_sub19_dec31_dec_sub19_ldst_len + connect \dec31_dec_sub19_lk \dec31_dec_sub19_dec31_dec_sub19_lk + connect \dec31_dec_sub19_out_sel \dec31_dec_sub19_dec31_dec_sub19_out_sel + connect \dec31_dec_sub19_rc_sel \dec31_dec_sub19_dec31_dec_sub19_rc_sel + connect \dec31_dec_sub19_rsrv \dec31_dec_sub19_dec31_dec_sub19_rsrv + connect \dec31_dec_sub19_sgl_pipe \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe + connect \dec31_dec_sub19_sgn \dec31_dec_sub19_dec31_dec_sub19_sgn + connect \dec31_dec_sub19_sgn_ext \dec31_dec_sub19_dec31_dec_sub19_sgn_ext + connect \dec31_dec_sub19_upd \dec31_dec_sub19_dec31_dec_sub19_upd + connect \opcode_in \dec31_dec_sub19_opcode_in end - attribute \src "issuer_ls180.v:20245.3-20257.6" - process $proc$issuer_ls180.v:20245$428 - assign { } { } - assign { } { } - assign $0\SPR_dec31_dec_sub19_function_unit[11:0] $1\SPR_dec31_dec_sub19_function_unit[11:0] - attribute \src "issuer_ls180.v:20246.5-20246.29" - switch \initial - attribute \src "issuer_ls180.v:20246.9-20246.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \module_not_derived 1 + attribute \src "libresoc.v:16283.19-16309.4" + cell \dec31_dec_sub20 \dec31_dec_sub20 + connect \dec31_dec_sub20_asmcode \dec31_dec_sub20_dec31_dec_sub20_asmcode + connect \dec31_dec_sub20_br \dec31_dec_sub20_dec31_dec_sub20_br + connect \dec31_dec_sub20_cr_in \dec31_dec_sub20_dec31_dec_sub20_cr_in + connect \dec31_dec_sub20_cr_out \dec31_dec_sub20_dec31_dec_sub20_cr_out + connect \dec31_dec_sub20_cry_in \dec31_dec_sub20_dec31_dec_sub20_cry_in + connect \dec31_dec_sub20_cry_out \dec31_dec_sub20_dec31_dec_sub20_cry_out + connect \dec31_dec_sub20_form \dec31_dec_sub20_dec31_dec_sub20_form + connect \dec31_dec_sub20_function_unit \dec31_dec_sub20_dec31_dec_sub20_function_unit + connect \dec31_dec_sub20_in1_sel \dec31_dec_sub20_dec31_dec_sub20_in1_sel + connect \dec31_dec_sub20_in2_sel \dec31_dec_sub20_dec31_dec_sub20_in2_sel + connect \dec31_dec_sub20_in3_sel \dec31_dec_sub20_dec31_dec_sub20_in3_sel + connect \dec31_dec_sub20_internal_op \dec31_dec_sub20_dec31_dec_sub20_internal_op + connect \dec31_dec_sub20_inv_a \dec31_dec_sub20_dec31_dec_sub20_inv_a + connect \dec31_dec_sub20_inv_out \dec31_dec_sub20_dec31_dec_sub20_inv_out + connect \dec31_dec_sub20_is_32b \dec31_dec_sub20_dec31_dec_sub20_is_32b + connect \dec31_dec_sub20_ldst_len \dec31_dec_sub20_dec31_dec_sub20_ldst_len + connect \dec31_dec_sub20_lk \dec31_dec_sub20_dec31_dec_sub20_lk + connect \dec31_dec_sub20_out_sel \dec31_dec_sub20_dec31_dec_sub20_out_sel + connect \dec31_dec_sub20_rc_sel \dec31_dec_sub20_dec31_dec_sub20_rc_sel + connect \dec31_dec_sub20_rsrv \dec31_dec_sub20_dec31_dec_sub20_rsrv + connect \dec31_dec_sub20_sgl_pipe \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe + connect \dec31_dec_sub20_sgn \dec31_dec_sub20_dec31_dec_sub20_sgn + connect \dec31_dec_sub20_sgn_ext \dec31_dec_sub20_dec31_dec_sub20_sgn_ext + connect \dec31_dec_sub20_upd \dec31_dec_sub20_dec31_dec_sub20_upd + connect \opcode_in \dec31_dec_sub20_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16310.19-16336.4" + cell \dec31_dec_sub21 \dec31_dec_sub21 + connect \dec31_dec_sub21_asmcode \dec31_dec_sub21_dec31_dec_sub21_asmcode + connect \dec31_dec_sub21_br \dec31_dec_sub21_dec31_dec_sub21_br + connect \dec31_dec_sub21_cr_in \dec31_dec_sub21_dec31_dec_sub21_cr_in + connect \dec31_dec_sub21_cr_out \dec31_dec_sub21_dec31_dec_sub21_cr_out + connect \dec31_dec_sub21_cry_in \dec31_dec_sub21_dec31_dec_sub21_cry_in + connect \dec31_dec_sub21_cry_out \dec31_dec_sub21_dec31_dec_sub21_cry_out + connect \dec31_dec_sub21_form \dec31_dec_sub21_dec31_dec_sub21_form + connect \dec31_dec_sub21_function_unit \dec31_dec_sub21_dec31_dec_sub21_function_unit + connect \dec31_dec_sub21_in1_sel \dec31_dec_sub21_dec31_dec_sub21_in1_sel + connect \dec31_dec_sub21_in2_sel \dec31_dec_sub21_dec31_dec_sub21_in2_sel + connect \dec31_dec_sub21_in3_sel \dec31_dec_sub21_dec31_dec_sub21_in3_sel + connect \dec31_dec_sub21_internal_op \dec31_dec_sub21_dec31_dec_sub21_internal_op + connect \dec31_dec_sub21_inv_a \dec31_dec_sub21_dec31_dec_sub21_inv_a + connect \dec31_dec_sub21_inv_out \dec31_dec_sub21_dec31_dec_sub21_inv_out + connect \dec31_dec_sub21_is_32b \dec31_dec_sub21_dec31_dec_sub21_is_32b + connect \dec31_dec_sub21_ldst_len \dec31_dec_sub21_dec31_dec_sub21_ldst_len + connect \dec31_dec_sub21_lk \dec31_dec_sub21_dec31_dec_sub21_lk + connect \dec31_dec_sub21_out_sel \dec31_dec_sub21_dec31_dec_sub21_out_sel + connect \dec31_dec_sub21_rc_sel \dec31_dec_sub21_dec31_dec_sub21_rc_sel + connect \dec31_dec_sub21_rsrv \dec31_dec_sub21_dec31_dec_sub21_rsrv + connect \dec31_dec_sub21_sgl_pipe \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe + connect \dec31_dec_sub21_sgn \dec31_dec_sub21_dec31_dec_sub21_sgn + connect \dec31_dec_sub21_sgn_ext \dec31_dec_sub21_dec31_dec_sub21_sgn_ext + connect \dec31_dec_sub21_upd \dec31_dec_sub21_dec31_dec_sub21_upd + connect \opcode_in \dec31_dec_sub21_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16337.19-16363.4" + cell \dec31_dec_sub22 \dec31_dec_sub22 + connect \dec31_dec_sub22_asmcode \dec31_dec_sub22_dec31_dec_sub22_asmcode + connect \dec31_dec_sub22_br \dec31_dec_sub22_dec31_dec_sub22_br + connect \dec31_dec_sub22_cr_in \dec31_dec_sub22_dec31_dec_sub22_cr_in + connect \dec31_dec_sub22_cr_out \dec31_dec_sub22_dec31_dec_sub22_cr_out + connect \dec31_dec_sub22_cry_in \dec31_dec_sub22_dec31_dec_sub22_cry_in + connect \dec31_dec_sub22_cry_out \dec31_dec_sub22_dec31_dec_sub22_cry_out + connect \dec31_dec_sub22_form \dec31_dec_sub22_dec31_dec_sub22_form + connect \dec31_dec_sub22_function_unit \dec31_dec_sub22_dec31_dec_sub22_function_unit + connect \dec31_dec_sub22_in1_sel \dec31_dec_sub22_dec31_dec_sub22_in1_sel + connect \dec31_dec_sub22_in2_sel \dec31_dec_sub22_dec31_dec_sub22_in2_sel + connect \dec31_dec_sub22_in3_sel \dec31_dec_sub22_dec31_dec_sub22_in3_sel + connect \dec31_dec_sub22_internal_op \dec31_dec_sub22_dec31_dec_sub22_internal_op + connect \dec31_dec_sub22_inv_a \dec31_dec_sub22_dec31_dec_sub22_inv_a + connect \dec31_dec_sub22_inv_out \dec31_dec_sub22_dec31_dec_sub22_inv_out + connect \dec31_dec_sub22_is_32b \dec31_dec_sub22_dec31_dec_sub22_is_32b + connect \dec31_dec_sub22_ldst_len \dec31_dec_sub22_dec31_dec_sub22_ldst_len + connect \dec31_dec_sub22_lk \dec31_dec_sub22_dec31_dec_sub22_lk + connect \dec31_dec_sub22_out_sel \dec31_dec_sub22_dec31_dec_sub22_out_sel + connect \dec31_dec_sub22_rc_sel \dec31_dec_sub22_dec31_dec_sub22_rc_sel + connect \dec31_dec_sub22_rsrv \dec31_dec_sub22_dec31_dec_sub22_rsrv + connect \dec31_dec_sub22_sgl_pipe \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe + connect \dec31_dec_sub22_sgn \dec31_dec_sub22_dec31_dec_sub22_sgn + connect \dec31_dec_sub22_sgn_ext \dec31_dec_sub22_dec31_dec_sub22_sgn_ext + connect \dec31_dec_sub22_upd \dec31_dec_sub22_dec31_dec_sub22_upd + connect \opcode_in \dec31_dec_sub22_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16364.19-16390.4" + cell \dec31_dec_sub23 \dec31_dec_sub23 + connect \dec31_dec_sub23_asmcode \dec31_dec_sub23_dec31_dec_sub23_asmcode + connect \dec31_dec_sub23_br \dec31_dec_sub23_dec31_dec_sub23_br + connect \dec31_dec_sub23_cr_in \dec31_dec_sub23_dec31_dec_sub23_cr_in + connect \dec31_dec_sub23_cr_out \dec31_dec_sub23_dec31_dec_sub23_cr_out + connect \dec31_dec_sub23_cry_in \dec31_dec_sub23_dec31_dec_sub23_cry_in + connect \dec31_dec_sub23_cry_out \dec31_dec_sub23_dec31_dec_sub23_cry_out + connect \dec31_dec_sub23_form \dec31_dec_sub23_dec31_dec_sub23_form + connect \dec31_dec_sub23_function_unit \dec31_dec_sub23_dec31_dec_sub23_function_unit + connect \dec31_dec_sub23_in1_sel \dec31_dec_sub23_dec31_dec_sub23_in1_sel + connect \dec31_dec_sub23_in2_sel \dec31_dec_sub23_dec31_dec_sub23_in2_sel + connect \dec31_dec_sub23_in3_sel \dec31_dec_sub23_dec31_dec_sub23_in3_sel + connect \dec31_dec_sub23_internal_op \dec31_dec_sub23_dec31_dec_sub23_internal_op + connect \dec31_dec_sub23_inv_a \dec31_dec_sub23_dec31_dec_sub23_inv_a + connect \dec31_dec_sub23_inv_out \dec31_dec_sub23_dec31_dec_sub23_inv_out + connect \dec31_dec_sub23_is_32b \dec31_dec_sub23_dec31_dec_sub23_is_32b + connect \dec31_dec_sub23_ldst_len \dec31_dec_sub23_dec31_dec_sub23_ldst_len + connect \dec31_dec_sub23_lk \dec31_dec_sub23_dec31_dec_sub23_lk + connect \dec31_dec_sub23_out_sel \dec31_dec_sub23_dec31_dec_sub23_out_sel + connect \dec31_dec_sub23_rc_sel \dec31_dec_sub23_dec31_dec_sub23_rc_sel + connect \dec31_dec_sub23_rsrv \dec31_dec_sub23_dec31_dec_sub23_rsrv + connect \dec31_dec_sub23_sgl_pipe \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe + connect \dec31_dec_sub23_sgn \dec31_dec_sub23_dec31_dec_sub23_sgn + connect \dec31_dec_sub23_sgn_ext \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + connect \dec31_dec_sub23_upd \dec31_dec_sub23_dec31_dec_sub23_upd + connect \opcode_in \dec31_dec_sub23_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16391.19-16417.4" + cell \dec31_dec_sub24 \dec31_dec_sub24 + connect \dec31_dec_sub24_asmcode \dec31_dec_sub24_dec31_dec_sub24_asmcode + connect \dec31_dec_sub24_br \dec31_dec_sub24_dec31_dec_sub24_br + connect \dec31_dec_sub24_cr_in \dec31_dec_sub24_dec31_dec_sub24_cr_in + connect \dec31_dec_sub24_cr_out \dec31_dec_sub24_dec31_dec_sub24_cr_out + connect \dec31_dec_sub24_cry_in \dec31_dec_sub24_dec31_dec_sub24_cry_in + connect \dec31_dec_sub24_cry_out \dec31_dec_sub24_dec31_dec_sub24_cry_out + connect \dec31_dec_sub24_form \dec31_dec_sub24_dec31_dec_sub24_form + connect \dec31_dec_sub24_function_unit \dec31_dec_sub24_dec31_dec_sub24_function_unit + connect \dec31_dec_sub24_in1_sel \dec31_dec_sub24_dec31_dec_sub24_in1_sel + connect \dec31_dec_sub24_in2_sel \dec31_dec_sub24_dec31_dec_sub24_in2_sel + connect \dec31_dec_sub24_in3_sel \dec31_dec_sub24_dec31_dec_sub24_in3_sel + connect \dec31_dec_sub24_internal_op \dec31_dec_sub24_dec31_dec_sub24_internal_op + connect \dec31_dec_sub24_inv_a \dec31_dec_sub24_dec31_dec_sub24_inv_a + connect \dec31_dec_sub24_inv_out \dec31_dec_sub24_dec31_dec_sub24_inv_out + connect \dec31_dec_sub24_is_32b \dec31_dec_sub24_dec31_dec_sub24_is_32b + connect \dec31_dec_sub24_ldst_len \dec31_dec_sub24_dec31_dec_sub24_ldst_len + connect \dec31_dec_sub24_lk \dec31_dec_sub24_dec31_dec_sub24_lk + connect \dec31_dec_sub24_out_sel \dec31_dec_sub24_dec31_dec_sub24_out_sel + connect \dec31_dec_sub24_rc_sel \dec31_dec_sub24_dec31_dec_sub24_rc_sel + connect \dec31_dec_sub24_rsrv \dec31_dec_sub24_dec31_dec_sub24_rsrv + connect \dec31_dec_sub24_sgl_pipe \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe + connect \dec31_dec_sub24_sgn \dec31_dec_sub24_dec31_dec_sub24_sgn + connect \dec31_dec_sub24_sgn_ext \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + connect \dec31_dec_sub24_upd \dec31_dec_sub24_dec31_dec_sub24_upd + connect \opcode_in \dec31_dec_sub24_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16418.19-16444.4" + cell \dec31_dec_sub26 \dec31_dec_sub26 + connect \dec31_dec_sub26_asmcode \dec31_dec_sub26_dec31_dec_sub26_asmcode + connect \dec31_dec_sub26_br \dec31_dec_sub26_dec31_dec_sub26_br + connect \dec31_dec_sub26_cr_in \dec31_dec_sub26_dec31_dec_sub26_cr_in + connect \dec31_dec_sub26_cr_out \dec31_dec_sub26_dec31_dec_sub26_cr_out + connect \dec31_dec_sub26_cry_in \dec31_dec_sub26_dec31_dec_sub26_cry_in + connect \dec31_dec_sub26_cry_out \dec31_dec_sub26_dec31_dec_sub26_cry_out + connect \dec31_dec_sub26_form \dec31_dec_sub26_dec31_dec_sub26_form + connect \dec31_dec_sub26_function_unit \dec31_dec_sub26_dec31_dec_sub26_function_unit + connect \dec31_dec_sub26_in1_sel \dec31_dec_sub26_dec31_dec_sub26_in1_sel + connect \dec31_dec_sub26_in2_sel \dec31_dec_sub26_dec31_dec_sub26_in2_sel + connect \dec31_dec_sub26_in3_sel \dec31_dec_sub26_dec31_dec_sub26_in3_sel + connect \dec31_dec_sub26_internal_op \dec31_dec_sub26_dec31_dec_sub26_internal_op + connect \dec31_dec_sub26_inv_a \dec31_dec_sub26_dec31_dec_sub26_inv_a + connect \dec31_dec_sub26_inv_out \dec31_dec_sub26_dec31_dec_sub26_inv_out + connect \dec31_dec_sub26_is_32b \dec31_dec_sub26_dec31_dec_sub26_is_32b + connect \dec31_dec_sub26_ldst_len \dec31_dec_sub26_dec31_dec_sub26_ldst_len + connect \dec31_dec_sub26_lk \dec31_dec_sub26_dec31_dec_sub26_lk + connect \dec31_dec_sub26_out_sel \dec31_dec_sub26_dec31_dec_sub26_out_sel + connect \dec31_dec_sub26_rc_sel \dec31_dec_sub26_dec31_dec_sub26_rc_sel + connect \dec31_dec_sub26_rsrv \dec31_dec_sub26_dec31_dec_sub26_rsrv + connect \dec31_dec_sub26_sgl_pipe \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe + connect \dec31_dec_sub26_sgn \dec31_dec_sub26_dec31_dec_sub26_sgn + connect \dec31_dec_sub26_sgn_ext \dec31_dec_sub26_dec31_dec_sub26_sgn_ext + connect \dec31_dec_sub26_upd \dec31_dec_sub26_dec31_dec_sub26_upd + connect \opcode_in \dec31_dec_sub26_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16445.19-16471.4" + cell \dec31_dec_sub27 \dec31_dec_sub27 + connect \dec31_dec_sub27_asmcode \dec31_dec_sub27_dec31_dec_sub27_asmcode + connect \dec31_dec_sub27_br \dec31_dec_sub27_dec31_dec_sub27_br + connect \dec31_dec_sub27_cr_in \dec31_dec_sub27_dec31_dec_sub27_cr_in + connect \dec31_dec_sub27_cr_out \dec31_dec_sub27_dec31_dec_sub27_cr_out + connect \dec31_dec_sub27_cry_in \dec31_dec_sub27_dec31_dec_sub27_cry_in + connect \dec31_dec_sub27_cry_out \dec31_dec_sub27_dec31_dec_sub27_cry_out + connect \dec31_dec_sub27_form \dec31_dec_sub27_dec31_dec_sub27_form + connect \dec31_dec_sub27_function_unit \dec31_dec_sub27_dec31_dec_sub27_function_unit + connect \dec31_dec_sub27_in1_sel \dec31_dec_sub27_dec31_dec_sub27_in1_sel + connect \dec31_dec_sub27_in2_sel \dec31_dec_sub27_dec31_dec_sub27_in2_sel + connect \dec31_dec_sub27_in3_sel \dec31_dec_sub27_dec31_dec_sub27_in3_sel + connect \dec31_dec_sub27_internal_op \dec31_dec_sub27_dec31_dec_sub27_internal_op + connect \dec31_dec_sub27_inv_a \dec31_dec_sub27_dec31_dec_sub27_inv_a + connect \dec31_dec_sub27_inv_out \dec31_dec_sub27_dec31_dec_sub27_inv_out + connect \dec31_dec_sub27_is_32b \dec31_dec_sub27_dec31_dec_sub27_is_32b + connect \dec31_dec_sub27_ldst_len \dec31_dec_sub27_dec31_dec_sub27_ldst_len + connect \dec31_dec_sub27_lk \dec31_dec_sub27_dec31_dec_sub27_lk + connect \dec31_dec_sub27_out_sel \dec31_dec_sub27_dec31_dec_sub27_out_sel + connect \dec31_dec_sub27_rc_sel \dec31_dec_sub27_dec31_dec_sub27_rc_sel + connect \dec31_dec_sub27_rsrv \dec31_dec_sub27_dec31_dec_sub27_rsrv + connect \dec31_dec_sub27_sgl_pipe \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe + connect \dec31_dec_sub27_sgn \dec31_dec_sub27_dec31_dec_sub27_sgn + connect \dec31_dec_sub27_sgn_ext \dec31_dec_sub27_dec31_dec_sub27_sgn_ext + connect \dec31_dec_sub27_upd \dec31_dec_sub27_dec31_dec_sub27_upd + connect \opcode_in \dec31_dec_sub27_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16472.19-16498.4" + cell \dec31_dec_sub28 \dec31_dec_sub28 + connect \dec31_dec_sub28_asmcode \dec31_dec_sub28_dec31_dec_sub28_asmcode + connect \dec31_dec_sub28_br \dec31_dec_sub28_dec31_dec_sub28_br + connect \dec31_dec_sub28_cr_in \dec31_dec_sub28_dec31_dec_sub28_cr_in + connect \dec31_dec_sub28_cr_out \dec31_dec_sub28_dec31_dec_sub28_cr_out + connect \dec31_dec_sub28_cry_in \dec31_dec_sub28_dec31_dec_sub28_cry_in + connect \dec31_dec_sub28_cry_out \dec31_dec_sub28_dec31_dec_sub28_cry_out + connect \dec31_dec_sub28_form \dec31_dec_sub28_dec31_dec_sub28_form + connect \dec31_dec_sub28_function_unit \dec31_dec_sub28_dec31_dec_sub28_function_unit + connect \dec31_dec_sub28_in1_sel \dec31_dec_sub28_dec31_dec_sub28_in1_sel + connect \dec31_dec_sub28_in2_sel \dec31_dec_sub28_dec31_dec_sub28_in2_sel + connect \dec31_dec_sub28_in3_sel \dec31_dec_sub28_dec31_dec_sub28_in3_sel + connect \dec31_dec_sub28_internal_op \dec31_dec_sub28_dec31_dec_sub28_internal_op + connect \dec31_dec_sub28_inv_a \dec31_dec_sub28_dec31_dec_sub28_inv_a + connect \dec31_dec_sub28_inv_out \dec31_dec_sub28_dec31_dec_sub28_inv_out + connect \dec31_dec_sub28_is_32b \dec31_dec_sub28_dec31_dec_sub28_is_32b + connect \dec31_dec_sub28_ldst_len \dec31_dec_sub28_dec31_dec_sub28_ldst_len + connect \dec31_dec_sub28_lk \dec31_dec_sub28_dec31_dec_sub28_lk + connect \dec31_dec_sub28_out_sel \dec31_dec_sub28_dec31_dec_sub28_out_sel + connect \dec31_dec_sub28_rc_sel \dec31_dec_sub28_dec31_dec_sub28_rc_sel + connect \dec31_dec_sub28_rsrv \dec31_dec_sub28_dec31_dec_sub28_rsrv + connect \dec31_dec_sub28_sgl_pipe \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe + connect \dec31_dec_sub28_sgn \dec31_dec_sub28_dec31_dec_sub28_sgn + connect \dec31_dec_sub28_sgn_ext \dec31_dec_sub28_dec31_dec_sub28_sgn_ext + connect \dec31_dec_sub28_upd \dec31_dec_sub28_dec31_dec_sub28_upd + connect \opcode_in \dec31_dec_sub28_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16499.18-16525.4" + cell \dec31_dec_sub4 \dec31_dec_sub4 + connect \dec31_dec_sub4_asmcode \dec31_dec_sub4_dec31_dec_sub4_asmcode + connect \dec31_dec_sub4_br \dec31_dec_sub4_dec31_dec_sub4_br + connect \dec31_dec_sub4_cr_in \dec31_dec_sub4_dec31_dec_sub4_cr_in + connect \dec31_dec_sub4_cr_out \dec31_dec_sub4_dec31_dec_sub4_cr_out + connect \dec31_dec_sub4_cry_in \dec31_dec_sub4_dec31_dec_sub4_cry_in + connect \dec31_dec_sub4_cry_out \dec31_dec_sub4_dec31_dec_sub4_cry_out + connect \dec31_dec_sub4_form \dec31_dec_sub4_dec31_dec_sub4_form + connect \dec31_dec_sub4_function_unit \dec31_dec_sub4_dec31_dec_sub4_function_unit + connect \dec31_dec_sub4_in1_sel \dec31_dec_sub4_dec31_dec_sub4_in1_sel + connect \dec31_dec_sub4_in2_sel \dec31_dec_sub4_dec31_dec_sub4_in2_sel + connect \dec31_dec_sub4_in3_sel \dec31_dec_sub4_dec31_dec_sub4_in3_sel + connect \dec31_dec_sub4_internal_op \dec31_dec_sub4_dec31_dec_sub4_internal_op + connect \dec31_dec_sub4_inv_a \dec31_dec_sub4_dec31_dec_sub4_inv_a + connect \dec31_dec_sub4_inv_out \dec31_dec_sub4_dec31_dec_sub4_inv_out + connect \dec31_dec_sub4_is_32b \dec31_dec_sub4_dec31_dec_sub4_is_32b + connect \dec31_dec_sub4_ldst_len \dec31_dec_sub4_dec31_dec_sub4_ldst_len + connect \dec31_dec_sub4_lk \dec31_dec_sub4_dec31_dec_sub4_lk + connect \dec31_dec_sub4_out_sel \dec31_dec_sub4_dec31_dec_sub4_out_sel + connect \dec31_dec_sub4_rc_sel \dec31_dec_sub4_dec31_dec_sub4_rc_sel + connect \dec31_dec_sub4_rsrv \dec31_dec_sub4_dec31_dec_sub4_rsrv + connect \dec31_dec_sub4_sgl_pipe \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe + connect \dec31_dec_sub4_sgn \dec31_dec_sub4_dec31_dec_sub4_sgn + connect \dec31_dec_sub4_sgn_ext \dec31_dec_sub4_dec31_dec_sub4_sgn_ext + connect \dec31_dec_sub4_upd \dec31_dec_sub4_dec31_dec_sub4_upd + connect \opcode_in \dec31_dec_sub4_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16526.18-16552.4" + cell \dec31_dec_sub8 \dec31_dec_sub8 + connect \dec31_dec_sub8_asmcode \dec31_dec_sub8_dec31_dec_sub8_asmcode + connect \dec31_dec_sub8_br \dec31_dec_sub8_dec31_dec_sub8_br + connect \dec31_dec_sub8_cr_in \dec31_dec_sub8_dec31_dec_sub8_cr_in + connect \dec31_dec_sub8_cr_out \dec31_dec_sub8_dec31_dec_sub8_cr_out + connect \dec31_dec_sub8_cry_in \dec31_dec_sub8_dec31_dec_sub8_cry_in + connect \dec31_dec_sub8_cry_out \dec31_dec_sub8_dec31_dec_sub8_cry_out + connect \dec31_dec_sub8_form \dec31_dec_sub8_dec31_dec_sub8_form + connect \dec31_dec_sub8_function_unit \dec31_dec_sub8_dec31_dec_sub8_function_unit + connect \dec31_dec_sub8_in1_sel \dec31_dec_sub8_dec31_dec_sub8_in1_sel + connect \dec31_dec_sub8_in2_sel \dec31_dec_sub8_dec31_dec_sub8_in2_sel + connect \dec31_dec_sub8_in3_sel \dec31_dec_sub8_dec31_dec_sub8_in3_sel + connect \dec31_dec_sub8_internal_op \dec31_dec_sub8_dec31_dec_sub8_internal_op + connect \dec31_dec_sub8_inv_a \dec31_dec_sub8_dec31_dec_sub8_inv_a + connect \dec31_dec_sub8_inv_out \dec31_dec_sub8_dec31_dec_sub8_inv_out + connect \dec31_dec_sub8_is_32b \dec31_dec_sub8_dec31_dec_sub8_is_32b + connect \dec31_dec_sub8_ldst_len \dec31_dec_sub8_dec31_dec_sub8_ldst_len + connect \dec31_dec_sub8_lk \dec31_dec_sub8_dec31_dec_sub8_lk + connect \dec31_dec_sub8_out_sel \dec31_dec_sub8_dec31_dec_sub8_out_sel + connect \dec31_dec_sub8_rc_sel \dec31_dec_sub8_dec31_dec_sub8_rc_sel + connect \dec31_dec_sub8_rsrv \dec31_dec_sub8_dec31_dec_sub8_rsrv + connect \dec31_dec_sub8_sgl_pipe \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe + connect \dec31_dec_sub8_sgn \dec31_dec_sub8_dec31_dec_sub8_sgn + connect \dec31_dec_sub8_sgn_ext \dec31_dec_sub8_dec31_dec_sub8_sgn_ext + connect \dec31_dec_sub8_upd \dec31_dec_sub8_dec31_dec_sub8_upd + connect \opcode_in \dec31_dec_sub8_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16553.18-16579.4" + cell \dec31_dec_sub9 \dec31_dec_sub9 + connect \dec31_dec_sub9_asmcode \dec31_dec_sub9_dec31_dec_sub9_asmcode + connect \dec31_dec_sub9_br \dec31_dec_sub9_dec31_dec_sub9_br + connect \dec31_dec_sub9_cr_in \dec31_dec_sub9_dec31_dec_sub9_cr_in + connect \dec31_dec_sub9_cr_out \dec31_dec_sub9_dec31_dec_sub9_cr_out + connect \dec31_dec_sub9_cry_in \dec31_dec_sub9_dec31_dec_sub9_cry_in + connect \dec31_dec_sub9_cry_out \dec31_dec_sub9_dec31_dec_sub9_cry_out + connect \dec31_dec_sub9_form \dec31_dec_sub9_dec31_dec_sub9_form + connect \dec31_dec_sub9_function_unit \dec31_dec_sub9_dec31_dec_sub9_function_unit + connect \dec31_dec_sub9_in1_sel \dec31_dec_sub9_dec31_dec_sub9_in1_sel + connect \dec31_dec_sub9_in2_sel \dec31_dec_sub9_dec31_dec_sub9_in2_sel + connect \dec31_dec_sub9_in3_sel \dec31_dec_sub9_dec31_dec_sub9_in3_sel + connect \dec31_dec_sub9_internal_op \dec31_dec_sub9_dec31_dec_sub9_internal_op + connect \dec31_dec_sub9_inv_a \dec31_dec_sub9_dec31_dec_sub9_inv_a + connect \dec31_dec_sub9_inv_out \dec31_dec_sub9_dec31_dec_sub9_inv_out + connect \dec31_dec_sub9_is_32b \dec31_dec_sub9_dec31_dec_sub9_is_32b + connect \dec31_dec_sub9_ldst_len \dec31_dec_sub9_dec31_dec_sub9_ldst_len + connect \dec31_dec_sub9_lk \dec31_dec_sub9_dec31_dec_sub9_lk + connect \dec31_dec_sub9_out_sel \dec31_dec_sub9_dec31_dec_sub9_out_sel + connect \dec31_dec_sub9_rc_sel \dec31_dec_sub9_dec31_dec_sub9_rc_sel + connect \dec31_dec_sub9_rsrv \dec31_dec_sub9_dec31_dec_sub9_rsrv + connect \dec31_dec_sub9_sgl_pipe \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + connect \dec31_dec_sub9_sgn \dec31_dec_sub9_dec31_dec_sub9_sgn + connect \dec31_dec_sub9_sgn_ext \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd + connect \opcode_in \dec31_dec_sub9_opcode_in + end + attribute \src "libresoc.v:11695.7-11695.20" + process $proc$libresoc.v:11695$366 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:16580.3-16640.6" + process $proc$libresoc.v:16580$342 + assign { } { } + assign { } { } + assign $0\dec31_function_unit[11:0] $1\dec31_function_unit[11:0] + attribute \src "libresoc.v:16581.5-16581.29" + switch \initial + attribute \src "libresoc.v:16581.9-16581.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\SPR_dec31_dec_sub19_function_unit[11:0] 12'010000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\dec31_function_unit[11:0] \dec31_dec_sub10_dec31_dec_sub10_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub28_dec31_dec_sub28_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub0_dec31_dec_sub0_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub26_dec31_dec_sub26_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub19_dec31_dec_sub19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub22_dec31_dec_sub22_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub9_dec31_dec_sub9_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub11_dec31_dec_sub11_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub27_dec31_dec_sub27_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub15_dec31_dec_sub15_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub20_dec31_dec_sub20_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub21_dec31_dec_sub21_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub23_dec31_dec_sub23_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub16_dec31_dec_sub16_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub18_dec31_dec_sub18_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub8_dec31_dec_sub8_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } - assign $1\SPR_dec31_dec_sub19_function_unit[11:0] 12'010000000000 + assign $1\dec31_function_unit[11:0] \dec31_dec_sub24_dec31_dec_sub24_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub4_dec31_dec_sub4_function_unit case - assign $1\SPR_dec31_dec_sub19_function_unit[11:0] 12'000000000000 + assign $1\dec31_function_unit[11:0] 12'000000000000 end sync always - update \SPR_dec31_dec_sub19_function_unit $0\SPR_dec31_dec_sub19_function_unit[11:0] + update \dec31_function_unit $0\dec31_function_unit[11:0] end - attribute \src "issuer_ls180.v:20258.3-20270.6" - process $proc$issuer_ls180.v:20258$429 + attribute \src "libresoc.v:16641.3-16701.6" + process $proc$libresoc.v:16641$343 assign { } { } assign { } { } - assign $0\SPR_dec31_dec_sub19_internal_op[6:0] $1\SPR_dec31_dec_sub19_internal_op[6:0] - attribute \src "issuer_ls180.v:20259.5-20259.29" + assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0] + attribute \src "libresoc.v:16642.5-16642.29" switch \initial - attribute \src "issuer_ls180.v:20259.9-20259.17" + attribute \src "libresoc.v:16642.9-16642.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\SPR_dec31_dec_sub19_internal_op[6:0] 7'0101110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\dec31_internal_op[6:0] \dec31_dec_sub10_dec31_dec_sub10_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign $1\SPR_dec31_dec_sub19_internal_op[6:0] 7'0110001 + assign $1\dec31_internal_op[6:0] \dec31_dec_sub28_dec31_dec_sub28_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub0_dec31_dec_sub0_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub26_dec31_dec_sub26_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub19_dec31_dec_sub19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub22_dec31_dec_sub22_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub9_dec31_dec_sub9_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub11_dec31_dec_sub11_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub27_dec31_dec_sub27_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub15_dec31_dec_sub15_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub20_dec31_dec_sub20_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub21_dec31_dec_sub21_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub23_dec31_dec_sub23_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub16_dec31_dec_sub16_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub18_dec31_dec_sub18_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub8_dec31_dec_sub8_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub24_dec31_dec_sub24_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub4_dec31_dec_sub4_internal_op case - assign $1\SPR_dec31_dec_sub19_internal_op[6:0] 7'0000000 + assign $1\dec31_internal_op[6:0] 7'0000000 end sync always - update \SPR_dec31_dec_sub19_internal_op $0\SPR_dec31_dec_sub19_internal_op[6:0] + update \dec31_internal_op $0\dec31_internal_op[6:0] end - attribute \src "issuer_ls180.v:20271.3-20283.6" - process $proc$issuer_ls180.v:20271$430 + attribute \src "libresoc.v:16702.3-16762.6" + process $proc$libresoc.v:16702$344 assign { } { } assign { } { } - assign $0\SPR_dec31_dec_sub19_cr_in[2:0] $1\SPR_dec31_dec_sub19_cr_in[2:0] - attribute \src "issuer_ls180.v:20272.5-20272.29" + assign $0\dec31_form[4:0] $1\dec31_form[4:0] + attribute \src "libresoc.v:16703.5-16703.29" switch \initial - attribute \src "issuer_ls180.v:20272.9-20272.17" + attribute \src "libresoc.v:16703.9-16703.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\SPR_dec31_dec_sub19_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\dec31_form[4:0] \dec31_dec_sub10_dec31_dec_sub10_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub28_dec31_dec_sub28_form + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub0_dec31_dec_sub0_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub26_dec31_dec_sub26_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub19_dec31_dec_sub19_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub22_dec31_dec_sub22_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub9_dec31_dec_sub9_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub11_dec31_dec_sub11_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub27_dec31_dec_sub27_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub15_dec31_dec_sub15_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub20_dec31_dec_sub20_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub21_dec31_dec_sub21_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub23_dec31_dec_sub23_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub16_dec31_dec_sub16_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 assign { } { } - assign $1\SPR_dec31_dec_sub19_cr_in[2:0] 3'000 + assign $1\dec31_form[4:0] \dec31_dec_sub18_dec31_dec_sub18_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub8_dec31_dec_sub8_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub24_dec31_dec_sub24_form + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub4_dec31_dec_sub4_form case - assign $1\SPR_dec31_dec_sub19_cr_in[2:0] 3'000 + assign $1\dec31_form[4:0] 5'00000 end sync always - update \SPR_dec31_dec_sub19_cr_in $0\SPR_dec31_dec_sub19_cr_in[2:0] + update \dec31_form $0\dec31_form[4:0] end - attribute \src "issuer_ls180.v:20284.3-20296.6" - process $proc$issuer_ls180.v:20284$431 + attribute \src "libresoc.v:16763.3-16823.6" + process $proc$libresoc.v:16763$345 assign { } { } assign { } { } - assign $0\SPR_dec31_dec_sub19_cr_out[2:0] $1\SPR_dec31_dec_sub19_cr_out[2:0] - attribute \src "issuer_ls180.v:20285.5-20285.29" + assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0] + attribute \src "libresoc.v:16764.5-16764.29" switch \initial - attribute \src "issuer_ls180.v:20285.9-20285.17" + attribute \src "libresoc.v:16764.9-16764.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\SPR_dec31_dec_sub19_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\dec31_asmcode[7:0] \dec31_dec_sub10_dec31_dec_sub10_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub28_dec31_dec_sub28_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub0_dec31_dec_sub0_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub26_dec31_dec_sub26_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub19_dec31_dec_sub19_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub22_dec31_dec_sub22_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub9_dec31_dec_sub9_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub11_dec31_dec_sub11_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub27_dec31_dec_sub27_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub15_dec31_dec_sub15_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub20_dec31_dec_sub20_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub21_dec31_dec_sub21_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub23_dec31_dec_sub23_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub16_dec31_dec_sub16_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub18_dec31_dec_sub18_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub8_dec31_dec_sub8_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub24_dec31_dec_sub24_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $1\SPR_dec31_dec_sub19_cr_out[2:0] 3'000 + assign $1\dec31_asmcode[7:0] \dec31_dec_sub4_dec31_dec_sub4_asmcode case - assign $1\SPR_dec31_dec_sub19_cr_out[2:0] 3'000 + assign $1\dec31_asmcode[7:0] 8'00000000 end sync always - update \SPR_dec31_dec_sub19_cr_out $0\SPR_dec31_dec_sub19_cr_out[2:0] + update \dec31_asmcode $0\dec31_asmcode[7:0] end - attribute \src "issuer_ls180.v:20297.3-20309.6" - process $proc$issuer_ls180.v:20297$432 + attribute \src "libresoc.v:16824.3-16884.6" + process $proc$libresoc.v:16824$346 assign { } { } assign { } { } - assign $0\SPR_dec31_dec_sub19_rc_sel[1:0] $1\SPR_dec31_dec_sub19_rc_sel[1:0] - attribute \src "issuer_ls180.v:20298.5-20298.29" + assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0] + attribute \src "libresoc.v:16825.5-16825.29" switch \initial - attribute \src "issuer_ls180.v:20298.9-20298.17" + attribute \src "libresoc.v:16825.9-16825.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\SPR_dec31_dec_sub19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub10_dec31_dec_sub10_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub28_dec31_dec_sub28_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub0_dec31_dec_sub0_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub26_dec31_dec_sub26_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub19_dec31_dec_sub19_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub22_dec31_dec_sub22_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub9_dec31_dec_sub9_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub11_dec31_dec_sub11_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 assign { } { } - assign $1\SPR_dec31_dec_sub19_rc_sel[1:0] 2'00 + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub27_dec31_dec_sub27_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub15_dec31_dec_sub15_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub20_dec31_dec_sub20_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub21_dec31_dec_sub21_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub23_dec31_dec_sub23_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub16_dec31_dec_sub16_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub18_dec31_dec_sub18_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub8_dec31_dec_sub8_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub24_dec31_dec_sub24_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub4_dec31_dec_sub4_in1_sel case - assign $1\SPR_dec31_dec_sub19_rc_sel[1:0] 2'00 + assign $1\dec31_in1_sel[2:0] 3'000 end sync always - update \SPR_dec31_dec_sub19_rc_sel $0\SPR_dec31_dec_sub19_rc_sel[1:0] + update \dec31_in1_sel $0\dec31_in1_sel[2:0] end - attribute \src "issuer_ls180.v:20310.3-20322.6" - process $proc$issuer_ls180.v:20310$433 + attribute \src "libresoc.v:16885.3-16945.6" + process $proc$libresoc.v:16885$347 assign { } { } assign { } { } - assign $0\SPR_dec31_dec_sub19_is_32b[0:0] $1\SPR_dec31_dec_sub19_is_32b[0:0] - attribute \src "issuer_ls180.v:20311.5-20311.29" + assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0] + attribute \src "libresoc.v:16886.5-16886.29" switch \initial - attribute \src "issuer_ls180.v:20311.9-20311.17" + attribute \src "libresoc.v:16886.9-16886.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } - assign $1\SPR_dec31_dec_sub19_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub10_dec31_dec_sub10_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub28_dec31_dec_sub28_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub0_dec31_dec_sub0_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub26_dec31_dec_sub26_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub19_dec31_dec_sub19_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub22_dec31_dec_sub22_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub9_dec31_dec_sub9_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub11_dec31_dec_sub11_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub27_dec31_dec_sub27_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub15_dec31_dec_sub15_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub20_dec31_dec_sub20_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub21_dec31_dec_sub21_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub23_dec31_dec_sub23_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub16_dec31_dec_sub16_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub18_dec31_dec_sub18_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub8_dec31_dec_sub8_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub24_dec31_dec_sub24_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $1\SPR_dec31_dec_sub19_is_32b[0:0] 1'0 + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub4_dec31_dec_sub4_in2_sel case - assign $1\SPR_dec31_dec_sub19_is_32b[0:0] 1'0 + assign $1\dec31_in2_sel[3:0] 4'0000 end sync always - update \SPR_dec31_dec_sub19_is_32b $0\SPR_dec31_dec_sub19_is_32b[0:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:20328.1-20386.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.adr_l" -attribute \generator "nMigen" -module \adr_l - attribute \src "issuer_ls180.v:20329.7-20329.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:20374.3-20382.6" - wire $0\q_int$next[0:0]$445 - attribute \src "issuer_ls180.v:20372.3-20373.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:20374.3-20382.6" - wire $1\q_int$next[0:0]$446 - attribute \src "issuer_ls180.v:20353.7-20353.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:20364.17-20364.96" - wire $and$issuer_ls180.v:20364$435_Y - attribute \src "issuer_ls180.v:20369.17-20369.96" - wire $and$issuer_ls180.v:20369$440_Y - attribute \src "issuer_ls180.v:20366.18-20366.93" - wire $not$issuer_ls180.v:20366$437_Y - attribute \src "issuer_ls180.v:20368.17-20368.92" - wire $not$issuer_ls180.v:20368$439_Y - attribute \src "issuer_ls180.v:20371.17-20371.92" - wire $not$issuer_ls180.v:20371$442_Y - attribute \src "issuer_ls180.v:20365.18-20365.98" - wire $or$issuer_ls180.v:20365$436_Y - attribute \src "issuer_ls180.v:20367.18-20367.99" - wire $or$issuer_ls180.v:20367$438_Y - attribute \src "issuer_ls180.v:20370.17-20370.97" - wire $or$issuer_ls180.v:20370$441_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:20329.7-20329.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:20364$435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:20364$435_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:20369$440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:20369$440_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:20366$437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_adr - connect \Y $not$issuer_ls180.v:20366$437_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:20368$439 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_adr - connect \Y $not$issuer_ls180.v:20368$439_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:20371$442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_adr - connect \Y $not$issuer_ls180.v:20371$442_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:20365$436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_adr - connect \Y $or$issuer_ls180.v:20365$436_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:20367$438 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_adr - connect \B \q_int - connect \Y $or$issuer_ls180.v:20367$438_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:20370$441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_adr - connect \Y $or$issuer_ls180.v:20370$441_Y - end - attribute \src "issuer_ls180.v:20329.7-20329.20" - process $proc$issuer_ls180.v:20329$447 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:20353.7-20353.19" - process $proc$issuer_ls180.v:20353$448 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:20372.3-20373.27" - process $proc$issuer_ls180.v:20372$443 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_in2_sel $0\dec31_in2_sel[3:0] end - attribute \src "issuer_ls180.v:20374.3-20382.6" - process $proc$issuer_ls180.v:20374$444 + attribute \src "libresoc.v:16946.3-17006.6" + process $proc$libresoc.v:16946$348 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$445 $1\q_int$next[0:0]$446 - attribute \src "issuer_ls180.v:20375.5-20375.29" + assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0] + attribute \src "libresoc.v:16947.5-16947.29" switch \initial - attribute \src "issuer_ls180.v:20375.9-20375.17" + attribute \src "libresoc.v:16947.9-16947.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 assign { } { } - assign $1\q_int$next[0:0]$446 1'0 + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_in3_sel case - assign $1\q_int$next[0:0]$446 \$5 + assign $1\dec31_in3_sel[1:0] 2'00 end sync always - update \q_int$next $0\q_int$next[0:0]$445 - end - connect \$9 $and$issuer_ls180.v:20364$435_Y - connect \$11 $or$issuer_ls180.v:20365$436_Y - connect \$13 $not$issuer_ls180.v:20366$437_Y - connect \$15 $or$issuer_ls180.v:20367$438_Y - connect \$1 $not$issuer_ls180.v:20368$439_Y - connect \$3 $and$issuer_ls180.v:20369$440_Y - connect \$5 $or$issuer_ls180.v:20370$441_Y - connect \$7 $not$issuer_ls180.v:20371$442_Y - connect \qlq_adr \$15 - connect \qn_adr \$13 - connect \q_adr \$11 -end -attribute \src "issuer_ls180.v:20390.1-20448.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.adrok_l" -attribute \generator "nMigen" -module \adrok_l - attribute \src "issuer_ls180.v:20391.7-20391.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:20436.3-20444.6" - wire $0\q_int$next[0:0]$459 - attribute \src "issuer_ls180.v:20434.3-20435.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:20436.3-20444.6" - wire $1\q_int$next[0:0]$460 - attribute \src "issuer_ls180.v:20415.7-20415.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:20426.17-20426.96" - wire $and$issuer_ls180.v:20426$449_Y - attribute \src "issuer_ls180.v:20431.17-20431.96" - wire $and$issuer_ls180.v:20431$454_Y - attribute \src "issuer_ls180.v:20428.18-20428.100" - wire $not$issuer_ls180.v:20428$451_Y - attribute \src "issuer_ls180.v:20430.17-20430.99" - wire $not$issuer_ls180.v:20430$453_Y - attribute \src "issuer_ls180.v:20433.17-20433.99" - wire $not$issuer_ls180.v:20433$456_Y - attribute \src "issuer_ls180.v:20427.18-20427.105" - wire $or$issuer_ls180.v:20427$450_Y - attribute \src "issuer_ls180.v:20429.18-20429.106" - wire $or$issuer_ls180.v:20429$452_Y - attribute \src "issuer_ls180.v:20432.17-20432.104" - wire $or$issuer_ls180.v:20432$455_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 6 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:20391.7-20391.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 5 \q_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire output 4 \qn_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:20426$449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:20426$449_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:20431$454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:20431$454_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:20428$451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_addr_acked - connect \Y $not$issuer_ls180.v:20428$451_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:20430$453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_addr_acked - connect \Y $not$issuer_ls180.v:20430$453_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:20433$456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_addr_acked - connect \Y $not$issuer_ls180.v:20433$456_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:20427$450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_addr_acked - connect \Y $or$issuer_ls180.v:20427$450_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:20429$452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_addr_acked - connect \B \q_int - connect \Y $or$issuer_ls180.v:20429$452_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:20432$455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_addr_acked - connect \Y $or$issuer_ls180.v:20432$455_Y + update \dec31_in3_sel $0\dec31_in3_sel[1:0] end - attribute \src "issuer_ls180.v:20391.7-20391.20" - process $proc$issuer_ls180.v:20391$461 + attribute \src "libresoc.v:17007.3-17067.6" + process $proc$libresoc.v:17007$349 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:20415.7-20415.19" - process $proc$issuer_ls180.v:20415$462 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $0\dec31_out_sel[1:0] $1\dec31_out_sel[1:0] + attribute \src "libresoc.v:17008.5-17008.29" + switch \initial + attribute \src "libresoc.v:17008.9-17008.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_out_sel + case + assign $1\dec31_out_sel[1:0] 2'00 + end sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:20434.3-20435.27" - process $proc$issuer_ls180.v:20434$457 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_out_sel $0\dec31_out_sel[1:0] end - attribute \src "issuer_ls180.v:20436.3-20444.6" - process $proc$issuer_ls180.v:20436$458 + attribute \src "libresoc.v:17068.3-17128.6" + process $proc$libresoc.v:17068$350 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$459 $1\q_int$next[0:0]$460 - attribute \src "issuer_ls180.v:20437.5-20437.29" + assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0] + attribute \src "libresoc.v:17069.5-17069.29" switch \initial - attribute \src "issuer_ls180.v:20437.9-20437.17" + attribute \src "libresoc.v:17069.9-17069.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 assign { } { } - assign $1\q_int$next[0:0]$460 1'0 + assign $1\dec31_cr_in[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_in case - assign $1\q_int$next[0:0]$460 \$5 + assign $1\dec31_cr_in[2:0] 3'000 end sync always - update \q_int$next $0\q_int$next[0:0]$459 + update \dec31_cr_in $0\dec31_cr_in[2:0] end - connect \$9 $and$issuer_ls180.v:20426$449_Y - connect \$11 $or$issuer_ls180.v:20427$450_Y - connect \$13 $not$issuer_ls180.v:20428$451_Y - connect \$15 $or$issuer_ls180.v:20429$452_Y - connect \$1 $not$issuer_ls180.v:20430$453_Y - connect \$3 $and$issuer_ls180.v:20431$454_Y - connect \$5 $or$issuer_ls180.v:20432$455_Y - connect \$7 $not$issuer_ls180.v:20433$456_Y - connect \qlq_addr_acked \$15 - connect \qn_addr_acked \$13 - connect \q_addr_acked \$11 -end -attribute \src "issuer_ls180.v:20452.1-21777.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0" -attribute \generator "nMigen" -module \alu0 - attribute \src "issuer_ls180.v:21288.3-21289.25" - wire $0\all_rd_dly[0:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire width 4 $0\alu_alu0_alu_op__data_len$next[3:0]$609 - attribute \src "issuer_ls180.v:21260.3-21261.67" - wire width 4 $0\alu_alu0_alu_op__data_len[3:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire width 12 $0\alu_alu0_alu_op__fn_unit$next[11:0]$610 - attribute \src "issuer_ls180.v:21230.3-21231.65" - wire width 12 $0\alu_alu0_alu_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire width 64 $0\alu_alu0_alu_op__imm_data__data$next[63:0]$611 - attribute \src "issuer_ls180.v:21232.3-21233.79" - wire width 64 $0\alu_alu0_alu_op__imm_data__data[63:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$612 - attribute \src "issuer_ls180.v:21234.3-21235.75" - wire $0\alu_alu0_alu_op__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire width 2 $0\alu_alu0_alu_op__input_carry$next[1:0]$613 - attribute \src "issuer_ls180.v:21252.3-21253.73" - wire width 2 $0\alu_alu0_alu_op__input_carry[1:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire width 32 $0\alu_alu0_alu_op__insn$next[31:0]$614 - attribute \src "issuer_ls180.v:21262.3-21263.59" - wire width 32 $0\alu_alu0_alu_op__insn[31:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire width 7 $0\alu_alu0_alu_op__insn_type$next[6:0]$615 - attribute \src "issuer_ls180.v:21228.3-21229.69" - wire width 7 $0\alu_alu0_alu_op__insn_type[6:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire $0\alu_alu0_alu_op__invert_in$next[0:0]$616 - attribute \src "issuer_ls180.v:21244.3-21245.69" - wire $0\alu_alu0_alu_op__invert_in[0:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire $0\alu_alu0_alu_op__invert_out$next[0:0]$617 - attribute \src "issuer_ls180.v:21248.3-21249.71" - wire $0\alu_alu0_alu_op__invert_out[0:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire $0\alu_alu0_alu_op__is_32bit$next[0:0]$618 - attribute \src "issuer_ls180.v:21256.3-21257.67" - wire $0\alu_alu0_alu_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire $0\alu_alu0_alu_op__is_signed$next[0:0]$619 - attribute \src "issuer_ls180.v:21258.3-21259.69" - wire $0\alu_alu0_alu_op__is_signed[0:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire $0\alu_alu0_alu_op__oe__oe$next[0:0]$620 - attribute \src "issuer_ls180.v:21240.3-21241.63" - wire $0\alu_alu0_alu_op__oe__oe[0:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire $0\alu_alu0_alu_op__oe__ok$next[0:0]$621 - attribute \src "issuer_ls180.v:21242.3-21243.63" - wire $0\alu_alu0_alu_op__oe__ok[0:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire $0\alu_alu0_alu_op__output_carry$next[0:0]$622 - attribute \src "issuer_ls180.v:21254.3-21255.75" - wire $0\alu_alu0_alu_op__output_carry[0:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire $0\alu_alu0_alu_op__rc__ok$next[0:0]$623 - attribute \src "issuer_ls180.v:21238.3-21239.63" - wire $0\alu_alu0_alu_op__rc__ok[0:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire $0\alu_alu0_alu_op__rc__rc$next[0:0]$624 - attribute \src "issuer_ls180.v:21236.3-21237.63" - wire $0\alu_alu0_alu_op__rc__rc[0:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire $0\alu_alu0_alu_op__write_cr0$next[0:0]$625 - attribute \src "issuer_ls180.v:21250.3-21251.69" - wire $0\alu_alu0_alu_op__write_cr0[0:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire $0\alu_alu0_alu_op__zero_a$next[0:0]$626 - attribute \src "issuer_ls180.v:21246.3-21247.63" - wire $0\alu_alu0_alu_op__zero_a[0:0] - attribute \src "issuer_ls180.v:21286.3-21287.40" - wire $0\alu_done_dly[0:0] - attribute \src "issuer_ls180.v:21676.3-21684.6" - wire $0\alu_l_r_alu$next[0:0]$707 - attribute \src "issuer_ls180.v:21196.3-21197.39" - wire $0\alu_l_r_alu[0:0] - attribute \src "issuer_ls180.v:21667.3-21675.6" - wire $0\alui_l_r_alui$next[0:0]$704 - attribute \src "issuer_ls180.v:21198.3-21199.43" - wire $0\alui_l_r_alui[0:0] - attribute \src "issuer_ls180.v:21517.3-21538.6" - wire width 64 $0\data_r0__o$next[63:0]$652 - attribute \src "issuer_ls180.v:21224.3-21225.37" - wire width 64 $0\data_r0__o[63:0] - attribute \src "issuer_ls180.v:21517.3-21538.6" - wire $0\data_r0__o_ok$next[0:0]$653 - attribute \src "issuer_ls180.v:21226.3-21227.43" - wire $0\data_r0__o_ok[0:0] - attribute \src "issuer_ls180.v:21539.3-21560.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$660 - attribute \src "issuer_ls180.v:21220.3-21221.43" - wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "issuer_ls180.v:21539.3-21560.6" - wire $0\data_r1__cr_a_ok$next[0:0]$661 - attribute \src "issuer_ls180.v:21222.3-21223.49" - wire $0\data_r1__cr_a_ok[0:0] - attribute \src "issuer_ls180.v:21561.3-21582.6" - wire width 2 $0\data_r2__xer_ca$next[1:0]$668 - attribute \src "issuer_ls180.v:21216.3-21217.47" - wire width 2 $0\data_r2__xer_ca[1:0] - attribute \src "issuer_ls180.v:21561.3-21582.6" - wire $0\data_r2__xer_ca_ok$next[0:0]$669 - attribute \src "issuer_ls180.v:21218.3-21219.53" - wire $0\data_r2__xer_ca_ok[0:0] - attribute \src "issuer_ls180.v:21583.3-21604.6" - wire width 2 $0\data_r3__xer_ov$next[1:0]$676 - attribute \src "issuer_ls180.v:21212.3-21213.47" - wire width 2 $0\data_r3__xer_ov[1:0] - attribute \src "issuer_ls180.v:21583.3-21604.6" - wire $0\data_r3__xer_ov_ok$next[0:0]$677 - attribute \src "issuer_ls180.v:21214.3-21215.53" - wire $0\data_r3__xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:21605.3-21626.6" - wire $0\data_r4__xer_so$next[0:0]$684 - attribute \src "issuer_ls180.v:21208.3-21209.47" - wire $0\data_r4__xer_so[0:0] - attribute \src "issuer_ls180.v:21605.3-21626.6" - wire $0\data_r4__xer_so_ok$next[0:0]$685 - attribute \src "issuer_ls180.v:21210.3-21211.53" - wire $0\data_r4__xer_so_ok[0:0] - attribute \src "issuer_ls180.v:21685.3-21694.6" - wire width 64 $0\dest1_o[63:0] - attribute \src "issuer_ls180.v:21695.3-21704.6" - wire width 4 $0\dest2_o[3:0] - attribute \src "issuer_ls180.v:21705.3-21714.6" - wire width 2 $0\dest3_o[1:0] - attribute \src "issuer_ls180.v:21715.3-21724.6" - wire width 2 $0\dest4_o[1:0] - attribute \src "issuer_ls180.v:21725.3-21734.6" - wire $0\dest5_o[0:0] - attribute \src "issuer_ls180.v:20453.7-20453.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:21433.3-21441.6" - wire $0\opc_l_r_opc$next[0:0]$594 - attribute \src "issuer_ls180.v:21272.3-21273.39" - wire $0\opc_l_r_opc[0:0] - attribute \src "issuer_ls180.v:21424.3-21432.6" - wire $0\opc_l_s_opc$next[0:0]$591 - attribute \src "issuer_ls180.v:21274.3-21275.39" - wire $0\opc_l_s_opc[0:0] - attribute \src "issuer_ls180.v:21735.3-21743.6" - wire width 5 $0\prev_wr_go$next[4:0]$715 - attribute \src "issuer_ls180.v:21284.3-21285.37" - wire width 5 $0\prev_wr_go[4:0] - attribute \src "issuer_ls180.v:21378.3-21387.6" - wire $0\req_done[0:0] - attribute \src "issuer_ls180.v:21469.3-21477.6" - wire width 5 $0\req_l_r_req$next[4:0]$606 - attribute \src "issuer_ls180.v:21264.3-21265.39" - wire width 5 $0\req_l_r_req[4:0] - attribute \src "issuer_ls180.v:21460.3-21468.6" - wire width 5 $0\req_l_s_req$next[4:0]$603 - attribute \src "issuer_ls180.v:21266.3-21267.39" - wire width 5 $0\req_l_s_req[4:0] - attribute \src "issuer_ls180.v:21397.3-21405.6" - wire $0\rok_l_r_rdok$next[0:0]$582 - attribute \src "issuer_ls180.v:21280.3-21281.41" - wire $0\rok_l_r_rdok[0:0] - attribute \src "issuer_ls180.v:21388.3-21396.6" - wire $0\rok_l_s_rdok$next[0:0]$579 - attribute \src "issuer_ls180.v:21282.3-21283.41" - wire $0\rok_l_s_rdok[0:0] - attribute \src "issuer_ls180.v:21415.3-21423.6" - wire $0\rst_l_r_rst$next[0:0]$588 - attribute \src "issuer_ls180.v:21276.3-21277.39" - wire $0\rst_l_r_rst[0:0] - attribute \src "issuer_ls180.v:21406.3-21414.6" - wire $0\rst_l_s_rst$next[0:0]$585 - attribute \src "issuer_ls180.v:21278.3-21279.39" - wire $0\rst_l_s_rst[0:0] - attribute \src "issuer_ls180.v:21451.3-21459.6" - wire width 4 $0\src_l_r_src$next[3:0]$600 - attribute \src "issuer_ls180.v:21268.3-21269.39" - wire width 4 $0\src_l_r_src[3:0] - attribute \src "issuer_ls180.v:21442.3-21450.6" - wire width 4 $0\src_l_s_src$next[3:0]$597 - attribute \src "issuer_ls180.v:21270.3-21271.39" - wire width 4 $0\src_l_s_src[3:0] - attribute \src "issuer_ls180.v:21627.3-21636.6" - wire width 64 $0\src_r0$next[63:0]$692 - attribute \src "issuer_ls180.v:21206.3-21207.29" - wire width 64 $0\src_r0[63:0] - attribute \src "issuer_ls180.v:21637.3-21646.6" - wire width 64 $0\src_r1$next[63:0]$695 - attribute \src "issuer_ls180.v:21204.3-21205.29" - wire width 64 $0\src_r1[63:0] - attribute \src "issuer_ls180.v:21647.3-21656.6" - wire $0\src_r2$next[0:0]$698 - attribute \src "issuer_ls180.v:21202.3-21203.29" - wire $0\src_r2[0:0] - attribute \src "issuer_ls180.v:21657.3-21666.6" - wire width 2 $0\src_r3$next[1:0]$701 - attribute \src "issuer_ls180.v:21200.3-21201.29" - wire width 2 $0\src_r3[1:0] - attribute \src "issuer_ls180.v:20591.7-20591.24" - wire $1\all_rd_dly[0:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire width 4 $1\alu_alu0_alu_op__data_len$next[3:0]$627 - attribute \src "issuer_ls180.v:20599.13-20599.45" - wire width 4 $1\alu_alu0_alu_op__data_len[3:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire width 12 $1\alu_alu0_alu_op__fn_unit$next[11:0]$628 - attribute \src "issuer_ls180.v:20616.14-20616.48" - wire width 12 $1\alu_alu0_alu_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire width 64 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$629 - attribute \src "issuer_ls180.v:20620.14-20620.68" - wire width 64 $1\alu_alu0_alu_op__imm_data__data[63:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$630 - attribute \src "issuer_ls180.v:20624.7-20624.43" - wire $1\alu_alu0_alu_op__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire width 2 $1\alu_alu0_alu_op__input_carry$next[1:0]$631 - attribute \src "issuer_ls180.v:20632.13-20632.48" - wire width 2 $1\alu_alu0_alu_op__input_carry[1:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire width 32 $1\alu_alu0_alu_op__insn$next[31:0]$632 - attribute \src "issuer_ls180.v:20636.14-20636.43" - wire width 32 $1\alu_alu0_alu_op__insn[31:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire width 7 $1\alu_alu0_alu_op__insn_type$next[6:0]$633 - attribute \src "issuer_ls180.v:20714.13-20714.47" - wire width 7 $1\alu_alu0_alu_op__insn_type[6:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire $1\alu_alu0_alu_op__invert_in$next[0:0]$634 - attribute \src "issuer_ls180.v:20718.7-20718.40" - wire $1\alu_alu0_alu_op__invert_in[0:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire $1\alu_alu0_alu_op__invert_out$next[0:0]$635 - attribute \src "issuer_ls180.v:20722.7-20722.41" - wire $1\alu_alu0_alu_op__invert_out[0:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire $1\alu_alu0_alu_op__is_32bit$next[0:0]$636 - attribute \src "issuer_ls180.v:20726.7-20726.39" - wire $1\alu_alu0_alu_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire $1\alu_alu0_alu_op__is_signed$next[0:0]$637 - attribute \src "issuer_ls180.v:20730.7-20730.40" - wire $1\alu_alu0_alu_op__is_signed[0:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire $1\alu_alu0_alu_op__oe__oe$next[0:0]$638 - attribute \src "issuer_ls180.v:20734.7-20734.37" - wire $1\alu_alu0_alu_op__oe__oe[0:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire $1\alu_alu0_alu_op__oe__ok$next[0:0]$639 - attribute \src "issuer_ls180.v:20738.7-20738.37" - wire $1\alu_alu0_alu_op__oe__ok[0:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire $1\alu_alu0_alu_op__output_carry$next[0:0]$640 - attribute \src "issuer_ls180.v:20742.7-20742.43" - wire $1\alu_alu0_alu_op__output_carry[0:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire $1\alu_alu0_alu_op__rc__ok$next[0:0]$641 - attribute \src "issuer_ls180.v:20746.7-20746.37" - wire $1\alu_alu0_alu_op__rc__ok[0:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire $1\alu_alu0_alu_op__rc__rc$next[0:0]$642 - attribute \src "issuer_ls180.v:20750.7-20750.37" - wire $1\alu_alu0_alu_op__rc__rc[0:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire $1\alu_alu0_alu_op__write_cr0$next[0:0]$643 - attribute \src "issuer_ls180.v:20754.7-20754.40" - wire $1\alu_alu0_alu_op__write_cr0[0:0] - attribute \src "issuer_ls180.v:21478.3-21516.6" - wire $1\alu_alu0_alu_op__zero_a$next[0:0]$644 - attribute \src "issuer_ls180.v:20758.7-20758.37" - wire $1\alu_alu0_alu_op__zero_a[0:0] - attribute \src "issuer_ls180.v:20790.7-20790.26" - wire $1\alu_done_dly[0:0] - attribute \src "issuer_ls180.v:21676.3-21684.6" - wire $1\alu_l_r_alu$next[0:0]$708 - attribute \src "issuer_ls180.v:20798.7-20798.25" - wire $1\alu_l_r_alu[0:0] - attribute \src "issuer_ls180.v:21667.3-21675.6" - wire $1\alui_l_r_alui$next[0:0]$705 - attribute \src "issuer_ls180.v:20810.7-20810.27" - wire $1\alui_l_r_alui[0:0] - attribute \src "issuer_ls180.v:21517.3-21538.6" - wire width 64 $1\data_r0__o$next[63:0]$654 - attribute \src "issuer_ls180.v:20844.14-20844.47" - wire width 64 $1\data_r0__o[63:0] - attribute \src "issuer_ls180.v:21517.3-21538.6" - wire $1\data_r0__o_ok$next[0:0]$655 - attribute \src "issuer_ls180.v:20848.7-20848.27" - wire $1\data_r0__o_ok[0:0] - attribute \src "issuer_ls180.v:21539.3-21560.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$662 - attribute \src "issuer_ls180.v:20852.13-20852.33" - wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "issuer_ls180.v:21539.3-21560.6" - wire $1\data_r1__cr_a_ok$next[0:0]$663 - attribute \src "issuer_ls180.v:20856.7-20856.30" - wire $1\data_r1__cr_a_ok[0:0] - attribute \src "issuer_ls180.v:21561.3-21582.6" - wire width 2 $1\data_r2__xer_ca$next[1:0]$670 - attribute \src "issuer_ls180.v:20860.13-20860.35" - wire width 2 $1\data_r2__xer_ca[1:0] - attribute \src "issuer_ls180.v:21561.3-21582.6" - wire $1\data_r2__xer_ca_ok$next[0:0]$671 - attribute \src "issuer_ls180.v:20864.7-20864.32" - wire $1\data_r2__xer_ca_ok[0:0] - attribute \src "issuer_ls180.v:21583.3-21604.6" - wire width 2 $1\data_r3__xer_ov$next[1:0]$678 - attribute \src "issuer_ls180.v:20868.13-20868.35" - wire width 2 $1\data_r3__xer_ov[1:0] - attribute \src "issuer_ls180.v:21583.3-21604.6" - wire $1\data_r3__xer_ov_ok$next[0:0]$679 - attribute \src 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parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \req_l_q_req - connect \B { \$115 \$117 \$119 \$121 \$123 } - connect \Y $and$issuer_ls180.v:21144$478_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$issuer_ls180.v:21145$479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$125 - connect \B \cu_wrmask_o - connect \Y $and$issuer_ls180.v:21145$479_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$issuer_ls180.v:21146$480 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:21146$480_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$issuer_ls180.v:21147$481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:21147$481_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$issuer_ls180.v:21148$482 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [2] - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:21148$482_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$issuer_ls180.v:21149$483 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [3] - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:21149$483_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$issuer_ls180.v:21150$484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [4] - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:21150$484_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:21152$486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd - connect \B \$13 - connect \Y $and$issuer_ls180.v:21152$486_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:21154$488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done - connect \B \$17 - connect \Y $and$issuer_ls180.v:21154$488_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$issuer_ls180.v:21155$489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$issuer_ls180.v:21155$489_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$issuer_ls180.v:21157$491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wr__rel_o - connect \B \$25 - connect \Y $and$issuer_ls180.v:21157$491_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$issuer_ls180.v:21160$494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \$23 - connect \Y $and$issuer_ls180.v:21160$494_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$issuer_ls180.v:21164$498 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \rok_l_q_rdok - connect \Y $and$issuer_ls180.v:21164$498_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$issuer_ls180.v:21166$500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_any - connect \B \$39 - connect \Y $and$issuer_ls180.v:21166$500_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$issuer_ls180.v:21167$501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \req_l_q_req - connect \B \cu_wrmask_o - connect \Y $and$issuer_ls180.v:21167$501_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$issuer_ls180.v:21169$503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$41 - connect \B \$45 - connect \Y $and$issuer_ls180.v:21169$503_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$issuer_ls180.v:21171$505 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$49 - connect \B \alu_alu0_n_ready_i - connect \Y $and$issuer_ls180.v:21171$505_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$issuer_ls180.v:21172$506 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$51 - connect \B \alu_alu0_n_valid_o - connect \Y $and$issuer_ls180.v:21172$506_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$issuer_ls180.v:21173$507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$53 - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:21173$507_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$issuer_ls180.v:21178$512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_alu0_n_valid_o - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:21178$512_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$issuer_ls180.v:21179$513 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $and$issuer_ls180.v:21179$513_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$issuer_ls180.v:21182$516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o_ok - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:21182$516_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$issuer_ls180.v:21183$517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cr_a_ok - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:21183$517_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$issuer_ls180.v:21184$518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_ca_ok - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:21184$518_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$issuer_ls180.v:21185$519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_ov_ok - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:21185$519_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$issuer_ls180.v:21186$520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_so_ok - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:21186$520_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$issuer_ls180.v:21168$502 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$43 - connect \B 1'0 - connect \Y $eq$issuer_ls180.v:21168$502_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$issuer_ls180.v:21170$504 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o - connect \B 1'0 - connect \Y $eq$issuer_ls180.v:21170$504_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$issuer_ls180.v:21133$467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_alu0_alu_op__zero_a - connect \Y $not$issuer_ls180.v:21133$467_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$issuer_ls180.v:21134$468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_alu0_alu_op__imm_data__ok - connect \Y $not$issuer_ls180.v:21134$468_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$issuer_ls180.v:21136$470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rdmaskn_i - connect \Y $not$issuer_ls180.v:21136$470_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:21151$485 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $not$issuer_ls180.v:21151$485_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:21153$487 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $not$issuer_ls180.v:21153$487_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$issuer_ls180.v:21156$490 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wrmask_o - connect \Y $not$issuer_ls180.v:21156$490_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$issuer_ls180.v:21159$493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:21159$493_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$issuer_ls180.v:21165$499 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_alu0_n_ready_i - connect \Y $not$issuer_ls180.v:21165$499_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$issuer_ls180.v:21180$514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rd__rel_o - connect \Y $not$issuer_ls180.v:21180$514_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$issuer_ls180.v:21163$497 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$33 - connect \B \$35 - connect \Y $or$issuer_ls180.v:21163$497_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$issuer_ls180.v:21174$508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $or$issuer_ls180.v:21174$508_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$issuer_ls180.v:21175$509 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $or$issuer_ls180.v:21175$509_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$issuer_ls180.v:21176$510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$issuer_ls180.v:21176$510_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$issuer_ls180.v:21177$511 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$issuer_ls180.v:21177$511_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$issuer_ls180.v:21181$515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $or$issuer_ls180.v:21181$515_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$issuer_ls180.v:21190$524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$6 - connect \B \cu_rd__go_i - connect \Y $or$issuer_ls180.v:21190$524_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$issuer_ls180.v:21129$463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $reduce_and$issuer_ls180.v:21129$463_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$issuer_ls180.v:21158$492 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \$27 - connect \Y $reduce_or$issuer_ls180.v:21158$492_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$issuer_ls180.v:21161$495 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $reduce_or$issuer_ls180.v:21161$495_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$issuer_ls180.v:21162$496 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $reduce_or$issuer_ls180.v:21162$496_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$issuer_ls180.v:21187$521 - parameter \WIDTH 1 - connect \A \src_l_q_src [0] - connect \B \opc_l_q_opc - connect \S \alu_alu0_alu_op__zero_a - connect \Y $ternary$issuer_ls180.v:21187$521_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$issuer_ls180.v:21188$522 - parameter \WIDTH 64 - connect \A \src1_i - connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \S \alu_alu0_alu_op__zero_a - connect \Y $ternary$issuer_ls180.v:21188$522_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$issuer_ls180.v:21189$523 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \alu_alu0_alu_op__imm_data__ok - connect \Y $ternary$issuer_ls180.v:21189$523_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$issuer_ls180.v:21191$525 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \alu_alu0_alu_op__imm_data__data - connect \S \alu_alu0_alu_op__imm_data__ok - connect \Y $ternary$issuer_ls180.v:21191$525_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:21192$526 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $ternary$issuer_ls180.v:21192$526_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:21193$527 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm$88 - connect \S \src_sel$85 - connect \Y $ternary$issuer_ls180.v:21193$527_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:21194$528 - parameter \WIDTH 1 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $ternary$issuer_ls180.v:21194$528_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:21195$529 - parameter \WIDTH 2 - connect \A \src_r3 - connect \B \src4_i - connect \S \src_l_q_src [3] - connect \Y $ternary$issuer_ls180.v:21195$529_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:21290.12-21329.4" - cell \alu_alu0 \alu_alu0 - connect \alu_op__data_len \alu_alu0_alu_op__data_len - connect \alu_op__fn_unit \alu_alu0_alu_op__fn_unit - connect \alu_op__imm_data__data \alu_alu0_alu_op__imm_data__data - connect \alu_op__imm_data__ok \alu_alu0_alu_op__imm_data__ok - connect \alu_op__input_carry \alu_alu0_alu_op__input_carry - connect \alu_op__insn \alu_alu0_alu_op__insn - connect \alu_op__insn_type \alu_alu0_alu_op__insn_type - connect \alu_op__invert_in \alu_alu0_alu_op__invert_in - connect \alu_op__invert_out \alu_alu0_alu_op__invert_out - connect \alu_op__is_32bit \alu_alu0_alu_op__is_32bit - connect \alu_op__is_signed \alu_alu0_alu_op__is_signed - connect \alu_op__oe__oe \alu_alu0_alu_op__oe__oe - connect \alu_op__oe__ok \alu_alu0_alu_op__oe__ok - connect \alu_op__output_carry \alu_alu0_alu_op__output_carry - connect \alu_op__rc__ok \alu_alu0_alu_op__rc__ok - connect \alu_op__rc__rc \alu_alu0_alu_op__rc__rc - connect \alu_op__write_cr0 \alu_alu0_alu_op__write_cr0 - connect \alu_op__zero_a \alu_alu0_alu_op__zero_a - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \alu_alu0_cr_a - connect \cr_a_ok \cr_a_ok - connect \n_ready_i \alu_alu0_n_ready_i - connect \n_valid_o \alu_alu0_n_valid_o - connect \o \alu_alu0_o - connect \o_ok \o_ok - connect \p_ready_o \alu_alu0_p_ready_o - connect \p_valid_i \alu_alu0_p_valid_i - connect \ra \alu_alu0_ra - connect \rb \alu_alu0_rb - connect \xer_ca \alu_alu0_xer_ca - connect \xer_ca$2 \alu_alu0_xer_ca$2 - connect \xer_ca_ok \xer_ca_ok - connect \xer_ov \alu_alu0_xer_ov - connect \xer_ov_ok \xer_ov_ok - connect \xer_so \alu_alu0_xer_so - connect \xer_so$1 \alu_alu0_xer_so$1 - connect \xer_so_ok \xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:21330.9-21336.4" - cell \alu_l \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:21337.10-21343.4" - cell \alui_l \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:21344.9-21350.4" - cell \opc_l \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_opc \opc_l_q_opc - connect \r_opc \opc_l_r_opc - connect \s_opc \opc_l_s_opc - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:21351.9-21357.4" - cell \req_l \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \r_req \req_l_r_req - connect \s_req \req_l_s_req - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:21358.9-21364.4" - cell \rok_l \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \r_rdok \rok_l_r_rdok - connect \s_rdok \rok_l_s_rdok - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:21365.9-21370.4" - cell \rst_l \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_rst \rst_l_r_rst - connect \s_rst \rst_l_s_rst - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:21371.9-21377.4" - cell \src_l \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_src \src_l_q_src - connect \r_src \src_l_r_src - connect \s_src \src_l_s_src - end - attribute \src "issuer_ls180.v:20453.7-20453.20" - process $proc$issuer_ls180.v:20453$717 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:20591.7-20591.24" - process $proc$issuer_ls180.v:20591$718 - assign { } { } - assign $1\all_rd_dly[0:0] 1'0 - sync always - sync init - update \all_rd_dly $1\all_rd_dly[0:0] - end - attribute \src "issuer_ls180.v:20599.13-20599.45" - process $proc$issuer_ls180.v:20599$719 - assign { } { } - assign $1\alu_alu0_alu_op__data_len[3:0] 4'0000 - sync always - sync init - update \alu_alu0_alu_op__data_len $1\alu_alu0_alu_op__data_len[3:0] - end - attribute \src "issuer_ls180.v:20616.14-20616.48" - process $proc$issuer_ls180.v:20616$720 - assign { } { } - assign $1\alu_alu0_alu_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \alu_alu0_alu_op__fn_unit $1\alu_alu0_alu_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:20620.14-20620.68" - process $proc$issuer_ls180.v:20620$721 - assign { } { } - assign $1\alu_alu0_alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_alu0_alu_op__imm_data__data $1\alu_alu0_alu_op__imm_data__data[63:0] - end - attribute \src "issuer_ls180.v:20624.7-20624.43" - process $proc$issuer_ls180.v:20624$722 - assign { } { } - assign $1\alu_alu0_alu_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \alu_alu0_alu_op__imm_data__ok $1\alu_alu0_alu_op__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:20632.13-20632.48" - process $proc$issuer_ls180.v:20632$723 - assign { } { } - assign $1\alu_alu0_alu_op__input_carry[1:0] 2'00 - sync always - sync init - update \alu_alu0_alu_op__input_carry $1\alu_alu0_alu_op__input_carry[1:0] - end - attribute \src "issuer_ls180.v:20636.14-20636.43" - process $proc$issuer_ls180.v:20636$724 - assign { } { } - assign $1\alu_alu0_alu_op__insn[31:0] 0 - sync always - sync init - update \alu_alu0_alu_op__insn $1\alu_alu0_alu_op__insn[31:0] - end - attribute \src "issuer_ls180.v:20714.13-20714.47" - process $proc$issuer_ls180.v:20714$725 - assign { } { } - assign $1\alu_alu0_alu_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \alu_alu0_alu_op__insn_type $1\alu_alu0_alu_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:20718.7-20718.40" - process $proc$issuer_ls180.v:20718$726 - assign { } { } - assign $1\alu_alu0_alu_op__invert_in[0:0] 1'0 - sync always - sync init - update \alu_alu0_alu_op__invert_in $1\alu_alu0_alu_op__invert_in[0:0] - end - attribute \src "issuer_ls180.v:20722.7-20722.41" - process $proc$issuer_ls180.v:20722$727 - assign { } { } - assign $1\alu_alu0_alu_op__invert_out[0:0] 1'0 - sync always - sync init - update \alu_alu0_alu_op__invert_out $1\alu_alu0_alu_op__invert_out[0:0] - end - attribute \src "issuer_ls180.v:20726.7-20726.39" - process $proc$issuer_ls180.v:20726$728 - assign { } { } - assign $1\alu_alu0_alu_op__is_32bit[0:0] 1'0 - sync always - sync init - update \alu_alu0_alu_op__is_32bit $1\alu_alu0_alu_op__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:20730.7-20730.40" - process $proc$issuer_ls180.v:20730$729 - assign { } { } - assign $1\alu_alu0_alu_op__is_signed[0:0] 1'0 - sync always - sync init - update \alu_alu0_alu_op__is_signed $1\alu_alu0_alu_op__is_signed[0:0] - end - attribute \src "issuer_ls180.v:20734.7-20734.37" - process $proc$issuer_ls180.v:20734$730 - assign { } { } - assign $1\alu_alu0_alu_op__oe__oe[0:0] 1'0 - sync always - sync init - update \alu_alu0_alu_op__oe__oe $1\alu_alu0_alu_op__oe__oe[0:0] - end - attribute \src "issuer_ls180.v:20738.7-20738.37" - process $proc$issuer_ls180.v:20738$731 - assign { } { } - assign $1\alu_alu0_alu_op__oe__ok[0:0] 1'0 - sync always - sync init - update \alu_alu0_alu_op__oe__ok $1\alu_alu0_alu_op__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:20742.7-20742.43" - process $proc$issuer_ls180.v:20742$732 - assign { } { } - assign $1\alu_alu0_alu_op__output_carry[0:0] 1'0 - sync always - sync init - update \alu_alu0_alu_op__output_carry $1\alu_alu0_alu_op__output_carry[0:0] - end - attribute \src "issuer_ls180.v:20746.7-20746.37" - process $proc$issuer_ls180.v:20746$733 - assign { } { } - assign $1\alu_alu0_alu_op__rc__ok[0:0] 1'0 - sync always - sync init - update \alu_alu0_alu_op__rc__ok $1\alu_alu0_alu_op__rc__ok[0:0] - end - attribute \src "issuer_ls180.v:20750.7-20750.37" - process $proc$issuer_ls180.v:20750$734 - assign { } { } - assign $1\alu_alu0_alu_op__rc__rc[0:0] 1'0 - sync always - sync init - update \alu_alu0_alu_op__rc__rc $1\alu_alu0_alu_op__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:20754.7-20754.40" - process $proc$issuer_ls180.v:20754$735 - assign { } { } - assign $1\alu_alu0_alu_op__write_cr0[0:0] 1'0 - sync always - sync init - update \alu_alu0_alu_op__write_cr0 $1\alu_alu0_alu_op__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:20758.7-20758.37" - process $proc$issuer_ls180.v:20758$736 - assign { } { } - assign $1\alu_alu0_alu_op__zero_a[0:0] 1'0 - sync always - sync init - update \alu_alu0_alu_op__zero_a $1\alu_alu0_alu_op__zero_a[0:0] - end - attribute \src "issuer_ls180.v:20790.7-20790.26" - process $proc$issuer_ls180.v:20790$737 - assign { } { } - assign $1\alu_done_dly[0:0] 1'0 - sync always - sync init - update \alu_done_dly $1\alu_done_dly[0:0] - end - attribute \src "issuer_ls180.v:20798.7-20798.25" - process $proc$issuer_ls180.v:20798$738 - assign { } { } - assign $1\alu_l_r_alu[0:0] 1'1 - sync always - sync init - update \alu_l_r_alu $1\alu_l_r_alu[0:0] - end - attribute \src "issuer_ls180.v:20810.7-20810.27" - process $proc$issuer_ls180.v:20810$739 - assign { } { } - assign $1\alui_l_r_alui[0:0] 1'1 - sync always - sync init - update \alui_l_r_alui $1\alui_l_r_alui[0:0] - end - attribute \src "issuer_ls180.v:20844.14-20844.47" - process $proc$issuer_ls180.v:20844$740 - assign { } { } - assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r0__o $1\data_r0__o[63:0] - end - attribute \src "issuer_ls180.v:20848.7-20848.27" - process $proc$issuer_ls180.v:20848$741 - assign { } { } - assign $1\data_r0__o_ok[0:0] 1'0 - sync always - sync init - update \data_r0__o_ok $1\data_r0__o_ok[0:0] - end - attribute \src "issuer_ls180.v:20852.13-20852.33" - process $proc$issuer_ls180.v:20852$742 - assign { } { } - assign $1\data_r1__cr_a[3:0] 4'0000 - sync always - sync init - update \data_r1__cr_a $1\data_r1__cr_a[3:0] - end - attribute \src "issuer_ls180.v:20856.7-20856.30" - process $proc$issuer_ls180.v:20856$743 - assign { } { } - assign $1\data_r1__cr_a_ok[0:0] 1'0 - sync always - sync init - update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:20860.13-20860.35" - process $proc$issuer_ls180.v:20860$744 - assign { } { } - assign $1\data_r2__xer_ca[1:0] 2'00 - sync always - sync init - update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] - end - attribute \src "issuer_ls180.v:20864.7-20864.32" - process $proc$issuer_ls180.v:20864$745 - assign { } { } - assign $1\data_r2__xer_ca_ok[0:0] 1'0 - sync always - sync init - update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] - end - attribute \src "issuer_ls180.v:20868.13-20868.35" - process $proc$issuer_ls180.v:20868$746 - assign { } { } - assign $1\data_r3__xer_ov[1:0] 2'00 - sync always - sync init - update \data_r3__xer_ov $1\data_r3__xer_ov[1:0] - end - attribute \src "issuer_ls180.v:20872.7-20872.32" - process $proc$issuer_ls180.v:20872$747 - assign { } { } - assign $1\data_r3__xer_ov_ok[0:0] 1'0 - sync always - sync init - update \data_r3__xer_ov_ok $1\data_r3__xer_ov_ok[0:0] - end - attribute \src "issuer_ls180.v:20876.7-20876.29" - process $proc$issuer_ls180.v:20876$748 - assign { } { } - assign $1\data_r4__xer_so[0:0] 1'0 - sync always - sync init - update \data_r4__xer_so $1\data_r4__xer_so[0:0] - end - attribute \src "issuer_ls180.v:20880.7-20880.32" - process $proc$issuer_ls180.v:20880$749 - assign { } { } - assign $1\data_r4__xer_so_ok[0:0] 1'0 - sync always - sync init - update \data_r4__xer_so_ok $1\data_r4__xer_so_ok[0:0] - end - attribute \src "issuer_ls180.v:20903.7-20903.25" - process $proc$issuer_ls180.v:20903$750 - assign { } { } - assign $1\opc_l_r_opc[0:0] 1'1 - sync always - sync init - update \opc_l_r_opc $1\opc_l_r_opc[0:0] - end - attribute \src "issuer_ls180.v:20907.7-20907.25" - process $proc$issuer_ls180.v:20907$751 - assign { } { } - assign $1\opc_l_s_opc[0:0] 1'0 - sync always - sync init - update \opc_l_s_opc $1\opc_l_s_opc[0:0] - end - attribute \src "issuer_ls180.v:21038.13-21038.31" - process $proc$issuer_ls180.v:21038$752 - assign { } { } - assign $1\prev_wr_go[4:0] 5'00000 - sync always - sync init - update \prev_wr_go $1\prev_wr_go[4:0] - end - attribute \src "issuer_ls180.v:21046.13-21046.32" - process $proc$issuer_ls180.v:21046$753 - assign { } { } - assign $1\req_l_r_req[4:0] 5'11111 - sync always - sync init - update \req_l_r_req $1\req_l_r_req[4:0] - end - attribute \src "issuer_ls180.v:21050.13-21050.32" - process $proc$issuer_ls180.v:21050$754 - assign { } { } - assign $1\req_l_s_req[4:0] 5'00000 - sync always - sync init - update \req_l_s_req $1\req_l_s_req[4:0] - end - attribute \src "issuer_ls180.v:21062.7-21062.26" - process $proc$issuer_ls180.v:21062$755 - assign { } { } - assign $1\rok_l_r_rdok[0:0] 1'1 - sync always - sync init - update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] - end - attribute \src "issuer_ls180.v:21066.7-21066.26" - process $proc$issuer_ls180.v:21066$756 - assign { } { } - assign $1\rok_l_s_rdok[0:0] 1'0 - sync always - sync init - update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] - end - attribute \src "issuer_ls180.v:21070.7-21070.25" - process $proc$issuer_ls180.v:21070$757 - assign { } { } - assign $1\rst_l_r_rst[0:0] 1'1 - sync always - sync init - update \rst_l_r_rst $1\rst_l_r_rst[0:0] - end - attribute \src "issuer_ls180.v:21074.7-21074.25" - process $proc$issuer_ls180.v:21074$758 - assign { } { } - assign $1\rst_l_s_rst[0:0] 1'0 - sync always - sync init - update \rst_l_s_rst $1\rst_l_s_rst[0:0] - end - attribute \src "issuer_ls180.v:21090.13-21090.31" - process $proc$issuer_ls180.v:21090$759 - assign { } { } - assign $1\src_l_r_src[3:0] 4'1111 - sync always - sync init - update \src_l_r_src $1\src_l_r_src[3:0] - end - attribute \src "issuer_ls180.v:21094.13-21094.31" - process $proc$issuer_ls180.v:21094$760 - assign { } { } - assign $1\src_l_s_src[3:0] 4'0000 - sync always - sync init - update \src_l_s_src $1\src_l_s_src[3:0] - end - attribute \src "issuer_ls180.v:21102.14-21102.43" - process $proc$issuer_ls180.v:21102$761 - assign { } { } - assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r0 $1\src_r0[63:0] - end - attribute \src "issuer_ls180.v:21106.14-21106.43" - process $proc$issuer_ls180.v:21106$762 - assign { } { } - assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r1 $1\src_r1[63:0] - end - attribute \src "issuer_ls180.v:21110.7-21110.20" - process $proc$issuer_ls180.v:21110$763 - assign { } { } - assign $1\src_r2[0:0] 1'0 - sync always - sync init - update \src_r2 $1\src_r2[0:0] - end - attribute \src "issuer_ls180.v:21114.13-21114.26" - process $proc$issuer_ls180.v:21114$764 - assign { } { } - assign $1\src_r3[1:0] 2'00 - sync always - sync init - update \src_r3 $1\src_r3[1:0] - end - attribute \src "issuer_ls180.v:21196.3-21197.39" - process $proc$issuer_ls180.v:21196$530 - assign { } { } - assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next - sync posedge \coresync_clk - update \alu_l_r_alu $0\alu_l_r_alu[0:0] - end - attribute \src "issuer_ls180.v:21198.3-21199.43" - process $proc$issuer_ls180.v:21198$531 - assign { } { } - assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next - sync posedge \coresync_clk - update \alui_l_r_alui $0\alui_l_r_alui[0:0] - end - attribute \src "issuer_ls180.v:21200.3-21201.29" - process $proc$issuer_ls180.v:21200$532 - assign { } { } - assign $0\src_r3[1:0] \src_r3$next - sync posedge \coresync_clk - update \src_r3 $0\src_r3[1:0] - end - attribute \src "issuer_ls180.v:21202.3-21203.29" - process $proc$issuer_ls180.v:21202$533 - assign { } { } - assign $0\src_r2[0:0] \src_r2$next - sync posedge \coresync_clk - update \src_r2 $0\src_r2[0:0] - end - attribute \src "issuer_ls180.v:21204.3-21205.29" - process $proc$issuer_ls180.v:21204$534 - assign { } { } - assign $0\src_r1[63:0] \src_r1$next - sync posedge \coresync_clk - update \src_r1 $0\src_r1[63:0] - end - attribute \src "issuer_ls180.v:21206.3-21207.29" - process $proc$issuer_ls180.v:21206$535 - assign { } { } - assign $0\src_r0[63:0] \src_r0$next - sync posedge \coresync_clk - update \src_r0 $0\src_r0[63:0] - end - attribute \src "issuer_ls180.v:21208.3-21209.47" - process $proc$issuer_ls180.v:21208$536 - assign { } { } - assign $0\data_r4__xer_so[0:0] \data_r4__xer_so$next - sync posedge \coresync_clk - update \data_r4__xer_so $0\data_r4__xer_so[0:0] - end - attribute \src "issuer_ls180.v:21210.3-21211.53" - process $proc$issuer_ls180.v:21210$537 - assign { } { } - assign $0\data_r4__xer_so_ok[0:0] \data_r4__xer_so_ok$next - sync posedge \coresync_clk - update \data_r4__xer_so_ok $0\data_r4__xer_so_ok[0:0] - end - attribute \src "issuer_ls180.v:21212.3-21213.47" - process $proc$issuer_ls180.v:21212$538 - assign { } { } - assign $0\data_r3__xer_ov[1:0] \data_r3__xer_ov$next - sync posedge \coresync_clk - update \data_r3__xer_ov $0\data_r3__xer_ov[1:0] - end - attribute \src "issuer_ls180.v:21214.3-21215.53" - process $proc$issuer_ls180.v:21214$539 - assign { } { } - assign $0\data_r3__xer_ov_ok[0:0] \data_r3__xer_ov_ok$next - sync posedge \coresync_clk - update \data_r3__xer_ov_ok $0\data_r3__xer_ov_ok[0:0] - end - attribute \src "issuer_ls180.v:21216.3-21217.47" - process $proc$issuer_ls180.v:21216$540 - assign { } { } - assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next - sync posedge \coresync_clk - update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] - end - attribute \src "issuer_ls180.v:21218.3-21219.53" - process $proc$issuer_ls180.v:21218$541 - assign { } { } - assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next - sync posedge \coresync_clk - update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] - end - attribute \src "issuer_ls180.v:21220.3-21221.43" - process $proc$issuer_ls180.v:21220$542 - assign { } { } - assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next - sync posedge \coresync_clk - update \data_r1__cr_a $0\data_r1__cr_a[3:0] - end - attribute \src "issuer_ls180.v:21222.3-21223.49" - process $proc$issuer_ls180.v:21222$543 - assign { } { } - assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next - sync posedge \coresync_clk - update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:21224.3-21225.37" - process $proc$issuer_ls180.v:21224$544 - assign { } { } - assign $0\data_r0__o[63:0] \data_r0__o$next - sync posedge \coresync_clk - update \data_r0__o $0\data_r0__o[63:0] - end - attribute \src "issuer_ls180.v:21226.3-21227.43" - process $proc$issuer_ls180.v:21226$545 - assign { } { } - assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next - sync posedge \coresync_clk - update \data_r0__o_ok $0\data_r0__o_ok[0:0] - end - attribute \src "issuer_ls180.v:21228.3-21229.69" - process $proc$issuer_ls180.v:21228$546 - assign { } { } - assign $0\alu_alu0_alu_op__insn_type[6:0] \alu_alu0_alu_op__insn_type$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__insn_type $0\alu_alu0_alu_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:21230.3-21231.65" - process $proc$issuer_ls180.v:21230$547 - assign { } { } - assign $0\alu_alu0_alu_op__fn_unit[11:0] \alu_alu0_alu_op__fn_unit$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__fn_unit $0\alu_alu0_alu_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:21232.3-21233.79" - process $proc$issuer_ls180.v:21232$548 - assign { } { } - assign $0\alu_alu0_alu_op__imm_data__data[63:0] \alu_alu0_alu_op__imm_data__data$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__imm_data__data $0\alu_alu0_alu_op__imm_data__data[63:0] - end - attribute \src "issuer_ls180.v:21234.3-21235.75" - process $proc$issuer_ls180.v:21234$549 - assign { } { } - assign $0\alu_alu0_alu_op__imm_data__ok[0:0] \alu_alu0_alu_op__imm_data__ok$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__imm_data__ok $0\alu_alu0_alu_op__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:21236.3-21237.63" - process $proc$issuer_ls180.v:21236$550 - assign { } { } - assign $0\alu_alu0_alu_op__rc__rc[0:0] \alu_alu0_alu_op__rc__rc$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__rc__rc $0\alu_alu0_alu_op__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:21238.3-21239.63" - process $proc$issuer_ls180.v:21238$551 - assign { } { } - assign $0\alu_alu0_alu_op__rc__ok[0:0] \alu_alu0_alu_op__rc__ok$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__rc__ok $0\alu_alu0_alu_op__rc__ok[0:0] - end - attribute \src "issuer_ls180.v:21240.3-21241.63" - process $proc$issuer_ls180.v:21240$552 - assign { } { } - assign $0\alu_alu0_alu_op__oe__oe[0:0] \alu_alu0_alu_op__oe__oe$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__oe__oe $0\alu_alu0_alu_op__oe__oe[0:0] - end - attribute \src "issuer_ls180.v:21242.3-21243.63" - process $proc$issuer_ls180.v:21242$553 - assign { } { } - assign $0\alu_alu0_alu_op__oe__ok[0:0] \alu_alu0_alu_op__oe__ok$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__oe__ok $0\alu_alu0_alu_op__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:21244.3-21245.69" - process $proc$issuer_ls180.v:21244$554 - assign { } { } - assign $0\alu_alu0_alu_op__invert_in[0:0] \alu_alu0_alu_op__invert_in$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__invert_in $0\alu_alu0_alu_op__invert_in[0:0] - end - attribute \src "issuer_ls180.v:21246.3-21247.63" - process $proc$issuer_ls180.v:21246$555 - assign { } { } - assign $0\alu_alu0_alu_op__zero_a[0:0] \alu_alu0_alu_op__zero_a$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__zero_a $0\alu_alu0_alu_op__zero_a[0:0] - end - attribute \src "issuer_ls180.v:21248.3-21249.71" - process $proc$issuer_ls180.v:21248$556 - assign { } { } - assign $0\alu_alu0_alu_op__invert_out[0:0] \alu_alu0_alu_op__invert_out$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__invert_out $0\alu_alu0_alu_op__invert_out[0:0] - end - attribute \src "issuer_ls180.v:21250.3-21251.69" - process $proc$issuer_ls180.v:21250$557 - assign { } { } - assign $0\alu_alu0_alu_op__write_cr0[0:0] \alu_alu0_alu_op__write_cr0$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__write_cr0 $0\alu_alu0_alu_op__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:21252.3-21253.73" - process $proc$issuer_ls180.v:21252$558 - assign { } { } - assign $0\alu_alu0_alu_op__input_carry[1:0] \alu_alu0_alu_op__input_carry$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__input_carry $0\alu_alu0_alu_op__input_carry[1:0] - end - attribute \src "issuer_ls180.v:21254.3-21255.75" - process $proc$issuer_ls180.v:21254$559 - assign { } { } - assign $0\alu_alu0_alu_op__output_carry[0:0] \alu_alu0_alu_op__output_carry$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__output_carry $0\alu_alu0_alu_op__output_carry[0:0] - end - attribute \src "issuer_ls180.v:21256.3-21257.67" - process $proc$issuer_ls180.v:21256$560 - assign { } { } - assign $0\alu_alu0_alu_op__is_32bit[0:0] \alu_alu0_alu_op__is_32bit$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__is_32bit $0\alu_alu0_alu_op__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:21258.3-21259.69" - process $proc$issuer_ls180.v:21258$561 - assign { } { } - assign $0\alu_alu0_alu_op__is_signed[0:0] \alu_alu0_alu_op__is_signed$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__is_signed $0\alu_alu0_alu_op__is_signed[0:0] - end - attribute \src "issuer_ls180.v:21260.3-21261.67" - process $proc$issuer_ls180.v:21260$562 - assign { } { } - assign $0\alu_alu0_alu_op__data_len[3:0] \alu_alu0_alu_op__data_len$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__data_len $0\alu_alu0_alu_op__data_len[3:0] - end - attribute \src "issuer_ls180.v:21262.3-21263.59" - process $proc$issuer_ls180.v:21262$563 - assign { } { } - assign $0\alu_alu0_alu_op__insn[31:0] \alu_alu0_alu_op__insn$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__insn $0\alu_alu0_alu_op__insn[31:0] - end - attribute \src "issuer_ls180.v:21264.3-21265.39" - process $proc$issuer_ls180.v:21264$564 - assign { } { } - assign $0\req_l_r_req[4:0] \req_l_r_req$next - sync posedge \coresync_clk - update \req_l_r_req $0\req_l_r_req[4:0] - end - attribute \src "issuer_ls180.v:21266.3-21267.39" - process $proc$issuer_ls180.v:21266$565 - assign { } { } - assign $0\req_l_s_req[4:0] \req_l_s_req$next - sync posedge \coresync_clk - update \req_l_s_req $0\req_l_s_req[4:0] - end - attribute \src "issuer_ls180.v:21268.3-21269.39" - process $proc$issuer_ls180.v:21268$566 - assign { } { } - assign $0\src_l_r_src[3:0] \src_l_r_src$next - sync posedge \coresync_clk - update \src_l_r_src $0\src_l_r_src[3:0] - end - attribute \src "issuer_ls180.v:21270.3-21271.39" - process $proc$issuer_ls180.v:21270$567 - assign { } { } - assign $0\src_l_s_src[3:0] \src_l_s_src$next - sync posedge \coresync_clk - update \src_l_s_src $0\src_l_s_src[3:0] - end - attribute \src "issuer_ls180.v:21272.3-21273.39" - process $proc$issuer_ls180.v:21272$568 - assign { } { } - assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next - sync posedge \coresync_clk - update \opc_l_r_opc $0\opc_l_r_opc[0:0] - end - attribute \src "issuer_ls180.v:21274.3-21275.39" - process $proc$issuer_ls180.v:21274$569 - assign { } { } - assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next - sync posedge \coresync_clk - update \opc_l_s_opc $0\opc_l_s_opc[0:0] - end - attribute \src "issuer_ls180.v:21276.3-21277.39" - process $proc$issuer_ls180.v:21276$570 - assign { } { } - assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next - sync posedge \coresync_clk - update \rst_l_r_rst $0\rst_l_r_rst[0:0] - end - attribute \src "issuer_ls180.v:21278.3-21279.39" - process $proc$issuer_ls180.v:21278$571 - assign { } { } - assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next - sync posedge \coresync_clk - update \rst_l_s_rst $0\rst_l_s_rst[0:0] - end - attribute \src "issuer_ls180.v:21280.3-21281.41" - process $proc$issuer_ls180.v:21280$572 - assign { } { } - assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next - sync posedge \coresync_clk - update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] - end - attribute \src "issuer_ls180.v:21282.3-21283.41" - process $proc$issuer_ls180.v:21282$573 - assign { } { } - assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next - sync posedge \coresync_clk - update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] - end - attribute \src "issuer_ls180.v:21284.3-21285.37" - process $proc$issuer_ls180.v:21284$574 - assign { } { } - assign $0\prev_wr_go[4:0] \prev_wr_go$next - sync posedge \coresync_clk - update \prev_wr_go $0\prev_wr_go[4:0] - end - attribute \src "issuer_ls180.v:21286.3-21287.40" - process $proc$issuer_ls180.v:21286$575 - assign { } { } - assign $0\alu_done_dly[0:0] \alu_alu0_n_valid_o - sync posedge \coresync_clk - update \alu_done_dly $0\alu_done_dly[0:0] - end - attribute \src "issuer_ls180.v:21288.3-21289.25" - process $proc$issuer_ls180.v:21288$576 - assign { } { } - assign $0\all_rd_dly[0:0] \$11 - sync posedge \coresync_clk - update \all_rd_dly $0\all_rd_dly[0:0] - end - attribute \src "issuer_ls180.v:21378.3-21387.6" - process $proc$issuer_ls180.v:21378$577 + attribute \src "libresoc.v:17129.3-17189.6" + process $proc$libresoc.v:17129$351 assign { } { } assign { } { } - assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "issuer_ls180.v:21379.5-21379.29" + assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0] + attribute \src "libresoc.v:17130.5-17130.29" switch \initial - attribute \src "issuer_ls180.v:21379.9-21379.17" + attribute \src "libresoc.v:17130.9-17130.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch \$55 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } - assign $1\req_done[0:0] 1'1 - case - assign $1\req_done[0:0] \$47 - end - sync always - update \req_done $0\req_done[0:0] - end - attribute \src "issuer_ls180.v:21388.3-21396.6" - process $proc$issuer_ls180.v:21388$578 - assign { } { } - assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$579 $1\rok_l_s_rdok$next[0:0]$580 - attribute \src "issuer_ls180.v:21389.5-21389.29" - switch \initial - attribute \src "issuer_ls180.v:21389.9-21389.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_cr_out[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$580 1'0 - case - assign $1\rok_l_s_rdok$next[0:0]$580 \cu_issue_i - end - sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$579 - end - attribute \src "issuer_ls180.v:21397.3-21405.6" - process $proc$issuer_ls180.v:21397$581 - assign { } { } - assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$582 $1\rok_l_r_rdok$next[0:0]$583 - attribute \src "issuer_ls180.v:21398.5-21398.29" - switch \initial - attribute \src "issuer_ls180.v:21398.9-21398.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_cr_out[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$583 1'1 + assign $1\dec31_cr_out[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_out case - assign $1\rok_l_r_rdok$next[0:0]$583 \$65 + assign $1\dec31_cr_out[2:0] 3'000 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$582 + update \dec31_cr_out $0\dec31_cr_out[2:0] end - attribute \src "issuer_ls180.v:21406.3-21414.6" - process $proc$issuer_ls180.v:21406$584 + attribute \src "libresoc.v:17190.3-17250.6" + process $proc$libresoc.v:17190$352 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$585 $1\rst_l_s_rst$next[0:0]$586 - attribute \src "issuer_ls180.v:21407.5-21407.29" + assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0] + attribute \src "libresoc.v:17191.5-17191.29" switch \initial - attribute \src "issuer_ls180.v:21407.9-21407.17" + attribute \src "libresoc.v:17191.9-17191.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub10_dec31_dec_sub10_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub28_dec31_dec_sub28_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub0_dec31_dec_sub0_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub26_dec31_dec_sub26_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub19_dec31_dec_sub19_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub22_dec31_dec_sub22_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub9_dec31_dec_sub9_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub11_dec31_dec_sub11_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub27_dec31_dec_sub27_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub15_dec31_dec_sub15_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$586 1'0 + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub20_dec31_dec_sub20_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub21_dec31_dec_sub21_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub23_dec31_dec_sub23_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub16_dec31_dec_sub16_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub18_dec31_dec_sub18_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub8_dec31_dec_sub8_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub24_dec31_dec_sub24_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub4_dec31_dec_sub4_ldst_len case - assign $1\rst_l_s_rst$next[0:0]$586 \all_rd + assign $1\dec31_ldst_len[3:0] 4'0000 end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$585 + update \dec31_ldst_len $0\dec31_ldst_len[3:0] end - attribute \src "issuer_ls180.v:21415.3-21423.6" - process $proc$issuer_ls180.v:21415$587 + attribute \src "libresoc.v:17251.3-17311.6" + process $proc$libresoc.v:17251$353 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$588 $1\rst_l_r_rst$next[0:0]$589 - attribute \src "issuer_ls180.v:21416.5-21416.29" + assign $0\dec31_upd[1:0] $1\dec31_upd[1:0] + attribute \src "libresoc.v:17252.5-17252.29" switch \initial - attribute \src "issuer_ls180.v:21416.9-21416.17" + attribute \src "libresoc.v:17252.9-17252.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$589 1'1 - case - assign $1\rst_l_r_rst$next[0:0]$589 \rst_r - end - sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$588 - end - attribute \src "issuer_ls180.v:21424.3-21432.6" - process $proc$issuer_ls180.v:21424$590 - assign { } { } - assign { } { } - assign $0\opc_l_s_opc$next[0:0]$591 $1\opc_l_s_opc$next[0:0]$592 - attribute \src "issuer_ls180.v:21425.5-21425.29" - switch \initial - attribute \src "issuer_ls180.v:21425.9-21425.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_upd[1:0] \dec31_dec_sub10_dec31_dec_sub10_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$592 1'0 - case - assign $1\opc_l_s_opc$next[0:0]$592 \cu_issue_i - end - sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$591 - end - attribute \src "issuer_ls180.v:21433.3-21441.6" - process $proc$issuer_ls180.v:21433$593 - assign { } { } - assign { } { } - assign $0\opc_l_r_opc$next[0:0]$594 $1\opc_l_r_opc$next[0:0]$595 - attribute \src "issuer_ls180.v:21434.5-21434.29" - switch \initial - attribute \src "issuer_ls180.v:21434.9-21434.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_upd[1:0] \dec31_dec_sub28_dec31_dec_sub28_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$595 1'1 - case - assign $1\opc_l_r_opc$next[0:0]$595 \req_done - end - sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$594 - end - attribute \src "issuer_ls180.v:21442.3-21450.6" - process $proc$issuer_ls180.v:21442$596 - assign { } { } - assign { } { } - assign $0\src_l_s_src$next[3:0]$597 $1\src_l_s_src$next[3:0]$598 - attribute \src "issuer_ls180.v:21443.5-21443.29" - switch \initial - attribute \src "issuer_ls180.v:21443.9-21443.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_upd[1:0] \dec31_dec_sub0_dec31_dec_sub0_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 assign { } { } - assign $1\src_l_s_src$next[3:0]$598 4'0000 - case - assign $1\src_l_s_src$next[3:0]$598 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } - end - sync always - update \src_l_s_src$next $0\src_l_s_src$next[3:0]$597 - end - attribute \src "issuer_ls180.v:21451.3-21459.6" - process $proc$issuer_ls180.v:21451$599 - assign { } { } - assign { } { } - assign $0\src_l_r_src$next[3:0]$600 $1\src_l_r_src$next[3:0]$601 - attribute \src "issuer_ls180.v:21452.5-21452.29" - switch \initial - attribute \src "issuer_ls180.v:21452.9-21452.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_upd[1:0] \dec31_dec_sub26_dec31_dec_sub26_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } - assign $1\src_l_r_src$next[3:0]$601 4'1111 - case - assign $1\src_l_r_src$next[3:0]$601 \reset_r - end - sync always - update \src_l_r_src$next $0\src_l_r_src$next[3:0]$600 - end - attribute \src "issuer_ls180.v:21460.3-21468.6" - process $proc$issuer_ls180.v:21460$602 - assign { } { } - assign { } { } - assign $0\req_l_s_req$next[4:0]$603 $1\req_l_s_req$next[4:0]$604 - attribute \src "issuer_ls180.v:21461.5-21461.29" - switch \initial - attribute \src "issuer_ls180.v:21461.9-21461.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_upd[1:0] \dec31_dec_sub19_dec31_dec_sub19_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\req_l_s_req$next[4:0]$604 5'00000 - case - assign $1\req_l_s_req$next[4:0]$604 \$67 - end - sync always - update \req_l_s_req$next $0\req_l_s_req$next[4:0]$603 - end - attribute \src "issuer_ls180.v:21469.3-21477.6" - process $proc$issuer_ls180.v:21469$605 - assign { } { } - assign { } { } - assign $0\req_l_r_req$next[4:0]$606 $1\req_l_r_req$next[4:0]$607 - attribute \src "issuer_ls180.v:21470.5-21470.29" - switch \initial - attribute \src "issuer_ls180.v:21470.9-21470.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_upd[1:0] \dec31_dec_sub22_dec31_dec_sub22_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub9_dec31_dec_sub9_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub11_dec31_dec_sub11_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub27_dec31_dec_sub27_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub15_dec31_dec_sub15_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub20_dec31_dec_sub20_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub21_dec31_dec_sub21_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub23_dec31_dec_sub23_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub16_dec31_dec_sub16_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub18_dec31_dec_sub18_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub8_dec31_dec_sub8_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } - assign $1\req_l_r_req$next[4:0]$607 5'11111 + assign $1\dec31_upd[1:0] \dec31_dec_sub24_dec31_dec_sub24_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub4_dec31_dec_sub4_upd case - assign $1\req_l_r_req$next[4:0]$607 \$69 + assign $1\dec31_upd[1:0] 2'00 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[4:0]$606 + update \dec31_upd $0\dec31_upd[1:0] end - attribute \src "issuer_ls180.v:21478.3-21516.6" - process $proc$issuer_ls180.v:21478$608 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:17312.3-17372.6" + process $proc$libresoc.v:17312$354 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_alu0_alu_op__data_len$next[3:0]$609 $1\alu_alu0_alu_op__data_len$next[3:0]$627 - assign $0\alu_alu0_alu_op__fn_unit$next[11:0]$610 $1\alu_alu0_alu_op__fn_unit$next[11:0]$628 - assign { } { } - assign { } { } - assign $0\alu_alu0_alu_op__input_carry$next[1:0]$613 $1\alu_alu0_alu_op__input_carry$next[1:0]$631 - assign $0\alu_alu0_alu_op__insn$next[31:0]$614 $1\alu_alu0_alu_op__insn$next[31:0]$632 - assign $0\alu_alu0_alu_op__insn_type$next[6:0]$615 $1\alu_alu0_alu_op__insn_type$next[6:0]$633 - assign $0\alu_alu0_alu_op__invert_in$next[0:0]$616 $1\alu_alu0_alu_op__invert_in$next[0:0]$634 - assign $0\alu_alu0_alu_op__invert_out$next[0:0]$617 $1\alu_alu0_alu_op__invert_out$next[0:0]$635 - assign $0\alu_alu0_alu_op__is_32bit$next[0:0]$618 $1\alu_alu0_alu_op__is_32bit$next[0:0]$636 - assign $0\alu_alu0_alu_op__is_signed$next[0:0]$619 $1\alu_alu0_alu_op__is_signed$next[0:0]$637 - assign { } { } - assign { } { } - assign $0\alu_alu0_alu_op__output_carry$next[0:0]$622 $1\alu_alu0_alu_op__output_carry$next[0:0]$640 - assign { } { } - assign { } { } - assign $0\alu_alu0_alu_op__write_cr0$next[0:0]$625 $1\alu_alu0_alu_op__write_cr0$next[0:0]$643 - assign $0\alu_alu0_alu_op__zero_a$next[0:0]$626 $1\alu_alu0_alu_op__zero_a$next[0:0]$644 - assign $0\alu_alu0_alu_op__imm_data__data$next[63:0]$611 $2\alu_alu0_alu_op__imm_data__data$next[63:0]$645 - assign $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$612 $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$646 - assign $0\alu_alu0_alu_op__oe__oe$next[0:0]$620 $2\alu_alu0_alu_op__oe__oe$next[0:0]$647 - assign $0\alu_alu0_alu_op__oe__ok$next[0:0]$621 $2\alu_alu0_alu_op__oe__ok$next[0:0]$648 - assign $0\alu_alu0_alu_op__rc__ok$next[0:0]$623 $2\alu_alu0_alu_op__rc__ok$next[0:0]$649 - assign $0\alu_alu0_alu_op__rc__rc$next[0:0]$624 $2\alu_alu0_alu_op__rc__rc$next[0:0]$650 - attribute \src "issuer_ls180.v:21479.5-21479.29" + assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0] + attribute \src "libresoc.v:17313.5-17313.29" switch \initial - attribute \src "issuer_ls180.v:21479.9-21479.17" + attribute \src "libresoc.v:17313.9-17313.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 assign { } { } - assign { $1\alu_alu0_alu_op__insn$next[31:0]$632 $1\alu_alu0_alu_op__data_len$next[3:0]$627 $1\alu_alu0_alu_op__is_signed$next[0:0]$637 $1\alu_alu0_alu_op__is_32bit$next[0:0]$636 $1\alu_alu0_alu_op__output_carry$next[0:0]$640 $1\alu_alu0_alu_op__input_carry$next[1:0]$631 $1\alu_alu0_alu_op__write_cr0$next[0:0]$643 $1\alu_alu0_alu_op__invert_out$next[0:0]$635 $1\alu_alu0_alu_op__zero_a$next[0:0]$644 $1\alu_alu0_alu_op__invert_in$next[0:0]$634 $1\alu_alu0_alu_op__oe__ok$next[0:0]$639 $1\alu_alu0_alu_op__oe__oe$next[0:0]$638 $1\alu_alu0_alu_op__rc__ok$next[0:0]$641 $1\alu_alu0_alu_op__rc__rc$next[0:0]$642 $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$630 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$629 $1\alu_alu0_alu_op__fn_unit$next[11:0]$628 $1\alu_alu0_alu_op__insn_type$next[6:0]$633 } { \oper_i_alu_alu0__insn \oper_i_alu_alu0__data_len \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__insn_type } - case - assign $1\alu_alu0_alu_op__data_len$next[3:0]$627 \alu_alu0_alu_op__data_len - assign $1\alu_alu0_alu_op__fn_unit$next[11:0]$628 \alu_alu0_alu_op__fn_unit - assign $1\alu_alu0_alu_op__imm_data__data$next[63:0]$629 \alu_alu0_alu_op__imm_data__data - assign $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$630 \alu_alu0_alu_op__imm_data__ok - assign $1\alu_alu0_alu_op__input_carry$next[1:0]$631 \alu_alu0_alu_op__input_carry - assign $1\alu_alu0_alu_op__insn$next[31:0]$632 \alu_alu0_alu_op__insn - assign $1\alu_alu0_alu_op__insn_type$next[6:0]$633 \alu_alu0_alu_op__insn_type - assign $1\alu_alu0_alu_op__invert_in$next[0:0]$634 \alu_alu0_alu_op__invert_in - assign $1\alu_alu0_alu_op__invert_out$next[0:0]$635 \alu_alu0_alu_op__invert_out - assign $1\alu_alu0_alu_op__is_32bit$next[0:0]$636 \alu_alu0_alu_op__is_32bit - assign $1\alu_alu0_alu_op__is_signed$next[0:0]$637 \alu_alu0_alu_op__is_signed - assign $1\alu_alu0_alu_op__oe__oe$next[0:0]$638 \alu_alu0_alu_op__oe__oe - assign $1\alu_alu0_alu_op__oe__ok$next[0:0]$639 \alu_alu0_alu_op__oe__ok - assign $1\alu_alu0_alu_op__output_carry$next[0:0]$640 \alu_alu0_alu_op__output_carry - assign $1\alu_alu0_alu_op__rc__ok$next[0:0]$641 \alu_alu0_alu_op__rc__ok - assign $1\alu_alu0_alu_op__rc__rc$next[0:0]$642 \alu_alu0_alu_op__rc__rc - assign $1\alu_alu0_alu_op__write_cr0$next[0:0]$643 \alu_alu0_alu_op__write_cr0 - assign $1\alu_alu0_alu_op__zero_a$next[0:0]$644 \alu_alu0_alu_op__zero_a - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $2\alu_alu0_alu_op__imm_data__data$next[63:0]$645 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$646 1'0 - assign $2\alu_alu0_alu_op__rc__rc$next[0:0]$650 1'0 - assign $2\alu_alu0_alu_op__rc__ok$next[0:0]$649 1'0 - assign $2\alu_alu0_alu_op__oe__oe$next[0:0]$647 1'0 - assign $2\alu_alu0_alu_op__oe__ok$next[0:0]$648 1'0 + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_rc_sel case - assign $2\alu_alu0_alu_op__imm_data__data$next[63:0]$645 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$629 - assign $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$646 $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$630 - assign $2\alu_alu0_alu_op__oe__oe$next[0:0]$647 $1\alu_alu0_alu_op__oe__oe$next[0:0]$638 - assign $2\alu_alu0_alu_op__oe__ok$next[0:0]$648 $1\alu_alu0_alu_op__oe__ok$next[0:0]$639 - assign $2\alu_alu0_alu_op__rc__ok$next[0:0]$649 $1\alu_alu0_alu_op__rc__ok$next[0:0]$641 - assign $2\alu_alu0_alu_op__rc__rc$next[0:0]$650 $1\alu_alu0_alu_op__rc__rc$next[0:0]$642 + assign $1\dec31_rc_sel[1:0] 2'00 end sync always - update \alu_alu0_alu_op__data_len$next $0\alu_alu0_alu_op__data_len$next[3:0]$609 - update \alu_alu0_alu_op__fn_unit$next $0\alu_alu0_alu_op__fn_unit$next[11:0]$610 - update \alu_alu0_alu_op__imm_data__data$next $0\alu_alu0_alu_op__imm_data__data$next[63:0]$611 - update \alu_alu0_alu_op__imm_data__ok$next $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$612 - update \alu_alu0_alu_op__input_carry$next $0\alu_alu0_alu_op__input_carry$next[1:0]$613 - update \alu_alu0_alu_op__insn$next $0\alu_alu0_alu_op__insn$next[31:0]$614 - update \alu_alu0_alu_op__insn_type$next $0\alu_alu0_alu_op__insn_type$next[6:0]$615 - update \alu_alu0_alu_op__invert_in$next $0\alu_alu0_alu_op__invert_in$next[0:0]$616 - update \alu_alu0_alu_op__invert_out$next $0\alu_alu0_alu_op__invert_out$next[0:0]$617 - update \alu_alu0_alu_op__is_32bit$next $0\alu_alu0_alu_op__is_32bit$next[0:0]$618 - update \alu_alu0_alu_op__is_signed$next $0\alu_alu0_alu_op__is_signed$next[0:0]$619 - update \alu_alu0_alu_op__oe__oe$next $0\alu_alu0_alu_op__oe__oe$next[0:0]$620 - update \alu_alu0_alu_op__oe__ok$next $0\alu_alu0_alu_op__oe__ok$next[0:0]$621 - update \alu_alu0_alu_op__output_carry$next $0\alu_alu0_alu_op__output_carry$next[0:0]$622 - update \alu_alu0_alu_op__rc__ok$next $0\alu_alu0_alu_op__rc__ok$next[0:0]$623 - update \alu_alu0_alu_op__rc__rc$next $0\alu_alu0_alu_op__rc__rc$next[0:0]$624 - update \alu_alu0_alu_op__write_cr0$next $0\alu_alu0_alu_op__write_cr0$next[0:0]$625 - update \alu_alu0_alu_op__zero_a$next $0\alu_alu0_alu_op__zero_a$next[0:0]$626 + update \dec31_rc_sel $0\dec31_rc_sel[1:0] end - attribute \src "issuer_ls180.v:21517.3-21538.6" - process $proc$issuer_ls180.v:21517$651 - assign { } { } - assign { } { } + attribute \src "libresoc.v:17373.3-17433.6" + process $proc$libresoc.v:17373$355 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\data_r0__o$next[63:0]$652 $2\data_r0__o$next[63:0]$656 - assign { } { } - assign $0\data_r0__o_ok$next[0:0]$653 $3\data_r0__o_ok$next[0:0]$658 - attribute \src "issuer_ls180.v:21518.5-21518.29" + assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0] + attribute \src "libresoc.v:17374.5-17374.29" switch \initial - attribute \src "issuer_ls180.v:21518.9-21518.17" + attribute \src "libresoc.v:17374.9-17374.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub10_dec31_dec_sub10_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$655 $1\data_r0__o$next[63:0]$654 } { \o_ok \alu_alu0_o } - case - assign $1\data_r0__o$next[63:0]$654 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$655 \data_r0__o_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_cry_in[1:0] \dec31_dec_sub28_dec31_dec_sub28_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub0_dec31_dec_sub0_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$657 $2\data_r0__o$next[63:0]$656 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r0__o$next[63:0]$656 $1\data_r0__o$next[63:0]$654 - assign $2\data_r0__o_ok$next[0:0]$657 $1\data_r0__o_ok$next[0:0]$655 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_cry_in[1:0] \dec31_dec_sub26_dec31_dec_sub26_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$658 1'0 - case - assign $3\data_r0__o_ok$next[0:0]$658 $2\data_r0__o_ok$next[0:0]$657 - end - sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$652 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$653 - end - attribute \src "issuer_ls180.v:21539.3-21560.6" - process $proc$issuer_ls180.v:21539$659 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r1__cr_a$next[3:0]$660 $2\data_r1__cr_a$next[3:0]$664 - assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$661 $3\data_r1__cr_a_ok$next[0:0]$666 - attribute \src "issuer_ls180.v:21540.5-21540.29" - switch \initial - attribute \src "issuer_ls180.v:21540.9-21540.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_cry_in[1:0] \dec31_dec_sub19_dec31_dec_sub19_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub22_dec31_dec_sub22_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$663 $1\data_r1__cr_a$next[3:0]$662 } { \cr_a_ok \alu_alu0_cr_a } - case - assign $1\data_r1__cr_a$next[3:0]$662 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$663 \data_r1__cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_cry_in[1:0] \dec31_dec_sub9_dec31_dec_sub9_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub11_dec31_dec_sub11_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$665 $2\data_r1__cr_a$next[3:0]$664 } 5'00000 - case - assign $2\data_r1__cr_a$next[3:0]$664 $1\data_r1__cr_a$next[3:0]$662 - assign $2\data_r1__cr_a_ok$next[0:0]$665 $1\data_r1__cr_a_ok$next[0:0]$663 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_cry_in[1:0] \dec31_dec_sub27_dec31_dec_sub27_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$666 1'0 - case - assign $3\data_r1__cr_a_ok$next[0:0]$666 $2\data_r1__cr_a_ok$next[0:0]$665 - end - sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$660 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$661 - end - attribute \src "issuer_ls180.v:21561.3-21582.6" - process $proc$issuer_ls180.v:21561$667 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r2__xer_ca$next[1:0]$668 $2\data_r2__xer_ca$next[1:0]$672 - assign { } { } - assign $0\data_r2__xer_ca_ok$next[0:0]$669 $3\data_r2__xer_ca_ok$next[0:0]$674 - attribute \src "issuer_ls180.v:21562.5-21562.29" - switch \initial - attribute \src "issuer_ls180.v:21562.9-21562.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_cry_in[1:0] \dec31_dec_sub15_dec31_dec_sub15_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub20_dec31_dec_sub20_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub21_dec31_dec_sub21_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } - assign { $1\data_r2__xer_ca_ok$next[0:0]$671 $1\data_r2__xer_ca$next[1:0]$670 } { \xer_ca_ok \alu_alu0_xer_ca } - case - assign $1\data_r2__xer_ca$next[1:0]$670 \data_r2__xer_ca - assign $1\data_r2__xer_ca_ok$next[0:0]$671 \data_r2__xer_ca_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_cry_in[1:0] \dec31_dec_sub23_dec31_dec_sub23_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub16_dec31_dec_sub16_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 assign { } { } - assign { $2\data_r2__xer_ca_ok$next[0:0]$673 $2\data_r2__xer_ca$next[1:0]$672 } 3'000 - case - assign $2\data_r2__xer_ca$next[1:0]$672 $1\data_r2__xer_ca$next[1:0]$670 - assign $2\data_r2__xer_ca_ok$next[0:0]$673 $1\data_r2__xer_ca_ok$next[0:0]$671 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_cry_in[1:0] \dec31_dec_sub18_dec31_dec_sub18_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } - assign $3\data_r2__xer_ca_ok$next[0:0]$674 1'0 + assign $1\dec31_cry_in[1:0] \dec31_dec_sub8_dec31_dec_sub8_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub24_dec31_dec_sub24_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub4_dec31_dec_sub4_cry_in case - assign $3\data_r2__xer_ca_ok$next[0:0]$674 $2\data_r2__xer_ca_ok$next[0:0]$673 + assign $1\dec31_cry_in[1:0] 2'00 end sync always - update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$668 - update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$669 + update \dec31_cry_in $0\dec31_cry_in[1:0] end - attribute \src "issuer_ls180.v:21583.3-21604.6" - process $proc$issuer_ls180.v:21583$675 - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:17434.3-17494.6" + process $proc$libresoc.v:17434$356 assign { } { } assign { } { } - assign { } { } - assign $0\data_r3__xer_ov$next[1:0]$676 $2\data_r3__xer_ov$next[1:0]$680 - assign { } { } - assign $0\data_r3__xer_ov_ok$next[0:0]$677 $3\data_r3__xer_ov_ok$next[0:0]$682 - attribute \src "issuer_ls180.v:21584.5-21584.29" + assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0] + attribute \src "libresoc.v:17435.5-17435.29" switch \initial - attribute \src "issuer_ls180.v:21584.9-21584.17" + attribute \src "libresoc.v:17435.9-17435.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign { $1\data_r3__xer_ov_ok$next[0:0]$679 $1\data_r3__xer_ov$next[1:0]$678 } { \xer_ov_ok \alu_alu0_xer_ov } - case - assign $1\data_r3__xer_ov$next[1:0]$678 \data_r3__xer_ov - assign $1\data_r3__xer_ov_ok$next[0:0]$679 \data_r3__xer_ov_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_inv_a[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 assign { } { } - assign { $2\data_r3__xer_ov_ok$next[0:0]$681 $2\data_r3__xer_ov$next[1:0]$680 } 3'000 - case - assign $2\data_r3__xer_ov$next[1:0]$680 $1\data_r3__xer_ov$next[1:0]$678 - assign $2\data_r3__xer_ov_ok$next[0:0]$681 $1\data_r3__xer_ov_ok$next[0:0]$679 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_inv_a[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } - assign $3\data_r3__xer_ov_ok$next[0:0]$682 1'0 - case - assign $3\data_r3__xer_ov_ok$next[0:0]$682 $2\data_r3__xer_ov_ok$next[0:0]$681 - end - sync always - update \data_r3__xer_ov$next $0\data_r3__xer_ov$next[1:0]$676 - update \data_r3__xer_ov_ok$next $0\data_r3__xer_ov_ok$next[0:0]$677 - end - attribute \src "issuer_ls180.v:21605.3-21626.6" - process $proc$issuer_ls180.v:21605$683 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r4__xer_so$next[0:0]$684 $2\data_r4__xer_so$next[0:0]$688 - assign { } { } - assign $0\data_r4__xer_so_ok$next[0:0]$685 $3\data_r4__xer_so_ok$next[0:0]$690 - attribute \src "issuer_ls180.v:21606.5-21606.29" - switch \initial - attribute \src "issuer_ls180.v:21606.9-21606.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_inv_a[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } - assign { $1\data_r4__xer_so_ok$next[0:0]$687 $1\data_r4__xer_so$next[0:0]$686 } { \xer_so_ok \alu_alu0_xer_so } - case - assign $1\data_r4__xer_so$next[0:0]$686 \data_r4__xer_so - assign $1\data_r4__xer_so_ok$next[0:0]$687 \data_r4__xer_so_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_inv_a[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 assign { } { } - assign { $2\data_r4__xer_so_ok$next[0:0]$689 $2\data_r4__xer_so$next[0:0]$688 } 2'00 - case - assign $2\data_r4__xer_so$next[0:0]$688 $1\data_r4__xer_so$next[0:0]$686 - assign $2\data_r4__xer_so_ok$next[0:0]$689 $1\data_r4__xer_so_ok$next[0:0]$687 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_inv_a[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 assign { } { } - assign $3\data_r4__xer_so_ok$next[0:0]$690 1'0 - case - assign $3\data_r4__xer_so_ok$next[0:0]$690 $2\data_r4__xer_so_ok$next[0:0]$689 - end - sync always - update \data_r4__xer_so$next $0\data_r4__xer_so$next[0:0]$684 - update \data_r4__xer_so_ok$next $0\data_r4__xer_so_ok$next[0:0]$685 - end - attribute \src "issuer_ls180.v:21627.3-21636.6" - process $proc$issuer_ls180.v:21627$691 - assign { } { } - assign { } { } - assign $0\src_r0$next[63:0]$692 $1\src_r0$next[63:0]$693 - attribute \src "issuer_ls180.v:21628.5-21628.29" - switch \initial - attribute \src "issuer_ls180.v:21628.9-21628.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_inv_a[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } - assign $1\src_r0$next[63:0]$693 \src_or_imm - case - assign $1\src_r0$next[63:0]$693 \src_r0 - end - sync always - update \src_r0$next $0\src_r0$next[63:0]$692 - end - attribute \src "issuer_ls180.v:21637.3-21646.6" - process $proc$issuer_ls180.v:21637$694 - assign { } { } - assign { } { } - assign $0\src_r1$next[63:0]$695 $1\src_r1$next[63:0]$696 - attribute \src "issuer_ls180.v:21638.5-21638.29" - switch \initial - attribute \src "issuer_ls180.v:21638.9-21638.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_sel$85 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_inv_a[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } - assign $1\src_r1$next[63:0]$696 \src_or_imm$88 + assign $1\dec31_inv_a[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_a case - assign $1\src_r1$next[63:0]$696 \src_r1 + assign $1\dec31_inv_a[0:0] 1'0 end sync always - update \src_r1$next $0\src_r1$next[63:0]$695 + update \dec31_inv_a $0\dec31_inv_a[0:0] end - attribute \src "issuer_ls180.v:21647.3-21656.6" - process $proc$issuer_ls180.v:21647$697 + attribute \src "libresoc.v:17495.3-17555.6" + process $proc$libresoc.v:17495$357 assign { } { } assign { } { } - assign $0\src_r2$next[0:0]$698 $1\src_r2$next[0:0]$699 - attribute \src "issuer_ls180.v:21648.5-21648.29" + assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0] + attribute \src "libresoc.v:17496.5-17496.29" switch \initial - attribute \src "issuer_ls180.v:21648.9-21648.17" + attribute \src "libresoc.v:17496.9-17496.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $1\src_r2$next[0:0]$699 \src3_i + assign $1\dec31_inv_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_out case - assign $1\src_r2$next[0:0]$699 \src_r2 + assign $1\dec31_inv_out[0:0] 1'0 end sync always - update \src_r2$next $0\src_r2$next[0:0]$698 + update \dec31_inv_out $0\dec31_inv_out[0:0] end - attribute \src "issuer_ls180.v:21657.3-21666.6" - process $proc$issuer_ls180.v:21657$700 + attribute \src "libresoc.v:17556.3-17616.6" + process $proc$libresoc.v:17556$358 assign { } { } assign { } { } - assign $0\src_r3$next[1:0]$701 $1\src_r3$next[1:0]$702 - attribute \src "issuer_ls180.v:21658.5-21658.29" + assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0] + attribute \src "libresoc.v:17557.5-17557.29" switch \initial - attribute \src "issuer_ls180.v:21658.9-21658.17" + attribute \src "libresoc.v:17557.9-17557.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [3] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } - assign $1\src_r3$next[1:0]$702 \src4_i + assign $1\dec31_cry_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_cry_out case - assign $1\src_r3$next[1:0]$702 \src_r3 + assign $1\dec31_cry_out[0:0] 1'0 end sync always - update \src_r3$next $0\src_r3$next[1:0]$701 + update \dec31_cry_out $0\dec31_cry_out[0:0] end - attribute \src "issuer_ls180.v:21667.3-21675.6" - process $proc$issuer_ls180.v:21667$703 + attribute \src "libresoc.v:17617.3-17677.6" + process $proc$libresoc.v:17617$359 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$704 $1\alui_l_r_alui$next[0:0]$705 - attribute \src "issuer_ls180.v:21668.5-21668.29" + assign $0\dec31_br[0:0] $1\dec31_br[0:0] + attribute \src "libresoc.v:17618.5-17618.29" switch \initial - attribute \src "issuer_ls180.v:21668.9-21668.17" + attribute \src "libresoc.v:17618.9-17618.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub10_dec31_dec_sub10_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub28_dec31_dec_sub28_br + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub0_dec31_dec_sub0_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub26_dec31_dec_sub26_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub19_dec31_dec_sub19_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub22_dec31_dec_sub22_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub9_dec31_dec_sub9_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub11_dec31_dec_sub11_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub27_dec31_dec_sub27_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub15_dec31_dec_sub15_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub20_dec31_dec_sub20_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub21_dec31_dec_sub21_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub23_dec31_dec_sub23_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub16_dec31_dec_sub16_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub18_dec31_dec_sub18_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub8_dec31_dec_sub8_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub24_dec31_dec_sub24_br + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$705 1'1 + assign $1\dec31_br[0:0] \dec31_dec_sub4_dec31_dec_sub4_br case - assign $1\alui_l_r_alui$next[0:0]$705 \$99 + assign $1\dec31_br[0:0] 1'0 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$704 + update \dec31_br $0\dec31_br[0:0] end - attribute \src "issuer_ls180.v:21676.3-21684.6" - process $proc$issuer_ls180.v:21676$706 + attribute \src "libresoc.v:17678.3-17738.6" + process $proc$libresoc.v:17678$360 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$707 $1\alu_l_r_alu$next[0:0]$708 - attribute \src "issuer_ls180.v:21677.5-21677.29" + assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0] + attribute \src "libresoc.v:17679.5-17679.29" switch \initial - attribute \src "issuer_ls180.v:21677.9-21677.17" + attribute \src "libresoc.v:17679.9-17679.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$708 1'1 + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn_ext case - assign $1\alu_l_r_alu$next[0:0]$708 \$101 + assign $1\dec31_sgn_ext[0:0] 1'0 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$707 + update \dec31_sgn_ext $0\dec31_sgn_ext[0:0] end - attribute \src "issuer_ls180.v:21685.3-21694.6" - process $proc$issuer_ls180.v:21685$709 + attribute \src "libresoc.v:17739.3-17799.6" + process $proc$libresoc.v:17739$361 assign { } { } assign { } { } - assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "issuer_ls180.v:21686.5-21686.29" + assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0] + attribute \src "libresoc.v:17740.5-17740.29" switch \initial - attribute \src "issuer_ls180.v:21686.9-21686.17" + attribute \src "libresoc.v:17740.9-17740.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$129 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub10_dec31_dec_sub10_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub28_dec31_dec_sub28_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub0_dec31_dec_sub0_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub26_dec31_dec_sub26_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub19_dec31_dec_sub19_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub22_dec31_dec_sub22_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub9_dec31_dec_sub9_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub11_dec31_dec_sub11_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub27_dec31_dec_sub27_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub15_dec31_dec_sub15_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub20_dec31_dec_sub20_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub21_dec31_dec_sub21_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub23_dec31_dec_sub23_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub16_dec31_dec_sub16_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 assign { } { } - assign $1\dest1_o[63:0] \data_r0__o + assign $1\dec31_rsrv[0:0] \dec31_dec_sub18_dec31_dec_sub18_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub8_dec31_dec_sub8_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub24_dec31_dec_sub24_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub4_dec31_dec_sub4_rsrv case - assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dec31_rsrv[0:0] 1'0 end sync always - update \dest1_o $0\dest1_o[63:0] + update \dec31_rsrv $0\dec31_rsrv[0:0] end - attribute \src "issuer_ls180.v:21695.3-21704.6" - process $proc$issuer_ls180.v:21695$710 + attribute \src "libresoc.v:17800.3-17860.6" + process $proc$libresoc.v:17800$362 assign { } { } assign { } { } - assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "issuer_ls180.v:21696.5-21696.29" + assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0] + attribute \src "libresoc.v:17801.5-17801.29" switch \initial - attribute \src "issuer_ls180.v:21696.9-21696.17" + attribute \src "libresoc.v:17801.9-17801.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$131 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub10_dec31_dec_sub10_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub28_dec31_dec_sub28_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub0_dec31_dec_sub0_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub26_dec31_dec_sub26_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub19_dec31_dec_sub19_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub22_dec31_dec_sub22_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub9_dec31_dec_sub9_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub11_dec31_dec_sub11_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub27_dec31_dec_sub27_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub15_dec31_dec_sub15_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub20_dec31_dec_sub20_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub21_dec31_dec_sub21_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub23_dec31_dec_sub23_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub16_dec31_dec_sub16_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub18_dec31_dec_sub18_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub8_dec31_dec_sub8_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub24_dec31_dec_sub24_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $1\dest2_o[3:0] \data_r1__cr_a + assign $1\dec31_is_32b[0:0] \dec31_dec_sub4_dec31_dec_sub4_is_32b case - assign $1\dest2_o[3:0] 4'0000 + assign $1\dec31_is_32b[0:0] 1'0 end sync always - update \dest2_o $0\dest2_o[3:0] + update \dec31_is_32b $0\dec31_is_32b[0:0] end - attribute \src "issuer_ls180.v:21705.3-21714.6" - process $proc$issuer_ls180.v:21705$711 + attribute \src "libresoc.v:17861.3-17921.6" + process $proc$libresoc.v:17861$363 assign { } { } assign { } { } - assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "issuer_ls180.v:21706.5-21706.29" + assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0] + attribute \src "libresoc.v:17862.5-17862.29" switch \initial - attribute \src "issuer_ls180.v:21706.9-21706.17" + attribute \src "libresoc.v:17862.9-17862.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$133 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $1\dest3_o[1:0] \data_r2__xer_ca + assign $1\dec31_sgn[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn case - assign $1\dest3_o[1:0] 2'00 + assign $1\dec31_sgn[0:0] 1'0 end sync always - update \dest3_o $0\dest3_o[1:0] + update \dec31_sgn $0\dec31_sgn[0:0] end - attribute \src "issuer_ls180.v:21715.3-21724.6" - process $proc$issuer_ls180.v:21715$712 + attribute \src "libresoc.v:17922.3-17982.6" + process $proc$libresoc.v:17922$364 assign { } { } assign { } { } - assign $0\dest4_o[1:0] $1\dest4_o[1:0] - attribute \src "issuer_ls180.v:21716.5-21716.29" + assign $0\dec31_lk[0:0] $1\dec31_lk[0:0] + attribute \src "libresoc.v:17923.5-17923.29" switch \initial - attribute \src "issuer_ls180.v:21716.9-21716.17" + attribute \src "libresoc.v:17923.9-17923.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$135 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub10_dec31_dec_sub10_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub28_dec31_dec_sub28_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub0_dec31_dec_sub0_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub26_dec31_dec_sub26_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub19_dec31_dec_sub19_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub22_dec31_dec_sub22_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub9_dec31_dec_sub9_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub11_dec31_dec_sub11_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 assign { } { } - assign $1\dest4_o[1:0] \data_r3__xer_ov + assign $1\dec31_lk[0:0] \dec31_dec_sub27_dec31_dec_sub27_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub15_dec31_dec_sub15_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub20_dec31_dec_sub20_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub21_dec31_dec_sub21_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub23_dec31_dec_sub23_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub16_dec31_dec_sub16_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub18_dec31_dec_sub18_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub8_dec31_dec_sub8_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub24_dec31_dec_sub24_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub4_dec31_dec_sub4_lk case - assign $1\dest4_o[1:0] 2'00 + assign $1\dec31_lk[0:0] 1'0 end sync always - update \dest4_o $0\dest4_o[1:0] + update \dec31_lk $0\dec31_lk[0:0] end - attribute \src "issuer_ls180.v:21725.3-21734.6" - process $proc$issuer_ls180.v:21725$713 + attribute \src "libresoc.v:17983.3-18043.6" + process $proc$libresoc.v:17983$365 assign { } { } assign { } { } - assign $0\dest5_o[0:0] $1\dest5_o[0:0] - attribute \src "issuer_ls180.v:21726.5-21726.29" + assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0] + attribute \src "libresoc.v:17984.5-17984.29" switch \initial - attribute \src "issuer_ls180.v:21726.9-21726.17" + attribute \src "libresoc.v:17984.9-17984.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$137 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } - assign $1\dest5_o[0:0] \data_r4__xer_so + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe case - assign $1\dest5_o[0:0] 1'0 + assign $1\dec31_sgl_pipe[0:0] 1'0 end sync always - update \dest5_o $0\dest5_o[0:0] + update \dec31_sgl_pipe $0\dec31_sgl_pipe[0:0] end - attribute \src "issuer_ls180.v:21735.3-21743.6" - process $proc$issuer_ls180.v:21735$714 - assign { } { } - assign { } { } - assign $0\prev_wr_go$next[4:0]$715 $1\prev_wr_go$next[4:0]$716 - attribute \src "issuer_ls180.v:21736.5-21736.29" - switch \initial - attribute \src "issuer_ls180.v:21736.9-21736.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\prev_wr_go$next[4:0]$716 5'00000 - case - assign $1\prev_wr_go$next[4:0]$716 \$21 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[4:0]$715 - end - connect \$5 $reduce_and$issuer_ls180.v:21129$463_Y - connect \$99 $and$issuer_ls180.v:21130$464_Y - connect \$101 $and$issuer_ls180.v:21131$465_Y - connect \$103 $and$issuer_ls180.v:21132$466_Y - connect \$105 $not$issuer_ls180.v:21133$467_Y - connect \$107 $not$issuer_ls180.v:21134$468_Y - connect \$109 $and$issuer_ls180.v:21135$469_Y - connect \$111 $not$issuer_ls180.v:21136$470_Y - connect \$113 $and$issuer_ls180.v:21137$471_Y - connect \$115 $and$issuer_ls180.v:21138$472_Y - connect \$117 $and$issuer_ls180.v:21139$473_Y - connect \$11 $and$issuer_ls180.v:21140$474_Y - connect \$119 $and$issuer_ls180.v:21141$475_Y - connect \$121 $and$issuer_ls180.v:21142$476_Y - connect \$123 $and$issuer_ls180.v:21143$477_Y - connect \$125 $and$issuer_ls180.v:21144$478_Y - connect \$127 $and$issuer_ls180.v:21145$479_Y - connect \$129 $and$issuer_ls180.v:21146$480_Y - connect \$131 $and$issuer_ls180.v:21147$481_Y - connect \$133 $and$issuer_ls180.v:21148$482_Y - connect \$135 $and$issuer_ls180.v:21149$483_Y - connect \$137 $and$issuer_ls180.v:21150$484_Y - connect \$13 $not$issuer_ls180.v:21151$485_Y - connect \$15 $and$issuer_ls180.v:21152$486_Y - connect \$17 $not$issuer_ls180.v:21153$487_Y - connect \$19 $and$issuer_ls180.v:21154$488_Y - connect \$21 $and$issuer_ls180.v:21155$489_Y - connect \$25 $not$issuer_ls180.v:21156$490_Y - connect \$27 $and$issuer_ls180.v:21157$491_Y - connect \$24 $reduce_or$issuer_ls180.v:21158$492_Y - connect \$23 $not$issuer_ls180.v:21159$493_Y - connect \$31 $and$issuer_ls180.v:21160$494_Y - connect \$33 $reduce_or$issuer_ls180.v:21161$495_Y - connect \$35 $reduce_or$issuer_ls180.v:21162$496_Y - connect \$37 $or$issuer_ls180.v:21163$497_Y - connect \$3 $and$issuer_ls180.v:21164$498_Y - connect \$39 $not$issuer_ls180.v:21165$499_Y - connect \$41 $and$issuer_ls180.v:21166$500_Y - connect \$43 $and$issuer_ls180.v:21167$501_Y - connect \$45 $eq$issuer_ls180.v:21168$502_Y - connect \$47 $and$issuer_ls180.v:21169$503_Y - connect \$49 $eq$issuer_ls180.v:21170$504_Y - connect \$51 $and$issuer_ls180.v:21171$505_Y - connect \$53 $and$issuer_ls180.v:21172$506_Y - connect \$55 $and$issuer_ls180.v:21173$507_Y - connect \$57 $or$issuer_ls180.v:21174$508_Y - connect \$59 $or$issuer_ls180.v:21175$509_Y - connect \$61 $or$issuer_ls180.v:21176$510_Y - connect \$63 $or$issuer_ls180.v:21177$511_Y - connect \$65 $and$issuer_ls180.v:21178$512_Y - connect \$67 $and$issuer_ls180.v:21179$513_Y - connect \$6 $not$issuer_ls180.v:21180$514_Y - connect \$69 $or$issuer_ls180.v:21181$515_Y - connect \$71 $and$issuer_ls180.v:21182$516_Y - connect \$73 $and$issuer_ls180.v:21183$517_Y - connect \$75 $and$issuer_ls180.v:21184$518_Y - connect \$77 $and$issuer_ls180.v:21185$519_Y - connect \$79 $and$issuer_ls180.v:21186$520_Y - connect \$81 $ternary$issuer_ls180.v:21187$521_Y - connect \$83 $ternary$issuer_ls180.v:21188$522_Y - connect \$86 $ternary$issuer_ls180.v:21189$523_Y - connect \$8 $or$issuer_ls180.v:21190$524_Y - connect \$89 $ternary$issuer_ls180.v:21191$525_Y - connect \$91 $ternary$issuer_ls180.v:21192$526_Y - connect \$93 $ternary$issuer_ls180.v:21193$527_Y - connect \$95 $ternary$issuer_ls180.v:21194$528_Y - connect \$97 $ternary$issuer_ls180.v:21195$529_Y - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 - connect \cu_wr__rel_o \$127 - connect \cu_rd__rel_o \$113 - connect \cu_busy_o \opc_l_q_opc - connect \alu_l_s_alu \all_rd_pulse - connect \alu_alu0_n_ready_i \alu_l_q_alu - connect \alui_l_s_alui \all_rd_pulse - connect \alu_alu0_p_valid_i \alui_l_q_alui - connect \alu_alu0_xer_ca$2 \$97 - connect \alu_alu0_xer_so$1 \$95 - connect \alu_alu0_rb \$93 - connect \alu_alu0_ra \$91 - connect \src_or_imm$88 \$89 - connect \src_sel$85 \$86 - connect \src_or_imm \$83 - connect \src_sel \$81 - connect \cu_wrmask_o { \$79 \$77 \$75 \$73 \$71 } - connect \reset_r \$63 - connect \reset_w \$61 - connect \rst_r \$59 - connect \reset \$57 - connect \wr_any \$37 - connect \cu_done_o \$31 - connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } - connect \alu_pulse \alu_done_rise - connect \alu_done_rise \$19 - connect \alu_done_dly$next \alu_done - connect \alu_done \alu_alu0_n_valid_o - connect \all_rd_pulse \all_rd_rise - connect \all_rd_rise \$15 - connect \all_rd_dly$next \all_rd - connect \all_rd \$11 + connect \dec31_dec_sub4_opcode_in \opcode_in + connect \dec31_dec_sub24_opcode_in \opcode_in + connect \dec31_dec_sub8_opcode_in \opcode_in + connect \dec31_dec_sub18_opcode_in \opcode_in + connect \dec31_dec_sub16_opcode_in \opcode_in + connect \dec31_dec_sub23_opcode_in \opcode_in + connect \dec31_dec_sub21_opcode_in \opcode_in + connect \dec31_dec_sub20_opcode_in \opcode_in + connect \dec31_dec_sub15_opcode_in \opcode_in + connect \dec31_dec_sub27_opcode_in \opcode_in + connect \dec31_dec_sub11_opcode_in \opcode_in + connect \dec31_dec_sub9_opcode_in \opcode_in + connect \dec31_dec_sub22_opcode_in \opcode_in + connect \dec31_dec_sub19_opcode_in \opcode_in + connect \dec31_dec_sub26_opcode_in \opcode_in + connect \dec31_dec_sub0_opcode_in \opcode_in + connect \dec31_dec_sub28_opcode_in \opcode_in + connect \dec31_dec_sub10_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] end -attribute \src "issuer_ls180.v:21781.1-22841.10" +attribute \src "libresoc.v:18068.1-18783.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub0" attribute \generator "nMigen" -module \alu_alu0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 25 \alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$70 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 10 \alu_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_op__fn_unit$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 11 \alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__data$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__imm_data__ok$57 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 21 \alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 26 \alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$71 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 9 \alu_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_in$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_out$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 23 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_32bit$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 24 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_signed$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__oe$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__ok$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 22 \alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__output_carry$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__ok$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__rc$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__write_cr0$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__zero_a$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 38 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 6 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 28 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$53 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 8 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 7 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 27 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 37 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 36 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe1_alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe1_alu_op__data_len$20 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe1_alu_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe1_alu_op__fn_unit$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe1_alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe1_alu_op__imm_data__data$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__imm_data__ok$7 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe1_alu_op__input_carry +module \dec31_dec_sub0 + attribute \src "libresoc.v:18421.3-18439.6" + wire width 8 $0\dec31_dec_sub0_asmcode[7:0] + attribute \src "libresoc.v:18497.3-18515.6" + wire $0\dec31_dec_sub0_br[0:0] + attribute \src "libresoc.v:18744.3-18762.6" + wire width 3 $0\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:18763.3-18781.6" + wire width 3 $0\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:18402.3-18420.6" + wire width 2 $0\dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:18478.3-18496.6" + wire $0\dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:18649.3-18667.6" + wire width 5 $0\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:18326.3-18344.6" + wire width 12 $0\dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:18668.3-18686.6" + wire width 3 $0\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:18687.3-18705.6" + wire width 4 $0\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:18706.3-18724.6" + wire width 2 $0\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:18535.3-18553.6" + wire width 7 $0\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:18440.3-18458.6" + wire $0\dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:18459.3-18477.6" + wire $0\dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:18573.3-18591.6" + wire $0\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:18345.3-18363.6" + wire width 4 $0\dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:18611.3-18629.6" + wire $0\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:18725.3-18743.6" + wire width 2 $0\dec31_dec_sub0_out_sel[1:0] + attribute \src "libresoc.v:18383.3-18401.6" + wire width 2 $0\dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:18554.3-18572.6" + wire $0\dec31_dec_sub0_rsrv[0:0] + attribute \src "libresoc.v:18630.3-18648.6" + wire $0\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:18592.3-18610.6" + wire $0\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:18516.3-18534.6" + wire $0\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "libresoc.v:18364.3-18382.6" + wire width 2 $0\dec31_dec_sub0_upd[1:0] + attribute \src "libresoc.v:18069.7-18069.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:18421.3-18439.6" + wire width 8 $1\dec31_dec_sub0_asmcode[7:0] + attribute \src "libresoc.v:18497.3-18515.6" + wire $1\dec31_dec_sub0_br[0:0] + attribute \src "libresoc.v:18744.3-18762.6" + wire width 3 $1\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:18763.3-18781.6" + wire width 3 $1\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:18402.3-18420.6" + wire width 2 $1\dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:18478.3-18496.6" + wire $1\dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:18649.3-18667.6" + wire width 5 $1\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:18326.3-18344.6" + wire width 12 $1\dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:18668.3-18686.6" + wire width 3 $1\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:18687.3-18705.6" + wire width 4 $1\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:18706.3-18724.6" + wire width 2 $1\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:18535.3-18553.6" + wire width 7 $1\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:18440.3-18458.6" + wire $1\dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:18459.3-18477.6" + wire $1\dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:18573.3-18591.6" + wire $1\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:18345.3-18363.6" + wire width 4 $1\dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:18611.3-18629.6" + wire $1\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:18725.3-18743.6" + wire width 2 $1\dec31_dec_sub0_out_sel[1:0] + attribute \src "libresoc.v:18383.3-18401.6" + wire width 2 $1\dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:18554.3-18572.6" + wire $1\dec31_dec_sub0_rsrv[0:0] + attribute \src "libresoc.v:18630.3-18648.6" + wire $1\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:18592.3-18610.6" + wire $1\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:18516.3-18534.6" + wire $1\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "libresoc.v:18364.3-18382.6" + wire width 2 $1\dec31_dec_sub0_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub0_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub0_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub0_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe1_alu_op__input_carry$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe1_alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe1_alu_op__insn$21 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe1_alu_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe1_alu_op__insn_type$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__invert_in$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__invert_out$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__is_32bit$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__is_signed$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__oe__oe$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__oe__ok$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__output_carry$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__rc__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__rc__rc$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__write_cr0$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__zero_a$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \pipe1_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe1_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe1_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe1_muxid$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \pipe1_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \pipe1_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe1_o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \pipe1_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \pipe1_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe1_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe1_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe1_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \pipe1_xer_ca$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe1_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe1_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe1_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe1_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \pipe1_xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe1_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe2_alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe2_alu_op__data_len$41 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe2_alu_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub0_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub0_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -34054,108 +25129,39 @@ module \alu_alu0 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe2_alu_op__fn_unit$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe2_alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe2_alu_op__imm_data__data$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__imm_data__ok$28 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe2_alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe2_alu_op__input_carry$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe2_alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe2_alu_op__insn$42 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe2_alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub0_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub0_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub0_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub0_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -34230,1092 +25236,1073 @@ module \alu_alu0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe2_alu_op__insn_type$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__invert_in$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__invert_out$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__is_32bit$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__is_signed$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__oe__oe$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__oe__ok$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__output_carry$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__rc__ok$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__rc__rc$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__write_cr0$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__zero_a$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \pipe2_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \pipe2_cr_a$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe2_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe2_cr_a_ok$46 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe2_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe2_muxid$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \pipe2_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \pipe2_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe2_o$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe2_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe2_o_ok$44 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \pipe2_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \pipe2_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe2_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe2_xer_ca$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe2_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe2_xer_ca_ok$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe2_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe2_xer_ov$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe2_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe2_xer_ov_ok$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe2_xer_so$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe2_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe2_xer_so_ok$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 32 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 33 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 29 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 35 \xer_ca$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 30 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 4 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 31 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 34 \xer_so$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 5 \xer_so_ok - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:22680.5-22683.4" - cell \n \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub0_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub0_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub0_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub0_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub0_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub0_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub0_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub0_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub0_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub0_upd + attribute \src "libresoc.v:18069.7-18069.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:18069.7-18069.20" + process $proc$libresoc.v:18069$391 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:22684.5-22687.4" - cell \p \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i + attribute \src "libresoc.v:18326.3-18344.6" + process $proc$libresoc.v:18326$367 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_function_unit[11:0] $1\dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:18327.5-18327.29" + switch \initial + attribute \src "libresoc.v:18327.9-18327.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000001000000 + case + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[11:0] end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:22688.9-22747.4" - cell \pipe1 \pipe1 - connect \alu_op__data_len \pipe1_alu_op__data_len - connect \alu_op__data_len$18 \pipe1_alu_op__data_len$20 - connect \alu_op__fn_unit \pipe1_alu_op__fn_unit - connect \alu_op__fn_unit$3 \pipe1_alu_op__fn_unit$5 - connect \alu_op__imm_data__data \pipe1_alu_op__imm_data__data - connect \alu_op__imm_data__data$4 \pipe1_alu_op__imm_data__data$6 - connect \alu_op__imm_data__ok \pipe1_alu_op__imm_data__ok - connect \alu_op__imm_data__ok$5 \pipe1_alu_op__imm_data__ok$7 - connect \alu_op__input_carry \pipe1_alu_op__input_carry - connect \alu_op__input_carry$14 \pipe1_alu_op__input_carry$16 - connect \alu_op__insn \pipe1_alu_op__insn - connect \alu_op__insn$19 \pipe1_alu_op__insn$21 - connect \alu_op__insn_type \pipe1_alu_op__insn_type - connect \alu_op__insn_type$2 \pipe1_alu_op__insn_type$4 - connect \alu_op__invert_in \pipe1_alu_op__invert_in - connect \alu_op__invert_in$10 \pipe1_alu_op__invert_in$12 - connect \alu_op__invert_out \pipe1_alu_op__invert_out - connect \alu_op__invert_out$12 \pipe1_alu_op__invert_out$14 - connect \alu_op__is_32bit \pipe1_alu_op__is_32bit - connect \alu_op__is_32bit$16 \pipe1_alu_op__is_32bit$18 - connect \alu_op__is_signed \pipe1_alu_op__is_signed - connect \alu_op__is_signed$17 \pipe1_alu_op__is_signed$19 - connect \alu_op__oe__oe \pipe1_alu_op__oe__oe - connect \alu_op__oe__oe$8 \pipe1_alu_op__oe__oe$10 - connect \alu_op__oe__ok \pipe1_alu_op__oe__ok - connect \alu_op__oe__ok$9 \pipe1_alu_op__oe__ok$11 - connect \alu_op__output_carry \pipe1_alu_op__output_carry - connect \alu_op__output_carry$15 \pipe1_alu_op__output_carry$17 - connect \alu_op__rc__ok \pipe1_alu_op__rc__ok - connect \alu_op__rc__ok$7 \pipe1_alu_op__rc__ok$9 - connect \alu_op__rc__rc \pipe1_alu_op__rc__rc - connect \alu_op__rc__rc$6 \pipe1_alu_op__rc__rc$8 - connect \alu_op__write_cr0 \pipe1_alu_op__write_cr0 - connect \alu_op__write_cr0$13 \pipe1_alu_op__write_cr0$15 - connect \alu_op__zero_a \pipe1_alu_op__zero_a - connect \alu_op__zero_a$11 \pipe1_alu_op__zero_a$13 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \pipe1_cr_a - connect \cr_a_ok \pipe1_cr_a_ok - connect \muxid \pipe1_muxid - connect \muxid$1 \pipe1_muxid$3 - connect \n_ready_i \pipe1_n_ready_i - connect \n_valid_o \pipe1_n_valid_o - connect \o \pipe1_o - connect \o_ok \pipe1_o_ok - connect \p_ready_o \pipe1_p_ready_o - connect \p_valid_i \pipe1_p_valid_i - connect \ra \pipe1_ra - connect \rb \pipe1_rb - connect \xer_ca \pipe1_xer_ca - connect \xer_ca$21 \pipe1_xer_ca$23 - connect \xer_ca_ok \pipe1_xer_ca_ok - connect \xer_ov \pipe1_xer_ov - connect \xer_ov_ok \pipe1_xer_ov_ok - connect \xer_so \pipe1_xer_so - connect \xer_so$20 \pipe1_xer_so$22 - connect \xer_so_ok \pipe1_xer_so_ok + attribute \src "libresoc.v:18345.3-18363.6" + process $proc$libresoc.v:18345$368 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:18346.5-18346.29" + switch \initial + attribute \src "libresoc.v:18346.9-18346.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0] end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:22748.9-22813.4" - cell \pipe2 \pipe2 - connect \alu_op__data_len \pipe2_alu_op__data_len - connect \alu_op__data_len$18 \pipe2_alu_op__data_len$41 - connect \alu_op__fn_unit \pipe2_alu_op__fn_unit - connect \alu_op__fn_unit$3 \pipe2_alu_op__fn_unit$26 - connect \alu_op__imm_data__data \pipe2_alu_op__imm_data__data - connect \alu_op__imm_data__data$4 \pipe2_alu_op__imm_data__data$27 - connect \alu_op__imm_data__ok \pipe2_alu_op__imm_data__ok - connect \alu_op__imm_data__ok$5 \pipe2_alu_op__imm_data__ok$28 - connect \alu_op__input_carry \pipe2_alu_op__input_carry - connect \alu_op__input_carry$14 \pipe2_alu_op__input_carry$37 - connect \alu_op__insn \pipe2_alu_op__insn - connect \alu_op__insn$19 \pipe2_alu_op__insn$42 - connect \alu_op__insn_type \pipe2_alu_op__insn_type - connect \alu_op__insn_type$2 \pipe2_alu_op__insn_type$25 - connect \alu_op__invert_in \pipe2_alu_op__invert_in - connect \alu_op__invert_in$10 \pipe2_alu_op__invert_in$33 - connect \alu_op__invert_out \pipe2_alu_op__invert_out - connect \alu_op__invert_out$12 \pipe2_alu_op__invert_out$35 - connect \alu_op__is_32bit \pipe2_alu_op__is_32bit - connect \alu_op__is_32bit$16 \pipe2_alu_op__is_32bit$39 - connect \alu_op__is_signed \pipe2_alu_op__is_signed - connect \alu_op__is_signed$17 \pipe2_alu_op__is_signed$40 - connect \alu_op__oe__oe \pipe2_alu_op__oe__oe - connect \alu_op__oe__oe$8 \pipe2_alu_op__oe__oe$31 - connect \alu_op__oe__ok \pipe2_alu_op__oe__ok - connect \alu_op__oe__ok$9 \pipe2_alu_op__oe__ok$32 - connect \alu_op__output_carry \pipe2_alu_op__output_carry - connect \alu_op__output_carry$15 \pipe2_alu_op__output_carry$38 - connect \alu_op__rc__ok \pipe2_alu_op__rc__ok - connect \alu_op__rc__ok$7 \pipe2_alu_op__rc__ok$30 - connect \alu_op__rc__rc \pipe2_alu_op__rc__rc - connect \alu_op__rc__rc$6 \pipe2_alu_op__rc__rc$29 - connect \alu_op__write_cr0 \pipe2_alu_op__write_cr0 - connect \alu_op__write_cr0$13 \pipe2_alu_op__write_cr0$36 - connect \alu_op__zero_a \pipe2_alu_op__zero_a - connect \alu_op__zero_a$11 \pipe2_alu_op__zero_a$34 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \pipe2_cr_a - connect \cr_a$22 \pipe2_cr_a$45 - connect \cr_a_ok \pipe2_cr_a_ok - connect \cr_a_ok$23 \pipe2_cr_a_ok$46 - connect \muxid \pipe2_muxid - connect \muxid$1 \pipe2_muxid$24 - connect \n_ready_i \pipe2_n_ready_i - connect \n_valid_o \pipe2_n_valid_o - connect \o \pipe2_o - connect \o$20 \pipe2_o$43 - connect \o_ok \pipe2_o_ok - connect \o_ok$21 \pipe2_o_ok$44 - connect \p_ready_o \pipe2_p_ready_o - connect \p_valid_i \pipe2_p_valid_i - connect \xer_ca \pipe2_xer_ca - connect \xer_ca$24 \pipe2_xer_ca$47 - connect \xer_ca_ok \pipe2_xer_ca_ok - connect \xer_ca_ok$25 \pipe2_xer_ca_ok$48 - connect \xer_ov \pipe2_xer_ov - connect \xer_ov$26 \pipe2_xer_ov$49 - connect \xer_ov_ok \pipe2_xer_ov_ok - connect \xer_ov_ok$27 \pipe2_xer_ov_ok$50 - connect \xer_so \pipe2_xer_so - connect \xer_so$28 \pipe2_xer_so$51 - connect \xer_so_ok \pipe2_xer_so_ok - connect \xer_so_ok$29 \pipe2_xer_so_ok$52 - end - connect \muxid 2'00 - connect { \xer_so_ok \xer_so } { \pipe2_xer_so_ok$52 \pipe2_xer_so$51 } - connect { \xer_ov_ok \xer_ov } { \pipe2_xer_ov_ok$50 \pipe2_xer_ov$49 } - connect { \xer_ca_ok \xer_ca } { \pipe2_xer_ca_ok$48 \pipe2_xer_ca$47 } - connect { \cr_a_ok \cr_a } { \pipe2_cr_a_ok$46 \pipe2_cr_a$45 } - connect { \o_ok \o } { \pipe2_o_ok$44 \pipe2_o$43 } - connect { \alu_op__insn$71 \alu_op__data_len$70 \alu_op__is_signed$69 \alu_op__is_32bit$68 \alu_op__output_carry$67 \alu_op__input_carry$66 \alu_op__write_cr0$65 \alu_op__invert_out$64 \alu_op__zero_a$63 \alu_op__invert_in$62 \alu_op__oe__ok$61 \alu_op__oe__oe$60 \alu_op__rc__ok$59 \alu_op__rc__rc$58 \alu_op__imm_data__ok$57 \alu_op__imm_data__data$56 \alu_op__fn_unit$55 \alu_op__insn_type$54 } { \pipe2_alu_op__insn$42 \pipe2_alu_op__data_len$41 \pipe2_alu_op__is_signed$40 \pipe2_alu_op__is_32bit$39 \pipe2_alu_op__output_carry$38 \pipe2_alu_op__input_carry$37 \pipe2_alu_op__write_cr0$36 \pipe2_alu_op__invert_out$35 \pipe2_alu_op__zero_a$34 \pipe2_alu_op__invert_in$33 \pipe2_alu_op__oe__ok$32 \pipe2_alu_op__oe__oe$31 \pipe2_alu_op__rc__ok$30 \pipe2_alu_op__rc__rc$29 \pipe2_alu_op__imm_data__ok$28 \pipe2_alu_op__imm_data__data$27 \pipe2_alu_op__fn_unit$26 \pipe2_alu_op__insn_type$25 } - connect \muxid$53 \pipe2_muxid$24 - connect \pipe2_n_ready_i \n_ready_i - connect \n_valid_o \pipe2_n_valid_o - connect \pipe1_xer_ca$23 \xer_ca$2 - connect \pipe1_xer_so$22 \xer_so$1 - connect \pipe1_rb \rb - connect \pipe1_ra \ra - connect { \pipe1_alu_op__insn$21 \pipe1_alu_op__data_len$20 \pipe1_alu_op__is_signed$19 \pipe1_alu_op__is_32bit$18 \pipe1_alu_op__output_carry$17 \pipe1_alu_op__input_carry$16 \pipe1_alu_op__write_cr0$15 \pipe1_alu_op__invert_out$14 \pipe1_alu_op__zero_a$13 \pipe1_alu_op__invert_in$12 \pipe1_alu_op__oe__ok$11 \pipe1_alu_op__oe__oe$10 \pipe1_alu_op__rc__ok$9 \pipe1_alu_op__rc__rc$8 \pipe1_alu_op__imm_data__ok$7 \pipe1_alu_op__imm_data__data$6 \pipe1_alu_op__fn_unit$5 \pipe1_alu_op__insn_type$4 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } - connect \pipe1_muxid$3 2'00 - connect \p_ready_o \pipe1_p_ready_o - connect \pipe1_p_valid_i \p_valid_i - connect { \pipe2_xer_so_ok \pipe2_xer_so } { \pipe1_xer_so_ok \pipe1_xer_so } - connect { \pipe2_xer_ov_ok \pipe2_xer_ov } { \pipe1_xer_ov_ok \pipe1_xer_ov } - connect { \pipe2_xer_ca_ok \pipe2_xer_ca } { \pipe1_xer_ca_ok \pipe1_xer_ca } - connect { \pipe2_cr_a_ok \pipe2_cr_a } { \pipe1_cr_a_ok \pipe1_cr_a } - connect { \pipe2_o_ok \pipe2_o } { \pipe1_o_ok \pipe1_o } - connect { \pipe2_alu_op__insn \pipe2_alu_op__data_len \pipe2_alu_op__is_signed \pipe2_alu_op__is_32bit \pipe2_alu_op__output_carry \pipe2_alu_op__input_carry \pipe2_alu_op__write_cr0 \pipe2_alu_op__invert_out \pipe2_alu_op__zero_a \pipe2_alu_op__invert_in \pipe2_alu_op__oe__ok \pipe2_alu_op__oe__oe \pipe2_alu_op__rc__ok \pipe2_alu_op__rc__rc \pipe2_alu_op__imm_data__ok \pipe2_alu_op__imm_data__data \pipe2_alu_op__fn_unit \pipe2_alu_op__insn_type } { \pipe1_alu_op__insn \pipe1_alu_op__data_len \pipe1_alu_op__is_signed \pipe1_alu_op__is_32bit \pipe1_alu_op__output_carry \pipe1_alu_op__input_carry \pipe1_alu_op__write_cr0 \pipe1_alu_op__invert_out \pipe1_alu_op__zero_a \pipe1_alu_op__invert_in \pipe1_alu_op__oe__ok \pipe1_alu_op__oe__oe \pipe1_alu_op__rc__ok \pipe1_alu_op__rc__rc \pipe1_alu_op__imm_data__ok \pipe1_alu_op__imm_data__data \pipe1_alu_op__fn_unit \pipe1_alu_op__insn_type } - connect \pipe2_muxid \pipe1_muxid - connect \pipe1_n_ready_i \pipe2_p_ready_o - connect \pipe2_p_valid_i \pipe1_n_valid_o -end -attribute \src "issuer_ls180.v:22845.1-23380.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0" -attribute \generator "nMigen" -module \alu_branch0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \br_op__cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \br_op__cia$15 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 9 \br_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \br_op__fn_unit$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 11 \br_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \br_op__imm_data__data$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \br_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \br_op__imm_data__ok$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 10 \br_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \br_op__insn$18 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe_fast2_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \pipe_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \pipe_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe_nia_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \pipe_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \pipe_p_valid_i - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:23322.10-23325.4" - cell \n$18 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o + attribute \src "libresoc.v:18364.3-18382.6" + process $proc$libresoc.v:18364$369 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0] + attribute \src "libresoc.v:18365.5-18365.29" + switch \initial + attribute \src "libresoc.v:18365.9-18365.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0] end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:23326.10-23329.4" - cell \p$17 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i + attribute \src "libresoc.v:18383.3-18401.6" + process $proc$libresoc.v:18383$370 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:18384.5-18384.29" + switch \initial + attribute \src "libresoc.v:18384.9-18384.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0] end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:23330.13-23364.4" - cell \pipe$19 \pipe - connect \br_op__cia \pipe_br_op__cia - connect \br_op__cia$2 \pipe_br_op__cia$4 - connect \br_op__fn_unit \pipe_br_op__fn_unit - connect \br_op__fn_unit$4 \pipe_br_op__fn_unit$6 - connect \br_op__imm_data__data \pipe_br_op__imm_data__data - connect \br_op__imm_data__data$6 \pipe_br_op__imm_data__data$8 - connect \br_op__imm_data__ok \pipe_br_op__imm_data__ok - connect \br_op__imm_data__ok$7 \pipe_br_op__imm_data__ok$9 - connect \br_op__insn \pipe_br_op__insn - connect \br_op__insn$5 \pipe_br_op__insn$7 - connect \br_op__insn_type \pipe_br_op__insn_type - connect \br_op__insn_type$3 \pipe_br_op__insn_type$5 - connect \br_op__is_32bit \pipe_br_op__is_32bit - connect \br_op__is_32bit$9 \pipe_br_op__is_32bit$11 - connect \br_op__lk \pipe_br_op__lk - connect \br_op__lk$8 \pipe_br_op__lk$10 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \pipe_cr_a - connect \fast1 \pipe_fast1 - connect \fast1$10 \pipe_fast1$12 - connect \fast1_ok \pipe_fast1_ok - connect \fast2 \pipe_fast2 - connect \fast2$11 \pipe_fast2$13 - connect \fast2_ok \pipe_fast2_ok - connect \muxid \pipe_muxid - connect \muxid$1 \pipe_muxid$3 - connect \n_ready_i \pipe_n_ready_i - connect \n_valid_o \pipe_n_valid_o - connect \nia \pipe_nia - connect \nia_ok \pipe_nia_ok - connect \p_ready_o \pipe_p_ready_o - connect \p_valid_i \pipe_p_valid_i - end - connect \muxid 2'00 - connect { \nia_ok \nia } { \pipe_nia_ok \pipe_nia } - connect { \fast2_ok \fast2 } { \pipe_fast2_ok \pipe_fast2$13 } - connect { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } - connect { \br_op__is_32bit$22 \br_op__lk$21 \br_op__imm_data__ok$20 \br_op__imm_data__data$19 \br_op__insn$18 \br_op__fn_unit$17 \br_op__insn_type$16 \br_op__cia$15 } { \pipe_br_op__is_32bit$11 \pipe_br_op__lk$10 \pipe_br_op__imm_data__ok$9 \pipe_br_op__imm_data__data$8 \pipe_br_op__insn$7 \pipe_br_op__fn_unit$6 \pipe_br_op__insn_type$5 \pipe_br_op__cia$4 } - connect \muxid$14 \pipe_muxid$3 - connect \pipe_n_ready_i \n_ready_i - connect \n_valid_o \pipe_n_valid_o - connect \pipe_cr_a \cr_a - connect \pipe_fast2 \fast2$2 - connect \pipe_fast1 \fast1$1 - connect { \pipe_br_op__is_32bit \pipe_br_op__lk \pipe_br_op__imm_data__ok \pipe_br_op__imm_data__data \pipe_br_op__insn \pipe_br_op__fn_unit \pipe_br_op__insn_type \pipe_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } - connect \pipe_muxid 2'00 - connect \p_ready_o \pipe_p_ready_o - connect \pipe_p_valid_i \p_valid_i + attribute \src "libresoc.v:18402.3-18420.6" + process $proc$libresoc.v:18402$371 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:18403.5-18403.29" + switch \initial + attribute \src "libresoc.v:18403.9-18403.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0] + end + attribute \src "libresoc.v:18421.3-18439.6" + process $proc$libresoc.v:18421$372 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0] + attribute \src "libresoc.v:18422.5-18422.29" + switch \initial + attribute \src "libresoc.v:18422.9-18422.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'10011011 + case + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0] + end + attribute \src "libresoc.v:18440.3-18458.6" + process $proc$libresoc.v:18440$373 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:18441.5-18441.29" + switch \initial + attribute \src "libresoc.v:18441.9-18441.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0] + end + attribute \src "libresoc.v:18459.3-18477.6" + process $proc$libresoc.v:18459$374 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:18460.5-18460.29" + switch \initial + attribute \src "libresoc.v:18460.9-18460.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0] + end + attribute \src "libresoc.v:18478.3-18496.6" + process $proc$libresoc.v:18478$375 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:18479.5-18479.29" + switch \initial + attribute \src "libresoc.v:18479.9-18479.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0] + end + attribute \src "libresoc.v:18497.3-18515.6" + process $proc$libresoc.v:18497$376 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0] + attribute \src "libresoc.v:18498.5-18498.29" + switch \initial + attribute \src "libresoc.v:18498.9-18498.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + case + assign $1\dec31_dec_sub0_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0] + end + attribute \src "libresoc.v:18516.3-18534.6" + process $proc$libresoc.v:18516$377 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "libresoc.v:18517.5-18517.29" + switch \initial + attribute \src "libresoc.v:18517.9-18517.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0] + end + attribute \src "libresoc.v:18535.3-18553.6" + process $proc$libresoc.v:18535$378 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:18536.5-18536.29" + switch \initial + attribute \src "libresoc.v:18536.9-18536.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0111011 + case + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] + end + attribute \src "libresoc.v:18554.3-18572.6" + process $proc$libresoc.v:18554$379 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0] + attribute \src "libresoc.v:18555.5-18555.29" + switch \initial + attribute \src "libresoc.v:18555.9-18555.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0] + end + attribute \src "libresoc.v:18573.3-18591.6" + process $proc$libresoc.v:18573$380 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:18574.5-18574.29" + switch \initial + attribute \src "libresoc.v:18574.9-18574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] + end + attribute \src "libresoc.v:18592.3-18610.6" + process $proc$libresoc.v:18592$381 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:18593.5-18593.29" + switch \initial + attribute \src "libresoc.v:18593.9-18593.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0] + end + attribute \src "libresoc.v:18611.3-18629.6" + process $proc$libresoc.v:18611$382 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:18612.5-18612.29" + switch \initial + attribute \src "libresoc.v:18612.9-18612.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0] + end + attribute \src "libresoc.v:18630.3-18648.6" + process $proc$libresoc.v:18630$383 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:18631.5-18631.29" + switch \initial + attribute \src "libresoc.v:18631.9-18631.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0] + end + attribute \src "libresoc.v:18649.3-18667.6" + process $proc$libresoc.v:18649$384 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:18650.5-18650.29" + switch \initial + attribute \src "libresoc.v:18650.9-18650.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'11000 + case + assign $1\dec31_dec_sub0_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] + end + attribute \src "libresoc.v:18668.3-18686.6" + process $proc$libresoc.v:18668$385 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:18669.5-18669.29" + switch \initial + attribute \src "libresoc.v:18669.9-18669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0] + end + attribute \src "libresoc.v:18687.3-18705.6" + process $proc$libresoc.v:18687$386 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:18688.5-18688.29" + switch \initial + attribute \src "libresoc.v:18688.9-18688.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0] + end + attribute \src "libresoc.v:18706.3-18724.6" + process $proc$libresoc.v:18706$387 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:18707.5-18707.29" + switch \initial + attribute \src "libresoc.v:18707.9-18707.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0] + end + attribute \src "libresoc.v:18725.3-18743.6" + process $proc$libresoc.v:18725$388 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_out_sel[1:0] $1\dec31_dec_sub0_out_sel[1:0] + attribute \src "libresoc.v:18726.5-18726.29" + switch \initial + attribute \src "libresoc.v:18726.9-18726.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_out_sel $0\dec31_dec_sub0_out_sel[1:0] + end + attribute \src "libresoc.v:18744.3-18762.6" + process $proc$libresoc.v:18744$389 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:18745.5-18745.29" + switch \initial + attribute \src "libresoc.v:18745.9-18745.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'011 + case + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0] + end + attribute \src "libresoc.v:18763.3-18781.6" + process $proc$libresoc.v:18763$390 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:18764.5-18764.29" + switch \initial + attribute \src "libresoc.v:18764.9-18764.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] end -attribute \src "issuer_ls180.v:23384.1-23887.10" +attribute \src "libresoc.v:18787.1-19934.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub10" attribute \generator "nMigen" -module \alu_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 21 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 4 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 12 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 16 \cr_a$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 17 \cr_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 18 \cr_c - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 8 \cr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \cr_op__fn_unit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 9 \cr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \cr_op__insn$12 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 7 \cr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \cr_op__insn_type$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 output 11 \full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 input 15 \full_cr$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \full_cr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 6 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 5 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 10 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 20 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 19 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \pipe_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \pipe_cr_a$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \pipe_cr_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \pipe_cr_c - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_cr_op__fn_unit +module \dec31_dec_sub10 + attribute \src "libresoc.v:19230.3-19266.6" + wire width 8 $0\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:19378.3-19414.6" + wire $0\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:19859.3-19895.6" + wire width 3 $0\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:19896.3-19932.6" + wire width 3 $0\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:19193.3-19229.6" + wire width 2 $0\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:19341.3-19377.6" + wire $0\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:19674.3-19710.6" + wire width 5 $0\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:19045.3-19081.6" + wire width 12 $0\dec31_dec_sub10_function_unit[11:0] + attribute \src "libresoc.v:19711.3-19747.6" + wire width 3 $0\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:19748.3-19784.6" + wire width 4 $0\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:19785.3-19821.6" + wire width 2 $0\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:19452.3-19488.6" + wire width 7 $0\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:19267.3-19303.6" + wire $0\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:19304.3-19340.6" + wire $0\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:19526.3-19562.6" + wire $0\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:19082.3-19118.6" + wire width 4 $0\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:19600.3-19636.6" + wire $0\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:19822.3-19858.6" + wire width 2 $0\dec31_dec_sub10_out_sel[1:0] + attribute \src "libresoc.v:19156.3-19192.6" + wire width 2 $0\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:19489.3-19525.6" + wire $0\dec31_dec_sub10_rsrv[0:0] + attribute \src "libresoc.v:19637.3-19673.6" + wire $0\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:19563.3-19599.6" + wire $0\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:19415.3-19451.6" + wire $0\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:19119.3-19155.6" + wire width 2 $0\dec31_dec_sub10_upd[1:0] + attribute \src "libresoc.v:18788.7-18788.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:19230.3-19266.6" + wire width 8 $1\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:19378.3-19414.6" + wire $1\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:19859.3-19895.6" + wire width 3 $1\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:19896.3-19932.6" + wire width 3 $1\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:19193.3-19229.6" + wire width 2 $1\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:19341.3-19377.6" + wire $1\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:19674.3-19710.6" + wire width 5 $1\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:19045.3-19081.6" + wire width 12 $1\dec31_dec_sub10_function_unit[11:0] + attribute \src "libresoc.v:19711.3-19747.6" + wire width 3 $1\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:19748.3-19784.6" + wire width 4 $1\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:19785.3-19821.6" + wire width 2 $1\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:19452.3-19488.6" + wire width 7 $1\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:19267.3-19303.6" + wire $1\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:19304.3-19340.6" + wire $1\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:19526.3-19562.6" + wire $1\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:19082.3-19118.6" + wire width 4 $1\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:19600.3-19636.6" + wire $1\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:19822.3-19858.6" + wire width 2 $1\dec31_dec_sub10_out_sel[1:0] + attribute \src "libresoc.v:19156.3-19192.6" + wire width 2 $1\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:19489.3-19525.6" + wire $1\dec31_dec_sub10_rsrv[0:0] + attribute \src "libresoc.v:19637.3-19673.6" + wire $1\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:19563.3-19599.6" + wire $1\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:19415.3-19451.6" + wire $1\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:19119.3-19155.6" + wire width 2 $1\dec31_dec_sub10_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub10_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub10_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub10_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub10_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub10_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub10_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -35329,12 +26316,39 @@ module \alu_cr0 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_cr_op__fn_unit$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_cr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_cr_op__insn$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub10_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub10_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub10_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub10_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -35409,3961 +26423,1649 @@ module \alu_cr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_cr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_cr_op__insn_type$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 \pipe_full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 \pipe_full_cr$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe_full_cr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \pipe_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \pipe_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe_o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \pipe_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \pipe_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 13 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 14 \rb - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:23833.9-23836.4" - cell \n$6 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:23837.9-23840.4" - cell \p$5 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:23841.8-23868.4" - cell \pipe \pipe - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \pipe_cr_a - connect \cr_a$6 \pipe_cr_a$8 - connect \cr_a_ok \pipe_cr_a_ok - connect \cr_b \pipe_cr_b - connect \cr_c \pipe_cr_c - connect \cr_op__fn_unit \pipe_cr_op__fn_unit - connect \cr_op__fn_unit$3 \pipe_cr_op__fn_unit$5 - connect \cr_op__insn \pipe_cr_op__insn - connect \cr_op__insn$4 \pipe_cr_op__insn$6 - connect \cr_op__insn_type \pipe_cr_op__insn_type - connect \cr_op__insn_type$2 \pipe_cr_op__insn_type$4 - connect \full_cr \pipe_full_cr - connect \full_cr$5 \pipe_full_cr$7 - connect \full_cr_ok \pipe_full_cr_ok - connect \muxid \pipe_muxid - connect \muxid$1 \pipe_muxid$3 - connect \n_ready_i \pipe_n_ready_i - connect \n_valid_o \pipe_n_valid_o - connect \o \pipe_o - connect \o_ok \pipe_o_ok - connect \p_ready_o \pipe_p_ready_o - connect \p_valid_i \pipe_p_valid_i - connect \ra \pipe_ra - connect \rb \pipe_rb - end - connect \muxid 2'00 - connect { \cr_a_ok \cr_a } { \pipe_cr_a_ok \pipe_cr_a$8 } - connect { \full_cr_ok \full_cr } { \pipe_full_cr_ok \pipe_full_cr$7 } - connect { \o_ok \o } { \pipe_o_ok \pipe_o } - connect { \cr_op__insn$12 \cr_op__fn_unit$11 \cr_op__insn_type$10 } { \pipe_cr_op__insn$6 \pipe_cr_op__fn_unit$5 \pipe_cr_op__insn_type$4 } - connect \muxid$9 \pipe_muxid$3 - connect \pipe_n_ready_i \n_ready_i - connect \n_valid_o \pipe_n_valid_o - connect \pipe_cr_c \cr_c - connect \pipe_cr_b \cr_b - connect \pipe_cr_a \cr_a$2 - connect \pipe_full_cr \full_cr$1 - connect \pipe_rb \rb - connect \pipe_ra \ra - connect { \pipe_cr_op__insn \pipe_cr_op__fn_unit \pipe_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } - connect \pipe_muxid 2'00 - connect \p_ready_o \pipe_p_ready_o - connect \pipe_p_valid_i \p_valid_i -end -attribute \src "issuer_ls180.v:23891.1-25332.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0" -attribute \generator "nMigen" -module \alu_div0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 35 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 27 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 24 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$88 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 9 \logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 10 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$75 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 18 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 25 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$89 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 8 \logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 22 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 23 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 21 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$71 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 7 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 6 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 26 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 34 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 33 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \pipe_end_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe_end_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire \pipe_end_div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire \pipe_end_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire \pipe_end_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \pipe_end_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \pipe_end_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_end_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_end_logical_op__data_len$68 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_end_logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_end_logical_op__fn_unit$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_end_logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_end_logical_op__imm_data__data$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_end_logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_end_logical_op__imm_data__ok$55 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_end_logical_op__input_carry - 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attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute 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\pipe_middle_0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \pipe_middle_0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \pipe_middle_0_operation - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \pipe_middle_0_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \pipe_middle_0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 64 \pipe_middle_0_quotient_root - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_0_ra$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_0_rb$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" - wire width 192 \pipe_middle_0_remainder - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \pipe_middle_0_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \pipe_middle_0_xer_so$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire \pipe_start_div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire \pipe_start_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire \pipe_start_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \pipe_start_dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \pipe_start_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \pipe_start_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \pipe_start_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_start_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_start_logical_op__data_len$19 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_start_logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_start_logical_op__fn_unit$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_start_logical_op__imm_data__data - attribute \src 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attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_start_logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_start_logical_op__insn_type$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__invert_in$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__invert_out$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__is_32bit$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__is_signed$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__oe__oe$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__oe__ok$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__output_carry$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__rc__ok$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__rc__rc$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__write_cr0$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__zero_a$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_start_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_start_muxid$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \pipe_start_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \pipe_start_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \pipe_start_operation - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \pipe_start_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \pipe_start_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_start_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_start_ra$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_start_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_start_rb$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \pipe_start_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \pipe_start_xer_so$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 30 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 31 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 28 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 29 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 32 \xer_so$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 4 \xer_so_ok - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:25088.10-25091.4" - cell \n$72 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:25092.10-25095.4" - cell \p$71 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:25096.12-25159.4" - cell \pipe_end \pipe_end - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \pipe_end_cr_a - connect \cr_a_ok \pipe_end_cr_a_ok - connect \div_by_zero \pipe_end_div_by_zero - connect \dive_abs_ov32 \pipe_end_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_end_dive_abs_ov64 - connect \dividend_neg \pipe_end_dividend_neg - connect \divisor_neg \pipe_end_divisor_neg - connect \logical_op__data_len \pipe_end_logical_op__data_len - connect \logical_op__data_len$18 \pipe_end_logical_op__data_len$68 - connect \logical_op__fn_unit \pipe_end_logical_op__fn_unit - connect \logical_op__fn_unit$3 \pipe_end_logical_op__fn_unit$53 - connect \logical_op__imm_data__data \pipe_end_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \pipe_end_logical_op__imm_data__data$54 - connect \logical_op__imm_data__ok \pipe_end_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \pipe_end_logical_op__imm_data__ok$55 - connect \logical_op__input_carry \pipe_end_logical_op__input_carry - connect \logical_op__input_carry$12 \pipe_end_logical_op__input_carry$62 - connect \logical_op__insn \pipe_end_logical_op__insn - connect \logical_op__insn$19 \pipe_end_logical_op__insn$69 - connect \logical_op__insn_type \pipe_end_logical_op__insn_type - connect \logical_op__insn_type$2 \pipe_end_logical_op__insn_type$52 - connect \logical_op__invert_in \pipe_end_logical_op__invert_in - connect \logical_op__invert_in$10 \pipe_end_logical_op__invert_in$60 - connect \logical_op__invert_out \pipe_end_logical_op__invert_out - connect \logical_op__invert_out$13 \pipe_end_logical_op__invert_out$63 - connect \logical_op__is_32bit \pipe_end_logical_op__is_32bit - connect \logical_op__is_32bit$16 \pipe_end_logical_op__is_32bit$66 - connect \logical_op__is_signed \pipe_end_logical_op__is_signed - connect \logical_op__is_signed$17 \pipe_end_logical_op__is_signed$67 - connect \logical_op__oe__oe \pipe_end_logical_op__oe__oe - connect \logical_op__oe__oe$8 \pipe_end_logical_op__oe__oe$58 - connect \logical_op__oe__ok \pipe_end_logical_op__oe__ok - connect \logical_op__oe__ok$9 \pipe_end_logical_op__oe__ok$59 - connect \logical_op__output_carry \pipe_end_logical_op__output_carry - connect \logical_op__output_carry$15 \pipe_end_logical_op__output_carry$65 - connect \logical_op__rc__ok \pipe_end_logical_op__rc__ok - connect \logical_op__rc__ok$7 \pipe_end_logical_op__rc__ok$57 - connect \logical_op__rc__rc \pipe_end_logical_op__rc__rc - connect \logical_op__rc__rc$6 \pipe_end_logical_op__rc__rc$56 - connect \logical_op__write_cr0 \pipe_end_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \pipe_end_logical_op__write_cr0$64 - connect \logical_op__zero_a \pipe_end_logical_op__zero_a - connect \logical_op__zero_a$11 \pipe_end_logical_op__zero_a$61 - connect \muxid \pipe_end_muxid - connect \muxid$1 \pipe_end_muxid$51 - connect \n_ready_i \pipe_end_n_ready_i - connect \n_valid_o \pipe_end_n_valid_o - connect \o \pipe_end_o - connect \o_ok \pipe_end_o_ok - connect \p_ready_o \pipe_end_p_ready_o - connect \p_valid_i \pipe_end_p_valid_i - connect \quotient_root \pipe_end_quotient_root - connect \ra \pipe_end_ra - connect \rb \pipe_end_rb - connect \remainder \pipe_end_remainder - connect \xer_ov \pipe_end_xer_ov - connect \xer_ov_ok \pipe_end_xer_ov_ok - connect \xer_so \pipe_end_xer_so - connect \xer_so$20 \pipe_end_xer_so$70 - connect \xer_so_ok \pipe_end_xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:25160.17-25226.4" - cell \pipe_middle_0 \pipe_middle_0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \div_by_zero \pipe_middle_0_div_by_zero - connect \div_by_zero$27 \pipe_middle_0_div_by_zero$50 - connect \dive_abs_ov32 \pipe_middle_0_dive_abs_ov32 - connect \dive_abs_ov32$25 \pipe_middle_0_dive_abs_ov32$48 - connect \dive_abs_ov64 \pipe_middle_0_dive_abs_ov64 - connect \dive_abs_ov64$26 \pipe_middle_0_dive_abs_ov64$49 - connect \dividend \pipe_middle_0_dividend - connect \dividend_neg \pipe_middle_0_dividend_neg - connect \dividend_neg$24 \pipe_middle_0_dividend_neg$47 - connect \divisor_neg \pipe_middle_0_divisor_neg - connect \divisor_neg$23 \pipe_middle_0_divisor_neg$46 - connect \divisor_radicand \pipe_middle_0_divisor_radicand - connect \logical_op__data_len \pipe_middle_0_logical_op__data_len - connect \logical_op__data_len$18 \pipe_middle_0_logical_op__data_len$41 - connect \logical_op__fn_unit \pipe_middle_0_logical_op__fn_unit - connect \logical_op__fn_unit$3 \pipe_middle_0_logical_op__fn_unit$26 - connect \logical_op__imm_data__data \pipe_middle_0_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \pipe_middle_0_logical_op__imm_data__data$27 - connect \logical_op__imm_data__ok \pipe_middle_0_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \pipe_middle_0_logical_op__imm_data__ok$28 - connect \logical_op__input_carry \pipe_middle_0_logical_op__input_carry - connect \logical_op__input_carry$12 \pipe_middle_0_logical_op__input_carry$35 - connect \logical_op__insn \pipe_middle_0_logical_op__insn - connect \logical_op__insn$19 \pipe_middle_0_logical_op__insn$42 - connect \logical_op__insn_type \pipe_middle_0_logical_op__insn_type - connect \logical_op__insn_type$2 \pipe_middle_0_logical_op__insn_type$25 - connect \logical_op__invert_in \pipe_middle_0_logical_op__invert_in - connect \logical_op__invert_in$10 \pipe_middle_0_logical_op__invert_in$33 - connect \logical_op__invert_out \pipe_middle_0_logical_op__invert_out - connect \logical_op__invert_out$13 \pipe_middle_0_logical_op__invert_out$36 - connect \logical_op__is_32bit \pipe_middle_0_logical_op__is_32bit - connect \logical_op__is_32bit$16 \pipe_middle_0_logical_op__is_32bit$39 - connect \logical_op__is_signed \pipe_middle_0_logical_op__is_signed - connect \logical_op__is_signed$17 \pipe_middle_0_logical_op__is_signed$40 - connect \logical_op__oe__oe \pipe_middle_0_logical_op__oe__oe - connect \logical_op__oe__oe$8 \pipe_middle_0_logical_op__oe__oe$31 - connect \logical_op__oe__ok \pipe_middle_0_logical_op__oe__ok - connect \logical_op__oe__ok$9 \pipe_middle_0_logical_op__oe__ok$32 - connect \logical_op__output_carry \pipe_middle_0_logical_op__output_carry - connect \logical_op__output_carry$15 \pipe_middle_0_logical_op__output_carry$38 - connect \logical_op__rc__ok \pipe_middle_0_logical_op__rc__ok - connect \logical_op__rc__ok$7 \pipe_middle_0_logical_op__rc__ok$30 - connect \logical_op__rc__rc \pipe_middle_0_logical_op__rc__rc - connect \logical_op__rc__rc$6 \pipe_middle_0_logical_op__rc__rc$29 - connect \logical_op__write_cr0 \pipe_middle_0_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \pipe_middle_0_logical_op__write_cr0$37 - connect \logical_op__zero_a \pipe_middle_0_logical_op__zero_a - connect \logical_op__zero_a$11 \pipe_middle_0_logical_op__zero_a$34 - connect \muxid \pipe_middle_0_muxid - connect \muxid$1 \pipe_middle_0_muxid$24 - connect \n_ready_i \pipe_middle_0_n_ready_i - connect \n_valid_o \pipe_middle_0_n_valid_o - connect \operation \pipe_middle_0_operation - connect \p_ready_o \pipe_middle_0_p_ready_o - connect \p_valid_i \pipe_middle_0_p_valid_i - connect \quotient_root \pipe_middle_0_quotient_root - connect \ra \pipe_middle_0_ra - connect \ra$20 \pipe_middle_0_ra$43 - connect \rb \pipe_middle_0_rb - connect \rb$21 \pipe_middle_0_rb$44 - connect \remainder \pipe_middle_0_remainder - connect \xer_so \pipe_middle_0_xer_so - connect \xer_so$22 \pipe_middle_0_xer_so$45 - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:25227.14-25286.4" - cell \pipe_start \pipe_start - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \div_by_zero \pipe_start_div_by_zero - connect \dive_abs_ov32 \pipe_start_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_start_dive_abs_ov64 - connect \dividend \pipe_start_dividend - connect \dividend_neg \pipe_start_dividend_neg - connect \divisor_neg \pipe_start_divisor_neg - connect \divisor_radicand \pipe_start_divisor_radicand - connect \logical_op__data_len \pipe_start_logical_op__data_len - connect \logical_op__data_len$18 \pipe_start_logical_op__data_len$19 - connect \logical_op__fn_unit \pipe_start_logical_op__fn_unit - connect \logical_op__fn_unit$3 \pipe_start_logical_op__fn_unit$4 - connect \logical_op__imm_data__data \pipe_start_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \pipe_start_logical_op__imm_data__data$5 - connect \logical_op__imm_data__ok \pipe_start_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \pipe_start_logical_op__imm_data__ok$6 - connect \logical_op__input_carry \pipe_start_logical_op__input_carry - connect \logical_op__input_carry$12 \pipe_start_logical_op__input_carry$13 - connect \logical_op__insn \pipe_start_logical_op__insn - connect \logical_op__insn$19 \pipe_start_logical_op__insn$20 - connect \logical_op__insn_type \pipe_start_logical_op__insn_type - connect \logical_op__insn_type$2 \pipe_start_logical_op__insn_type$3 - connect \logical_op__invert_in \pipe_start_logical_op__invert_in - connect \logical_op__invert_in$10 \pipe_start_logical_op__invert_in$11 - connect \logical_op__invert_out \pipe_start_logical_op__invert_out - connect \logical_op__invert_out$13 \pipe_start_logical_op__invert_out$14 - connect \logical_op__is_32bit \pipe_start_logical_op__is_32bit - connect \logical_op__is_32bit$16 \pipe_start_logical_op__is_32bit$17 - connect \logical_op__is_signed \pipe_start_logical_op__is_signed - connect \logical_op__is_signed$17 \pipe_start_logical_op__is_signed$18 - connect \logical_op__oe__oe \pipe_start_logical_op__oe__oe - connect \logical_op__oe__oe$8 \pipe_start_logical_op__oe__oe$9 - connect \logical_op__oe__ok \pipe_start_logical_op__oe__ok - connect \logical_op__oe__ok$9 \pipe_start_logical_op__oe__ok$10 - connect \logical_op__output_carry \pipe_start_logical_op__output_carry - connect \logical_op__output_carry$15 \pipe_start_logical_op__output_carry$16 - connect \logical_op__rc__ok \pipe_start_logical_op__rc__ok - connect \logical_op__rc__ok$7 \pipe_start_logical_op__rc__ok$8 - connect \logical_op__rc__rc \pipe_start_logical_op__rc__rc - connect \logical_op__rc__rc$6 \pipe_start_logical_op__rc__rc$7 - connect \logical_op__write_cr0 \pipe_start_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \pipe_start_logical_op__write_cr0$15 - connect \logical_op__zero_a \pipe_start_logical_op__zero_a - connect \logical_op__zero_a$11 \pipe_start_logical_op__zero_a$12 - connect \muxid \pipe_start_muxid - connect \muxid$1 \pipe_start_muxid$2 - connect \n_ready_i \pipe_start_n_ready_i - connect \n_valid_o \pipe_start_n_valid_o - connect \operation \pipe_start_operation - connect \p_ready_o \pipe_start_p_ready_o - connect \p_valid_i \pipe_start_p_valid_i - connect \ra \pipe_start_ra - connect \ra$20 \pipe_start_ra$21 - connect \rb \pipe_start_rb - connect \rb$21 \pipe_start_rb$22 - connect \xer_so \pipe_start_xer_so - connect \xer_so$22 \pipe_start_xer_so$23 - end - connect \muxid 2'00 - connect { \xer_so_ok \xer_so } { \pipe_end_xer_so_ok \pipe_end_xer_so$70 } - connect { \xer_ov_ok \xer_ov } { \pipe_end_xer_ov_ok \pipe_end_xer_ov } - connect { \cr_a_ok \cr_a } { \pipe_end_cr_a_ok \pipe_end_cr_a } - connect { \o_ok \o } { \pipe_end_o_ok \pipe_end_o } - connect { \logical_op__insn$89 \logical_op__data_len$88 \logical_op__is_signed$87 \logical_op__is_32bit$86 \logical_op__output_carry$85 \logical_op__write_cr0$84 \logical_op__invert_out$83 \logical_op__input_carry$82 \logical_op__zero_a$81 \logical_op__invert_in$80 \logical_op__oe__ok$79 \logical_op__oe__oe$78 \logical_op__rc__ok$77 \logical_op__rc__rc$76 \logical_op__imm_data__ok$75 \logical_op__imm_data__data$74 \logical_op__fn_unit$73 \logical_op__insn_type$72 } { \pipe_end_logical_op__insn$69 \pipe_end_logical_op__data_len$68 \pipe_end_logical_op__is_signed$67 \pipe_end_logical_op__is_32bit$66 \pipe_end_logical_op__output_carry$65 \pipe_end_logical_op__write_cr0$64 \pipe_end_logical_op__invert_out$63 \pipe_end_logical_op__input_carry$62 \pipe_end_logical_op__zero_a$61 \pipe_end_logical_op__invert_in$60 \pipe_end_logical_op__oe__ok$59 \pipe_end_logical_op__oe__oe$58 \pipe_end_logical_op__rc__ok$57 \pipe_end_logical_op__rc__rc$56 \pipe_end_logical_op__imm_data__ok$55 \pipe_end_logical_op__imm_data__data$54 \pipe_end_logical_op__fn_unit$53 \pipe_end_logical_op__insn_type$52 } - connect \muxid$71 \pipe_end_muxid$51 - connect \pipe_end_n_ready_i \n_ready_i - connect \n_valid_o \pipe_end_n_valid_o - connect \pipe_start_xer_so$23 \xer_so$1 - connect \pipe_start_rb$22 \rb - connect \pipe_start_ra$21 \ra - connect { \pipe_start_logical_op__insn$20 \pipe_start_logical_op__data_len$19 \pipe_start_logical_op__is_signed$18 \pipe_start_logical_op__is_32bit$17 \pipe_start_logical_op__output_carry$16 \pipe_start_logical_op__write_cr0$15 \pipe_start_logical_op__invert_out$14 \pipe_start_logical_op__input_carry$13 \pipe_start_logical_op__zero_a$12 \pipe_start_logical_op__invert_in$11 \pipe_start_logical_op__oe__ok$10 \pipe_start_logical_op__oe__oe$9 \pipe_start_logical_op__rc__ok$8 \pipe_start_logical_op__rc__rc$7 \pipe_start_logical_op__imm_data__ok$6 \pipe_start_logical_op__imm_data__data$5 \pipe_start_logical_op__fn_unit$4 \pipe_start_logical_op__insn_type$3 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - connect \pipe_start_muxid$2 2'00 - connect \p_ready_o \pipe_start_p_ready_o - connect \pipe_start_p_valid_i \p_valid_i - connect \pipe_end_remainder \pipe_middle_0_remainder - connect \pipe_end_quotient_root \pipe_middle_0_quotient_root - connect \pipe_end_div_by_zero \pipe_middle_0_div_by_zero$50 - connect \pipe_end_dive_abs_ov64 \pipe_middle_0_dive_abs_ov64$49 - connect \pipe_end_dive_abs_ov32 \pipe_middle_0_dive_abs_ov32$48 - connect \pipe_end_dividend_neg \pipe_middle_0_dividend_neg$47 - connect \pipe_end_divisor_neg \pipe_middle_0_divisor_neg$46 - connect \pipe_end_xer_so \pipe_middle_0_xer_so$45 - connect \pipe_end_rb \pipe_middle_0_rb$44 - connect \pipe_end_ra \pipe_middle_0_ra$43 - connect { \pipe_end_logical_op__insn \pipe_end_logical_op__data_len \pipe_end_logical_op__is_signed \pipe_end_logical_op__is_32bit \pipe_end_logical_op__output_carry \pipe_end_logical_op__write_cr0 \pipe_end_logical_op__invert_out \pipe_end_logical_op__input_carry \pipe_end_logical_op__zero_a \pipe_end_logical_op__invert_in \pipe_end_logical_op__oe__ok \pipe_end_logical_op__oe__oe \pipe_end_logical_op__rc__ok \pipe_end_logical_op__rc__rc \pipe_end_logical_op__imm_data__ok \pipe_end_logical_op__imm_data__data \pipe_end_logical_op__fn_unit \pipe_end_logical_op__insn_type } { \pipe_middle_0_logical_op__insn$42 \pipe_middle_0_logical_op__data_len$41 \pipe_middle_0_logical_op__is_signed$40 \pipe_middle_0_logical_op__is_32bit$39 \pipe_middle_0_logical_op__output_carry$38 \pipe_middle_0_logical_op__write_cr0$37 \pipe_middle_0_logical_op__invert_out$36 \pipe_middle_0_logical_op__input_carry$35 \pipe_middle_0_logical_op__zero_a$34 \pipe_middle_0_logical_op__invert_in$33 \pipe_middle_0_logical_op__oe__ok$32 \pipe_middle_0_logical_op__oe__oe$31 \pipe_middle_0_logical_op__rc__ok$30 \pipe_middle_0_logical_op__rc__rc$29 \pipe_middle_0_logical_op__imm_data__ok$28 \pipe_middle_0_logical_op__imm_data__data$27 \pipe_middle_0_logical_op__fn_unit$26 \pipe_middle_0_logical_op__insn_type$25 } - connect \pipe_end_muxid \pipe_middle_0_muxid$24 - connect \pipe_middle_0_n_ready_i \pipe_end_p_ready_o - connect \pipe_end_p_valid_i \pipe_middle_0_n_valid_o - connect \pipe_middle_0_operation \pipe_start_operation - connect \pipe_middle_0_divisor_radicand \pipe_start_divisor_radicand - connect \pipe_middle_0_dividend \pipe_start_dividend - connect \pipe_middle_0_div_by_zero \pipe_start_div_by_zero - connect \pipe_middle_0_dive_abs_ov64 \pipe_start_dive_abs_ov64 - connect \pipe_middle_0_dive_abs_ov32 \pipe_start_dive_abs_ov32 - connect \pipe_middle_0_dividend_neg \pipe_start_dividend_neg - connect \pipe_middle_0_divisor_neg \pipe_start_divisor_neg - connect \pipe_middle_0_xer_so \pipe_start_xer_so - connect \pipe_middle_0_rb \pipe_start_rb - connect \pipe_middle_0_ra \pipe_start_ra - connect { \pipe_middle_0_logical_op__insn \pipe_middle_0_logical_op__data_len \pipe_middle_0_logical_op__is_signed \pipe_middle_0_logical_op__is_32bit \pipe_middle_0_logical_op__output_carry \pipe_middle_0_logical_op__write_cr0 \pipe_middle_0_logical_op__invert_out \pipe_middle_0_logical_op__input_carry \pipe_middle_0_logical_op__zero_a \pipe_middle_0_logical_op__invert_in \pipe_middle_0_logical_op__oe__ok \pipe_middle_0_logical_op__oe__oe \pipe_middle_0_logical_op__rc__ok \pipe_middle_0_logical_op__rc__rc \pipe_middle_0_logical_op__imm_data__ok \pipe_middle_0_logical_op__imm_data__data \pipe_middle_0_logical_op__fn_unit \pipe_middle_0_logical_op__insn_type } { \pipe_start_logical_op__insn \pipe_start_logical_op__data_len \pipe_start_logical_op__is_signed \pipe_start_logical_op__is_32bit \pipe_start_logical_op__output_carry \pipe_start_logical_op__write_cr0 \pipe_start_logical_op__invert_out \pipe_start_logical_op__input_carry \pipe_start_logical_op__zero_a \pipe_start_logical_op__invert_in \pipe_start_logical_op__oe__ok \pipe_start_logical_op__oe__oe \pipe_start_logical_op__rc__ok \pipe_start_logical_op__rc__rc \pipe_start_logical_op__imm_data__ok \pipe_start_logical_op__imm_data__data \pipe_start_logical_op__fn_unit \pipe_start_logical_op__insn_type } - connect \pipe_middle_0_muxid \pipe_start_muxid - connect \pipe_start_n_ready_i \pipe_middle_0_p_ready_o - connect \pipe_middle_0_p_valid_i \pipe_start_n_valid_o -end -attribute \src "issuer_ls180.v:25336.1-25394.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_l" -attribute \generator "nMigen" -module \alu_l - attribute \src "issuer_ls180.v:25337.7-25337.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:25382.3-25390.6" - wire $0\q_int$next[0:0]$775 - attribute \src "issuer_ls180.v:25380.3-25381.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:25382.3-25390.6" - wire $1\q_int$next[0:0]$776 - attribute \src "issuer_ls180.v:25361.7-25361.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:25372.17-25372.96" - wire $and$issuer_ls180.v:25372$765_Y - attribute \src "issuer_ls180.v:25377.17-25377.96" - wire $and$issuer_ls180.v:25377$770_Y - attribute \src "issuer_ls180.v:25374.18-25374.93" - wire $not$issuer_ls180.v:25374$767_Y - attribute \src "issuer_ls180.v:25376.17-25376.92" - wire $not$issuer_ls180.v:25376$769_Y - attribute \src "issuer_ls180.v:25379.17-25379.92" - wire $not$issuer_ls180.v:25379$772_Y - attribute \src "issuer_ls180.v:25373.18-25373.98" - wire $or$issuer_ls180.v:25373$766_Y - attribute \src "issuer_ls180.v:25375.18-25375.99" - wire $or$issuer_ls180.v:25375$768_Y - attribute \src "issuer_ls180.v:25378.17-25378.97" - wire $or$issuer_ls180.v:25378$771_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:25337.7-25337.15" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub10_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub10_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub10_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub10_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub10_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub10_upd + attribute \src "libresoc.v:18788.7-18788.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:25372$765 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:25372$765_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:25377$770 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:25377$770_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:25374$767 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $not$issuer_ls180.v:25374$767_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:25376$769 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$issuer_ls180.v:25376$769_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:25379$772 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$issuer_ls180.v:25379$772_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:25373$766 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alu - connect \Y $or$issuer_ls180.v:25373$766_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:25375$768 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $or$issuer_ls180.v:25375$768_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:25378$771 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alu - connect \Y $or$issuer_ls180.v:25378$771_Y - end - attribute \src "issuer_ls180.v:25337.7-25337.20" - process $proc$issuer_ls180.v:25337$777 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:18788.7-18788.20" + process $proc$libresoc.v:18788$416 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "issuer_ls180.v:25361.7-25361.19" - process $proc$issuer_ls180.v:25361$778 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:25380.3-25381.27" - process $proc$issuer_ls180.v:25380$773 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:25382.3-25390.6" - process $proc$issuer_ls180.v:25382$774 + attribute \src "libresoc.v:19045.3-19081.6" + process $proc$libresoc.v:19045$392 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$775 $1\q_int$next[0:0]$776 - attribute \src "issuer_ls180.v:25383.5-25383.29" + assign $0\dec31_dec_sub10_function_unit[11:0] $1\dec31_dec_sub10_function_unit[11:0] + attribute \src "libresoc.v:19046.5-19046.29" switch \initial - attribute \src "issuer_ls180.v:25383.9-25383.17" + attribute \src "libresoc.v:19046.9-19046.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } - assign $1\q_int$next[0:0]$776 1'0 + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 case - assign $1\q_int$next[0:0]$776 \$5 + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000000 end sync always - update \q_int$next $0\q_int$next[0:0]$775 - end - connect \$9 $and$issuer_ls180.v:25372$765_Y - connect \$11 $or$issuer_ls180.v:25373$766_Y - connect \$13 $not$issuer_ls180.v:25374$767_Y - connect \$15 $or$issuer_ls180.v:25375$768_Y - connect \$1 $not$issuer_ls180.v:25376$769_Y - connect \$3 $and$issuer_ls180.v:25377$770_Y - connect \$5 $or$issuer_ls180.v:25378$771_Y - connect \$7 $not$issuer_ls180.v:25379$772_Y - connect \qlq_alu \$15 - connect \qn_alu \$13 - connect \q_alu \$11 -end -attribute \src "issuer_ls180.v:25398.1-25456.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_l" -attribute \generator "nMigen" -module \alu_l$104 - attribute \src "issuer_ls180.v:25399.7-25399.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:25444.3-25452.6" - wire $0\q_int$next[0:0]$789 - attribute \src "issuer_ls180.v:25442.3-25443.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:25444.3-25452.6" - wire $1\q_int$next[0:0]$790 - attribute \src "issuer_ls180.v:25423.7-25423.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:25434.17-25434.96" - wire $and$issuer_ls180.v:25434$779_Y - attribute \src "issuer_ls180.v:25439.17-25439.96" - wire $and$issuer_ls180.v:25439$784_Y - attribute \src "issuer_ls180.v:25436.18-25436.93" - wire $not$issuer_ls180.v:25436$781_Y - attribute \src "issuer_ls180.v:25438.17-25438.92" - wire $not$issuer_ls180.v:25438$783_Y - attribute \src "issuer_ls180.v:25441.17-25441.92" - wire $not$issuer_ls180.v:25441$786_Y - attribute \src "issuer_ls180.v:25435.18-25435.98" - wire $or$issuer_ls180.v:25435$780_Y - attribute \src "issuer_ls180.v:25437.18-25437.99" - wire $or$issuer_ls180.v:25437$782_Y - attribute \src "issuer_ls180.v:25440.17-25440.97" - wire $or$issuer_ls180.v:25440$785_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:25399.7-25399.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:25434$779 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:25434$779_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:25439$784 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:25439$784_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:25436$781 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $not$issuer_ls180.v:25436$781_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:25438$783 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$issuer_ls180.v:25438$783_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:25441$786 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$issuer_ls180.v:25441$786_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:25435$780 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alu - connect \Y $or$issuer_ls180.v:25435$780_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:25437$782 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $or$issuer_ls180.v:25437$782_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:25440$785 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alu - connect \Y $or$issuer_ls180.v:25440$785_Y - end - attribute \src "issuer_ls180.v:25399.7-25399.20" - process $proc$issuer_ls180.v:25399$791 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:25423.7-25423.19" - process $proc$issuer_ls180.v:25423$792 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:25442.3-25443.27" - process $proc$issuer_ls180.v:25442$787 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[11:0] end - attribute \src "issuer_ls180.v:25444.3-25452.6" - process $proc$issuer_ls180.v:25444$788 + attribute \src "libresoc.v:19082.3-19118.6" + process $proc$libresoc.v:19082$393 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$789 $1\q_int$next[0:0]$790 - attribute \src "issuer_ls180.v:25445.5-25445.29" + assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:19083.5-19083.29" switch \initial - attribute \src "issuer_ls180.v:25445.9-25445.17" + attribute \src "libresoc.v:19083.9-19083.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } - assign $1\q_int$next[0:0]$790 1'0 - case - assign $1\q_int$next[0:0]$790 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$789 - end - connect \$9 $and$issuer_ls180.v:25434$779_Y - connect \$11 $or$issuer_ls180.v:25435$780_Y - connect \$13 $not$issuer_ls180.v:25436$781_Y - connect \$15 $or$issuer_ls180.v:25437$782_Y - connect \$1 $not$issuer_ls180.v:25438$783_Y - connect \$3 $and$issuer_ls180.v:25439$784_Y - connect \$5 $or$issuer_ls180.v:25440$785_Y - connect \$7 $not$issuer_ls180.v:25441$786_Y - connect \qlq_alu \$15 - connect \qn_alu \$13 - connect \q_alu \$11 -end -attribute \src "issuer_ls180.v:25460.1-25518.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_l" -attribute \generator "nMigen" -module \alu_l$122 - attribute \src "issuer_ls180.v:25461.7-25461.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:25506.3-25514.6" - wire $0\q_int$next[0:0]$803 - attribute \src "issuer_ls180.v:25504.3-25505.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:25506.3-25514.6" - wire $1\q_int$next[0:0]$804 - attribute \src "issuer_ls180.v:25485.7-25485.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:25496.17-25496.96" - wire $and$issuer_ls180.v:25496$793_Y - attribute \src "issuer_ls180.v:25501.17-25501.96" - wire $and$issuer_ls180.v:25501$798_Y - attribute \src "issuer_ls180.v:25498.18-25498.93" - wire $not$issuer_ls180.v:25498$795_Y - attribute \src "issuer_ls180.v:25500.17-25500.92" - wire $not$issuer_ls180.v:25500$797_Y - attribute \src "issuer_ls180.v:25503.17-25503.92" - wire $not$issuer_ls180.v:25503$800_Y - attribute \src "issuer_ls180.v:25497.18-25497.98" - wire $or$issuer_ls180.v:25497$794_Y - attribute \src "issuer_ls180.v:25499.18-25499.99" - wire $or$issuer_ls180.v:25499$796_Y - attribute \src "issuer_ls180.v:25502.17-25502.97" - wire $or$issuer_ls180.v:25502$799_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:25461.7-25461.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:25496$793 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:25496$793_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:25501$798 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:25501$798_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:25498$795 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $not$issuer_ls180.v:25498$795_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:25500$797 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$issuer_ls180.v:25500$797_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:25503$800 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$issuer_ls180.v:25503$800_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:25497$794 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alu - connect \Y $or$issuer_ls180.v:25497$794_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:25499$796 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $or$issuer_ls180.v:25499$796_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:25502$799 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alu - connect \Y $or$issuer_ls180.v:25502$799_Y - end - attribute \src "issuer_ls180.v:25461.7-25461.20" - process $proc$issuer_ls180.v:25461$805 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:25485.7-25485.19" - process $proc$issuer_ls180.v:25485$806 - assign { } { } - assign $1\q_int[0:0] 1'0 + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + end sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:25504.3-25505.27" - process $proc$issuer_ls180.v:25504$801 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0] end - attribute \src "issuer_ls180.v:25506.3-25514.6" - process $proc$issuer_ls180.v:25506$802 + attribute \src "libresoc.v:19119.3-19155.6" + process $proc$libresoc.v:19119$394 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$803 $1\q_int$next[0:0]$804 - attribute \src "issuer_ls180.v:25507.5-25507.29" + assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] + attribute \src "libresoc.v:19120.5-19120.29" switch \initial - attribute \src "issuer_ls180.v:25507.9-25507.17" + attribute \src "libresoc.v:19120.9-19120.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\q_int$next[0:0]$804 1'0 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 case - assign $1\q_int$next[0:0]$804 \$5 + assign $1\dec31_dec_sub10_upd[1:0] 2'00 end sync always - update \q_int$next $0\q_int$next[0:0]$803 - end - connect \$9 $and$issuer_ls180.v:25496$793_Y - connect \$11 $or$issuer_ls180.v:25497$794_Y - connect \$13 $not$issuer_ls180.v:25498$795_Y - connect \$15 $or$issuer_ls180.v:25499$796_Y - connect \$1 $not$issuer_ls180.v:25500$797_Y - connect \$3 $and$issuer_ls180.v:25501$798_Y - connect \$5 $or$issuer_ls180.v:25502$799_Y - connect \$7 $not$issuer_ls180.v:25503$800_Y - connect \qlq_alu \$15 - connect \qn_alu \$13 - connect \q_alu \$11 -end -attribute \src "issuer_ls180.v:25522.1-25580.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.alu_l" -attribute \generator "nMigen" -module \alu_l$125 - attribute \src "issuer_ls180.v:25523.7-25523.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:25568.3-25576.6" - wire $0\q_int$next[0:0]$817 - attribute \src "issuer_ls180.v:25566.3-25567.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:25568.3-25576.6" - wire $1\q_int$next[0:0]$818 - attribute \src "issuer_ls180.v:25547.7-25547.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:25558.17-25558.96" - wire $and$issuer_ls180.v:25558$807_Y - attribute \src "issuer_ls180.v:25563.17-25563.96" - wire $and$issuer_ls180.v:25563$812_Y - attribute \src "issuer_ls180.v:25560.18-25560.93" - wire $not$issuer_ls180.v:25560$809_Y - attribute \src "issuer_ls180.v:25562.17-25562.92" - wire $not$issuer_ls180.v:25562$811_Y - attribute \src "issuer_ls180.v:25565.17-25565.92" - wire $not$issuer_ls180.v:25565$814_Y - attribute \src "issuer_ls180.v:25559.18-25559.98" - wire $or$issuer_ls180.v:25559$808_Y - attribute \src "issuer_ls180.v:25561.18-25561.99" - wire $or$issuer_ls180.v:25561$810_Y - attribute \src "issuer_ls180.v:25564.17-25564.97" - wire $or$issuer_ls180.v:25564$813_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:25523.7-25523.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:25558$807 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:25558$807_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:25563$812 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:25563$812_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:25560$809 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $not$issuer_ls180.v:25560$809_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:25562$811 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$issuer_ls180.v:25562$811_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:25565$814 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$issuer_ls180.v:25565$814_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:25559$808 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alu - connect \Y $or$issuer_ls180.v:25559$808_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:25561$810 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $or$issuer_ls180.v:25561$810_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:25564$813 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alu - connect \Y $or$issuer_ls180.v:25564$813_Y + update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] end - attribute \src "issuer_ls180.v:25523.7-25523.20" - process $proc$issuer_ls180.v:25523$819 + attribute \src "libresoc.v:19156.3-19192.6" + process $proc$libresoc.v:19156$395 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:25547.7-25547.19" - process $proc$issuer_ls180.v:25547$820 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:19157.5-19157.29" + switch \initial + attribute \src "libresoc.v:19157.9-19157.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'00 + end sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:25566.3-25567.27" - process $proc$issuer_ls180.v:25566$815 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0] end - attribute \src "issuer_ls180.v:25568.3-25576.6" - process $proc$issuer_ls180.v:25568$816 + attribute \src "libresoc.v:19193.3-19229.6" + process $proc$libresoc.v:19193$396 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$817 $1\q_int$next[0:0]$818 - attribute \src "issuer_ls180.v:25569.5-25569.29" + assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:19194.5-19194.29" switch \initial - attribute \src "issuer_ls180.v:25569.9-25569.17" + attribute \src "libresoc.v:19194.9-19194.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } - assign $1\q_int$next[0:0]$818 1'0 + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 case - assign $1\q_int$next[0:0]$818 \$5 + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 end sync always - update \q_int$next $0\q_int$next[0:0]$817 - end - connect \$9 $and$issuer_ls180.v:25558$807_Y - connect \$11 $or$issuer_ls180.v:25559$808_Y - connect \$13 $not$issuer_ls180.v:25560$809_Y - connect \$15 $or$issuer_ls180.v:25561$810_Y - connect \$1 $not$issuer_ls180.v:25562$811_Y - connect \$3 $and$issuer_ls180.v:25563$812_Y - connect \$5 $or$issuer_ls180.v:25564$813_Y - connect \$7 $not$issuer_ls180.v:25565$814_Y - connect \qlq_alu \$15 - connect \qn_alu \$13 - connect \q_alu \$11 -end -attribute \src "issuer_ls180.v:25584.1-25642.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_l" -attribute \generator "nMigen" -module \alu_l$16 - attribute \src "issuer_ls180.v:25585.7-25585.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:25630.3-25638.6" - wire $0\q_int$next[0:0]$831 - attribute \src "issuer_ls180.v:25628.3-25629.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:25630.3-25638.6" - wire $1\q_int$next[0:0]$832 - attribute \src "issuer_ls180.v:25609.7-25609.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:25620.17-25620.96" - wire $and$issuer_ls180.v:25620$821_Y - attribute \src "issuer_ls180.v:25625.17-25625.96" - wire $and$issuer_ls180.v:25625$826_Y - attribute \src "issuer_ls180.v:25622.18-25622.93" - wire $not$issuer_ls180.v:25622$823_Y - attribute \src "issuer_ls180.v:25624.17-25624.92" - wire $not$issuer_ls180.v:25624$825_Y - attribute \src "issuer_ls180.v:25627.17-25627.92" - wire $not$issuer_ls180.v:25627$828_Y - attribute \src "issuer_ls180.v:25621.18-25621.98" - wire $or$issuer_ls180.v:25621$822_Y - attribute \src "issuer_ls180.v:25623.18-25623.99" - wire $or$issuer_ls180.v:25623$824_Y - attribute \src "issuer_ls180.v:25626.17-25626.97" - wire $or$issuer_ls180.v:25626$827_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:25585.7-25585.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:25620$821 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:25620$821_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:25625$826 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:25625$826_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:25622$823 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $not$issuer_ls180.v:25622$823_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:25624$825 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$issuer_ls180.v:25624$825_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:25627$828 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$issuer_ls180.v:25627$828_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:25621$822 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alu - connect \Y $or$issuer_ls180.v:25621$822_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:25623$824 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $or$issuer_ls180.v:25623$824_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:25626$827 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alu - connect \Y $or$issuer_ls180.v:25626$827_Y + update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0] end - attribute \src "issuer_ls180.v:25585.7-25585.20" - process $proc$issuer_ls180.v:25585$833 + attribute \src "libresoc.v:19230.3-19266.6" + process $proc$libresoc.v:19230$397 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:25609.7-25609.19" - process $proc$issuer_ls180.v:25609$834 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:19231.5-19231.29" + switch \initial + attribute \src "libresoc.v:19231.9-19231.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001110 + case + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000000 + end sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:25628.3-25629.27" - process $proc$issuer_ls180.v:25628$829 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0] end - attribute \src "issuer_ls180.v:25630.3-25638.6" - process $proc$issuer_ls180.v:25630$830 + attribute \src "libresoc.v:19267.3-19303.6" + process $proc$libresoc.v:19267$398 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$831 $1\q_int$next[0:0]$832 - attribute \src "issuer_ls180.v:25631.5-25631.29" + assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:19268.5-19268.29" switch \initial - attribute \src "issuer_ls180.v:25631.9-25631.17" + attribute \src "libresoc.v:19268.9-19268.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\q_int$next[0:0]$832 1'0 + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 case - assign $1\q_int$next[0:0]$832 \$5 + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[0:0]$831 - end - connect \$9 $and$issuer_ls180.v:25620$821_Y - connect \$11 $or$issuer_ls180.v:25621$822_Y - connect \$13 $not$issuer_ls180.v:25622$823_Y - connect \$15 $or$issuer_ls180.v:25623$824_Y - connect \$1 $not$issuer_ls180.v:25624$825_Y - connect \$3 $and$issuer_ls180.v:25625$826_Y - connect \$5 $or$issuer_ls180.v:25626$827_Y - connect \$7 $not$issuer_ls180.v:25627$828_Y - connect \qlq_alu \$15 - connect \qn_alu \$13 - connect \q_alu \$11 -end -attribute \src "issuer_ls180.v:25646.1-25704.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_l" -attribute \generator "nMigen" -module \alu_l$29 - attribute \src "issuer_ls180.v:25647.7-25647.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:25692.3-25700.6" - wire $0\q_int$next[0:0]$845 - attribute \src "issuer_ls180.v:25690.3-25691.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:25692.3-25700.6" - wire $1\q_int$next[0:0]$846 - attribute \src "issuer_ls180.v:25671.7-25671.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:25682.17-25682.96" - wire $and$issuer_ls180.v:25682$835_Y - attribute \src "issuer_ls180.v:25687.17-25687.96" - wire $and$issuer_ls180.v:25687$840_Y - attribute \src "issuer_ls180.v:25684.18-25684.93" - wire $not$issuer_ls180.v:25684$837_Y - attribute \src "issuer_ls180.v:25686.17-25686.92" - wire $not$issuer_ls180.v:25686$839_Y - attribute \src "issuer_ls180.v:25689.17-25689.92" - wire $not$issuer_ls180.v:25689$842_Y - attribute \src "issuer_ls180.v:25683.18-25683.98" - wire $or$issuer_ls180.v:25683$836_Y - attribute \src "issuer_ls180.v:25685.18-25685.99" - wire $or$issuer_ls180.v:25685$838_Y - attribute \src "issuer_ls180.v:25688.17-25688.97" - wire $or$issuer_ls180.v:25688$841_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:25647.7-25647.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:25682$835 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:25682$835_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:25687$840 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:25687$840_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:25684$837 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $not$issuer_ls180.v:25684$837_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:25686$839 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$issuer_ls180.v:25686$839_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:25689$842 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$issuer_ls180.v:25689$842_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:25683$836 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alu - connect \Y $or$issuer_ls180.v:25683$836_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:25685$838 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $or$issuer_ls180.v:25685$838_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:25688$841 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alu - connect \Y $or$issuer_ls180.v:25688$841_Y + update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0] end - attribute \src "issuer_ls180.v:25647.7-25647.20" - process $proc$issuer_ls180.v:25647$847 + attribute \src "libresoc.v:19304.3-19340.6" + process $proc$libresoc.v:19304$399 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:25671.7-25671.19" - process $proc$issuer_ls180.v:25671$848 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:19305.5-19305.29" + switch \initial + attribute \src "libresoc.v:19305.9-19305.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + end sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:25690.3-25691.27" - process $proc$issuer_ls180.v:25690$843 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0] end - attribute \src "issuer_ls180.v:25692.3-25700.6" - process $proc$issuer_ls180.v:25692$844 + attribute \src "libresoc.v:19341.3-19377.6" + process $proc$libresoc.v:19341$400 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$845 $1\q_int$next[0:0]$846 - attribute \src "issuer_ls180.v:25693.5-25693.29" + assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:19342.5-19342.29" switch \initial - attribute \src "issuer_ls180.v:25693.9-25693.17" + attribute \src "libresoc.v:19342.9-19342.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } - assign $1\q_int$next[0:0]$846 1'0 + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 case - assign $1\q_int$next[0:0]$846 \$5 + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[0:0]$845 - end - connect \$9 $and$issuer_ls180.v:25682$835_Y - connect \$11 $or$issuer_ls180.v:25683$836_Y - connect \$13 $not$issuer_ls180.v:25684$837_Y - connect \$15 $or$issuer_ls180.v:25685$838_Y - connect \$1 $not$issuer_ls180.v:25686$839_Y - connect \$3 $and$issuer_ls180.v:25687$840_Y - connect \$5 $or$issuer_ls180.v:25688$841_Y - connect \$7 $not$issuer_ls180.v:25689$842_Y - connect \qlq_alu \$15 - connect \qn_alu \$13 - connect \q_alu \$11 -end -attribute \src "issuer_ls180.v:25708.1-25766.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_l" -attribute \generator "nMigen" -module \alu_l$42 - attribute \src "issuer_ls180.v:25709.7-25709.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:25754.3-25762.6" - wire $0\q_int$next[0:0]$859 - attribute \src "issuer_ls180.v:25752.3-25753.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:25754.3-25762.6" - wire $1\q_int$next[0:0]$860 - attribute \src "issuer_ls180.v:25733.7-25733.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:25744.17-25744.96" - wire $and$issuer_ls180.v:25744$849_Y - attribute \src "issuer_ls180.v:25749.17-25749.96" - wire $and$issuer_ls180.v:25749$854_Y - attribute \src "issuer_ls180.v:25746.18-25746.93" - wire $not$issuer_ls180.v:25746$851_Y - attribute \src "issuer_ls180.v:25748.17-25748.92" - wire $not$issuer_ls180.v:25748$853_Y - attribute \src "issuer_ls180.v:25751.17-25751.92" - wire $not$issuer_ls180.v:25751$856_Y - attribute \src "issuer_ls180.v:25745.18-25745.98" - wire $or$issuer_ls180.v:25745$850_Y - attribute \src "issuer_ls180.v:25747.18-25747.99" - wire $or$issuer_ls180.v:25747$852_Y - attribute \src "issuer_ls180.v:25750.17-25750.97" - wire $or$issuer_ls180.v:25750$855_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:25709.7-25709.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:25744$849 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:25744$849_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:25749$854 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:25749$854_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:25746$851 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $not$issuer_ls180.v:25746$851_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:25748$853 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$issuer_ls180.v:25748$853_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:25751$856 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$issuer_ls180.v:25751$856_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:25745$850 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alu - connect \Y $or$issuer_ls180.v:25745$850_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:25747$852 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $or$issuer_ls180.v:25747$852_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:25750$855 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alu - connect \Y $or$issuer_ls180.v:25750$855_Y + update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0] end - attribute \src "issuer_ls180.v:25709.7-25709.20" - process $proc$issuer_ls180.v:25709$861 + attribute \src "libresoc.v:19378.3-19414.6" + process $proc$libresoc.v:19378$401 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:25733.7-25733.19" - process $proc$issuer_ls180.v:25733$862 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:19379.5-19379.29" + switch \initial + attribute \src "libresoc.v:19379.9-19379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + case + assign $1\dec31_dec_sub10_br[0:0] 1'0 + end sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:25752.3-25753.27" - process $proc$issuer_ls180.v:25752$857 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0] end - attribute \src "issuer_ls180.v:25754.3-25762.6" - process $proc$issuer_ls180.v:25754$858 + attribute \src "libresoc.v:19415.3-19451.6" + process $proc$libresoc.v:19415$402 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$859 $1\q_int$next[0:0]$860 - attribute \src "issuer_ls180.v:25755.5-25755.29" + assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:19416.5-19416.29" switch \initial - attribute \src "issuer_ls180.v:25755.9-25755.17" + attribute \src "libresoc.v:19416.9-19416.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\q_int$next[0:0]$860 1'0 + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 case - assign $1\q_int$next[0:0]$860 \$5 + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[0:0]$859 - end - connect \$9 $and$issuer_ls180.v:25744$849_Y - connect \$11 $or$issuer_ls180.v:25745$850_Y - connect \$13 $not$issuer_ls180.v:25746$851_Y - connect \$15 $or$issuer_ls180.v:25747$852_Y - connect \$1 $not$issuer_ls180.v:25748$853_Y - connect \$3 $and$issuer_ls180.v:25749$854_Y - connect \$5 $or$issuer_ls180.v:25750$855_Y - connect \$7 $not$issuer_ls180.v:25751$856_Y - connect \qlq_alu \$15 - connect \qn_alu \$13 - connect \q_alu \$11 -end -attribute \src "issuer_ls180.v:25770.1-25828.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_l" -attribute \generator "nMigen" -module \alu_l$58 - attribute \src "issuer_ls180.v:25771.7-25771.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:25816.3-25824.6" - wire $0\q_int$next[0:0]$873 - attribute \src "issuer_ls180.v:25814.3-25815.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:25816.3-25824.6" - wire $1\q_int$next[0:0]$874 - attribute \src "issuer_ls180.v:25795.7-25795.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:25806.17-25806.96" - wire $and$issuer_ls180.v:25806$863_Y - attribute \src "issuer_ls180.v:25811.17-25811.96" - wire $and$issuer_ls180.v:25811$868_Y - attribute \src "issuer_ls180.v:25808.18-25808.93" - wire $not$issuer_ls180.v:25808$865_Y - attribute \src "issuer_ls180.v:25810.17-25810.92" - wire $not$issuer_ls180.v:25810$867_Y - attribute \src "issuer_ls180.v:25813.17-25813.92" - wire $not$issuer_ls180.v:25813$870_Y - attribute \src "issuer_ls180.v:25807.18-25807.98" - wire $or$issuer_ls180.v:25807$864_Y - attribute \src "issuer_ls180.v:25809.18-25809.99" - wire $or$issuer_ls180.v:25809$866_Y - attribute \src "issuer_ls180.v:25812.17-25812.97" - wire $or$issuer_ls180.v:25812$869_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:25771.7-25771.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:25806$863 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:25806$863_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:25811$868 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:25811$868_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:25808$865 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $not$issuer_ls180.v:25808$865_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:25810$867 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$issuer_ls180.v:25810$867_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:25813$870 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$issuer_ls180.v:25813$870_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:25807$864 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alu - connect \Y $or$issuer_ls180.v:25807$864_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:25809$866 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $or$issuer_ls180.v:25809$866_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:25812$869 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alu - connect \Y $or$issuer_ls180.v:25812$869_Y + update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0] end - attribute \src "issuer_ls180.v:25771.7-25771.20" - process $proc$issuer_ls180.v:25771$875 + attribute \src "libresoc.v:19452.3-19488.6" + process $proc$libresoc.v:19452$403 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:25795.7-25795.19" - process $proc$issuer_ls180.v:25795$876 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:19453.5-19453.29" + switch \initial + attribute \src "libresoc.v:19453.9-19453.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + case + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000000 + end sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:25814.3-25815.27" - process $proc$issuer_ls180.v:25814$871 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] end - attribute \src "issuer_ls180.v:25816.3-25824.6" - process $proc$issuer_ls180.v:25816$872 + attribute \src "libresoc.v:19489.3-19525.6" + process $proc$libresoc.v:19489$404 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$873 $1\q_int$next[0:0]$874 - attribute \src "issuer_ls180.v:25817.5-25817.29" + assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0] + attribute \src "libresoc.v:19490.5-19490.29" switch \initial - attribute \src "issuer_ls180.v:25817.9-25817.17" + attribute \src "libresoc.v:19490.9-19490.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } - assign $1\q_int$next[0:0]$874 1'0 + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 case - assign $1\q_int$next[0:0]$874 \$5 + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[0:0]$873 - end - connect \$9 $and$issuer_ls180.v:25806$863_Y - connect \$11 $or$issuer_ls180.v:25807$864_Y - connect \$13 $not$issuer_ls180.v:25808$865_Y - connect \$15 $or$issuer_ls180.v:25809$866_Y - connect \$1 $not$issuer_ls180.v:25810$867_Y - connect \$3 $and$issuer_ls180.v:25811$868_Y - connect \$5 $or$issuer_ls180.v:25812$869_Y - connect \$7 $not$issuer_ls180.v:25813$870_Y - connect \qlq_alu \$15 - connect \qn_alu \$13 - connect \q_alu \$11 -end -attribute \src "issuer_ls180.v:25832.1-25890.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_l" -attribute \generator "nMigen" -module \alu_l$70 - attribute \src "issuer_ls180.v:25833.7-25833.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:25878.3-25886.6" - wire $0\q_int$next[0:0]$887 - attribute \src "issuer_ls180.v:25876.3-25877.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:25878.3-25886.6" - wire $1\q_int$next[0:0]$888 - attribute \src "issuer_ls180.v:25857.7-25857.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:25868.17-25868.96" - wire $and$issuer_ls180.v:25868$877_Y - attribute \src "issuer_ls180.v:25873.17-25873.96" - wire $and$issuer_ls180.v:25873$882_Y - attribute \src "issuer_ls180.v:25870.18-25870.93" - wire $not$issuer_ls180.v:25870$879_Y - attribute \src "issuer_ls180.v:25872.17-25872.92" - wire $not$issuer_ls180.v:25872$881_Y - attribute \src "issuer_ls180.v:25875.17-25875.92" - wire $not$issuer_ls180.v:25875$884_Y - attribute \src "issuer_ls180.v:25869.18-25869.98" - wire $or$issuer_ls180.v:25869$878_Y - attribute \src "issuer_ls180.v:25871.18-25871.99" - wire $or$issuer_ls180.v:25871$880_Y - attribute \src "issuer_ls180.v:25874.17-25874.97" - wire $or$issuer_ls180.v:25874$883_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:25833.7-25833.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:25868$877 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:25868$877_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:25873$882 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:25873$882_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:25870$879 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $not$issuer_ls180.v:25870$879_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:25872$881 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$issuer_ls180.v:25872$881_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:25875$884 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$issuer_ls180.v:25875$884_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:25869$878 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alu - connect \Y $or$issuer_ls180.v:25869$878_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:25871$880 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $or$issuer_ls180.v:25871$880_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:25874$883 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alu - connect \Y $or$issuer_ls180.v:25874$883_Y + update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0] end - attribute \src "issuer_ls180.v:25833.7-25833.20" - process $proc$issuer_ls180.v:25833$889 + attribute \src "libresoc.v:19526.3-19562.6" + process $proc$libresoc.v:19526$405 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:25857.7-25857.19" - process $proc$issuer_ls180.v:25857$890 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:19527.5-19527.29" + switch \initial + attribute \src "libresoc.v:19527.9-19527.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + end sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:25876.3-25877.27" - process $proc$issuer_ls180.v:25876$885 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] end - attribute \src "issuer_ls180.v:25878.3-25886.6" - process $proc$issuer_ls180.v:25878$886 + attribute \src "libresoc.v:19563.3-19599.6" + process $proc$libresoc.v:19563$406 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$887 $1\q_int$next[0:0]$888 - attribute \src "issuer_ls180.v:25879.5-25879.29" + assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:19564.5-19564.29" switch \initial - attribute \src "issuer_ls180.v:25879.9-25879.17" + attribute \src "libresoc.v:19564.9-19564.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\q_int$next[0:0]$888 1'0 + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 case - assign $1\q_int$next[0:0]$888 \$5 + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[0:0]$887 - end - connect \$9 $and$issuer_ls180.v:25868$877_Y - connect \$11 $or$issuer_ls180.v:25869$878_Y - connect \$13 $not$issuer_ls180.v:25870$879_Y - connect \$15 $or$issuer_ls180.v:25871$880_Y - connect \$1 $not$issuer_ls180.v:25872$881_Y - connect \$3 $and$issuer_ls180.v:25873$882_Y - connect \$5 $or$issuer_ls180.v:25874$883_Y - connect \$7 $not$issuer_ls180.v:25875$884_Y - connect \qlq_alu \$15 - connect \qn_alu \$13 - connect \q_alu \$11 -end -attribute \src "issuer_ls180.v:25894.1-25952.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_l" -attribute \generator "nMigen" -module \alu_l$87 - attribute \src "issuer_ls180.v:25895.7-25895.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:25940.3-25948.6" - wire $0\q_int$next[0:0]$901 - attribute \src "issuer_ls180.v:25938.3-25939.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:25940.3-25948.6" - wire $1\q_int$next[0:0]$902 - attribute \src "issuer_ls180.v:25919.7-25919.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:25930.17-25930.96" - wire $and$issuer_ls180.v:25930$891_Y - attribute \src "issuer_ls180.v:25935.17-25935.96" - wire $and$issuer_ls180.v:25935$896_Y - attribute \src "issuer_ls180.v:25932.18-25932.93" - wire $not$issuer_ls180.v:25932$893_Y - attribute \src "issuer_ls180.v:25934.17-25934.92" - wire $not$issuer_ls180.v:25934$895_Y - attribute \src "issuer_ls180.v:25937.17-25937.92" - wire $not$issuer_ls180.v:25937$898_Y - attribute \src "issuer_ls180.v:25931.18-25931.98" - wire $or$issuer_ls180.v:25931$892_Y - attribute \src "issuer_ls180.v:25933.18-25933.99" - wire $or$issuer_ls180.v:25933$894_Y - attribute \src "issuer_ls180.v:25936.17-25936.97" - wire $or$issuer_ls180.v:25936$897_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:25895.7-25895.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:25930$891 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:25930$891_Y + update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:25935$896 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:25935$896_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:25932$893 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $not$issuer_ls180.v:25932$893_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:25934$895 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$issuer_ls180.v:25934$895_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:25937$898 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$issuer_ls180.v:25937$898_Y + attribute \src "libresoc.v:19600.3-19636.6" + process $proc$libresoc.v:19600$407 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:19601.5-19601.29" + switch \initial + attribute \src "libresoc.v:19601.9-19601.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:25931$892 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alu - connect \Y $or$issuer_ls180.v:25931$892_Y + attribute \src "libresoc.v:19637.3-19673.6" + process $proc$libresoc.v:19637$408 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:19638.5-19638.29" + switch \initial + attribute \src "libresoc.v:19638.9-19638.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:25933$894 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $or$issuer_ls180.v:25933$894_Y + attribute \src "libresoc.v:19674.3-19710.6" + process $proc$libresoc.v:19674$409 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:19675.5-19675.29" + switch \initial + attribute \src "libresoc.v:19675.9-19675.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub10_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:25936$897 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alu - connect \Y $or$issuer_ls180.v:25936$897_Y + attribute \src "libresoc.v:19711.3-19747.6" + process $proc$libresoc.v:19711$410 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:19712.5-19712.29" + switch \initial + attribute \src "libresoc.v:19712.9-19712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0] end - attribute \src "issuer_ls180.v:25895.7-25895.20" - process $proc$issuer_ls180.v:25895$903 + attribute \src "libresoc.v:19748.3-19784.6" + process $proc$libresoc.v:19748$411 assign { } { } - assign $0\initial[0:0] 1'0 + assign { } { } + assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:19749.5-19749.29" + switch \initial + attribute \src "libresoc.v:19749.9-19749.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + end sync always - update \initial $0\initial[0:0] - sync init + update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0] end - attribute \src "issuer_ls180.v:25919.7-25919.19" - process $proc$issuer_ls180.v:25919$904 + attribute \src "libresoc.v:19785.3-19821.6" + process $proc$libresoc.v:19785$412 + assign { } { } assign { } { } - assign $1\q_int[0:0] 1'0 + assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:19786.5-19786.29" + switch \initial + attribute \src "libresoc.v:19786.9-19786.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + end sync always - sync init - update \q_int $1\q_int[0:0] + update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0] end - attribute \src "issuer_ls180.v:25938.3-25939.27" - process $proc$issuer_ls180.v:25938$899 + attribute \src "libresoc.v:19822.3-19858.6" + process $proc$libresoc.v:19822$413 assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + assign { } { } + assign $0\dec31_dec_sub10_out_sel[1:0] $1\dec31_dec_sub10_out_sel[1:0] + attribute \src "libresoc.v:19823.5-19823.29" + switch \initial + attribute \src "libresoc.v:19823.9-19823.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub10_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_out_sel $0\dec31_dec_sub10_out_sel[1:0] end - attribute \src "issuer_ls180.v:25940.3-25948.6" - process $proc$issuer_ls180.v:25940$900 + attribute \src "libresoc.v:19859.3-19895.6" + process $proc$libresoc.v:19859$414 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$901 $1\q_int$next[0:0]$902 - attribute \src "issuer_ls180.v:25941.5-25941.29" + assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:19860.5-19860.29" switch \initial - attribute \src "issuer_ls180.v:25941.9-25941.17" + attribute \src "libresoc.v:19860.9-19860.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0] + end + attribute \src "libresoc.v:19896.3-19932.6" + process $proc$libresoc.v:19896$415 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:19897.5-19897.29" + switch \initial + attribute \src "libresoc.v:19897.9-19897.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\q_int$next[0:0]$902 1'0 + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 case - assign $1\q_int$next[0:0]$902 \$5 + assign $1\dec31_dec_sub10_cr_out[2:0] 3'000 end sync always - update \q_int$next $0\q_int$next[0:0]$901 + update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0] end - connect \$9 $and$issuer_ls180.v:25930$891_Y - connect \$11 $or$issuer_ls180.v:25931$892_Y - connect \$13 $not$issuer_ls180.v:25932$893_Y - connect \$15 $or$issuer_ls180.v:25933$894_Y - connect \$1 $not$issuer_ls180.v:25934$895_Y - connect \$3 $and$issuer_ls180.v:25935$896_Y - connect \$5 $or$issuer_ls180.v:25936$897_Y - connect \$7 $not$issuer_ls180.v:25937$898_Y - connect \qlq_alu \$15 - connect \qn_alu \$13 - connect \q_alu \$11 + connect \opcode_switch \opcode_in [10:6] end -attribute \src "issuer_ls180.v:25956.1-26951.10" +attribute \src "libresoc.v:19938.1-21517.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub11" attribute \generator "nMigen" -module \alu_logical0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 3 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 22 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$61 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 7 \logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 8 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$48 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 16 \logical_op__input_carry +module \dec31_dec_sub11 + attribute \src "libresoc.v:20471.3-20525.6" + wire width 8 $0\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:20691.3-20745.6" + wire $0\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:21406.3-21460.6" + wire width 3 $0\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:21461.3-21515.6" + wire width 3 $0\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:20416.3-20470.6" + wire width 2 $0\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:20636.3-20690.6" + wire $0\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:21131.3-21185.6" + wire width 5 $0\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:20196.3-20250.6" + wire width 12 $0\dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:21186.3-21240.6" + wire width 3 $0\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:21241.3-21295.6" + wire width 4 $0\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:21296.3-21350.6" + wire width 2 $0\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:20801.3-20855.6" + wire width 7 $0\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:20526.3-20580.6" + wire $0\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:20581.3-20635.6" + wire $0\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:20911.3-20965.6" + wire $0\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:20251.3-20305.6" + wire width 4 $0\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:21021.3-21075.6" + wire $0\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:21351.3-21405.6" + wire width 2 $0\dec31_dec_sub11_out_sel[1:0] + attribute \src "libresoc.v:20361.3-20415.6" + wire width 2 $0\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:20856.3-20910.6" + wire $0\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:21076.3-21130.6" + wire $0\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:20966.3-21020.6" + wire $0\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:20746.3-20800.6" + wire $0\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:20306.3-20360.6" + wire width 2 $0\dec31_dec_sub11_upd[1:0] + attribute \src "libresoc.v:19939.7-19939.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20471.3-20525.6" + wire width 8 $1\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:20691.3-20745.6" + wire $1\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:21406.3-21460.6" + wire width 3 $1\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:21461.3-21515.6" + wire width 3 $1\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:20416.3-20470.6" + wire width 2 $1\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:20636.3-20690.6" + wire $1\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:21131.3-21185.6" + wire width 5 $1\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:20196.3-20250.6" + wire width 12 $1\dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:21186.3-21240.6" + wire width 3 $1\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:21241.3-21295.6" + wire width 4 $1\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:21296.3-21350.6" + wire width 2 $1\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:20801.3-20855.6" + wire width 7 $1\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:20526.3-20580.6" + wire $1\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:20581.3-20635.6" + wire $1\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:20911.3-20965.6" + wire $1\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:20251.3-20305.6" + wire width 4 $1\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:21021.3-21075.6" + wire $1\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:21351.3-21405.6" + wire width 2 $1\dec31_dec_sub11_out_sel[1:0] + attribute \src "libresoc.v:20361.3-20415.6" + wire width 2 $1\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:20856.3-20910.6" + wire $1\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:21076.3-21130.6" + wire $1\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:20966.3-21020.6" + wire $1\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:20746.3-20800.6" + wire $1\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:20306.3-20360.6" + wire width 2 $1\dec31_dec_sub11_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub11_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub11_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub11_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 23 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$62 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 6 \logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 21 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \logical_pipe1_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \logical_pipe1_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_pipe1_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_pipe1_logical_op__data_len$18 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_pipe1_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub11_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub11_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -39377,108 +28079,39 @@ module \alu_logical0 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_pipe1_logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_pipe1_logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_pipe1_logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe1_logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe1_logical_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_pipe1_logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_pipe1_logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_pipe1_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_pipe1_logical_op__insn$19 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_pipe1_logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub11_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub11_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub11_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub11_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -39553,8844 +28186,2225 @@ module \alu_logical0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_pipe1_logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe1_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe1_logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe1_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe1_logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe1_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe1_logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe1_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe1_logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe1_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe1_logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe1_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe1_logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe1_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe1_logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe1_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe1_logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe1_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe1_logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe1_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe1_logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe1_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe1_logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \logical_pipe1_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \logical_pipe1_muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \logical_pipe1_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \logical_pipe1_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \logical_pipe1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \logical_pipe1_o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \logical_pipe1_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \logical_pipe1_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \logical_pipe1_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \logical_pipe1_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \logical_pipe1_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \logical_pipe1_xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \logical_pipe1_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \logical_pipe2_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \logical_pipe2_cr_a$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \logical_pipe2_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \logical_pipe2_cr_a_ok$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_pipe2_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_pipe2_logical_op__data_len$38 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_pipe2_logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_pipe2_logical_op__fn_unit$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_pipe2_logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_pipe2_logical_op__imm_data__data$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__imm_data__ok$25 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_pipe2_logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub11_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub11_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub11_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub11_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub11_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_pipe2_logical_op__input_carry$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_pipe2_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_pipe2_logical_op__insn$39 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_pipe2_logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_pipe2_logical_op__insn_type$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__invert_in$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__invert_out$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__is_32bit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__is_signed$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__oe__oe$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__oe__ok$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__output_carry$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__rc__ok$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__rc__rc$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__write_cr0$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__zero_a$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \logical_pipe2_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \logical_pipe2_muxid$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \logical_pipe2_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \logical_pipe2_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \logical_pipe2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \logical_pipe2_o$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \logical_pipe2_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \logical_pipe2_o_ok$41 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \logical_pipe2_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \logical_pipe2_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \logical_pipe2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \logical_pipe2_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$44 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 5 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 4 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 24 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 30 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 29 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 26 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 27 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 28 \xer_so - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:26811.17-26865.4" - cell \logical_pipe1 \logical_pipe1 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \logical_pipe1_cr_a - connect \cr_a_ok \logical_pipe1_cr_a_ok - connect \logical_op__data_len \logical_pipe1_logical_op__data_len - connect \logical_op__data_len$18 \logical_pipe1_logical_op__data_len$18 - connect \logical_op__fn_unit \logical_pipe1_logical_op__fn_unit - connect \logical_op__fn_unit$3 \logical_pipe1_logical_op__fn_unit$3 - connect \logical_op__imm_data__data \logical_pipe1_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \logical_pipe1_logical_op__imm_data__data$4 - connect \logical_op__imm_data__ok \logical_pipe1_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \logical_pipe1_logical_op__imm_data__ok$5 - connect \logical_op__input_carry \logical_pipe1_logical_op__input_carry - connect \logical_op__input_carry$12 \logical_pipe1_logical_op__input_carry$12 - connect \logical_op__insn \logical_pipe1_logical_op__insn - connect \logical_op__insn$19 \logical_pipe1_logical_op__insn$19 - connect \logical_op__insn_type \logical_pipe1_logical_op__insn_type - connect \logical_op__insn_type$2 \logical_pipe1_logical_op__insn_type$2 - connect \logical_op__invert_in \logical_pipe1_logical_op__invert_in - connect \logical_op__invert_in$10 \logical_pipe1_logical_op__invert_in$10 - connect \logical_op__invert_out \logical_pipe1_logical_op__invert_out - connect \logical_op__invert_out$13 \logical_pipe1_logical_op__invert_out$13 - connect \logical_op__is_32bit \logical_pipe1_logical_op__is_32bit - connect \logical_op__is_32bit$16 \logical_pipe1_logical_op__is_32bit$16 - connect \logical_op__is_signed \logical_pipe1_logical_op__is_signed - connect \logical_op__is_signed$17 \logical_pipe1_logical_op__is_signed$17 - connect \logical_op__oe__oe \logical_pipe1_logical_op__oe__oe - connect \logical_op__oe__oe$8 \logical_pipe1_logical_op__oe__oe$8 - connect \logical_op__oe__ok \logical_pipe1_logical_op__oe__ok - connect \logical_op__oe__ok$9 \logical_pipe1_logical_op__oe__ok$9 - connect \logical_op__output_carry \logical_pipe1_logical_op__output_carry - connect \logical_op__output_carry$15 \logical_pipe1_logical_op__output_carry$15 - connect \logical_op__rc__ok \logical_pipe1_logical_op__rc__ok - connect \logical_op__rc__ok$7 \logical_pipe1_logical_op__rc__ok$7 - connect \logical_op__rc__rc \logical_pipe1_logical_op__rc__rc - connect \logical_op__rc__rc$6 \logical_pipe1_logical_op__rc__rc$6 - connect \logical_op__write_cr0 \logical_pipe1_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \logical_pipe1_logical_op__write_cr0$14 - connect \logical_op__zero_a \logical_pipe1_logical_op__zero_a - connect \logical_op__zero_a$11 \logical_pipe1_logical_op__zero_a$11 - connect \muxid \logical_pipe1_muxid - connect \muxid$1 \logical_pipe1_muxid$1 - connect \n_ready_i \logical_pipe1_n_ready_i - connect \n_valid_o \logical_pipe1_n_valid_o - connect \o \logical_pipe1_o - connect \o_ok \logical_pipe1_o_ok - connect \p_ready_o \logical_pipe1_p_ready_o - connect \p_valid_i \logical_pipe1_p_valid_i - connect \ra \logical_pipe1_ra - connect \rb \logical_pipe1_rb - connect \xer_so \logical_pipe1_xer_so - connect \xer_so$20 \logical_pipe1_xer_so$20 - connect \xer_so_ok \logical_pipe1_xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:26866.17-26921.4" - cell \logical_pipe2 \logical_pipe2 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \logical_pipe2_cr_a - connect \cr_a$22 \logical_pipe2_cr_a$42 - connect \cr_a_ok \logical_pipe2_cr_a_ok - connect \cr_a_ok$23 \logical_pipe2_cr_a_ok$43 - connect \logical_op__data_len \logical_pipe2_logical_op__data_len - connect \logical_op__data_len$18 \logical_pipe2_logical_op__data_len$38 - connect \logical_op__fn_unit \logical_pipe2_logical_op__fn_unit - connect \logical_op__fn_unit$3 \logical_pipe2_logical_op__fn_unit$23 - connect \logical_op__imm_data__data \logical_pipe2_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \logical_pipe2_logical_op__imm_data__data$24 - connect \logical_op__imm_data__ok \logical_pipe2_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \logical_pipe2_logical_op__imm_data__ok$25 - connect \logical_op__input_carry \logical_pipe2_logical_op__input_carry - connect \logical_op__input_carry$12 \logical_pipe2_logical_op__input_carry$32 - connect \logical_op__insn \logical_pipe2_logical_op__insn - connect \logical_op__insn$19 \logical_pipe2_logical_op__insn$39 - connect \logical_op__insn_type \logical_pipe2_logical_op__insn_type - connect \logical_op__insn_type$2 \logical_pipe2_logical_op__insn_type$22 - connect \logical_op__invert_in \logical_pipe2_logical_op__invert_in - connect \logical_op__invert_in$10 \logical_pipe2_logical_op__invert_in$30 - connect \logical_op__invert_out \logical_pipe2_logical_op__invert_out - connect \logical_op__invert_out$13 \logical_pipe2_logical_op__invert_out$33 - connect \logical_op__is_32bit \logical_pipe2_logical_op__is_32bit - connect \logical_op__is_32bit$16 \logical_pipe2_logical_op__is_32bit$36 - connect \logical_op__is_signed \logical_pipe2_logical_op__is_signed - connect \logical_op__is_signed$17 \logical_pipe2_logical_op__is_signed$37 - connect \logical_op__oe__oe \logical_pipe2_logical_op__oe__oe - connect \logical_op__oe__oe$8 \logical_pipe2_logical_op__oe__oe$28 - connect \logical_op__oe__ok \logical_pipe2_logical_op__oe__ok - connect \logical_op__oe__ok$9 \logical_pipe2_logical_op__oe__ok$29 - connect \logical_op__output_carry \logical_pipe2_logical_op__output_carry - connect \logical_op__output_carry$15 \logical_pipe2_logical_op__output_carry$35 - connect \logical_op__rc__ok \logical_pipe2_logical_op__rc__ok - connect \logical_op__rc__ok$7 \logical_pipe2_logical_op__rc__ok$27 - connect \logical_op__rc__rc \logical_pipe2_logical_op__rc__rc - connect \logical_op__rc__rc$6 \logical_pipe2_logical_op__rc__rc$26 - connect \logical_op__write_cr0 \logical_pipe2_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \logical_pipe2_logical_op__write_cr0$34 - connect \logical_op__zero_a \logical_pipe2_logical_op__zero_a - connect \logical_op__zero_a$11 \logical_pipe2_logical_op__zero_a$31 - connect \muxid \logical_pipe2_muxid - connect \muxid$1 \logical_pipe2_muxid$21 - connect \n_ready_i \logical_pipe2_n_ready_i - connect \n_valid_o \logical_pipe2_n_valid_o - connect \o \logical_pipe2_o - connect \o$20 \logical_pipe2_o$40 - connect \o_ok \logical_pipe2_o_ok - connect \o_ok$21 \logical_pipe2_o_ok$41 - connect \p_ready_o \logical_pipe2_p_ready_o - connect \p_valid_i \logical_pipe2_p_valid_i - connect \xer_so \logical_pipe2_xer_so - connect \xer_so_ok \logical_pipe2_xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:26922.10-26925.4" - cell \n$44 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:26926.10-26929.4" - cell \p$43 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - connect \muxid 2'00 - connect { \cr_a_ok \cr_a } { \logical_pipe2_cr_a_ok$43 \logical_pipe2_cr_a$42 } - connect { \o_ok \o } { \logical_pipe2_o_ok$41 \logical_pipe2_o$40 } - connect { \logical_op__insn$62 \logical_op__data_len$61 \logical_op__is_signed$60 \logical_op__is_32bit$59 \logical_op__output_carry$58 \logical_op__write_cr0$57 \logical_op__invert_out$56 \logical_op__input_carry$55 \logical_op__zero_a$54 \logical_op__invert_in$53 \logical_op__oe__ok$52 \logical_op__oe__oe$51 \logical_op__rc__ok$50 \logical_op__rc__rc$49 \logical_op__imm_data__ok$48 \logical_op__imm_data__data$47 \logical_op__fn_unit$46 \logical_op__insn_type$45 } { \logical_pipe2_logical_op__insn$39 \logical_pipe2_logical_op__data_len$38 \logical_pipe2_logical_op__is_signed$37 \logical_pipe2_logical_op__is_32bit$36 \logical_pipe2_logical_op__output_carry$35 \logical_pipe2_logical_op__write_cr0$34 \logical_pipe2_logical_op__invert_out$33 \logical_pipe2_logical_op__input_carry$32 \logical_pipe2_logical_op__zero_a$31 \logical_pipe2_logical_op__invert_in$30 \logical_pipe2_logical_op__oe__ok$29 \logical_pipe2_logical_op__oe__oe$28 \logical_pipe2_logical_op__rc__ok$27 \logical_pipe2_logical_op__rc__rc$26 \logical_pipe2_logical_op__imm_data__ok$25 \logical_pipe2_logical_op__imm_data__data$24 \logical_pipe2_logical_op__fn_unit$23 \logical_pipe2_logical_op__insn_type$22 } - connect \muxid$44 \logical_pipe2_muxid$21 - connect \logical_pipe2_n_ready_i \n_ready_i - connect \n_valid_o \logical_pipe2_n_valid_o - connect \logical_pipe1_xer_so$20 \xer_so - connect \logical_pipe1_rb \rb - connect \logical_pipe1_ra \ra - connect { \logical_pipe1_logical_op__insn$19 \logical_pipe1_logical_op__data_len$18 \logical_pipe1_logical_op__is_signed$17 \logical_pipe1_logical_op__is_32bit$16 \logical_pipe1_logical_op__output_carry$15 \logical_pipe1_logical_op__write_cr0$14 \logical_pipe1_logical_op__invert_out$13 \logical_pipe1_logical_op__input_carry$12 \logical_pipe1_logical_op__zero_a$11 \logical_pipe1_logical_op__invert_in$10 \logical_pipe1_logical_op__oe__ok$9 \logical_pipe1_logical_op__oe__oe$8 \logical_pipe1_logical_op__rc__ok$7 \logical_pipe1_logical_op__rc__rc$6 \logical_pipe1_logical_op__imm_data__ok$5 \logical_pipe1_logical_op__imm_data__data$4 \logical_pipe1_logical_op__fn_unit$3 \logical_pipe1_logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - connect \logical_pipe1_muxid$1 2'00 - connect \p_ready_o \logical_pipe1_p_ready_o - connect \logical_pipe1_p_valid_i \p_valid_i - connect { \logical_pipe2_xer_so_ok \logical_pipe2_xer_so } { \logical_pipe1_xer_so_ok \logical_pipe1_xer_so } - connect { \logical_pipe2_cr_a_ok \logical_pipe2_cr_a } { \logical_pipe1_cr_a_ok \logical_pipe1_cr_a } - connect { \logical_pipe2_o_ok \logical_pipe2_o } { \logical_pipe1_o_ok \logical_pipe1_o } - connect { \logical_pipe2_logical_op__insn \logical_pipe2_logical_op__data_len \logical_pipe2_logical_op__is_signed \logical_pipe2_logical_op__is_32bit \logical_pipe2_logical_op__output_carry \logical_pipe2_logical_op__write_cr0 \logical_pipe2_logical_op__invert_out \logical_pipe2_logical_op__input_carry \logical_pipe2_logical_op__zero_a \logical_pipe2_logical_op__invert_in \logical_pipe2_logical_op__oe__ok \logical_pipe2_logical_op__oe__oe \logical_pipe2_logical_op__rc__ok \logical_pipe2_logical_op__rc__rc \logical_pipe2_logical_op__imm_data__ok \logical_pipe2_logical_op__imm_data__data \logical_pipe2_logical_op__fn_unit \logical_pipe2_logical_op__insn_type } { \logical_pipe1_logical_op__insn \logical_pipe1_logical_op__data_len \logical_pipe1_logical_op__is_signed \logical_pipe1_logical_op__is_32bit \logical_pipe1_logical_op__output_carry \logical_pipe1_logical_op__write_cr0 \logical_pipe1_logical_op__invert_out \logical_pipe1_logical_op__input_carry \logical_pipe1_logical_op__zero_a \logical_pipe1_logical_op__invert_in \logical_pipe1_logical_op__oe__ok \logical_pipe1_logical_op__oe__oe \logical_pipe1_logical_op__rc__ok \logical_pipe1_logical_op__rc__rc \logical_pipe1_logical_op__imm_data__ok \logical_pipe1_logical_op__imm_data__data \logical_pipe1_logical_op__fn_unit \logical_pipe1_logical_op__insn_type } - connect \logical_pipe2_muxid \logical_pipe1_muxid - connect \logical_pipe1_n_ready_i \logical_pipe2_p_ready_o - connect \logical_pipe2_p_valid_i \logical_pipe1_n_valid_o -end -attribute \src "issuer_ls180.v:26955.1-28148.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0" -attribute \generator "nMigen" -module \alu_mul0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 29 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 21 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \cr_a_ok - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 9 \mul_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_op__fn_unit$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 10 \mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__data$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__imm_data__ok$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 19 \mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_op__insn$61 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 8 \mul_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute 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"OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_32bit$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_signed$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__oe$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__ok$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__ok$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__rc$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__write_cr0$58 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute 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attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_pipe1_mul_op__fn_unit$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe1_mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe1_mul_op__imm_data__data$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__imm_data__ok$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_pipe1_mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_pipe1_mul_op__insn$14 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute 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"OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_pipe1_mul_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute 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\mul_pipe1_mul_op__is_signed$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__oe__oe$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__oe__ok$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__rc__ok$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__rc__rc$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__write_cr0$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul_pipe1_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul_pipe1_muxid$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \mul_pipe1_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \mul_pipe1_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire \mul_pipe1_neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire \mul_pipe1_neg_res32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \mul_pipe1_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \mul_pipe1_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul_pipe1_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul_pipe1_ra$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul_pipe1_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul_pipe1_rb$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \mul_pipe1_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \mul_pipe1_xer_so$17 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute 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\src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_pipe2_mul_op__fn_unit$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe2_mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe2_mul_op__imm_data__data$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__imm_data__ok$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_pipe2_mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_pipe2_mul_op__insn$30 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_pipe2_mul_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_pipe2_mul_op__insn_type$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__is_32bit$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__is_signed$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__oe__oe$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__oe__ok$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__rc__ok$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__rc__rc$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__write_cr0$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul_pipe2_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul_pipe2_muxid$18 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \mul_pipe2_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \mul_pipe2_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire \mul_pipe2_neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire \mul_pipe2_neg_res$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire \mul_pipe2_neg_res32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire \mul_pipe2_neg_res32$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 \mul_pipe2_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \mul_pipe2_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \mul_pipe2_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul_pipe2_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul_pipe2_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \mul_pipe2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \mul_pipe2_xer_so$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \mul_pipe3_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \mul_pipe3_cr_a_ok - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_pipe3_mul_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_pipe3_mul_op__fn_unit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe3_mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe3_mul_op__imm_data__data$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__imm_data__ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_pipe3_mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_pipe3_mul_op__insn$46 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_pipe3_mul_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_pipe3_mul_op__insn_type$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__is_32bit$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__is_signed$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__oe__oe$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__oe__ok$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__rc__ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__rc__rc$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__write_cr0$43 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul_pipe3_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul_pipe3_muxid$34 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \mul_pipe3_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \mul_pipe3_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire \mul_pipe3_neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire \mul_pipe3_neg_res32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 \mul_pipe3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \mul_pipe3_o$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \mul_pipe3_o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \mul_pipe3_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \mul_pipe3_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \mul_pipe3_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \mul_pipe3_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \mul_pipe3_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \mul_pipe3_xer_so$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \mul_pipe3_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$49 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 7 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 6 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 20 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 28 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 27 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 24 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 25 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 22 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 23 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 26 \xer_so$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 4 \xer_so_ok - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:27976.13-28017.4" - cell \mul_pipe1 \mul_pipe1 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \mul_op__fn_unit \mul_pipe1_mul_op__fn_unit - connect \mul_op__fn_unit$3 \mul_pipe1_mul_op__fn_unit$4 - connect \mul_op__imm_data__data \mul_pipe1_mul_op__imm_data__data - connect \mul_op__imm_data__data$4 \mul_pipe1_mul_op__imm_data__data$5 - connect \mul_op__imm_data__ok \mul_pipe1_mul_op__imm_data__ok - connect \mul_op__imm_data__ok$5 \mul_pipe1_mul_op__imm_data__ok$6 - connect \mul_op__insn \mul_pipe1_mul_op__insn - connect \mul_op__insn$13 \mul_pipe1_mul_op__insn$14 - connect \mul_op__insn_type \mul_pipe1_mul_op__insn_type - connect \mul_op__insn_type$2 \mul_pipe1_mul_op__insn_type$3 - connect \mul_op__is_32bit \mul_pipe1_mul_op__is_32bit - connect \mul_op__is_32bit$11 \mul_pipe1_mul_op__is_32bit$12 - connect \mul_op__is_signed \mul_pipe1_mul_op__is_signed - connect \mul_op__is_signed$12 \mul_pipe1_mul_op__is_signed$13 - connect \mul_op__oe__oe \mul_pipe1_mul_op__oe__oe - connect \mul_op__oe__oe$8 \mul_pipe1_mul_op__oe__oe$9 - connect \mul_op__oe__ok \mul_pipe1_mul_op__oe__ok - connect \mul_op__oe__ok$9 \mul_pipe1_mul_op__oe__ok$10 - connect \mul_op__rc__ok \mul_pipe1_mul_op__rc__ok - connect \mul_op__rc__ok$7 \mul_pipe1_mul_op__rc__ok$8 - connect \mul_op__rc__rc \mul_pipe1_mul_op__rc__rc - connect \mul_op__rc__rc$6 \mul_pipe1_mul_op__rc__rc$7 - connect \mul_op__write_cr0 \mul_pipe1_mul_op__write_cr0 - connect \mul_op__write_cr0$10 \mul_pipe1_mul_op__write_cr0$11 - connect \muxid \mul_pipe1_muxid - connect \muxid$1 \mul_pipe1_muxid$2 - connect \n_ready_i \mul_pipe1_n_ready_i - connect \n_valid_o \mul_pipe1_n_valid_o - connect \neg_res \mul_pipe1_neg_res - connect \neg_res32 \mul_pipe1_neg_res32 - connect \p_ready_o \mul_pipe1_p_ready_o - connect \p_valid_i \mul_pipe1_p_valid_i - connect \ra \mul_pipe1_ra - connect \ra$14 \mul_pipe1_ra$15 - connect \rb \mul_pipe1_rb - connect \rb$15 \mul_pipe1_rb$16 - connect \xer_so \mul_pipe1_xer_so - connect \xer_so$16 \mul_pipe1_xer_so$17 + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub11_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub11_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub11_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub11_upd + attribute \src "libresoc.v:19939.7-19939.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:19939.7-19939.20" + process $proc$libresoc.v:19939$441 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:28018.13-28060.4" - cell \mul_pipe2 \mul_pipe2 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \mul_op__fn_unit \mul_pipe2_mul_op__fn_unit - connect \mul_op__fn_unit$3 \mul_pipe2_mul_op__fn_unit$20 - connect \mul_op__imm_data__data \mul_pipe2_mul_op__imm_data__data - connect \mul_op__imm_data__data$4 \mul_pipe2_mul_op__imm_data__data$21 - connect \mul_op__imm_data__ok \mul_pipe2_mul_op__imm_data__ok - connect \mul_op__imm_data__ok$5 \mul_pipe2_mul_op__imm_data__ok$22 - connect \mul_op__insn \mul_pipe2_mul_op__insn - connect \mul_op__insn$13 \mul_pipe2_mul_op__insn$30 - connect \mul_op__insn_type \mul_pipe2_mul_op__insn_type - connect \mul_op__insn_type$2 \mul_pipe2_mul_op__insn_type$19 - connect \mul_op__is_32bit \mul_pipe2_mul_op__is_32bit - connect \mul_op__is_32bit$11 \mul_pipe2_mul_op__is_32bit$28 - connect \mul_op__is_signed \mul_pipe2_mul_op__is_signed - connect \mul_op__is_signed$12 \mul_pipe2_mul_op__is_signed$29 - connect \mul_op__oe__oe \mul_pipe2_mul_op__oe__oe - connect \mul_op__oe__oe$8 \mul_pipe2_mul_op__oe__oe$25 - connect \mul_op__oe__ok \mul_pipe2_mul_op__oe__ok - connect \mul_op__oe__ok$9 \mul_pipe2_mul_op__oe__ok$26 - connect \mul_op__rc__ok \mul_pipe2_mul_op__rc__ok - connect \mul_op__rc__ok$7 \mul_pipe2_mul_op__rc__ok$24 - connect \mul_op__rc__rc \mul_pipe2_mul_op__rc__rc - connect \mul_op__rc__rc$6 \mul_pipe2_mul_op__rc__rc$23 - connect \mul_op__write_cr0 \mul_pipe2_mul_op__write_cr0 - connect \mul_op__write_cr0$10 \mul_pipe2_mul_op__write_cr0$27 - connect \muxid \mul_pipe2_muxid - connect \muxid$1 \mul_pipe2_muxid$18 - connect \n_ready_i \mul_pipe2_n_ready_i - connect \n_valid_o \mul_pipe2_n_valid_o - connect \neg_res \mul_pipe2_neg_res - connect \neg_res$15 \mul_pipe2_neg_res$32 - connect \neg_res32 \mul_pipe2_neg_res32 - connect \neg_res32$16 \mul_pipe2_neg_res32$33 - connect \o \mul_pipe2_o - connect \p_ready_o \mul_pipe2_p_ready_o - connect \p_valid_i \mul_pipe2_p_valid_i - connect \ra \mul_pipe2_ra - connect \rb \mul_pipe2_rb - connect \xer_so \mul_pipe2_xer_so - connect \xer_so$14 \mul_pipe2_xer_so$31 + attribute \src "libresoc.v:20196.3-20250.6" + process $proc$libresoc.v:20196$417 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_function_unit[11:0] $1\dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:20197.5-20197.29" + switch \initial + attribute \src "libresoc.v:20197.9-20197.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + case + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[11:0] end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:28061.13-28106.4" - cell \mul_pipe3 \mul_pipe3 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \mul_pipe3_cr_a - connect \cr_a_ok \mul_pipe3_cr_a_ok - connect \mul_op__fn_unit \mul_pipe3_mul_op__fn_unit - connect \mul_op__fn_unit$3 \mul_pipe3_mul_op__fn_unit$36 - connect \mul_op__imm_data__data \mul_pipe3_mul_op__imm_data__data - connect \mul_op__imm_data__data$4 \mul_pipe3_mul_op__imm_data__data$37 - connect \mul_op__imm_data__ok \mul_pipe3_mul_op__imm_data__ok - connect \mul_op__imm_data__ok$5 \mul_pipe3_mul_op__imm_data__ok$38 - connect \mul_op__insn \mul_pipe3_mul_op__insn - connect \mul_op__insn$13 \mul_pipe3_mul_op__insn$46 - connect \mul_op__insn_type \mul_pipe3_mul_op__insn_type - connect \mul_op__insn_type$2 \mul_pipe3_mul_op__insn_type$35 - connect \mul_op__is_32bit \mul_pipe3_mul_op__is_32bit - connect \mul_op__is_32bit$11 \mul_pipe3_mul_op__is_32bit$44 - connect \mul_op__is_signed \mul_pipe3_mul_op__is_signed - connect \mul_op__is_signed$12 \mul_pipe3_mul_op__is_signed$45 - connect \mul_op__oe__oe \mul_pipe3_mul_op__oe__oe - connect \mul_op__oe__oe$8 \mul_pipe3_mul_op__oe__oe$41 - connect \mul_op__oe__ok \mul_pipe3_mul_op__oe__ok - connect \mul_op__oe__ok$9 \mul_pipe3_mul_op__oe__ok$42 - connect \mul_op__rc__ok \mul_pipe3_mul_op__rc__ok - connect \mul_op__rc__ok$7 \mul_pipe3_mul_op__rc__ok$40 - connect \mul_op__rc__rc \mul_pipe3_mul_op__rc__rc - connect \mul_op__rc__rc$6 \mul_pipe3_mul_op__rc__rc$39 - connect \mul_op__write_cr0 \mul_pipe3_mul_op__write_cr0 - connect \mul_op__write_cr0$10 \mul_pipe3_mul_op__write_cr0$43 - connect \muxid \mul_pipe3_muxid - connect \muxid$1 \mul_pipe3_muxid$34 - connect \n_ready_i \mul_pipe3_n_ready_i - connect \n_valid_o \mul_pipe3_n_valid_o - connect \neg_res \mul_pipe3_neg_res - connect \neg_res32 \mul_pipe3_neg_res32 - connect \o \mul_pipe3_o - connect \o$14 \mul_pipe3_o$47 - connect \o_ok \mul_pipe3_o_ok - connect \p_ready_o \mul_pipe3_p_ready_o - connect \p_valid_i \mul_pipe3_p_valid_i - connect \xer_ov \mul_pipe3_xer_ov - connect \xer_ov_ok \mul_pipe3_xer_ov_ok - connect \xer_so \mul_pipe3_xer_so - connect \xer_so$15 \mul_pipe3_xer_so$48 - connect \xer_so_ok \mul_pipe3_xer_so_ok + attribute \src "libresoc.v:20251.3-20305.6" + process $proc$libresoc.v:20251$418 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:20252.5-20252.29" + switch \initial + attribute \src "libresoc.v:20252.9-20252.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0] end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:28107.10-28110.4" - cell \n$89 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o + attribute \src "libresoc.v:20306.3-20360.6" + process $proc$libresoc.v:20306$419 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] + attribute \src "libresoc.v:20307.5-20307.29" + switch \initial + attribute \src "libresoc.v:20307.9-20307.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:28111.10-28114.4" - cell \p$88 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - connect \muxid 2'00 - connect { \xer_so_ok \xer_so } { \mul_pipe3_xer_so_ok \mul_pipe3_xer_so$48 } - connect { \xer_ov_ok \xer_ov } { \mul_pipe3_xer_ov_ok \mul_pipe3_xer_ov } - connect { \cr_a_ok \cr_a } { \mul_pipe3_cr_a_ok \mul_pipe3_cr_a } - connect { \o_ok \o } { \mul_pipe3_o_ok \mul_pipe3_o$47 } - connect { \mul_op__insn$61 \mul_op__is_signed$60 \mul_op__is_32bit$59 \mul_op__write_cr0$58 \mul_op__oe__ok$57 \mul_op__oe__oe$56 \mul_op__rc__ok$55 \mul_op__rc__rc$54 \mul_op__imm_data__ok$53 \mul_op__imm_data__data$52 \mul_op__fn_unit$51 \mul_op__insn_type$50 } { \mul_pipe3_mul_op__insn$46 \mul_pipe3_mul_op__is_signed$45 \mul_pipe3_mul_op__is_32bit$44 \mul_pipe3_mul_op__write_cr0$43 \mul_pipe3_mul_op__oe__ok$42 \mul_pipe3_mul_op__oe__oe$41 \mul_pipe3_mul_op__rc__ok$40 \mul_pipe3_mul_op__rc__rc$39 \mul_pipe3_mul_op__imm_data__ok$38 \mul_pipe3_mul_op__imm_data__data$37 \mul_pipe3_mul_op__fn_unit$36 \mul_pipe3_mul_op__insn_type$35 } - connect \muxid$49 \mul_pipe3_muxid$34 - connect \mul_pipe3_n_ready_i \n_ready_i - connect \n_valid_o \mul_pipe3_n_valid_o - connect \mul_pipe1_xer_so$17 \xer_so$1 - connect \mul_pipe1_rb$16 \rb - connect \mul_pipe1_ra$15 \ra - connect { \mul_pipe1_mul_op__insn$14 \mul_pipe1_mul_op__is_signed$13 \mul_pipe1_mul_op__is_32bit$12 \mul_pipe1_mul_op__write_cr0$11 \mul_pipe1_mul_op__oe__ok$10 \mul_pipe1_mul_op__oe__oe$9 \mul_pipe1_mul_op__rc__ok$8 \mul_pipe1_mul_op__rc__rc$7 \mul_pipe1_mul_op__imm_data__ok$6 \mul_pipe1_mul_op__imm_data__data$5 \mul_pipe1_mul_op__fn_unit$4 \mul_pipe1_mul_op__insn_type$3 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } - connect \mul_pipe1_muxid$2 2'00 - connect \p_ready_o \mul_pipe1_p_ready_o - connect \mul_pipe1_p_valid_i \p_valid_i - connect \mul_pipe3_neg_res32 \mul_pipe2_neg_res32$33 - connect \mul_pipe3_neg_res \mul_pipe2_neg_res$32 - connect \mul_pipe3_xer_so \mul_pipe2_xer_so$31 - connect \mul_pipe3_o \mul_pipe2_o - connect { \mul_pipe3_mul_op__insn \mul_pipe3_mul_op__is_signed \mul_pipe3_mul_op__is_32bit \mul_pipe3_mul_op__write_cr0 \mul_pipe3_mul_op__oe__ok \mul_pipe3_mul_op__oe__oe \mul_pipe3_mul_op__rc__ok \mul_pipe3_mul_op__rc__rc \mul_pipe3_mul_op__imm_data__ok \mul_pipe3_mul_op__imm_data__data \mul_pipe3_mul_op__fn_unit \mul_pipe3_mul_op__insn_type } { \mul_pipe2_mul_op__insn$30 \mul_pipe2_mul_op__is_signed$29 \mul_pipe2_mul_op__is_32bit$28 \mul_pipe2_mul_op__write_cr0$27 \mul_pipe2_mul_op__oe__ok$26 \mul_pipe2_mul_op__oe__oe$25 \mul_pipe2_mul_op__rc__ok$24 \mul_pipe2_mul_op__rc__rc$23 \mul_pipe2_mul_op__imm_data__ok$22 \mul_pipe2_mul_op__imm_data__data$21 \mul_pipe2_mul_op__fn_unit$20 \mul_pipe2_mul_op__insn_type$19 } - connect \mul_pipe3_muxid \mul_pipe2_muxid$18 - connect \mul_pipe2_n_ready_i \mul_pipe3_p_ready_o - connect \mul_pipe3_p_valid_i \mul_pipe2_n_valid_o - connect \mul_pipe2_neg_res32 \mul_pipe1_neg_res32 - connect \mul_pipe2_neg_res \mul_pipe1_neg_res - connect \mul_pipe2_xer_so \mul_pipe1_xer_so - connect \mul_pipe2_rb \mul_pipe1_rb - connect \mul_pipe2_ra \mul_pipe1_ra - connect { \mul_pipe2_mul_op__insn \mul_pipe2_mul_op__is_signed \mul_pipe2_mul_op__is_32bit \mul_pipe2_mul_op__write_cr0 \mul_pipe2_mul_op__oe__ok \mul_pipe2_mul_op__oe__oe \mul_pipe2_mul_op__rc__ok \mul_pipe2_mul_op__rc__rc \mul_pipe2_mul_op__imm_data__ok \mul_pipe2_mul_op__imm_data__data \mul_pipe2_mul_op__fn_unit \mul_pipe2_mul_op__insn_type } { \mul_pipe1_mul_op__insn \mul_pipe1_mul_op__is_signed \mul_pipe1_mul_op__is_32bit \mul_pipe1_mul_op__write_cr0 \mul_pipe1_mul_op__oe__ok \mul_pipe1_mul_op__oe__oe \mul_pipe1_mul_op__rc__ok \mul_pipe1_mul_op__rc__rc \mul_pipe1_mul_op__imm_data__ok \mul_pipe1_mul_op__imm_data__data \mul_pipe1_mul_op__fn_unit \mul_pipe1_mul_op__insn_type } - connect \mul_pipe2_muxid \mul_pipe1_muxid - connect \mul_pipe1_n_ready_i \mul_pipe2_p_ready_o - connect \mul_pipe2_p_valid_i \mul_pipe1_n_valid_o -end -attribute \src "issuer_ls180.v:28152.1-29151.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0" -attribute \generator "nMigen" -module \alu_shift_rot0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 33 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 4 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 24 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$44 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 6 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 5 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 23 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 32 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 31 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \pipe1_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe1_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe1_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe1_muxid$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \pipe1_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \pipe1_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe1_o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \pipe1_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \pipe1_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe1_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe1_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe1_rc - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe1_sr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe1_sr_op__fn_unit$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe1_sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe1_sr_op__imm_data__data$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_sr_op__imm_data__ok$6 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe1_sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe1_sr_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_sr_op__input_cr$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe1_sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe1_sr_op__insn$18 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe1_sr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - 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\pipe2_sr_op__oe__ok$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__output_carry$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__output_cr$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__rc__ok$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__rc__rc$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__write_cr0$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe2_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe2_xer_ca$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe2_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe2_xer_ca_ok$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe2_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 26 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 27 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 28 \rc - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 8 \sr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \sr_op__fn_unit$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 9 \sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__data$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__imm_data__ok$48 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 16 \sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__input_cr$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$60 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 7 \sr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_32bit$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 21 \sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_signed$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__oe$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__ok$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_carry$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_cr$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__ok$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__rc$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \sr_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__write_cr0$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 25 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 30 \xer_ca$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 29 \xer_so - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:29007.11-29010.4" - cell \n$106 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o + attribute \src "libresoc.v:20361.3-20415.6" + process $proc$libresoc.v:20361$420 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:20362.5-20362.29" + switch \initial + attribute \src "libresoc.v:20362.9-20362.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0] end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:29011.11-29014.4" - cell \p$105 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i + attribute \src "libresoc.v:20416.3-20470.6" + process $proc$libresoc.v:20416$421 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:20417.5-20417.29" + switch \initial + attribute \src "libresoc.v:20417.9-20417.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0] end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:29015.15-29069.4" - cell \pipe1$107 \pipe1 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \pipe1_cr_a - connect \cr_a_ok \pipe1_cr_a_ok - connect \muxid \pipe1_muxid - connect \muxid$1 \pipe1_muxid$2 - connect \n_ready_i \pipe1_n_ready_i - connect \n_valid_o \pipe1_n_valid_o - connect \o \pipe1_o - connect \o_ok \pipe1_o_ok - connect \p_ready_o \pipe1_p_ready_o - connect \p_valid_i \pipe1_p_valid_i - connect \ra \pipe1_ra - connect \rb \pipe1_rb - connect \rc \pipe1_rc - connect \sr_op__fn_unit \pipe1_sr_op__fn_unit - connect \sr_op__fn_unit$3 \pipe1_sr_op__fn_unit$4 - connect \sr_op__imm_data__data \pipe1_sr_op__imm_data__data - connect \sr_op__imm_data__data$4 \pipe1_sr_op__imm_data__data$5 - connect \sr_op__imm_data__ok \pipe1_sr_op__imm_data__ok - connect \sr_op__imm_data__ok$5 \pipe1_sr_op__imm_data__ok$6 - connect \sr_op__input_carry \pipe1_sr_op__input_carry - connect \sr_op__input_carry$11 \pipe1_sr_op__input_carry$12 - connect \sr_op__input_cr \pipe1_sr_op__input_cr - connect \sr_op__input_cr$13 \pipe1_sr_op__input_cr$14 - connect \sr_op__insn \pipe1_sr_op__insn - connect \sr_op__insn$17 \pipe1_sr_op__insn$18 - connect \sr_op__insn_type \pipe1_sr_op__insn_type - connect \sr_op__insn_type$2 \pipe1_sr_op__insn_type$3 - connect \sr_op__is_32bit \pipe1_sr_op__is_32bit - connect \sr_op__is_32bit$15 \pipe1_sr_op__is_32bit$16 - connect \sr_op__is_signed \pipe1_sr_op__is_signed - connect \sr_op__is_signed$16 \pipe1_sr_op__is_signed$17 - connect \sr_op__oe__oe \pipe1_sr_op__oe__oe - connect \sr_op__oe__oe$8 \pipe1_sr_op__oe__oe$9 - connect \sr_op__oe__ok \pipe1_sr_op__oe__ok - connect \sr_op__oe__ok$9 \pipe1_sr_op__oe__ok$10 - connect \sr_op__output_carry \pipe1_sr_op__output_carry - connect \sr_op__output_carry$12 \pipe1_sr_op__output_carry$13 - connect \sr_op__output_cr \pipe1_sr_op__output_cr - connect \sr_op__output_cr$14 \pipe1_sr_op__output_cr$15 - connect \sr_op__rc__ok \pipe1_sr_op__rc__ok - connect \sr_op__rc__ok$7 \pipe1_sr_op__rc__ok$8 - connect \sr_op__rc__rc \pipe1_sr_op__rc__rc - connect \sr_op__rc__rc$6 \pipe1_sr_op__rc__rc$7 - connect \sr_op__write_cr0 \pipe1_sr_op__write_cr0 - connect \sr_op__write_cr0$10 \pipe1_sr_op__write_cr0$11 - connect \xer_ca \pipe1_xer_ca - connect \xer_ca$19 \pipe1_xer_ca$20 - connect \xer_ca_ok \pipe1_xer_ca_ok - connect \xer_so \pipe1_xer_so - connect \xer_so$18 \pipe1_xer_so$19 - connect \xer_so_ok \pipe1_xer_so_ok + attribute \src "libresoc.v:20471.3-20525.6" + process $proc$libresoc.v:20471$422 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:20472.5-20472.29" + switch \initial + attribute \src "libresoc.v:20472.9-20472.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000010 + case + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0] end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:29070.15-29125.4" - cell \pipe2$112 \pipe2 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \pipe2_cr_a - connect \cr_a$20 \pipe2_cr_a$40 - connect \cr_a_ok \pipe2_cr_a_ok - connect \cr_a_ok$21 \pipe2_cr_a_ok$41 - connect \muxid \pipe2_muxid - connect \muxid$1 \pipe2_muxid$21 - connect \n_ready_i \pipe2_n_ready_i - connect \n_valid_o \pipe2_n_valid_o - connect \o \pipe2_o - connect \o$18 \pipe2_o$38 - connect \o_ok \pipe2_o_ok - connect \o_ok$19 \pipe2_o_ok$39 - connect \p_ready_o \pipe2_p_ready_o - connect \p_valid_i \pipe2_p_valid_i - connect \sr_op__fn_unit \pipe2_sr_op__fn_unit - connect \sr_op__fn_unit$3 \pipe2_sr_op__fn_unit$23 - connect \sr_op__imm_data__data \pipe2_sr_op__imm_data__data - connect \sr_op__imm_data__data$4 \pipe2_sr_op__imm_data__data$24 - connect \sr_op__imm_data__ok \pipe2_sr_op__imm_data__ok - connect \sr_op__imm_data__ok$5 \pipe2_sr_op__imm_data__ok$25 - connect \sr_op__input_carry \pipe2_sr_op__input_carry - connect \sr_op__input_carry$11 \pipe2_sr_op__input_carry$31 - connect \sr_op__input_cr \pipe2_sr_op__input_cr - connect \sr_op__input_cr$13 \pipe2_sr_op__input_cr$33 - connect \sr_op__insn \pipe2_sr_op__insn - connect \sr_op__insn$17 \pipe2_sr_op__insn$37 - connect \sr_op__insn_type \pipe2_sr_op__insn_type - connect \sr_op__insn_type$2 \pipe2_sr_op__insn_type$22 - connect \sr_op__is_32bit \pipe2_sr_op__is_32bit - connect \sr_op__is_32bit$15 \pipe2_sr_op__is_32bit$35 - connect \sr_op__is_signed \pipe2_sr_op__is_signed - connect \sr_op__is_signed$16 \pipe2_sr_op__is_signed$36 - connect \sr_op__oe__oe \pipe2_sr_op__oe__oe - connect \sr_op__oe__oe$8 \pipe2_sr_op__oe__oe$28 - connect \sr_op__oe__ok \pipe2_sr_op__oe__ok - connect \sr_op__oe__ok$9 \pipe2_sr_op__oe__ok$29 - connect \sr_op__output_carry \pipe2_sr_op__output_carry - connect \sr_op__output_carry$12 \pipe2_sr_op__output_carry$32 - connect \sr_op__output_cr \pipe2_sr_op__output_cr - connect \sr_op__output_cr$14 \pipe2_sr_op__output_cr$34 - connect \sr_op__rc__ok \pipe2_sr_op__rc__ok - connect \sr_op__rc__ok$7 \pipe2_sr_op__rc__ok$27 - connect \sr_op__rc__rc \pipe2_sr_op__rc__rc - connect \sr_op__rc__rc$6 \pipe2_sr_op__rc__rc$26 - connect \sr_op__write_cr0 \pipe2_sr_op__write_cr0 - connect \sr_op__write_cr0$10 \pipe2_sr_op__write_cr0$30 - connect \xer_ca \pipe2_xer_ca - connect \xer_ca$22 \pipe2_xer_ca$42 - connect \xer_ca_ok \pipe2_xer_ca_ok - connect \xer_ca_ok$23 \pipe2_xer_ca_ok$43 - connect \xer_so \pipe2_xer_so - connect \xer_so_ok \pipe2_xer_so_ok - end - connect \muxid 2'00 - connect { \xer_ca_ok \xer_ca } { \pipe2_xer_ca_ok$43 \pipe2_xer_ca$42 } - connect { \cr_a_ok \cr_a } { \pipe2_cr_a_ok$41 \pipe2_cr_a$40 } - connect { \o_ok \o } { \pipe2_o_ok$39 \pipe2_o$38 } - connect { \sr_op__insn$60 \sr_op__is_signed$59 \sr_op__is_32bit$58 \sr_op__output_cr$57 \sr_op__input_cr$56 \sr_op__output_carry$55 \sr_op__input_carry$54 \sr_op__write_cr0$53 \sr_op__oe__ok$52 \sr_op__oe__oe$51 \sr_op__rc__ok$50 \sr_op__rc__rc$49 \sr_op__imm_data__ok$48 \sr_op__imm_data__data$47 \sr_op__fn_unit$46 \sr_op__insn_type$45 } { \pipe2_sr_op__insn$37 \pipe2_sr_op__is_signed$36 \pipe2_sr_op__is_32bit$35 \pipe2_sr_op__output_cr$34 \pipe2_sr_op__input_cr$33 \pipe2_sr_op__output_carry$32 \pipe2_sr_op__input_carry$31 \pipe2_sr_op__write_cr0$30 \pipe2_sr_op__oe__ok$29 \pipe2_sr_op__oe__oe$28 \pipe2_sr_op__rc__ok$27 \pipe2_sr_op__rc__rc$26 \pipe2_sr_op__imm_data__ok$25 \pipe2_sr_op__imm_data__data$24 \pipe2_sr_op__fn_unit$23 \pipe2_sr_op__insn_type$22 } - connect \muxid$44 \pipe2_muxid$21 - connect \pipe2_n_ready_i \n_ready_i - connect \n_valid_o \pipe2_n_valid_o - connect \pipe1_xer_ca$20 \xer_ca$1 - connect \pipe1_xer_so$19 \xer_so - connect \pipe1_rc \rc - connect \pipe1_rb \rb - connect \pipe1_ra \ra - connect { \pipe1_sr_op__insn$18 \pipe1_sr_op__is_signed$17 \pipe1_sr_op__is_32bit$16 \pipe1_sr_op__output_cr$15 \pipe1_sr_op__input_cr$14 \pipe1_sr_op__output_carry$13 \pipe1_sr_op__input_carry$12 \pipe1_sr_op__write_cr0$11 \pipe1_sr_op__oe__ok$10 \pipe1_sr_op__oe__oe$9 \pipe1_sr_op__rc__ok$8 \pipe1_sr_op__rc__rc$7 \pipe1_sr_op__imm_data__ok$6 \pipe1_sr_op__imm_data__data$5 \pipe1_sr_op__fn_unit$4 \pipe1_sr_op__insn_type$3 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } - connect \pipe1_muxid$2 2'00 - connect \p_ready_o \pipe1_p_ready_o - connect \pipe1_p_valid_i \p_valid_i - connect { \pipe2_xer_ca_ok \pipe2_xer_ca } { \pipe1_xer_ca_ok \pipe1_xer_ca } - connect { \pipe2_xer_so_ok \pipe2_xer_so } { \pipe1_xer_so_ok \pipe1_xer_so } - connect { \pipe2_cr_a_ok \pipe2_cr_a } { \pipe1_cr_a_ok \pipe1_cr_a } - connect { \pipe2_o_ok \pipe2_o } { \pipe1_o_ok \pipe1_o } - connect { \pipe2_sr_op__insn \pipe2_sr_op__is_signed \pipe2_sr_op__is_32bit \pipe2_sr_op__output_cr \pipe2_sr_op__input_cr \pipe2_sr_op__output_carry \pipe2_sr_op__input_carry \pipe2_sr_op__write_cr0 \pipe2_sr_op__oe__ok \pipe2_sr_op__oe__oe \pipe2_sr_op__rc__ok \pipe2_sr_op__rc__rc \pipe2_sr_op__imm_data__ok \pipe2_sr_op__imm_data__data \pipe2_sr_op__fn_unit \pipe2_sr_op__insn_type } { \pipe1_sr_op__insn \pipe1_sr_op__is_signed \pipe1_sr_op__is_32bit \pipe1_sr_op__output_cr \pipe1_sr_op__input_cr \pipe1_sr_op__output_carry \pipe1_sr_op__input_carry \pipe1_sr_op__write_cr0 \pipe1_sr_op__oe__ok \pipe1_sr_op__oe__oe \pipe1_sr_op__rc__ok \pipe1_sr_op__rc__rc \pipe1_sr_op__imm_data__ok \pipe1_sr_op__imm_data__data \pipe1_sr_op__fn_unit \pipe1_sr_op__insn_type } - connect \pipe2_muxid \pipe1_muxid - connect \pipe1_n_ready_i \pipe2_p_ready_o - connect \pipe2_p_valid_i \pipe1_n_valid_o -end -attribute \src "issuer_ls180.v:29155.1-29701.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0" -attribute \generator "nMigen" -module \alu_spr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 28 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 7 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 16 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 22 \fast1$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 5 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 9 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 8 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 14 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 27 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 26 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_fast1$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe_fast1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid$6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \pipe_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \pipe_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe_o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \pipe_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \pipe_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_spr1$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe_spr1_ok - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_spr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_spr_op__fn_unit$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_spr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_spr_op__insn$9 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_spr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_spr_op__insn_type$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_spr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_spr_op__is_32bit$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \pipe_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe_xer_ca$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \pipe_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe_xer_ov$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \pipe_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe_xer_so$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 15 \spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 21 \spr1$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 6 \spr1_ok - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 11 \spr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \spr_op__fn_unit$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 12 \spr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \spr_op__insn$19 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 10 \spr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \spr_op__insn_type$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \spr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \spr_op__is_32bit$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 19 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 25 \xer_ca$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 18 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 24 \xer_ov$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 17 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 23 \xer_so$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 4 \xer_so_ok - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:29636.10-29639.4" - cell \n$60 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:29640.10-29643.4" - cell \p$59 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:29644.13-29679.4" - cell \pipe$61 \pipe - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \fast1 \pipe_fast1 - connect \fast1$7 \pipe_fast1$12 - connect \fast1_ok \pipe_fast1_ok - connect \muxid \pipe_muxid - connect \muxid$1 \pipe_muxid$6 - connect \n_ready_i \pipe_n_ready_i - connect \n_valid_o \pipe_n_valid_o - connect \o \pipe_o - connect \o_ok \pipe_o_ok - connect \p_ready_o \pipe_p_ready_o - connect \p_valid_i \pipe_p_valid_i - connect \ra \pipe_ra - connect \spr1 \pipe_spr1 - connect \spr1$6 \pipe_spr1$11 - connect \spr1_ok \pipe_spr1_ok - connect \spr_op__fn_unit \pipe_spr_op__fn_unit - connect \spr_op__fn_unit$3 \pipe_spr_op__fn_unit$8 - connect \spr_op__insn \pipe_spr_op__insn - connect \spr_op__insn$4 \pipe_spr_op__insn$9 - connect \spr_op__insn_type \pipe_spr_op__insn_type - connect \spr_op__insn_type$2 \pipe_spr_op__insn_type$7 - connect \spr_op__is_32bit \pipe_spr_op__is_32bit - connect \spr_op__is_32bit$5 \pipe_spr_op__is_32bit$10 - connect \xer_ca \pipe_xer_ca - connect \xer_ca$10 \pipe_xer_ca$15 - connect \xer_ca_ok \pipe_xer_ca_ok - connect \xer_ov \pipe_xer_ov - connect \xer_ov$9 \pipe_xer_ov$14 - connect \xer_ov_ok \pipe_xer_ov_ok - connect \xer_so \pipe_xer_so - connect \xer_so$8 \pipe_xer_so$13 - connect \xer_so_ok \pipe_xer_so_ok - end - connect \muxid 2'00 - connect { \xer_ca_ok \xer_ca } { \pipe_xer_ca_ok \pipe_xer_ca$15 } - connect { \xer_ov_ok \xer_ov } { \pipe_xer_ov_ok \pipe_xer_ov$14 } - connect { \xer_so_ok \xer_so } { \pipe_xer_so_ok \pipe_xer_so$13 } - connect { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } - connect { \spr1_ok \spr1 } { \pipe_spr1_ok \pipe_spr1$11 } - connect { \o_ok \o } { \pipe_o_ok \pipe_o } - connect { \spr_op__is_32bit$20 \spr_op__insn$19 \spr_op__fn_unit$18 \spr_op__insn_type$17 } { \pipe_spr_op__is_32bit$10 \pipe_spr_op__insn$9 \pipe_spr_op__fn_unit$8 \pipe_spr_op__insn_type$7 } - connect \muxid$16 \pipe_muxid$6 - connect \pipe_n_ready_i \n_ready_i - connect \n_valid_o \pipe_n_valid_o - connect \pipe_xer_ca \xer_ca$5 - connect \pipe_xer_ov \xer_ov$4 - connect \pipe_xer_so \xer_so$3 - connect \pipe_fast1 \fast1$2 - connect \pipe_spr1 \spr1$1 - connect \pipe_ra \ra - connect { \pipe_spr_op__is_32bit \pipe_spr_op__insn \pipe_spr_op__fn_unit \pipe_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } - connect \pipe_muxid 2'00 - connect \p_ready_o \pipe_p_ready_o - connect \pipe_p_valid_i \p_valid_i -end -attribute \src "issuer_ls180.v:29705.1-30268.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0" -attribute \generator "nMigen" -module \alu_trap0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 28 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 6 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 18 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 24 \fast1$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 19 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 25 \fast2$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 21 \msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 5 \msr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 8 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 7 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 20 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 4 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 17 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 27 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 26 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_fast1$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_fast2$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe_msr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \pipe_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \pipe_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe_nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe_o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \pipe_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \pipe_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_trap_op__cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_trap_op__cia$8 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_trap_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_trap_op__fn_unit$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_trap_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_trap_op__insn$6 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_trap_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_trap_op__insn_type$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_trap_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_trap_op__is_32bit$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_trap_op__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_trap_op__msr$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe_trap_op__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe_trap_op__trapaddr$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_trap_op__traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_trap_op__traptype$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 22 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 23 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 13 \trap_op__cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__cia$19 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 10 \trap_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \trap_op__fn_unit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 11 \trap_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \trap_op__insn$17 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 9 \trap_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__insn_type$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \trap_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \trap_op__is_32bit$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 12 \trap_op__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__msr$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 16 \trap_op__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__trapaddr$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 15 \trap_op__traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__traptype$21 - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:30202.10-30205.4" - cell \n$31 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:30206.10-30209.4" - cell \p$30 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:30210.13-30249.4" - cell \pipe$32 \pipe - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \fast1 \pipe_fast1 - connect \fast1$10 \pipe_fast1$12 - connect \fast1_ok \pipe_fast1_ok - connect \fast2 \pipe_fast2 - connect \fast2$11 \pipe_fast2$13 - connect \fast2_ok \pipe_fast2_ok - connect \msr \pipe_msr - connect \msr_ok \pipe_msr_ok - connect \muxid \pipe_muxid - connect \muxid$1 \pipe_muxid$3 - connect \n_ready_i \pipe_n_ready_i - connect \n_valid_o \pipe_n_valid_o - connect \nia \pipe_nia - connect \nia_ok \pipe_nia_ok - connect \o \pipe_o - connect \o_ok \pipe_o_ok - connect \p_ready_o \pipe_p_ready_o - connect \p_valid_i \pipe_p_valid_i - connect \ra \pipe_ra - connect \rb \pipe_rb - connect \trap_op__cia \pipe_trap_op__cia - connect \trap_op__cia$6 \pipe_trap_op__cia$8 - connect \trap_op__fn_unit \pipe_trap_op__fn_unit - connect \trap_op__fn_unit$3 \pipe_trap_op__fn_unit$5 - connect \trap_op__insn \pipe_trap_op__insn - connect \trap_op__insn$4 \pipe_trap_op__insn$6 - connect \trap_op__insn_type \pipe_trap_op__insn_type - connect \trap_op__insn_type$2 \pipe_trap_op__insn_type$4 - connect \trap_op__is_32bit \pipe_trap_op__is_32bit - connect \trap_op__is_32bit$7 \pipe_trap_op__is_32bit$9 - connect \trap_op__msr \pipe_trap_op__msr - connect \trap_op__msr$5 \pipe_trap_op__msr$7 - connect \trap_op__trapaddr \pipe_trap_op__trapaddr - connect \trap_op__trapaddr$9 \pipe_trap_op__trapaddr$11 - connect \trap_op__traptype \pipe_trap_op__traptype - connect \trap_op__traptype$8 \pipe_trap_op__traptype$10 - end - connect \muxid 2'00 - connect { \msr_ok \msr } { \pipe_msr_ok \pipe_msr } - connect { \nia_ok \nia } { \pipe_nia_ok \pipe_nia } - connect { \fast2_ok \fast2 } { \pipe_fast2_ok \pipe_fast2$13 } - connect { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } - connect { \o_ok \o } { \pipe_o_ok \pipe_o } - connect { \trap_op__trapaddr$22 \trap_op__traptype$21 \trap_op__is_32bit$20 \trap_op__cia$19 \trap_op__msr$18 \trap_op__insn$17 \trap_op__fn_unit$16 \trap_op__insn_type$15 } { \pipe_trap_op__trapaddr$11 \pipe_trap_op__traptype$10 \pipe_trap_op__is_32bit$9 \pipe_trap_op__cia$8 \pipe_trap_op__msr$7 \pipe_trap_op__insn$6 \pipe_trap_op__fn_unit$5 \pipe_trap_op__insn_type$4 } - connect \muxid$14 \pipe_muxid$3 - connect \pipe_n_ready_i \n_ready_i - connect \n_valid_o \pipe_n_valid_o - connect \pipe_fast2 \fast2$2 - connect \pipe_fast1 \fast1$1 - connect \pipe_rb \rb - connect \pipe_ra \ra - connect { \pipe_trap_op__trapaddr \pipe_trap_op__traptype \pipe_trap_op__is_32bit \pipe_trap_op__cia \pipe_trap_op__msr \pipe_trap_op__insn \pipe_trap_op__fn_unit \pipe_trap_op__insn_type } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } - connect \pipe_muxid 2'00 - connect \p_ready_o \pipe_p_ready_o - connect \pipe_p_valid_i \p_valid_i -end -attribute \src "issuer_ls180.v:30272.1-30330.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alui_l" -attribute \generator "nMigen" -module \alui_l - attribute \src "issuer_ls180.v:30273.7-30273.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:30318.3-30326.6" - wire $0\q_int$next[0:0]$915 - attribute \src "issuer_ls180.v:30316.3-30317.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:30318.3-30326.6" - wire $1\q_int$next[0:0]$916 - attribute \src "issuer_ls180.v:30297.7-30297.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:30308.17-30308.96" - wire $and$issuer_ls180.v:30308$905_Y - attribute \src "issuer_ls180.v:30313.17-30313.96" - wire $and$issuer_ls180.v:30313$910_Y - attribute \src "issuer_ls180.v:30310.18-30310.94" - wire $not$issuer_ls180.v:30310$907_Y - attribute \src "issuer_ls180.v:30312.17-30312.93" - wire $not$issuer_ls180.v:30312$909_Y - attribute \src "issuer_ls180.v:30315.17-30315.93" - wire $not$issuer_ls180.v:30315$912_Y - attribute \src "issuer_ls180.v:30309.18-30309.99" - wire $or$issuer_ls180.v:30309$906_Y - attribute \src "issuer_ls180.v:30311.18-30311.100" - wire $or$issuer_ls180.v:30311$908_Y - attribute \src "issuer_ls180.v:30314.17-30314.98" - wire $or$issuer_ls180.v:30314$911_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:30273.7-30273.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:30308$905 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:30308$905_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:30313$910 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:30313$910_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:30310$907 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $not$issuer_ls180.v:30310$907_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:30312$909 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$issuer_ls180.v:30312$909_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:30315$912 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$issuer_ls180.v:30315$912_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:30309$906 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alui - connect \Y $or$issuer_ls180.v:30309$906_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:30311$908 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $or$issuer_ls180.v:30311$908_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:30314$911 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alui - connect \Y $or$issuer_ls180.v:30314$911_Y - end - attribute \src "issuer_ls180.v:30273.7-30273.20" - process $proc$issuer_ls180.v:30273$917 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:30297.7-30297.19" - process $proc$issuer_ls180.v:30297$918 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:30316.3-30317.27" - process $proc$issuer_ls180.v:30316$913 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:30318.3-30326.6" - process $proc$issuer_ls180.v:30318$914 + attribute \src "libresoc.v:20526.3-20580.6" + process $proc$libresoc.v:20526$423 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$915 $1\q_int$next[0:0]$916 - attribute \src "issuer_ls180.v:30319.5-30319.29" + assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:20527.5-20527.29" switch \initial - attribute \src "issuer_ls180.v:30319.9-30319.17" + attribute \src "libresoc.v:20527.9-20527.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } - assign $1\q_int$next[0:0]$916 1'0 + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 case - assign $1\q_int$next[0:0]$916 \$5 + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[0:0]$915 - end - connect \$9 $and$issuer_ls180.v:30308$905_Y - connect \$11 $or$issuer_ls180.v:30309$906_Y - connect \$13 $not$issuer_ls180.v:30310$907_Y - connect \$15 $or$issuer_ls180.v:30311$908_Y - connect \$1 $not$issuer_ls180.v:30312$909_Y - connect \$3 $and$issuer_ls180.v:30313$910_Y - connect \$5 $or$issuer_ls180.v:30314$911_Y - connect \$7 $not$issuer_ls180.v:30315$912_Y - connect \qlq_alui \$15 - connect \qn_alui \$13 - connect \q_alui \$11 -end -attribute \src "issuer_ls180.v:30334.1-30392.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alui_l" -attribute \generator "nMigen" -module \alui_l$103 - attribute \src "issuer_ls180.v:30335.7-30335.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:30380.3-30388.6" - wire $0\q_int$next[0:0]$929 - attribute \src "issuer_ls180.v:30378.3-30379.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:30380.3-30388.6" - wire $1\q_int$next[0:0]$930 - attribute \src "issuer_ls180.v:30359.7-30359.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:30370.17-30370.96" - wire $and$issuer_ls180.v:30370$919_Y - attribute \src "issuer_ls180.v:30375.17-30375.96" - wire $and$issuer_ls180.v:30375$924_Y - attribute \src "issuer_ls180.v:30372.18-30372.94" - wire $not$issuer_ls180.v:30372$921_Y - attribute \src "issuer_ls180.v:30374.17-30374.93" - wire $not$issuer_ls180.v:30374$923_Y - attribute \src "issuer_ls180.v:30377.17-30377.93" - wire $not$issuer_ls180.v:30377$926_Y - attribute \src "issuer_ls180.v:30371.18-30371.99" - wire $or$issuer_ls180.v:30371$920_Y - attribute \src "issuer_ls180.v:30373.18-30373.100" - wire $or$issuer_ls180.v:30373$922_Y - attribute \src "issuer_ls180.v:30376.17-30376.98" - wire $or$issuer_ls180.v:30376$925_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:30335.7-30335.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:30370$919 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:30370$919_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:30375$924 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:30375$924_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:30372$921 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $not$issuer_ls180.v:30372$921_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:30374$923 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$issuer_ls180.v:30374$923_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:30377$926 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$issuer_ls180.v:30377$926_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:30371$920 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alui - connect \Y $or$issuer_ls180.v:30371$920_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:30373$922 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $or$issuer_ls180.v:30373$922_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:30376$925 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alui - connect \Y $or$issuer_ls180.v:30376$925_Y - end - attribute \src "issuer_ls180.v:30335.7-30335.20" - process $proc$issuer_ls180.v:30335$931 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:30359.7-30359.19" - process $proc$issuer_ls180.v:30359$932 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:30378.3-30379.27" - process $proc$issuer_ls180.v:30378$927 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0] end - attribute \src "issuer_ls180.v:30380.3-30388.6" - process $proc$issuer_ls180.v:30380$928 + attribute \src "libresoc.v:20581.3-20635.6" + process $proc$libresoc.v:20581$424 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$929 $1\q_int$next[0:0]$930 - attribute \src "issuer_ls180.v:30381.5-30381.29" + assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:20582.5-20582.29" switch \initial - attribute \src "issuer_ls180.v:30381.9-30381.17" + attribute \src "libresoc.v:20582.9-20582.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } - assign $1\q_int$next[0:0]$930 1'0 + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 case - assign $1\q_int$next[0:0]$930 \$5 + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[0:0]$929 - end - connect \$9 $and$issuer_ls180.v:30370$919_Y - connect \$11 $or$issuer_ls180.v:30371$920_Y - connect \$13 $not$issuer_ls180.v:30372$921_Y - connect \$15 $or$issuer_ls180.v:30373$922_Y - connect \$1 $not$issuer_ls180.v:30374$923_Y - connect \$3 $and$issuer_ls180.v:30375$924_Y - connect \$5 $or$issuer_ls180.v:30376$925_Y - connect \$7 $not$issuer_ls180.v:30377$926_Y - connect \qlq_alui \$15 - connect \qn_alui \$13 - connect \q_alui \$11 -end -attribute \src "issuer_ls180.v:30396.1-30454.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alui_l" -attribute \generator "nMigen" -module \alui_l$121 - attribute \src "issuer_ls180.v:30397.7-30397.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:30442.3-30450.6" - wire $0\q_int$next[0:0]$943 - attribute \src "issuer_ls180.v:30440.3-30441.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:30442.3-30450.6" - wire $1\q_int$next[0:0]$944 - attribute \src "issuer_ls180.v:30421.7-30421.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:30432.17-30432.96" - wire $and$issuer_ls180.v:30432$933_Y - attribute \src "issuer_ls180.v:30437.17-30437.96" - wire $and$issuer_ls180.v:30437$938_Y - attribute \src "issuer_ls180.v:30434.18-30434.94" - wire $not$issuer_ls180.v:30434$935_Y - attribute \src "issuer_ls180.v:30436.17-30436.93" - wire $not$issuer_ls180.v:30436$937_Y - attribute \src "issuer_ls180.v:30439.17-30439.93" - wire $not$issuer_ls180.v:30439$940_Y - attribute \src "issuer_ls180.v:30433.18-30433.99" - wire $or$issuer_ls180.v:30433$934_Y - attribute \src "issuer_ls180.v:30435.18-30435.100" - wire $or$issuer_ls180.v:30435$936_Y - attribute \src "issuer_ls180.v:30438.17-30438.98" - wire $or$issuer_ls180.v:30438$939_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:30397.7-30397.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:30432$933 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:30432$933_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:30437$938 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:30437$938_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:30434$935 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $not$issuer_ls180.v:30434$935_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:30436$937 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$issuer_ls180.v:30436$937_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:30439$940 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$issuer_ls180.v:30439$940_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:30433$934 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alui - connect \Y $or$issuer_ls180.v:30433$934_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:30435$936 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $or$issuer_ls180.v:30435$936_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:30438$939 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alui - connect \Y $or$issuer_ls180.v:30438$939_Y - end - attribute \src "issuer_ls180.v:30397.7-30397.20" - process $proc$issuer_ls180.v:30397$945 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:30421.7-30421.19" - process $proc$issuer_ls180.v:30421$946 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:30440.3-30441.27" - process $proc$issuer_ls180.v:30440$941 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0] end - attribute \src "issuer_ls180.v:30442.3-30450.6" - process $proc$issuer_ls180.v:30442$942 + attribute \src "libresoc.v:20636.3-20690.6" + process $proc$libresoc.v:20636$425 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$943 $1\q_int$next[0:0]$944 - attribute \src "issuer_ls180.v:30443.5-30443.29" + assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:20637.5-20637.29" switch \initial - attribute \src "issuer_ls180.v:30443.9-30443.17" + attribute \src "libresoc.v:20637.9-20637.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\q_int$next[0:0]$944 1'0 + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 case - assign $1\q_int$next[0:0]$944 \$5 + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[0:0]$943 - end - connect \$9 $and$issuer_ls180.v:30432$933_Y - connect \$11 $or$issuer_ls180.v:30433$934_Y - connect \$13 $not$issuer_ls180.v:30434$935_Y - connect \$15 $or$issuer_ls180.v:30435$936_Y - connect \$1 $not$issuer_ls180.v:30436$937_Y - connect \$3 $and$issuer_ls180.v:30437$938_Y - connect \$5 $or$issuer_ls180.v:30438$939_Y - connect \$7 $not$issuer_ls180.v:30439$940_Y - connect \qlq_alui \$15 - connect \qn_alui \$13 - connect \q_alui \$11 -end -attribute \src "issuer_ls180.v:30458.1-30516.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alui_l" -attribute \generator "nMigen" -module \alui_l$15 - attribute \src "issuer_ls180.v:30459.7-30459.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:30504.3-30512.6" - wire $0\q_int$next[0:0]$957 - attribute \src "issuer_ls180.v:30502.3-30503.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:30504.3-30512.6" - wire $1\q_int$next[0:0]$958 - attribute \src "issuer_ls180.v:30483.7-30483.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:30494.17-30494.96" - wire $and$issuer_ls180.v:30494$947_Y - attribute \src "issuer_ls180.v:30499.17-30499.96" - wire $and$issuer_ls180.v:30499$952_Y - attribute \src "issuer_ls180.v:30496.18-30496.94" - wire $not$issuer_ls180.v:30496$949_Y - attribute \src "issuer_ls180.v:30498.17-30498.93" - wire $not$issuer_ls180.v:30498$951_Y - attribute \src "issuer_ls180.v:30501.17-30501.93" - wire $not$issuer_ls180.v:30501$954_Y - attribute \src "issuer_ls180.v:30495.18-30495.99" - wire $or$issuer_ls180.v:30495$948_Y - attribute \src "issuer_ls180.v:30497.18-30497.100" - wire $or$issuer_ls180.v:30497$950_Y - attribute \src "issuer_ls180.v:30500.17-30500.98" - wire $or$issuer_ls180.v:30500$953_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:30459.7-30459.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:30494$947 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:30494$947_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:30499$952 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:30499$952_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:30496$949 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $not$issuer_ls180.v:30496$949_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:30498$951 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$issuer_ls180.v:30498$951_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:30501$954 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$issuer_ls180.v:30501$954_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:30495$948 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alui - connect \Y $or$issuer_ls180.v:30495$948_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:30497$950 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $or$issuer_ls180.v:30497$950_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:30500$953 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alui - connect \Y $or$issuer_ls180.v:30500$953_Y + update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0] end - attribute \src "issuer_ls180.v:30459.7-30459.20" - process $proc$issuer_ls180.v:30459$959 + attribute \src "libresoc.v:20691.3-20745.6" + process $proc$libresoc.v:20691$426 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:30483.7-30483.19" - process $proc$issuer_ls180.v:30483$960 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:20692.5-20692.29" + switch \initial + attribute \src "libresoc.v:20692.9-20692.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + case + assign $1\dec31_dec_sub11_br[0:0] 1'0 + end sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:30502.3-30503.27" - process $proc$issuer_ls180.v:30502$955 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0] end - attribute \src "issuer_ls180.v:30504.3-30512.6" - process $proc$issuer_ls180.v:30504$956 + attribute \src "libresoc.v:20746.3-20800.6" + process $proc$libresoc.v:20746$427 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$957 $1\q_int$next[0:0]$958 - attribute \src "issuer_ls180.v:30505.5-30505.29" + assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:20747.5-20747.29" switch \initial - attribute \src "issuer_ls180.v:30505.9-30505.17" + attribute \src "libresoc.v:20747.9-20747.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } - assign $1\q_int$next[0:0]$958 1'0 + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 case - assign $1\q_int$next[0:0]$958 \$5 + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[0:0]$957 + update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0] end - connect \$9 $and$issuer_ls180.v:30494$947_Y - connect \$11 $or$issuer_ls180.v:30495$948_Y - connect \$13 $not$issuer_ls180.v:30496$949_Y - connect \$15 $or$issuer_ls180.v:30497$950_Y - connect \$1 $not$issuer_ls180.v:30498$951_Y - connect \$3 $and$issuer_ls180.v:30499$952_Y - connect \$5 $or$issuer_ls180.v:30500$953_Y - connect \$7 $not$issuer_ls180.v:30501$954_Y - connect \qlq_alui \$15 - connect \qn_alui \$13 - connect \q_alui \$11 -end -attribute \src "issuer_ls180.v:30520.1-30578.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alui_l" -attribute \generator "nMigen" -module \alui_l$28 - attribute \src "issuer_ls180.v:30521.7-30521.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:30566.3-30574.6" - wire $0\q_int$next[0:0]$971 - attribute \src "issuer_ls180.v:30564.3-30565.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:30566.3-30574.6" - wire $1\q_int$next[0:0]$972 - attribute \src "issuer_ls180.v:30545.7-30545.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:30556.17-30556.96" - wire $and$issuer_ls180.v:30556$961_Y - attribute \src "issuer_ls180.v:30561.17-30561.96" - wire $and$issuer_ls180.v:30561$966_Y - attribute \src "issuer_ls180.v:30558.18-30558.94" - wire $not$issuer_ls180.v:30558$963_Y - attribute \src "issuer_ls180.v:30560.17-30560.93" - wire $not$issuer_ls180.v:30560$965_Y - attribute \src "issuer_ls180.v:30563.17-30563.93" - wire $not$issuer_ls180.v:30563$968_Y - attribute \src "issuer_ls180.v:30557.18-30557.99" - wire $or$issuer_ls180.v:30557$962_Y - attribute \src "issuer_ls180.v:30559.18-30559.100" - wire $or$issuer_ls180.v:30559$964_Y - attribute \src "issuer_ls180.v:30562.17-30562.98" - wire $or$issuer_ls180.v:30562$967_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:30521.7-30521.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:30556$961 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:30556$961_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:30561$966 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:30561$966_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:30558$963 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $not$issuer_ls180.v:30558$963_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:30560$965 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$issuer_ls180.v:30560$965_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:30563$968 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$issuer_ls180.v:30563$968_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:30557$962 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alui - connect \Y $or$issuer_ls180.v:30557$962_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:30559$964 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $or$issuer_ls180.v:30559$964_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:30562$967 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alui - connect \Y $or$issuer_ls180.v:30562$967_Y - end - attribute \src "issuer_ls180.v:30521.7-30521.20" - process $proc$issuer_ls180.v:30521$973 + attribute \src "libresoc.v:20801.3-20855.6" + process $proc$libresoc.v:20801$428 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:30545.7-30545.19" - process $proc$issuer_ls180.v:30545$974 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:20802.5-20802.29" + switch \initial + attribute \src "libresoc.v:20802.9-20802.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 + case + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0000000 + end sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:30564.3-30565.27" - process $proc$issuer_ls180.v:30564$969 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] end - attribute \src "issuer_ls180.v:30566.3-30574.6" - process $proc$issuer_ls180.v:30566$970 + attribute \src "libresoc.v:20856.3-20910.6" + process $proc$libresoc.v:20856$429 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$971 $1\q_int$next[0:0]$972 - attribute \src "issuer_ls180.v:30567.5-30567.29" + assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:20857.5-20857.29" switch \initial - attribute \src "issuer_ls180.v:30567.9-30567.17" + attribute \src "libresoc.v:20857.9-20857.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 assign { } { } - assign $1\q_int$next[0:0]$972 1'0 + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 case - assign $1\q_int$next[0:0]$972 \$5 + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[0:0]$971 - end - connect \$9 $and$issuer_ls180.v:30556$961_Y - connect \$11 $or$issuer_ls180.v:30557$962_Y - connect \$13 $not$issuer_ls180.v:30558$963_Y - connect \$15 $or$issuer_ls180.v:30559$964_Y - connect \$1 $not$issuer_ls180.v:30560$965_Y - connect \$3 $and$issuer_ls180.v:30561$966_Y - connect \$5 $or$issuer_ls180.v:30562$967_Y - connect \$7 $not$issuer_ls180.v:30563$968_Y - connect \qlq_alui \$15 - connect \qn_alui \$13 - connect \q_alui \$11 -end -attribute \src "issuer_ls180.v:30582.1-30640.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alui_l" -attribute \generator "nMigen" -module \alui_l$41 - attribute \src "issuer_ls180.v:30583.7-30583.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:30628.3-30636.6" - wire $0\q_int$next[0:0]$985 - attribute \src "issuer_ls180.v:30626.3-30627.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:30628.3-30636.6" - wire $1\q_int$next[0:0]$986 - attribute \src "issuer_ls180.v:30607.7-30607.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:30618.17-30618.96" - wire $and$issuer_ls180.v:30618$975_Y - attribute \src "issuer_ls180.v:30623.17-30623.96" - wire $and$issuer_ls180.v:30623$980_Y - attribute \src "issuer_ls180.v:30620.18-30620.94" - wire $not$issuer_ls180.v:30620$977_Y - attribute \src "issuer_ls180.v:30622.17-30622.93" - wire $not$issuer_ls180.v:30622$979_Y - attribute \src "issuer_ls180.v:30625.17-30625.93" - wire $not$issuer_ls180.v:30625$982_Y - attribute \src "issuer_ls180.v:30619.18-30619.99" - wire $or$issuer_ls180.v:30619$976_Y - attribute \src "issuer_ls180.v:30621.18-30621.100" - wire $or$issuer_ls180.v:30621$978_Y - attribute \src "issuer_ls180.v:30624.17-30624.98" - wire $or$issuer_ls180.v:30624$981_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:30583.7-30583.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:30618$975 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:30618$975_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:30623$980 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:30623$980_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:30620$977 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $not$issuer_ls180.v:30620$977_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:30622$979 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$issuer_ls180.v:30622$979_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:30625$982 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$issuer_ls180.v:30625$982_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:30619$976 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alui - connect \Y $or$issuer_ls180.v:30619$976_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:30621$978 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $or$issuer_ls180.v:30621$978_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:30624$981 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alui - connect \Y $or$issuer_ls180.v:30624$981_Y + update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0] end - attribute \src "issuer_ls180.v:30583.7-30583.20" - process $proc$issuer_ls180.v:30583$987 + attribute \src "libresoc.v:20911.3-20965.6" + process $proc$libresoc.v:20911$430 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:30607.7-30607.19" - process $proc$issuer_ls180.v:30607$988 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:20912.5-20912.29" + switch \initial + attribute \src "libresoc.v:20912.9-20912.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub11_is_32b[0:0] 1'0 + end sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:30626.3-30627.27" - process $proc$issuer_ls180.v:30626$983 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] end - attribute \src "issuer_ls180.v:30628.3-30636.6" - process $proc$issuer_ls180.v:30628$984 + attribute \src "libresoc.v:20966.3-21020.6" + process $proc$libresoc.v:20966$431 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$985 $1\q_int$next[0:0]$986 - attribute \src "issuer_ls180.v:30629.5-30629.29" + assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:20967.5-20967.29" switch \initial - attribute \src "issuer_ls180.v:30629.9-30629.17" + attribute \src "libresoc.v:20967.9-20967.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 assign { } { } - assign $1\q_int$next[0:0]$986 1'0 + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 case - assign $1\q_int$next[0:0]$986 \$5 + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[0:0]$985 - end - connect \$9 $and$issuer_ls180.v:30618$975_Y - connect \$11 $or$issuer_ls180.v:30619$976_Y - connect \$13 $not$issuer_ls180.v:30620$977_Y - connect \$15 $or$issuer_ls180.v:30621$978_Y - connect \$1 $not$issuer_ls180.v:30622$979_Y - connect \$3 $and$issuer_ls180.v:30623$980_Y - connect \$5 $or$issuer_ls180.v:30624$981_Y - connect \$7 $not$issuer_ls180.v:30625$982_Y - connect \qlq_alui \$15 - connect \qn_alui \$13 - connect \q_alui \$11 -end -attribute \src "issuer_ls180.v:30644.1-30702.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alui_l" -attribute \generator "nMigen" -module \alui_l$57 - attribute \src "issuer_ls180.v:30645.7-30645.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:30690.3-30698.6" - wire $0\q_int$next[0:0]$999 - attribute \src "issuer_ls180.v:30688.3-30689.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:30690.3-30698.6" - wire $1\q_int$next[0:0]$1000 - attribute \src "issuer_ls180.v:30669.7-30669.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:30680.17-30680.96" - wire $and$issuer_ls180.v:30680$989_Y - attribute \src "issuer_ls180.v:30685.17-30685.96" - wire $and$issuer_ls180.v:30685$994_Y - attribute \src "issuer_ls180.v:30682.18-30682.94" - wire $not$issuer_ls180.v:30682$991_Y - attribute \src "issuer_ls180.v:30684.17-30684.93" - wire $not$issuer_ls180.v:30684$993_Y - attribute \src "issuer_ls180.v:30687.17-30687.93" - wire $not$issuer_ls180.v:30687$996_Y - attribute \src "issuer_ls180.v:30681.18-30681.99" - wire $or$issuer_ls180.v:30681$990_Y - attribute \src "issuer_ls180.v:30683.18-30683.100" - wire $or$issuer_ls180.v:30683$992_Y - attribute \src "issuer_ls180.v:30686.17-30686.98" - wire $or$issuer_ls180.v:30686$995_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:30645.7-30645.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:30680$989 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:30680$989_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:30685$994 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:30685$994_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:30682$991 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $not$issuer_ls180.v:30682$991_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:30684$993 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$issuer_ls180.v:30684$993_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:30687$996 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$issuer_ls180.v:30687$996_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:30681$990 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alui - connect \Y $or$issuer_ls180.v:30681$990_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:30683$992 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $or$issuer_ls180.v:30683$992_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:30686$995 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alui - connect \Y $or$issuer_ls180.v:30686$995_Y + update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0] end - attribute \src "issuer_ls180.v:30645.7-30645.20" - process $proc$issuer_ls180.v:30645$1001 + attribute \src "libresoc.v:21021.3-21075.6" + process $proc$libresoc.v:21021$432 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:30669.7-30669.19" - process $proc$issuer_ls180.v:30669$1002 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:21022.5-21022.29" + switch \initial + attribute \src "libresoc.v:21022.9-21022.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + end sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:30688.3-30689.27" - process $proc$issuer_ls180.v:30688$997 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0] end - attribute \src "issuer_ls180.v:30690.3-30698.6" - process $proc$issuer_ls180.v:30690$998 + attribute \src "libresoc.v:21076.3-21130.6" + process $proc$libresoc.v:21076$433 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$999 $1\q_int$next[0:0]$1000 - attribute \src "issuer_ls180.v:30691.5-30691.29" + assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:21077.5-21077.29" switch \initial - attribute \src "issuer_ls180.v:30691.9-30691.17" + attribute \src "libresoc.v:21077.9-21077.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\q_int$next[0:0]$1000 1'0 + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 case - assign $1\q_int$next[0:0]$1000 \$5 + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[0:0]$999 - end - connect \$9 $and$issuer_ls180.v:30680$989_Y - connect \$11 $or$issuer_ls180.v:30681$990_Y - connect \$13 $not$issuer_ls180.v:30682$991_Y - connect \$15 $or$issuer_ls180.v:30683$992_Y - connect \$1 $not$issuer_ls180.v:30684$993_Y - connect \$3 $and$issuer_ls180.v:30685$994_Y - connect \$5 $or$issuer_ls180.v:30686$995_Y - connect \$7 $not$issuer_ls180.v:30687$996_Y - connect \qlq_alui \$15 - connect \qn_alui \$13 - connect \q_alui \$11 -end -attribute \src "issuer_ls180.v:30706.1-30764.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alui_l" -attribute \generator "nMigen" -module \alui_l$69 - attribute \src "issuer_ls180.v:30707.7-30707.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:30752.3-30760.6" - wire $0\q_int$next[0:0]$1013 - attribute \src "issuer_ls180.v:30750.3-30751.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:30752.3-30760.6" - wire $1\q_int$next[0:0]$1014 - attribute \src "issuer_ls180.v:30731.7-30731.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:30742.17-30742.96" - wire $and$issuer_ls180.v:30742$1003_Y - attribute \src "issuer_ls180.v:30747.17-30747.96" - wire $and$issuer_ls180.v:30747$1008_Y - attribute \src "issuer_ls180.v:30744.18-30744.94" - wire $not$issuer_ls180.v:30744$1005_Y - attribute \src "issuer_ls180.v:30746.17-30746.93" - wire $not$issuer_ls180.v:30746$1007_Y - attribute \src "issuer_ls180.v:30749.17-30749.93" - wire $not$issuer_ls180.v:30749$1010_Y - attribute \src "issuer_ls180.v:30743.18-30743.99" - wire $or$issuer_ls180.v:30743$1004_Y - attribute \src "issuer_ls180.v:30745.18-30745.100" - wire $or$issuer_ls180.v:30745$1006_Y - attribute \src "issuer_ls180.v:30748.17-30748.98" - wire $or$issuer_ls180.v:30748$1009_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:30707.7-30707.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:30742$1003 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:30742$1003_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:30747$1008 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:30747$1008_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:30744$1005 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $not$issuer_ls180.v:30744$1005_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:30746$1007 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$issuer_ls180.v:30746$1007_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:30749$1010 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$issuer_ls180.v:30749$1010_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:30743$1004 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alui - connect \Y $or$issuer_ls180.v:30743$1004_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:30745$1006 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $or$issuer_ls180.v:30745$1006_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:30748$1009 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alui - connect \Y $or$issuer_ls180.v:30748$1009_Y + update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0] end - attribute \src "issuer_ls180.v:30707.7-30707.20" - process $proc$issuer_ls180.v:30707$1015 + attribute \src "libresoc.v:21131.3-21185.6" + process $proc$libresoc.v:21131$434 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:30731.7-30731.19" - process $proc$issuer_ls180.v:30731$1016 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:21132.5-21132.29" + switch \initial + attribute \src "libresoc.v:21132.9-21132.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub11_form[4:0] 5'00000 + end sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:30750.3-30751.27" - process $proc$issuer_ls180.v:30750$1011 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] end - attribute \src "issuer_ls180.v:30752.3-30760.6" - process $proc$issuer_ls180.v:30752$1012 + attribute \src "libresoc.v:21186.3-21240.6" + process $proc$libresoc.v:21186$435 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$1013 $1\q_int$next[0:0]$1014 - attribute \src "issuer_ls180.v:30753.5-30753.29" + assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:21187.5-21187.29" switch \initial - attribute \src "issuer_ls180.v:30753.9-30753.17" + attribute \src "libresoc.v:21187.9-21187.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } - assign $1\q_int$next[0:0]$1014 1'0 + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 case - assign $1\q_int$next[0:0]$1014 \$5 + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'000 end sync always - update \q_int$next $0\q_int$next[0:0]$1013 - end - connect \$9 $and$issuer_ls180.v:30742$1003_Y - connect \$11 $or$issuer_ls180.v:30743$1004_Y - connect \$13 $not$issuer_ls180.v:30744$1005_Y - connect \$15 $or$issuer_ls180.v:30745$1006_Y - connect \$1 $not$issuer_ls180.v:30746$1007_Y - connect \$3 $and$issuer_ls180.v:30747$1008_Y - connect \$5 $or$issuer_ls180.v:30748$1009_Y - connect \$7 $not$issuer_ls180.v:30749$1010_Y - connect \qlq_alui \$15 - connect \qn_alui \$13 - connect \q_alui \$11 -end -attribute \src "issuer_ls180.v:30768.1-30826.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alui_l" -attribute \generator "nMigen" -module \alui_l$86 - attribute \src "issuer_ls180.v:30769.7-30769.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:30814.3-30822.6" - wire $0\q_int$next[0:0]$1027 - attribute \src "issuer_ls180.v:30812.3-30813.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:30814.3-30822.6" - wire $1\q_int$next[0:0]$1028 - attribute \src "issuer_ls180.v:30793.7-30793.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:30804.17-30804.96" - wire $and$issuer_ls180.v:30804$1017_Y - attribute \src "issuer_ls180.v:30809.17-30809.96" - wire $and$issuer_ls180.v:30809$1022_Y - attribute \src "issuer_ls180.v:30806.18-30806.94" - wire $not$issuer_ls180.v:30806$1019_Y - attribute \src "issuer_ls180.v:30808.17-30808.93" - wire $not$issuer_ls180.v:30808$1021_Y - attribute \src "issuer_ls180.v:30811.17-30811.93" - wire $not$issuer_ls180.v:30811$1024_Y - attribute \src "issuer_ls180.v:30805.18-30805.99" - wire $or$issuer_ls180.v:30805$1018_Y - attribute \src "issuer_ls180.v:30807.18-30807.100" - wire $or$issuer_ls180.v:30807$1020_Y - attribute \src "issuer_ls180.v:30810.17-30810.98" - wire $or$issuer_ls180.v:30810$1023_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:30769.7-30769.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:30804$1017 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:30804$1017_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:30809$1022 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:30809$1022_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:30806$1019 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $not$issuer_ls180.v:30806$1019_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:30808$1021 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$issuer_ls180.v:30808$1021_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:30811$1024 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$issuer_ls180.v:30811$1024_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:30805$1018 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alui - connect \Y $or$issuer_ls180.v:30805$1018_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:30807$1020 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $or$issuer_ls180.v:30807$1020_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:30810$1023 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alui - connect \Y $or$issuer_ls180.v:30810$1023_Y + update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0] end - attribute \src "issuer_ls180.v:30769.7-30769.20" - process $proc$issuer_ls180.v:30769$1029 + attribute \src "libresoc.v:21241.3-21295.6" + process $proc$libresoc.v:21241$436 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:30793.7-30793.19" - process $proc$issuer_ls180.v:30793$1030 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:21242.5-21242.29" + switch \initial + attribute \src "libresoc.v:21242.9-21242.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0000 + end sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:30812.3-30813.27" - process $proc$issuer_ls180.v:30812$1025 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0] end - attribute \src "issuer_ls180.v:30814.3-30822.6" - process $proc$issuer_ls180.v:30814$1026 + attribute \src "libresoc.v:21296.3-21350.6" + process $proc$libresoc.v:21296$437 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$1027 $1\q_int$next[0:0]$1028 - attribute \src "issuer_ls180.v:30815.5-30815.29" + assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:21297.5-21297.29" switch \initial - attribute \src "issuer_ls180.v:30815.9-30815.17" + attribute \src "libresoc.v:21297.9-21297.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } - assign $1\q_int$next[0:0]$1028 1'0 + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 case - assign $1\q_int$next[0:0]$1028 \$5 + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 end sync always - update \q_int$next $0\q_int$next[0:0]$1027 - end - connect \$9 $and$issuer_ls180.v:30804$1017_Y - connect \$11 $or$issuer_ls180.v:30805$1018_Y - connect \$13 $not$issuer_ls180.v:30806$1019_Y - connect \$15 $or$issuer_ls180.v:30807$1020_Y - connect \$1 $not$issuer_ls180.v:30808$1021_Y - connect \$3 $and$issuer_ls180.v:30809$1022_Y - connect \$5 $or$issuer_ls180.v:30810$1023_Y - connect \$7 $not$issuer_ls180.v:30811$1024_Y - connect \qlq_alui \$15 - connect \qn_alui \$13 - connect \q_alui \$11 -end -attribute \src "issuer_ls180.v:30830.1-32174.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.main.bpermd" -attribute \generator "nMigen" -module \bpermd - attribute \src "issuer_ls180.v:30831.7-30831.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:31008.3-32099.6" - wire width 64 $0\perm[63:0] - attribute \src "issuer_ls180.v:31008.3-32099.6" - wire $10\perm[4:4] - attribute \src "issuer_ls180.v:31008.3-32099.6" - wire $11\perm[5:5] - attribute \src "issuer_ls180.v:31008.3-32099.6" - wire $12\perm[5:5] - attribute \src "issuer_ls180.v:31008.3-32099.6" - wire $13\perm[6:6] - attribute \src "issuer_ls180.v:31008.3-32099.6" - wire $14\perm[6:6] - attribute \src "issuer_ls180.v:31008.3-32099.6" - wire $15\perm[7:7] - attribute \src "issuer_ls180.v:31008.3-32099.6" - wire $16\perm[7:7] - attribute \src "issuer_ls180.v:31008.3-32099.6" - wire $1\perm[0:0] - attribute \src "issuer_ls180.v:31008.3-32099.6" - wire $2\perm[0:0] - attribute \src "issuer_ls180.v:31008.3-32099.6" - wire $3\perm[1:1] - attribute \src "issuer_ls180.v:31008.3-32099.6" - wire $4\perm[1:1] - attribute \src "issuer_ls180.v:31008.3-32099.6" - wire $5\perm[2:2] - attribute \src "issuer_ls180.v:31008.3-32099.6" - wire $6\perm[2:2] - attribute \src "issuer_ls180.v:31008.3-32099.6" - wire $7\perm[3:3] - attribute \src "issuer_ls180.v:31008.3-32099.6" - wire $8\perm[3:3] - attribute \src "issuer_ls180.v:31008.3-32099.6" - wire $9\perm[4:4] - attribute \src "issuer_ls180.v:31000.17-31000.104" - wire $lt$issuer_ls180.v:31000$1031_Y - attribute \src "issuer_ls180.v:31001.18-31001.105" - wire $lt$issuer_ls180.v:31001$1032_Y - attribute \src "issuer_ls180.v:31002.18-31002.105" - wire $lt$issuer_ls180.v:31002$1033_Y - attribute \src "issuer_ls180.v:31003.18-31003.105" - wire $lt$issuer_ls180.v:31003$1034_Y - attribute \src "issuer_ls180.v:31004.17-31004.104" - wire $lt$issuer_ls180.v:31004$1035_Y - attribute \src "issuer_ls180.v:31005.17-31005.104" - wire $lt$issuer_ls180.v:31005$1036_Y - attribute \src "issuer_ls180.v:31006.17-31006.104" - wire $lt$issuer_ls180.v:31006$1037_Y - attribute \src "issuer_ls180.v:31007.17-31007.104" - wire $lt$issuer_ls180.v:31007$1038_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" - wire width 8 \idx_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" - wire width 8 \idx_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" - wire width 8 \idx_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" - wire width 8 \idx_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" - wire width 8 \idx_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" - wire width 8 \idx_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" - wire width 8 \idx_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" - wire width 8 \idx_7 - attribute \src "issuer_ls180.v:30831.7-30831.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:60" - wire width 64 \perm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:55" - wire width 64 output 2 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:56" - wire width 64 input 1 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" - wire width 64 input 3 \rs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$issuer_ls180.v:31000$1031 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_4 - connect \B 7'1000000 - connect \Y $lt$issuer_ls180.v:31000$1031_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$issuer_ls180.v:31001$1032 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_5 - connect \B 7'1000000 - connect \Y $lt$issuer_ls180.v:31001$1032_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$issuer_ls180.v:31002$1033 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_6 - connect \B 7'1000000 - connect \Y $lt$issuer_ls180.v:31002$1033_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$issuer_ls180.v:31003$1034 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_7 - connect \B 7'1000000 - connect \Y $lt$issuer_ls180.v:31003$1034_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$issuer_ls180.v:31004$1035 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_0 - connect \B 7'1000000 - connect \Y $lt$issuer_ls180.v:31004$1035_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$issuer_ls180.v:31005$1036 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_1 - connect \B 7'1000000 - connect \Y $lt$issuer_ls180.v:31005$1036_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$issuer_ls180.v:31006$1037 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_2 - connect \B 7'1000000 - connect \Y $lt$issuer_ls180.v:31006$1037_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$issuer_ls180.v:31007$1038 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_3 - connect \B 7'1000000 - connect \Y $lt$issuer_ls180.v:31007$1038_Y + update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0] end - attribute \src "issuer_ls180.v:30831.7-30831.20" - process $proc$issuer_ls180.v:30831$1040 + attribute \src "libresoc.v:21351.3-21405.6" + process $proc$libresoc.v:21351$438 assign { } { } - assign $0\initial[0:0] 1'0 + assign { } { } + assign $0\dec31_dec_sub11_out_sel[1:0] $1\dec31_dec_sub11_out_sel[1:0] + attribute \src "libresoc.v:21352.5-21352.29" + switch \initial + attribute \src "libresoc.v:21352.9-21352.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub11_out_sel[1:0] 2'00 + end sync always - update \initial $0\initial[0:0] - sync init + update \dec31_dec_sub11_out_sel $0\dec31_dec_sub11_out_sel[1:0] end - attribute \src "issuer_ls180.v:31008.3-32099.6" - process $proc$issuer_ls180.v:31008$1039 + attribute \src "libresoc.v:21406.3-21460.6" + process $proc$libresoc.v:21406$439 + assign { } { } assign { } { } - assign $0\perm[63:0] [63:8] 56'00000000000000000000000000000000000000000000000000000000 - assign $0\perm[63:0] [0] $1\perm[0:0] - assign $0\perm[63:0] [1] $3\perm[1:1] - assign $0\perm[63:0] [2] $5\perm[2:2] - assign $0\perm[63:0] [3] $7\perm[3:3] - assign $0\perm[63:0] [4] $9\perm[4:4] - assign $0\perm[63:0] [5] $11\perm[5:5] - assign $0\perm[63:0] [6] $13\perm[6:6] - assign $0\perm[63:0] [7] $15\perm[7:7] - attribute \src "issuer_ls180.v:31009.5-31009.29" + assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:21407.5-21407.29" switch \initial - attribute \src "issuer_ls180.v:31009.9-31009.17" + attribute \src "libresoc.v:21407.9-21407.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 assign { } { } - assign $1\perm[0:0] $2\perm[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000000 - assign { } { } - assign $2\perm[0:0] \rb64_0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000001 - assign { } { } - assign $2\perm[0:0] \rb64_1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000010 - assign { } { } - assign $2\perm[0:0] \rb64_2 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000011 - assign { } { } - assign $2\perm[0:0] \rb64_3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000100 - assign { } { } - assign $2\perm[0:0] \rb64_4 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000101 - assign { } { } - assign $2\perm[0:0] \rb64_5 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000110 - assign { } { } - assign $2\perm[0:0] \rb64_6 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000111 - assign { } { } - assign $2\perm[0:0] \rb64_7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001000 - assign { } { } - assign $2\perm[0:0] \rb64_8 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001001 - assign { } { } - assign $2\perm[0:0] \rb64_9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001010 - assign { } { } - assign $2\perm[0:0] \rb64_10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001011 - assign { } { } - assign $2\perm[0:0] \rb64_11 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001100 - assign { } { } - assign $2\perm[0:0] \rb64_12 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001101 - assign { } { } - assign $2\perm[0:0] \rb64_13 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001110 - assign { } { } - assign $2\perm[0:0] \rb64_14 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001111 - assign { } { } - assign $2\perm[0:0] \rb64_15 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010000 - assign { } { } - assign $2\perm[0:0] \rb64_16 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010001 - assign { } { } - assign $2\perm[0:0] \rb64_17 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010010 - assign { } { } - assign $2\perm[0:0] \rb64_18 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010011 - assign { } { } - assign $2\perm[0:0] \rb64_19 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010100 - assign { } { } - assign $2\perm[0:0] \rb64_20 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010101 - assign { } { } - assign $2\perm[0:0] \rb64_21 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010110 - assign { } { } - assign $2\perm[0:0] \rb64_22 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010111 - assign { } { } - assign $2\perm[0:0] \rb64_23 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011000 - assign { } { } - assign $2\perm[0:0] \rb64_24 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011001 - assign { } { } - assign $2\perm[0:0] \rb64_25 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011010 - assign { } { } - assign $2\perm[0:0] \rb64_26 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011011 - assign { } { } - assign $2\perm[0:0] \rb64_27 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011100 - assign { } { } - assign $2\perm[0:0] \rb64_28 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011101 - assign { } { } - assign $2\perm[0:0] \rb64_29 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011110 - assign { } { } - assign $2\perm[0:0] \rb64_30 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011111 - assign { } { } - assign $2\perm[0:0] \rb64_31 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100000 - assign { } { } - assign $2\perm[0:0] \rb64_32 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100001 - assign { } { } - assign $2\perm[0:0] \rb64_33 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100010 - assign { } { } - assign $2\perm[0:0] \rb64_34 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100011 - assign { } { } - assign $2\perm[0:0] \rb64_35 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100100 - assign { } { } - assign $2\perm[0:0] \rb64_36 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100101 - assign { } { } - assign $2\perm[0:0] \rb64_37 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100110 - assign { } { } - assign $2\perm[0:0] \rb64_38 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100111 - assign { } { } - assign $2\perm[0:0] \rb64_39 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101000 - assign { } { } - assign $2\perm[0:0] \rb64_40 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101001 - assign { } { } - assign $2\perm[0:0] \rb64_41 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101010 - assign { } { } - assign $2\perm[0:0] \rb64_42 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101011 - assign { } { } - assign $2\perm[0:0] \rb64_43 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101100 - assign { } { } - assign $2\perm[0:0] \rb64_44 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101101 - assign { } { } - assign $2\perm[0:0] \rb64_45 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101110 - assign { } { } - assign $2\perm[0:0] \rb64_46 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101111 - assign { } { } - assign $2\perm[0:0] \rb64_47 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110000 - assign { } { } - assign $2\perm[0:0] \rb64_48 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110001 - assign { } { } - assign $2\perm[0:0] \rb64_49 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110010 - assign { } { } - assign $2\perm[0:0] \rb64_50 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110011 - assign { } { } - assign $2\perm[0:0] \rb64_51 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110100 - assign { } { } - assign $2\perm[0:0] \rb64_52 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110101 - assign { } { } - assign $2\perm[0:0] \rb64_53 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110110 - assign { } { } - assign $2\perm[0:0] \rb64_54 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110111 - assign { } { } - assign $2\perm[0:0] \rb64_55 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111000 - assign { } { } - assign $2\perm[0:0] \rb64_56 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111001 - assign { } { } - assign $2\perm[0:0] \rb64_57 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111010 - assign { } { } - assign $2\perm[0:0] \rb64_58 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111011 - assign { } { } - assign $2\perm[0:0] \rb64_59 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111100 - assign { } { } - assign $2\perm[0:0] \rb64_60 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111101 - assign { } { } - assign $2\perm[0:0] \rb64_61 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111110 - assign { } { } - assign $2\perm[0:0] \rb64_62 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'-------- - assign { } { } - assign $2\perm[0:0] \rb64_63 - case - assign $2\perm[0:0] 1'0 - end - case - assign $1\perm[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign $3\perm[1:1] $4\perm[1:1] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000000 - assign { } { } - assign $4\perm[1:1] \rb64_0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000001 - assign { } { } - assign $4\perm[1:1] \rb64_1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000010 - assign { } { } - assign $4\perm[1:1] \rb64_2 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000011 - assign { } { } - assign $4\perm[1:1] \rb64_3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000100 - assign { } { } - assign $4\perm[1:1] \rb64_4 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000101 - assign { } { } - assign $4\perm[1:1] \rb64_5 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000110 - assign { } { } - assign $4\perm[1:1] \rb64_6 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000111 - assign { } { } - assign $4\perm[1:1] \rb64_7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001000 - assign { } { } - assign $4\perm[1:1] \rb64_8 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001001 - assign { } { } - assign $4\perm[1:1] \rb64_9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001010 - assign { } { } - assign $4\perm[1:1] \rb64_10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001011 - assign { } { } - assign $4\perm[1:1] \rb64_11 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001100 - assign { } { } - assign $4\perm[1:1] \rb64_12 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001101 - assign { } { } - assign $4\perm[1:1] \rb64_13 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001110 - assign { } { } - assign $4\perm[1:1] \rb64_14 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001111 - assign { } { } - assign $4\perm[1:1] \rb64_15 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010000 - assign { } { } - assign $4\perm[1:1] \rb64_16 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010001 - assign { } { } - assign $4\perm[1:1] \rb64_17 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010010 - assign { } { } - assign $4\perm[1:1] \rb64_18 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010011 - assign { } { } - assign $4\perm[1:1] \rb64_19 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010100 - assign { } { } - assign $4\perm[1:1] \rb64_20 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010101 - assign { } { } - assign $4\perm[1:1] \rb64_21 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010110 - assign { } { } - assign $4\perm[1:1] \rb64_22 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010111 - assign { } { } - assign $4\perm[1:1] \rb64_23 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011000 - assign { } { } - assign $4\perm[1:1] \rb64_24 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011001 - assign { } { } - assign $4\perm[1:1] \rb64_25 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011010 - assign { } { } - assign $4\perm[1:1] \rb64_26 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011011 - assign { } { } - assign $4\perm[1:1] \rb64_27 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011100 - assign { } { } - assign $4\perm[1:1] \rb64_28 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011101 - assign { } { } - assign $4\perm[1:1] \rb64_29 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011110 - assign { } { } - assign $4\perm[1:1] \rb64_30 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011111 - assign { } { } - assign $4\perm[1:1] \rb64_31 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100000 - assign { } { } - assign $4\perm[1:1] \rb64_32 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100001 - assign { } { } - assign $4\perm[1:1] \rb64_33 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100010 - assign { } { } - assign $4\perm[1:1] \rb64_34 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100011 - assign { } { } - assign $4\perm[1:1] \rb64_35 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100100 - assign { } { } - assign $4\perm[1:1] \rb64_36 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100101 - assign { } { } - assign $4\perm[1:1] \rb64_37 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100110 - assign { } { } - assign $4\perm[1:1] \rb64_38 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100111 - assign { } { } - assign $4\perm[1:1] \rb64_39 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101000 - assign { } { } - assign $4\perm[1:1] \rb64_40 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101001 - assign { } { } - assign $4\perm[1:1] \rb64_41 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101010 - assign { } { } - assign $4\perm[1:1] \rb64_42 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101011 - assign { } { } - assign $4\perm[1:1] \rb64_43 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101100 - assign { } { } - assign $4\perm[1:1] \rb64_44 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101101 - assign { } { } - assign $4\perm[1:1] \rb64_45 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101110 - assign { } { } - assign $4\perm[1:1] \rb64_46 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101111 - assign { } { } - assign $4\perm[1:1] \rb64_47 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110000 - assign { } { } - assign $4\perm[1:1] \rb64_48 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110001 - assign { } { } - assign $4\perm[1:1] \rb64_49 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110010 - assign { } { } - assign $4\perm[1:1] \rb64_50 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110011 - assign { } { } - assign $4\perm[1:1] \rb64_51 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110100 - assign { } { } - assign $4\perm[1:1] \rb64_52 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110101 - assign { } { } - assign $4\perm[1:1] \rb64_53 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110110 - assign { } { } - assign $4\perm[1:1] \rb64_54 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110111 - assign { } { } - assign $4\perm[1:1] \rb64_55 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111000 - assign { } { } - assign $4\perm[1:1] \rb64_56 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111001 - assign { } { } - assign $4\perm[1:1] \rb64_57 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111010 - assign { } { } - assign $4\perm[1:1] \rb64_58 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111011 - assign { } { } - assign $4\perm[1:1] \rb64_59 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111100 - assign { } { } - assign $4\perm[1:1] \rb64_60 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111101 - assign { } { } - assign $4\perm[1:1] \rb64_61 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111110 - assign { } { } - assign $4\perm[1:1] \rb64_62 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'-------- - assign { } { } - assign $4\perm[1:1] \rb64_63 - case - assign $4\perm[1:1] 1'0 - end - case - assign $3\perm[1:1] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch \$5 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 assign { } { } - assign $5\perm[2:2] $6\perm[2:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_2 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000000 - assign { } { } - assign $6\perm[2:2] \rb64_0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000001 - assign { } { } - assign $6\perm[2:2] \rb64_1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000010 - assign { } { } - assign $6\perm[2:2] \rb64_2 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000011 - assign { } { } - assign $6\perm[2:2] \rb64_3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000100 - assign { } { } - assign $6\perm[2:2] \rb64_4 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000101 - assign { } { } - assign $6\perm[2:2] \rb64_5 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000110 - assign { } { } - assign $6\perm[2:2] \rb64_6 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000111 - assign { } { } - assign $6\perm[2:2] \rb64_7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001000 - assign { } { } - assign $6\perm[2:2] \rb64_8 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001001 - assign { } { } - assign $6\perm[2:2] \rb64_9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001010 - assign { } { } - assign $6\perm[2:2] \rb64_10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001011 - assign { } { } - assign $6\perm[2:2] \rb64_11 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001100 - assign { } { } - assign $6\perm[2:2] \rb64_12 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001101 - assign { } { } - assign $6\perm[2:2] \rb64_13 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001110 - assign { } { } - assign $6\perm[2:2] \rb64_14 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001111 - assign { } { } - assign $6\perm[2:2] \rb64_15 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010000 - assign { } { } - assign $6\perm[2:2] \rb64_16 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010001 - assign { } { } - assign $6\perm[2:2] \rb64_17 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010010 - assign { } { } - assign $6\perm[2:2] \rb64_18 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010011 - assign { } { } - assign $6\perm[2:2] \rb64_19 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010100 - assign { } { } - assign $6\perm[2:2] \rb64_20 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010101 - assign { } { } - assign $6\perm[2:2] \rb64_21 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010110 - assign { } { } - assign $6\perm[2:2] \rb64_22 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010111 - assign { } { } - assign $6\perm[2:2] \rb64_23 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011000 - assign { } { } - assign $6\perm[2:2] \rb64_24 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011001 - assign { } { } - assign $6\perm[2:2] \rb64_25 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011010 - assign { } { } - assign $6\perm[2:2] \rb64_26 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011011 - assign { } { } - assign $6\perm[2:2] \rb64_27 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011100 - assign { } { } - assign $6\perm[2:2] \rb64_28 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011101 - assign { } { } - assign $6\perm[2:2] \rb64_29 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011110 - assign { } { } - assign $6\perm[2:2] \rb64_30 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011111 - assign { } { } - assign $6\perm[2:2] \rb64_31 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100000 - assign { } { } - assign $6\perm[2:2] \rb64_32 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100001 - assign { } { } - assign $6\perm[2:2] \rb64_33 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100010 - assign { } { } - assign $6\perm[2:2] \rb64_34 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100011 - assign { } { } - assign $6\perm[2:2] \rb64_35 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100100 - assign { } { } - assign $6\perm[2:2] \rb64_36 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100101 - assign { } { } - assign $6\perm[2:2] \rb64_37 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100110 - assign { } { } - assign $6\perm[2:2] \rb64_38 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100111 - assign { } { } - assign $6\perm[2:2] \rb64_39 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101000 - assign { } { } - assign $6\perm[2:2] \rb64_40 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101001 - assign { } { } - assign $6\perm[2:2] \rb64_41 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101010 - assign { } { } - assign $6\perm[2:2] \rb64_42 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101011 - assign { } { } - assign $6\perm[2:2] \rb64_43 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101100 - assign { } { } - assign $6\perm[2:2] \rb64_44 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101101 - assign { } { } - assign $6\perm[2:2] \rb64_45 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101110 - assign { } { } - assign $6\perm[2:2] \rb64_46 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101111 - assign { } { } - assign $6\perm[2:2] \rb64_47 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110000 - assign { } { } - assign $6\perm[2:2] \rb64_48 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110001 - assign { } { } - assign $6\perm[2:2] \rb64_49 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110010 - assign { } { } - assign $6\perm[2:2] \rb64_50 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110011 - assign { } { } - assign $6\perm[2:2] \rb64_51 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110100 - assign { } { } - assign $6\perm[2:2] \rb64_52 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110101 - assign { } { } - assign $6\perm[2:2] \rb64_53 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110110 - assign { } { } - assign $6\perm[2:2] \rb64_54 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110111 - assign { } { } - assign $6\perm[2:2] \rb64_55 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111000 - assign { } { } - assign $6\perm[2:2] \rb64_56 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111001 - assign { } { } - assign $6\perm[2:2] \rb64_57 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111010 - assign { } { } - assign $6\perm[2:2] \rb64_58 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111011 - assign { } { } - assign $6\perm[2:2] \rb64_59 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111100 - assign { } { } - assign $6\perm[2:2] \rb64_60 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111101 - assign { } { } - assign $6\perm[2:2] \rb64_61 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111110 - assign { } { } - assign $6\perm[2:2] \rb64_62 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'-------- - assign { } { } - assign $6\perm[2:2] \rb64_63 - case - assign $6\perm[2:2] 1'0 - end - case - assign $5\perm[2:2] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch \$7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 assign { } { } - assign $7\perm[3:3] $8\perm[3:3] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000000 - assign { } { } - assign $8\perm[3:3] \rb64_0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000001 - assign { } { } - assign $8\perm[3:3] \rb64_1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000010 - assign { } { } - assign $8\perm[3:3] \rb64_2 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000011 - assign { } { } - assign $8\perm[3:3] \rb64_3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000100 - assign { } { } - assign $8\perm[3:3] \rb64_4 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000101 - assign { } { } - assign $8\perm[3:3] \rb64_5 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000110 - assign { } { } - assign $8\perm[3:3] \rb64_6 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000111 - assign { } { } - assign $8\perm[3:3] \rb64_7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001000 - assign { } { } - assign $8\perm[3:3] \rb64_8 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001001 - assign { } { } - assign $8\perm[3:3] \rb64_9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001010 - assign { } { } - assign $8\perm[3:3] \rb64_10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001011 - assign { } { } - assign $8\perm[3:3] \rb64_11 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001100 - assign { } { } - assign $8\perm[3:3] \rb64_12 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001101 - assign { } { } - assign $8\perm[3:3] \rb64_13 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001110 - assign { } { } - assign $8\perm[3:3] \rb64_14 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001111 - assign { } { } - assign $8\perm[3:3] \rb64_15 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010000 - assign { } { } - assign $8\perm[3:3] \rb64_16 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010001 - assign { } { } - assign $8\perm[3:3] \rb64_17 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010010 - assign { } { } - assign $8\perm[3:3] \rb64_18 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010011 - assign { } { } - assign $8\perm[3:3] \rb64_19 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010100 - assign { } { } - assign $8\perm[3:3] \rb64_20 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010101 - assign { } { } - assign $8\perm[3:3] \rb64_21 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010110 - assign { } { } - assign $8\perm[3:3] \rb64_22 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010111 - assign { } { } - assign $8\perm[3:3] \rb64_23 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011000 - assign { } { } - assign $8\perm[3:3] \rb64_24 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011001 - assign { } { } - assign $8\perm[3:3] \rb64_25 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011010 - assign { } { } - assign $8\perm[3:3] \rb64_26 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011011 - assign { } { } - assign $8\perm[3:3] \rb64_27 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011100 - assign { } { } - assign $8\perm[3:3] \rb64_28 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011101 - assign { } { } - assign $8\perm[3:3] \rb64_29 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011110 - assign { } { } - assign $8\perm[3:3] \rb64_30 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011111 - assign { } { } - assign $8\perm[3:3] \rb64_31 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100000 - assign { } { } - assign $8\perm[3:3] \rb64_32 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100001 - assign { } { } - assign $8\perm[3:3] \rb64_33 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100010 - assign { } { } - assign $8\perm[3:3] \rb64_34 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100011 - assign { } { } - assign $8\perm[3:3] \rb64_35 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100100 - assign { } { } - assign $8\perm[3:3] \rb64_36 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100101 - assign { } { } - assign $8\perm[3:3] \rb64_37 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100110 - assign { } { } - assign $8\perm[3:3] \rb64_38 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100111 - assign { } { } - assign $8\perm[3:3] \rb64_39 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101000 - assign { } { } - assign $8\perm[3:3] \rb64_40 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101001 - assign { } { } - assign $8\perm[3:3] \rb64_41 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101010 - assign { } { } - assign $8\perm[3:3] \rb64_42 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101011 - assign { } { } - assign $8\perm[3:3] \rb64_43 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101100 - assign { } { } - assign $8\perm[3:3] \rb64_44 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101101 - assign { } { } - assign $8\perm[3:3] \rb64_45 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101110 - assign { } { } - assign $8\perm[3:3] \rb64_46 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101111 - assign { } { } - assign $8\perm[3:3] \rb64_47 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110000 - assign { } { } - assign $8\perm[3:3] \rb64_48 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110001 - assign { } { } - assign $8\perm[3:3] \rb64_49 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110010 - assign { } { } - assign $8\perm[3:3] \rb64_50 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110011 - assign { } { } - assign $8\perm[3:3] \rb64_51 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110100 - assign { } { } - assign $8\perm[3:3] \rb64_52 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110101 - assign { } { } - assign $8\perm[3:3] \rb64_53 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110110 - assign { } { } - assign $8\perm[3:3] \rb64_54 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110111 - assign { } { } - assign $8\perm[3:3] \rb64_55 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111000 - assign { } { } - assign $8\perm[3:3] \rb64_56 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111001 - assign { } { } - assign $8\perm[3:3] \rb64_57 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111010 - assign { } { } - assign $8\perm[3:3] \rb64_58 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111011 - assign { } { } - assign $8\perm[3:3] \rb64_59 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111100 - assign { } { } - assign $8\perm[3:3] \rb64_60 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111101 - assign { } { } - assign $8\perm[3:3] \rb64_61 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111110 - assign { } { } - assign $8\perm[3:3] \rb64_62 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'-------- - assign { } { } - assign $8\perm[3:3] \rb64_63 - case - assign $8\perm[3:3] 1'0 - end - case - assign $7\perm[3:3] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch \$9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 assign { } { } - assign $9\perm[4:4] $10\perm[4:4] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_4 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000000 - assign { } { } - assign $10\perm[4:4] \rb64_0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000001 - assign { } { } - assign $10\perm[4:4] \rb64_1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000010 - assign { } { } - assign $10\perm[4:4] \rb64_2 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000011 - assign { } { } - assign $10\perm[4:4] \rb64_3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000100 - assign { } { } - assign $10\perm[4:4] \rb64_4 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000101 - assign { } { } - assign $10\perm[4:4] \rb64_5 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000110 - assign { } { } - assign $10\perm[4:4] \rb64_6 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000111 - assign { } { } - assign $10\perm[4:4] \rb64_7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001000 - assign { } { } - assign $10\perm[4:4] \rb64_8 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001001 - assign { } { } - assign $10\perm[4:4] \rb64_9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001010 - assign { } { } - assign $10\perm[4:4] \rb64_10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001011 - assign { } { } - assign $10\perm[4:4] \rb64_11 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001100 - assign { } { } - assign $10\perm[4:4] \rb64_12 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001101 - assign { } { } - assign $10\perm[4:4] \rb64_13 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001110 - assign { } { } - assign $10\perm[4:4] \rb64_14 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001111 - assign { } { } - assign $10\perm[4:4] \rb64_15 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010000 - assign { } { } - assign $10\perm[4:4] \rb64_16 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010001 - assign { } { } - assign $10\perm[4:4] \rb64_17 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010010 - assign { } { } - assign $10\perm[4:4] \rb64_18 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010011 - assign { } { } - assign $10\perm[4:4] \rb64_19 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010100 - assign { } { } - assign $10\perm[4:4] \rb64_20 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010101 - assign { } { } - assign $10\perm[4:4] \rb64_21 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010110 - assign { } { } - assign $10\perm[4:4] \rb64_22 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010111 - assign { } { } - assign $10\perm[4:4] \rb64_23 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011000 - assign { } { } - assign $10\perm[4:4] \rb64_24 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011001 - assign { } { } - assign $10\perm[4:4] \rb64_25 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011010 - assign { } { } - assign $10\perm[4:4] \rb64_26 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011011 - assign { } { } - assign $10\perm[4:4] \rb64_27 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011100 - assign { } { } - assign $10\perm[4:4] \rb64_28 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011101 - assign { } { } - assign $10\perm[4:4] \rb64_29 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011110 - assign { } { } - assign $10\perm[4:4] \rb64_30 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011111 - assign { } { } - assign $10\perm[4:4] \rb64_31 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100000 - assign { } { } - assign $10\perm[4:4] \rb64_32 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100001 - assign { } { } - assign $10\perm[4:4] \rb64_33 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100010 - assign { } { } - assign $10\perm[4:4] \rb64_34 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100011 - assign { } { } - assign $10\perm[4:4] \rb64_35 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100100 - assign { } { } - assign $10\perm[4:4] \rb64_36 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100101 - assign { } { } - assign $10\perm[4:4] \rb64_37 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100110 - assign { } { } - assign $10\perm[4:4] \rb64_38 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100111 - assign { } { } - assign $10\perm[4:4] \rb64_39 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101000 - assign { } { } - assign $10\perm[4:4] \rb64_40 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101001 - assign { } { } - assign $10\perm[4:4] \rb64_41 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101010 - assign { } { } - assign $10\perm[4:4] \rb64_42 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101011 - assign { } { } - assign $10\perm[4:4] \rb64_43 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101100 - assign { } { } - assign $10\perm[4:4] \rb64_44 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101101 - assign { } { } - assign $10\perm[4:4] \rb64_45 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101110 - assign { } { } - assign $10\perm[4:4] \rb64_46 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101111 - assign { } { } - assign $10\perm[4:4] \rb64_47 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110000 - assign { } { } - assign $10\perm[4:4] \rb64_48 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110001 - assign { } { } - assign $10\perm[4:4] \rb64_49 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110010 - assign { } { } - assign $10\perm[4:4] \rb64_50 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110011 - assign { } { } - assign $10\perm[4:4] \rb64_51 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110100 - assign { } { } - assign $10\perm[4:4] \rb64_52 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110101 - assign { } { } - assign $10\perm[4:4] \rb64_53 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110110 - assign { } { } - assign $10\perm[4:4] \rb64_54 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110111 - assign { } { } - assign $10\perm[4:4] \rb64_55 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111000 - assign { } { } - assign $10\perm[4:4] \rb64_56 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111001 - assign { } { } - assign $10\perm[4:4] \rb64_57 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111010 - assign { } { } - assign $10\perm[4:4] \rb64_58 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111011 - assign { } { } - assign $10\perm[4:4] \rb64_59 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111100 - assign { } { } - assign $10\perm[4:4] \rb64_60 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111101 - assign { } { } - assign $10\perm[4:4] \rb64_61 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111110 - assign { } { } - assign $10\perm[4:4] \rb64_62 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'-------- - assign { } { } - assign $10\perm[4:4] \rb64_63 - case - assign $10\perm[4:4] 1'0 - end - case - assign $9\perm[4:4] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch \$11 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 assign { } { } - assign $11\perm[5:5] $12\perm[5:5] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_5 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000000 - assign { } { } - assign $12\perm[5:5] \rb64_0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000001 - assign { } { } - assign $12\perm[5:5] \rb64_1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000010 - assign { } { } - assign $12\perm[5:5] \rb64_2 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000011 - assign { } { } - assign $12\perm[5:5] \rb64_3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000100 - assign { } { } - assign $12\perm[5:5] \rb64_4 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000101 - assign { } { } - assign $12\perm[5:5] \rb64_5 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000110 - assign { } { } - assign $12\perm[5:5] \rb64_6 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000111 - assign { } { } - assign $12\perm[5:5] \rb64_7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001000 - assign { } { } - assign $12\perm[5:5] \rb64_8 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001001 - assign { } { } - assign $12\perm[5:5] \rb64_9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001010 - assign { } { } - assign $12\perm[5:5] \rb64_10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001011 - assign { } { } - assign $12\perm[5:5] \rb64_11 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001100 - assign { } { } - assign $12\perm[5:5] \rb64_12 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001101 - assign { } { } - assign $12\perm[5:5] \rb64_13 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001110 - assign { } { } - assign $12\perm[5:5] \rb64_14 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001111 - assign { } { } - assign $12\perm[5:5] \rb64_15 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010000 - assign { } { } - assign $12\perm[5:5] \rb64_16 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010001 - assign { } { } - assign $12\perm[5:5] \rb64_17 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010010 - assign { } { } - assign $12\perm[5:5] \rb64_18 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010011 - assign { } { } - assign $12\perm[5:5] \rb64_19 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010100 - assign { } { } - assign $12\perm[5:5] \rb64_20 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010101 - assign { } { } - assign $12\perm[5:5] \rb64_21 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010110 - assign { } { } - assign $12\perm[5:5] \rb64_22 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010111 - assign { } { } - assign $12\perm[5:5] \rb64_23 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011000 - assign { } { } - assign $12\perm[5:5] \rb64_24 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011001 - assign { } { } - assign $12\perm[5:5] \rb64_25 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011010 - assign { } { } - assign $12\perm[5:5] \rb64_26 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011011 - assign { } { } - assign $12\perm[5:5] \rb64_27 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011100 - assign { } { } - assign $12\perm[5:5] \rb64_28 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011101 - assign { } { } - assign $12\perm[5:5] \rb64_29 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011110 - assign { } { } - assign $12\perm[5:5] \rb64_30 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011111 - assign { } { } - assign $12\perm[5:5] \rb64_31 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100000 - assign { } { } - assign $12\perm[5:5] \rb64_32 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100001 - assign { } { } - assign $12\perm[5:5] \rb64_33 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100010 - assign { } { } - assign $12\perm[5:5] \rb64_34 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100011 - assign { } { } - assign $12\perm[5:5] \rb64_35 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100100 - assign { } { } - assign $12\perm[5:5] \rb64_36 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100101 - assign { } { } - assign $12\perm[5:5] \rb64_37 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100110 - assign { } { } - assign $12\perm[5:5] \rb64_38 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100111 - assign { } { } - assign $12\perm[5:5] \rb64_39 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101000 - assign { } { } - assign $12\perm[5:5] \rb64_40 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101001 - assign { } { } - assign $12\perm[5:5] \rb64_41 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101010 - assign { } { } - assign $12\perm[5:5] \rb64_42 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101011 - assign { } { } - assign $12\perm[5:5] \rb64_43 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101100 - assign { } { } - assign $12\perm[5:5] \rb64_44 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101101 - assign { } { } - assign $12\perm[5:5] \rb64_45 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101110 - assign { } { } - assign $12\perm[5:5] \rb64_46 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101111 - assign { } { } - assign $12\perm[5:5] \rb64_47 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110000 - assign { } { } - assign $12\perm[5:5] \rb64_48 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110001 - assign { } { } - assign $12\perm[5:5] \rb64_49 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110010 - assign { } { } - assign $12\perm[5:5] \rb64_50 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110011 - assign { } { } - assign $12\perm[5:5] \rb64_51 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110100 - assign { } { } - assign $12\perm[5:5] \rb64_52 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110101 - assign { } { } - assign $12\perm[5:5] \rb64_53 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110110 - assign { } { } - assign $12\perm[5:5] \rb64_54 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110111 - assign { } { } - assign $12\perm[5:5] \rb64_55 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111000 - assign { } { } - assign $12\perm[5:5] \rb64_56 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111001 - assign { } { } - assign $12\perm[5:5] \rb64_57 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111010 - assign { } { } - assign $12\perm[5:5] \rb64_58 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111011 - assign { } { } - assign $12\perm[5:5] \rb64_59 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111100 - assign { } { } - assign $12\perm[5:5] \rb64_60 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111101 - assign { } { } - assign $12\perm[5:5] \rb64_61 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111110 - assign { } { } - assign $12\perm[5:5] \rb64_62 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'-------- - assign { } { } - assign $12\perm[5:5] \rb64_63 - case - assign $12\perm[5:5] 1'0 - end + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 case - assign $11\perm[5:5] 1'0 + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch \$13 - attribute \src "issuer_ls180.v:0.0-0.0" + sync always + update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0] + end + attribute \src "libresoc.v:21461.3-21515.6" + process $proc$libresoc.v:21461$440 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:21462.5-21462.29" + switch \initial + attribute \src "libresoc.v:21462.9-21462.17" case 1'1 - assign { } { } - assign $13\perm[6:6] $14\perm[6:6] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_6 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000000 - assign { } { } - assign $14\perm[6:6] \rb64_0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000001 - assign { } { } - assign $14\perm[6:6] \rb64_1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000010 - assign { } { } - assign $14\perm[6:6] \rb64_2 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000011 - assign { } { } - assign $14\perm[6:6] \rb64_3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000100 - assign { } { } - assign $14\perm[6:6] \rb64_4 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000101 - assign { } { } - assign $14\perm[6:6] \rb64_5 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000110 - assign { } { } - assign $14\perm[6:6] \rb64_6 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000111 - assign { } { } - assign $14\perm[6:6] \rb64_7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001000 - assign { } { } - assign $14\perm[6:6] \rb64_8 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001001 - assign { } { } - assign $14\perm[6:6] \rb64_9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001010 - assign { } { } - assign $14\perm[6:6] \rb64_10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001011 - assign { } { } - assign $14\perm[6:6] \rb64_11 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001100 - assign { } { } - assign $14\perm[6:6] \rb64_12 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001101 - assign { } { } - assign $14\perm[6:6] \rb64_13 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001110 - assign { } { } - assign $14\perm[6:6] \rb64_14 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001111 - assign { } { } - assign $14\perm[6:6] \rb64_15 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010000 - assign { } { } - assign $14\perm[6:6] \rb64_16 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010001 - assign { } { } - assign $14\perm[6:6] \rb64_17 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010010 - assign { } { } - assign $14\perm[6:6] \rb64_18 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010011 - assign { } { } - assign $14\perm[6:6] \rb64_19 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010100 - assign { } { } - assign $14\perm[6:6] \rb64_20 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010101 - assign { } { } - assign $14\perm[6:6] \rb64_21 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010110 - assign { } { } - assign $14\perm[6:6] \rb64_22 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010111 - assign { } { } - assign $14\perm[6:6] \rb64_23 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011000 - assign { } { } - assign $14\perm[6:6] \rb64_24 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011001 - assign { } { } - assign $14\perm[6:6] \rb64_25 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011010 - assign { } { } - assign $14\perm[6:6] \rb64_26 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011011 - assign { } { } - assign $14\perm[6:6] \rb64_27 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011100 - assign { } { } - assign $14\perm[6:6] \rb64_28 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011101 - assign { } { } - assign $14\perm[6:6] \rb64_29 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011110 - assign { } { } - assign $14\perm[6:6] \rb64_30 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011111 - assign { } { } - assign $14\perm[6:6] \rb64_31 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100000 - assign { } { } - assign $14\perm[6:6] \rb64_32 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100001 - assign { } { } - assign $14\perm[6:6] \rb64_33 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100010 - assign { } { } - assign $14\perm[6:6] \rb64_34 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100011 - assign { } { } - assign $14\perm[6:6] \rb64_35 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100100 - assign { } { } - assign $14\perm[6:6] \rb64_36 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100101 - assign { } { } - assign $14\perm[6:6] \rb64_37 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100110 - assign { } { } - assign $14\perm[6:6] \rb64_38 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100111 - assign { } { } - assign $14\perm[6:6] \rb64_39 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101000 - assign { } { } - assign $14\perm[6:6] \rb64_40 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101001 - assign { } { } - assign $14\perm[6:6] \rb64_41 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101010 - assign { } { } - assign $14\perm[6:6] \rb64_42 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101011 - assign { } { } - assign $14\perm[6:6] \rb64_43 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101100 - assign { } { } - assign $14\perm[6:6] \rb64_44 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101101 - assign { } { } - assign $14\perm[6:6] \rb64_45 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101110 - assign { } { } - assign $14\perm[6:6] \rb64_46 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101111 - assign { } { } - assign $14\perm[6:6] \rb64_47 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110000 - assign { } { } - assign $14\perm[6:6] \rb64_48 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110001 - assign { } { } - assign $14\perm[6:6] \rb64_49 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110010 - assign { } { } - assign $14\perm[6:6] \rb64_50 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110011 - assign { } { } - assign $14\perm[6:6] \rb64_51 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110100 - assign { } { } - assign $14\perm[6:6] \rb64_52 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110101 - assign { } { } - assign $14\perm[6:6] \rb64_53 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110110 - assign { } { } - assign $14\perm[6:6] \rb64_54 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110111 - assign { } { } - assign $14\perm[6:6] \rb64_55 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111000 - assign { } { } - assign $14\perm[6:6] \rb64_56 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111001 - assign { } { } - assign $14\perm[6:6] \rb64_57 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111010 - assign { } { } - assign $14\perm[6:6] \rb64_58 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111011 - assign { } { } - assign $14\perm[6:6] \rb64_59 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111100 - assign { } { } - assign $14\perm[6:6] \rb64_60 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111101 - assign { } { } - assign $14\perm[6:6] \rb64_61 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111110 - assign { } { } - assign $14\perm[6:6] \rb64_62 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'-------- - assign { } { } - assign $14\perm[6:6] \rb64_63 - case - assign $14\perm[6:6] 1'0 - end case - assign $13\perm[6:6] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch \$15 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 assign { } { } - assign $15\perm[7:7] $16\perm[7:7] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000000 - assign { } { } - assign $16\perm[7:7] \rb64_0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000001 - assign { } { } - assign $16\perm[7:7] \rb64_1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000010 - assign { } { } - assign $16\perm[7:7] \rb64_2 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000011 - assign { } { } - assign $16\perm[7:7] \rb64_3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000100 - assign { } { } - assign $16\perm[7:7] \rb64_4 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000101 - assign { } { } - assign $16\perm[7:7] \rb64_5 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000110 - assign { } { } - assign $16\perm[7:7] \rb64_6 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00000111 - assign { } { } - assign $16\perm[7:7] \rb64_7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001000 - assign { } { } - assign $16\perm[7:7] \rb64_8 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001001 - assign { } { } - assign $16\perm[7:7] \rb64_9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001010 - assign { } { } - assign $16\perm[7:7] \rb64_10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001011 - assign { } { } - assign $16\perm[7:7] \rb64_11 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001100 - assign { } { } - assign $16\perm[7:7] \rb64_12 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001101 - assign { } { } - assign $16\perm[7:7] \rb64_13 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001110 - assign { } { } - assign $16\perm[7:7] \rb64_14 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00001111 - assign { } { } - assign $16\perm[7:7] \rb64_15 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010000 - assign { } { } - assign $16\perm[7:7] \rb64_16 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010001 - assign { } { } - assign $16\perm[7:7] \rb64_17 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010010 - assign { } { } - assign $16\perm[7:7] \rb64_18 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010011 - assign { } { } - assign $16\perm[7:7] \rb64_19 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010100 - assign { } { } - assign $16\perm[7:7] \rb64_20 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010101 - assign { } { } - assign $16\perm[7:7] \rb64_21 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010110 - assign { } { } - assign $16\perm[7:7] \rb64_22 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00010111 - assign { } { } - assign $16\perm[7:7] \rb64_23 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011000 - assign { } { } - assign $16\perm[7:7] \rb64_24 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011001 - assign { } { } - assign $16\perm[7:7] \rb64_25 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011010 - assign { } { } - assign $16\perm[7:7] \rb64_26 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011011 - assign { } { } - assign $16\perm[7:7] \rb64_27 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011100 - assign { } { } - assign $16\perm[7:7] \rb64_28 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011101 - assign { } { } - assign $16\perm[7:7] \rb64_29 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011110 - assign { } { } - assign $16\perm[7:7] \rb64_30 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00011111 - assign { } { } - assign $16\perm[7:7] \rb64_31 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100000 - assign { } { } - assign $16\perm[7:7] \rb64_32 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100001 - assign { } { } - assign $16\perm[7:7] \rb64_33 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100010 - assign { } { } - assign $16\perm[7:7] \rb64_34 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100011 - assign { } { } - assign $16\perm[7:7] \rb64_35 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100100 - assign { } { } - assign $16\perm[7:7] \rb64_36 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100101 - assign { } { } - assign $16\perm[7:7] \rb64_37 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100110 - assign { } { } - assign $16\perm[7:7] \rb64_38 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00100111 - assign { } { } - assign $16\perm[7:7] \rb64_39 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101000 - assign { } { } - assign $16\perm[7:7] \rb64_40 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101001 - assign { } { } - assign $16\perm[7:7] \rb64_41 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101010 - assign { } { } - assign $16\perm[7:7] \rb64_42 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101011 - assign { } { } - assign $16\perm[7:7] \rb64_43 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101100 - assign { } { } - assign $16\perm[7:7] \rb64_44 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101101 - assign { } { } - assign $16\perm[7:7] \rb64_45 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101110 - assign { } { } - assign $16\perm[7:7] \rb64_46 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00101111 - assign { } { } - assign $16\perm[7:7] \rb64_47 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110000 - assign { } { } - assign $16\perm[7:7] \rb64_48 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110001 - assign { } { } - assign $16\perm[7:7] \rb64_49 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110010 - assign { } { } - assign $16\perm[7:7] \rb64_50 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110011 - assign { } { } - assign $16\perm[7:7] \rb64_51 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110100 - assign { } { } - assign $16\perm[7:7] \rb64_52 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110101 - assign { } { } - assign $16\perm[7:7] \rb64_53 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110110 - assign { } { } - assign $16\perm[7:7] \rb64_54 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00110111 - assign { } { } - assign $16\perm[7:7] \rb64_55 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111000 - assign { } { } - assign $16\perm[7:7] \rb64_56 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111001 - assign { } { } - assign $16\perm[7:7] \rb64_57 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111010 - assign { } { } - assign $16\perm[7:7] \rb64_58 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111011 - assign { } { } - assign $16\perm[7:7] \rb64_59 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111100 - assign { } { } - assign $16\perm[7:7] \rb64_60 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111101 - assign { } { } - assign $16\perm[7:7] \rb64_61 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'00111110 - assign { } { } - assign $16\perm[7:7] \rb64_62 - attribute \src "issuer_ls180.v:0.0-0.0" - case 8'-------- - assign { } { } - assign $16\perm[7:7] \rb64_63 - case - assign $16\perm[7:7] 1'0 - end + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 case - assign $15\perm[7:7] 1'0 - end - sync always - update \perm $0\perm[63:0] - end - connect \$9 $lt$issuer_ls180.v:31000$1031_Y - connect \$11 $lt$issuer_ls180.v:31001$1032_Y - connect \$13 $lt$issuer_ls180.v:31002$1033_Y - connect \$15 $lt$issuer_ls180.v:31003$1034_Y - connect \$1 $lt$issuer_ls180.v:31004$1035_Y - connect \$3 $lt$issuer_ls180.v:31005$1036_Y - connect \$5 $lt$issuer_ls180.v:31006$1037_Y - connect \$7 $lt$issuer_ls180.v:31007$1038_Y - connect \ra [7:0] \perm [7:0] - connect \ra [63:8] 56'00000000000000000000000000000000000000000000000000000000 - connect \idx_7 \rs [63:56] - connect \idx_6 \rs [55:48] - connect \idx_5 \rs [47:40] - connect \idx_4 \rs [39:32] - connect \idx_3 \rs [31:24] - connect \idx_2 \rs [23:16] - connect \idx_1 \rs [15:8] - connect \idx_0 \rs [7:0] - connect \rb64_63 \rb [0] - connect \rb64_62 \rb [1] - connect \rb64_61 \rb [2] - connect \rb64_60 \rb [3] - connect \rb64_59 \rb [4] - connect \rb64_58 \rb [5] - connect \rb64_57 \rb [6] - connect \rb64_56 \rb [7] - connect \rb64_55 \rb [8] - connect \rb64_54 \rb [9] - connect \rb64_53 \rb [10] - connect \rb64_52 \rb [11] - connect \rb64_51 \rb [12] - connect \rb64_50 \rb [13] - connect \rb64_49 \rb [14] - connect \rb64_48 \rb [15] - connect \rb64_47 \rb [16] - connect \rb64_46 \rb [17] - connect \rb64_45 \rb [18] - connect \rb64_44 \rb [19] - connect \rb64_43 \rb [20] - connect \rb64_42 \rb [21] - connect \rb64_41 \rb [22] - connect \rb64_40 \rb [23] - connect \rb64_39 \rb [24] - connect \rb64_38 \rb [25] - connect \rb64_37 \rb [26] - connect \rb64_36 \rb [27] - connect \rb64_35 \rb [28] - connect \rb64_34 \rb [29] - connect \rb64_33 \rb [30] - connect \rb64_32 \rb [31] - connect \rb64_31 \rb [32] - connect \rb64_30 \rb [33] - connect \rb64_29 \rb [34] - connect \rb64_28 \rb [35] - connect \rb64_27 \rb [36] - connect \rb64_26 \rb [37] - connect \rb64_25 \rb [38] - connect \rb64_24 \rb [39] - connect \rb64_23 \rb [40] - connect \rb64_22 \rb [41] - connect \rb64_21 \rb [42] - connect \rb64_20 \rb [43] - connect \rb64_19 \rb [44] - connect \rb64_18 \rb [45] - connect \rb64_17 \rb [46] - connect \rb64_16 \rb [47] - connect \rb64_15 \rb [48] - connect \rb64_14 \rb [49] - connect \rb64_13 \rb [50] - connect \rb64_12 \rb [51] - connect \rb64_11 \rb [52] - connect \rb64_10 \rb [53] - connect \rb64_9 \rb [54] - connect \rb64_8 \rb [55] - connect \rb64_7 \rb [56] - connect \rb64_6 \rb [57] - connect \rb64_5 \rb [58] - connect \rb64_4 \rb [59] - connect \rb64_3 \rb [60] - connect \rb64_2 \rb [61] - connect \rb64_1 \rb [62] - connect \rb64_0 \rb [63] + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] end -attribute \src "issuer_ls180.v:32178.1-33227.10" +attribute \src "libresoc.v:21521.1-24252.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub15" attribute \generator "nMigen" -module \branch0 - attribute \src "issuer_ls180.v:32844.3-32845.25" - wire $0\all_rd_dly[0:0] - attribute \src "issuer_ls180.v:33019.3-33043.6" - wire width 64 $0\alu_branch0_br_op__cia$next[63:0]$1162 - attribute \src "issuer_ls180.v:32804.3-32805.61" - wire width 64 $0\alu_branch0_br_op__cia[63:0] - attribute \src "issuer_ls180.v:33019.3-33043.6" - wire width 12 $0\alu_branch0_br_op__fn_unit$next[11:0]$1163 - attribute \src "issuer_ls180.v:32808.3-32809.69" - wire width 12 $0\alu_branch0_br_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:33019.3-33043.6" - wire width 64 $0\alu_branch0_br_op__imm_data__data$next[63:0]$1164 - attribute \src "issuer_ls180.v:32812.3-32813.83" - wire width 64 $0\alu_branch0_br_op__imm_data__data[63:0] - attribute \src "issuer_ls180.v:33019.3-33043.6" - wire $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1165 - attribute \src "issuer_ls180.v:32814.3-32815.79" - wire $0\alu_branch0_br_op__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:33019.3-33043.6" - wire width 32 $0\alu_branch0_br_op__insn$next[31:0]$1166 - attribute \src "issuer_ls180.v:32810.3-32811.63" - wire width 32 $0\alu_branch0_br_op__insn[31:0] - attribute \src "issuer_ls180.v:33019.3-33043.6" - wire width 7 $0\alu_branch0_br_op__insn_type$next[6:0]$1167 - attribute \src "issuer_ls180.v:32806.3-32807.73" - wire width 7 $0\alu_branch0_br_op__insn_type[6:0] - attribute \src "issuer_ls180.v:33019.3-33043.6" - wire $0\alu_branch0_br_op__is_32bit$next[0:0]$1168 - attribute \src "issuer_ls180.v:32818.3-32819.71" - wire $0\alu_branch0_br_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:33019.3-33043.6" - wire $0\alu_branch0_br_op__lk$next[0:0]$1169 - attribute \src "issuer_ls180.v:32816.3-32817.59" - wire $0\alu_branch0_br_op__lk[0:0] - attribute \src "issuer_ls180.v:32842.3-32843.43" - wire $0\alu_done_dly[0:0] - attribute \src "issuer_ls180.v:33149.3-33157.6" - wire $0\alu_l_r_alu$next[0:0]$1217 - attribute \src "issuer_ls180.v:32782.3-32783.39" - wire $0\alu_l_r_alu[0:0] - attribute \src "issuer_ls180.v:33140.3-33148.6" - wire $0\alui_l_r_alui$next[0:0]$1214 - attribute \src "issuer_ls180.v:32784.3-32785.43" - wire $0\alui_l_r_alui[0:0] - attribute \src "issuer_ls180.v:33044.3-33065.6" - wire width 64 $0\data_r0__fast1$next[63:0]$1181 - attribute \src "issuer_ls180.v:32800.3-32801.45" - wire width 64 $0\data_r0__fast1[63:0] - attribute \src "issuer_ls180.v:33044.3-33065.6" - wire $0\data_r0__fast1_ok$next[0:0]$1182 - attribute \src "issuer_ls180.v:32802.3-32803.51" - wire $0\data_r0__fast1_ok[0:0] - attribute \src "issuer_ls180.v:33066.3-33087.6" - wire width 64 $0\data_r1__fast2$next[63:0]$1189 - attribute \src "issuer_ls180.v:32796.3-32797.45" - wire width 64 $0\data_r1__fast2[63:0] - attribute \src "issuer_ls180.v:33066.3-33087.6" - wire $0\data_r1__fast2_ok$next[0:0]$1190 - attribute \src "issuer_ls180.v:32798.3-32799.51" - wire $0\data_r1__fast2_ok[0:0] - attribute \src "issuer_ls180.v:33088.3-33109.6" - wire width 64 $0\data_r2__nia$next[63:0]$1197 - attribute \src "issuer_ls180.v:32792.3-32793.41" - wire width 64 $0\data_r2__nia[63:0] - attribute \src "issuer_ls180.v:33088.3-33109.6" - wire $0\data_r2__nia_ok$next[0:0]$1198 - attribute \src "issuer_ls180.v:32794.3-32795.47" - wire $0\data_r2__nia_ok[0:0] - attribute \src "issuer_ls180.v:33158.3-33167.6" - wire width 64 $0\dest1_o[63:0] - attribute \src "issuer_ls180.v:33168.3-33177.6" - wire width 64 $0\dest2_o[63:0] - attribute \src "issuer_ls180.v:33178.3-33187.6" - wire width 64 $0\dest3_o[63:0] - attribute \src "issuer_ls180.v:32179.7-32179.20" +module \dec31_dec_sub15 + attribute \src "libresoc.v:22294.3-22396.6" + wire width 8 $0\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:22706.3-22808.6" + wire $0\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:24045.3-24147.6" + wire width 3 $0\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:24148.3-24250.6" + wire width 3 $0\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:22191.3-22293.6" + wire width 2 $0\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:22603.3-22705.6" + wire $0\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:23530.3-23632.6" + wire width 5 $0\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:21779.3-21881.6" + wire width 12 $0\dec31_dec_sub15_function_unit[11:0] + attribute \src "libresoc.v:23633.3-23735.6" + wire width 3 $0\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:23736.3-23838.6" + wire width 4 $0\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:23839.3-23941.6" + wire width 2 $0\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:22912.3-23014.6" + wire width 7 $0\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:22397.3-22499.6" + wire $0\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:22500.3-22602.6" + wire $0\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:23118.3-23220.6" + wire $0\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:21882.3-21984.6" + wire width 4 $0\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:23324.3-23426.6" + wire $0\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:23942.3-24044.6" + wire width 2 $0\dec31_dec_sub15_out_sel[1:0] + attribute \src "libresoc.v:22088.3-22190.6" + wire width 2 $0\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:23015.3-23117.6" + wire $0\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:23427.3-23529.6" + wire $0\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:23221.3-23323.6" + wire $0\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:22809.3-22911.6" + wire $0\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:21985.3-22087.6" + wire width 2 $0\dec31_dec_sub15_upd[1:0] + attribute \src "libresoc.v:21522.7-21522.20" wire $0\initial[0:0] - attribute \src "issuer_ls180.v:32974.3-32982.6" - wire $0\opc_l_r_opc$next[0:0]$1147 - attribute \src "issuer_ls180.v:32828.3-32829.39" - wire $0\opc_l_r_opc[0:0] - attribute \src "issuer_ls180.v:32965.3-32973.6" - wire $0\opc_l_s_opc$next[0:0]$1144 - attribute \src "issuer_ls180.v:32830.3-32831.39" - wire $0\opc_l_s_opc[0:0] - attribute \src "issuer_ls180.v:33188.3-33196.6" - wire width 3 $0\prev_wr_go$next[2:0]$1223 - attribute \src "issuer_ls180.v:32840.3-32841.37" - wire width 3 $0\prev_wr_go[2:0] - attribute \src "issuer_ls180.v:32919.3-32928.6" - wire $0\req_done[0:0] - attribute \src "issuer_ls180.v:33010.3-33018.6" - wire width 3 $0\req_l_r_req$next[2:0]$1159 - attribute \src "issuer_ls180.v:32820.3-32821.39" - wire width 3 $0\req_l_r_req[2:0] - attribute \src "issuer_ls180.v:33001.3-33009.6" - wire width 3 $0\req_l_s_req$next[2:0]$1156 - attribute \src "issuer_ls180.v:32822.3-32823.39" - wire width 3 $0\req_l_s_req[2:0] - attribute \src "issuer_ls180.v:32938.3-32946.6" - wire $0\rok_l_r_rdok$next[0:0]$1135 - attribute \src "issuer_ls180.v:32836.3-32837.41" - wire $0\rok_l_r_rdok[0:0] - attribute \src "issuer_ls180.v:32929.3-32937.6" - wire $0\rok_l_s_rdok$next[0:0]$1132 - attribute \src "issuer_ls180.v:32838.3-32839.41" - wire $0\rok_l_s_rdok[0:0] - attribute \src "issuer_ls180.v:32956.3-32964.6" - wire $0\rst_l_r_rst$next[0:0]$1141 - attribute \src "issuer_ls180.v:32832.3-32833.39" - wire $0\rst_l_r_rst[0:0] - attribute \src "issuer_ls180.v:32947.3-32955.6" - wire $0\rst_l_s_rst$next[0:0]$1138 - attribute \src "issuer_ls180.v:32834.3-32835.39" - wire $0\rst_l_s_rst[0:0] - attribute \src "issuer_ls180.v:32992.3-33000.6" - wire width 3 $0\src_l_r_src$next[2:0]$1153 - attribute \src "issuer_ls180.v:32824.3-32825.39" - wire width 3 $0\src_l_r_src[2:0] - attribute \src "issuer_ls180.v:32983.3-32991.6" - wire width 3 $0\src_l_s_src$next[2:0]$1150 - attribute \src "issuer_ls180.v:32826.3-32827.39" - wire width 3 $0\src_l_s_src[2:0] - attribute \src "issuer_ls180.v:33110.3-33119.6" - wire width 64 $0\src_r0$next[63:0]$1205 - attribute \src "issuer_ls180.v:32790.3-32791.29" - wire width 64 $0\src_r0[63:0] - attribute \src "issuer_ls180.v:33120.3-33129.6" - wire width 64 $0\src_r1$next[63:0]$1208 - attribute \src "issuer_ls180.v:32788.3-32789.29" - wire width 64 $0\src_r1[63:0] - attribute \src "issuer_ls180.v:33130.3-33139.6" - wire width 4 $0\src_r2$next[3:0]$1211 - attribute \src "issuer_ls180.v:32786.3-32787.29" - wire width 4 $0\src_r2[3:0] - attribute \src "issuer_ls180.v:32297.7-32297.24" - wire $1\all_rd_dly[0:0] - attribute \src "issuer_ls180.v:33019.3-33043.6" - wire width 64 $1\alu_branch0_br_op__cia$next[63:0]$1170 - attribute \src "issuer_ls180.v:32305.14-32305.59" - wire width 64 $1\alu_branch0_br_op__cia[63:0] - attribute \src "issuer_ls180.v:33019.3-33043.6" - wire width 12 $1\alu_branch0_br_op__fn_unit$next[11:0]$1171 - attribute \src "issuer_ls180.v:32322.14-32322.50" - wire width 12 $1\alu_branch0_br_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:33019.3-33043.6" - wire width 64 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1172 - attribute \src "issuer_ls180.v:32326.14-32326.70" - wire width 64 $1\alu_branch0_br_op__imm_data__data[63:0] - attribute \src "issuer_ls180.v:33019.3-33043.6" - wire $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1173 - attribute \src "issuer_ls180.v:32330.7-32330.45" - wire $1\alu_branch0_br_op__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:33019.3-33043.6" - wire width 32 $1\alu_branch0_br_op__insn$next[31:0]$1174 - attribute \src "issuer_ls180.v:32334.14-32334.45" - wire width 32 $1\alu_branch0_br_op__insn[31:0] - attribute \src "issuer_ls180.v:33019.3-33043.6" - wire width 7 $1\alu_branch0_br_op__insn_type$next[6:0]$1175 - attribute \src "issuer_ls180.v:32412.13-32412.49" - wire width 7 $1\alu_branch0_br_op__insn_type[6:0] - attribute \src "issuer_ls180.v:33019.3-33043.6" - wire $1\alu_branch0_br_op__is_32bit$next[0:0]$1176 - attribute \src "issuer_ls180.v:32416.7-32416.41" - wire $1\alu_branch0_br_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:33019.3-33043.6" - wire $1\alu_branch0_br_op__lk$next[0:0]$1177 - attribute \src "issuer_ls180.v:32420.7-32420.35" - wire $1\alu_branch0_br_op__lk[0:0] - attribute \src "issuer_ls180.v:32446.7-32446.26" - wire $1\alu_done_dly[0:0] - attribute \src "issuer_ls180.v:33149.3-33157.6" - wire $1\alu_l_r_alu$next[0:0]$1218 - attribute \src "issuer_ls180.v:32454.7-32454.25" - wire $1\alu_l_r_alu[0:0] - attribute \src "issuer_ls180.v:33140.3-33148.6" - wire $1\alui_l_r_alui$next[0:0]$1215 - attribute \src "issuer_ls180.v:32466.7-32466.27" - wire $1\alui_l_r_alui[0:0] - attribute \src "issuer_ls180.v:33044.3-33065.6" - wire width 64 $1\data_r0__fast1$next[63:0]$1183 - attribute \src "issuer_ls180.v:32498.14-32498.51" - wire width 64 $1\data_r0__fast1[63:0] - attribute \src "issuer_ls180.v:33044.3-33065.6" - wire $1\data_r0__fast1_ok$next[0:0]$1184 - attribute \src "issuer_ls180.v:32502.7-32502.31" - wire $1\data_r0__fast1_ok[0:0] - attribute \src "issuer_ls180.v:33066.3-33087.6" - wire width 64 $1\data_r1__fast2$next[63:0]$1191 - attribute \src "issuer_ls180.v:32506.14-32506.51" - wire width 64 $1\data_r1__fast2[63:0] - attribute \src "issuer_ls180.v:33066.3-33087.6" - wire $1\data_r1__fast2_ok$next[0:0]$1192 - attribute \src "issuer_ls180.v:32510.7-32510.31" - wire $1\data_r1__fast2_ok[0:0] - attribute \src "issuer_ls180.v:33088.3-33109.6" - wire width 64 $1\data_r2__nia$next[63:0]$1199 - attribute \src "issuer_ls180.v:32514.14-32514.49" - wire width 64 $1\data_r2__nia[63:0] - attribute \src "issuer_ls180.v:33088.3-33109.6" - wire $1\data_r2__nia_ok$next[0:0]$1200 - attribute \src "issuer_ls180.v:32518.7-32518.29" - wire $1\data_r2__nia_ok[0:0] - attribute \src "issuer_ls180.v:33158.3-33167.6" - wire width 64 $1\dest1_o[63:0] - attribute \src "issuer_ls180.v:33168.3-33177.6" - wire width 64 $1\dest2_o[63:0] - attribute \src "issuer_ls180.v:33178.3-33187.6" - wire width 64 $1\dest3_o[63:0] - attribute \src "issuer_ls180.v:32974.3-32982.6" - wire $1\opc_l_r_opc$next[0:0]$1148 - attribute \src "issuer_ls180.v:32539.7-32539.25" - wire $1\opc_l_r_opc[0:0] - attribute \src "issuer_ls180.v:32965.3-32973.6" - wire $1\opc_l_s_opc$next[0:0]$1145 - attribute \src "issuer_ls180.v:32543.7-32543.25" - wire $1\opc_l_s_opc[0:0] - attribute \src "issuer_ls180.v:33188.3-33196.6" - wire width 3 $1\prev_wr_go$next[2:0]$1224 - attribute \src "issuer_ls180.v:32650.13-32650.30" - wire width 3 $1\prev_wr_go[2:0] - attribute \src "issuer_ls180.v:32919.3-32928.6" - wire $1\req_done[0:0] - attribute \src "issuer_ls180.v:33010.3-33018.6" - wire width 3 $1\req_l_r_req$next[2:0]$1160 - attribute \src "issuer_ls180.v:32658.13-32658.31" - wire width 3 $1\req_l_r_req[2:0] - attribute \src "issuer_ls180.v:33001.3-33009.6" - wire width 3 $1\req_l_s_req$next[2:0]$1157 - attribute \src "issuer_ls180.v:32662.13-32662.31" - wire width 3 $1\req_l_s_req[2:0] - attribute \src "issuer_ls180.v:32938.3-32946.6" - wire $1\rok_l_r_rdok$next[0:0]$1136 - attribute \src "issuer_ls180.v:32674.7-32674.26" - wire $1\rok_l_r_rdok[0:0] - attribute \src "issuer_ls180.v:32929.3-32937.6" - wire $1\rok_l_s_rdok$next[0:0]$1133 - attribute \src "issuer_ls180.v:32678.7-32678.26" - wire $1\rok_l_s_rdok[0:0] - attribute \src "issuer_ls180.v:32956.3-32964.6" - wire $1\rst_l_r_rst$next[0:0]$1142 - attribute \src "issuer_ls180.v:32682.7-32682.25" - wire $1\rst_l_r_rst[0:0] - attribute \src "issuer_ls180.v:32947.3-32955.6" - wire $1\rst_l_s_rst$next[0:0]$1139 - attribute \src "issuer_ls180.v:32686.7-32686.25" - wire $1\rst_l_s_rst[0:0] - attribute \src "issuer_ls180.v:32992.3-33000.6" - wire width 3 $1\src_l_r_src$next[2:0]$1154 - attribute \src "issuer_ls180.v:32700.13-32700.31" - wire width 3 $1\src_l_r_src[2:0] - attribute \src "issuer_ls180.v:32983.3-32991.6" - wire width 3 $1\src_l_s_src$next[2:0]$1151 - attribute \src "issuer_ls180.v:32704.13-32704.31" - wire width 3 $1\src_l_s_src[2:0] - attribute \src "issuer_ls180.v:33110.3-33119.6" - wire width 64 $1\src_r0$next[63:0]$1206 - attribute \src "issuer_ls180.v:32710.14-32710.43" - wire width 64 $1\src_r0[63:0] - attribute \src "issuer_ls180.v:33120.3-33129.6" - wire width 64 $1\src_r1$next[63:0]$1209 - attribute \src "issuer_ls180.v:32714.14-32714.43" - wire width 64 $1\src_r1[63:0] - attribute \src "issuer_ls180.v:33130.3-33139.6" - wire width 4 $1\src_r2$next[3:0]$1212 - attribute \src "issuer_ls180.v:32718.13-32718.26" - wire width 4 $1\src_r2[3:0] - attribute \src "issuer_ls180.v:33019.3-33043.6" - wire width 64 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1178 - attribute \src "issuer_ls180.v:33019.3-33043.6" - wire $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1179 - attribute \src "issuer_ls180.v:33044.3-33065.6" - wire width 64 $2\data_r0__fast1$next[63:0]$1185 - attribute \src "issuer_ls180.v:33044.3-33065.6" - wire $2\data_r0__fast1_ok$next[0:0]$1186 - attribute \src "issuer_ls180.v:33066.3-33087.6" - wire width 64 $2\data_r1__fast2$next[63:0]$1193 - attribute \src "issuer_ls180.v:33066.3-33087.6" - wire $2\data_r1__fast2_ok$next[0:0]$1194 - attribute \src "issuer_ls180.v:33088.3-33109.6" - wire width 64 $2\data_r2__nia$next[63:0]$1201 - attribute \src "issuer_ls180.v:33088.3-33109.6" - wire $2\data_r2__nia_ok$next[0:0]$1202 - attribute \src "issuer_ls180.v:33044.3-33065.6" - wire $3\data_r0__fast1_ok$next[0:0]$1187 - attribute \src "issuer_ls180.v:33066.3-33087.6" - wire $3\data_r1__fast2_ok$next[0:0]$1195 - attribute \src "issuer_ls180.v:33088.3-33109.6" - wire $3\data_r2__nia_ok$next[0:0]$1203 - attribute \src "issuer_ls180.v:32726.18-32726.112" - wire width 3 $and$issuer_ls180.v:32726$1042_Y - attribute \src "issuer_ls180.v:32727.19-32727.125" - wire $and$issuer_ls180.v:32727$1043_Y - attribute \src "issuer_ls180.v:32728.19-32728.125" - wire $and$issuer_ls180.v:32728$1044_Y - attribute \src "issuer_ls180.v:32729.19-32729.125" - wire $and$issuer_ls180.v:32729$1045_Y - attribute \src "issuer_ls180.v:32730.19-32730.141" - wire width 3 $and$issuer_ls180.v:32730$1046_Y - attribute \src "issuer_ls180.v:32731.19-32731.121" - wire width 3 $and$issuer_ls180.v:32731$1047_Y - attribute \src "issuer_ls180.v:32732.19-32732.127" - wire $and$issuer_ls180.v:32732$1048_Y - attribute \src "issuer_ls180.v:32733.19-32733.127" - wire $and$issuer_ls180.v:32733$1049_Y - attribute \src "issuer_ls180.v:32734.19-32734.127" - wire $and$issuer_ls180.v:32734$1050_Y - attribute \src "issuer_ls180.v:32735.18-32735.110" - wire $and$issuer_ls180.v:32735$1051_Y - attribute \src "issuer_ls180.v:32737.18-32737.98" - wire $and$issuer_ls180.v:32737$1053_Y - attribute \src "issuer_ls180.v:32739.18-32739.100" - wire $and$issuer_ls180.v:32739$1055_Y - attribute \src "issuer_ls180.v:32740.18-32740.149" - wire width 3 $and$issuer_ls180.v:32740$1056_Y - attribute \src "issuer_ls180.v:32742.18-32742.119" - wire width 3 $and$issuer_ls180.v:32742$1058_Y - attribute \src "issuer_ls180.v:32745.18-32745.116" - wire $and$issuer_ls180.v:32745$1061_Y - attribute \src "issuer_ls180.v:32749.17-32749.123" - wire $and$issuer_ls180.v:32749$1065_Y - attribute \src "issuer_ls180.v:32751.18-32751.113" - wire $and$issuer_ls180.v:32751$1067_Y - attribute \src "issuer_ls180.v:32752.18-32752.125" - wire width 3 $and$issuer_ls180.v:32752$1068_Y - attribute \src "issuer_ls180.v:32754.18-32754.112" - wire $and$issuer_ls180.v:32754$1070_Y - attribute \src "issuer_ls180.v:32756.18-32756.129" - wire $and$issuer_ls180.v:32756$1072_Y - attribute \src "issuer_ls180.v:32757.18-32757.129" - wire $and$issuer_ls180.v:32757$1073_Y - attribute \src "issuer_ls180.v:32758.18-32758.117" - wire $and$issuer_ls180.v:32758$1074_Y - attribute \src "issuer_ls180.v:32763.18-32763.133" - wire $and$issuer_ls180.v:32763$1079_Y - attribute \src "issuer_ls180.v:32764.18-32764.124" - wire width 3 $and$issuer_ls180.v:32764$1080_Y - attribute \src "issuer_ls180.v:32767.18-32767.120" - wire $and$issuer_ls180.v:32767$1083_Y - attribute \src "issuer_ls180.v:32768.18-32768.120" - wire $and$issuer_ls180.v:32768$1084_Y - attribute \src "issuer_ls180.v:32769.18-32769.118" - wire $and$issuer_ls180.v:32769$1085_Y - attribute \src "issuer_ls180.v:32775.18-32775.137" - wire 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\$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - wire \$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 3 \$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - wire \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 3 \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 3 \$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 3 \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - wire \all_rd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \all_rd_dly$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" - wire \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \all_rd_rise - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_branch0_br_op__cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_branch0_br_op__cia$next + attribute \src "libresoc.v:22294.3-22396.6" + wire width 8 $1\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:22706.3-22808.6" + wire $1\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:24045.3-24147.6" + wire width 3 $1\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:24148.3-24250.6" + wire width 3 $1\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:22191.3-22293.6" + wire width 2 $1\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:22603.3-22705.6" + wire $1\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:23530.3-23632.6" + wire width 5 $1\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:21779.3-21881.6" + wire width 12 $1\dec31_dec_sub15_function_unit[11:0] + attribute \src "libresoc.v:23633.3-23735.6" + wire width 3 $1\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:23736.3-23838.6" + wire width 4 $1\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:23839.3-23941.6" + wire width 2 $1\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:22912.3-23014.6" + wire width 7 $1\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:22397.3-22499.6" + wire $1\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:22500.3-22602.6" + wire $1\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:23118.3-23220.6" + wire $1\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:21882.3-21984.6" + wire width 4 $1\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:23324.3-23426.6" + wire $1\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:23942.3-24044.6" + wire width 2 $1\dec31_dec_sub15_out_sel[1:0] + attribute \src "libresoc.v:22088.3-22190.6" + wire width 2 $1\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:23015.3-23117.6" + wire $1\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:23427.3-23529.6" + wire $1\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:23221.3-23323.6" + wire $1\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:22809.3-22911.6" + wire $1\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:21985.3-22087.6" + wire width 2 $1\dec31_dec_sub15_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub15_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub15_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub15_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub15_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub15_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub15_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub15_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -48404,22 +30418,39 @@ module \branch0 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_branch0_br_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_branch0_br_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_branch0_br_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_branch0_br_op__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_branch0_br_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_branch0_br_op__imm_data__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_branch0_br_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_branch0_br_op__insn$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub15_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub15_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub15_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub15_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -48494,11449 +30525,3761 @@ module \branch0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_branch0_br_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_branch0_br_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_branch0_br_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_branch0_br_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_branch0_br_op__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_branch0_br_op__lk$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \alu_branch0_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_branch0_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_branch0_fast1$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_branch0_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_branch0_fast2$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \alu_branch0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \alu_branch0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_branch0_nia - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \alu_branch0_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \alu_branch0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" - wire \alu_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \alu_done_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \alu_l_s_alu - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 3 \alu_pulsem - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 26 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 25 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 10 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 9 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 13 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 12 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 11 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" - wire \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 19 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 18 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 3 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__fast1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r0__fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r0__fast1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r1__fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r1__fast2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r1__fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r1__fast2_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r2__nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r2__nia$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r2__nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r2__nia_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 21 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 22 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 24 \dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 17 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 20 \fast2_ok - attribute \src "issuer_ls180.v:32179.7-32179.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub15_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub15_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub15_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub15_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub15_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub15_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub15_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub15_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub15_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub15_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub15_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub15_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub15_upd + attribute \src "libresoc.v:21522.7-21522.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 23 \nia_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 1 \oper_i_alu_branch0__cia - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 3 \oper_i_alu_branch0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 5 \oper_i_alu_branch0__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \oper_i_alu_branch0__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 4 \oper_i_alu_branch0__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 2 \oper_i_alu_branch0__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \oper_i_alu_branch0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \oper_i_alu_branch0__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 3 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 3 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" - wire \req_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \req_l_r_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \req_l_s_req$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" - wire \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 3 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" - wire width 3 \reset_w - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \rok_l_r_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \rok_l_s_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \rst_l_r_rst$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \rst_l_s_rst$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" - wire \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 15 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 16 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 14 \src3_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 \src_l_q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 4 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 4 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - wire \src_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" - wire \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$issuer_ls180.v:32726$1042 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$95 - connect \B \$97 - connect \Y $and$issuer_ls180.v:32726$1042_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$issuer_ls180.v:32727$1043 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $and$issuer_ls180.v:32727$1043_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$issuer_ls180.v:32728$1044 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $and$issuer_ls180.v:32728$1044_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$issuer_ls180.v:32729$1045 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $and$issuer_ls180.v:32729$1045_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$issuer_ls180.v:32730$1046 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \req_l_q_req - connect \B { \$101 \$103 \$105 } - connect \Y $and$issuer_ls180.v:32730$1046_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$issuer_ls180.v:32731$1047 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$107 - connect \B \cu_wrmask_o - connect \Y $and$issuer_ls180.v:32731$1047_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$issuer_ls180.v:32732$1048 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:32732$1048_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$issuer_ls180.v:32733$1049 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:32733$1049_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$issuer_ls180.v:32734$1050 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [2] - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:32734$1050_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$issuer_ls180.v:32735$1051 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \$5 - connect \Y $and$issuer_ls180.v:32735$1051_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:32737$1053 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd - connect \B \$13 - connect \Y $and$issuer_ls180.v:32737$1053_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:32739$1055 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done - connect \B \$17 - connect \Y $and$issuer_ls180.v:32739$1055_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$issuer_ls180.v:32740$1056 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$issuer_ls180.v:32740$1056_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$issuer_ls180.v:32742$1058 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__rel_o - connect \B \$25 - connect \Y $and$issuer_ls180.v:32742$1058_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$issuer_ls180.v:32745$1061 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \$23 - connect \Y $and$issuer_ls180.v:32745$1061_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$issuer_ls180.v:32749$1065 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \rok_l_q_rdok - connect \Y $and$issuer_ls180.v:32749$1065_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$issuer_ls180.v:32751$1067 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_any - connect \B \$39 - connect \Y $and$issuer_ls180.v:32751$1067_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$issuer_ls180.v:32752$1068 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \req_l_q_req - connect \B \cu_wrmask_o - connect \Y $and$issuer_ls180.v:32752$1068_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$issuer_ls180.v:32754$1070 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$41 - connect \B \$45 - connect \Y $and$issuer_ls180.v:32754$1070_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$issuer_ls180.v:32756$1072 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$49 - connect \B \alu_branch0_n_ready_i - connect \Y $and$issuer_ls180.v:32756$1072_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$issuer_ls180.v:32757$1073 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$51 - connect \B \alu_branch0_n_valid_o - connect \Y $and$issuer_ls180.v:32757$1073_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$issuer_ls180.v:32758$1074 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$53 - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:32758$1074_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$issuer_ls180.v:32763$1079 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_branch0_n_valid_o - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:32763$1079_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$issuer_ls180.v:32764$1080 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $and$issuer_ls180.v:32764$1080_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$issuer_ls180.v:32767$1083 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fast1_ok - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:32767$1083_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$issuer_ls180.v:32768$1084 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fast2_ok - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:32768$1084_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$issuer_ls180.v:32769$1085 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \nia_ok - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:32769$1085_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$issuer_ls180.v:32775$1091 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_branch0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $and$issuer_ls180.v:32775$1091_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$issuer_ls180.v:32777$1093 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_branch0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $and$issuer_ls180.v:32777$1093_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$issuer_ls180.v:32778$1094 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$issuer_ls180.v:32778$1094_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$issuer_ls180.v:32780$1096 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$91 - connect \B { 1'1 \$93 1'1 } - connect \Y $and$issuer_ls180.v:32780$1096_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$issuer_ls180.v:32753$1069 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$43 - connect \B 1'0 - connect \Y $eq$issuer_ls180.v:32753$1069_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$issuer_ls180.v:32755$1071 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o - connect \B 1'0 - connect \Y $eq$issuer_ls180.v:32755$1071_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:32736$1052 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $not$issuer_ls180.v:32736$1052_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:32738$1054 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $not$issuer_ls180.v:32738$1054_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$issuer_ls180.v:32741$1057 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wrmask_o - connect \Y $not$issuer_ls180.v:32741$1057_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$issuer_ls180.v:32744$1060 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:32744$1060_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$issuer_ls180.v:32750$1066 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_branch0_n_ready_i - connect \Y $not$issuer_ls180.v:32750$1066_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$issuer_ls180.v:32765$1081 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__rel_o - connect \Y $not$issuer_ls180.v:32765$1081_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$issuer_ls180.v:32779$1095 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_branch0_br_op__imm_data__ok - connect \Y $not$issuer_ls180.v:32779$1095_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$issuer_ls180.v:32781$1097 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rdmaskn_i - connect \Y $not$issuer_ls180.v:32781$1097_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$issuer_ls180.v:32748$1064 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$33 - connect \B \$35 - connect \Y $or$issuer_ls180.v:32748$1064_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$issuer_ls180.v:32759$1075 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $or$issuer_ls180.v:32759$1075_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$issuer_ls180.v:32760$1076 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $or$issuer_ls180.v:32760$1076_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$issuer_ls180.v:32761$1077 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$issuer_ls180.v:32761$1077_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$issuer_ls180.v:32762$1078 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$issuer_ls180.v:32762$1078_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$issuer_ls180.v:32766$1082 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $or$issuer_ls180.v:32766$1082_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$issuer_ls180.v:32776$1092 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$6 - connect \B \cu_rd__go_i - connect \Y $or$issuer_ls180.v:32776$1092_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$issuer_ls180.v:32725$1041 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $reduce_and$issuer_ls180.v:32725$1041_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$issuer_ls180.v:32743$1059 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \$27 - connect \Y $reduce_or$issuer_ls180.v:32743$1059_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$issuer_ls180.v:32746$1062 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $reduce_or$issuer_ls180.v:32746$1062_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$issuer_ls180.v:32747$1063 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $reduce_or$issuer_ls180.v:32747$1063_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$issuer_ls180.v:32770$1086 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \alu_branch0_br_op__imm_data__ok - connect \Y $ternary$issuer_ls180.v:32770$1086_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$issuer_ls180.v:32771$1087 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \alu_branch0_br_op__imm_data__data - connect \S \alu_branch0_br_op__imm_data__ok - connect \Y $ternary$issuer_ls180.v:32771$1087_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:32772$1088 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src1_i - connect \S \src_l_q_src [0] - connect \Y $ternary$issuer_ls180.v:32772$1088_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:32773$1089 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $ternary$issuer_ls180.v:32773$1089_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:32774$1090 - parameter \WIDTH 4 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $ternary$issuer_ls180.v:32774$1090_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:32846.15-32870.4" - cell \alu_branch0 \alu_branch0 - connect \br_op__cia \alu_branch0_br_op__cia - connect \br_op__fn_unit \alu_branch0_br_op__fn_unit - connect \br_op__imm_data__data \alu_branch0_br_op__imm_data__data - connect \br_op__imm_data__ok \alu_branch0_br_op__imm_data__ok - connect \br_op__insn \alu_branch0_br_op__insn - connect \br_op__insn_type \alu_branch0_br_op__insn_type - connect \br_op__is_32bit \alu_branch0_br_op__is_32bit - connect \br_op__lk \alu_branch0_br_op__lk - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \alu_branch0_cr_a - connect \fast1 \alu_branch0_fast1 - connect \fast1$1 \alu_branch0_fast1$1 - connect \fast1_ok \fast1_ok - connect \fast2 \alu_branch0_fast2 - connect \fast2$2 \alu_branch0_fast2$2 - connect \fast2_ok \fast2_ok - connect \n_ready_i \alu_branch0_n_ready_i - connect \n_valid_o \alu_branch0_n_valid_o - connect \nia \alu_branch0_nia - connect \nia_ok \nia_ok - connect \p_ready_o \alu_branch0_p_ready_o - connect \p_valid_i \alu_branch0_p_valid_i - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:32871.14-32877.4" - cell \alu_l$29 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:32878.15-32884.4" - cell \alui_l$28 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:32885.14-32891.4" - cell \opc_l$24 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_opc \opc_l_q_opc - connect \r_opc \opc_l_r_opc - connect \s_opc \opc_l_s_opc - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:32892.14-32898.4" - cell \req_l$25 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \r_req \req_l_r_req - connect \s_req \req_l_s_req - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:32899.14-32905.4" - cell \rok_l$27 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \r_rdok \rok_l_r_rdok - connect \s_rdok \rok_l_s_rdok - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:32906.14-32911.4" - cell \rst_l$26 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_rst \rst_l_r_rst - connect \s_rst \rst_l_s_rst - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:32912.14-32918.4" - cell \src_l$23 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_src \src_l_q_src - connect \r_src \src_l_r_src - connect \s_src \src_l_s_src - end - attribute \src "issuer_ls180.v:32179.7-32179.20" - process $proc$issuer_ls180.v:32179$1225 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:21522.7-21522.20" + process $proc$libresoc.v:21522$466 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "issuer_ls180.v:32297.7-32297.24" - process $proc$issuer_ls180.v:32297$1226 - assign { } { } - assign $1\all_rd_dly[0:0] 1'0 - sync always - sync init - update \all_rd_dly $1\all_rd_dly[0:0] - end - attribute \src "issuer_ls180.v:32305.14-32305.59" - process $proc$issuer_ls180.v:32305$1227 - assign { } { } - assign $1\alu_branch0_br_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_branch0_br_op__cia $1\alu_branch0_br_op__cia[63:0] - end - attribute \src "issuer_ls180.v:32322.14-32322.50" - process $proc$issuer_ls180.v:32322$1228 - assign { } { } - assign $1\alu_branch0_br_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \alu_branch0_br_op__fn_unit $1\alu_branch0_br_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:32326.14-32326.70" - process $proc$issuer_ls180.v:32326$1229 - assign { } { } - assign $1\alu_branch0_br_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_branch0_br_op__imm_data__data $1\alu_branch0_br_op__imm_data__data[63:0] - end - attribute \src "issuer_ls180.v:32330.7-32330.45" - process $proc$issuer_ls180.v:32330$1230 - assign { } { } - assign $1\alu_branch0_br_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \alu_branch0_br_op__imm_data__ok $1\alu_branch0_br_op__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:32334.14-32334.45" - process $proc$issuer_ls180.v:32334$1231 - assign { } { } - assign $1\alu_branch0_br_op__insn[31:0] 0 - sync always - sync init - update \alu_branch0_br_op__insn $1\alu_branch0_br_op__insn[31:0] - end - attribute \src "issuer_ls180.v:32412.13-32412.49" - process $proc$issuer_ls180.v:32412$1232 - assign { } { } - assign $1\alu_branch0_br_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \alu_branch0_br_op__insn_type $1\alu_branch0_br_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:32416.7-32416.41" - process $proc$issuer_ls180.v:32416$1233 - assign { } { } - assign $1\alu_branch0_br_op__is_32bit[0:0] 1'0 - sync always - sync init - update \alu_branch0_br_op__is_32bit $1\alu_branch0_br_op__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:32420.7-32420.35" - process $proc$issuer_ls180.v:32420$1234 - assign { } { } - assign $1\alu_branch0_br_op__lk[0:0] 1'0 - sync always - sync init - update \alu_branch0_br_op__lk $1\alu_branch0_br_op__lk[0:0] - end - attribute \src "issuer_ls180.v:32446.7-32446.26" - process $proc$issuer_ls180.v:32446$1235 - assign { } { } - assign $1\alu_done_dly[0:0] 1'0 - sync always - sync init - update \alu_done_dly $1\alu_done_dly[0:0] - end - attribute \src "issuer_ls180.v:32454.7-32454.25" - process $proc$issuer_ls180.v:32454$1236 - assign { } { } - assign $1\alu_l_r_alu[0:0] 1'1 - sync always - sync init - update \alu_l_r_alu $1\alu_l_r_alu[0:0] - end - attribute \src "issuer_ls180.v:32466.7-32466.27" - process $proc$issuer_ls180.v:32466$1237 - assign { } { } - assign $1\alui_l_r_alui[0:0] 1'1 - sync always - sync init - update \alui_l_r_alui $1\alui_l_r_alui[0:0] - end - attribute \src "issuer_ls180.v:32498.14-32498.51" - process $proc$issuer_ls180.v:32498$1238 - assign { } { } - assign $1\data_r0__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r0__fast1 $1\data_r0__fast1[63:0] - end - attribute \src "issuer_ls180.v:32502.7-32502.31" - process $proc$issuer_ls180.v:32502$1239 - assign { } { } - assign $1\data_r0__fast1_ok[0:0] 1'0 - sync always - sync init - update \data_r0__fast1_ok $1\data_r0__fast1_ok[0:0] - end - attribute \src "issuer_ls180.v:32506.14-32506.51" - process $proc$issuer_ls180.v:32506$1240 - assign { } { } - assign $1\data_r1__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r1__fast2 $1\data_r1__fast2[63:0] - end - attribute \src "issuer_ls180.v:32510.7-32510.31" - process $proc$issuer_ls180.v:32510$1241 - assign { } { } - assign $1\data_r1__fast2_ok[0:0] 1'0 - sync always - sync init - update \data_r1__fast2_ok $1\data_r1__fast2_ok[0:0] - end - attribute \src "issuer_ls180.v:32514.14-32514.49" - process $proc$issuer_ls180.v:32514$1242 - assign { } { } - assign $1\data_r2__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r2__nia $1\data_r2__nia[63:0] - end - attribute \src "issuer_ls180.v:32518.7-32518.29" - process $proc$issuer_ls180.v:32518$1243 - assign { } { } - assign $1\data_r2__nia_ok[0:0] 1'0 - sync always - sync init - update \data_r2__nia_ok $1\data_r2__nia_ok[0:0] - end - attribute \src "issuer_ls180.v:32539.7-32539.25" - process $proc$issuer_ls180.v:32539$1244 - assign { } { } - assign $1\opc_l_r_opc[0:0] 1'1 - sync always - sync init - update \opc_l_r_opc $1\opc_l_r_opc[0:0] - end - attribute \src "issuer_ls180.v:32543.7-32543.25" - process $proc$issuer_ls180.v:32543$1245 - assign { } { } - assign $1\opc_l_s_opc[0:0] 1'0 - sync always - sync init - update \opc_l_s_opc $1\opc_l_s_opc[0:0] - end - attribute \src "issuer_ls180.v:32650.13-32650.30" - process $proc$issuer_ls180.v:32650$1246 - assign { } { } - assign $1\prev_wr_go[2:0] 3'000 - sync always - sync init - update \prev_wr_go $1\prev_wr_go[2:0] - end - attribute \src "issuer_ls180.v:32658.13-32658.31" - process $proc$issuer_ls180.v:32658$1247 - assign { } { } - assign $1\req_l_r_req[2:0] 3'111 - sync always - sync init - update \req_l_r_req $1\req_l_r_req[2:0] - end - attribute \src "issuer_ls180.v:32662.13-32662.31" - process $proc$issuer_ls180.v:32662$1248 - assign { } { } - assign $1\req_l_s_req[2:0] 3'000 - sync always - sync init - update \req_l_s_req $1\req_l_s_req[2:0] - end - attribute \src "issuer_ls180.v:32674.7-32674.26" - process $proc$issuer_ls180.v:32674$1249 - assign { } { } - assign $1\rok_l_r_rdok[0:0] 1'1 - sync always - sync init - update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] - end - attribute \src "issuer_ls180.v:32678.7-32678.26" - process $proc$issuer_ls180.v:32678$1250 - assign { } { } - assign $1\rok_l_s_rdok[0:0] 1'0 - sync always - sync init - update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] - end - attribute \src "issuer_ls180.v:32682.7-32682.25" - process $proc$issuer_ls180.v:32682$1251 - assign { } { } - assign $1\rst_l_r_rst[0:0] 1'1 - sync always - sync init - update \rst_l_r_rst $1\rst_l_r_rst[0:0] - end - attribute \src "issuer_ls180.v:32686.7-32686.25" - process $proc$issuer_ls180.v:32686$1252 - assign { } { } - assign $1\rst_l_s_rst[0:0] 1'0 - sync always - sync init - update \rst_l_s_rst $1\rst_l_s_rst[0:0] - end - attribute \src "issuer_ls180.v:32700.13-32700.31" - process $proc$issuer_ls180.v:32700$1253 - assign { } { } - assign $1\src_l_r_src[2:0] 3'111 - sync always - sync init - update \src_l_r_src $1\src_l_r_src[2:0] - end - attribute \src "issuer_ls180.v:32704.13-32704.31" - process $proc$issuer_ls180.v:32704$1254 - assign { } { } - assign $1\src_l_s_src[2:0] 3'000 - sync always - sync init - update \src_l_s_src $1\src_l_s_src[2:0] - end - attribute \src "issuer_ls180.v:32710.14-32710.43" - process $proc$issuer_ls180.v:32710$1255 - assign { } { } - assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r0 $1\src_r0[63:0] - end - attribute \src "issuer_ls180.v:32714.14-32714.43" - process $proc$issuer_ls180.v:32714$1256 - assign { } { } - assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r1 $1\src_r1[63:0] - end - attribute \src "issuer_ls180.v:32718.13-32718.26" - process $proc$issuer_ls180.v:32718$1257 - assign { } { } - assign $1\src_r2[3:0] 4'0000 - sync always - sync init - update \src_r2 $1\src_r2[3:0] - end - attribute \src "issuer_ls180.v:32782.3-32783.39" - process $proc$issuer_ls180.v:32782$1098 - assign { } { } - assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next - sync posedge \coresync_clk - update \alu_l_r_alu $0\alu_l_r_alu[0:0] - end - attribute \src "issuer_ls180.v:32784.3-32785.43" - process $proc$issuer_ls180.v:32784$1099 - assign { } { } - assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next - sync posedge \coresync_clk - update \alui_l_r_alui $0\alui_l_r_alui[0:0] - end - attribute \src "issuer_ls180.v:32786.3-32787.29" - process $proc$issuer_ls180.v:32786$1100 - assign { } { } - assign $0\src_r2[3:0] \src_r2$next - sync posedge \coresync_clk - update \src_r2 $0\src_r2[3:0] - end - attribute \src "issuer_ls180.v:32788.3-32789.29" - process $proc$issuer_ls180.v:32788$1101 - assign { } { } - assign $0\src_r1[63:0] \src_r1$next - sync posedge \coresync_clk - update \src_r1 $0\src_r1[63:0] - end - attribute \src "issuer_ls180.v:32790.3-32791.29" - process $proc$issuer_ls180.v:32790$1102 - assign { } { } - assign $0\src_r0[63:0] \src_r0$next - sync posedge \coresync_clk - update \src_r0 $0\src_r0[63:0] - end - attribute \src "issuer_ls180.v:32792.3-32793.41" - process $proc$issuer_ls180.v:32792$1103 - assign { } { } - assign $0\data_r2__nia[63:0] \data_r2__nia$next - sync posedge \coresync_clk - update \data_r2__nia $0\data_r2__nia[63:0] - end - attribute \src "issuer_ls180.v:32794.3-32795.47" - process $proc$issuer_ls180.v:32794$1104 - assign { } { } - assign $0\data_r2__nia_ok[0:0] \data_r2__nia_ok$next - sync posedge \coresync_clk - update \data_r2__nia_ok $0\data_r2__nia_ok[0:0] - end - attribute \src "issuer_ls180.v:32796.3-32797.45" - process $proc$issuer_ls180.v:32796$1105 - assign { } { } - assign $0\data_r1__fast2[63:0] \data_r1__fast2$next - sync posedge \coresync_clk - update \data_r1__fast2 $0\data_r1__fast2[63:0] - end - attribute \src "issuer_ls180.v:32798.3-32799.51" - process $proc$issuer_ls180.v:32798$1106 - assign { } { } - assign $0\data_r1__fast2_ok[0:0] \data_r1__fast2_ok$next - sync posedge \coresync_clk - update \data_r1__fast2_ok $0\data_r1__fast2_ok[0:0] - end - attribute \src "issuer_ls180.v:32800.3-32801.45" - process $proc$issuer_ls180.v:32800$1107 - assign { } { } - assign $0\data_r0__fast1[63:0] \data_r0__fast1$next - sync posedge \coresync_clk - update \data_r0__fast1 $0\data_r0__fast1[63:0] - end - attribute \src "issuer_ls180.v:32802.3-32803.51" - process $proc$issuer_ls180.v:32802$1108 - assign { } { } - assign $0\data_r0__fast1_ok[0:0] \data_r0__fast1_ok$next - sync posedge \coresync_clk - update \data_r0__fast1_ok $0\data_r0__fast1_ok[0:0] - end - attribute \src "issuer_ls180.v:32804.3-32805.61" - process $proc$issuer_ls180.v:32804$1109 - assign { } { } - assign $0\alu_branch0_br_op__cia[63:0] \alu_branch0_br_op__cia$next - sync posedge \coresync_clk - update \alu_branch0_br_op__cia $0\alu_branch0_br_op__cia[63:0] - end - attribute \src "issuer_ls180.v:32806.3-32807.73" - process $proc$issuer_ls180.v:32806$1110 - assign { } { } - assign $0\alu_branch0_br_op__insn_type[6:0] \alu_branch0_br_op__insn_type$next - sync posedge \coresync_clk - update \alu_branch0_br_op__insn_type $0\alu_branch0_br_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:32808.3-32809.69" - process $proc$issuer_ls180.v:32808$1111 - assign { } { } - assign $0\alu_branch0_br_op__fn_unit[11:0] \alu_branch0_br_op__fn_unit$next - sync posedge \coresync_clk - update \alu_branch0_br_op__fn_unit $0\alu_branch0_br_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:32810.3-32811.63" - process $proc$issuer_ls180.v:32810$1112 - assign { } { } - assign $0\alu_branch0_br_op__insn[31:0] \alu_branch0_br_op__insn$next - sync posedge \coresync_clk - update \alu_branch0_br_op__insn $0\alu_branch0_br_op__insn[31:0] - end - attribute \src "issuer_ls180.v:32812.3-32813.83" - process $proc$issuer_ls180.v:32812$1113 - assign { } { } - assign $0\alu_branch0_br_op__imm_data__data[63:0] \alu_branch0_br_op__imm_data__data$next - sync posedge \coresync_clk - update \alu_branch0_br_op__imm_data__data $0\alu_branch0_br_op__imm_data__data[63:0] - end - attribute \src "issuer_ls180.v:32814.3-32815.79" - process $proc$issuer_ls180.v:32814$1114 - assign { } { } - assign $0\alu_branch0_br_op__imm_data__ok[0:0] \alu_branch0_br_op__imm_data__ok$next - sync posedge \coresync_clk - update \alu_branch0_br_op__imm_data__ok $0\alu_branch0_br_op__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:32816.3-32817.59" - process $proc$issuer_ls180.v:32816$1115 - assign { } { } - assign $0\alu_branch0_br_op__lk[0:0] \alu_branch0_br_op__lk$next - sync posedge \coresync_clk - update \alu_branch0_br_op__lk $0\alu_branch0_br_op__lk[0:0] - end - attribute \src "issuer_ls180.v:32818.3-32819.71" - process $proc$issuer_ls180.v:32818$1116 - assign { } { } - assign $0\alu_branch0_br_op__is_32bit[0:0] \alu_branch0_br_op__is_32bit$next - sync posedge \coresync_clk - update \alu_branch0_br_op__is_32bit $0\alu_branch0_br_op__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:32820.3-32821.39" - process $proc$issuer_ls180.v:32820$1117 - assign { } { } - assign $0\req_l_r_req[2:0] \req_l_r_req$next - sync posedge \coresync_clk - update \req_l_r_req $0\req_l_r_req[2:0] - end - attribute \src "issuer_ls180.v:32822.3-32823.39" - process $proc$issuer_ls180.v:32822$1118 - assign { } { } - assign $0\req_l_s_req[2:0] \req_l_s_req$next - sync posedge \coresync_clk - update \req_l_s_req $0\req_l_s_req[2:0] - end - attribute \src "issuer_ls180.v:32824.3-32825.39" - process $proc$issuer_ls180.v:32824$1119 - assign { } { } - assign $0\src_l_r_src[2:0] \src_l_r_src$next - sync posedge \coresync_clk - update \src_l_r_src $0\src_l_r_src[2:0] - end - attribute \src "issuer_ls180.v:32826.3-32827.39" - process $proc$issuer_ls180.v:32826$1120 - assign { } { } - assign $0\src_l_s_src[2:0] \src_l_s_src$next - sync posedge \coresync_clk - update \src_l_s_src $0\src_l_s_src[2:0] - end - attribute \src "issuer_ls180.v:32828.3-32829.39" - process $proc$issuer_ls180.v:32828$1121 - assign { } { } - assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next - sync posedge \coresync_clk - update \opc_l_r_opc $0\opc_l_r_opc[0:0] - end - attribute \src "issuer_ls180.v:32830.3-32831.39" - process $proc$issuer_ls180.v:32830$1122 - assign { } { } - assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next - sync posedge \coresync_clk - update \opc_l_s_opc $0\opc_l_s_opc[0:0] - end - attribute \src "issuer_ls180.v:32832.3-32833.39" - process $proc$issuer_ls180.v:32832$1123 - assign { } { } - assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next - sync posedge \coresync_clk - update \rst_l_r_rst $0\rst_l_r_rst[0:0] - end - attribute \src "issuer_ls180.v:32834.3-32835.39" - process $proc$issuer_ls180.v:32834$1124 - assign { } { } - assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next - sync posedge \coresync_clk - update \rst_l_s_rst $0\rst_l_s_rst[0:0] - end - attribute \src "issuer_ls180.v:32836.3-32837.41" - process $proc$issuer_ls180.v:32836$1125 - assign { } { } - assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next - sync posedge \coresync_clk - update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] - end - attribute \src "issuer_ls180.v:32838.3-32839.41" - process $proc$issuer_ls180.v:32838$1126 - assign { } { } - assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next - sync posedge \coresync_clk - update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] - end - attribute \src "issuer_ls180.v:32840.3-32841.37" - process $proc$issuer_ls180.v:32840$1127 - assign { } { } - assign $0\prev_wr_go[2:0] \prev_wr_go$next - sync posedge \coresync_clk - update \prev_wr_go $0\prev_wr_go[2:0] - end - attribute \src "issuer_ls180.v:32842.3-32843.43" - process $proc$issuer_ls180.v:32842$1128 - assign { } { } - assign $0\alu_done_dly[0:0] \alu_branch0_n_valid_o - sync posedge \coresync_clk - update \alu_done_dly $0\alu_done_dly[0:0] - end - attribute \src "issuer_ls180.v:32844.3-32845.25" - process $proc$issuer_ls180.v:32844$1129 - assign { } { } - assign $0\all_rd_dly[0:0] \$11 - sync posedge \coresync_clk - update \all_rd_dly $0\all_rd_dly[0:0] - end - attribute \src "issuer_ls180.v:32919.3-32928.6" - process $proc$issuer_ls180.v:32919$1130 + attribute \src "libresoc.v:21779.3-21881.6" + process $proc$libresoc.v:21779$442 assign { } { } assign { } { } - assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "issuer_ls180.v:32920.5-32920.29" + assign $0\dec31_dec_sub15_function_unit[11:0] $1\dec31_dec_sub15_function_unit[11:0] + attribute \src "libresoc.v:21780.5-21780.29" switch \initial - attribute \src "issuer_ls180.v:32920.9-32920.17" + attribute \src "libresoc.v:21780.9-21780.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch \$55 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\req_done[0:0] 1'1 - case - assign $1\req_done[0:0] \$47 - end - sync always - update \req_done $0\req_done[0:0] - end - attribute \src "issuer_ls180.v:32929.3-32937.6" - process $proc$issuer_ls180.v:32929$1131 - assign { } { } - assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$1132 $1\rok_l_s_rdok$next[0:0]$1133 - attribute \src "issuer_ls180.v:32930.5-32930.29" - switch \initial - attribute \src "issuer_ls180.v:32930.9-32930.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$1133 1'0 - case - assign $1\rok_l_s_rdok$next[0:0]$1133 \cu_issue_i - end - sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$1132 - end - attribute \src "issuer_ls180.v:32938.3-32946.6" - process $proc$issuer_ls180.v:32938$1134 - assign { } { } - assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$1135 $1\rok_l_r_rdok$next[0:0]$1136 - attribute \src "issuer_ls180.v:32939.5-32939.29" - switch \initial - attribute \src "issuer_ls180.v:32939.9-32939.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$1136 1'1 - case - assign $1\rok_l_r_rdok$next[0:0]$1136 \$65 - end - sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$1135 - end - attribute \src "issuer_ls180.v:32947.3-32955.6" - process $proc$issuer_ls180.v:32947$1137 - assign { } { } - assign { } { } - assign $0\rst_l_s_rst$next[0:0]$1138 $1\rst_l_s_rst$next[0:0]$1139 - attribute \src "issuer_ls180.v:32948.5-32948.29" - switch \initial - attribute \src "issuer_ls180.v:32948.9-32948.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$1139 1'0 - case - assign $1\rst_l_s_rst$next[0:0]$1139 \all_rd - end - sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$1138 - end - attribute \src "issuer_ls180.v:32956.3-32964.6" - process $proc$issuer_ls180.v:32956$1140 - assign { } { } - assign { } { } - assign $0\rst_l_r_rst$next[0:0]$1141 $1\rst_l_r_rst$next[0:0]$1142 - attribute \src "issuer_ls180.v:32957.5-32957.29" - switch \initial - attribute \src "issuer_ls180.v:32957.9-32957.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$1142 1'1 - case - assign $1\rst_l_r_rst$next[0:0]$1142 \rst_r - end - sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$1141 - end - attribute \src "issuer_ls180.v:32965.3-32973.6" - process $proc$issuer_ls180.v:32965$1143 - assign { } { } - assign { } { } - assign $0\opc_l_s_opc$next[0:0]$1144 $1\opc_l_s_opc$next[0:0]$1145 - attribute \src "issuer_ls180.v:32966.5-32966.29" - switch \initial - attribute \src "issuer_ls180.v:32966.9-32966.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$1145 1'0 - case - assign $1\opc_l_s_opc$next[0:0]$1145 \cu_issue_i - end - sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$1144 - end - attribute \src "issuer_ls180.v:32974.3-32982.6" - process $proc$issuer_ls180.v:32974$1146 - assign { } { } - assign { } { } - assign $0\opc_l_r_opc$next[0:0]$1147 $1\opc_l_r_opc$next[0:0]$1148 - attribute \src "issuer_ls180.v:32975.5-32975.29" - switch \initial - attribute \src "issuer_ls180.v:32975.9-32975.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$1148 1'1 - case - assign $1\opc_l_r_opc$next[0:0]$1148 \req_done - end - sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$1147 - end - attribute \src "issuer_ls180.v:32983.3-32991.6" - process $proc$issuer_ls180.v:32983$1149 - assign { } { } - assign { } { } - assign $0\src_l_s_src$next[2:0]$1150 $1\src_l_s_src$next[2:0]$1151 - attribute \src "issuer_ls180.v:32984.5-32984.29" - switch \initial - attribute \src "issuer_ls180.v:32984.9-32984.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } - assign $1\src_l_s_src$next[2:0]$1151 3'000 - case - assign $1\src_l_s_src$next[2:0]$1151 { \cu_issue_i \cu_issue_i \cu_issue_i } - end - sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$1150 - end - attribute \src "issuer_ls180.v:32992.3-33000.6" - process $proc$issuer_ls180.v:32992$1152 - assign { } { } - assign { } { } - assign $0\src_l_r_src$next[2:0]$1153 $1\src_l_r_src$next[2:0]$1154 - attribute \src "issuer_ls180.v:32993.5-32993.29" - switch \initial - attribute \src "issuer_ls180.v:32993.9-32993.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } - assign $1\src_l_r_src$next[2:0]$1154 3'111 - case - assign $1\src_l_r_src$next[2:0]$1154 \reset_r - end - sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$1153 - end - attribute \src "issuer_ls180.v:33001.3-33009.6" - process $proc$issuer_ls180.v:33001$1155 - assign { } { } - assign { } { } - assign $0\req_l_s_req$next[2:0]$1156 $1\req_l_s_req$next[2:0]$1157 - attribute \src "issuer_ls180.v:33002.5-33002.29" - switch \initial - attribute \src "issuer_ls180.v:33002.9-33002.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } - assign $1\req_l_s_req$next[2:0]$1157 3'000 - case - assign $1\req_l_s_req$next[2:0]$1157 \$67 - end - sync always - update \req_l_s_req$next $0\req_l_s_req$next[2:0]$1156 - end - attribute \src "issuer_ls180.v:33010.3-33018.6" - process $proc$issuer_ls180.v:33010$1158 - assign { } { } - assign { } { } - assign $0\req_l_r_req$next[2:0]$1159 $1\req_l_r_req$next[2:0]$1160 - attribute \src "issuer_ls180.v:33011.5-33011.29" - switch \initial - attribute \src "issuer_ls180.v:33011.9-33011.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } - assign $1\req_l_r_req$next[2:0]$1160 3'111 - case - assign $1\req_l_r_req$next[2:0]$1160 \$69 - end - sync always - update \req_l_r_req$next $0\req_l_r_req$next[2:0]$1159 - end - attribute \src "issuer_ls180.v:33019.3-33043.6" - process $proc$issuer_ls180.v:33019$1161 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_branch0_br_op__cia$next[63:0]$1162 $1\alu_branch0_br_op__cia$next[63:0]$1170 - assign $0\alu_branch0_br_op__fn_unit$next[11:0]$1163 $1\alu_branch0_br_op__fn_unit$next[11:0]$1171 - assign { } { } - assign { } { } - assign $0\alu_branch0_br_op__insn$next[31:0]$1166 $1\alu_branch0_br_op__insn$next[31:0]$1174 - assign $0\alu_branch0_br_op__insn_type$next[6:0]$1167 $1\alu_branch0_br_op__insn_type$next[6:0]$1175 - assign $0\alu_branch0_br_op__is_32bit$next[0:0]$1168 $1\alu_branch0_br_op__is_32bit$next[0:0]$1176 - assign $0\alu_branch0_br_op__lk$next[0:0]$1169 $1\alu_branch0_br_op__lk$next[0:0]$1177 - assign $0\alu_branch0_br_op__imm_data__data$next[63:0]$1164 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1178 - assign $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1165 $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1179 - attribute \src "issuer_ls180.v:33020.5-33020.29" - switch \initial - attribute \src "issuer_ls180.v:33020.9-33020.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 assign { } { } - assign { $1\alu_branch0_br_op__is_32bit$next[0:0]$1176 $1\alu_branch0_br_op__lk$next[0:0]$1177 $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1173 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1172 $1\alu_branch0_br_op__insn$next[31:0]$1174 $1\alu_branch0_br_op__fn_unit$next[11:0]$1171 $1\alu_branch0_br_op__insn_type$next[6:0]$1175 $1\alu_branch0_br_op__cia$next[63:0]$1170 } { \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__lk \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__insn \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__cia } - case - assign $1\alu_branch0_br_op__cia$next[63:0]$1170 \alu_branch0_br_op__cia - assign $1\alu_branch0_br_op__fn_unit$next[11:0]$1171 \alu_branch0_br_op__fn_unit - assign $1\alu_branch0_br_op__imm_data__data$next[63:0]$1172 \alu_branch0_br_op__imm_data__data - assign $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1173 \alu_branch0_br_op__imm_data__ok - assign $1\alu_branch0_br_op__insn$next[31:0]$1174 \alu_branch0_br_op__insn - assign $1\alu_branch0_br_op__insn_type$next[6:0]$1175 \alu_branch0_br_op__insn_type - assign $1\alu_branch0_br_op__is_32bit$next[0:0]$1176 \alu_branch0_br_op__is_32bit - assign $1\alu_branch0_br_op__lk$next[0:0]$1177 \alu_branch0_br_op__lk - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } - assign $2\alu_branch0_br_op__imm_data__data$next[63:0]$1178 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1179 1'0 - case - assign $2\alu_branch0_br_op__imm_data__data$next[63:0]$1178 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1172 - assign $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1179 $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1173 - end - sync always - update \alu_branch0_br_op__cia$next $0\alu_branch0_br_op__cia$next[63:0]$1162 - update \alu_branch0_br_op__fn_unit$next $0\alu_branch0_br_op__fn_unit$next[11:0]$1163 - update \alu_branch0_br_op__imm_data__data$next $0\alu_branch0_br_op__imm_data__data$next[63:0]$1164 - update \alu_branch0_br_op__imm_data__ok$next $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1165 - update \alu_branch0_br_op__insn$next $0\alu_branch0_br_op__insn$next[31:0]$1166 - update \alu_branch0_br_op__insn_type$next $0\alu_branch0_br_op__insn_type$next[6:0]$1167 - update \alu_branch0_br_op__is_32bit$next $0\alu_branch0_br_op__is_32bit$next[0:0]$1168 - update \alu_branch0_br_op__lk$next $0\alu_branch0_br_op__lk$next[0:0]$1169 - end - attribute \src "issuer_ls180.v:33044.3-33065.6" - process $proc$issuer_ls180.v:33044$1180 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r0__fast1$next[63:0]$1181 $2\data_r0__fast1$next[63:0]$1185 - assign { } { } - assign $0\data_r0__fast1_ok$next[0:0]$1182 $3\data_r0__fast1_ok$next[0:0]$1187 - attribute \src "issuer_ls180.v:33045.5-33045.29" - switch \initial - attribute \src "issuer_ls180.v:33045.9-33045.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign { $1\data_r0__fast1_ok$next[0:0]$1184 $1\data_r0__fast1$next[63:0]$1183 } { \fast1_ok \alu_branch0_fast1 } - case - assign $1\data_r0__fast1$next[63:0]$1183 \data_r0__fast1 - assign $1\data_r0__fast1_ok$next[0:0]$1184 \data_r0__fast1_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign { $2\data_r0__fast1_ok$next[0:0]$1186 $2\data_r0__fast1$next[63:0]$1185 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r0__fast1$next[63:0]$1185 $1\data_r0__fast1$next[63:0]$1183 - assign $2\data_r0__fast1_ok$next[0:0]$1186 $1\data_r0__fast1_ok$next[0:0]$1184 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign $3\data_r0__fast1_ok$next[0:0]$1187 1'0 + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 case - assign $3\data_r0__fast1_ok$next[0:0]$1187 $2\data_r0__fast1_ok$next[0:0]$1186 + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000000000000 end sync always - update \data_r0__fast1$next $0\data_r0__fast1$next[63:0]$1181 - update \data_r0__fast1_ok$next $0\data_r0__fast1_ok$next[0:0]$1182 + update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[11:0] end - attribute \src "issuer_ls180.v:33066.3-33087.6" - process $proc$issuer_ls180.v:33066$1188 - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:21882.3-21984.6" + process $proc$libresoc.v:21882$443 assign { } { } assign { } { } - assign $0\data_r1__fast2$next[63:0]$1189 $2\data_r1__fast2$next[63:0]$1193 - assign { } { } - assign $0\data_r1__fast2_ok$next[0:0]$1190 $3\data_r1__fast2_ok$next[0:0]$1195 - attribute \src "issuer_ls180.v:33067.5-33067.29" + assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:21883.5-21883.29" switch \initial - attribute \src "issuer_ls180.v:33067.9-33067.17" + attribute \src "libresoc.v:21883.9-21883.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } - assign { $1\data_r1__fast2_ok$next[0:0]$1192 $1\data_r1__fast2$next[63:0]$1191 } { \fast2_ok \alu_branch0_fast2 } - case - assign $1\data_r1__fast2$next[63:0]$1191 \data_r1__fast2 - assign $1\data_r1__fast2_ok$next[0:0]$1192 \data_r1__fast2_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } - assign { $2\data_r1__fast2_ok$next[0:0]$1194 $2\data_r1__fast2$next[63:0]$1193 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r1__fast2$next[63:0]$1193 $1\data_r1__fast2$next[63:0]$1191 - assign $2\data_r1__fast2_ok$next[0:0]$1194 $1\data_r1__fast2_ok$next[0:0]$1192 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 assign { } { } - assign $3\data_r1__fast2_ok$next[0:0]$1195 1'0 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 case - assign $3\data_r1__fast2_ok$next[0:0]$1195 $2\data_r1__fast2_ok$next[0:0]$1194 + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 end sync always - update \data_r1__fast2$next $0\data_r1__fast2$next[63:0]$1189 - update \data_r1__fast2_ok$next $0\data_r1__fast2_ok$next[0:0]$1190 + update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0] end - attribute \src "issuer_ls180.v:33088.3-33109.6" - process $proc$issuer_ls180.v:33088$1196 - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:21985.3-22087.6" + process $proc$libresoc.v:21985$444 assign { } { } assign { } { } - assign { } { } - assign $0\data_r2__nia$next[63:0]$1197 $2\data_r2__nia$next[63:0]$1201 - assign { } { } - assign $0\data_r2__nia_ok$next[0:0]$1198 $3\data_r2__nia_ok$next[0:0]$1203 - attribute \src "issuer_ls180.v:33089.5-33089.29" + assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] + attribute \src "libresoc.v:21986.5-21986.29" switch \initial - attribute \src "issuer_ls180.v:33089.9-33089.17" + attribute \src "libresoc.v:21986.9-21986.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } - assign { $1\data_r2__nia_ok$next[0:0]$1200 $1\data_r2__nia$next[63:0]$1199 } { \nia_ok \alu_branch0_nia } - case - assign $1\data_r2__nia$next[63:0]$1199 \data_r2__nia - assign $1\data_r2__nia_ok$next[0:0]$1200 \data_r2__nia_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } - assign { $2\data_r2__nia_ok$next[0:0]$1202 $2\data_r2__nia$next[63:0]$1201 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r2__nia$next[63:0]$1201 $1\data_r2__nia$next[63:0]$1199 - assign $2\data_r2__nia_ok$next[0:0]$1202 $1\data_r2__nia_ok$next[0:0]$1200 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 assign { } { } - assign $3\data_r2__nia_ok$next[0:0]$1203 1'0 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 case - assign $3\data_r2__nia_ok$next[0:0]$1203 $2\data_r2__nia_ok$next[0:0]$1202 + assign $1\dec31_dec_sub15_upd[1:0] 2'00 end sync always - update \data_r2__nia$next $0\data_r2__nia$next[63:0]$1197 - update \data_r2__nia_ok$next $0\data_r2__nia_ok$next[0:0]$1198 + update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] end - attribute \src "issuer_ls180.v:33110.3-33119.6" - process $proc$issuer_ls180.v:33110$1204 + attribute \src "libresoc.v:22088.3-22190.6" + process $proc$libresoc.v:22088$445 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$1205 $1\src_r0$next[63:0]$1206 - attribute \src "issuer_ls180.v:33111.5-33111.29" + assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:22089.5-22089.29" switch \initial - attribute \src "issuer_ls180.v:33111.9-33111.17" + attribute \src "libresoc.v:22089.9-22089.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\src_r0$next[63:0]$1206 \src1_i - case - assign $1\src_r0$next[63:0]$1206 \src_r0 - end - sync always - update \src_r0$next $0\src_r0$next[63:0]$1205 - end - attribute \src "issuer_ls180.v:33120.3-33129.6" - process $proc$issuer_ls180.v:33120$1207 - assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0] + end + attribute \src "libresoc.v:22191.3-22293.6" + process $proc$libresoc.v:22191$446 assign { } { } - assign $0\src_r1$next[63:0]$1208 $1\src_r1$next[63:0]$1209 - attribute \src "issuer_ls180.v:33121.5-33121.29" + assign { } { } + assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:22192.5-22192.29" switch \initial - attribute \src "issuer_ls180.v:33121.9-33121.17" + attribute \src "libresoc.v:22192.9-22192.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 assign { } { } - assign $1\src_r1$next[63:0]$1209 \src_or_imm + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 case - assign $1\src_r1$next[63:0]$1209 \src_r1 + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 end sync always - update \src_r1$next $0\src_r1$next[63:0]$1208 + update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0] end - attribute \src "issuer_ls180.v:33130.3-33139.6" - process $proc$issuer_ls180.v:33130$1210 + attribute \src "libresoc.v:22294.3-22396.6" + process $proc$libresoc.v:22294$447 assign { } { } assign { } { } - assign $0\src_r2$next[3:0]$1211 $1\src_r2$next[3:0]$1212 - attribute \src "issuer_ls180.v:33131.5-33131.29" + assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:22295.5-22295.29" switch \initial - attribute \src "issuer_ls180.v:33131.9-33131.17" + attribute \src "libresoc.v:22295.9-22295.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 assign { } { } - assign $1\src_r2$next[3:0]$1212 \src3_i + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 case - assign $1\src_r2$next[3:0]$1212 \src_r2 + assign $1\dec31_dec_sub15_asmcode[7:0] 8'00000000 end sync always - update \src_r2$next $0\src_r2$next[3:0]$1211 + update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0] end - attribute \src "issuer_ls180.v:33140.3-33148.6" - process $proc$issuer_ls180.v:33140$1213 + attribute \src "libresoc.v:22397.3-22499.6" + process $proc$libresoc.v:22397$448 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$1214 $1\alui_l_r_alui$next[0:0]$1215 - attribute \src "issuer_ls180.v:33141.5-33141.29" + assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:22398.5-22398.29" switch \initial - attribute \src "issuer_ls180.v:33141.9-33141.17" + attribute \src "libresoc.v:22398.9-22398.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$1215 1'1 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 case - assign $1\alui_l_r_alui$next[0:0]$1215 \$87 + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$1214 + update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0] end - attribute \src "issuer_ls180.v:33149.3-33157.6" - process $proc$issuer_ls180.v:33149$1216 + attribute \src "libresoc.v:22500.3-22602.6" + process $proc$libresoc.v:22500$449 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$1217 $1\alu_l_r_alu$next[0:0]$1218 - attribute \src "issuer_ls180.v:33150.5-33150.29" + assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:22501.5-22501.29" switch \initial - attribute \src "issuer_ls180.v:33150.9-33150.17" + attribute \src "libresoc.v:22501.9-22501.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$1218 1'1 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 case - assign $1\alu_l_r_alu$next[0:0]$1218 \$89 + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$1217 + update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0] end - attribute \src "issuer_ls180.v:33158.3-33167.6" - process $proc$issuer_ls180.v:33158$1219 + attribute \src "libresoc.v:22603.3-22705.6" + process $proc$libresoc.v:22603$450 assign { } { } assign { } { } - assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "issuer_ls180.v:33159.5-33159.29" + assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:22604.5-22604.29" switch \initial - attribute \src "issuer_ls180.v:33159.9-33159.17" + attribute \src "libresoc.v:22604.9-22604.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\dest1_o[63:0] \data_r0__fast1 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 case - assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 end sync always - update \dest1_o $0\dest1_o[63:0] + update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0] end - attribute \src "issuer_ls180.v:33168.3-33177.6" - process $proc$issuer_ls180.v:33168$1220 + attribute \src "libresoc.v:22706.3-22808.6" + process $proc$libresoc.v:22706$451 assign { } { } assign { } { } - assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "issuer_ls180.v:33169.5-33169.29" + assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:22707.5-22707.29" switch \initial - attribute \src "issuer_ls180.v:33169.9-33169.17" + attribute \src "libresoc.v:22707.9-22707.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$113 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 assign { } { } - assign $1\dest2_o[63:0] \data_r1__fast2 + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 case - assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dec31_dec_sub15_br[0:0] 1'0 end sync always - update \dest2_o $0\dest2_o[63:0] + update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0] end - attribute \src "issuer_ls180.v:33178.3-33187.6" - process $proc$issuer_ls180.v:33178$1221 + attribute \src "libresoc.v:22809.3-22911.6" + process $proc$libresoc.v:22809$452 assign { } { } assign { } { } - assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "issuer_ls180.v:33179.5-33179.29" + assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:22810.5-22810.29" switch \initial - attribute \src "issuer_ls180.v:33179.9-33179.17" + attribute \src "libresoc.v:22810.9-22810.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$115 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 assign { } { } - assign $1\dest3_o[63:0] \data_r2__nia + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 case - assign $1\dest3_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 end sync always - update \dest3_o $0\dest3_o[63:0] + update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0] end - attribute \src "issuer_ls180.v:33188.3-33196.6" - process $proc$issuer_ls180.v:33188$1222 + attribute \src "libresoc.v:22912.3-23014.6" + process $proc$libresoc.v:22912$453 assign { } { } assign { } { } - assign $0\prev_wr_go$next[2:0]$1223 $1\prev_wr_go$next[2:0]$1224 - attribute \src "issuer_ls180.v:33189.5-33189.29" + assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:22913.5-22913.29" switch \initial - attribute \src "issuer_ls180.v:33189.9-33189.17" + attribute \src "libresoc.v:22913.9-22913.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\prev_wr_go$next[2:0]$1224 3'000 - case - assign $1\prev_wr_go$next[2:0]$1224 \$21 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[2:0]$1223 - end - connect \$5 $reduce_and$issuer_ls180.v:32725$1041_Y - connect \$99 $and$issuer_ls180.v:32726$1042_Y - connect \$101 $and$issuer_ls180.v:32727$1043_Y - connect \$103 $and$issuer_ls180.v:32728$1044_Y - connect \$105 $and$issuer_ls180.v:32729$1045_Y - connect \$107 $and$issuer_ls180.v:32730$1046_Y - connect \$109 $and$issuer_ls180.v:32731$1047_Y - connect \$111 $and$issuer_ls180.v:32732$1048_Y - connect \$113 $and$issuer_ls180.v:32733$1049_Y - connect \$115 $and$issuer_ls180.v:32734$1050_Y - connect \$11 $and$issuer_ls180.v:32735$1051_Y - connect \$13 $not$issuer_ls180.v:32736$1052_Y - connect \$15 $and$issuer_ls180.v:32737$1053_Y - connect \$17 $not$issuer_ls180.v:32738$1054_Y - connect \$19 $and$issuer_ls180.v:32739$1055_Y - connect \$21 $and$issuer_ls180.v:32740$1056_Y - connect \$25 $not$issuer_ls180.v:32741$1057_Y - connect \$27 $and$issuer_ls180.v:32742$1058_Y - connect \$24 $reduce_or$issuer_ls180.v:32743$1059_Y - connect \$23 $not$issuer_ls180.v:32744$1060_Y - connect \$31 $and$issuer_ls180.v:32745$1061_Y - connect \$33 $reduce_or$issuer_ls180.v:32746$1062_Y - connect \$35 $reduce_or$issuer_ls180.v:32747$1063_Y - connect \$37 $or$issuer_ls180.v:32748$1064_Y - connect \$3 $and$issuer_ls180.v:32749$1065_Y - connect \$39 $not$issuer_ls180.v:32750$1066_Y - connect \$41 $and$issuer_ls180.v:32751$1067_Y - connect \$43 $and$issuer_ls180.v:32752$1068_Y - connect \$45 $eq$issuer_ls180.v:32753$1069_Y - connect \$47 $and$issuer_ls180.v:32754$1070_Y - connect \$49 $eq$issuer_ls180.v:32755$1071_Y - connect \$51 $and$issuer_ls180.v:32756$1072_Y - connect \$53 $and$issuer_ls180.v:32757$1073_Y - connect \$55 $and$issuer_ls180.v:32758$1074_Y - connect \$57 $or$issuer_ls180.v:32759$1075_Y - connect \$59 $or$issuer_ls180.v:32760$1076_Y - connect \$61 $or$issuer_ls180.v:32761$1077_Y - connect \$63 $or$issuer_ls180.v:32762$1078_Y - connect \$65 $and$issuer_ls180.v:32763$1079_Y - connect \$67 $and$issuer_ls180.v:32764$1080_Y - connect \$6 $not$issuer_ls180.v:32765$1081_Y - connect \$69 $or$issuer_ls180.v:32766$1082_Y - connect \$71 $and$issuer_ls180.v:32767$1083_Y - connect \$73 $and$issuer_ls180.v:32768$1084_Y - connect \$75 $and$issuer_ls180.v:32769$1085_Y - connect \$77 $ternary$issuer_ls180.v:32770$1086_Y - connect \$79 $ternary$issuer_ls180.v:32771$1087_Y - connect \$81 $ternary$issuer_ls180.v:32772$1088_Y - connect \$83 $ternary$issuer_ls180.v:32773$1089_Y - connect \$85 $ternary$issuer_ls180.v:32774$1090_Y - connect \$87 $and$issuer_ls180.v:32775$1091_Y - connect \$8 $or$issuer_ls180.v:32776$1092_Y - connect \$89 $and$issuer_ls180.v:32777$1093_Y - connect \$91 $and$issuer_ls180.v:32778$1094_Y - connect \$93 $not$issuer_ls180.v:32779$1095_Y - connect \$95 $and$issuer_ls180.v:32780$1096_Y - connect \$97 $not$issuer_ls180.v:32781$1097_Y - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 - connect \cu_wr__rel_o \$109 - connect \cu_rd__rel_o \$99 - connect \cu_busy_o \opc_l_q_opc - connect \alu_l_s_alu \all_rd_pulse - connect \alu_branch0_n_ready_i \alu_l_q_alu - connect \alui_l_s_alui \all_rd_pulse - connect \alu_branch0_p_valid_i \alui_l_q_alui - connect \alu_branch0_cr_a \$85 - connect \alu_branch0_fast2$2 \$83 - connect \alu_branch0_fast1$1 \$81 - connect \src_or_imm \$79 - connect \src_sel \$77 - connect \cu_wrmask_o { \$75 \$73 \$71 } - connect \reset_r \$63 - connect \reset_w \$61 - connect \rst_r \$59 - connect \reset \$57 - connect \wr_any \$37 - connect \cu_done_o \$31 - connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } - connect \alu_pulse \alu_done_rise - connect \alu_done_rise \$19 - connect \alu_done_dly$next \alu_done - connect \alu_done \alu_branch0_n_valid_o - connect \all_rd_pulse \all_rd_rise - connect \all_rd_rise \$15 - connect \all_rd_dly$next \all_rd - connect \all_rd \$11 -end -attribute \src "issuer_ls180.v:33231.1-33289.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.busy_l" -attribute \generator "nMigen" -module \busy_l - attribute \src "issuer_ls180.v:33232.7-33232.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:33277.3-33285.6" - wire $0\q_int$next[0:0]$1268 - attribute \src "issuer_ls180.v:33275.3-33276.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:33277.3-33285.6" - wire $1\q_int$next[0:0]$1269 - attribute \src "issuer_ls180.v:33256.7-33256.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:33267.17-33267.96" - wire $and$issuer_ls180.v:33267$1258_Y - attribute \src "issuer_ls180.v:33272.17-33272.96" - wire $and$issuer_ls180.v:33272$1263_Y - attribute \src "issuer_ls180.v:33269.18-33269.94" - wire $not$issuer_ls180.v:33269$1260_Y - attribute \src "issuer_ls180.v:33271.17-33271.93" - wire $not$issuer_ls180.v:33271$1262_Y - attribute \src "issuer_ls180.v:33274.17-33274.93" - wire $not$issuer_ls180.v:33274$1265_Y - attribute \src "issuer_ls180.v:33268.18-33268.99" - wire $or$issuer_ls180.v:33268$1259_Y - attribute \src "issuer_ls180.v:33270.18-33270.100" - wire $or$issuer_ls180.v:33270$1261_Y - attribute \src "issuer_ls180.v:33273.17-33273.98" - wire $or$issuer_ls180.v:33273$1264_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:33232.7-33232.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:33267$1258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:33267$1258_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:33272$1263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:33272$1263_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:33269$1260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_busy - connect \Y $not$issuer_ls180.v:33269$1260_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:33271$1262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_busy - connect \Y $not$issuer_ls180.v:33271$1262_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:33274$1265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_busy - connect \Y $not$issuer_ls180.v:33274$1265_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:33268$1259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_busy - connect \Y $or$issuer_ls180.v:33268$1259_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:33270$1261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_busy - connect \B \q_int - connect \Y $or$issuer_ls180.v:33270$1261_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:33273$1264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_busy - connect \Y $or$issuer_ls180.v:33273$1264_Y - end - attribute \src "issuer_ls180.v:33232.7-33232.20" - process $proc$issuer_ls180.v:33232$1270 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:33256.7-33256.19" - process $proc$issuer_ls180.v:33256$1271 - assign { } { } - assign $1\q_int[0:0] 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + case + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0000000 + end sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:33275.3-33276.27" - process $proc$issuer_ls180.v:33275$1266 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] end - attribute \src "issuer_ls180.v:33277.3-33285.6" - process $proc$issuer_ls180.v:33277$1267 + attribute \src "libresoc.v:23015.3-23117.6" + process $proc$libresoc.v:23015$454 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$1268 $1\q_int$next[0:0]$1269 - attribute \src "issuer_ls180.v:33278.5-33278.29" + assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:23016.5-23016.29" switch \initial - attribute \src "issuer_ls180.v:33278.9-33278.17" + attribute \src "libresoc.v:23016.9-23016.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\q_int$next[0:0]$1269 1'0 - case - assign $1\q_int$next[0:0]$1269 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$1268 - end - connect \$9 $and$issuer_ls180.v:33267$1258_Y - connect \$11 $or$issuer_ls180.v:33268$1259_Y - connect \$13 $not$issuer_ls180.v:33269$1260_Y - connect \$15 $or$issuer_ls180.v:33270$1261_Y - connect \$1 $not$issuer_ls180.v:33271$1262_Y - connect \$3 $and$issuer_ls180.v:33272$1263_Y - connect \$5 $or$issuer_ls180.v:33273$1264_Y - connect \$7 $not$issuer_ls180.v:33274$1265_Y - connect \qlq_busy \$15 - connect \qn_busy \$13 - connect \q_busy \$11 -end -attribute \src "issuer_ls180.v:33293.1-34901.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.main.clz" -attribute \generator "nMigen" -module \clz - attribute \src "issuer_ls180.v:33768.3-33782.6" - wire width 2 $0\cnt_1_0[1:0] - attribute \src "issuer_ls180.v:33858.3-33872.6" - wire width 2 $0\cnt_1_10[1:0] - attribute \src "issuer_ls180.v:33873.3-33887.6" - wire width 2 $0\cnt_1_11[1:0] - attribute \src "issuer_ls180.v:33888.3-33902.6" - wire width 2 $0\cnt_1_12[1:0] - attribute \src "issuer_ls180.v:33903.3-33917.6" - wire width 2 $0\cnt_1_13[1:0] - attribute \src "issuer_ls180.v:33918.3-33932.6" - wire width 2 $0\cnt_1_14[1:0] - attribute \src "issuer_ls180.v:33948.3-33962.6" - wire width 2 $0\cnt_1_15[1:0] - attribute \src "issuer_ls180.v:33963.3-33977.6" - wire width 2 $0\cnt_1_16[1:0] - attribute \src "issuer_ls180.v:33978.3-33992.6" - wire width 2 $0\cnt_1_17[1:0] - attribute \src "issuer_ls180.v:33993.3-34007.6" - wire width 2 $0\cnt_1_18[1:0] - attribute \src "issuer_ls180.v:34008.3-34022.6" - wire width 2 $0\cnt_1_19[1:0] - attribute \src "issuer_ls180.v:33933.3-33947.6" - wire width 2 $0\cnt_1_1[1:0] - attribute \src "issuer_ls180.v:34023.3-34037.6" - wire width 2 $0\cnt_1_20[1:0] - attribute \src "issuer_ls180.v:34038.3-34052.6" - wire width 2 $0\cnt_1_21[1:0] - attribute \src "issuer_ls180.v:34053.3-34067.6" - wire width 2 $0\cnt_1_22[1:0] - attribute \src "issuer_ls180.v:34068.3-34082.6" - wire width 2 $0\cnt_1_23[1:0] - attribute \src "issuer_ls180.v:34083.3-34097.6" - wire width 2 $0\cnt_1_24[1:0] - attribute \src "issuer_ls180.v:34113.3-34127.6" - wire width 2 $0\cnt_1_25[1:0] - attribute \src "issuer_ls180.v:34128.3-34142.6" - wire width 2 $0\cnt_1_26[1:0] - attribute \src "issuer_ls180.v:34143.3-34157.6" - wire width 2 $0\cnt_1_27[1:0] - attribute \src "issuer_ls180.v:34158.3-34172.6" - wire width 2 $0\cnt_1_28[1:0] - attribute \src "issuer_ls180.v:34173.3-34187.6" - wire width 2 $0\cnt_1_29[1:0] - attribute \src "issuer_ls180.v:34098.3-34112.6" - wire width 2 $0\cnt_1_2[1:0] - attribute \src "issuer_ls180.v:34188.3-34202.6" - wire width 2 $0\cnt_1_30[1:0] - attribute \src "issuer_ls180.v:34203.3-34217.6" - wire width 2 $0\cnt_1_31[1:0] - attribute \src "issuer_ls180.v:34338.3-34352.6" - wire width 2 $0\cnt_1_3[1:0] - attribute \src "issuer_ls180.v:34753.3-34767.6" - wire width 2 $0\cnt_1_4[1:0] - attribute \src "issuer_ls180.v:33783.3-33797.6" - wire width 2 $0\cnt_1_5[1:0] - attribute \src "issuer_ls180.v:33798.3-33812.6" - wire width 2 $0\cnt_1_6[1:0] - attribute \src "issuer_ls180.v:33813.3-33827.6" - wire width 2 $0\cnt_1_7[1:0] - attribute \src "issuer_ls180.v:33828.3-33842.6" - wire width 2 $0\cnt_1_8[1:0] - attribute \src "issuer_ls180.v:33843.3-33857.6" - wire width 2 $0\cnt_1_9[1:0] - attribute \src "issuer_ls180.v:34218.3-34237.6" - wire width 3 $0\cnt_2_0[2:0] - attribute \src "issuer_ls180.v:34318.3-34337.6" - wire width 3 $0\cnt_2_10[2:0] - attribute \src "issuer_ls180.v:34353.3-34372.6" - wire width 3 $0\cnt_2_12[2:0] - attribute \src "issuer_ls180.v:34373.3-34392.6" - wire width 3 $0\cnt_2_14[2:0] - attribute \src "issuer_ls180.v:34393.3-34412.6" - wire width 3 $0\cnt_2_16[2:0] - attribute \src "issuer_ls180.v:34413.3-34432.6" - wire width 3 $0\cnt_2_18[2:0] - attribute \src "issuer_ls180.v:34433.3-34452.6" - wire width 3 $0\cnt_2_20[2:0] - attribute \src "issuer_ls180.v:34453.3-34472.6" - wire width 3 $0\cnt_2_22[2:0] - attribute \src "issuer_ls180.v:34473.3-34492.6" - wire width 3 $0\cnt_2_24[2:0] - attribute \src "issuer_ls180.v:34493.3-34512.6" - wire width 3 $0\cnt_2_26[2:0] - attribute \src "issuer_ls180.v:34513.3-34532.6" - wire width 3 $0\cnt_2_28[2:0] - attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 5 \cnt_4_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 5 \cnt_4_2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 5 \cnt_4_4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 5 \cnt_4_6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 6 \cnt_5_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 6 \cnt_5_2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 7 \cnt_6_0 - attribute \src "issuer_ls180.v:33294.7-33294.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" - wire width 7 output 1 \lz - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair18 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair34 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair36 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair38 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair40 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair42 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair44 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair46 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair48 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair50 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair52 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair54 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair56 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair58 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair60 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair62 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:11" - wire width 64 input 2 \sig_in - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33675$1272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_2 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33675$1272_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33676$1273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_0 [2] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33676$1273_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33678$1275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_6 [2] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33678$1275_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33679$1276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_4 [2] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33679$1276_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33681$1278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_10 [2] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33681$1278_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33682$1279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_8 [2] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33682$1279_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33684$1281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_14 [2] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33684$1281_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33685$1282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_12 [2] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33685$1282_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33688$1285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_18 [2] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33688$1285_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33689$1286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_16 [2] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33689$1286_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33691$1288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_22 [2] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33691$1288_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33692$1289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_20 [2] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33692$1289_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33694$1291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_26 [2] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33694$1291_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33695$1292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_24 [2] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33695$1292_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33697$1294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_5 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33697$1294_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33698$1295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_30 [2] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33698$1295_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33699$1296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_28 [2] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33699$1296_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33701$1298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_2 [3] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33701$1298_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33702$1299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_0 [3] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33702$1299_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33704$1301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_6 [3] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33704$1301_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33705$1302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_4 [3] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33705$1302_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33707$1304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_10 [3] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33707$1304_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33708$1305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_4 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33708$1305_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33709$1306 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_8 [3] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33709$1306_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33711$1308 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_14 [3] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33711$1308_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33712$1309 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_12 [3] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33712$1309_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33714$1311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_4_2 [4] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33714$1311_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33715$1312 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_4_0 [4] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33715$1312_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33717$1314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_4_6 [4] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33717$1314_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33718$1315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_4_4 [4] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33718$1315_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33721$1318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_5_2 [5] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33721$1318_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33722$1319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_5_0 [5] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33722$1319_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33724$1321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_1 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33724$1321_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33725$1322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_7 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33725$1322_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33726$1323 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_6 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33726$1323_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33728$1325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_9 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33728$1325_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33729$1326 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_8 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33729$1326_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33731$1328 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_11 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33731$1328_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33732$1329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_10 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33732$1329_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33734$1331 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_13 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33734$1331_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33735$1332 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_0 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33735$1332_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33736$1333 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_12 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33736$1333_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33738$1335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_15 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33738$1335_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33739$1336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_14 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33739$1336_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33741$1338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_17 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33741$1338_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33742$1339 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_16 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33742$1339_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33744$1341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_19 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33744$1341_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33745$1342 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_18 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33745$1342_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33748$1345 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_21 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33748$1345_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33749$1346 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_20 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33749$1346_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33751$1348 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_23 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33751$1348_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33752$1349 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_22 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33752$1349_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33754$1351 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_25 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33754$1351_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33755$1352 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_24 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33755$1352_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33757$1354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_3 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33757$1354_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33758$1355 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_27 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33758$1355_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33759$1356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_26 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33759$1356_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33761$1358 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_29 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33761$1358_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33762$1359 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_28 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33762$1359_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33764$1361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_31 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33764$1361_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$issuer_ls180.v:33765$1362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_30 [1] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33765$1362_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$issuer_ls180.v:33767$1364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_2 [2] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:33767$1364_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33677$1274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'01 \cnt_2_0 [1:0] } - connect \Y $pos$issuer_ls180.v:33677$1274_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33680$1277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'01 \cnt_2_4 [1:0] } - connect \Y $pos$issuer_ls180.v:33680$1277_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33683$1280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'01 \cnt_2_8 [1:0] } - connect \Y $pos$issuer_ls180.v:33683$1280_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33686$1283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_2 [0] } - connect \Y $pos$issuer_ls180.v:33686$1283_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33687$1284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'01 \cnt_2_12 [1:0] } - connect \Y $pos$issuer_ls180.v:33687$1284_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33690$1287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'01 \cnt_2_16 [1:0] } - connect \Y $pos$issuer_ls180.v:33690$1287_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33693$1290 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'01 \cnt_2_20 [1:0] } - connect \Y $pos$issuer_ls180.v:33693$1290_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33696$1293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'01 \cnt_2_24 [1:0] } - connect \Y $pos$issuer_ls180.v:33696$1293_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33700$1297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'01 \cnt_2_28 [1:0] } - connect \Y $pos$issuer_ls180.v:33700$1297_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33703$1300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'01 \cnt_3_0 [2:0] } - connect \Y $pos$issuer_ls180.v:33703$1300_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33706$1303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'01 \cnt_3_4 [2:0] } - connect \Y $pos$issuer_ls180.v:33706$1303_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33710$1307 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'01 \cnt_3_8 [2:0] } - connect \Y $pos$issuer_ls180.v:33710$1307_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33713$1310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'01 \cnt_3_12 [2:0] } - connect \Y $pos$issuer_ls180.v:33713$1310_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33716$1313 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A { 2'01 \cnt_4_0 [3:0] } - connect \Y $pos$issuer_ls180.v:33716$1313_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33719$1316 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_4 [0] } - connect \Y $pos$issuer_ls180.v:33719$1316_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33720$1317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A { 2'01 \cnt_4_4 [3:0] } - connect \Y $pos$issuer_ls180.v:33720$1317_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33723$1320 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 7 - connect \A { 2'01 \cnt_5_0 [4:0] } - connect \Y $pos$issuer_ls180.v:33723$1320_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33727$1324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_6 [0] } - connect \Y $pos$issuer_ls180.v:33727$1324_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33730$1327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_8 [0] } - connect \Y $pos$issuer_ls180.v:33730$1327_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33733$1330 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_10 [0] } - connect \Y $pos$issuer_ls180.v:33733$1330_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33737$1334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_12 [0] } - connect \Y $pos$issuer_ls180.v:33737$1334_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33740$1337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_14 [0] } - connect \Y $pos$issuer_ls180.v:33740$1337_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33743$1340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_16 [0] } - connect \Y $pos$issuer_ls180.v:33743$1340_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33746$1343 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_0 [0] } - connect \Y $pos$issuer_ls180.v:33746$1343_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33747$1344 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_18 [0] } - connect \Y $pos$issuer_ls180.v:33747$1344_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33750$1347 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_20 [0] } - connect \Y $pos$issuer_ls180.v:33750$1347_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33753$1350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_22 [0] } - connect \Y $pos$issuer_ls180.v:33753$1350_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33756$1353 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_24 [0] } - connect \Y $pos$issuer_ls180.v:33756$1353_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33760$1357 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_26 [0] } - connect \Y $pos$issuer_ls180.v:33760$1357_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33763$1360 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_28 [0] } - connect \Y $pos$issuer_ls180.v:33763$1360_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$issuer_ls180.v:33766$1363 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_30 [0] } - connect \Y $pos$issuer_ls180.v:33766$1363_Y - end - attribute \src "issuer_ls180.v:33294.7-33294.20" - process $proc$issuer_ls180.v:33294$1428 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:33768.3-33782.6" - process $proc$issuer_ls180.v:33768$1365 - assign { } { } - assign $0\cnt_1_0[1:0] $1\cnt_1_0[1:0] - attribute \src "issuer_ls180.v:33769.5-33769.29" - switch \initial - attribute \src "issuer_ls180.v:33769.9-33769.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_0[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } - assign $1\cnt_1_0[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } - assign $1\cnt_1_0[1:0] 2'00 - end - sync always - update \cnt_1_0 $0\cnt_1_0[1:0] - end - attribute \src "issuer_ls180.v:33783.3-33797.6" - process $proc$issuer_ls180.v:33783$1366 - assign { } { } - assign $0\cnt_1_5[1:0] $1\cnt_1_5[1:0] - attribute \src "issuer_ls180.v:33784.5-33784.29" - switch \initial - attribute \src "issuer_ls180.v:33784.9-33784.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } - assign $1\cnt_1_5[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $1\cnt_1_5[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 assign { } { } - assign $1\cnt_1_5[1:0] 2'00 - end - sync always - update \cnt_1_5 $0\cnt_1_5[1:0] - end - attribute \src "issuer_ls180.v:33798.3-33812.6" - process $proc$issuer_ls180.v:33798$1367 - assign { } { } - assign $0\cnt_1_6[1:0] $1\cnt_1_6[1:0] - attribute \src "issuer_ls180.v:33799.5-33799.29" - switch \initial - attribute \src "issuer_ls180.v:33799.9-33799.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair12 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } - assign $1\cnt_1_6[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } - assign $1\cnt_1_6[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } - assign $1\cnt_1_6[1:0] 2'00 - end - sync always - update \cnt_1_6 $0\cnt_1_6[1:0] - end - attribute \src "issuer_ls180.v:33813.3-33827.6" - process $proc$issuer_ls180.v:33813$1368 - assign { } { } - assign $0\cnt_1_7[1:0] $1\cnt_1_7[1:0] - attribute \src "issuer_ls180.v:33814.5-33814.29" - switch \initial - attribute \src "issuer_ls180.v:33814.9-33814.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair14 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } - assign $1\cnt_1_7[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } - assign $1\cnt_1_7[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } - assign $1\cnt_1_7[1:0] 2'00 - end - sync always - update \cnt_1_7 $0\cnt_1_7[1:0] - end - attribute \src "issuer_ls180.v:33828.3-33842.6" - process $proc$issuer_ls180.v:33828$1369 - assign { } { } - assign $0\cnt_1_8[1:0] $1\cnt_1_8[1:0] - attribute \src "issuer_ls180.v:33829.5-33829.29" - switch \initial - attribute \src "issuer_ls180.v:33829.9-33829.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair16 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 assign { } { } - assign $1\cnt_1_8[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 assign { } { } - assign $1\cnt_1_8[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 assign { } { } - assign $1\cnt_1_8[1:0] 2'00 - end - sync always - update \cnt_1_8 $0\cnt_1_8[1:0] - end - attribute \src "issuer_ls180.v:33843.3-33857.6" - process $proc$issuer_ls180.v:33843$1370 - assign { } { } - assign $0\cnt_1_9[1:0] $1\cnt_1_9[1:0] - attribute \src "issuer_ls180.v:33844.5-33844.29" - switch \initial - attribute \src "issuer_ls180.v:33844.9-33844.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair18 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 assign { } { } - assign $1\cnt_1_9[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\cnt_1_9[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } - assign $1\cnt_1_9[1:0] 2'00 - end - sync always - update \cnt_1_9 $0\cnt_1_9[1:0] - end - attribute \src "issuer_ls180.v:33858.3-33872.6" - process $proc$issuer_ls180.v:33858$1371 - assign { } { } - assign $0\cnt_1_10[1:0] $1\cnt_1_10[1:0] - attribute \src "issuer_ls180.v:33859.5-33859.29" - switch \initial - attribute \src "issuer_ls180.v:33859.9-33859.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair20 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 assign { } { } - assign $1\cnt_1_10[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } - assign $1\cnt_1_10[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } - assign $1\cnt_1_10[1:0] 2'00 - end - sync always - update \cnt_1_10 $0\cnt_1_10[1:0] - end - attribute \src "issuer_ls180.v:33873.3-33887.6" - process $proc$issuer_ls180.v:33873$1372 - assign { } { } - assign $0\cnt_1_11[1:0] $1\cnt_1_11[1:0] - attribute \src "issuer_ls180.v:33874.5-33874.29" - switch \initial - attribute \src "issuer_ls180.v:33874.9-33874.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair22 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 assign { } { } - assign $1\cnt_1_11[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\cnt_1_11[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } - assign $1\cnt_1_11[1:0] 2'00 - end - sync always - update \cnt_1_11 $0\cnt_1_11[1:0] - end - attribute \src "issuer_ls180.v:33888.3-33902.6" - process $proc$issuer_ls180.v:33888$1373 - assign { } { } - assign $0\cnt_1_12[1:0] $1\cnt_1_12[1:0] - attribute \src "issuer_ls180.v:33889.5-33889.29" - switch \initial - attribute \src "issuer_ls180.v:33889.9-33889.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair24 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } - assign $1\cnt_1_12[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $1\cnt_1_12[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 assign { } { } - assign $1\cnt_1_12[1:0] 2'00 - end - sync always - update \cnt_1_12 $0\cnt_1_12[1:0] - end - attribute \src "issuer_ls180.v:33903.3-33917.6" - process $proc$issuer_ls180.v:33903$1374 - assign { } { } - assign $0\cnt_1_13[1:0] $1\cnt_1_13[1:0] - attribute \src "issuer_ls180.v:33904.5-33904.29" - switch \initial - attribute \src "issuer_ls180.v:33904.9-33904.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair26 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 assign { } { } - assign $1\cnt_1_13[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign $1\cnt_1_13[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 assign { } { } - assign $1\cnt_1_13[1:0] 2'00 - end - sync always - update \cnt_1_13 $0\cnt_1_13[1:0] - end - attribute \src "issuer_ls180.v:33918.3-33932.6" - process $proc$issuer_ls180.v:33918$1375 - assign { } { } - assign $0\cnt_1_14[1:0] $1\cnt_1_14[1:0] - attribute \src "issuer_ls180.v:33919.5-33919.29" - switch \initial - attribute \src "issuer_ls180.v:33919.9-33919.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair28 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 assign { } { } - assign $1\cnt_1_14[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 assign { } { } - assign $1\cnt_1_14[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 case - assign { } { } - assign $1\cnt_1_14[1:0] 2'00 + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 end sync always - update \cnt_1_14 $0\cnt_1_14[1:0] + update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0] end - attribute \src "issuer_ls180.v:33933.3-33947.6" - process $proc$issuer_ls180.v:33933$1376 + attribute \src "libresoc.v:23118.3-23220.6" + process $proc$libresoc.v:23118$455 + assign { } { } assign { } { } - assign $0\cnt_1_1[1:0] $1\cnt_1_1[1:0] - attribute \src "issuer_ls180.v:33934.5-33934.29" + assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:23119.5-23119.29" switch \initial - attribute \src "issuer_ls180.v:33934.9-33934.17" + attribute \src "libresoc.v:23119.9-23119.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair2 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\cnt_1_1[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } - assign $1\cnt_1_1[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } - assign $1\cnt_1_1[1:0] 2'00 - end - sync always - update \cnt_1_1 $0\cnt_1_1[1:0] - end - attribute \src "issuer_ls180.v:33948.3-33962.6" - process $proc$issuer_ls180.v:33948$1377 - assign { } { } - assign $0\cnt_1_15[1:0] $1\cnt_1_15[1:0] - attribute \src "issuer_ls180.v:33949.5-33949.29" - switch \initial - attribute \src "issuer_ls180.v:33949.9-33949.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair30 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } - assign $1\cnt_1_15[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $1\cnt_1_15[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 assign { } { } - assign $1\cnt_1_15[1:0] 2'00 - end - sync always - update \cnt_1_15 $0\cnt_1_15[1:0] - end - attribute \src "issuer_ls180.v:33963.3-33977.6" - process $proc$issuer_ls180.v:33963$1378 - assign { } { } - assign $0\cnt_1_16[1:0] $1\cnt_1_16[1:0] - attribute \src "issuer_ls180.v:33964.5-33964.29" - switch \initial - attribute \src "issuer_ls180.v:33964.9-33964.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair32 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } - assign $1\cnt_1_16[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } - assign $1\cnt_1_16[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } - assign $1\cnt_1_16[1:0] 2'00 - end - sync always - update \cnt_1_16 $0\cnt_1_16[1:0] - end - attribute \src "issuer_ls180.v:33978.3-33992.6" - process $proc$issuer_ls180.v:33978$1379 - assign { } { } - assign $0\cnt_1_17[1:0] $1\cnt_1_17[1:0] - attribute \src "issuer_ls180.v:33979.5-33979.29" - switch \initial - attribute \src "issuer_ls180.v:33979.9-33979.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair34 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } - assign $1\cnt_1_17[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } - assign $1\cnt_1_17[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } - assign $1\cnt_1_17[1:0] 2'00 - end - sync always - update \cnt_1_17 $0\cnt_1_17[1:0] - end - attribute \src "issuer_ls180.v:33993.3-34007.6" - process $proc$issuer_ls180.v:33993$1380 - assign { } { } - assign $0\cnt_1_18[1:0] $1\cnt_1_18[1:0] - attribute \src "issuer_ls180.v:33994.5-33994.29" - switch \initial - attribute \src "issuer_ls180.v:33994.9-33994.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair36 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 assign { } { } - assign $1\cnt_1_18[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 assign { } { } - assign $1\cnt_1_18[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 assign { } { } - assign $1\cnt_1_18[1:0] 2'00 - end - sync always - update \cnt_1_18 $0\cnt_1_18[1:0] - end - attribute \src "issuer_ls180.v:34008.3-34022.6" - process $proc$issuer_ls180.v:34008$1381 - assign { } { } - assign $0\cnt_1_19[1:0] $1\cnt_1_19[1:0] - attribute \src "issuer_ls180.v:34009.5-34009.29" - switch \initial - attribute \src "issuer_ls180.v:34009.9-34009.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair38 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 assign { } { } - assign $1\cnt_1_19[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\cnt_1_19[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } - assign $1\cnt_1_19[1:0] 2'00 - end - sync always - update \cnt_1_19 $0\cnt_1_19[1:0] - end - attribute \src "issuer_ls180.v:34023.3-34037.6" - process $proc$issuer_ls180.v:34023$1382 - assign { } { } - assign $0\cnt_1_20[1:0] $1\cnt_1_20[1:0] - attribute \src "issuer_ls180.v:34024.5-34024.29" - switch \initial - attribute \src "issuer_ls180.v:34024.9-34024.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair40 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 assign { } { } - assign $1\cnt_1_20[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } - assign $1\cnt_1_20[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } - assign $1\cnt_1_20[1:0] 2'00 - end - sync always - update \cnt_1_20 $0\cnt_1_20[1:0] - end - attribute \src "issuer_ls180.v:34038.3-34052.6" - process $proc$issuer_ls180.v:34038$1383 - assign { } { } - assign $0\cnt_1_21[1:0] $1\cnt_1_21[1:0] - attribute \src "issuer_ls180.v:34039.5-34039.29" - switch \initial - attribute \src "issuer_ls180.v:34039.9-34039.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair42 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 assign { } { } - assign $1\cnt_1_21[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\cnt_1_21[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } - assign $1\cnt_1_21[1:0] 2'00 - end - sync always - update \cnt_1_21 $0\cnt_1_21[1:0] - end - attribute \src "issuer_ls180.v:34053.3-34067.6" - process $proc$issuer_ls180.v:34053$1384 - assign { } { } - assign $0\cnt_1_22[1:0] $1\cnt_1_22[1:0] - attribute \src "issuer_ls180.v:34054.5-34054.29" - switch \initial - attribute \src "issuer_ls180.v:34054.9-34054.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair44 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } - assign $1\cnt_1_22[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $1\cnt_1_22[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 assign { } { } - assign $1\cnt_1_22[1:0] 2'00 - end - sync always - update \cnt_1_22 $0\cnt_1_22[1:0] - end - attribute \src "issuer_ls180.v:34068.3-34082.6" - process $proc$issuer_ls180.v:34068$1385 - assign { } { } - assign $0\cnt_1_23[1:0] $1\cnt_1_23[1:0] - attribute \src "issuer_ls180.v:34069.5-34069.29" - switch \initial - attribute \src "issuer_ls180.v:34069.9-34069.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair46 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 assign { } { } - assign $1\cnt_1_23[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign $1\cnt_1_23[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 assign { } { } - assign $1\cnt_1_23[1:0] 2'00 - end - sync always - update \cnt_1_23 $0\cnt_1_23[1:0] - end - attribute \src "issuer_ls180.v:34083.3-34097.6" - process $proc$issuer_ls180.v:34083$1386 - assign { } { } - assign $0\cnt_1_24[1:0] $1\cnt_1_24[1:0] - attribute \src "issuer_ls180.v:34084.5-34084.29" - switch \initial - attribute \src "issuer_ls180.v:34084.9-34084.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair48 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 assign { } { } - assign $1\cnt_1_24[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 assign { } { } - assign $1\cnt_1_24[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 case - assign { } { } - assign $1\cnt_1_24[1:0] 2'00 + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 end sync always - update \cnt_1_24 $0\cnt_1_24[1:0] + update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] end - attribute \src "issuer_ls180.v:34098.3-34112.6" - process $proc$issuer_ls180.v:34098$1387 + attribute \src "libresoc.v:23221.3-23323.6" + process $proc$libresoc.v:23221$456 assign { } { } - assign $0\cnt_1_2[1:0] $1\cnt_1_2[1:0] - attribute \src "issuer_ls180.v:34099.5-34099.29" + assign { } { } + assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:23222.5-23222.29" switch \initial - attribute \src "issuer_ls180.v:34099.9-34099.17" + attribute \src "libresoc.v:23222.9-23222.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair4 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\cnt_1_2[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } - assign $1\cnt_1_2[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } - assign $1\cnt_1_2[1:0] 2'00 - end - sync always - update \cnt_1_2 $0\cnt_1_2[1:0] - end - attribute \src "issuer_ls180.v:34113.3-34127.6" - process $proc$issuer_ls180.v:34113$1388 - assign { } { } - assign $0\cnt_1_25[1:0] $1\cnt_1_25[1:0] - attribute \src "issuer_ls180.v:34114.5-34114.29" - switch \initial - attribute \src "issuer_ls180.v:34114.9-34114.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair50 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } - assign $1\cnt_1_25[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $1\cnt_1_25[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 assign { } { } - assign $1\cnt_1_25[1:0] 2'00 - end - sync always - update \cnt_1_25 $0\cnt_1_25[1:0] - end - attribute \src "issuer_ls180.v:34128.3-34142.6" - process $proc$issuer_ls180.v:34128$1389 - assign { } { } - assign $0\cnt_1_26[1:0] $1\cnt_1_26[1:0] - attribute \src "issuer_ls180.v:34129.5-34129.29" - switch \initial - attribute \src "issuer_ls180.v:34129.9-34129.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair52 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } - assign $1\cnt_1_26[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } - assign $1\cnt_1_26[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } - assign $1\cnt_1_26[1:0] 2'00 - end - sync always - update \cnt_1_26 $0\cnt_1_26[1:0] - end - attribute \src "issuer_ls180.v:34143.3-34157.6" - process $proc$issuer_ls180.v:34143$1390 - assign { } { } - assign $0\cnt_1_27[1:0] $1\cnt_1_27[1:0] - attribute \src "issuer_ls180.v:34144.5-34144.29" - switch \initial - attribute \src "issuer_ls180.v:34144.9-34144.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair54 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } - assign $1\cnt_1_27[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } - assign $1\cnt_1_27[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } - assign $1\cnt_1_27[1:0] 2'00 - end - sync always - update \cnt_1_27 $0\cnt_1_27[1:0] - end - attribute \src "issuer_ls180.v:34158.3-34172.6" - process $proc$issuer_ls180.v:34158$1391 - assign { } { } - assign $0\cnt_1_28[1:0] $1\cnt_1_28[1:0] - attribute \src "issuer_ls180.v:34159.5-34159.29" - switch \initial - attribute \src "issuer_ls180.v:34159.9-34159.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair56 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 assign { } { } - assign $1\cnt_1_28[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 assign { } { } - assign $1\cnt_1_28[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 assign { } { } - assign $1\cnt_1_28[1:0] 2'00 - end - sync always - update \cnt_1_28 $0\cnt_1_28[1:0] - end - attribute \src "issuer_ls180.v:34173.3-34187.6" - process $proc$issuer_ls180.v:34173$1392 - assign { } { } - assign $0\cnt_1_29[1:0] $1\cnt_1_29[1:0] - attribute \src "issuer_ls180.v:34174.5-34174.29" - switch \initial - attribute \src "issuer_ls180.v:34174.9-34174.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair58 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 assign { } { } - assign $1\cnt_1_29[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\cnt_1_29[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } - assign $1\cnt_1_29[1:0] 2'00 - end - sync always - update \cnt_1_29 $0\cnt_1_29[1:0] - end - attribute \src "issuer_ls180.v:34188.3-34202.6" - process $proc$issuer_ls180.v:34188$1393 - assign { } { } - assign $0\cnt_1_30[1:0] $1\cnt_1_30[1:0] - attribute \src "issuer_ls180.v:34189.5-34189.29" - switch \initial - attribute \src "issuer_ls180.v:34189.9-34189.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair60 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 assign { } { } - assign $1\cnt_1_30[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } - assign $1\cnt_1_30[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } - assign $1\cnt_1_30[1:0] 2'00 - end - sync always - update \cnt_1_30 $0\cnt_1_30[1:0] - end - attribute \src "issuer_ls180.v:34203.3-34217.6" - process $proc$issuer_ls180.v:34203$1394 - assign { } { } - assign $0\cnt_1_31[1:0] $1\cnt_1_31[1:0] - attribute \src "issuer_ls180.v:34204.5-34204.29" - switch \initial - attribute \src "issuer_ls180.v:34204.9-34204.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair62 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 assign { } { } - assign $1\cnt_1_31[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\cnt_1_31[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } - assign $1\cnt_1_31[1:0] 2'00 - end - sync always - update \cnt_1_31 $0\cnt_1_31[1:0] - end - attribute \src "issuer_ls180.v:34218.3-34237.6" - process $proc$issuer_ls180.v:34218$1395 - assign { } { } - assign $0\cnt_2_0[2:0] $1\cnt_2_0[2:0] - attribute \src "issuer_ls180.v:34219.5-34219.29" - switch \initial - attribute \src "issuer_ls180.v:34219.9-34219.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } - assign $1\cnt_2_0[2:0] $2\cnt_2_0[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_0[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_0[2:0] \$5 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $1\cnt_2_0[2:0] { 1'0 \cnt_1_1 } - end - sync always - update \cnt_2_0 $0\cnt_2_0[2:0] - end - attribute \src "issuer_ls180.v:34238.3-34257.6" - process $proc$issuer_ls180.v:34238$1396 - assign { } { } - assign $0\cnt_2_2[2:0] $1\cnt_2_2[2:0] - attribute \src "issuer_ls180.v:34239.5-34239.29" - switch \initial - attribute \src "issuer_ls180.v:34239.9-34239.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 assign { } { } - assign $1\cnt_2_2[2:0] $2\cnt_2_2[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_2[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_2[2:0] \$11 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 assign { } { } - assign $1\cnt_2_2[2:0] { 1'0 \cnt_1_3 } - end - sync always - update \cnt_2_2 $0\cnt_2_2[2:0] - end - attribute \src "issuer_ls180.v:34258.3-34277.6" - process $proc$issuer_ls180.v:34258$1397 - assign { } { } - assign $0\cnt_2_4[2:0] $1\cnt_2_4[2:0] - attribute \src "issuer_ls180.v:34259.5-34259.29" - switch \initial - attribute \src "issuer_ls180.v:34259.9-34259.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$13 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign $1\cnt_2_4[2:0] $2\cnt_2_4[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$15 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_4[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_4[2:0] \$17 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 assign { } { } - assign $1\cnt_2_4[2:0] { 1'0 \cnt_1_5 } - end - sync always - update \cnt_2_4 $0\cnt_2_4[2:0] - end - attribute \src "issuer_ls180.v:34278.3-34297.6" - process $proc$issuer_ls180.v:34278$1398 - assign { } { } - assign $0\cnt_2_6[2:0] $1\cnt_2_6[2:0] - attribute \src "issuer_ls180.v:34279.5-34279.29" - switch \initial - attribute \src "issuer_ls180.v:34279.9-34279.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$19 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 assign { } { } - assign $1\cnt_2_6[2:0] $2\cnt_2_6[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$21 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_6[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_6[2:0] \$23 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 assign { } { } - assign $1\cnt_2_6[2:0] { 1'0 \cnt_1_7 } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 end sync always - update \cnt_2_6 $0\cnt_2_6[2:0] + update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0] end - attribute \src "issuer_ls180.v:34298.3-34317.6" - process $proc$issuer_ls180.v:34298$1399 + attribute \src "libresoc.v:23324.3-23426.6" + process $proc$libresoc.v:23324$457 assign { } { } - assign $0\cnt_2_8[2:0] $1\cnt_2_8[2:0] - attribute \src "issuer_ls180.v:34299.5-34299.29" + assign { } { } + assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:23325.5-23325.29" switch \initial - attribute \src "issuer_ls180.v:34299.9-34299.17" + attribute \src "libresoc.v:23325.9-23325.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$25 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\cnt_2_8[2:0] $2\cnt_2_8[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$27 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_8[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_8[2:0] \$29 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } - assign $1\cnt_2_8[2:0] { 1'0 \cnt_1_9 } - end - sync always - update \cnt_2_8 $0\cnt_2_8[2:0] - end - attribute \src "issuer_ls180.v:34318.3-34337.6" - process $proc$issuer_ls180.v:34318$1400 - assign { } { } - assign $0\cnt_2_10[2:0] $1\cnt_2_10[2:0] - attribute \src "issuer_ls180.v:34319.5-34319.29" - switch \initial - attribute \src "issuer_ls180.v:34319.9-34319.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$31 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } - assign $1\cnt_2_10[2:0] $2\cnt_2_10[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$33 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_10[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_10[2:0] \$35 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } - assign $1\cnt_2_10[2:0] { 1'0 \cnt_1_11 } - end - sync always - update \cnt_2_10 $0\cnt_2_10[2:0] - end - attribute \src "issuer_ls180.v:34338.3-34352.6" - process $proc$issuer_ls180.v:34338$1401 - assign { } { } - assign $0\cnt_1_3[1:0] $1\cnt_1_3[1:0] - attribute \src "issuer_ls180.v:34339.5-34339.29" - switch \initial - attribute \src "issuer_ls180.v:34339.9-34339.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair6 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $1\cnt_1_3[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 assign { } { } - assign $1\cnt_1_3[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } - assign $1\cnt_1_3[1:0] 2'00 - end - sync always - update \cnt_1_3 $0\cnt_1_3[1:0] - end - attribute \src "issuer_ls180.v:34353.3-34372.6" - process $proc$issuer_ls180.v:34353$1402 - assign { } { } - assign $0\cnt_2_12[2:0] $1\cnt_2_12[2:0] - attribute \src "issuer_ls180.v:34354.5-34354.29" - switch \initial - attribute \src "issuer_ls180.v:34354.9-34354.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$37 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } - assign $1\cnt_2_12[2:0] $2\cnt_2_12[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$39 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_12[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_12[2:0] \$41 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } - assign $1\cnt_2_12[2:0] { 1'0 \cnt_1_13 } - end - sync always - update \cnt_2_12 $0\cnt_2_12[2:0] - end - attribute \src "issuer_ls180.v:34373.3-34392.6" - process $proc$issuer_ls180.v:34373$1403 - assign { } { } - assign $0\cnt_2_14[2:0] $1\cnt_2_14[2:0] - attribute \src "issuer_ls180.v:34374.5-34374.29" - switch \initial - attribute \src "issuer_ls180.v:34374.9-34374.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$43 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } - assign $1\cnt_2_14[2:0] $2\cnt_2_14[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$45 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_14[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_14[2:0] \$47 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } - assign $1\cnt_2_14[2:0] { 1'0 \cnt_1_15 } - end - sync always - update \cnt_2_14 $0\cnt_2_14[2:0] - end - attribute \src "issuer_ls180.v:34393.3-34412.6" - process $proc$issuer_ls180.v:34393$1404 - assign { } { } - assign $0\cnt_2_16[2:0] $1\cnt_2_16[2:0] - attribute \src "issuer_ls180.v:34394.5-34394.29" - switch \initial - attribute \src "issuer_ls180.v:34394.9-34394.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$49 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } - assign $1\cnt_2_16[2:0] $2\cnt_2_16[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$51 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_16[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_16[2:0] \$53 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 assign { } { } - assign $1\cnt_2_16[2:0] { 1'0 \cnt_1_17 } - end - sync always - update \cnt_2_16 $0\cnt_2_16[2:0] - end - attribute \src "issuer_ls180.v:34413.3-34432.6" - process $proc$issuer_ls180.v:34413$1405 - assign { } { } - assign $0\cnt_2_18[2:0] $1\cnt_2_18[2:0] - attribute \src "issuer_ls180.v:34414.5-34414.29" - switch \initial - attribute \src "issuer_ls180.v:34414.9-34414.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$55 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 assign { } { } - assign $1\cnt_2_18[2:0] $2\cnt_2_18[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$57 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_18[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_18[2:0] \$59 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 assign { } { } - assign $1\cnt_2_18[2:0] { 1'0 \cnt_1_19 } - end - sync always - update \cnt_2_18 $0\cnt_2_18[2:0] - end - attribute \src "issuer_ls180.v:34433.3-34452.6" - process $proc$issuer_ls180.v:34433$1406 - assign { } { } - assign $0\cnt_2_20[2:0] $1\cnt_2_20[2:0] - attribute \src "issuer_ls180.v:34434.5-34434.29" - switch \initial - attribute \src "issuer_ls180.v:34434.9-34434.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$61 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 assign { } { } - assign $1\cnt_2_20[2:0] $2\cnt_2_20[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$63 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_20[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_20[2:0] \$65 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\cnt_2_20[2:0] { 1'0 \cnt_1_21 } - end - sync always - update \cnt_2_20 $0\cnt_2_20[2:0] - end - attribute \src "issuer_ls180.v:34453.3-34472.6" - process $proc$issuer_ls180.v:34453$1407 - assign { } { } - assign $0\cnt_2_22[2:0] $1\cnt_2_22[2:0] - attribute \src "issuer_ls180.v:34454.5-34454.29" - switch \initial - attribute \src "issuer_ls180.v:34454.9-34454.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$67 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } - assign $1\cnt_2_22[2:0] $2\cnt_2_22[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$69 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_22[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_22[2:0] \$71 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 assign { } { } - assign $1\cnt_2_22[2:0] { 1'0 \cnt_1_23 } - end - sync always - update \cnt_2_22 $0\cnt_2_22[2:0] - end - attribute \src "issuer_ls180.v:34473.3-34492.6" - process $proc$issuer_ls180.v:34473$1408 - assign { } { } - assign $0\cnt_2_24[2:0] $1\cnt_2_24[2:0] - attribute \src "issuer_ls180.v:34474.5-34474.29" - switch \initial - attribute \src "issuer_ls180.v:34474.9-34474.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$73 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } - assign $1\cnt_2_24[2:0] $2\cnt_2_24[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$75 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_24[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_24[2:0] \$77 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } - assign $1\cnt_2_24[2:0] { 1'0 \cnt_1_25 } - end - sync always - update \cnt_2_24 $0\cnt_2_24[2:0] - end - attribute \src "issuer_ls180.v:34493.3-34512.6" - process $proc$issuer_ls180.v:34493$1409 - assign { } { } - assign $0\cnt_2_26[2:0] $1\cnt_2_26[2:0] - attribute \src "issuer_ls180.v:34494.5-34494.29" - switch \initial - attribute \src "issuer_ls180.v:34494.9-34494.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$79 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 assign { } { } - assign $1\cnt_2_26[2:0] $2\cnt_2_26[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$81 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_26[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_26[2:0] \$83 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\cnt_2_26[2:0] { 1'0 \cnt_1_27 } - end - sync always - update \cnt_2_26 $0\cnt_2_26[2:0] - end - attribute \src "issuer_ls180.v:34513.3-34532.6" - process $proc$issuer_ls180.v:34513$1410 - assign { } { } - assign $0\cnt_2_28[2:0] $1\cnt_2_28[2:0] - attribute \src "issuer_ls180.v:34514.5-34514.29" - switch \initial - attribute \src "issuer_ls180.v:34514.9-34514.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$85 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } - assign $1\cnt_2_28[2:0] $2\cnt_2_28[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$87 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_28[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_28[2:0] \$89 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } - assign $1\cnt_2_28[2:0] { 1'0 \cnt_1_29 } - end - sync always - update \cnt_2_28 $0\cnt_2_28[2:0] - end - attribute \src "issuer_ls180.v:34533.3-34552.6" - process $proc$issuer_ls180.v:34533$1411 - assign { } { } - assign $0\cnt_2_30[2:0] $1\cnt_2_30[2:0] - attribute \src "issuer_ls180.v:34534.5-34534.29" - switch \initial - attribute \src "issuer_ls180.v:34534.9-34534.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$91 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $1\cnt_2_30[2:0] $2\cnt_2_30[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$93 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_30[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_30[2:0] \$95 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 assign { } { } - assign $1\cnt_2_30[2:0] { 1'0 \cnt_1_31 } - end - sync always - update \cnt_2_30 $0\cnt_2_30[2:0] - end - attribute \src "issuer_ls180.v:34553.3-34572.6" - process $proc$issuer_ls180.v:34553$1412 - assign { } { } - assign $0\cnt_3_0[3:0] $1\cnt_3_0[3:0] - attribute \src "issuer_ls180.v:34554.5-34554.29" - switch \initial - attribute \src "issuer_ls180.v:34554.9-34554.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$97 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 assign { } { } - assign $1\cnt_3_0[3:0] $2\cnt_3_0[3:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$99 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_3_0[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_3_0[3:0] \$101 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign $1\cnt_3_0[3:0] { 1'0 \cnt_2_2 } - end - sync always - update \cnt_3_0 $0\cnt_3_0[3:0] - end - attribute \src "issuer_ls180.v:34573.3-34592.6" - process $proc$issuer_ls180.v:34573$1413 - assign { } { } - assign $0\cnt_3_2[3:0] $1\cnt_3_2[3:0] - attribute \src "issuer_ls180.v:34574.5-34574.29" - switch \initial - attribute \src "issuer_ls180.v:34574.9-34574.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$103 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 assign { } { } - assign $1\cnt_3_2[3:0] $2\cnt_3_2[3:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$105 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_3_2[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_3_2[3:0] \$107 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 assign { } { } - assign $1\cnt_3_2[3:0] { 1'0 \cnt_2_6 } - end - sync always - update \cnt_3_2 $0\cnt_3_2[3:0] - end - attribute \src "issuer_ls180.v:34593.3-34612.6" - process $proc$issuer_ls180.v:34593$1414 - assign { } { } - assign $0\cnt_3_4[3:0] $1\cnt_3_4[3:0] - attribute \src "issuer_ls180.v:34594.5-34594.29" - switch \initial - attribute \src "issuer_ls180.v:34594.9-34594.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$109 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 assign { } { } - assign $1\cnt_3_4[3:0] $2\cnt_3_4[3:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_3_4[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_3_4[3:0] \$113 - end - attribute \src "issuer_ls180.v:0.0-0.0" + assign $1\dec31_dec_sub15_lk[0:0] 1'0 case - assign { } { } - assign $1\cnt_3_4[3:0] { 1'0 \cnt_2_10 } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 end sync always - update \cnt_3_4 $0\cnt_3_4[3:0] + update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0] end - attribute \src "issuer_ls180.v:34613.3-34632.6" - process $proc$issuer_ls180.v:34613$1415 + attribute \src "libresoc.v:23427.3-23529.6" + process $proc$libresoc.v:23427$458 + assign { } { } assign { } { } - assign $0\cnt_3_6[3:0] $1\cnt_3_6[3:0] - attribute \src "issuer_ls180.v:34614.5-34614.29" + assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:23428.5-23428.29" switch \initial - attribute \src "issuer_ls180.v:34614.9-34614.17" + attribute \src "libresoc.v:23428.9-23428.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$115 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\cnt_3_6[3:0] $2\cnt_3_6[3:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$117 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_3_6[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_3_6[3:0] \$119 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } - assign $1\cnt_3_6[3:0] { 1'0 \cnt_2_14 } - end - sync always - update \cnt_3_6 $0\cnt_3_6[3:0] - end - attribute \src "issuer_ls180.v:34633.3-34652.6" - process $proc$issuer_ls180.v:34633$1416 - assign { } { } - assign $0\cnt_3_8[3:0] $1\cnt_3_8[3:0] - attribute \src "issuer_ls180.v:34634.5-34634.29" - switch \initial - attribute \src "issuer_ls180.v:34634.9-34634.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$121 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } - assign $1\cnt_3_8[3:0] $2\cnt_3_8[3:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$123 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_3_8[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_3_8[3:0] \$125 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } - assign $1\cnt_3_8[3:0] { 1'0 \cnt_2_18 } - end - sync always - update \cnt_3_8 $0\cnt_3_8[3:0] - end - attribute \src "issuer_ls180.v:34653.3-34672.6" - process $proc$issuer_ls180.v:34653$1417 - assign { } { } - assign $0\cnt_3_10[3:0] $1\cnt_3_10[3:0] - attribute \src "issuer_ls180.v:34654.5-34654.29" - switch \initial - attribute \src "issuer_ls180.v:34654.9-34654.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$127 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $1\cnt_3_10[3:0] $2\cnt_3_10[3:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$129 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_3_10[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_3_10[3:0] \$131 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 assign { } { } - assign $1\cnt_3_10[3:0] { 1'0 \cnt_2_22 } - end - sync always - update \cnt_3_10 $0\cnt_3_10[3:0] - end - attribute \src "issuer_ls180.v:34673.3-34692.6" - process $proc$issuer_ls180.v:34673$1418 - assign { } { } - assign $0\cnt_3_12[3:0] $1\cnt_3_12[3:0] - attribute \src "issuer_ls180.v:34674.5-34674.29" - switch \initial - attribute \src "issuer_ls180.v:34674.9-34674.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$133 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } - assign $1\cnt_3_12[3:0] $2\cnt_3_12[3:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$135 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_3_12[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_3_12[3:0] \$137 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } - assign $1\cnt_3_12[3:0] { 1'0 \cnt_2_26 } - end - sync always - update \cnt_3_12 $0\cnt_3_12[3:0] - end - attribute \src "issuer_ls180.v:34693.3-34712.6" - process $proc$issuer_ls180.v:34693$1419 - assign { } { } - assign $0\cnt_3_14[3:0] $1\cnt_3_14[3:0] - attribute \src "issuer_ls180.v:34694.5-34694.29" - switch \initial - attribute \src "issuer_ls180.v:34694.9-34694.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$139 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } - assign $1\cnt_3_14[3:0] $2\cnt_3_14[3:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$141 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_3_14[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_3_14[3:0] \$143 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } - assign $1\cnt_3_14[3:0] { 1'0 \cnt_2_30 } - end - sync always - update \cnt_3_14 $0\cnt_3_14[3:0] - end - attribute \src "issuer_ls180.v:34713.3-34732.6" - process $proc$issuer_ls180.v:34713$1420 - assign { } { } - assign $0\cnt_4_0[4:0] $1\cnt_4_0[4:0] - attribute \src "issuer_ls180.v:34714.5-34714.29" - switch \initial - attribute \src "issuer_ls180.v:34714.9-34714.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$145 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } - assign $1\cnt_4_0[4:0] $2\cnt_4_0[4:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$147 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_4_0[4:0] 5'10000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_4_0[4:0] \$149 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } - assign $1\cnt_4_0[4:0] { 1'0 \cnt_3_2 } - end - sync always - update \cnt_4_0 $0\cnt_4_0[4:0] - end - attribute \src "issuer_ls180.v:34733.3-34752.6" - process $proc$issuer_ls180.v:34733$1421 - assign { } { } - assign $0\cnt_4_2[4:0] $1\cnt_4_2[4:0] - attribute \src "issuer_ls180.v:34734.5-34734.29" - switch \initial - attribute \src "issuer_ls180.v:34734.9-34734.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$151 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 assign { } { } - assign $1\cnt_4_2[4:0] $2\cnt_4_2[4:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$153 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_4_2[4:0] 5'10000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_4_2[4:0] \$155 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 assign { } { } - assign $1\cnt_4_2[4:0] { 1'0 \cnt_3_6 } - end - sync always - update \cnt_4_2 $0\cnt_4_2[4:0] - end - attribute \src "issuer_ls180.v:34753.3-34767.6" - process $proc$issuer_ls180.v:34753$1422 - assign { } { } - assign $0\cnt_1_4[1:0] $1\cnt_1_4[1:0] - attribute \src "issuer_ls180.v:34754.5-34754.29" - switch \initial - attribute \src "issuer_ls180.v:34754.9-34754.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair8 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 assign { } { } - assign $1\cnt_1_4[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 assign { } { } - assign $1\cnt_1_4[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\cnt_1_4[1:0] 2'00 - end - sync always - update \cnt_1_4 $0\cnt_1_4[1:0] - end - attribute \src "issuer_ls180.v:34768.3-34787.6" - process $proc$issuer_ls180.v:34768$1423 - assign { } { } - assign $0\cnt_4_4[4:0] $1\cnt_4_4[4:0] - attribute \src "issuer_ls180.v:34769.5-34769.29" - switch \initial - attribute \src "issuer_ls180.v:34769.9-34769.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$157 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } - assign $1\cnt_4_4[4:0] $2\cnt_4_4[4:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$159 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_4_4[4:0] 5'10000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_4_4[4:0] \$161 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 assign { } { } - assign $1\cnt_4_4[4:0] { 1'0 \cnt_3_10 } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'0 end sync always - update \cnt_4_4 $0\cnt_4_4[4:0] + update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0] end - attribute \src "issuer_ls180.v:34788.3-34807.6" - process $proc$issuer_ls180.v:34788$1424 + attribute \src "libresoc.v:23530.3-23632.6" + process $proc$libresoc.v:23530$459 assign { } { } - assign $0\cnt_4_6[4:0] $1\cnt_4_6[4:0] - attribute \src "issuer_ls180.v:34789.5-34789.29" + assign { } { } + assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:23531.5-23531.29" switch \initial - attribute \src "issuer_ls180.v:34789.9-34789.17" + attribute \src "libresoc.v:23531.9-23531.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$163 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\cnt_4_6[4:0] $2\cnt_4_6[4:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$165 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_4_6[4:0] 5'10000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_4_6[4:0] \$167 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $1\cnt_4_6[4:0] { 1'0 \cnt_3_14 } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + case + assign $1\dec31_dec_sub15_form[4:0] 5'00000 end sync always - update \cnt_4_6 $0\cnt_4_6[4:0] + update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] end - attribute \src "issuer_ls180.v:34808.3-34827.6" - process $proc$issuer_ls180.v:34808$1425 + attribute \src "libresoc.v:23633.3-23735.6" + process $proc$libresoc.v:23633$460 assign { } { } - assign $0\cnt_5_0[5:0] $1\cnt_5_0[5:0] - attribute \src "issuer_ls180.v:34809.5-34809.29" + assign { } { } + assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:23634.5-23634.29" switch \initial - attribute \src "issuer_ls180.v:34809.9-34809.17" + attribute \src "libresoc.v:23634.9-23634.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$169 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\cnt_5_0[5:0] $2\cnt_5_0[5:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$171 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_5_0[5:0] 6'100000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_5_0[5:0] \$173 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } - assign $1\cnt_5_0[5:0] { 1'0 \cnt_4_2 } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'000 end sync always - update \cnt_5_0 $0\cnt_5_0[5:0] + update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0] end - attribute \src "issuer_ls180.v:34828.3-34847.6" - process $proc$issuer_ls180.v:34828$1426 + attribute \src "libresoc.v:23736.3-23838.6" + process $proc$libresoc.v:23736$461 + assign { } { } assign { } { } - assign $0\cnt_5_2[5:0] $1\cnt_5_2[5:0] - attribute \src "issuer_ls180.v:34829.5-34829.29" + assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:23737.5-23737.29" switch \initial - attribute \src "issuer_ls180.v:34829.9-34829.17" + attribute \src "libresoc.v:23737.9-23737.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$175 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\cnt_5_2[5:0] $2\cnt_5_2[5:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$177 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_5_2[5:0] 6'100000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_5_2[5:0] \$179 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 assign { } { } - assign $1\cnt_5_2[5:0] { 1'0 \cnt_4_6 } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0000 end sync always - update \cnt_5_2 $0\cnt_5_2[5:0] + update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0] end - attribute \src "issuer_ls180.v:34848.3-34867.6" - process $proc$issuer_ls180.v:34848$1427 + attribute \src "libresoc.v:23839.3-23941.6" + process $proc$libresoc.v:23839$462 + assign { } { } assign { } { } - assign $0\cnt_6_0[6:0] $1\cnt_6_0[6:0] - attribute \src "issuer_ls180.v:34849.5-34849.29" + assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:23840.5-23840.29" switch \initial - attribute \src "issuer_ls180.v:34849.9-34849.17" + attribute \src "libresoc.v:23840.9-23840.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$181 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\cnt_6_0[6:0] $2\cnt_6_0[6:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$183 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_6_0[6:0] 7'1000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_6_0[6:0] \$185 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_6_0[6:0] { 1'0 \cnt_5_2 } - end - sync always - update \cnt_6_0 $0\cnt_6_0[6:0] - end - connect \$9 $eq$issuer_ls180.v:33675$1272_Y - connect \$99 $eq$issuer_ls180.v:33676$1273_Y - connect \$101 $pos$issuer_ls180.v:33677$1274_Y - connect \$103 $eq$issuer_ls180.v:33678$1275_Y - connect \$105 $eq$issuer_ls180.v:33679$1276_Y - connect \$107 $pos$issuer_ls180.v:33680$1277_Y - connect \$109 $eq$issuer_ls180.v:33681$1278_Y - connect \$111 $eq$issuer_ls180.v:33682$1279_Y - connect \$113 $pos$issuer_ls180.v:33683$1280_Y - connect \$115 $eq$issuer_ls180.v:33684$1281_Y - connect \$117 $eq$issuer_ls180.v:33685$1282_Y - connect \$11 $pos$issuer_ls180.v:33686$1283_Y - connect \$119 $pos$issuer_ls180.v:33687$1284_Y - connect \$121 $eq$issuer_ls180.v:33688$1285_Y - connect \$123 $eq$issuer_ls180.v:33689$1286_Y - connect \$125 $pos$issuer_ls180.v:33690$1287_Y - connect \$127 $eq$issuer_ls180.v:33691$1288_Y - connect \$129 $eq$issuer_ls180.v:33692$1289_Y - connect \$131 $pos$issuer_ls180.v:33693$1290_Y - connect \$133 $eq$issuer_ls180.v:33694$1291_Y - connect \$135 $eq$issuer_ls180.v:33695$1292_Y - connect \$137 $pos$issuer_ls180.v:33696$1293_Y - connect \$13 $eq$issuer_ls180.v:33697$1294_Y - connect \$139 $eq$issuer_ls180.v:33698$1295_Y - connect \$141 $eq$issuer_ls180.v:33699$1296_Y - connect \$143 $pos$issuer_ls180.v:33700$1297_Y - connect \$145 $eq$issuer_ls180.v:33701$1298_Y - connect \$147 $eq$issuer_ls180.v:33702$1299_Y - connect \$149 $pos$issuer_ls180.v:33703$1300_Y - connect \$151 $eq$issuer_ls180.v:33704$1301_Y - connect \$153 $eq$issuer_ls180.v:33705$1302_Y - connect \$155 $pos$issuer_ls180.v:33706$1303_Y - connect \$157 $eq$issuer_ls180.v:33707$1304_Y - connect \$15 $eq$issuer_ls180.v:33708$1305_Y - connect \$159 $eq$issuer_ls180.v:33709$1306_Y - connect \$161 $pos$issuer_ls180.v:33710$1307_Y - connect \$163 $eq$issuer_ls180.v:33711$1308_Y - connect \$165 $eq$issuer_ls180.v:33712$1309_Y - connect \$167 $pos$issuer_ls180.v:33713$1310_Y - connect \$169 $eq$issuer_ls180.v:33714$1311_Y - connect \$171 $eq$issuer_ls180.v:33715$1312_Y - connect \$173 $pos$issuer_ls180.v:33716$1313_Y - connect \$175 $eq$issuer_ls180.v:33717$1314_Y - connect \$177 $eq$issuer_ls180.v:33718$1315_Y - connect \$17 $pos$issuer_ls180.v:33719$1316_Y - connect \$179 $pos$issuer_ls180.v:33720$1317_Y - connect \$181 $eq$issuer_ls180.v:33721$1318_Y - connect \$183 $eq$issuer_ls180.v:33722$1319_Y - connect \$185 $pos$issuer_ls180.v:33723$1320_Y - connect \$1 $eq$issuer_ls180.v:33724$1321_Y - connect \$19 $eq$issuer_ls180.v:33725$1322_Y - connect \$21 $eq$issuer_ls180.v:33726$1323_Y - connect \$23 $pos$issuer_ls180.v:33727$1324_Y - connect \$25 $eq$issuer_ls180.v:33728$1325_Y - connect \$27 $eq$issuer_ls180.v:33729$1326_Y - connect \$29 $pos$issuer_ls180.v:33730$1327_Y - connect \$31 $eq$issuer_ls180.v:33731$1328_Y - connect \$33 $eq$issuer_ls180.v:33732$1329_Y - connect \$35 $pos$issuer_ls180.v:33733$1330_Y - connect \$37 $eq$issuer_ls180.v:33734$1331_Y - connect \$3 $eq$issuer_ls180.v:33735$1332_Y - connect \$39 $eq$issuer_ls180.v:33736$1333_Y - connect \$41 $pos$issuer_ls180.v:33737$1334_Y - connect \$43 $eq$issuer_ls180.v:33738$1335_Y - connect \$45 $eq$issuer_ls180.v:33739$1336_Y - connect \$47 $pos$issuer_ls180.v:33740$1337_Y - connect \$49 $eq$issuer_ls180.v:33741$1338_Y - connect \$51 $eq$issuer_ls180.v:33742$1339_Y - connect \$53 $pos$issuer_ls180.v:33743$1340_Y - connect \$55 $eq$issuer_ls180.v:33744$1341_Y - connect \$57 $eq$issuer_ls180.v:33745$1342_Y - connect \$5 $pos$issuer_ls180.v:33746$1343_Y - connect \$59 $pos$issuer_ls180.v:33747$1344_Y - connect \$61 $eq$issuer_ls180.v:33748$1345_Y - connect \$63 $eq$issuer_ls180.v:33749$1346_Y - connect \$65 $pos$issuer_ls180.v:33750$1347_Y - connect \$67 $eq$issuer_ls180.v:33751$1348_Y - connect \$69 $eq$issuer_ls180.v:33752$1349_Y - connect \$71 $pos$issuer_ls180.v:33753$1350_Y - connect \$73 $eq$issuer_ls180.v:33754$1351_Y - connect \$75 $eq$issuer_ls180.v:33755$1352_Y - connect \$77 $pos$issuer_ls180.v:33756$1353_Y - connect \$7 $eq$issuer_ls180.v:33757$1354_Y - connect \$79 $eq$issuer_ls180.v:33758$1355_Y - connect \$81 $eq$issuer_ls180.v:33759$1356_Y - connect \$83 $pos$issuer_ls180.v:33760$1357_Y - connect \$85 $eq$issuer_ls180.v:33761$1358_Y - connect \$87 $eq$issuer_ls180.v:33762$1359_Y - connect \$89 $pos$issuer_ls180.v:33763$1360_Y - connect \$91 $eq$issuer_ls180.v:33764$1361_Y - connect \$93 $eq$issuer_ls180.v:33765$1362_Y - connect \$95 $pos$issuer_ls180.v:33766$1363_Y - connect \$97 $eq$issuer_ls180.v:33767$1364_Y - connect \lz \cnt_6_0 - connect \pair62 \sig_in [63:62] - connect \pair60 \sig_in [61:60] - connect \pair58 \sig_in [59:58] - connect \pair56 \sig_in [57:56] - connect \pair54 \sig_in [55:54] - connect \pair52 \sig_in [53:52] - connect \pair50 \sig_in [51:50] - connect \pair48 \sig_in [49:48] - connect \pair46 \sig_in [47:46] - connect \pair44 \sig_in [45:44] - connect \pair42 \sig_in [43:42] - connect \pair40 \sig_in [41:40] - connect \pair38 \sig_in [39:38] - connect \pair36 \sig_in [37:36] - connect \pair34 \sig_in [35:34] - connect \pair32 \sig_in [33:32] - connect \pair30 \sig_in [31:30] - connect \pair28 \sig_in [29:28] - connect \pair26 \sig_in [27:26] - connect \pair24 \sig_in [25:24] - connect \pair22 \sig_in [23:22] - connect \pair20 \sig_in [21:20] - connect \pair18 \sig_in [19:18] - connect \pair16 \sig_in [17:16] - connect \pair14 \sig_in [15:14] - connect \pair12 \sig_in [13:12] - connect \pair10 \sig_in [11:10] - connect \pair8 \sig_in [9:8] - connect \pair6 \sig_in [7:6] - connect \pair4 \sig_in [5:4] - connect \pair2 \sig_in [3:2] - connect \pair0 \sig_in [1:0] -end -attribute \src "issuer_ls180.v:34905.1-47599.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core" -attribute \generator "nMigen" -module \core - attribute \src "issuer_ls180.v:44577.3-44597.6" - wire $0\core_terminate_o$next[0:0]$2512 - attribute \src "issuer_ls180.v:41536.3-41537.49" - wire $0\core_terminate_o[0:0] - attribute \src "issuer_ls180.v:44448.3-44538.6" - wire $0\corebusy_o[0:0] - attribute \src "issuer_ls180.v:44393.3-44419.6" - wire width 2 $0\counter$next[1:0]$2486 - attribute \src "issuer_ls180.v:41538.3-41539.31" - wire width 2 $0\counter[1:0] - attribute \src "issuer_ls180.v:44878.3-44886.6" - wire $0\dp_CR_cr_a_branch0_1$next[0:0]$2568 - attribute \src "issuer_ls180.v:41472.3-41473.57" - wire $0\dp_CR_cr_a_branch0_1[0:0] - attribute \src "issuer_ls180.v:44859.3-44867.6" - wire $0\dp_CR_cr_a_cr0_0$next[0:0]$2562 - attribute \src "issuer_ls180.v:41474.3-41475.49" - wire $0\dp_CR_cr_a_cr0_0[0:0] - attribute \src "issuer_ls180.v:44897.3-44905.6" - wire $0\dp_CR_cr_b_cr0_0$next[0:0]$2574 - attribute \src "issuer_ls180.v:41470.3-41471.49" - wire $0\dp_CR_cr_b_cr0_0[0:0] - attribute \src "issuer_ls180.v:44946.3-44954.6" - wire $0\dp_CR_cr_c_cr0_0$next[0:0]$2581 - attribute \src "issuer_ls180.v:41468.3-41469.49" - wire $0\dp_CR_cr_c_cr0_0[0:0] - attribute \src "issuer_ls180.v:44810.3-44818.6" - wire $0\dp_CR_full_cr_cr0_0$next[0:0]$2555 - attribute \src "issuer_ls180.v:41476.3-41477.55" - wire $0\dp_CR_full_cr_cr0_0[0:0] - attribute \src "issuer_ls180.v:44965.3-44973.6" - wire $0\dp_FAST_fast1_branch0_0$next[0:0]$2587 - attribute \src "issuer_ls180.v:41466.3-41467.63" - wire $0\dp_FAST_fast1_branch0_0[0:0] - attribute \src "issuer_ls180.v:45032.3-45040.6" - wire $0\dp_FAST_fast1_spr0_2$next[0:0]$2600 - attribute \src "issuer_ls180.v:41462.3-41463.57" - wire $0\dp_FAST_fast1_spr0_2[0:0] - attribute \src "issuer_ls180.v:44984.3-44992.6" - wire $0\dp_FAST_fast1_trap0_1$next[0:0]$2593 - attribute \src "issuer_ls180.v:41464.3-41465.59" - wire $0\dp_FAST_fast1_trap0_1[0:0] - attribute \src "issuer_ls180.v:45051.3-45059.6" - wire $0\dp_FAST_fast2_branch0_0$next[0:0]$2606 - attribute \src "issuer_ls180.v:41460.3-41461.63" - wire $0\dp_FAST_fast2_branch0_0[0:0] - attribute \src "issuer_ls180.v:45099.3-45107.6" - wire $0\dp_FAST_fast2_trap0_1$next[0:0]$2613 - attribute \src "issuer_ls180.v:41458.3-41459.59" - wire $0\dp_FAST_fast2_trap0_1[0:0] - attribute \src "issuer_ls180.v:44032.3-44040.6" - wire $0\dp_INT_ra_alu0_0$next[0:0]$2378 - attribute \src "issuer_ls180.v:41534.3-41535.49" - wire $0\dp_INT_ra_alu0_0[0:0] - attribute \src "issuer_ls180.v:44051.3-44059.6" - wire $0\dp_INT_ra_cr0_1$next[0:0]$2382 - attribute \src "issuer_ls180.v:41532.3-41533.47" - wire $0\dp_INT_ra_cr0_1[0:0] - attribute \src "issuer_ls180.v:44127.3-44135.6" - wire $0\dp_INT_ra_div0_5$next[0:0]$2406 - attribute \src "issuer_ls180.v:41524.3-41525.49" - wire $0\dp_INT_ra_div0_5[0:0] - attribute \src "issuer_ls180.v:44184.3-44192.6" - wire $0\dp_INT_ra_ldst0_8$next[0:0]$2424 - attribute \src "issuer_ls180.v:41518.3-41519.51" - wire $0\dp_INT_ra_ldst0_8[0:0] - attribute \src "issuer_ls180.v:44089.3-44097.6" - wire $0\dp_INT_ra_logical0_3$next[0:0]$2394 - attribute \src "issuer_ls180.v:41528.3-41529.57" - wire $0\dp_INT_ra_logical0_3[0:0] - attribute \src "issuer_ls180.v:44146.3-44154.6" - wire $0\dp_INT_ra_mul0_6$next[0:0]$2412 - attribute \src "issuer_ls180.v:41522.3-41523.49" - wire $0\dp_INT_ra_mul0_6[0:0] - attribute \src "issuer_ls180.v:44165.3-44173.6" - wire $0\dp_INT_ra_shiftrot0_7$next[0:0]$2418 - attribute \src "issuer_ls180.v:41520.3-41521.59" - wire $0\dp_INT_ra_shiftrot0_7[0:0] - attribute \src "issuer_ls180.v:44108.3-44116.6" - wire $0\dp_INT_ra_spr0_4$next[0:0]$2400 - attribute \src "issuer_ls180.v:41526.3-41527.49" - wire $0\dp_INT_ra_spr0_4[0:0] - attribute \src "issuer_ls180.v:44070.3-44078.6" - wire $0\dp_INT_ra_trap0_2$next[0:0]$2388 - attribute \src "issuer_ls180.v:41530.3-41531.51" - wire $0\dp_INT_ra_trap0_2[0:0] - attribute \src "issuer_ls180.v:44203.3-44211.6" - wire $0\dp_INT_rb_alu0_0$next[0:0]$2430 - attribute \src "issuer_ls180.v:41516.3-41517.49" - wire $0\dp_INT_rb_alu0_0[0:0] - attribute \src "issuer_ls180.v:44222.3-44230.6" - wire $0\dp_INT_rb_cr0_1$next[0:0]$2434 - attribute \src "issuer_ls180.v:41514.3-41515.47" - wire $0\dp_INT_rb_cr0_1[0:0] - attribute \src "issuer_ls180.v:44279.3-44287.6" - wire $0\dp_INT_rb_div0_4$next[0:0]$2452 - attribute \src "issuer_ls180.v:41508.3-41509.49" - wire $0\dp_INT_rb_div0_4[0:0] - attribute \src "issuer_ls180.v:44336.3-44344.6" - wire $0\dp_INT_rb_ldst0_7$next[0:0]$2470 - attribute \src "issuer_ls180.v:41502.3-41503.51" - wire $0\dp_INT_rb_ldst0_7[0:0] - attribute \src "issuer_ls180.v:44260.3-44268.6" - wire $0\dp_INT_rb_logical0_3$next[0:0]$2446 - attribute \src "issuer_ls180.v:41510.3-41511.57" - wire $0\dp_INT_rb_logical0_3[0:0] - attribute \src "issuer_ls180.v:44298.3-44306.6" - wire $0\dp_INT_rb_mul0_5$next[0:0]$2458 - attribute \src "issuer_ls180.v:41506.3-41507.49" - wire $0\dp_INT_rb_mul0_5[0:0] - attribute \src "issuer_ls180.v:44317.3-44325.6" - wire $0\dp_INT_rb_shiftrot0_6$next[0:0]$2464 - attribute \src "issuer_ls180.v:41504.3-41505.59" - wire $0\dp_INT_rb_shiftrot0_6[0:0] - attribute \src "issuer_ls180.v:44241.3-44249.6" - wire $0\dp_INT_rb_trap0_2$next[0:0]$2440 - attribute \src "issuer_ls180.v:41512.3-41513.51" - wire $0\dp_INT_rb_trap0_2[0:0] - attribute \src "issuer_ls180.v:44374.3-44382.6" - wire $0\dp_INT_rc_ldst0_1$next[0:0]$2480 - attribute \src "issuer_ls180.v:41498.3-41499.51" - wire $0\dp_INT_rc_ldst0_1[0:0] - attribute \src "issuer_ls180.v:44355.3-44363.6" - wire $0\dp_INT_rc_shiftrot0_0$next[0:0]$2476 - attribute \src "issuer_ls180.v:41500.3-41501.59" - wire $0\dp_INT_rc_shiftrot0_0[0:0] - attribute \src "issuer_ls180.v:45147.3-45155.6" - wire $0\dp_SPR_spr1_spr0_0$next[0:0]$2620 - attribute \src "issuer_ls180.v:41456.3-41457.53" - wire $0\dp_SPR_spr1_spr0_0[0:0] - attribute \src "issuer_ls180.v:44675.3-44683.6" - wire $0\dp_XER_xer_ca_alu0_0$next[0:0]$2533 - attribute \src "issuer_ls180.v:41484.3-41485.57" - wire $0\dp_XER_xer_ca_alu0_0[0:0] - attribute \src "issuer_ls180.v:44742.3-44750.6" - wire $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2544 - attribute \src "issuer_ls180.v:41480.3-41481.67" - wire $0\dp_XER_xer_ca_shiftrot0_2[0:0] - attribute \src "issuer_ls180.v:44723.3-44731.6" - wire $0\dp_XER_xer_ca_spr0_1$next[0:0]$2540 - attribute \src "issuer_ls180.v:41482.3-41483.57" - wire $0\dp_XER_xer_ca_spr0_1[0:0] - attribute \src "issuer_ls180.v:44791.3-44799.6" - wire $0\dp_XER_xer_ov_spr0_0$next[0:0]$2549 - attribute \src "issuer_ls180.v:41478.3-41479.57" - wire $0\dp_XER_xer_ov_spr0_0[0:0] - attribute \src "issuer_ls180.v:44420.3-44428.6" - wire $0\dp_XER_xer_so_alu0_0$next[0:0]$2492 - attribute \src "issuer_ls180.v:41496.3-41497.57" - wire $0\dp_XER_xer_so_alu0_0[0:0] - attribute \src "issuer_ls180.v:44568.3-44576.6" - wire $0\dp_XER_xer_so_div0_3$next[0:0]$2509 - attribute \src "issuer_ls180.v:41490.3-41491.57" - wire $0\dp_XER_xer_so_div0_3[0:0] - attribute \src "issuer_ls180.v:44439.3-44447.6" - wire $0\dp_XER_xer_so_logical0_1$next[0:0]$2498 - attribute \src "issuer_ls180.v:41494.3-41495.65" - wire $0\dp_XER_xer_so_logical0_1[0:0] - attribute \src "issuer_ls180.v:44608.3-44616.6" - wire $0\dp_XER_xer_so_mul0_4$next[0:0]$2520 - attribute \src "issuer_ls180.v:41488.3-41489.57" - wire $0\dp_XER_xer_so_mul0_4[0:0] - attribute \src "issuer_ls180.v:44627.3-44635.6" - wire $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2526 - attribute \src "issuer_ls180.v:41486.3-41487.67" - wire $0\dp_XER_xer_so_shiftrot0_5[0:0] - attribute \src "issuer_ls180.v:44549.3-44557.6" - wire $0\dp_XER_xer_so_spr0_2$next[0:0]$2505 - attribute \src "issuer_ls180.v:41492.3-41493.57" - wire $0\dp_XER_xer_so_spr0_2[0:0] - attribute \src "issuer_ls180.v:46399.3-46427.6" - wire $0\fus_cu_issue_i$10[0:0]$2784 - attribute \src "issuer_ls180.v:46895.3-46923.6" - wire $0\fus_cu_issue_i$13[0:0]$2809 - attribute \src "issuer_ls180.v:42280.3-42308.6" - wire $0\fus_cu_issue_i$16[0:0]$2278 - attribute \src "issuer_ls180.v:42776.3-42804.6" - wire $0\fus_cu_issue_i$19[0:0]$2303 - attribute \src "issuer_ls180.v:43098.3-43126.6" - wire $0\fus_cu_issue_i$22[0:0]$2322 - attribute \src "issuer_ls180.v:43536.3-43564.6" - wire $0\fus_cu_issue_i$25[0:0]$2345 - attribute \src "issuer_ls180.v:43974.3-44002.6" - wire $0\fus_cu_issue_i$28[0:0]$2368 - attribute \src "issuer_ls180.v:45667.3-45695.6" - wire $0\fus_cu_issue_i$4[0:0]$2689 - attribute \src "issuer_ls180.v:46064.3-46092.6" - wire $0\fus_cu_issue_i$7[0:0]$2751 - attribute \src "issuer_ls180.v:45459.3-45487.6" - wire $0\fus_cu_issue_i[0:0] - attribute \src "issuer_ls180.v:46428.3-46456.6" - wire width 4 $0\fus_cu_rdmaskn_i$12[3:0]$2789 - attribute \src "issuer_ls180.v:46924.3-46952.6" - wire width 3 $0\fus_cu_rdmaskn_i$15[2:0]$2814 - attribute \src "issuer_ls180.v:42309.3-42337.6" - wire width 6 $0\fus_cu_rdmaskn_i$18[5:0]$2283 - attribute \src "issuer_ls180.v:42805.3-42833.6" - wire width 3 $0\fus_cu_rdmaskn_i$21[2:0]$2308 - attribute \src "issuer_ls180.v:43127.3-43155.6" - wire width 3 $0\fus_cu_rdmaskn_i$24[2:0]$2327 - attribute \src "issuer_ls180.v:43565.3-43593.6" - wire width 5 $0\fus_cu_rdmaskn_i$27[4:0]$2350 - attribute \src "issuer_ls180.v:44003.3-44031.6" - wire width 3 $0\fus_cu_rdmaskn_i$30[2:0]$2373 - attribute \src "issuer_ls180.v:45714.3-45742.6" - wire width 6 $0\fus_cu_rdmaskn_i$6[5:0]$2700 - attribute \src "issuer_ls180.v:46102.3-46130.6" - wire width 3 $0\fus_cu_rdmaskn_i$9[2:0]$2759 - attribute \src "issuer_ls180.v:45497.3-45525.6" - wire width 4 $0\fus_cu_rdmaskn_i[3:0] - attribute \src "issuer_ls180.v:45374.3-45402.6" - wire width 4 $0\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "issuer_ls180.v:44694.3-44722.6" - wire width 12 $0\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "issuer_ls180.v:44761.3-44790.6" - wire width 64 $0\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "issuer_ls180.v:44761.3-44790.6" - wire $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:45213.3-45241.6" - wire width 2 $0\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "issuer_ls180.v:45421.3-45449.6" - wire width 32 $0\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "issuer_ls180.v:44636.3-44664.6" - wire width 7 $0\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "issuer_ls180.v:45003.3-45031.6" - wire $0\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "issuer_ls180.v:45118.3-45146.6" - wire $0\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "issuer_ls180.v:45298.3-45326.6" - wire $0\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "issuer_ls180.v:45336.3-45364.6" - wire $0\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "issuer_ls180.v:44916.3-44945.6" - wire $0\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "issuer_ls180.v:44916.3-44945.6" - wire $0\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "issuer_ls180.v:45251.3-45279.6" - wire $0\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "issuer_ls180.v:44829.3-44858.6" - wire $0\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "issuer_ls180.v:44829.3-44858.6" - wire $0\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "issuer_ls180.v:45166.3-45194.6" - wire $0\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "issuer_ls180.v:45060.3-45088.6" - wire $0\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "issuer_ls180.v:45752.3-45780.6" - wire width 64 $0\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "issuer_ls180.v:45837.3-45865.6" - wire width 12 $0\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "issuer_ls180.v:45922.3-45951.6" - wire width 64 $0\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "issuer_ls180.v:45922.3-45951.6" - wire $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:45875.3-45903.6" - wire width 32 $0\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "issuer_ls180.v:45799.3-45827.6" - wire width 7 $0\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "issuer_ls180.v:46017.3-46045.6" - wire $0\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "issuer_ls180.v:45979.3-46007.6" - wire $0\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "issuer_ls180.v:45582.3-45610.6" - wire width 12 $0\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "issuer_ls180.v:45629.3-45657.6" - wire width 32 $0\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "issuer_ls180.v:45544.3-45572.6" - wire width 7 $0\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "issuer_ls180.v:42718.3-42746.6" - wire width 4 $0\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "issuer_ls180.v:42367.3-42395.6" - wire width 12 $0\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "issuer_ls180.v:42396.3-42425.6" - wire width 64 $0\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "issuer_ls180.v:42396.3-42425.6" - wire $0\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:42544.3-42572.6" - wire width 2 $0\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "issuer_ls180.v:42747.3-42775.6" - wire width 32 $0\fus_oper_i_alu_div0__insn[31:0] - attribute \src "issuer_ls180.v:42338.3-42366.6" - wire width 7 $0\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "issuer_ls180.v:42486.3-42514.6" - wire $0\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "issuer_ls180.v:42573.3-42601.6" - wire $0\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "issuer_ls180.v:42660.3-42688.6" - wire $0\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "issuer_ls180.v:42689.3-42717.6" - wire $0\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "issuer_ls180.v:42456.3-42485.6" - wire $0\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "issuer_ls180.v:42456.3-42485.6" - wire $0\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "issuer_ls180.v:42631.3-42659.6" - wire $0\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "issuer_ls180.v:42426.3-42455.6" - wire $0\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "issuer_ls180.v:42426.3-42455.6" - wire $0\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "issuer_ls180.v:42602.3-42630.6" - wire $0\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "issuer_ls180.v:42515.3-42543.6" - wire $0\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "issuer_ls180.v:46837.3-46865.6" - wire width 4 $0\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "issuer_ls180.v:46486.3-46514.6" - wire width 12 $0\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "issuer_ls180.v:46515.3-46544.6" - wire width 64 $0\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "issuer_ls180.v:46515.3-46544.6" - wire $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:46663.3-46691.6" - wire width 2 $0\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "issuer_ls180.v:46866.3-46894.6" - wire width 32 $0\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "issuer_ls180.v:46457.3-46485.6" - wire width 7 $0\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "issuer_ls180.v:46605.3-46633.6" - wire $0\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "issuer_ls180.v:46692.3-46720.6" - wire $0\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "issuer_ls180.v:46779.3-46807.6" - wire $0\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "issuer_ls180.v:46808.3-46836.6" - wire $0\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "issuer_ls180.v:46575.3-46604.6" - wire $0\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "issuer_ls180.v:46575.3-46604.6" - wire $0\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "issuer_ls180.v:46750.3-46778.6" - wire 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"issuer_ls180.v:43333.3-43361.6" - wire width 2 $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "issuer_ls180.v:43391.3-43419.6" - wire $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "issuer_ls180.v:43507.3-43535.6" - wire width 32 $0\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "issuer_ls180.v:43156.3-43184.6" - wire width 7 $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "issuer_ls180.v:43449.3-43477.6" - wire $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "issuer_ls180.v:43478.3-43506.6" - wire $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "issuer_ls180.v:43274.3-43303.6" - wire $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "issuer_ls180.v:43274.3-43303.6" - wire $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "issuer_ls180.v:43362.3-43390.6" - wire $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "issuer_ls180.v:43420.3-43448.6" - wire $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "issuer_ls180.v:43244.3-43273.6" - wire $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "issuer_ls180.v:43244.3-43273.6" - wire $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "issuer_ls180.v:43304.3-43332.6" - wire $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "issuer_ls180.v:46982.3-47010.6" - wire width 12 $0\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "issuer_ls180.v:47011.3-47039.6" - wire width 32 $0\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "issuer_ls180.v:46953.3-46981.6" - wire width 7 $0\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "issuer_ls180.v:42251.3-42279.6" - wire $0\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "issuer_ls180.v:46283.3-46311.6" - wire width 64 $0\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "issuer_ls180.v:46187.3-46215.6" - wire width 12 $0\fus_oper_i_alu_trap0__fn_unit[11:0] - attribute \src "issuer_ls180.v:46225.3-46253.6" - wire width 32 $0\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "issuer_ls180.v:46149.3-46177.6" - wire width 7 $0\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "issuer_ls180.v:46312.3-46340.6" - wire $0\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "issuer_ls180.v:46254.3-46282.6" - wire width 64 $0\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "issuer_ls180.v:46370.3-46398.6" - wire width 13 $0\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "issuer_ls180.v:46341.3-46369.6" - wire width 7 $0\fus_oper_i_alu_trap0__traptype[6:0] - attribute \src "issuer_ls180.v:43858.3-43886.6" - wire $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "issuer_ls180.v:43829.3-43857.6" - wire width 4 $0\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "issuer_ls180.v:43623.3-43651.6" - wire width 12 $0\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "issuer_ls180.v:43652.3-43681.6" - wire width 64 $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "issuer_ls180.v:43652.3-43681.6" - wire $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:43945.3-43973.6" - wire width 32 $0\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "issuer_ls180.v:43594.3-43622.6" - wire width 7 $0\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "issuer_ls180.v:43771.3-43799.6" - wire $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "issuer_ls180.v:43800.3-43828.6" - wire $0\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "issuer_ls180.v:43916.3-43944.6" - wire width 2 $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "issuer_ls180.v:43741.3-43770.6" - wire $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "issuer_ls180.v:43741.3-43770.6" - wire $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "issuer_ls180.v:43711.3-43740.6" - wire $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "issuer_ls180.v:43711.3-43740.6" - wire $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "issuer_ls180.v:43887.3-43915.6" - wire $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "issuer_ls180.v:43682.3-43710.6" - wire $0\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "issuer_ls180.v:44060.3-44069.6" - wire width 64 $0\fus_src1_i$33[63:0]$2385 - attribute \src "issuer_ls180.v:44079.3-44088.6" - wire width 64 $0\fus_src1_i$36[63:0]$2391 - attribute \src "issuer_ls180.v:44098.3-44107.6" - wire width 64 $0\fus_src1_i$39[63:0]$2397 - attribute \src "issuer_ls180.v:44117.3-44126.6" - wire width 64 $0\fus_src1_i$42[63:0]$2403 - attribute \src "issuer_ls180.v:44136.3-44145.6" - wire width 64 $0\fus_src1_i$45[63:0]$2409 - attribute \src "issuer_ls180.v:44155.3-44164.6" - wire width 64 $0\fus_src1_i$48[63:0]$2415 - attribute \src "issuer_ls180.v:44174.3-44183.6" - wire width 64 $0\fus_src1_i$51[63:0]$2421 - attribute \src "issuer_ls180.v:44193.3-44202.6" - wire width 64 $0\fus_src1_i$54[63:0]$2427 - attribute \src "issuer_ls180.v:44974.3-44983.6" - wire width 64 $0\fus_src1_i$77[63:0]$2590 - attribute \src "issuer_ls180.v:44041.3-44050.6" - wire width 64 $0\fus_src1_i[63:0] - attribute \src "issuer_ls180.v:44231.3-44240.6" - wire width 64 $0\fus_src2_i$55[63:0]$2437 - attribute \src "issuer_ls180.v:44250.3-44259.6" - wire width 64 $0\fus_src2_i$56[63:0]$2443 - attribute \src "issuer_ls180.v:44269.3-44278.6" - wire width 64 $0\fus_src2_i$57[63:0]$2449 - attribute \src "issuer_ls180.v:44288.3-44297.6" - wire width 64 $0\fus_src2_i$58[63:0]$2455 - attribute \src "issuer_ls180.v:44307.3-44316.6" - wire width 64 $0\fus_src2_i$59[63:0]$2461 - attribute \src "issuer_ls180.v:44326.3-44335.6" - wire width 64 $0\fus_src2_i$60[63:0]$2467 - attribute \src "issuer_ls180.v:44345.3-44354.6" - wire width 64 $0\fus_src2_i$61[63:0]$2473 - attribute \src "issuer_ls180.v:45089.3-45098.6" - wire width 64 $0\fus_src2_i$80[63:0]$2610 - attribute \src "issuer_ls180.v:45156.3-45165.6" - wire width 64 $0\fus_src2_i$82[63:0]$2623 - attribute \src "issuer_ls180.v:44212.3-44221.6" - wire width 64 $0\fus_src2_i[63:0] - attribute \src "issuer_ls180.v:44383.3-44392.6" - wire width 64 $0\fus_src3_i$62[63:0]$2483 - attribute \src "issuer_ls180.v:44429.3-44438.6" - wire $0\fus_src3_i$63[0:0]$2495 - attribute \src "issuer_ls180.v:44539.3-44548.6" - wire $0\fus_src3_i$64[0:0]$2502 - attribute \src "issuer_ls180.v:44598.3-44607.6" - wire $0\fus_src3_i$65[0:0]$2517 - attribute \src "issuer_ls180.v:44617.3-44626.6" - wire $0\fus_src3_i$66[0:0]$2523 - attribute \src "issuer_ls180.v:44819.3-44828.6" - wire width 32 $0\fus_src3_i$70[31:0]$2558 - attribute \src "issuer_ls180.v:44887.3-44896.6" - wire width 4 $0\fus_src3_i$74[3:0]$2571 - attribute \src "issuer_ls180.v:44993.3-45002.6" - wire width 64 $0\fus_src3_i$78[63:0]$2596 - attribute \src "issuer_ls180.v:45041.3-45050.6" - wire width 64 $0\fus_src3_i$79[63:0]$2603 - attribute \src "issuer_ls180.v:44364.3-44373.6" - wire width 64 $0\fus_src3_i[63:0] - attribute \src "issuer_ls180.v:44665.3-44674.6" - wire $0\fus_src4_i$67[0:0]$2530 - attribute \src "issuer_ls180.v:44684.3-44693.6" - wire width 2 $0\fus_src4_i$68[1:0]$2536 - attribute \src "issuer_ls180.v:44868.3-44877.6" - wire width 4 $0\fus_src4_i$71[3:0]$2565 - attribute \src "issuer_ls180.v:45108.3-45117.6" - wire width 64 $0\fus_src4_i$81[63:0]$2616 - attribute \src "issuer_ls180.v:44558.3-44567.6" - wire $0\fus_src4_i[0:0] - attribute \src "issuer_ls180.v:44800.3-44809.6" - wire width 2 $0\fus_src5_i$69[1:0]$2552 - attribute \src "issuer_ls180.v:44906.3-44915.6" - wire width 4 $0\fus_src5_i$75[3:0]$2577 - attribute \src "issuer_ls180.v:44751.3-44760.6" - wire width 2 $0\fus_src5_i[1:0] - attribute \src "issuer_ls180.v:44955.3-44964.6" - wire width 4 $0\fus_src6_i$76[3:0]$2584 - attribute \src "issuer_ls180.v:44732.3-44741.6" - wire width 2 $0\fus_src6_i[1:0] - attribute \src "issuer_ls180.v:34906.7-34906.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:45280.3-45288.6" - wire $0\wr_pick_dly$1007$next[0:0]$2638 - attribute \src "issuer_ls180.v:41448.3-41449.51" - wire $0\wr_pick_dly$1007[0:0]$2228 - attribute \src "issuer_ls180.v:40280.7-40280.32" - wire $0\wr_pick_dly$1007[0:0]$2866 - attribute \src "issuer_ls180.v:45289.3-45297.6" - wire $0\wr_pick_dly$1025$next[0:0]$2641 - attribute \src "issuer_ls180.v:41446.3-41447.51" - wire $0\wr_pick_dly$1025[0:0]$2226 - attribute \src "issuer_ls180.v:40284.7-40284.32" - wire $0\wr_pick_dly$1025[0:0]$2868 - attribute \src "issuer_ls180.v:45327.3-45335.6" - wire $0\wr_pick_dly$1047$next[0:0]$2645 - attribute \src "issuer_ls180.v:41444.3-41445.51" - wire $0\wr_pick_dly$1047[0:0]$2224 - attribute \src "issuer_ls180.v:40288.7-40288.32" - wire $0\wr_pick_dly$1047[0:0]$2870 - attribute \src "issuer_ls180.v:45365.3-45373.6" - wire $0\wr_pick_dly$1067$next[0:0]$2649 - attribute \src "issuer_ls180.v:41442.3-41443.51" - wire $0\wr_pick_dly$1067[0:0]$2222 - attribute \src "issuer_ls180.v:40292.7-40292.32" - wire $0\wr_pick_dly$1067[0:0]$2872 - attribute \src "issuer_ls180.v:45403.3-45411.6" - wire $0\wr_pick_dly$1087$next[0:0]$2653 - attribute \src "issuer_ls180.v:41440.3-41441.51" - wire $0\wr_pick_dly$1087[0:0]$2220 - attribute \src "issuer_ls180.v:40296.7-40296.32" - wire $0\wr_pick_dly$1087[0:0]$2874 - attribute \src "issuer_ls180.v:45412.3-45420.6" - wire $0\wr_pick_dly$1106$next[0:0]$2656 - attribute \src "issuer_ls180.v:41438.3-41439.51" - wire $0\wr_pick_dly$1106[0:0]$2218 - attribute \src "issuer_ls180.v:40300.7-40300.32" - wire $0\wr_pick_dly$1106[0:0]$2876 - attribute \src "issuer_ls180.v:45450.3-45458.6" - wire $0\wr_pick_dly$1124$next[0:0]$2660 - attribute \src "issuer_ls180.v:41436.3-41437.51" - wire $0\wr_pick_dly$1124[0:0]$2216 - attribute \src "issuer_ls180.v:40304.7-40304.32" - wire $0\wr_pick_dly$1124[0:0]$2878 - attribute \src "issuer_ls180.v:45488.3-45496.6" - wire $0\wr_pick_dly$1197$next[0:0]$2664 - attribute \src "issuer_ls180.v:41434.3-41435.51" - wire $0\wr_pick_dly$1197[0:0]$2214 - attribute \src "issuer_ls180.v:40308.7-40308.32" - wire $0\wr_pick_dly$1197[0:0]$2880 - attribute \src "issuer_ls180.v:45526.3-45534.6" - wire $0\wr_pick_dly$1225$next[0:0]$2668 - attribute \src "issuer_ls180.v:41432.3-41433.51" - wire $0\wr_pick_dly$1225[0:0]$2212 - attribute \src "issuer_ls180.v:40312.7-40312.32" - wire $0\wr_pick_dly$1225[0:0]$2882 - attribute \src "issuer_ls180.v:45535.3-45543.6" - wire $0\wr_pick_dly$1245$next[0:0]$2671 - attribute \src "issuer_ls180.v:41430.3-41431.51" - wire $0\wr_pick_dly$1245[0:0]$2210 - attribute \src "issuer_ls180.v:40316.7-40316.32" - wire $0\wr_pick_dly$1245[0:0]$2884 - attribute \src "issuer_ls180.v:45573.3-45581.6" - wire $0\wr_pick_dly$1265$next[0:0]$2675 - attribute \src "issuer_ls180.v:41428.3-41429.51" - wire $0\wr_pick_dly$1265[0:0]$2208 - attribute \src "issuer_ls180.v:40320.7-40320.32" - wire $0\wr_pick_dly$1265[0:0]$2886 - attribute \src "issuer_ls180.v:45611.3-45619.6" - wire $0\wr_pick_dly$1285$next[0:0]$2679 - attribute \src "issuer_ls180.v:41426.3-41427.51" - wire $0\wr_pick_dly$1285[0:0]$2206 - attribute \src "issuer_ls180.v:40324.7-40324.32" - wire $0\wr_pick_dly$1285[0:0]$2888 - attribute \src "issuer_ls180.v:45620.3-45628.6" - wire $0\wr_pick_dly$1305$next[0:0]$2682 - attribute \src "issuer_ls180.v:41424.3-41425.51" - wire $0\wr_pick_dly$1305[0:0]$2204 - attribute \src "issuer_ls180.v:40328.7-40328.32" - wire $0\wr_pick_dly$1305[0:0]$2890 - attribute \src "issuer_ls180.v:45658.3-45666.6" - wire $0\wr_pick_dly$1325$next[0:0]$2686 - attribute \src "issuer_ls180.v:41422.3-41423.51" - wire $0\wr_pick_dly$1325[0:0]$2202 - attribute \src "issuer_ls180.v:40332.7-40332.32" - wire $0\wr_pick_dly$1325[0:0]$2892 - attribute \src "issuer_ls180.v:45696.3-45704.6" - wire $0\wr_pick_dly$1372$next[0:0]$2694 - attribute \src "issuer_ls180.v:41420.3-41421.51" - wire $0\wr_pick_dly$1372[0:0]$2200 - attribute \src "issuer_ls180.v:40336.7-40336.32" - wire $0\wr_pick_dly$1372[0:0]$2894 - attribute \src "issuer_ls180.v:45705.3-45713.6" - wire $0\wr_pick_dly$1388$next[0:0]$2697 - attribute \src "issuer_ls180.v:41418.3-41419.51" - wire $0\wr_pick_dly$1388[0:0]$2198 - attribute \src "issuer_ls180.v:40340.7-40340.32" - wire $0\wr_pick_dly$1388[0:0]$2896 - attribute \src "issuer_ls180.v:45743.3-45751.6" - wire $0\wr_pick_dly$1404$next[0:0]$2705 - attribute \src "issuer_ls180.v:41416.3-41417.51" - wire $0\wr_pick_dly$1404[0:0]$2196 - attribute \src "issuer_ls180.v:40344.7-40344.32" - wire $0\wr_pick_dly$1404[0:0]$2898 - attribute \src "issuer_ls180.v:45781.3-45789.6" - wire $0\wr_pick_dly$1438$next[0:0]$2709 - attribute \src "issuer_ls180.v:41414.3-41415.51" - wire $0\wr_pick_dly$1438[0:0]$2194 - attribute \src "issuer_ls180.v:40348.7-40348.32" - wire $0\wr_pick_dly$1438[0:0]$2900 - attribute \src "issuer_ls180.v:45790.3-45798.6" - wire $0\wr_pick_dly$1454$next[0:0]$2712 - attribute \src "issuer_ls180.v:41412.3-41413.51" - wire $0\wr_pick_dly$1454[0:0]$2192 - attribute \src "issuer_ls180.v:40352.7-40352.32" - wire $0\wr_pick_dly$1454[0:0]$2902 - attribute \src "issuer_ls180.v:45828.3-45836.6" - wire $0\wr_pick_dly$1470$next[0:0]$2716 - attribute \src "issuer_ls180.v:41410.3-41411.51" - wire $0\wr_pick_dly$1470[0:0]$2190 - attribute \src "issuer_ls180.v:40356.7-40356.32" - wire $0\wr_pick_dly$1470[0:0]$2904 - attribute \src "issuer_ls180.v:45866.3-45874.6" - wire $0\wr_pick_dly$1486$next[0:0]$2720 - attribute \src "issuer_ls180.v:41408.3-41409.51" - wire $0\wr_pick_dly$1486[0:0]$2188 - attribute \src "issuer_ls180.v:40360.7-40360.32" - wire $0\wr_pick_dly$1486[0:0]$2906 - attribute \src "issuer_ls180.v:45904.3-45912.6" - wire $0\wr_pick_dly$1522$next[0:0]$2724 - attribute \src "issuer_ls180.v:41406.3-41407.51" - wire $0\wr_pick_dly$1522[0:0]$2186 - attribute \src "issuer_ls180.v:40364.7-40364.32" - wire $0\wr_pick_dly$1522[0:0]$2908 - attribute \src "issuer_ls180.v:45913.3-45921.6" - wire $0\wr_pick_dly$1538$next[0:0]$2727 - attribute \src "issuer_ls180.v:41404.3-41405.51" - wire $0\wr_pick_dly$1538[0:0]$2184 - attribute \src "issuer_ls180.v:40368.7-40368.32" - wire $0\wr_pick_dly$1538[0:0]$2910 - attribute \src "issuer_ls180.v:45952.3-45960.6" - wire $0\wr_pick_dly$1554$next[0:0]$2731 - attribute \src "issuer_ls180.v:41402.3-41403.51" - wire $0\wr_pick_dly$1554[0:0]$2182 - attribute \src "issuer_ls180.v:40372.7-40372.32" - wire $0\wr_pick_dly$1554[0:0]$2912 - attribute \src "issuer_ls180.v:45961.3-45969.6" - wire $0\wr_pick_dly$1570$next[0:0]$2734 - attribute \src "issuer_ls180.v:41400.3-41401.51" - wire $0\wr_pick_dly$1570[0:0]$2180 - attribute \src "issuer_ls180.v:40376.7-40376.32" - wire $0\wr_pick_dly$1570[0:0]$2914 - attribute \src "issuer_ls180.v:45970.3-45978.6" - wire $0\wr_pick_dly$1612$next[0:0]$2737 - attribute \src "issuer_ls180.v:41398.3-41399.51" - wire $0\wr_pick_dly$1612[0:0]$2178 - attribute \src "issuer_ls180.v:40380.7-40380.32" - wire $0\wr_pick_dly$1612[0:0]$2916 - attribute \src "issuer_ls180.v:46008.3-46016.6" - wire $0\wr_pick_dly$1631$next[0:0]$2741 - attribute \src "issuer_ls180.v:41396.3-41397.51" - wire $0\wr_pick_dly$1631[0:0]$2176 - attribute \src "issuer_ls180.v:40384.7-40384.32" - wire $0\wr_pick_dly$1631[0:0]$2918 - attribute \src "issuer_ls180.v:46046.3-46054.6" - wire $0\wr_pick_dly$1647$next[0:0]$2745 - attribute \src "issuer_ls180.v:41394.3-41395.51" - wire $0\wr_pick_dly$1647[0:0]$2174 - attribute \src "issuer_ls180.v:40388.7-40388.32" - wire $0\wr_pick_dly$1647[0:0]$2920 - attribute \src "issuer_ls180.v:46055.3-46063.6" - wire $0\wr_pick_dly$1663$next[0:0]$2748 - attribute \src "issuer_ls180.v:41392.3-41393.51" - wire $0\wr_pick_dly$1663[0:0]$2172 - attribute \src "issuer_ls180.v:40392.7-40392.32" - wire $0\wr_pick_dly$1663[0:0]$2922 - attribute \src "issuer_ls180.v:46093.3-46101.6" - wire $0\wr_pick_dly$1679$next[0:0]$2756 - attribute \src "issuer_ls180.v:41390.3-41391.51" - wire $0\wr_pick_dly$1679[0:0]$2170 - attribute \src "issuer_ls180.v:40396.7-40396.32" - wire $0\wr_pick_dly$1679[0:0]$2924 - attribute \src "issuer_ls180.v:46131.3-46139.6" - wire $0\wr_pick_dly$1723$next[0:0]$2764 - attribute \src "issuer_ls180.v:41388.3-41389.51" - wire $0\wr_pick_dly$1723[0:0]$2168 - attribute \src "issuer_ls180.v:40400.7-40400.32" - wire $0\wr_pick_dly$1723[0:0]$2926 - attribute \src "issuer_ls180.v:46140.3-46148.6" - wire $0\wr_pick_dly$1739$next[0:0]$2767 - attribute \src "issuer_ls180.v:41386.3-41387.51" - wire $0\wr_pick_dly$1739[0:0]$2166 - attribute \src "issuer_ls180.v:40404.7-40404.32" - wire $0\wr_pick_dly$1739[0:0]$2928 - attribute \src "issuer_ls180.v:46178.3-46186.6" - wire $0\wr_pick_dly$1763$next[0:0]$2771 - attribute \src "issuer_ls180.v:41384.3-41385.51" - wire $0\wr_pick_dly$1763[0:0]$2164 - attribute \src "issuer_ls180.v:40408.7-40408.32" - wire $0\wr_pick_dly$1763[0:0]$2930 - attribute \src "issuer_ls180.v:46216.3-46224.6" - wire $0\wr_pick_dly$1783$next[0:0]$2775 - attribute \src "issuer_ls180.v:41382.3-41383.51" - wire $0\wr_pick_dly$1783[0:0]$2162 - attribute \src "issuer_ls180.v:40412.7-40412.32" - wire $0\wr_pick_dly$1783[0:0]$2932 - attribute \src "issuer_ls180.v:45204.3-45212.6" - wire $0\wr_pick_dly$967$next[0:0]$2630 - attribute \src "issuer_ls180.v:41452.3-41453.49" - wire $0\wr_pick_dly$967[0:0]$2232 - attribute \src "issuer_ls180.v:40416.7-40416.31" - wire $0\wr_pick_dly$967[0:0]$2934 - attribute \src "issuer_ls180.v:45242.3-45250.6" - wire $0\wr_pick_dly$986$next[0:0]$2634 - attribute \src "issuer_ls180.v:41450.3-41451.49" - wire $0\wr_pick_dly$986[0:0]$2230 - attribute \src "issuer_ls180.v:40420.7-40420.31" - wire $0\wr_pick_dly$986[0:0]$2936 - attribute \src "issuer_ls180.v:45195.3-45203.6" - wire $0\wr_pick_dly$next[0:0]$2627 - attribute \src "issuer_ls180.v:41454.3-41455.39" - wire $0\wr_pick_dly[0:0] - attribute \src "issuer_ls180.v:44448.3-44538.6" - wire $10\corebusy_o[0:0] - attribute \src "issuer_ls180.v:44448.3-44538.6" - wire $11\corebusy_o[0:0] - attribute \src "issuer_ls180.v:44448.3-44538.6" - wire $12\corebusy_o[0:0] - attribute \src "issuer_ls180.v:44448.3-44538.6" - wire $13\corebusy_o[0:0] - attribute \src "issuer_ls180.v:44577.3-44597.6" - wire $1\core_terminate_o$next[0:0]$2513 - attribute \src "issuer_ls180.v:36924.7-36924.30" - wire $1\core_terminate_o[0:0] - attribute \src "issuer_ls180.v:44448.3-44538.6" - wire $1\corebusy_o[0:0] - attribute \src "issuer_ls180.v:44393.3-44419.6" - wire width 2 $1\counter$next[1:0]$2487 - attribute \src "issuer_ls180.v:36937.13-36937.27" - wire width 2 $1\counter[1:0] - attribute \src "issuer_ls180.v:44878.3-44886.6" - wire $1\dp_CR_cr_a_branch0_1$next[0:0]$2569 - attribute \src "issuer_ls180.v:38065.7-38065.34" - wire $1\dp_CR_cr_a_branch0_1[0:0] - attribute \src "issuer_ls180.v:44859.3-44867.6" - wire $1\dp_CR_cr_a_cr0_0$next[0:0]$2563 - attribute \src "issuer_ls180.v:38069.7-38069.30" - wire $1\dp_CR_cr_a_cr0_0[0:0] - attribute \src "issuer_ls180.v:44897.3-44905.6" - wire $1\dp_CR_cr_b_cr0_0$next[0:0]$2575 - attribute \src "issuer_ls180.v:38073.7-38073.30" - wire $1\dp_CR_cr_b_cr0_0[0:0] - attribute \src "issuer_ls180.v:44946.3-44954.6" - wire $1\dp_CR_cr_c_cr0_0$next[0:0]$2582 - attribute \src "issuer_ls180.v:38077.7-38077.30" - wire $1\dp_CR_cr_c_cr0_0[0:0] - attribute \src "issuer_ls180.v:44810.3-44818.6" - wire $1\dp_CR_full_cr_cr0_0$next[0:0]$2556 - attribute \src "issuer_ls180.v:38081.7-38081.33" - wire $1\dp_CR_full_cr_cr0_0[0:0] - attribute \src "issuer_ls180.v:44965.3-44973.6" - wire $1\dp_FAST_fast1_branch0_0$next[0:0]$2588 - attribute \src "issuer_ls180.v:38085.7-38085.37" - wire $1\dp_FAST_fast1_branch0_0[0:0] - attribute \src "issuer_ls180.v:45032.3-45040.6" - wire $1\dp_FAST_fast1_spr0_2$next[0:0]$2601 - attribute \src "issuer_ls180.v:38089.7-38089.34" - wire $1\dp_FAST_fast1_spr0_2[0:0] - attribute \src "issuer_ls180.v:44984.3-44992.6" - wire $1\dp_FAST_fast1_trap0_1$next[0:0]$2594 - attribute \src "issuer_ls180.v:38093.7-38093.35" - wire $1\dp_FAST_fast1_trap0_1[0:0] - attribute \src "issuer_ls180.v:45051.3-45059.6" - wire $1\dp_FAST_fast2_branch0_0$next[0:0]$2607 - attribute \src "issuer_ls180.v:38097.7-38097.37" - wire $1\dp_FAST_fast2_branch0_0[0:0] - attribute \src "issuer_ls180.v:45099.3-45107.6" - wire $1\dp_FAST_fast2_trap0_1$next[0:0]$2614 - attribute \src "issuer_ls180.v:38101.7-38101.35" - wire $1\dp_FAST_fast2_trap0_1[0:0] - attribute \src "issuer_ls180.v:44032.3-44040.6" - wire $1\dp_INT_ra_alu0_0$next[0:0]$2379 - attribute \src "issuer_ls180.v:38105.7-38105.30" - wire $1\dp_INT_ra_alu0_0[0:0] - attribute \src "issuer_ls180.v:44051.3-44059.6" - wire $1\dp_INT_ra_cr0_1$next[0:0]$2383 - attribute \src "issuer_ls180.v:38109.7-38109.29" - wire $1\dp_INT_ra_cr0_1[0:0] - attribute \src "issuer_ls180.v:44127.3-44135.6" - wire $1\dp_INT_ra_div0_5$next[0:0]$2407 - attribute \src "issuer_ls180.v:38113.7-38113.30" - wire $1\dp_INT_ra_div0_5[0:0] - attribute \src "issuer_ls180.v:44184.3-44192.6" - wire $1\dp_INT_ra_ldst0_8$next[0:0]$2425 - attribute \src "issuer_ls180.v:38117.7-38117.31" - wire $1\dp_INT_ra_ldst0_8[0:0] - attribute \src "issuer_ls180.v:44089.3-44097.6" - wire $1\dp_INT_ra_logical0_3$next[0:0]$2395 - attribute \src "issuer_ls180.v:38121.7-38121.34" - wire $1\dp_INT_ra_logical0_3[0:0] - attribute \src "issuer_ls180.v:44146.3-44154.6" - wire $1\dp_INT_ra_mul0_6$next[0:0]$2413 - attribute \src "issuer_ls180.v:38125.7-38125.30" - wire $1\dp_INT_ra_mul0_6[0:0] - attribute \src "issuer_ls180.v:44165.3-44173.6" - wire $1\dp_INT_ra_shiftrot0_7$next[0:0]$2419 - attribute \src "issuer_ls180.v:38129.7-38129.35" - wire $1\dp_INT_ra_shiftrot0_7[0:0] - attribute \src "issuer_ls180.v:44108.3-44116.6" - wire $1\dp_INT_ra_spr0_4$next[0:0]$2401 - attribute \src "issuer_ls180.v:38133.7-38133.30" - wire $1\dp_INT_ra_spr0_4[0:0] - attribute \src "issuer_ls180.v:44070.3-44078.6" - wire $1\dp_INT_ra_trap0_2$next[0:0]$2389 - attribute \src "issuer_ls180.v:38137.7-38137.31" - wire $1\dp_INT_ra_trap0_2[0:0] - attribute \src "issuer_ls180.v:44203.3-44211.6" - wire $1\dp_INT_rb_alu0_0$next[0:0]$2431 - attribute \src "issuer_ls180.v:38141.7-38141.30" - wire $1\dp_INT_rb_alu0_0[0:0] - attribute \src "issuer_ls180.v:44222.3-44230.6" - wire $1\dp_INT_rb_cr0_1$next[0:0]$2435 - attribute \src "issuer_ls180.v:38145.7-38145.29" - wire $1\dp_INT_rb_cr0_1[0:0] - attribute \src "issuer_ls180.v:44279.3-44287.6" - wire $1\dp_INT_rb_div0_4$next[0:0]$2453 - attribute \src "issuer_ls180.v:38149.7-38149.30" - wire $1\dp_INT_rb_div0_4[0:0] - attribute \src "issuer_ls180.v:44336.3-44344.6" - wire $1\dp_INT_rb_ldst0_7$next[0:0]$2471 - attribute \src "issuer_ls180.v:38153.7-38153.31" - wire $1\dp_INT_rb_ldst0_7[0:0] - attribute \src "issuer_ls180.v:44260.3-44268.6" - wire $1\dp_INT_rb_logical0_3$next[0:0]$2447 - attribute \src "issuer_ls180.v:38157.7-38157.34" - wire $1\dp_INT_rb_logical0_3[0:0] - attribute \src "issuer_ls180.v:44298.3-44306.6" - wire $1\dp_INT_rb_mul0_5$next[0:0]$2459 - attribute \src "issuer_ls180.v:38161.7-38161.30" - wire $1\dp_INT_rb_mul0_5[0:0] - attribute \src "issuer_ls180.v:44317.3-44325.6" - wire $1\dp_INT_rb_shiftrot0_6$next[0:0]$2465 - attribute \src "issuer_ls180.v:38165.7-38165.35" - wire $1\dp_INT_rb_shiftrot0_6[0:0] - attribute \src "issuer_ls180.v:44241.3-44249.6" - wire $1\dp_INT_rb_trap0_2$next[0:0]$2441 - attribute \src "issuer_ls180.v:38169.7-38169.31" - wire $1\dp_INT_rb_trap0_2[0:0] - attribute \src "issuer_ls180.v:44374.3-44382.6" - wire $1\dp_INT_rc_ldst0_1$next[0:0]$2481 - attribute \src "issuer_ls180.v:38173.7-38173.31" - wire $1\dp_INT_rc_ldst0_1[0:0] - attribute \src "issuer_ls180.v:44355.3-44363.6" - wire $1\dp_INT_rc_shiftrot0_0$next[0:0]$2477 - attribute \src "issuer_ls180.v:38177.7-38177.35" - wire $1\dp_INT_rc_shiftrot0_0[0:0] - attribute \src "issuer_ls180.v:45147.3-45155.6" - wire $1\dp_SPR_spr1_spr0_0$next[0:0]$2621 - attribute \src "issuer_ls180.v:38181.7-38181.32" - wire $1\dp_SPR_spr1_spr0_0[0:0] - attribute \src "issuer_ls180.v:44675.3-44683.6" - wire $1\dp_XER_xer_ca_alu0_0$next[0:0]$2534 - attribute \src "issuer_ls180.v:38185.7-38185.34" - wire $1\dp_XER_xer_ca_alu0_0[0:0] - attribute \src "issuer_ls180.v:44742.3-44750.6" - wire $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2545 - attribute \src "issuer_ls180.v:38189.7-38189.39" - wire $1\dp_XER_xer_ca_shiftrot0_2[0:0] - attribute \src "issuer_ls180.v:44723.3-44731.6" - wire $1\dp_XER_xer_ca_spr0_1$next[0:0]$2541 - attribute \src "issuer_ls180.v:38193.7-38193.34" - wire $1\dp_XER_xer_ca_spr0_1[0:0] - attribute \src "issuer_ls180.v:44791.3-44799.6" - wire $1\dp_XER_xer_ov_spr0_0$next[0:0]$2550 - attribute \src "issuer_ls180.v:38197.7-38197.34" - wire $1\dp_XER_xer_ov_spr0_0[0:0] - attribute \src "issuer_ls180.v:44420.3-44428.6" - wire $1\dp_XER_xer_so_alu0_0$next[0:0]$2493 - attribute \src "issuer_ls180.v:38201.7-38201.34" - wire $1\dp_XER_xer_so_alu0_0[0:0] - attribute \src "issuer_ls180.v:44568.3-44576.6" - wire $1\dp_XER_xer_so_div0_3$next[0:0]$2510 - attribute \src "issuer_ls180.v:38205.7-38205.34" - wire $1\dp_XER_xer_so_div0_3[0:0] - attribute \src "issuer_ls180.v:44439.3-44447.6" - wire $1\dp_XER_xer_so_logical0_1$next[0:0]$2499 - attribute \src "issuer_ls180.v:38209.7-38209.38" - wire $1\dp_XER_xer_so_logical0_1[0:0] - attribute \src "issuer_ls180.v:44608.3-44616.6" - wire $1\dp_XER_xer_so_mul0_4$next[0:0]$2521 - attribute \src "issuer_ls180.v:38213.7-38213.34" - wire $1\dp_XER_xer_so_mul0_4[0:0] - attribute \src "issuer_ls180.v:44627.3-44635.6" - wire $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2527 - attribute \src "issuer_ls180.v:38217.7-38217.39" - wire $1\dp_XER_xer_so_shiftrot0_5[0:0] - attribute \src "issuer_ls180.v:44549.3-44557.6" - wire $1\dp_XER_xer_so_spr0_2$next[0:0]$2506 - attribute \src "issuer_ls180.v:38221.7-38221.34" - wire $1\dp_XER_xer_so_spr0_2[0:0] - attribute \src "issuer_ls180.v:46399.3-46427.6" - wire $1\fus_cu_issue_i$10[0:0]$2785 - attribute \src "issuer_ls180.v:46895.3-46923.6" - wire $1\fus_cu_issue_i$13[0:0]$2810 - attribute \src "issuer_ls180.v:42280.3-42308.6" - wire $1\fus_cu_issue_i$16[0:0]$2279 - attribute \src "issuer_ls180.v:42776.3-42804.6" - wire $1\fus_cu_issue_i$19[0:0]$2304 - attribute \src "issuer_ls180.v:43098.3-43126.6" - wire $1\fus_cu_issue_i$22[0:0]$2323 - attribute \src "issuer_ls180.v:43536.3-43564.6" - wire $1\fus_cu_issue_i$25[0:0]$2346 - attribute \src "issuer_ls180.v:43974.3-44002.6" - wire $1\fus_cu_issue_i$28[0:0]$2369 - attribute \src "issuer_ls180.v:45667.3-45695.6" - wire $1\fus_cu_issue_i$4[0:0]$2690 - attribute \src "issuer_ls180.v:46064.3-46092.6" - wire $1\fus_cu_issue_i$7[0:0]$2752 - attribute \src "issuer_ls180.v:45459.3-45487.6" - wire $1\fus_cu_issue_i[0:0] - attribute \src "issuer_ls180.v:46428.3-46456.6" - wire width 4 $1\fus_cu_rdmaskn_i$12[3:0]$2790 - attribute \src "issuer_ls180.v:46924.3-46952.6" - wire width 3 $1\fus_cu_rdmaskn_i$15[2:0]$2815 - attribute \src "issuer_ls180.v:42309.3-42337.6" - wire width 6 $1\fus_cu_rdmaskn_i$18[5:0]$2284 - attribute \src "issuer_ls180.v:42805.3-42833.6" - wire width 3 $1\fus_cu_rdmaskn_i$21[2:0]$2309 - attribute \src "issuer_ls180.v:43127.3-43155.6" - wire width 3 $1\fus_cu_rdmaskn_i$24[2:0]$2328 - attribute \src "issuer_ls180.v:43565.3-43593.6" - wire width 5 $1\fus_cu_rdmaskn_i$27[4:0]$2351 - attribute \src "issuer_ls180.v:44003.3-44031.6" - wire width 3 $1\fus_cu_rdmaskn_i$30[2:0]$2374 - attribute \src "issuer_ls180.v:45714.3-45742.6" - wire width 6 $1\fus_cu_rdmaskn_i$6[5:0]$2701 - attribute \src "issuer_ls180.v:46102.3-46130.6" - wire width 3 $1\fus_cu_rdmaskn_i$9[2:0]$2760 - attribute \src "issuer_ls180.v:45497.3-45525.6" - wire width 4 $1\fus_cu_rdmaskn_i[3:0] - attribute \src "issuer_ls180.v:45374.3-45402.6" - wire width 4 $1\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src 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attribute \src "issuer_ls180.v:44916.3-44945.6" - wire $1\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "issuer_ls180.v:44916.3-44945.6" - wire $1\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "issuer_ls180.v:45251.3-45279.6" - wire $1\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "issuer_ls180.v:44829.3-44858.6" - wire $1\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "issuer_ls180.v:44829.3-44858.6" - wire $1\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "issuer_ls180.v:45166.3-45194.6" - wire $1\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "issuer_ls180.v:45060.3-45088.6" - wire $1\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "issuer_ls180.v:45752.3-45780.6" - wire width 64 $1\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "issuer_ls180.v:45837.3-45865.6" - wire width 12 $1\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "issuer_ls180.v:45922.3-45951.6" - wire width 64 $1\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "issuer_ls180.v:45922.3-45951.6" - wire $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:45875.3-45903.6" - wire width 32 $1\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "issuer_ls180.v:45799.3-45827.6" - wire width 7 $1\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "issuer_ls180.v:46017.3-46045.6" - wire $1\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "issuer_ls180.v:45979.3-46007.6" - wire $1\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "issuer_ls180.v:45582.3-45610.6" - wire width 12 $1\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "issuer_ls180.v:45629.3-45657.6" - wire width 32 $1\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "issuer_ls180.v:45544.3-45572.6" - wire width 7 $1\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "issuer_ls180.v:42718.3-42746.6" - wire width 4 $1\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "issuer_ls180.v:42367.3-42395.6" - wire width 12 $1\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "issuer_ls180.v:42396.3-42425.6" - wire width 64 $1\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "issuer_ls180.v:42396.3-42425.6" - wire $1\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:42544.3-42572.6" - wire width 2 $1\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "issuer_ls180.v:42747.3-42775.6" - wire width 32 $1\fus_oper_i_alu_div0__insn[31:0] - attribute \src "issuer_ls180.v:42338.3-42366.6" - wire width 7 $1\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "issuer_ls180.v:42486.3-42514.6" - wire $1\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "issuer_ls180.v:42573.3-42601.6" - wire $1\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "issuer_ls180.v:42660.3-42688.6" - wire $1\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "issuer_ls180.v:42689.3-42717.6" - wire $1\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "issuer_ls180.v:42456.3-42485.6" - wire $1\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "issuer_ls180.v:42456.3-42485.6" - wire $1\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "issuer_ls180.v:42631.3-42659.6" - wire $1\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "issuer_ls180.v:42426.3-42455.6" - wire $1\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "issuer_ls180.v:42426.3-42455.6" - wire $1\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "issuer_ls180.v:42602.3-42630.6" - wire $1\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "issuer_ls180.v:42515.3-42543.6" - wire $1\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "issuer_ls180.v:46837.3-46865.6" - wire width 4 $1\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "issuer_ls180.v:46486.3-46514.6" - wire width 12 $1\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "issuer_ls180.v:46515.3-46544.6" - wire width 64 $1\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "issuer_ls180.v:46515.3-46544.6" - wire $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:46663.3-46691.6" - wire width 2 $1\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "issuer_ls180.v:46866.3-46894.6" - wire width 32 $1\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "issuer_ls180.v:46457.3-46485.6" - wire width 7 $1\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "issuer_ls180.v:46605.3-46633.6" - wire $1\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "issuer_ls180.v:46692.3-46720.6" - wire $1\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "issuer_ls180.v:46779.3-46807.6" - wire $1\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "issuer_ls180.v:46808.3-46836.6" - wire $1\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "issuer_ls180.v:46575.3-46604.6" - wire $1\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "issuer_ls180.v:46575.3-46604.6" - wire $1\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "issuer_ls180.v:46750.3-46778.6" - wire $1\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "issuer_ls180.v:46545.3-46574.6" - wire $1\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "issuer_ls180.v:46545.3-46574.6" - wire $1\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "issuer_ls180.v:46721.3-46749.6" - wire $1\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "issuer_ls180.v:46634.3-46662.6" - wire $1\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "issuer_ls180.v:42863.3-42891.6" - wire width 12 $1\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "issuer_ls180.v:42892.3-42921.6" - wire width 64 $1\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "issuer_ls180.v:42892.3-42921.6" - wire $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:43069.3-43097.6" - wire width 32 $1\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "issuer_ls180.v:42834.3-42862.6" - wire width 7 $1\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "issuer_ls180.v:43011.3-43039.6" - wire $1\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "issuer_ls180.v:43040.3-43068.6" - wire $1\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "issuer_ls180.v:42952.3-42981.6" - wire $1\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "issuer_ls180.v:42952.3-42981.6" - wire $1\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "issuer_ls180.v:42922.3-42951.6" - wire $1\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "issuer_ls180.v:42922.3-42951.6" - wire $1\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "issuer_ls180.v:42982.3-43010.6" - wire $1\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "issuer_ls180.v:43185.3-43213.6" - wire width 12 $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src "issuer_ls180.v:43214.3-43243.6" - wire width 64 $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "issuer_ls180.v:43214.3-43243.6" - wire $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:43333.3-43361.6" - wire width 2 $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "issuer_ls180.v:43391.3-43419.6" - wire $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "issuer_ls180.v:43507.3-43535.6" - wire width 32 $1\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "issuer_ls180.v:43156.3-43184.6" - wire width 7 $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "issuer_ls180.v:43449.3-43477.6" - wire $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "issuer_ls180.v:43478.3-43506.6" - wire $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "issuer_ls180.v:43274.3-43303.6" - wire $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "issuer_ls180.v:43274.3-43303.6" - wire $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "issuer_ls180.v:43362.3-43390.6" - wire $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "issuer_ls180.v:43420.3-43448.6" - wire $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "issuer_ls180.v:43244.3-43273.6" - wire $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "issuer_ls180.v:43244.3-43273.6" - wire $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "issuer_ls180.v:43304.3-43332.6" - wire $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "issuer_ls180.v:46982.3-47010.6" - wire width 12 $1\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "issuer_ls180.v:47011.3-47039.6" - wire width 32 $1\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "issuer_ls180.v:46953.3-46981.6" - wire width 7 $1\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "issuer_ls180.v:42251.3-42279.6" - wire $1\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "issuer_ls180.v:46283.3-46311.6" - wire width 64 $1\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "issuer_ls180.v:46187.3-46215.6" - wire width 12 $1\fus_oper_i_alu_trap0__fn_unit[11:0] - attribute \src "issuer_ls180.v:46225.3-46253.6" - wire width 32 $1\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "issuer_ls180.v:46149.3-46177.6" - wire width 7 $1\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "issuer_ls180.v:46312.3-46340.6" - wire $1\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "issuer_ls180.v:46254.3-46282.6" - wire width 64 $1\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "issuer_ls180.v:46370.3-46398.6" - wire width 13 $1\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "issuer_ls180.v:46341.3-46369.6" - wire width 7 $1\fus_oper_i_alu_trap0__traptype[6:0] - attribute \src "issuer_ls180.v:43858.3-43886.6" - wire $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "issuer_ls180.v:43829.3-43857.6" - wire width 4 $1\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "issuer_ls180.v:43623.3-43651.6" - wire width 12 $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "issuer_ls180.v:43652.3-43681.6" - wire width 64 $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "issuer_ls180.v:43652.3-43681.6" - wire $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:43945.3-43973.6" - wire width 32 $1\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "issuer_ls180.v:43594.3-43622.6" - wire width 7 $1\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "issuer_ls180.v:43771.3-43799.6" - wire $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "issuer_ls180.v:43800.3-43828.6" - wire $1\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "issuer_ls180.v:43916.3-43944.6" - wire width 2 $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "issuer_ls180.v:43741.3-43770.6" - wire $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "issuer_ls180.v:43741.3-43770.6" - wire $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "issuer_ls180.v:43711.3-43740.6" - wire $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "issuer_ls180.v:43711.3-43740.6" - wire $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "issuer_ls180.v:43887.3-43915.6" - wire $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "issuer_ls180.v:43682.3-43710.6" - wire $1\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "issuer_ls180.v:44060.3-44069.6" - wire width 64 $1\fus_src1_i$33[63:0]$2386 - attribute \src "issuer_ls180.v:44079.3-44088.6" - wire width 64 $1\fus_src1_i$36[63:0]$2392 - attribute \src "issuer_ls180.v:44098.3-44107.6" - wire width 64 $1\fus_src1_i$39[63:0]$2398 - attribute \src "issuer_ls180.v:44117.3-44126.6" - wire width 64 $1\fus_src1_i$42[63:0]$2404 - attribute \src "issuer_ls180.v:44136.3-44145.6" - wire width 64 $1\fus_src1_i$45[63:0]$2410 - attribute \src "issuer_ls180.v:44155.3-44164.6" - wire width 64 $1\fus_src1_i$48[63:0]$2416 - attribute \src "issuer_ls180.v:44174.3-44183.6" - wire width 64 $1\fus_src1_i$51[63:0]$2422 - attribute \src "issuer_ls180.v:44193.3-44202.6" - wire width 64 $1\fus_src1_i$54[63:0]$2428 - attribute \src "issuer_ls180.v:44974.3-44983.6" - wire width 64 $1\fus_src1_i$77[63:0]$2591 - attribute \src "issuer_ls180.v:44041.3-44050.6" - wire width 64 $1\fus_src1_i[63:0] - attribute \src "issuer_ls180.v:44231.3-44240.6" - wire width 64 $1\fus_src2_i$55[63:0]$2438 - attribute \src "issuer_ls180.v:44250.3-44259.6" - wire width 64 $1\fus_src2_i$56[63:0]$2444 - attribute \src "issuer_ls180.v:44269.3-44278.6" - wire width 64 $1\fus_src2_i$57[63:0]$2450 - attribute \src "issuer_ls180.v:44288.3-44297.6" - wire width 64 $1\fus_src2_i$58[63:0]$2456 - attribute \src "issuer_ls180.v:44307.3-44316.6" - wire width 64 $1\fus_src2_i$59[63:0]$2462 - attribute \src "issuer_ls180.v:44326.3-44335.6" - wire width 64 $1\fus_src2_i$60[63:0]$2468 - attribute \src "issuer_ls180.v:44345.3-44354.6" - wire width 64 $1\fus_src2_i$61[63:0]$2474 - attribute \src "issuer_ls180.v:45089.3-45098.6" - wire width 64 $1\fus_src2_i$80[63:0]$2611 - attribute \src "issuer_ls180.v:45156.3-45165.6" - wire width 64 $1\fus_src2_i$82[63:0]$2624 - attribute \src "issuer_ls180.v:44212.3-44221.6" - wire width 64 $1\fus_src2_i[63:0] - attribute \src "issuer_ls180.v:44383.3-44392.6" - wire width 64 $1\fus_src3_i$62[63:0]$2484 - attribute \src "issuer_ls180.v:44429.3-44438.6" - wire $1\fus_src3_i$63[0:0]$2496 - attribute \src "issuer_ls180.v:44539.3-44548.6" - wire $1\fus_src3_i$64[0:0]$2503 - attribute \src "issuer_ls180.v:44598.3-44607.6" - wire $1\fus_src3_i$65[0:0]$2518 - attribute \src "issuer_ls180.v:44617.3-44626.6" - wire $1\fus_src3_i$66[0:0]$2524 - attribute \src "issuer_ls180.v:44819.3-44828.6" - wire width 32 $1\fus_src3_i$70[31:0]$2559 - attribute \src "issuer_ls180.v:44887.3-44896.6" - wire width 4 $1\fus_src3_i$74[3:0]$2572 - attribute \src "issuer_ls180.v:44993.3-45002.6" - wire width 64 $1\fus_src3_i$78[63:0]$2597 - attribute \src "issuer_ls180.v:45041.3-45050.6" - wire width 64 $1\fus_src3_i$79[63:0]$2604 - attribute \src "issuer_ls180.v:44364.3-44373.6" - wire width 64 $1\fus_src3_i[63:0] - attribute \src "issuer_ls180.v:44665.3-44674.6" - wire $1\fus_src4_i$67[0:0]$2531 - attribute \src "issuer_ls180.v:44684.3-44693.6" - wire width 2 $1\fus_src4_i$68[1:0]$2537 - attribute \src "issuer_ls180.v:44868.3-44877.6" - wire width 4 $1\fus_src4_i$71[3:0]$2566 - attribute \src "issuer_ls180.v:45108.3-45117.6" - wire width 64 $1\fus_src4_i$81[63:0]$2617 - attribute \src "issuer_ls180.v:44558.3-44567.6" - wire $1\fus_src4_i[0:0] - attribute \src "issuer_ls180.v:44800.3-44809.6" - wire width 2 $1\fus_src5_i$69[1:0]$2553 - attribute \src "issuer_ls180.v:44906.3-44915.6" - wire width 4 $1\fus_src5_i$75[3:0]$2578 - attribute \src "issuer_ls180.v:44751.3-44760.6" - wire width 2 $1\fus_src5_i[1:0] - attribute \src "issuer_ls180.v:44955.3-44964.6" - wire width 4 $1\fus_src6_i$76[3:0]$2585 - attribute \src "issuer_ls180.v:44732.3-44741.6" - wire width 2 $1\fus_src6_i[1:0] - attribute \src "issuer_ls180.v:45280.3-45288.6" - wire $1\wr_pick_dly$1007$next[0:0]$2639 - attribute \src "issuer_ls180.v:45289.3-45297.6" - wire $1\wr_pick_dly$1025$next[0:0]$2642 - attribute \src "issuer_ls180.v:45327.3-45335.6" - wire $1\wr_pick_dly$1047$next[0:0]$2646 - attribute \src "issuer_ls180.v:45365.3-45373.6" - wire $1\wr_pick_dly$1067$next[0:0]$2650 - attribute \src "issuer_ls180.v:45403.3-45411.6" - wire $1\wr_pick_dly$1087$next[0:0]$2654 - attribute \src "issuer_ls180.v:45412.3-45420.6" - wire $1\wr_pick_dly$1106$next[0:0]$2657 - attribute \src "issuer_ls180.v:45450.3-45458.6" - wire $1\wr_pick_dly$1124$next[0:0]$2661 - attribute \src "issuer_ls180.v:45488.3-45496.6" - wire $1\wr_pick_dly$1197$next[0:0]$2665 - attribute \src "issuer_ls180.v:45526.3-45534.6" - wire $1\wr_pick_dly$1225$next[0:0]$2669 - attribute \src "issuer_ls180.v:45535.3-45543.6" - wire $1\wr_pick_dly$1245$next[0:0]$2672 - attribute \src "issuer_ls180.v:45573.3-45581.6" - wire $1\wr_pick_dly$1265$next[0:0]$2676 - attribute \src "issuer_ls180.v:45611.3-45619.6" - wire $1\wr_pick_dly$1285$next[0:0]$2680 - attribute \src "issuer_ls180.v:45620.3-45628.6" - wire $1\wr_pick_dly$1305$next[0:0]$2683 - attribute \src "issuer_ls180.v:45658.3-45666.6" - wire $1\wr_pick_dly$1325$next[0:0]$2687 - attribute \src "issuer_ls180.v:45696.3-45704.6" - wire $1\wr_pick_dly$1372$next[0:0]$2695 - attribute \src "issuer_ls180.v:45705.3-45713.6" - wire $1\wr_pick_dly$1388$next[0:0]$2698 - attribute \src "issuer_ls180.v:45743.3-45751.6" - wire $1\wr_pick_dly$1404$next[0:0]$2706 - attribute \src "issuer_ls180.v:45781.3-45789.6" - wire $1\wr_pick_dly$1438$next[0:0]$2710 - attribute \src "issuer_ls180.v:45790.3-45798.6" - wire $1\wr_pick_dly$1454$next[0:0]$2713 - attribute \src "issuer_ls180.v:45828.3-45836.6" - wire $1\wr_pick_dly$1470$next[0:0]$2717 - attribute \src "issuer_ls180.v:45866.3-45874.6" - wire $1\wr_pick_dly$1486$next[0:0]$2721 - attribute \src "issuer_ls180.v:45904.3-45912.6" - wire $1\wr_pick_dly$1522$next[0:0]$2725 - attribute \src "issuer_ls180.v:45913.3-45921.6" - wire $1\wr_pick_dly$1538$next[0:0]$2728 - attribute \src "issuer_ls180.v:45952.3-45960.6" - wire $1\wr_pick_dly$1554$next[0:0]$2732 - attribute \src "issuer_ls180.v:45961.3-45969.6" - wire $1\wr_pick_dly$1570$next[0:0]$2735 - attribute \src "issuer_ls180.v:45970.3-45978.6" - wire $1\wr_pick_dly$1612$next[0:0]$2738 - attribute \src "issuer_ls180.v:46008.3-46016.6" - wire $1\wr_pick_dly$1631$next[0:0]$2742 - attribute \src "issuer_ls180.v:46046.3-46054.6" - wire $1\wr_pick_dly$1647$next[0:0]$2746 - attribute \src "issuer_ls180.v:46055.3-46063.6" - wire $1\wr_pick_dly$1663$next[0:0]$2749 - attribute \src "issuer_ls180.v:46093.3-46101.6" - wire $1\wr_pick_dly$1679$next[0:0]$2757 - attribute \src "issuer_ls180.v:46131.3-46139.6" - wire $1\wr_pick_dly$1723$next[0:0]$2765 - attribute \src "issuer_ls180.v:46140.3-46148.6" - wire $1\wr_pick_dly$1739$next[0:0]$2768 - attribute \src "issuer_ls180.v:46178.3-46186.6" - wire $1\wr_pick_dly$1763$next[0:0]$2772 - attribute \src "issuer_ls180.v:46216.3-46224.6" - wire $1\wr_pick_dly$1783$next[0:0]$2776 - attribute \src "issuer_ls180.v:45204.3-45212.6" - wire $1\wr_pick_dly$967$next[0:0]$2631 - attribute \src "issuer_ls180.v:45242.3-45250.6" - wire $1\wr_pick_dly$986$next[0:0]$2635 - attribute \src "issuer_ls180.v:45195.3-45203.6" - wire $1\wr_pick_dly$next[0:0]$2628 - attribute \src "issuer_ls180.v:40278.7-40278.25" - wire $1\wr_pick_dly[0:0] - attribute \src "issuer_ls180.v:44577.3-44597.6" - wire $2\core_terminate_o$next[0:0]$2514 - attribute \src "issuer_ls180.v:44448.3-44538.6" - wire $2\corebusy_o[0:0] - attribute \src "issuer_ls180.v:44393.3-44419.6" - wire width 2 $2\counter$next[1:0]$2488 - attribute \src "issuer_ls180.v:46399.3-46427.6" - wire $2\fus_cu_issue_i$10[0:0]$2786 - attribute \src "issuer_ls180.v:46895.3-46923.6" - wire $2\fus_cu_issue_i$13[0:0]$2811 - attribute \src "issuer_ls180.v:42280.3-42308.6" - wire $2\fus_cu_issue_i$16[0:0]$2280 - attribute \src "issuer_ls180.v:42776.3-42804.6" - wire $2\fus_cu_issue_i$19[0:0]$2305 - attribute \src "issuer_ls180.v:43098.3-43126.6" - wire $2\fus_cu_issue_i$22[0:0]$2324 - attribute \src "issuer_ls180.v:43536.3-43564.6" - wire $2\fus_cu_issue_i$25[0:0]$2347 - attribute \src "issuer_ls180.v:43974.3-44002.6" - wire $2\fus_cu_issue_i$28[0:0]$2370 - attribute \src "issuer_ls180.v:45667.3-45695.6" - wire $2\fus_cu_issue_i$4[0:0]$2691 - attribute \src "issuer_ls180.v:46064.3-46092.6" - wire $2\fus_cu_issue_i$7[0:0]$2753 - attribute \src "issuer_ls180.v:45459.3-45487.6" - wire $2\fus_cu_issue_i[0:0] - attribute \src "issuer_ls180.v:46428.3-46456.6" - wire width 4 $2\fus_cu_rdmaskn_i$12[3:0]$2791 - attribute \src "issuer_ls180.v:46924.3-46952.6" - wire width 3 $2\fus_cu_rdmaskn_i$15[2:0]$2816 - attribute \src "issuer_ls180.v:42309.3-42337.6" - wire width 6 $2\fus_cu_rdmaskn_i$18[5:0]$2285 - attribute \src "issuer_ls180.v:42805.3-42833.6" - wire width 3 $2\fus_cu_rdmaskn_i$21[2:0]$2310 - attribute \src "issuer_ls180.v:43127.3-43155.6" - wire width 3 $2\fus_cu_rdmaskn_i$24[2:0]$2329 - attribute \src "issuer_ls180.v:43565.3-43593.6" - wire width 5 $2\fus_cu_rdmaskn_i$27[4:0]$2352 - attribute \src "issuer_ls180.v:44003.3-44031.6" - wire width 3 $2\fus_cu_rdmaskn_i$30[2:0]$2375 - attribute \src "issuer_ls180.v:45714.3-45742.6" - wire width 6 $2\fus_cu_rdmaskn_i$6[5:0]$2702 - attribute \src "issuer_ls180.v:46102.3-46130.6" - wire width 3 $2\fus_cu_rdmaskn_i$9[2:0]$2761 - attribute \src "issuer_ls180.v:45497.3-45525.6" - wire width 4 $2\fus_cu_rdmaskn_i[3:0] - attribute \src "issuer_ls180.v:45374.3-45402.6" - wire width 4 $2\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "issuer_ls180.v:44694.3-44722.6" - wire width 12 $2\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "issuer_ls180.v:44761.3-44790.6" - wire width 64 $2\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "issuer_ls180.v:44761.3-44790.6" - wire $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:45213.3-45241.6" - wire width 2 $2\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "issuer_ls180.v:45421.3-45449.6" - wire width 32 $2\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "issuer_ls180.v:44636.3-44664.6" - wire width 7 $2\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "issuer_ls180.v:45003.3-45031.6" - wire $2\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "issuer_ls180.v:45118.3-45146.6" - wire $2\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "issuer_ls180.v:45298.3-45326.6" - wire $2\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "issuer_ls180.v:45336.3-45364.6" - wire $2\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "issuer_ls180.v:44916.3-44945.6" - wire $2\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "issuer_ls180.v:44916.3-44945.6" - wire $2\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "issuer_ls180.v:45251.3-45279.6" - wire $2\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "issuer_ls180.v:44829.3-44858.6" - wire $2\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "issuer_ls180.v:44829.3-44858.6" - wire $2\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "issuer_ls180.v:45166.3-45194.6" - wire $2\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "issuer_ls180.v:45060.3-45088.6" - wire $2\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "issuer_ls180.v:45752.3-45780.6" - wire width 64 $2\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "issuer_ls180.v:45837.3-45865.6" - wire width 12 $2\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "issuer_ls180.v:45922.3-45951.6" - wire width 64 $2\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "issuer_ls180.v:45922.3-45951.6" - wire $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:45875.3-45903.6" - wire width 32 $2\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "issuer_ls180.v:45799.3-45827.6" - wire width 7 $2\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "issuer_ls180.v:46017.3-46045.6" - wire $2\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "issuer_ls180.v:45979.3-46007.6" - wire $2\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "issuer_ls180.v:45582.3-45610.6" - wire width 12 $2\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "issuer_ls180.v:45629.3-45657.6" - wire width 32 $2\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "issuer_ls180.v:45544.3-45572.6" - wire width 7 $2\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "issuer_ls180.v:42718.3-42746.6" - wire width 4 $2\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "issuer_ls180.v:42367.3-42395.6" - wire width 12 $2\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "issuer_ls180.v:42396.3-42425.6" - wire width 64 $2\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "issuer_ls180.v:42396.3-42425.6" - wire $2\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:42544.3-42572.6" - wire width 2 $2\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "issuer_ls180.v:42747.3-42775.6" - wire width 32 $2\fus_oper_i_alu_div0__insn[31:0] - attribute \src "issuer_ls180.v:42338.3-42366.6" - wire width 7 $2\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "issuer_ls180.v:42486.3-42514.6" - wire $2\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "issuer_ls180.v:42573.3-42601.6" - wire $2\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "issuer_ls180.v:42660.3-42688.6" - wire $2\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "issuer_ls180.v:42689.3-42717.6" - wire $2\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "issuer_ls180.v:42456.3-42485.6" - wire $2\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "issuer_ls180.v:42456.3-42485.6" - wire $2\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "issuer_ls180.v:42631.3-42659.6" - wire $2\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "issuer_ls180.v:42426.3-42455.6" - wire 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attribute \src "issuer_ls180.v:46254.3-46282.6" - wire width 64 $2\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "issuer_ls180.v:46370.3-46398.6" - wire width 13 $2\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "issuer_ls180.v:46341.3-46369.6" - wire width 7 $2\fus_oper_i_alu_trap0__traptype[6:0] - attribute \src "issuer_ls180.v:43858.3-43886.6" - wire $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "issuer_ls180.v:43829.3-43857.6" - wire width 4 $2\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "issuer_ls180.v:43623.3-43651.6" - wire width 12 $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "issuer_ls180.v:43652.3-43681.6" - wire width 64 $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "issuer_ls180.v:43652.3-43681.6" - wire $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:43945.3-43973.6" - wire width 32 $2\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "issuer_ls180.v:43594.3-43622.6" - wire width 7 $2\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "issuer_ls180.v:43771.3-43799.6" - wire $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "issuer_ls180.v:43800.3-43828.6" - wire $2\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "issuer_ls180.v:43916.3-43944.6" - wire width 2 $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "issuer_ls180.v:43741.3-43770.6" - wire $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "issuer_ls180.v:43741.3-43770.6" - wire $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "issuer_ls180.v:43711.3-43740.6" - wire $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "issuer_ls180.v:43711.3-43740.6" - wire $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "issuer_ls180.v:43887.3-43915.6" - wire $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "issuer_ls180.v:43682.3-43710.6" - wire $2\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "issuer_ls180.v:44577.3-44597.6" - wire $3\core_terminate_o$next[0:0]$2515 - attribute \src "issuer_ls180.v:44448.3-44538.6" - wire $3\corebusy_o[0:0] - attribute \src "issuer_ls180.v:44393.3-44419.6" - wire width 2 $3\counter$next[1:0]$2489 - attribute \src "issuer_ls180.v:46399.3-46427.6" - wire $3\fus_cu_issue_i$10[0:0]$2787 - attribute \src "issuer_ls180.v:46895.3-46923.6" - wire $3\fus_cu_issue_i$13[0:0]$2812 - attribute \src "issuer_ls180.v:42280.3-42308.6" - wire $3\fus_cu_issue_i$16[0:0]$2281 - attribute \src "issuer_ls180.v:42776.3-42804.6" - wire $3\fus_cu_issue_i$19[0:0]$2306 - attribute \src "issuer_ls180.v:43098.3-43126.6" - wire $3\fus_cu_issue_i$22[0:0]$2325 - attribute \src "issuer_ls180.v:43536.3-43564.6" - wire $3\fus_cu_issue_i$25[0:0]$2348 - attribute \src "issuer_ls180.v:43974.3-44002.6" - wire $3\fus_cu_issue_i$28[0:0]$2371 - attribute \src "issuer_ls180.v:45667.3-45695.6" - wire $3\fus_cu_issue_i$4[0:0]$2692 - attribute \src "issuer_ls180.v:46064.3-46092.6" - wire $3\fus_cu_issue_i$7[0:0]$2754 - attribute \src "issuer_ls180.v:45459.3-45487.6" - wire $3\fus_cu_issue_i[0:0] - attribute \src "issuer_ls180.v:46428.3-46456.6" - wire width 4 $3\fus_cu_rdmaskn_i$12[3:0]$2792 - attribute \src "issuer_ls180.v:46924.3-46952.6" - wire width 3 $3\fus_cu_rdmaskn_i$15[2:0]$2817 - attribute \src "issuer_ls180.v:42309.3-42337.6" - wire width 6 $3\fus_cu_rdmaskn_i$18[5:0]$2286 - attribute \src "issuer_ls180.v:42805.3-42833.6" - wire width 3 $3\fus_cu_rdmaskn_i$21[2:0]$2311 - attribute \src "issuer_ls180.v:43127.3-43155.6" - wire width 3 $3\fus_cu_rdmaskn_i$24[2:0]$2330 - attribute \src "issuer_ls180.v:43565.3-43593.6" - wire width 5 $3\fus_cu_rdmaskn_i$27[4:0]$2353 - attribute \src "issuer_ls180.v:44003.3-44031.6" - wire width 3 $3\fus_cu_rdmaskn_i$30[2:0]$2376 - attribute \src "issuer_ls180.v:45714.3-45742.6" - wire width 6 $3\fus_cu_rdmaskn_i$6[5:0]$2703 - attribute \src "issuer_ls180.v:46102.3-46130.6" - wire width 3 $3\fus_cu_rdmaskn_i$9[2:0]$2762 - attribute \src "issuer_ls180.v:45497.3-45525.6" - wire width 4 $3\fus_cu_rdmaskn_i[3:0] - attribute \src "issuer_ls180.v:45374.3-45402.6" - wire width 4 $3\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "issuer_ls180.v:44694.3-44722.6" - wire width 12 $3\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "issuer_ls180.v:44761.3-44790.6" - wire width 64 $3\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "issuer_ls180.v:44761.3-44790.6" - wire $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:45213.3-45241.6" - wire width 2 $3\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "issuer_ls180.v:45421.3-45449.6" - wire width 32 $3\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "issuer_ls180.v:44636.3-44664.6" - wire width 7 $3\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "issuer_ls180.v:45003.3-45031.6" - wire $3\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "issuer_ls180.v:45118.3-45146.6" - wire $3\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "issuer_ls180.v:45298.3-45326.6" - wire $3\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "issuer_ls180.v:45336.3-45364.6" - wire $3\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "issuer_ls180.v:44916.3-44945.6" - wire $3\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "issuer_ls180.v:44916.3-44945.6" - wire $3\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "issuer_ls180.v:45251.3-45279.6" - wire $3\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "issuer_ls180.v:44829.3-44858.6" - wire $3\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "issuer_ls180.v:44829.3-44858.6" - wire $3\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "issuer_ls180.v:45166.3-45194.6" - wire $3\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "issuer_ls180.v:45060.3-45088.6" - wire $3\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "issuer_ls180.v:45752.3-45780.6" - wire width 64 $3\fus_oper_i_alu_branch0__cia[63:0] - attribute \src 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attribute \src "issuer_ls180.v:41239.19-41239.130" - wire $eq$issuer_ls180.v:41239$2017_Y - attribute \src "issuer_ls180.v:41241.19-41241.115" - wire $eq$issuer_ls180.v:41241$2019_Y - attribute \src "issuer_ls180.v:41266.19-41266.115" - wire $eq$issuer_ls180.v:41266$2045_Y - attribute \src "issuer_ls180.v:40823.20-40823.95" - wire width 3 $extend$issuer_ls180.v:40823$1595_Y - attribute \src "issuer_ls180.v:40889.20-40889.95" - wire width 2 $extend$issuer_ls180.v:40889$1662_Y - attribute \src "issuer_ls180.v:40893.20-40893.95" - wire width 3 $extend$issuer_ls180.v:40893$1667_Y - attribute \src "issuer_ls180.v:40965.20-40965.95" - wire width 4 $extend$issuer_ls180.v:40965$1740_Y - attribute \src "issuer_ls180.v:40973.20-40973.104" - wire width 4 $extend$issuer_ls180.v:40973$1749_Y - attribute \src "issuer_ls180.v:41238.19-41238.93" - wire width 3 $extend$issuer_ls180.v:41238$2015_Y - attribute \src "issuer_ls180.v:41263.19-41263.93" - wire width 3 $extend$issuer_ls180.v:41263$2041_Y - attribute \src "issuer_ls180.v:40993.19-40993.103" - wire $ne$issuer_ls180.v:40993$1770_Y - attribute \src "issuer_ls180.v:40995.19-40995.103" - wire $ne$issuer_ls180.v:40995$1772_Y - attribute \src "issuer_ls180.v:40660.20-40660.106" - wire $not$issuer_ls180.v:40660$1432_Y - attribute \src "issuer_ls180.v:40666.20-40666.106" - wire $not$issuer_ls180.v:40666$1438_Y - attribute \src "issuer_ls180.v:40672.20-40672.106" - wire $not$issuer_ls180.v:40672$1444_Y - attribute \src "issuer_ls180.v:40678.20-40678.106" - wire $not$issuer_ls180.v:40678$1450_Y - attribute \src "issuer_ls180.v:40684.20-40684.106" - wire $not$issuer_ls180.v:40684$1456_Y - attribute \src "issuer_ls180.v:40690.20-40690.106" - wire $not$issuer_ls180.v:40690$1462_Y - attribute \src "issuer_ls180.v:40696.20-40696.106" - wire $not$issuer_ls180.v:40696$1468_Y - attribute \src "issuer_ls180.v:40730.20-40730.106" - wire $not$issuer_ls180.v:40730$1502_Y - attribute \src "issuer_ls180.v:40742.20-40742.106" - wire $not$issuer_ls180.v:40742$1514_Y - attribute \src "issuer_ls180.v:40750.20-40750.106" - wire $not$issuer_ls180.v:40750$1522_Y - attribute \src "issuer_ls180.v:40758.20-40758.106" - wire $not$issuer_ls180.v:40758$1530_Y - attribute \src "issuer_ls180.v:40766.20-40766.106" - wire $not$issuer_ls180.v:40766$1538_Y - attribute \src "issuer_ls180.v:40774.20-40774.106" - wire $not$issuer_ls180.v:40774$1546_Y - attribute \src "issuer_ls180.v:40782.20-40782.106" - wire $not$issuer_ls180.v:40782$1554_Y - attribute \src "issuer_ls180.v:40803.20-40803.106" - wire $not$issuer_ls180.v:40803$1575_Y - attribute \src "issuer_ls180.v:40809.20-40809.106" - wire $not$issuer_ls180.v:40809$1581_Y - attribute \src "issuer_ls180.v:40815.20-40815.106" - wire $not$issuer_ls180.v:40815$1587_Y - attribute \src "issuer_ls180.v:40830.20-40830.106" - wire $not$issuer_ls180.v:40830$1603_Y - attribute \src "issuer_ls180.v:40836.20-40836.106" - wire $not$issuer_ls180.v:40836$1609_Y - attribute \src "issuer_ls180.v:40842.20-40842.106" - wire $not$issuer_ls180.v:40842$1615_Y - attribute \src "issuer_ls180.v:40848.20-40848.106" - wire $not$issuer_ls180.v:40848$1621_Y - attribute \src "issuer_ls180.v:40864.20-40864.106" - wire $not$issuer_ls180.v:40864$1637_Y - attribute \src "issuer_ls180.v:40870.20-40870.106" - wire $not$issuer_ls180.v:40870$1643_Y - attribute \src "issuer_ls180.v:40876.20-40876.106" - wire $not$issuer_ls180.v:40876$1649_Y - attribute \src "issuer_ls180.v:40882.20-40882.106" - wire $not$issuer_ls180.v:40882$1655_Y - attribute \src "issuer_ls180.v:40901.20-40901.106" - wire $not$issuer_ls180.v:40901$1676_Y - attribute \src "issuer_ls180.v:40909.20-40909.106" - wire $not$issuer_ls180.v:40909$1684_Y - attribute \src "issuer_ls180.v:40915.20-40915.106" - wire $not$issuer_ls180.v:40915$1690_Y - attribute \src "issuer_ls180.v:40922.20-40922.106" - wire $not$issuer_ls180.v:40922$1697_Y - attribute \src "issuer_ls180.v:40929.20-40929.106" - wire $not$issuer_ls180.v:40929$1704_Y - attribute \src "issuer_ls180.v:40951.20-40951.106" - wire $not$issuer_ls180.v:40951$1726_Y - attribute \src "issuer_ls180.v:40958.20-40958.106" - wire $not$issuer_ls180.v:40958$1733_Y - attribute \src "issuer_ls180.v:40969.20-40969.106" - wire $not$issuer_ls180.v:40969$1745_Y - attribute \src "issuer_ls180.v:40978.20-40978.106" - wire $not$issuer_ls180.v:40978$1755_Y - attribute \src "issuer_ls180.v:41006.19-41006.136" - wire width 4 $not$issuer_ls180.v:41006$1783_Y - attribute \src "issuer_ls180.v:41007.19-41007.192" - wire width 6 $not$issuer_ls180.v:41007$1784_Y - attribute \src "issuer_ls180.v:41008.19-41008.138" - wire width 3 $not$issuer_ls180.v:41008$1785_Y - attribute \src "issuer_ls180.v:41009.19-41009.150" - wire width 4 $not$issuer_ls180.v:41009$1786_Y - attribute \src "issuer_ls180.v:41016.19-41016.128" - wire width 3 $not$issuer_ls180.v:41016$1793_Y - attribute \src "issuer_ls180.v:41031.19-41031.159" - wire width 6 $not$issuer_ls180.v:41031$1808_Y - attribute \src "issuer_ls180.v:41038.19-41038.128" - wire width 3 $not$issuer_ls180.v:41038$1815_Y - attribute \src "issuer_ls180.v:41045.19-41045.128" - wire width 3 $not$issuer_ls180.v:41045$1822_Y - attribute \src "issuer_ls180.v:41056.19-41056.150" - wire width 5 $not$issuer_ls180.v:41056$1833_Y - attribute \src "issuer_ls180.v:41057.19-41057.134" - wire width 3 $not$issuer_ls180.v:41057$1834_Y - attribute \src "issuer_ls180.v:41060.19-41060.106" - wire $not$issuer_ls180.v:41060$1837_Y - attribute \src "issuer_ls180.v:41066.19-41066.105" - wire $not$issuer_ls180.v:41066$1843_Y - attribute \src "issuer_ls180.v:41072.19-41072.107" - wire $not$issuer_ls180.v:41072$1849_Y - attribute \src "issuer_ls180.v:41078.19-41078.110" - wire $not$issuer_ls180.v:41078$1855_Y - attribute \src "issuer_ls180.v:41084.19-41084.106" - wire $not$issuer_ls180.v:41084$1861_Y - attribute \src "issuer_ls180.v:41090.19-41090.106" - wire $not$issuer_ls180.v:41090$1867_Y - attribute \src "issuer_ls180.v:41096.19-41096.106" - wire $not$issuer_ls180.v:41096$1873_Y - attribute \src "issuer_ls180.v:41102.19-41102.111" - wire $not$issuer_ls180.v:41102$1879_Y - attribute \src "issuer_ls180.v:41108.19-41108.107" - wire $not$issuer_ls180.v:41108$1885_Y - attribute \src "issuer_ls180.v:41123.19-41123.106" - wire $not$issuer_ls180.v:41123$1900_Y - attribute \src "issuer_ls180.v:41129.19-41129.105" - wire $not$issuer_ls180.v:41129$1906_Y - attribute \src "issuer_ls180.v:41135.19-41135.107" - wire $not$issuer_ls180.v:41135$1912_Y - attribute \src "issuer_ls180.v:41141.19-41141.110" - wire $not$issuer_ls180.v:41141$1918_Y - attribute \src "issuer_ls180.v:41147.19-41147.106" - wire $not$issuer_ls180.v:41147$1924_Y - attribute \src "issuer_ls180.v:41153.19-41153.106" - wire $not$issuer_ls180.v:41153$1930_Y - attribute \src "issuer_ls180.v:41159.19-41159.111" - wire $not$issuer_ls180.v:41159$1936_Y - attribute \src "issuer_ls180.v:41165.19-41165.107" - wire $not$issuer_ls180.v:41165$1942_Y - attribute \src "issuer_ls180.v:41179.19-41179.111" - wire $not$issuer_ls180.v:41179$1956_Y - attribute \src "issuer_ls180.v:41185.19-41185.107" - wire $not$issuer_ls180.v:41185$1962_Y - attribute \src "issuer_ls180.v:41199.19-41199.110" - wire $not$issuer_ls180.v:41199$1976_Y - attribute \src "issuer_ls180.v:41205.19-41205.114" - wire $not$issuer_ls180.v:41205$1982_Y - attribute \src "issuer_ls180.v:41211.19-41211.110" - wire $not$issuer_ls180.v:41211$1988_Y - attribute \src "issuer_ls180.v:41217.19-41217.110" - wire $not$issuer_ls180.v:41217$1994_Y - attribute \src "issuer_ls180.v:41223.19-41223.110" - wire $not$issuer_ls180.v:41223$2000_Y - attribute \src "issuer_ls180.v:41229.19-41229.115" - wire $not$issuer_ls180.v:41229$2006_Y - attribute \src "issuer_ls180.v:41245.19-41245.110" - wire $not$issuer_ls180.v:41245$2023_Y - attribute \src "issuer_ls180.v:41251.19-41251.110" - wire $not$issuer_ls180.v:41251$2029_Y - attribute \src "issuer_ls180.v:41257.19-41257.115" - wire $not$issuer_ls180.v:41257$2035_Y - attribute \src "issuer_ls180.v:41270.19-41270.110" - wire $not$issuer_ls180.v:41270$2049_Y - attribute \src "issuer_ls180.v:41276.19-41276.109" - wire $not$issuer_ls180.v:41276$2055_Y - attribute \src "issuer_ls180.v:41282.19-41282.106" - wire $not$issuer_ls180.v:41282$2061_Y - attribute \src "issuer_ls180.v:41290.19-41290.110" - wire $not$issuer_ls180.v:41290$2069_Y - attribute \src "issuer_ls180.v:41299.19-41299.106" - wire $not$issuer_ls180.v:41299$2078_Y - attribute \src "issuer_ls180.v:41307.19-41307.106" - wire $not$issuer_ls180.v:41307$2086_Y - attribute \src "issuer_ls180.v:41315.19-41315.113" - wire $not$issuer_ls180.v:41315$2094_Y - attribute \src "issuer_ls180.v:41321.19-41321.111" - wire $not$issuer_ls180.v:41321$2100_Y - attribute \src "issuer_ls180.v:41327.19-41327.110" - wire $not$issuer_ls180.v:41327$2106_Y - attribute \src "issuer_ls180.v:41336.19-41336.113" - wire $not$issuer_ls180.v:41336$2115_Y - attribute \src "issuer_ls180.v:41342.19-41342.111" - wire $not$issuer_ls180.v:41342$2121_Y - attribute \src "issuer_ls180.v:41350.19-41350.108" - wire $not$issuer_ls180.v:41350$2129_Y - attribute \src "issuer_ls180.v:41367.19-41367.99" - wire $not$issuer_ls180.v:41367$2146_Y - attribute \src "issuer_ls180.v:41373.19-41373.104" - wire $not$issuer_ls180.v:41373$2152_Y - attribute \src "issuer_ls180.v:41379.19-41379.104" - wire $not$issuer_ls180.v:41379$2158_Y - attribute \src "issuer_ls180.v:40700.20-40700.117" - wire width 64 $or$issuer_ls180.v:40700$1472_Y - attribute \src "issuer_ls180.v:40701.20-40701.123" - wire width 64 $or$issuer_ls180.v:40701$1473_Y - attribute \src "issuer_ls180.v:40702.20-40702.113" - wire width 64 $or$issuer_ls180.v:40702$1474_Y - attribute \src "issuer_ls180.v:40703.20-40703.103" - wire width 64 $or$issuer_ls180.v:40703$1475_Y - attribute \src "issuer_ls180.v:40704.20-40704.123" - wire width 64 $or$issuer_ls180.v:40704$1476_Y - attribute \src "issuer_ls180.v:40705.20-40705.122" - wire width 65 $or$issuer_ls180.v:40705$1477_Y - attribute \src "issuer_ls180.v:40706.20-40706.113" - wire width 65 $or$issuer_ls180.v:40706$1478_Y - attribute \src "issuer_ls180.v:40707.20-40707.103" - wire width 65 $or$issuer_ls180.v:40707$1479_Y - attribute \src "issuer_ls180.v:40708.20-40708.103" - wire width 65 $or$issuer_ls180.v:40708$1480_Y - attribute \src "issuer_ls180.v:40709.20-40709.109" - wire width 5 $or$issuer_ls180.v:40709$1481_Y - attribute \src "issuer_ls180.v:40710.20-40710.117" - wire width 5 $or$issuer_ls180.v:40710$1482_Y - attribute \src "issuer_ls180.v:40711.20-40711.109" - wire width 5 $or$issuer_ls180.v:40711$1483_Y - attribute \src "issuer_ls180.v:40712.20-40712.103" - wire width 5 $or$issuer_ls180.v:40712$1484_Y - attribute \src "issuer_ls180.v:40713.20-40713.117" - wire width 5 $or$issuer_ls180.v:40713$1485_Y - attribute \src "issuer_ls180.v:40714.20-40714.117" - wire width 5 $or$issuer_ls180.v:40714$1486_Y - attribute \src "issuer_ls180.v:40715.20-40715.110" - wire width 5 $or$issuer_ls180.v:40715$1487_Y - attribute \src "issuer_ls180.v:40716.20-40716.103" - wire width 5 $or$issuer_ls180.v:40716$1488_Y - attribute \src "issuer_ls180.v:40717.20-40717.103" - wire width 5 $or$issuer_ls180.v:40717$1489_Y - attribute \src "issuer_ls180.v:40718.20-40718.99" - wire $or$issuer_ls180.v:40718$1490_Y - attribute \src "issuer_ls180.v:40719.20-40719.107" - wire $or$issuer_ls180.v:40719$1491_Y - attribute \src "issuer_ls180.v:40720.20-40720.104" - wire $or$issuer_ls180.v:40720$1492_Y - attribute \src "issuer_ls180.v:40721.20-40721.103" - wire $or$issuer_ls180.v:40721$1493_Y - attribute \src "issuer_ls180.v:40722.20-40722.107" - wire $or$issuer_ls180.v:40722$1494_Y - attribute \src "issuer_ls180.v:40723.20-40723.107" - wire $or$issuer_ls180.v:40723$1495_Y - attribute \src "issuer_ls180.v:40724.20-40724.105" - wire $or$issuer_ls180.v:40724$1496_Y - attribute \src "issuer_ls180.v:40725.20-40725.103" - wire $or$issuer_ls180.v:40725$1497_Y - attribute \src "issuer_ls180.v:40726.20-40726.103" - wire $or$issuer_ls180.v:40726$1498_Y - attribute \src "issuer_ls180.v:40788.20-40788.117" - wire width 4 $or$issuer_ls180.v:40788$1560_Y - attribute \src "issuer_ls180.v:40789.20-40789.113" - wire width 4 $or$issuer_ls180.v:40789$1561_Y - attribute \src "issuer_ls180.v:40790.20-40790.123" - wire width 4 $or$issuer_ls180.v:40790$1562_Y - attribute \src "issuer_ls180.v:40791.20-40791.113" - wire width 4 $or$issuer_ls180.v:40791$1563_Y - attribute \src "issuer_ls180.v:40792.20-40792.103" - wire width 4 $or$issuer_ls180.v:40792$1564_Y - attribute \src "issuer_ls180.v:40793.20-40793.117" - wire width 16 $or$issuer_ls180.v:40793$1565_Y - attribute \src "issuer_ls180.v:40794.20-40794.110" - wire width 16 $or$issuer_ls180.v:40794$1566_Y - attribute \src "issuer_ls180.v:40795.20-40795.117" - wire width 16 $or$issuer_ls180.v:40795$1567_Y - attribute \src "issuer_ls180.v:40796.20-40796.110" - wire width 16 $or$issuer_ls180.v:40796$1568_Y - attribute \src "issuer_ls180.v:40797.20-40797.103" - wire width 16 $or$issuer_ls180.v:40797$1569_Y - attribute \src "issuer_ls180.v:40819.20-40819.117" - wire width 2 $or$issuer_ls180.v:40819$1591_Y - attribute \src "issuer_ls180.v:40820.20-40820.113" - wire width 2 $or$issuer_ls180.v:40820$1592_Y - attribute \src "issuer_ls180.v:40821.20-40821.117" - wire width 2 $or$issuer_ls180.v:40821$1593_Y - attribute \src "issuer_ls180.v:40822.20-40822.110" - wire width 2 $or$issuer_ls180.v:40822$1594_Y - attribute \src "issuer_ls180.v:40852.20-40852.112" - wire width 2 $or$issuer_ls180.v:40852$1625_Y - attribute \src "issuer_ls180.v:40853.20-40853.123" - wire width 2 $or$issuer_ls180.v:40853$1626_Y - attribute \src "issuer_ls180.v:40854.20-40854.103" - wire width 2 $or$issuer_ls180.v:40854$1627_Y - attribute \src "issuer_ls180.v:40855.20-40855.117" - wire width 3 $or$issuer_ls180.v:40855$1628_Y - attribute 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$or$issuer_ls180.v:41115$1892_Y - attribute \src "issuer_ls180.v:41116.19-41116.137" - wire width 5 $or$issuer_ls180.v:41116$1893_Y - attribute \src "issuer_ls180.v:41117.19-41117.115" - wire width 5 $or$issuer_ls180.v:41117$1894_Y - attribute \src "issuer_ls180.v:41118.19-41118.100" - wire width 5 $or$issuer_ls180.v:41118$1895_Y - attribute \src "issuer_ls180.v:41119.19-41119.100" - wire width 5 $or$issuer_ls180.v:41119$1896_Y - attribute \src "issuer_ls180.v:41169.19-41169.130" - wire width 5 $or$issuer_ls180.v:41169$1946_Y - attribute \src "issuer_ls180.v:41170.19-41170.136" - wire width 5 $or$issuer_ls180.v:41170$1947_Y - attribute \src "issuer_ls180.v:41171.19-41171.100" - wire width 5 $or$issuer_ls180.v:41171$1948_Y - attribute \src "issuer_ls180.v:41172.19-41172.131" - wire width 5 $or$issuer_ls180.v:41172$1949_Y - attribute \src "issuer_ls180.v:41173.19-41173.137" - wire width 5 $or$issuer_ls180.v:41173$1950_Y - attribute \src "issuer_ls180.v:41174.19-41174.100" - wire width 5 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\addr_en_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 10 \addr_en_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 2 \addr_en_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 2 \addr_en_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 2 \addr_en_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 3 \addr_en_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire \addr_en_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire \addr_en_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire \addr_en_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire \addr_en_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire \addr_en_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire \addr_en_XER_xer_so_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:88" - wire input 55 \bigendian_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 8 \cia__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 7 \cia__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" - wire width 64 input 39 \core_core_cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 input 50 \core_core_cr_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 51 \core_core_cr_rd_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 input 52 \core_core_cr_wr + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0] + end + attribute \src "libresoc.v:23942.3-24044.6" + process $proc$libresoc.v:23942$463 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_out_sel[1:0] $1\dec31_dec_sub15_out_sel[1:0] + attribute \src "libresoc.v:23943.5-23943.29" + switch \initial + attribute \src "libresoc.v:23943.9-23943.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub15_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_out_sel $0\dec31_dec_sub15_out_sel[1:0] + end + attribute \src "libresoc.v:24045.3-24147.6" + process $proc$libresoc.v:24045$464 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:24046.5-24046.29" + switch \initial + attribute \src "libresoc.v:24046.9-24046.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + case + assign $1\dec31_dec_sub15_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0] + end + attribute \src "libresoc.v:24148.3-24250.6" + process $proc$libresoc.v:24148$465 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:24149.5-24149.29" + switch \initial + attribute \src "libresoc.v:24149.9-24149.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:24256.1-24755.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub16" +attribute \generator "nMigen" +module \dec31_dec_sub16 + attribute \src "libresoc.v:24564.3-24573.6" + wire width 8 $0\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:24604.3-24613.6" + wire $0\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:24734.3-24743.6" + wire width 3 $0\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:24744.3-24753.6" + wire width 3 $0\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:24554.3-24563.6" + wire width 2 $0\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:24594.3-24603.6" + wire $0\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:24684.3-24693.6" + wire width 5 $0\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:24514.3-24523.6" + wire width 12 $0\dec31_dec_sub16_function_unit[11:0] + attribute \src "libresoc.v:24694.3-24703.6" + wire width 3 $0\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:24704.3-24713.6" + wire width 4 $0\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:24714.3-24723.6" + wire width 2 $0\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:24624.3-24633.6" + wire width 7 $0\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:24574.3-24583.6" + wire $0\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:24584.3-24593.6" + wire $0\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:24644.3-24653.6" + wire $0\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:24524.3-24533.6" + wire width 4 $0\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:24664.3-24673.6" + wire $0\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:24724.3-24733.6" + wire width 2 $0\dec31_dec_sub16_out_sel[1:0] + attribute \src "libresoc.v:24544.3-24553.6" + wire width 2 $0\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:24634.3-24643.6" + wire $0\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:24674.3-24683.6" + wire $0\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:24654.3-24663.6" + wire $0\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:24614.3-24623.6" + wire $0\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:24534.3-24543.6" + wire width 2 $0\dec31_dec_sub16_upd[1:0] + attribute \src "libresoc.v:24257.7-24257.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:24564.3-24573.6" + wire width 8 $1\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:24604.3-24613.6" + wire $1\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:24734.3-24743.6" + wire width 3 $1\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:24744.3-24753.6" + wire width 3 $1\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:24554.3-24563.6" + wire width 2 $1\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:24594.3-24603.6" + wire $1\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:24684.3-24693.6" + wire width 5 $1\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:24514.3-24523.6" + wire width 12 $1\dec31_dec_sub16_function_unit[11:0] + attribute \src "libresoc.v:24694.3-24703.6" + wire width 3 $1\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:24704.3-24713.6" + wire width 4 $1\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:24714.3-24723.6" + wire width 2 $1\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:24624.3-24633.6" + wire width 7 $1\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:24574.3-24583.6" + wire $1\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:24584.3-24593.6" + wire $1\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:24644.3-24653.6" + wire $1\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:24524.3-24533.6" + wire width 4 $1\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:24664.3-24673.6" + wire $1\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:24724.3-24733.6" + wire width 2 $1\dec31_dec_sub16_out_sel[1:0] + attribute \src "libresoc.v:24544.3-24553.6" + wire width 2 $1\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:24634.3-24643.6" + wire $1\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:24674.3-24683.6" + wire $1\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:24654.3-24663.6" + wire $1\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:24614.3-24623.6" + wire $1\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:24534.3-24543.6" + wire width 2 $1\dec31_dec_sub16_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub16_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub16_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub16_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub16_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub16_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub16_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub16_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -59950,16 +34293,39 @@ module \core attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" - wire width 12 input 42 \core_core_fn_unit - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" - wire width 2 input 47 \core_core_input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" - wire width 32 input 40 \core_core_insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub16_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub16_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub16_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub16_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -60034,836 +34400,785 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" - wire width 7 input 41 \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" - wire input 53 \core_core_is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" - wire width 64 input 38 \core_core_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 45 \core_core_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 46 \core_core_oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 43 \core_core_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 44 \core_core_rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 13 input 49 \core_core_trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 7 input 48 \core_core_traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 input 31 \core_cr_in1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 32 \core_cr_in1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 input 33 \core_cr_in2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 input 35 \core_cr_in2$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 34 \core_cr_in2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 36 \core_cr_in2_ok$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 input 37 \core_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 input 14 \core_ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 input 25 \core_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 26 \core_fast1_ok - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dec_BRANCH_BRANCH_BRANCH__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_BRANCH_BRANCH_BRANCH__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_BRANCH_BRANCH_BRANCH__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire \dec_BRANCH_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 \dec_BRANCH_raw_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_CR_CR_CR__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_CR_CR_CR__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 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attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_CR_CR_CR__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire \dec_CR_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 \dec_CR_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \dec_DIV_DIV_DIV__data_len - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_DIV_DIV_DIV__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dec_DIV_DIV_DIV__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_DIV_DIV_DIV__imm_data__ok + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub16_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub16_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub16_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub16_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub16_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub16_upd + attribute \src "libresoc.v:24257.7-24257.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:24257.7-24257.20" + process $proc$libresoc.v:24257$491 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:24514.3-24523.6" + process $proc$libresoc.v:24514$467 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_function_unit[11:0] $1\dec31_dec_sub16_function_unit[11:0] + attribute \src "libresoc.v:24515.5-24515.29" + switch \initial + attribute \src "libresoc.v:24515.9-24515.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_function_unit[11:0] 12'000001000000 + case + assign $1\dec31_dec_sub16_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[11:0] + end + attribute \src "libresoc.v:24524.3-24533.6" + process $proc$libresoc.v:24524$468 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:24525.5-24525.29" + switch \initial + attribute \src "libresoc.v:24525.9-24525.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0] + end + attribute \src "libresoc.v:24534.3-24543.6" + process $proc$libresoc.v:24534$469 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] + attribute \src "libresoc.v:24535.5-24535.29" + switch \initial + attribute \src "libresoc.v:24535.9-24535.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub16_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] + end + attribute \src "libresoc.v:24544.3-24553.6" + process $proc$libresoc.v:24544$470 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:24545.5-24545.29" + switch \initial + attribute \src "libresoc.v:24545.9-24545.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0] + end + attribute \src "libresoc.v:24554.3-24563.6" + process $proc$libresoc.v:24554$471 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:24555.5-24555.29" + switch \initial + attribute \src "libresoc.v:24555.9-24555.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0] + end + attribute \src "libresoc.v:24564.3-24573.6" + process $proc$libresoc.v:24564$472 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:24565.5-24565.29" + switch \initial + attribute \src "libresoc.v:24565.9-24565.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_asmcode[7:0] 8'01110110 + case + assign $1\dec31_dec_sub16_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0] + end + attribute \src "libresoc.v:24574.3-24583.6" + process $proc$libresoc.v:24574$473 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:24575.5-24575.29" + switch \initial + attribute \src "libresoc.v:24575.9-24575.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0] + end + attribute \src "libresoc.v:24584.3-24593.6" + process $proc$libresoc.v:24584$474 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:24585.5-24585.29" + switch \initial + attribute \src "libresoc.v:24585.9-24585.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0] + end + attribute \src "libresoc.v:24594.3-24603.6" + process $proc$libresoc.v:24594$475 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:24595.5-24595.29" + switch \initial + attribute \src "libresoc.v:24595.9-24595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0] + end + attribute \src "libresoc.v:24604.3-24613.6" + process $proc$libresoc.v:24604$476 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:24605.5-24605.29" + switch \initial + attribute \src "libresoc.v:24605.9-24605.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_br[0:0] 1'0 + case + assign $1\dec31_dec_sub16_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0] + end + attribute \src "libresoc.v:24614.3-24623.6" + process $proc$libresoc.v:24614$477 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:24615.5-24615.29" + switch \initial + attribute \src "libresoc.v:24615.9-24615.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0] + end + attribute \src "libresoc.v:24624.3-24633.6" + process $proc$libresoc.v:24624$478 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:24625.5-24625.29" + switch \initial + attribute \src "libresoc.v:24625.9-24625.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_internal_op[6:0] 7'0110000 + case + assign $1\dec31_dec_sub16_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] + end + attribute \src "libresoc.v:24634.3-24643.6" + process $proc$libresoc.v:24634$479 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:24635.5-24635.29" + switch \initial + attribute \src "libresoc.v:24635.9-24635.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0] + end + attribute \src "libresoc.v:24644.3-24653.6" + process $proc$libresoc.v:24644$480 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:24645.5-24645.29" + switch \initial + attribute \src "libresoc.v:24645.9-24645.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] + end + attribute \src "libresoc.v:24654.3-24663.6" + process $proc$libresoc.v:24654$481 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:24655.5-24655.29" + switch \initial + attribute \src "libresoc.v:24655.9-24655.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0] + end + attribute \src "libresoc.v:24664.3-24673.6" + process $proc$libresoc.v:24664$482 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:24665.5-24665.29" + switch \initial + attribute \src "libresoc.v:24665.9-24665.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub16_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0] + end + attribute \src "libresoc.v:24674.3-24683.6" + process $proc$libresoc.v:24674$483 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:24675.5-24675.29" + switch \initial + attribute \src "libresoc.v:24675.9-24675.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0] + end + attribute \src "libresoc.v:24684.3-24693.6" + process $proc$libresoc.v:24684$484 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:24685.5-24685.29" + switch \initial + attribute \src "libresoc.v:24685.9-24685.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_form[4:0] 5'01010 + case + assign $1\dec31_dec_sub16_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] + end + attribute \src "libresoc.v:24694.3-24703.6" + process $proc$libresoc.v:24694$485 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:24695.5-24695.29" + switch \initial + attribute \src "libresoc.v:24695.9-24695.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub16_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0] + end + attribute \src "libresoc.v:24704.3-24713.6" + process $proc$libresoc.v:24704$486 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:24705.5-24705.29" + switch \initial + attribute \src "libresoc.v:24705.9-24705.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0] + end + attribute \src "libresoc.v:24714.3-24723.6" + process $proc$libresoc.v:24714$487 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:24715.5-24715.29" + switch \initial + attribute \src "libresoc.v:24715.9-24715.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0] + end + attribute \src "libresoc.v:24724.3-24733.6" + process $proc$libresoc.v:24724$488 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_out_sel[1:0] $1\dec31_dec_sub16_out_sel[1:0] + attribute \src "libresoc.v:24725.5-24725.29" + switch \initial + attribute \src "libresoc.v:24725.9-24725.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_out_sel $0\dec31_dec_sub16_out_sel[1:0] + end + attribute \src "libresoc.v:24734.3-24743.6" + process $proc$libresoc.v:24734$489 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:24735.5-24735.29" + switch \initial + attribute \src "libresoc.v:24735.9-24735.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cr_in[2:0] 3'110 + case + assign $1\dec31_dec_sub16_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0] + end + attribute \src "libresoc.v:24744.3-24753.6" + process $proc$libresoc.v:24744$490 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:24745.5-24745.29" + switch \initial + attribute \src "libresoc.v:24745.9-24745.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cr_out[2:0] 3'100 + case + assign $1\dec31_dec_sub16_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:24759.1-25546.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub18" +attribute \generator "nMigen" +module \dec31_dec_sub18 + attribute \src "libresoc.v:25127.3-25148.6" + wire width 8 $0\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:25215.3-25236.6" + wire $0\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:25501.3-25522.6" + wire width 3 $0\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:25523.3-25544.6" + wire width 3 $0\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:25105.3-25126.6" + wire width 2 $0\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:25193.3-25214.6" + wire $0\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:25391.3-25412.6" + wire width 5 $0\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:25017.3-25038.6" + wire width 12 $0\dec31_dec_sub18_function_unit[11:0] + attribute \src "libresoc.v:25413.3-25434.6" + wire width 3 $0\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:25435.3-25456.6" + wire width 4 $0\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:25457.3-25478.6" + wire width 2 $0\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:25259.3-25280.6" + wire width 7 $0\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:25149.3-25170.6" + wire $0\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:25171.3-25192.6" + wire $0\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:25303.3-25324.6" + wire $0\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:25039.3-25060.6" + wire width 4 $0\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:25347.3-25368.6" + wire $0\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:25479.3-25500.6" + wire width 2 $0\dec31_dec_sub18_out_sel[1:0] + attribute \src "libresoc.v:25083.3-25104.6" + wire width 2 $0\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:25281.3-25302.6" + wire $0\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:25369.3-25390.6" + wire $0\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:25325.3-25346.6" + wire $0\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:25237.3-25258.6" + wire $0\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:25061.3-25082.6" + wire width 2 $0\dec31_dec_sub18_upd[1:0] + attribute \src "libresoc.v:24760.7-24760.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:25127.3-25148.6" + wire width 8 $1\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:25215.3-25236.6" + wire $1\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:25501.3-25522.6" + wire width 3 $1\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:25523.3-25544.6" + wire width 3 $1\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:25105.3-25126.6" + wire width 2 $1\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:25193.3-25214.6" + wire $1\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:25391.3-25412.6" + wire width 5 $1\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:25017.3-25038.6" + wire width 12 $1\dec31_dec_sub18_function_unit[11:0] + attribute \src "libresoc.v:25413.3-25434.6" + wire width 3 $1\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:25435.3-25456.6" + wire width 4 $1\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:25457.3-25478.6" + wire width 2 $1\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:25259.3-25280.6" + wire width 7 $1\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:25149.3-25170.6" + wire $1\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:25171.3-25192.6" + wire $1\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:25303.3-25324.6" + wire $1\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:25039.3-25060.6" + wire width 4 $1\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:25347.3-25368.6" + wire $1\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:25479.3-25500.6" + wire width 2 $1\dec31_dec_sub18_out_sel[1:0] + attribute \src "libresoc.v:25083.3-25104.6" + wire width 2 $1\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:25281.3-25302.6" + wire $1\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:25369.3-25390.6" + wire $1\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:25325.3-25346.6" + wire $1\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:25237.3-25258.6" + wire $1\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:25061.3-25082.6" + wire width 2 $1\dec31_dec_sub18_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub18_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub18_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub18_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub18_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \dec_DIV_DIV_DIV__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_DIV_DIV_DIV__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_DIV_DIV_DIV__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_DIV_DIV_DIV__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_DIV_DIV_DIV__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_DIV_DIV_DIV__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_DIV_DIV_DIV__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_DIV_DIV_DIV__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_DIV_DIV_DIV__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_DIV_DIV_DIV__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_DIV_DIV_DIV__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_DIV_DIV_DIV__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_DIV_DIV_DIV__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_DIV_DIV_DIV__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire \dec_DIV_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 \dec_DIV_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LDST_LDST_LDST__byte_reverse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \dec_LDST_LDST_LDST__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub18_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub18_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub18_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -60877,14 +35192,39 @@ module \core attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_LDST_LDST_LDST__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dec_LDST_LDST_LDST__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LDST_LDST_LDST__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_LDST_LDST_LDST__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub18_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub18_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub18_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub18_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -60959,166 +35299,1169 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_LDST_LDST_LDST__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LDST_LDST_LDST__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LDST_LDST_LDST__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub18_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub18_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub18_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub18_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub18_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub18_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub18_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub18_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub18_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub18_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub18_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub18_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \dec_LDST_LDST_LDST__ldst_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LDST_LDST_LDST__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LDST_LDST_LDST__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LDST_LDST_LDST__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LDST_LDST_LDST__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LDST_LDST_LDST__sign_extend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LDST_LDST_LDST__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire \dec_LDST_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 \dec_LDST_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \dec_LOGICAL_LOGICAL_LOGICAL__data_len - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_LOGICAL_LOGICAL_LOGICAL__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \dec_LOGICAL_LOGICAL_LOGICAL__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_LOGICAL_LOGICAL_LOGICAL__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_LOGICAL_LOGICAL_LOGICAL__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LOGICAL_LOGICAL_LOGICAL__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LOGICAL_LOGICAL_LOGICAL__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LOGICAL_LOGICAL_LOGICAL__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LOGICAL_LOGICAL_LOGICAL__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LOGICAL_LOGICAL_LOGICAL__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LOGICAL_LOGICAL_LOGICAL__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LOGICAL_LOGICAL_LOGICAL__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LOGICAL_LOGICAL_LOGICAL__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LOGICAL_LOGICAL_LOGICAL__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LOGICAL_LOGICAL_LOGICAL__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LOGICAL_LOGICAL_LOGICAL__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire \dec_LOGICAL_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 \dec_LOGICAL_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub18_upd + attribute \src "libresoc.v:24760.7-24760.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:24760.7-24760.20" + process $proc$libresoc.v:24760$516 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:25017.3-25038.6" + process $proc$libresoc.v:25017$492 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_function_unit[11:0] $1\dec31_dec_sub18_function_unit[11:0] + attribute \src "libresoc.v:25018.5-25018.29" + switch \initial + attribute \src "libresoc.v:25018.9-25018.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 + case + assign $1\dec31_dec_sub18_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[11:0] + end + attribute \src "libresoc.v:25039.3-25060.6" + process $proc$libresoc.v:25039$493 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:25040.5-25040.29" + switch \initial + attribute \src "libresoc.v:25040.9-25040.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] + end + attribute \src "libresoc.v:25061.3-25082.6" + process $proc$libresoc.v:25061$494 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] + attribute \src "libresoc.v:25062.5-25062.29" + switch \initial + attribute \src "libresoc.v:25062.9-25062.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] + end + attribute \src "libresoc.v:25083.3-25104.6" + process $proc$libresoc.v:25083$495 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:25084.5-25084.29" + switch \initial + attribute \src "libresoc.v:25084.9-25084.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] + end + attribute \src "libresoc.v:25105.3-25126.6" + process $proc$libresoc.v:25105$496 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:25106.5-25106.29" + switch \initial + attribute \src "libresoc.v:25106.9-25106.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] + end + attribute \src "libresoc.v:25127.3-25148.6" + process $proc$libresoc.v:25127$497 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:25128.5-25128.29" + switch \initial + attribute \src "libresoc.v:25128.9-25128.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'01111000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'01110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'10011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001101 + case + assign $1\dec31_dec_sub18_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0] + end + attribute \src "libresoc.v:25149.3-25170.6" + process $proc$libresoc.v:25149$498 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:25150.5-25150.29" + switch \initial + attribute \src "libresoc.v:25150.9-25150.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0] + end + attribute \src "libresoc.v:25171.3-25192.6" + process $proc$libresoc.v:25171$499 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:25172.5-25172.29" + switch \initial + attribute \src "libresoc.v:25172.9-25172.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0] + end + attribute \src "libresoc.v:25193.3-25214.6" + process $proc$libresoc.v:25193$500 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:25194.5-25194.29" + switch \initial + attribute \src "libresoc.v:25194.9-25194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0] + end + attribute \src "libresoc.v:25215.3-25236.6" + process $proc$libresoc.v:25215$501 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:25216.5-25216.29" + switch \initial + attribute \src "libresoc.v:25216.9-25216.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + case + assign $1\dec31_dec_sub18_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0] + end + attribute \src "libresoc.v:25237.3-25258.6" + process $proc$libresoc.v:25237$502 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:25238.5-25238.29" + switch \initial + attribute \src "libresoc.v:25238.9-25238.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0] + end + attribute \src "libresoc.v:25259.3-25280.6" + process $proc$libresoc.v:25259$503 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:25260.5-25260.29" + switch \initial + attribute \src "libresoc.v:25260.9-25260.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + case + assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] + end + attribute \src "libresoc.v:25281.3-25302.6" + process $proc$libresoc.v:25281$504 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:25282.5-25282.29" + switch \initial + attribute \src "libresoc.v:25282.9-25282.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0] + end + attribute \src "libresoc.v:25303.3-25324.6" + process $proc$libresoc.v:25303$505 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:25304.5-25304.29" + switch \initial + attribute \src "libresoc.v:25304.9-25304.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] + end + attribute \src "libresoc.v:25325.3-25346.6" + process $proc$libresoc.v:25325$506 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:25326.5-25326.29" + switch \initial + attribute \src "libresoc.v:25326.9-25326.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0] + end + attribute \src "libresoc.v:25347.3-25368.6" + process $proc$libresoc.v:25347$507 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:25348.5-25348.29" + switch \initial + attribute \src "libresoc.v:25348.9-25348.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0] + end + attribute \src "libresoc.v:25369.3-25390.6" + process $proc$libresoc.v:25369$508 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:25370.5-25370.29" + switch \initial + attribute \src "libresoc.v:25370.9-25370.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0] + end + attribute \src "libresoc.v:25391.3-25412.6" + process $proc$libresoc.v:25391$509 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:25392.5-25392.29" + switch \initial + attribute \src "libresoc.v:25392.9-25392.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub18_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] + end + attribute \src "libresoc.v:25413.3-25434.6" + process $proc$libresoc.v:25413$510 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:25414.5-25414.29" + switch \initial + attribute \src "libresoc.v:25414.9-25414.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0] + end + attribute \src "libresoc.v:25435.3-25456.6" + process $proc$libresoc.v:25435$511 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:25436.5-25436.29" + switch \initial + attribute \src "libresoc.v:25436.9-25436.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0] + end + attribute \src "libresoc.v:25457.3-25478.6" + process $proc$libresoc.v:25457$512 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:25458.5-25458.29" + switch \initial + attribute \src "libresoc.v:25458.9-25458.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0] + end + attribute \src "libresoc.v:25479.3-25500.6" + process $proc$libresoc.v:25479$513 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_out_sel[1:0] $1\dec31_dec_sub18_out_sel[1:0] + attribute \src "libresoc.v:25480.5-25480.29" + switch \initial + attribute \src "libresoc.v:25480.9-25480.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[1:0] + end + attribute \src "libresoc.v:25501.3-25522.6" + process $proc$libresoc.v:25501$514 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:25502.5-25502.29" + switch \initial + attribute \src "libresoc.v:25502.9-25502.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] + end + attribute \src "libresoc.v:25523.3-25544.6" + process $proc$libresoc.v:25523$515 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:25524.5-25524.29" + switch \initial + attribute \src "libresoc.v:25524.9-25524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:25550.1-26265.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub19" +attribute \generator "nMigen" +module \dec31_dec_sub19 + attribute \src "libresoc.v:25903.3-25921.6" + wire width 8 $0\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:25979.3-25997.6" + wire $0\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:26226.3-26244.6" + wire width 3 $0\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:26245.3-26263.6" + wire width 3 $0\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:25884.3-25902.6" + wire width 2 $0\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:25960.3-25978.6" + wire $0\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:26131.3-26149.6" + wire width 5 $0\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:25808.3-25826.6" + wire width 12 $0\dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:26150.3-26168.6" + wire width 3 $0\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:26169.3-26187.6" + wire width 4 $0\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:26188.3-26206.6" + wire width 2 $0\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:26017.3-26035.6" + wire width 7 $0\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:25922.3-25940.6" + wire $0\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:25941.3-25959.6" + wire $0\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:26055.3-26073.6" + wire $0\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:25827.3-25845.6" + wire width 4 $0\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:26093.3-26111.6" + wire $0\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:26207.3-26225.6" + wire width 2 $0\dec31_dec_sub19_out_sel[1:0] + attribute \src "libresoc.v:25865.3-25883.6" + wire width 2 $0\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:26036.3-26054.6" + wire $0\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:26112.3-26130.6" + wire $0\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:26074.3-26092.6" + wire $0\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:25998.3-26016.6" + wire $0\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:25846.3-25864.6" + wire width 2 $0\dec31_dec_sub19_upd[1:0] + attribute \src "libresoc.v:25551.7-25551.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:25903.3-25921.6" + wire width 8 $1\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:25979.3-25997.6" + wire $1\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:26226.3-26244.6" + wire width 3 $1\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:26245.3-26263.6" + wire width 3 $1\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:25884.3-25902.6" + wire width 2 $1\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:25960.3-25978.6" + wire $1\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:26131.3-26149.6" + wire width 5 $1\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:25808.3-25826.6" + wire width 12 $1\dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:26150.3-26168.6" + wire width 3 $1\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:26169.3-26187.6" + wire width 4 $1\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:26188.3-26206.6" + wire width 2 $1\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:26017.3-26035.6" + wire width 7 $1\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:25922.3-25940.6" + wire $1\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:25941.3-25959.6" + wire $1\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:26055.3-26073.6" + wire $1\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:25827.3-25845.6" + wire width 4 $1\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:26093.3-26111.6" + wire $1\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:26207.3-26225.6" + wire width 2 $1\dec31_dec_sub19_out_sel[1:0] + attribute \src "libresoc.v:25865.3-25883.6" + wire width 2 $1\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:26036.3-26054.6" + wire $1\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:26112.3-26130.6" + wire $1\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:26074.3-26092.6" + wire $1\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:25998.3-26016.6" + wire $1\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:25846.3-25864.6" + wire width 2 $1\dec31_dec_sub19_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub19_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -61132,14 +36475,39 @@ module \core attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_MUL_MUL_MUL__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dec_MUL_MUL_MUL__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_MUL_MUL_MUL__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_MUL_MUL_MUL__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -61214,153 +36582,1073 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_MUL_MUL_MUL__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_MUL_MUL_MUL__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_MUL_MUL_MUL__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_MUL_MUL_MUL__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_MUL_MUL_MUL__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_MUL_MUL_MUL__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_MUL_MUL_MUL__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_MUL_MUL_MUL__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire \dec_MUL_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 \dec_MUL_raw_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub19_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire \dec_SHIFT_ROT_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 \dec_SHIFT_ROT_raw_opcode_in + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub19_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub19_upd + attribute \src "libresoc.v:25551.7-25551.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:25551.7-25551.20" + process $proc$libresoc.v:25551$541 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:25808.3-25826.6" + process $proc$libresoc.v:25808$517 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_function_unit[11:0] $1\dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:25809.5-25809.29" + switch \initial + attribute \src "libresoc.v:25809.9-25809.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000 + case + assign $1\dec31_dec_sub19_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[11:0] + end + attribute \src "libresoc.v:25827.3-25845.6" + process $proc$libresoc.v:25827$518 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:25828.5-25828.29" + switch \initial + attribute \src "libresoc.v:25828.9-25828.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0] + end + attribute \src "libresoc.v:25846.3-25864.6" + process $proc$libresoc.v:25846$519 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] + attribute \src "libresoc.v:25847.5-25847.29" + switch \initial + attribute \src "libresoc.v:25847.9-25847.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] + end + attribute \src "libresoc.v:25865.3-25883.6" + process $proc$libresoc.v:25865$520 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:25866.5-25866.29" + switch \initial + attribute \src "libresoc.v:25866.9-25866.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0] + end + attribute \src "libresoc.v:25884.3-25902.6" + process $proc$libresoc.v:25884$521 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:25885.5-25885.29" + switch \initial + attribute \src "libresoc.v:25885.9-25885.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0] + end + attribute \src "libresoc.v:25903.3-25921.6" + process $proc$libresoc.v:25903$522 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:25904.5-25904.29" + switch \initial + attribute \src "libresoc.v:25904.9-25904.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01111001 + case + assign $1\dec31_dec_sub19_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0] + end + attribute \src "libresoc.v:25922.3-25940.6" + process $proc$libresoc.v:25922$523 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:25923.5-25923.29" + switch \initial + attribute \src "libresoc.v:25923.9-25923.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0] + end + attribute \src "libresoc.v:25941.3-25959.6" + process $proc$libresoc.v:25941$524 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:25942.5-25942.29" + switch \initial + attribute \src "libresoc.v:25942.9-25942.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0] + end + attribute \src "libresoc.v:25960.3-25978.6" + process $proc$libresoc.v:25960$525 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:25961.5-25961.29" + switch \initial + attribute \src "libresoc.v:25961.9-25961.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0] + end + attribute \src "libresoc.v:25979.3-25997.6" + process $proc$libresoc.v:25979$526 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:25980.5-25980.29" + switch \initial + attribute \src "libresoc.v:25980.9-25980.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + case + assign $1\dec31_dec_sub19_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0] + end + attribute \src "libresoc.v:25998.3-26016.6" + process $proc$libresoc.v:25998$527 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:25999.5-25999.29" + switch \initial + attribute \src "libresoc.v:25999.9-25999.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0] + end + attribute \src "libresoc.v:26017.3-26035.6" + process $proc$libresoc.v:26017$528 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:26018.5-26018.29" + switch \initial + attribute \src "libresoc.v:26018.9-26018.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'1000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0110001 + case + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] + end + attribute \src "libresoc.v:26036.3-26054.6" + process $proc$libresoc.v:26036$529 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:26037.5-26037.29" + switch \initial + attribute \src "libresoc.v:26037.9-26037.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0] + end + attribute \src "libresoc.v:26055.3-26073.6" + process $proc$libresoc.v:26055$530 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:26056.5-26056.29" + switch \initial + attribute \src "libresoc.v:26056.9-26056.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] + end + attribute \src "libresoc.v:26074.3-26092.6" + process $proc$libresoc.v:26074$531 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:26075.5-26075.29" + switch \initial + attribute \src "libresoc.v:26075.9-26075.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0] + end + attribute \src "libresoc.v:26093.3-26111.6" + process $proc$libresoc.v:26093$532 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:26094.5-26094.29" + switch \initial + attribute \src "libresoc.v:26094.9-26094.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0] + end + attribute \src "libresoc.v:26112.3-26130.6" + process $proc$libresoc.v:26112$533 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:26113.5-26113.29" + switch \initial + attribute \src "libresoc.v:26113.9-26113.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0] + end + attribute \src "libresoc.v:26131.3-26149.6" + process $proc$libresoc.v:26131$534 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:26132.5-26132.29" + switch \initial + attribute \src "libresoc.v:26132.9-26132.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + case + assign $1\dec31_dec_sub19_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] + end + attribute \src "libresoc.v:26150.3-26168.6" + process $proc$libresoc.v:26150$535 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:26151.5-26151.29" + switch \initial + attribute \src "libresoc.v:26151.9-26151.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0] + end + attribute \src "libresoc.v:26169.3-26187.6" + process $proc$libresoc.v:26169$536 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:26170.5-26170.29" + switch \initial + attribute \src "libresoc.v:26170.9-26170.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0] + end + attribute \src "libresoc.v:26188.3-26206.6" + process $proc$libresoc.v:26188$537 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:26189.5-26189.29" + switch \initial + attribute \src "libresoc.v:26189.9-26189.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0] + end + attribute \src "libresoc.v:26207.3-26225.6" + process $proc$libresoc.v:26207$538 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_out_sel[1:0] $1\dec31_dec_sub19_out_sel[1:0] + attribute \src "libresoc.v:26208.5-26208.29" + switch \initial + attribute \src "libresoc.v:26208.9-26208.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'11 + case + assign $1\dec31_dec_sub19_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[1:0] + end + attribute \src "libresoc.v:26226.3-26244.6" + process $proc$libresoc.v:26226$539 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:26227.5-26227.29" + switch \initial + attribute \src "libresoc.v:26227.9-26227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] + end + attribute \src "libresoc.v:26245.3-26263.6" + process $proc$libresoc.v:26245$540 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:26246.5-26246.29" + switch \initial + attribute \src "libresoc.v:26246.9-26246.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:26269.1-27128.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub20" +attribute \generator "nMigen" +module \dec31_dec_sub20 + attribute \src "libresoc.v:26652.3-26676.6" + wire width 8 $0\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:26752.3-26776.6" + wire $0\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:27077.3-27101.6" + wire width 3 $0\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:27102.3-27126.6" + wire width 3 $0\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:26627.3-26651.6" + wire width 2 $0\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:26727.3-26751.6" + wire $0\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:26952.3-26976.6" + wire width 5 $0\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:26527.3-26551.6" + wire width 12 $0\dec31_dec_sub20_function_unit[11:0] + attribute \src "libresoc.v:26977.3-27001.6" + wire width 3 $0\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:27002.3-27026.6" + wire width 4 $0\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:27027.3-27051.6" + wire width 2 $0\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:26802.3-26826.6" + wire width 7 $0\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:26677.3-26701.6" + wire $0\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:26702.3-26726.6" + wire $0\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:26852.3-26876.6" + wire $0\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:26552.3-26576.6" + wire width 4 $0\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:26902.3-26926.6" + wire $0\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:27052.3-27076.6" + wire width 2 $0\dec31_dec_sub20_out_sel[1:0] + attribute \src "libresoc.v:26602.3-26626.6" + wire width 2 $0\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:26827.3-26851.6" + wire $0\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:26927.3-26951.6" + wire $0\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:26877.3-26901.6" + wire $0\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:26777.3-26801.6" + wire $0\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:26577.3-26601.6" + wire width 2 $0\dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:26270.7-26270.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26652.3-26676.6" + wire width 8 $1\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:26752.3-26776.6" + wire $1\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:27077.3-27101.6" + wire width 3 $1\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:27102.3-27126.6" + wire width 3 $1\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:26627.3-26651.6" + wire width 2 $1\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:26727.3-26751.6" + wire $1\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:26952.3-26976.6" + wire width 5 $1\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:26527.3-26551.6" + wire width 12 $1\dec31_dec_sub20_function_unit[11:0] + attribute \src "libresoc.v:26977.3-27001.6" + wire width 3 $1\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:27002.3-27026.6" + wire width 4 $1\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:27027.3-27051.6" + wire width 2 $1\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:26802.3-26826.6" + wire width 7 $1\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:26677.3-26701.6" + wire $1\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:26702.3-26726.6" + wire $1\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:26852.3-26876.6" + wire $1\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:26552.3-26576.6" + wire width 4 $1\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:26902.3-26926.6" + wire $1\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:27052.3-27076.6" + wire width 2 $1\dec31_dec_sub20_out_sel[1:0] + attribute \src "libresoc.v:26602.3-26626.6" + wire width 2 $1\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:26827.3-26851.6" + wire $1\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:26927.3-26951.6" + wire $1\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:26877.3-26901.6" + wire $1\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:26777.3-26801.6" + wire $1\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:26577.3-26601.6" + wire width 2 $1\dec31_dec_sub20_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub20_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub20_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub20_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub20_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub20_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub20_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub20_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -61374,10 +37662,39 @@ module \core attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_SPR_SPR_SPR__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_SPR_SPR_SPR__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub20_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub20_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub20_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub20_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -61452,643 +37769,1265 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_SPR_SPR_SPR__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SPR_SPR_SPR__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire \dec_SPR_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 \dec_SPR_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 61 \dmi__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 63 \dmi__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 62 \dmi__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_CR_cr_a_branch0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_CR_cr_a_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_CR_cr_b_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_CR_cr_c_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_CR_full_cr_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_FAST_fast1_branch0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_FAST_fast1_spr0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_FAST_fast1_trap0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_FAST_fast2_branch0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_FAST_fast2_trap0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_ra_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_ra_cr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_ra_div0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_ra_ldst0_8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_ra_logical0_3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_ra_mul0_6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_ra_shiftrot0_7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_ra_spr0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_ra_trap0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_rb_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_rb_cr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_rb_div0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_rb_ldst0_7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_rb_logical0_3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_rb_mul0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_rb_shiftrot0_6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_rb_trap0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_rc_ldst0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_INT_rc_shiftrot0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_SPR_spr1_spr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_XER_xer_ca_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_XER_xer_ca_shiftrot0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_XER_xer_ca_spr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_XER_xer_ov_spr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_XER_xer_so_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_XER_xer_so_div0_3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_XER_xer_so_logical0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_XER_xer_so_mul0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_XER_xer_so_shiftrot0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_XER_xer_so_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire \dp_XER_xer_so_spr0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" - wire \en_alu0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" - wire \en_branch0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" - wire \en_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" - wire \en_div0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" - wire \en_ldst0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" - wire \en_logical0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" - wire \en_mul0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" - wire \en_shiftrot0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" - wire \en_spr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" - wire \en_trap0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \fast_dest1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \fast_dest1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \fast_dest1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \fast_src1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \fast_src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \fast_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 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\fus_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_o_ok$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_o_ok$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_o_ok$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_o_ok$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_o_ok$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_o_ok$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_o_ok$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \fus_oper_i_alu_alu0__data_len - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \fus_oper_i_alu_alu0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \fus_oper_i_alu_alu0__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \fus_oper_i_alu_alu0__imm_data__ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub20_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub20_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub20_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub20_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub20_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub20_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub20_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \fus_oper_i_alu_alu0__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \fus_oper_i_alu_alu0__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \fus_oper_i_alu_alu0__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \fus_oper_i_alu_alu0__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \fus_oper_i_alu_alu0__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \fus_oper_i_alu_alu0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \fus_oper_i_alu_alu0__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \fus_oper_i_alu_alu0__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \fus_oper_i_alu_alu0__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \fus_oper_i_alu_alu0__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \fus_oper_i_alu_alu0__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \fus_oper_i_alu_alu0__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \fus_oper_i_alu_alu0__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \fus_oper_i_alu_alu0__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \fus_oper_i_alu_branch0__cia + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub20_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub20_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub20_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub20_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub20_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub20_upd + attribute \src "libresoc.v:26270.7-26270.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:26270.7-26270.20" + process $proc$libresoc.v:26270$566 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26527.3-26551.6" + process $proc$libresoc.v:26527$542 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_function_unit[11:0] $1\dec31_dec_sub20_function_unit[11:0] + attribute \src "libresoc.v:26528.5-26528.29" + switch \initial + attribute \src "libresoc.v:26528.9-26528.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + case + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[11:0] + end + attribute \src "libresoc.v:26552.3-26576.6" + process $proc$libresoc.v:26552$543 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:26553.5-26553.29" + switch \initial + attribute \src "libresoc.v:26553.9-26553.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + case + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0] + end + attribute \src "libresoc.v:26577.3-26601.6" + process $proc$libresoc.v:26577$544 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:26578.5-26578.29" + switch \initial + attribute \src "libresoc.v:26578.9-26578.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] + end + attribute \src "libresoc.v:26602.3-26626.6" + process $proc$libresoc.v:26602$545 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:26603.5-26603.29" + switch \initial + attribute \src "libresoc.v:26603.9-26603.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0] + end + attribute \src "libresoc.v:26627.3-26651.6" + process $proc$libresoc.v:26627$546 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:26628.5-26628.29" + switch \initial + attribute \src "libresoc.v:26628.9-26628.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0] + end + attribute \src "libresoc.v:26652.3-26676.6" + process $proc$libresoc.v:26652$547 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:26653.5-26653.29" + switch \initial + attribute \src "libresoc.v:26653.9-26653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01011001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'10101101 + case + assign $1\dec31_dec_sub20_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0] + end + attribute \src "libresoc.v:26677.3-26701.6" + process $proc$libresoc.v:26677$548 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:26678.5-26678.29" + switch \initial + attribute \src "libresoc.v:26678.9-26678.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0] + end + attribute \src "libresoc.v:26702.3-26726.6" + process $proc$libresoc.v:26702$549 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:26703.5-26703.29" + switch \initial + attribute \src "libresoc.v:26703.9-26703.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0] + end + attribute \src "libresoc.v:26727.3-26751.6" + process $proc$libresoc.v:26727$550 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:26728.5-26728.29" + switch \initial + attribute \src "libresoc.v:26728.9-26728.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0] + end + attribute \src "libresoc.v:26752.3-26776.6" + process $proc$libresoc.v:26752$551 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:26753.5-26753.29" + switch \initial + attribute \src "libresoc.v:26753.9-26753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'1 + case + assign $1\dec31_dec_sub20_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0] + end + attribute \src "libresoc.v:26777.3-26801.6" + process $proc$libresoc.v:26777$552 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:26778.5-26778.29" + switch \initial + attribute \src "libresoc.v:26778.9-26778.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0] + end + attribute \src "libresoc.v:26802.3-26826.6" + process $proc$libresoc.v:26802$553 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:26803.5-26803.29" + switch \initial + attribute \src "libresoc.v:26803.9-26803.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] + end + attribute \src "libresoc.v:26827.3-26851.6" + process $proc$libresoc.v:26827$554 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:26828.5-26828.29" + switch \initial + attribute \src "libresoc.v:26828.9-26828.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0] + end + attribute \src "libresoc.v:26852.3-26876.6" + process $proc$libresoc.v:26852$555 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:26853.5-26853.29" + switch \initial + attribute \src "libresoc.v:26853.9-26853.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] + end + attribute \src "libresoc.v:26877.3-26901.6" + process $proc$libresoc.v:26877$556 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:26878.5-26878.29" + switch \initial + attribute \src "libresoc.v:26878.9-26878.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] + end + attribute \src "libresoc.v:26902.3-26926.6" + process $proc$libresoc.v:26902$557 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:26903.5-26903.29" + switch \initial + attribute \src "libresoc.v:26903.9-26903.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] + end + attribute \src "libresoc.v:26927.3-26951.6" + process $proc$libresoc.v:26927$558 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:26928.5-26928.29" + switch \initial + attribute \src "libresoc.v:26928.9-26928.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] + end + attribute \src "libresoc.v:26952.3-26976.6" + process $proc$libresoc.v:26952$559 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:26953.5-26953.29" + switch \initial + attribute \src "libresoc.v:26953.9-26953.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub20_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] + end + attribute \src "libresoc.v:26977.3-27001.6" + process $proc$libresoc.v:26977$560 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:26978.5-26978.29" + switch \initial + attribute \src "libresoc.v:26978.9-26978.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] + end + attribute \src "libresoc.v:27002.3-27026.6" + process $proc$libresoc.v:27002$561 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:27003.5-27003.29" + switch \initial + attribute \src "libresoc.v:27003.9-27003.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] + end + attribute \src "libresoc.v:27027.3-27051.6" + process $proc$libresoc.v:27027$562 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:27028.5-27028.29" + switch \initial + attribute \src "libresoc.v:27028.9-27028.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] + end + attribute \src "libresoc.v:27052.3-27076.6" + process $proc$libresoc.v:27052$563 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_out_sel[1:0] $1\dec31_dec_sub20_out_sel[1:0] + attribute \src "libresoc.v:27053.5-27053.29" + switch \initial + attribute \src "libresoc.v:27053.9-27053.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_out_sel $0\dec31_dec_sub20_out_sel[1:0] + end + attribute \src "libresoc.v:27077.3-27101.6" + process $proc$libresoc.v:27077$564 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:27078.5-27078.29" + switch \initial + attribute \src "libresoc.v:27078.9-27078.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0] + end + attribute \src "libresoc.v:27102.3-27126.6" + process $proc$libresoc.v:27102$565 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:27103.5-27103.29" + switch \initial + attribute \src "libresoc.v:27103.9-27103.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:27132.1-28549.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub21" +attribute \generator "nMigen" +module \dec31_dec_sub21 + attribute \src "libresoc.v:28174.3-28204.6" + wire width 8 $0\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:27782.3-27830.6" + wire $0\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:28450.3-28498.6" + wire width 3 $0\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:28499.3-28547.6" + wire width 3 $0\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:27586.3-27634.6" + wire width 2 $0\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:27733.3-27781.6" + wire $0\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:28205.3-28253.6" + wire width 5 $0\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:27390.3-27438.6" + wire width 12 $0\dec31_dec_sub21_function_unit[11:0] + attribute \src "libresoc.v:28254.3-28302.6" + wire width 3 $0\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:28303.3-28351.6" + wire width 4 $0\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:28352.3-28400.6" + wire width 2 $0\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:27929.3-27977.6" + wire width 7 $0\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:27635.3-27683.6" + wire $0\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:27684.3-27732.6" + wire $0\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:27978.3-28026.6" + wire $0\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:27439.3-27487.6" + wire width 4 $0\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:28076.3-28124.6" + wire $0\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:28401.3-28449.6" + wire width 2 $0\dec31_dec_sub21_out_sel[1:0] + attribute \src "libresoc.v:27537.3-27585.6" + wire width 2 $0\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:27880.3-27928.6" + wire $0\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:28125.3-28173.6" + wire $0\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:28027.3-28075.6" + wire $0\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:27831.3-27879.6" + wire $0\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:27488.3-27536.6" + wire width 2 $0\dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:27133.7-27133.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:28174.3-28204.6" + wire width 8 $1\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:27782.3-27830.6" + wire $1\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:28450.3-28498.6" + wire width 3 $1\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:28499.3-28547.6" + wire width 3 $1\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:27586.3-27634.6" + wire width 2 $1\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:27733.3-27781.6" + wire $1\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:28205.3-28253.6" + wire width 5 $1\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:27390.3-27438.6" + wire width 12 $1\dec31_dec_sub21_function_unit[11:0] + attribute \src "libresoc.v:28254.3-28302.6" + wire width 3 $1\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:28303.3-28351.6" + wire width 4 $1\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:28352.3-28400.6" + wire width 2 $1\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:27929.3-27977.6" + wire width 7 $1\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:27635.3-27683.6" + wire $1\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:27684.3-27732.6" + wire $1\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:27978.3-28026.6" + wire $1\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:27439.3-27487.6" + wire width 4 $1\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:28076.3-28124.6" + wire $1\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:28401.3-28449.6" + wire width 2 $1\dec31_dec_sub21_out_sel[1:0] + attribute \src "libresoc.v:27537.3-27585.6" + wire width 2 $1\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:27880.3-27928.6" + wire $1\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:28125.3-28173.6" + wire $1\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:28027.3-28075.6" + wire $1\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:27831.3-27879.6" + wire $1\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:27488.3-27536.6" + wire width 2 $1\dec31_dec_sub21_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub21_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub21_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub21_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub21_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub21_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub21_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub21_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -62102,14 +39041,39 @@ module \core attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \fus_oper_i_alu_branch0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \fus_oper_i_alu_branch0__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \fus_oper_i_alu_branch0__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \fus_oper_i_alu_branch0__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub21_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \fus_oper_i_ldst_ldst0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \fus_oper_i_ldst_ldst0__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \fus_oper_i_ldst_ldst0__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \fus_oper_i_ldst_ldst0__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute 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- wire \fus_oper_i_ldst_ldst0__is_signed + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub21_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub21_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub21_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub21_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub21_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \fus_oper_i_ldst_ldst0__ldst_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \fus_oper_i_ldst_ldst0__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \fus_oper_i_ldst_ldst0__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \fus_oper_i_ldst_ldst0__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \fus_oper_i_ldst_ldst0__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \fus_oper_i_ldst_ldst0__sign_extend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \fus_oper_i_ldst_ldst0__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src3_i$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire \fus_src3_i$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire \fus_src3_i$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire \fus_src3_i$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire \fus_src3_i$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 32 \fus_src3_i$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 \fus_src3_i$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src3_i$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src3_i$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire \fus_src4_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire \fus_src4_i$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 \fus_src4_i$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 \fus_src4_i$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src4_i$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 \fus_src5_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 \fus_src5_i$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 \fus_src5_i$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 \fus_src6_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 \fus_src6_i$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_xer_ca_ok$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_xer_ca_ok$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_xer_ov_ok$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_xer_ov_ok$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_xer_ov_ok$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_xer_so_ok$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_xer_so_ok$133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_xer_so_ok$134 - attribute \src "issuer_ls180.v:34906.7-34906.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub21_upd + attribute \src "libresoc.v:27133.7-27133.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 \int_dest1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \int_dest1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \int_dest1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 \int_src1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \int_src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \int_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 \int_src2__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \int_src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \int_src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 \int_src3__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \int_src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \int_src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 68 \issue__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 71 \issue__addr$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 73 \issue__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 70 \issue__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 69 \issue__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 72 \issue__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:92" - wire input 59 \issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:91" - wire input 58 \ivalid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 56 \msr__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \msr__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire \pick_XER_xer_so_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:87" - wire width 32 input 54 \raw_insn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire \rdflag_CR_cr_a_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire \rdflag_CR_cr_b_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire \rdflag_CR_cr_c_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire \rdflag_CR_full_cr_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire \rdflag_FAST_fast1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire \rdflag_FAST_fast2_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire \rdflag_INT_ra_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire \rdflag_INT_rb_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire \rdflag_INT_rc_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire \rdflag_SPR_spr1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire \rdflag_XER_xer_ca_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire \rdflag_XER_xer_ov_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire \rdflag_XER_xer_so_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_CR_cr_a_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 2 \rdpick_CR_cr_a_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 2 \rdpick_CR_cr_a_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_CR_cr_b_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire \rdpick_CR_cr_b_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire \rdpick_CR_cr_b_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_CR_cr_c_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire \rdpick_CR_cr_c_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire \rdpick_CR_cr_c_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_CR_full_cr_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire \rdpick_CR_full_cr_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire \rdpick_CR_full_cr_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_FAST_fast1_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 3 \rdpick_FAST_fast1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 3 \rdpick_FAST_fast1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_FAST_fast2_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 2 \rdpick_FAST_fast2_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 2 \rdpick_FAST_fast2_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_INT_ra_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 9 \rdpick_INT_ra_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 9 \rdpick_INT_ra_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_INT_rb_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \rdpick_INT_rb_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \rdpick_INT_rb_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_INT_rc_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 2 \rdpick_INT_rc_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 2 \rdpick_INT_rc_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_SPR_spr1_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire \rdpick_SPR_spr1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire \rdpick_SPR_spr1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_XER_xer_ca_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 3 \rdpick_XER_xer_ca_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 3 \rdpick_XER_xer_ca_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_XER_xer_ov_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire \rdpick_XER_xer_ov_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire \rdpick_XER_xer_ov_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_XER_xer_so_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 6 \rdpick_XER_xer_so_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 6 \rdpick_XER_xer_so_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire \rp_XER_xer_so_spr0_2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 7 \spr_spr1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 7 \spr_spr1__addr$159 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \spr_spr1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \spr_spr1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \spr_spr1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \spr_spr1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \state_data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \state_data_i$158 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 60 \state_nia_wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \state_wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1014 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1036 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1056 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1076 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1095 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1230 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1250 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1270 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1290 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1310 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1330 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1377 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1393 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1409 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1443 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1459 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1475 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1491 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1527 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1543 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1559 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1575 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1620 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1636 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1652 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1668 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1684 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1728 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1744 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1768 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire \wp$1788 - attribute \src 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\wr_pick$1194 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire \wr_pick$1222 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire \wr_pick$1242 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire \wr_pick$1262 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire \wr_pick$1282 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire \wr_pick$1302 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire \wr_pick$1322 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire \wr_pick$1369 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire \wr_pick$1385 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire \wr_pick$1401 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire \wr_pick$1435 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire \wr_pick$1660 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire \wr_pick$1676 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire \wr_pick$1720 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire \wr_pick$1736 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire \wr_pick$1760 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire \wr_pick$1780 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire \wr_pick$964 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire \wr_pick$983 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1007 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1007$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1025 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1025$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1047 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1047$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1067 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1067$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1087 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1087$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1106 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1106$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1124 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1124$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1197 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1197$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1225 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1225$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1245 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1245$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1265 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1265$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1285 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1285$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1305 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1305$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1325 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1325$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1372 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1372$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1388 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1388$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1404 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1404$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1438 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1438$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1454 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1454$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1470 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1470$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1486 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1486$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1522 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1522$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1538 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1538$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1554 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1554$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1570 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1570$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1612 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1612$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1631 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1631$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1647 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1647$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1663 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1663$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1679 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1679$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1723 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1723$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1739 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1739$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1763 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1763$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1783 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1783$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$967 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$967$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$986 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$986$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1008 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1013 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1026 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1031 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1032 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1033 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1034 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1035 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1048 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1053 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1054 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1055 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1068 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1073 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1074 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1075 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1088 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1093 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1094 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1107 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1112 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1613 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1618 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1619 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$954 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$955 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$956 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$957 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$968 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$973 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$974 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$987 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$992 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$993 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$994 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$995 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_alu0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_alu0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_alu0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_alu0_xer_ov_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_alu0_xer_so_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_branch0_fast1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_branch0_fast1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_branch0_nia_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_cr0_cr_a_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_cr0_full_cr_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_cr0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_div0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_div0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_div0_xer_ov_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_div0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_ldst0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_ldst0_o_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_logical0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_logical0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_mul0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_mul0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_mul0_xer_ov_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_mul0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_shiftrot0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_shiftrot0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_shiftrot0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_spr0_fast1_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_spr0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_spr0_spr1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_spr0_xer_ca_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_spr0_xer_ov_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_spr0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_trap0_fast1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_trap0_fast1_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_trap0_msr_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_trap0_nia_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire \wrflag_trap0_o_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \wrpick_CR_cr_a_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 6 \wrpick_CR_cr_a_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 6 \wrpick_CR_cr_a_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \wrpick_CR_full_cr_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire \wrpick_CR_full_cr_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire \wrpick_CR_full_cr_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \wrpick_FAST_fast1_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 5 \wrpick_FAST_fast1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 5 \wrpick_FAST_fast1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \wrpick_INT_o_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 10 \wrpick_INT_o_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 10 \wrpick_INT_o_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \wrpick_SPR_spr1_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire \wrpick_SPR_spr1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire \wrpick_SPR_spr1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \wrpick_STATE_msr_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire \wrpick_STATE_msr_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire \wrpick_STATE_msr_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \wrpick_STATE_nia_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 2 \wrpick_STATE_nia_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 2 \wrpick_STATE_nia_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \wrpick_XER_xer_ca_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 3 \wrpick_XER_xer_ca_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 3 \wrpick_XER_xer_ca_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \wrpick_XER_xer_ov_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 4 \wrpick_XER_xer_ov_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 4 \wrpick_XER_xer_ov_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \wrpick_XER_xer_so_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 4 \wrpick_XER_xer_so_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 4 \wrpick_XER_xer_so_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i$154 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i$156 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen$155 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40658$1430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok$89 - connect \B \fus_cu_busy_o$14 - connect \Y $and$issuer_ls180.v:40658$1430_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:27133.7-27133.20" + process $proc$libresoc.v:27133$591 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40659$1431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [3] - connect \B \wrpick_INT_o_en_o - connect \Y $and$issuer_ls180.v:40659$1431_Y + attribute \src "libresoc.v:27390.3-27438.6" + process $proc$libresoc.v:27390$567 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_function_unit[11:0] $1\dec31_dec_sub21_function_unit[11:0] + attribute \src "libresoc.v:27391.5-27391.29" + switch \initial + attribute \src "libresoc.v:27391.9-27391.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + case + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40661$1433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1004 - connect \B \$1009 - connect \Y $and$issuer_ls180.v:40661$1433_Y + attribute \src "libresoc.v:27439.3-27487.6" + process $proc$libresoc.v:27439$568 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:27440.5-27440.29" + switch \initial + attribute \src "libresoc.v:27440.9-27440.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + case + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40662$1434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1004 - connect \B \wrpick_INT_o_en_o - connect \Y $and$issuer_ls180.v:40662$1434_Y + attribute \src "libresoc.v:27488.3-27536.6" + process $proc$libresoc.v:27488$569 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:27489.5-27489.29" + switch \initial + attribute \src "libresoc.v:27489.9-27489.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + case + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40664$1436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok$92 - connect \B \fus_cu_busy_o$17 - connect \Y $and$issuer_ls180.v:40664$1436_Y + attribute \src "libresoc.v:27537.3-27585.6" + process $proc$libresoc.v:27537$570 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:27538.5-27538.29" + switch \initial + attribute \src "libresoc.v:27538.9-27538.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40665$1437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [4] - connect \B \wrpick_INT_o_en_o - connect \Y $and$issuer_ls180.v:40665$1437_Y + attribute \src "libresoc.v:27586.3-27634.6" + process $proc$libresoc.v:27586$571 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:27587.5-27587.29" + switch \initial + attribute \src "libresoc.v:27587.9-27587.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40667$1439 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1022 - connect \B \$1027 - connect \Y $and$issuer_ls180.v:40667$1439_Y + attribute \src "libresoc.v:27635.3-27683.6" + process $proc$libresoc.v:27635$572 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:27636.5-27636.29" + switch \initial + attribute \src "libresoc.v:27636.9-27636.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40668$1440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1022 - connect \B \wrpick_INT_o_en_o - connect \Y $and$issuer_ls180.v:40668$1440_Y + attribute \src "libresoc.v:27684.3-27732.6" + process $proc$libresoc.v:27684$573 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:27685.5-27685.29" + switch \initial + attribute \src "libresoc.v:27685.9-27685.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40670$1442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok$95 - connect \B \fus_cu_busy_o$20 - connect \Y $and$issuer_ls180.v:40670$1442_Y + attribute \src "libresoc.v:27733.3-27781.6" + process $proc$libresoc.v:27733$574 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:27734.5-27734.29" + switch \initial + attribute \src "libresoc.v:27734.9-27734.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40671$1443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [5] - connect \B \wrpick_INT_o_en_o - connect \Y $and$issuer_ls180.v:40671$1443_Y + attribute \src "libresoc.v:27782.3-27830.6" + process $proc$libresoc.v:27782$575 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:27783.5-27783.29" + switch \initial + attribute \src "libresoc.v:27783.9-27783.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + case + assign $1\dec31_dec_sub21_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40673$1445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1044 - connect \B \$1049 - connect \Y $and$issuer_ls180.v:40673$1445_Y + attribute \src "libresoc.v:27831.3-27879.6" + process $proc$libresoc.v:27831$576 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:27832.5-27832.29" + switch \initial + attribute \src "libresoc.v:27832.9-27832.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40674$1446 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1044 - connect \B \wrpick_INT_o_en_o - connect \Y $and$issuer_ls180.v:40674$1446_Y + attribute \src "libresoc.v:27880.3-27928.6" + process $proc$libresoc.v:27880$577 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:27881.5-27881.29" + switch \initial + attribute \src "libresoc.v:27881.9-27881.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40676$1448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok$98 - connect \B \fus_cu_busy_o$23 - connect \Y $and$issuer_ls180.v:40676$1448_Y + attribute \src "libresoc.v:27929.3-27977.6" + process $proc$libresoc.v:27929$578 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:27930.5-27930.29" + switch \initial + attribute \src "libresoc.v:27930.9-27930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40677$1449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [6] - connect \B \wrpick_INT_o_en_o - connect \Y $and$issuer_ls180.v:40677$1449_Y + attribute \src "libresoc.v:27978.3-28026.6" + process $proc$libresoc.v:27978$579 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:27979.5-27979.29" + switch \initial + attribute \src "libresoc.v:27979.9-27979.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40679$1451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1064 - connect \B \$1069 - connect \Y $and$issuer_ls180.v:40679$1451_Y + attribute \src "libresoc.v:28027.3-28075.6" + process $proc$libresoc.v:28027$580 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:28028.5-28028.29" + switch \initial + attribute \src "libresoc.v:28028.9-28028.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40680$1452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1064 - connect \B \wrpick_INT_o_en_o - connect \Y $and$issuer_ls180.v:40680$1452_Y + attribute \src "libresoc.v:28076.3-28124.6" + process $proc$libresoc.v:28076$581 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:28077.5-28077.29" + switch \initial + attribute \src "libresoc.v:28077.9-28077.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40682$1454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok$101 - connect \B \fus_cu_busy_o$26 - connect \Y $and$issuer_ls180.v:40682$1454_Y + attribute \src "libresoc.v:28125.3-28173.6" + process $proc$libresoc.v:28125$582 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:28126.5-28126.29" + switch \initial + attribute \src "libresoc.v:28126.9-28126.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40683$1455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [7] - connect \B \wrpick_INT_o_en_o - connect \Y $and$issuer_ls180.v:40683$1455_Y + attribute \src "libresoc.v:28174.3-28204.6" + process $proc$libresoc.v:28174$583 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:28175.5-28175.29" + switch \initial + attribute \src "libresoc.v:28175.9-28175.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01101000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10100111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110001 + case + assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40685$1457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1084 - connect \B \$1089 - connect \Y $and$issuer_ls180.v:40685$1457_Y + attribute \src "libresoc.v:28205.3-28253.6" + process $proc$libresoc.v:28205$584 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:28206.5-28206.29" + switch \initial + attribute \src "libresoc.v:28206.9-28206.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub21_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40686$1458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1084 - connect \B \wrpick_INT_o_en_o - connect \Y $and$issuer_ls180.v:40686$1458_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40688$1460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o_ok - connect \B \fus_cu_busy_o$29 - connect \Y $and$issuer_ls180.v:40688$1460_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40689$1461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [8] - connect \B \wrpick_INT_o_en_o - connect \Y $and$issuer_ls180.v:40689$1461_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40691$1463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1103 - connect \B \$1108 - connect \Y $and$issuer_ls180.v:40691$1463_Y + attribute \src "libresoc.v:28254.3-28302.6" + process $proc$libresoc.v:28254$585 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:28255.5-28255.29" + switch \initial + attribute \src "libresoc.v:28255.9-28255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40692$1464 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1103 - connect \B \wrpick_INT_o_en_o - connect \Y $and$issuer_ls180.v:40692$1464_Y + attribute \src "libresoc.v:28303.3-28351.6" + process $proc$libresoc.v:28303$586 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:28304.5-28304.29" + switch \initial + attribute \src "libresoc.v:28304.9-28304.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40694$1466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ea_ok - connect \B \fus_cu_busy_o$29 - connect \Y $and$issuer_ls180.v:40694$1466_Y + attribute \src "libresoc.v:28352.3-28400.6" + process $proc$libresoc.v:28352$587 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:28353.5-28353.29" + switch \initial + attribute \src "libresoc.v:28353.9-28353.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40695$1467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [9] - connect \B \wrpick_INT_o_en_o - connect \Y $and$issuer_ls180.v:40695$1467_Y + attribute \src "libresoc.v:28401.3-28449.6" + process $proc$libresoc.v:28401$588 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_out_sel[1:0] $1\dec31_dec_sub21_out_sel[1:0] + attribute \src "libresoc.v:28402.5-28402.29" + switch \initial + attribute \src "libresoc.v:28402.9-28402.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_out_sel $0\dec31_dec_sub21_out_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40697$1469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1121 - connect \B \$1125 - connect \Y $and$issuer_ls180.v:40697$1469_Y + attribute \src "libresoc.v:28450.3-28498.6" + process $proc$libresoc.v:28450$589 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:28451.5-28451.29" + switch \initial + attribute \src "libresoc.v:28451.9-28451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40698$1470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1121 - connect \B \wrpick_INT_o_en_o - connect \Y $and$issuer_ls180.v:40698$1470_Y + attribute \src "libresoc.v:28499.3-28547.6" + process $proc$libresoc.v:28499$590 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:28500.5-28500.29" + switch \initial + attribute \src "libresoc.v:28500.9-28500.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40727$1499 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_full_cr_ok - connect \B \fus_cu_busy_o$5 - connect \Y $and$issuer_ls180.v:40727$1499_Y + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:28553.1-30132.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub22" +attribute \generator "nMigen" +module \dec31_dec_sub22 + attribute \src "libresoc.v:29086.3-29140.6" + wire width 8 $0\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:29306.3-29360.6" + wire $0\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:30021.3-30075.6" + wire width 3 $0\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:30076.3-30130.6" + wire width 3 $0\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:29031.3-29085.6" + wire width 2 $0\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:29251.3-29305.6" + wire $0\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:29746.3-29800.6" + wire width 5 $0\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:28811.3-28865.6" + wire width 12 $0\dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:29801.3-29855.6" + wire width 3 $0\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:29856.3-29910.6" + wire width 4 $0\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:29911.3-29965.6" + wire width 2 $0\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:29416.3-29470.6" + wire width 7 $0\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:29141.3-29195.6" + wire $0\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:29196.3-29250.6" + wire $0\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:29526.3-29580.6" + wire $0\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:28866.3-28920.6" + wire width 4 $0\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:29636.3-29690.6" + wire $0\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:29966.3-30020.6" + wire width 2 $0\dec31_dec_sub22_out_sel[1:0] + attribute \src "libresoc.v:28976.3-29030.6" + wire width 2 $0\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:29471.3-29525.6" + wire $0\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:29691.3-29745.6" + wire $0\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:29581.3-29635.6" + wire $0\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:29361.3-29415.6" + wire $0\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:28921.3-28975.6" + wire width 2 $0\dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:28554.7-28554.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:29086.3-29140.6" + wire width 8 $1\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:29306.3-29360.6" + wire $1\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:30021.3-30075.6" + wire width 3 $1\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:30076.3-30130.6" + wire width 3 $1\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:29031.3-29085.6" + wire width 2 $1\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:29251.3-29305.6" + wire $1\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:29746.3-29800.6" + wire width 5 $1\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:28811.3-28865.6" + wire width 12 $1\dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:29801.3-29855.6" + wire width 3 $1\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:29856.3-29910.6" + wire width 4 $1\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:29911.3-29965.6" + wire width 2 $1\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:29416.3-29470.6" + wire width 7 $1\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:29141.3-29195.6" + wire $1\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:29196.3-29250.6" + wire $1\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:29526.3-29580.6" + wire $1\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:28866.3-28920.6" + wire width 4 $1\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:29636.3-29690.6" + wire $1\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:29966.3-30020.6" + wire width 2 $1\dec31_dec_sub22_out_sel[1:0] + attribute \src "libresoc.v:28976.3-29030.6" + wire width 2 $1\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:29471.3-29525.6" + wire $1\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:29691.3-29745.6" + wire $1\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:29581.3-29635.6" + wire $1\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:29361.3-29415.6" + wire $1\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:28921.3-28975.6" + wire width 2 $1\dec31_dec_sub22_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub22_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub22_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub22_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub22_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub22_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub22_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub22_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub22_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub22_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub22_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub22_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub22_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub22_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub22_upd + attribute \src "libresoc.v:28554.7-28554.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:28554.7-28554.20" + process $proc$libresoc.v:28554$616 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40728$1500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$84 [1] - connect \B \fu_enable [1] - connect \Y $and$issuer_ls180.v:40728$1500_Y + attribute \src "libresoc.v:28811.3-28865.6" + process $proc$libresoc.v:28811$592 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_function_unit[11:0] $1\dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:28812.5-28812.29" + switch \initial + attribute \src "libresoc.v:28812.9-28812.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + case + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40729$1501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_CR_full_cr_o - connect \B \wrpick_CR_full_cr_en_o - connect \Y $and$issuer_ls180.v:40729$1501_Y + attribute \src "libresoc.v:28866.3-28920.6" + process $proc$libresoc.v:28866$593 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:28867.5-28867.29" + switch \initial + attribute \src "libresoc.v:28867.9-28867.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40731$1503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1194 - connect \B \$1198 - connect \Y $and$issuer_ls180.v:40731$1503_Y + attribute \src "libresoc.v:28921.3-28975.6" + process $proc$libresoc.v:28921$594 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:28922.5-28922.29" + switch \initial + attribute \src "libresoc.v:28922.9-28922.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40732$1504 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1194 - connect \B \wrpick_CR_full_cr_en_o - connect \Y $and$issuer_ls180.v:40732$1504_Y + attribute \src "libresoc.v:28976.3-29030.6" + process $proc$libresoc.v:28976$595 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:28977.5-28977.29" + switch \initial + attribute \src "libresoc.v:28977.9-28977.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40734$1506 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok - connect \B \fus_cu_busy_o - connect \Y $and$issuer_ls180.v:40734$1506_Y + attribute \src "libresoc.v:29031.3-29085.6" + process $proc$libresoc.v:29031$596 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:29032.5-29032.29" + switch \initial + attribute \src "libresoc.v:29032.9-29032.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40735$1507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o [1] - connect \B \fu_enable [0] - connect \Y $and$issuer_ls180.v:40735$1507_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40736$1508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$84 [2] - connect \B \fu_enable [1] - connect \Y $and$issuer_ls180.v:40736$1508_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40737$1509 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$90 [1] - connect \B \fu_enable [4] - connect \Y $and$issuer_ls180.v:40737$1509_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40738$1510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$96 [1] - connect \B \fu_enable [6] - connect \Y $and$issuer_ls180.v:40738$1510_Y + attribute \src "libresoc.v:29086.3-29140.6" + process $proc$libresoc.v:29086$597 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:29087.5-29087.29" + switch \initial + attribute \src "libresoc.v:29087.9-29087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'11001001 + case + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40739$1511 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$99 [1] - connect \B \fu_enable [7] - connect \Y $and$issuer_ls180.v:40739$1511_Y + attribute \src "libresoc.v:29141.3-29195.6" + process $proc$libresoc.v:29141$598 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:29142.5-29142.29" + switch \initial + attribute \src "libresoc.v:29142.9-29142.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40740$1512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$102 [1] - connect \B \fu_enable [8] - connect \Y $and$issuer_ls180.v:40740$1512_Y + attribute \src "libresoc.v:29196.3-29250.6" + process $proc$libresoc.v:29196$599 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:29197.5-29197.29" + switch \initial + attribute \src "libresoc.v:29197.9-29197.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40741$1513 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_CR_cr_a_o [0] - connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$issuer_ls180.v:40741$1513_Y + attribute \src "libresoc.v:29251.3-29305.6" + process $proc$libresoc.v:29251$600 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:29252.5-29252.29" + switch \initial + attribute \src "libresoc.v:29252.9-29252.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40743$1515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1222 - connect \B \$1226 - connect \Y $and$issuer_ls180.v:40743$1515_Y + attribute \src "libresoc.v:29306.3-29360.6" + process $proc$libresoc.v:29306$601 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:29307.5-29307.29" + switch \initial + attribute \src "libresoc.v:29307.9-29307.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + case + assign $1\dec31_dec_sub22_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40744$1516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1222 - connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$issuer_ls180.v:40744$1516_Y + attribute \src "libresoc.v:29361.3-29415.6" + process $proc$libresoc.v:29361$602 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:29362.5-29362.29" + switch \initial + attribute \src "libresoc.v:29362.9-29362.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40748$1520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$113 - connect \B \fus_cu_busy_o$5 - connect \Y $and$issuer_ls180.v:40748$1520_Y + attribute \src "libresoc.v:29416.3-29470.6" + process $proc$libresoc.v:29416$603 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:29417.5-29417.29" + switch \initial + attribute \src "libresoc.v:29417.9-29417.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0011100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + case + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40749$1521 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_CR_cr_a_o [1] - connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$issuer_ls180.v:40749$1521_Y + attribute \src "libresoc.v:29471.3-29525.6" + process $proc$libresoc.v:29471$604 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:29472.5-29472.29" + switch \initial + attribute \src "libresoc.v:29472.9-29472.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40751$1523 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1242 - connect \B \$1246 - connect \Y $and$issuer_ls180.v:40751$1523_Y + attribute \src "libresoc.v:29526.3-29580.6" + process $proc$libresoc.v:29526$605 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:29527.5-29527.29" + switch \initial + attribute \src "libresoc.v:29527.9-29527.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40752$1524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1242 - connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$issuer_ls180.v:40752$1524_Y + attribute \src "libresoc.v:29581.3-29635.6" + process $proc$libresoc.v:29581$606 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:29582.5-29582.29" + switch \initial + attribute \src "libresoc.v:29582.9-29582.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40756$1528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$114 - connect \B \fus_cu_busy_o$14 - connect \Y $and$issuer_ls180.v:40756$1528_Y + attribute \src "libresoc.v:29636.3-29690.6" + process $proc$libresoc.v:29636$607 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:29637.5-29637.29" + switch \initial + attribute \src "libresoc.v:29637.9-29637.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40757$1529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_CR_cr_a_o [2] - connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$issuer_ls180.v:40757$1529_Y + attribute \src "libresoc.v:29691.3-29745.6" + process $proc$libresoc.v:29691$608 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:29692.5-29692.29" + switch \initial + attribute \src "libresoc.v:29692.9-29692.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40759$1531 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1262 - connect \B \$1266 - connect \Y $and$issuer_ls180.v:40759$1531_Y + attribute \src "libresoc.v:29746.3-29800.6" + process $proc$libresoc.v:29746$609 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:29747.5-29747.29" + switch \initial + attribute \src "libresoc.v:29747.9-29747.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub22_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40760$1532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1262 - connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$issuer_ls180.v:40760$1532_Y + attribute \src "libresoc.v:29801.3-29855.6" + process $proc$libresoc.v:29801$610 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:29802.5-29802.29" + switch \initial + attribute \src "libresoc.v:29802.9-29802.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40764$1536 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$115 - connect \B \fus_cu_busy_o$20 - connect \Y $and$issuer_ls180.v:40764$1536_Y + attribute \src "libresoc.v:29856.3-29910.6" + process $proc$libresoc.v:29856$611 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:29857.5-29857.29" + switch \initial + attribute \src "libresoc.v:29857.9-29857.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40765$1537 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_CR_cr_a_o [3] - connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$issuer_ls180.v:40765$1537_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40767$1539 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1282 - connect \B \$1286 - connect \Y $and$issuer_ls180.v:40767$1539_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40768$1540 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1282 - connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$issuer_ls180.v:40768$1540_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40772$1544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$116 - connect \B \fus_cu_busy_o$23 - connect \Y $and$issuer_ls180.v:40772$1544_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40773$1545 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_CR_cr_a_o [4] - connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$issuer_ls180.v:40773$1545_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40775$1547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1302 - connect \B \$1306 - connect \Y $and$issuer_ls180.v:40775$1547_Y + attribute \src "libresoc.v:29911.3-29965.6" + process $proc$libresoc.v:29911$612 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:29912.5-29912.29" + switch \initial + attribute \src "libresoc.v:29912.9-29912.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40776$1548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1302 - connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$issuer_ls180.v:40776$1548_Y + attribute \src "libresoc.v:29966.3-30020.6" + process $proc$libresoc.v:29966$613 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_out_sel[1:0] $1\dec31_dec_sub22_out_sel[1:0] + attribute \src "libresoc.v:29967.5-29967.29" + switch \initial + attribute \src "libresoc.v:29967.9-29967.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_out_sel $0\dec31_dec_sub22_out_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40780$1552 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$117 - connect \B \fus_cu_busy_o$26 - connect \Y $and$issuer_ls180.v:40780$1552_Y + attribute \src "libresoc.v:30021.3-30075.6" + process $proc$libresoc.v:30021$614 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:30022.5-30022.29" + switch \initial + attribute \src "libresoc.v:30022.9-30022.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40781$1553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_CR_cr_a_o [5] - connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$issuer_ls180.v:40781$1553_Y + attribute \src "libresoc.v:30076.3-30130.6" + process $proc$libresoc.v:30076$615 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:30077.5-30077.29" + switch \initial + attribute \src "libresoc.v:30077.9-30077.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40783$1555 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1322 - connect \B \$1326 - connect \Y $and$issuer_ls180.v:40783$1555_Y + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:30136.1-31571.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub23" +attribute \generator "nMigen" +module \dec31_dec_sub23 + attribute \src "libresoc.v:30639.3-30687.6" + wire width 8 $0\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:30835.3-30883.6" + wire $0\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:31472.3-31520.6" + wire width 3 $0\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:31521.3-31569.6" + wire width 3 $0\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:30590.3-30638.6" + wire width 2 $0\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:30786.3-30834.6" + wire $0\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:31227.3-31275.6" + wire width 5 $0\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:30394.3-30442.6" + wire width 12 $0\dec31_dec_sub23_function_unit[11:0] + attribute \src "libresoc.v:31276.3-31324.6" + wire width 3 $0\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:31325.3-31373.6" + wire width 4 $0\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:31374.3-31422.6" + wire width 2 $0\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:30933.3-30981.6" + wire width 7 $0\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:30688.3-30736.6" + wire $0\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:30737.3-30785.6" + wire $0\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:31031.3-31079.6" + wire $0\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:30443.3-30491.6" + wire width 4 $0\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:31129.3-31177.6" + wire $0\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:31423.3-31471.6" + wire width 2 $0\dec31_dec_sub23_out_sel[1:0] + attribute \src "libresoc.v:30541.3-30589.6" + wire width 2 $0\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:30982.3-31030.6" + wire $0\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:31178.3-31226.6" + wire $0\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:31080.3-31128.6" + wire $0\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:30884.3-30932.6" + wire $0\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:30492.3-30540.6" + wire width 2 $0\dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:30137.7-30137.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:30639.3-30687.6" + wire width 8 $1\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:30835.3-30883.6" + wire $1\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:31472.3-31520.6" + wire width 3 $1\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:31521.3-31569.6" + wire width 3 $1\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:30590.3-30638.6" + wire width 2 $1\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:30786.3-30834.6" + wire $1\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:31227.3-31275.6" + wire width 5 $1\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:30394.3-30442.6" + wire width 12 $1\dec31_dec_sub23_function_unit[11:0] + attribute \src "libresoc.v:31276.3-31324.6" + wire width 3 $1\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:31325.3-31373.6" + wire width 4 $1\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:31374.3-31422.6" + wire width 2 $1\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:30933.3-30981.6" + wire width 7 $1\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:30688.3-30736.6" + wire $1\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:30737.3-30785.6" + wire $1\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:31031.3-31079.6" + wire $1\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:30443.3-30491.6" + wire width 4 $1\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:31129.3-31177.6" + wire $1\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:31423.3-31471.6" + wire width 2 $1\dec31_dec_sub23_out_sel[1:0] + attribute \src "libresoc.v:30541.3-30589.6" + wire width 2 $1\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:30982.3-31030.6" + wire $1\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:31178.3-31226.6" + wire $1\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:31080.3-31128.6" + wire $1\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:30884.3-30932.6" + wire $1\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:30492.3-30540.6" + wire width 2 $1\dec31_dec_sub23_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub23_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub23_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub23_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub23_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub23_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub23_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub23_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub23_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub23_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub23_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub23_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub23_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub23_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub23_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub23_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub23_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub23_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub23_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub23_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub23_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub23_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub23_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub23_upd + attribute \src "libresoc.v:30137.7-30137.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:30137.7-30137.20" + process $proc$libresoc.v:30137$641 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40784$1556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1322 - connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$issuer_ls180.v:40784$1556_Y + attribute \src "libresoc.v:30394.3-30442.6" + process $proc$libresoc.v:30394$617 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_function_unit[11:0] $1\dec31_dec_sub23_function_unit[11:0] + attribute \src "libresoc.v:30395.5-30395.29" + switch \initial + attribute \src "libresoc.v:30395.9-30395.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + case + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40798$1570 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_ca_ok - connect \B \fus_cu_busy_o - connect \Y $and$issuer_ls180.v:40798$1570_Y + attribute \src "libresoc.v:30443.3-30491.6" + process $proc$libresoc.v:30443$618 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:30444.5-30444.29" + switch \initial + attribute \src "libresoc.v:30444.9-30444.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + case + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40799$1571 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o [2] - connect \B \fu_enable [0] - connect \Y $and$issuer_ls180.v:40799$1571_Y + attribute \src "libresoc.v:30492.3-30540.6" + process $proc$libresoc.v:30492$619 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:30493.5-30493.29" + switch \initial + attribute \src "libresoc.v:30493.9-30493.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40800$1572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [5] - connect \B \fu_enable [5] - connect \Y $and$issuer_ls180.v:40800$1572_Y + attribute \src "libresoc.v:30541.3-30589.6" + process $proc$libresoc.v:30541$620 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:30542.5-30542.29" + switch \initial + attribute \src "libresoc.v:30542.9-30542.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40801$1573 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$102 [2] - connect \B \fu_enable [8] - connect \Y $and$issuer_ls180.v:40801$1573_Y + attribute \src "libresoc.v:30590.3-30638.6" + process $proc$libresoc.v:30590$621 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:30591.5-30591.29" + switch \initial + attribute \src "libresoc.v:30591.9-30591.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40802$1574 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ca_o [0] - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$issuer_ls180.v:40802$1574_Y + attribute \src "libresoc.v:30639.3-30687.6" + process $proc$libresoc.v:30639$622 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:30640.5-30640.29" + switch \initial + attribute \src "libresoc.v:30640.9-30640.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111101 + case + assign $1\dec31_dec_sub23_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40804$1576 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1369 - connect \B \$1373 - connect \Y $and$issuer_ls180.v:40804$1576_Y + attribute \src "libresoc.v:30688.3-30736.6" + process $proc$libresoc.v:30688$623 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:30689.5-30689.29" + switch \initial + attribute \src "libresoc.v:30689.9-30689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40805$1577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1369 - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$issuer_ls180.v:40805$1577_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40807$1579 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_ca_ok$123 - connect \B \fus_cu_busy_o$17 - connect \Y $and$issuer_ls180.v:40807$1579_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40808$1580 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ca_o [1] - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$issuer_ls180.v:40808$1580_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40810$1582 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1385 - connect \B \$1389 - connect \Y $and$issuer_ls180.v:40810$1582_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40811$1583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1385 - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$issuer_ls180.v:40811$1583_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40813$1585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_ca_ok$124 - connect \B \fus_cu_busy_o$26 - connect \Y $and$issuer_ls180.v:40813$1585_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40814$1586 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ca_o [2] - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$issuer_ls180.v:40814$1586_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40816$1588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1401 - connect \B \$1405 - connect \Y $and$issuer_ls180.v:40816$1588_Y + attribute \src "libresoc.v:30737.3-30785.6" + process $proc$libresoc.v:30737$624 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:30738.5-30738.29" + switch \initial + attribute \src "libresoc.v:30738.9-30738.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40817$1589 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1401 - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$issuer_ls180.v:40817$1589_Y + attribute \src "libresoc.v:30786.3-30834.6" + process $proc$libresoc.v:30786$625 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:30787.5-30787.29" + switch \initial + attribute \src "libresoc.v:30787.9-30787.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40824$1597 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_ov_ok - connect \B \fus_cu_busy_o - connect \Y $and$issuer_ls180.v:40824$1597_Y + attribute \src "libresoc.v:30835.3-30883.6" + process $proc$libresoc.v:30835$626 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:30836.5-30836.29" + switch \initial + attribute \src "libresoc.v:30836.9-30836.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + case + assign $1\dec31_dec_sub23_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40825$1598 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o [3] - connect \B \fu_enable [0] - connect \Y $and$issuer_ls180.v:40825$1598_Y + attribute \src "libresoc.v:30884.3-30932.6" + process $proc$libresoc.v:30884$627 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:30885.5-30885.29" + switch \initial + attribute \src "libresoc.v:30885.9-30885.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40826$1599 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [4] - connect \B \fu_enable [5] - connect \Y $and$issuer_ls180.v:40826$1599_Y + attribute \src "libresoc.v:30933.3-30981.6" + process $proc$libresoc.v:30933$628 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:30934.5-30934.29" + switch \initial + attribute \src "libresoc.v:30934.9-30934.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40827$1600 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$96 [2] - connect \B \fu_enable [6] - connect \Y $and$issuer_ls180.v:40827$1600_Y + attribute \src "libresoc.v:30982.3-31030.6" + process $proc$libresoc.v:30982$629 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:30983.5-30983.29" + switch \initial + attribute \src "libresoc.v:30983.9-30983.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40828$1601 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$99 [2] - connect \B \fu_enable [7] - connect \Y $and$issuer_ls180.v:40828$1601_Y + attribute \src "libresoc.v:31031.3-31079.6" + process $proc$libresoc.v:31031$630 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:31032.5-31032.29" + switch \initial + attribute \src "libresoc.v:31032.9-31032.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40829$1602 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ov_o [0] - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$issuer_ls180.v:40829$1602_Y + attribute \src "libresoc.v:31080.3-31128.6" + process $proc$libresoc.v:31080$631 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:31081.5-31081.29" + switch \initial + attribute \src "libresoc.v:31081.9-31081.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40831$1604 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1435 - connect \B \$1439 - connect \Y $and$issuer_ls180.v:40831$1604_Y + attribute \src "libresoc.v:31129.3-31177.6" + process $proc$libresoc.v:31129$632 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:31130.5-31130.29" + switch \initial + attribute \src "libresoc.v:31130.9-31130.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40832$1605 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1435 - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$issuer_ls180.v:40832$1605_Y + attribute \src "libresoc.v:31178.3-31226.6" + process $proc$libresoc.v:31178$633 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:31179.5-31179.29" + switch \initial + attribute \src "libresoc.v:31179.9-31179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40834$1607 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_ov_ok$127 - connect \B \fus_cu_busy_o$17 - connect \Y $and$issuer_ls180.v:40834$1607_Y + attribute \src "libresoc.v:31227.3-31275.6" + process $proc$libresoc.v:31227$634 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:31228.5-31228.29" + switch \initial + attribute \src "libresoc.v:31228.9-31228.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub23_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40835$1608 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ov_o [1] - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$issuer_ls180.v:40835$1608_Y + attribute \src "libresoc.v:31276.3-31324.6" + process $proc$libresoc.v:31276$635 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:31277.5-31277.29" + switch \initial + attribute \src "libresoc.v:31277.9-31277.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40837$1610 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1451 - connect \B \$1455 - connect \Y $and$issuer_ls180.v:40837$1610_Y + attribute \src "libresoc.v:31325.3-31373.6" + process $proc$libresoc.v:31325$636 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:31326.5-31326.29" + switch \initial + attribute \src "libresoc.v:31326.9-31326.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40838$1611 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1451 - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$issuer_ls180.v:40838$1611_Y + attribute \src "libresoc.v:31374.3-31422.6" + process $proc$libresoc.v:31374$637 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:31375.5-31375.29" + switch \initial + attribute \src "libresoc.v:31375.9-31375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40840$1613 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_ov_ok$128 - connect \B \fus_cu_busy_o$20 - connect \Y $and$issuer_ls180.v:40840$1613_Y + attribute \src "libresoc.v:31423.3-31471.6" + process $proc$libresoc.v:31423$638 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_out_sel[1:0] $1\dec31_dec_sub23_out_sel[1:0] + attribute \src "libresoc.v:31424.5-31424.29" + switch \initial + attribute \src "libresoc.v:31424.9-31424.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_out_sel $0\dec31_dec_sub23_out_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40841$1614 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ov_o [2] - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$issuer_ls180.v:40841$1614_Y + attribute \src "libresoc.v:31472.3-31520.6" + process $proc$libresoc.v:31472$639 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:31473.5-31473.29" + switch \initial + attribute \src "libresoc.v:31473.9-31473.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40843$1616 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1467 - connect \B \$1471 - connect \Y $and$issuer_ls180.v:40843$1616_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40844$1617 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1467 - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$issuer_ls180.v:40844$1617_Y + attribute \src "libresoc.v:31521.3-31569.6" + process $proc$libresoc.v:31521$640 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:31522.5-31522.29" + switch \initial + attribute \src "libresoc.v:31522.9-31522.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40846$1619 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_ov_ok$129 - connect \B \fus_cu_busy_o$23 - connect \Y $and$issuer_ls180.v:40846$1619_Y + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:31575.1-32290.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub24" +attribute \generator "nMigen" +module \dec31_dec_sub24 + attribute \src "libresoc.v:31928.3-31946.6" + wire width 8 $0\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:32004.3-32022.6" + wire $0\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:32251.3-32269.6" + wire width 3 $0\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:32270.3-32288.6" + wire width 3 $0\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:31909.3-31927.6" + wire width 2 $0\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:31985.3-32003.6" + wire $0\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:32156.3-32174.6" + wire width 5 $0\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:31833.3-31851.6" + wire width 12 $0\dec31_dec_sub24_function_unit[11:0] + attribute \src "libresoc.v:32175.3-32193.6" + wire width 3 $0\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:32194.3-32212.6" + wire width 4 $0\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:32213.3-32231.6" + wire width 2 $0\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:32042.3-32060.6" + wire width 7 $0\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:31947.3-31965.6" + wire $0\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:31966.3-31984.6" + wire $0\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:32080.3-32098.6" + wire $0\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:31852.3-31870.6" + wire width 4 $0\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:32118.3-32136.6" + wire $0\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:32232.3-32250.6" + wire width 2 $0\dec31_dec_sub24_out_sel[1:0] + attribute \src "libresoc.v:31890.3-31908.6" + wire width 2 $0\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:32061.3-32079.6" + wire $0\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:32137.3-32155.6" + wire $0\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:32099.3-32117.6" + wire $0\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:32023.3-32041.6" + wire $0\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:31871.3-31889.6" + wire width 2 $0\dec31_dec_sub24_upd[1:0] + attribute \src "libresoc.v:31576.7-31576.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31928.3-31946.6" + wire width 8 $1\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:32004.3-32022.6" + wire $1\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:32251.3-32269.6" + wire width 3 $1\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:32270.3-32288.6" + wire width 3 $1\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:31909.3-31927.6" + wire width 2 $1\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:31985.3-32003.6" + wire $1\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:32156.3-32174.6" + wire width 5 $1\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:31833.3-31851.6" + wire width 12 $1\dec31_dec_sub24_function_unit[11:0] + attribute \src "libresoc.v:32175.3-32193.6" + wire width 3 $1\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:32194.3-32212.6" + wire width 4 $1\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:32213.3-32231.6" + wire width 2 $1\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:32042.3-32060.6" + wire width 7 $1\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:31947.3-31965.6" + wire $1\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:31966.3-31984.6" + wire $1\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:32080.3-32098.6" + wire $1\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:31852.3-31870.6" + wire width 4 $1\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:32118.3-32136.6" + wire $1\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:32232.3-32250.6" + wire width 2 $1\dec31_dec_sub24_out_sel[1:0] + attribute \src "libresoc.v:31890.3-31908.6" + wire width 2 $1\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:32061.3-32079.6" + wire $1\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:32137.3-32155.6" + wire $1\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:32099.3-32117.6" + wire $1\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:32023.3-32041.6" + wire $1\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:31871.3-31889.6" + wire width 2 $1\dec31_dec_sub24_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub24_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub24_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub24_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub24_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub24_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub24_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub24_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub24_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub24_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub24_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub24_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub24_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub24_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub24_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub24_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub24_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub24_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub24_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub24_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub24_upd + attribute \src "libresoc.v:31576.7-31576.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:31576.7-31576.20" + process $proc$libresoc.v:31576$666 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40847$1620 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ov_o [3] - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$issuer_ls180.v:40847$1620_Y + attribute \src "libresoc.v:31833.3-31851.6" + process $proc$libresoc.v:31833$642 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_function_unit[11:0] $1\dec31_dec_sub24_function_unit[11:0] + attribute \src "libresoc.v:31834.5-31834.29" + switch \initial + attribute \src "libresoc.v:31834.9-31834.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + case + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40849$1622 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1483 - connect \B \$1487 - connect \Y $and$issuer_ls180.v:40849$1622_Y + attribute \src "libresoc.v:31852.3-31870.6" + process $proc$libresoc.v:31852$643 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:31853.5-31853.29" + switch \initial + attribute \src "libresoc.v:31853.9-31853.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40850$1623 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1483 - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$issuer_ls180.v:40850$1623_Y + attribute \src "libresoc.v:31871.3-31889.6" + process $proc$libresoc.v:31871$644 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] + attribute \src "libresoc.v:31872.5-31872.29" + switch \initial + attribute \src "libresoc.v:31872.9-31872.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40858$1631 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_so_ok - connect \B \fus_cu_busy_o - connect \Y $and$issuer_ls180.v:40858$1631_Y + attribute \src "libresoc.v:31890.3-31908.6" + process $proc$libresoc.v:31890$645 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:31891.5-31891.29" + switch \initial + attribute \src "libresoc.v:31891.9-31891.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40859$1632 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o [4] - connect \B \fu_enable [0] - connect \Y $and$issuer_ls180.v:40859$1632_Y + attribute \src "libresoc.v:31909.3-31927.6" + process $proc$libresoc.v:31909$646 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:31910.5-31910.29" + switch \initial + attribute \src "libresoc.v:31910.9-31910.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40860$1633 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [3] - connect \B \fu_enable [5] - connect \Y $and$issuer_ls180.v:40860$1633_Y + attribute \src "libresoc.v:31928.3-31946.6" + process $proc$libresoc.v:31928$647 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:31929.5-31929.29" + switch \initial + attribute \src "libresoc.v:31929.9-31929.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100101 + case + assign $1\dec31_dec_sub24_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40861$1634 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$96 [3] - connect \B \fu_enable [6] - connect \Y $and$issuer_ls180.v:40861$1634_Y + attribute \src "libresoc.v:31947.3-31965.6" + process $proc$libresoc.v:31947$648 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:31948.5-31948.29" + switch \initial + attribute \src "libresoc.v:31948.9-31948.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40862$1635 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$99 [3] - connect \B \fu_enable [7] - connect \Y $and$issuer_ls180.v:40862$1635_Y + attribute \src "libresoc.v:31966.3-31984.6" + process $proc$libresoc.v:31966$649 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:31967.5-31967.29" + switch \initial + attribute \src "libresoc.v:31967.9-31967.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40863$1636 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_so_o [0] - connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$issuer_ls180.v:40863$1636_Y + attribute \src "libresoc.v:31985.3-32003.6" + process $proc$libresoc.v:31985$650 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:31986.5-31986.29" + switch \initial + attribute \src "libresoc.v:31986.9-31986.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40865$1638 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1519 - connect \B \$1523 - connect \Y $and$issuer_ls180.v:40865$1638_Y + attribute \src "libresoc.v:32004.3-32022.6" + process $proc$libresoc.v:32004$651 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:32005.5-32005.29" + switch \initial + attribute \src "libresoc.v:32005.9-32005.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + case + assign $1\dec31_dec_sub24_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40866$1639 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1519 - connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$issuer_ls180.v:40866$1639_Y + attribute \src "libresoc.v:32023.3-32041.6" + process $proc$libresoc.v:32023$652 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:32024.5-32024.29" + switch \initial + attribute \src "libresoc.v:32024.9-32024.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40868$1641 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_so_ok$132 - connect \B \fus_cu_busy_o$17 - connect \Y $and$issuer_ls180.v:40868$1641_Y + attribute \src "libresoc.v:32042.3-32060.6" + process $proc$libresoc.v:32042$653 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:32043.5-32043.29" + switch \initial + attribute \src "libresoc.v:32043.9-32043.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + case + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40869$1642 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_so_o [1] - connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$issuer_ls180.v:40869$1642_Y + attribute \src "libresoc.v:32061.3-32079.6" + process $proc$libresoc.v:32061$654 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:32062.5-32062.29" + switch \initial + attribute \src "libresoc.v:32062.9-32062.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40871$1644 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1535 - connect \B \$1539 - connect \Y $and$issuer_ls180.v:40871$1644_Y + attribute \src "libresoc.v:32080.3-32098.6" + process $proc$libresoc.v:32080$655 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:32081.5-32081.29" + switch \initial + attribute \src "libresoc.v:32081.9-32081.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub24_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40872$1645 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1535 - connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$issuer_ls180.v:40872$1645_Y + attribute \src "libresoc.v:32099.3-32117.6" + process $proc$libresoc.v:32099$656 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:32100.5-32100.29" + switch \initial + attribute \src "libresoc.v:32100.9-32100.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40874$1647 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_so_ok$133 - connect \B \fus_cu_busy_o$20 - connect \Y $and$issuer_ls180.v:40874$1647_Y + attribute \src "libresoc.v:32118.3-32136.6" + process $proc$libresoc.v:32118$657 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:32119.5-32119.29" + switch \initial + attribute \src "libresoc.v:32119.9-32119.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40875$1648 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_so_o [2] - connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$issuer_ls180.v:40875$1648_Y + attribute \src "libresoc.v:32137.3-32155.6" + process $proc$libresoc.v:32137$658 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:32138.5-32138.29" + switch \initial + attribute \src "libresoc.v:32138.9-32138.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40877$1650 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1551 - connect \B \$1555 - connect \Y $and$issuer_ls180.v:40877$1650_Y + attribute \src "libresoc.v:32156.3-32174.6" + process $proc$libresoc.v:32156$659 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:32157.5-32157.29" + switch \initial + attribute \src "libresoc.v:32157.9-32157.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub24_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40878$1651 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1551 - connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$issuer_ls180.v:40878$1651_Y + attribute \src "libresoc.v:32175.3-32193.6" + process $proc$libresoc.v:32175$660 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:32176.5-32176.29" + switch \initial + attribute \src "libresoc.v:32176.9-32176.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40880$1653 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_so_ok$134 - connect \B \fus_cu_busy_o$23 - connect \Y $and$issuer_ls180.v:40880$1653_Y + attribute \src "libresoc.v:32194.3-32212.6" + process $proc$libresoc.v:32194$661 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:32195.5-32195.29" + switch \initial + attribute \src "libresoc.v:32195.9-32195.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40881$1654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_so_o [3] - connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$issuer_ls180.v:40881$1654_Y + attribute \src "libresoc.v:32213.3-32231.6" + process $proc$libresoc.v:32213$662 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:32214.5-32214.29" + switch \initial + attribute \src "libresoc.v:32214.9-32214.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40883$1656 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1567 - connect \B \$1571 - connect \Y $and$issuer_ls180.v:40883$1656_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40884$1657 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1567 - connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$issuer_ls180.v:40884$1657_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40894$1669 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_fast1_ok - connect \B \fus_cu_busy_o$8 - connect \Y $and$issuer_ls180.v:40894$1669_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40895$1670 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$139 [0] - connect \B \fu_enable [2] - connect \Y $and$issuer_ls180.v:40895$1670_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40896$1671 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$87 [1] - connect \B \fu_enable [3] - connect \Y $and$issuer_ls180.v:40896$1671_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40897$1672 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [2] - connect \B \fu_enable [5] - connect \Y $and$issuer_ls180.v:40897$1672_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40898$1673 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$139 [1] - connect \B \fu_enable [2] - connect \Y $and$issuer_ls180.v:40898$1673_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40899$1674 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$87 [2] - connect \B \fu_enable [3] - connect \Y $and$issuer_ls180.v:40899$1674_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40900$1675 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_FAST_fast1_o [0] - connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$issuer_ls180.v:40900$1675_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40902$1677 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1609 - connect \B \$1614 - connect \Y $and$issuer_ls180.v:40902$1677_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $and $and$issuer_ls180.v:40903$1678 - parameter \A_SIGNED 0 - parameter \A_WIDTH 12 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 12 - connect \A \core_core_fn_unit - connect \B 2'10 - connect \Y $and$issuer_ls180.v:40903$1678_Y + attribute \src "libresoc.v:32232.3-32250.6" + process $proc$libresoc.v:32232$663 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_out_sel[1:0] $1\dec31_dec_sub24_out_sel[1:0] + attribute \src "libresoc.v:32233.5-32233.29" + switch \initial + attribute \src "libresoc.v:32233.9-32233.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub24_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_out_sel $0\dec31_dec_sub24_out_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40904$1679 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1609 - connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$issuer_ls180.v:40904$1679_Y + attribute \src "libresoc.v:32251.3-32269.6" + process $proc$libresoc.v:32251$664 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:32252.5-32252.29" + switch \initial + attribute \src "libresoc.v:32252.9-32252.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40906$1681 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_fast1_ok$141 - connect \B \fus_cu_busy_o$11 - connect \Y $and$issuer_ls180.v:40906$1681_Y + attribute \src "libresoc.v:32270.3-32288.6" + process $proc$libresoc.v:32270$665 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:32271.5-32271.29" + switch \initial + attribute \src "libresoc.v:32271.9-32271.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub24_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40908$1683 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_FAST_fast1_o [1] - connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$issuer_ls180.v:40908$1683_Y + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:32294.1-33801.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub26" +attribute \generator "nMigen" +module \dec31_dec_sub26 + attribute \src "libresoc.v:32812.3-32863.6" + wire width 8 $0\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:33020.3-33071.6" + wire $0\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:33696.3-33747.6" + wire width 3 $0\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:33748.3-33799.6" + wire width 3 $0\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:32760.3-32811.6" + wire width 2 $0\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:32968.3-33019.6" + wire $0\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:33436.3-33487.6" + wire width 5 $0\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:32552.3-32603.6" + wire width 12 $0\dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:33488.3-33539.6" + wire width 3 $0\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:33540.3-33591.6" + wire width 4 $0\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:33592.3-33643.6" + wire width 2 $0\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:33124.3-33175.6" + wire width 7 $0\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:32864.3-32915.6" + wire $0\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:32916.3-32967.6" + wire $0\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:33228.3-33279.6" + wire $0\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:32604.3-32655.6" + wire width 4 $0\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:33332.3-33383.6" + wire $0\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:33644.3-33695.6" + wire width 2 $0\dec31_dec_sub26_out_sel[1:0] + attribute \src "libresoc.v:32708.3-32759.6" + wire width 2 $0\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:33176.3-33227.6" + wire $0\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:33384.3-33435.6" + wire $0\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:33280.3-33331.6" + wire $0\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:33072.3-33123.6" + wire $0\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:32656.3-32707.6" + wire width 2 $0\dec31_dec_sub26_upd[1:0] + attribute \src "libresoc.v:32295.7-32295.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:32812.3-32863.6" + wire width 8 $1\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:33020.3-33071.6" + wire $1\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:33696.3-33747.6" + wire width 3 $1\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:33748.3-33799.6" + wire width 3 $1\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:32760.3-32811.6" + wire width 2 $1\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:32968.3-33019.6" + wire $1\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:33436.3-33487.6" + wire width 5 $1\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:32552.3-32603.6" + wire width 12 $1\dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:33488.3-33539.6" + wire width 3 $1\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:33540.3-33591.6" + wire width 4 $1\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:33592.3-33643.6" + wire width 2 $1\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:33124.3-33175.6" + wire width 7 $1\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:32864.3-32915.6" + wire $1\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:32916.3-32967.6" + wire $1\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:33228.3-33279.6" + wire $1\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:32604.3-32655.6" + wire width 4 $1\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:33332.3-33383.6" + wire $1\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:33644.3-33695.6" + wire width 2 $1\dec31_dec_sub26_out_sel[1:0] + attribute \src "libresoc.v:32708.3-32759.6" + wire width 2 $1\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:33176.3-33227.6" + wire $1\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:33384.3-33435.6" + wire $1\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:33280.3-33331.6" + wire $1\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:33072.3-33123.6" + wire $1\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:32656.3-32707.6" + wire width 2 $1\dec31_dec_sub26_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub26_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub26_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub26_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub26_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub26_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub26_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub26_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub26_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub26_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub26_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub26_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub26_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub26_upd + attribute \src "libresoc.v:32295.7-32295.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:32295.7-32295.20" + process $proc$libresoc.v:32295$691 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40910$1685 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1628 - connect \B \$1632 - connect \Y $and$issuer_ls180.v:40910$1685_Y + attribute \src "libresoc.v:32552.3-32603.6" + process $proc$libresoc.v:32552$667 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_function_unit[11:0] $1\dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:32553.5-32553.29" + switch \initial + attribute \src "libresoc.v:32553.9-32553.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 + case + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40911$1686 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1628 - connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$issuer_ls180.v:40911$1686_Y + attribute \src "libresoc.v:32604.3-32655.6" + process $proc$libresoc.v:32604$668 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:32605.5-32605.29" + switch \initial + attribute \src "libresoc.v:32605.9-32605.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40913$1688 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_fast1_ok$142 - connect \B \fus_cu_busy_o$17 - connect \Y $and$issuer_ls180.v:40913$1688_Y + attribute \src "libresoc.v:32656.3-32707.6" + process $proc$libresoc.v:32656$669 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] + attribute \src "libresoc.v:32657.5-32657.29" + switch \initial + attribute \src "libresoc.v:32657.9-32657.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40914$1689 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_FAST_fast1_o [2] - connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$issuer_ls180.v:40914$1689_Y + attribute \src "libresoc.v:32708.3-32759.6" + process $proc$libresoc.v:32708$670 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:32709.5-32709.29" + switch \initial + attribute \src "libresoc.v:32709.9-32709.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40916$1691 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1644 - connect \B \$1648 - connect \Y $and$issuer_ls180.v:40916$1691_Y + attribute \src "libresoc.v:32760.3-32811.6" + process $proc$libresoc.v:32760$671 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:32761.5-32761.29" + switch \initial + attribute \src "libresoc.v:32761.9-32761.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40917$1692 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1644 - connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$issuer_ls180.v:40917$1692_Y + attribute \src "libresoc.v:32812.3-32863.6" + process $proc$libresoc.v:32812$672 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:32813.5-32813.29" + switch \initial + attribute \src "libresoc.v:32813.9-32813.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100001 + case + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40919$1694 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_fast2_ok - connect \B \fus_cu_busy_o$8 - connect \Y $and$issuer_ls180.v:40919$1694_Y + attribute \src "libresoc.v:32864.3-32915.6" + process $proc$libresoc.v:32864$673 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:32865.5-32865.29" + switch \initial + attribute \src "libresoc.v:32865.9-32865.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $and $and$issuer_ls180.v:40920$1695 - parameter \A_SIGNED 0 - parameter \A_WIDTH 12 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 12 - connect \A \core_core_fn_unit - connect \B 7'1000000 - connect \Y $and$issuer_ls180.v:40920$1695_Y + attribute \src "libresoc.v:32916.3-32967.6" + process $proc$libresoc.v:32916$674 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:32917.5-32917.29" + switch \initial + attribute \src "libresoc.v:32917.9-32917.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40921$1696 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_FAST_fast1_o [3] - connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$issuer_ls180.v:40921$1696_Y + attribute \src "libresoc.v:32968.3-33019.6" + process $proc$libresoc.v:32968$675 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:32969.5-32969.29" + switch \initial + attribute \src "libresoc.v:32969.9-32969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40923$1698 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1660 - connect \B \$1664 - connect \Y $and$issuer_ls180.v:40923$1698_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40925$1700 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1660 - connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$issuer_ls180.v:40925$1700_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40927$1702 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_fast2_ok$143 - connect \B \fus_cu_busy_o$11 - connect \Y $and$issuer_ls180.v:40927$1702_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40928$1703 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_FAST_fast1_o [4] - connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$issuer_ls180.v:40928$1703_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40930$1705 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1676 - connect \B \$1680 - connect \Y $and$issuer_ls180.v:40930$1705_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40931$1706 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1676 - connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$issuer_ls180.v:40931$1706_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $and $and$issuer_ls180.v:40938$1713 - parameter \A_SIGNED 0 - parameter \A_WIDTH 12 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 12 - connect \A \core_core_fn_unit - connect \B 6'100000 - connect \Y $and$issuer_ls180.v:40938$1713_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40947$1722 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_nia_ok - connect \B \fus_cu_busy_o$8 - connect \Y $and$issuer_ls180.v:40947$1722_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40948$1723 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$139 [2] - connect \B \fu_enable [2] - connect \Y $and$issuer_ls180.v:40948$1723_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40949$1724 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$87 [3] - connect \B \fu_enable [3] - connect \Y $and$issuer_ls180.v:40949$1724_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40950$1725 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_STATE_nia_o [0] - connect \B \wrpick_STATE_nia_en_o - connect \Y $and$issuer_ls180.v:40950$1725_Y + attribute \src "libresoc.v:33020.3-33071.6" + process $proc$libresoc.v:33020$676 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:33021.5-33021.29" + switch \initial + attribute \src "libresoc.v:33021.9-33021.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + case + assign $1\dec31_dec_sub26_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40952$1727 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1720 - connect \B \$1724 - connect \Y $and$issuer_ls180.v:40952$1727_Y + attribute \src "libresoc.v:33072.3-33123.6" + process $proc$libresoc.v:33072$677 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:33073.5-33073.29" + switch \initial + attribute \src "libresoc.v:33073.9-33073.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40953$1728 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1720 - connect \B \wrpick_STATE_nia_en_o - connect \Y $and$issuer_ls180.v:40953$1728_Y + attribute \src "libresoc.v:33124.3-33175.6" + process $proc$libresoc.v:33124$678 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:33125.5-33125.29" + switch \initial + attribute \src "libresoc.v:33125.9-33125.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 + case + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40955$1730 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_nia_ok$149 - connect \B \fus_cu_busy_o$11 - connect \Y $and$issuer_ls180.v:40955$1730_Y + attribute \src "libresoc.v:33176.3-33227.6" + process $proc$libresoc.v:33176$679 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:33177.5-33177.29" + switch \initial + attribute \src "libresoc.v:33177.9-33177.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40956$1731 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_STATE_nia_o [1] - connect \B \wrpick_STATE_nia_en_o - connect \Y $and$issuer_ls180.v:40956$1731_Y + attribute \src "libresoc.v:33228.3-33279.6" + process $proc$libresoc.v:33228$680 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:33229.5-33229.29" + switch \initial + attribute \src "libresoc.v:33229.9-33229.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $and $and$issuer_ls180.v:40957$1732 - parameter \A_SIGNED 0 - parameter \A_WIDTH 12 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 12 - connect \A \core_core_fn_unit - connect \B 8'10000000 - connect \Y $and$issuer_ls180.v:40957$1732_Y + attribute \src "libresoc.v:33280.3-33331.6" + process $proc$libresoc.v:33280$681 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:33281.5-33281.29" + switch \initial + attribute \src "libresoc.v:33281.9-33281.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'1 + case + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40959$1734 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1736 - connect \B \$1740 - connect \Y $and$issuer_ls180.v:40959$1734_Y + attribute \src "libresoc.v:33332.3-33383.6" + process $proc$libresoc.v:33332$682 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:33333.5-33333.29" + switch \initial + attribute \src "libresoc.v:33333.9-33333.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40960$1735 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1736 - connect \B \wrpick_STATE_nia_en_o - connect \Y $and$issuer_ls180.v:40960$1735_Y + attribute \src "libresoc.v:33384.3-33435.6" + process $proc$libresoc.v:33384$683 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:33385.5-33385.29" + switch \initial + attribute \src "libresoc.v:33385.9-33385.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40966$1742 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_msr_ok - connect \B \fus_cu_busy_o$11 - connect \Y $and$issuer_ls180.v:40966$1742_Y + attribute \src "libresoc.v:33436.3-33487.6" + process $proc$libresoc.v:33436$684 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:33437.5-33437.29" + switch \initial + attribute \src "libresoc.v:33437.9-33437.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'10000 + case + assign $1\dec31_dec_sub26_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40967$1743 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$87 [4] - connect \B \fu_enable [3] - connect \Y $and$issuer_ls180.v:40967$1743_Y + attribute \src "libresoc.v:33488.3-33539.6" + process $proc$libresoc.v:33488$685 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:33489.5-33489.29" + switch \initial + attribute \src "libresoc.v:33489.9-33489.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40968$1744 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_STATE_msr_o - connect \B \wrpick_STATE_msr_en_o - connect \Y $and$issuer_ls180.v:40968$1744_Y + attribute \src "libresoc.v:33540.3-33591.6" + process $proc$libresoc.v:33540$686 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:33541.5-33541.29" + switch \initial + attribute \src "libresoc.v:33541.9-33541.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 + case + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40970$1746 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1760 - connect \B \$1764 - connect \Y $and$issuer_ls180.v:40970$1746_Y + attribute \src "libresoc.v:33592.3-33643.6" + process $proc$libresoc.v:33592$687 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:33593.5-33593.29" + switch \initial + attribute \src "libresoc.v:33593.9-33593.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40971$1747 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1760 - connect \B \wrpick_STATE_msr_en_o - connect \Y $and$issuer_ls180.v:40971$1747_Y + attribute \src "libresoc.v:33644.3-33695.6" + process $proc$libresoc.v:33644$688 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_out_sel[1:0] $1\dec31_dec_sub26_out_sel[1:0] + attribute \src "libresoc.v:33645.5-33645.29" + switch \initial + attribute \src "libresoc.v:33645.9-33645.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub26_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_out_sel $0\dec31_dec_sub26_out_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:40974$1751 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_spr1_ok - connect \B \fus_cu_busy_o$17 - connect \Y $and$issuer_ls180.v:40974$1751_Y + attribute \src "libresoc.v:33696.3-33747.6" + process $proc$libresoc.v:33696$689 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:33697.5-33697.29" + switch \initial + attribute \src "libresoc.v:33697.9-33697.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:40975$1752 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [1] - connect \B \fu_enable [5] - connect \Y $and$issuer_ls180.v:40975$1752_Y + attribute \src "libresoc.v:33748.3-33799.6" + process $proc$libresoc.v:33748$690 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:33749.5-33749.29" + switch \initial + attribute \src "libresoc.v:33749.9-33749.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $and $and$issuer_ls180.v:40976$1753 - parameter \A_SIGNED 0 - parameter \A_WIDTH 12 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 12 - connect \A \core_core_fn_unit - connect \B 5'10000 - connect \Y $and$issuer_ls180.v:40976$1753_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:40977$1754 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_SPR_spr1_o - connect \B \wrpick_SPR_spr1_en_o - connect \Y $and$issuer_ls180.v:40977$1754_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:40979$1756 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1780 - connect \B \$1784 - connect \Y $and$issuer_ls180.v:40979$1756_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:40981$1758 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1780 - connect \B \wrpick_SPR_spr1_en_o - connect \Y $and$issuer_ls180.v:40981$1758_Y + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:33805.1-34520.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub27" +attribute \generator "nMigen" +module \dec31_dec_sub27 + attribute \src "libresoc.v:34158.3-34176.6" + wire width 8 $0\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:34234.3-34252.6" + wire $0\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:34481.3-34499.6" + wire width 3 $0\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:34500.3-34518.6" + wire width 3 $0\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:34139.3-34157.6" + wire width 2 $0\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:34215.3-34233.6" + wire $0\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:34386.3-34404.6" + wire width 5 $0\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:34063.3-34081.6" + wire width 12 $0\dec31_dec_sub27_function_unit[11:0] + attribute \src "libresoc.v:34405.3-34423.6" + wire width 3 $0\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:34424.3-34442.6" + wire width 4 $0\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:34443.3-34461.6" + wire width 2 $0\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:34272.3-34290.6" + wire width 7 $0\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:34177.3-34195.6" + wire $0\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:34196.3-34214.6" + wire $0\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:34310.3-34328.6" + wire $0\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:34082.3-34100.6" + wire width 4 $0\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:34348.3-34366.6" + wire $0\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:34462.3-34480.6" + wire width 2 $0\dec31_dec_sub27_out_sel[1:0] + attribute \src "libresoc.v:34120.3-34138.6" + wire width 2 $0\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:34291.3-34309.6" + wire $0\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:34367.3-34385.6" + wire $0\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:34329.3-34347.6" + wire $0\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:34253.3-34271.6" + wire $0\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:34101.3-34119.6" + wire width 2 $0\dec31_dec_sub27_upd[1:0] + attribute \src "libresoc.v:33806.7-33806.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:34158.3-34176.6" + wire width 8 $1\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:34234.3-34252.6" + wire $1\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:34481.3-34499.6" + wire width 3 $1\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:34500.3-34518.6" + wire width 3 $1\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:34139.3-34157.6" + wire width 2 $1\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:34215.3-34233.6" + wire $1\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:34386.3-34404.6" + wire width 5 $1\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:34063.3-34081.6" + wire width 12 $1\dec31_dec_sub27_function_unit[11:0] + attribute \src "libresoc.v:34405.3-34423.6" + wire width 3 $1\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:34424.3-34442.6" + wire width 4 $1\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:34443.3-34461.6" + wire width 2 $1\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:34272.3-34290.6" + wire width 7 $1\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:34177.3-34195.6" + wire $1\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:34196.3-34214.6" + wire $1\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:34310.3-34328.6" + wire $1\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:34082.3-34100.6" + wire width 4 $1\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:34348.3-34366.6" + wire $1\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:34462.3-34480.6" + wire width 2 $1\dec31_dec_sub27_out_sel[1:0] + attribute \src "libresoc.v:34120.3-34138.6" + wire width 2 $1\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:34291.3-34309.6" + wire $1\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:34367.3-34385.6" + wire $1\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:34329.3-34347.6" + wire $1\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:34253.3-34271.6" + wire $1\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:34101.3-34119.6" + wire width 2 $1\dec31_dec_sub27_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub27_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub27_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub27_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub27_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub27_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub27_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub27_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub27_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub27_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub27_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub27_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub27_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub27_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub27_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub27_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub27_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub27_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub27_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub27_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub27_upd + attribute \src "libresoc.v:33806.7-33806.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:33806.7-33806.20" + process $proc$libresoc.v:33806$716 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $and $and$issuer_ls180.v:40983$1760 - parameter \A_SIGNED 0 - parameter \A_WIDTH 12 - parameter \B_SIGNED 0 - parameter \B_WIDTH 11 - parameter \Y_WIDTH 12 - connect \A \core_core_fn_unit - connect \B 11'10000000000 - connect \Y $and$issuer_ls180.v:40983$1760_Y + attribute \src "libresoc.v:34063.3-34081.6" + process $proc$libresoc.v:34063$692 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_function_unit[11:0] $1\dec31_dec_sub27_function_unit[11:0] + attribute \src "libresoc.v:34064.5-34064.29" + switch \initial + attribute \src "libresoc.v:34064.9-34064.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + case + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $and $and$issuer_ls180.v:40985$1762 - parameter \A_SIGNED 0 - parameter \A_WIDTH 12 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 12 - connect \A \core_core_fn_unit - connect \B 10'1000000000 - connect \Y $and$issuer_ls180.v:40985$1762_Y + attribute \src "libresoc.v:34082.3-34100.6" + process $proc$libresoc.v:34082$693 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:34083.5-34083.29" + switch \initial + attribute \src "libresoc.v:34083.9-34083.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $and $and$issuer_ls180.v:40987$1764 - parameter \A_SIGNED 0 - parameter \A_WIDTH 12 - parameter \B_SIGNED 0 - parameter \B_WIDTH 9 - parameter \Y_WIDTH 12 - connect \A \core_core_fn_unit - connect \B 9'100000000 - connect \Y $and$issuer_ls180.v:40987$1764_Y + attribute \src "libresoc.v:34101.3-34119.6" + process $proc$libresoc.v:34101$694 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] + attribute \src "libresoc.v:34102.5-34102.29" + switch \initial + attribute \src "libresoc.v:34102.9-34102.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $and $and$issuer_ls180.v:40989$1766 - parameter \A_SIGNED 0 - parameter \A_WIDTH 12 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 12 - connect \A \core_core_fn_unit - connect \B 4'1000 - connect \Y $and$issuer_ls180.v:40989$1766_Y + attribute \src "libresoc.v:34120.3-34138.6" + process $proc$libresoc.v:34120$695 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:34121.5-34121.29" + switch \initial + attribute \src "libresoc.v:34121.9-34121.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $and $and$issuer_ls180.v:40991$1768 - parameter \A_SIGNED 0 - parameter \A_WIDTH 12 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 12 - connect \A \core_core_fn_unit - connect \B 3'100 - connect \Y $and$issuer_ls180.v:40991$1768_Y + attribute \src "libresoc.v:34139.3-34157.6" + process $proc$libresoc.v:34139$696 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:34140.5-34140.29" + switch \initial + attribute \src "libresoc.v:34140.9-34140.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$issuer_ls180.v:40996$1773 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $and$issuer_ls180.v:40996$1773_Y + attribute \src "libresoc.v:34158.3-34176.6" + process $proc$libresoc.v:34158$697 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:34159.5-34159.29" + switch \initial + attribute \src "libresoc.v:34159.9-34159.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'01000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100100 + case + assign $1\dec31_dec_sub27_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$issuer_ls180.v:40997$1774 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 1'1 - connect \Y $and$issuer_ls180.v:40997$1774_Y + attribute \src "libresoc.v:34177.3-34195.6" + process $proc$libresoc.v:34177$698 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:34178.5-34178.29" + switch \initial + attribute \src "libresoc.v:34178.9-34178.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$issuer_ls180.v:41000$1777 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_rc - connect \B \core_core_rc_ok - connect \Y $and$issuer_ls180.v:41000$1777_Y + attribute \src "libresoc.v:34196.3-34214.6" + process $proc$libresoc.v:34196$699 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:34197.5-34197.29" + switch \initial + attribute \src "libresoc.v:34197.9-34197.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$issuer_ls180.v:41003$1780 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 3'100 - connect \Y $and$issuer_ls180.v:41003$1780_Y + attribute \src "libresoc.v:34215.3-34233.6" + process $proc$libresoc.v:34215$700 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:34216.5-34216.29" + switch \initial + attribute \src "libresoc.v:34216.9-34216.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$issuer_ls180.v:41010$1787 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $and$issuer_ls180.v:41010$1787_Y + attribute \src "libresoc.v:34234.3-34252.6" + process $proc$libresoc.v:34234$701 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:34235.5-34235.29" + switch \initial + attribute \src "libresoc.v:34235.9-34235.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + case + assign $1\dec31_dec_sub27_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$issuer_ls180.v:41011$1788 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 1'1 - connect \Y $and$issuer_ls180.v:41011$1788_Y + attribute \src "libresoc.v:34253.3-34271.6" + process $proc$libresoc.v:34253$702 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:34254.5-34254.29" + switch \initial + attribute \src "libresoc.v:34254.9-34254.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$issuer_ls180.v:41014$1791 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_rc - connect \B \core_core_rc_ok - connect \Y $and$issuer_ls180.v:41014$1791_Y + attribute \src "libresoc.v:34272.3-34290.6" + process $proc$libresoc.v:34272$703 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:34273.5-34273.29" + switch \initial + attribute \src "libresoc.v:34273.9-34273.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 + case + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$issuer_ls180.v:41017$1794 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $and$issuer_ls180.v:41017$1794_Y + attribute \src "libresoc.v:34291.3-34309.6" + process $proc$libresoc.v:34291$704 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:34292.5-34292.29" + switch \initial + attribute \src "libresoc.v:34292.9-34292.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$issuer_ls180.v:41018$1795 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 1'1 - connect \Y $and$issuer_ls180.v:41018$1795_Y + attribute \src "libresoc.v:34310.3-34328.6" + process $proc$libresoc.v:34310$705 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:34311.5-34311.29" + switch \initial + attribute \src "libresoc.v:34311.9-34311.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$issuer_ls180.v:41021$1798 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_rc - connect \B \core_core_rc_ok - connect \Y $and$issuer_ls180.v:41021$1798_Y + attribute \src "libresoc.v:34329.3-34347.6" + process $proc$libresoc.v:34329$706 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:34330.5-34330.29" + switch \initial + attribute \src "libresoc.v:34330.9-34330.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $and $and$issuer_ls180.v:41023$1800 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $and$issuer_ls180.v:41023$1800_Y + attribute \src "libresoc.v:34348.3-34366.6" + process $proc$libresoc.v:34348$707 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:34349.5-34349.29" + switch \initial + attribute \src "libresoc.v:34349.9-34349.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $and $and$issuer_ls180.v:41024$1801 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 2'10 - connect \Y $and$issuer_ls180.v:41024$1801_Y + attribute \src "libresoc.v:34367.3-34385.6" + process $proc$libresoc.v:34367$708 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:34368.5-34368.29" + switch \initial + attribute \src "libresoc.v:34368.9-34368.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$issuer_ls180.v:41028$1805 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 3'100 - connect \Y $and$issuer_ls180.v:41028$1805_Y + attribute \src "libresoc.v:34386.3-34404.6" + process $proc$libresoc.v:34386$709 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:34387.5-34387.29" + switch \initial + attribute \src "libresoc.v:34387.9-34387.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub27_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$issuer_ls180.v:41032$1809 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $and$issuer_ls180.v:41032$1809_Y + attribute \src "libresoc.v:34405.3-34423.6" + process $proc$libresoc.v:34405$710 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:34406.5-34406.29" + switch \initial + attribute \src "libresoc.v:34406.9-34406.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$issuer_ls180.v:41033$1810 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 1'1 - connect \Y $and$issuer_ls180.v:41033$1810_Y + attribute \src "libresoc.v:34424.3-34442.6" + process $proc$libresoc.v:34424$711 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:34425.5-34425.29" + switch \initial + attribute \src "libresoc.v:34425.9-34425.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$issuer_ls180.v:41036$1813 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_rc - connect \B \core_core_rc_ok - connect \Y $and$issuer_ls180.v:41036$1813_Y + attribute \src "libresoc.v:34443.3-34461.6" + process $proc$libresoc.v:34443$712 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:34444.5-34444.29" + switch \initial + attribute \src "libresoc.v:34444.9-34444.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$issuer_ls180.v:41039$1816 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $and$issuer_ls180.v:41039$1816_Y + attribute \src "libresoc.v:34462.3-34480.6" + process $proc$libresoc.v:34462$713 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_out_sel[1:0] $1\dec31_dec_sub27_out_sel[1:0] + attribute \src "libresoc.v:34463.5-34463.29" + switch \initial + attribute \src "libresoc.v:34463.9-34463.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub27_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_out_sel $0\dec31_dec_sub27_out_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$issuer_ls180.v:41040$1817 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 1'1 - connect \Y $and$issuer_ls180.v:41040$1817_Y + attribute \src "libresoc.v:34481.3-34499.6" + process $proc$libresoc.v:34481$714 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:34482.5-34482.29" + switch \initial + attribute \src "libresoc.v:34482.9-34482.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$issuer_ls180.v:41043$1820 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_rc - connect \B \core_core_rc_ok - connect \Y $and$issuer_ls180.v:41043$1820_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$issuer_ls180.v:41046$1823 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $and$issuer_ls180.v:41046$1823_Y + attribute \src "libresoc.v:34500.3-34518.6" + process $proc$libresoc.v:34500$715 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:34501.5-34501.29" + switch \initial + attribute \src "libresoc.v:34501.9-34501.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub27_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$issuer_ls180.v:41047$1824 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 1'1 - connect \Y $and$issuer_ls180.v:41047$1824_Y + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:34524.1-35671.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub28" +attribute \generator "nMigen" +module \dec31_dec_sub28 + attribute \src "libresoc.v:34967.3-35003.6" + wire width 8 $0\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:35115.3-35151.6" + wire $0\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:35596.3-35632.6" + wire width 3 $0\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:35633.3-35669.6" + wire width 3 $0\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:34930.3-34966.6" + wire width 2 $0\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:35078.3-35114.6" + wire $0\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:35411.3-35447.6" + wire width 5 $0\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:34782.3-34818.6" + wire width 12 $0\dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:35448.3-35484.6" + wire width 3 $0\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:35485.3-35521.6" + wire width 4 $0\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:35522.3-35558.6" + wire width 2 $0\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:35189.3-35225.6" + wire width 7 $0\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:35004.3-35040.6" + wire $0\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:35041.3-35077.6" + wire $0\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:35263.3-35299.6" + wire $0\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:34819.3-34855.6" + wire width 4 $0\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:35337.3-35373.6" + wire $0\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:35559.3-35595.6" + wire width 2 $0\dec31_dec_sub28_out_sel[1:0] + attribute \src "libresoc.v:34893.3-34929.6" + wire width 2 $0\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:35226.3-35262.6" + wire $0\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:35374.3-35410.6" + wire $0\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:35300.3-35336.6" + wire $0\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:35152.3-35188.6" + wire $0\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:34856.3-34892.6" + wire width 2 $0\dec31_dec_sub28_upd[1:0] + attribute \src "libresoc.v:34525.7-34525.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:34967.3-35003.6" + wire width 8 $1\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:35115.3-35151.6" + wire $1\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:35596.3-35632.6" + wire width 3 $1\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:35633.3-35669.6" + wire width 3 $1\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:34930.3-34966.6" + wire width 2 $1\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:35078.3-35114.6" + wire $1\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:35411.3-35447.6" + wire width 5 $1\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:34782.3-34818.6" + wire width 12 $1\dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:35448.3-35484.6" + wire width 3 $1\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:35485.3-35521.6" + wire width 4 $1\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:35522.3-35558.6" + wire width 2 $1\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:35189.3-35225.6" + wire width 7 $1\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:35004.3-35040.6" + wire $1\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:35041.3-35077.6" + wire $1\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:35263.3-35299.6" + wire $1\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:34819.3-34855.6" + wire width 4 $1\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:35337.3-35373.6" + wire $1\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:35559.3-35595.6" + wire width 2 $1\dec31_dec_sub28_out_sel[1:0] + attribute \src "libresoc.v:34893.3-34929.6" + wire width 2 $1\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:35226.3-35262.6" + wire $1\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:35374.3-35410.6" + wire $1\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:35300.3-35336.6" + wire $1\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:35152.3-35188.6" + wire $1\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:34856.3-34892.6" + wire width 2 $1\dec31_dec_sub28_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub28_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub28_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub28_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub28_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub28_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub28_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub28_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub28_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub28_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub28_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub28_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub28_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub28_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub28_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub28_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub28_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub28_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub28_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub28_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub28_upd + attribute \src "libresoc.v:34525.7-34525.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:34525.7-34525.20" + process $proc$libresoc.v:34525$741 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$issuer_ls180.v:41050$1827 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_rc - connect \B \core_core_rc_ok - connect \Y $and$issuer_ls180.v:41050$1827_Y + attribute \src "libresoc.v:34782.3-34818.6" + process $proc$libresoc.v:34782$717 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_function_unit[11:0] $1\dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:34783.5-34783.29" + switch \initial + attribute \src "libresoc.v:34783.9-34783.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + case + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$issuer_ls180.v:41053$1830 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 3'100 - connect \Y $and$issuer_ls180.v:41053$1830_Y + attribute \src "libresoc.v:34819.3-34855.6" + process $proc$libresoc.v:34819$718 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:34820.5-34820.29" + switch \initial + attribute \src "libresoc.v:34820.9-34820.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41058$1835 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o [0] - connect \B \fu_enable [0] - connect \Y $and$issuer_ls180.v:41058$1835_Y + attribute \src "libresoc.v:34856.3-34892.6" + process $proc$libresoc.v:34856$719 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] + attribute \src "libresoc.v:34857.5-34857.29" + switch \initial + attribute \src "libresoc.v:34857.9-34857.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41059$1836 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$331 - connect \B \rdflag_INT_ra_0 - connect \Y $and$issuer_ls180.v:41059$1836_Y + attribute \src "libresoc.v:34893.3-34929.6" + process $proc$libresoc.v:34893$720 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:34894.5-34894.29" + switch \initial + attribute \src "libresoc.v:34894.9-34894.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41061$1838 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$333 - connect \B \$335 - connect \Y $and$issuer_ls180.v:41061$1838_Y + attribute \src "libresoc.v:34930.3-34966.6" + process $proc$libresoc.v:34930$721 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:34931.5-34931.29" + switch \initial + attribute \src "libresoc.v:34931.9-34931.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41062$1839 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [0] - connect \B \rdpick_INT_ra_en_o - connect \Y $and$issuer_ls180.v:41062$1839_Y + attribute \src "libresoc.v:34967.3-35003.6" + process $proc$libresoc.v:34967$722 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:34968.5-34968.29" + switch \initial + attribute \src "libresoc.v:34968.9-34968.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00001111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'01000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'11010000 + case + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41064$1841 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$31 [0] - connect \B \fu_enable [1] - connect \Y $and$issuer_ls180.v:41064$1841_Y + attribute \src "libresoc.v:35004.3-35040.6" + process $proc$libresoc.v:35004$723 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:35005.5-35005.29" + switch \initial + attribute \src "libresoc.v:35005.9-35005.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41065$1842 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$343 - connect \B \rdflag_INT_ra_0 - connect \Y $and$issuer_ls180.v:41065$1842_Y + attribute \src "libresoc.v:35041.3-35077.6" + process $proc$libresoc.v:35041$724 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:35042.5-35042.29" + switch \initial + attribute \src "libresoc.v:35042.9-35042.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41067$1844 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$345 - connect \B \$347 - connect \Y $and$issuer_ls180.v:41067$1844_Y + attribute \src "libresoc.v:35078.3-35114.6" + process $proc$libresoc.v:35078$725 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:35079.5-35079.29" + switch \initial + attribute \src "libresoc.v:35079.9-35079.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41068$1845 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [1] - connect \B \rdpick_INT_ra_en_o - connect \Y $and$issuer_ls180.v:41068$1845_Y + attribute \src "libresoc.v:35115.3-35151.6" + process $proc$libresoc.v:35115$726 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:35116.5-35116.29" + switch \initial + attribute \src "libresoc.v:35116.9-35116.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + case + assign $1\dec31_dec_sub28_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41070$1847 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$34 [0] - connect \B \fu_enable [3] - connect \Y $and$issuer_ls180.v:41070$1847_Y + attribute \src "libresoc.v:35152.3-35188.6" + process $proc$libresoc.v:35152$727 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:35153.5-35153.29" + switch \initial + attribute \src "libresoc.v:35153.9-35153.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41071$1848 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$355 - connect \B \rdflag_INT_ra_0 - connect \Y $and$issuer_ls180.v:41071$1848_Y + attribute \src "libresoc.v:35189.3-35225.6" + process $proc$libresoc.v:35189$728 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:35190.5-35190.29" + switch \initial + attribute \src "libresoc.v:35190.9-35190.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 + case + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41073$1850 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$357 - connect \B \$359 - connect \Y $and$issuer_ls180.v:41073$1850_Y + attribute \src "libresoc.v:35226.3-35262.6" + process $proc$libresoc.v:35226$729 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:35227.5-35227.29" + switch \initial + attribute \src "libresoc.v:35227.9-35227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41074$1851 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [2] - connect \B \rdpick_INT_ra_en_o - connect \Y $and$issuer_ls180.v:41074$1851_Y + attribute \src "libresoc.v:35263.3-35299.6" + process $proc$libresoc.v:35263$730 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:35264.5-35264.29" + switch \initial + attribute \src "libresoc.v:35264.9-35264.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41076$1853 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$37 [0] - connect \B \fu_enable [4] - connect \Y $and$issuer_ls180.v:41076$1853_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41077$1854 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$367 - connect \B \rdflag_INT_ra_0 - connect \Y $and$issuer_ls180.v:41077$1854_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41079$1856 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$369 - connect \B \$371 - connect \Y $and$issuer_ls180.v:41079$1856_Y + attribute \src "libresoc.v:35300.3-35336.6" + process $proc$libresoc.v:35300$731 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:35301.5-35301.29" + switch \initial + attribute \src "libresoc.v:35301.9-35301.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41080$1857 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [3] - connect \B \rdpick_INT_ra_en_o - connect \Y $and$issuer_ls180.v:41080$1857_Y + attribute \src "libresoc.v:35337.3-35373.6" + process $proc$libresoc.v:35337$732 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:35338.5-35338.29" + switch \initial + attribute \src "libresoc.v:35338.9-35338.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41082$1859 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$40 [0] - connect \B \fu_enable [5] - connect \Y $and$issuer_ls180.v:41082$1859_Y + attribute \src "libresoc.v:35374.3-35410.6" + process $proc$libresoc.v:35374$733 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:35375.5-35375.29" + switch \initial + attribute \src "libresoc.v:35375.9-35375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41083$1860 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$379 - connect \B \rdflag_INT_ra_0 - connect \Y $and$issuer_ls180.v:41083$1860_Y + attribute \src "libresoc.v:35411.3-35447.6" + process $proc$libresoc.v:35411$734 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:35412.5-35412.29" + switch \initial + attribute \src "libresoc.v:35412.9-35412.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub28_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41085$1862 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$381 - connect \B \$383 - connect \Y $and$issuer_ls180.v:41085$1862_Y + attribute \src "libresoc.v:35448.3-35484.6" + process $proc$libresoc.v:35448$735 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:35449.5-35449.29" + switch \initial + attribute \src "libresoc.v:35449.9-35449.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41086$1863 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [4] - connect \B \rdpick_INT_ra_en_o - connect \Y $and$issuer_ls180.v:41086$1863_Y + attribute \src "libresoc.v:35485.3-35521.6" + process $proc$libresoc.v:35485$736 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:35486.5-35486.29" + switch \initial + attribute \src "libresoc.v:35486.9-35486.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41088$1865 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$43 [0] - connect \B \fu_enable [6] - connect \Y $and$issuer_ls180.v:41088$1865_Y + attribute \src "libresoc.v:35522.3-35558.6" + process $proc$libresoc.v:35522$737 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:35523.5-35523.29" + switch \initial + attribute \src "libresoc.v:35523.9-35523.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41089$1866 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$391 - connect \B \rdflag_INT_ra_0 - connect \Y $and$issuer_ls180.v:41089$1866_Y + attribute \src "libresoc.v:35559.3-35595.6" + process $proc$libresoc.v:35559$738 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_out_sel[1:0] $1\dec31_dec_sub28_out_sel[1:0] + attribute \src "libresoc.v:35560.5-35560.29" + switch \initial + attribute \src "libresoc.v:35560.9-35560.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub28_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_out_sel $0\dec31_dec_sub28_out_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41091$1868 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$393 - connect \B \$395 - connect \Y $and$issuer_ls180.v:41091$1868_Y + attribute \src "libresoc.v:35596.3-35632.6" + process $proc$libresoc.v:35596$739 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:35597.5-35597.29" + switch \initial + attribute \src "libresoc.v:35597.9-35597.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41092$1869 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [5] - connect \B \rdpick_INT_ra_en_o - connect \Y $and$issuer_ls180.v:41092$1869_Y + attribute \src "libresoc.v:35633.3-35669.6" + process $proc$libresoc.v:35633$740 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:35634.5-35634.29" + switch \initial + attribute \src "libresoc.v:35634.9-35634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41094$1871 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$46 [0] - connect \B \fu_enable [7] - connect \Y $and$issuer_ls180.v:41094$1871_Y + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:35675.1-36246.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub4" +attribute \generator "nMigen" +module \dec31_dec_sub4 + attribute \src "libresoc.v:35998.3-36010.6" + wire width 8 $0\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:36050.3-36062.6" + wire $0\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:36219.3-36231.6" + wire width 3 $0\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:36232.3-36244.6" + wire width 3 $0\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:35985.3-35997.6" + wire width 2 $0\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:36037.3-36049.6" + wire $0\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:36154.3-36166.6" + wire width 5 $0\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:35933.3-35945.6" + wire width 12 $0\dec31_dec_sub4_function_unit[11:0] + attribute \src "libresoc.v:36167.3-36179.6" + wire width 3 $0\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:36180.3-36192.6" + wire width 4 $0\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:36193.3-36205.6" + wire width 2 $0\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:36076.3-36088.6" + wire width 7 $0\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:36011.3-36023.6" + wire $0\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:36024.3-36036.6" + wire $0\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:36102.3-36114.6" + wire $0\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:35946.3-35958.6" + wire width 4 $0\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:36128.3-36140.6" + wire $0\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:36206.3-36218.6" + wire width 2 $0\dec31_dec_sub4_out_sel[1:0] + attribute \src "libresoc.v:35972.3-35984.6" + wire width 2 $0\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:36089.3-36101.6" + wire $0\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:36141.3-36153.6" + wire $0\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:36115.3-36127.6" + wire $0\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:36063.3-36075.6" + wire $0\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:35959.3-35971.6" + wire width 2 $0\dec31_dec_sub4_upd[1:0] + attribute \src "libresoc.v:35676.7-35676.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:35998.3-36010.6" + wire width 8 $1\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:36050.3-36062.6" + wire $1\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:36219.3-36231.6" + wire width 3 $1\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:36232.3-36244.6" + wire width 3 $1\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:35985.3-35997.6" + wire width 2 $1\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:36037.3-36049.6" + wire $1\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:36154.3-36166.6" + wire width 5 $1\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:35933.3-35945.6" + wire width 12 $1\dec31_dec_sub4_function_unit[11:0] + attribute \src "libresoc.v:36167.3-36179.6" + wire width 3 $1\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:36180.3-36192.6" + wire width 4 $1\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:36193.3-36205.6" + wire width 2 $1\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:36076.3-36088.6" + wire width 7 $1\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:36011.3-36023.6" + wire $1\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:36024.3-36036.6" + wire $1\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:36102.3-36114.6" + wire $1\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:35946.3-35958.6" + wire width 4 $1\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:36128.3-36140.6" + wire $1\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:36206.3-36218.6" + wire width 2 $1\dec31_dec_sub4_out_sel[1:0] + attribute \src "libresoc.v:35972.3-35984.6" + wire width 2 $1\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:36089.3-36101.6" + wire $1\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:36141.3-36153.6" + wire $1\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:36115.3-36127.6" + wire $1\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:36063.3-36075.6" + wire $1\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:35959.3-35971.6" + wire width 2 $1\dec31_dec_sub4_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub4_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub4_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub4_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub4_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub4_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub4_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub4_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub4_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub4_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub4_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub4_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub4_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub4_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub4_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub4_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub4_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub4_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub4_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub4_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub4_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub4_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub4_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub4_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub4_upd + attribute \src "libresoc.v:35676.7-35676.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:35676.7-35676.20" + process $proc$libresoc.v:35676$766 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41095$1872 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$403 - connect \B \rdflag_INT_ra_0 - connect \Y $and$issuer_ls180.v:41095$1872_Y + attribute \src "libresoc.v:35933.3-35945.6" + process $proc$libresoc.v:35933$742 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_function_unit[11:0] $1\dec31_dec_sub4_function_unit[11:0] + attribute \src "libresoc.v:35934.5-35934.29" + switch \initial + attribute \src "libresoc.v:35934.9-35934.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000 + case + assign $1\dec31_dec_sub4_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41097$1874 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$405 - connect \B \$407 - connect \Y $and$issuer_ls180.v:41097$1874_Y + attribute \src "libresoc.v:35946.3-35958.6" + process $proc$libresoc.v:35946$743 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:35947.5-35947.29" + switch \initial + attribute \src "libresoc.v:35947.9-35947.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41098$1875 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [6] - connect \B \rdpick_INT_ra_en_o - connect \Y $and$issuer_ls180.v:41098$1875_Y + attribute \src "libresoc.v:35959.3-35971.6" + process $proc$libresoc.v:35959$744 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] + attribute \src "libresoc.v:35960.5-35960.29" + switch \initial + attribute \src "libresoc.v:35960.9-35960.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41100$1877 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$49 [0] - connect \B \fu_enable [8] - connect \Y $and$issuer_ls180.v:41100$1877_Y + attribute \src "libresoc.v:35972.3-35984.6" + process $proc$libresoc.v:35972$745 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:35973.5-35973.29" + switch \initial + attribute \src "libresoc.v:35973.9-35973.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41101$1878 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$415 - connect \B \rdflag_INT_ra_0 - connect \Y $and$issuer_ls180.v:41101$1878_Y + attribute \src "libresoc.v:35985.3-35997.6" + process $proc$libresoc.v:35985$746 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:35986.5-35986.29" + switch \initial + attribute \src "libresoc.v:35986.9-35986.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41103$1880 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$417 - connect \B \$419 - connect \Y $and$issuer_ls180.v:41103$1880_Y + attribute \src "libresoc.v:35998.3-36010.6" + process $proc$libresoc.v:35998$747 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:35999.5-35999.29" + switch \initial + attribute \src "libresoc.v:35999.9-35999.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001110 + case + assign $1\dec31_dec_sub4_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41104$1881 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [7] - connect \B \rdpick_INT_ra_en_o - connect \Y $and$issuer_ls180.v:41104$1881_Y + attribute \src "libresoc.v:36011.3-36023.6" + process $proc$libresoc.v:36011$748 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:36012.5-36012.29" + switch \initial + attribute \src "libresoc.v:36012.9-36012.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41106$1883 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$52 [0] - connect \B \fu_enable [9] - connect \Y $and$issuer_ls180.v:41106$1883_Y + attribute \src "libresoc.v:36024.3-36036.6" + process $proc$libresoc.v:36024$749 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:36025.5-36025.29" + switch \initial + attribute \src "libresoc.v:36025.9-36025.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41107$1884 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$427 - connect \B \rdflag_INT_ra_0 - connect \Y $and$issuer_ls180.v:41107$1884_Y + attribute \src "libresoc.v:36037.3-36049.6" + process $proc$libresoc.v:36037$750 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:36038.5-36038.29" + switch \initial + attribute \src "libresoc.v:36038.9-36038.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41109$1886 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$429 - connect \B \$431 - connect \Y $and$issuer_ls180.v:41109$1886_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41110$1887 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [8] - connect \B \rdpick_INT_ra_en_o - connect \Y $and$issuer_ls180.v:41110$1887_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41121$1898 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o [1] - connect \B \fu_enable [0] - connect \Y $and$issuer_ls180.v:41121$1898_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41122$1899 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$457 - connect \B \rdflag_INT_rb_0 - connect \Y $and$issuer_ls180.v:41122$1899_Y + attribute \src "libresoc.v:36050.3-36062.6" + process $proc$libresoc.v:36050$751 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:36051.5-36051.29" + switch \initial + attribute \src "libresoc.v:36051.9-36051.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_br[0:0] 1'0 + case + assign $1\dec31_dec_sub4_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41124$1901 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$459 - connect \B \$461 - connect \Y $and$issuer_ls180.v:41124$1901_Y + attribute \src "libresoc.v:36063.3-36075.6" + process $proc$libresoc.v:36063$752 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:36064.5-36064.29" + switch \initial + attribute \src "libresoc.v:36064.9-36064.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41125$1902 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rb_o [0] - connect \B \rdpick_INT_rb_en_o - connect \Y $and$issuer_ls180.v:41125$1902_Y + attribute \src "libresoc.v:36076.3-36088.6" + process $proc$libresoc.v:36076$753 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:36077.5-36077.29" + switch \initial + attribute \src "libresoc.v:36077.9-36077.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + case + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41127$1904 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$31 [1] - connect \B \fu_enable [1] - connect \Y $and$issuer_ls180.v:41127$1904_Y + attribute \src "libresoc.v:36089.3-36101.6" + process $proc$libresoc.v:36089$754 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:36090.5-36090.29" + switch \initial + attribute \src "libresoc.v:36090.9-36090.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41128$1905 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$469 - connect \B \rdflag_INT_rb_0 - connect \Y $and$issuer_ls180.v:41128$1905_Y + attribute \src "libresoc.v:36102.3-36114.6" + process $proc$libresoc.v:36102$755 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:36103.5-36103.29" + switch \initial + attribute \src "libresoc.v:36103.9-36103.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41130$1907 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$471 - connect \B \$473 - connect \Y $and$issuer_ls180.v:41130$1907_Y + attribute \src "libresoc.v:36115.3-36127.6" + process $proc$libresoc.v:36115$756 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:36116.5-36116.29" + switch \initial + attribute \src "libresoc.v:36116.9-36116.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41131$1908 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rb_o [1] - connect \B \rdpick_INT_rb_en_o - connect \Y $and$issuer_ls180.v:41131$1908_Y + attribute \src "libresoc.v:36128.3-36140.6" + process $proc$libresoc.v:36128$757 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:36129.5-36129.29" + switch \initial + attribute \src "libresoc.v:36129.9-36129.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41133$1910 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$34 [1] - connect \B \fu_enable [3] - connect \Y $and$issuer_ls180.v:41133$1910_Y + attribute \src "libresoc.v:36141.3-36153.6" + process $proc$libresoc.v:36141$758 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:36142.5-36142.29" + switch \initial + attribute \src "libresoc.v:36142.9-36142.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41134$1911 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$481 - connect \B \rdflag_INT_rb_0 - connect \Y $and$issuer_ls180.v:41134$1911_Y + attribute \src "libresoc.v:36154.3-36166.6" + process $proc$libresoc.v:36154$759 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:36155.5-36155.29" + switch \initial + attribute \src "libresoc.v:36155.9-36155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub4_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41136$1913 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$483 - connect \B \$485 - connect \Y $and$issuer_ls180.v:41136$1913_Y + attribute \src "libresoc.v:36167.3-36179.6" + process $proc$libresoc.v:36167$760 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:36168.5-36168.29" + switch \initial + attribute \src "libresoc.v:36168.9-36168.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41137$1914 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rb_o [2] - connect \B \rdpick_INT_rb_en_o - connect \Y $and$issuer_ls180.v:41137$1914_Y + attribute \src "libresoc.v:36180.3-36192.6" + process $proc$libresoc.v:36180$761 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:36181.5-36181.29" + switch \initial + attribute \src "libresoc.v:36181.9-36181.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41139$1916 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$37 [1] - connect \B \fu_enable [4] - connect \Y $and$issuer_ls180.v:41139$1916_Y + attribute \src "libresoc.v:36193.3-36205.6" + process $proc$libresoc.v:36193$762 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:36194.5-36194.29" + switch \initial + attribute \src "libresoc.v:36194.9-36194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41140$1917 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$493 - connect \B \rdflag_INT_rb_0 - connect \Y $and$issuer_ls180.v:41140$1917_Y + attribute \src "libresoc.v:36206.3-36218.6" + process $proc$libresoc.v:36206$763 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_out_sel[1:0] $1\dec31_dec_sub4_out_sel[1:0] + attribute \src "libresoc.v:36207.5-36207.29" + switch \initial + attribute \src "libresoc.v:36207.9-36207.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_out_sel $0\dec31_dec_sub4_out_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41142$1919 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$495 - connect \B \$497 - connect \Y $and$issuer_ls180.v:41142$1919_Y + attribute \src "libresoc.v:36219.3-36231.6" + process $proc$libresoc.v:36219$764 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:36220.5-36220.29" + switch \initial + attribute \src "libresoc.v:36220.9-36220.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41143$1920 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rb_o [3] - connect \B \rdpick_INT_rb_en_o - connect \Y $and$issuer_ls180.v:41143$1920_Y + attribute \src "libresoc.v:36232.3-36244.6" + process $proc$libresoc.v:36232$765 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:36233.5-36233.29" + switch \initial + attribute \src "libresoc.v:36233.9-36233.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41145$1922 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$43 [1] - connect \B \fu_enable [6] - connect \Y $and$issuer_ls180.v:41145$1922_Y + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:36250.1-37541.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub8" +attribute \generator "nMigen" +module \dec31_dec_sub8 + attribute \src "libresoc.v:36723.3-36765.6" + wire width 8 $0\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:36895.3-36937.6" + wire $0\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:37454.3-37496.6" + wire width 3 $0\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:37497.3-37539.6" + wire width 3 $0\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:36680.3-36722.6" + wire width 2 $0\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:36852.3-36894.6" + wire $0\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:37239.3-37281.6" + wire width 5 $0\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:36508.3-36550.6" + wire width 12 $0\dec31_dec_sub8_function_unit[11:0] + attribute \src "libresoc.v:37282.3-37324.6" + wire width 3 $0\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:37325.3-37367.6" + wire width 4 $0\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:37368.3-37410.6" + wire width 2 $0\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:36981.3-37023.6" + wire width 7 $0\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:36766.3-36808.6" + wire $0\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:36809.3-36851.6" + wire $0\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:37067.3-37109.6" + wire $0\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:36551.3-36593.6" + wire width 4 $0\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:37153.3-37195.6" + wire $0\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:37411.3-37453.6" + wire width 2 $0\dec31_dec_sub8_out_sel[1:0] + attribute \src "libresoc.v:36637.3-36679.6" + wire width 2 $0\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:37024.3-37066.6" + wire $0\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:37196.3-37238.6" + wire $0\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:37110.3-37152.6" + wire $0\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:36938.3-36980.6" + wire $0\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:36594.3-36636.6" + wire width 2 $0\dec31_dec_sub8_upd[1:0] + attribute \src "libresoc.v:36251.7-36251.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:36723.3-36765.6" + wire width 8 $1\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:36895.3-36937.6" + wire $1\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:37454.3-37496.6" + wire width 3 $1\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:37497.3-37539.6" + wire width 3 $1\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:36680.3-36722.6" + wire width 2 $1\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:36852.3-36894.6" + wire $1\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:37239.3-37281.6" + wire width 5 $1\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:36508.3-36550.6" + wire width 12 $1\dec31_dec_sub8_function_unit[11:0] + attribute \src "libresoc.v:37282.3-37324.6" + wire width 3 $1\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:37325.3-37367.6" + wire width 4 $1\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:37368.3-37410.6" + wire width 2 $1\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:36981.3-37023.6" + wire width 7 $1\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:36766.3-36808.6" + wire $1\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:36809.3-36851.6" + wire $1\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:37067.3-37109.6" + wire $1\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:36551.3-36593.6" + wire width 4 $1\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:37153.3-37195.6" + wire $1\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:37411.3-37453.6" + wire width 2 $1\dec31_dec_sub8_out_sel[1:0] + attribute \src "libresoc.v:36637.3-36679.6" + wire width 2 $1\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:37024.3-37066.6" + wire $1\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:37196.3-37238.6" + wire $1\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:37110.3-37152.6" + wire $1\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:36938.3-36980.6" + wire $1\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:36594.3-36636.6" + wire width 2 $1\dec31_dec_sub8_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub8_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub8_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub8_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub8_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub8_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub8_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub8_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub8_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub8_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub8_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub8_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub8_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub8_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub8_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub8_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub8_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub8_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub8_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub8_upd + attribute \src "libresoc.v:36251.7-36251.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:36251.7-36251.20" + process $proc$libresoc.v:36251$791 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41146$1923 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$505 - connect \B \rdflag_INT_rb_0 - connect \Y $and$issuer_ls180.v:41146$1923_Y + attribute \src "libresoc.v:36508.3-36550.6" + process $proc$libresoc.v:36508$767 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_function_unit[11:0] $1\dec31_dec_sub8_function_unit[11:0] + attribute \src "libresoc.v:36509.5-36509.29" + switch \initial + attribute \src "libresoc.v:36509.9-36509.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + case + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41148$1925 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$507 - connect \B \$509 - connect \Y $and$issuer_ls180.v:41148$1925_Y + attribute \src "libresoc.v:36551.3-36593.6" + process $proc$libresoc.v:36551$768 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:36552.5-36552.29" + switch \initial + attribute \src "libresoc.v:36552.9-36552.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41149$1926 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rb_o [4] - connect \B \rdpick_INT_rb_en_o - connect \Y $and$issuer_ls180.v:41149$1926_Y + attribute \src "libresoc.v:36594.3-36636.6" + process $proc$libresoc.v:36594$769 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] + attribute \src "libresoc.v:36595.5-36595.29" + switch \initial + attribute \src "libresoc.v:36595.9-36595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41151$1928 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$46 [1] - connect \B \fu_enable [7] - connect \Y $and$issuer_ls180.v:41151$1928_Y + attribute \src "libresoc.v:36637.3-36679.6" + process $proc$libresoc.v:36637$770 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:36638.5-36638.29" + switch \initial + attribute \src "libresoc.v:36638.9-36638.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41152$1929 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$517 - connect \B \rdflag_INT_rb_0 - connect \Y $and$issuer_ls180.v:41152$1929_Y + attribute \src "libresoc.v:36680.3-36722.6" + process $proc$libresoc.v:36680$771 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:36681.5-36681.29" + switch \initial + attribute \src "libresoc.v:36681.9-36681.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + case + assign $1\dec31_dec_sub8_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41154$1931 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$519 - connect \B \$521 - connect \Y $and$issuer_ls180.v:41154$1931_Y + attribute \src "libresoc.v:36723.3-36765.6" + process $proc$libresoc.v:36723$772 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:36724.5-36724.29" + switch \initial + attribute \src "libresoc.v:36724.9-36724.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111111 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11001000 + case + assign $1\dec31_dec_sub8_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41155$1932 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rb_o [5] - connect \B \rdpick_INT_rb_en_o - connect \Y $and$issuer_ls180.v:41155$1932_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41157$1934 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$49 [1] - connect \B \fu_enable [8] - connect \Y $and$issuer_ls180.v:41157$1934_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41158$1935 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$529 - connect \B \rdflag_INT_rb_0 - connect \Y $and$issuer_ls180.v:41158$1935_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41160$1937 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$531 - connect \B \$533 - connect \Y $and$issuer_ls180.v:41160$1937_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41161$1938 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rb_o [6] - connect \B \rdpick_INT_rb_en_o - connect \Y $and$issuer_ls180.v:41161$1938_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41163$1940 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$52 [1] - connect \B \fu_enable [9] - connect \Y $and$issuer_ls180.v:41163$1940_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41164$1941 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$541 - connect \B \rdflag_INT_rb_0 - connect \Y $and$issuer_ls180.v:41164$1941_Y + attribute \src "libresoc.v:36766.3-36808.6" + process $proc$libresoc.v:36766$773 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:36767.5-36767.29" + switch \initial + attribute \src "libresoc.v:36767.9-36767.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + case + assign $1\dec31_dec_sub8_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41166$1943 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$543 - connect \B \$545 - connect \Y $and$issuer_ls180.v:41166$1943_Y + attribute \src "libresoc.v:36809.3-36851.6" + process $proc$libresoc.v:36809$774 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:36810.5-36810.29" + switch \initial + attribute \src "libresoc.v:36810.9-36810.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41167$1944 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rb_o [7] - connect \B \rdpick_INT_rb_en_o - connect \Y $and$issuer_ls180.v:41167$1944_Y + attribute \src "libresoc.v:36852.3-36894.6" + process $proc$libresoc.v:36852$775 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:36853.5-36853.29" + switch \initial + attribute \src "libresoc.v:36853.9-36853.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41177$1954 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$49 [2] - connect \B \fu_enable [8] - connect \Y $and$issuer_ls180.v:41177$1954_Y + attribute \src "libresoc.v:36895.3-36937.6" + process $proc$libresoc.v:36895$776 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:36896.5-36896.29" + switch \initial + attribute \src "libresoc.v:36896.9-36896.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + case + assign $1\dec31_dec_sub8_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41178$1955 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$569 - connect \B \rdflag_INT_rc_0 - connect \Y $and$issuer_ls180.v:41178$1955_Y + attribute \src "libresoc.v:36938.3-36980.6" + process $proc$libresoc.v:36938$777 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:36939.5-36939.29" + switch \initial + attribute \src "libresoc.v:36939.9-36939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41180$1957 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$571 - connect \B \$573 - connect \Y $and$issuer_ls180.v:41180$1957_Y + attribute \src "libresoc.v:36981.3-37023.6" + process $proc$libresoc.v:36981$778 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:36982.5-36982.29" + switch \initial + attribute \src "libresoc.v:36982.9-36982.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + case + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41181$1958 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rc_o [0] - connect \B \rdpick_INT_rc_en_o - connect \Y $and$issuer_ls180.v:41181$1958_Y + attribute \src "libresoc.v:37024.3-37066.6" + process $proc$libresoc.v:37024$779 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:37025.5-37025.29" + switch \initial + attribute \src "libresoc.v:37025.9-37025.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41183$1960 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$52 [2] - connect \B \fu_enable [9] - connect \Y $and$issuer_ls180.v:41183$1960_Y + attribute \src "libresoc.v:37067.3-37109.6" + process $proc$libresoc.v:37067$780 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:37068.5-37068.29" + switch \initial + attribute \src "libresoc.v:37068.9-37068.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41184$1961 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$581 - connect \B \rdflag_INT_rc_0 - connect \Y $and$issuer_ls180.v:41184$1961_Y + attribute \src "libresoc.v:37110.3-37152.6" + process $proc$libresoc.v:37110$781 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:37111.5-37111.29" + switch \initial + attribute \src "libresoc.v:37111.9-37111.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41186$1963 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$583 - connect \B \$585 - connect \Y $and$issuer_ls180.v:41186$1963_Y + attribute \src "libresoc.v:37153.3-37195.6" + process $proc$libresoc.v:37153$782 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:37154.5-37154.29" + switch \initial + attribute \src "libresoc.v:37154.9-37154.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41187$1964 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rc_o [1] - connect \B \rdpick_INT_rc_en_o - connect \Y $and$issuer_ls180.v:41187$1964_Y + attribute \src "libresoc.v:37196.3-37238.6" + process $proc$libresoc.v:37196$783 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:37197.5-37197.29" + switch \initial + attribute \src "libresoc.v:37197.9-37197.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$issuer_ls180.v:41191$1968 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $and$issuer_ls180.v:41191$1968_Y + attribute \src "libresoc.v:37239.3-37281.6" + process $proc$libresoc.v:37239$784 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:37240.5-37240.29" + switch \initial + attribute \src "libresoc.v:37240.9-37240.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub8_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$issuer_ls180.v:41192$1969 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 1'1 - connect \Y $and$issuer_ls180.v:41192$1969_Y + attribute \src "libresoc.v:37282.3-37324.6" + process $proc$libresoc.v:37282$785 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:37283.5-37283.29" + switch \initial + attribute \src "libresoc.v:37283.9-37283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$issuer_ls180.v:41195$1972 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_rc - connect \B \core_core_rc_ok - connect \Y $and$issuer_ls180.v:41195$1972_Y + attribute \src "libresoc.v:37325.3-37367.6" + process $proc$libresoc.v:37325$786 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:37326.5-37326.29" + switch \initial + attribute \src "libresoc.v:37326.9-37326.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41197$1974 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o [2] - connect \B \fu_enable [0] - connect \Y $and$issuer_ls180.v:41197$1974_Y + attribute \src "libresoc.v:37368.3-37410.6" + process $proc$libresoc.v:37368$787 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:37369.5-37369.29" + switch \initial + attribute \src "libresoc.v:37369.9-37369.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41198$1975 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$609 - connect \B \rdflag_XER_xer_so_0 - connect \Y $and$issuer_ls180.v:41198$1975_Y + attribute \src "libresoc.v:37411.3-37453.6" + process $proc$libresoc.v:37411$788 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_out_sel[1:0] $1\dec31_dec_sub8_out_sel[1:0] + attribute \src "libresoc.v:37412.5-37412.29" + switch \initial + attribute \src "libresoc.v:37412.9-37412.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub8_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_out_sel $0\dec31_dec_sub8_out_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41200$1977 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$611 - connect \B \$613 - connect \Y $and$issuer_ls180.v:41200$1977_Y + attribute \src "libresoc.v:37454.3-37496.6" + process $proc$libresoc.v:37454$789 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:37455.5-37455.29" + switch \initial + attribute \src "libresoc.v:37455.9-37455.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41201$1978 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_so_o [0] - connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$issuer_ls180.v:41201$1978_Y + attribute \src "libresoc.v:37497.3-37539.6" + process $proc$libresoc.v:37497$790 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:37498.5-37498.29" + switch \initial + attribute \src "libresoc.v:37498.9-37498.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41203$1980 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$37 [2] - connect \B \fu_enable [4] - connect \Y $and$issuer_ls180.v:41203$1980_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41204$1981 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$621 - connect \B \rdflag_XER_xer_so_0 - connect \Y $and$issuer_ls180.v:41204$1981_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41206$1983 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$623 - connect \B \$625 - connect \Y $and$issuer_ls180.v:41206$1983_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41207$1984 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_so_o [1] - connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$issuer_ls180.v:41207$1984_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41209$1986 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$40 [3] - connect \B \fu_enable [5] - connect \Y $and$issuer_ls180.v:41209$1986_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41210$1987 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$633 - connect \B \rdflag_XER_xer_so_0 - connect \Y $and$issuer_ls180.v:41210$1987_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41212$1989 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$635 - connect \B \$637 - connect \Y $and$issuer_ls180.v:41212$1989_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41213$1990 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_so_o [2] - connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$issuer_ls180.v:41213$1990_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41215$1992 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$43 [2] - connect \B \fu_enable [6] - connect \Y $and$issuer_ls180.v:41215$1992_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41216$1993 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$645 - connect \B \rdflag_XER_xer_so_0 - connect \Y $and$issuer_ls180.v:41216$1993_Y + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:37545.1-39124.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub9" +attribute \generator "nMigen" +module \dec31_dec_sub9 + attribute \src "libresoc.v:38078.3-38132.6" + wire width 8 $0\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:38298.3-38352.6" + wire $0\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:39013.3-39067.6" + wire width 3 $0\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:39068.3-39122.6" + wire width 3 $0\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:38023.3-38077.6" + wire width 2 $0\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:38243.3-38297.6" + wire $0\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:38738.3-38792.6" + wire width 5 $0\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:37803.3-37857.6" + wire width 12 $0\dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:38793.3-38847.6" + wire width 3 $0\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:38848.3-38902.6" + wire width 4 $0\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:38903.3-38957.6" + wire width 2 $0\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:38408.3-38462.6" + wire width 7 $0\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:38133.3-38187.6" + wire $0\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:38188.3-38242.6" + wire $0\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:38518.3-38572.6" + wire $0\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:37858.3-37912.6" + wire width 4 $0\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:38628.3-38682.6" + wire $0\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:38958.3-39012.6" + wire width 2 $0\dec31_dec_sub9_out_sel[1:0] + attribute \src "libresoc.v:37968.3-38022.6" + wire width 2 $0\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:38463.3-38517.6" + wire $0\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:38683.3-38737.6" + wire $0\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:38573.3-38627.6" + wire $0\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:38353.3-38407.6" + wire $0\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:37913.3-37967.6" + wire width 2 $0\dec31_dec_sub9_upd[1:0] + attribute \src "libresoc.v:37546.7-37546.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:38078.3-38132.6" + wire width 8 $1\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:38298.3-38352.6" + wire $1\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:39013.3-39067.6" + wire width 3 $1\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:39068.3-39122.6" + wire width 3 $1\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:38023.3-38077.6" + wire width 2 $1\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:38243.3-38297.6" + wire $1\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:38738.3-38792.6" + wire width 5 $1\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:37803.3-37857.6" + wire width 12 $1\dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:38793.3-38847.6" + wire width 3 $1\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:38848.3-38902.6" + wire width 4 $1\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:38903.3-38957.6" + wire width 2 $1\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:38408.3-38462.6" + wire width 7 $1\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:38133.3-38187.6" + wire $1\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:38188.3-38242.6" + wire $1\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:38518.3-38572.6" + wire $1\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:37858.3-37912.6" + wire width 4 $1\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:38628.3-38682.6" + wire $1\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:38958.3-39012.6" + wire width 2 $1\dec31_dec_sub9_out_sel[1:0] + attribute \src "libresoc.v:37968.3-38022.6" + wire width 2 $1\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:38463.3-38517.6" + wire $1\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:38683.3-38737.6" + wire $1\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:38573.3-38627.6" + wire $1\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:38353.3-38407.6" + wire $1\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:37913.3-37967.6" + wire width 2 $1\dec31_dec_sub9_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub9_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub9_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub9_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub9_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub9_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub9_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub9_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub9_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub9_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub9_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub9_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub9_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub9_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub9_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub9_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub9_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub9_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub9_upd + attribute \src "libresoc.v:37546.7-37546.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:37546.7-37546.20" + process $proc$libresoc.v:37546$816 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41218$1995 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$647 - connect \B \$649 - connect \Y $and$issuer_ls180.v:41218$1995_Y + attribute \src "libresoc.v:37803.3-37857.6" + process $proc$libresoc.v:37803$792 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_function_unit[11:0] $1\dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:37804.5-37804.29" + switch \initial + attribute \src "libresoc.v:37804.9-37804.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + case + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41219$1996 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_so_o [3] - connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$issuer_ls180.v:41219$1996_Y + attribute \src "libresoc.v:37858.3-37912.6" + process $proc$libresoc.v:37858$793 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:37859.5-37859.29" + switch \initial + attribute \src "libresoc.v:37859.9-37859.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41221$1998 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$46 [2] - connect \B \fu_enable [7] - connect \Y $and$issuer_ls180.v:41221$1998_Y + attribute \src "libresoc.v:37913.3-37967.6" + process $proc$libresoc.v:37913$794 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] + attribute \src "libresoc.v:37914.5-37914.29" + switch \initial + attribute \src "libresoc.v:37914.9-37914.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41222$1999 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$657 - connect \B \rdflag_XER_xer_so_0 - connect \Y $and$issuer_ls180.v:41222$1999_Y + attribute \src "libresoc.v:37968.3-38022.6" + process $proc$libresoc.v:37968$795 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:37969.5-37969.29" + switch \initial + attribute \src "libresoc.v:37969.9-37969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41224$2001 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$659 - connect \B \$661 - connect \Y $and$issuer_ls180.v:41224$2001_Y + attribute \src "libresoc.v:38023.3-38077.6" + process $proc$libresoc.v:38023$796 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:38024.5-38024.29" + switch \initial + attribute \src "libresoc.v:38024.9-38024.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41225$2002 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_so_o [4] - connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$issuer_ls180.v:41225$2002_Y + attribute \src "libresoc.v:38078.3-38132.6" + process $proc$libresoc.v:38078$797 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:38079.5-38079.29" + switch \initial + attribute \src "libresoc.v:38079.9-38079.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111111 + case + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41227$2004 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$49 [3] - connect \B \fu_enable [8] - connect \Y $and$issuer_ls180.v:41227$2004_Y + attribute \src "libresoc.v:38133.3-38187.6" + process $proc$libresoc.v:38133$798 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:38134.5-38134.29" + switch \initial + attribute \src "libresoc.v:38134.9-38134.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41228$2005 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$669 - connect \B \rdflag_XER_xer_so_0 - connect \Y $and$issuer_ls180.v:41228$2005_Y + attribute \src "libresoc.v:38188.3-38242.6" + process $proc$libresoc.v:38188$799 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:38189.5-38189.29" + switch \initial + attribute \src "libresoc.v:38189.9-38189.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41230$2007 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$671 - connect \B \$673 - connect \Y $and$issuer_ls180.v:41230$2007_Y + attribute \src "libresoc.v:38243.3-38297.6" + process $proc$libresoc.v:38243$800 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:38244.5-38244.29" + switch \initial + attribute \src "libresoc.v:38244.9-38244.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41231$2008 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_so_o [5] - connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$issuer_ls180.v:41231$2008_Y + attribute \src "libresoc.v:38298.3-38352.6" + process $proc$libresoc.v:38298$801 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:38299.5-38299.29" + switch \initial + attribute \src "libresoc.v:38299.9-38299.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + case + assign $1\dec31_dec_sub9_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$issuer_ls180.v:41240$2018 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 3'100 - connect \Y $and$issuer_ls180.v:41240$2018_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41243$2021 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o [3] - connect \B \fu_enable [0] - connect \Y $and$issuer_ls180.v:41243$2021_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41244$2022 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$701 - connect \B \rdflag_XER_xer_ca_0 - connect \Y $and$issuer_ls180.v:41244$2022_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41246$2024 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$703 - connect \B \$705 - connect \Y $and$issuer_ls180.v:41246$2024_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41247$2025 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_ca_o [0] - connect \B \rdpick_XER_xer_ca_en_o - connect \Y $and$issuer_ls180.v:41247$2025_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41249$2027 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$40 [5] - connect \B \fu_enable [5] - connect \Y $and$issuer_ls180.v:41249$2027_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41250$2028 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$713 - connect \B \rdflag_XER_xer_ca_0 - connect \Y $and$issuer_ls180.v:41250$2028_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41252$2030 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$715 - connect \B \$717 - connect \Y $and$issuer_ls180.v:41252$2030_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41253$2031 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_ca_o [1] - connect \B \rdpick_XER_xer_ca_en_o - connect \Y $and$issuer_ls180.v:41253$2031_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41255$2033 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$49 [4] - connect \B \fu_enable [8] - connect \Y $and$issuer_ls180.v:41255$2033_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41256$2034 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$725 - connect \B \rdflag_XER_xer_ca_0 - connect \Y $and$issuer_ls180.v:41256$2034_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41258$2036 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$727 - connect \B \$729 - connect \Y $and$issuer_ls180.v:41258$2036_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41259$2037 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_ca_o [2] - connect \B \rdpick_XER_xer_ca_en_o - connect \Y $and$issuer_ls180.v:41259$2037_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $and $and$issuer_ls180.v:41264$2043 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $and$issuer_ls180.v:41264$2043_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $and $and$issuer_ls180.v:41265$2044 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 2'10 - connect \Y $and$issuer_ls180.v:41265$2044_Y + attribute \src "libresoc.v:38353.3-38407.6" + process $proc$libresoc.v:38353$802 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:38354.5-38354.29" + switch \initial + attribute \src "libresoc.v:38354.9-38354.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41268$2047 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$40 [4] - connect \B \fu_enable [5] - connect \Y $and$issuer_ls180.v:41268$2047_Y + attribute \src "libresoc.v:38408.3-38462.6" + process $proc$libresoc.v:38408$803 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:38409.5-38409.29" + switch \initial + attribute \src "libresoc.v:38409.9-38409.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 + case + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41269$2048 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$751 - connect \B \rdflag_XER_xer_ov_0 - connect \Y $and$issuer_ls180.v:41269$2048_Y + attribute \src "libresoc.v:38463.3-38517.6" + process $proc$libresoc.v:38463$804 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:38464.5-38464.29" + switch \initial + attribute \src "libresoc.v:38464.9-38464.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41271$2050 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$753 - connect \B \$755 - connect \Y $and$issuer_ls180.v:41271$2050_Y + attribute \src "libresoc.v:38518.3-38572.6" + process $proc$libresoc.v:38518$805 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:38519.5-38519.29" + switch \initial + attribute \src "libresoc.v:38519.9-38519.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41272$2051 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_ov_o - connect \B \rdpick_XER_xer_ov_en_o - connect \Y $and$issuer_ls180.v:41272$2051_Y + attribute \src "libresoc.v:38573.3-38627.6" + process $proc$libresoc.v:38573$806 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:38574.5-38574.29" + switch \initial + attribute \src "libresoc.v:38574.9-38574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + case + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41274$2053 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$31 [2] - connect \B \fu_enable [1] - connect \Y $and$issuer_ls180.v:41274$2053_Y + attribute \src "libresoc.v:38628.3-38682.6" + process $proc$libresoc.v:38628$807 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:38629.5-38629.29" + switch \initial + attribute \src "libresoc.v:38629.9-38629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41275$2054 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$763 - connect \B \rdflag_CR_full_cr_0 - connect \Y $and$issuer_ls180.v:41275$2054_Y + attribute \src "libresoc.v:38683.3-38737.6" + process $proc$libresoc.v:38683$808 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:38684.5-38684.29" + switch \initial + attribute \src "libresoc.v:38684.9-38684.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41277$2056 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$765 - connect \B \$767 - connect \Y $and$issuer_ls180.v:41277$2056_Y + attribute \src "libresoc.v:38738.3-38792.6" + process $proc$libresoc.v:38738$809 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:38739.5-38739.29" + switch \initial + attribute \src "libresoc.v:38739.9-38739.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub9_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41278$2057 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_CR_full_cr_o - connect \B \rdpick_CR_full_cr_en_o - connect \Y $and$issuer_ls180.v:41278$2057_Y + attribute \src "libresoc.v:38793.3-38847.6" + process $proc$libresoc.v:38793$810 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:38794.5-38794.29" + switch \initial + attribute \src "libresoc.v:38794.9-38794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41280$2059 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$31 [3] - connect \B \fu_enable [1] - connect \Y $and$issuer_ls180.v:41280$2059_Y + attribute \src "libresoc.v:38848.3-38902.6" + process $proc$libresoc.v:38848$811 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:38849.5-38849.29" + switch \initial + attribute \src "libresoc.v:38849.9-38849.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41281$2060 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$775 - connect \B \rdflag_CR_cr_a_0 - connect \Y $and$issuer_ls180.v:41281$2060_Y + attribute \src "libresoc.v:38903.3-38957.6" + process $proc$libresoc.v:38903$812 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:38904.5-38904.29" + switch \initial + attribute \src "libresoc.v:38904.9-38904.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41283$2062 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$777 - connect \B \$779 - connect \Y $and$issuer_ls180.v:41283$2062_Y + attribute \src "libresoc.v:38958.3-39012.6" + process $proc$libresoc.v:38958$813 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_out_sel[1:0] $1\dec31_dec_sub9_out_sel[1:0] + attribute \src "libresoc.v:38959.5-38959.29" + switch \initial + attribute \src "libresoc.v:38959.9-38959.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub9_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_out_sel $0\dec31_dec_sub9_out_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41284$2063 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_CR_cr_a_o [0] - connect \B \rdpick_CR_cr_a_en_o - connect \Y $and$issuer_ls180.v:41284$2063_Y + attribute \src "libresoc.v:39013.3-39067.6" + process $proc$libresoc.v:39013$814 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:39014.5-39014.29" + switch \initial + attribute \src "libresoc.v:39014.9-39014.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41288$2067 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$72 [2] - connect \B \fu_enable [2] - connect \Y $and$issuer_ls180.v:41288$2067_Y + attribute \src "libresoc.v:39068.3-39122.6" + process $proc$libresoc.v:39068$815 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:39069.5-39069.29" + switch \initial + attribute \src "libresoc.v:39069.9-39069.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41289$2068 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$791 - connect \B \rdflag_CR_cr_a_0 - connect \Y $and$issuer_ls180.v:41289$2068_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41291$2070 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$793 - connect \B \$795 - connect \Y $and$issuer_ls180.v:41291$2070_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41292$2071 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_CR_cr_a_o [1] - connect \B \rdpick_CR_cr_a_en_o - connect \Y $and$issuer_ls180.v:41292$2071_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41297$2076 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$31 [4] - connect \B \fu_enable [1] - connect \Y $and$issuer_ls180.v:41297$2076_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41298$2077 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$810 - connect \B \rdflag_CR_cr_b_0 - connect \Y $and$issuer_ls180.v:41298$2077_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41300$2079 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$812 - connect \B \$814 - connect \Y $and$issuer_ls180.v:41300$2079_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41301$2080 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_CR_cr_b_o - connect \B \rdpick_CR_cr_b_en_o - connect \Y $and$issuer_ls180.v:41301$2080_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41305$2084 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$31 [5] - connect \B \fu_enable [1] - connect \Y $and$issuer_ls180.v:41305$2084_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41306$2085 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$826 - connect \B \rdflag_CR_cr_c_0 - connect \Y $and$issuer_ls180.v:41306$2085_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41308$2087 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$828 - connect \B \$830 - connect \Y $and$issuer_ls180.v:41308$2087_Y + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:39128.1-39771.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec58" +attribute \generator "nMigen" +module \dec58 + attribute \src "libresoc.v:39466.3-39481.6" + wire width 8 $0\dec58_asmcode[7:0] + attribute \src "libresoc.v:39530.3-39545.6" + wire $0\dec58_br[0:0] + attribute \src "libresoc.v:39738.3-39753.6" + wire width 3 $0\dec58_cr_in[2:0] + attribute \src "libresoc.v:39754.3-39769.6" + wire width 3 $0\dec58_cr_out[2:0] + attribute \src "libresoc.v:39450.3-39465.6" + wire width 2 $0\dec58_cry_in[1:0] + attribute \src "libresoc.v:39514.3-39529.6" + wire $0\dec58_cry_out[0:0] + attribute \src "libresoc.v:39658.3-39673.6" + wire width 5 $0\dec58_form[4:0] + attribute \src "libresoc.v:39386.3-39401.6" + wire width 12 $0\dec58_function_unit[11:0] + attribute \src "libresoc.v:39674.3-39689.6" + wire width 3 $0\dec58_in1_sel[2:0] + attribute \src "libresoc.v:39690.3-39705.6" + wire width 4 $0\dec58_in2_sel[3:0] + attribute \src "libresoc.v:39706.3-39721.6" + wire width 2 $0\dec58_in3_sel[1:0] + attribute \src "libresoc.v:39562.3-39577.6" + wire width 7 $0\dec58_internal_op[6:0] + attribute \src "libresoc.v:39482.3-39497.6" + wire $0\dec58_inv_a[0:0] + attribute \src "libresoc.v:39498.3-39513.6" + wire $0\dec58_inv_out[0:0] + attribute \src "libresoc.v:39594.3-39609.6" + wire $0\dec58_is_32b[0:0] + attribute \src "libresoc.v:39402.3-39417.6" + wire width 4 $0\dec58_ldst_len[3:0] + attribute \src "libresoc.v:39626.3-39641.6" + wire $0\dec58_lk[0:0] + attribute \src "libresoc.v:39722.3-39737.6" + wire width 2 $0\dec58_out_sel[1:0] + attribute \src "libresoc.v:39434.3-39449.6" + wire width 2 $0\dec58_rc_sel[1:0] + attribute \src "libresoc.v:39578.3-39593.6" + wire $0\dec58_rsrv[0:0] + attribute \src "libresoc.v:39642.3-39657.6" + wire $0\dec58_sgl_pipe[0:0] + attribute \src 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"libresoc.v:39610.3-39625.6" + wire $1\dec58_sgn[0:0] + attribute \src "libresoc.v:39546.3-39561.6" + wire $1\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:39418.3-39433.6" + wire width 2 $1\dec58_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec58_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec58_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec58_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec58_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec58_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec58_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec58_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec58_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec58_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec58_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec58_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec58_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec58_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec58_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec58_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec58_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec58_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec58_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec58_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec58_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec58_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec58_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec58_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec58_upd + attribute \src "libresoc.v:39129.7-39129.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 2 \opcode_switch + attribute \src "libresoc.v:39129.7-39129.20" + process $proc$libresoc.v:39129$841 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41309$2088 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_CR_cr_c_o - connect \B \rdpick_CR_cr_c_en_o - connect \Y $and$issuer_ls180.v:41309$2088_Y + attribute \src "libresoc.v:39386.3-39401.6" + process $proc$libresoc.v:39386$817 + assign { } { } + assign { } { } + assign $0\dec58_function_unit[11:0] $1\dec58_function_unit[11:0] + attribute \src "libresoc.v:39387.5-39387.29" + switch \initial + attribute \src "libresoc.v:39387.9-39387.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_function_unit[11:0] 12'000000000100 + case + assign $1\dec58_function_unit[11:0] 12'000000000000 + end + sync always + update \dec58_function_unit $0\dec58_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41313$2092 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$72 [0] - connect \B \fu_enable [2] - connect \Y $and$issuer_ls180.v:41313$2092_Y + attribute \src "libresoc.v:39402.3-39417.6" + process $proc$libresoc.v:39402$818 + assign { } { } + assign { } { } + assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0] + attribute \src "libresoc.v:39403.5-39403.29" + switch \initial + attribute \src "libresoc.v:39403.9-39403.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'0100 + case + assign $1\dec58_ldst_len[3:0] 4'0000 + end + sync always + update \dec58_ldst_len $0\dec58_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41314$2093 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$842 - connect \B \rdflag_FAST_fast1_0 - connect \Y $and$issuer_ls180.v:41314$2093_Y + attribute \src "libresoc.v:39418.3-39433.6" + process $proc$libresoc.v:39418$819 + assign { } { } + assign { } { } + assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] + attribute \src "libresoc.v:39419.5-39419.29" + switch \initial + attribute \src "libresoc.v:39419.9-39419.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_upd[1:0] 2'00 + case + assign $1\dec58_upd[1:0] 2'00 + end + sync always + update \dec58_upd $0\dec58_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41316$2095 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$844 - connect \B \$846 - connect \Y $and$issuer_ls180.v:41316$2095_Y + attribute \src "libresoc.v:39434.3-39449.6" + process $proc$libresoc.v:39434$820 + assign { } { } + assign { } { } + assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0] + attribute \src "libresoc.v:39435.5-39435.29" + switch \initial + attribute \src "libresoc.v:39435.9-39435.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + case + assign $1\dec58_rc_sel[1:0] 2'00 + end + sync always + update \dec58_rc_sel $0\dec58_rc_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41317$2096 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_FAST_fast1_o [0] - connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$issuer_ls180.v:41317$2096_Y + attribute \src "libresoc.v:39450.3-39465.6" + process $proc$libresoc.v:39450$821 + assign { } { } + assign { } { } + assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0] + attribute \src "libresoc.v:39451.5-39451.29" + switch \initial + attribute \src "libresoc.v:39451.9-39451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + case + assign $1\dec58_cry_in[1:0] 2'00 + end + sync always + update \dec58_cry_in $0\dec58_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41319$2098 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$34 [2] - connect \B \fu_enable [3] - connect \Y $and$issuer_ls180.v:41319$2098_Y + attribute \src "libresoc.v:39466.3-39481.6" + process $proc$libresoc.v:39466$822 + assign { } { } + assign { } { } + assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0] + attribute \src "libresoc.v:39467.5-39467.29" + switch \initial + attribute \src "libresoc.v:39467.9-39467.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01010010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01010101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01100010 + case + assign $1\dec58_asmcode[7:0] 8'00000000 + end + sync always + update \dec58_asmcode $0\dec58_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41320$2099 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$854 - connect \B \rdflag_FAST_fast1_0 - connect \Y $and$issuer_ls180.v:41320$2099_Y + attribute \src "libresoc.v:39482.3-39497.6" + process $proc$libresoc.v:39482$823 + assign { } { } + assign { } { } + assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0] + attribute \src "libresoc.v:39483.5-39483.29" + switch \initial + attribute \src "libresoc.v:39483.9-39483.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + case + assign $1\dec58_inv_a[0:0] 1'0 + end + sync always + update \dec58_inv_a $0\dec58_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41322$2101 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$856 - connect \B \$858 - connect \Y $and$issuer_ls180.v:41322$2101_Y + attribute \src "libresoc.v:39498.3-39513.6" + process $proc$libresoc.v:39498$824 + assign { } { } + assign { } { } + assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0] + attribute \src "libresoc.v:39499.5-39499.29" + switch \initial + attribute \src "libresoc.v:39499.9-39499.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + case + assign $1\dec58_inv_out[0:0] 1'0 + end + sync always + update \dec58_inv_out $0\dec58_inv_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41323$2102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_FAST_fast1_o [1] - connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$issuer_ls180.v:41323$2102_Y + attribute \src "libresoc.v:39514.3-39529.6" + process $proc$libresoc.v:39514$825 + assign { } { } + assign { } { } + assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0] + attribute \src "libresoc.v:39515.5-39515.29" + switch \initial + attribute \src "libresoc.v:39515.9-39515.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + case + assign $1\dec58_cry_out[0:0] 1'0 + end + sync always + update \dec58_cry_out $0\dec58_cry_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41325$2104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$40 [2] - connect \B \fu_enable [5] - connect \Y $and$issuer_ls180.v:41325$2104_Y + attribute \src "libresoc.v:39530.3-39545.6" + process $proc$libresoc.v:39530$826 + assign { } { } + assign { } { } + assign $0\dec58_br[0:0] $1\dec58_br[0:0] + attribute \src "libresoc.v:39531.5-39531.29" + switch \initial + attribute \src "libresoc.v:39531.9-39531.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + case + assign $1\dec58_br[0:0] 1'0 + end + sync always + update \dec58_br $0\dec58_br[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41326$2105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$866 - connect \B \rdflag_FAST_fast1_0 - connect \Y $and$issuer_ls180.v:41326$2105_Y + attribute \src "libresoc.v:39546.3-39561.6" + process $proc$libresoc.v:39546$827 + assign { } { } + assign { } { } + assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:39547.5-39547.29" + switch \initial + attribute \src "libresoc.v:39547.9-39547.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'1 + case + assign $1\dec58_sgn_ext[0:0] 1'0 + end + sync always + update \dec58_sgn_ext $0\dec58_sgn_ext[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41328$2107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$868 - connect \B \$870 - connect \Y $and$issuer_ls180.v:41328$2107_Y + attribute \src "libresoc.v:39562.3-39577.6" + process $proc$libresoc.v:39562$828 + assign { } { } + assign { } { } + assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] + attribute \src "libresoc.v:39563.5-39563.29" + switch \initial + attribute \src "libresoc.v:39563.9-39563.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + case + assign $1\dec58_internal_op[6:0] 7'0000000 + end + sync always + update \dec58_internal_op $0\dec58_internal_op[6:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41329$2108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_FAST_fast1_o [2] - connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$issuer_ls180.v:41329$2108_Y + attribute \src "libresoc.v:39578.3-39593.6" + process $proc$libresoc.v:39578$829 + assign { } { } + assign { } { } + assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0] + attribute \src "libresoc.v:39579.5-39579.29" + switch \initial + attribute \src "libresoc.v:39579.9-39579.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + case + assign $1\dec58_rsrv[0:0] 1'0 + end + sync always + update \dec58_rsrv $0\dec58_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41334$2113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$72 [1] - connect \B \fu_enable [2] - connect \Y $and$issuer_ls180.v:41334$2113_Y + attribute \src "libresoc.v:39594.3-39609.6" + process $proc$libresoc.v:39594$830 + assign { } { } + assign { } { } + assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] + attribute \src "libresoc.v:39595.5-39595.29" + switch \initial + attribute \src "libresoc.v:39595.9-39595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + case + assign $1\dec58_is_32b[0:0] 1'0 + end + sync always + update \dec58_is_32b $0\dec58_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41335$2114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$884 - connect \B \rdflag_FAST_fast2_0 - connect \Y $and$issuer_ls180.v:41335$2114_Y + attribute \src "libresoc.v:39610.3-39625.6" + process $proc$libresoc.v:39610$831 + assign { } { } + assign { } { } + assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0] + attribute \src "libresoc.v:39611.5-39611.29" + switch \initial + attribute \src "libresoc.v:39611.9-39611.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + case + assign $1\dec58_sgn[0:0] 1'0 + end + sync always + update \dec58_sgn $0\dec58_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41337$2116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$886 - connect \B \$888 - connect \Y $and$issuer_ls180.v:41337$2116_Y + attribute \src "libresoc.v:39626.3-39641.6" + process $proc$libresoc.v:39626$832 + assign { } { } + assign { } { } + assign $0\dec58_lk[0:0] $1\dec58_lk[0:0] + attribute \src "libresoc.v:39627.5-39627.29" + switch \initial + attribute \src "libresoc.v:39627.9-39627.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + case + assign $1\dec58_lk[0:0] 1'0 + end + sync always + update \dec58_lk $0\dec58_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41338$2117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_FAST_fast2_o [0] - connect \B \rdpick_FAST_fast2_en_o - connect \Y $and$issuer_ls180.v:41338$2117_Y + attribute \src "libresoc.v:39642.3-39657.6" + process $proc$libresoc.v:39642$833 + assign { } { } + assign { } { } + assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:39643.5-39643.29" + switch \initial + attribute \src "libresoc.v:39643.9-39643.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + case + assign $1\dec58_sgl_pipe[0:0] 1'0 + end + sync always + update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41340$2119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$34 [3] - connect \B \fu_enable [3] - connect \Y $and$issuer_ls180.v:41340$2119_Y + attribute \src "libresoc.v:39658.3-39673.6" + process $proc$libresoc.v:39658$834 + assign { } { } + assign { } { } + assign $0\dec58_form[4:0] $1\dec58_form[4:0] + attribute \src "libresoc.v:39659.5-39659.29" + switch \initial + attribute \src "libresoc.v:39659.9-39659.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + case + assign $1\dec58_form[4:0] 5'00000 + end + sync always + update \dec58_form $0\dec58_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41341$2120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$896 - connect \B \rdflag_FAST_fast2_0 - connect \Y $and$issuer_ls180.v:41341$2120_Y + attribute \src "libresoc.v:39674.3-39689.6" + process $proc$libresoc.v:39674$835 + assign { } { } + assign { } { } + assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0] + attribute \src "libresoc.v:39675.5-39675.29" + switch \initial + attribute \src "libresoc.v:39675.9-39675.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + case + assign $1\dec58_in1_sel[2:0] 3'000 + end + sync always + update \dec58_in1_sel $0\dec58_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41343$2122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$898 - connect \B \$900 - connect \Y $and$issuer_ls180.v:41343$2122_Y + attribute \src "libresoc.v:39690.3-39705.6" + process $proc$libresoc.v:39690$836 + assign { } { } + assign { } { } + assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0] + attribute \src "libresoc.v:39691.5-39691.29" + switch \initial + attribute \src "libresoc.v:39691.9-39691.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + case + assign $1\dec58_in2_sel[3:0] 4'0000 + end + sync always + update \dec58_in2_sel $0\dec58_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41344$2123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_FAST_fast2_o [1] - connect \B \rdpick_FAST_fast2_en_o - connect \Y $and$issuer_ls180.v:41344$2123_Y + attribute \src "libresoc.v:39706.3-39721.6" + process $proc$libresoc.v:39706$837 + assign { } { } + assign { } { } + assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0] + attribute \src "libresoc.v:39707.5-39707.29" + switch \initial + attribute \src "libresoc.v:39707.9-39707.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + case + assign $1\dec58_in3_sel[1:0] 2'00 + end + sync always + update \dec58_in3_sel $0\dec58_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41348$2127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$40 [1] - connect \B \fu_enable [5] - connect \Y $and$issuer_ls180.v:41348$2127_Y + attribute \src "libresoc.v:39722.3-39737.6" + process $proc$libresoc.v:39722$838 + assign { } { } + assign { } { } + assign $0\dec58_out_sel[1:0] $1\dec58_out_sel[1:0] + attribute \src "libresoc.v:39723.5-39723.29" + switch \initial + attribute \src "libresoc.v:39723.9-39723.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_out_sel[1:0] 2'01 + case + assign $1\dec58_out_sel[1:0] 2'00 + end + sync always + update \dec58_out_sel $0\dec58_out_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $and$issuer_ls180.v:41349$2128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$912 - connect \B \rdflag_SPR_spr1_0 - connect \Y $and$issuer_ls180.v:41349$2128_Y + attribute \src "libresoc.v:39738.3-39753.6" + process $proc$libresoc.v:39738$839 + assign { } { } + assign { } { } + assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0] + attribute \src "libresoc.v:39739.5-39739.29" + switch \initial + attribute \src "libresoc.v:39739.9-39739.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + case + assign $1\dec58_cr_in[2:0] 3'000 + end + sync always + update \dec58_cr_in $0\dec58_cr_in[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $and$issuer_ls180.v:41351$2130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$914 - connect \B \$916 - connect \Y $and$issuer_ls180.v:41351$2130_Y + attribute \src "libresoc.v:39754.3-39769.6" + process $proc$libresoc.v:39754$840 + assign { } { } + assign { } { } + assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0] + attribute \src "libresoc.v:39755.5-39755.29" + switch \initial + attribute \src "libresoc.v:39755.9-39755.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + case + assign $1\dec58_cr_out[2:0] 3'000 + end + sync always + update \dec58_cr_out $0\dec58_cr_out[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$issuer_ls180.v:41352$2131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_SPR_spr1_o - connect \B \rdpick_SPR_spr1_en_o - connect \Y $and$issuer_ls180.v:41352$2131_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:41355$2134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok - connect \B \fus_cu_busy_o - connect \Y $and$issuer_ls180.v:41355$2134_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:41356$2135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o [0] - connect \B \fu_enable [0] - connect \Y $and$issuer_ls180.v:41356$2135_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:41357$2136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$84 [0] - connect \B \fu_enable [1] - connect \Y $and$issuer_ls180.v:41357$2136_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:41358$2137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$87 [0] - connect \B \fu_enable [3] - connect \Y $and$issuer_ls180.v:41358$2137_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:41359$2138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$90 [0] - connect \B \fu_enable [4] - connect \Y $and$issuer_ls180.v:41359$2138_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:41360$2139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [0] - connect \B \fu_enable [5] - connect \Y $and$issuer_ls180.v:41360$2139_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:41361$2140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$96 [0] - connect \B \fu_enable [6] - connect \Y $and$issuer_ls180.v:41361$2140_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:41362$2141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$99 [0] - connect \B \fu_enable [7] - connect \Y $and$issuer_ls180.v:41362$2141_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:41363$2142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$102 [0] - connect \B \fu_enable [8] - connect \Y $and$issuer_ls180.v:41363$2142_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:41364$2143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$104 [0] - connect \B \fu_enable [9] - connect \Y $and$issuer_ls180.v:41364$2143_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $and$issuer_ls180.v:41365$2144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$104 [1] - connect \B \fu_enable [9] - connect \Y $and$issuer_ls180.v:41365$2144_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:41366$2145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [0] - connect \B \wrpick_INT_o_en_o - connect \Y $and$issuer_ls180.v:41366$2145_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:41368$2147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick - connect \B \$950 - connect \Y $and$issuer_ls180.v:41368$2147_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:41369$2148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick - connect \B \wrpick_INT_o_en_o - connect \Y $and$issuer_ls180.v:41369$2148_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:41371$2150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok$83 - connect \B \fus_cu_busy_o$5 - connect \Y $and$issuer_ls180.v:41371$2150_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:41372$2151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [1] - connect \B \wrpick_INT_o_en_o - connect \Y $and$issuer_ls180.v:41372$2151_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:41374$2153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$964 - connect \B \$969 - connect \Y $and$issuer_ls180.v:41374$2153_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:41375$2154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$964 - connect \B \wrpick_INT_o_en_o - connect \Y $and$issuer_ls180.v:41375$2154_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $and$issuer_ls180.v:41377$2156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok$86 - connect \B \fus_cu_busy_o$11 - connect \Y $and$issuer_ls180.v:41377$2156_Y + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "libresoc.v:39775.1-40346.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec62" +attribute \generator "nMigen" +module \dec62 + attribute \src "libresoc.v:40098.3-40110.6" + wire width 8 $0\dec62_asmcode[7:0] + attribute \src "libresoc.v:40150.3-40162.6" + wire $0\dec62_br[0:0] + attribute \src "libresoc.v:40319.3-40331.6" + wire width 3 $0\dec62_cr_in[2:0] + attribute \src "libresoc.v:40332.3-40344.6" + wire width 3 $0\dec62_cr_out[2:0] + attribute \src "libresoc.v:40085.3-40097.6" + wire width 2 $0\dec62_cry_in[1:0] + attribute \src "libresoc.v:40137.3-40149.6" + wire $0\dec62_cry_out[0:0] + attribute \src "libresoc.v:40254.3-40266.6" + wire width 5 $0\dec62_form[4:0] + attribute \src "libresoc.v:40033.3-40045.6" + wire width 12 $0\dec62_function_unit[11:0] + attribute \src "libresoc.v:40267.3-40279.6" + wire width 3 $0\dec62_in1_sel[2:0] + attribute \src "libresoc.v:40280.3-40292.6" + wire width 4 $0\dec62_in2_sel[3:0] + attribute \src "libresoc.v:40293.3-40305.6" + wire width 2 $0\dec62_in3_sel[1:0] + attribute \src "libresoc.v:40176.3-40188.6" + wire width 7 $0\dec62_internal_op[6:0] + attribute \src "libresoc.v:40111.3-40123.6" + wire $0\dec62_inv_a[0:0] + attribute \src "libresoc.v:40124.3-40136.6" + wire $0\dec62_inv_out[0:0] + attribute \src "libresoc.v:40202.3-40214.6" + wire $0\dec62_is_32b[0:0] + attribute \src "libresoc.v:40046.3-40058.6" + wire width 4 $0\dec62_ldst_len[3:0] + attribute \src "libresoc.v:40228.3-40240.6" + wire $0\dec62_lk[0:0] + attribute \src "libresoc.v:40306.3-40318.6" + wire width 2 $0\dec62_out_sel[1:0] + attribute \src "libresoc.v:40072.3-40084.6" + wire width 2 $0\dec62_rc_sel[1:0] + attribute \src "libresoc.v:40189.3-40201.6" + wire $0\dec62_rsrv[0:0] + attribute \src "libresoc.v:40241.3-40253.6" + wire $0\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:40215.3-40227.6" + wire $0\dec62_sgn[0:0] + attribute \src "libresoc.v:40163.3-40175.6" + wire $0\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:40059.3-40071.6" + wire width 2 $0\dec62_upd[1:0] + attribute \src "libresoc.v:39776.7-39776.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:40098.3-40110.6" + wire width 8 $1\dec62_asmcode[7:0] + attribute \src "libresoc.v:40150.3-40162.6" + wire $1\dec62_br[0:0] + attribute \src "libresoc.v:40319.3-40331.6" + wire width 3 $1\dec62_cr_in[2:0] + attribute \src "libresoc.v:40332.3-40344.6" + wire width 3 $1\dec62_cr_out[2:0] + attribute \src "libresoc.v:40085.3-40097.6" + wire width 2 $1\dec62_cry_in[1:0] + attribute \src "libresoc.v:40137.3-40149.6" + wire $1\dec62_cry_out[0:0] + attribute \src "libresoc.v:40254.3-40266.6" + wire width 5 $1\dec62_form[4:0] + attribute \src "libresoc.v:40033.3-40045.6" + wire width 12 $1\dec62_function_unit[11:0] + attribute \src "libresoc.v:40267.3-40279.6" + wire width 3 $1\dec62_in1_sel[2:0] + attribute \src "libresoc.v:40280.3-40292.6" + wire width 4 $1\dec62_in2_sel[3:0] + attribute \src "libresoc.v:40293.3-40305.6" + wire width 2 $1\dec62_in3_sel[1:0] + attribute \src "libresoc.v:40176.3-40188.6" + wire width 7 $1\dec62_internal_op[6:0] + attribute \src "libresoc.v:40111.3-40123.6" + wire $1\dec62_inv_a[0:0] + attribute \src "libresoc.v:40124.3-40136.6" + wire $1\dec62_inv_out[0:0] + attribute \src "libresoc.v:40202.3-40214.6" + wire $1\dec62_is_32b[0:0] + attribute \src "libresoc.v:40046.3-40058.6" + wire width 4 $1\dec62_ldst_len[3:0] + attribute \src "libresoc.v:40228.3-40240.6" + wire $1\dec62_lk[0:0] + attribute \src "libresoc.v:40306.3-40318.6" + wire width 2 $1\dec62_out_sel[1:0] + attribute \src "libresoc.v:40072.3-40084.6" + wire width 2 $1\dec62_rc_sel[1:0] + attribute \src "libresoc.v:40189.3-40201.6" + wire $1\dec62_rsrv[0:0] + attribute \src "libresoc.v:40241.3-40253.6" + wire $1\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:40215.3-40227.6" + wire $1\dec62_sgn[0:0] + attribute \src "libresoc.v:40163.3-40175.6" + wire $1\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:40059.3-40071.6" + wire width 2 $1\dec62_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec62_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec62_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec62_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec62_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec62_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec62_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec62_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec62_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec62_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec62_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec62_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec62_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec62_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec62_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec62_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec62_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec62_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec62_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec62_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec62_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec62_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec62_upd + attribute \src "libresoc.v:39776.7-39776.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 2 \opcode_switch + attribute \src "libresoc.v:39776.7-39776.20" + process $proc$libresoc.v:39776$866 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $and$issuer_ls180.v:41378$2157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [2] - connect \B \wrpick_INT_o_en_o - connect \Y $and$issuer_ls180.v:41378$2157_Y + attribute \src "libresoc.v:40033.3-40045.6" + process $proc$libresoc.v:40033$842 + assign { } { } + assign { } { } + assign $0\dec62_function_unit[11:0] $1\dec62_function_unit[11:0] + attribute \src "libresoc.v:40034.5-40034.29" + switch \initial + attribute \src "libresoc.v:40034.9-40034.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_function_unit[11:0] 12'000000000100 + case + assign $1\dec62_function_unit[11:0] 12'000000000000 + end + sync always + update \dec62_function_unit $0\dec62_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:41380$2159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$983 - connect \B \$988 - connect \Y $and$issuer_ls180.v:41380$2159_Y + attribute \src "libresoc.v:40046.3-40058.6" + process $proc$libresoc.v:40046$843 + assign { } { } + assign { } { } + assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0] + attribute \src "libresoc.v:40047.5-40047.29" + switch \initial + attribute \src "libresoc.v:40047.9-40047.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_ldst_len[3:0] 4'1000 + case + assign $1\dec62_ldst_len[3:0] 4'0000 + end + sync always + update \dec62_ldst_len $0\dec62_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$issuer_ls180.v:41381$2160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$983 - connect \B \wrpick_INT_o_en_o - connect \Y $and$issuer_ls180.v:41381$2160_Y + attribute \src "libresoc.v:40059.3-40071.6" + process $proc$libresoc.v:40059$844 + assign { } { } + assign { } { } + assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] + attribute \src "libresoc.v:40060.5-40060.29" + switch \initial + attribute \src "libresoc.v:40060.9-40060.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_upd[1:0] 2'01 + case + assign $1\dec62_upd[1:0] 2'00 + end + sync always + update \dec62_upd $0\dec62_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$issuer_ls180.v:40998$1775 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$210 - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:40998$1775_Y + attribute \src "libresoc.v:40072.3-40084.6" + process $proc$libresoc.v:40072$845 + assign { } { } + assign { } { } + assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0] + attribute \src "libresoc.v:40073.5-40073.29" + switch \initial + attribute \src "libresoc.v:40073.9-40073.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_rc_sel[1:0] 2'00 + case + assign $1\dec62_rc_sel[1:0] 2'00 + end + sync always + update \dec62_rc_sel $0\dec62_rc_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$issuer_ls180.v:41002$1779 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \core_core_input_carry - connect \B 2'10 - connect \Y $eq$issuer_ls180.v:41002$1779_Y + attribute \src "libresoc.v:40085.3-40097.6" + process $proc$libresoc.v:40085$846 + assign { } { } + assign { } { } + assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0] + attribute \src "libresoc.v:40086.5-40086.29" + switch \initial + attribute \src "libresoc.v:40086.9-40086.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cry_in[1:0] 2'00 + case + assign $1\dec62_cry_in[1:0] 2'00 + end + sync always + update \dec62_cry_in $0\dec62_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$issuer_ls180.v:41004$1781 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \$222 - connect \B 3'100 - connect \Y $eq$issuer_ls180.v:41004$1781_Y + attribute \src "libresoc.v:40098.3-40110.6" + process $proc$libresoc.v:40098$847 + assign { } { } + assign { } { } + assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0] + attribute \src "libresoc.v:40099.5-40099.29" + switch \initial + attribute \src "libresoc.v:40099.9-40099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_asmcode[7:0] 8'10101100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_asmcode[7:0] 8'10101111 + case + assign $1\dec62_asmcode[7:0] 8'00000000 + end + sync always + update \dec62_asmcode $0\dec62_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$issuer_ls180.v:41012$1789 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$238 - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:41012$1789_Y + attribute \src "libresoc.v:40111.3-40123.6" + process $proc$libresoc.v:40111$848 + assign { } { } + assign { } { } + assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0] + attribute \src "libresoc.v:40112.5-40112.29" + switch \initial + attribute \src "libresoc.v:40112.9-40112.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_inv_a[0:0] 1'0 + case + assign $1\dec62_inv_a[0:0] 1'0 + end + sync always + update \dec62_inv_a $0\dec62_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$issuer_ls180.v:41019$1796 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$252 - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:41019$1796_Y + attribute \src "libresoc.v:40124.3-40136.6" + process $proc$libresoc.v:40124$849 + assign { } { } + assign { } { } + assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0] + attribute \src "libresoc.v:40125.5-40125.29" + switch \initial + attribute \src "libresoc.v:40125.9-40125.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_inv_out[0:0] 1'0 + case + assign $1\dec62_inv_out[0:0] 1'0 + end + sync always + update \dec62_inv_out $0\dec62_inv_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $eq $eq$issuer_ls180.v:41025$1802 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \$264 - connect \B 2'10 - connect \Y $eq$issuer_ls180.v:41025$1802_Y + attribute \src "libresoc.v:40137.3-40149.6" + process $proc$libresoc.v:40137$850 + assign { } { } + assign { } { } + assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0] + attribute \src "libresoc.v:40138.5-40138.29" + switch \initial + attribute \src "libresoc.v:40138.9-40138.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cry_out[0:0] 1'0 + case + assign $1\dec62_cry_out[0:0] 1'0 + end + sync always + update \dec62_cry_out $0\dec62_cry_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$issuer_ls180.v:41027$1804 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \core_core_input_carry - connect \B 2'10 - connect \Y $eq$issuer_ls180.v:41027$1804_Y + attribute \src "libresoc.v:40150.3-40162.6" + process $proc$libresoc.v:40150$851 + assign { } { } + assign { } { } + assign $0\dec62_br[0:0] $1\dec62_br[0:0] + attribute \src "libresoc.v:40151.5-40151.29" + switch \initial + attribute \src "libresoc.v:40151.9-40151.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_br[0:0] 1'0 + case + assign $1\dec62_br[0:0] 1'0 + end + sync always + update \dec62_br $0\dec62_br[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$issuer_ls180.v:41029$1806 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \$272 - connect \B 3'100 - connect \Y $eq$issuer_ls180.v:41029$1806_Y + attribute \src "libresoc.v:40163.3-40175.6" + process $proc$libresoc.v:40163$852 + assign { } { } + assign { } { } + assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:40164.5-40164.29" + switch \initial + attribute \src "libresoc.v:40164.9-40164.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sgn_ext[0:0] 1'0 + case + assign $1\dec62_sgn_ext[0:0] 1'0 + end + sync always + update \dec62_sgn_ext $0\dec62_sgn_ext[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$issuer_ls180.v:41034$1811 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$282 - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:41034$1811_Y + attribute \src "libresoc.v:40176.3-40188.6" + process $proc$libresoc.v:40176$853 + assign { } { } + assign { } { } + assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] + attribute \src "libresoc.v:40177.5-40177.29" + switch \initial + attribute \src "libresoc.v:40177.9-40177.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_internal_op[6:0] 7'0100110 + case + assign $1\dec62_internal_op[6:0] 7'0000000 + end + sync always + update \dec62_internal_op $0\dec62_internal_op[6:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$issuer_ls180.v:41041$1818 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$296 - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:41041$1818_Y + attribute \src "libresoc.v:40189.3-40201.6" + process $proc$libresoc.v:40189$854 + assign { } { } + assign { } { } + assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0] + attribute \src "libresoc.v:40190.5-40190.29" + switch \initial + attribute \src "libresoc.v:40190.9-40190.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_rsrv[0:0] 1'0 + case + assign $1\dec62_rsrv[0:0] 1'0 + end + sync always + update \dec62_rsrv $0\dec62_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$issuer_ls180.v:41048$1825 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$310 - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:41048$1825_Y + attribute \src "libresoc.v:40202.3-40214.6" + process $proc$libresoc.v:40202$855 + assign { } { } + assign { } { } + assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] + attribute \src "libresoc.v:40203.5-40203.29" + switch \initial + attribute \src "libresoc.v:40203.9-40203.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_is_32b[0:0] 1'0 + case + assign $1\dec62_is_32b[0:0] 1'0 + end + sync always + update \dec62_is_32b $0\dec62_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$issuer_ls180.v:41052$1829 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \core_core_input_carry - connect \B 2'10 - connect \Y $eq$issuer_ls180.v:41052$1829_Y + attribute \src "libresoc.v:40215.3-40227.6" + process $proc$libresoc.v:40215$856 + assign { } { } + assign { } { } + assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0] + attribute \src "libresoc.v:40216.5-40216.29" + switch \initial + attribute \src "libresoc.v:40216.9-40216.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sgn[0:0] 1'0 + case + assign $1\dec62_sgn[0:0] 1'0 + end + sync always + update \dec62_sgn $0\dec62_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$issuer_ls180.v:41054$1831 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \$322 - connect \B 3'100 - connect \Y $eq$issuer_ls180.v:41054$1831_Y + attribute \src "libresoc.v:40228.3-40240.6" + process $proc$libresoc.v:40228$857 + assign { } { } + assign { } { } + assign $0\dec62_lk[0:0] $1\dec62_lk[0:0] + attribute \src "libresoc.v:40229.5-40229.29" + switch \initial + attribute \src "libresoc.v:40229.9-40229.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_lk[0:0] 1'0 + case + assign $1\dec62_lk[0:0] 1'0 + end + sync always + update \dec62_lk $0\dec62_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$issuer_ls180.v:41193$1970 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$599 - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:41193$1970_Y + attribute \src "libresoc.v:40241.3-40253.6" + process $proc$libresoc.v:40241$858 + assign { } { } + assign { } { } + assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:40242.5-40242.29" + switch \initial + attribute \src "libresoc.v:40242.9-40242.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sgl_pipe[0:0] 1'1 + case + assign $1\dec62_sgl_pipe[0:0] 1'0 + end + sync always + update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$issuer_ls180.v:41239$2017 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \core_core_input_carry - connect \B 2'10 - connect \Y $eq$issuer_ls180.v:41239$2017_Y + attribute \src "libresoc.v:40254.3-40266.6" + process $proc$libresoc.v:40254$859 + assign { } { } + assign { } { } + assign $0\dec62_form[4:0] $1\dec62_form[4:0] + attribute \src "libresoc.v:40255.5-40255.29" + switch \initial + attribute \src "libresoc.v:40255.9-40255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_form[4:0] 5'00101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_form[4:0] 5'00101 + case + assign $1\dec62_form[4:0] 5'00000 + end + sync always + update \dec62_form $0\dec62_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$issuer_ls180.v:41241$2019 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \$695 - connect \B 3'100 - connect \Y $eq$issuer_ls180.v:41241$2019_Y + attribute \src "libresoc.v:40267.3-40279.6" + process $proc$libresoc.v:40267$860 + assign { } { } + assign { } { } + assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0] + attribute \src "libresoc.v:40268.5-40268.29" + switch \initial + attribute \src "libresoc.v:40268.9-40268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in1_sel[2:0] 3'010 + case + assign $1\dec62_in1_sel[2:0] 3'000 + end + sync always + update \dec62_in1_sel $0\dec62_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $eq $eq$issuer_ls180.v:41266$2045 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \$745 - connect \B 2'10 - connect \Y $eq$issuer_ls180.v:41266$2045_Y + attribute \src "libresoc.v:40280.3-40292.6" + process $proc$libresoc.v:40280$861 + assign { } { } + assign { } { } + assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0] + attribute \src "libresoc.v:40281.5-40281.29" + switch \initial + attribute \src "libresoc.v:40281.9-40281.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in2_sel[3:0] 4'1000 + case + assign $1\dec62_in2_sel[3:0] 4'0000 + end + sync always + update \dec62_in2_sel $0\dec62_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $extend$issuer_ls180.v:40823$1595 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A \$1422 - connect \Y $extend$issuer_ls180.v:40823$1595_Y + attribute \src "libresoc.v:40293.3-40305.6" + process $proc$libresoc.v:40293$862 + assign { } { } + assign { } { } + assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0] + attribute \src "libresoc.v:40294.5-40294.29" + switch \initial + attribute \src "libresoc.v:40294.9-40294.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in3_sel[1:0] 2'01 + case + assign $1\dec62_in3_sel[1:0] 2'00 + end + sync always + update \dec62_in3_sel $0\dec62_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $extend$issuer_ls180.v:40889$1662 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \$1586 - connect \Y $extend$issuer_ls180.v:40889$1662_Y + attribute \src "libresoc.v:40306.3-40318.6" + process $proc$libresoc.v:40306$863 + assign { } { } + assign { } { } + assign $0\dec62_out_sel[1:0] $1\dec62_out_sel[1:0] + attribute \src "libresoc.v:40307.5-40307.29" + switch \initial + attribute \src "libresoc.v:40307.9-40307.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_out_sel[1:0] 2'00 + case + assign $1\dec62_out_sel[1:0] 2'00 + end + sync always + update \dec62_out_sel $0\dec62_out_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $extend$issuer_ls180.v:40893$1667 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \$1594 - connect \Y $extend$issuer_ls180.v:40893$1667_Y + attribute \src "libresoc.v:40319.3-40331.6" + process $proc$libresoc.v:40319$864 + assign { } { } + assign { } { } + assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0] + attribute \src "libresoc.v:40320.5-40320.29" + switch \initial + attribute \src "libresoc.v:40320.9-40320.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } 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+ cell $and $and$libresoc.v:40744$881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1124 - connect \Y $not$issuer_ls180.v:40696$1468_Y + connect \A \$3 + connect \B \$5 + connect \Y $and$libresoc.v:40744$881_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40730$1502 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" + cell $eq $eq$libresoc.v:40731$868 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1197 - connect \Y $not$issuer_ls180.v:40730$1502_Y + connect \A \sel_in + connect \B 3'100 + connect \Y $eq$libresoc.v:40731$868_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40742$1514 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" + cell $eq $eq$libresoc.v:40732$869 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1225 - connect \Y $not$issuer_ls180.v:40742$1514_Y + connect \A \sel_in + connect \B 3'001 + connect \Y $eq$libresoc.v:40732$869_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40750$1522 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + cell $eq $eq$libresoc.v:40733$870 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1245 - connect \Y $not$issuer_ls180.v:40750$1522_Y + connect \A \sel_in + connect \B 3'010 + connect \Y $eq$libresoc.v:40733$870_Y end - attribute \src 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3'100 + connect \Y $eq$libresoc.v:40738$875_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40774$1546 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + cell $eq $eq$libresoc.v:40742$879 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1305 - connect \Y $not$issuer_ls180.v:40774$1546_Y + connect \A \sel_in + connect \B 3'010 + connect \Y $eq$libresoc.v:40742$879_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40782$1554 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + cell $ne $ne$libresoc.v:40734$871 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1325 - connect \Y $not$issuer_ls180.v:40782$1554_Y + connect \A \ra + connect \B 5'00000 + connect \Y $ne$libresoc.v:40734$871_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40803$1575 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + cell $ne $ne$libresoc.v:40743$880 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1372 - connect \Y $not$issuer_ls180.v:40803$1575_Y + connect \A \ra + connect \B 5'00000 + connect \Y $ne$libresoc.v:40743$880_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40809$1581 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" + cell $not $not$libresoc.v:40739$876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1388 - connect \Y $not$issuer_ls180.v:40809$1581_Y + connect \A \BO [2] + connect \Y $not$libresoc.v:40739$876_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40815$1587 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" + cell $not $not$libresoc.v:40740$877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1404 - connect \Y $not$issuer_ls180.v:40815$1587_Y + connect \A \XL_XO [5] + connect \Y $not$libresoc.v:40740$877_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40830$1603 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + cell $or $or$libresoc.v:40730$867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1438 - connect \Y $not$issuer_ls180.v:40830$1603_Y + connect \A \$1 + connect \B \$7 + connect \Y $or$libresoc.v:40730$867_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40836$1609 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + cell $or $or$libresoc.v:40737$874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1454 - connect \Y $not$issuer_ls180.v:40836$1609_Y + connect \A \$13 + connect \B \$19 + connect \Y $or$libresoc.v:40737$874_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40842$1615 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1470 - connect \Y $not$issuer_ls180.v:40842$1615_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:40745.10-40751.4" + cell \sprmap \sprmap + connect \fast_o \sprmap_fast_o + connect \fast_o_ok \sprmap_fast_o_ok + connect \spr_i \sprmap_spr_i + connect \spr_o \sprmap_spr_o + connect \spr_o_ok \sprmap_spr_o_ok end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40848$1621 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1486 - connect \Y $not$issuer_ls180.v:40848$1621_Y + attribute \src "libresoc.v:40351.7-40351.20" + process $proc$libresoc.v:40351$888 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40864$1637 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1522 - connect \Y $not$issuer_ls180.v:40864$1637_Y + attribute \src "libresoc.v:40752.3-40767.6" + process $proc$libresoc.v:40752$882 + assign { } { } + assign { } { } + assign { } { } + assign $0\reg_a[4:0] $2\reg_a[4:0] + attribute \src "libresoc.v:40753.5-40753.29" + switch \initial + attribute \src "libresoc.v:40753.9-40753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg_a[4:0] \ra + case + assign $1\reg_a[4:0] 5'00000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg_a[4:0] \RS + case + assign $2\reg_a[4:0] $1\reg_a[4:0] + end + sync always + update \reg_a $0\reg_a[4:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40870$1643 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1538 - connect \Y $not$issuer_ls180.v:40870$1643_Y + attribute \src "libresoc.v:40768.3-40783.6" + process $proc$libresoc.v:40768$883 + assign { } { } + assign { } { } + assign { } { } + assign $0\reg_a_ok[0:0] $2\reg_a_ok[0:0] + attribute \src "libresoc.v:40769.5-40769.29" + switch \initial + attribute \src "libresoc.v:40769.9-40769.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg_a_ok[0:0] 1'1 + case + assign $1\reg_a_ok[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg_a_ok[0:0] 1'1 + case + assign $2\reg_a_ok[0:0] $1\reg_a_ok[0:0] + end + sync always + update \reg_a_ok $0\reg_a_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40876$1649 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1554 - connect \Y $not$issuer_ls180.v:40876$1649_Y + attribute \src "libresoc.v:40784.3-40819.6" + process $proc$libresoc.v:40784$884 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast_a[2:0] $1\fast_a[2:0] + assign $0\fast_a_ok[0:0] $1\fast_a_ok[0:0] + attribute \src "libresoc.v:40785.5-40785.29" + switch \initial + attribute \src "libresoc.v:40785.9-40785.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign { } { } + assign { } { } + assign $1\fast_a[2:0] $2\fast_a[2:0] + assign $1\fast_a_ok[0:0] $2\fast_a_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\fast_a[2:0] 3'000 + assign $2\fast_a_ok[0:0] 1'1 + case + assign $2\fast_a[2:0] 3'000 + assign $2\fast_a_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign { } { } + assign { } { } + assign $1\fast_a[2:0] $3\fast_a[2:0] + assign $1\fast_a_ok[0:0] $3\fast_a_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $3\fast_a[2:0] 3'000 + assign $3\fast_a_ok[0:0] 1'1 + case + assign $3\fast_a[2:0] 3'000 + assign $3\fast_a_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 + assign { } { } + assign { } { } + assign { $1\fast_a_ok[0:0] $1\fast_a[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } + case + assign $1\fast_a[2:0] 3'000 + assign $1\fast_a_ok[0:0] 1'0 + end + sync always + update \fast_a $0\fast_a[2:0] + update \fast_a_ok $0\fast_a_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40882$1655 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1570 - connect \Y $not$issuer_ls180.v:40882$1655_Y + attribute \src "libresoc.v:40820.3-40830.6" + process $proc$libresoc.v:40820$885 + assign { } { } + assign { } { } + assign $0\spr[9:0] $1\spr[9:0] + attribute \src "libresoc.v:40821.5-40821.29" + switch \initial + attribute \src "libresoc.v:40821.9-40821.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 + assign { } { } + assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } + case + assign $1\spr[9:0] 10'0000000000 + end + sync always + update \spr $0\spr[9:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40901$1676 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1612 - connect \Y $not$issuer_ls180.v:40901$1676_Y + attribute \src "libresoc.v:40831.3-40841.6" + process $proc$libresoc.v:40831$886 + assign { } { } + assign { } { } + assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:40832.5-40832.29" + switch \initial + attribute \src "libresoc.v:40832.9-40832.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 + assign { } { } + assign $1\sprmap_spr_i[9:0] \spr + case + assign $1\sprmap_spr_i[9:0] 10'0000000000 + end + sync always + update \sprmap_spr_i $0\sprmap_spr_i[9:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40909$1684 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1631 - connect \Y $not$issuer_ls180.v:40909$1684_Y + attribute \src "libresoc.v:40842.3-40853.6" + process $proc$libresoc.v:40842$887 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\spr_a[9:0] $1\spr_a[9:0] + assign $0\spr_a_ok[0:0] $1\spr_a_ok[0:0] + attribute \src "libresoc.v:40843.5-40843.29" + switch \initial + attribute \src "libresoc.v:40843.9-40843.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 + assign { } { } + assign { } { } + assign { $1\spr_a_ok[0:0] $1\spr_a[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } + case + assign $1\spr_a[9:0] 10'0000000000 + assign $1\spr_a_ok[0:0] 1'0 + end + sync always + update \spr_a $0\spr_a[9:0] + update \spr_a_ok $0\spr_a_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40915$1690 + connect \$9 $or$libresoc.v:40730$867_Y + connect \$11 $eq$libresoc.v:40731$868_Y + connect \$13 $eq$libresoc.v:40732$869_Y + connect \$15 $eq$libresoc.v:40733$870_Y + connect \$17 $ne$libresoc.v:40734$871_Y + connect \$1 $eq$libresoc.v:40735$872_Y + connect \$19 $and$libresoc.v:40736$873_Y + connect \$21 $or$libresoc.v:40737$874_Y + connect \$23 $eq$libresoc.v:40738$875_Y + connect \$25 $not$libresoc.v:40739$876_Y + connect \$27 $not$libresoc.v:40740$877_Y + connect \$29 $and$libresoc.v:40741$878_Y + connect \$3 $eq$libresoc.v:40742$879_Y + connect \$5 $ne$libresoc.v:40743$880_Y + connect \$7 $and$libresoc.v:40744$881_Y + connect \ra \RA +end +attribute \src "libresoc.v:40859.1-41050.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_b" +attribute \generator "nMigen" +module \dec_b + attribute \src "libresoc.v:41014.3-41031.6" + wire width 3 $0\fast_b[2:0] + attribute \src "libresoc.v:41032.3-41049.6" + wire $0\fast_b_ok[0:0] + attribute \src "libresoc.v:40860.7-40860.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:40984.3-40998.6" + wire width 5 $0\reg_b[4:0] + attribute \src "libresoc.v:40999.3-41013.6" + wire $0\reg_b_ok[0:0] + attribute \src "libresoc.v:41014.3-41031.6" + wire width 3 $1\fast_b[2:0] + attribute \src "libresoc.v:41032.3-41049.6" + wire $1\fast_b_ok[0:0] + attribute \src "libresoc.v:40984.3-40998.6" + wire width 5 $1\reg_b[4:0] + attribute \src "libresoc.v:40999.3-41013.6" + wire $1\reg_b_ok[0:0] + attribute \src "libresoc.v:41014.3-41031.6" + wire width 3 $2\fast_b[2:0] + attribute \src "libresoc.v:41032.3-41049.6" + wire $2\fast_b_ok[0:0] + attribute \src "libresoc.v:40980.17-40980.117" + wire $eq$libresoc.v:40980$889_Y + attribute \src "libresoc.v:40982.17-40982.117" + wire $eq$libresoc.v:40982$891_Y + attribute \src "libresoc.v:40981.17-40981.107" + wire $not$libresoc.v:40981$890_Y + attribute \src "libresoc.v:40983.17-40983.107" + wire $not$libresoc.v:40983$892_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 6 \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 input 8 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 4 \fast_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 5 \fast_b_ok + attribute \src "libresoc.v:40860.7-40860.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 9 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 2 \reg_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \reg_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire width 4 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + cell $eq $eq$libresoc.v:40980$889 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1647 - connect \Y $not$issuer_ls180.v:40915$1690_Y + connect \A \internal_op + connect \B 7'0001000 + connect \Y $eq$libresoc.v:40980$889_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40922$1697 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + cell $eq $eq$libresoc.v:40982$891 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1663 - connect \Y $not$issuer_ls180.v:40922$1697_Y + connect \A \internal_op + connect \B 7'0001000 + connect \Y $eq$libresoc.v:40982$891_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40929$1704 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + cell $not $not$libresoc.v:40981$890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1679 - connect \Y $not$issuer_ls180.v:40929$1704_Y + connect \A \XL_XO [9] + connect \Y $not$libresoc.v:40981$890_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40951$1726 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + cell $not $not$libresoc.v:40983$892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1723 - connect \Y $not$issuer_ls180.v:40951$1726_Y + connect \A \XL_XO [9] + connect \Y $not$libresoc.v:40983$892_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40958$1733 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1739 - connect \Y $not$issuer_ls180.v:40958$1733_Y + attribute \src "libresoc.v:40860.7-40860.20" + process $proc$libresoc.v:40860$897 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40969$1745 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1763 - connect \Y $not$issuer_ls180.v:40969$1745_Y + attribute \src "libresoc.v:40984.3-40998.6" + process $proc$libresoc.v:40984$893 + assign { } { } + assign { } { } + assign $0\reg_b[4:0] $1\reg_b[4:0] + attribute \src "libresoc.v:40985.5-40985.29" + switch \initial + attribute \src "libresoc.v:40985.9-40985.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\reg_b[4:0] \RB + attribute \src "libresoc.v:0.0-0.0" + case 4'1101 + assign { } { } + assign $1\reg_b[4:0] \RS + case + assign $1\reg_b[4:0] 5'00000 + end + sync always + update \reg_b $0\reg_b[4:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:40978$1755 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1783 - connect \Y $not$issuer_ls180.v:40978$1755_Y + attribute \src "libresoc.v:40999.3-41013.6" + process $proc$libresoc.v:40999$894 + assign { } { } + assign { } { } + assign $0\reg_b_ok[0:0] $1\reg_b_ok[0:0] + attribute \src "libresoc.v:41000.5-41000.29" + switch \initial + attribute \src "libresoc.v:41000.9-41000.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\reg_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1101 + assign { } { } + assign $1\reg_b_ok[0:0] 1'1 + case + assign $1\reg_b_ok[0:0] 1'0 + end + sync always + update \reg_b_ok $0\reg_b_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" - cell $not $not$issuer_ls180.v:41006$1783 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { \$226 \$218 \core_reg2_ok \core_reg1_ok } - connect \Y $not$issuer_ls180.v:41006$1783_Y + attribute \src "libresoc.v:41014.3-41031.6" + process $proc$libresoc.v:41014$895 + assign { } { } + assign { } { } + assign $0\fast_b[2:0] $1\fast_b[2:0] + attribute \src "libresoc.v:41015.5-41015.29" + switch \initial + attribute \src "libresoc.v:41015.9-41015.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fast_b[2:0] $2\fast_b[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + switch { \XL_XO [5] \$3 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\fast_b[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\fast_b[2:0] 3'010 + case + assign $2\fast_b[2:0] 3'000 + end + case + assign $1\fast_b[2:0] 3'000 + end + sync always + update \fast_b $0\fast_b[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" - cell $not $not$issuer_ls180.v:41007$1784 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A { \core_cr_in2_ok$2 \core_cr_in2_ok \core_cr_in1_ok \core_core_cr_rd_ok \core_reg2_ok \core_reg1_ok } - connect \Y $not$issuer_ls180.v:41007$1784_Y + attribute \src "libresoc.v:41032.3-41049.6" + process $proc$libresoc.v:41032$896 + assign { } { } + assign { } { } + assign $0\fast_b_ok[0:0] $1\fast_b_ok[0:0] + attribute \src "libresoc.v:41033.5-41033.29" + switch \initial + attribute \src "libresoc.v:41033.9-41033.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fast_b_ok[0:0] $2\fast_b_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + switch { \XL_XO [5] \$7 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\fast_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\fast_b_ok[0:0] 1'1 + case + assign $2\fast_b_ok[0:0] 1'0 + end + case + assign $1\fast_b_ok[0:0] 1'0 + end + sync always + update \fast_b_ok $0\fast_b_ok[0:0] end - attribute \src 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$and$libresoc.v:41251$904_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:40723$1495 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $eq $eq$libresoc.v:41248$901 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \wp$1113 - connect \B \wp$1129 - connect \Y $or$issuer_ls180.v:40723$1495_Y + connect \A \internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:41248$901_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:40724$1496 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $eq $eq$libresoc.v:41250$903 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \wp$1095 - connect \B \$1182 - connect \Y $or$issuer_ls180.v:40724$1496_Y + connect \A \internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:41250$903_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:40725$1497 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1180 - connect \B \$1184 - connect \Y $or$issuer_ls180.v:40725$1497_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:41252.9-41255.4" + cell \ppick \ppick + connect \i \ppick_i + connect \o \ppick_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:40726$1498 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1178 - connect \B \$1186 - connect \Y $or$issuer_ls180.v:40726$1498_Y + attribute \src "libresoc.v:41107.7-41107.20" + process $proc$libresoc.v:41107$915 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:40788$1560 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \fus_dest3_o - connect \B \fus_dest2_o$119 - connect \Y $or$issuer_ls180.v:40788$1560_Y + attribute \src "libresoc.v:41256.3-41282.6" + process $proc$libresoc.v:41256$905 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:41257.5-41257.29" + switch \initial + attribute \src "libresoc.v:41257.9-41257.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:40789$1561 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \fus_dest2_o$118 - connect \B \$1340 - connect \Y $or$issuer_ls180.v:40789$1561_Y + attribute \src "libresoc.v:41283.3-41293.6" + process $proc$libresoc.v:41283$906 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:41284.5-41284.29" + switch \initial + attribute \src "libresoc.v:41284.9-41284.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:40790$1562 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \fus_dest2_o$121 - connect \B \fus_dest2_o$122 - connect \Y $or$issuer_ls180.v:40790$1562_Y + attribute \src "libresoc.v:41294.3-41304.6" + process $proc$libresoc.v:41294$907 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:41295.5-41295.29" + switch \initial + attribute \src "libresoc.v:41295.9-41295.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:40791$1563 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \fus_dest2_o$120 - connect \B \$1344 - connect \Y $or$issuer_ls180.v:40791$1563_Y + attribute \src "libresoc.v:41305.3-41331.6" + process $proc$libresoc.v:41305$908 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:41306.5-41306.29" + switch \initial + attribute \src "libresoc.v:41306.9-41306.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \BI [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:40792$1564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$1342 - connect \B \$1346 - connect \Y $or$issuer_ls180.v:40792$1564_Y + attribute \src "libresoc.v:41332.3-41342.6" + process $proc$libresoc.v:41332$909 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:41333.5-41333.29" + switch \initial + attribute \src "libresoc.v:41333.9-41333.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:40793$1565 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 16 - connect \A \addr_en$1253 - connect \B \addr_en$1273 - connect \Y $or$issuer_ls180.v:40793$1565_Y + attribute \src "libresoc.v:41343.3-41353.6" + process $proc$libresoc.v:41343$910 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:41344.5-41344.29" + switch \initial + attribute \src "libresoc.v:41344.9-41344.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:40794$1566 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 16 - connect \A \addr_en$1233 - connect \B \$1351 - connect \Y $or$issuer_ls180.v:40794$1566_Y + attribute \src "libresoc.v:41354.3-41364.6" + process $proc$libresoc.v:41354$911 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:41355.5-41355.29" + switch \initial + attribute \src "libresoc.v:41355.9-41355.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:40795$1567 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 16 - connect \A \addr_en$1313 - connect \B \addr_en$1333 - connect \Y $or$issuer_ls180.v:40795$1567_Y + attribute \src "libresoc.v:41365.3-41375.6" + process $proc$libresoc.v:41365$912 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:41366.5-41366.29" + switch \initial + attribute \src "libresoc.v:41366.9-41366.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:40796$1568 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 16 - connect \A \addr_en$1293 - connect \B \$1355 - connect \Y $or$issuer_ls180.v:40796$1568_Y + attribute \src "libresoc.v:41376.3-41391.6" + process $proc$libresoc.v:41376$913 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:41377.5-41377.29" + switch \initial + attribute \src "libresoc.v:41377.9-41377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:40797$1569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 16 - connect \A \$1353 - connect \B \$1357 - connect \Y $or$issuer_ls180.v:40797$1569_Y + attribute \src "libresoc.v:41392.3-41410.6" + process $proc$libresoc.v:41392$914 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:41393.5-41393.29" + switch \initial + attribute \src "libresoc.v:41393.9-41393.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:40819$1591 + connect \$1 $eq$libresoc.v:41248$901_Y + connect \$3 $and$libresoc.v:41249$902_Y + connect \$5 $eq$libresoc.v:41250$903_Y + connect \$7 $and$libresoc.v:41251$904_Y +end +attribute \src "libresoc.v:41415.1-41658.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out + attribute \src "libresoc.v:41572.3-41590.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:41542.3-41560.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:41623.3-41657.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:41561.3-41571.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:41416.7-41416.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:41591.3-41601.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:41602.3-41622.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:41572.3-41590.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:41542.3-41560.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:41623.3-41657.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:41561.3-41571.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:41591.3-41601.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:41602.3-41622.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:41623.3-41657.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:41602.3-41622.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:41623.3-41657.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:41602.3-41622.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:41623.3-41657.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:41535.17-41535.117" + wire $eq$libresoc.v:41535$916_Y + attribute \src "libresoc.v:41536.17-41536.117" + wire $eq$libresoc.v:41536$917_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 8 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 input 10 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 9 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 6 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 7 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 output 4 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 5 \cr_fxm_ok + attribute \src "libresoc.v:41416.7-41416.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + wire width 32 input 11 \insn_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:578" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + cell $eq $eq$libresoc.v:41535$916 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \fus_dest6_o - connect \B \fus_dest3_o$126 - connect \Y $or$issuer_ls180.v:40819$1591_Y + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:41535$916_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:40820$1592 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + cell $eq $eq$libresoc.v:41536$917 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \fus_dest3_o$125 - connect \B \$1415 - connect \Y $or$issuer_ls180.v:40820$1592_Y + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:41536$917_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:40821$1593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \addr_en$1396 - connect \B \addr_en$1412 - connect \Y $or$issuer_ls180.v:40821$1593_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:41537.13-41541.4" + cell \ppick$1 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:40822$1594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \addr_en$1380 - connect \B \$1420 - connect \Y $or$issuer_ls180.v:40822$1594_Y + attribute \src "libresoc.v:41416.7-41416.20" + process $proc$libresoc.v:41416$924 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:40852$1625 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \fus_dest4_o - connect \B \fus_dest5_o - connect \Y $or$issuer_ls180.v:40852$1625_Y + attribute \src "libresoc.v:41542.3-41560.6" + process $proc$libresoc.v:41542$918 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:41543.5-41543.29" + switch \initial + attribute \src "libresoc.v:41543.9-41543.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:40853$1626 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \fus_dest3_o$130 - connect \B \fus_dest3_o$131 - connect \Y $or$issuer_ls180.v:40853$1626_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:40854$1627 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \$1497 - connect \B \$1499 - connect \Y $or$issuer_ls180.v:40854$1627_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:40855$1628 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \addr_en$1446 - connect \B \addr_en$1462 - connect \Y $or$issuer_ls180.v:40855$1628_Y + attribute \src "libresoc.v:41561.3-41571.6" + process $proc$libresoc.v:41561$919 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:41562.5-41562.29" + switch \initial + attribute \src "libresoc.v:41562.9-41562.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:40856$1629 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \addr_en$1478 - connect \B \addr_en$1494 - connect \Y $or$issuer_ls180.v:40856$1629_Y + attribute \src "libresoc.v:41572.3-41590.6" + process $proc$libresoc.v:41572$920 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:41573.5-41573.29" + switch \initial + attribute \src "libresoc.v:41573.9-41573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:40857$1630 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$1503 - connect \B \$1505 - connect \Y $or$issuer_ls180.v:40857$1630_Y + attribute \src "libresoc.v:41591.3-41601.6" + process $proc$libresoc.v:41591$921 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:41592.5-41592.29" + switch \initial + attribute \src "libresoc.v:41592.9-41592.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:40886$1659 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_dest5_o$135 - connect \B \fus_dest4_o$136 - connect \Y $or$issuer_ls180.v:40886$1659_Y + attribute \src "libresoc.v:41602.3-41622.6" + process $proc$libresoc.v:41602$922 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:41603.5-41603.29" + switch \initial + attribute \src "libresoc.v:41603.9-41603.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:40887$1660 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_dest4_o$137 - connect \B \fus_dest4_o$138 - connect \Y $or$issuer_ls180.v:40887$1660_Y + attribute \src "libresoc.v:41623.3-41657.6" + process $proc$libresoc.v:41623$923 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:41624.5-41624.29" + switch \initial + attribute \src "libresoc.v:41624.9-41624.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:40888$1661 + connect \$1 $eq$libresoc.v:41535$916_Y + connect \$3 $eq$libresoc.v:41536$917_Y +end +attribute \src "libresoc.v:41662.1-42139.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_o" +attribute \generator "nMigen" +module \dec_o + attribute \src "libresoc.v:42100.3-42138.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:42100.3-42138.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:41663.7-41663.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:42026.3-42040.6" + wire width 5 $0\reg_o[4:0] + attribute \src "libresoc.v:42041.3-42055.6" + wire $0\reg_o_ok[0:0] + attribute \src "libresoc.v:42056.3-42066.6" + wire width 10 $0\spr[9:0] + attribute \src "libresoc.v:42083.3-42099.6" + wire width 10 $0\spr_o[9:0] + attribute \src "libresoc.v:42083.3-42099.6" + wire $0\spr_o_ok[0:0] + attribute \src "libresoc.v:42067.3-42082.6" + wire width 10 $0\sprmap_spr_i[9:0] + attribute \src "libresoc.v:42100.3-42138.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:42100.3-42138.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:42026.3-42040.6" + wire width 5 $1\reg_o[4:0] + attribute \src "libresoc.v:42041.3-42055.6" + wire $1\reg_o_ok[0:0] + attribute \src "libresoc.v:42056.3-42066.6" + wire width 10 $1\spr[9:0] + attribute \src "libresoc.v:42083.3-42099.6" + wire width 10 $1\spr_o[9:0] + attribute \src "libresoc.v:42083.3-42099.6" + wire $1\spr_o_ok[0:0] + attribute \src "libresoc.v:42067.3-42082.6" + wire width 10 $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:42100.3-42138.6" + wire width 3 $2\fast_o[2:0] + attribute \src "libresoc.v:42100.3-42138.6" + wire $2\fast_o_ok[0:0] + attribute \src "libresoc.v:42083.3-42099.6" + wire width 10 $2\spr_o[9:0] + attribute \src "libresoc.v:42083.3-42099.6" + wire $2\spr_o_ok[0:0] + attribute \src "libresoc.v:42067.3-42082.6" + wire width 10 $2\sprmap_spr_i[9:0] + attribute \src "libresoc.v:42100.3-42138.6" + wire width 3 $3\fast_o[2:0] + attribute \src "libresoc.v:42100.3-42138.6" + wire $3\fast_o_ok[0:0] + attribute \src "libresoc.v:42100.3-42138.6" + wire width 3 $4\fast_o[2:0] + attribute \src "libresoc.v:42100.3-42138.6" + wire $4\fast_o_ok[0:0] + attribute \src "libresoc.v:42015.17-42015.117" + wire $eq$libresoc.v:42015$925_Y + attribute \src "libresoc.v:42016.17-42016.117" + wire $eq$libresoc.v:42016$926_Y + attribute \src "libresoc.v:42017.17-42017.117" + wire $eq$libresoc.v:42017$927_Y + attribute \src "libresoc.v:42018.17-42018.104" + wire $not$libresoc.v:42018$928_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 10 \BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 9 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 8 \RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 input 11 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 6 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 7 \fast_o_ok + attribute \src "libresoc.v:41663.7-41663.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute 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"PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \sprmap_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \sprmap_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + cell $eq $eq$libresoc.v:42015$925 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \$1582 - connect \B \$1584 - connect \Y $or$issuer_ls180.v:40888$1661_Y + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:42015$925_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:40890$1664 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + cell $eq $eq$libresoc.v:42016$926 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \addr_en$1530 - connect \B \addr_en$1546 - connect \Y $or$issuer_ls180.v:40890$1664_Y + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:42016$926_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:40891$1665 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + cell $eq $eq$libresoc.v:42017$927 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \addr_en$1562 - connect \B \addr_en$1578 - connect \Y $or$issuer_ls180.v:40891$1665_Y + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:42017$927_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:40892$1666 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + cell $not $not$libresoc.v:42018$928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1590 - connect \B \$1592 - connect \Y $or$issuer_ls180.v:40892$1666_Y + connect \A \BO [2] + connect \Y $not$libresoc.v:42018$928_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:40933$1708 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \fus_dest1_o$144 - connect \B \fus_dest2_o$145 - connect \Y $or$issuer_ls180.v:40933$1708_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:42019.14-42025.4" + cell \sprmap$2 \sprmap + connect \fast_o \sprmap_fast_o + connect \fast_o_ok \sprmap_fast_o_ok + connect \spr_i \sprmap_spr_i + connect \spr_o \sprmap_spr_o + connect \spr_o_ok \sprmap_spr_o_ok end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:40934$1709 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \fus_dest2_o$147 - connect \B \fus_dest3_o$148 - connect \Y $or$issuer_ls180.v:40934$1709_Y + attribute \src "libresoc.v:41663.7-41663.20" + process $proc$libresoc.v:41663$935 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:40935$1710 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \fus_dest3_o$146 - connect \B \$1692 - connect \Y $or$issuer_ls180.v:40935$1710_Y + attribute \src "libresoc.v:42026.3-42040.6" + process $proc$libresoc.v:42026$929 + assign { } { } + assign { } { } + assign $0\reg_o[4:0] $1\reg_o[4:0] + attribute \src "libresoc.v:42027.5-42027.29" + switch \initial + attribute \src "libresoc.v:42027.9-42027.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_o[4:0] \RT + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_o[4:0] \RA + case + assign $1\reg_o[4:0] 5'00000 + end + sync always + update \reg_o $0\reg_o[4:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:40936$1711 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \$1690 - connect \B \$1694 - connect \Y $or$issuer_ls180.v:40936$1711_Y + attribute \src "libresoc.v:42041.3-42055.6" + process $proc$libresoc.v:42041$930 + assign { } { } + assign { } { } + assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] + attribute \src "libresoc.v:42042.5-42042.29" + switch \initial + attribute \src "libresoc.v:42042.9-42042.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_o_ok[0:0] 1'1 + case + assign $1\reg_o_ok[0:0] 1'0 + end + sync always + update \reg_o_ok $0\reg_o_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:40937$1712 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \addr_en$1623 - connect \B \addr_en$1639 - connect \Y $or$issuer_ls180.v:40937$1712_Y + attribute \src "libresoc.v:42056.3-42066.6" + process $proc$libresoc.v:42056$931 + assign { } { } + assign { } { } + assign $0\spr[9:0] $1\spr[9:0] + attribute \src "libresoc.v:42057.5-42057.29" + switch \initial + attribute \src "libresoc.v:42057.9-42057.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } + case + assign $1\spr[9:0] 10'0000000000 + end + sync always + update \spr $0\spr[9:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:40939$1714 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \addr_en$1671 - connect \B \addr_en$1687 - connect \Y $or$issuer_ls180.v:40939$1714_Y + attribute \src "libresoc.v:42067.3-42082.6" + process $proc$libresoc.v:42067$932 + assign { } { } + assign { } { } + assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:42068.5-42068.29" + switch \initial + attribute \src "libresoc.v:42068.9-42068.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\sprmap_spr_i[9:0] $2\sprmap_spr_i[9:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sprmap_spr_i[9:0] \spr + case + assign $2\sprmap_spr_i[9:0] 10'0000000000 + end + case + assign $1\sprmap_spr_i[9:0] 10'0000000000 + end + sync always + update \sprmap_spr_i $0\sprmap_spr_i[9:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:40940$1715 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \addr_en$1655 - connect \B \$1700 - connect \Y $or$issuer_ls180.v:40940$1715_Y + attribute \src "libresoc.v:42083.3-42099.6" + process $proc$libresoc.v:42083$933 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\spr_o[9:0] $1\spr_o[9:0] + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:42084.5-42084.29" + switch \initial + attribute \src "libresoc.v:42084.9-42084.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign { } { } + assign $1\spr_o[9:0] $2\spr_o[9:0] + assign $1\spr_o_ok[0:0] $2\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\spr_o_ok[0:0] $2\spr_o[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } + case + assign $2\spr_o[9:0] 10'0000000000 + assign $2\spr_o_ok[0:0] 1'0 + end + case + assign $1\spr_o[9:0] 10'0000000000 + assign $1\spr_o_ok[0:0] 1'0 + end + sync always + update \spr_o $0\spr_o[9:0] + update \spr_o_ok $0\spr_o_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:40941$1716 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$1698 - connect \B \$1702 - connect \Y $or$issuer_ls180.v:40941$1716_Y + attribute \src "libresoc.v:42100.3-42138.6" + process $proc$libresoc.v:42100$934 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $3\fast_o[2:0] + assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0] + attribute \src "libresoc.v:42101.5-42101.29" + switch \initial + attribute \src "libresoc.v:42101.9-42101.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign { } { } + assign $1\fast_o[2:0] $2\fast_o[2:0] + assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\fast_o_ok[0:0] $2\fast_o[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } + case + assign $2\fast_o[2:0] 3'000 + assign $2\fast_o_ok[0:0] 1'0 + end + case + assign $1\fast_o[2:0] 3'000 + assign $1\fast_o_ok[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:337" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 , 7'0001000 + assign { } { } + assign { } { } + assign $3\fast_o[2:0] $4\fast_o[2:0] + assign $3\fast_o_ok[0:0] $4\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $4\fast_o[2:0] 3'000 + assign $4\fast_o_ok[0:0] 1'1 + case + assign $4\fast_o[2:0] $1\fast_o[2:0] + assign $4\fast_o_ok[0:0] $1\fast_o_ok[0:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign { } { } + assign $3\fast_o[2:0] 3'011 + assign $3\fast_o_ok[0:0] 1'1 + case + assign $3\fast_o[2:0] $1\fast_o[2:0] + assign $3\fast_o_ok[0:0] $1\fast_o_ok[0:0] + end + sync always + update \fast_o $0\fast_o[2:0] + update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:40942$1717 + connect \$1 $eq$libresoc.v:42015$925_Y + connect \$3 $eq$libresoc.v:42016$926_Y + connect \$5 $eq$libresoc.v:42017$927_Y + connect \$7 $not$libresoc.v:42018$928_Y +end +attribute \src "libresoc.v:42143.1-42304.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_o2" +attribute \generator "nMigen" +module \dec_o2 + attribute \src "libresoc.v:42264.3-42283.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:42284.3-42303.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:42144.7-42144.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:42250.3-42263.6" + wire width 5 $0\reg_o[4:0] + attribute \src "libresoc.v:42250.3-42263.6" + wire $0\reg_o_ok[0:0] + attribute \src "libresoc.v:42264.3-42283.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:42284.3-42303.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:42250.3-42263.6" + wire width 5 $1\reg_o[4:0] + attribute \src "libresoc.v:42250.3-42263.6" + wire $1\reg_o_ok[0:0] + attribute \src "libresoc.v:42264.3-42283.6" + wire width 3 $2\fast_o[2:0] + attribute \src "libresoc.v:42284.3-42303.6" + wire $2\fast_o_ok[0:0] + attribute \src "libresoc.v:42248.17-42248.108" + wire $eq$libresoc.v:42248$936_Y + attribute \src "libresoc.v:42249.17-42249.100" + wire width 6 $extend$libresoc.v:42249$937_Y + attribute \src "libresoc.v:42249.17-42249.100" + wire width 6 $pos$libresoc.v:42249$938_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 4 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 5 \fast_o_ok + attribute \src "libresoc.v:42144.7-42144.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 8 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363" + wire input 1 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 2 \reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \reg_o_ok + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 input 6 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" + cell $eq $eq$libresoc.v:42248$936 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \wp$1620 - connect \B \wp$1636 - connect \Y $or$issuer_ls180.v:40942$1717_Y + connect \A \upd + connect \B 2'01 + connect \Y $eq$libresoc.v:42248$936_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:40943$1718 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$libresoc.v:42249$937 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wp$1668 - connect \B \wp$1684 - connect \Y $or$issuer_ls180.v:40943$1718_Y + parameter \A_WIDTH 5 + parameter \Y_WIDTH 6 + connect \A \RA + connect \Y $extend$libresoc.v:42249$937_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:40945$1720 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$libresoc.v:42249$938 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wp$1652 - connect \B \$1708 - connect \Y $or$issuer_ls180.v:40945$1720_Y + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A $extend$libresoc.v:42249$937_Y + connect \Y $pos$libresoc.v:42249$938_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:40946$1721 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1706 - connect \B \$1710 - connect \Y $or$issuer_ls180.v:40946$1721_Y + attribute \src "libresoc.v:42144.7-42144.20" + process $proc$libresoc.v:42144$942 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:40963$1738 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \fus_dest3_o$150 - connect \B \fus_dest4_o$151 - connect \Y $or$issuer_ls180.v:40963$1738_Y + attribute \src "libresoc.v:42250.3-42263.6" + process $proc$libresoc.v:42250$939 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg_o[4:0] $1\reg_o[4:0] + assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] + attribute \src "libresoc.v:42251.5-42251.29" + switch \initial + attribute \src "libresoc.v:42251.9-42251.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\reg_o[4:0] \$3 [4:0] + assign $1\reg_o_ok[0:0] 1'1 + case + assign $1\reg_o[4:0] 5'00000 + assign $1\reg_o_ok[0:0] 1'0 + end + sync always + update \reg_o $0\reg_o[4:0] + update \reg_o_ok $0\reg_o_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:40964$1739 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \addr_en$1731 - connect \B \addr_en$1747 - connect \Y $or$issuer_ls180.v:40964$1739_Y + attribute \src "libresoc.v:42264.3-42283.6" + process $proc$libresoc.v:42264$940 + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "libresoc.v:42265.5-42265.29" + switch \initial + attribute \src "libresoc.v:42265.9-42265.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:381" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 , 7'0000110 , 7'0001000 + assign { } { } + assign $1\fast_o[2:0] $2\fast_o[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:385" + switch \lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast_o[2:0] 3'001 + case + assign $2\fast_o[2:0] 3'000 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\fast_o[2:0] 3'100 + case + assign $1\fast_o[2:0] 3'000 + end + sync always + update \fast_o $0\fast_o[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$issuer_ls180.v:40999$1776 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$208 - connect \B \$212 - connect \Y $or$issuer_ls180.v:40999$1776_Y + attribute \src "libresoc.v:42284.3-42303.6" + process $proc$libresoc.v:42284$941 + assign { } { } + assign { } { } + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "libresoc.v:42285.5-42285.29" + switch \initial + attribute \src "libresoc.v:42285.9-42285.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:381" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 , 7'0000110 , 7'0001000 + assign { } { } + assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:385" + switch \lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast_o_ok[0:0] 1'1 + case + assign $2\fast_o_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + case + assign $1\fast_o_ok[0:0] 1'0 + end + sync always + update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$issuer_ls180.v:41001$1778 - parameter \A_SIGNED 0 + connect \$1 $eq$libresoc.v:42248$936_Y + connect \$3 $pos$libresoc.v:42249$938_Y +end +attribute \src "libresoc.v:42308.1-42442.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_oe" +attribute \generator "nMigen" +module \dec_oe + attribute \src "libresoc.v:42309.7-42309.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:42400.3-42420.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:42421.3-42441.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:42400.3-42420.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:42421.3-42441.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:42400.3-42420.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:42421.3-42441.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 4 \OE + attribute \src "libresoc.v:42309.7-42309.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 1 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:42309.7-42309.20" + process $proc$libresoc.v:42309$945 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:42400.3-42420.6" + process $proc$libresoc.v:42400$943 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:42401.5-42401.29" + switch \initial + attribute \src "libresoc.v:42401.9-42401.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:42421.3-42441.6" + process $proc$libresoc.v:42421$944 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:42422.5-42422.29" + switch \initial + attribute \src "libresoc.v:42422.9-42422.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:42446.1-42500.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_rc" +attribute \generator "nMigen" +module \dec_rc + attribute \src "libresoc.v:42447.7-42447.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:42462.3-42480.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:42481.3-42499.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:42462.3-42480.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:42481.3-42499.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 3 \Rc + attribute \src "libresoc.v:42447.7-42447.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:42447.7-42447.20" + process $proc$libresoc.v:42447$948 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:42462.3-42480.6" + process $proc$libresoc.v:42462$946 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:42463.5-42463.29" + switch \initial + attribute \src "libresoc.v:42463.9-42463.17" + case 1'1 + case + end + attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$41 + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27" + wire \f_stall_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" + wire input 3 \f_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 8 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 13 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 \ibus__adr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 7 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire \ibus__cyc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 12 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 9 \ibus__err + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + cell $and $and$libresoc.v:42640$971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$262 - connect \B \$266 - connect \Y $or$issuer_ls180.v:41026$1803_Y + connect \A \ibus__cyc + connect \B \ibus__err + connect \Y $and$libresoc.v:42640$971_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $not $not$libresoc.v:42619$950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:42619$950_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $not $not$libresoc.v:42622$953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:42622$953_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $not $not$libresoc.v:42623$954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:42623$954_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $not $not$libresoc.v:42625$956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:42625$956_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $not $not$libresoc.v:42628$959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:42628$959_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $not $not$libresoc.v:42630$961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:42630$961_Y + end + attribute \src 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$not$libresoc.v:42641$972_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $not $not$libresoc.v:42643$974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:42643$974_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$issuer_ls180.v:41030$1807 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$libresoc.v:42618$949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$270 - connect \B \$274 - connect \Y $or$issuer_ls180.v:41030$1807_Y + connect \A \$5 + connect \B \$7 + connect \Y $or$libresoc.v:42618$949_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$issuer_ls180.v:41035$1812 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$libresoc.v:42621$952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$280 - connect \B \$284 - connect \Y $or$issuer_ls180.v:41035$1812_Y + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:42621$952_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$issuer_ls180.v:41037$1814 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$libresoc.v:42624$955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$286 - connect \B \$288 - connect \Y $or$issuer_ls180.v:41037$1814_Y + connect \A \$15 + connect \B \$17 + connect \Y $or$libresoc.v:42624$955_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$issuer_ls180.v:41042$1819 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$libresoc.v:42627$958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$294 - connect \B \$298 - connect \Y $or$issuer_ls180.v:41042$1819_Y + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:42627$958_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$issuer_ls180.v:41044$1821 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$libresoc.v:42629$960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$300 - connect \B \$302 - connect \Y $or$issuer_ls180.v:41044$1821_Y + connect \A \$25 + connect \B \$27 + connect \Y $or$libresoc.v:42629$960_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$issuer_ls180.v:41049$1826 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$libresoc.v:42632$963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$308 - connect \B \$312 - connect \Y $or$issuer_ls180.v:41049$1826_Y + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:42632$963_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$issuer_ls180.v:41051$1828 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$libresoc.v:42635$966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$314 - connect \B \$316 - connect \Y $or$issuer_ls180.v:41051$1828_Y + connect \A \$35 + connect \B \$37 + connect \Y $or$libresoc.v:42635$966_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$issuer_ls180.v:41055$1832 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$libresoc.v:42642$973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$320 - connect \B \$324 - connect \Y $or$issuer_ls180.v:41055$1832_Y + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:42642$973_Y + end + attribute \src "libresoc.v:42505.7-42505.20" + process $proc$libresoc.v:42505$1016 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:42569.14-42569.44" + process $proc$libresoc.v:42569$1017 + assign { } { } + assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \f_badaddr_o $1\f_badaddr_o[44:0] + end + attribute \src "libresoc.v:42576.7-42576.27" + process $proc$libresoc.v:42576$1018 + assign { } { } + assign $1\f_fetch_err_o[0:0] 1'0 + sync always + sync init + update \f_fetch_err_o $1\f_fetch_err_o[0:0] + end + attribute \src "libresoc.v:42590.14-42590.42" + process $proc$libresoc.v:42590$1019 + assign { } { } + assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \ibus__adr $1\ibus__adr[44:0] + end + attribute \src "libresoc.v:42595.7-42595.23" + process $proc$libresoc.v:42595$1020 + assign { } { } + assign $1\ibus__cyc[0:0] 1'0 + sync always + sync init + update \ibus__cyc $1\ibus__cyc[0:0] + end + attribute \src "libresoc.v:42604.13-42604.30" + process $proc$libresoc.v:42604$1021 + assign { } { } + assign $1\ibus__sel[7:0] 8'00000000 + sync always + sync init + update \ibus__sel $1\ibus__sel[7:0] + end + attribute \src "libresoc.v:42609.7-42609.23" + process $proc$libresoc.v:42609$1022 + assign { } { } + assign $1\ibus__stb[0:0] 1'0 + sync always + sync init + update \ibus__stb $1\ibus__stb[0:0] + end + attribute \src "libresoc.v:42613.14-42613.47" + process $proc$libresoc.v:42613$1023 + assign { } { } + assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ibus_rdata $1\ibus_rdata[63:0] + end + attribute \src "libresoc.v:42644.3-42645.39" + process $proc$libresoc.v:42644$975 + assign { } { } + assign $0\f_badaddr_o[44:0] \f_badaddr_o$next + sync posedge \clk + update \f_badaddr_o $0\f_badaddr_o[44:0] + end + attribute \src "libresoc.v:42646.3-42647.43" + process $proc$libresoc.v:42646$976 + assign { } { } + assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next + sync posedge \clk + update \f_fetch_err_o $0\f_fetch_err_o[0:0] + end + attribute \src "libresoc.v:42648.3-42649.35" + process $proc$libresoc.v:42648$977 + assign { } { } + assign $0\ibus__adr[44:0] \ibus__adr$next + sync posedge \clk + update \ibus__adr $0\ibus__adr[44:0] + end + attribute \src "libresoc.v:42650.3-42651.37" + process $proc$libresoc.v:42650$978 + assign { } { } + assign $0\ibus_rdata[63:0] \ibus_rdata$next + sync posedge \clk + update \ibus_rdata $0\ibus_rdata[63:0] + end + attribute \src "libresoc.v:42652.3-42653.35" + process $proc$libresoc.v:42652$979 + assign { } { } + assign $0\ibus__sel[7:0] \ibus__sel$next + sync posedge \clk + update \ibus__sel $0\ibus__sel[7:0] + end + attribute \src "libresoc.v:42654.3-42655.35" + process $proc$libresoc.v:42654$980 + assign { } { } + assign $0\ibus__stb[0:0] \ibus__stb$next + sync posedge \clk + update \ibus__stb $0\ibus__stb[0:0] + end + attribute \src "libresoc.v:42656.3-42657.35" + process $proc$libresoc.v:42656$981 + assign { } { } + assign $0\ibus__cyc[0:0] \ibus__cyc$next + sync posedge \clk + update \ibus__cyc $0\ibus__cyc[0:0] + end + attribute \src "libresoc.v:42658.3-42680.6" + process $proc$libresoc.v:42658$982 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__cyc$next[0:0]$983 $3\ibus__cyc$next[0:0]$986 + attribute \src "libresoc.v:42659.5-42659.29" + switch \initial + attribute \src "libresoc.v:42659.9-42659.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { \$3 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ibus__cyc$next[0:0]$984 $2\ibus__cyc$next[0:0]$985 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ibus__cyc$next[0:0]$985 1'0 + case + assign $2\ibus__cyc$next[0:0]$985 \ibus__cyc + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ibus__cyc$next[0:0]$984 1'1 + case + assign $1\ibus__cyc$next[0:0]$984 \ibus__cyc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__cyc$next[0:0]$986 1'0 + case + assign $3\ibus__cyc$next[0:0]$986 $1\ibus__cyc$next[0:0]$984 + end + sync always + update \ibus__cyc$next $0\ibus__cyc$next[0:0]$983 + end + attribute \src "libresoc.v:42681.3-42703.6" + process $proc$libresoc.v:42681$987 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__stb$next[0:0]$988 $3\ibus__stb$next[0:0]$991 + attribute \src "libresoc.v:42682.5-42682.29" + switch \initial + attribute \src "libresoc.v:42682.9-42682.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { \$13 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ibus__stb$next[0:0]$989 $2\ibus__stb$next[0:0]$990 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ibus__stb$next[0:0]$990 1'0 + case + assign $2\ibus__stb$next[0:0]$990 \ibus__stb + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ibus__stb$next[0:0]$989 1'1 + case + assign $1\ibus__stb$next[0:0]$989 \ibus__stb + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__stb$next[0:0]$991 1'0 + case + assign $3\ibus__stb$next[0:0]$991 $1\ibus__stb$next[0:0]$989 + end + sync always + update \ibus__stb$next $0\ibus__stb$next[0:0]$988 + end + attribute \src "libresoc.v:42704.3-42726.6" + process $proc$libresoc.v:42704$992 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__sel$next[7:0]$993 $3\ibus__sel$next[7:0]$996 + attribute \src "libresoc.v:42705.5-42705.29" + switch \initial + attribute \src "libresoc.v:42705.9-42705.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { \$23 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ibus__sel$next[7:0]$994 $2\ibus__sel$next[7:0]$995 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ibus__sel$next[7:0]$995 8'00000000 + case + assign $2\ibus__sel$next[7:0]$995 \ibus__sel + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ibus__sel$next[7:0]$994 8'11111111 + case + assign $1\ibus__sel$next[7:0]$994 \ibus__sel + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__sel$next[7:0]$996 8'00000000 + case + assign $3\ibus__sel$next[7:0]$996 $1\ibus__sel$next[7:0]$994 + end + sync always + update \ibus__sel$next $0\ibus__sel$next[7:0]$993 + end + attribute \src "libresoc.v:42727.3-42746.6" + process $proc$libresoc.v:42727$997 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus_rdata$next[63:0]$998 $3\ibus_rdata$next[63:0]$1001 + attribute \src "libresoc.v:42728.5-42728.29" + switch \initial + attribute \src "libresoc.v:42728.9-42728.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { \$33 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ibus_rdata$next[63:0]$999 $2\ibus_rdata$next[63:0]$1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + switch \$39 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ibus_rdata$next[63:0]$1000 \ibus__dat_r + case + assign $2\ibus_rdata$next[63:0]$1000 \ibus_rdata + end + case + assign $1\ibus_rdata$next[63:0]$999 \ibus_rdata + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus_rdata$next[63:0]$1001 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\ibus_rdata$next[63:0]$1001 $1\ibus_rdata$next[63:0]$999 + end + sync always + update \ibus_rdata$next $0\ibus_rdata$next[63:0]$998 + end + attribute \src "libresoc.v:42747.3-42764.6" + process $proc$libresoc.v:42747$1002 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__adr$next[44:0]$1003 $2\ibus__adr$next[44:0]$1005 + attribute \src "libresoc.v:42748.5-42748.29" + switch \initial + attribute \src "libresoc.v:42748.9-42748.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { \$43 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $1\ibus__adr$next[44:0]$1004 \ibus__adr + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ibus__adr$next[44:0]$1004 \a_pc_i [47:3] + case + assign $1\ibus__adr$next[44:0]$1004 \ibus__adr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ibus__adr$next[44:0]$1005 45'000000000000000000000000000000000000000000000 + case + assign $2\ibus__adr$next[44:0]$1005 $1\ibus__adr$next[44:0]$1004 + end + sync always + update \ibus__adr$next $0\ibus__adr$next[44:0]$1003 + end + attribute \src "libresoc.v:42765.3-42782.6" + process $proc$libresoc.v:42765$1006 + assign { } { } + assign { } { } + assign { } { } + assign $0\f_fetch_err_o$next[0:0]$1007 $2\f_fetch_err_o$next[0:0]$1009 + attribute \src "libresoc.v:42766.5-42766.29" + switch \initial + attribute \src "libresoc.v:42766.9-42766.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + switch { \$47 \$45 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\f_fetch_err_o$next[0:0]$1008 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\f_fetch_err_o$next[0:0]$1008 1'0 + case + assign $1\f_fetch_err_o$next[0:0]$1008 \f_fetch_err_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\f_fetch_err_o$next[0:0]$1009 1'0 + case + assign $2\f_fetch_err_o$next[0:0]$1009 $1\f_fetch_err_o$next[0:0]$1008 + end + sync always + update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$1007 + end + attribute \src "libresoc.v:42783.3-42797.6" + process $proc$libresoc.v:42783$1010 + assign { } { } + assign { } { } + assign { } { } + assign $0\f_badaddr_o$next[44:0]$1011 $2\f_badaddr_o$next[44:0]$1013 + attribute \src "libresoc.v:42784.5-42784.29" + switch \initial + attribute \src "libresoc.v:42784.9-42784.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + switch { \$51 \$49 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\f_badaddr_o$next[44:0]$1012 \ibus__adr + case + assign $1\f_badaddr_o$next[44:0]$1012 \f_badaddr_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\f_badaddr_o$next[44:0]$1013 45'000000000000000000000000000000000000000000000 + case + assign $2\f_badaddr_o$next[44:0]$1013 $1\f_badaddr_o$next[44:0]$1012 + end + sync always + update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$1011 + end + attribute \src "libresoc.v:42798.3-42809.6" + process $proc$libresoc.v:42798$1014 + assign { } { } + assign $0\f_busy_o[0:0] $1\f_busy_o[0:0] + attribute \src "libresoc.v:42799.5-42799.29" + switch \initial + attribute \src "libresoc.v:42799.9-42799.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + switch \f_fetch_err_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\f_busy_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\f_busy_o[0:0] \ibus__cyc + end + sync always + update \f_busy_o $0\f_busy_o[0:0] + end + attribute \src "libresoc.v:42810.3-42822.6" + process $proc$libresoc.v:42810$1015 + assign { } { } + assign { } { } + assign $0\f_instr_o[63:0] $1\f_instr_o[63:0] + attribute \src "libresoc.v:42811.5-42811.29" + switch \initial + attribute \src "libresoc.v:42811.9-42811.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + switch \f_fetch_err_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\f_instr_o[63:0] \ibus_rdata + end + sync always + update \f_instr_o $0\f_instr_o[63:0] + end + connect \$9 $or$libresoc.v:42618$949_Y + connect \$11 $not$libresoc.v:42619$950_Y + connect \$13 $and$libresoc.v:42620$951_Y + connect \$15 $or$libresoc.v:42621$952_Y + connect \$17 $not$libresoc.v:42622$953_Y + connect \$1 $not$libresoc.v:42623$954_Y + connect \$19 $or$libresoc.v:42624$955_Y + connect \$21 $not$libresoc.v:42625$956_Y + connect \$23 $and$libresoc.v:42626$957_Y + connect \$25 $or$libresoc.v:42627$958_Y + connect \$27 $not$libresoc.v:42628$959_Y + connect \$29 $or$libresoc.v:42629$960_Y + connect \$31 $not$libresoc.v:42630$961_Y + connect \$33 $and$libresoc.v:42631$962_Y + connect \$35 $or$libresoc.v:42632$963_Y + connect \$37 $not$libresoc.v:42633$964_Y + connect \$3 $and$libresoc.v:42634$965_Y + connect \$39 $or$libresoc.v:42635$966_Y + connect \$41 $not$libresoc.v:42636$967_Y + connect \$43 $and$libresoc.v:42637$968_Y + connect \$45 $and$libresoc.v:42638$969_Y + connect \$47 $not$libresoc.v:42639$970_Y + connect \$49 $and$libresoc.v:42640$971_Y + connect \$51 $not$libresoc.v:42641$972_Y + connect \$5 $or$libresoc.v:42642$973_Y + connect \$7 $not$libresoc.v:42643$974_Y + connect \a_stall_i 1'0 + connect \f_stall_i 1'0 + connect \a_busy_o \ibus__cyc +end +attribute \src "libresoc.v:42830.1-44581.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.jtag" +attribute \generator "nMigen" +module \jtag + attribute \src "libresoc.v:43857.3-43880.6" + wire $0\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:44218.3-44233.6" + wire $0\TAP_tdo[0:0] + attribute \src "libresoc.v:44015.3-44047.6" + wire width 4 $0\dmi0_addr_i$next[3:0]$1235 + attribute \src "libresoc.v:43721.3-43722.39" + wire width 4 $0\dmi0_addr_i[3:0] + attribute \src "libresoc.v:44441.3-44457.6" + wire $0\dmi0_addrsr__oe$next[0:0]$1318 + attribute \src "libresoc.v:43741.3-43742.47" + wire $0\dmi0_addrsr__oe[0:0] + attribute \src "libresoc.v:44458.3-44478.6" + wire width 8 $0\dmi0_addrsr_reg$next[7:0]$1322 + attribute \src "libresoc.v:43739.3-43740.47" + wire width 8 $0\dmi0_addrsr_reg[7:0] + attribute \src "libresoc.v:44423.3-44431.6" + wire $0\dmi0_addrsr_update_core$next[0:0]$1312 + attribute \src "libresoc.v:43745.3-43746.63" + wire $0\dmi0_addrsr_update_core[0:0] + attribute \src "libresoc.v:44432.3-44440.6" + wire $0\dmi0_addrsr_update_core_prev$next[0:0]$1315 + attribute \src "libresoc.v:43743.3-43744.73" + wire $0\dmi0_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:44128.3-44148.6" + wire width 64 $0\dmi0_datasr__i$next[63:0]$1253 + attribute \src "libresoc.v:43715.3-43716.45" + wire width 64 $0\dmi0_datasr__i[63:0] + attribute \src "libresoc.v:43819.3-43835.6" + wire width 2 $0\dmi0_datasr__oe$next[1:0]$1202 + attribute \src "libresoc.v:43733.3-43734.47" + wire width 2 $0\dmi0_datasr__oe[1:0] + attribute \src "libresoc.v:43836.3-43856.6" + wire width 64 $0\dmi0_datasr_reg$next[63:0]$1206 + attribute \src "libresoc.v:43731.3-43732.47" + wire width 64 $0\dmi0_datasr_reg[63:0] + attribute \src "libresoc.v:44479.3-44487.6" + wire $0\dmi0_datasr_update_core$next[0:0]$1327 + attribute \src "libresoc.v:43737.3-43738.63" + wire $0\dmi0_datasr_update_core[0:0] + attribute \src "libresoc.v:43810.3-43818.6" + wire $0\dmi0_datasr_update_core_prev$next[0:0]$1199 + attribute \src "libresoc.v:43735.3-43736.73" + wire $0\dmi0_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:44101.3-44127.6" + wire width 64 $0\dmi0_din$next[63:0]$1248 + attribute \src "libresoc.v:43717.3-43718.33" + wire width 64 $0\dmi0_din[63:0] + attribute \src "libresoc.v:44048.3-44100.6" + wire width 3 $0\fsm_state$275$next[2:0]$1241 + attribute \src "libresoc.v:43719.3-43720.45" + wire width 3 $0\fsm_state$275[2:0]$1170 + attribute \src "libresoc.v:43232.13-43232.35" + wire width 3 $0\fsm_state$275[2:0]$1343 + attribute \src "libresoc.v:43914.3-43966.6" + wire width 3 $0\fsm_state$next[2:0]$1218 + attribute \src "libresoc.v:43727.3-43728.35" + wire width 3 $0\fsm_state[2:0] + attribute \src "libresoc.v:42831.7-42831.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:44234.3-44254.6" + wire width 50 $0\io_bd$next[49:0]$1263 + attribute \src "libresoc.v:43771.3-43772.27" + wire width 50 $0\io_bd[49:0] + attribute \src "libresoc.v:44149.3-44217.6" + wire width 50 $0\io_sr$next[49:0]$1258 + attribute \src "libresoc.v:43773.3-43774.27" + wire width 50 $0\io_sr[49:0] + attribute \src "libresoc.v:43881.3-43913.6" + wire width 29 $0\jtag_wb__adr$next[28:0]$1212 + attribute \src "libresoc.v:43729.3-43730.41" + wire width 29 $0\jtag_wb__adr[28:0] + attribute \src "libresoc.v:43967.3-43993.6" + wire width 64 $0\jtag_wb__dat_w$next[63:0]$1225 + attribute \src "libresoc.v:43725.3-43726.45" + wire width 64 $0\jtag_wb__dat_w[63:0] + attribute \src "libresoc.v:44329.3-44345.6" + wire $0\jtag_wb_addrsr__oe$next[0:0]$1288 + attribute \src "libresoc.v:43757.3-43758.53" + wire $0\jtag_wb_addrsr__oe[0:0] + attribute \src "libresoc.v:44346.3-44366.6" + wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$1292 + attribute \src "libresoc.v:43755.3-43756.53" + wire width 29 $0\jtag_wb_addrsr_reg[28:0] + attribute \src "libresoc.v:44311.3-44319.6" + wire $0\jtag_wb_addrsr_update_core$next[0:0]$1282 + attribute \src "libresoc.v:43761.3-43762.69" + wire $0\jtag_wb_addrsr_update_core[0:0] + attribute \src "libresoc.v:44320.3-44328.6" + wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1285 + attribute \src "libresoc.v:43759.3-43760.79" + wire $0\jtag_wb_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:43994.3-44014.6" + wire width 64 $0\jtag_wb_datasr__i$next[63:0]$1230 + attribute \src "libresoc.v:43723.3-43724.51" + wire width 64 $0\jtag_wb_datasr__i[63:0] + attribute \src "libresoc.v:44385.3-44401.6" + wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$1303 + attribute \src "libresoc.v:43749.3-43750.53" + wire width 2 $0\jtag_wb_datasr__oe[1:0] + attribute \src "libresoc.v:44402.3-44422.6" + wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$1307 + attribute \src "libresoc.v:43747.3-43748.53" + wire width 64 $0\jtag_wb_datasr_reg[63:0] + attribute \src "libresoc.v:44367.3-44375.6" + wire $0\jtag_wb_datasr_update_core$next[0:0]$1297 + attribute \src "libresoc.v:43753.3-43754.69" + wire $0\jtag_wb_datasr_update_core[0:0] + attribute \src "libresoc.v:44376.3-44384.6" + wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$1300 + attribute \src "libresoc.v:43751.3-43752.79" + wire $0\jtag_wb_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:44273.3-44289.6" + wire $0\sr0__oe$next[0:0]$1273 + attribute \src "libresoc.v:43765.3-43766.31" + wire $0\sr0__oe[0:0] + attribute \src "libresoc.v:44290.3-44310.6" + wire width 3 $0\sr0_reg$next[2:0]$1277 + attribute \src "libresoc.v:43763.3-43764.31" + wire width 3 $0\sr0_reg[2:0] + attribute \src "libresoc.v:44255.3-44263.6" + wire $0\sr0_update_core$next[0:0]$1267 + attribute \src "libresoc.v:43769.3-43770.47" + wire $0\sr0_update_core[0:0] + attribute \src "libresoc.v:44264.3-44272.6" + wire $0\sr0_update_core_prev$next[0:0]$1270 + attribute \src "libresoc.v:43767.3-43768.57" + wire $0\sr0_update_core_prev[0:0] + attribute \src "libresoc.v:43857.3-43880.6" + wire $1\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:44218.3-44233.6" + wire $1\TAP_tdo[0:0] + attribute \src "libresoc.v:44015.3-44047.6" + wire width 4 $1\dmi0_addr_i$next[3:0]$1236 + attribute \src "libresoc.v:43157.13-43157.31" + wire width 4 $1\dmi0_addr_i[3:0] + attribute \src "libresoc.v:44441.3-44457.6" + wire $1\dmi0_addrsr__oe$next[0:0]$1319 + attribute \src "libresoc.v:43165.7-43165.29" + wire $1\dmi0_addrsr__oe[0:0] + attribute \src "libresoc.v:44458.3-44478.6" + wire width 8 $1\dmi0_addrsr_reg$next[7:0]$1323 + attribute \src "libresoc.v:43173.13-43173.36" + wire width 8 $1\dmi0_addrsr_reg[7:0] + attribute \src "libresoc.v:44423.3-44431.6" + wire $1\dmi0_addrsr_update_core$next[0:0]$1313 + attribute \src "libresoc.v:43181.7-43181.37" + wire $1\dmi0_addrsr_update_core[0:0] + attribute \src "libresoc.v:44432.3-44440.6" + wire $1\dmi0_addrsr_update_core_prev$next[0:0]$1316 + attribute \src "libresoc.v:43185.7-43185.42" + wire $1\dmi0_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:44128.3-44148.6" + wire width 64 $1\dmi0_datasr__i$next[63:0]$1254 + attribute \src "libresoc.v:43189.14-43189.51" + wire width 64 $1\dmi0_datasr__i[63:0] + attribute \src "libresoc.v:43819.3-43835.6" + wire width 2 $1\dmi0_datasr__oe$next[1:0]$1203 + attribute \src "libresoc.v:43195.13-43195.35" + wire width 2 $1\dmi0_datasr__oe[1:0] + attribute \src "libresoc.v:43836.3-43856.6" + wire width 64 $1\dmi0_datasr_reg$next[63:0]$1207 + attribute \src "libresoc.v:43203.14-43203.52" + wire width 64 $1\dmi0_datasr_reg[63:0] + attribute \src "libresoc.v:44479.3-44487.6" + wire $1\dmi0_datasr_update_core$next[0:0]$1328 + attribute \src "libresoc.v:43211.7-43211.37" + wire $1\dmi0_datasr_update_core[0:0] + attribute \src "libresoc.v:43810.3-43818.6" + wire $1\dmi0_datasr_update_core_prev$next[0:0]$1200 + attribute \src "libresoc.v:43215.7-43215.42" + wire $1\dmi0_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:44101.3-44127.6" + wire width 64 $1\dmi0_din$next[63:0]$1249 + attribute \src "libresoc.v:43220.14-43220.45" + wire width 64 $1\dmi0_din[63:0] + attribute \src "libresoc.v:44048.3-44100.6" + wire width 3 $1\fsm_state$275$next[2:0]$1242 + attribute \src "libresoc.v:43914.3-43966.6" + wire width 3 $1\fsm_state$next[2:0]$1219 + attribute \src "libresoc.v:43230.13-43230.29" + wire width 3 $1\fsm_state[2:0] + attribute \src "libresoc.v:44234.3-44254.6" + wire width 50 $1\io_bd$next[49:0]$1264 + attribute \src "libresoc.v:43430.14-43430.39" + wire width 50 $1\io_bd[49:0] + attribute \src "libresoc.v:44149.3-44217.6" + wire width 50 $1\io_sr$next[49:0]$1259 + attribute \src "libresoc.v:43442.14-43442.39" + wire width 50 $1\io_sr[49:0] + attribute \src "libresoc.v:43881.3-43913.6" + wire width 29 $1\jtag_wb__adr$next[28:0]$1213 + attribute \src "libresoc.v:43451.14-43451.41" + wire width 29 $1\jtag_wb__adr[28:0] + attribute \src "libresoc.v:43967.3-43993.6" + wire width 64 $1\jtag_wb__dat_w$next[63:0]$1226 + attribute \src "libresoc.v:43460.14-43460.51" + wire width 64 $1\jtag_wb__dat_w[63:0] + attribute \src "libresoc.v:44329.3-44345.6" + wire $1\jtag_wb_addrsr__oe$next[0:0]$1289 + attribute \src "libresoc.v:43474.7-43474.32" + wire $1\jtag_wb_addrsr__oe[0:0] + attribute \src "libresoc.v:44346.3-44366.6" + wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$1293 + attribute \src "libresoc.v:43482.14-43482.47" + wire width 29 $1\jtag_wb_addrsr_reg[28:0] + attribute \src "libresoc.v:44311.3-44319.6" + wire $1\jtag_wb_addrsr_update_core$next[0:0]$1283 + attribute \src "libresoc.v:43490.7-43490.40" + wire $1\jtag_wb_addrsr_update_core[0:0] + attribute \src "libresoc.v:44320.3-44328.6" + wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1286 + attribute \src "libresoc.v:43494.7-43494.45" + wire $1\jtag_wb_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:43994.3-44014.6" + wire width 64 $1\jtag_wb_datasr__i$next[63:0]$1231 + attribute \src "libresoc.v:43498.14-43498.54" + wire width 64 $1\jtag_wb_datasr__i[63:0] + attribute \src "libresoc.v:44385.3-44401.6" + wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$1304 + attribute \src "libresoc.v:43504.13-43504.38" + wire width 2 $1\jtag_wb_datasr__oe[1:0] + attribute \src "libresoc.v:44402.3-44422.6" + wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$1308 + attribute \src "libresoc.v:43512.14-43512.55" + wire width 64 $1\jtag_wb_datasr_reg[63:0] + attribute \src "libresoc.v:44367.3-44375.6" + wire $1\jtag_wb_datasr_update_core$next[0:0]$1298 + attribute \src "libresoc.v:43520.7-43520.40" + wire $1\jtag_wb_datasr_update_core[0:0] + attribute \src "libresoc.v:44376.3-44384.6" + wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$1301 + attribute \src "libresoc.v:43524.7-43524.45" + wire $1\jtag_wb_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:44273.3-44289.6" + wire $1\sr0__oe$next[0:0]$1274 + attribute \src "libresoc.v:43542.7-43542.21" + wire $1\sr0__oe[0:0] + attribute \src "libresoc.v:44290.3-44310.6" + wire width 3 $1\sr0_reg$next[2:0]$1278 + attribute \src "libresoc.v:43550.13-43550.27" + wire width 3 $1\sr0_reg[2:0] + attribute \src "libresoc.v:44255.3-44263.6" + wire $1\sr0_update_core$next[0:0]$1268 + attribute \src "libresoc.v:43558.7-43558.29" + wire $1\sr0_update_core[0:0] + attribute \src "libresoc.v:44264.3-44272.6" + wire $1\sr0_update_core_prev$next[0:0]$1271 + attribute \src "libresoc.v:43562.7-43562.34" + wire $1\sr0_update_core_prev[0:0] + attribute \src "libresoc.v:44015.3-44047.6" + wire width 4 $2\dmi0_addr_i$next[3:0]$1237 + attribute \src "libresoc.v:44441.3-44457.6" + wire $2\dmi0_addrsr__oe$next[0:0]$1320 + attribute \src "libresoc.v:44458.3-44478.6" + wire width 8 $2\dmi0_addrsr_reg$next[7:0]$1324 + attribute \src "libresoc.v:44128.3-44148.6" + wire width 64 $2\dmi0_datasr__i$next[63:0]$1255 + attribute \src "libresoc.v:43819.3-43835.6" + wire width 2 $2\dmi0_datasr__oe$next[1:0]$1204 + attribute \src "libresoc.v:43836.3-43856.6" + wire width 64 $2\dmi0_datasr_reg$next[63:0]$1208 + attribute \src "libresoc.v:44101.3-44127.6" + wire width 64 $2\dmi0_din$next[63:0]$1250 + attribute \src "libresoc.v:44048.3-44100.6" + wire width 3 $2\fsm_state$275$next[2:0]$1243 + attribute \src "libresoc.v:43914.3-43966.6" + wire width 3 $2\fsm_state$next[2:0]$1220 + attribute \src "libresoc.v:44234.3-44254.6" + wire width 50 $2\io_bd$next[49:0]$1265 + attribute \src "libresoc.v:44149.3-44217.6" + wire width 50 $2\io_sr$next[49:0]$1260 + attribute \src "libresoc.v:43881.3-43913.6" + wire width 29 $2\jtag_wb__adr$next[28:0]$1214 + attribute \src "libresoc.v:43967.3-43993.6" + wire width 64 $2\jtag_wb__dat_w$next[63:0]$1227 + attribute \src "libresoc.v:44329.3-44345.6" + wire $2\jtag_wb_addrsr__oe$next[0:0]$1290 + attribute \src "libresoc.v:44346.3-44366.6" + wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$1294 + attribute \src "libresoc.v:43994.3-44014.6" + wire width 64 $2\jtag_wb_datasr__i$next[63:0]$1232 + attribute \src "libresoc.v:44385.3-44401.6" + wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$1305 + attribute \src "libresoc.v:44402.3-44422.6" + wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$1309 + attribute \src "libresoc.v:44273.3-44289.6" + wire $2\sr0__oe$next[0:0]$1275 + attribute \src "libresoc.v:44290.3-44310.6" + wire width 3 $2\sr0_reg$next[2:0]$1279 + attribute \src "libresoc.v:44015.3-44047.6" + wire width 4 $3\dmi0_addr_i$next[3:0]$1238 + attribute \src "libresoc.v:44458.3-44478.6" + wire width 8 $3\dmi0_addrsr_reg$next[7:0]$1325 + attribute \src "libresoc.v:44128.3-44148.6" + wire width 64 $3\dmi0_datasr__i$next[63:0]$1256 + attribute \src "libresoc.v:43836.3-43856.6" + wire width 64 $3\dmi0_datasr_reg$next[63:0]$1209 + attribute \src "libresoc.v:44101.3-44127.6" + wire width 64 $3\dmi0_din$next[63:0]$1251 + attribute \src "libresoc.v:44048.3-44100.6" + wire width 3 $3\fsm_state$275$next[2:0]$1244 + attribute \src "libresoc.v:43914.3-43966.6" + wire width 3 $3\fsm_state$next[2:0]$1221 + attribute \src "libresoc.v:43881.3-43913.6" + wire width 29 $3\jtag_wb__adr$next[28:0]$1215 + attribute \src "libresoc.v:43967.3-43993.6" + wire width 64 $3\jtag_wb__dat_w$next[63:0]$1228 + attribute \src "libresoc.v:44346.3-44366.6" + wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$1295 + attribute \src "libresoc.v:43994.3-44014.6" + wire width 64 $3\jtag_wb_datasr__i$next[63:0]$1233 + attribute \src "libresoc.v:44402.3-44422.6" + wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$1310 + attribute \src "libresoc.v:44290.3-44310.6" + wire width 3 $3\sr0_reg$next[2:0]$1280 + attribute \src "libresoc.v:44015.3-44047.6" + wire width 4 $4\dmi0_addr_i$next[3:0]$1239 + attribute \src "libresoc.v:44048.3-44100.6" + wire width 3 $4\fsm_state$275$next[2:0]$1245 + attribute \src "libresoc.v:43914.3-43966.6" + wire width 3 $4\fsm_state$next[2:0]$1222 + attribute \src "libresoc.v:43881.3-43913.6" + wire width 29 $4\jtag_wb__adr$next[28:0]$1216 + attribute \src "libresoc.v:44048.3-44100.6" + wire width 3 $5\fsm_state$275$next[2:0]$1246 + attribute \src "libresoc.v:43914.3-43966.6" + wire width 3 $5\fsm_state$next[2:0]$1223 + attribute \src "libresoc.v:43667.19-43667.110" + wire width 30 $add$libresoc.v:43667$1118_Y + attribute \src "libresoc.v:43668.19-43668.110" + wire width 30 $add$libresoc.v:43668$1119_Y + attribute \src "libresoc.v:43675.19-43675.109" + wire width 5 $add$libresoc.v:43675$1127_Y + attribute \src "libresoc.v:43676.19-43676.109" + wire width 5 $add$libresoc.v:43676$1128_Y + attribute \src "libresoc.v:43600.19-43600.110" + wire $and$libresoc.v:43600$1051_Y + attribute \src "libresoc.v:43607.19-43607.110" + wire $and$libresoc.v:43607$1058_Y + attribute \src "libresoc.v:43610.19-43610.114" + wire $and$libresoc.v:43610$1061_Y + attribute \src "libresoc.v:43612.19-43612.112" + wire $and$libresoc.v:43612$1063_Y + attribute \src "libresoc.v:43614.19-43614.113" + wire $and$libresoc.v:43614$1065_Y + attribute \src "libresoc.v:43616.19-43616.121" + wire $and$libresoc.v:43616$1067_Y + attribute \src "libresoc.v:43620.19-43620.114" + wire $and$libresoc.v:43620$1071_Y + attribute \src "libresoc.v:43622.19-43622.112" + wire $and$libresoc.v:43622$1073_Y + attribute \src "libresoc.v:43624.19-43624.113" + wire $and$libresoc.v:43624$1075_Y + attribute \src "libresoc.v:43626.19-43626.132" + wire $and$libresoc.v:43626$1077_Y + attribute \src "libresoc.v:43629.18-43629.108" + wire $and$libresoc.v:43629$1080_Y + attribute \src "libresoc.v:43632.19-43632.114" + wire $and$libresoc.v:43632$1083_Y + attribute \src "libresoc.v:43634.19-43634.112" + wire $and$libresoc.v:43634$1085_Y + attribute \src "libresoc.v:43636.19-43636.113" + wire $and$libresoc.v:43636$1087_Y + attribute \src "libresoc.v:43638.19-43638.132" + wire $and$libresoc.v:43638$1089_Y + attribute \src "libresoc.v:43640.18-43640.110" + wire $and$libresoc.v:43640$1091_Y + attribute \src "libresoc.v:43642.19-43642.114" + wire $and$libresoc.v:43642$1093_Y + attribute \src "libresoc.v:43644.19-43644.112" + wire $and$libresoc.v:43644$1095_Y + attribute \src "libresoc.v:43646.19-43646.113" + wire $and$libresoc.v:43646$1097_Y + attribute \src "libresoc.v:43648.19-43648.129" + wire $and$libresoc.v:43648$1099_Y + attribute \src "libresoc.v:43653.19-43653.114" + wire $and$libresoc.v:43653$1104_Y + attribute \src "libresoc.v:43655.19-43655.112" + wire $and$libresoc.v:43655$1106_Y + attribute \src "libresoc.v:43657.19-43657.113" + wire $and$libresoc.v:43657$1108_Y + attribute \src "libresoc.v:43659.19-43659.129" + wire $and$libresoc.v:43659$1110_Y + attribute \src "libresoc.v:43679.18-43679.108" + wire $and$libresoc.v:43679$1131_Y + attribute \src "libresoc.v:43680.18-43680.111" + wire $and$libresoc.v:43680$1132_Y + attribute \src "libresoc.v:43704.17-43704.110" + wire $and$libresoc.v:43704$1156_Y + attribute \src "libresoc.v:43573.17-43573.110" + wire $eq$libresoc.v:43573$1024_Y + attribute \src "libresoc.v:43584.18-43584.111" + wire $eq$libresoc.v:43584$1035_Y + attribute \src "libresoc.v:43597.19-43597.112" + wire $eq$libresoc.v:43597$1048_Y + attribute \src "libresoc.v:43598.19-43598.112" + wire $eq$libresoc.v:43598$1049_Y + attribute \src "libresoc.v:43601.19-43601.112" + wire $eq$libresoc.v:43601$1052_Y + attribute \src "libresoc.v:43602.19-43602.112" + wire $eq$libresoc.v:43602$1053_Y + attribute \src "libresoc.v:43604.19-43604.112" + wire $eq$libresoc.v:43604$1055_Y + attribute \src "libresoc.v:43606.18-43606.111" + wire $eq$libresoc.v:43606$1057_Y + attribute \src "libresoc.v:43608.19-43608.112" + wire $eq$libresoc.v:43608$1059_Y + attribute \src "libresoc.v:43618.19-43618.112" + wire $eq$libresoc.v:43618$1069_Y + attribute \src "libresoc.v:43627.19-43627.112" + wire $eq$libresoc.v:43627$1078_Y + attribute \src "libresoc.v:43628.17-43628.110" + wire $eq$libresoc.v:43628$1079_Y + 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\$256 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" + wire \$259 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" + wire \$261 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" + wire \$263 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:231" + wire \$265 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:201" + wire width 30 \$267 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:201" + wire width 30 \$268 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:225" + wire width 30 \$270 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:225" + wire width 30 \$271 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 8 \$273 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" + wire \$276 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" + wire \$278 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" + wire \$280 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:183" + wire \$282 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:153" + wire width 5 \$284 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:153" + wire width 5 \$285 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:177" + wire width 5 \$287 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:177" + wire width 5 \$288 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:386" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:475" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:472" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:382" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 118 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 58 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire output 109 \TAP_bus__tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 119 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:394" + wire \TAP_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire \_fsm_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire \_fsm_isdr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire \_fsm_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire \_fsm_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:27" + wire \_fsm_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:215" + wire \_idblock_TAP_id_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + wire width 4 \_irblock_ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:129" + wire \_irblock_tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" + wire input 6 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" + wire input 4 \dmi0_ack_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 4 output 120 \dmi0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 4 \dmi0_addr_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:130" + wire width 8 \dmi0_addrsr__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:130" + wire width 8 \dmi0_addrsr__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:130" + wire \dmi0_addrsr__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:130" + wire \dmi0_addrsr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" + wire \dmi0_addrsr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" + wire \dmi0_addrsr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 8 \dmi0_addrsr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 8 \dmi0_addrsr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" + wire \dmi0_addrsr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" + wire \dmi0_addrsr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \dmi0_addrsr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \dmi0_addrsr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \dmi0_addrsr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \dmi0_addrsr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" + wire width 64 \dmi0_datasr__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" + wire width 64 \dmi0_datasr__i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" + wire width 64 \dmi0_datasr__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" + wire width 2 \dmi0_datasr__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" + wire width 2 \dmi0_datasr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" + wire \dmi0_datasr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" + wire width 2 \dmi0_datasr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 64 \dmi0_datasr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 64 \dmi0_datasr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" + wire \dmi0_datasr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" + wire \dmi0_datasr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \dmi0_datasr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \dmi0_datasr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \dmi0_datasr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \dmi0_datasr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 output 3 \dmi0_din + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 \dmi0_din$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 64 input 5 \dmi0_dout + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire output 1 \dmi0_req_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + wire output 2 \dmi0_we_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" + wire width 3 \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" + wire width 3 \fsm_state$275 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" + wire width 3 \fsm_state$275$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" + wire width 3 \fsm_state$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 61 \gpio_gpio0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 11 \gpio_gpio0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 12 \gpio_gpio0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 10 \gpio_gpio0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 62 \gpio_gpio0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 63 \gpio_gpio0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 91 \gpio_gpio10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 41 \gpio_gpio10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 42 \gpio_gpio10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 40 \gpio_gpio10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 92 \gpio_gpio10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 93 \gpio_gpio10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 94 \gpio_gpio11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 44 \gpio_gpio11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 45 \gpio_gpio11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 43 \gpio_gpio11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 95 \gpio_gpio11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 96 \gpio_gpio11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 97 \gpio_gpio12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 47 \gpio_gpio12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 48 \gpio_gpio12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 46 \gpio_gpio12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 98 \gpio_gpio12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 99 \gpio_gpio12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 100 \gpio_gpio13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 50 \gpio_gpio13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 51 \gpio_gpio13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 49 \gpio_gpio13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 101 \gpio_gpio13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 102 \gpio_gpio13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 103 \gpio_gpio14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 53 \gpio_gpio14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 54 \gpio_gpio14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 52 \gpio_gpio14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 104 \gpio_gpio14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 105 \gpio_gpio14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 106 \gpio_gpio15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 56 \gpio_gpio15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 57 \gpio_gpio15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 55 \gpio_gpio15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 107 \gpio_gpio15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 108 \gpio_gpio15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 64 \gpio_gpio1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 14 \gpio_gpio1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 15 \gpio_gpio1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 13 \gpio_gpio1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 65 \gpio_gpio1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 66 \gpio_gpio1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 67 \gpio_gpio2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 17 \gpio_gpio2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 18 \gpio_gpio2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 16 \gpio_gpio2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 68 \gpio_gpio2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 69 \gpio_gpio2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 70 \gpio_gpio3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 20 \gpio_gpio3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 21 \gpio_gpio3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 19 \gpio_gpio3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 71 \gpio_gpio3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 72 \gpio_gpio3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 73 \gpio_gpio4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 23 \gpio_gpio4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 24 \gpio_gpio4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 22 \gpio_gpio4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 74 \gpio_gpio4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 75 \gpio_gpio4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 76 \gpio_gpio5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 26 \gpio_gpio5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 27 \gpio_gpio5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 25 \gpio_gpio5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 77 \gpio_gpio5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 78 \gpio_gpio5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 79 \gpio_gpio6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 29 \gpio_gpio6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 30 \gpio_gpio6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 28 \gpio_gpio6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 80 \gpio_gpio6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 81 \gpio_gpio6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 82 \gpio_gpio7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 32 \gpio_gpio7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 33 \gpio_gpio7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 31 \gpio_gpio7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 83 \gpio_gpio7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 84 \gpio_gpio7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 85 \gpio_gpio8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 35 \gpio_gpio8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 36 \gpio_gpio8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 34 \gpio_gpio8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 86 \gpio_gpio8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 87 \gpio_gpio8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 88 \gpio_gpio9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 38 \gpio_gpio9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 39 \gpio_gpio9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 37 \gpio_gpio9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 89 \gpio_gpio9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 90 \gpio_gpio9__pad__oe + attribute \src "libresoc.v:42831.7-42831.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:437" + wire width 50 \io_bd + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:437" + wire width 50 \io_bd$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + wire \io_bd2core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:376" + wire \io_bd2io + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:373" + wire \io_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" + wire \io_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:436" + wire width 50 \io_sr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:436" + wire width 50 \io_sr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" + wire \io_update + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire input 116 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 29 output 110 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 29 \jtag_wb__adr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 112 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 64 input 117 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 64 output 115 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 64 \jtag_wb__dat_w$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 111 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 113 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 114 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:78" + wire width 29 \jtag_wb_addrsr__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:78" + wire width 29 \jtag_wb_addrsr__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:78" + wire \jtag_wb_addrsr__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:78" + wire \jtag_wb_addrsr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" + wire \jtag_wb_addrsr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" + wire \jtag_wb_addrsr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 29 \jtag_wb_addrsr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 29 \jtag_wb_addrsr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" + wire \jtag_wb_addrsr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" + wire \jtag_wb_addrsr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \jtag_wb_addrsr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \jtag_wb_addrsr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \jtag_wb_addrsr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \jtag_wb_addrsr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" + wire width 64 \jtag_wb_datasr__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" + wire width 64 \jtag_wb_datasr__i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" + wire width 64 \jtag_wb_datasr__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" + wire width 2 \jtag_wb_datasr__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" + wire width 2 \jtag_wb_datasr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" + wire \jtag_wb_datasr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" + wire width 2 \jtag_wb_datasr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 64 \jtag_wb_datasr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 64 \jtag_wb_datasr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" + wire \jtag_wb_datasr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" + wire \jtag_wb_datasr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \jtag_wb_datasr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \jtag_wb_datasr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \jtag_wb_datasr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \jtag_wb_datasr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" + wire \negjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" + wire \negjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" + wire input 7 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:52" + wire width 3 \sr0__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:52" + wire width 3 \sr0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:52" + wire \sr0__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:52" + wire \sr0__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" + wire \sr0_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" + wire \sr0_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 3 \sr0_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 3 \sr0_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" + wire \sr0_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" + wire \sr0_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \sr0_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \sr0_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \sr0_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \sr0_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 60 \uart_rx__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 9 \uart_rx__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 8 \uart_tx__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 59 \uart_tx__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:201" + cell $add $add$libresoc.v:43667$1118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 29 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 30 + connect \A \jtag_wb__adr + connect \B 1'1 + connect \Y $add$libresoc.v:43667$1118_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:41112$1889 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:225" + cell $add $add$libresoc.v:43668$1119 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 29 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_ra_alu0_0 - connect \B \addr_en_INT_ra_cr0_1 - connect \Y $or$issuer_ls180.v:41112$1889_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 30 + connect \A \jtag_wb__adr + connect \B 1'1 + connect \Y $add$libresoc.v:43668$1119_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:41113$1890 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:153" + cell $add $add$libresoc.v:43675$1127 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 + parameter \B_WIDTH 1 parameter \Y_WIDTH 5 - connect \A \addr_en_INT_ra_trap0_2 - connect \B \addr_en_INT_ra_logical0_3 - connect \Y $or$issuer_ls180.v:41113$1890_Y + connect \A \dmi0_addr_i + connect \B 1'1 + connect \Y $add$libresoc.v:43675$1127_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:41114$1891 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:177" + cell $add $add$libresoc.v:43676$1128 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 + parameter \B_WIDTH 1 parameter \Y_WIDTH 5 - connect \A \$439 - connect \B \$441 - connect \Y $or$issuer_ls180.v:41114$1891_Y + connect \A \dmi0_addr_i + connect \B 1'1 + connect \Y $add$libresoc.v:43676$1128_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:41115$1892 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $and $and$libresoc.v:43600$1051 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_ra_spr0_4 - connect \B \addr_en_INT_ra_div0_5 - connect \Y $or$issuer_ls180.v:41115$1892_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$145 + connect \Y $and$libresoc.v:43600$1051_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:41116$1893 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + cell $and $and$libresoc.v:43607$1058 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_ra_shiftrot0_7 - connect \B \addr_en_INT_ra_ldst0_8 - connect \Y $or$issuer_ls180.v:41116$1893_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$157 + connect \Y $and$libresoc.v:43607$1058_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:41117$1894 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $and $and$libresoc.v:43610$1061 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_ra_mul0_6 - connect \B \$447 - connect \Y $or$issuer_ls180.v:41117$1894_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$163 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:43610$1061_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:41118$1895 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $and $and$libresoc.v:43612$1063 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$445 - connect \B \$449 - connect \Y $or$issuer_ls180.v:41118$1895_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$167 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:43612$1063_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:41119$1896 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $and $and$libresoc.v:43614$1065 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$443 - connect \B \$451 - connect \Y $or$issuer_ls180.v:41119$1896_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$171 + connect \B \_fsm_update + connect \Y $and$libresoc.v:43614$1065_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:41169$1946 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $and $and$libresoc.v:43616$1067 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_rb_alu0_0 - connect \B \addr_en_INT_rb_cr0_1 - connect \Y $or$issuer_ls180.v:41169$1946_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_update_core_prev + connect \B \$175 + connect \Y $and$libresoc.v:43616$1067_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:41170$1947 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $and $and$libresoc.v:43620$1071 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_rb_trap0_2 - connect \B \addr_en_INT_rb_logical0_3 - connect \Y $or$issuer_ls180.v:41170$1947_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$181 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:43620$1071_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:41171$1948 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $and $and$libresoc.v:43622$1073 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$553 - connect \B \$555 - connect \Y $or$issuer_ls180.v:41171$1948_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$185 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:43622$1073_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:41172$1949 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $and $and$libresoc.v:43624$1075 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_rb_div0_4 - connect \B \addr_en_INT_rb_mul0_5 - connect \Y $or$issuer_ls180.v:41172$1949_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$189 + connect \B \_fsm_update + connect \Y $and$libresoc.v:43624$1075_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:41173$1950 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $and $and$libresoc.v:43626$1077 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_rb_shiftrot0_6 - connect \B \addr_en_INT_rb_ldst0_7 - connect \Y $or$issuer_ls180.v:41173$1950_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_update_core_prev + connect \B \$193 + connect \Y $and$libresoc.v:43626$1077_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:41174$1951 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + cell $and $and$libresoc.v:43629$1080 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$559 - connect \B \$561 - connect \Y $or$issuer_ls180.v:41174$1951_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$17 + connect \Y $and$libresoc.v:43629$1080_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:41175$1952 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $and $and$libresoc.v:43632$1083 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$557 - connect \B \$563 - connect \Y $or$issuer_ls180.v:41175$1952_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$201 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:43632$1083_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:41189$1966 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $and $and$libresoc.v:43634$1085 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_rc_shiftrot0_0 - connect \B \addr_en_INT_rc_ldst0_1 - connect \Y $or$issuer_ls180.v:41189$1966_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$205 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:43634$1085_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$issuer_ls180.v:41194$1971 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $and $and$libresoc.v:43636$1087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$597 - connect \B \$601 - connect \Y $or$issuer_ls180.v:41194$1971_Y + connect \A \$209 + connect \B \_fsm_update + connect \Y $and$libresoc.v:43636$1087_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$issuer_ls180.v:41196$1973 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $and $and$libresoc.v:43638$1089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$603 - connect \B \$605 - connect \Y $or$issuer_ls180.v:41196$1973_Y + connect \A \jtag_wb_datasr_update_core_prev + connect \B \$213 + connect \Y $and$libresoc.v:43638$1089_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:41233$2010 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" + cell $and $and$libresoc.v:43640$1091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \addr_en_XER_xer_so_logical0_1 - connect \B \addr_en_XER_xer_so_spr0_2 - connect \Y $or$issuer_ls180.v:41233$2010_Y + connect \A \$19 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:43640$1091_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:41234$2011 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $and $and$libresoc.v:43642$1093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \addr_en_XER_xer_so_alu0_0 - connect \B \$682 - connect \Y $or$issuer_ls180.v:41234$2011_Y + connect \A \$219 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:43642$1093_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:41235$2012 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $and $and$libresoc.v:43644$1095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \addr_en_XER_xer_so_mul0_4 - connect \B \addr_en_XER_xer_so_shiftrot0_5 - connect \Y $or$issuer_ls180.v:41235$2012_Y + connect \A \$223 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:43644$1095_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:41236$2013 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $and $and$libresoc.v:43646$1097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \addr_en_XER_xer_so_div0_3 - connect \B \$686 - connect \Y $or$issuer_ls180.v:41236$2013_Y + connect \A \$227 + connect \B \_fsm_update + connect \Y $and$libresoc.v:43646$1097_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:41237$2014 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $and $and$libresoc.v:43648$1099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$684 - connect \B \$688 - connect \Y $or$issuer_ls180.v:41237$2014_Y + connect \A \dmi0_addrsr_update_core_prev + connect \B \$231 + connect \Y $and$libresoc.v:43648$1099_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$issuer_ls180.v:41242$2020 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $and $and$libresoc.v:43653$1104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$693 - connect \B \$697 - connect \Y $or$issuer_ls180.v:41242$2020_Y + connect \A \$239 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:43653$1104_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:41261$2039 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $and $and$libresoc.v:43655$1106 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \addr_en_XER_xer_ca_spr0_1 - connect \B \addr_en_XER_xer_ca_shiftrot0_2 - connect \Y $or$issuer_ls180.v:41261$2039_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$243 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:43655$1106_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:41262$2040 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $and $and$libresoc.v:43657$1108 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \addr_en_XER_xer_ca_alu0_0 - connect \B \$738 - connect \Y $or$issuer_ls180.v:41262$2040_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$247 + connect \B \_fsm_update + connect \Y $and$libresoc.v:43657$1108_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $or $or$issuer_ls180.v:41267$2046 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $and $and$libresoc.v:43659$1110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$743 - connect \B \$747 - connect \Y $or$issuer_ls180.v:41267$2046_Y + connect \A \dmi0_datasr_update_core_prev + connect \B \$251 + connect \Y $and$libresoc.v:43659$1110_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:41296$2075 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + cell $and $and$libresoc.v:43679$1131 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 16 - connect \A \addr_en_CR_cr_a_cr0_0 - connect \B \addr_en_CR_cr_a_branch0_1 - connect \Y $or$issuer_ls180.v:41296$2075_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$31 + connect \Y $and$libresoc.v:43679$1131_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:41331$2110 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" + cell $and $and$libresoc.v:43680$1132 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \addr_en_FAST_fast1_trap0_1 - connect \B \addr_en_FAST_fast1_spr0_2 - connect \Y $or$issuer_ls180.v:41331$2110_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \_fsm_update + connect \Y $and$libresoc.v:43680$1132_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:41332$2111 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:382" + cell $and $and$libresoc.v:43704$1156 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \addr_en_FAST_fast1_branch0_0 - connect \B \$878 - connect \Y $or$issuer_ls180.v:41332$2111_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:43704$1156_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:41346$2125 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:43573$1024 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \addr_en_FAST_fast2_branch0_0 - connect \B \addr_en_FAST_fast2_trap0_1 - connect \Y $or$issuer_ls180.v:41346$2125_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:43573$1024_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $pos$issuer_ls180.v:40823$1596 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:43584$1035 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $extend$issuer_ls180.v:40823$1595_Y - connect \Y $pos$issuer_ls180.v:40823$1596_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:43584$1035_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $pos$issuer_ls180.v:40889$1663 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $eq $eq$libresoc.v:43597$1048 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A $extend$issuer_ls180.v:40889$1662_Y - connect \Y $pos$issuer_ls180.v:40889$1663_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'1 + connect \Y $eq$libresoc.v:43597$1048_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $pos$issuer_ls180.v:40893$1668 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $eq $eq$libresoc.v:43598$1049 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $extend$issuer_ls180.v:40893$1667_Y - connect \Y $pos$issuer_ls180.v:40893$1668_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 4'1111 + connect \Y $eq$libresoc.v:43598$1049_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $pos $pos$issuer_ls180.v:40965$1741 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:43601$1052 parameter \A_SIGNED 0 parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $extend$issuer_ls180.v:40965$1740_Y - connect \Y $pos$issuer_ls180.v:40965$1741_Y + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:43601$1052_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $pos $pos$issuer_ls180.v:40973$1750 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:43602$1053 parameter \A_SIGNED 0 parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $extend$issuer_ls180.v:40973$1749_Y - connect \Y $pos$issuer_ls180.v:40973$1750_Y + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:43602$1053_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $pos$issuer_ls180.v:41238$2016 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" + cell $eq $eq$libresoc.v:43604$1055 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $extend$issuer_ls180.v:41238$2015_Y - connect \Y $pos$issuer_ls180.v:41238$2016_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:43604$1055_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $pos$issuer_ls180.v:41263$2042 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" + cell $eq $eq$libresoc.v:43606$1057 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $extend$issuer_ls180.v:41263$2041_Y - connect \Y $pos$issuer_ls180.v:41263$2042_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:43606$1057_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $reduce_or $reduce_or$issuer_ls180.v:40907$1682 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + cell $eq $eq$libresoc.v:43608$1059 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$161 - connect \Y $reduce_or$issuer_ls180.v:40907$1682_Y + connect \A \_irblock_ir + connect \B 3'100 + connect \Y $eq$libresoc.v:43608$1059_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $reduce_or $reduce_or$issuer_ls180.v:40924$1699 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + cell $eq $eq$libresoc.v:43618$1069 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$165 - connect \Y $reduce_or$issuer_ls180.v:40924$1699_Y + connect \A \_irblock_ir + connect \B 3'101 + connect \Y $eq$libresoc.v:43618$1069_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $reduce_or $reduce_or$issuer_ls180.v:40944$1719 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + cell $eq $eq$libresoc.v:43627$1078 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$169 - connect \Y $reduce_or$issuer_ls180.v:40944$1719_Y + connect \A \_irblock_ir + connect \B 3'110 + connect \Y $eq$libresoc.v:43627$1078_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $reduce_or $reduce_or$issuer_ls180.v:40962$1737 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:43628$1079 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$173 - connect \Y $reduce_or$issuer_ls180.v:40962$1737_Y + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:43628$1079_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $reduce_or $reduce_or$issuer_ls180.v:40980$1757 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + cell $eq $eq$libresoc.v:43630$1081 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$177 - connect \Y $reduce_or$issuer_ls180.v:40980$1757_Y + connect \A \_irblock_ir + connect \B 3'111 + connect \Y $eq$libresoc.v:43630$1081_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $reduce_or $reduce_or$issuer_ls180.v:40984$1761 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + cell $eq $eq$libresoc.v:43639$1090 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \$181 - connect \Y $reduce_or$issuer_ls180.v:40984$1761_Y + connect \A \_irblock_ir + connect \B 4'1000 + connect \Y $eq$libresoc.v:43639$1090_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $reduce_or $reduce_or$issuer_ls180.v:40986$1763 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + cell $eq $eq$libresoc.v:43649$1100 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \$185 - connect \Y $reduce_or$issuer_ls180.v:40986$1763_Y + connect \A \_irblock_ir + connect \B 4'1001 + connect \Y $eq$libresoc.v:43649$1100_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $reduce_or $reduce_or$issuer_ls180.v:40988$1765 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + cell $eq $eq$libresoc.v:43650$1101 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \$189 - connect \Y $reduce_or$issuer_ls180.v:40988$1765_Y + connect \A \_irblock_ir + connect \B 4'1010 + connect \Y $eq$libresoc.v:43650$1101_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $reduce_or $reduce_or$issuer_ls180.v:40990$1767 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:43651$1102 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$193 - connect \Y $reduce_or$issuer_ls180.v:40990$1767_Y + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:43651$1102_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $reduce_or $reduce_or$issuer_ls180.v:40992$1769 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:229" + cell $eq $eq$libresoc.v:43660$1111 parameter \A_SIGNED 0 - parameter \A_WIDTH 12 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$197 - connect \Y $reduce_or$issuer_ls180.v:40992$1769_Y + connect \A \fsm_state + connect \B 1'0 + connect \Y $eq$libresoc.v:43660$1111_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" - cell $reduce_or $reduce_or$issuer_ls180.v:41120$1897 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:43662$1113 parameter \A_SIGNED 0 - parameter \A_WIDTH 9 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A { \rp_INT_ra_ldst0_8 \rp_INT_ra_shiftrot0_7 \rp_INT_ra_mul0_6 \rp_INT_ra_div0_5 \rp_INT_ra_spr0_4 \rp_INT_ra_logical0_3 \rp_INT_ra_trap0_2 \rp_INT_ra_cr0_1 \rp_INT_ra_alu0_0 } - connect \Y $reduce_or$issuer_ls180.v:41120$1897_Y + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:43662$1113_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" - cell $reduce_or $reduce_or$issuer_ls180.v:41176$1953 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" + cell $eq $eq$libresoc.v:43663$1114 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \rp_INT_rb_ldst0_7 \rp_INT_rb_shiftrot0_6 \rp_INT_rb_mul0_5 \rp_INT_rb_div0_4 \rp_INT_rb_logical0_3 \rp_INT_rb_trap0_2 \rp_INT_rb_cr0_1 \rp_INT_rb_alu0_0 } - connect \Y $reduce_or$issuer_ls180.v:41176$1953_Y + connect \A \fsm_state + connect \B 1'1 + connect \Y $eq$libresoc.v:43663$1114_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" - cell $reduce_or $reduce_or$issuer_ls180.v:41190$1967 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" + cell $eq $eq$libresoc.v:43664$1115 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A { \rp_INT_rc_ldst0_1 \rp_INT_rc_shiftrot0_0 } - connect \Y $reduce_or$issuer_ls180.v:41190$1967_Y + connect \A \fsm_state + connect \B 2'10 + connect \Y $eq$libresoc.v:43664$1115_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" - cell $reduce_or $reduce_or$issuer_ls180.v:41333$2112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:231" + cell $eq $eq$libresoc.v:43666$1117 parameter \A_SIGNED 0 parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A { \rp_FAST_fast1_spr0_2 \rp_FAST_fast1_trap0_1 \rp_FAST_fast1_branch0_0 } - connect \Y $reduce_or$issuer_ls180.v:41333$2112_Y + connect \A \fsm_state + connect \B 2'10 + connect \Y $eq$libresoc.v:43666$1117_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" - cell $reduce_or $reduce_or$issuer_ls180.v:41347$2126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" + cell $eq $eq$libresoc.v:43670$1122 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \rp_FAST_fast2_trap0_1 \rp_FAST_fast2_branch0_0 } - connect \Y $reduce_or$issuer_ls180.v:41347$2126_Y + connect \A \fsm_state$275 + connect \B 1'1 + connect \Y $eq$libresoc.v:43670$1122_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" - cell $reduce_or $reduce_or$issuer_ls180.v:41354$2133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" + cell $eq $eq$libresoc.v:43671$1123 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \rp_SPR_spr1_spr0_0 - connect \Y $reduce_or$issuer_ls180.v:41354$2133_Y + connect \A \fsm_state$275 + connect \B 2'10 + connect \Y $eq$libresoc.v:43671$1123_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$issuer_ls180.v:40746$1518 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:183" + cell $eq $eq$libresoc.v:43674$1126 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B \$1234 - connect \Y $sshl$issuer_ls180.v:40746$1518_Y + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state$275 + connect \B 2'10 + connect \Y $eq$libresoc.v:43674$1126_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$issuer_ls180.v:40754$1526 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" + cell $eq $eq$libresoc.v:43677$1129 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B \$1254 - connect \Y $sshl$issuer_ls180.v:40754$1526_Y + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:43677$1129_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$issuer_ls180.v:40762$1534 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" + cell $eq $eq$libresoc.v:43681$1133 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B \$1274 - connect \Y $sshl$issuer_ls180.v:40762$1534_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:43681$1133_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$issuer_ls180.v:40770$1542 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:43682$1134 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B \$1294 - connect \Y $sshl$issuer_ls180.v:40770$1542_Y + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:43682$1134_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:386" + cell $eq $eq$libresoc.v:43683$1135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:43683$1135_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + cell $pos $extend$libresoc.v:43669$1120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \dmi0_addr_i + connect \Y $extend$libresoc.v:43669$1120_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$issuer_ls180.v:40778$1550 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $ne $ne$libresoc.v:43609$1060 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B \$1314 - connect \Y $sshl$issuer_ls180.v:40778$1550_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43609$1060_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$issuer_ls180.v:40786$1558 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $ne $ne$libresoc.v:43611$1062 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B \$1334 - connect \Y $sshl$issuer_ls180.v:40786$1558_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43611$1062_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sshl $sshl$issuer_ls180.v:41286$2065 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $ne $ne$libresoc.v:43613$1064 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B \$785 - connect \Y $sshl$issuer_ls180.v:41286$2065_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43613$1064_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sshl $sshl$issuer_ls180.v:41294$2073 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $ne $ne$libresoc.v:43619$1070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B \$801 - connect \Y $sshl$issuer_ls180.v:41294$2073_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43619$1070_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" - cell $sshl $sshl$issuer_ls180.v:41303$2082 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $ne $ne$libresoc.v:43621$1072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B \$820 - connect \Y $sshl$issuer_ls180.v:41303$2082_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43621$1072_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" - cell $sshl $sshl$issuer_ls180.v:41311$2090 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $ne $ne$libresoc.v:43623$1074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B \$836 - connect \Y $sshl$issuer_ls180.v:41311$2090_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43623$1074_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$issuer_ls180.v:40745$1517 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $ne $ne$libresoc.v:43631$1082 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \core_cr_out - connect \Y $sub$issuer_ls180.v:40745$1517_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43631$1082_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$issuer_ls180.v:40753$1525 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $ne $ne$libresoc.v:43633$1084 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \core_cr_out - connect \Y $sub$issuer_ls180.v:40753$1525_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43633$1084_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$issuer_ls180.v:40761$1533 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $ne $ne$libresoc.v:43635$1086 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \core_cr_out - connect \Y $sub$issuer_ls180.v:40761$1533_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43635$1086_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$issuer_ls180.v:40769$1541 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $ne $ne$libresoc.v:43641$1092 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \core_cr_out - connect \Y $sub$issuer_ls180.v:40769$1541_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43641$1092_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$issuer_ls180.v:40777$1549 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $ne $ne$libresoc.v:43643$1094 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \core_cr_out - connect \Y $sub$issuer_ls180.v:40777$1549_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43643$1094_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$issuer_ls180.v:40785$1557 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $ne $ne$libresoc.v:43645$1096 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \core_cr_out - connect \Y $sub$issuer_ls180.v:40785$1557_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43645$1096_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $sub $sub$issuer_ls180.v:40994$1771 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $ne $ne$libresoc.v:43652$1103 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \counter - connect \B 1'1 - connect \Y $sub$issuer_ls180.v:40994$1771_Y + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43652$1103_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sub $sub$issuer_ls180.v:41285$2064 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $ne $ne$libresoc.v:43654$1105 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \core_cr_in1 - connect \Y $sub$issuer_ls180.v:41285$2064_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43654$1105_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sub $sub$issuer_ls180.v:41293$2072 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $ne $ne$libresoc.v:43656$1107 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \core_cr_in1 - connect \Y $sub$issuer_ls180.v:41293$2072_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:43656$1107_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" - cell $sub $sub$issuer_ls180.v:41302$2081 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $not $not$libresoc.v:43615$1066 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_update_core + connect \Y $not$libresoc.v:43615$1066_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $not $not$libresoc.v:43625$1076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_update_core + connect \Y $not$libresoc.v:43625$1076_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $not $not$libresoc.v:43637$1088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_update_core + connect \Y $not$libresoc.v:43637$1088_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $not $not$libresoc.v:43647$1098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_update_core + connect \Y $not$libresoc.v:43647$1098_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $not $not$libresoc.v:43658$1109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_update_core + connect \Y $not$libresoc.v:43658$1109_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:229" + cell $not $not$libresoc.v:43661$1112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$256 + connect \Y $not$libresoc.v:43661$1112_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $or $or$libresoc.v:43595$1046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \core_cr_in2 - connect \Y $sub$issuer_ls180.v:41302$2081_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \$11 + connect \Y $or$libresoc.v:43595$1046_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" - cell $sub $sub$issuer_ls180.v:41310$2089 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $or $or$libresoc.v:43599$1050 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \core_cr_in2$1 - connect \Y $sub$issuer_ls180.v:41310$2089_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40657$1429 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_rego - connect \S \wp$996 - connect \Y $ternary$issuer_ls180.v:40657$1429_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40663$1435 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_rego - connect \S \wp$1014 - connect \Y $ternary$issuer_ls180.v:40663$1435_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40669$1441 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_rego - connect \S \wp$1036 - connect \Y $ternary$issuer_ls180.v:40669$1441_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40675$1447 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_rego - connect \S \wp$1056 - connect \Y $ternary$issuer_ls180.v:40675$1447_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40681$1453 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_rego - connect \S \wp$1076 - connect \Y $ternary$issuer_ls180.v:40681$1453_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40687$1459 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_rego - connect \S \wp$1095 - connect \Y $ternary$issuer_ls180.v:40687$1459_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40693$1465 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_rego - connect \S \wp$1113 - connect \Y $ternary$issuer_ls180.v:40693$1465_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40699$1471 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_ea - connect \S \wp$1129 - connect \Y $ternary$issuer_ls180.v:40699$1471_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40733$1505 - parameter \WIDTH 8 - connect \A 8'00000000 - connect \B \core_core_cr_wr - connect \S \wp$1202 - connect \Y $ternary$issuer_ls180.v:40733$1505_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40747$1519 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$1236 - connect \S \wp$1230 - connect \Y $ternary$issuer_ls180.v:40747$1519_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40755$1527 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$1256 - connect \S \wp$1250 - connect \Y $ternary$issuer_ls180.v:40755$1527_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40763$1535 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$1276 - connect \S \wp$1270 - connect \Y $ternary$issuer_ls180.v:40763$1535_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40771$1543 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$1296 - connect \S \wp$1290 - connect \Y $ternary$issuer_ls180.v:40771$1543_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40779$1551 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$1316 - connect \S \wp$1310 - connect \Y $ternary$issuer_ls180.v:40779$1551_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40787$1559 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$1336 - connect \S \wp$1330 - connect \Y $ternary$issuer_ls180.v:40787$1559_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40806$1578 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \wp$1377 - connect \Y $ternary$issuer_ls180.v:40806$1578_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$141 + connect \B \$143 + connect \Y $or$libresoc.v:43599$1050_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40812$1584 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \wp$1393 - connect \Y $ternary$issuer_ls180.v:40812$1584_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $or $or$libresoc.v:43603$1054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$149 + connect \B \$151 + connect \Y $or$libresoc.v:43603$1054_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40818$1590 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \wp$1409 - connect \Y $ternary$issuer_ls180.v:40818$1590_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + cell $or $or$libresoc.v:43605$1056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$153 + connect \B \$155 + connect \Y $or$libresoc.v:43605$1056_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40833$1606 - parameter \WIDTH 3 - connect \A 3'000 - connect \B 3'100 - connect \S \wp$1443 - connect \Y $ternary$issuer_ls180.v:40833$1606_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + cell $or $or$libresoc.v:43617$1068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$13 + connect \B \$15 + connect \Y $or$libresoc.v:43617$1068_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40839$1612 - parameter \WIDTH 3 - connect \A 3'000 - connect \B 3'100 - connect \S \wp$1459 - connect \Y $ternary$issuer_ls180.v:40839$1612_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" + cell $or $or$libresoc.v:43665$1116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$259 + connect \B \$261 + connect \Y $or$libresoc.v:43665$1116_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40845$1618 - parameter \WIDTH 3 - connect \A 3'000 - connect \B 3'100 - connect \S \wp$1475 - connect \Y $ternary$issuer_ls180.v:40845$1618_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $or $or$libresoc.v:43672$1124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \B \$25 + connect \Y $or$libresoc.v:43672$1124_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40851$1624 - parameter \WIDTH 3 - connect \A 3'000 - connect \B 3'100 - connect \S \wp$1491 - connect \Y $ternary$issuer_ls180.v:40851$1624_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" + cell $or $or$libresoc.v:43673$1125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$276 + connect \B \$278 + connect \Y $or$libresoc.v:43673$1125_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40867$1640 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \wp$1527 - connect \Y $ternary$issuer_ls180.v:40867$1640_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + cell $or $or$libresoc.v:43678$1130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \B \$29 + connect \Y $or$libresoc.v:43678$1130_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40873$1646 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \wp$1543 - connect \Y $ternary$issuer_ls180.v:40873$1646_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $or $or$libresoc.v:43693$1145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$3 + connect \Y $or$libresoc.v:43693$1145_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40879$1652 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \wp$1559 - connect \Y $ternary$issuer_ls180.v:40879$1652_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + cell $pos $pos$libresoc.v:43669$1121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:43669$1120_Y + connect \Y $pos$libresoc.v:43669$1121_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40885$1658 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \wp$1575 - connect \Y $ternary$issuer_ls180.v:40885$1658_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40905$1680 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fasto1 - connect \S \wp$1620 - connect \Y $ternary$issuer_ls180.v:40905$1680_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40912$1687 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fasto1 - connect \S \wp$1636 - connect \Y $ternary$issuer_ls180.v:40912$1687_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40918$1693 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fasto1 - connect \S \wp$1652 - connect \Y $ternary$issuer_ls180.v:40918$1693_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40926$1701 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fasto2 - connect \S \wp$1668 - connect \Y $ternary$issuer_ls180.v:40926$1701_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40932$1707 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fasto2 - connect \S \wp$1684 - connect \Y $ternary$issuer_ls180.v:40932$1707_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40954$1729 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43574$1025 parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \wp$1728 - connect \Y $ternary$issuer_ls180.v:40954$1729_Y + connect \A \gpio_gpio9__pad__i + connect \B \io_bd [29] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43574$1025_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40961$1736 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43575$1026 parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \wp$1744 - connect \Y $ternary$issuer_ls180.v:40961$1736_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40972$1748 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \wp$1768 - connect \Y $ternary$issuer_ls180.v:40972$1748_Y + connect \A \gpio_gpio9__core__o + connect \B \io_bd [30] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43575$1026_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:40982$1759 - parameter \WIDTH 10 - connect \A 10'0000000000 - connect \B \core_spro - connect \S \wp$1788 - connect \Y $ternary$issuer_ls180.v:40982$1759_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41063$1840 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_alu0_0 - connect \Y $ternary$issuer_ls180.v:41063$1840_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41069$1846 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_cr0_1 - connect \Y $ternary$issuer_ls180.v:41069$1846_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41075$1852 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_trap0_2 - connect \Y $ternary$issuer_ls180.v:41075$1852_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41081$1858 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_logical0_3 - connect \Y $ternary$issuer_ls180.v:41081$1858_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41087$1864 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_spr0_4 - connect \Y $ternary$issuer_ls180.v:41087$1864_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41093$1870 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_div0_5 - connect \Y $ternary$issuer_ls180.v:41093$1870_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41099$1876 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_mul0_6 - connect \Y $ternary$issuer_ls180.v:41099$1876_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41105$1882 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_shiftrot0_7 - connect \Y $ternary$issuer_ls180.v:41105$1882_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41111$1888 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_ldst0_8 - connect \Y $ternary$issuer_ls180.v:41111$1888_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41126$1903 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg2 - connect \S \rp_INT_rb_alu0_0 - connect \Y $ternary$issuer_ls180.v:41126$1903_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41132$1909 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg2 - connect \S \rp_INT_rb_cr0_1 - connect \Y $ternary$issuer_ls180.v:41132$1909_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41138$1915 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg2 - connect \S \rp_INT_rb_trap0_2 - connect \Y $ternary$issuer_ls180.v:41138$1915_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41144$1921 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg2 - connect \S \rp_INT_rb_logical0_3 - connect \Y $ternary$issuer_ls180.v:41144$1921_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41150$1927 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg2 - connect \S \rp_INT_rb_div0_4 - connect \Y $ternary$issuer_ls180.v:41150$1927_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41156$1933 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg2 - connect \S \rp_INT_rb_mul0_5 - connect \Y $ternary$issuer_ls180.v:41156$1933_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41162$1939 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg2 - connect \S \rp_INT_rb_shiftrot0_6 - connect \Y $ternary$issuer_ls180.v:41162$1939_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41168$1945 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg2 - connect \S \rp_INT_rb_ldst0_7 - connect \Y $ternary$issuer_ls180.v:41168$1945_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41182$1959 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg3 - connect \S \rp_INT_rc_shiftrot0_0 - connect \Y $ternary$issuer_ls180.v:41182$1959_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41188$1965 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg3 - connect \S \rp_INT_rc_ldst0_1 - connect \Y $ternary$issuer_ls180.v:41188$1965_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41202$1979 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43576$1027 parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \rp_XER_xer_so_alu0_0 - connect \Y $ternary$issuer_ls180.v:41202$1979_Y + connect \A \gpio_gpio9__core__oe + connect \B \io_bd [31] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43576$1027_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41208$1985 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43577$1028 parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \rp_XER_xer_so_logical0_1 - connect \Y $ternary$issuer_ls180.v:41208$1985_Y + connect \A \gpio_gpio10__pad__i + connect \B \io_bd [32] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43577$1028_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41214$1991 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43578$1029 parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \rp_XER_xer_so_spr0_2 - connect \Y $ternary$issuer_ls180.v:41214$1991_Y + connect \A \gpio_gpio10__core__o + connect \B \io_bd [33] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43578$1029_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41220$1997 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43579$1030 parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \rp_XER_xer_so_div0_3 - connect \Y $ternary$issuer_ls180.v:41220$1997_Y + connect \A \gpio_gpio10__core__oe + connect \B \io_bd [34] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43579$1030_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41226$2003 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43580$1031 parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \rp_XER_xer_so_mul0_4 - connect \Y $ternary$issuer_ls180.v:41226$2003_Y + connect \A \gpio_gpio11__pad__i + connect \B \io_bd [35] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43580$1031_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41232$2009 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43581$1032 parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \rp_XER_xer_so_shiftrot0_5 - connect \Y $ternary$issuer_ls180.v:41232$2009_Y + connect \A \gpio_gpio11__core__o + connect \B \io_bd [36] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43581$1032_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41248$2026 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \rp_XER_xer_ca_alu0_0 - connect \Y $ternary$issuer_ls180.v:41248$2026_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43582$1033 + parameter \WIDTH 1 + connect \A \gpio_gpio11__core__oe + connect \B \io_bd [37] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43582$1033_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41254$2032 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \rp_XER_xer_ca_spr0_1 - connect \Y $ternary$issuer_ls180.v:41254$2032_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43583$1034 + parameter \WIDTH 1 + connect \A \gpio_gpio12__pad__i + connect \B \io_bd [38] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43583$1034_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41260$2038 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \rp_XER_xer_ca_shiftrot0_2 - connect \Y $ternary$issuer_ls180.v:41260$2038_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43585$1036 + parameter \WIDTH 1 + connect \A \gpio_gpio12__core__o + connect \B \io_bd [39] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43585$1036_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41273$2052 - parameter \WIDTH 3 - connect \A 3'000 - connect \B 3'100 - connect \S \rp_XER_xer_ov_spr0_0 - connect \Y $ternary$issuer_ls180.v:41273$2052_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43586$1037 + parameter \WIDTH 1 + connect \A \gpio_gpio12__core__oe + connect \B \io_bd [40] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43586$1037_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41279$2058 - parameter \WIDTH 8 - connect \A 8'00000000 - connect \B \core_core_cr_rd - connect \S \rp_CR_full_cr_cr0_0 - connect \Y $ternary$issuer_ls180.v:41279$2058_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41287$2066 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$787 - connect \S \rp_CR_cr_a_cr0_0 - connect \Y $ternary$issuer_ls180.v:41287$2066_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41295$2074 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$803 - connect \S \rp_CR_cr_a_branch0_1 - connect \Y $ternary$issuer_ls180.v:41295$2074_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41304$2083 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$822 - connect \S \rp_CR_cr_b_cr0_0 - connect \Y $ternary$issuer_ls180.v:41304$2083_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41312$2091 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$838 - connect \S \rp_CR_cr_c_cr0_0 - connect \Y $ternary$issuer_ls180.v:41312$2091_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41318$2097 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fast1 - connect \S \rp_FAST_fast1_branch0_0 - connect \Y $ternary$issuer_ls180.v:41318$2097_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41324$2103 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fast1 - connect \S \rp_FAST_fast1_trap0_1 - connect \Y $ternary$issuer_ls180.v:41324$2103_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41330$2109 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fast1 - connect \S \rp_FAST_fast1_spr0_2 - connect \Y $ternary$issuer_ls180.v:41330$2109_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41339$2118 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fast2 - connect \S \rp_FAST_fast2_branch0_0 - connect \Y $ternary$issuer_ls180.v:41339$2118_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41345$2124 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fast2 - connect \S \rp_FAST_fast2_trap0_1 - connect \Y $ternary$issuer_ls180.v:41345$2124_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $ternary$issuer_ls180.v:41353$2132 - parameter \WIDTH 10 - connect \A 10'0000000000 - connect \B \core_spr1 - connect \S \rp_SPR_spr1_spr0_0 - connect \Y $ternary$issuer_ls180.v:41353$2132_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:41370$2149 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_rego - connect \S \wp - connect \Y $ternary$issuer_ls180.v:41370$2149_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $ternary$issuer_ls180.v:41376$2155 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_rego - connect \S \wp$975 - connect \Y $ternary$issuer_ls180.v:41376$2155_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43587$1038 + parameter \WIDTH 1 + connect \A \gpio_gpio13__pad__i + connect \B \io_bd [41] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43587$1038_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:41540.6-41557.4" - cell \cr \cr - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \data_i \cr_data_i - connect \full_rd2__data_o \full_rd2__data_o - connect \full_rd2__ren \full_rd2__ren - connect \full_rd__data_o \cr_full_rd__data_o - connect \full_rd__ren \cr_full_rd__ren - connect \full_wr__data_i \cr_full_wr__data_i - connect \full_wr__wen \cr_full_wr__wen - connect \src1__data_o \cr_src1__data_o - connect \src1__ren \cr_src1__ren - connect \src2__data_o \cr_src2__data_o - connect \src2__ren \cr_src2__ren - connect \src3__data_o \cr_src3__data_o - connect \src3__ren \cr_src3__ren - connect \wen \cr_wen + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43588$1039 + parameter \WIDTH 1 + connect \A \gpio_gpio13__core__o + connect \B \io_bd [42] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43588$1039_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:41558.11-41579.4" - cell \dec_ALU \dec_ALU - connect \ALU_ALU__data_len \dec_ALU_ALU_ALU__data_len - connect \ALU_ALU__fn_unit \dec_ALU_ALU_ALU__fn_unit - connect \ALU_ALU__imm_data__data \dec_ALU_ALU_ALU__imm_data__data - connect \ALU_ALU__imm_data__ok \dec_ALU_ALU_ALU__imm_data__ok - connect \ALU_ALU__input_carry \dec_ALU_ALU_ALU__input_carry - connect \ALU_ALU__insn \dec_ALU_ALU_ALU__insn - connect \ALU_ALU__insn_type \dec_ALU_ALU_ALU__insn_type - connect \ALU_ALU__invert_in \dec_ALU_ALU_ALU__invert_in - connect \ALU_ALU__invert_out \dec_ALU_ALU_ALU__invert_out - connect \ALU_ALU__is_32bit \dec_ALU_ALU_ALU__is_32bit - connect \ALU_ALU__is_signed \dec_ALU_ALU_ALU__is_signed - connect \ALU_ALU__oe__oe \dec_ALU_ALU_ALU__oe__oe - connect \ALU_ALU__oe__ok \dec_ALU_ALU_ALU__oe__ok - connect \ALU_ALU__output_carry \dec_ALU_ALU_ALU__output_carry - connect \ALU_ALU__rc__ok \dec_ALU_ALU_ALU__rc__ok - connect \ALU_ALU__rc__rc \dec_ALU_ALU_ALU__rc__rc - connect \ALU_ALU__write_cr0 \dec_ALU_ALU_ALU__write_cr0 - connect \ALU_ALU__zero_a \dec_ALU_ALU_ALU__zero_a - connect \bigendian \dec_ALU_bigendian - connect \raw_opcode_in \dec_ALU_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43589$1040 + parameter \WIDTH 1 + connect \A \gpio_gpio13__core__oe + connect \B \io_bd [43] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43589$1040_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:41580.14-41592.4" - cell \dec_BRANCH \dec_BRANCH - connect \BRANCH_BRANCH__cia \dec_BRANCH_BRANCH_BRANCH__cia - connect \BRANCH_BRANCH__fn_unit \dec_BRANCH_BRANCH_BRANCH__fn_unit - connect \BRANCH_BRANCH__imm_data__data \dec_BRANCH_BRANCH_BRANCH__imm_data__data - connect \BRANCH_BRANCH__imm_data__ok \dec_BRANCH_BRANCH_BRANCH__imm_data__ok - connect \BRANCH_BRANCH__insn \dec_BRANCH_BRANCH_BRANCH__insn - connect \BRANCH_BRANCH__insn_type \dec_BRANCH_BRANCH_BRANCH__insn_type - connect \BRANCH_BRANCH__is_32bit \dec_BRANCH_BRANCH_BRANCH__is_32bit - connect \BRANCH_BRANCH__lk \dec_BRANCH_BRANCH_BRANCH__lk - connect \bigendian \dec_BRANCH_bigendian - connect \core_pc \core_pc - connect \raw_opcode_in \dec_BRANCH_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43590$1041 + parameter \WIDTH 1 + connect \A \gpio_gpio14__pad__i + connect \B \io_bd [44] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43590$1041_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:41593.10-41599.4" - cell \dec_CR \dec_CR - connect \CR_CR__fn_unit \dec_CR_CR_CR__fn_unit - connect \CR_CR__insn \dec_CR_CR_CR__insn - connect \CR_CR__insn_type \dec_CR_CR_CR__insn_type - connect \bigendian \dec_CR_bigendian - connect \raw_opcode_in \dec_CR_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43591$1042 + parameter \WIDTH 1 + connect \A \gpio_gpio14__core__o + connect \B \io_bd [45] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43591$1042_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:41600.11-41621.4" - cell \dec_DIV \dec_DIV - connect \DIV_DIV__data_len \dec_DIV_DIV_DIV__data_len - connect \DIV_DIV__fn_unit \dec_DIV_DIV_DIV__fn_unit - connect \DIV_DIV__imm_data__data \dec_DIV_DIV_DIV__imm_data__data - connect \DIV_DIV__imm_data__ok \dec_DIV_DIV_DIV__imm_data__ok - connect \DIV_DIV__input_carry \dec_DIV_DIV_DIV__input_carry - connect \DIV_DIV__insn \dec_DIV_DIV_DIV__insn - connect \DIV_DIV__insn_type \dec_DIV_DIV_DIV__insn_type - connect \DIV_DIV__invert_in \dec_DIV_DIV_DIV__invert_in - connect \DIV_DIV__invert_out \dec_DIV_DIV_DIV__invert_out - connect \DIV_DIV__is_32bit \dec_DIV_DIV_DIV__is_32bit - connect \DIV_DIV__is_signed \dec_DIV_DIV_DIV__is_signed - connect \DIV_DIV__oe__oe \dec_DIV_DIV_DIV__oe__oe - connect \DIV_DIV__oe__ok \dec_DIV_DIV_DIV__oe__ok - connect \DIV_DIV__output_carry \dec_DIV_DIV_DIV__output_carry - connect \DIV_DIV__rc__ok \dec_DIV_DIV_DIV__rc__ok - connect \DIV_DIV__rc__rc \dec_DIV_DIV_DIV__rc__rc - connect \DIV_DIV__write_cr0 \dec_DIV_DIV_DIV__write_cr0 - connect \DIV_DIV__zero_a \dec_DIV_DIV_DIV__zero_a - connect \bigendian \dec_DIV_bigendian - connect \raw_opcode_in \dec_DIV_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43592$1043 + parameter \WIDTH 1 + connect \A \gpio_gpio14__core__oe + connect \B \io_bd [46] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43592$1043_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:41622.12-41641.4" - cell \dec_LDST \dec_LDST - connect \LDST_LDST__byte_reverse \dec_LDST_LDST_LDST__byte_reverse - connect \LDST_LDST__data_len \dec_LDST_LDST_LDST__data_len - connect \LDST_LDST__fn_unit \dec_LDST_LDST_LDST__fn_unit - connect \LDST_LDST__imm_data__data \dec_LDST_LDST_LDST__imm_data__data - connect \LDST_LDST__imm_data__ok \dec_LDST_LDST_LDST__imm_data__ok - connect \LDST_LDST__insn \dec_LDST_LDST_LDST__insn - connect \LDST_LDST__insn_type \dec_LDST_LDST_LDST__insn_type - connect \LDST_LDST__is_32bit \dec_LDST_LDST_LDST__is_32bit - connect \LDST_LDST__is_signed \dec_LDST_LDST_LDST__is_signed - connect \LDST_LDST__ldst_mode \dec_LDST_LDST_LDST__ldst_mode - connect \LDST_LDST__oe__oe \dec_LDST_LDST_LDST__oe__oe - connect \LDST_LDST__oe__ok \dec_LDST_LDST_LDST__oe__ok - connect \LDST_LDST__rc__ok \dec_LDST_LDST_LDST__rc__ok - connect \LDST_LDST__rc__rc \dec_LDST_LDST_LDST__rc__rc - connect \LDST_LDST__sign_extend \dec_LDST_LDST_LDST__sign_extend - connect \LDST_LDST__zero_a \dec_LDST_LDST_LDST__zero_a - connect \bigendian \dec_LDST_bigendian - connect \raw_opcode_in \dec_LDST_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43593$1044 + parameter \WIDTH 1 + connect \A \gpio_gpio15__pad__i + connect \B \io_bd [47] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43593$1044_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:41642.15-41663.4" - cell \dec_LOGICAL \dec_LOGICAL - connect \LOGICAL_LOGICAL__data_len \dec_LOGICAL_LOGICAL_LOGICAL__data_len - connect \LOGICAL_LOGICAL__fn_unit \dec_LOGICAL_LOGICAL_LOGICAL__fn_unit - connect \LOGICAL_LOGICAL__imm_data__data \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__data - connect \LOGICAL_LOGICAL__imm_data__ok \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__ok - connect \LOGICAL_LOGICAL__input_carry \dec_LOGICAL_LOGICAL_LOGICAL__input_carry - connect \LOGICAL_LOGICAL__insn \dec_LOGICAL_LOGICAL_LOGICAL__insn - connect \LOGICAL_LOGICAL__insn_type \dec_LOGICAL_LOGICAL_LOGICAL__insn_type - connect \LOGICAL_LOGICAL__invert_in \dec_LOGICAL_LOGICAL_LOGICAL__invert_in - connect \LOGICAL_LOGICAL__invert_out \dec_LOGICAL_LOGICAL_LOGICAL__invert_out - connect \LOGICAL_LOGICAL__is_32bit \dec_LOGICAL_LOGICAL_LOGICAL__is_32bit - connect \LOGICAL_LOGICAL__is_signed \dec_LOGICAL_LOGICAL_LOGICAL__is_signed - connect \LOGICAL_LOGICAL__oe__oe \dec_LOGICAL_LOGICAL_LOGICAL__oe__oe - connect \LOGICAL_LOGICAL__oe__ok \dec_LOGICAL_LOGICAL_LOGICAL__oe__ok - connect \LOGICAL_LOGICAL__output_carry \dec_LOGICAL_LOGICAL_LOGICAL__output_carry - connect \LOGICAL_LOGICAL__rc__ok \dec_LOGICAL_LOGICAL_LOGICAL__rc__ok - connect \LOGICAL_LOGICAL__rc__rc \dec_LOGICAL_LOGICAL_LOGICAL__rc__rc - connect \LOGICAL_LOGICAL__write_cr0 \dec_LOGICAL_LOGICAL_LOGICAL__write_cr0 - connect \LOGICAL_LOGICAL__zero_a \dec_LOGICAL_LOGICAL_LOGICAL__zero_a - connect \bigendian \dec_LOGICAL_bigendian - connect \raw_opcode_in \dec_LOGICAL_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43594$1045 + parameter \WIDTH 1 + connect \A \gpio_gpio15__core__o + connect \B \io_bd [48] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43594$1045_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:41664.11-41679.4" - cell \dec_MUL \dec_MUL - connect \MUL_MUL__fn_unit \dec_MUL_MUL_MUL__fn_unit - connect \MUL_MUL__imm_data__data \dec_MUL_MUL_MUL__imm_data__data - connect \MUL_MUL__imm_data__ok \dec_MUL_MUL_MUL__imm_data__ok - connect \MUL_MUL__insn \dec_MUL_MUL_MUL__insn - connect \MUL_MUL__insn_type \dec_MUL_MUL_MUL__insn_type - connect \MUL_MUL__is_32bit \dec_MUL_MUL_MUL__is_32bit - connect \MUL_MUL__is_signed \dec_MUL_MUL_MUL__is_signed - connect \MUL_MUL__oe__oe \dec_MUL_MUL_MUL__oe__oe - connect \MUL_MUL__oe__ok \dec_MUL_MUL_MUL__oe__ok - connect \MUL_MUL__rc__ok \dec_MUL_MUL_MUL__rc__ok - connect \MUL_MUL__rc__rc \dec_MUL_MUL_MUL__rc__rc - connect \MUL_MUL__write_cr0 \dec_MUL_MUL_MUL__write_cr0 - connect \bigendian \dec_MUL_bigendian - connect \raw_opcode_in \dec_MUL_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43596$1047 + parameter \WIDTH 1 + connect \A \gpio_gpio15__core__oe + connect \B \io_bd [49] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43596$1047_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:41680.17-41699.4" - cell \dec_SHIFT_ROT \dec_SHIFT_ROT - connect \SHIFT_ROT_SHIFT_ROT__fn_unit \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__fn_unit - connect \SHIFT_ROT_SHIFT_ROT__imm_data__data \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__data - connect \SHIFT_ROT_SHIFT_ROT__imm_data__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__ok - connect \SHIFT_ROT_SHIFT_ROT__input_carry \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_carry - connect \SHIFT_ROT_SHIFT_ROT__input_cr \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_cr - connect \SHIFT_ROT_SHIFT_ROT__insn \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn - connect \SHIFT_ROT_SHIFT_ROT__insn_type \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn_type - connect \SHIFT_ROT_SHIFT_ROT__is_32bit \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_32bit - connect \SHIFT_ROT_SHIFT_ROT__is_signed \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_signed - connect \SHIFT_ROT_SHIFT_ROT__oe__oe \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__oe - connect \SHIFT_ROT_SHIFT_ROT__oe__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__ok - connect \SHIFT_ROT_SHIFT_ROT__output_carry \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_carry - connect \SHIFT_ROT_SHIFT_ROT__output_cr \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_cr - connect \SHIFT_ROT_SHIFT_ROT__rc__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__ok - connect \SHIFT_ROT_SHIFT_ROT__rc__rc \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__rc - connect \SHIFT_ROT_SHIFT_ROT__write_cr0 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__write_cr0 - connect \bigendian \dec_SHIFT_ROT_bigendian - connect \raw_opcode_in \dec_SHIFT_ROT_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:475" + cell $mux $ternary$libresoc.v:43684$1136 + parameter \WIDTH 1 + connect \A \uart_tx__core__o + connect \B \io_bd [0] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43684$1136_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:41700.11-41707.4" - cell \dec_SPR \dec_SPR - connect \SPR_SPR__fn_unit \dec_SPR_SPR_SPR__fn_unit - connect \SPR_SPR__insn \dec_SPR_SPR_SPR__insn - connect \SPR_SPR__insn_type \dec_SPR_SPR_SPR__insn_type - connect \SPR_SPR__is_32bit \dec_SPR_SPR_SPR__is_32bit - connect \bigendian \dec_SPR_bigendian - connect \raw_opcode_in \dec_SPR_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:472" + cell $mux $ternary$libresoc.v:43685$1137 + parameter \WIDTH 1 + connect \A \uart_rx__pad__i + connect \B \io_bd [1] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43685$1137_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:41708.8-41726.4" - cell \fast \fast - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dest1__addr \fast_dest1__addr - connect \dest1__data_i \fast_dest1__data_i - connect \dest1__wen \fast_dest1__wen - connect \issue__addr \issue__addr - connect \issue__addr$1 \issue__addr$3 - connect \issue__data_i \issue__data_i - connect \issue__data_o \issue__data_o - connect \issue__ren \issue__ren - connect \issue__wen \issue__wen - connect \src1__addr \fast_src1__addr - connect \src1__data_o \fast_src1__data_o - connect \src1__ren \fast_src1__ren - connect \src2__addr \fast_src2__addr - connect \src2__data_o \fast_src2__data_o - connect \src2__ren \fast_src2__ren + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43686$1138 + parameter \WIDTH 1 + connect \A \gpio_gpio0__pad__i + connect \B \io_bd [2] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43686$1138_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:41727.7-42049.4" - cell \fus \fus - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a_ok \fus_cr_a_ok - connect \cr_a_ok$110 \fus_cr_a_ok$113 - connect \cr_a_ok$111 \fus_cr_a_ok$114 - connect \cr_a_ok$112 \fus_cr_a_ok$115 - connect \cr_a_ok$113 \fus_cr_a_ok$116 - connect \cr_a_ok$114 \fus_cr_a_ok$117 - connect \cu_ad__go_i \cu_ad__go_i - connect \cu_ad__rel_o \cu_ad__rel_o - connect \cu_busy_o \fus_cu_busy_o - connect \cu_busy_o$11 \fus_cu_busy_o$14 - connect \cu_busy_o$14 \fus_cu_busy_o$17 - connect \cu_busy_o$17 \fus_cu_busy_o$20 - connect \cu_busy_o$2 \fus_cu_busy_o$5 - connect \cu_busy_o$20 \fus_cu_busy_o$23 - connect \cu_busy_o$23 \fus_cu_busy_o$26 - connect \cu_busy_o$26 \fus_cu_busy_o$29 - connect \cu_busy_o$5 \fus_cu_busy_o$8 - connect \cu_busy_o$8 \fus_cu_busy_o$11 - connect \cu_issue_i \fus_cu_issue_i - connect \cu_issue_i$1 \fus_cu_issue_i$4 - connect \cu_issue_i$10 \fus_cu_issue_i$13 - connect \cu_issue_i$13 \fus_cu_issue_i$16 - connect \cu_issue_i$16 \fus_cu_issue_i$19 - connect \cu_issue_i$19 \fus_cu_issue_i$22 - connect \cu_issue_i$22 \fus_cu_issue_i$25 - connect \cu_issue_i$25 \fus_cu_issue_i$28 - connect \cu_issue_i$4 \fus_cu_issue_i$7 - connect \cu_issue_i$7 \fus_cu_issue_i$10 - connect \cu_rd__go_i \fus_cu_rd__go_i - connect \cu_rd__go_i$29 \fus_cu_rd__go_i$32 - connect \cu_rd__go_i$32 \fus_cu_rd__go_i$35 - connect \cu_rd__go_i$35 \fus_cu_rd__go_i$38 - connect \cu_rd__go_i$38 \fus_cu_rd__go_i$41 - connect \cu_rd__go_i$41 \fus_cu_rd__go_i$44 - connect \cu_rd__go_i$44 \fus_cu_rd__go_i$47 - connect \cu_rd__go_i$47 \fus_cu_rd__go_i$50 - connect \cu_rd__go_i$50 \fus_cu_rd__go_i$53 - connect \cu_rd__go_i$70 \fus_cu_rd__go_i$73 - connect \cu_rd__rel_o \fus_cu_rd__rel_o - connect \cu_rd__rel_o$28 \fus_cu_rd__rel_o$31 - connect \cu_rd__rel_o$31 \fus_cu_rd__rel_o$34 - connect \cu_rd__rel_o$34 \fus_cu_rd__rel_o$37 - connect \cu_rd__rel_o$37 \fus_cu_rd__rel_o$40 - connect \cu_rd__rel_o$40 \fus_cu_rd__rel_o$43 - connect \cu_rd__rel_o$43 \fus_cu_rd__rel_o$46 - connect \cu_rd__rel_o$46 \fus_cu_rd__rel_o$49 - connect \cu_rd__rel_o$49 \fus_cu_rd__rel_o$52 - connect \cu_rd__rel_o$69 \fus_cu_rd__rel_o$72 - connect \cu_rdmaskn_i \fus_cu_rdmaskn_i - connect \cu_rdmaskn_i$12 \fus_cu_rdmaskn_i$15 - connect \cu_rdmaskn_i$15 \fus_cu_rdmaskn_i$18 - connect \cu_rdmaskn_i$18 \fus_cu_rdmaskn_i$21 - connect \cu_rdmaskn_i$21 \fus_cu_rdmaskn_i$24 - connect \cu_rdmaskn_i$24 \fus_cu_rdmaskn_i$27 - connect \cu_rdmaskn_i$27 \fus_cu_rdmaskn_i$30 - connect \cu_rdmaskn_i$3 \fus_cu_rdmaskn_i$6 - connect \cu_rdmaskn_i$6 \fus_cu_rdmaskn_i$9 - connect \cu_rdmaskn_i$9 \fus_cu_rdmaskn_i$12 - connect \cu_st__go_i \cu_st__go_i - connect \cu_st__rel_o \cu_st__rel_o - connect \cu_wr__go_i \fus_cu_wr__go_i - connect \cu_wr__go_i$100 \fus_cu_wr__go_i$103 - connect \cu_wr__go_i$102 \fus_cu_wr__go_i$105 - connect \cu_wr__go_i$137 \fus_cu_wr__go_i$140 - connect \cu_wr__go_i$82 \fus_cu_wr__go_i$85 - connect \cu_wr__go_i$85 \fus_cu_wr__go_i$88 - connect \cu_wr__go_i$88 \fus_cu_wr__go_i$91 - connect \cu_wr__go_i$91 \fus_cu_wr__go_i$94 - connect \cu_wr__go_i$94 \fus_cu_wr__go_i$97 - connect \cu_wr__go_i$97 \fus_cu_wr__go_i$100 - connect \cu_wr__rel_o \fus_cu_wr__rel_o - connect \cu_wr__rel_o$101 \fus_cu_wr__rel_o$104 - connect \cu_wr__rel_o$136 \fus_cu_wr__rel_o$139 - connect \cu_wr__rel_o$81 \fus_cu_wr__rel_o$84 - connect \cu_wr__rel_o$84 \fus_cu_wr__rel_o$87 - connect \cu_wr__rel_o$87 \fus_cu_wr__rel_o$90 - connect \cu_wr__rel_o$90 \fus_cu_wr__rel_o$93 - connect \cu_wr__rel_o$93 \fus_cu_wr__rel_o$96 - connect \cu_wr__rel_o$96 \fus_cu_wr__rel_o$99 - connect \cu_wr__rel_o$99 \fus_cu_wr__rel_o$102 - connect \dest1_o \fus_dest1_o - connect \dest1_o$103 \fus_dest1_o$106 - connect \dest1_o$104 \fus_dest1_o$107 - connect \dest1_o$105 \fus_dest1_o$108 - connect \dest1_o$106 \fus_dest1_o$109 - connect \dest1_o$107 \fus_dest1_o$110 - connect \dest1_o$108 \fus_dest1_o$111 - connect \dest1_o$109 \fus_dest1_o$112 - connect \dest1_o$141 \fus_dest1_o$144 - connect \dest2_o \fus_dest2_o - connect \dest2_o$115 \fus_dest2_o$118 - connect \dest2_o$116 \fus_dest2_o$119 - connect \dest2_o$117 \fus_dest2_o$120 - connect \dest2_o$118 \fus_dest2_o$121 - connect \dest2_o$119 \fus_dest2_o$122 - connect \dest2_o$142 \fus_dest2_o$145 - connect \dest2_o$144 \fus_dest2_o$147 - connect \dest2_o$150 \fus_dest2_o$153 - connect \dest3_o \fus_dest3_o - connect \dest3_o$122 \fus_dest3_o$125 - connect \dest3_o$123 \fus_dest3_o$126 - connect \dest3_o$127 \fus_dest3_o$130 - connect \dest3_o$128 \fus_dest3_o$131 - connect \dest3_o$143 \fus_dest3_o$146 - connect \dest3_o$145 \fus_dest3_o$148 - connect \dest3_o$147 \fus_dest3_o$150 - connect \dest4_o \fus_dest4_o - connect \dest4_o$133 \fus_dest4_o$136 - connect \dest4_o$134 \fus_dest4_o$137 - connect \dest4_o$135 \fus_dest4_o$138 - connect \dest4_o$148 \fus_dest4_o$151 - connect \dest5_o \fus_dest5_o - connect \dest5_o$132 \fus_dest5_o$135 - connect \dest5_o$149 \fus_dest5_o$152 - connect \dest6_o \fus_dest6_o - connect \ea \fus_ea - connect \fast1_ok \fus_fast1_ok - connect \fast1_ok$138 \fus_fast1_ok$141 - connect \fast1_ok$139 \fus_fast1_ok$142 - connect \fast2_ok \fus_fast2_ok - connect \fast2_ok$140 \fus_fast2_ok$143 - connect \full_cr_ok \fus_full_cr_ok - connect \ldst_port0_addr_exc_o \fus_ldst_port0_addr_exc_o - connect \ldst_port0_addr_i \fus_ldst_port0_addr_i - connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok - connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o - connect \ldst_port0_busy_o \fus_ldst_port0_busy_o - connect \ldst_port0_data_len \fus_ldst_port0_data_len - connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i - connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i - connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i - connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok - connect \msr_ok \fus_msr_ok - connect \nia_ok \fus_nia_ok - connect \nia_ok$146 \fus_nia_ok$149 - connect \o \fus_o - connect \o_ok \fus_o_ok - connect \o_ok$80 \fus_o_ok$83 - connect \o_ok$83 \fus_o_ok$86 - connect \o_ok$86 \fus_o_ok$89 - connect \o_ok$89 \fus_o_ok$92 - connect \o_ok$92 \fus_o_ok$95 - connect \o_ok$95 \fus_o_ok$98 - connect \o_ok$98 \fus_o_ok$101 - connect \oper_i_alu_alu0__data_len \fus_oper_i_alu_alu0__data_len - connect \oper_i_alu_alu0__fn_unit \fus_oper_i_alu_alu0__fn_unit - connect \oper_i_alu_alu0__imm_data__data \fus_oper_i_alu_alu0__imm_data__data - connect \oper_i_alu_alu0__imm_data__ok \fus_oper_i_alu_alu0__imm_data__ok - connect \oper_i_alu_alu0__input_carry \fus_oper_i_alu_alu0__input_carry - connect \oper_i_alu_alu0__insn \fus_oper_i_alu_alu0__insn - connect \oper_i_alu_alu0__insn_type \fus_oper_i_alu_alu0__insn_type - connect \oper_i_alu_alu0__invert_in \fus_oper_i_alu_alu0__invert_in - connect \oper_i_alu_alu0__invert_out \fus_oper_i_alu_alu0__invert_out - connect \oper_i_alu_alu0__is_32bit \fus_oper_i_alu_alu0__is_32bit - connect \oper_i_alu_alu0__is_signed \fus_oper_i_alu_alu0__is_signed - connect \oper_i_alu_alu0__oe__oe \fus_oper_i_alu_alu0__oe__oe - connect \oper_i_alu_alu0__oe__ok \fus_oper_i_alu_alu0__oe__ok - connect \oper_i_alu_alu0__output_carry \fus_oper_i_alu_alu0__output_carry - connect \oper_i_alu_alu0__rc__ok \fus_oper_i_alu_alu0__rc__ok - connect \oper_i_alu_alu0__rc__rc \fus_oper_i_alu_alu0__rc__rc - connect \oper_i_alu_alu0__write_cr0 \fus_oper_i_alu_alu0__write_cr0 - connect \oper_i_alu_alu0__zero_a \fus_oper_i_alu_alu0__zero_a - connect \oper_i_alu_branch0__cia \fus_oper_i_alu_branch0__cia - connect \oper_i_alu_branch0__fn_unit \fus_oper_i_alu_branch0__fn_unit - connect \oper_i_alu_branch0__imm_data__data \fus_oper_i_alu_branch0__imm_data__data - connect \oper_i_alu_branch0__imm_data__ok \fus_oper_i_alu_branch0__imm_data__ok - connect \oper_i_alu_branch0__insn \fus_oper_i_alu_branch0__insn - connect \oper_i_alu_branch0__insn_type \fus_oper_i_alu_branch0__insn_type - connect \oper_i_alu_branch0__is_32bit \fus_oper_i_alu_branch0__is_32bit - connect \oper_i_alu_branch0__lk \fus_oper_i_alu_branch0__lk - connect \oper_i_alu_cr0__fn_unit \fus_oper_i_alu_cr0__fn_unit - connect \oper_i_alu_cr0__insn \fus_oper_i_alu_cr0__insn - connect \oper_i_alu_cr0__insn_type \fus_oper_i_alu_cr0__insn_type - connect \oper_i_alu_div0__data_len \fus_oper_i_alu_div0__data_len - connect \oper_i_alu_div0__fn_unit \fus_oper_i_alu_div0__fn_unit - connect \oper_i_alu_div0__imm_data__data \fus_oper_i_alu_div0__imm_data__data - connect \oper_i_alu_div0__imm_data__ok \fus_oper_i_alu_div0__imm_data__ok - connect \oper_i_alu_div0__input_carry \fus_oper_i_alu_div0__input_carry - connect \oper_i_alu_div0__insn \fus_oper_i_alu_div0__insn - connect \oper_i_alu_div0__insn_type \fus_oper_i_alu_div0__insn_type - connect \oper_i_alu_div0__invert_in \fus_oper_i_alu_div0__invert_in - connect \oper_i_alu_div0__invert_out \fus_oper_i_alu_div0__invert_out - connect \oper_i_alu_div0__is_32bit \fus_oper_i_alu_div0__is_32bit - connect \oper_i_alu_div0__is_signed \fus_oper_i_alu_div0__is_signed - connect \oper_i_alu_div0__oe__oe \fus_oper_i_alu_div0__oe__oe - connect \oper_i_alu_div0__oe__ok \fus_oper_i_alu_div0__oe__ok - connect \oper_i_alu_div0__output_carry \fus_oper_i_alu_div0__output_carry - connect \oper_i_alu_div0__rc__ok \fus_oper_i_alu_div0__rc__ok - connect \oper_i_alu_div0__rc__rc \fus_oper_i_alu_div0__rc__rc - connect \oper_i_alu_div0__write_cr0 \fus_oper_i_alu_div0__write_cr0 - connect \oper_i_alu_div0__zero_a \fus_oper_i_alu_div0__zero_a - connect \oper_i_alu_logical0__data_len \fus_oper_i_alu_logical0__data_len - connect \oper_i_alu_logical0__fn_unit \fus_oper_i_alu_logical0__fn_unit - connect \oper_i_alu_logical0__imm_data__data \fus_oper_i_alu_logical0__imm_data__data - connect \oper_i_alu_logical0__imm_data__ok \fus_oper_i_alu_logical0__imm_data__ok - connect \oper_i_alu_logical0__input_carry \fus_oper_i_alu_logical0__input_carry - connect \oper_i_alu_logical0__insn \fus_oper_i_alu_logical0__insn - connect \oper_i_alu_logical0__insn_type \fus_oper_i_alu_logical0__insn_type - connect \oper_i_alu_logical0__invert_in \fus_oper_i_alu_logical0__invert_in - connect \oper_i_alu_logical0__invert_out \fus_oper_i_alu_logical0__invert_out - connect \oper_i_alu_logical0__is_32bit \fus_oper_i_alu_logical0__is_32bit - connect \oper_i_alu_logical0__is_signed \fus_oper_i_alu_logical0__is_signed - connect \oper_i_alu_logical0__oe__oe \fus_oper_i_alu_logical0__oe__oe - connect \oper_i_alu_logical0__oe__ok \fus_oper_i_alu_logical0__oe__ok - connect \oper_i_alu_logical0__output_carry \fus_oper_i_alu_logical0__output_carry - connect \oper_i_alu_logical0__rc__ok \fus_oper_i_alu_logical0__rc__ok - connect \oper_i_alu_logical0__rc__rc \fus_oper_i_alu_logical0__rc__rc - connect \oper_i_alu_logical0__write_cr0 \fus_oper_i_alu_logical0__write_cr0 - connect \oper_i_alu_logical0__zero_a \fus_oper_i_alu_logical0__zero_a - connect \oper_i_alu_mul0__fn_unit \fus_oper_i_alu_mul0__fn_unit - connect \oper_i_alu_mul0__imm_data__data \fus_oper_i_alu_mul0__imm_data__data - connect \oper_i_alu_mul0__imm_data__ok \fus_oper_i_alu_mul0__imm_data__ok - connect \oper_i_alu_mul0__insn \fus_oper_i_alu_mul0__insn - connect \oper_i_alu_mul0__insn_type \fus_oper_i_alu_mul0__insn_type - connect \oper_i_alu_mul0__is_32bit \fus_oper_i_alu_mul0__is_32bit - connect \oper_i_alu_mul0__is_signed \fus_oper_i_alu_mul0__is_signed - connect \oper_i_alu_mul0__oe__oe \fus_oper_i_alu_mul0__oe__oe - connect \oper_i_alu_mul0__oe__ok \fus_oper_i_alu_mul0__oe__ok - connect \oper_i_alu_mul0__rc__ok \fus_oper_i_alu_mul0__rc__ok - connect \oper_i_alu_mul0__rc__rc \fus_oper_i_alu_mul0__rc__rc - connect \oper_i_alu_mul0__write_cr0 \fus_oper_i_alu_mul0__write_cr0 - connect \oper_i_alu_shift_rot0__fn_unit \fus_oper_i_alu_shift_rot0__fn_unit - connect \oper_i_alu_shift_rot0__imm_data__data \fus_oper_i_alu_shift_rot0__imm_data__data - connect \oper_i_alu_shift_rot0__imm_data__ok \fus_oper_i_alu_shift_rot0__imm_data__ok - connect \oper_i_alu_shift_rot0__input_carry \fus_oper_i_alu_shift_rot0__input_carry - connect \oper_i_alu_shift_rot0__input_cr \fus_oper_i_alu_shift_rot0__input_cr - connect \oper_i_alu_shift_rot0__insn \fus_oper_i_alu_shift_rot0__insn - connect \oper_i_alu_shift_rot0__insn_type \fus_oper_i_alu_shift_rot0__insn_type - connect \oper_i_alu_shift_rot0__is_32bit \fus_oper_i_alu_shift_rot0__is_32bit - connect \oper_i_alu_shift_rot0__is_signed \fus_oper_i_alu_shift_rot0__is_signed - connect \oper_i_alu_shift_rot0__oe__oe \fus_oper_i_alu_shift_rot0__oe__oe - connect \oper_i_alu_shift_rot0__oe__ok \fus_oper_i_alu_shift_rot0__oe__ok - connect \oper_i_alu_shift_rot0__output_carry \fus_oper_i_alu_shift_rot0__output_carry - connect \oper_i_alu_shift_rot0__output_cr \fus_oper_i_alu_shift_rot0__output_cr - connect \oper_i_alu_shift_rot0__rc__ok \fus_oper_i_alu_shift_rot0__rc__ok - connect \oper_i_alu_shift_rot0__rc__rc \fus_oper_i_alu_shift_rot0__rc__rc - connect \oper_i_alu_shift_rot0__write_cr0 \fus_oper_i_alu_shift_rot0__write_cr0 - connect \oper_i_alu_spr0__fn_unit \fus_oper_i_alu_spr0__fn_unit - connect \oper_i_alu_spr0__insn \fus_oper_i_alu_spr0__insn - connect \oper_i_alu_spr0__insn_type \fus_oper_i_alu_spr0__insn_type - connect \oper_i_alu_spr0__is_32bit \fus_oper_i_alu_spr0__is_32bit - connect \oper_i_alu_trap0__cia \fus_oper_i_alu_trap0__cia - connect \oper_i_alu_trap0__fn_unit \fus_oper_i_alu_trap0__fn_unit - connect \oper_i_alu_trap0__insn \fus_oper_i_alu_trap0__insn - connect \oper_i_alu_trap0__insn_type \fus_oper_i_alu_trap0__insn_type - connect \oper_i_alu_trap0__is_32bit \fus_oper_i_alu_trap0__is_32bit - connect \oper_i_alu_trap0__msr \fus_oper_i_alu_trap0__msr - connect \oper_i_alu_trap0__trapaddr \fus_oper_i_alu_trap0__trapaddr - connect \oper_i_alu_trap0__traptype \fus_oper_i_alu_trap0__traptype - connect \oper_i_ldst_ldst0__byte_reverse \fus_oper_i_ldst_ldst0__byte_reverse - connect \oper_i_ldst_ldst0__data_len \fus_oper_i_ldst_ldst0__data_len - connect \oper_i_ldst_ldst0__fn_unit \fus_oper_i_ldst_ldst0__fn_unit - connect \oper_i_ldst_ldst0__imm_data__data \fus_oper_i_ldst_ldst0__imm_data__data - connect \oper_i_ldst_ldst0__imm_data__ok \fus_oper_i_ldst_ldst0__imm_data__ok - connect \oper_i_ldst_ldst0__insn \fus_oper_i_ldst_ldst0__insn - connect \oper_i_ldst_ldst0__insn_type \fus_oper_i_ldst_ldst0__insn_type - connect \oper_i_ldst_ldst0__is_32bit \fus_oper_i_ldst_ldst0__is_32bit - connect \oper_i_ldst_ldst0__is_signed \fus_oper_i_ldst_ldst0__is_signed - connect \oper_i_ldst_ldst0__ldst_mode \fus_oper_i_ldst_ldst0__ldst_mode - connect \oper_i_ldst_ldst0__oe__oe \fus_oper_i_ldst_ldst0__oe__oe - connect \oper_i_ldst_ldst0__oe__ok \fus_oper_i_ldst_ldst0__oe__ok - connect \oper_i_ldst_ldst0__rc__ok \fus_oper_i_ldst_ldst0__rc__ok - connect \oper_i_ldst_ldst0__rc__rc \fus_oper_i_ldst_ldst0__rc__rc - connect \oper_i_ldst_ldst0__sign_extend \fus_oper_i_ldst_ldst0__sign_extend - connect \oper_i_ldst_ldst0__zero_a \fus_oper_i_ldst_ldst0__zero_a - connect \spr1_ok \fus_spr1_ok - connect \src1_i \fus_src1_i - connect \src1_i$30 \fus_src1_i$33 - connect \src1_i$33 \fus_src1_i$36 - connect \src1_i$36 \fus_src1_i$39 - connect \src1_i$39 \fus_src1_i$42 - connect \src1_i$42 \fus_src1_i$45 - connect \src1_i$45 \fus_src1_i$48 - connect \src1_i$48 \fus_src1_i$51 - connect \src1_i$51 \fus_src1_i$54 - connect \src1_i$74 \fus_src1_i$77 - connect \src2_i \fus_src2_i - connect \src2_i$52 \fus_src2_i$55 - connect \src2_i$53 \fus_src2_i$56 - connect \src2_i$54 \fus_src2_i$57 - connect \src2_i$55 \fus_src2_i$58 - connect \src2_i$56 \fus_src2_i$59 - connect \src2_i$57 \fus_src2_i$60 - connect \src2_i$58 \fus_src2_i$61 - connect \src2_i$77 \fus_src2_i$80 - connect \src2_i$79 \fus_src2_i$82 - connect \src3_i \fus_src3_i - connect \src3_i$59 \fus_src3_i$62 - connect \src3_i$60 \fus_src3_i$63 - connect \src3_i$61 \fus_src3_i$64 - connect \src3_i$62 \fus_src3_i$65 - connect \src3_i$63 \fus_src3_i$66 - connect \src3_i$67 \fus_src3_i$70 - connect \src3_i$71 \fus_src3_i$74 - connect \src3_i$75 \fus_src3_i$78 - connect \src3_i$76 \fus_src3_i$79 - connect \src4_i \fus_src4_i - connect \src4_i$64 \fus_src4_i$67 - connect \src4_i$65 \fus_src4_i$68 - connect \src4_i$68 \fus_src4_i$71 - connect \src4_i$78 \fus_src4_i$81 - connect \src5_i \fus_src5_i - connect \src5_i$66 \fus_src5_i$69 - connect \src5_i$72 \fus_src5_i$75 - connect \src6_i \fus_src6_i - connect \src6_i$73 \fus_src6_i$76 - connect \xer_ca_ok \fus_xer_ca_ok - connect \xer_ca_ok$120 \fus_xer_ca_ok$123 - connect \xer_ca_ok$121 \fus_xer_ca_ok$124 - connect \xer_ov_ok \fus_xer_ov_ok - connect \xer_ov_ok$124 \fus_xer_ov_ok$127 - connect \xer_ov_ok$125 \fus_xer_ov_ok$128 - connect \xer_ov_ok$126 \fus_xer_ov_ok$129 - connect \xer_so_ok \fus_xer_so_ok - connect \xer_so_ok$129 \fus_xer_so_ok$132 - connect \xer_so_ok$130 \fus_xer_so_ok$133 - connect \xer_so_ok$131 \fus_xer_so_ok$134 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43687$1139 + parameter \WIDTH 1 + connect \A \gpio_gpio0__core__o + connect \B \io_bd [3] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43687$1139_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42050.9-42068.4" - cell \int \int - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dest1__addr \int_dest1__addr - connect \dest1__data_i \int_dest1__data_i - connect \dest1__wen \int_dest1__wen - connect \dmi__addr \dmi__addr - connect \dmi__data_o \dmi__data_o - connect \dmi__ren \dmi__ren - connect \src1__addr \int_src1__addr - connect \src1__data_o \int_src1__data_o - connect \src1__ren \int_src1__ren - connect \src2__addr \int_src2__addr - connect \src2__data_o \int_src2__data_o - connect \src2__ren \int_src2__ren - connect \src3__addr \int_src3__addr - connect \src3__data_o \int_src3__data_o - connect \src3__ren \int_src3__ren + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43688$1140 + parameter \WIDTH 1 + connect \A \gpio_gpio0__core__oe + connect \B \io_bd [4] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43688$1140_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42069.6-42093.4" - cell \l0 \l0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dbus__ack \dbus__ack - connect \dbus__adr \dbus__adr - connect \dbus__cyc \dbus__cyc - connect \dbus__dat_r \dbus__dat_r - connect \dbus__dat_w \dbus__dat_w - connect \dbus__err \dbus__err - connect \dbus__sel \dbus__sel - connect \dbus__stb \dbus__stb - connect \dbus__we \dbus__we - connect \ldst_port0_addr_exc_o \fus_ldst_port0_addr_exc_o - connect \ldst_port0_addr_i \fus_ldst_port0_addr_i - connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok - connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o - connect \ldst_port0_busy_o \fus_ldst_port0_busy_o - connect \ldst_port0_data_len \fus_ldst_port0_data_len - connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i - connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i - connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i - connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43689$1141 + parameter \WIDTH 1 + connect \A \gpio_gpio1__pad__i + connect \B \io_bd [5] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43689$1141_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42094.18-42098.4" - cell \rdpick_CR_cr_a \rdpick_CR_cr_a - connect \en_o \rdpick_CR_cr_a_en_o - connect \i \rdpick_CR_cr_a_i - connect \o \rdpick_CR_cr_a_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43690$1142 + parameter \WIDTH 1 + connect \A \gpio_gpio1__core__o + connect \B \io_bd [6] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43690$1142_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42099.18-42103.4" - cell \rdpick_CR_cr_b \rdpick_CR_cr_b - connect \en_o \rdpick_CR_cr_b_en_o - connect \i \rdpick_CR_cr_b_i - connect \o \rdpick_CR_cr_b_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43691$1143 + parameter \WIDTH 1 + connect \A \gpio_gpio1__core__oe + connect \B \io_bd [7] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43691$1143_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42104.18-42108.4" - cell \rdpick_CR_cr_c \rdpick_CR_cr_c - connect \en_o \rdpick_CR_cr_c_en_o - connect \i \rdpick_CR_cr_c_i - connect \o \rdpick_CR_cr_c_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43692$1144 + parameter \WIDTH 1 + connect \A \gpio_gpio2__pad__i + connect \B \io_bd [8] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43692$1144_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42109.21-42113.4" - cell \rdpick_CR_full_cr \rdpick_CR_full_cr - connect \en_o \rdpick_CR_full_cr_en_o - connect \i \rdpick_CR_full_cr_i - connect \o \rdpick_CR_full_cr_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43694$1146 + parameter \WIDTH 1 + connect \A \gpio_gpio2__core__o + connect \B \io_bd [9] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43694$1146_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42114.21-42118.4" - cell \rdpick_FAST_fast1 \rdpick_FAST_fast1 - connect \en_o \rdpick_FAST_fast1_en_o - connect \i \rdpick_FAST_fast1_i - connect \o \rdpick_FAST_fast1_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43695$1147 + parameter \WIDTH 1 + connect \A \gpio_gpio2__core__oe + connect \B \io_bd [10] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43695$1147_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42119.21-42123.4" - cell \rdpick_FAST_fast2 \rdpick_FAST_fast2 - connect \en_o \rdpick_FAST_fast2_en_o - connect \i \rdpick_FAST_fast2_i - connect \o \rdpick_FAST_fast2_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43696$1148 + parameter \WIDTH 1 + connect \A \gpio_gpio3__pad__i + connect \B \io_bd [11] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43696$1148_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42124.17-42128.4" - cell \rdpick_INT_ra \rdpick_INT_ra - connect \en_o \rdpick_INT_ra_en_o - connect \i \rdpick_INT_ra_i - connect \o \rdpick_INT_ra_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43697$1149 + parameter \WIDTH 1 + connect \A \gpio_gpio3__core__o + connect \B \io_bd [12] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43697$1149_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42129.17-42133.4" - cell \rdpick_INT_rb \rdpick_INT_rb - connect \en_o \rdpick_INT_rb_en_o - connect \i \rdpick_INT_rb_i - connect \o \rdpick_INT_rb_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43698$1150 + parameter \WIDTH 1 + connect \A \gpio_gpio3__core__oe + connect \B \io_bd [13] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43698$1150_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42134.17-42138.4" - cell \rdpick_INT_rc \rdpick_INT_rc - connect \en_o \rdpick_INT_rc_en_o - connect \i \rdpick_INT_rc_i - connect \o \rdpick_INT_rc_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43699$1151 + parameter \WIDTH 1 + connect \A \gpio_gpio4__pad__i + connect \B \io_bd [14] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43699$1151_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42139.19-42143.4" - cell \rdpick_SPR_spr1 \rdpick_SPR_spr1 - connect \en_o \rdpick_SPR_spr1_en_o - connect \i \rdpick_SPR_spr1_i - connect \o \rdpick_SPR_spr1_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43700$1152 + parameter \WIDTH 1 + connect \A \gpio_gpio4__core__o + connect \B \io_bd [15] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43700$1152_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42144.21-42148.4" - cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca - connect \en_o \rdpick_XER_xer_ca_en_o - connect \i \rdpick_XER_xer_ca_i - connect \o \rdpick_XER_xer_ca_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43701$1153 + parameter \WIDTH 1 + connect \A \gpio_gpio4__core__oe + connect \B \io_bd [16] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43701$1153_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42149.21-42153.4" - cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov - connect \en_o \rdpick_XER_xer_ov_en_o - connect \i \rdpick_XER_xer_ov_i - connect \o \rdpick_XER_xer_ov_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43702$1154 + parameter \WIDTH 1 + connect \A \gpio_gpio5__pad__i + connect \B \io_bd [17] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43702$1154_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42154.21-42158.4" - cell \rdpick_XER_xer_so \rdpick_XER_xer_so - connect \en_o \rdpick_XER_xer_so_en_o - connect \i \rdpick_XER_xer_so_i - connect \o \rdpick_XER_xer_so_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43703$1155 + parameter \WIDTH 1 + connect \A \gpio_gpio5__core__o + connect \B \io_bd [18] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43703$1155_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42159.7-42168.4" - cell \spr \spr - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \spr1__addr \spr_spr1__addr - connect \spr1__addr$1 \spr_spr1__addr$159 - connect \spr1__data_i \spr_spr1__data_i - connect \spr1__data_o \spr_spr1__data_o - connect \spr1__ren \spr_spr1__ren - connect \spr1__wen \spr_spr1__wen + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43705$1157 + parameter \WIDTH 1 + connect \A \gpio_gpio5__core__oe + connect \B \io_bd [19] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43705$1157_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42169.9-42182.4" - cell \state \state - connect \cia__data_o \cia__data_o - connect \cia__ren \cia__ren - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \data_i \data_i - connect \data_i$1 \state_data_i - connect \data_i$2 \state_data_i$158 - connect \msr__data_o \msr__data_o - connect \msr__ren \msr__ren - connect \state_nia_wen \state_nia_wen - connect \wen \wen - connect \wen$3 \state_wen + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43706$1158 + parameter \WIDTH 1 + connect \A \gpio_gpio6__pad__i + connect \B \io_bd [20] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43706$1158_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42183.18-42187.4" - cell \wrpick_CR_cr_a \wrpick_CR_cr_a - connect \en_o \wrpick_CR_cr_a_en_o - connect \i \wrpick_CR_cr_a_i - connect \o \wrpick_CR_cr_a_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43707$1159 + parameter \WIDTH 1 + connect \A \gpio_gpio6__core__o + connect \B \io_bd [21] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43707$1159_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42188.21-42192.4" - cell \wrpick_CR_full_cr \wrpick_CR_full_cr - connect \en_o \wrpick_CR_full_cr_en_o - connect \i \wrpick_CR_full_cr_i - connect \o \wrpick_CR_full_cr_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43708$1160 + parameter \WIDTH 1 + connect \A \gpio_gpio6__core__oe + connect \B \io_bd [22] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43708$1160_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42193.21-42197.4" - cell \wrpick_FAST_fast1 \wrpick_FAST_fast1 - connect \en_o \wrpick_FAST_fast1_en_o - connect \i \wrpick_FAST_fast1_i - connect \o \wrpick_FAST_fast1_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43709$1161 + parameter \WIDTH 1 + connect \A \gpio_gpio7__pad__i + connect \B \io_bd [23] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43709$1161_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42198.16-42202.4" - cell \wrpick_INT_o \wrpick_INT_o - connect \en_o \wrpick_INT_o_en_o - connect \i \wrpick_INT_o_i - connect \o \wrpick_INT_o_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43710$1162 + parameter \WIDTH 1 + connect \A \gpio_gpio7__core__o + connect \B \io_bd [24] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43710$1162_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42203.19-42207.4" - cell \wrpick_SPR_spr1 \wrpick_SPR_spr1 - connect \en_o \wrpick_SPR_spr1_en_o - connect \i \wrpick_SPR_spr1_i - connect \o \wrpick_SPR_spr1_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43711$1163 + parameter \WIDTH 1 + connect \A \gpio_gpio7__core__oe + connect \B \io_bd [25] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43711$1163_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42208.20-42212.4" - cell \wrpick_STATE_msr \wrpick_STATE_msr - connect \en_o \wrpick_STATE_msr_en_o - connect \i \wrpick_STATE_msr_i - connect \o \wrpick_STATE_msr_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:43712$1164 + parameter \WIDTH 1 + connect \A \gpio_gpio8__pad__i + connect \B \io_bd [26] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:43712$1164_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42213.20-42217.4" - cell \wrpick_STATE_nia \wrpick_STATE_nia - connect \en_o \wrpick_STATE_nia_en_o - connect \i \wrpick_STATE_nia_i - connect \o \wrpick_STATE_nia_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:43713$1165 + parameter \WIDTH 1 + connect \A \gpio_gpio8__core__o + connect \B \io_bd [27] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43713$1165_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42218.21-42222.4" - cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca - connect \en_o \wrpick_XER_xer_ca_en_o - connect \i \wrpick_XER_xer_ca_i - connect \o \wrpick_XER_xer_ca_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:43714$1166 + parameter \WIDTH 1 + connect \A \gpio_gpio8__core__oe + connect \B \io_bd [28] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:43714$1166_Y end attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42223.21-42227.4" - cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov - connect \en_o \wrpick_XER_xer_ov_en_o - connect \i \wrpick_XER_xer_ov_i - connect \o \wrpick_XER_xer_ov_o + attribute \src "libresoc.v:43775.8-43787.4" + cell \_fsm \_fsm + connect \TAP_bus__tck \TAP_bus__tck + connect \TAP_bus__tms \TAP_bus__tms + connect \capture \_fsm_capture + connect \isdr \_fsm_isdr + connect \isir \_fsm_isir + connect \negjtag_clk \negjtag_clk + connect \negjtag_rst \negjtag_rst + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \shift \_fsm_shift + connect \update \_fsm_update end attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42228.21-42232.4" - cell \wrpick_XER_xer_so \wrpick_XER_xer_so - connect \en_o \wrpick_XER_xer_so_en_o - connect \i \wrpick_XER_xer_so_i - connect \o \wrpick_XER_xer_so_o + attribute \src "libresoc.v:43788.12-43798.4" + cell \_idblock \_idblock + connect \TAP_bus__tdi \TAP_bus__tdi + connect \TAP_id_tdo \_idblock_TAP_id_tdo + connect \capture \_fsm_capture + connect \ir \_irblock_ir + connect \isdr \_fsm_isdr + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \shift \_fsm_shift + connect \update \_fsm_update end attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:42233.7-42250.4" - cell \xer \xer - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \data_i \xer_data_i - connect \data_i$1 \xer_data_i$154 - connect \data_i$3 \xer_data_i$156 - connect \full_rd__data_o \full_rd__data_o - connect \full_rd__ren \full_rd__ren - connect \src1__data_o \xer_src1__data_o - connect \src1__ren \xer_src1__ren - connect \src2__data_o \xer_src2__data_o - connect \src2__ren \xer_src2__ren - connect \src3__data_o \xer_src3__data_o - connect \src3__ren \xer_src3__ren - connect \wen \xer_wen - connect \wen$2 \xer_wen$155 - connect \wen$4 \xer_wen$157 - end - attribute \src "issuer_ls180.v:34906.7-34906.20" - process $proc$issuer_ls180.v:34906$2821 + attribute \src "libresoc.v:43799.12-43809.4" + cell \_irblock \_irblock + connect \TAP_bus__tdi \TAP_bus__tdi + connect \capture \_fsm_capture + connect \ir \_irblock_ir + connect \isir \_fsm_isir + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \shift \_fsm_shift + connect \tdo \_irblock_tdo + connect \update \_fsm_update + end + attribute \src "libresoc.v:42831.7-42831.20" + process $proc$libresoc.v:42831$1329 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "issuer_ls180.v:36924.7-36924.30" - process $proc$issuer_ls180.v:36924$2822 - assign { } { } - assign $1\core_terminate_o[0:0] 1'0 - sync always - sync init - update \core_terminate_o $1\core_terminate_o[0:0] - end - attribute \src "issuer_ls180.v:36937.13-36937.27" - process $proc$issuer_ls180.v:36937$2823 - assign { } { } - assign $1\counter[1:0] 2'00 - sync always - sync init - update \counter $1\counter[1:0] - end - attribute \src "issuer_ls180.v:38065.7-38065.34" - process $proc$issuer_ls180.v:38065$2824 - assign { } { } - assign $1\dp_CR_cr_a_branch0_1[0:0] 1'0 - sync always - sync init - update \dp_CR_cr_a_branch0_1 $1\dp_CR_cr_a_branch0_1[0:0] - end - attribute \src "issuer_ls180.v:38069.7-38069.30" - process $proc$issuer_ls180.v:38069$2825 - assign { } { } - assign $1\dp_CR_cr_a_cr0_0[0:0] 1'0 - sync always - sync init - update \dp_CR_cr_a_cr0_0 $1\dp_CR_cr_a_cr0_0[0:0] - end - attribute \src "issuer_ls180.v:38073.7-38073.30" - process $proc$issuer_ls180.v:38073$2826 - assign { } { } - assign $1\dp_CR_cr_b_cr0_0[0:0] 1'0 - sync always - sync init - update \dp_CR_cr_b_cr0_0 $1\dp_CR_cr_b_cr0_0[0:0] - end - attribute \src "issuer_ls180.v:38077.7-38077.30" - process $proc$issuer_ls180.v:38077$2827 - assign { } { } - assign $1\dp_CR_cr_c_cr0_0[0:0] 1'0 - sync always - sync init - update \dp_CR_cr_c_cr0_0 $1\dp_CR_cr_c_cr0_0[0:0] - end - attribute \src "issuer_ls180.v:38081.7-38081.33" - process $proc$issuer_ls180.v:38081$2828 - assign { } { } - assign $1\dp_CR_full_cr_cr0_0[0:0] 1'0 - sync always - sync init - update \dp_CR_full_cr_cr0_0 $1\dp_CR_full_cr_cr0_0[0:0] - end - attribute \src "issuer_ls180.v:38085.7-38085.37" - process $proc$issuer_ls180.v:38085$2829 - assign { } { } - assign $1\dp_FAST_fast1_branch0_0[0:0] 1'0 - sync always - sync init - update \dp_FAST_fast1_branch0_0 $1\dp_FAST_fast1_branch0_0[0:0] - end - attribute \src "issuer_ls180.v:38089.7-38089.34" - process $proc$issuer_ls180.v:38089$2830 - assign { } { } - assign $1\dp_FAST_fast1_spr0_2[0:0] 1'0 - sync always - sync init - update \dp_FAST_fast1_spr0_2 $1\dp_FAST_fast1_spr0_2[0:0] - end - attribute \src "issuer_ls180.v:38093.7-38093.35" - process $proc$issuer_ls180.v:38093$2831 - assign { } { } - assign $1\dp_FAST_fast1_trap0_1[0:0] 1'0 - sync always - sync init - update \dp_FAST_fast1_trap0_1 $1\dp_FAST_fast1_trap0_1[0:0] - end - attribute \src "issuer_ls180.v:38097.7-38097.37" - process $proc$issuer_ls180.v:38097$2832 - assign { } { } - assign $1\dp_FAST_fast2_branch0_0[0:0] 1'0 - sync always - sync init - update \dp_FAST_fast2_branch0_0 $1\dp_FAST_fast2_branch0_0[0:0] - end - attribute \src "issuer_ls180.v:38101.7-38101.35" - process $proc$issuer_ls180.v:38101$2833 - assign { } { } - assign $1\dp_FAST_fast2_trap0_1[0:0] 1'0 - sync always - sync init - update \dp_FAST_fast2_trap0_1 $1\dp_FAST_fast2_trap0_1[0:0] - end - attribute \src "issuer_ls180.v:38105.7-38105.30" - process $proc$issuer_ls180.v:38105$2834 - assign { } { } - assign $1\dp_INT_ra_alu0_0[0:0] 1'0 - sync always - sync init - update \dp_INT_ra_alu0_0 $1\dp_INT_ra_alu0_0[0:0] - end - attribute \src "issuer_ls180.v:38109.7-38109.29" - process $proc$issuer_ls180.v:38109$2835 - assign { } { } - assign $1\dp_INT_ra_cr0_1[0:0] 1'0 - sync always - sync init - update \dp_INT_ra_cr0_1 $1\dp_INT_ra_cr0_1[0:0] - end - attribute \src "issuer_ls180.v:38113.7-38113.30" - process $proc$issuer_ls180.v:38113$2836 - assign { } { } - assign $1\dp_INT_ra_div0_5[0:0] 1'0 - sync always - sync init - update \dp_INT_ra_div0_5 $1\dp_INT_ra_div0_5[0:0] - end - attribute \src "issuer_ls180.v:38117.7-38117.31" - process $proc$issuer_ls180.v:38117$2837 - assign { } { } - assign $1\dp_INT_ra_ldst0_8[0:0] 1'0 - sync always - sync init - update \dp_INT_ra_ldst0_8 $1\dp_INT_ra_ldst0_8[0:0] - end - attribute \src "issuer_ls180.v:38121.7-38121.34" - process $proc$issuer_ls180.v:38121$2838 - assign { } { } - assign $1\dp_INT_ra_logical0_3[0:0] 1'0 - sync always - sync init - update \dp_INT_ra_logical0_3 $1\dp_INT_ra_logical0_3[0:0] - end - attribute \src "issuer_ls180.v:38125.7-38125.30" - process $proc$issuer_ls180.v:38125$2839 - assign { } { } - assign $1\dp_INT_ra_mul0_6[0:0] 1'0 - sync always - sync init - update \dp_INT_ra_mul0_6 $1\dp_INT_ra_mul0_6[0:0] - end - attribute \src "issuer_ls180.v:38129.7-38129.35" - process $proc$issuer_ls180.v:38129$2840 - assign { } { } - assign $1\dp_INT_ra_shiftrot0_7[0:0] 1'0 - sync always - sync init - update \dp_INT_ra_shiftrot0_7 $1\dp_INT_ra_shiftrot0_7[0:0] - end - attribute \src "issuer_ls180.v:38133.7-38133.30" - process $proc$issuer_ls180.v:38133$2841 - assign { } { } - assign $1\dp_INT_ra_spr0_4[0:0] 1'0 - sync always - sync init - update \dp_INT_ra_spr0_4 $1\dp_INT_ra_spr0_4[0:0] - end - attribute \src "issuer_ls180.v:38137.7-38137.31" - process $proc$issuer_ls180.v:38137$2842 - assign { } { } - assign $1\dp_INT_ra_trap0_2[0:0] 1'0 - sync always - sync init - update \dp_INT_ra_trap0_2 $1\dp_INT_ra_trap0_2[0:0] - end - attribute \src "issuer_ls180.v:38141.7-38141.30" - process $proc$issuer_ls180.v:38141$2843 - assign { } { } - assign $1\dp_INT_rb_alu0_0[0:0] 1'0 - sync always - sync init - update \dp_INT_rb_alu0_0 $1\dp_INT_rb_alu0_0[0:0] - end - attribute \src "issuer_ls180.v:38145.7-38145.29" - process $proc$issuer_ls180.v:38145$2844 - assign { } { } - assign $1\dp_INT_rb_cr0_1[0:0] 1'0 - sync always - sync init - update \dp_INT_rb_cr0_1 $1\dp_INT_rb_cr0_1[0:0] - end - attribute \src "issuer_ls180.v:38149.7-38149.30" - process $proc$issuer_ls180.v:38149$2845 - assign { } { } - assign $1\dp_INT_rb_div0_4[0:0] 1'0 - sync always - sync init - update \dp_INT_rb_div0_4 $1\dp_INT_rb_div0_4[0:0] - end - attribute \src "issuer_ls180.v:38153.7-38153.31" - process $proc$issuer_ls180.v:38153$2846 - assign { } { } - assign $1\dp_INT_rb_ldst0_7[0:0] 1'0 - sync always - sync init - update \dp_INT_rb_ldst0_7 $1\dp_INT_rb_ldst0_7[0:0] - end - attribute \src "issuer_ls180.v:38157.7-38157.34" - process $proc$issuer_ls180.v:38157$2847 - assign { } { } - assign $1\dp_INT_rb_logical0_3[0:0] 1'0 - sync always - sync init - update \dp_INT_rb_logical0_3 $1\dp_INT_rb_logical0_3[0:0] - end - attribute \src "issuer_ls180.v:38161.7-38161.30" - process $proc$issuer_ls180.v:38161$2848 - assign { } { } - assign $1\dp_INT_rb_mul0_5[0:0] 1'0 - sync always - sync init - update \dp_INT_rb_mul0_5 $1\dp_INT_rb_mul0_5[0:0] - end - attribute \src "issuer_ls180.v:38165.7-38165.35" - process $proc$issuer_ls180.v:38165$2849 - assign { } { } - assign $1\dp_INT_rb_shiftrot0_6[0:0] 1'0 - sync always - sync init - update \dp_INT_rb_shiftrot0_6 $1\dp_INT_rb_shiftrot0_6[0:0] - end - attribute \src "issuer_ls180.v:38169.7-38169.31" - process $proc$issuer_ls180.v:38169$2850 - assign { } { } - assign $1\dp_INT_rb_trap0_2[0:0] 1'0 - sync always - sync init - update \dp_INT_rb_trap0_2 $1\dp_INT_rb_trap0_2[0:0] - end - attribute \src "issuer_ls180.v:38173.7-38173.31" - process $proc$issuer_ls180.v:38173$2851 - assign { } { } - assign $1\dp_INT_rc_ldst0_1[0:0] 1'0 - sync always - sync init - update \dp_INT_rc_ldst0_1 $1\dp_INT_rc_ldst0_1[0:0] - end - attribute \src "issuer_ls180.v:38177.7-38177.35" - process $proc$issuer_ls180.v:38177$2852 - assign { } { } - assign $1\dp_INT_rc_shiftrot0_0[0:0] 1'0 - sync always - sync init - update \dp_INT_rc_shiftrot0_0 $1\dp_INT_rc_shiftrot0_0[0:0] - end - attribute \src "issuer_ls180.v:38181.7-38181.32" - process $proc$issuer_ls180.v:38181$2853 - assign { } { } - assign $1\dp_SPR_spr1_spr0_0[0:0] 1'0 - sync always - sync init - update \dp_SPR_spr1_spr0_0 $1\dp_SPR_spr1_spr0_0[0:0] - end - attribute \src "issuer_ls180.v:38185.7-38185.34" - process $proc$issuer_ls180.v:38185$2854 - assign { } { } - assign $1\dp_XER_xer_ca_alu0_0[0:0] 1'0 - sync always - sync init - update \dp_XER_xer_ca_alu0_0 $1\dp_XER_xer_ca_alu0_0[0:0] - end - attribute \src "issuer_ls180.v:38189.7-38189.39" - process $proc$issuer_ls180.v:38189$2855 - assign { } { } - assign $1\dp_XER_xer_ca_shiftrot0_2[0:0] 1'0 - sync always - sync init - update \dp_XER_xer_ca_shiftrot0_2 $1\dp_XER_xer_ca_shiftrot0_2[0:0] - end - attribute \src "issuer_ls180.v:38193.7-38193.34" - process $proc$issuer_ls180.v:38193$2856 - assign { } { } - assign $1\dp_XER_xer_ca_spr0_1[0:0] 1'0 - sync always - sync init - update \dp_XER_xer_ca_spr0_1 $1\dp_XER_xer_ca_spr0_1[0:0] - end - attribute \src "issuer_ls180.v:38197.7-38197.34" - process $proc$issuer_ls180.v:38197$2857 - assign { } { } - assign $1\dp_XER_xer_ov_spr0_0[0:0] 1'0 - sync always - sync init - update \dp_XER_xer_ov_spr0_0 $1\dp_XER_xer_ov_spr0_0[0:0] - end - attribute \src "issuer_ls180.v:38201.7-38201.34" - process $proc$issuer_ls180.v:38201$2858 - assign { } { } - assign $1\dp_XER_xer_so_alu0_0[0:0] 1'0 - sync always - sync init - update \dp_XER_xer_so_alu0_0 $1\dp_XER_xer_so_alu0_0[0:0] - end - attribute \src "issuer_ls180.v:38205.7-38205.34" - process $proc$issuer_ls180.v:38205$2859 - assign { } { } - assign $1\dp_XER_xer_so_div0_3[0:0] 1'0 - sync always - sync init - update \dp_XER_xer_so_div0_3 $1\dp_XER_xer_so_div0_3[0:0] - end - attribute \src "issuer_ls180.v:38209.7-38209.38" - process $proc$issuer_ls180.v:38209$2860 - assign { } { } - assign $1\dp_XER_xer_so_logical0_1[0:0] 1'0 - sync always - sync init - update \dp_XER_xer_so_logical0_1 $1\dp_XER_xer_so_logical0_1[0:0] - end - attribute \src "issuer_ls180.v:38213.7-38213.34" - process $proc$issuer_ls180.v:38213$2861 - assign { } { } - assign $1\dp_XER_xer_so_mul0_4[0:0] 1'0 - sync always - sync init - update \dp_XER_xer_so_mul0_4 $1\dp_XER_xer_so_mul0_4[0:0] - end - attribute \src "issuer_ls180.v:38217.7-38217.39" - process $proc$issuer_ls180.v:38217$2862 - assign { } { } - assign $1\dp_XER_xer_so_shiftrot0_5[0:0] 1'0 - sync always - sync init - update \dp_XER_xer_so_shiftrot0_5 $1\dp_XER_xer_so_shiftrot0_5[0:0] - end - attribute \src "issuer_ls180.v:38221.7-38221.34" - process $proc$issuer_ls180.v:38221$2863 - assign { } { } - assign $1\dp_XER_xer_so_spr0_2[0:0] 1'0 - sync always - sync init - update \dp_XER_xer_so_spr0_2 $1\dp_XER_xer_so_spr0_2[0:0] - end - attribute \src "issuer_ls180.v:40278.7-40278.25" - process $proc$issuer_ls180.v:40278$2864 - assign { } { } - assign $1\wr_pick_dly[0:0] 1'0 - sync always - sync init - update \wr_pick_dly $1\wr_pick_dly[0:0] - end - attribute \src "issuer_ls180.v:40280.7-40280.32" - process $proc$issuer_ls180.v:40280$2865 - assign { } { } - assign $0\wr_pick_dly$1007[0:0]$2866 1'0 - sync always - sync init - update \wr_pick_dly$1007 $0\wr_pick_dly$1007[0:0]$2866 - end - attribute \src "issuer_ls180.v:40284.7-40284.32" - process $proc$issuer_ls180.v:40284$2867 - assign { } { } - assign $0\wr_pick_dly$1025[0:0]$2868 1'0 - sync always - sync init - update \wr_pick_dly$1025 $0\wr_pick_dly$1025[0:0]$2868 - end - attribute \src "issuer_ls180.v:40288.7-40288.32" - process $proc$issuer_ls180.v:40288$2869 - assign { } { } - assign $0\wr_pick_dly$1047[0:0]$2870 1'0 - sync always - sync init - update \wr_pick_dly$1047 $0\wr_pick_dly$1047[0:0]$2870 - end - attribute \src "issuer_ls180.v:40292.7-40292.32" - process $proc$issuer_ls180.v:40292$2871 - assign { } { } - assign $0\wr_pick_dly$1067[0:0]$2872 1'0 - sync always - sync init - update \wr_pick_dly$1067 $0\wr_pick_dly$1067[0:0]$2872 - end - attribute \src "issuer_ls180.v:40296.7-40296.32" - process $proc$issuer_ls180.v:40296$2873 - assign { } { } - assign $0\wr_pick_dly$1087[0:0]$2874 1'0 - sync always - sync init - update \wr_pick_dly$1087 $0\wr_pick_dly$1087[0:0]$2874 - end - attribute \src "issuer_ls180.v:40300.7-40300.32" - process $proc$issuer_ls180.v:40300$2875 - assign { } { } - assign $0\wr_pick_dly$1106[0:0]$2876 1'0 - sync always - sync init - update \wr_pick_dly$1106 $0\wr_pick_dly$1106[0:0]$2876 - end - attribute \src "issuer_ls180.v:40304.7-40304.32" - process $proc$issuer_ls180.v:40304$2877 + attribute \src "libresoc.v:43157.13-43157.31" + process $proc$libresoc.v:43157$1330 assign { } { } - assign $0\wr_pick_dly$1124[0:0]$2878 1'0 + assign $1\dmi0_addr_i[3:0] 4'0000 sync always sync init - update \wr_pick_dly$1124 $0\wr_pick_dly$1124[0:0]$2878 + update \dmi0_addr_i $1\dmi0_addr_i[3:0] end - attribute \src "issuer_ls180.v:40308.7-40308.32" - process $proc$issuer_ls180.v:40308$2879 + attribute \src "libresoc.v:43165.7-43165.29" + process $proc$libresoc.v:43165$1331 assign { } { } - assign $0\wr_pick_dly$1197[0:0]$2880 1'0 + assign $1\dmi0_addrsr__oe[0:0] 1'0 sync always sync init - update \wr_pick_dly$1197 $0\wr_pick_dly$1197[0:0]$2880 + update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0] end - attribute \src "issuer_ls180.v:40312.7-40312.32" - process $proc$issuer_ls180.v:40312$2881 + attribute \src "libresoc.v:43173.13-43173.36" + process $proc$libresoc.v:43173$1332 assign { } { } - assign $0\wr_pick_dly$1225[0:0]$2882 1'0 + assign $1\dmi0_addrsr_reg[7:0] 8'00000000 sync always sync init - update \wr_pick_dly$1225 $0\wr_pick_dly$1225[0:0]$2882 + update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0] end - attribute \src "issuer_ls180.v:40316.7-40316.32" - process $proc$issuer_ls180.v:40316$2883 + attribute \src "libresoc.v:43181.7-43181.37" + process $proc$libresoc.v:43181$1333 assign { } { } - assign $0\wr_pick_dly$1245[0:0]$2884 1'0 + assign $1\dmi0_addrsr_update_core[0:0] 1'0 sync always sync init - update \wr_pick_dly$1245 $0\wr_pick_dly$1245[0:0]$2884 + update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0] end - attribute \src "issuer_ls180.v:40320.7-40320.32" - process $proc$issuer_ls180.v:40320$2885 + attribute \src "libresoc.v:43185.7-43185.42" + process $proc$libresoc.v:43185$1334 assign { } { } - assign $0\wr_pick_dly$1265[0:0]$2886 1'0 + assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0 sync always sync init - update \wr_pick_dly$1265 $0\wr_pick_dly$1265[0:0]$2886 + update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0] end - attribute \src "issuer_ls180.v:40324.7-40324.32" - process $proc$issuer_ls180.v:40324$2887 + attribute \src "libresoc.v:43189.14-43189.51" + process $proc$libresoc.v:43189$1335 assign { } { } - assign $0\wr_pick_dly$1285[0:0]$2888 1'0 + assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \wr_pick_dly$1285 $0\wr_pick_dly$1285[0:0]$2888 + update \dmi0_datasr__i $1\dmi0_datasr__i[63:0] end - attribute \src "issuer_ls180.v:40328.7-40328.32" - process $proc$issuer_ls180.v:40328$2889 + attribute \src "libresoc.v:43195.13-43195.35" + process $proc$libresoc.v:43195$1336 assign { } { } - assign $0\wr_pick_dly$1305[0:0]$2890 1'0 + assign $1\dmi0_datasr__oe[1:0] 2'00 sync always sync init - update \wr_pick_dly$1305 $0\wr_pick_dly$1305[0:0]$2890 + update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0] end - attribute \src "issuer_ls180.v:40332.7-40332.32" - process $proc$issuer_ls180.v:40332$2891 + attribute \src "libresoc.v:43203.14-43203.52" + process $proc$libresoc.v:43203$1337 assign { } { } - assign $0\wr_pick_dly$1325[0:0]$2892 1'0 + assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \wr_pick_dly$1325 $0\wr_pick_dly$1325[0:0]$2892 + update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0] end - attribute \src "issuer_ls180.v:40336.7-40336.32" - process $proc$issuer_ls180.v:40336$2893 + attribute \src "libresoc.v:43211.7-43211.37" + process $proc$libresoc.v:43211$1338 assign { } { } - assign $0\wr_pick_dly$1372[0:0]$2894 1'0 + assign $1\dmi0_datasr_update_core[0:0] 1'0 sync always sync init - update \wr_pick_dly$1372 $0\wr_pick_dly$1372[0:0]$2894 + update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0] end - attribute \src "issuer_ls180.v:40340.7-40340.32" - process $proc$issuer_ls180.v:40340$2895 + attribute \src "libresoc.v:43215.7-43215.42" + process $proc$libresoc.v:43215$1339 assign { } { } - assign $0\wr_pick_dly$1388[0:0]$2896 1'0 + assign $1\dmi0_datasr_update_core_prev[0:0] 1'0 sync always sync init - update \wr_pick_dly$1388 $0\wr_pick_dly$1388[0:0]$2896 + update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0] end - attribute \src "issuer_ls180.v:40344.7-40344.32" - process $proc$issuer_ls180.v:40344$2897 + attribute \src "libresoc.v:43220.14-43220.45" + process $proc$libresoc.v:43220$1340 assign { } { } - assign $0\wr_pick_dly$1404[0:0]$2898 1'0 + assign $1\dmi0_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \wr_pick_dly$1404 $0\wr_pick_dly$1404[0:0]$2898 + update \dmi0_din $1\dmi0_din[63:0] end - attribute \src "issuer_ls180.v:40348.7-40348.32" - process $proc$issuer_ls180.v:40348$2899 + attribute \src "libresoc.v:43230.13-43230.29" + process $proc$libresoc.v:43230$1341 assign { } { } - assign $0\wr_pick_dly$1438[0:0]$2900 1'0 + assign $1\fsm_state[2:0] 3'000 sync always sync init - update \wr_pick_dly$1438 $0\wr_pick_dly$1438[0:0]$2900 + update \fsm_state $1\fsm_state[2:0] end - attribute \src "issuer_ls180.v:40352.7-40352.32" - process $proc$issuer_ls180.v:40352$2901 + attribute \src "libresoc.v:43232.13-43232.35" + process $proc$libresoc.v:43232$1342 assign { } { } - assign $0\wr_pick_dly$1454[0:0]$2902 1'0 + assign $0\fsm_state$275[2:0]$1343 3'000 sync always sync init - update \wr_pick_dly$1454 $0\wr_pick_dly$1454[0:0]$2902 + update \fsm_state$275 $0\fsm_state$275[2:0]$1343 end - attribute \src "issuer_ls180.v:40356.7-40356.32" - process $proc$issuer_ls180.v:40356$2903 + attribute \src "libresoc.v:43430.14-43430.39" + process $proc$libresoc.v:43430$1344 assign { } { } - assign $0\wr_pick_dly$1470[0:0]$2904 1'0 + assign $1\io_bd[49:0] 50'00000000000000000000000000000000000000000000000000 sync always sync init - update \wr_pick_dly$1470 $0\wr_pick_dly$1470[0:0]$2904 + update \io_bd $1\io_bd[49:0] end - attribute \src "issuer_ls180.v:40360.7-40360.32" - process $proc$issuer_ls180.v:40360$2905 + attribute \src "libresoc.v:43442.14-43442.39" + process $proc$libresoc.v:43442$1345 assign { } { } - assign $0\wr_pick_dly$1486[0:0]$2906 1'0 + assign $1\io_sr[49:0] 50'00000000000000000000000000000000000000000000000000 sync always sync init - update \wr_pick_dly$1486 $0\wr_pick_dly$1486[0:0]$2906 + update \io_sr $1\io_sr[49:0] end - attribute \src "issuer_ls180.v:40364.7-40364.32" - process $proc$issuer_ls180.v:40364$2907 + attribute \src "libresoc.v:43451.14-43451.41" + process $proc$libresoc.v:43451$1346 assign { } { } - assign $0\wr_pick_dly$1522[0:0]$2908 1'0 + assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000 sync always sync init - update \wr_pick_dly$1522 $0\wr_pick_dly$1522[0:0]$2908 + update \jtag_wb__adr $1\jtag_wb__adr[28:0] end - attribute \src "issuer_ls180.v:40368.7-40368.32" - process $proc$issuer_ls180.v:40368$2909 + attribute \src "libresoc.v:43460.14-43460.51" + process $proc$libresoc.v:43460$1347 assign { } { } - assign $0\wr_pick_dly$1538[0:0]$2910 1'0 + assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \wr_pick_dly$1538 $0\wr_pick_dly$1538[0:0]$2910 + update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0] end - attribute \src "issuer_ls180.v:40372.7-40372.32" - process $proc$issuer_ls180.v:40372$2911 + attribute \src "libresoc.v:43474.7-43474.32" + process $proc$libresoc.v:43474$1348 assign { } { } - assign $0\wr_pick_dly$1554[0:0]$2912 1'0 + assign $1\jtag_wb_addrsr__oe[0:0] 1'0 sync always sync init - update \wr_pick_dly$1554 $0\wr_pick_dly$1554[0:0]$2912 + update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0] end - attribute \src "issuer_ls180.v:40376.7-40376.32" - process $proc$issuer_ls180.v:40376$2913 + attribute \src "libresoc.v:43482.14-43482.47" + process $proc$libresoc.v:43482$1349 assign { } { } - assign $0\wr_pick_dly$1570[0:0]$2914 1'0 + assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000 sync always sync init - update \wr_pick_dly$1570 $0\wr_pick_dly$1570[0:0]$2914 + update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0] end - attribute \src "issuer_ls180.v:40380.7-40380.32" - process $proc$issuer_ls180.v:40380$2915 + attribute \src "libresoc.v:43490.7-43490.40" + process $proc$libresoc.v:43490$1350 assign { } { } - assign $0\wr_pick_dly$1612[0:0]$2916 1'0 + assign $1\jtag_wb_addrsr_update_core[0:0] 1'0 sync always sync init - update \wr_pick_dly$1612 $0\wr_pick_dly$1612[0:0]$2916 + update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0] end - attribute \src "issuer_ls180.v:40384.7-40384.32" - process $proc$issuer_ls180.v:40384$2917 + attribute \src "libresoc.v:43494.7-43494.45" + process $proc$libresoc.v:43494$1351 assign { } { } - assign $0\wr_pick_dly$1631[0:0]$2918 1'0 + assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0 sync always sync init - update \wr_pick_dly$1631 $0\wr_pick_dly$1631[0:0]$2918 + update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0] end - attribute \src "issuer_ls180.v:40388.7-40388.32" - process $proc$issuer_ls180.v:40388$2919 + attribute \src "libresoc.v:43498.14-43498.54" + process $proc$libresoc.v:43498$1352 assign { } { } - assign $0\wr_pick_dly$1647[0:0]$2920 1'0 + assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \wr_pick_dly$1647 $0\wr_pick_dly$1647[0:0]$2920 + update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0] end - attribute \src "issuer_ls180.v:40392.7-40392.32" - process $proc$issuer_ls180.v:40392$2921 + attribute \src "libresoc.v:43504.13-43504.38" + process $proc$libresoc.v:43504$1353 assign { } { } - assign $0\wr_pick_dly$1663[0:0]$2922 1'0 + assign $1\jtag_wb_datasr__oe[1:0] 2'00 sync always sync init - update \wr_pick_dly$1663 $0\wr_pick_dly$1663[0:0]$2922 + update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0] end - attribute \src "issuer_ls180.v:40396.7-40396.32" - process $proc$issuer_ls180.v:40396$2923 + attribute \src "libresoc.v:43512.14-43512.55" + process $proc$libresoc.v:43512$1354 assign { } { } - assign $0\wr_pick_dly$1679[0:0]$2924 1'0 + assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \wr_pick_dly$1679 $0\wr_pick_dly$1679[0:0]$2924 + update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0] end - attribute \src "issuer_ls180.v:40400.7-40400.32" - process $proc$issuer_ls180.v:40400$2925 + attribute \src "libresoc.v:43520.7-43520.40" + process $proc$libresoc.v:43520$1355 assign { } { } - assign $0\wr_pick_dly$1723[0:0]$2926 1'0 + assign $1\jtag_wb_datasr_update_core[0:0] 1'0 sync always sync init - update \wr_pick_dly$1723 $0\wr_pick_dly$1723[0:0]$2926 + update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0] end - attribute \src "issuer_ls180.v:40404.7-40404.32" - process $proc$issuer_ls180.v:40404$2927 + attribute \src "libresoc.v:43524.7-43524.45" + process $proc$libresoc.v:43524$1356 assign { } { } - assign $0\wr_pick_dly$1739[0:0]$2928 1'0 + assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0 sync always sync init - update \wr_pick_dly$1739 $0\wr_pick_dly$1739[0:0]$2928 + update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0] end - attribute \src "issuer_ls180.v:40408.7-40408.32" - process $proc$issuer_ls180.v:40408$2929 + attribute \src "libresoc.v:43542.7-43542.21" + process $proc$libresoc.v:43542$1357 assign { } { } - assign $0\wr_pick_dly$1763[0:0]$2930 1'0 + assign $1\sr0__oe[0:0] 1'0 sync always sync init - update \wr_pick_dly$1763 $0\wr_pick_dly$1763[0:0]$2930 + update \sr0__oe $1\sr0__oe[0:0] end - attribute \src "issuer_ls180.v:40412.7-40412.32" - process $proc$issuer_ls180.v:40412$2931 + attribute \src "libresoc.v:43550.13-43550.27" + process $proc$libresoc.v:43550$1358 assign { } { } - assign $0\wr_pick_dly$1783[0:0]$2932 1'0 + assign $1\sr0_reg[2:0] 3'000 sync always sync init - update \wr_pick_dly$1783 $0\wr_pick_dly$1783[0:0]$2932 + update \sr0_reg $1\sr0_reg[2:0] end - attribute \src "issuer_ls180.v:40416.7-40416.31" - process $proc$issuer_ls180.v:40416$2933 + attribute \src "libresoc.v:43558.7-43558.29" + process $proc$libresoc.v:43558$1359 assign { } { } - assign $0\wr_pick_dly$967[0:0]$2934 1'0 + assign $1\sr0_update_core[0:0] 1'0 sync always sync init - update \wr_pick_dly$967 $0\wr_pick_dly$967[0:0]$2934 + update \sr0_update_core $1\sr0_update_core[0:0] end - attribute \src "issuer_ls180.v:40420.7-40420.31" - process $proc$issuer_ls180.v:40420$2935 + attribute \src "libresoc.v:43562.7-43562.34" + process $proc$libresoc.v:43562$1360 assign { } { } - assign $0\wr_pick_dly$986[0:0]$2936 1'0 + assign $1\sr0_update_core_prev[0:0] 1'0 sync always sync init - update \wr_pick_dly$986 $0\wr_pick_dly$986[0:0]$2936 - end - attribute \src "issuer_ls180.v:41382.3-41383.51" - process $proc$issuer_ls180.v:41382$2161 - assign { } { } - assign $0\wr_pick_dly$1783[0:0]$2162 \wr_pick_dly$1783$next - sync posedge \coresync_clk - update \wr_pick_dly$1783 $0\wr_pick_dly$1783[0:0]$2162 - end - attribute \src "issuer_ls180.v:41384.3-41385.51" - process $proc$issuer_ls180.v:41384$2163 - assign { } { } - assign $0\wr_pick_dly$1763[0:0]$2164 \wr_pick_dly$1763$next - sync posedge \coresync_clk - update \wr_pick_dly$1763 $0\wr_pick_dly$1763[0:0]$2164 - end - attribute \src "issuer_ls180.v:41386.3-41387.51" - process $proc$issuer_ls180.v:41386$2165 - assign { } { } - assign $0\wr_pick_dly$1739[0:0]$2166 \wr_pick_dly$1739$next - sync posedge \coresync_clk - update \wr_pick_dly$1739 $0\wr_pick_dly$1739[0:0]$2166 - end - attribute \src "issuer_ls180.v:41388.3-41389.51" - process $proc$issuer_ls180.v:41388$2167 - assign { } { } - assign $0\wr_pick_dly$1723[0:0]$2168 \wr_pick_dly$1723$next - sync posedge \coresync_clk - update \wr_pick_dly$1723 $0\wr_pick_dly$1723[0:0]$2168 - end - attribute \src "issuer_ls180.v:41390.3-41391.51" - process $proc$issuer_ls180.v:41390$2169 - assign { } { } - assign $0\wr_pick_dly$1679[0:0]$2170 \wr_pick_dly$1679$next - sync posedge \coresync_clk - update \wr_pick_dly$1679 $0\wr_pick_dly$1679[0:0]$2170 - end - attribute \src "issuer_ls180.v:41392.3-41393.51" - process $proc$issuer_ls180.v:41392$2171 - assign { } { } - assign $0\wr_pick_dly$1663[0:0]$2172 \wr_pick_dly$1663$next - sync posedge \coresync_clk - update \wr_pick_dly$1663 $0\wr_pick_dly$1663[0:0]$2172 - end - attribute \src "issuer_ls180.v:41394.3-41395.51" - process $proc$issuer_ls180.v:41394$2173 - assign { } { } - assign $0\wr_pick_dly$1647[0:0]$2174 \wr_pick_dly$1647$next - sync posedge \coresync_clk - update \wr_pick_dly$1647 $0\wr_pick_dly$1647[0:0]$2174 - end - attribute \src "issuer_ls180.v:41396.3-41397.51" - process $proc$issuer_ls180.v:41396$2175 - assign { } { } - assign $0\wr_pick_dly$1631[0:0]$2176 \wr_pick_dly$1631$next - sync posedge \coresync_clk - update \wr_pick_dly$1631 $0\wr_pick_dly$1631[0:0]$2176 - end - attribute \src "issuer_ls180.v:41398.3-41399.51" - process $proc$issuer_ls180.v:41398$2177 - assign { } { } - assign $0\wr_pick_dly$1612[0:0]$2178 \wr_pick_dly$1612$next - sync posedge \coresync_clk - update \wr_pick_dly$1612 $0\wr_pick_dly$1612[0:0]$2178 - end - attribute \src "issuer_ls180.v:41400.3-41401.51" - process $proc$issuer_ls180.v:41400$2179 - assign { } { } - assign $0\wr_pick_dly$1570[0:0]$2180 \wr_pick_dly$1570$next - sync posedge \coresync_clk - update \wr_pick_dly$1570 $0\wr_pick_dly$1570[0:0]$2180 - end - attribute \src "issuer_ls180.v:41402.3-41403.51" - process $proc$issuer_ls180.v:41402$2181 - assign { } { } - assign $0\wr_pick_dly$1554[0:0]$2182 \wr_pick_dly$1554$next - sync posedge \coresync_clk - update \wr_pick_dly$1554 $0\wr_pick_dly$1554[0:0]$2182 - end - attribute \src "issuer_ls180.v:41404.3-41405.51" - process $proc$issuer_ls180.v:41404$2183 - assign { } { } - assign $0\wr_pick_dly$1538[0:0]$2184 \wr_pick_dly$1538$next - sync posedge \coresync_clk - update \wr_pick_dly$1538 $0\wr_pick_dly$1538[0:0]$2184 - end - attribute \src "issuer_ls180.v:41406.3-41407.51" - process $proc$issuer_ls180.v:41406$2185 - assign { } { } - assign $0\wr_pick_dly$1522[0:0]$2186 \wr_pick_dly$1522$next - sync posedge \coresync_clk - update \wr_pick_dly$1522 $0\wr_pick_dly$1522[0:0]$2186 - end - attribute \src "issuer_ls180.v:41408.3-41409.51" - process $proc$issuer_ls180.v:41408$2187 - assign { } { } - assign $0\wr_pick_dly$1486[0:0]$2188 \wr_pick_dly$1486$next - sync posedge \coresync_clk - update \wr_pick_dly$1486 $0\wr_pick_dly$1486[0:0]$2188 - end - attribute \src "issuer_ls180.v:41410.3-41411.51" - process $proc$issuer_ls180.v:41410$2189 - assign { } { } - assign $0\wr_pick_dly$1470[0:0]$2190 \wr_pick_dly$1470$next - sync posedge \coresync_clk - update \wr_pick_dly$1470 $0\wr_pick_dly$1470[0:0]$2190 - end - attribute \src "issuer_ls180.v:41412.3-41413.51" - process $proc$issuer_ls180.v:41412$2191 - assign { } { } - assign $0\wr_pick_dly$1454[0:0]$2192 \wr_pick_dly$1454$next - sync posedge \coresync_clk - update \wr_pick_dly$1454 $0\wr_pick_dly$1454[0:0]$2192 - end - attribute \src "issuer_ls180.v:41414.3-41415.51" - process $proc$issuer_ls180.v:41414$2193 - assign { } { } - assign $0\wr_pick_dly$1438[0:0]$2194 \wr_pick_dly$1438$next - sync posedge \coresync_clk - update \wr_pick_dly$1438 $0\wr_pick_dly$1438[0:0]$2194 - end - attribute \src "issuer_ls180.v:41416.3-41417.51" - process $proc$issuer_ls180.v:41416$2195 - assign { } { } - assign $0\wr_pick_dly$1404[0:0]$2196 \wr_pick_dly$1404$next - sync posedge \coresync_clk - update \wr_pick_dly$1404 $0\wr_pick_dly$1404[0:0]$2196 - end - attribute \src "issuer_ls180.v:41418.3-41419.51" - process $proc$issuer_ls180.v:41418$2197 - assign { } { } - assign $0\wr_pick_dly$1388[0:0]$2198 \wr_pick_dly$1388$next - sync posedge \coresync_clk - update \wr_pick_dly$1388 $0\wr_pick_dly$1388[0:0]$2198 - end - attribute \src "issuer_ls180.v:41420.3-41421.51" - process $proc$issuer_ls180.v:41420$2199 - assign { } { } - assign $0\wr_pick_dly$1372[0:0]$2200 \wr_pick_dly$1372$next - sync posedge \coresync_clk - update \wr_pick_dly$1372 $0\wr_pick_dly$1372[0:0]$2200 - end - attribute \src "issuer_ls180.v:41422.3-41423.51" - process $proc$issuer_ls180.v:41422$2201 - assign { } { } - assign $0\wr_pick_dly$1325[0:0]$2202 \wr_pick_dly$1325$next - sync posedge \coresync_clk - update \wr_pick_dly$1325 $0\wr_pick_dly$1325[0:0]$2202 - end - attribute \src "issuer_ls180.v:41424.3-41425.51" - process $proc$issuer_ls180.v:41424$2203 - assign { } { } - assign $0\wr_pick_dly$1305[0:0]$2204 \wr_pick_dly$1305$next - sync posedge \coresync_clk - update \wr_pick_dly$1305 $0\wr_pick_dly$1305[0:0]$2204 - end - attribute \src "issuer_ls180.v:41426.3-41427.51" - process $proc$issuer_ls180.v:41426$2205 - assign { } { } - assign $0\wr_pick_dly$1285[0:0]$2206 \wr_pick_dly$1285$next - sync posedge \coresync_clk - update \wr_pick_dly$1285 $0\wr_pick_dly$1285[0:0]$2206 - end - attribute \src "issuer_ls180.v:41428.3-41429.51" - process $proc$issuer_ls180.v:41428$2207 - assign { } { } - assign $0\wr_pick_dly$1265[0:0]$2208 \wr_pick_dly$1265$next - sync posedge \coresync_clk - update \wr_pick_dly$1265 $0\wr_pick_dly$1265[0:0]$2208 - end - attribute \src "issuer_ls180.v:41430.3-41431.51" - process $proc$issuer_ls180.v:41430$2209 - assign { } { } - assign $0\wr_pick_dly$1245[0:0]$2210 \wr_pick_dly$1245$next - sync posedge \coresync_clk - update \wr_pick_dly$1245 $0\wr_pick_dly$1245[0:0]$2210 - end - attribute \src "issuer_ls180.v:41432.3-41433.51" - process $proc$issuer_ls180.v:41432$2211 - assign { } { } - assign $0\wr_pick_dly$1225[0:0]$2212 \wr_pick_dly$1225$next - sync posedge \coresync_clk - update \wr_pick_dly$1225 $0\wr_pick_dly$1225[0:0]$2212 - end - attribute \src "issuer_ls180.v:41434.3-41435.51" - process $proc$issuer_ls180.v:41434$2213 - assign { } { } - assign $0\wr_pick_dly$1197[0:0]$2214 \wr_pick_dly$1197$next - sync posedge \coresync_clk - update \wr_pick_dly$1197 $0\wr_pick_dly$1197[0:0]$2214 - end - attribute \src "issuer_ls180.v:41436.3-41437.51" - process $proc$issuer_ls180.v:41436$2215 - assign { } { } - assign $0\wr_pick_dly$1124[0:0]$2216 \wr_pick_dly$1124$next - sync posedge \coresync_clk - update \wr_pick_dly$1124 $0\wr_pick_dly$1124[0:0]$2216 - end - attribute \src "issuer_ls180.v:41438.3-41439.51" - process $proc$issuer_ls180.v:41438$2217 - assign { } { } - assign $0\wr_pick_dly$1106[0:0]$2218 \wr_pick_dly$1106$next - sync posedge \coresync_clk - update \wr_pick_dly$1106 $0\wr_pick_dly$1106[0:0]$2218 - end - attribute \src "issuer_ls180.v:41440.3-41441.51" - process $proc$issuer_ls180.v:41440$2219 - assign { } { } - assign $0\wr_pick_dly$1087[0:0]$2220 \wr_pick_dly$1087$next - sync posedge \coresync_clk - update \wr_pick_dly$1087 $0\wr_pick_dly$1087[0:0]$2220 - end - attribute \src "issuer_ls180.v:41442.3-41443.51" - process $proc$issuer_ls180.v:41442$2221 - assign { } { } - assign $0\wr_pick_dly$1067[0:0]$2222 \wr_pick_dly$1067$next - sync posedge \coresync_clk - update \wr_pick_dly$1067 $0\wr_pick_dly$1067[0:0]$2222 - end - attribute \src "issuer_ls180.v:41444.3-41445.51" - process $proc$issuer_ls180.v:41444$2223 - assign { } { } - assign $0\wr_pick_dly$1047[0:0]$2224 \wr_pick_dly$1047$next - sync posedge \coresync_clk - update \wr_pick_dly$1047 $0\wr_pick_dly$1047[0:0]$2224 - end - attribute \src "issuer_ls180.v:41446.3-41447.51" - process $proc$issuer_ls180.v:41446$2225 - assign { } { } - assign $0\wr_pick_dly$1025[0:0]$2226 \wr_pick_dly$1025$next - sync posedge \coresync_clk - update \wr_pick_dly$1025 $0\wr_pick_dly$1025[0:0]$2226 - end - attribute \src "issuer_ls180.v:41448.3-41449.51" - process $proc$issuer_ls180.v:41448$2227 - assign { } { } - assign $0\wr_pick_dly$1007[0:0]$2228 \wr_pick_dly$1007$next - sync posedge \coresync_clk - update \wr_pick_dly$1007 $0\wr_pick_dly$1007[0:0]$2228 - end - attribute \src "issuer_ls180.v:41450.3-41451.49" - process $proc$issuer_ls180.v:41450$2229 - assign { } { } - assign $0\wr_pick_dly$986[0:0]$2230 \wr_pick_dly$986$next - sync posedge \coresync_clk - update \wr_pick_dly$986 $0\wr_pick_dly$986[0:0]$2230 - end - attribute \src "issuer_ls180.v:41452.3-41453.49" - process $proc$issuer_ls180.v:41452$2231 - assign { } { } - assign $0\wr_pick_dly$967[0:0]$2232 \wr_pick_dly$967$next - sync posedge \coresync_clk - update \wr_pick_dly$967 $0\wr_pick_dly$967[0:0]$2232 - end - attribute \src "issuer_ls180.v:41454.3-41455.39" - process $proc$issuer_ls180.v:41454$2233 - assign { } { } - assign $0\wr_pick_dly[0:0] \wr_pick_dly$next - sync posedge \coresync_clk - update \wr_pick_dly $0\wr_pick_dly[0:0] - end - attribute \src "issuer_ls180.v:41456.3-41457.53" - process $proc$issuer_ls180.v:41456$2234 - assign { } { } - assign $0\dp_SPR_spr1_spr0_0[0:0] \dp_SPR_spr1_spr0_0$next - sync posedge \coresync_clk - update \dp_SPR_spr1_spr0_0 $0\dp_SPR_spr1_spr0_0[0:0] - end - attribute \src "issuer_ls180.v:41458.3-41459.59" - process $proc$issuer_ls180.v:41458$2235 - assign { } { } - assign $0\dp_FAST_fast2_trap0_1[0:0] \dp_FAST_fast2_trap0_1$next - sync posedge \coresync_clk - update \dp_FAST_fast2_trap0_1 $0\dp_FAST_fast2_trap0_1[0:0] - end - attribute \src "issuer_ls180.v:41460.3-41461.63" - process $proc$issuer_ls180.v:41460$2236 - assign { } { } - assign $0\dp_FAST_fast2_branch0_0[0:0] \dp_FAST_fast2_branch0_0$next - sync posedge \coresync_clk - update \dp_FAST_fast2_branch0_0 $0\dp_FAST_fast2_branch0_0[0:0] - end - attribute \src "issuer_ls180.v:41462.3-41463.57" - process $proc$issuer_ls180.v:41462$2237 - assign { } { } - assign $0\dp_FAST_fast1_spr0_2[0:0] \dp_FAST_fast1_spr0_2$next - sync posedge \coresync_clk - update \dp_FAST_fast1_spr0_2 $0\dp_FAST_fast1_spr0_2[0:0] - end - attribute \src "issuer_ls180.v:41464.3-41465.59" - process $proc$issuer_ls180.v:41464$2238 - assign { } { } - assign $0\dp_FAST_fast1_trap0_1[0:0] \dp_FAST_fast1_trap0_1$next - sync posedge \coresync_clk - update \dp_FAST_fast1_trap0_1 $0\dp_FAST_fast1_trap0_1[0:0] - end - attribute \src "issuer_ls180.v:41466.3-41467.63" - process $proc$issuer_ls180.v:41466$2239 - assign { } { } - assign $0\dp_FAST_fast1_branch0_0[0:0] \dp_FAST_fast1_branch0_0$next - sync posedge \coresync_clk - update \dp_FAST_fast1_branch0_0 $0\dp_FAST_fast1_branch0_0[0:0] - end - attribute \src "issuer_ls180.v:41468.3-41469.49" - process $proc$issuer_ls180.v:41468$2240 - assign { } { } - assign $0\dp_CR_cr_c_cr0_0[0:0] \dp_CR_cr_c_cr0_0$next - sync posedge \coresync_clk - update \dp_CR_cr_c_cr0_0 $0\dp_CR_cr_c_cr0_0[0:0] - end - attribute \src "issuer_ls180.v:41470.3-41471.49" - process $proc$issuer_ls180.v:41470$2241 - assign { } { } - assign $0\dp_CR_cr_b_cr0_0[0:0] \dp_CR_cr_b_cr0_0$next - sync posedge \coresync_clk - update \dp_CR_cr_b_cr0_0 $0\dp_CR_cr_b_cr0_0[0:0] - end - attribute \src "issuer_ls180.v:41472.3-41473.57" - process $proc$issuer_ls180.v:41472$2242 - assign { } { } - assign $0\dp_CR_cr_a_branch0_1[0:0] \dp_CR_cr_a_branch0_1$next - sync posedge \coresync_clk - update \dp_CR_cr_a_branch0_1 $0\dp_CR_cr_a_branch0_1[0:0] - end - attribute \src "issuer_ls180.v:41474.3-41475.49" - process $proc$issuer_ls180.v:41474$2243 - assign { } { } - assign $0\dp_CR_cr_a_cr0_0[0:0] \dp_CR_cr_a_cr0_0$next - sync posedge \coresync_clk - update \dp_CR_cr_a_cr0_0 $0\dp_CR_cr_a_cr0_0[0:0] + update \sr0_update_core_prev $1\sr0_update_core_prev[0:0] end - attribute \src "issuer_ls180.v:41476.3-41477.55" - process $proc$issuer_ls180.v:41476$2244 + attribute \src "libresoc.v:43715.3-43716.45" + process $proc$libresoc.v:43715$1167 assign { } { } - assign $0\dp_CR_full_cr_cr0_0[0:0] \dp_CR_full_cr_cr0_0$next - sync posedge \coresync_clk - update \dp_CR_full_cr_cr0_0 $0\dp_CR_full_cr_cr0_0[0:0] - end - attribute \src "issuer_ls180.v:41478.3-41479.57" - process $proc$issuer_ls180.v:41478$2245 - assign { } { } - assign $0\dp_XER_xer_ov_spr0_0[0:0] \dp_XER_xer_ov_spr0_0$next - sync posedge \coresync_clk - update \dp_XER_xer_ov_spr0_0 $0\dp_XER_xer_ov_spr0_0[0:0] - end - attribute \src "issuer_ls180.v:41480.3-41481.67" - process $proc$issuer_ls180.v:41480$2246 - assign { } { } - assign $0\dp_XER_xer_ca_shiftrot0_2[0:0] \dp_XER_xer_ca_shiftrot0_2$next - sync posedge \coresync_clk - update \dp_XER_xer_ca_shiftrot0_2 $0\dp_XER_xer_ca_shiftrot0_2[0:0] + assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next + sync posedge \clk + update \dmi0_datasr__i $0\dmi0_datasr__i[63:0] end - attribute \src "issuer_ls180.v:41482.3-41483.57" - process $proc$issuer_ls180.v:41482$2247 + attribute \src "libresoc.v:43717.3-43718.33" + process $proc$libresoc.v:43717$1168 assign { } { } - assign $0\dp_XER_xer_ca_spr0_1[0:0] \dp_XER_xer_ca_spr0_1$next - sync posedge \coresync_clk - update \dp_XER_xer_ca_spr0_1 $0\dp_XER_xer_ca_spr0_1[0:0] + assign $0\dmi0_din[63:0] \dmi0_din$next + sync posedge \clk + update \dmi0_din $0\dmi0_din[63:0] end - attribute \src "issuer_ls180.v:41484.3-41485.57" - process $proc$issuer_ls180.v:41484$2248 + attribute \src "libresoc.v:43719.3-43720.45" + process $proc$libresoc.v:43719$1169 assign { } { } - assign $0\dp_XER_xer_ca_alu0_0[0:0] \dp_XER_xer_ca_alu0_0$next - sync posedge \coresync_clk - update \dp_XER_xer_ca_alu0_0 $0\dp_XER_xer_ca_alu0_0[0:0] + assign $0\fsm_state$275[2:0]$1170 \fsm_state$275$next + sync posedge \clk + update \fsm_state$275 $0\fsm_state$275[2:0]$1170 end - attribute \src "issuer_ls180.v:41486.3-41487.67" - process $proc$issuer_ls180.v:41486$2249 + attribute \src "libresoc.v:43721.3-43722.39" + process $proc$libresoc.v:43721$1171 assign { } { } - assign $0\dp_XER_xer_so_shiftrot0_5[0:0] \dp_XER_xer_so_shiftrot0_5$next - sync posedge \coresync_clk - update \dp_XER_xer_so_shiftrot0_5 $0\dp_XER_xer_so_shiftrot0_5[0:0] + assign $0\dmi0_addr_i[3:0] \dmi0_addr_i$next + sync posedge \clk + update \dmi0_addr_i $0\dmi0_addr_i[3:0] end - attribute \src "issuer_ls180.v:41488.3-41489.57" - process $proc$issuer_ls180.v:41488$2250 + attribute \src "libresoc.v:43723.3-43724.51" + process $proc$libresoc.v:43723$1172 assign { } { } - assign $0\dp_XER_xer_so_mul0_4[0:0] \dp_XER_xer_so_mul0_4$next - sync posedge \coresync_clk - update \dp_XER_xer_so_mul0_4 $0\dp_XER_xer_so_mul0_4[0:0] + assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next + sync posedge \clk + update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0] end - attribute \src "issuer_ls180.v:41490.3-41491.57" - process $proc$issuer_ls180.v:41490$2251 + attribute \src "libresoc.v:43725.3-43726.45" + process $proc$libresoc.v:43725$1173 assign { } { } - assign $0\dp_XER_xer_so_div0_3[0:0] \dp_XER_xer_so_div0_3$next - sync posedge \coresync_clk - update \dp_XER_xer_so_div0_3 $0\dp_XER_xer_so_div0_3[0:0] + assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next + sync posedge \clk + update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0] end - attribute \src "issuer_ls180.v:41492.3-41493.57" - process $proc$issuer_ls180.v:41492$2252 + attribute \src "libresoc.v:43727.3-43728.35" + process $proc$libresoc.v:43727$1174 assign { } { } - assign $0\dp_XER_xer_so_spr0_2[0:0] \dp_XER_xer_so_spr0_2$next - sync posedge \coresync_clk - update \dp_XER_xer_so_spr0_2 $0\dp_XER_xer_so_spr0_2[0:0] + assign $0\fsm_state[2:0] \fsm_state$next + sync posedge \clk + update \fsm_state $0\fsm_state[2:0] end - attribute \src "issuer_ls180.v:41494.3-41495.65" - process $proc$issuer_ls180.v:41494$2253 + attribute \src "libresoc.v:43729.3-43730.41" + process $proc$libresoc.v:43729$1175 assign { } { } - assign $0\dp_XER_xer_so_logical0_1[0:0] \dp_XER_xer_so_logical0_1$next - sync posedge \coresync_clk - update \dp_XER_xer_so_logical0_1 $0\dp_XER_xer_so_logical0_1[0:0] + assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next + sync posedge \clk + update \jtag_wb__adr $0\jtag_wb__adr[28:0] end - attribute \src "issuer_ls180.v:41496.3-41497.57" - process $proc$issuer_ls180.v:41496$2254 + attribute \src "libresoc.v:43731.3-43732.47" + process $proc$libresoc.v:43731$1176 assign { } { } - assign $0\dp_XER_xer_so_alu0_0[0:0] \dp_XER_xer_so_alu0_0$next - sync posedge \coresync_clk - update \dp_XER_xer_so_alu0_0 $0\dp_XER_xer_so_alu0_0[0:0] + assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next + sync posedge \posjtag_clk + update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0] end - attribute \src "issuer_ls180.v:41498.3-41499.51" - process $proc$issuer_ls180.v:41498$2255 + attribute \src "libresoc.v:43733.3-43734.47" + process $proc$libresoc.v:43733$1177 assign { } { } - assign $0\dp_INT_rc_ldst0_1[0:0] \dp_INT_rc_ldst0_1$next - sync posedge \coresync_clk - update \dp_INT_rc_ldst0_1 $0\dp_INT_rc_ldst0_1[0:0] + assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next + sync posedge \clk + update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0] end - attribute \src "issuer_ls180.v:41500.3-41501.59" - process $proc$issuer_ls180.v:41500$2256 + attribute \src "libresoc.v:43735.3-43736.73" + process $proc$libresoc.v:43735$1178 assign { } { } - assign $0\dp_INT_rc_shiftrot0_0[0:0] \dp_INT_rc_shiftrot0_0$next - sync posedge \coresync_clk - update \dp_INT_rc_shiftrot0_0 $0\dp_INT_rc_shiftrot0_0[0:0] + assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next + sync posedge \clk + update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0] end - attribute \src "issuer_ls180.v:41502.3-41503.51" - process $proc$issuer_ls180.v:41502$2257 + attribute \src "libresoc.v:43737.3-43738.63" + process $proc$libresoc.v:43737$1179 assign { } { } - assign $0\dp_INT_rb_ldst0_7[0:0] \dp_INT_rb_ldst0_7$next - sync posedge \coresync_clk - update \dp_INT_rb_ldst0_7 $0\dp_INT_rb_ldst0_7[0:0] + assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next + sync posedge \clk + update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0] end - attribute \src "issuer_ls180.v:41504.3-41505.59" - process $proc$issuer_ls180.v:41504$2258 + attribute \src "libresoc.v:43739.3-43740.47" + process $proc$libresoc.v:43739$1180 assign { } { } - assign $0\dp_INT_rb_shiftrot0_6[0:0] \dp_INT_rb_shiftrot0_6$next - sync posedge \coresync_clk - update \dp_INT_rb_shiftrot0_6 $0\dp_INT_rb_shiftrot0_6[0:0] + assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next + sync posedge \posjtag_clk + update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0] end - attribute \src "issuer_ls180.v:41506.3-41507.49" - process $proc$issuer_ls180.v:41506$2259 + attribute \src "libresoc.v:43741.3-43742.47" + process $proc$libresoc.v:43741$1181 assign { } { } - assign $0\dp_INT_rb_mul0_5[0:0] \dp_INT_rb_mul0_5$next - sync posedge \coresync_clk - update \dp_INT_rb_mul0_5 $0\dp_INT_rb_mul0_5[0:0] + assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next + sync posedge \clk + update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0] end - attribute \src "issuer_ls180.v:41508.3-41509.49" - process $proc$issuer_ls180.v:41508$2260 + attribute \src "libresoc.v:43743.3-43744.73" + process $proc$libresoc.v:43743$1182 assign { } { } - assign $0\dp_INT_rb_div0_4[0:0] \dp_INT_rb_div0_4$next - sync posedge \coresync_clk - update \dp_INT_rb_div0_4 $0\dp_INT_rb_div0_4[0:0] + assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next + sync posedge \clk + update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0] end - attribute \src "issuer_ls180.v:41510.3-41511.57" - process $proc$issuer_ls180.v:41510$2261 + attribute \src "libresoc.v:43745.3-43746.63" + process $proc$libresoc.v:43745$1183 assign { } { } - assign $0\dp_INT_rb_logical0_3[0:0] \dp_INT_rb_logical0_3$next - sync posedge \coresync_clk - update \dp_INT_rb_logical0_3 $0\dp_INT_rb_logical0_3[0:0] + assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next + sync posedge \clk + update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0] end - attribute \src "issuer_ls180.v:41512.3-41513.51" - process $proc$issuer_ls180.v:41512$2262 + attribute \src "libresoc.v:43747.3-43748.53" + process $proc$libresoc.v:43747$1184 assign { } { } - assign $0\dp_INT_rb_trap0_2[0:0] \dp_INT_rb_trap0_2$next - sync posedge \coresync_clk - update \dp_INT_rb_trap0_2 $0\dp_INT_rb_trap0_2[0:0] + assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next + sync posedge \posjtag_clk + update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0] end - attribute \src "issuer_ls180.v:41514.3-41515.47" - process $proc$issuer_ls180.v:41514$2263 + attribute \src "libresoc.v:43749.3-43750.53" + process $proc$libresoc.v:43749$1185 assign { } { } - assign $0\dp_INT_rb_cr0_1[0:0] \dp_INT_rb_cr0_1$next - sync posedge \coresync_clk - update \dp_INT_rb_cr0_1 $0\dp_INT_rb_cr0_1[0:0] + assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next + sync posedge \clk + update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0] end - attribute \src "issuer_ls180.v:41516.3-41517.49" - process $proc$issuer_ls180.v:41516$2264 + attribute \src "libresoc.v:43751.3-43752.79" + process $proc$libresoc.v:43751$1186 assign { } { } - assign $0\dp_INT_rb_alu0_0[0:0] \dp_INT_rb_alu0_0$next - sync posedge \coresync_clk - update \dp_INT_rb_alu0_0 $0\dp_INT_rb_alu0_0[0:0] + assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next + sync posedge \clk + update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0] end - attribute \src "issuer_ls180.v:41518.3-41519.51" - process $proc$issuer_ls180.v:41518$2265 + attribute \src "libresoc.v:43753.3-43754.69" + process $proc$libresoc.v:43753$1187 assign { } { } - assign $0\dp_INT_ra_ldst0_8[0:0] \dp_INT_ra_ldst0_8$next - sync posedge \coresync_clk - update \dp_INT_ra_ldst0_8 $0\dp_INT_ra_ldst0_8[0:0] + assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next + sync posedge \clk + update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0] end - attribute \src "issuer_ls180.v:41520.3-41521.59" - process $proc$issuer_ls180.v:41520$2266 + attribute \src "libresoc.v:43755.3-43756.53" + process $proc$libresoc.v:43755$1188 assign { } { } - assign $0\dp_INT_ra_shiftrot0_7[0:0] \dp_INT_ra_shiftrot0_7$next - sync posedge \coresync_clk - update \dp_INT_ra_shiftrot0_7 $0\dp_INT_ra_shiftrot0_7[0:0] + assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next + sync posedge \posjtag_clk + update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0] end - attribute \src "issuer_ls180.v:41522.3-41523.49" - process $proc$issuer_ls180.v:41522$2267 + attribute \src "libresoc.v:43757.3-43758.53" + process $proc$libresoc.v:43757$1189 assign { } { } - assign $0\dp_INT_ra_mul0_6[0:0] \dp_INT_ra_mul0_6$next - sync posedge \coresync_clk - update \dp_INT_ra_mul0_6 $0\dp_INT_ra_mul0_6[0:0] + assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next + sync posedge \clk + update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0] end - attribute \src "issuer_ls180.v:41524.3-41525.49" - process $proc$issuer_ls180.v:41524$2268 + attribute \src "libresoc.v:43759.3-43760.79" + process $proc$libresoc.v:43759$1190 assign { } { } - assign $0\dp_INT_ra_div0_5[0:0] \dp_INT_ra_div0_5$next - sync posedge \coresync_clk - update \dp_INT_ra_div0_5 $0\dp_INT_ra_div0_5[0:0] + assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next + sync posedge \clk + update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0] end - attribute \src "issuer_ls180.v:41526.3-41527.49" - process $proc$issuer_ls180.v:41526$2269 + attribute \src "libresoc.v:43761.3-43762.69" + process $proc$libresoc.v:43761$1191 assign { } { } - assign $0\dp_INT_ra_spr0_4[0:0] \dp_INT_ra_spr0_4$next - sync posedge \coresync_clk - update \dp_INT_ra_spr0_4 $0\dp_INT_ra_spr0_4[0:0] + assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next + sync posedge \clk + update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0] end - attribute \src "issuer_ls180.v:41528.3-41529.57" - process $proc$issuer_ls180.v:41528$2270 + attribute \src "libresoc.v:43763.3-43764.31" + process $proc$libresoc.v:43763$1192 assign { } { } - assign $0\dp_INT_ra_logical0_3[0:0] \dp_INT_ra_logical0_3$next - sync posedge \coresync_clk - update \dp_INT_ra_logical0_3 $0\dp_INT_ra_logical0_3[0:0] + assign $0\sr0_reg[2:0] \sr0_reg$next + sync posedge \posjtag_clk + update \sr0_reg $0\sr0_reg[2:0] end - attribute \src "issuer_ls180.v:41530.3-41531.51" - process $proc$issuer_ls180.v:41530$2271 + attribute \src "libresoc.v:43765.3-43766.31" + process $proc$libresoc.v:43765$1193 assign { } { } - assign $0\dp_INT_ra_trap0_2[0:0] \dp_INT_ra_trap0_2$next - sync posedge \coresync_clk - update \dp_INT_ra_trap0_2 $0\dp_INT_ra_trap0_2[0:0] + assign $0\sr0__oe[0:0] \sr0__oe$next + sync posedge \clk + update \sr0__oe $0\sr0__oe[0:0] end - attribute \src "issuer_ls180.v:41532.3-41533.47" - process $proc$issuer_ls180.v:41532$2272 + attribute \src "libresoc.v:43767.3-43768.57" + process $proc$libresoc.v:43767$1194 assign { } { } - assign $0\dp_INT_ra_cr0_1[0:0] \dp_INT_ra_cr0_1$next - sync posedge \coresync_clk - update \dp_INT_ra_cr0_1 $0\dp_INT_ra_cr0_1[0:0] + assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next + sync posedge \clk + update \sr0_update_core_prev $0\sr0_update_core_prev[0:0] end - attribute \src "issuer_ls180.v:41534.3-41535.49" - process $proc$issuer_ls180.v:41534$2273 + attribute \src "libresoc.v:43769.3-43770.47" + process $proc$libresoc.v:43769$1195 assign { } { } - assign $0\dp_INT_ra_alu0_0[0:0] \dp_INT_ra_alu0_0$next - sync posedge \coresync_clk - update \dp_INT_ra_alu0_0 $0\dp_INT_ra_alu0_0[0:0] + assign $0\sr0_update_core[0:0] \sr0_update_core$next + sync posedge \clk + update \sr0_update_core $0\sr0_update_core[0:0] end - attribute \src "issuer_ls180.v:41536.3-41537.49" - process $proc$issuer_ls180.v:41536$2274 + attribute \src "libresoc.v:43771.3-43772.27" + process $proc$libresoc.v:43771$1196 assign { } { } - assign $0\core_terminate_o[0:0] \core_terminate_o$next - sync posedge \coresync_clk - update \core_terminate_o $0\core_terminate_o[0:0] + assign $0\io_bd[49:0] \io_bd$next + sync negedge \negjtag_clk + update \io_bd $0\io_bd[49:0] end - attribute \src "issuer_ls180.v:41538.3-41539.31" - process $proc$issuer_ls180.v:41538$2275 + attribute \src "libresoc.v:43773.3-43774.27" + process $proc$libresoc.v:43773$1197 assign { } { } - assign $0\counter[1:0] \counter$next - sync posedge \coresync_clk - update \counter $0\counter[1:0] + assign $0\io_sr[49:0] \io_sr$next + sync posedge \posjtag_clk + update \io_sr $0\io_sr[49:0] end - attribute \src "issuer_ls180.v:42251.3-42279.6" - process $proc$issuer_ls180.v:42251$2276 + attribute \src "libresoc.v:43810.3-43818.6" + process $proc$libresoc.v:43810$1198 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_spr0__is_32bit[0:0] $1\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "issuer_ls180.v:42252.5-42252.29" + assign $0\dmi0_datasr_update_core_prev$next[0:0]$1199 $1\dmi0_datasr_update_core_prev$next[0:0]$1200 + attribute \src "libresoc.v:43811.5-43811.29" switch \initial - attribute \src "issuer_ls180.v:42252.9-42252.17" + attribute \src "libresoc.v:43811.9-43811.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] $2\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] $3\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [5] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] \dec_SPR_SPR_SPR__is_32bit - case - assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 - end - end + assign $1\dmi0_datasr_update_core_prev$next[0:0]$1200 1'0 case - assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + assign $1\dmi0_datasr_update_core_prev$next[0:0]$1200 \dmi0_datasr_update_core end sync always - update \fus_oper_i_alu_spr0__is_32bit $0\fus_oper_i_alu_spr0__is_32bit[0:0] + update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$1199 end - attribute \src "issuer_ls180.v:42280.3-42308.6" - process $proc$issuer_ls180.v:42280$2277 + attribute \src "libresoc.v:43819.3-43835.6" + process $proc$libresoc.v:43819$1201 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$16[0:0]$2278 $1\fus_cu_issue_i$16[0:0]$2279 - attribute \src "issuer_ls180.v:42281.5-42281.29" + assign $0\dmi0_datasr__oe$next[1:0]$1202 $2\dmi0_datasr__oe$next[1:0]$1204 + attribute \src "libresoc.v:43820.5-43820.29" switch \initial - attribute \src "issuer_ls180.v:42281.9-42281.17" + attribute \src "libresoc.v:43820.9-43820.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + switch \$253 + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$16[0:0]$2279 $2\fus_cu_issue_i$16[0:0]$2280 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_issue_i$16[0:0]$2280 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_issue_i$16[0:0]$2280 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_issue_i$16[0:0]$2280 $3\fus_cu_issue_i$16[0:0]$2281 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [5] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_issue_i$16[0:0]$2281 \issue_i - case - assign $3\fus_cu_issue_i$16[0:0]$2281 1'0 - end - end + assign $1\dmi0_datasr__oe$next[1:0]$1203 \dmi0_datasr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dmi0_datasr__oe$next[1:0]$1203 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_datasr__oe$next[1:0]$1204 2'00 case - assign $1\fus_cu_issue_i$16[0:0]$2279 1'0 + assign $2\dmi0_datasr__oe$next[1:0]$1204 $1\dmi0_datasr__oe$next[1:0]$1203 end sync always - update \fus_cu_issue_i$16 $0\fus_cu_issue_i$16[0:0]$2278 + update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$1202 end - attribute \src "issuer_ls180.v:42309.3-42337.6" - process $proc$issuer_ls180.v:42309$2282 + attribute \src "libresoc.v:43836.3-43856.6" + process $proc$libresoc.v:43836$1205 + assign { } { } + assign { } { } assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$18[5:0]$2283 $1\fus_cu_rdmaskn_i$18[5:0]$2284 - attribute \src "issuer_ls180.v:42310.5-42310.29" + assign $0\dmi0_datasr_reg$next[63:0]$1206 $3\dmi0_datasr_reg$next[63:0]$1209 + attribute \src "libresoc.v:43837.5-43837.29" switch \initial - attribute \src "issuer_ls180.v:42310.9-42310.17" + attribute \src "libresoc.v:43837.9-43837.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" + switch \dmi0_datasr_shift + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$18[5:0]$2284 $2\fus_cu_rdmaskn_i$18[5:0]$2285 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_rdmaskn_i$18[5:0]$2285 6'000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_rdmaskn_i$18[5:0]$2285 6'000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_rdmaskn_i$18[5:0]$2285 $3\fus_cu_rdmaskn_i$18[5:0]$2286 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [5] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_rdmaskn_i$18[5:0]$2286 \$249 - case - assign $3\fus_cu_rdmaskn_i$18[5:0]$2286 6'000000 - end - end + assign $1\dmi0_datasr_reg$next[63:0]$1207 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } case - assign $1\fus_cu_rdmaskn_i$18[5:0]$2284 6'000000 + assign $1\dmi0_datasr_reg$next[63:0]$1207 \dmi0_datasr_reg end - sync always - update \fus_cu_rdmaskn_i$18 $0\fus_cu_rdmaskn_i$18[5:0]$2283 - end - attribute \src "issuer_ls180.v:42338.3-42366.6" - process $proc$issuer_ls180.v:42338$2287 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_div0__insn_type[6:0] $1\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "issuer_ls180.v:42339.5-42339.29" - switch \initial - attribute \src "issuer_ls180.v:42339.9-42339.17" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" + switch \dmi0_datasr_capture + attribute \src "libresoc.v:0.0-0.0" case 1'1 + assign { } { } + assign $2\dmi0_datasr_reg$next[63:0]$1208 \dmi0_datasr__i case + assign $2\dmi0_datasr_reg$next[63:0]$1208 $1\dmi0_datasr_reg$next[63:0]$1207 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_div0__insn_type[6:0] $2\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_div0__insn_type[6:0] $3\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [6] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_div0__insn_type[6:0] \dec_DIV_DIV_DIV__insn_type - case - assign $3\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 - end - end + assign $3\dmi0_datasr_reg$next[63:0]$1209 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 + assign $3\dmi0_datasr_reg$next[63:0]$1209 $2\dmi0_datasr_reg$next[63:0]$1208 end sync always - update \fus_oper_i_alu_div0__insn_type $0\fus_oper_i_alu_div0__insn_type[6:0] + update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$1206 end - attribute \src "issuer_ls180.v:42367.3-42395.6" - process $proc$issuer_ls180.v:42367$2288 - assign { } { } + attribute \src "libresoc.v:43857.3-43880.6" + process $proc$libresoc.v:43857$1210 assign { } { } - assign $0\fus_oper_i_alu_div0__fn_unit[11:0] $1\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "issuer_ls180.v:42368.5-42368.29" + assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:43858.5-43858.29" switch \initial - attribute \src "issuer_ls180.v:42368.9-42368.17" + attribute \src "libresoc.v:43858.9-43858.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:571" + switch { \dmi0_datasr_shift \dmi0_addrsr_shift \jtag_wb_datasr_shift \jtag_wb_addrsr_shift \sr0_shift } + attribute \src "libresoc.v:0.0-0.0" + case 5'----1 assign { } { } - assign $1\fus_oper_i_alu_div0__fn_unit[11:0] $2\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_div0__fn_unit[11:0] $3\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [6] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_div0__fn_unit[11:0] \dec_DIV_DIV_DIV__fn_unit - case - assign $3\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 - end - end + assign $1\TAP_bus__tdo[0:0] \sr0_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 5'---1- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \jtag_wb_addrsr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 5'--1-- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \jtag_wb_datasr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 5'-1--- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \dmi0_addrsr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 5'1---- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \dmi0_datasr_reg [0] + attribute \src "libresoc.v:0.0-0.0" case - assign $1\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 + assign { } { } + assign $1\TAP_bus__tdo[0:0] \TAP_tdo end sync always - update \fus_oper_i_alu_div0__fn_unit $0\fus_oper_i_alu_div0__fn_unit[11:0] + update \TAP_bus__tdo $0\TAP_bus__tdo[0:0] end - attribute \src "issuer_ls180.v:42396.3-42425.6" - process $proc$issuer_ls180.v:42396$2289 - assign { } { } + attribute \src "libresoc.v:43881.3-43913.6" + process $proc$libresoc.v:43881$1211 assign { } { } assign { } { } assign { } { } - assign $0\fus_oper_i_alu_div0__imm_data__data[63:0] $1\fus_oper_i_alu_div0__imm_data__data[63:0] - assign $0\fus_oper_i_alu_div0__imm_data__ok[0:0] $1\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:42397.5-42397.29" + assign $0\jtag_wb__adr$next[28:0]$1212 $4\jtag_wb__adr$next[28:0]$1216 + attribute \src "libresoc.v:43882.5-43882.29" switch \initial - attribute \src "issuer_ls180.v:42397.9-42397.17" + attribute \src "libresoc.v:43882.9-43882.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 assign { } { } - assign $1\fus_oper_i_alu_div0__imm_data__data[63:0] $2\fus_oper_i_alu_div0__imm_data__data[63:0] - assign $1\fus_oper_i_alu_div0__imm_data__ok[0:0] $2\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\jtag_wb__adr$next[28:0]$1213 $2\jtag_wb__adr$next[28:0]$1214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:196" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 assign { } { } + assign $2\jtag_wb__adr$next[28:0]$1214 \jtag_wb_addrsr__o + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- assign { } { } - assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] $3\fus_oper_i_alu_div0__imm_data__data[63:0] - assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] $3\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [6] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_div0__imm_data__ok[0:0] $3\fus_oper_i_alu_div0__imm_data__data[63:0] } { \dec_DIV_DIV_DIV__imm_data__ok \dec_DIV_DIV_DIV__imm_data__data } - case - assign $3\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 - end + assign $2\jtag_wb__adr$next[28:0]$1214 \$267 [28:0] + case + assign $2\jtag_wb__adr$next[28:0]$1214 \jtag_wb__adr + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\jtag_wb__adr$next[28:0]$1213 $3\jtag_wb__adr$next[28:0]$1215 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:224" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb__adr$next[28:0]$1215 \$270 [28:0] + case + assign $3\jtag_wb__adr$next[28:0]$1215 \jtag_wb__adr end case - assign $1\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 + assign $1\jtag_wb__adr$next[28:0]$1213 \jtag_wb__adr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\jtag_wb__adr$next[28:0]$1216 29'00000000000000000000000000000 + case + assign $4\jtag_wb__adr$next[28:0]$1216 $1\jtag_wb__adr$next[28:0]$1213 end sync always - update \fus_oper_i_alu_div0__imm_data__data $0\fus_oper_i_alu_div0__imm_data__data[63:0] - update \fus_oper_i_alu_div0__imm_data__ok $0\fus_oper_i_alu_div0__imm_data__ok[0:0] + update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$1212 end - attribute \src "issuer_ls180.v:42426.3-42455.6" - process $proc$issuer_ls180.v:42426$2290 - assign { } { } + attribute \src "libresoc.v:43914.3-43966.6" + process $proc$libresoc.v:43914$1217 assign { } { } assign { } { } assign { } { } - assign $0\fus_oper_i_alu_div0__rc__ok[0:0] $1\fus_oper_i_alu_div0__rc__ok[0:0] - assign $0\fus_oper_i_alu_div0__rc__rc[0:0] $1\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "issuer_ls180.v:42427.5-42427.29" + assign $0\fsm_state$next[2:0]$1218 $5\fsm_state$next[2:0]$1223 + attribute \src "libresoc.v:43915.5-43915.29" switch \initial - attribute \src "issuer_ls180.v:42427.9-42427.17" + attribute \src "libresoc.v:43915.9-43915.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 assign { } { } - assign $1\fus_oper_i_alu_div0__rc__ok[0:0] $2\fus_oper_i_alu_div0__rc__ok[0:0] - assign $1\fus_oper_i_alu_div0__rc__rc[0:0] $2\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" + assign $1\fsm_state$next[2:0]$1219 $2\fsm_state$next[2:0]$1220 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:196" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\fsm_state$next[2:0]$1220 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\fsm_state$next[2:0]$1220 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\fsm_state$next[2:0]$1220 3'010 case + assign $2\fsm_state$next[2:0]$1220 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\fsm_state$next[2:0]$1219 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\fsm_state$next[2:0]$1219 $3\fsm_state$next[2:0]$1221 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:213" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } + assign $3\fsm_state$next[2:0]$1221 3'000 + case + assign $3\fsm_state$next[2:0]$1221 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\fsm_state$next[2:0]$1219 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\fsm_state$next[2:0]$1219 $4\fsm_state$next[2:0]$1222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:224" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $2\fus_oper_i_alu_div0__rc__ok[0:0] $3\fus_oper_i_alu_div0__rc__ok[0:0] - assign $2\fus_oper_i_alu_div0__rc__rc[0:0] $3\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [6] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_div0__rc__ok[0:0] $3\fus_oper_i_alu_div0__rc__rc[0:0] } { \dec_DIV_DIV_DIV__rc__ok \dec_DIV_DIV_DIV__rc__rc } - case - assign $3\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 - assign $3\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 - end + assign $4\fsm_state$next[2:0]$1222 3'001 + case + assign $4\fsm_state$next[2:0]$1222 \fsm_state end case - assign $1\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 - assign $1\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 + assign $1\fsm_state$next[2:0]$1219 \fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[2:0]$1223 3'000 + case + assign $5\fsm_state$next[2:0]$1223 $1\fsm_state$next[2:0]$1219 end sync always - update \fus_oper_i_alu_div0__rc__ok $0\fus_oper_i_alu_div0__rc__ok[0:0] - update \fus_oper_i_alu_div0__rc__rc $0\fus_oper_i_alu_div0__rc__rc[0:0] + update \fsm_state$next $0\fsm_state$next[2:0]$1218 end - attribute \src "issuer_ls180.v:42456.3-42485.6" - process $proc$issuer_ls180.v:42456$2291 - assign { } { } + attribute \src "libresoc.v:43967.3-43993.6" + process $proc$libresoc.v:43967$1224 assign { } { } assign { } { } assign { } { } - assign $0\fus_oper_i_alu_div0__oe__oe[0:0] $1\fus_oper_i_alu_div0__oe__oe[0:0] - assign $0\fus_oper_i_alu_div0__oe__ok[0:0] $1\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "issuer_ls180.v:42457.5-42457.29" + assign $0\jtag_wb__dat_w$next[63:0]$1225 $3\jtag_wb__dat_w$next[63:0]$1228 + attribute \src "libresoc.v:43968.5-43968.29" switch \initial - attribute \src "issuer_ls180.v:42457.9-42457.17" + attribute \src "libresoc.v:43968.9-43968.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 assign { } { } - assign $1\fus_oper_i_alu_div0__oe__oe[0:0] $2\fus_oper_i_alu_div0__oe__oe[0:0] - assign $1\fus_oper_i_alu_div0__oe__ok[0:0] $2\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } + assign $1\jtag_wb__dat_w$next[63:0]$1226 $2\jtag_wb__dat_w$next[63:0]$1227 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:196" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $2\jtag_wb__dat_w$next[63:0]$1227 \jtag_wb__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $2\jtag_wb__dat_w$next[63:0]$1227 \jtag_wb__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- assign { } { } - assign $2\fus_oper_i_alu_div0__oe__oe[0:0] $3\fus_oper_i_alu_div0__oe__oe[0:0] - assign $2\fus_oper_i_alu_div0__oe__ok[0:0] $3\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [6] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_div0__oe__ok[0:0] $3\fus_oper_i_alu_div0__oe__oe[0:0] } { \dec_DIV_DIV_DIV__oe__ok \dec_DIV_DIV_DIV__oe__oe } - case - assign $3\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 - assign $3\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 - end + assign $2\jtag_wb__dat_w$next[63:0]$1227 \jtag_wb_datasr__o + case + assign $2\jtag_wb__dat_w$next[63:0]$1227 \jtag_wb__dat_w end case - assign $1\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 - assign $1\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 + assign $1\jtag_wb__dat_w$next[63:0]$1226 \jtag_wb__dat_w + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb__dat_w$next[63:0]$1228 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb__dat_w$next[63:0]$1228 $1\jtag_wb__dat_w$next[63:0]$1226 end sync always - update \fus_oper_i_alu_div0__oe__oe $0\fus_oper_i_alu_div0__oe__oe[0:0] - update \fus_oper_i_alu_div0__oe__ok $0\fus_oper_i_alu_div0__oe__ok[0:0] + update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$1225 end - attribute \src "issuer_ls180.v:42486.3-42514.6" - process $proc$issuer_ls180.v:42486$2292 + attribute \src "libresoc.v:43994.3-44014.6" + process $proc$libresoc.v:43994$1229 + assign { } { } assign { } { } assign { } { } - assign $0\fus_oper_i_alu_div0__invert_in[0:0] $1\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "issuer_ls180.v:42487.5-42487.29" + assign $0\jtag_wb_datasr__i$next[63:0]$1230 $3\jtag_wb_datasr__i$next[63:0]$1233 + attribute \src "libresoc.v:43995.5-43995.29" switch \initial - attribute \src "issuer_ls180.v:42487.9-42487.17" + attribute \src "libresoc.v:43995.9-43995.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'011 assign { } { } - assign $1\fus_oper_i_alu_div0__invert_in[0:0] $2\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__invert_in[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__invert_in[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\jtag_wb_datasr__i$next[63:0]$1231 $2\jtag_wb_datasr__i$next[63:0]$1232 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:213" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $2\fus_oper_i_alu_div0__invert_in[0:0] $3\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [6] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_div0__invert_in[0:0] \dec_DIV_DIV_DIV__invert_in - case - assign $3\fus_oper_i_alu_div0__invert_in[0:0] 1'0 - end + assign $2\jtag_wb_datasr__i$next[63:0]$1232 \jtag_wb__dat_r + case + assign $2\jtag_wb_datasr__i$next[63:0]$1232 \jtag_wb_datasr__i end case - assign $1\fus_oper_i_alu_div0__invert_in[0:0] 1'0 + assign $1\jtag_wb_datasr__i$next[63:0]$1231 \jtag_wb_datasr__i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_datasr__i$next[63:0]$1233 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb_datasr__i$next[63:0]$1233 $1\jtag_wb_datasr__i$next[63:0]$1231 end sync always - update \fus_oper_i_alu_div0__invert_in $0\fus_oper_i_alu_div0__invert_in[0:0] + update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$1230 end - attribute \src "issuer_ls180.v:42515.3-42543.6" - process $proc$issuer_ls180.v:42515$2293 + attribute \src "libresoc.v:44015.3-44047.6" + process $proc$libresoc.v:44015$1234 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_div0__zero_a[0:0] $1\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "issuer_ls180.v:42516.5-42516.29" + assign { } { } + assign $0\dmi0_addr_i$next[3:0]$1235 $4\dmi0_addr_i$next[3:0]$1239 + attribute \src "libresoc.v:44016.5-44016.29" switch \initial - attribute \src "issuer_ls180.v:42516.9-42516.17" + attribute \src "libresoc.v:44016.9-44016.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" + switch \fsm_state$275 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 assign { } { } - assign $1\fus_oper_i_alu_div0__zero_a[0:0] $2\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__zero_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__zero_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" + assign $1\dmi0_addr_i$next[3:0]$1236 $2\dmi0_addr_i$next[3:0]$1237 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:148" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\dmi0_addr_i$next[3:0]$1237 \dmi0_addrsr__o [3:0] + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\dmi0_addr_i$next[3:0]$1237 \$284 [3:0] case + assign $2\dmi0_addr_i$next[3:0]$1237 \dmi0_addr_i + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\dmi0_addr_i$next[3:0]$1236 $3\dmi0_addr_i$next[3:0]$1238 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:176" + switch \dmi0_ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $2\fus_oper_i_alu_div0__zero_a[0:0] $3\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [6] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_div0__zero_a[0:0] \dec_DIV_DIV_DIV__zero_a - case - assign $3\fus_oper_i_alu_div0__zero_a[0:0] 1'0 - end + assign $3\dmi0_addr_i$next[3:0]$1238 \$287 [3:0] + case + assign $3\dmi0_addr_i$next[3:0]$1238 \dmi0_addr_i end case - assign $1\fus_oper_i_alu_div0__zero_a[0:0] 1'0 + assign $1\dmi0_addr_i$next[3:0]$1236 \dmi0_addr_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\dmi0_addr_i$next[3:0]$1239 4'0000 + case + assign $4\dmi0_addr_i$next[3:0]$1239 $1\dmi0_addr_i$next[3:0]$1236 end sync always - update \fus_oper_i_alu_div0__zero_a $0\fus_oper_i_alu_div0__zero_a[0:0] + update \dmi0_addr_i$next $0\dmi0_addr_i$next[3:0]$1235 end - attribute \src "issuer_ls180.v:42544.3-42572.6" - process $proc$issuer_ls180.v:42544$2294 + attribute \src "libresoc.v:44048.3-44100.6" + process $proc$libresoc.v:44048$1240 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_div0__input_carry[1:0] $1\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "issuer_ls180.v:42545.5-42545.29" + assign { } { } + assign $0\fsm_state$275$next[2:0]$1241 $5\fsm_state$275$next[2:0]$1246 + attribute \src "libresoc.v:44049.5-44049.29" switch \initial - attribute \src "issuer_ls180.v:42545.9-42545.17" + attribute \src "libresoc.v:44049.9-44049.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" + switch \fsm_state$275 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\fsm_state$275$next[2:0]$1242 $2\fsm_state$275$next[2:0]$1243 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:148" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\fsm_state$275$next[2:0]$1243 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\fsm_state$275$next[2:0]$1243 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\fsm_state$275$next[2:0]$1243 3'010 + case + assign $2\fsm_state$275$next[2:0]$1243 \fsm_state$275 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\fsm_state$275$next[2:0]$1242 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 assign { } { } - assign $1\fus_oper_i_alu_div0__input_carry[1:0] $2\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__input_carry[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__input_carry[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" + assign $1\fsm_state$275$next[2:0]$1242 $3\fsm_state$275$next[2:0]$1244 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:165" + switch \dmi0_ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$275$next[2:0]$1244 3'000 case + assign $3\fsm_state$275$next[2:0]$1244 \fsm_state$275 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\fsm_state$275$next[2:0]$1242 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\fsm_state$275$next[2:0]$1242 $4\fsm_state$275$next[2:0]$1245 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:176" + switch \dmi0_ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $2\fus_oper_i_alu_div0__input_carry[1:0] $3\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [6] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_div0__input_carry[1:0] \dec_DIV_DIV_DIV__input_carry - case - assign $3\fus_oper_i_alu_div0__input_carry[1:0] 2'00 - end + assign $4\fsm_state$275$next[2:0]$1245 3'001 + case + assign $4\fsm_state$275$next[2:0]$1245 \fsm_state$275 end case - assign $1\fus_oper_i_alu_div0__input_carry[1:0] 2'00 + assign $1\fsm_state$275$next[2:0]$1242 \fsm_state$275 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$275$next[2:0]$1246 3'000 + case + assign $5\fsm_state$275$next[2:0]$1246 $1\fsm_state$275$next[2:0]$1242 end sync always - update \fus_oper_i_alu_div0__input_carry $0\fus_oper_i_alu_div0__input_carry[1:0] + update \fsm_state$275$next $0\fsm_state$275$next[2:0]$1241 end - attribute \src "issuer_ls180.v:42573.3-42601.6" - process $proc$issuer_ls180.v:42573$2295 + attribute \src "libresoc.v:44101.3-44127.6" + process $proc$libresoc.v:44101$1247 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_div0__invert_out[0:0] $1\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "issuer_ls180.v:42574.5-42574.29" + assign { } { } + assign $0\dmi0_din$next[63:0]$1248 $3\dmi0_din$next[63:0]$1251 + attribute \src "libresoc.v:44102.5-44102.29" switch \initial - attribute \src "issuer_ls180.v:42574.9-42574.17" + attribute \src "libresoc.v:44102.9-44102.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" + switch \fsm_state$275 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 assign { } { } - assign $1\fus_oper_i_alu_div0__invert_out[0:0] $2\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__invert_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__invert_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dmi0_din$next[63:0]$1249 $2\dmi0_din$next[63:0]$1250 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:148" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $2\dmi0_din$next[63:0]$1250 \dmi0_din + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $2\dmi0_din$next[63:0]$1250 \dmi0_din + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- assign { } { } - assign $2\fus_oper_i_alu_div0__invert_out[0:0] $3\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [6] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_div0__invert_out[0:0] \dec_DIV_DIV_DIV__invert_out - case - assign $3\fus_oper_i_alu_div0__invert_out[0:0] 1'0 - end + assign $2\dmi0_din$next[63:0]$1250 \dmi0_datasr__o + case + assign $2\dmi0_din$next[63:0]$1250 \dmi0_din end case - assign $1\fus_oper_i_alu_div0__invert_out[0:0] 1'0 + assign $1\dmi0_din$next[63:0]$1249 \dmi0_din end - sync always - update \fus_oper_i_alu_div0__invert_out $0\fus_oper_i_alu_div0__invert_out[0:0] - end - attribute \src "issuer_ls180.v:42602.3-42630.6" - process $proc$issuer_ls180.v:42602$2296 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_div0__write_cr0[0:0] $1\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "issuer_ls180.v:42603.5-42603.29" - switch \initial - attribute \src "issuer_ls180.v:42603.9-42603.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_div0__write_cr0[0:0] $2\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_div0__write_cr0[0:0] $3\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [6] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_div0__write_cr0[0:0] \dec_DIV_DIV_DIV__write_cr0 - case - assign $3\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_div0__write_cr0 $0\fus_oper_i_alu_div0__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:42631.3-42659.6" - process $proc$issuer_ls180.v:42631$2297 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_div0__output_carry[0:0] $1\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "issuer_ls180.v:42632.5-42632.29" - switch \initial - attribute \src "issuer_ls180.v:42632.9-42632.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_div0__output_carry[0:0] $2\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__output_carry[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__output_carry[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_div0__output_carry[0:0] $3\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [6] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_div0__output_carry[0:0] \dec_DIV_DIV_DIV__output_carry - case - assign $3\fus_oper_i_alu_div0__output_carry[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_div0__output_carry[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_div0__output_carry $0\fus_oper_i_alu_div0__output_carry[0:0] - end - attribute \src "issuer_ls180.v:42660.3-42688.6" - process $proc$issuer_ls180.v:42660$2298 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_div0__is_32bit[0:0] $1\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "issuer_ls180.v:42661.5-42661.29" - switch \initial - attribute \src "issuer_ls180.v:42661.9-42661.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_div0__is_32bit[0:0] $2\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_div0__is_32bit[0:0] $3\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [6] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_div0__is_32bit[0:0] \dec_DIV_DIV_DIV__is_32bit - case - assign $3\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_div0__is_32bit $0\fus_oper_i_alu_div0__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:42689.3-42717.6" - process $proc$issuer_ls180.v:42689$2299 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_div0__is_signed[0:0] $1\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "issuer_ls180.v:42690.5-42690.29" - switch \initial - attribute \src "issuer_ls180.v:42690.9-42690.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_div0__is_signed[0:0] $2\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__is_signed[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__is_signed[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_div0__is_signed[0:0] $3\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [6] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_div0__is_signed[0:0] \dec_DIV_DIV_DIV__is_signed - case - assign $3\fus_oper_i_alu_div0__is_signed[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_div0__is_signed[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_div0__is_signed $0\fus_oper_i_alu_div0__is_signed[0:0] - end - attribute \src "issuer_ls180.v:42718.3-42746.6" - process $proc$issuer_ls180.v:42718$2300 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_div0__data_len[3:0] $1\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "issuer_ls180.v:42719.5-42719.29" - switch \initial - attribute \src "issuer_ls180.v:42719.9-42719.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_div0__data_len[3:0] $2\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__data_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__data_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_div0__data_len[3:0] $3\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [6] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_div0__data_len[3:0] \dec_DIV_DIV_DIV__data_len - case - assign $3\fus_oper_i_alu_div0__data_len[3:0] 4'0000 - end - end - case - assign $1\fus_oper_i_alu_div0__data_len[3:0] 4'0000 - end - sync always - update \fus_oper_i_alu_div0__data_len $0\fus_oper_i_alu_div0__data_len[3:0] - end - attribute \src "issuer_ls180.v:42747.3-42775.6" - process $proc$issuer_ls180.v:42747$2301 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_div0__insn[31:0] $1\fus_oper_i_alu_div0__insn[31:0] - attribute \src "issuer_ls180.v:42748.5-42748.29" - switch \initial - attribute \src "issuer_ls180.v:42748.9-42748.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_div0__insn[31:0] $2\fus_oper_i_alu_div0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__insn[31:0] 0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__insn[31:0] 0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_div0__insn[31:0] $3\fus_oper_i_alu_div0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [6] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_div0__insn[31:0] \dec_DIV_DIV_DIV__insn - case - assign $3\fus_oper_i_alu_div0__insn[31:0] 0 - end - end - case - assign $1\fus_oper_i_alu_div0__insn[31:0] 0 - end - sync always - update \fus_oper_i_alu_div0__insn $0\fus_oper_i_alu_div0__insn[31:0] - end - attribute \src "issuer_ls180.v:42776.3-42804.6" - process $proc$issuer_ls180.v:42776$2302 - assign { } { } - assign { } { } - assign $0\fus_cu_issue_i$19[0:0]$2303 $1\fus_cu_issue_i$19[0:0]$2304 - attribute \src "issuer_ls180.v:42777.5-42777.29" - switch \initial - attribute \src "issuer_ls180.v:42777.9-42777.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_issue_i$19[0:0]$2304 $2\fus_cu_issue_i$19[0:0]$2305 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_issue_i$19[0:0]$2305 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_issue_i$19[0:0]$2305 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_issue_i$19[0:0]$2305 $3\fus_cu_issue_i$19[0:0]$2306 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [6] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_issue_i$19[0:0]$2306 \issue_i - case - assign $3\fus_cu_issue_i$19[0:0]$2306 1'0 - end - end - case - assign $1\fus_cu_issue_i$19[0:0]$2304 1'0 - end - sync always - update \fus_cu_issue_i$19 $0\fus_cu_issue_i$19[0:0]$2303 - end - attribute \src "issuer_ls180.v:42805.3-42833.6" - process $proc$issuer_ls180.v:42805$2307 - assign { } { } - assign { } { } - assign $0\fus_cu_rdmaskn_i$21[2:0]$2308 $1\fus_cu_rdmaskn_i$21[2:0]$2309 - attribute \src "issuer_ls180.v:42806.5-42806.29" - switch \initial - attribute \src "issuer_ls180.v:42806.9-42806.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_rdmaskn_i$21[2:0]$2309 $2\fus_cu_rdmaskn_i$21[2:0]$2310 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_rdmaskn_i$21[2:0]$2310 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_rdmaskn_i$21[2:0]$2310 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_rdmaskn_i$21[2:0]$2310 $3\fus_cu_rdmaskn_i$21[2:0]$2311 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [6] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_rdmaskn_i$21[2:0]$2311 \$279 - case - assign $3\fus_cu_rdmaskn_i$21[2:0]$2311 3'000 - end - end - case - assign $1\fus_cu_rdmaskn_i$21[2:0]$2309 3'000 - end - sync always - update \fus_cu_rdmaskn_i$21 $0\fus_cu_rdmaskn_i$21[2:0]$2308 - end - attribute \src "issuer_ls180.v:42834.3-42862.6" - process $proc$issuer_ls180.v:42834$2312 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_mul0__insn_type[6:0] $1\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "issuer_ls180.v:42835.5-42835.29" - switch \initial - attribute \src "issuer_ls180.v:42835.9-42835.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_mul0__insn_type[6:0] $2\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_mul0__insn_type[6:0] $3\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [7] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_mul0__insn_type[6:0] \dec_MUL_MUL_MUL__insn_type - case - assign $3\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 - end - end - case - assign $1\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 - end - sync always - update \fus_oper_i_alu_mul0__insn_type $0\fus_oper_i_alu_mul0__insn_type[6:0] - end - attribute \src "issuer_ls180.v:42863.3-42891.6" - process $proc$issuer_ls180.v:42863$2313 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_mul0__fn_unit[11:0] $1\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "issuer_ls180.v:42864.5-42864.29" - switch \initial - attribute \src "issuer_ls180.v:42864.9-42864.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_mul0__fn_unit[11:0] $2\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_mul0__fn_unit[11:0] $3\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [7] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_mul0__fn_unit[11:0] \dec_MUL_MUL_MUL__fn_unit - case - assign $3\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 - end - end - case - assign $1\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 - end - sync always - update \fus_oper_i_alu_mul0__fn_unit $0\fus_oper_i_alu_mul0__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:42892.3-42921.6" - process $proc$issuer_ls180.v:42892$2314 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_mul0__imm_data__data[63:0] $1\fus_oper_i_alu_mul0__imm_data__data[63:0] - assign $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:42893.5-42893.29" - switch \initial - attribute \src "issuer_ls180.v:42893.9-42893.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_mul0__imm_data__data[63:0] $2\fus_oper_i_alu_mul0__imm_data__data[63:0] - assign $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] $3\fus_oper_i_alu_mul0__imm_data__data[63:0] - assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [7] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] $3\fus_oper_i_alu_mul0__imm_data__data[63:0] } { \dec_MUL_MUL_MUL__imm_data__ok \dec_MUL_MUL_MUL__imm_data__data } - case - assign $3\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_mul0__imm_data__data $0\fus_oper_i_alu_mul0__imm_data__data[63:0] - update \fus_oper_i_alu_mul0__imm_data__ok $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:42922.3-42951.6" - process $proc$issuer_ls180.v:42922$2315 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_mul0__rc__ok[0:0] $1\fus_oper_i_alu_mul0__rc__ok[0:0] - assign $0\fus_oper_i_alu_mul0__rc__rc[0:0] $1\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "issuer_ls180.v:42923.5-42923.29" - switch \initial - attribute \src "issuer_ls180.v:42923.9-42923.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_mul0__rc__ok[0:0] $2\fus_oper_i_alu_mul0__rc__ok[0:0] - assign $1\fus_oper_i_alu_mul0__rc__rc[0:0] $2\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] $3\fus_oper_i_alu_mul0__rc__ok[0:0] - assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] $3\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [7] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_mul0__rc__ok[0:0] $3\fus_oper_i_alu_mul0__rc__rc[0:0] } { \dec_MUL_MUL_MUL__rc__ok \dec_MUL_MUL_MUL__rc__rc } - case - assign $3\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 - assign $3\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 - assign $1\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_mul0__rc__ok $0\fus_oper_i_alu_mul0__rc__ok[0:0] - update \fus_oper_i_alu_mul0__rc__rc $0\fus_oper_i_alu_mul0__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:42952.3-42981.6" - process $proc$issuer_ls180.v:42952$2316 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_mul0__oe__oe[0:0] $1\fus_oper_i_alu_mul0__oe__oe[0:0] - assign $0\fus_oper_i_alu_mul0__oe__ok[0:0] $1\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "issuer_ls180.v:42953.5-42953.29" - switch \initial - attribute \src "issuer_ls180.v:42953.9-42953.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_mul0__oe__oe[0:0] $2\fus_oper_i_alu_mul0__oe__oe[0:0] - assign $1\fus_oper_i_alu_mul0__oe__ok[0:0] $2\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] $3\fus_oper_i_alu_mul0__oe__oe[0:0] - assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] $3\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [7] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_mul0__oe__ok[0:0] $3\fus_oper_i_alu_mul0__oe__oe[0:0] } { \dec_MUL_MUL_MUL__oe__ok \dec_MUL_MUL_MUL__oe__oe } - case - assign $3\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 - assign $3\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 - assign $1\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_mul0__oe__oe $0\fus_oper_i_alu_mul0__oe__oe[0:0] - update \fus_oper_i_alu_mul0__oe__ok $0\fus_oper_i_alu_mul0__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:42982.3-43010.6" - process $proc$issuer_ls180.v:42982$2317 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_mul0__write_cr0[0:0] $1\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "issuer_ls180.v:42983.5-42983.29" - switch \initial - attribute \src "issuer_ls180.v:42983.9-42983.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_mul0__write_cr0[0:0] $2\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] $3\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [7] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_mul0__write_cr0[0:0] \dec_MUL_MUL_MUL__write_cr0 - case - assign $3\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_mul0__write_cr0 $0\fus_oper_i_alu_mul0__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:43011.3-43039.6" - process $proc$issuer_ls180.v:43011$2318 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_mul0__is_32bit[0:0] $1\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "issuer_ls180.v:43012.5-43012.29" - switch \initial - attribute \src "issuer_ls180.v:43012.9-43012.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_mul0__is_32bit[0:0] $2\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] $3\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [7] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_mul0__is_32bit[0:0] \dec_MUL_MUL_MUL__is_32bit - case - assign $3\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_mul0__is_32bit $0\fus_oper_i_alu_mul0__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:43040.3-43068.6" - process $proc$issuer_ls180.v:43040$2319 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_mul0__is_signed[0:0] $1\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "issuer_ls180.v:43041.5-43041.29" - switch \initial - attribute \src "issuer_ls180.v:43041.9-43041.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_mul0__is_signed[0:0] $2\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_mul0__is_signed[0:0] $3\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [7] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_mul0__is_signed[0:0] \dec_MUL_MUL_MUL__is_signed - case - assign $3\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_mul0__is_signed $0\fus_oper_i_alu_mul0__is_signed[0:0] - end - attribute \src "issuer_ls180.v:43069.3-43097.6" - process $proc$issuer_ls180.v:43069$2320 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_mul0__insn[31:0] $1\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "issuer_ls180.v:43070.5-43070.29" - switch \initial - attribute \src "issuer_ls180.v:43070.9-43070.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_mul0__insn[31:0] $2\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_mul0__insn[31:0] 0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_mul0__insn[31:0] 0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_mul0__insn[31:0] $3\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [7] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_mul0__insn[31:0] \dec_MUL_MUL_MUL__insn - case - assign $3\fus_oper_i_alu_mul0__insn[31:0] 0 - end - end - case - assign $1\fus_oper_i_alu_mul0__insn[31:0] 0 - end - sync always - update \fus_oper_i_alu_mul0__insn $0\fus_oper_i_alu_mul0__insn[31:0] - end - attribute \src "issuer_ls180.v:43098.3-43126.6" - process $proc$issuer_ls180.v:43098$2321 - assign { } { } - assign { } { } - assign $0\fus_cu_issue_i$22[0:0]$2322 $1\fus_cu_issue_i$22[0:0]$2323 - attribute \src "issuer_ls180.v:43099.5-43099.29" - switch \initial - attribute \src "issuer_ls180.v:43099.9-43099.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_issue_i$22[0:0]$2323 $2\fus_cu_issue_i$22[0:0]$2324 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_issue_i$22[0:0]$2324 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_issue_i$22[0:0]$2324 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_issue_i$22[0:0]$2324 $3\fus_cu_issue_i$22[0:0]$2325 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [7] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_issue_i$22[0:0]$2325 \issue_i - case - assign $3\fus_cu_issue_i$22[0:0]$2325 1'0 - end - end - case - assign $1\fus_cu_issue_i$22[0:0]$2323 1'0 - end - sync always - update \fus_cu_issue_i$22 $0\fus_cu_issue_i$22[0:0]$2322 - end - attribute \src "issuer_ls180.v:43127.3-43155.6" - process $proc$issuer_ls180.v:43127$2326 - assign { } { } - assign { } { } - assign $0\fus_cu_rdmaskn_i$24[2:0]$2327 $1\fus_cu_rdmaskn_i$24[2:0]$2328 - attribute \src "issuer_ls180.v:43128.5-43128.29" - switch \initial - attribute \src "issuer_ls180.v:43128.9-43128.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$24[2:0]$2328 $2\fus_cu_rdmaskn_i$24[2:0]$2329 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_rdmaskn_i$24[2:0]$2329 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_rdmaskn_i$24[2:0]$2329 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_rdmaskn_i$24[2:0]$2329 $3\fus_cu_rdmaskn_i$24[2:0]$2330 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [7] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_rdmaskn_i$24[2:0]$2330 \$293 - case - assign $3\fus_cu_rdmaskn_i$24[2:0]$2330 3'000 - end - end + assign $3\dmi0_din$next[63:0]$1251 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\fus_cu_rdmaskn_i$24[2:0]$2328 3'000 + assign $3\dmi0_din$next[63:0]$1251 $1\dmi0_din$next[63:0]$1249 end sync always - update \fus_cu_rdmaskn_i$24 $0\fus_cu_rdmaskn_i$24[2:0]$2327 + update \dmi0_din$next $0\dmi0_din$next[63:0]$1248 end - attribute \src "issuer_ls180.v:43156.3-43184.6" - process $proc$issuer_ls180.v:43156$2331 + attribute \src "libresoc.v:44128.3-44148.6" + process $proc$libresoc.v:44128$1252 assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "issuer_ls180.v:43157.5-43157.29" - switch \initial - attribute \src "issuer_ls180.v:43157.9-43157.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [8] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn_type - case - assign $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 - end - end - case - assign $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 - end - sync always - update \fus_oper_i_alu_shift_rot0__insn_type $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] - end - attribute \src "issuer_ls180.v:43185.3-43213.6" - process $proc$issuer_ls180.v:43185$2332 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__fn_unit[11:0] $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src "issuer_ls180.v:43186.5-43186.29" + assign $0\dmi0_datasr__i$next[63:0]$1253 $3\dmi0_datasr__i$next[63:0]$1256 + attribute \src "libresoc.v:44129.5-44129.29" switch \initial - attribute \src "issuer_ls180.v:43186.9-43186.17" + attribute \src "libresoc.v:44129.9-44129.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" + switch \fsm_state$275 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\dmi0_datasr__i$next[63:0]$1254 $2\dmi0_datasr__i$next[63:0]$1255 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:165" + switch \dmi0_ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [8] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__fn_unit - case - assign $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 - end - end - case - assign $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 - end - sync always - update \fus_oper_i_alu_shift_rot0__fn_unit $0\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:43214.3-43243.6" - process $proc$issuer_ls180.v:43214$2333 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - assign $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:43215.5-43215.29" - switch \initial - attribute \src "issuer_ls180.v:43215.9-43215.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - assign $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" + assign $2\dmi0_datasr__i$next[63:0]$1255 \dmi0_dout case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [8] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] } { \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__data } - case - assign $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 - end + assign $2\dmi0_datasr__i$next[63:0]$1255 \dmi0_datasr__i end case - assign $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_shift_rot0__imm_data__data $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - update \fus_oper_i_alu_shift_rot0__imm_data__ok $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:43244.3-43273.6" - process $proc$issuer_ls180.v:43244$2334 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - assign $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "issuer_ls180.v:43245.5-43245.29" - switch \initial - attribute \src "issuer_ls180.v:43245.9-43245.17" - case 1'1 - case + assign $1\dmi0_datasr__i$next[63:0]$1254 \dmi0_datasr__i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - assign $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [8] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] } { \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__rc } - case - assign $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 - assign $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 - end - end + assign $3\dmi0_datasr__i$next[63:0]$1256 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 - assign $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 + assign $3\dmi0_datasr__i$next[63:0]$1256 $1\dmi0_datasr__i$next[63:0]$1254 end sync always - update \fus_oper_i_alu_shift_rot0__rc__ok $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - update \fus_oper_i_alu_shift_rot0__rc__rc $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$1253 end - attribute \src "issuer_ls180.v:43274.3-43303.6" - process $proc$issuer_ls180.v:43274$2335 - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:44149.3-44217.6" + process $proc$libresoc.v:44149$1257 assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - assign $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "issuer_ls180.v:43275.5-43275.29" - switch \initial - attribute \src "issuer_ls180.v:43275.9-43275.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - assign $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [8] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] } { \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__oe } - case - assign $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 - assign $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 - assign $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_shift_rot0__oe__oe $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - update \fus_oper_i_alu_shift_rot0__oe__ok $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:43304.3-43332.6" - process $proc$issuer_ls180.v:43304$2336 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "issuer_ls180.v:43305.5-43305.29" + assign $0\io_sr$next[49:0]$1258 $2\io_sr$next[49:0]$1260 + attribute \src "libresoc.v:44150.5-44150.29" switch \initial - attribute \src "issuer_ls180.v:43305.9-43305.17" + attribute \src "libresoc.v:44150.9-44150.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:439" + switch { \io_update \io_shift \io_capture } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [8] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__write_cr0 - case - assign $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_shift_rot0__write_cr0 $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:43333.3-43361.6" - process $proc$issuer_ls180.v:43333$2337 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "issuer_ls180.v:43334.5-43334.29" - switch \initial - attribute \src "issuer_ls180.v:43334.9-43334.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\io_sr$next[49:0]$1259 [0] \uart_tx__core__o + assign $1\io_sr$next[49:0]$1259 [1] \uart_rx__pad__i + assign $1\io_sr$next[49:0]$1259 [2] \gpio_gpio0__pad__i + assign $1\io_sr$next[49:0]$1259 [3] \gpio_gpio0__core__o + assign $1\io_sr$next[49:0]$1259 [4] \gpio_gpio0__core__oe + assign $1\io_sr$next[49:0]$1259 [5] \gpio_gpio1__pad__i + assign $1\io_sr$next[49:0]$1259 [6] \gpio_gpio1__core__o + assign $1\io_sr$next[49:0]$1259 [7] \gpio_gpio1__core__oe + assign $1\io_sr$next[49:0]$1259 [8] \gpio_gpio2__pad__i + assign $1\io_sr$next[49:0]$1259 [9] \gpio_gpio2__core__o + assign $1\io_sr$next[49:0]$1259 [10] \gpio_gpio2__core__oe + assign $1\io_sr$next[49:0]$1259 [11] \gpio_gpio3__pad__i + assign $1\io_sr$next[49:0]$1259 [12] \gpio_gpio3__core__o + assign $1\io_sr$next[49:0]$1259 [13] \gpio_gpio3__core__oe + assign $1\io_sr$next[49:0]$1259 [14] \gpio_gpio4__pad__i + assign $1\io_sr$next[49:0]$1259 [15] \gpio_gpio4__core__o + assign $1\io_sr$next[49:0]$1259 [16] \gpio_gpio4__core__oe + assign $1\io_sr$next[49:0]$1259 [17] \gpio_gpio5__pad__i + assign $1\io_sr$next[49:0]$1259 [18] \gpio_gpio5__core__o + assign $1\io_sr$next[49:0]$1259 [19] \gpio_gpio5__core__oe + assign $1\io_sr$next[49:0]$1259 [20] \gpio_gpio6__pad__i + assign $1\io_sr$next[49:0]$1259 [21] \gpio_gpio6__core__o + assign $1\io_sr$next[49:0]$1259 [22] \gpio_gpio6__core__oe + assign $1\io_sr$next[49:0]$1259 [23] \gpio_gpio7__pad__i + assign $1\io_sr$next[49:0]$1259 [24] \gpio_gpio7__core__o + assign $1\io_sr$next[49:0]$1259 [25] \gpio_gpio7__core__oe + assign $1\io_sr$next[49:0]$1259 [26] \gpio_gpio8__pad__i + assign $1\io_sr$next[49:0]$1259 [27] \gpio_gpio8__core__o + assign $1\io_sr$next[49:0]$1259 [28] \gpio_gpio8__core__oe + assign $1\io_sr$next[49:0]$1259 [29] \gpio_gpio9__pad__i + assign $1\io_sr$next[49:0]$1259 [30] \gpio_gpio9__core__o + assign $1\io_sr$next[49:0]$1259 [31] \gpio_gpio9__core__oe + assign $1\io_sr$next[49:0]$1259 [32] \gpio_gpio10__pad__i + assign $1\io_sr$next[49:0]$1259 [33] \gpio_gpio10__core__o + assign $1\io_sr$next[49:0]$1259 [34] \gpio_gpio10__core__oe + assign $1\io_sr$next[49:0]$1259 [35] \gpio_gpio11__pad__i + assign $1\io_sr$next[49:0]$1259 [36] \gpio_gpio11__core__o + assign $1\io_sr$next[49:0]$1259 [37] \gpio_gpio11__core__oe + assign $1\io_sr$next[49:0]$1259 [38] \gpio_gpio12__pad__i + assign $1\io_sr$next[49:0]$1259 [39] \gpio_gpio12__core__o + assign $1\io_sr$next[49:0]$1259 [40] \gpio_gpio12__core__oe + assign $1\io_sr$next[49:0]$1259 [41] \gpio_gpio13__pad__i + assign $1\io_sr$next[49:0]$1259 [42] \gpio_gpio13__core__o + assign $1\io_sr$next[49:0]$1259 [43] \gpio_gpio13__core__oe + assign $1\io_sr$next[49:0]$1259 [44] \gpio_gpio14__pad__i + assign $1\io_sr$next[49:0]$1259 [45] \gpio_gpio14__core__o + assign $1\io_sr$next[49:0]$1259 [46] \gpio_gpio14__core__oe + assign $1\io_sr$next[49:0]$1259 [47] \gpio_gpio15__pad__i + assign $1\io_sr$next[49:0]$1259 [48] \gpio_gpio15__core__o + assign $1\io_sr$next[49:0]$1259 [49] \gpio_gpio15__core__oe + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [8] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_carry - case - assign $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 - end - end + assign $1\io_sr$next[49:0]$1259 { \io_sr [48:0] \TAP_bus__tdi } case - assign $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 + assign $1\io_sr$next[49:0]$1259 \io_sr end - sync always - update \fus_oper_i_alu_shift_rot0__input_carry $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] - end - attribute \src "issuer_ls180.v:43362.3-43390.6" - process $proc$issuer_ls180.v:43362$2338 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "issuer_ls180.v:43363.5-43363.29" - switch \initial - attribute \src "issuer_ls180.v:43363.9-43363.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [8] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_carry - case - assign $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 - end - end + assign $2\io_sr$next[49:0]$1260 50'00000000000000000000000000000000000000000000000000 case - assign $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 + assign $2\io_sr$next[49:0]$1260 $1\io_sr$next[49:0]$1259 end sync always - update \fus_oper_i_alu_shift_rot0__output_carry $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] + update \io_sr$next $0\io_sr$next[49:0]$1258 end - attribute \src "issuer_ls180.v:43391.3-43419.6" - process $proc$issuer_ls180.v:43391$2339 + attribute \src "libresoc.v:44218.3-44233.6" + process $proc$libresoc.v:44218$1261 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "issuer_ls180.v:43392.5-43392.29" + assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0] + attribute \src "libresoc.v:44219.5-44219.29" switch \initial - attribute \src "issuer_ls180.v:43392.9-43392.17" + attribute \src "libresoc.v:44219.9-44219.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:395" + switch { \$159 \$147 \_fsm_isir } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [8] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_cr - case - assign $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_shift_rot0__input_cr $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] - end - attribute \src "issuer_ls180.v:43420.3-43448.6" - process $proc$issuer_ls180.v:43420$2340 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "issuer_ls180.v:43421.5-43421.29" - switch \initial - attribute \src "issuer_ls180.v:43421.9-43421.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\TAP_tdo[0:0] \_irblock_tdo + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [8] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_cr - case - assign $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_shift_rot0__output_cr $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] - end - attribute \src "issuer_ls180.v:43449.3-43477.6" - process $proc$issuer_ls180.v:43449$2341 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "issuer_ls180.v:43450.5-43450.29" - switch \initial - attribute \src "issuer_ls180.v:43450.9-43450.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\TAP_tdo[0:0] \_idblock_TAP_id_tdo + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [8] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_32bit - case - assign $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 - end - end + assign $1\TAP_tdo[0:0] \io_sr [49] case - assign $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 + assign $1\TAP_tdo[0:0] 1'0 end sync always - update \fus_oper_i_alu_shift_rot0__is_32bit $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + update \TAP_tdo $0\TAP_tdo[0:0] end - attribute \src "issuer_ls180.v:43478.3-43506.6" - process $proc$issuer_ls180.v:43478$2342 - assign { } { } + attribute \src "libresoc.v:44234.3-44254.6" + process $proc$libresoc.v:44234$1262 assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "issuer_ls180.v:43479.5-43479.29" - switch \initial - attribute \src "issuer_ls180.v:43479.9-43479.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [8] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_signed - case - assign $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_shift_rot0__is_signed $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] - end - attribute \src "issuer_ls180.v:43507.3-43535.6" - process $proc$issuer_ls180.v:43507$2343 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__insn[31:0] $1\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "issuer_ls180.v:43508.5-43508.29" + assign $0\io_bd$next[49:0]$1263 $2\io_bd$next[49:0]$1265 + attribute \src "libresoc.v:44235.5-44235.29" switch \initial - attribute \src "issuer_ls180.v:43508.9-43508.17" + attribute \src "libresoc.v:44235.9-44235.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:439" + switch { \io_update \io_shift \io_capture } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $1\io_bd$next[49:0]$1264 \io_bd + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $1\io_bd$next[49:0]$1264 \io_bd + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__insn[31:0] $2\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] 0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] 0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] $3\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [8] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__insn[31:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn - case - assign $3\fus_oper_i_alu_shift_rot0__insn[31:0] 0 - end - end - case - assign $1\fus_oper_i_alu_shift_rot0__insn[31:0] 0 - end - sync always - update \fus_oper_i_alu_shift_rot0__insn $0\fus_oper_i_alu_shift_rot0__insn[31:0] - end - attribute \src "issuer_ls180.v:43536.3-43564.6" - process $proc$issuer_ls180.v:43536$2344 - assign { } { } - assign { } { } - assign $0\fus_cu_issue_i$25[0:0]$2345 $1\fus_cu_issue_i$25[0:0]$2346 - attribute \src "issuer_ls180.v:43537.5-43537.29" - switch \initial - attribute \src "issuer_ls180.v:43537.9-43537.17" - case 1'1 + assign $1\io_bd$next[49:0]$1264 \io_sr case + assign $1\io_bd$next[49:0]$1264 \io_bd end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \negjtag_rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$25[0:0]$2346 $2\fus_cu_issue_i$25[0:0]$2347 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_issue_i$25[0:0]$2347 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_issue_i$25[0:0]$2347 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_issue_i$25[0:0]$2347 $3\fus_cu_issue_i$25[0:0]$2348 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [8] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_issue_i$25[0:0]$2348 \issue_i - case - assign $3\fus_cu_issue_i$25[0:0]$2348 1'0 - end - end + assign $2\io_bd$next[49:0]$1265 50'00000000000000000000000000000000000000000000000000 case - assign $1\fus_cu_issue_i$25[0:0]$2346 1'0 + assign $2\io_bd$next[49:0]$1265 $1\io_bd$next[49:0]$1264 end sync always - update \fus_cu_issue_i$25 $0\fus_cu_issue_i$25[0:0]$2345 + update \io_bd$next $0\io_bd$next[49:0]$1263 end - attribute \src "issuer_ls180.v:43565.3-43593.6" - process $proc$issuer_ls180.v:43565$2349 + attribute \src "libresoc.v:44255.3-44263.6" + process $proc$libresoc.v:44255$1266 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$27[4:0]$2350 $1\fus_cu_rdmaskn_i$27[4:0]$2351 - attribute \src "issuer_ls180.v:43566.5-43566.29" + assign $0\sr0_update_core$next[0:0]$1267 $1\sr0_update_core$next[0:0]$1268 + attribute \src "libresoc.v:44256.5-44256.29" switch \initial - attribute \src "issuer_ls180.v:43566.9-43566.17" + attribute \src "libresoc.v:44256.9-44256.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$27[4:0]$2351 $2\fus_cu_rdmaskn_i$27[4:0]$2352 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_rdmaskn_i$27[4:0]$2352 5'00000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_rdmaskn_i$27[4:0]$2352 5'00000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_rdmaskn_i$27[4:0]$2352 $3\fus_cu_rdmaskn_i$27[4:0]$2353 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [8] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_rdmaskn_i$27[4:0]$2353 \$307 - case - assign $3\fus_cu_rdmaskn_i$27[4:0]$2353 5'00000 - end - end + assign $1\sr0_update_core$next[0:0]$1268 1'0 case - assign $1\fus_cu_rdmaskn_i$27[4:0]$2351 5'00000 + assign $1\sr0_update_core$next[0:0]$1268 \sr0_update end sync always - update \fus_cu_rdmaskn_i$27 $0\fus_cu_rdmaskn_i$27[4:0]$2350 + update \sr0_update_core$next $0\sr0_update_core$next[0:0]$1267 end - attribute \src "issuer_ls180.v:43594.3-43622.6" - process $proc$issuer_ls180.v:43594$2354 + attribute \src "libresoc.v:44264.3-44272.6" + process $proc$libresoc.v:44264$1269 assign { } { } assign { } { } - assign $0\fus_oper_i_ldst_ldst0__insn_type[6:0] $1\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "issuer_ls180.v:43595.5-43595.29" + assign $0\sr0_update_core_prev$next[0:0]$1270 $1\sr0_update_core_prev$next[0:0]$1271 + attribute \src "libresoc.v:44265.5-44265.29" switch \initial - attribute \src "issuer_ls180.v:43595.9-43595.17" + attribute \src "libresoc.v:44265.9-44265.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_ldst_ldst0__insn_type[6:0] $2\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] $3\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [9] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_ldst_ldst0__insn_type[6:0] \dec_LDST_LDST_LDST__insn_type - case - assign $3\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 - end - end + assign $1\sr0_update_core_prev$next[0:0]$1271 1'0 case - assign $1\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 + assign $1\sr0_update_core_prev$next[0:0]$1271 \sr0_update_core end sync always - update \fus_oper_i_ldst_ldst0__insn_type $0\fus_oper_i_ldst_ldst0__insn_type[6:0] + update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$1270 end - attribute \src "issuer_ls180.v:43623.3-43651.6" - process $proc$issuer_ls180.v:43623$2355 + attribute \src "libresoc.v:44273.3-44289.6" + process $proc$libresoc.v:44273$1272 assign { } { } assign { } { } - assign $0\fus_oper_i_ldst_ldst0__fn_unit[11:0] $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "issuer_ls180.v:43624.5-43624.29" + assign $0\sr0__oe$next[0:0]$1273 $2\sr0__oe$next[0:0]$1275 + attribute \src "libresoc.v:44274.5-44274.29" switch \initial - attribute \src "issuer_ls180.v:43624.9-43624.17" + attribute \src "libresoc.v:44274.9-44274.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + switch \$177 + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [9] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] \dec_LDST_LDST_LDST__fn_unit - case - assign $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 - end - end - case - assign $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 - end - sync always - update \fus_oper_i_ldst_ldst0__fn_unit $0\fus_oper_i_ldst_ldst0__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:43652.3-43681.6" - process $proc$issuer_ls180.v:43652$2356 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - assign $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:43653.5-43653.29" - switch \initial - attribute \src "issuer_ls180.v:43653.9-43653.17" - case 1'1 + assign $1\sr0__oe$next[0:0]$1274 \sr0_isir + attribute \src "libresoc.v:0.0-0.0" case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 assign { } { } - assign { } { } - assign $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - assign $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [9] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] } { \dec_LDST_LDST_LDST__imm_data__ok \dec_LDST_LDST_LDST__imm_data__data } - case - assign $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 - end - sync always - update \fus_oper_i_ldst_ldst0__imm_data__data $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - update \fus_oper_i_ldst_ldst0__imm_data__ok $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:43682.3-43710.6" - process $proc$issuer_ls180.v:43682$2357 - assign { } { } - assign { } { } - assign $0\fus_oper_i_ldst_ldst0__zero_a[0:0] $1\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "issuer_ls180.v:43683.5-43683.29" - switch \initial - attribute \src "issuer_ls180.v:43683.9-43683.17" - case 1'1 - case + assign $1\sr0__oe$next[0:0]$1274 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_ldst_ldst0__zero_a[0:0] $2\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] $3\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [9] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_ldst_ldst0__zero_a[0:0] \dec_LDST_LDST_LDST__zero_a - case - assign $3\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 - end - end + assign $2\sr0__oe$next[0:0]$1275 1'0 case - assign $1\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 + assign $2\sr0__oe$next[0:0]$1275 $1\sr0__oe$next[0:0]$1274 end sync always - update \fus_oper_i_ldst_ldst0__zero_a $0\fus_oper_i_ldst_ldst0__zero_a[0:0] + update \sr0__oe$next $0\sr0__oe$next[0:0]$1273 end - attribute \src "issuer_ls180.v:43711.3-43740.6" - process $proc$issuer_ls180.v:43711$2358 + attribute \src "libresoc.v:44290.3-44310.6" + process $proc$libresoc.v:44290$1276 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] - assign $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "issuer_ls180.v:43712.5-43712.29" + assign $0\sr0_reg$next[2:0]$1277 $3\sr0_reg$next[2:0]$1280 + attribute \src "libresoc.v:44291.5-44291.29" switch \initial - attribute \src "issuer_ls180.v:43712.9-43712.17" + attribute \src "libresoc.v:44291.9-44291.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" + switch \sr0_shift + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] - assign $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] - assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [9] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] } { \dec_LDST_LDST_LDST__rc__ok \dec_LDST_LDST_LDST__rc__rc } - case - assign $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 - assign $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 - assign $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 - end - sync always - update \fus_oper_i_ldst_ldst0__rc__ok $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] - update \fus_oper_i_ldst_ldst0__rc__rc $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:43741.3-43770.6" - process $proc$issuer_ls180.v:43741$2359 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] - assign $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "issuer_ls180.v:43742.5-43742.29" - switch \initial - attribute \src "issuer_ls180.v:43742.9-43742.17" - case 1'1 + assign $1\sr0_reg$next[2:0]$1278 { \TAP_bus__tdi \sr0_reg [2:1] } case + assign $1\sr0_reg$next[2:0]$1278 \sr0_reg end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" + switch \sr0_capture + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] - assign $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] - assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [9] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] } { \dec_LDST_LDST_LDST__oe__ok \dec_LDST_LDST_LDST__oe__oe } - case - assign $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 - assign $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 - assign $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 - end - sync always - update \fus_oper_i_ldst_ldst0__oe__oe $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] - update \fus_oper_i_ldst_ldst0__oe__ok $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:43771.3-43799.6" - process $proc$issuer_ls180.v:43771$2360 - assign { } { } - assign { } { } - assign $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "issuer_ls180.v:43772.5-43772.29" - switch \initial - attribute \src "issuer_ls180.v:43772.9-43772.17" - case 1'1 + assign $2\sr0_reg$next[2:0]$1279 \sr0__i case + assign $2\sr0_reg$next[2:0]$1279 $1\sr0_reg$next[2:0]$1278 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [9] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] \dec_LDST_LDST_LDST__is_32bit - case - assign $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 - end - end + assign $3\sr0_reg$next[2:0]$1280 3'000 case - assign $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 + assign $3\sr0_reg$next[2:0]$1280 $2\sr0_reg$next[2:0]$1279 end sync always - update \fus_oper_i_ldst_ldst0__is_32bit $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] + update \sr0_reg$next $0\sr0_reg$next[2:0]$1277 end - attribute \src "issuer_ls180.v:43800.3-43828.6" - process $proc$issuer_ls180.v:43800$2361 + attribute \src "libresoc.v:44311.3-44319.6" + process $proc$libresoc.v:44311$1281 assign { } { } assign { } { } - assign $0\fus_oper_i_ldst_ldst0__is_signed[0:0] $1\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "issuer_ls180.v:43801.5-43801.29" + assign $0\jtag_wb_addrsr_update_core$next[0:0]$1282 $1\jtag_wb_addrsr_update_core$next[0:0]$1283 + attribute \src "libresoc.v:44312.5-44312.29" switch \initial - attribute \src "issuer_ls180.v:43801.9-43801.17" + attribute \src "libresoc.v:44312.9-44312.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_ldst_ldst0__is_signed[0:0] $2\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] $3\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [9] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_ldst_ldst0__is_signed[0:0] \dec_LDST_LDST_LDST__is_signed - case - assign $3\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 - end - end + assign $1\jtag_wb_addrsr_update_core$next[0:0]$1283 1'0 case - assign $1\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 + assign $1\jtag_wb_addrsr_update_core$next[0:0]$1283 \jtag_wb_addrsr_update end sync always - update \fus_oper_i_ldst_ldst0__is_signed $0\fus_oper_i_ldst_ldst0__is_signed[0:0] + update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$1282 end - attribute \src "issuer_ls180.v:43829.3-43857.6" - process $proc$issuer_ls180.v:43829$2362 + attribute \src "libresoc.v:44320.3-44328.6" + process $proc$libresoc.v:44320$1284 assign { } { } assign { } { } - assign $0\fus_oper_i_ldst_ldst0__data_len[3:0] $1\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "issuer_ls180.v:43830.5-43830.29" + assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1285 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1286 + attribute \src "libresoc.v:44321.5-44321.29" switch \initial - attribute \src "issuer_ls180.v:43830.9-43830.17" + attribute \src "libresoc.v:44321.9-44321.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_ldst_ldst0__data_len[3:0] $2\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] $3\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [9] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_ldst_ldst0__data_len[3:0] \dec_LDST_LDST_LDST__data_len - case - assign $3\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 - end - end + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1286 1'0 case - assign $1\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1286 \jtag_wb_addrsr_update_core end sync always - update \fus_oper_i_ldst_ldst0__data_len $0\fus_oper_i_ldst_ldst0__data_len[3:0] + update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1285 end - attribute \src "issuer_ls180.v:43858.3-43886.6" - process $proc$issuer_ls180.v:43858$2363 + attribute \src "libresoc.v:44329.3-44345.6" + process $proc$libresoc.v:44329$1287 assign { } { } assign { } { } - assign $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "issuer_ls180.v:43859.5-43859.29" + assign $0\jtag_wb_addrsr__oe$next[0:0]$1288 $2\jtag_wb_addrsr__oe$next[0:0]$1290 + attribute \src "libresoc.v:44330.5-44330.29" switch \initial - attribute \src "issuer_ls180.v:43859.9-43859.17" + attribute \src "libresoc.v:44330.9-44330.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + switch \$195 + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [9] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] \dec_LDST_LDST_LDST__byte_reverse - case - assign $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 - end - sync always - update \fus_oper_i_ldst_ldst0__byte_reverse $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - end - attribute \src "issuer_ls180.v:43887.3-43915.6" - process $proc$issuer_ls180.v:43887$2364 - assign { } { } - assign { } { } - assign $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "issuer_ls180.v:43888.5-43888.29" - switch \initial - attribute \src "issuer_ls180.v:43888.9-43888.17" - case 1'1 + assign $1\jtag_wb_addrsr__oe$next[0:0]$1289 \jtag_wb_addrsr_isir + attribute \src "libresoc.v:0.0-0.0" case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 assign { } { } - assign $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [9] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] \dec_LDST_LDST_LDST__sign_extend - case - assign $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 - end - sync always - update \fus_oper_i_ldst_ldst0__sign_extend $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] - end - attribute \src "issuer_ls180.v:43916.3-43944.6" - process $proc$issuer_ls180.v:43916$2365 - assign { } { } - assign { } { } - assign $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "issuer_ls180.v:43917.5-43917.29" - switch \initial - attribute \src "issuer_ls180.v:43917.9-43917.17" - case 1'1 - case + assign $1\jtag_wb_addrsr__oe$next[0:0]$1289 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [9] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] \dec_LDST_LDST_LDST__ldst_mode - case - assign $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 - end - end + assign $2\jtag_wb_addrsr__oe$next[0:0]$1290 1'0 case - assign $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 + assign $2\jtag_wb_addrsr__oe$next[0:0]$1290 $1\jtag_wb_addrsr__oe$next[0:0]$1289 end sync always - update \fus_oper_i_ldst_ldst0__ldst_mode $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$1288 end - attribute \src "issuer_ls180.v:43945.3-43973.6" - process $proc$issuer_ls180.v:43945$2366 + attribute \src "libresoc.v:44346.3-44366.6" + process $proc$libresoc.v:44346$1291 assign { } { } assign { } { } - assign $0\fus_oper_i_ldst_ldst0__insn[31:0] $1\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "issuer_ls180.v:43946.5-43946.29" - switch \initial - attribute \src "issuer_ls180.v:43946.9-43946.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_ldst_ldst0__insn[31:0] $2\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__insn[31:0] 0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__insn[31:0] 0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__insn[31:0] $3\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [9] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_ldst_ldst0__insn[31:0] \dec_LDST_LDST_LDST__insn - case - assign $3\fus_oper_i_ldst_ldst0__insn[31:0] 0 - end - end - case - assign $1\fus_oper_i_ldst_ldst0__insn[31:0] 0 - end - sync always - update \fus_oper_i_ldst_ldst0__insn $0\fus_oper_i_ldst_ldst0__insn[31:0] - end - attribute \src "issuer_ls180.v:43974.3-44002.6" - process $proc$issuer_ls180.v:43974$2367 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$28[0:0]$2368 $1\fus_cu_issue_i$28[0:0]$2369 - attribute \src "issuer_ls180.v:43975.5-43975.29" + assign $0\jtag_wb_addrsr_reg$next[28:0]$1292 $3\jtag_wb_addrsr_reg$next[28:0]$1295 + attribute \src "libresoc.v:44347.5-44347.29" switch \initial - attribute \src "issuer_ls180.v:43975.9-43975.17" + attribute \src "libresoc.v:44347.9-44347.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" + switch \jtag_wb_addrsr_shift + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$28[0:0]$2369 $2\fus_cu_issue_i$28[0:0]$2370 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_issue_i$28[0:0]$2370 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_issue_i$28[0:0]$2370 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_issue_i$28[0:0]$2370 $3\fus_cu_issue_i$28[0:0]$2371 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [9] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_issue_i$28[0:0]$2371 \issue_i - case - assign $3\fus_cu_issue_i$28[0:0]$2371 1'0 - end - end + assign $1\jtag_wb_addrsr_reg$next[28:0]$1293 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } case - assign $1\fus_cu_issue_i$28[0:0]$2369 1'0 + assign $1\jtag_wb_addrsr_reg$next[28:0]$1293 \jtag_wb_addrsr_reg end - sync always - update \fus_cu_issue_i$28 $0\fus_cu_issue_i$28[0:0]$2368 - end - attribute \src "issuer_ls180.v:44003.3-44031.6" - process $proc$issuer_ls180.v:44003$2372 - assign { } { } - assign { } { } - assign $0\fus_cu_rdmaskn_i$30[2:0]$2373 $1\fus_cu_rdmaskn_i$30[2:0]$2374 - attribute \src "issuer_ls180.v:44004.5-44004.29" - switch \initial - attribute \src "issuer_ls180.v:44004.9-44004.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" + switch \jtag_wb_addrsr_capture + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$30[2:0]$2374 $2\fus_cu_rdmaskn_i$30[2:0]$2375 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_rdmaskn_i$30[2:0]$2375 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_rdmaskn_i$30[2:0]$2375 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_rdmaskn_i$30[2:0]$2375 $3\fus_cu_rdmaskn_i$30[2:0]$2376 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [9] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_rdmaskn_i$30[2:0]$2376 \$329 - case - assign $3\fus_cu_rdmaskn_i$30[2:0]$2376 3'000 - end - end - case - assign $1\fus_cu_rdmaskn_i$30[2:0]$2374 3'000 - end - sync always - update \fus_cu_rdmaskn_i$30 $0\fus_cu_rdmaskn_i$30[2:0]$2373 - end - attribute \src "issuer_ls180.v:44032.3-44040.6" - process $proc$issuer_ls180.v:44032$2377 - assign { } { } - assign { } { } - assign $0\dp_INT_ra_alu0_0$next[0:0]$2378 $1\dp_INT_ra_alu0_0$next[0:0]$2379 - attribute \src "issuer_ls180.v:44033.5-44033.29" - switch \initial - attribute \src "issuer_ls180.v:44033.9-44033.17" - case 1'1 + assign $2\jtag_wb_addrsr_reg$next[28:0]$1294 \jtag_wb_addrsr__i case + assign $2\jtag_wb_addrsr_reg$next[28:0]$1294 $1\jtag_wb_addrsr_reg$next[28:0]$1293 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_ra_alu0_0$next[0:0]$2379 1'0 - case - assign $1\dp_INT_ra_alu0_0$next[0:0]$2379 \rp_INT_ra_alu0_0 - end - sync always - update \dp_INT_ra_alu0_0$next $0\dp_INT_ra_alu0_0$next[0:0]$2378 - end - attribute \src "issuer_ls180.v:44041.3-44050.6" - process $proc$issuer_ls180.v:44041$2380 - assign { } { } - assign { } { } - assign $0\fus_src1_i[63:0] $1\fus_src1_i[63:0] - attribute \src "issuer_ls180.v:44042.5-44042.29" - switch \initial - attribute \src "issuer_ls180.v:44042.9-44042.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_INT_ra_alu0_0 - attribute \src "issuer_ls180.v:0.0-0.0" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i[63:0] \int_src1__data_o + assign $3\jtag_wb_addrsr_reg$next[28:0]$1295 29'00000000000000000000000000000 case - assign $1\fus_src1_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\jtag_wb_addrsr_reg$next[28:0]$1295 $2\jtag_wb_addrsr_reg$next[28:0]$1294 end sync always - update \fus_src1_i $0\fus_src1_i[63:0] + update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$1292 end - attribute \src "issuer_ls180.v:44051.3-44059.6" - process $proc$issuer_ls180.v:44051$2381 + attribute \src "libresoc.v:44367.3-44375.6" + process $proc$libresoc.v:44367$1296 assign { } { } assign { } { } - assign $0\dp_INT_ra_cr0_1$next[0:0]$2382 $1\dp_INT_ra_cr0_1$next[0:0]$2383 - attribute \src "issuer_ls180.v:44052.5-44052.29" + assign $0\jtag_wb_datasr_update_core$next[0:0]$1297 $1\jtag_wb_datasr_update_core$next[0:0]$1298 + attribute \src "libresoc.v:44368.5-44368.29" switch \initial - attribute \src "issuer_ls180.v:44052.9-44052.17" + attribute \src "libresoc.v:44368.9-44368.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_ra_cr0_1$next[0:0]$2383 1'0 - case - assign $1\dp_INT_ra_cr0_1$next[0:0]$2383 \rp_INT_ra_cr0_1 - end - sync always - update \dp_INT_ra_cr0_1$next $0\dp_INT_ra_cr0_1$next[0:0]$2382 - end - attribute \src "issuer_ls180.v:44060.3-44069.6" - process $proc$issuer_ls180.v:44060$2384 - assign { } { } - assign { } { } - assign $0\fus_src1_i$33[63:0]$2385 $1\fus_src1_i$33[63:0]$2386 - attribute \src "issuer_ls180.v:44061.5-44061.29" - switch \initial - attribute \src "issuer_ls180.v:44061.9-44061.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_INT_ra_cr0_1 - attribute \src "issuer_ls180.v:0.0-0.0" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$33[63:0]$2386 \int_src1__data_o + assign $1\jtag_wb_datasr_update_core$next[0:0]$1298 1'0 case - assign $1\fus_src1_i$33[63:0]$2386 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\jtag_wb_datasr_update_core$next[0:0]$1298 \jtag_wb_datasr_update end sync always - update \fus_src1_i$33 $0\fus_src1_i$33[63:0]$2385 + update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$1297 end - attribute \src "issuer_ls180.v:44070.3-44078.6" - process $proc$issuer_ls180.v:44070$2387 + attribute \src "libresoc.v:44376.3-44384.6" + process $proc$libresoc.v:44376$1299 assign { } { } assign { } { } - assign $0\dp_INT_ra_trap0_2$next[0:0]$2388 $1\dp_INT_ra_trap0_2$next[0:0]$2389 - attribute \src "issuer_ls180.v:44071.5-44071.29" + assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$1300 $1\jtag_wb_datasr_update_core_prev$next[0:0]$1301 + attribute \src "libresoc.v:44377.5-44377.29" switch \initial - attribute \src "issuer_ls180.v:44071.9-44071.17" + attribute \src "libresoc.v:44377.9-44377.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_ra_trap0_2$next[0:0]$2389 1'0 - case - assign $1\dp_INT_ra_trap0_2$next[0:0]$2389 \rp_INT_ra_trap0_2 - end - sync always - update \dp_INT_ra_trap0_2$next $0\dp_INT_ra_trap0_2$next[0:0]$2388 - end - attribute \src "issuer_ls180.v:44079.3-44088.6" - process $proc$issuer_ls180.v:44079$2390 - assign { } { } - assign { } { } - assign $0\fus_src1_i$36[63:0]$2391 $1\fus_src1_i$36[63:0]$2392 - attribute \src "issuer_ls180.v:44080.5-44080.29" - switch \initial - attribute \src "issuer_ls180.v:44080.9-44080.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_INT_ra_trap0_2 - attribute \src "issuer_ls180.v:0.0-0.0" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$36[63:0]$2392 \int_src1__data_o + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$1301 1'0 case - assign $1\fus_src1_i$36[63:0]$2392 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$1301 \jtag_wb_datasr_update_core end sync always - update \fus_src1_i$36 $0\fus_src1_i$36[63:0]$2391 + update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$1300 end - attribute \src "issuer_ls180.v:44089.3-44097.6" - process $proc$issuer_ls180.v:44089$2393 + attribute \src "libresoc.v:44385.3-44401.6" + process $proc$libresoc.v:44385$1302 assign { } { } assign { } { } - assign $0\dp_INT_ra_logical0_3$next[0:0]$2394 $1\dp_INT_ra_logical0_3$next[0:0]$2395 - attribute \src "issuer_ls180.v:44090.5-44090.29" + assign $0\jtag_wb_datasr__oe$next[1:0]$1303 $2\jtag_wb_datasr__oe$next[1:0]$1305 + attribute \src "libresoc.v:44386.5-44386.29" switch \initial - attribute \src "issuer_ls180.v:44090.9-44090.17" + attribute \src "libresoc.v:44386.9-44386.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + switch \$215 + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_logical0_3$next[0:0]$2395 1'0 - case - assign $1\dp_INT_ra_logical0_3$next[0:0]$2395 \rp_INT_ra_logical0_3 - end - sync always - update \dp_INT_ra_logical0_3$next $0\dp_INT_ra_logical0_3$next[0:0]$2394 - end - attribute \src "issuer_ls180.v:44098.3-44107.6" - process $proc$issuer_ls180.v:44098$2396 - assign { } { } - assign { } { } - assign $0\fus_src1_i$39[63:0]$2397 $1\fus_src1_i$39[63:0]$2398 - attribute \src "issuer_ls180.v:44099.5-44099.29" - switch \initial - attribute \src "issuer_ls180.v:44099.9-44099.17" - case 1'1 + assign $1\jtag_wb_datasr__oe$next[1:0]$1304 \jtag_wb_datasr_isir + attribute \src "libresoc.v:0.0-0.0" case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_INT_ra_logical0_3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 assign { } { } - assign $1\fus_src1_i$39[63:0]$2398 \int_src1__data_o - case - assign $1\fus_src1_i$39[63:0]$2398 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src1_i$39 $0\fus_src1_i$39[63:0]$2397 - end - attribute \src "issuer_ls180.v:44108.3-44116.6" - process $proc$issuer_ls180.v:44108$2399 - assign { } { } - assign { } { } - assign $0\dp_INT_ra_spr0_4$next[0:0]$2400 $1\dp_INT_ra_spr0_4$next[0:0]$2401 - attribute \src "issuer_ls180.v:44109.5-44109.29" - switch \initial - attribute \src "issuer_ls180.v:44109.9-44109.17" - case 1'1 - case + assign $1\jtag_wb_datasr__oe$next[1:0]$1304 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_spr0_4$next[0:0]$2401 1'0 + assign $2\jtag_wb_datasr__oe$next[1:0]$1305 2'00 case - assign $1\dp_INT_ra_spr0_4$next[0:0]$2401 \rp_INT_ra_spr0_4 + assign $2\jtag_wb_datasr__oe$next[1:0]$1305 $1\jtag_wb_datasr__oe$next[1:0]$1304 end sync always - update \dp_INT_ra_spr0_4$next $0\dp_INT_ra_spr0_4$next[0:0]$2400 + update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$1303 end - attribute \src "issuer_ls180.v:44117.3-44126.6" - process $proc$issuer_ls180.v:44117$2402 + attribute \src "libresoc.v:44402.3-44422.6" + process $proc$libresoc.v:44402$1306 assign { } { } assign { } { } - assign $0\fus_src1_i$42[63:0]$2403 $1\fus_src1_i$42[63:0]$2404 - attribute \src "issuer_ls180.v:44118.5-44118.29" - switch \initial - attribute \src "issuer_ls180.v:44118.9-44118.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_INT_ra_spr0_4 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src1_i$42[63:0]$2404 \int_src1__data_o - case - assign $1\fus_src1_i$42[63:0]$2404 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src1_i$42 $0\fus_src1_i$42[63:0]$2403 - end - attribute \src "issuer_ls180.v:44127.3-44135.6" - process $proc$issuer_ls180.v:44127$2405 assign { } { } assign { } { } - assign $0\dp_INT_ra_div0_5$next[0:0]$2406 $1\dp_INT_ra_div0_5$next[0:0]$2407 - attribute \src "issuer_ls180.v:44128.5-44128.29" + assign $0\jtag_wb_datasr_reg$next[63:0]$1307 $3\jtag_wb_datasr_reg$next[63:0]$1310 + attribute \src "libresoc.v:44403.5-44403.29" switch \initial - attribute \src "issuer_ls180.v:44128.9-44128.17" + attribute \src "libresoc.v:44403.9-44403.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" + switch \jtag_wb_datasr_shift + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_div0_5$next[0:0]$2407 1'0 - case - assign $1\dp_INT_ra_div0_5$next[0:0]$2407 \rp_INT_ra_div0_5 - end - sync always - update \dp_INT_ra_div0_5$next $0\dp_INT_ra_div0_5$next[0:0]$2406 - end - attribute \src "issuer_ls180.v:44136.3-44145.6" - process $proc$issuer_ls180.v:44136$2408 - assign { } { } - assign { } { } - assign $0\fus_src1_i$45[63:0]$2409 $1\fus_src1_i$45[63:0]$2410 - attribute \src "issuer_ls180.v:44137.5-44137.29" - switch \initial - attribute \src "issuer_ls180.v:44137.9-44137.17" - case 1'1 + assign $1\jtag_wb_datasr_reg$next[63:0]$1308 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } case + assign $1\jtag_wb_datasr_reg$next[63:0]$1308 \jtag_wb_datasr_reg end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_INT_ra_div0_5 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" + switch \jtag_wb_datasr_capture + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$45[63:0]$2410 \int_src1__data_o - case - assign $1\fus_src1_i$45[63:0]$2410 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src1_i$45 $0\fus_src1_i$45[63:0]$2409 - end - attribute \src "issuer_ls180.v:44146.3-44154.6" - process $proc$issuer_ls180.v:44146$2411 - assign { } { } - assign { } { } - assign $0\dp_INT_ra_mul0_6$next[0:0]$2412 $1\dp_INT_ra_mul0_6$next[0:0]$2413 - attribute \src "issuer_ls180.v:44147.5-44147.29" - switch \initial - attribute \src "issuer_ls180.v:44147.9-44147.17" - case 1'1 + assign $2\jtag_wb_datasr_reg$next[63:0]$1309 \jtag_wb_datasr__i case + assign $2\jtag_wb_datasr_reg$next[63:0]$1309 $1\jtag_wb_datasr_reg$next[63:0]$1308 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_ra_mul0_6$next[0:0]$2413 1'0 - case - assign $1\dp_INT_ra_mul0_6$next[0:0]$2413 \rp_INT_ra_mul0_6 - end - sync always - update \dp_INT_ra_mul0_6$next $0\dp_INT_ra_mul0_6$next[0:0]$2412 - end - attribute \src "issuer_ls180.v:44155.3-44164.6" - process $proc$issuer_ls180.v:44155$2414 - assign { } { } - assign { } { } - assign $0\fus_src1_i$48[63:0]$2415 $1\fus_src1_i$48[63:0]$2416 - attribute \src "issuer_ls180.v:44156.5-44156.29" - switch \initial - attribute \src "issuer_ls180.v:44156.9-44156.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_INT_ra_mul0_6 - attribute \src "issuer_ls180.v:0.0-0.0" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$48[63:0]$2416 \int_src1__data_o + assign $3\jtag_wb_datasr_reg$next[63:0]$1310 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\fus_src1_i$48[63:0]$2416 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\jtag_wb_datasr_reg$next[63:0]$1310 $2\jtag_wb_datasr_reg$next[63:0]$1309 end sync always - update \fus_src1_i$48 $0\fus_src1_i$48[63:0]$2415 + update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$1307 end - attribute \src "issuer_ls180.v:44165.3-44173.6" - process $proc$issuer_ls180.v:44165$2417 + attribute \src "libresoc.v:44423.3-44431.6" + process $proc$libresoc.v:44423$1311 assign { } { } assign { } { } - assign $0\dp_INT_ra_shiftrot0_7$next[0:0]$2418 $1\dp_INT_ra_shiftrot0_7$next[0:0]$2419 - attribute \src "issuer_ls180.v:44166.5-44166.29" + assign $0\dmi0_addrsr_update_core$next[0:0]$1312 $1\dmi0_addrsr_update_core$next[0:0]$1313 + attribute \src "libresoc.v:44424.5-44424.29" switch \initial - attribute \src "issuer_ls180.v:44166.9-44166.17" + attribute \src "libresoc.v:44424.9-44424.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2419 1'0 - case - assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2419 \rp_INT_ra_shiftrot0_7 - end - sync always - update \dp_INT_ra_shiftrot0_7$next $0\dp_INT_ra_shiftrot0_7$next[0:0]$2418 - end - attribute \src "issuer_ls180.v:44174.3-44183.6" - process $proc$issuer_ls180.v:44174$2420 - assign { } { } - assign { } { } - assign $0\fus_src1_i$51[63:0]$2421 $1\fus_src1_i$51[63:0]$2422 - attribute \src "issuer_ls180.v:44175.5-44175.29" - switch \initial - attribute \src "issuer_ls180.v:44175.9-44175.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_INT_ra_shiftrot0_7 - attribute \src "issuer_ls180.v:0.0-0.0" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$51[63:0]$2422 \int_src1__data_o + assign $1\dmi0_addrsr_update_core$next[0:0]$1313 1'0 case - assign $1\fus_src1_i$51[63:0]$2422 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dmi0_addrsr_update_core$next[0:0]$1313 \dmi0_addrsr_update end sync always - update \fus_src1_i$51 $0\fus_src1_i$51[63:0]$2421 + update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$1312 end - attribute \src "issuer_ls180.v:44184.3-44192.6" - process $proc$issuer_ls180.v:44184$2423 + attribute \src "libresoc.v:44432.3-44440.6" + process $proc$libresoc.v:44432$1314 assign { } { } assign { } { } - assign $0\dp_INT_ra_ldst0_8$next[0:0]$2424 $1\dp_INT_ra_ldst0_8$next[0:0]$2425 - attribute \src "issuer_ls180.v:44185.5-44185.29" + assign $0\dmi0_addrsr_update_core_prev$next[0:0]$1315 $1\dmi0_addrsr_update_core_prev$next[0:0]$1316 + attribute \src "libresoc.v:44433.5-44433.29" switch \initial - attribute \src "issuer_ls180.v:44185.9-44185.17" + attribute \src "libresoc.v:44433.9-44433.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_ra_ldst0_8$next[0:0]$2425 1'0 - case - assign $1\dp_INT_ra_ldst0_8$next[0:0]$2425 \rp_INT_ra_ldst0_8 - end - sync always - update \dp_INT_ra_ldst0_8$next $0\dp_INT_ra_ldst0_8$next[0:0]$2424 - end - attribute \src "issuer_ls180.v:44193.3-44202.6" - process $proc$issuer_ls180.v:44193$2426 - assign { } { } - assign { } { } - assign $0\fus_src1_i$54[63:0]$2427 $1\fus_src1_i$54[63:0]$2428 - attribute \src "issuer_ls180.v:44194.5-44194.29" - switch \initial - attribute \src "issuer_ls180.v:44194.9-44194.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_INT_ra_ldst0_8 - attribute \src "issuer_ls180.v:0.0-0.0" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$54[63:0]$2428 \int_src1__data_o + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$1316 1'0 case - assign $1\fus_src1_i$54[63:0]$2428 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$1316 \dmi0_addrsr_update_core end sync always - update \fus_src1_i$54 $0\fus_src1_i$54[63:0]$2427 + update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$1315 end - attribute \src "issuer_ls180.v:44203.3-44211.6" - process $proc$issuer_ls180.v:44203$2429 + attribute \src "libresoc.v:44441.3-44457.6" + process $proc$libresoc.v:44441$1317 assign { } { } assign { } { } - assign $0\dp_INT_rb_alu0_0$next[0:0]$2430 $1\dp_INT_rb_alu0_0$next[0:0]$2431 - attribute \src "issuer_ls180.v:44204.5-44204.29" + assign $0\dmi0_addrsr__oe$next[0:0]$1318 $2\dmi0_addrsr__oe$next[0:0]$1320 + attribute \src "libresoc.v:44442.5-44442.29" switch \initial - attribute \src "issuer_ls180.v:44204.9-44204.17" + attribute \src "libresoc.v:44442.9-44442.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + switch \$233 + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_alu0_0$next[0:0]$2431 1'0 - case - assign $1\dp_INT_rb_alu0_0$next[0:0]$2431 \rp_INT_rb_alu0_0 - end - sync always - update \dp_INT_rb_alu0_0$next $0\dp_INT_rb_alu0_0$next[0:0]$2430 - end - attribute \src "issuer_ls180.v:44212.3-44221.6" - process $proc$issuer_ls180.v:44212$2432 - assign { } { } - assign { } { } - assign $0\fus_src2_i[63:0] $1\fus_src2_i[63:0] - attribute \src "issuer_ls180.v:44213.5-44213.29" - switch \initial - attribute \src "issuer_ls180.v:44213.9-44213.17" - case 1'1 + assign $1\dmi0_addrsr__oe$next[0:0]$1319 \dmi0_addrsr_isir + attribute \src "libresoc.v:0.0-0.0" case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_INT_rb_alu0_0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 assign { } { } - assign $1\fus_src2_i[63:0] \int_src2__data_o - case - assign $1\fus_src2_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src2_i $0\fus_src2_i[63:0] - end - attribute \src "issuer_ls180.v:44222.3-44230.6" - process $proc$issuer_ls180.v:44222$2433 - assign { } { } - assign { } { } - assign $0\dp_INT_rb_cr0_1$next[0:0]$2434 $1\dp_INT_rb_cr0_1$next[0:0]$2435 - attribute \src "issuer_ls180.v:44223.5-44223.29" - switch \initial - attribute \src "issuer_ls180.v:44223.9-44223.17" - case 1'1 - case + assign $1\dmi0_addrsr__oe$next[0:0]$1319 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_cr0_1$next[0:0]$2435 1'0 + assign $2\dmi0_addrsr__oe$next[0:0]$1320 1'0 case - assign $1\dp_INT_rb_cr0_1$next[0:0]$2435 \rp_INT_rb_cr0_1 + assign $2\dmi0_addrsr__oe$next[0:0]$1320 $1\dmi0_addrsr__oe$next[0:0]$1319 end sync always - update \dp_INT_rb_cr0_1$next $0\dp_INT_rb_cr0_1$next[0:0]$2434 + update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$1318 end - attribute \src "issuer_ls180.v:44231.3-44240.6" - process $proc$issuer_ls180.v:44231$2436 + attribute \src "libresoc.v:44458.3-44478.6" + process $proc$libresoc.v:44458$1321 assign { } { } assign { } { } - assign $0\fus_src2_i$55[63:0]$2437 $1\fus_src2_i$55[63:0]$2438 - attribute \src "issuer_ls180.v:44232.5-44232.29" - switch \initial - attribute \src "issuer_ls180.v:44232.9-44232.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_INT_rb_cr0_1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src2_i$55[63:0]$2438 \int_src2__data_o - case - assign $1\fus_src2_i$55[63:0]$2438 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src2_i$55 $0\fus_src2_i$55[63:0]$2437 - end - attribute \src "issuer_ls180.v:44241.3-44249.6" - process $proc$issuer_ls180.v:44241$2439 assign { } { } assign { } { } - assign $0\dp_INT_rb_trap0_2$next[0:0]$2440 $1\dp_INT_rb_trap0_2$next[0:0]$2441 - attribute \src "issuer_ls180.v:44242.5-44242.29" + assign $0\dmi0_addrsr_reg$next[7:0]$1322 $3\dmi0_addrsr_reg$next[7:0]$1325 + attribute \src "libresoc.v:44459.5-44459.29" switch \initial - attribute \src "issuer_ls180.v:44242.9-44242.17" + attribute \src "libresoc.v:44459.9-44459.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" + switch \dmi0_addrsr_shift + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_trap0_2$next[0:0]$2441 1'0 - case - assign $1\dp_INT_rb_trap0_2$next[0:0]$2441 \rp_INT_rb_trap0_2 - end - sync always - update \dp_INT_rb_trap0_2$next $0\dp_INT_rb_trap0_2$next[0:0]$2440 - end - attribute \src "issuer_ls180.v:44250.3-44259.6" - process $proc$issuer_ls180.v:44250$2442 - assign { } { } - assign { } { } - assign $0\fus_src2_i$56[63:0]$2443 $1\fus_src2_i$56[63:0]$2444 - attribute \src "issuer_ls180.v:44251.5-44251.29" - switch \initial - attribute \src "issuer_ls180.v:44251.9-44251.17" - case 1'1 + assign $1\dmi0_addrsr_reg$next[7:0]$1323 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } case + assign $1\dmi0_addrsr_reg$next[7:0]$1323 \dmi0_addrsr_reg end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_INT_rb_trap0_2 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" + switch \dmi0_addrsr_capture + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$56[63:0]$2444 \int_src2__data_o - case - assign $1\fus_src2_i$56[63:0]$2444 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src2_i$56 $0\fus_src2_i$56[63:0]$2443 - end - attribute \src "issuer_ls180.v:44260.3-44268.6" - process $proc$issuer_ls180.v:44260$2445 - assign { } { } - assign { } { } - assign $0\dp_INT_rb_logical0_3$next[0:0]$2446 $1\dp_INT_rb_logical0_3$next[0:0]$2447 - attribute \src "issuer_ls180.v:44261.5-44261.29" - switch \initial - attribute \src "issuer_ls180.v:44261.9-44261.17" - case 1'1 + assign $2\dmi0_addrsr_reg$next[7:0]$1324 \dmi0_addrsr__i case + assign $2\dmi0_addrsr_reg$next[7:0]$1324 $1\dmi0_addrsr_reg$next[7:0]$1323 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_rb_logical0_3$next[0:0]$2447 1'0 - case - assign $1\dp_INT_rb_logical0_3$next[0:0]$2447 \rp_INT_rb_logical0_3 - end - sync always - update \dp_INT_rb_logical0_3$next $0\dp_INT_rb_logical0_3$next[0:0]$2446 - end - attribute \src "issuer_ls180.v:44269.3-44278.6" - process $proc$issuer_ls180.v:44269$2448 - assign { } { } - assign { } { } - assign $0\fus_src2_i$57[63:0]$2449 $1\fus_src2_i$57[63:0]$2450 - attribute \src "issuer_ls180.v:44270.5-44270.29" - switch \initial - attribute \src "issuer_ls180.v:44270.9-44270.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_INT_rb_logical0_3 - attribute \src "issuer_ls180.v:0.0-0.0" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$57[63:0]$2450 \int_src2__data_o + assign $3\dmi0_addrsr_reg$next[7:0]$1325 8'00000000 case - assign $1\fus_src2_i$57[63:0]$2450 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dmi0_addrsr_reg$next[7:0]$1325 $2\dmi0_addrsr_reg$next[7:0]$1324 end sync always - update \fus_src2_i$57 $0\fus_src2_i$57[63:0]$2449 + update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$1322 end - attribute \src "issuer_ls180.v:44279.3-44287.6" - process $proc$issuer_ls180.v:44279$2451 + attribute \src "libresoc.v:44479.3-44487.6" + process $proc$libresoc.v:44479$1326 assign { } { } assign { } { } - assign $0\dp_INT_rb_div0_4$next[0:0]$2452 $1\dp_INT_rb_div0_4$next[0:0]$2453 - attribute \src "issuer_ls180.v:44280.5-44280.29" + assign $0\dmi0_datasr_update_core$next[0:0]$1327 $1\dmi0_datasr_update_core$next[0:0]$1328 + attribute \src "libresoc.v:44480.5-44480.29" switch \initial - attribute \src "issuer_ls180.v:44280.9-44280.17" + attribute \src "libresoc.v:44480.9-44480.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_rb_div0_4$next[0:0]$2453 1'0 - case - assign $1\dp_INT_rb_div0_4$next[0:0]$2453 \rp_INT_rb_div0_4 - end - sync always - update \dp_INT_rb_div0_4$next $0\dp_INT_rb_div0_4$next[0:0]$2452 - end - attribute \src "issuer_ls180.v:44288.3-44297.6" - process $proc$issuer_ls180.v:44288$2454 - assign { } { } - assign { } { } - assign $0\fus_src2_i$58[63:0]$2455 $1\fus_src2_i$58[63:0]$2456 - attribute \src "issuer_ls180.v:44289.5-44289.29" - switch \initial - attribute \src "issuer_ls180.v:44289.9-44289.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_INT_rb_div0_4 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src2_i$58[63:0]$2456 \int_src2__data_o - case - assign $1\fus_src2_i$58[63:0]$2456 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src2_i$58 $0\fus_src2_i$58[63:0]$2455 - end - attribute \src "issuer_ls180.v:44298.3-44306.6" - process $proc$issuer_ls180.v:44298$2457 - assign { } { } - assign { } { } - assign $0\dp_INT_rb_mul0_5$next[0:0]$2458 $1\dp_INT_rb_mul0_5$next[0:0]$2459 - attribute \src "issuer_ls180.v:44299.5-44299.29" - switch \initial - attribute \src "issuer_ls180.v:44299.9-44299.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_rb_mul0_5$next[0:0]$2459 1'0 - case - assign $1\dp_INT_rb_mul0_5$next[0:0]$2459 \rp_INT_rb_mul0_5 - end - sync always - update \dp_INT_rb_mul0_5$next $0\dp_INT_rb_mul0_5$next[0:0]$2458 - end - attribute \src "issuer_ls180.v:44307.3-44316.6" - process $proc$issuer_ls180.v:44307$2460 - assign { } { } - assign { } { } - assign $0\fus_src2_i$59[63:0]$2461 $1\fus_src2_i$59[63:0]$2462 - attribute \src "issuer_ls180.v:44308.5-44308.29" - switch \initial - attribute \src "issuer_ls180.v:44308.9-44308.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_INT_rb_mul0_5 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src2_i$59[63:0]$2462 \int_src2__data_o - case - assign $1\fus_src2_i$59[63:0]$2462 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src2_i$59 $0\fus_src2_i$59[63:0]$2461 - end - attribute \src "issuer_ls180.v:44317.3-44325.6" - process $proc$issuer_ls180.v:44317$2463 - assign { } { } - assign { } { } - assign $0\dp_INT_rb_shiftrot0_6$next[0:0]$2464 $1\dp_INT_rb_shiftrot0_6$next[0:0]$2465 - attribute \src "issuer_ls180.v:44318.5-44318.29" - switch \initial - attribute \src "issuer_ls180.v:44318.9-44318.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2465 1'0 - case - assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2465 \rp_INT_rb_shiftrot0_6 - end - sync always - update \dp_INT_rb_shiftrot0_6$next $0\dp_INT_rb_shiftrot0_6$next[0:0]$2464 - end - attribute \src "issuer_ls180.v:44326.3-44335.6" - process $proc$issuer_ls180.v:44326$2466 - assign { } { } - assign { } { } - assign $0\fus_src2_i$60[63:0]$2467 $1\fus_src2_i$60[63:0]$2468 - attribute \src "issuer_ls180.v:44327.5-44327.29" - switch \initial - attribute \src "issuer_ls180.v:44327.9-44327.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_INT_rb_shiftrot0_6 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src2_i$60[63:0]$2468 \int_src2__data_o - case - assign $1\fus_src2_i$60[63:0]$2468 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src2_i$60 $0\fus_src2_i$60[63:0]$2467 - end - attribute \src "issuer_ls180.v:44336.3-44344.6" - process $proc$issuer_ls180.v:44336$2469 - assign { } { } - assign { } { } - assign $0\dp_INT_rb_ldst0_7$next[0:0]$2470 $1\dp_INT_rb_ldst0_7$next[0:0]$2471 - attribute \src "issuer_ls180.v:44337.5-44337.29" - switch \initial - attribute \src "issuer_ls180.v:44337.9-44337.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_rb_ldst0_7$next[0:0]$2471 1'0 - case - assign $1\dp_INT_rb_ldst0_7$next[0:0]$2471 \rp_INT_rb_ldst0_7 - end - sync always - update \dp_INT_rb_ldst0_7$next $0\dp_INT_rb_ldst0_7$next[0:0]$2470 - end - attribute \src "issuer_ls180.v:44345.3-44354.6" - process $proc$issuer_ls180.v:44345$2472 - assign { } { } - assign { } { } - assign $0\fus_src2_i$61[63:0]$2473 $1\fus_src2_i$61[63:0]$2474 - attribute \src "issuer_ls180.v:44346.5-44346.29" - switch \initial - attribute \src "issuer_ls180.v:44346.9-44346.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_INT_rb_ldst0_7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src2_i$61[63:0]$2474 \int_src2__data_o - case - assign $1\fus_src2_i$61[63:0]$2474 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src2_i$61 $0\fus_src2_i$61[63:0]$2473 - end - attribute \src "issuer_ls180.v:44355.3-44363.6" - process $proc$issuer_ls180.v:44355$2475 - assign { } { } - assign { } { } - assign $0\dp_INT_rc_shiftrot0_0$next[0:0]$2476 $1\dp_INT_rc_shiftrot0_0$next[0:0]$2477 - attribute \src "issuer_ls180.v:44356.5-44356.29" - switch \initial - attribute \src "issuer_ls180.v:44356.9-44356.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2477 1'0 - case - assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2477 \rp_INT_rc_shiftrot0_0 - end - sync always - update \dp_INT_rc_shiftrot0_0$next $0\dp_INT_rc_shiftrot0_0$next[0:0]$2476 - end - attribute \src "issuer_ls180.v:44364.3-44373.6" - process $proc$issuer_ls180.v:44364$2478 - assign { } { } - assign { } { } - assign $0\fus_src3_i[63:0] $1\fus_src3_i[63:0] - attribute \src "issuer_ls180.v:44365.5-44365.29" - switch \initial - attribute \src "issuer_ls180.v:44365.9-44365.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_INT_rc_shiftrot0_0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src3_i[63:0] \int_src3__data_o - case - assign $1\fus_src3_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src3_i $0\fus_src3_i[63:0] - end - attribute \src "issuer_ls180.v:44374.3-44382.6" - process $proc$issuer_ls180.v:44374$2479 - assign { } { } - assign { } { } - assign $0\dp_INT_rc_ldst0_1$next[0:0]$2480 $1\dp_INT_rc_ldst0_1$next[0:0]$2481 - attribute \src "issuer_ls180.v:44375.5-44375.29" - switch \initial - attribute \src "issuer_ls180.v:44375.9-44375.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_rc_ldst0_1$next[0:0]$2481 1'0 - case - assign $1\dp_INT_rc_ldst0_1$next[0:0]$2481 \rp_INT_rc_ldst0_1 - end - sync always - update \dp_INT_rc_ldst0_1$next $0\dp_INT_rc_ldst0_1$next[0:0]$2480 - end - attribute \src "issuer_ls180.v:44383.3-44392.6" - process $proc$issuer_ls180.v:44383$2482 - assign { } { } - assign { } { } - assign $0\fus_src3_i$62[63:0]$2483 $1\fus_src3_i$62[63:0]$2484 - attribute \src "issuer_ls180.v:44384.5-44384.29" - switch \initial - attribute \src "issuer_ls180.v:44384.9-44384.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_INT_rc_ldst0_1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src3_i$62[63:0]$2484 \int_src3__data_o - case - assign $1\fus_src3_i$62[63:0]$2484 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src3_i$62 $0\fus_src3_i$62[63:0]$2483 - end - attribute \src "issuer_ls180.v:44393.3-44419.6" - process $proc$issuer_ls180.v:44393$2485 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\counter$next[1:0]$2486 $4\counter$next[1:0]$2490 - attribute \src "issuer_ls180.v:44394.5-44394.29" - switch \initial - attribute \src "issuer_ls180.v:44394.9-44394.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" - switch \$200 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\counter$next[1:0]$2487 \$202 [1:0] - case - assign $1\counter$next[1:0]$2487 \counter - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\counter$next[1:0]$2488 $3\counter$next[1:0]$2489 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign { } { } - assign $3\counter$next[1:0]$2489 2'10 - case - assign $3\counter$next[1:0]$2489 $1\counter$next[1:0]$2487 - end - case - assign $2\counter$next[1:0]$2488 $1\counter$next[1:0]$2487 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\counter$next[1:0]$2490 2'00 - case - assign $4\counter$next[1:0]$2490 $2\counter$next[1:0]$2488 - end - sync always - update \counter$next $0\counter$next[1:0]$2486 - end - attribute \src "issuer_ls180.v:44420.3-44428.6" - process $proc$issuer_ls180.v:44420$2491 - assign { } { } - assign { } { } - assign $0\dp_XER_xer_so_alu0_0$next[0:0]$2492 $1\dp_XER_xer_so_alu0_0$next[0:0]$2493 - attribute \src "issuer_ls180.v:44421.5-44421.29" - switch \initial - attribute \src "issuer_ls180.v:44421.9-44421.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2493 1'0 - case - assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2493 \rp_XER_xer_so_alu0_0 - end - sync always - update \dp_XER_xer_so_alu0_0$next $0\dp_XER_xer_so_alu0_0$next[0:0]$2492 - end - attribute \src "issuer_ls180.v:44429.3-44438.6" - process $proc$issuer_ls180.v:44429$2494 - assign { } { } - assign { } { } - assign $0\fus_src3_i$63[0:0]$2495 $1\fus_src3_i$63[0:0]$2496 - attribute \src "issuer_ls180.v:44430.5-44430.29" - switch \initial - attribute \src "issuer_ls180.v:44430.9-44430.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_XER_xer_so_alu0_0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src3_i$63[0:0]$2496 \xer_src1__data_o [0] - case - assign $1\fus_src3_i$63[0:0]$2496 1'0 - end - sync always - update \fus_src3_i$63 $0\fus_src3_i$63[0:0]$2495 - end - attribute \src "issuer_ls180.v:44439.3-44447.6" - process $proc$issuer_ls180.v:44439$2497 - assign { } { } - assign { } { } - assign $0\dp_XER_xer_so_logical0_1$next[0:0]$2498 $1\dp_XER_xer_so_logical0_1$next[0:0]$2499 - attribute \src "issuer_ls180.v:44440.5-44440.29" - switch \initial - attribute \src "issuer_ls180.v:44440.9-44440.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2499 1'0 - case - assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2499 \rp_XER_xer_so_logical0_1 - end - sync always - update \dp_XER_xer_so_logical0_1$next $0\dp_XER_xer_so_logical0_1$next[0:0]$2498 - end - attribute \src "issuer_ls180.v:44448.3-44538.6" - process $proc$issuer_ls180.v:44448$2500 - assign { } { } - assign { } { } - assign { } { } - assign $0\corebusy_o[0:0] $2\corebusy_o[0:0] - attribute \src "issuer_ls180.v:44449.5-44449.29" - switch \initial - attribute \src "issuer_ls180.v:44449.9-44449.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" - switch \$205 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\corebusy_o[0:0] 1'1 - case - assign $1\corebusy_o[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\corebusy_o[0:0] $3\corebusy_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $3\corebusy_o[0:0] $1\corebusy_o[0:0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign { } { } - assign $3\corebusy_o[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $3\corebusy_o[0:0] $13\corebusy_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\corebusy_o[0:0] \fus_cu_busy_o - case - assign $4\corebusy_o[0:0] $1\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [1] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\corebusy_o[0:0] \fus_cu_busy_o$5 - case - assign $5\corebusy_o[0:0] $4\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\corebusy_o[0:0] \fus_cu_busy_o$8 - case - assign $6\corebusy_o[0:0] $5\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [3] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\corebusy_o[0:0] \fus_cu_busy_o$11 - case - assign $7\corebusy_o[0:0] $6\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [4] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $8\corebusy_o[0:0] \fus_cu_busy_o$14 - case - assign $8\corebusy_o[0:0] $7\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [5] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $9\corebusy_o[0:0] \fus_cu_busy_o$17 - case - assign $9\corebusy_o[0:0] $8\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [6] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $10\corebusy_o[0:0] \fus_cu_busy_o$20 - case - assign $10\corebusy_o[0:0] $9\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [7] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $11\corebusy_o[0:0] \fus_cu_busy_o$23 - case - assign $11\corebusy_o[0:0] $10\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [8] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $12\corebusy_o[0:0] \fus_cu_busy_o$26 - case - assign $12\corebusy_o[0:0] $11\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [9] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $13\corebusy_o[0:0] \fus_cu_busy_o$29 - case - assign $13\corebusy_o[0:0] $12\corebusy_o[0:0] - end - end - case - assign $2\corebusy_o[0:0] $1\corebusy_o[0:0] - end - sync always - update \corebusy_o $0\corebusy_o[0:0] - end - attribute \src "issuer_ls180.v:44539.3-44548.6" - process $proc$issuer_ls180.v:44539$2501 - assign { } { } - assign { } { } - assign $0\fus_src3_i$64[0:0]$2502 $1\fus_src3_i$64[0:0]$2503 - attribute \src "issuer_ls180.v:44540.5-44540.29" - switch \initial - attribute \src "issuer_ls180.v:44540.9-44540.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_XER_xer_so_logical0_1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src3_i$64[0:0]$2503 \xer_src1__data_o [0] - case - assign $1\fus_src3_i$64[0:0]$2503 1'0 - end - sync always - update \fus_src3_i$64 $0\fus_src3_i$64[0:0]$2502 - end - attribute \src "issuer_ls180.v:44549.3-44557.6" - process $proc$issuer_ls180.v:44549$2504 - assign { } { } - assign { } { } - assign $0\dp_XER_xer_so_spr0_2$next[0:0]$2505 $1\dp_XER_xer_so_spr0_2$next[0:0]$2506 - attribute \src "issuer_ls180.v:44550.5-44550.29" - switch \initial - attribute \src "issuer_ls180.v:44550.9-44550.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2506 1'0 - case - assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2506 \rp_XER_xer_so_spr0_2 - end - sync always - update \dp_XER_xer_so_spr0_2$next $0\dp_XER_xer_so_spr0_2$next[0:0]$2505 - end - attribute \src "issuer_ls180.v:44558.3-44567.6" - process $proc$issuer_ls180.v:44558$2507 - assign { } { } - assign { } { } - assign $0\fus_src4_i[0:0] $1\fus_src4_i[0:0] - attribute \src "issuer_ls180.v:44559.5-44559.29" - switch \initial - attribute \src "issuer_ls180.v:44559.9-44559.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_XER_xer_so_spr0_2 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src4_i[0:0] \xer_src1__data_o [0] - case - assign $1\fus_src4_i[0:0] 1'0 - end - sync always - update \fus_src4_i $0\fus_src4_i[0:0] - end - attribute \src "issuer_ls180.v:44568.3-44576.6" - process $proc$issuer_ls180.v:44568$2508 - assign { } { } - assign { } { } - assign $0\dp_XER_xer_so_div0_3$next[0:0]$2509 $1\dp_XER_xer_so_div0_3$next[0:0]$2510 - attribute \src "issuer_ls180.v:44569.5-44569.29" - switch \initial - attribute \src "issuer_ls180.v:44569.9-44569.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_XER_xer_so_div0_3$next[0:0]$2510 1'0 - case - assign $1\dp_XER_xer_so_div0_3$next[0:0]$2510 \rp_XER_xer_so_div0_3 - end - sync always - update \dp_XER_xer_so_div0_3$next $0\dp_XER_xer_so_div0_3$next[0:0]$2509 - end - attribute \src "issuer_ls180.v:44577.3-44597.6" - process $proc$issuer_ls180.v:44577$2511 - assign { } { } - assign { } { } - assign { } { } - assign $0\core_terminate_o$next[0:0]$2512 $3\core_terminate_o$next[0:0]$2515 - attribute \src "issuer_ls180.v:44578.5-44578.29" - switch \initial - attribute \src "issuer_ls180.v:44578.9-44578.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\core_terminate_o$next[0:0]$2513 $2\core_terminate_o$next[0:0]$2514 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign { } { } - assign $2\core_terminate_o$next[0:0]$2514 1'1 - case - assign $2\core_terminate_o$next[0:0]$2514 \core_terminate_o - end - case - assign $1\core_terminate_o$next[0:0]$2513 \core_terminate_o - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\core_terminate_o$next[0:0]$2515 1'0 - case - assign $3\core_terminate_o$next[0:0]$2515 $1\core_terminate_o$next[0:0]$2513 - end - sync always - update \core_terminate_o$next $0\core_terminate_o$next[0:0]$2512 - end - attribute \src "issuer_ls180.v:44598.3-44607.6" - process $proc$issuer_ls180.v:44598$2516 - assign { } { } - assign { } { } - assign $0\fus_src3_i$65[0:0]$2517 $1\fus_src3_i$65[0:0]$2518 - attribute \src "issuer_ls180.v:44599.5-44599.29" - switch \initial - attribute \src "issuer_ls180.v:44599.9-44599.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_XER_xer_so_div0_3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src3_i$65[0:0]$2518 \xer_src1__data_o [0] - case - assign $1\fus_src3_i$65[0:0]$2518 1'0 - end - sync always - update \fus_src3_i$65 $0\fus_src3_i$65[0:0]$2517 - end - attribute \src "issuer_ls180.v:44608.3-44616.6" - process $proc$issuer_ls180.v:44608$2519 - assign { } { } - assign { } { } - assign $0\dp_XER_xer_so_mul0_4$next[0:0]$2520 $1\dp_XER_xer_so_mul0_4$next[0:0]$2521 - attribute \src "issuer_ls180.v:44609.5-44609.29" - switch \initial - attribute \src "issuer_ls180.v:44609.9-44609.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2521 1'0 - case - assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2521 \rp_XER_xer_so_mul0_4 - end - sync always - update \dp_XER_xer_so_mul0_4$next $0\dp_XER_xer_so_mul0_4$next[0:0]$2520 - end - attribute \src "issuer_ls180.v:44617.3-44626.6" - process $proc$issuer_ls180.v:44617$2522 - assign { } { } - assign { } { } - assign $0\fus_src3_i$66[0:0]$2523 $1\fus_src3_i$66[0:0]$2524 - attribute \src "issuer_ls180.v:44618.5-44618.29" - switch \initial - attribute \src "issuer_ls180.v:44618.9-44618.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_XER_xer_so_mul0_4 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src3_i$66[0:0]$2524 \xer_src1__data_o [0] - case - assign $1\fus_src3_i$66[0:0]$2524 1'0 - end - sync always - update \fus_src3_i$66 $0\fus_src3_i$66[0:0]$2523 - end - attribute \src "issuer_ls180.v:44627.3-44635.6" - process $proc$issuer_ls180.v:44627$2525 - assign { } { } - assign { } { } - assign $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2526 $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2527 - attribute \src "issuer_ls180.v:44628.5-44628.29" - switch \initial - attribute \src "issuer_ls180.v:44628.9-44628.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2527 1'0 - case - assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2527 \rp_XER_xer_so_shiftrot0_5 - end - sync always - update \dp_XER_xer_so_shiftrot0_5$next $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2526 - end - attribute \src "issuer_ls180.v:44636.3-44664.6" - process $proc$issuer_ls180.v:44636$2528 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__insn_type[6:0] $1\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "issuer_ls180.v:44637.5-44637.29" - switch \initial - attribute \src "issuer_ls180.v:44637.9-44637.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_alu0__insn_type[6:0] $2\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__insn_type[6:0] $3\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__insn_type[6:0] \dec_ALU_ALU_ALU__insn_type - case - assign $3\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 - end - end - case - assign $1\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 - end - sync always - update \fus_oper_i_alu_alu0__insn_type $0\fus_oper_i_alu_alu0__insn_type[6:0] - end - attribute \src "issuer_ls180.v:44665.3-44674.6" - process $proc$issuer_ls180.v:44665$2529 - assign { } { } - assign { } { } - assign $0\fus_src4_i$67[0:0]$2530 $1\fus_src4_i$67[0:0]$2531 - attribute \src "issuer_ls180.v:44666.5-44666.29" - switch \initial - attribute \src "issuer_ls180.v:44666.9-44666.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_XER_xer_so_shiftrot0_5 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src4_i$67[0:0]$2531 \xer_src1__data_o [0] - case - assign $1\fus_src4_i$67[0:0]$2531 1'0 - end - sync always - update \fus_src4_i$67 $0\fus_src4_i$67[0:0]$2530 - end - attribute \src "issuer_ls180.v:44675.3-44683.6" - process $proc$issuer_ls180.v:44675$2532 - assign { } { } - assign { } { } - assign $0\dp_XER_xer_ca_alu0_0$next[0:0]$2533 $1\dp_XER_xer_ca_alu0_0$next[0:0]$2534 - attribute \src "issuer_ls180.v:44676.5-44676.29" - switch \initial - attribute \src "issuer_ls180.v:44676.9-44676.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2534 1'0 - case - assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2534 \rp_XER_xer_ca_alu0_0 - end - sync always - update \dp_XER_xer_ca_alu0_0$next $0\dp_XER_xer_ca_alu0_0$next[0:0]$2533 - end - attribute \src "issuer_ls180.v:44684.3-44693.6" - process $proc$issuer_ls180.v:44684$2535 - assign { } { } - assign { } { } - assign $0\fus_src4_i$68[1:0]$2536 $1\fus_src4_i$68[1:0]$2537 - attribute \src "issuer_ls180.v:44685.5-44685.29" - switch \initial - attribute \src "issuer_ls180.v:44685.9-44685.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_XER_xer_ca_alu0_0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src4_i$68[1:0]$2537 \xer_src2__data_o - case - assign $1\fus_src4_i$68[1:0]$2537 2'00 - end - sync always - update \fus_src4_i$68 $0\fus_src4_i$68[1:0]$2536 - end - attribute \src "issuer_ls180.v:44694.3-44722.6" - process $proc$issuer_ls180.v:44694$2538 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__fn_unit[11:0] $1\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "issuer_ls180.v:44695.5-44695.29" - switch \initial - attribute \src "issuer_ls180.v:44695.9-44695.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_alu0__fn_unit[11:0] $2\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__fn_unit[11:0] $3\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__fn_unit[11:0] \dec_ALU_ALU_ALU__fn_unit - case - assign $3\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 - end - end - case - assign $1\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 - end - sync always - update \fus_oper_i_alu_alu0__fn_unit $0\fus_oper_i_alu_alu0__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:44723.3-44731.6" - process $proc$issuer_ls180.v:44723$2539 - assign { } { } - assign { } { } - assign $0\dp_XER_xer_ca_spr0_1$next[0:0]$2540 $1\dp_XER_xer_ca_spr0_1$next[0:0]$2541 - attribute \src "issuer_ls180.v:44724.5-44724.29" - switch \initial - attribute \src "issuer_ls180.v:44724.9-44724.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2541 1'0 - case - assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2541 \rp_XER_xer_ca_spr0_1 - end - sync always - update \dp_XER_xer_ca_spr0_1$next $0\dp_XER_xer_ca_spr0_1$next[0:0]$2540 - end - attribute \src "issuer_ls180.v:44732.3-44741.6" - process $proc$issuer_ls180.v:44732$2542 - assign { } { } - assign { } { } - assign $0\fus_src6_i[1:0] $1\fus_src6_i[1:0] - attribute \src "issuer_ls180.v:44733.5-44733.29" - switch \initial - attribute \src "issuer_ls180.v:44733.9-44733.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_XER_xer_ca_spr0_1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src6_i[1:0] \xer_src2__data_o - case - assign $1\fus_src6_i[1:0] 2'00 - end - sync always - update \fus_src6_i $0\fus_src6_i[1:0] - end - attribute \src "issuer_ls180.v:44742.3-44750.6" - process $proc$issuer_ls180.v:44742$2543 - assign { } { } - assign { } { } - assign $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2544 $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2545 - attribute \src "issuer_ls180.v:44743.5-44743.29" - switch \initial - attribute \src "issuer_ls180.v:44743.9-44743.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2545 1'0 - case - assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2545 \rp_XER_xer_ca_shiftrot0_2 - end - sync always - update \dp_XER_xer_ca_shiftrot0_2$next $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2544 - end - attribute \src "issuer_ls180.v:44751.3-44760.6" - process $proc$issuer_ls180.v:44751$2546 - assign { } { } - assign { } { } - assign $0\fus_src5_i[1:0] $1\fus_src5_i[1:0] - attribute \src "issuer_ls180.v:44752.5-44752.29" - switch \initial - attribute \src "issuer_ls180.v:44752.9-44752.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_XER_xer_ca_shiftrot0_2 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src5_i[1:0] \xer_src2__data_o - case - assign $1\fus_src5_i[1:0] 2'00 - end - sync always - update \fus_src5_i $0\fus_src5_i[1:0] - end - attribute \src "issuer_ls180.v:44761.3-44790.6" - process $proc$issuer_ls180.v:44761$2547 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__imm_data__data[63:0] $1\fus_oper_i_alu_alu0__imm_data__data[63:0] - assign $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:44762.5-44762.29" - switch \initial - attribute \src "issuer_ls180.v:44762.9-44762.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] $2\fus_oper_i_alu_alu0__imm_data__data[63:0] - assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] - assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] } { \dec_ALU_ALU_ALU__imm_data__ok \dec_ALU_ALU_ALU__imm_data__data } - case - assign $3\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_alu0__imm_data__data $0\fus_oper_i_alu_alu0__imm_data__data[63:0] - update \fus_oper_i_alu_alu0__imm_data__ok $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:44791.3-44799.6" - process $proc$issuer_ls180.v:44791$2548 - assign { } { } - assign { } { } - assign $0\dp_XER_xer_ov_spr0_0$next[0:0]$2549 $1\dp_XER_xer_ov_spr0_0$next[0:0]$2550 - attribute \src "issuer_ls180.v:44792.5-44792.29" - switch \initial - attribute \src "issuer_ls180.v:44792.9-44792.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2550 1'0 - case - assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2550 \rp_XER_xer_ov_spr0_0 - end - sync always - update \dp_XER_xer_ov_spr0_0$next $0\dp_XER_xer_ov_spr0_0$next[0:0]$2549 - end - attribute \src "issuer_ls180.v:44800.3-44809.6" - process $proc$issuer_ls180.v:44800$2551 - assign { } { } - assign { } { } - assign $0\fus_src5_i$69[1:0]$2552 $1\fus_src5_i$69[1:0]$2553 - attribute \src "issuer_ls180.v:44801.5-44801.29" - switch \initial - attribute \src "issuer_ls180.v:44801.9-44801.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_XER_xer_ov_spr0_0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src5_i$69[1:0]$2553 \xer_src3__data_o - case - assign $1\fus_src5_i$69[1:0]$2553 2'00 - end - sync always - update \fus_src5_i$69 $0\fus_src5_i$69[1:0]$2552 - end - attribute \src "issuer_ls180.v:44810.3-44818.6" - process $proc$issuer_ls180.v:44810$2554 - assign { } { } - assign { } { } - assign $0\dp_CR_full_cr_cr0_0$next[0:0]$2555 $1\dp_CR_full_cr_cr0_0$next[0:0]$2556 - attribute \src "issuer_ls180.v:44811.5-44811.29" - switch \initial - attribute \src "issuer_ls180.v:44811.9-44811.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2556 1'0 - case - assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2556 \rp_CR_full_cr_cr0_0 - end - sync always - update \dp_CR_full_cr_cr0_0$next $0\dp_CR_full_cr_cr0_0$next[0:0]$2555 - end - attribute \src "issuer_ls180.v:44819.3-44828.6" - process $proc$issuer_ls180.v:44819$2557 - assign { } { } - assign { } { } - assign $0\fus_src3_i$70[31:0]$2558 $1\fus_src3_i$70[31:0]$2559 - attribute \src "issuer_ls180.v:44820.5-44820.29" - switch \initial - attribute \src "issuer_ls180.v:44820.9-44820.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_CR_full_cr_cr0_0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src3_i$70[31:0]$2559 \cr_full_rd__data_o - case - assign $1\fus_src3_i$70[31:0]$2559 0 - end - sync always - update \fus_src3_i$70 $0\fus_src3_i$70[31:0]$2558 - end - attribute \src "issuer_ls180.v:44829.3-44858.6" - process $proc$issuer_ls180.v:44829$2560 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__rc__ok[0:0] $1\fus_oper_i_alu_alu0__rc__ok[0:0] - assign $0\fus_oper_i_alu_alu0__rc__rc[0:0] $1\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "issuer_ls180.v:44830.5-44830.29" - switch \initial - attribute \src "issuer_ls180.v:44830.9-44830.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] $2\fus_oper_i_alu_alu0__rc__ok[0:0] - assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] $2\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__ok[0:0] - assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] } { \dec_ALU_ALU_ALU__rc__ok \dec_ALU_ALU_ALU__rc__rc } - case - assign $3\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 - assign $3\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 - assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_alu0__rc__ok $0\fus_oper_i_alu_alu0__rc__ok[0:0] - update \fus_oper_i_alu_alu0__rc__rc $0\fus_oper_i_alu_alu0__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:44859.3-44867.6" - process $proc$issuer_ls180.v:44859$2561 - assign { } { } - assign { } { } - assign $0\dp_CR_cr_a_cr0_0$next[0:0]$2562 $1\dp_CR_cr_a_cr0_0$next[0:0]$2563 - attribute \src "issuer_ls180.v:44860.5-44860.29" - switch \initial - attribute \src "issuer_ls180.v:44860.9-44860.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2563 1'0 - case - assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2563 \rp_CR_cr_a_cr0_0 - end - sync always - update \dp_CR_cr_a_cr0_0$next $0\dp_CR_cr_a_cr0_0$next[0:0]$2562 - end - attribute \src "issuer_ls180.v:44868.3-44877.6" - process $proc$issuer_ls180.v:44868$2564 - assign { } { } - assign { } { } - assign $0\fus_src4_i$71[3:0]$2565 $1\fus_src4_i$71[3:0]$2566 - attribute \src "issuer_ls180.v:44869.5-44869.29" - switch \initial - attribute \src "issuer_ls180.v:44869.9-44869.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_CR_cr_a_cr0_0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src4_i$71[3:0]$2566 \cr_src1__data_o - case - assign $1\fus_src4_i$71[3:0]$2566 4'0000 - end - sync always - update \fus_src4_i$71 $0\fus_src4_i$71[3:0]$2565 - end - attribute \src "issuer_ls180.v:44878.3-44886.6" - process $proc$issuer_ls180.v:44878$2567 - assign { } { } - assign { } { } - assign $0\dp_CR_cr_a_branch0_1$next[0:0]$2568 $1\dp_CR_cr_a_branch0_1$next[0:0]$2569 - attribute \src "issuer_ls180.v:44879.5-44879.29" - switch \initial - attribute \src "issuer_ls180.v:44879.9-44879.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2569 1'0 - case - assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2569 \rp_CR_cr_a_branch0_1 - end - sync always - update \dp_CR_cr_a_branch0_1$next $0\dp_CR_cr_a_branch0_1$next[0:0]$2568 - end - attribute \src "issuer_ls180.v:44887.3-44896.6" - process $proc$issuer_ls180.v:44887$2570 - assign { } { } - assign { } { } - assign $0\fus_src3_i$74[3:0]$2571 $1\fus_src3_i$74[3:0]$2572 - attribute \src "issuer_ls180.v:44888.5-44888.29" - switch \initial - attribute \src "issuer_ls180.v:44888.9-44888.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_CR_cr_a_branch0_1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src3_i$74[3:0]$2572 \cr_src1__data_o - case - assign $1\fus_src3_i$74[3:0]$2572 4'0000 - end - sync always - update \fus_src3_i$74 $0\fus_src3_i$74[3:0]$2571 - end - attribute \src "issuer_ls180.v:44897.3-44905.6" - process $proc$issuer_ls180.v:44897$2573 - assign { } { } - assign { } { } - assign $0\dp_CR_cr_b_cr0_0$next[0:0]$2574 $1\dp_CR_cr_b_cr0_0$next[0:0]$2575 - attribute \src "issuer_ls180.v:44898.5-44898.29" - switch \initial - attribute \src "issuer_ls180.v:44898.9-44898.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2575 1'0 - case - assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2575 \rp_CR_cr_b_cr0_0 - end - sync always - update \dp_CR_cr_b_cr0_0$next $0\dp_CR_cr_b_cr0_0$next[0:0]$2574 - end - attribute \src "issuer_ls180.v:44906.3-44915.6" - process $proc$issuer_ls180.v:44906$2576 - assign { } { } - assign { } { } - assign $0\fus_src5_i$75[3:0]$2577 $1\fus_src5_i$75[3:0]$2578 - attribute \src "issuer_ls180.v:44907.5-44907.29" - switch \initial - attribute \src "issuer_ls180.v:44907.9-44907.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_CR_cr_b_cr0_0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src5_i$75[3:0]$2578 \cr_src2__data_o - case - assign $1\fus_src5_i$75[3:0]$2578 4'0000 - end - sync always - update \fus_src5_i$75 $0\fus_src5_i$75[3:0]$2577 - end - attribute \src "issuer_ls180.v:44916.3-44945.6" - process $proc$issuer_ls180.v:44916$2579 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__oe__oe[0:0] $1\fus_oper_i_alu_alu0__oe__oe[0:0] - assign $0\fus_oper_i_alu_alu0__oe__ok[0:0] $1\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "issuer_ls180.v:44917.5-44917.29" - switch \initial - attribute \src "issuer_ls180.v:44917.9-44917.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] $2\fus_oper_i_alu_alu0__oe__oe[0:0] - assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] $2\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] - assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] } { \dec_ALU_ALU_ALU__oe__ok \dec_ALU_ALU_ALU__oe__oe } - case - assign $3\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 - assign $3\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 - assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_alu0__oe__oe $0\fus_oper_i_alu_alu0__oe__oe[0:0] - update \fus_oper_i_alu_alu0__oe__ok $0\fus_oper_i_alu_alu0__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:44946.3-44954.6" - process $proc$issuer_ls180.v:44946$2580 - assign { } { } - assign { } { } - assign $0\dp_CR_cr_c_cr0_0$next[0:0]$2581 $1\dp_CR_cr_c_cr0_0$next[0:0]$2582 - attribute \src "issuer_ls180.v:44947.5-44947.29" - switch \initial - attribute \src "issuer_ls180.v:44947.9-44947.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2582 1'0 - case - assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2582 \rp_CR_cr_c_cr0_0 - end - sync always - update \dp_CR_cr_c_cr0_0$next $0\dp_CR_cr_c_cr0_0$next[0:0]$2581 - end - attribute \src "issuer_ls180.v:44955.3-44964.6" - process $proc$issuer_ls180.v:44955$2583 - assign { } { } - assign { } { } - assign $0\fus_src6_i$76[3:0]$2584 $1\fus_src6_i$76[3:0]$2585 - attribute \src "issuer_ls180.v:44956.5-44956.29" - switch \initial - attribute \src "issuer_ls180.v:44956.9-44956.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_CR_cr_c_cr0_0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src6_i$76[3:0]$2585 \cr_src3__data_o - case - assign $1\fus_src6_i$76[3:0]$2585 4'0000 - end - sync always - update \fus_src6_i$76 $0\fus_src6_i$76[3:0]$2584 - end - attribute \src "issuer_ls180.v:44965.3-44973.6" - process $proc$issuer_ls180.v:44965$2586 - assign { } { } - assign { } { } - assign $0\dp_FAST_fast1_branch0_0$next[0:0]$2587 $1\dp_FAST_fast1_branch0_0$next[0:0]$2588 - attribute \src "issuer_ls180.v:44966.5-44966.29" - switch \initial - attribute \src "issuer_ls180.v:44966.9-44966.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2588 1'0 - case - assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2588 \rp_FAST_fast1_branch0_0 - end - sync always - update \dp_FAST_fast1_branch0_0$next $0\dp_FAST_fast1_branch0_0$next[0:0]$2587 - end - attribute \src "issuer_ls180.v:44974.3-44983.6" - process $proc$issuer_ls180.v:44974$2589 - assign { } { } - assign { } { } - assign $0\fus_src1_i$77[63:0]$2590 $1\fus_src1_i$77[63:0]$2591 - attribute \src "issuer_ls180.v:44975.5-44975.29" - switch \initial - attribute \src "issuer_ls180.v:44975.9-44975.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_FAST_fast1_branch0_0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src1_i$77[63:0]$2591 \fast_src1__data_o - case - assign $1\fus_src1_i$77[63:0]$2591 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src1_i$77 $0\fus_src1_i$77[63:0]$2590 - end - attribute \src "issuer_ls180.v:44984.3-44992.6" - process $proc$issuer_ls180.v:44984$2592 - assign { } { } - assign { } { } - assign $0\dp_FAST_fast1_trap0_1$next[0:0]$2593 $1\dp_FAST_fast1_trap0_1$next[0:0]$2594 - attribute \src "issuer_ls180.v:44985.5-44985.29" - switch \initial - attribute \src "issuer_ls180.v:44985.9-44985.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2594 1'0 - case - assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2594 \rp_FAST_fast1_trap0_1 - end - sync always - update \dp_FAST_fast1_trap0_1$next $0\dp_FAST_fast1_trap0_1$next[0:0]$2593 - end - attribute \src "issuer_ls180.v:44993.3-45002.6" - process $proc$issuer_ls180.v:44993$2595 - assign { } { } - assign { } { } - assign $0\fus_src3_i$78[63:0]$2596 $1\fus_src3_i$78[63:0]$2597 - attribute \src "issuer_ls180.v:44994.5-44994.29" - switch \initial - attribute \src "issuer_ls180.v:44994.9-44994.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_FAST_fast1_trap0_1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src3_i$78[63:0]$2597 \fast_src1__data_o - case - assign $1\fus_src3_i$78[63:0]$2597 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src3_i$78 $0\fus_src3_i$78[63:0]$2596 - end - attribute \src "issuer_ls180.v:45003.3-45031.6" - process $proc$issuer_ls180.v:45003$2598 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__invert_in[0:0] $1\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "issuer_ls180.v:45004.5-45004.29" - switch \initial - attribute \src "issuer_ls180.v:45004.9-45004.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_alu0__invert_in[0:0] $2\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__invert_in[0:0] $3\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__invert_in[0:0] \dec_ALU_ALU_ALU__invert_in - case - assign $3\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_alu0__invert_in $0\fus_oper_i_alu_alu0__invert_in[0:0] - end - attribute \src "issuer_ls180.v:45032.3-45040.6" - process $proc$issuer_ls180.v:45032$2599 - assign { } { } - assign { } { } - assign $0\dp_FAST_fast1_spr0_2$next[0:0]$2600 $1\dp_FAST_fast1_spr0_2$next[0:0]$2601 - attribute \src "issuer_ls180.v:45033.5-45033.29" - switch \initial - attribute \src "issuer_ls180.v:45033.9-45033.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2601 1'0 - case - assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2601 \rp_FAST_fast1_spr0_2 - end - sync always - update \dp_FAST_fast1_spr0_2$next $0\dp_FAST_fast1_spr0_2$next[0:0]$2600 - end - attribute \src "issuer_ls180.v:45041.3-45050.6" - process $proc$issuer_ls180.v:45041$2602 - assign { } { } - assign { } { } - assign $0\fus_src3_i$79[63:0]$2603 $1\fus_src3_i$79[63:0]$2604 - attribute \src "issuer_ls180.v:45042.5-45042.29" - switch \initial - attribute \src "issuer_ls180.v:45042.9-45042.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_FAST_fast1_spr0_2 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src3_i$79[63:0]$2604 \fast_src1__data_o - case - assign $1\fus_src3_i$79[63:0]$2604 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src3_i$79 $0\fus_src3_i$79[63:0]$2603 - end - attribute \src "issuer_ls180.v:45051.3-45059.6" - process $proc$issuer_ls180.v:45051$2605 - assign { } { } - assign { } { } - assign $0\dp_FAST_fast2_branch0_0$next[0:0]$2606 $1\dp_FAST_fast2_branch0_0$next[0:0]$2607 - attribute \src "issuer_ls180.v:45052.5-45052.29" - switch \initial - attribute \src "issuer_ls180.v:45052.9-45052.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2607 1'0 - case - assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2607 \rp_FAST_fast2_branch0_0 - end - sync always - update \dp_FAST_fast2_branch0_0$next $0\dp_FAST_fast2_branch0_0$next[0:0]$2606 - end - attribute \src "issuer_ls180.v:45060.3-45088.6" - process $proc$issuer_ls180.v:45060$2608 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__zero_a[0:0] $1\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "issuer_ls180.v:45061.5-45061.29" - switch \initial - attribute \src "issuer_ls180.v:45061.9-45061.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_alu0__zero_a[0:0] $2\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__zero_a[0:0] $3\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__zero_a[0:0] \dec_ALU_ALU_ALU__zero_a - case - assign $3\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_alu0__zero_a $0\fus_oper_i_alu_alu0__zero_a[0:0] - end - attribute \src "issuer_ls180.v:45089.3-45098.6" - process $proc$issuer_ls180.v:45089$2609 - assign { } { } - assign { } { } - assign $0\fus_src2_i$80[63:0]$2610 $1\fus_src2_i$80[63:0]$2611 - attribute \src "issuer_ls180.v:45090.5-45090.29" - switch \initial - attribute \src "issuer_ls180.v:45090.9-45090.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_FAST_fast2_branch0_0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src2_i$80[63:0]$2611 \fast_src2__data_o - case - assign $1\fus_src2_i$80[63:0]$2611 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src2_i$80 $0\fus_src2_i$80[63:0]$2610 - end - attribute \src "issuer_ls180.v:45099.3-45107.6" - process $proc$issuer_ls180.v:45099$2612 - assign { } { } - assign { } { } - assign $0\dp_FAST_fast2_trap0_1$next[0:0]$2613 $1\dp_FAST_fast2_trap0_1$next[0:0]$2614 - attribute \src "issuer_ls180.v:45100.5-45100.29" - switch \initial - attribute \src "issuer_ls180.v:45100.9-45100.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2614 1'0 - case - assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2614 \rp_FAST_fast2_trap0_1 - end - sync always - update \dp_FAST_fast2_trap0_1$next $0\dp_FAST_fast2_trap0_1$next[0:0]$2613 - end - attribute \src "issuer_ls180.v:45108.3-45117.6" - process $proc$issuer_ls180.v:45108$2615 - assign { } { } - assign { } { } - assign $0\fus_src4_i$81[63:0]$2616 $1\fus_src4_i$81[63:0]$2617 - attribute \src "issuer_ls180.v:45109.5-45109.29" - switch \initial - attribute \src "issuer_ls180.v:45109.9-45109.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_FAST_fast2_trap0_1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src4_i$81[63:0]$2617 \fast_src2__data_o - case - assign $1\fus_src4_i$81[63:0]$2617 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src4_i$81 $0\fus_src4_i$81[63:0]$2616 - end - attribute \src "issuer_ls180.v:45118.3-45146.6" - process $proc$issuer_ls180.v:45118$2618 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__invert_out[0:0] $1\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "issuer_ls180.v:45119.5-45119.29" - switch \initial - attribute \src "issuer_ls180.v:45119.9-45119.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_alu0__invert_out[0:0] $2\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__invert_out[0:0] $3\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__invert_out[0:0] \dec_ALU_ALU_ALU__invert_out - case - assign $3\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_alu0__invert_out $0\fus_oper_i_alu_alu0__invert_out[0:0] - end - attribute \src "issuer_ls180.v:45147.3-45155.6" - process $proc$issuer_ls180.v:45147$2619 - assign { } { } - assign { } { } - assign $0\dp_SPR_spr1_spr0_0$next[0:0]$2620 $1\dp_SPR_spr1_spr0_0$next[0:0]$2621 - attribute \src "issuer_ls180.v:45148.5-45148.29" - switch \initial - attribute \src "issuer_ls180.v:45148.9-45148.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2621 1'0 - case - assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2621 \rp_SPR_spr1_spr0_0 - end - sync always - update \dp_SPR_spr1_spr0_0$next $0\dp_SPR_spr1_spr0_0$next[0:0]$2620 - end - attribute \src "issuer_ls180.v:45156.3-45165.6" - process $proc$issuer_ls180.v:45156$2622 - assign { } { } - assign { } { } - assign $0\fus_src2_i$82[63:0]$2623 $1\fus_src2_i$82[63:0]$2624 - attribute \src "issuer_ls180.v:45157.5-45157.29" - switch \initial - attribute \src "issuer_ls180.v:45157.9-45157.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch \dp_SPR_spr1_spr0_0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src2_i$82[63:0]$2624 \spr_spr1__data_o - case - assign $1\fus_src2_i$82[63:0]$2624 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src2_i$82 $0\fus_src2_i$82[63:0]$2623 - end - attribute \src "issuer_ls180.v:45166.3-45194.6" - process $proc$issuer_ls180.v:45166$2625 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__write_cr0[0:0] $1\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "issuer_ls180.v:45167.5-45167.29" - switch \initial - attribute \src "issuer_ls180.v:45167.9-45167.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_alu0__write_cr0[0:0] $2\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] $3\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__write_cr0[0:0] \dec_ALU_ALU_ALU__write_cr0 - case - assign $3\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_alu0__write_cr0 $0\fus_oper_i_alu_alu0__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:45195.3-45203.6" - process $proc$issuer_ls180.v:45195$2626 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$next[0:0]$2627 $1\wr_pick_dly$next[0:0]$2628 - attribute \src "issuer_ls180.v:45196.5-45196.29" - switch \initial - attribute \src "issuer_ls180.v:45196.9-45196.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$next[0:0]$2628 1'0 - case - assign $1\wr_pick_dly$next[0:0]$2628 \wr_pick - end - sync always - update \wr_pick_dly$next $0\wr_pick_dly$next[0:0]$2627 - end - attribute \src "issuer_ls180.v:45204.3-45212.6" - process $proc$issuer_ls180.v:45204$2629 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$967$next[0:0]$2630 $1\wr_pick_dly$967$next[0:0]$2631 - attribute \src "issuer_ls180.v:45205.5-45205.29" - switch \initial - attribute \src "issuer_ls180.v:45205.9-45205.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$967$next[0:0]$2631 1'0 - case - assign $1\wr_pick_dly$967$next[0:0]$2631 \wr_pick$964 - end - sync always - update \wr_pick_dly$967$next $0\wr_pick_dly$967$next[0:0]$2630 - end - attribute \src "issuer_ls180.v:45213.3-45241.6" - process $proc$issuer_ls180.v:45213$2632 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__input_carry[1:0] $1\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "issuer_ls180.v:45214.5-45214.29" - switch \initial - attribute \src "issuer_ls180.v:45214.9-45214.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_alu0__input_carry[1:0] $2\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__input_carry[1:0] $3\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__input_carry[1:0] \dec_ALU_ALU_ALU__input_carry - case - assign $3\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 - end - end - case - assign $1\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 - end - sync always - update \fus_oper_i_alu_alu0__input_carry $0\fus_oper_i_alu_alu0__input_carry[1:0] - end - attribute \src "issuer_ls180.v:45242.3-45250.6" - process $proc$issuer_ls180.v:45242$2633 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$986$next[0:0]$2634 $1\wr_pick_dly$986$next[0:0]$2635 - attribute \src "issuer_ls180.v:45243.5-45243.29" - switch \initial - attribute \src "issuer_ls180.v:45243.9-45243.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$986$next[0:0]$2635 1'0 - case - assign $1\wr_pick_dly$986$next[0:0]$2635 \wr_pick$983 - end - sync always - update \wr_pick_dly$986$next $0\wr_pick_dly$986$next[0:0]$2634 - end - attribute \src "issuer_ls180.v:45251.3-45279.6" - process $proc$issuer_ls180.v:45251$2636 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__output_carry[0:0] $1\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "issuer_ls180.v:45252.5-45252.29" - switch \initial - attribute \src "issuer_ls180.v:45252.9-45252.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_alu0__output_carry[0:0] $2\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__output_carry[0:0] $3\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__output_carry[0:0] \dec_ALU_ALU_ALU__output_carry - case - assign $3\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_alu0__output_carry $0\fus_oper_i_alu_alu0__output_carry[0:0] - end - attribute \src "issuer_ls180.v:45280.3-45288.6" - process $proc$issuer_ls180.v:45280$2637 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1007$next[0:0]$2638 $1\wr_pick_dly$1007$next[0:0]$2639 - attribute \src "issuer_ls180.v:45281.5-45281.29" - switch \initial - attribute \src "issuer_ls180.v:45281.9-45281.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1007$next[0:0]$2639 1'0 - case - assign $1\wr_pick_dly$1007$next[0:0]$2639 \wr_pick$1004 - end - sync always - update \wr_pick_dly$1007$next $0\wr_pick_dly$1007$next[0:0]$2638 - end - attribute \src "issuer_ls180.v:45289.3-45297.6" - process $proc$issuer_ls180.v:45289$2640 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1025$next[0:0]$2641 $1\wr_pick_dly$1025$next[0:0]$2642 - attribute \src "issuer_ls180.v:45290.5-45290.29" - switch \initial - attribute \src "issuer_ls180.v:45290.9-45290.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1025$next[0:0]$2642 1'0 - case - assign $1\wr_pick_dly$1025$next[0:0]$2642 \wr_pick$1022 - end - sync always - update \wr_pick_dly$1025$next $0\wr_pick_dly$1025$next[0:0]$2641 - end - attribute \src "issuer_ls180.v:45298.3-45326.6" - process $proc$issuer_ls180.v:45298$2643 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__is_32bit[0:0] $1\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "issuer_ls180.v:45299.5-45299.29" - switch \initial - attribute \src "issuer_ls180.v:45299.9-45299.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_alu0__is_32bit[0:0] $2\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] $3\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__is_32bit[0:0] \dec_ALU_ALU_ALU__is_32bit - case - assign $3\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_alu0__is_32bit $0\fus_oper_i_alu_alu0__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:45327.3-45335.6" - process $proc$issuer_ls180.v:45327$2644 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1047$next[0:0]$2645 $1\wr_pick_dly$1047$next[0:0]$2646 - attribute \src "issuer_ls180.v:45328.5-45328.29" - switch \initial - attribute \src "issuer_ls180.v:45328.9-45328.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1047$next[0:0]$2646 1'0 - case - assign $1\wr_pick_dly$1047$next[0:0]$2646 \wr_pick$1044 - end - sync always - update \wr_pick_dly$1047$next $0\wr_pick_dly$1047$next[0:0]$2645 - end - attribute \src "issuer_ls180.v:45336.3-45364.6" - process $proc$issuer_ls180.v:45336$2647 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__is_signed[0:0] $1\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "issuer_ls180.v:45337.5-45337.29" - switch \initial - attribute \src "issuer_ls180.v:45337.9-45337.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_alu0__is_signed[0:0] $2\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__is_signed[0:0] $3\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__is_signed[0:0] \dec_ALU_ALU_ALU__is_signed - case - assign $3\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_alu0__is_signed $0\fus_oper_i_alu_alu0__is_signed[0:0] - end - attribute \src "issuer_ls180.v:45365.3-45373.6" - process $proc$issuer_ls180.v:45365$2648 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1067$next[0:0]$2649 $1\wr_pick_dly$1067$next[0:0]$2650 - attribute \src "issuer_ls180.v:45366.5-45366.29" - switch \initial - attribute \src "issuer_ls180.v:45366.9-45366.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1067$next[0:0]$2650 1'0 - case - assign $1\wr_pick_dly$1067$next[0:0]$2650 \wr_pick$1064 - end - sync always - update \wr_pick_dly$1067$next $0\wr_pick_dly$1067$next[0:0]$2649 - end - attribute \src "issuer_ls180.v:45374.3-45402.6" - process $proc$issuer_ls180.v:45374$2651 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__data_len[3:0] $1\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "issuer_ls180.v:45375.5-45375.29" - switch \initial - attribute \src "issuer_ls180.v:45375.9-45375.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_alu0__data_len[3:0] $2\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__data_len[3:0] $3\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__data_len[3:0] \dec_ALU_ALU_ALU__data_len - case - assign $3\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 - end - end - case - assign $1\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 - end - sync always - update \fus_oper_i_alu_alu0__data_len $0\fus_oper_i_alu_alu0__data_len[3:0] - end - attribute \src "issuer_ls180.v:45403.3-45411.6" - process $proc$issuer_ls180.v:45403$2652 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1087$next[0:0]$2653 $1\wr_pick_dly$1087$next[0:0]$2654 - attribute \src "issuer_ls180.v:45404.5-45404.29" - switch \initial - attribute \src "issuer_ls180.v:45404.9-45404.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1087$next[0:0]$2654 1'0 - case - assign $1\wr_pick_dly$1087$next[0:0]$2654 \wr_pick$1084 - end - sync always - update \wr_pick_dly$1087$next $0\wr_pick_dly$1087$next[0:0]$2653 - end - attribute \src "issuer_ls180.v:45412.3-45420.6" - process $proc$issuer_ls180.v:45412$2655 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1106$next[0:0]$2656 $1\wr_pick_dly$1106$next[0:0]$2657 - attribute \src "issuer_ls180.v:45413.5-45413.29" - switch \initial - attribute \src "issuer_ls180.v:45413.9-45413.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1106$next[0:0]$2657 1'0 - case - assign $1\wr_pick_dly$1106$next[0:0]$2657 \wr_pick$1103 - end - sync always - update \wr_pick_dly$1106$next $0\wr_pick_dly$1106$next[0:0]$2656 - end - attribute \src "issuer_ls180.v:45421.3-45449.6" - process $proc$issuer_ls180.v:45421$2658 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__insn[31:0] $1\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "issuer_ls180.v:45422.5-45422.29" - switch \initial - attribute \src "issuer_ls180.v:45422.9-45422.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_alu0__insn[31:0] $2\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__insn[31:0] 0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__insn[31:0] 0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__insn[31:0] $3\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__insn[31:0] \dec_ALU_ALU_ALU__insn - case - assign $3\fus_oper_i_alu_alu0__insn[31:0] 0 - end - end - case - assign $1\fus_oper_i_alu_alu0__insn[31:0] 0 - end - sync always - update \fus_oper_i_alu_alu0__insn $0\fus_oper_i_alu_alu0__insn[31:0] - end - attribute \src "issuer_ls180.v:45450.3-45458.6" - process $proc$issuer_ls180.v:45450$2659 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1124$next[0:0]$2660 $1\wr_pick_dly$1124$next[0:0]$2661 - attribute \src "issuer_ls180.v:45451.5-45451.29" - switch \initial - attribute \src "issuer_ls180.v:45451.9-45451.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1124$next[0:0]$2661 1'0 - case - assign $1\wr_pick_dly$1124$next[0:0]$2661 \wr_pick$1121 - end - sync always - update \wr_pick_dly$1124$next $0\wr_pick_dly$1124$next[0:0]$2660 - end - attribute \src "issuer_ls180.v:45459.3-45487.6" - process $proc$issuer_ls180.v:45459$2662 - assign { } { } - assign { } { } - assign $0\fus_cu_issue_i[0:0] $1\fus_cu_issue_i[0:0] - attribute \src "issuer_ls180.v:45460.5-45460.29" - switch \initial - attribute \src "issuer_ls180.v:45460.9-45460.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_issue_i[0:0] $2\fus_cu_issue_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_issue_i[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_issue_i[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_issue_i[0:0] $3\fus_cu_issue_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_issue_i[0:0] \issue_i - case - assign $3\fus_cu_issue_i[0:0] 1'0 - end - end - case - assign $1\fus_cu_issue_i[0:0] 1'0 - end - sync always - update \fus_cu_issue_i $0\fus_cu_issue_i[0:0] - end - attribute \src "issuer_ls180.v:45488.3-45496.6" - process $proc$issuer_ls180.v:45488$2663 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1197$next[0:0]$2664 $1\wr_pick_dly$1197$next[0:0]$2665 - attribute \src "issuer_ls180.v:45489.5-45489.29" - switch \initial - attribute \src "issuer_ls180.v:45489.9-45489.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1197$next[0:0]$2665 1'0 - case - assign $1\wr_pick_dly$1197$next[0:0]$2665 \wr_pick$1194 - end - sync always - update \wr_pick_dly$1197$next $0\wr_pick_dly$1197$next[0:0]$2664 - end - attribute \src "issuer_ls180.v:45497.3-45525.6" - process $proc$issuer_ls180.v:45497$2666 - assign { } { } - assign { } { } - assign $0\fus_cu_rdmaskn_i[3:0] $1\fus_cu_rdmaskn_i[3:0] - attribute \src "issuer_ls180.v:45498.5-45498.29" - switch \initial - attribute \src "issuer_ls180.v:45498.9-45498.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_rdmaskn_i[3:0] $2\fus_cu_rdmaskn_i[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_rdmaskn_i[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_rdmaskn_i[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_rdmaskn_i[3:0] $3\fus_cu_rdmaskn_i[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_rdmaskn_i[3:0] \$207 - case - assign $3\fus_cu_rdmaskn_i[3:0] 4'0000 - end - end - case - assign $1\fus_cu_rdmaskn_i[3:0] 4'0000 - end - sync always - update \fus_cu_rdmaskn_i $0\fus_cu_rdmaskn_i[3:0] - end - attribute \src "issuer_ls180.v:45526.3-45534.6" - process $proc$issuer_ls180.v:45526$2667 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1225$next[0:0]$2668 $1\wr_pick_dly$1225$next[0:0]$2669 - attribute \src "issuer_ls180.v:45527.5-45527.29" - switch \initial - attribute \src "issuer_ls180.v:45527.9-45527.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1225$next[0:0]$2669 1'0 - case - assign $1\wr_pick_dly$1225$next[0:0]$2669 \wr_pick$1222 - end - sync always - update \wr_pick_dly$1225$next $0\wr_pick_dly$1225$next[0:0]$2668 - end - attribute \src "issuer_ls180.v:45535.3-45543.6" - process $proc$issuer_ls180.v:45535$2670 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1245$next[0:0]$2671 $1\wr_pick_dly$1245$next[0:0]$2672 - attribute \src "issuer_ls180.v:45536.5-45536.29" - switch \initial - attribute \src "issuer_ls180.v:45536.9-45536.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1245$next[0:0]$2672 1'0 - case - assign $1\wr_pick_dly$1245$next[0:0]$2672 \wr_pick$1242 - end - sync always - update \wr_pick_dly$1245$next $0\wr_pick_dly$1245$next[0:0]$2671 - end - attribute \src "issuer_ls180.v:45544.3-45572.6" - process $proc$issuer_ls180.v:45544$2673 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_cr0__insn_type[6:0] $1\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "issuer_ls180.v:45545.5-45545.29" - switch \initial - attribute \src "issuer_ls180.v:45545.9-45545.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_cr0__insn_type[6:0] $2\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_cr0__insn_type[6:0] $3\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [1] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_cr0__insn_type[6:0] \dec_CR_CR_CR__insn_type - case - assign $3\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 - end - end - case - assign $1\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 - end - sync always - update \fus_oper_i_alu_cr0__insn_type $0\fus_oper_i_alu_cr0__insn_type[6:0] - end - attribute \src "issuer_ls180.v:45573.3-45581.6" - process $proc$issuer_ls180.v:45573$2674 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1265$next[0:0]$2675 $1\wr_pick_dly$1265$next[0:0]$2676 - attribute \src "issuer_ls180.v:45574.5-45574.29" - switch \initial - attribute \src "issuer_ls180.v:45574.9-45574.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1265$next[0:0]$2676 1'0 - case - assign $1\wr_pick_dly$1265$next[0:0]$2676 \wr_pick$1262 - end - sync always - update \wr_pick_dly$1265$next $0\wr_pick_dly$1265$next[0:0]$2675 - end - attribute \src "issuer_ls180.v:45582.3-45610.6" - process $proc$issuer_ls180.v:45582$2677 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_cr0__fn_unit[11:0] $1\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "issuer_ls180.v:45583.5-45583.29" - switch \initial - attribute \src "issuer_ls180.v:45583.9-45583.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_cr0__fn_unit[11:0] $2\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_cr0__fn_unit[11:0] $3\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [1] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_cr0__fn_unit[11:0] \dec_CR_CR_CR__fn_unit - case - assign $3\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 - end - end - case - assign $1\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 - end - sync always - update \fus_oper_i_alu_cr0__fn_unit $0\fus_oper_i_alu_cr0__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:45611.3-45619.6" - process $proc$issuer_ls180.v:45611$2678 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1285$next[0:0]$2679 $1\wr_pick_dly$1285$next[0:0]$2680 - attribute \src "issuer_ls180.v:45612.5-45612.29" - switch \initial - attribute \src "issuer_ls180.v:45612.9-45612.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1285$next[0:0]$2680 1'0 - case - assign $1\wr_pick_dly$1285$next[0:0]$2680 \wr_pick$1282 - end - sync always - update \wr_pick_dly$1285$next $0\wr_pick_dly$1285$next[0:0]$2679 - end - attribute \src "issuer_ls180.v:45620.3-45628.6" - process $proc$issuer_ls180.v:45620$2681 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1305$next[0:0]$2682 $1\wr_pick_dly$1305$next[0:0]$2683 - attribute \src "issuer_ls180.v:45621.5-45621.29" - switch \initial - attribute \src "issuer_ls180.v:45621.9-45621.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1305$next[0:0]$2683 1'0 - case - assign $1\wr_pick_dly$1305$next[0:0]$2683 \wr_pick$1302 - end - sync always - update \wr_pick_dly$1305$next $0\wr_pick_dly$1305$next[0:0]$2682 - end - attribute \src "issuer_ls180.v:45629.3-45657.6" - process $proc$issuer_ls180.v:45629$2684 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_cr0__insn[31:0] $1\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "issuer_ls180.v:45630.5-45630.29" - switch \initial - attribute \src "issuer_ls180.v:45630.9-45630.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_cr0__insn[31:0] $2\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_cr0__insn[31:0] 0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_cr0__insn[31:0] 0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_cr0__insn[31:0] $3\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [1] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_cr0__insn[31:0] \dec_CR_CR_CR__insn - case - assign $3\fus_oper_i_alu_cr0__insn[31:0] 0 - end - end - case - assign $1\fus_oper_i_alu_cr0__insn[31:0] 0 - end - sync always - update \fus_oper_i_alu_cr0__insn $0\fus_oper_i_alu_cr0__insn[31:0] - end - attribute \src "issuer_ls180.v:45658.3-45666.6" - process $proc$issuer_ls180.v:45658$2685 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1325$next[0:0]$2686 $1\wr_pick_dly$1325$next[0:0]$2687 - attribute \src "issuer_ls180.v:45659.5-45659.29" - switch \initial - attribute \src "issuer_ls180.v:45659.9-45659.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1325$next[0:0]$2687 1'0 - case - assign $1\wr_pick_dly$1325$next[0:0]$2687 \wr_pick$1322 - end - sync always - update \wr_pick_dly$1325$next $0\wr_pick_dly$1325$next[0:0]$2686 - end - attribute \src "issuer_ls180.v:45667.3-45695.6" - process $proc$issuer_ls180.v:45667$2688 - assign { } { } - assign { } { } - assign $0\fus_cu_issue_i$4[0:0]$2689 $1\fus_cu_issue_i$4[0:0]$2690 - attribute \src "issuer_ls180.v:45668.5-45668.29" - switch \initial - attribute \src "issuer_ls180.v:45668.9-45668.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_issue_i$4[0:0]$2690 $2\fus_cu_issue_i$4[0:0]$2691 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_issue_i$4[0:0]$2691 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_issue_i$4[0:0]$2691 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_issue_i$4[0:0]$2691 $3\fus_cu_issue_i$4[0:0]$2692 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [1] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_issue_i$4[0:0]$2692 \issue_i - case - assign $3\fus_cu_issue_i$4[0:0]$2692 1'0 - end - end - case - assign $1\fus_cu_issue_i$4[0:0]$2690 1'0 - end - sync always - update \fus_cu_issue_i$4 $0\fus_cu_issue_i$4[0:0]$2689 - end - attribute \src "issuer_ls180.v:45696.3-45704.6" - process $proc$issuer_ls180.v:45696$2693 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1372$next[0:0]$2694 $1\wr_pick_dly$1372$next[0:0]$2695 - attribute \src "issuer_ls180.v:45697.5-45697.29" - switch \initial - attribute \src "issuer_ls180.v:45697.9-45697.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1372$next[0:0]$2695 1'0 - case - assign $1\wr_pick_dly$1372$next[0:0]$2695 \wr_pick$1369 - end - sync always - update \wr_pick_dly$1372$next $0\wr_pick_dly$1372$next[0:0]$2694 - end - attribute \src "issuer_ls180.v:45705.3-45713.6" - process $proc$issuer_ls180.v:45705$2696 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1388$next[0:0]$2697 $1\wr_pick_dly$1388$next[0:0]$2698 - attribute \src "issuer_ls180.v:45706.5-45706.29" - switch \initial - attribute \src "issuer_ls180.v:45706.9-45706.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1388$next[0:0]$2698 1'0 - case - assign $1\wr_pick_dly$1388$next[0:0]$2698 \wr_pick$1385 - end - sync always - update \wr_pick_dly$1388$next $0\wr_pick_dly$1388$next[0:0]$2697 - end - attribute \src "issuer_ls180.v:45714.3-45742.6" - process $proc$issuer_ls180.v:45714$2699 - assign { } { } - assign { } { } - assign $0\fus_cu_rdmaskn_i$6[5:0]$2700 $1\fus_cu_rdmaskn_i$6[5:0]$2701 - attribute \src "issuer_ls180.v:45715.5-45715.29" - switch \initial - attribute \src "issuer_ls180.v:45715.9-45715.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_rdmaskn_i$6[5:0]$2701 $2\fus_cu_rdmaskn_i$6[5:0]$2702 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_rdmaskn_i$6[5:0]$2702 6'000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_rdmaskn_i$6[5:0]$2702 6'000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_rdmaskn_i$6[5:0]$2702 $3\fus_cu_rdmaskn_i$6[5:0]$2703 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [1] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_rdmaskn_i$6[5:0]$2703 \$229 - case - assign $3\fus_cu_rdmaskn_i$6[5:0]$2703 6'000000 - end - end - case - assign $1\fus_cu_rdmaskn_i$6[5:0]$2701 6'000000 - end - sync always - update \fus_cu_rdmaskn_i$6 $0\fus_cu_rdmaskn_i$6[5:0]$2700 - end - attribute \src "issuer_ls180.v:45743.3-45751.6" - process $proc$issuer_ls180.v:45743$2704 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1404$next[0:0]$2705 $1\wr_pick_dly$1404$next[0:0]$2706 - attribute \src "issuer_ls180.v:45744.5-45744.29" - switch \initial - attribute \src "issuer_ls180.v:45744.9-45744.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1404$next[0:0]$2706 1'0 - case - assign $1\wr_pick_dly$1404$next[0:0]$2706 \wr_pick$1401 - end - sync always - update \wr_pick_dly$1404$next $0\wr_pick_dly$1404$next[0:0]$2705 - end - attribute \src "issuer_ls180.v:45752.3-45780.6" - process $proc$issuer_ls180.v:45752$2707 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_branch0__cia[63:0] $1\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "issuer_ls180.v:45753.5-45753.29" - switch \initial - attribute \src "issuer_ls180.v:45753.9-45753.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_branch0__cia[63:0] $2\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_branch0__cia[63:0] $3\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_branch0__cia[63:0] \dec_BRANCH_BRANCH_BRANCH__cia - case - assign $3\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - end - case - assign $1\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_oper_i_alu_branch0__cia $0\fus_oper_i_alu_branch0__cia[63:0] - end - attribute \src "issuer_ls180.v:45781.3-45789.6" - process $proc$issuer_ls180.v:45781$2708 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1438$next[0:0]$2709 $1\wr_pick_dly$1438$next[0:0]$2710 - attribute \src "issuer_ls180.v:45782.5-45782.29" - switch \initial - attribute \src "issuer_ls180.v:45782.9-45782.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1438$next[0:0]$2710 1'0 - case - assign $1\wr_pick_dly$1438$next[0:0]$2710 \wr_pick$1435 - end - sync always - update \wr_pick_dly$1438$next $0\wr_pick_dly$1438$next[0:0]$2709 - end - attribute \src "issuer_ls180.v:45790.3-45798.6" - process $proc$issuer_ls180.v:45790$2711 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1454$next[0:0]$2712 $1\wr_pick_dly$1454$next[0:0]$2713 - attribute \src "issuer_ls180.v:45791.5-45791.29" - switch \initial - attribute \src "issuer_ls180.v:45791.9-45791.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1454$next[0:0]$2713 1'0 - case - assign $1\wr_pick_dly$1454$next[0:0]$2713 \wr_pick$1451 - end - sync always - update \wr_pick_dly$1454$next $0\wr_pick_dly$1454$next[0:0]$2712 - end - attribute \src "issuer_ls180.v:45799.3-45827.6" - process $proc$issuer_ls180.v:45799$2714 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_branch0__insn_type[6:0] $1\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "issuer_ls180.v:45800.5-45800.29" - switch \initial - attribute \src "issuer_ls180.v:45800.9-45800.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_branch0__insn_type[6:0] $2\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_branch0__insn_type[6:0] $3\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_branch0__insn_type[6:0] \dec_BRANCH_BRANCH_BRANCH__insn_type - case - assign $3\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 - end - end - case - assign $1\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 - end - sync always - update \fus_oper_i_alu_branch0__insn_type $0\fus_oper_i_alu_branch0__insn_type[6:0] - end - attribute \src "issuer_ls180.v:45828.3-45836.6" - process $proc$issuer_ls180.v:45828$2715 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1470$next[0:0]$2716 $1\wr_pick_dly$1470$next[0:0]$2717 - attribute \src "issuer_ls180.v:45829.5-45829.29" - switch \initial - attribute \src "issuer_ls180.v:45829.9-45829.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1470$next[0:0]$2717 1'0 - case - assign $1\wr_pick_dly$1470$next[0:0]$2717 \wr_pick$1467 - end - sync always - update \wr_pick_dly$1470$next $0\wr_pick_dly$1470$next[0:0]$2716 - end - attribute \src "issuer_ls180.v:45837.3-45865.6" - process $proc$issuer_ls180.v:45837$2718 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_branch0__fn_unit[11:0] $1\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "issuer_ls180.v:45838.5-45838.29" - switch \initial - attribute \src "issuer_ls180.v:45838.9-45838.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_branch0__fn_unit[11:0] $2\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_branch0__fn_unit[11:0] $3\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_branch0__fn_unit[11:0] \dec_BRANCH_BRANCH_BRANCH__fn_unit - case - assign $3\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 - end - end - case - assign $1\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 - end - sync always - update \fus_oper_i_alu_branch0__fn_unit $0\fus_oper_i_alu_branch0__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:45866.3-45874.6" - process $proc$issuer_ls180.v:45866$2719 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1486$next[0:0]$2720 $1\wr_pick_dly$1486$next[0:0]$2721 - attribute \src "issuer_ls180.v:45867.5-45867.29" - switch \initial - attribute \src "issuer_ls180.v:45867.9-45867.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1486$next[0:0]$2721 1'0 - case - assign $1\wr_pick_dly$1486$next[0:0]$2721 \wr_pick$1483 - end - sync always - update \wr_pick_dly$1486$next $0\wr_pick_dly$1486$next[0:0]$2720 - end - attribute \src "issuer_ls180.v:45875.3-45903.6" - process $proc$issuer_ls180.v:45875$2722 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_branch0__insn[31:0] $1\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "issuer_ls180.v:45876.5-45876.29" - switch \initial - attribute \src "issuer_ls180.v:45876.9-45876.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_branch0__insn[31:0] $2\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_branch0__insn[31:0] 0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_branch0__insn[31:0] 0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_branch0__insn[31:0] $3\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_branch0__insn[31:0] \dec_BRANCH_BRANCH_BRANCH__insn - case - assign $3\fus_oper_i_alu_branch0__insn[31:0] 0 - end - end - case - assign $1\fus_oper_i_alu_branch0__insn[31:0] 0 - end - sync always - update \fus_oper_i_alu_branch0__insn $0\fus_oper_i_alu_branch0__insn[31:0] - end - attribute \src "issuer_ls180.v:45904.3-45912.6" - process $proc$issuer_ls180.v:45904$2723 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1522$next[0:0]$2724 $1\wr_pick_dly$1522$next[0:0]$2725 - attribute \src "issuer_ls180.v:45905.5-45905.29" - switch \initial - attribute \src "issuer_ls180.v:45905.9-45905.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1522$next[0:0]$2725 1'0 - case - assign $1\wr_pick_dly$1522$next[0:0]$2725 \wr_pick$1519 - end - sync always - update \wr_pick_dly$1522$next $0\wr_pick_dly$1522$next[0:0]$2724 - end - attribute \src "issuer_ls180.v:45913.3-45921.6" - process $proc$issuer_ls180.v:45913$2726 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1538$next[0:0]$2727 $1\wr_pick_dly$1538$next[0:0]$2728 - attribute \src "issuer_ls180.v:45914.5-45914.29" - switch \initial - attribute \src "issuer_ls180.v:45914.9-45914.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1538$next[0:0]$2728 1'0 - case - assign $1\wr_pick_dly$1538$next[0:0]$2728 \wr_pick$1535 - end - sync always - update \wr_pick_dly$1538$next $0\wr_pick_dly$1538$next[0:0]$2727 - end - attribute \src "issuer_ls180.v:45922.3-45951.6" - process $proc$issuer_ls180.v:45922$2729 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_branch0__imm_data__data[63:0] $1\fus_oper_i_alu_branch0__imm_data__data[63:0] - assign $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:45923.5-45923.29" - switch \initial - attribute \src "issuer_ls180.v:45923.9-45923.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_branch0__imm_data__data[63:0] $2\fus_oper_i_alu_branch0__imm_data__data[63:0] - assign $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] $3\fus_oper_i_alu_branch0__imm_data__data[63:0] - assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] $3\fus_oper_i_alu_branch0__imm_data__data[63:0] } { \dec_BRANCH_BRANCH_BRANCH__imm_data__ok \dec_BRANCH_BRANCH_BRANCH__imm_data__data } - case - assign $3\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_branch0__imm_data__data $0\fus_oper_i_alu_branch0__imm_data__data[63:0] - update \fus_oper_i_alu_branch0__imm_data__ok $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:45952.3-45960.6" - process $proc$issuer_ls180.v:45952$2730 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1554$next[0:0]$2731 $1\wr_pick_dly$1554$next[0:0]$2732 - attribute \src "issuer_ls180.v:45953.5-45953.29" - switch \initial - attribute \src "issuer_ls180.v:45953.9-45953.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1554$next[0:0]$2732 1'0 - case - assign $1\wr_pick_dly$1554$next[0:0]$2732 \wr_pick$1551 - end - sync always - update \wr_pick_dly$1554$next $0\wr_pick_dly$1554$next[0:0]$2731 - end - attribute \src "issuer_ls180.v:45961.3-45969.6" - process $proc$issuer_ls180.v:45961$2733 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1570$next[0:0]$2734 $1\wr_pick_dly$1570$next[0:0]$2735 - attribute \src "issuer_ls180.v:45962.5-45962.29" - switch \initial - attribute \src "issuer_ls180.v:45962.9-45962.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1570$next[0:0]$2735 1'0 - case - assign $1\wr_pick_dly$1570$next[0:0]$2735 \wr_pick$1567 - end - sync always - update \wr_pick_dly$1570$next $0\wr_pick_dly$1570$next[0:0]$2734 - end - attribute \src "issuer_ls180.v:45970.3-45978.6" - process $proc$issuer_ls180.v:45970$2736 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1612$next[0:0]$2737 $1\wr_pick_dly$1612$next[0:0]$2738 - attribute \src "issuer_ls180.v:45971.5-45971.29" - switch \initial - attribute \src "issuer_ls180.v:45971.9-45971.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1612$next[0:0]$2738 1'0 - case - assign $1\wr_pick_dly$1612$next[0:0]$2738 \wr_pick$1609 - end - sync always - update \wr_pick_dly$1612$next $0\wr_pick_dly$1612$next[0:0]$2737 - end - attribute \src "issuer_ls180.v:45979.3-46007.6" - process $proc$issuer_ls180.v:45979$2739 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_branch0__lk[0:0] $1\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "issuer_ls180.v:45980.5-45980.29" - switch \initial - attribute \src "issuer_ls180.v:45980.9-45980.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_branch0__lk[0:0] $2\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_branch0__lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_branch0__lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_branch0__lk[0:0] $3\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_branch0__lk[0:0] \dec_BRANCH_BRANCH_BRANCH__lk - case - assign $3\fus_oper_i_alu_branch0__lk[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_branch0__lk[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_branch0__lk $0\fus_oper_i_alu_branch0__lk[0:0] - end - attribute \src "issuer_ls180.v:46008.3-46016.6" - process $proc$issuer_ls180.v:46008$2740 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1631$next[0:0]$2741 $1\wr_pick_dly$1631$next[0:0]$2742 - attribute \src "issuer_ls180.v:46009.5-46009.29" - switch \initial - attribute \src "issuer_ls180.v:46009.9-46009.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1631$next[0:0]$2742 1'0 - case - assign $1\wr_pick_dly$1631$next[0:0]$2742 \wr_pick$1628 - end - sync always - update \wr_pick_dly$1631$next $0\wr_pick_dly$1631$next[0:0]$2741 - end - attribute \src "issuer_ls180.v:46017.3-46045.6" - process $proc$issuer_ls180.v:46017$2743 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_branch0__is_32bit[0:0] $1\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "issuer_ls180.v:46018.5-46018.29" - switch \initial - attribute \src "issuer_ls180.v:46018.9-46018.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] $2\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] $3\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_branch0__is_32bit[0:0] \dec_BRANCH_BRANCH_BRANCH__is_32bit - case - assign $3\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_branch0__is_32bit $0\fus_oper_i_alu_branch0__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:46046.3-46054.6" - process $proc$issuer_ls180.v:46046$2744 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1647$next[0:0]$2745 $1\wr_pick_dly$1647$next[0:0]$2746 - attribute \src "issuer_ls180.v:46047.5-46047.29" - switch \initial - attribute \src "issuer_ls180.v:46047.9-46047.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1647$next[0:0]$2746 1'0 - case - assign $1\wr_pick_dly$1647$next[0:0]$2746 \wr_pick$1644 - end - sync always - update \wr_pick_dly$1647$next $0\wr_pick_dly$1647$next[0:0]$2745 - end - attribute \src "issuer_ls180.v:46055.3-46063.6" - process $proc$issuer_ls180.v:46055$2747 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1663$next[0:0]$2748 $1\wr_pick_dly$1663$next[0:0]$2749 - attribute \src "issuer_ls180.v:46056.5-46056.29" - switch \initial - attribute \src "issuer_ls180.v:46056.9-46056.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1663$next[0:0]$2749 1'0 - case - assign $1\wr_pick_dly$1663$next[0:0]$2749 \wr_pick$1660 - end - sync always - update \wr_pick_dly$1663$next $0\wr_pick_dly$1663$next[0:0]$2748 - end - attribute \src "issuer_ls180.v:46064.3-46092.6" - process $proc$issuer_ls180.v:46064$2750 - assign { } { } - assign { } { } - assign $0\fus_cu_issue_i$7[0:0]$2751 $1\fus_cu_issue_i$7[0:0]$2752 - attribute \src "issuer_ls180.v:46065.5-46065.29" - switch \initial - attribute \src "issuer_ls180.v:46065.9-46065.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_issue_i$7[0:0]$2752 $2\fus_cu_issue_i$7[0:0]$2753 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_issue_i$7[0:0]$2753 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_issue_i$7[0:0]$2753 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_issue_i$7[0:0]$2753 $3\fus_cu_issue_i$7[0:0]$2754 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_issue_i$7[0:0]$2754 \issue_i - case - assign $3\fus_cu_issue_i$7[0:0]$2754 1'0 - end - end - case - assign $1\fus_cu_issue_i$7[0:0]$2752 1'0 - end - sync always - update \fus_cu_issue_i$7 $0\fus_cu_issue_i$7[0:0]$2751 - end - attribute \src "issuer_ls180.v:46093.3-46101.6" - process $proc$issuer_ls180.v:46093$2755 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1679$next[0:0]$2756 $1\wr_pick_dly$1679$next[0:0]$2757 - attribute \src "issuer_ls180.v:46094.5-46094.29" - switch \initial - attribute \src "issuer_ls180.v:46094.9-46094.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1679$next[0:0]$2757 1'0 - case - assign $1\wr_pick_dly$1679$next[0:0]$2757 \wr_pick$1676 - end - sync always - update \wr_pick_dly$1679$next $0\wr_pick_dly$1679$next[0:0]$2756 - end - attribute \src "issuer_ls180.v:46102.3-46130.6" - process $proc$issuer_ls180.v:46102$2758 - assign { } { } - assign { } { } - assign $0\fus_cu_rdmaskn_i$9[2:0]$2759 $1\fus_cu_rdmaskn_i$9[2:0]$2760 - attribute \src "issuer_ls180.v:46103.5-46103.29" - switch \initial - attribute \src "issuer_ls180.v:46103.9-46103.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_rdmaskn_i$9[2:0]$2760 $2\fus_cu_rdmaskn_i$9[2:0]$2761 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_rdmaskn_i$9[2:0]$2761 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_rdmaskn_i$9[2:0]$2761 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_rdmaskn_i$9[2:0]$2761 $3\fus_cu_rdmaskn_i$9[2:0]$2762 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_rdmaskn_i$9[2:0]$2762 \$231 - case - assign $3\fus_cu_rdmaskn_i$9[2:0]$2762 3'000 - end - end - case - assign $1\fus_cu_rdmaskn_i$9[2:0]$2760 3'000 - end - sync always - update \fus_cu_rdmaskn_i$9 $0\fus_cu_rdmaskn_i$9[2:0]$2759 - end - attribute \src "issuer_ls180.v:46131.3-46139.6" - process $proc$issuer_ls180.v:46131$2763 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1723$next[0:0]$2764 $1\wr_pick_dly$1723$next[0:0]$2765 - attribute \src "issuer_ls180.v:46132.5-46132.29" - switch \initial - attribute \src "issuer_ls180.v:46132.9-46132.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1723$next[0:0]$2765 1'0 - case - assign $1\wr_pick_dly$1723$next[0:0]$2765 \wr_pick$1720 - end - sync always - update \wr_pick_dly$1723$next $0\wr_pick_dly$1723$next[0:0]$2764 - end - attribute \src "issuer_ls180.v:46140.3-46148.6" - process $proc$issuer_ls180.v:46140$2766 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1739$next[0:0]$2767 $1\wr_pick_dly$1739$next[0:0]$2768 - attribute \src "issuer_ls180.v:46141.5-46141.29" - switch \initial - attribute \src "issuer_ls180.v:46141.9-46141.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1739$next[0:0]$2768 1'0 - case - assign $1\wr_pick_dly$1739$next[0:0]$2768 \wr_pick$1736 - end - sync always - update \wr_pick_dly$1739$next $0\wr_pick_dly$1739$next[0:0]$2767 - end - attribute \src "issuer_ls180.v:46149.3-46177.6" - process $proc$issuer_ls180.v:46149$2769 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_trap0__insn_type[6:0] $1\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "issuer_ls180.v:46150.5-46150.29" - switch \initial - attribute \src "issuer_ls180.v:46150.9-46150.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_trap0__insn_type[6:0] $2\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_trap0__insn_type[6:0] $3\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [3] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_trap0__insn_type[6:0] \core_core_insn_type - case - assign $3\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 - end - end - case - assign $1\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 - end - sync always - update \fus_oper_i_alu_trap0__insn_type $0\fus_oper_i_alu_trap0__insn_type[6:0] - end - attribute \src "issuer_ls180.v:46178.3-46186.6" - process $proc$issuer_ls180.v:46178$2770 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1763$next[0:0]$2771 $1\wr_pick_dly$1763$next[0:0]$2772 - attribute \src "issuer_ls180.v:46179.5-46179.29" - switch \initial - attribute \src "issuer_ls180.v:46179.9-46179.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1763$next[0:0]$2772 1'0 - case - assign $1\wr_pick_dly$1763$next[0:0]$2772 \wr_pick$1760 - end - sync always - update \wr_pick_dly$1763$next $0\wr_pick_dly$1763$next[0:0]$2771 - end - attribute \src "issuer_ls180.v:46187.3-46215.6" - process $proc$issuer_ls180.v:46187$2773 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_trap0__fn_unit[11:0] $1\fus_oper_i_alu_trap0__fn_unit[11:0] - attribute \src "issuer_ls180.v:46188.5-46188.29" - switch \initial - attribute \src "issuer_ls180.v:46188.9-46188.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_trap0__fn_unit[11:0] $2\fus_oper_i_alu_trap0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_trap0__fn_unit[11:0] 12'000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_trap0__fn_unit[11:0] 12'000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_trap0__fn_unit[11:0] $3\fus_oper_i_alu_trap0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [3] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_trap0__fn_unit[11:0] \core_core_fn_unit - case - assign $3\fus_oper_i_alu_trap0__fn_unit[11:0] 12'000000000000 - end - end - case - assign $1\fus_oper_i_alu_trap0__fn_unit[11:0] 12'000000000000 - end - sync always - update \fus_oper_i_alu_trap0__fn_unit $0\fus_oper_i_alu_trap0__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:46216.3-46224.6" - process $proc$issuer_ls180.v:46216$2774 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1783$next[0:0]$2775 $1\wr_pick_dly$1783$next[0:0]$2776 - attribute \src "issuer_ls180.v:46217.5-46217.29" - switch \initial - attribute \src "issuer_ls180.v:46217.9-46217.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1783$next[0:0]$2776 1'0 - case - assign $1\wr_pick_dly$1783$next[0:0]$2776 \wr_pick$1780 - end - sync always - update \wr_pick_dly$1783$next $0\wr_pick_dly$1783$next[0:0]$2775 - end - attribute \src "issuer_ls180.v:46225.3-46253.6" - process $proc$issuer_ls180.v:46225$2777 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_trap0__insn[31:0] $1\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "issuer_ls180.v:46226.5-46226.29" - switch \initial - attribute \src "issuer_ls180.v:46226.9-46226.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_trap0__insn[31:0] $2\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_trap0__insn[31:0] 0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_trap0__insn[31:0] 0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_trap0__insn[31:0] $3\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [3] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_trap0__insn[31:0] \core_core_insn - case - assign $3\fus_oper_i_alu_trap0__insn[31:0] 0 - end - end - case - assign $1\fus_oper_i_alu_trap0__insn[31:0] 0 - end - sync always - update \fus_oper_i_alu_trap0__insn $0\fus_oper_i_alu_trap0__insn[31:0] - end - attribute \src "issuer_ls180.v:46254.3-46282.6" - process $proc$issuer_ls180.v:46254$2778 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_trap0__msr[63:0] $1\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "issuer_ls180.v:46255.5-46255.29" - switch \initial - attribute \src "issuer_ls180.v:46255.9-46255.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_trap0__msr[63:0] $2\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_trap0__msr[63:0] $3\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [3] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_trap0__msr[63:0] \core_core_msr - case - assign $3\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - end - case - assign $1\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_oper_i_alu_trap0__msr $0\fus_oper_i_alu_trap0__msr[63:0] - end - attribute \src "issuer_ls180.v:46283.3-46311.6" - process $proc$issuer_ls180.v:46283$2779 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_trap0__cia[63:0] $1\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "issuer_ls180.v:46284.5-46284.29" - switch \initial - attribute \src "issuer_ls180.v:46284.9-46284.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_trap0__cia[63:0] $2\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_trap0__cia[63:0] $3\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [3] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_trap0__cia[63:0] \core_core_cia - case - assign $3\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - end - case - assign $1\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_oper_i_alu_trap0__cia $0\fus_oper_i_alu_trap0__cia[63:0] - end - attribute \src "issuer_ls180.v:46312.3-46340.6" - process $proc$issuer_ls180.v:46312$2780 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_trap0__is_32bit[0:0] $1\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "issuer_ls180.v:46313.5-46313.29" - switch \initial - attribute \src "issuer_ls180.v:46313.9-46313.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] $2\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] $3\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [3] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_trap0__is_32bit[0:0] \core_core_is_32bit - case - assign $3\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_trap0__is_32bit $0\fus_oper_i_alu_trap0__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:46341.3-46369.6" - process $proc$issuer_ls180.v:46341$2781 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_trap0__traptype[6:0] $1\fus_oper_i_alu_trap0__traptype[6:0] - attribute \src "issuer_ls180.v:46342.5-46342.29" - switch \initial - attribute \src "issuer_ls180.v:46342.9-46342.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_trap0__traptype[6:0] $2\fus_oper_i_alu_trap0__traptype[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_trap0__traptype[6:0] 7'0000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_trap0__traptype[6:0] 7'0000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_trap0__traptype[6:0] $3\fus_oper_i_alu_trap0__traptype[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [3] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_trap0__traptype[6:0] \core_core_traptype - case - assign $3\fus_oper_i_alu_trap0__traptype[6:0] 7'0000000 - end - end - case - assign $1\fus_oper_i_alu_trap0__traptype[6:0] 7'0000000 - end - sync always - update \fus_oper_i_alu_trap0__traptype $0\fus_oper_i_alu_trap0__traptype[6:0] - end - attribute \src "issuer_ls180.v:46370.3-46398.6" - process $proc$issuer_ls180.v:46370$2782 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_trap0__trapaddr[12:0] $1\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "issuer_ls180.v:46371.5-46371.29" - switch \initial - attribute \src "issuer_ls180.v:46371.9-46371.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] $2\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] $3\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [3] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_trap0__trapaddr[12:0] \core_core_trapaddr - case - assign $3\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 - end - end - case - assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 - end - sync always - update \fus_oper_i_alu_trap0__trapaddr $0\fus_oper_i_alu_trap0__trapaddr[12:0] - end - attribute \src "issuer_ls180.v:46399.3-46427.6" - process $proc$issuer_ls180.v:46399$2783 - assign { } { } - assign { } { } - assign $0\fus_cu_issue_i$10[0:0]$2784 $1\fus_cu_issue_i$10[0:0]$2785 - attribute \src "issuer_ls180.v:46400.5-46400.29" - switch \initial - attribute \src "issuer_ls180.v:46400.9-46400.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_issue_i$10[0:0]$2785 $2\fus_cu_issue_i$10[0:0]$2786 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_issue_i$10[0:0]$2786 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_issue_i$10[0:0]$2786 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_issue_i$10[0:0]$2786 $3\fus_cu_issue_i$10[0:0]$2787 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [3] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_issue_i$10[0:0]$2787 \issue_i - case - assign $3\fus_cu_issue_i$10[0:0]$2787 1'0 - end - end - case - assign $1\fus_cu_issue_i$10[0:0]$2785 1'0 - end - sync always - update \fus_cu_issue_i$10 $0\fus_cu_issue_i$10[0:0]$2784 - end - attribute \src "issuer_ls180.v:46428.3-46456.6" - process $proc$issuer_ls180.v:46428$2788 - assign { } { } - assign { } { } - assign $0\fus_cu_rdmaskn_i$12[3:0]$2789 $1\fus_cu_rdmaskn_i$12[3:0]$2790 - attribute \src "issuer_ls180.v:46429.5-46429.29" - switch \initial - attribute \src "issuer_ls180.v:46429.9-46429.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_rdmaskn_i$12[3:0]$2790 $2\fus_cu_rdmaskn_i$12[3:0]$2791 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_rdmaskn_i$12[3:0]$2791 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_rdmaskn_i$12[3:0]$2791 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_rdmaskn_i$12[3:0]$2791 $3\fus_cu_rdmaskn_i$12[3:0]$2792 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [3] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_rdmaskn_i$12[3:0]$2792 \$233 - case - assign $3\fus_cu_rdmaskn_i$12[3:0]$2792 4'0000 - end - end - case - assign $1\fus_cu_rdmaskn_i$12[3:0]$2790 4'0000 - end - sync always - update \fus_cu_rdmaskn_i$12 $0\fus_cu_rdmaskn_i$12[3:0]$2789 - end - attribute \src "issuer_ls180.v:46457.3-46485.6" - process $proc$issuer_ls180.v:46457$2793 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__insn_type[6:0] $1\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "issuer_ls180.v:46458.5-46458.29" - switch \initial - attribute \src "issuer_ls180.v:46458.9-46458.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__insn_type[6:0] $2\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__insn_type[6:0] $3\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [4] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__insn_type[6:0] \dec_LOGICAL_LOGICAL_LOGICAL__insn_type - case - assign $3\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 - end - end - case - assign $1\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 - end - sync always - update \fus_oper_i_alu_logical0__insn_type $0\fus_oper_i_alu_logical0__insn_type[6:0] - end - attribute \src "issuer_ls180.v:46486.3-46514.6" - process $proc$issuer_ls180.v:46486$2794 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__fn_unit[11:0] $1\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "issuer_ls180.v:46487.5-46487.29" - switch \initial - attribute \src "issuer_ls180.v:46487.9-46487.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__fn_unit[11:0] $2\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__fn_unit[11:0] $3\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [4] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__fn_unit[11:0] \dec_LOGICAL_LOGICAL_LOGICAL__fn_unit - case - assign $3\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 - end - end - case - assign $1\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 - end - sync always - update \fus_oper_i_alu_logical0__fn_unit $0\fus_oper_i_alu_logical0__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:46515.3-46544.6" - process $proc$issuer_ls180.v:46515$2795 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__imm_data__data[63:0] $1\fus_oper_i_alu_logical0__imm_data__data[63:0] - assign $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:46516.5-46516.29" - switch \initial - attribute \src "issuer_ls180.v:46516.9-46516.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_logical0__imm_data__data[63:0] $2\fus_oper_i_alu_logical0__imm_data__data[63:0] - assign $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] $3\fus_oper_i_alu_logical0__imm_data__data[63:0] - assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [4] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] $3\fus_oper_i_alu_logical0__imm_data__data[63:0] } { \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__ok \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__data } - case - assign $3\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__imm_data__data $0\fus_oper_i_alu_logical0__imm_data__data[63:0] - update \fus_oper_i_alu_logical0__imm_data__ok $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:46545.3-46574.6" - process $proc$issuer_ls180.v:46545$2796 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__rc__ok[0:0] $1\fus_oper_i_alu_logical0__rc__ok[0:0] - assign $0\fus_oper_i_alu_logical0__rc__rc[0:0] $1\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "issuer_ls180.v:46546.5-46546.29" - switch \initial - attribute \src "issuer_ls180.v:46546.9-46546.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_logical0__rc__ok[0:0] $2\fus_oper_i_alu_logical0__rc__ok[0:0] - assign $1\fus_oper_i_alu_logical0__rc__rc[0:0] $2\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] $3\fus_oper_i_alu_logical0__rc__ok[0:0] - assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] $3\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [4] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_logical0__rc__ok[0:0] $3\fus_oper_i_alu_logical0__rc__rc[0:0] } { \dec_LOGICAL_LOGICAL_LOGICAL__rc__ok \dec_LOGICAL_LOGICAL_LOGICAL__rc__rc } - case - assign $3\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 - assign $3\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 - assign $1\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__rc__ok $0\fus_oper_i_alu_logical0__rc__ok[0:0] - update \fus_oper_i_alu_logical0__rc__rc $0\fus_oper_i_alu_logical0__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:46575.3-46604.6" - process $proc$issuer_ls180.v:46575$2797 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__oe__oe[0:0] $1\fus_oper_i_alu_logical0__oe__oe[0:0] - assign $0\fus_oper_i_alu_logical0__oe__ok[0:0] $1\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "issuer_ls180.v:46576.5-46576.29" - switch \initial - attribute \src "issuer_ls180.v:46576.9-46576.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_logical0__oe__oe[0:0] $2\fus_oper_i_alu_logical0__oe__oe[0:0] - assign $1\fus_oper_i_alu_logical0__oe__ok[0:0] $2\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] $3\fus_oper_i_alu_logical0__oe__oe[0:0] - assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] $3\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [4] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_logical0__oe__ok[0:0] $3\fus_oper_i_alu_logical0__oe__oe[0:0] } { \dec_LOGICAL_LOGICAL_LOGICAL__oe__ok \dec_LOGICAL_LOGICAL_LOGICAL__oe__oe } - case - assign $3\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 - assign $3\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 - assign $1\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__oe__oe $0\fus_oper_i_alu_logical0__oe__oe[0:0] - update \fus_oper_i_alu_logical0__oe__ok $0\fus_oper_i_alu_logical0__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:46605.3-46633.6" - process $proc$issuer_ls180.v:46605$2798 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__invert_in[0:0] $1\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "issuer_ls180.v:46606.5-46606.29" - switch \initial - attribute \src "issuer_ls180.v:46606.9-46606.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__invert_in[0:0] $2\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__invert_in[0:0] $3\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [4] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__invert_in[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__invert_in - case - assign $3\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__invert_in $0\fus_oper_i_alu_logical0__invert_in[0:0] - end - attribute \src "issuer_ls180.v:46634.3-46662.6" - process $proc$issuer_ls180.v:46634$2799 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__zero_a[0:0] $1\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "issuer_ls180.v:46635.5-46635.29" - switch \initial - attribute \src "issuer_ls180.v:46635.9-46635.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__zero_a[0:0] $2\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__zero_a[0:0] $3\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [4] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__zero_a[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__zero_a - case - assign $3\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__zero_a $0\fus_oper_i_alu_logical0__zero_a[0:0] - end - attribute \src "issuer_ls180.v:46663.3-46691.6" - process $proc$issuer_ls180.v:46663$2800 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__input_carry[1:0] $1\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "issuer_ls180.v:46664.5-46664.29" - switch \initial - attribute \src "issuer_ls180.v:46664.9-46664.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__input_carry[1:0] $2\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__input_carry[1:0] $3\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [4] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__input_carry[1:0] \dec_LOGICAL_LOGICAL_LOGICAL__input_carry - case - assign $3\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 - end - end - case - assign $1\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 - end - sync always - update \fus_oper_i_alu_logical0__input_carry $0\fus_oper_i_alu_logical0__input_carry[1:0] - end - attribute \src "issuer_ls180.v:46692.3-46720.6" - process $proc$issuer_ls180.v:46692$2801 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__invert_out[0:0] $1\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "issuer_ls180.v:46693.5-46693.29" - switch \initial - attribute \src "issuer_ls180.v:46693.9-46693.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__invert_out[0:0] $2\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__invert_out[0:0] $3\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [4] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__invert_out[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__invert_out - case - assign $3\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__invert_out $0\fus_oper_i_alu_logical0__invert_out[0:0] - end - attribute \src "issuer_ls180.v:46721.3-46749.6" - process $proc$issuer_ls180.v:46721$2802 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__write_cr0[0:0] $1\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "issuer_ls180.v:46722.5-46722.29" - switch \initial - attribute \src "issuer_ls180.v:46722.9-46722.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__write_cr0[0:0] $2\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] $3\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [4] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__write_cr0[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__write_cr0 - case - assign $3\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__write_cr0 $0\fus_oper_i_alu_logical0__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:46750.3-46778.6" - process $proc$issuer_ls180.v:46750$2803 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__output_carry[0:0] $1\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "issuer_ls180.v:46751.5-46751.29" - switch \initial - attribute \src "issuer_ls180.v:46751.9-46751.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__output_carry[0:0] $2\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__output_carry[0:0] $3\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [4] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__output_carry[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__output_carry - case - assign $3\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__output_carry $0\fus_oper_i_alu_logical0__output_carry[0:0] - end - attribute \src "issuer_ls180.v:46779.3-46807.6" - process $proc$issuer_ls180.v:46779$2804 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__is_32bit[0:0] $1\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "issuer_ls180.v:46780.5-46780.29" - switch \initial - attribute \src "issuer_ls180.v:46780.9-46780.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] $2\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] $3\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [4] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__is_32bit - case - assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__is_32bit $0\fus_oper_i_alu_logical0__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:46808.3-46836.6" - process $proc$issuer_ls180.v:46808$2805 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__is_signed[0:0] $1\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "issuer_ls180.v:46809.5-46809.29" - switch \initial - attribute \src "issuer_ls180.v:46809.9-46809.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__is_signed[0:0] $2\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__is_signed[0:0] $3\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [4] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__is_signed[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__is_signed - case - assign $3\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__is_signed $0\fus_oper_i_alu_logical0__is_signed[0:0] - end - attribute \src "issuer_ls180.v:46837.3-46865.6" - process $proc$issuer_ls180.v:46837$2806 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__data_len[3:0] $1\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "issuer_ls180.v:46838.5-46838.29" - switch \initial - attribute \src "issuer_ls180.v:46838.9-46838.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__data_len[3:0] $2\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__data_len[3:0] $3\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [4] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__data_len[3:0] \dec_LOGICAL_LOGICAL_LOGICAL__data_len - case - assign $3\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 - end - end - case - assign $1\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 - end - sync always - update \fus_oper_i_alu_logical0__data_len $0\fus_oper_i_alu_logical0__data_len[3:0] - end - attribute \src "issuer_ls180.v:46866.3-46894.6" - process $proc$issuer_ls180.v:46866$2807 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__insn[31:0] $1\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "issuer_ls180.v:46867.5-46867.29" - switch \initial - attribute \src "issuer_ls180.v:46867.9-46867.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__insn[31:0] $2\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__insn[31:0] 0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__insn[31:0] 0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__insn[31:0] $3\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [4] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__insn[31:0] \dec_LOGICAL_LOGICAL_LOGICAL__insn - case - assign $3\fus_oper_i_alu_logical0__insn[31:0] 0 - end - end - case - assign $1\fus_oper_i_alu_logical0__insn[31:0] 0 - end - sync always - update \fus_oper_i_alu_logical0__insn $0\fus_oper_i_alu_logical0__insn[31:0] - end - attribute \src "issuer_ls180.v:46895.3-46923.6" - process $proc$issuer_ls180.v:46895$2808 - assign { } { } - assign { } { } - assign $0\fus_cu_issue_i$13[0:0]$2809 $1\fus_cu_issue_i$13[0:0]$2810 - attribute \src "issuer_ls180.v:46896.5-46896.29" - switch \initial - attribute \src "issuer_ls180.v:46896.9-46896.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_issue_i$13[0:0]$2810 $2\fus_cu_issue_i$13[0:0]$2811 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_issue_i$13[0:0]$2811 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_issue_i$13[0:0]$2811 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_issue_i$13[0:0]$2811 $3\fus_cu_issue_i$13[0:0]$2812 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [4] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_issue_i$13[0:0]$2812 \issue_i - case - assign $3\fus_cu_issue_i$13[0:0]$2812 1'0 - end - end - case - assign $1\fus_cu_issue_i$13[0:0]$2810 1'0 - end - sync always - update \fus_cu_issue_i$13 $0\fus_cu_issue_i$13[0:0]$2809 - end - attribute \src "issuer_ls180.v:46924.3-46952.6" - process $proc$issuer_ls180.v:46924$2813 - assign { } { } - assign { } { } - assign $0\fus_cu_rdmaskn_i$15[2:0]$2814 $1\fus_cu_rdmaskn_i$15[2:0]$2815 - attribute \src "issuer_ls180.v:46925.5-46925.29" - switch \initial - attribute \src "issuer_ls180.v:46925.9-46925.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_rdmaskn_i$15[2:0]$2815 $2\fus_cu_rdmaskn_i$15[2:0]$2816 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_rdmaskn_i$15[2:0]$2816 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_rdmaskn_i$15[2:0]$2816 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_rdmaskn_i$15[2:0]$2816 $3\fus_cu_rdmaskn_i$15[2:0]$2817 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [4] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_rdmaskn_i$15[2:0]$2817 \$235 - case - assign $3\fus_cu_rdmaskn_i$15[2:0]$2817 3'000 - end - end - case - assign $1\fus_cu_rdmaskn_i$15[2:0]$2815 3'000 - end - sync always - update \fus_cu_rdmaskn_i$15 $0\fus_cu_rdmaskn_i$15[2:0]$2814 - end - attribute \src "issuer_ls180.v:46953.3-46981.6" - process $proc$issuer_ls180.v:46953$2818 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_spr0__insn_type[6:0] $1\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "issuer_ls180.v:46954.5-46954.29" - switch \initial - attribute \src "issuer_ls180.v:46954.9-46954.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_spr0__insn_type[6:0] $2\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_spr0__insn_type[6:0] $3\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [5] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_spr0__insn_type[6:0] \dec_SPR_SPR_SPR__insn_type - case - assign $3\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 - end - end - case - assign $1\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 - end - sync always - update \fus_oper_i_alu_spr0__insn_type $0\fus_oper_i_alu_spr0__insn_type[6:0] - end - attribute \src "issuer_ls180.v:46982.3-47010.6" - process $proc$issuer_ls180.v:46982$2819 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_spr0__fn_unit[11:0] $1\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "issuer_ls180.v:46983.5-46983.29" - switch \initial - attribute \src "issuer_ls180.v:46983.9-46983.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_spr0__fn_unit[11:0] $2\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_spr0__fn_unit[11:0] $3\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [5] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_spr0__fn_unit[11:0] \dec_SPR_SPR_SPR__fn_unit - case - assign $3\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 - end - end - case - assign $1\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 - end - sync always - update \fus_oper_i_alu_spr0__fn_unit $0\fus_oper_i_alu_spr0__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:47011.3-47039.6" - process $proc$issuer_ls180.v:47011$2820 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_spr0__insn[31:0] $1\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "issuer_ls180.v:47012.5-47012.29" - switch \initial - attribute \src "issuer_ls180.v:47012.9-47012.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch \ivalid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_spr0__insn[31:0] $2\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_spr0__insn[31:0] $3\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch \fu_enable [5] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_spr0__insn[31:0] \dec_SPR_SPR_SPR__insn - case - assign $3\fus_oper_i_alu_spr0__insn[31:0] 0 - end - end - case - assign $1\fus_oper_i_alu_spr0__insn[31:0] 0 - end - sync always - update \fus_oper_i_alu_spr0__insn $0\fus_oper_i_alu_spr0__insn[31:0] - end - connect \$1000 $ternary$issuer_ls180.v:40657$1429_Y - connect \$1002 $and$issuer_ls180.v:40658$1430_Y - connect \$1005 $and$issuer_ls180.v:40659$1431_Y - connect \$1009 $not$issuer_ls180.v:40660$1432_Y - connect \$1011 $and$issuer_ls180.v:40661$1433_Y - connect \$1015 $and$issuer_ls180.v:40662$1434_Y - connect \$1018 $ternary$issuer_ls180.v:40663$1435_Y - connect \$1020 $and$issuer_ls180.v:40664$1436_Y - connect \$1023 $and$issuer_ls180.v:40665$1437_Y - connect \$1027 $not$issuer_ls180.v:40666$1438_Y - connect \$1029 $and$issuer_ls180.v:40667$1439_Y - connect \$1037 $and$issuer_ls180.v:40668$1440_Y - connect \$1040 $ternary$issuer_ls180.v:40669$1441_Y - connect \$1042 $and$issuer_ls180.v:40670$1442_Y - connect \$1045 $and$issuer_ls180.v:40671$1443_Y - connect \$1049 $not$issuer_ls180.v:40672$1444_Y - connect \$1051 $and$issuer_ls180.v:40673$1445_Y - connect \$1057 $and$issuer_ls180.v:40674$1446_Y - connect \$1060 $ternary$issuer_ls180.v:40675$1447_Y - connect \$1062 $and$issuer_ls180.v:40676$1448_Y - connect \$1065 $and$issuer_ls180.v:40677$1449_Y - connect \$1069 $not$issuer_ls180.v:40678$1450_Y - connect \$1071 $and$issuer_ls180.v:40679$1451_Y - connect \$1077 $and$issuer_ls180.v:40680$1452_Y - connect \$1080 $ternary$issuer_ls180.v:40681$1453_Y - connect \$1082 $and$issuer_ls180.v:40682$1454_Y - connect \$1085 $and$issuer_ls180.v:40683$1455_Y - connect \$1089 $not$issuer_ls180.v:40684$1456_Y - connect \$1091 $and$issuer_ls180.v:40685$1457_Y - connect \$1096 $and$issuer_ls180.v:40686$1458_Y - connect \$1099 $ternary$issuer_ls180.v:40687$1459_Y - connect \$1101 $and$issuer_ls180.v:40688$1460_Y - connect \$1104 $and$issuer_ls180.v:40689$1461_Y - connect \$1108 $not$issuer_ls180.v:40690$1462_Y - connect \$1110 $and$issuer_ls180.v:40691$1463_Y - connect \$1114 $and$issuer_ls180.v:40692$1464_Y - connect \$1117 $ternary$issuer_ls180.v:40693$1465_Y - connect \$1119 $and$issuer_ls180.v:40694$1466_Y - connect \$1122 $and$issuer_ls180.v:40695$1467_Y - connect \$1125 $not$issuer_ls180.v:40696$1468_Y - connect \$1127 $and$issuer_ls180.v:40697$1469_Y - connect \$1130 $and$issuer_ls180.v:40698$1470_Y - connect \$1133 $ternary$issuer_ls180.v:40699$1471_Y - connect \$1136 $or$issuer_ls180.v:40700$1472_Y - connect \$1138 $or$issuer_ls180.v:40701$1473_Y - connect \$1140 $or$issuer_ls180.v:40702$1474_Y - connect \$1142 $or$issuer_ls180.v:40703$1475_Y - connect \$1144 $or$issuer_ls180.v:40704$1476_Y - connect \$1146 $or$issuer_ls180.v:40705$1477_Y - connect \$1148 $or$issuer_ls180.v:40706$1478_Y - connect \$1150 $or$issuer_ls180.v:40707$1479_Y - connect \$1152 $or$issuer_ls180.v:40708$1480_Y - connect \$1154 $or$issuer_ls180.v:40709$1481_Y - connect \$1156 $or$issuer_ls180.v:40710$1482_Y - connect \$1158 $or$issuer_ls180.v:40711$1483_Y - connect \$1160 $or$issuer_ls180.v:40712$1484_Y - connect \$1162 $or$issuer_ls180.v:40713$1485_Y - connect \$1164 $or$issuer_ls180.v:40714$1486_Y - connect \$1166 $or$issuer_ls180.v:40715$1487_Y - connect \$1168 $or$issuer_ls180.v:40716$1488_Y - connect \$1170 $or$issuer_ls180.v:40717$1489_Y - connect \$1172 $or$issuer_ls180.v:40718$1490_Y - connect \$1174 $or$issuer_ls180.v:40719$1491_Y - connect \$1176 $or$issuer_ls180.v:40720$1492_Y - connect \$1178 $or$issuer_ls180.v:40721$1493_Y - connect \$1180 $or$issuer_ls180.v:40722$1494_Y - connect \$1182 $or$issuer_ls180.v:40723$1495_Y - connect \$1184 $or$issuer_ls180.v:40724$1496_Y - connect \$1186 $or$issuer_ls180.v:40725$1497_Y - connect \$1188 $or$issuer_ls180.v:40726$1498_Y - connect \$1190 $and$issuer_ls180.v:40727$1499_Y - connect \$1192 $and$issuer_ls180.v:40728$1500_Y - connect \$1195 $and$issuer_ls180.v:40729$1501_Y - connect \$1198 $not$issuer_ls180.v:40730$1502_Y - connect \$1200 $and$issuer_ls180.v:40731$1503_Y - connect \$1203 $and$issuer_ls180.v:40732$1504_Y - connect \$1206 $ternary$issuer_ls180.v:40733$1505_Y - connect \$1208 $and$issuer_ls180.v:40734$1506_Y - connect \$1210 $and$issuer_ls180.v:40735$1507_Y - connect \$1212 $and$issuer_ls180.v:40736$1508_Y - connect \$1214 $and$issuer_ls180.v:40737$1509_Y - connect \$1216 $and$issuer_ls180.v:40738$1510_Y - connect \$1218 $and$issuer_ls180.v:40739$1511_Y - connect \$1220 $and$issuer_ls180.v:40740$1512_Y - connect \$1223 $and$issuer_ls180.v:40741$1513_Y - connect \$1226 $not$issuer_ls180.v:40742$1514_Y - connect \$1228 $and$issuer_ls180.v:40743$1515_Y - connect \$1231 $and$issuer_ls180.v:40744$1516_Y - connect \$1234 $sub$issuer_ls180.v:40745$1517_Y - connect \$1236 $sshl$issuer_ls180.v:40746$1518_Y - connect \$1238 $ternary$issuer_ls180.v:40747$1519_Y - connect \$1240 $and$issuer_ls180.v:40748$1520_Y - connect \$1243 $and$issuer_ls180.v:40749$1521_Y - connect \$1246 $not$issuer_ls180.v:40750$1522_Y - connect \$1248 $and$issuer_ls180.v:40751$1523_Y - connect \$1251 $and$issuer_ls180.v:40752$1524_Y - connect \$1254 $sub$issuer_ls180.v:40753$1525_Y - connect \$1256 $sshl$issuer_ls180.v:40754$1526_Y - connect \$1258 $ternary$issuer_ls180.v:40755$1527_Y - connect \$1260 $and$issuer_ls180.v:40756$1528_Y - connect \$1263 $and$issuer_ls180.v:40757$1529_Y - connect \$1266 $not$issuer_ls180.v:40758$1530_Y - connect \$1268 $and$issuer_ls180.v:40759$1531_Y - connect \$1271 $and$issuer_ls180.v:40760$1532_Y - connect \$1274 $sub$issuer_ls180.v:40761$1533_Y - connect \$1276 $sshl$issuer_ls180.v:40762$1534_Y - connect \$1278 $ternary$issuer_ls180.v:40763$1535_Y - connect \$1280 $and$issuer_ls180.v:40764$1536_Y - connect \$1283 $and$issuer_ls180.v:40765$1537_Y - connect \$1286 $not$issuer_ls180.v:40766$1538_Y - connect \$1288 $and$issuer_ls180.v:40767$1539_Y - connect \$1291 $and$issuer_ls180.v:40768$1540_Y - connect \$1294 $sub$issuer_ls180.v:40769$1541_Y - connect \$1296 $sshl$issuer_ls180.v:40770$1542_Y - connect \$1298 $ternary$issuer_ls180.v:40771$1543_Y - connect \$1300 $and$issuer_ls180.v:40772$1544_Y - connect \$1303 $and$issuer_ls180.v:40773$1545_Y - connect \$1306 $not$issuer_ls180.v:40774$1546_Y - connect \$1308 $and$issuer_ls180.v:40775$1547_Y - connect \$1311 $and$issuer_ls180.v:40776$1548_Y - connect \$1314 $sub$issuer_ls180.v:40777$1549_Y - connect \$1316 $sshl$issuer_ls180.v:40778$1550_Y - connect \$1318 $ternary$issuer_ls180.v:40779$1551_Y - connect \$1320 $and$issuer_ls180.v:40780$1552_Y - connect \$1323 $and$issuer_ls180.v:40781$1553_Y - connect \$1326 $not$issuer_ls180.v:40782$1554_Y - connect \$1328 $and$issuer_ls180.v:40783$1555_Y - connect \$1331 $and$issuer_ls180.v:40784$1556_Y - connect \$1334 $sub$issuer_ls180.v:40785$1557_Y - connect \$1336 $sshl$issuer_ls180.v:40786$1558_Y - connect \$1338 $ternary$issuer_ls180.v:40787$1559_Y - connect \$1340 $or$issuer_ls180.v:40788$1560_Y - connect \$1342 $or$issuer_ls180.v:40789$1561_Y - connect \$1344 $or$issuer_ls180.v:40790$1562_Y - connect \$1346 $or$issuer_ls180.v:40791$1563_Y - connect \$1348 $or$issuer_ls180.v:40792$1564_Y - connect \$1351 $or$issuer_ls180.v:40793$1565_Y - connect \$1353 $or$issuer_ls180.v:40794$1566_Y - connect \$1355 $or$issuer_ls180.v:40795$1567_Y - connect \$1357 $or$issuer_ls180.v:40796$1568_Y - connect \$1359 $or$issuer_ls180.v:40797$1569_Y - connect \$1361 $and$issuer_ls180.v:40798$1570_Y - connect \$1363 $and$issuer_ls180.v:40799$1571_Y - connect \$1365 $and$issuer_ls180.v:40800$1572_Y - connect \$1367 $and$issuer_ls180.v:40801$1573_Y - connect \$1370 $and$issuer_ls180.v:40802$1574_Y - connect \$1373 $not$issuer_ls180.v:40803$1575_Y - connect \$1375 $and$issuer_ls180.v:40804$1576_Y - connect \$1378 $and$issuer_ls180.v:40805$1577_Y - connect \$1381 $ternary$issuer_ls180.v:40806$1578_Y - connect \$1383 $and$issuer_ls180.v:40807$1579_Y - connect \$1386 $and$issuer_ls180.v:40808$1580_Y - connect \$1389 $not$issuer_ls180.v:40809$1581_Y - connect \$1391 $and$issuer_ls180.v:40810$1582_Y - connect \$1394 $and$issuer_ls180.v:40811$1583_Y - connect \$1397 $ternary$issuer_ls180.v:40812$1584_Y - connect \$1399 $and$issuer_ls180.v:40813$1585_Y - connect \$1402 $and$issuer_ls180.v:40814$1586_Y - connect \$1405 $not$issuer_ls180.v:40815$1587_Y - connect \$1407 $and$issuer_ls180.v:40816$1588_Y - connect \$1410 $and$issuer_ls180.v:40817$1589_Y - connect \$1413 $ternary$issuer_ls180.v:40818$1590_Y - connect \$1415 $or$issuer_ls180.v:40819$1591_Y - connect \$1417 $or$issuer_ls180.v:40820$1592_Y - connect \$1420 $or$issuer_ls180.v:40821$1593_Y - connect \$1422 $or$issuer_ls180.v:40822$1594_Y - connect \$1419 $pos$issuer_ls180.v:40823$1596_Y - connect \$1425 $and$issuer_ls180.v:40824$1597_Y - connect \$1427 $and$issuer_ls180.v:40825$1598_Y - connect \$1429 $and$issuer_ls180.v:40826$1599_Y - connect \$1431 $and$issuer_ls180.v:40827$1600_Y - connect \$1433 $and$issuer_ls180.v:40828$1601_Y - connect \$1436 $and$issuer_ls180.v:40829$1602_Y - connect \$1439 $not$issuer_ls180.v:40830$1603_Y - connect \$1441 $and$issuer_ls180.v:40831$1604_Y - connect \$1444 $and$issuer_ls180.v:40832$1605_Y - connect \$1447 $ternary$issuer_ls180.v:40833$1606_Y - connect \$1449 $and$issuer_ls180.v:40834$1607_Y - connect \$1452 $and$issuer_ls180.v:40835$1608_Y - connect \$1455 $not$issuer_ls180.v:40836$1609_Y - connect \$1457 $and$issuer_ls180.v:40837$1610_Y - connect \$1460 $and$issuer_ls180.v:40838$1611_Y - connect \$1463 $ternary$issuer_ls180.v:40839$1612_Y - connect \$1465 $and$issuer_ls180.v:40840$1613_Y - connect \$1468 $and$issuer_ls180.v:40841$1614_Y - connect \$1471 $not$issuer_ls180.v:40842$1615_Y - connect \$1473 $and$issuer_ls180.v:40843$1616_Y - connect \$1476 $and$issuer_ls180.v:40844$1617_Y - connect \$1479 $ternary$issuer_ls180.v:40845$1618_Y - connect \$1481 $and$issuer_ls180.v:40846$1619_Y - connect \$1484 $and$issuer_ls180.v:40847$1620_Y - connect \$1487 $not$issuer_ls180.v:40848$1621_Y - connect \$1489 $and$issuer_ls180.v:40849$1622_Y - connect \$1492 $and$issuer_ls180.v:40850$1623_Y - connect \$1495 $ternary$issuer_ls180.v:40851$1624_Y - connect \$1497 $or$issuer_ls180.v:40852$1625_Y - connect \$1499 $or$issuer_ls180.v:40853$1626_Y - connect \$1501 $or$issuer_ls180.v:40854$1627_Y - connect \$1503 $or$issuer_ls180.v:40855$1628_Y - connect \$1505 $or$issuer_ls180.v:40856$1629_Y - connect \$1507 $or$issuer_ls180.v:40857$1630_Y - connect \$1509 $and$issuer_ls180.v:40858$1631_Y - connect \$1511 $and$issuer_ls180.v:40859$1632_Y - connect \$1513 $and$issuer_ls180.v:40860$1633_Y - connect \$1515 $and$issuer_ls180.v:40861$1634_Y - connect \$1517 $and$issuer_ls180.v:40862$1635_Y - connect \$1520 $and$issuer_ls180.v:40863$1636_Y - connect \$1523 $not$issuer_ls180.v:40864$1637_Y - connect \$1525 $and$issuer_ls180.v:40865$1638_Y - connect \$1528 $and$issuer_ls180.v:40866$1639_Y - connect \$1531 $ternary$issuer_ls180.v:40867$1640_Y - connect \$1533 $and$issuer_ls180.v:40868$1641_Y - connect \$1536 $and$issuer_ls180.v:40869$1642_Y - connect \$1539 $not$issuer_ls180.v:40870$1643_Y - connect \$1541 $and$issuer_ls180.v:40871$1644_Y - connect \$1544 $and$issuer_ls180.v:40872$1645_Y - connect \$1547 $ternary$issuer_ls180.v:40873$1646_Y - connect \$1549 $and$issuer_ls180.v:40874$1647_Y - connect \$1552 $and$issuer_ls180.v:40875$1648_Y - connect \$1555 $not$issuer_ls180.v:40876$1649_Y - connect \$1557 $and$issuer_ls180.v:40877$1650_Y - connect \$1560 $and$issuer_ls180.v:40878$1651_Y - connect \$1563 $ternary$issuer_ls180.v:40879$1652_Y - connect \$1565 $and$issuer_ls180.v:40880$1653_Y - connect \$1568 $and$issuer_ls180.v:40881$1654_Y - connect \$1571 $not$issuer_ls180.v:40882$1655_Y - connect \$1573 $and$issuer_ls180.v:40883$1656_Y - connect \$1576 $and$issuer_ls180.v:40884$1657_Y - connect \$1579 $ternary$issuer_ls180.v:40885$1658_Y - connect \$1582 $or$issuer_ls180.v:40886$1659_Y - connect \$1584 $or$issuer_ls180.v:40887$1660_Y - connect \$1586 $or$issuer_ls180.v:40888$1661_Y - connect \$1581 $pos$issuer_ls180.v:40889$1663_Y - connect \$1590 $or$issuer_ls180.v:40890$1664_Y - connect \$1592 $or$issuer_ls180.v:40891$1665_Y - connect \$1594 $or$issuer_ls180.v:40892$1666_Y - connect \$1589 $pos$issuer_ls180.v:40893$1668_Y - connect \$1597 $and$issuer_ls180.v:40894$1669_Y - connect \$1599 $and$issuer_ls180.v:40895$1670_Y - connect \$1601 $and$issuer_ls180.v:40896$1671_Y - connect \$1603 $and$issuer_ls180.v:40897$1672_Y - connect \$1605 $and$issuer_ls180.v:40898$1673_Y - connect \$1607 $and$issuer_ls180.v:40899$1674_Y - connect \$1610 $and$issuer_ls180.v:40900$1675_Y - connect \$1614 $not$issuer_ls180.v:40901$1676_Y - connect \$1616 $and$issuer_ls180.v:40902$1677_Y - connect \$161 $and$issuer_ls180.v:40903$1678_Y - connect \$1621 $and$issuer_ls180.v:40904$1679_Y - connect \$1624 $ternary$issuer_ls180.v:40905$1680_Y - connect \$1626 $and$issuer_ls180.v:40906$1681_Y - connect \$160 $reduce_or$issuer_ls180.v:40907$1682_Y - connect \$1629 $and$issuer_ls180.v:40908$1683_Y - connect \$1632 $not$issuer_ls180.v:40909$1684_Y - connect \$1634 $and$issuer_ls180.v:40910$1685_Y - connect \$1637 $and$issuer_ls180.v:40911$1686_Y - connect \$1640 $ternary$issuer_ls180.v:40912$1687_Y - connect \$1642 $and$issuer_ls180.v:40913$1688_Y - connect \$1645 $and$issuer_ls180.v:40914$1689_Y - connect \$1648 $not$issuer_ls180.v:40915$1690_Y - connect \$1650 $and$issuer_ls180.v:40916$1691_Y - connect \$1653 $and$issuer_ls180.v:40917$1692_Y - connect \$1656 $ternary$issuer_ls180.v:40918$1693_Y - connect \$1658 $and$issuer_ls180.v:40919$1694_Y - connect \$165 $and$issuer_ls180.v:40920$1695_Y - connect \$1661 $and$issuer_ls180.v:40921$1696_Y - connect \$1664 $not$issuer_ls180.v:40922$1697_Y - connect \$1666 $and$issuer_ls180.v:40923$1698_Y - connect \$164 $reduce_or$issuer_ls180.v:40924$1699_Y - connect \$1669 $and$issuer_ls180.v:40925$1700_Y - connect \$1672 $ternary$issuer_ls180.v:40926$1701_Y - connect \$1674 $and$issuer_ls180.v:40927$1702_Y - connect \$1677 $and$issuer_ls180.v:40928$1703_Y - connect \$1680 $not$issuer_ls180.v:40929$1704_Y - connect \$1682 $and$issuer_ls180.v:40930$1705_Y - connect \$1685 $and$issuer_ls180.v:40931$1706_Y - connect \$1688 $ternary$issuer_ls180.v:40932$1707_Y - connect \$1690 $or$issuer_ls180.v:40933$1708_Y - connect \$1692 $or$issuer_ls180.v:40934$1709_Y - connect \$1694 $or$issuer_ls180.v:40935$1710_Y - connect \$1696 $or$issuer_ls180.v:40936$1711_Y - connect \$1698 $or$issuer_ls180.v:40937$1712_Y - connect \$169 $and$issuer_ls180.v:40938$1713_Y - connect \$1700 $or$issuer_ls180.v:40939$1714_Y - connect \$1702 $or$issuer_ls180.v:40940$1715_Y - connect \$1704 $or$issuer_ls180.v:40941$1716_Y - connect \$1706 $or$issuer_ls180.v:40942$1717_Y - connect \$1708 $or$issuer_ls180.v:40943$1718_Y - connect \$168 $reduce_or$issuer_ls180.v:40944$1719_Y - connect \$1710 $or$issuer_ls180.v:40945$1720_Y - connect \$1712 $or$issuer_ls180.v:40946$1721_Y - connect \$1714 $and$issuer_ls180.v:40947$1722_Y - connect \$1716 $and$issuer_ls180.v:40948$1723_Y - connect \$1718 $and$issuer_ls180.v:40949$1724_Y - connect \$1721 $and$issuer_ls180.v:40950$1725_Y - connect \$1724 $not$issuer_ls180.v:40951$1726_Y - connect \$1726 $and$issuer_ls180.v:40952$1727_Y - connect \$1729 $and$issuer_ls180.v:40953$1728_Y - connect \$1732 $ternary$issuer_ls180.v:40954$1729_Y - connect \$1734 $and$issuer_ls180.v:40955$1730_Y - connect \$1737 $and$issuer_ls180.v:40956$1731_Y - connect \$173 $and$issuer_ls180.v:40957$1732_Y - connect \$1740 $not$issuer_ls180.v:40958$1733_Y - connect \$1742 $and$issuer_ls180.v:40959$1734_Y - connect \$1745 $and$issuer_ls180.v:40960$1735_Y - connect \$1748 $ternary$issuer_ls180.v:40961$1736_Y - connect \$172 $reduce_or$issuer_ls180.v:40962$1737_Y - connect \$1750 $or$issuer_ls180.v:40963$1738_Y - connect \$1753 $or$issuer_ls180.v:40964$1739_Y - connect \$1752 $pos$issuer_ls180.v:40965$1741_Y - connect \$1756 $and$issuer_ls180.v:40966$1742_Y - connect \$1758 $and$issuer_ls180.v:40967$1743_Y - connect \$1761 $and$issuer_ls180.v:40968$1744_Y - connect \$1764 $not$issuer_ls180.v:40969$1745_Y - connect \$1766 $and$issuer_ls180.v:40970$1746_Y - connect \$1769 $and$issuer_ls180.v:40971$1747_Y - connect \$1772 $ternary$issuer_ls180.v:40972$1748_Y - connect \$1774 $pos$issuer_ls180.v:40973$1750_Y - connect \$1776 $and$issuer_ls180.v:40974$1751_Y - connect \$1778 $and$issuer_ls180.v:40975$1752_Y - connect \$177 $and$issuer_ls180.v:40976$1753_Y - connect \$1781 $and$issuer_ls180.v:40977$1754_Y - connect \$1784 $not$issuer_ls180.v:40978$1755_Y - connect \$1786 $and$issuer_ls180.v:40979$1756_Y - connect \$176 $reduce_or$issuer_ls180.v:40980$1757_Y - connect \$1789 $and$issuer_ls180.v:40981$1758_Y - connect \$1792 $ternary$issuer_ls180.v:40982$1759_Y - connect \$181 $and$issuer_ls180.v:40983$1760_Y - connect \$180 $reduce_or$issuer_ls180.v:40984$1761_Y - connect \$185 $and$issuer_ls180.v:40985$1762_Y - connect \$184 $reduce_or$issuer_ls180.v:40986$1763_Y - connect \$189 $and$issuer_ls180.v:40987$1764_Y - connect \$188 $reduce_or$issuer_ls180.v:40988$1765_Y - connect \$193 $and$issuer_ls180.v:40989$1766_Y - connect \$192 $reduce_or$issuer_ls180.v:40990$1767_Y - connect \$197 $and$issuer_ls180.v:40991$1768_Y - connect \$196 $reduce_or$issuer_ls180.v:40992$1769_Y - connect \$200 $ne$issuer_ls180.v:40993$1770_Y - connect \$203 $sub$issuer_ls180.v:40994$1771_Y - connect \$205 $ne$issuer_ls180.v:40995$1772_Y - connect \$208 $and$issuer_ls180.v:40996$1773_Y - connect \$210 $and$issuer_ls180.v:40997$1774_Y - connect \$212 $eq$issuer_ls180.v:40998$1775_Y - connect \$214 $or$issuer_ls180.v:40999$1776_Y - connect \$216 $and$issuer_ls180.v:41000$1777_Y - connect \$218 $or$issuer_ls180.v:41001$1778_Y - connect \$220 $eq$issuer_ls180.v:41002$1779_Y - connect \$222 $and$issuer_ls180.v:41003$1780_Y - connect \$224 $eq$issuer_ls180.v:41004$1781_Y - connect \$226 $or$issuer_ls180.v:41005$1782_Y - connect \$207 $not$issuer_ls180.v:41006$1783_Y - connect \$229 $not$issuer_ls180.v:41007$1784_Y - connect \$231 $not$issuer_ls180.v:41008$1785_Y - connect \$233 $not$issuer_ls180.v:41009$1786_Y - connect \$236 $and$issuer_ls180.v:41010$1787_Y - connect \$238 $and$issuer_ls180.v:41011$1788_Y - connect \$240 $eq$issuer_ls180.v:41012$1789_Y - connect \$242 $or$issuer_ls180.v:41013$1790_Y - connect \$244 $and$issuer_ls180.v:41014$1791_Y - connect \$246 $or$issuer_ls180.v:41015$1792_Y - connect \$235 $not$issuer_ls180.v:41016$1793_Y - connect \$250 $and$issuer_ls180.v:41017$1794_Y - connect \$252 $and$issuer_ls180.v:41018$1795_Y - connect \$254 $eq$issuer_ls180.v:41019$1796_Y - connect \$256 $or$issuer_ls180.v:41020$1797_Y - connect \$258 $and$issuer_ls180.v:41021$1798_Y - connect \$260 $or$issuer_ls180.v:41022$1799_Y - connect \$262 $and$issuer_ls180.v:41023$1800_Y - connect \$264 $and$issuer_ls180.v:41024$1801_Y - connect \$266 $eq$issuer_ls180.v:41025$1802_Y - connect \$268 $or$issuer_ls180.v:41026$1803_Y - connect \$270 $eq$issuer_ls180.v:41027$1804_Y - connect \$272 $and$issuer_ls180.v:41028$1805_Y - connect \$274 $eq$issuer_ls180.v:41029$1806_Y - connect \$276 $or$issuer_ls180.v:41030$1807_Y - connect \$249 $not$issuer_ls180.v:41031$1808_Y - connect \$280 $and$issuer_ls180.v:41032$1809_Y - connect \$282 $and$issuer_ls180.v:41033$1810_Y - connect \$284 $eq$issuer_ls180.v:41034$1811_Y - connect \$286 $or$issuer_ls180.v:41035$1812_Y - connect \$288 $and$issuer_ls180.v:41036$1813_Y - connect \$290 $or$issuer_ls180.v:41037$1814_Y - connect \$279 $not$issuer_ls180.v:41038$1815_Y - connect \$294 $and$issuer_ls180.v:41039$1816_Y - connect \$296 $and$issuer_ls180.v:41040$1817_Y - connect \$298 $eq$issuer_ls180.v:41041$1818_Y - connect \$300 $or$issuer_ls180.v:41042$1819_Y - connect \$302 $and$issuer_ls180.v:41043$1820_Y - connect \$304 $or$issuer_ls180.v:41044$1821_Y - connect \$293 $not$issuer_ls180.v:41045$1822_Y - connect \$308 $and$issuer_ls180.v:41046$1823_Y - connect \$310 $and$issuer_ls180.v:41047$1824_Y - connect \$312 $eq$issuer_ls180.v:41048$1825_Y - connect \$314 $or$issuer_ls180.v:41049$1826_Y - connect \$316 $and$issuer_ls180.v:41050$1827_Y - connect \$318 $or$issuer_ls180.v:41051$1828_Y - connect \$320 $eq$issuer_ls180.v:41052$1829_Y - connect \$322 $and$issuer_ls180.v:41053$1830_Y - connect \$324 $eq$issuer_ls180.v:41054$1831_Y - connect \$326 $or$issuer_ls180.v:41055$1832_Y - connect \$307 $not$issuer_ls180.v:41056$1833_Y - connect \$329 $not$issuer_ls180.v:41057$1834_Y - connect \$331 $and$issuer_ls180.v:41058$1835_Y - connect \$333 $and$issuer_ls180.v:41059$1836_Y - connect \$335 $not$issuer_ls180.v:41060$1837_Y - connect \$337 $and$issuer_ls180.v:41061$1838_Y - connect \$339 $and$issuer_ls180.v:41062$1839_Y - connect \$341 $ternary$issuer_ls180.v:41063$1840_Y - connect \$343 $and$issuer_ls180.v:41064$1841_Y - connect \$345 $and$issuer_ls180.v:41065$1842_Y - connect \$347 $not$issuer_ls180.v:41066$1843_Y - connect \$349 $and$issuer_ls180.v:41067$1844_Y - connect \$351 $and$issuer_ls180.v:41068$1845_Y - connect \$353 $ternary$issuer_ls180.v:41069$1846_Y - connect \$355 $and$issuer_ls180.v:41070$1847_Y - connect \$357 $and$issuer_ls180.v:41071$1848_Y - connect \$359 $not$issuer_ls180.v:41072$1849_Y - connect \$361 $and$issuer_ls180.v:41073$1850_Y - connect \$363 $and$issuer_ls180.v:41074$1851_Y - connect \$365 $ternary$issuer_ls180.v:41075$1852_Y - connect \$367 $and$issuer_ls180.v:41076$1853_Y - connect \$369 $and$issuer_ls180.v:41077$1854_Y - connect \$371 $not$issuer_ls180.v:41078$1855_Y - connect \$373 $and$issuer_ls180.v:41079$1856_Y - connect \$375 $and$issuer_ls180.v:41080$1857_Y - connect \$377 $ternary$issuer_ls180.v:41081$1858_Y - connect \$379 $and$issuer_ls180.v:41082$1859_Y - connect \$381 $and$issuer_ls180.v:41083$1860_Y - connect \$383 $not$issuer_ls180.v:41084$1861_Y - connect \$385 $and$issuer_ls180.v:41085$1862_Y - connect \$387 $and$issuer_ls180.v:41086$1863_Y - connect \$389 $ternary$issuer_ls180.v:41087$1864_Y - connect \$391 $and$issuer_ls180.v:41088$1865_Y - connect \$393 $and$issuer_ls180.v:41089$1866_Y - connect \$395 $not$issuer_ls180.v:41090$1867_Y - connect \$397 $and$issuer_ls180.v:41091$1868_Y - connect \$399 $and$issuer_ls180.v:41092$1869_Y - connect \$401 $ternary$issuer_ls180.v:41093$1870_Y - connect \$403 $and$issuer_ls180.v:41094$1871_Y - connect \$405 $and$issuer_ls180.v:41095$1872_Y - connect \$407 $not$issuer_ls180.v:41096$1873_Y - connect \$409 $and$issuer_ls180.v:41097$1874_Y - connect \$411 $and$issuer_ls180.v:41098$1875_Y - connect \$413 $ternary$issuer_ls180.v:41099$1876_Y - connect \$415 $and$issuer_ls180.v:41100$1877_Y - connect \$417 $and$issuer_ls180.v:41101$1878_Y - connect \$419 $not$issuer_ls180.v:41102$1879_Y - connect \$421 $and$issuer_ls180.v:41103$1880_Y - connect \$423 $and$issuer_ls180.v:41104$1881_Y - connect \$425 $ternary$issuer_ls180.v:41105$1882_Y - connect \$427 $and$issuer_ls180.v:41106$1883_Y - connect \$429 $and$issuer_ls180.v:41107$1884_Y - connect \$431 $not$issuer_ls180.v:41108$1885_Y - connect \$433 $and$issuer_ls180.v:41109$1886_Y - connect \$435 $and$issuer_ls180.v:41110$1887_Y - connect \$437 $ternary$issuer_ls180.v:41111$1888_Y - connect \$439 $or$issuer_ls180.v:41112$1889_Y - connect \$441 $or$issuer_ls180.v:41113$1890_Y - connect \$443 $or$issuer_ls180.v:41114$1891_Y - connect \$445 $or$issuer_ls180.v:41115$1892_Y - connect \$447 $or$issuer_ls180.v:41116$1893_Y - connect \$449 $or$issuer_ls180.v:41117$1894_Y - connect \$451 $or$issuer_ls180.v:41118$1895_Y - connect \$453 $or$issuer_ls180.v:41119$1896_Y - connect \$455 $reduce_or$issuer_ls180.v:41120$1897_Y - connect \$457 $and$issuer_ls180.v:41121$1898_Y - connect \$459 $and$issuer_ls180.v:41122$1899_Y - connect \$461 $not$issuer_ls180.v:41123$1900_Y - connect \$463 $and$issuer_ls180.v:41124$1901_Y - connect \$465 $and$issuer_ls180.v:41125$1902_Y - connect \$467 $ternary$issuer_ls180.v:41126$1903_Y - connect \$469 $and$issuer_ls180.v:41127$1904_Y - connect \$471 $and$issuer_ls180.v:41128$1905_Y - connect \$473 $not$issuer_ls180.v:41129$1906_Y - connect \$475 $and$issuer_ls180.v:41130$1907_Y - connect \$477 $and$issuer_ls180.v:41131$1908_Y - connect \$479 $ternary$issuer_ls180.v:41132$1909_Y - connect \$481 $and$issuer_ls180.v:41133$1910_Y - connect \$483 $and$issuer_ls180.v:41134$1911_Y - connect \$485 $not$issuer_ls180.v:41135$1912_Y - connect \$487 $and$issuer_ls180.v:41136$1913_Y - connect \$489 $and$issuer_ls180.v:41137$1914_Y - connect \$491 $ternary$issuer_ls180.v:41138$1915_Y - connect \$493 $and$issuer_ls180.v:41139$1916_Y - connect \$495 $and$issuer_ls180.v:41140$1917_Y - connect \$497 $not$issuer_ls180.v:41141$1918_Y - connect \$499 $and$issuer_ls180.v:41142$1919_Y - connect \$501 $and$issuer_ls180.v:41143$1920_Y - connect \$503 $ternary$issuer_ls180.v:41144$1921_Y - connect \$505 $and$issuer_ls180.v:41145$1922_Y - connect \$507 $and$issuer_ls180.v:41146$1923_Y - connect \$509 $not$issuer_ls180.v:41147$1924_Y - connect \$511 $and$issuer_ls180.v:41148$1925_Y - connect \$513 $and$issuer_ls180.v:41149$1926_Y - connect \$515 $ternary$issuer_ls180.v:41150$1927_Y - connect \$517 $and$issuer_ls180.v:41151$1928_Y - connect \$519 $and$issuer_ls180.v:41152$1929_Y - connect \$521 $not$issuer_ls180.v:41153$1930_Y - connect \$523 $and$issuer_ls180.v:41154$1931_Y - connect \$525 $and$issuer_ls180.v:41155$1932_Y - connect \$527 $ternary$issuer_ls180.v:41156$1933_Y - connect \$529 $and$issuer_ls180.v:41157$1934_Y - connect \$531 $and$issuer_ls180.v:41158$1935_Y - connect \$533 $not$issuer_ls180.v:41159$1936_Y - connect \$535 $and$issuer_ls180.v:41160$1937_Y - connect \$537 $and$issuer_ls180.v:41161$1938_Y - connect \$539 $ternary$issuer_ls180.v:41162$1939_Y - connect \$541 $and$issuer_ls180.v:41163$1940_Y - connect \$543 $and$issuer_ls180.v:41164$1941_Y - connect \$545 $not$issuer_ls180.v:41165$1942_Y - connect \$547 $and$issuer_ls180.v:41166$1943_Y - connect \$549 $and$issuer_ls180.v:41167$1944_Y - connect \$551 $ternary$issuer_ls180.v:41168$1945_Y - connect \$553 $or$issuer_ls180.v:41169$1946_Y - connect \$555 $or$issuer_ls180.v:41170$1947_Y - connect \$557 $or$issuer_ls180.v:41171$1948_Y - connect \$559 $or$issuer_ls180.v:41172$1949_Y - connect \$561 $or$issuer_ls180.v:41173$1950_Y - connect \$563 $or$issuer_ls180.v:41174$1951_Y - connect \$565 $or$issuer_ls180.v:41175$1952_Y - connect \$567 $reduce_or$issuer_ls180.v:41176$1953_Y - connect \$569 $and$issuer_ls180.v:41177$1954_Y - connect \$571 $and$issuer_ls180.v:41178$1955_Y - connect \$573 $not$issuer_ls180.v:41179$1956_Y - connect \$575 $and$issuer_ls180.v:41180$1957_Y - connect \$577 $and$issuer_ls180.v:41181$1958_Y - connect \$579 $ternary$issuer_ls180.v:41182$1959_Y - connect \$581 $and$issuer_ls180.v:41183$1960_Y - connect \$583 $and$issuer_ls180.v:41184$1961_Y - connect \$585 $not$issuer_ls180.v:41185$1962_Y - connect \$587 $and$issuer_ls180.v:41186$1963_Y - connect \$589 $and$issuer_ls180.v:41187$1964_Y - connect \$591 $ternary$issuer_ls180.v:41188$1965_Y - connect \$593 $or$issuer_ls180.v:41189$1966_Y - connect \$595 $reduce_or$issuer_ls180.v:41190$1967_Y - connect \$597 $and$issuer_ls180.v:41191$1968_Y - connect \$599 $and$issuer_ls180.v:41192$1969_Y - connect \$601 $eq$issuer_ls180.v:41193$1970_Y - connect \$603 $or$issuer_ls180.v:41194$1971_Y - connect \$605 $and$issuer_ls180.v:41195$1972_Y - connect \$607 $or$issuer_ls180.v:41196$1973_Y - connect \$609 $and$issuer_ls180.v:41197$1974_Y - connect \$611 $and$issuer_ls180.v:41198$1975_Y - connect \$613 $not$issuer_ls180.v:41199$1976_Y - connect \$615 $and$issuer_ls180.v:41200$1977_Y - connect \$617 $and$issuer_ls180.v:41201$1978_Y - connect \$619 $ternary$issuer_ls180.v:41202$1979_Y - connect \$621 $and$issuer_ls180.v:41203$1980_Y - connect \$623 $and$issuer_ls180.v:41204$1981_Y - connect \$625 $not$issuer_ls180.v:41205$1982_Y - connect \$627 $and$issuer_ls180.v:41206$1983_Y - connect \$629 $and$issuer_ls180.v:41207$1984_Y - connect \$631 $ternary$issuer_ls180.v:41208$1985_Y - connect \$633 $and$issuer_ls180.v:41209$1986_Y - connect \$635 $and$issuer_ls180.v:41210$1987_Y - connect \$637 $not$issuer_ls180.v:41211$1988_Y - connect \$639 $and$issuer_ls180.v:41212$1989_Y - connect \$641 $and$issuer_ls180.v:41213$1990_Y - connect \$643 $ternary$issuer_ls180.v:41214$1991_Y - connect \$645 $and$issuer_ls180.v:41215$1992_Y - connect \$647 $and$issuer_ls180.v:41216$1993_Y - connect \$649 $not$issuer_ls180.v:41217$1994_Y - connect \$651 $and$issuer_ls180.v:41218$1995_Y - connect \$653 $and$issuer_ls180.v:41219$1996_Y - connect \$655 $ternary$issuer_ls180.v:41220$1997_Y - connect \$657 $and$issuer_ls180.v:41221$1998_Y - connect \$659 $and$issuer_ls180.v:41222$1999_Y - connect \$661 $not$issuer_ls180.v:41223$2000_Y - connect \$663 $and$issuer_ls180.v:41224$2001_Y - connect \$665 $and$issuer_ls180.v:41225$2002_Y - connect \$667 $ternary$issuer_ls180.v:41226$2003_Y - connect \$669 $and$issuer_ls180.v:41227$2004_Y - connect \$671 $and$issuer_ls180.v:41228$2005_Y - connect \$673 $not$issuer_ls180.v:41229$2006_Y - connect \$675 $and$issuer_ls180.v:41230$2007_Y - connect \$677 $and$issuer_ls180.v:41231$2008_Y - connect \$679 $ternary$issuer_ls180.v:41232$2009_Y - connect \$682 $or$issuer_ls180.v:41233$2010_Y - connect \$684 $or$issuer_ls180.v:41234$2011_Y - connect \$686 $or$issuer_ls180.v:41235$2012_Y - connect \$688 $or$issuer_ls180.v:41236$2013_Y - connect \$690 $or$issuer_ls180.v:41237$2014_Y - connect \$681 $pos$issuer_ls180.v:41238$2016_Y - connect \$693 $eq$issuer_ls180.v:41239$2017_Y - connect \$695 $and$issuer_ls180.v:41240$2018_Y - connect \$697 $eq$issuer_ls180.v:41241$2019_Y - connect \$699 $or$issuer_ls180.v:41242$2020_Y - connect \$701 $and$issuer_ls180.v:41243$2021_Y - connect \$703 $and$issuer_ls180.v:41244$2022_Y - connect \$705 $not$issuer_ls180.v:41245$2023_Y - connect \$707 $and$issuer_ls180.v:41246$2024_Y - connect \$709 $and$issuer_ls180.v:41247$2025_Y - connect \$711 $ternary$issuer_ls180.v:41248$2026_Y - connect \$713 $and$issuer_ls180.v:41249$2027_Y - connect \$715 $and$issuer_ls180.v:41250$2028_Y - connect \$717 $not$issuer_ls180.v:41251$2029_Y - connect \$719 $and$issuer_ls180.v:41252$2030_Y - connect \$721 $and$issuer_ls180.v:41253$2031_Y - connect \$723 $ternary$issuer_ls180.v:41254$2032_Y - connect \$725 $and$issuer_ls180.v:41255$2033_Y - connect \$727 $and$issuer_ls180.v:41256$2034_Y - connect \$729 $not$issuer_ls180.v:41257$2035_Y - connect \$731 $and$issuer_ls180.v:41258$2036_Y - connect \$733 $and$issuer_ls180.v:41259$2037_Y - connect \$735 $ternary$issuer_ls180.v:41260$2038_Y - connect \$738 $or$issuer_ls180.v:41261$2039_Y - connect \$740 $or$issuer_ls180.v:41262$2040_Y - connect \$737 $pos$issuer_ls180.v:41263$2042_Y - connect \$743 $and$issuer_ls180.v:41264$2043_Y - connect \$745 $and$issuer_ls180.v:41265$2044_Y - connect \$747 $eq$issuer_ls180.v:41266$2045_Y - connect \$749 $or$issuer_ls180.v:41267$2046_Y - connect \$751 $and$issuer_ls180.v:41268$2047_Y - connect \$753 $and$issuer_ls180.v:41269$2048_Y - connect \$755 $not$issuer_ls180.v:41270$2049_Y - connect \$757 $and$issuer_ls180.v:41271$2050_Y - connect \$759 $and$issuer_ls180.v:41272$2051_Y - connect \$761 $ternary$issuer_ls180.v:41273$2052_Y - connect \$763 $and$issuer_ls180.v:41274$2053_Y - connect \$765 $and$issuer_ls180.v:41275$2054_Y - connect \$767 $not$issuer_ls180.v:41276$2055_Y - connect \$769 $and$issuer_ls180.v:41277$2056_Y - connect \$771 $and$issuer_ls180.v:41278$2057_Y - connect \$773 $ternary$issuer_ls180.v:41279$2058_Y - connect \$775 $and$issuer_ls180.v:41280$2059_Y - connect \$777 $and$issuer_ls180.v:41281$2060_Y - connect \$779 $not$issuer_ls180.v:41282$2061_Y - connect \$781 $and$issuer_ls180.v:41283$2062_Y - connect \$783 $and$issuer_ls180.v:41284$2063_Y - connect \$785 $sub$issuer_ls180.v:41285$2064_Y - connect \$787 $sshl$issuer_ls180.v:41286$2065_Y - connect \$789 $ternary$issuer_ls180.v:41287$2066_Y - connect \$791 $and$issuer_ls180.v:41288$2067_Y - connect \$793 $and$issuer_ls180.v:41289$2068_Y - connect \$795 $not$issuer_ls180.v:41290$2069_Y - connect \$797 $and$issuer_ls180.v:41291$2070_Y - connect \$799 $and$issuer_ls180.v:41292$2071_Y - connect \$801 $sub$issuer_ls180.v:41293$2072_Y - connect \$803 $sshl$issuer_ls180.v:41294$2073_Y - connect \$805 $ternary$issuer_ls180.v:41295$2074_Y - connect \$808 $or$issuer_ls180.v:41296$2075_Y - connect \$810 $and$issuer_ls180.v:41297$2076_Y - connect \$812 $and$issuer_ls180.v:41298$2077_Y - connect \$814 $not$issuer_ls180.v:41299$2078_Y - connect \$816 $and$issuer_ls180.v:41300$2079_Y - connect \$818 $and$issuer_ls180.v:41301$2080_Y - connect \$820 $sub$issuer_ls180.v:41302$2081_Y - connect \$822 $sshl$issuer_ls180.v:41303$2082_Y - connect \$824 $ternary$issuer_ls180.v:41304$2083_Y - connect \$826 $and$issuer_ls180.v:41305$2084_Y - connect \$828 $and$issuer_ls180.v:41306$2085_Y - connect \$830 $not$issuer_ls180.v:41307$2086_Y - connect \$832 $and$issuer_ls180.v:41308$2087_Y - connect \$834 $and$issuer_ls180.v:41309$2088_Y - connect \$836 $sub$issuer_ls180.v:41310$2089_Y - connect \$838 $sshl$issuer_ls180.v:41311$2090_Y - connect \$840 $ternary$issuer_ls180.v:41312$2091_Y - connect \$842 $and$issuer_ls180.v:41313$2092_Y - connect \$844 $and$issuer_ls180.v:41314$2093_Y - connect \$846 $not$issuer_ls180.v:41315$2094_Y - connect \$848 $and$issuer_ls180.v:41316$2095_Y - connect \$850 $and$issuer_ls180.v:41317$2096_Y - connect \$852 $ternary$issuer_ls180.v:41318$2097_Y - connect \$854 $and$issuer_ls180.v:41319$2098_Y - connect \$856 $and$issuer_ls180.v:41320$2099_Y - connect \$858 $not$issuer_ls180.v:41321$2100_Y - connect \$860 $and$issuer_ls180.v:41322$2101_Y - connect \$862 $and$issuer_ls180.v:41323$2102_Y - connect \$864 $ternary$issuer_ls180.v:41324$2103_Y - connect \$866 $and$issuer_ls180.v:41325$2104_Y - connect \$868 $and$issuer_ls180.v:41326$2105_Y - connect \$870 $not$issuer_ls180.v:41327$2106_Y - connect \$872 $and$issuer_ls180.v:41328$2107_Y - connect \$874 $and$issuer_ls180.v:41329$2108_Y - connect \$876 $ternary$issuer_ls180.v:41330$2109_Y - connect \$878 $or$issuer_ls180.v:41331$2110_Y - connect \$880 $or$issuer_ls180.v:41332$2111_Y - connect \$882 $reduce_or$issuer_ls180.v:41333$2112_Y - connect \$884 $and$issuer_ls180.v:41334$2113_Y - connect \$886 $and$issuer_ls180.v:41335$2114_Y - connect \$888 $not$issuer_ls180.v:41336$2115_Y - connect \$890 $and$issuer_ls180.v:41337$2116_Y - connect \$892 $and$issuer_ls180.v:41338$2117_Y - connect \$894 $ternary$issuer_ls180.v:41339$2118_Y - connect \$896 $and$issuer_ls180.v:41340$2119_Y - connect \$898 $and$issuer_ls180.v:41341$2120_Y - connect \$900 $not$issuer_ls180.v:41342$2121_Y - connect \$902 $and$issuer_ls180.v:41343$2122_Y - connect \$904 $and$issuer_ls180.v:41344$2123_Y - connect \$906 $ternary$issuer_ls180.v:41345$2124_Y - connect \$908 $or$issuer_ls180.v:41346$2125_Y - connect \$910 $reduce_or$issuer_ls180.v:41347$2126_Y - connect \$912 $and$issuer_ls180.v:41348$2127_Y - connect \$914 $and$issuer_ls180.v:41349$2128_Y - connect \$916 $not$issuer_ls180.v:41350$2129_Y - connect \$918 $and$issuer_ls180.v:41351$2130_Y - connect \$920 $and$issuer_ls180.v:41352$2131_Y - connect \$922 $ternary$issuer_ls180.v:41353$2132_Y - connect \$924 $reduce_or$issuer_ls180.v:41354$2133_Y - connect \$926 $and$issuer_ls180.v:41355$2134_Y - connect \$928 $and$issuer_ls180.v:41356$2135_Y - connect \$930 $and$issuer_ls180.v:41357$2136_Y - connect \$932 $and$issuer_ls180.v:41358$2137_Y - connect \$934 $and$issuer_ls180.v:41359$2138_Y - connect \$936 $and$issuer_ls180.v:41360$2139_Y - connect \$938 $and$issuer_ls180.v:41361$2140_Y - connect \$940 $and$issuer_ls180.v:41362$2141_Y - connect \$942 $and$issuer_ls180.v:41363$2142_Y - connect \$944 $and$issuer_ls180.v:41364$2143_Y - connect \$946 $and$issuer_ls180.v:41365$2144_Y - connect \$948 $and$issuer_ls180.v:41366$2145_Y - connect \$950 $not$issuer_ls180.v:41367$2146_Y - connect \$952 $and$issuer_ls180.v:41368$2147_Y - connect \$958 $and$issuer_ls180.v:41369$2148_Y - connect \$960 $ternary$issuer_ls180.v:41370$2149_Y - connect \$962 $and$issuer_ls180.v:41371$2150_Y - connect \$965 $and$issuer_ls180.v:41372$2151_Y - connect \$969 $not$issuer_ls180.v:41373$2152_Y - connect \$971 $and$issuer_ls180.v:41374$2153_Y - connect \$976 $and$issuer_ls180.v:41375$2154_Y - connect \$979 $ternary$issuer_ls180.v:41376$2155_Y - connect \$981 $and$issuer_ls180.v:41377$2156_Y - connect \$984 $and$issuer_ls180.v:41378$2157_Y - connect \$988 $not$issuer_ls180.v:41379$2158_Y - connect \$990 $and$issuer_ls180.v:41380$2159_Y - connect \$997 $and$issuer_ls180.v:41381$2160_Y - connect \$202 \$203 - connect \$807 \$808 - connect \$1135 \$1152 - connect \$1350 \$1359 - connect \o_ok 1'0 - connect \ea_ok 1'0 - connect \coresync_rst \core_reset_i - connect \spr_spr1__wen \wp$1788 - connect \spr_spr1__addr$159 \addr_en$1791 [6:0] - connect \spr_spr1__data_i \fus_dest2_o$153 - connect \addr_en$1791 \$1792 - connect \wp$1788 \$1789 - connect \wr_pick_rise$1035 \$1786 - connect \wr_pick$1780 \$1781 - connect \wrpick_SPR_spr1_i \$1778 - connect \wrflag_spr0_spr1_1 \$1776 - connect \state_wen \$1774 - connect \state_data_i$158 \fus_dest5_o$152 - connect \addr_en$1771 \$1772 - connect \wp$1768 \$1769 - connect \wr_pick_rise$995 \$1766 - connect \wr_pick$1760 \$1761 - connect \wrpick_STATE_msr_i \$1758 - connect \wrflag_trap0_msr_4 \$1756 - connect \state_nia_wen \$1752 - connect \state_data_i \$1750 - connect \addr_en$1747 \$1748 - connect \wp$1744 \$1745 - connect \wr_pick_rise$994 \$1742 - connect \wr_pick$1736 \$1737 - connect \wrflag_trap0_nia_3 \$1734 - connect \addr_en$1731 \$1732 - connect \wp$1728 \$1729 - connect \wr_pick_rise$1619 \$1726 - connect \wr_pick$1720 \$1721 - connect \wrpick_STATE_nia_i [1] \$1718 - connect \wrpick_STATE_nia_i [0] \$1716 - connect \wrflag_branch0_nia_2 \$1714 - connect \fast_dest1__wen \$1712 - connect \fast_dest1__addr \$1704 - connect \fast_dest1__data_i \$1696 - connect \addr_en$1687 \$1688 - connect \wp$1684 \$1685 - connect \wr_pick_rise$993 \$1682 - connect \wr_pick$1676 \$1677 - connect \wrflag_trap0_fast1_2 \$1674 - connect \addr_en$1671 \$1672 - connect \wp$1668 \$1669 - connect \wr_pick_rise$1618 \$1666 - connect \wr_pick$1660 \$1661 - connect \wrflag_branch0_fast1_1 \$1658 - connect \addr_en$1655 \$1656 - connect \wp$1652 \$1653 - connect \wr_pick_rise$1034 \$1650 - connect \wr_pick$1644 \$1645 - connect \wrflag_spr0_fast1_2 \$1642 - connect \addr_en$1639 \$1640 - connect \wp$1636 \$1637 - connect \wr_pick_rise$992 \$1634 - connect \wr_pick$1628 \$1629 - connect \wrflag_trap0_fast1_1 \$1626 - connect \addr_en$1623 \$1624 - connect \wp$1620 \$1621 - connect \fus_cu_wr__go_i$140 [2] \wr_pick_rise$1619 - connect \fus_cu_wr__go_i$140 [1] \wr_pick_rise$1618 - connect \fus_cu_wr__go_i$140 [0] \wr_pick_rise$1613 - connect \wr_pick_rise$1613 \$1616 - connect \wr_pick$1609 \$1610 - connect \wrpick_FAST_fast1_i [4] \$1607 - connect \wrpick_FAST_fast1_i [3] \$1605 - connect \wrpick_FAST_fast1_i [2] \$1603 - connect \wrpick_FAST_fast1_i [1] \$1601 - connect \wrpick_FAST_fast1_i [0] \$1599 - connect \wrflag_branch0_fast1_0 \$1597 - connect \xer_wen$157 \$1589 - connect \xer_data_i$156 \$1581 - connect \addr_en$1578 \$1579 - connect \wp$1575 \$1576 - connect \wr_pick_rise$1075 \$1573 - connect \wr_pick$1567 \$1568 - connect \wrflag_mul0_xer_so_3 \$1565 - connect \addr_en$1562 \$1563 - connect \wp$1559 \$1560 - connect \wr_pick_rise$1055 \$1557 - connect \wr_pick$1551 \$1552 - connect \wrflag_div0_xer_so_3 \$1549 - connect \addr_en$1546 \$1547 - connect \wp$1543 \$1544 - connect \wr_pick_rise$1033 \$1541 - connect \wr_pick$1535 \$1536 - connect \wrflag_spr0_xer_so_3 \$1533 - connect \addr_en$1530 \$1531 - connect \wp$1527 \$1528 - connect \wr_pick_rise$957 \$1525 - connect \wr_pick$1519 \$1520 - connect \wrpick_XER_xer_so_i [3] \$1517 - connect \wrpick_XER_xer_so_i [2] \$1515 - connect \wrpick_XER_xer_so_i [1] \$1513 - connect \wrpick_XER_xer_so_i [0] \$1511 - connect \wrflag_alu0_xer_so_4 \$1509 - connect \xer_wen$155 \$1507 - connect \xer_data_i$154 \$1501 - connect \addr_en$1494 \$1495 - connect \wp$1491 \$1492 - connect \wr_pick_rise$1074 \$1489 - connect \wr_pick$1483 \$1484 - connect \wrflag_mul0_xer_ov_2 \$1481 - connect \addr_en$1478 \$1479 - connect \wp$1475 \$1476 - connect \wr_pick_rise$1054 \$1473 - connect \wr_pick$1467 \$1468 - connect \wrflag_div0_xer_ov_2 \$1465 - connect \addr_en$1462 \$1463 - connect \wp$1459 \$1460 - connect \wr_pick_rise$1032 \$1457 - connect \wr_pick$1451 \$1452 - connect \wrflag_spr0_xer_ov_4 \$1449 - connect \addr_en$1446 \$1447 - connect \wp$1443 \$1444 - connect \wr_pick_rise$956 \$1441 - connect \wr_pick$1435 \$1436 - connect \wrpick_XER_xer_ov_i [3] \$1433 - connect \wrpick_XER_xer_ov_i [2] \$1431 - connect \wrpick_XER_xer_ov_i [1] \$1429 - connect \wrpick_XER_xer_ov_i [0] \$1427 - connect \wrflag_alu0_xer_ov_3 \$1425 - connect \xer_wen \$1419 - connect \xer_data_i \$1417 - connect \addr_en$1412 \$1413 - connect \wp$1409 \$1410 - connect \wr_pick_rise$1094 \$1407 - connect \wr_pick$1401 \$1402 - connect \wrflag_shiftrot0_xer_ca_2 \$1399 - connect \addr_en$1396 \$1397 - connect \wp$1393 \$1394 - connect \wr_pick_rise$1031 \$1391 - connect \wr_pick$1385 \$1386 - connect \wrflag_spr0_xer_ca_5 \$1383 - connect \addr_en$1380 \$1381 - connect \wp$1377 \$1378 - connect \wr_pick_rise$955 \$1375 - connect \wr_pick$1369 \$1370 - connect \wrpick_XER_xer_ca_i [2] \$1367 - connect \wrpick_XER_xer_ca_i [1] \$1365 - connect \wrpick_XER_xer_ca_i [0] \$1363 - connect \wrflag_alu0_xer_ca_2 \$1361 - connect \cr_wen \$1359 [7:0] - connect \cr_data_i \$1348 - connect \addr_en$1333 \$1338 - connect \wp$1330 \$1331 - connect \wr_pick_rise$1093 \$1328 - connect \wr_pick$1322 \$1323 - connect \wrflag_shiftrot0_cr_a_1 \$1320 - connect \addr_en$1313 \$1318 - connect \wp$1310 \$1311 - connect \wr_pick_rise$1073 \$1308 - connect \wr_pick$1302 \$1303 - connect \wrflag_mul0_cr_a_1 \$1300 - connect \addr_en$1293 \$1298 - connect \wp$1290 \$1291 - connect \wr_pick_rise$1053 \$1288 - connect \wr_pick$1282 \$1283 - connect \wrflag_div0_cr_a_1 \$1280 - connect \addr_en$1273 \$1278 - connect \wp$1270 \$1271 - connect \wr_pick_rise$1013 \$1268 - connect \wr_pick$1262 \$1263 - connect \wrflag_logical0_cr_a_1 \$1260 - connect \addr_en$1253 \$1258 - connect \wp$1250 \$1251 - connect \wr_pick_rise$974 \$1248 - connect \wr_pick$1242 \$1243 - connect \wrflag_cr0_cr_a_2 \$1240 - connect \addr_en$1233 \$1238 - connect \wp$1230 \$1231 - connect \wr_pick_rise$954 \$1228 - connect \wr_pick$1222 \$1223 - connect \wrpick_CR_cr_a_i [5] \$1220 - connect \wrpick_CR_cr_a_i [4] \$1218 - connect \wrpick_CR_cr_a_i [3] \$1216 - connect \wrpick_CR_cr_a_i [2] \$1214 - connect \wrpick_CR_cr_a_i [1] \$1212 - connect \wrpick_CR_cr_a_i [0] \$1210 - connect \wrflag_alu0_cr_a_1 \$1208 - connect \cr_full_wr__wen \addr_en$1205 - connect \cr_full_wr__data_i \fus_dest2_o - connect \addr_en$1205 \$1206 - connect \wp$1202 \$1203 - connect \wr_pick_rise$973 \$1200 - connect \wr_pick$1194 \$1195 - connect \wrpick_CR_full_cr_i \$1192 - connect \wrflag_cr0_full_cr_1 \$1190 - connect \int_dest1__wen \$1188 - connect \int_dest1__addr \$1170 - connect \int_dest1__data_i \$1152 [63:0] - connect \addr_en$1132 \$1133 - connect \wp$1129 \$1130 - connect \wr_pick_rise$1112 \$1127 - connect \wr_pick$1121 \$1122 - connect \wrflag_ldst0_o_1 \$1119 - connect \addr_en$1116 \$1117 - connect \wp$1113 \$1114 - connect \fus_cu_wr__go_i$105 [1] \wr_pick_rise$1112 - connect \fus_cu_wr__go_i$105 [0] \wr_pick_rise$1107 - connect \wr_pick_rise$1107 \$1110 - connect \wr_pick$1103 \$1104 - connect \wrflag_ldst0_o_0 \$1101 - connect \addr_en$1098 \$1099 - connect \wp$1095 \$1096 - connect \fus_cu_wr__go_i$103 [2] \wr_pick_rise$1094 - connect \fus_cu_wr__go_i$103 [1] \wr_pick_rise$1093 - connect \fus_cu_wr__go_i$103 [0] \wr_pick_rise$1088 - connect \wr_pick_rise$1088 \$1091 - connect \wr_pick$1084 \$1085 - connect \wrflag_shiftrot0_o_0 \$1082 - connect \addr_en$1079 \$1080 - connect \wp$1076 \$1077 - connect \fus_cu_wr__go_i$100 [3] \wr_pick_rise$1075 - connect \fus_cu_wr__go_i$100 [2] \wr_pick_rise$1074 - connect \fus_cu_wr__go_i$100 [1] \wr_pick_rise$1073 - connect \fus_cu_wr__go_i$100 [0] \wr_pick_rise$1068 - connect \wr_pick_rise$1068 \$1071 - connect \wr_pick$1064 \$1065 - connect \wrflag_mul0_o_0 \$1062 - connect \addr_en$1059 \$1060 - connect \wp$1056 \$1057 - connect \fus_cu_wr__go_i$97 [3] \wr_pick_rise$1055 - connect \fus_cu_wr__go_i$97 [2] \wr_pick_rise$1054 - connect \fus_cu_wr__go_i$97 [1] \wr_pick_rise$1053 - connect \fus_cu_wr__go_i$97 [0] \wr_pick_rise$1048 - connect \wr_pick_rise$1048 \$1051 - connect \wr_pick$1044 \$1045 - connect \wrflag_div0_o_0 \$1042 - connect \addr_en$1039 \$1040 - connect \wp$1036 \$1037 - connect \fus_cu_wr__go_i$94 [1] \wr_pick_rise$1035 - connect \fus_cu_wr__go_i$94 [2] \wr_pick_rise$1034 - connect \fus_cu_wr__go_i$94 [3] \wr_pick_rise$1033 - connect \fus_cu_wr__go_i$94 [4] \wr_pick_rise$1032 - connect \fus_cu_wr__go_i$94 [5] \wr_pick_rise$1031 - connect \fus_cu_wr__go_i$94 [0] \wr_pick_rise$1026 - connect \wr_pick_rise$1026 \$1029 - connect \wr_pick$1022 \$1023 - connect \wrflag_spr0_o_0 \$1020 - connect \addr_en$1017 \$1018 - connect \wp$1014 \$1015 - connect \fus_cu_wr__go_i$91 [1] \wr_pick_rise$1013 - connect \fus_cu_wr__go_i$91 [0] \wr_pick_rise$1008 - connect \wr_pick_rise$1008 \$1011 - connect \wr_pick$1004 \$1005 - connect \wrflag_logical0_o_0 \$1002 - connect \addr_en$999 \$1000 - connect \wp$996 \$997 - connect \fus_cu_wr__go_i$88 [4] \wr_pick_rise$995 - connect \fus_cu_wr__go_i$88 [3] \wr_pick_rise$994 - connect \fus_cu_wr__go_i$88 [2] \wr_pick_rise$993 - connect \fus_cu_wr__go_i$88 [1] \wr_pick_rise$992 - connect \fus_cu_wr__go_i$88 [0] \wr_pick_rise$987 - connect \wr_pick_rise$987 \$990 - connect \wr_pick$983 \$984 - connect \wrflag_trap0_o_0 \$981 - connect \addr_en$978 \$979 - connect \wp$975 \$976 - connect \fus_cu_wr__go_i$85 [2] \wr_pick_rise$974 - connect \fus_cu_wr__go_i$85 [1] \wr_pick_rise$973 - connect \fus_cu_wr__go_i$85 [0] \wr_pick_rise$968 - connect \wr_pick_rise$968 \$971 - connect \wr_pick$964 \$965 - connect \wrflag_cr0_o_0 \$962 - connect \addr_en \$960 - connect \wp \$958 - connect \fus_cu_wr__go_i [4] \wr_pick_rise$957 - connect \fus_cu_wr__go_i [3] \wr_pick_rise$956 - connect \fus_cu_wr__go_i [2] \wr_pick_rise$955 - connect \fus_cu_wr__go_i [1] \wr_pick_rise$954 - connect \fus_cu_wr__go_i [0] \wr_pick_rise - connect \wr_pick_rise \$952 - connect \wr_pick \$948 - connect \wrpick_INT_o_i [9] \$946 - connect \wrpick_INT_o_i [8] \$944 - connect \wrpick_INT_o_i [7] \$942 - connect \wrpick_INT_o_i [6] \$940 - connect \wrpick_INT_o_i [5] \$938 - connect \wrpick_INT_o_i [4] \$936 - connect \wrpick_INT_o_i [3] \$934 - connect \wrpick_INT_o_i [2] \$932 - connect \wrpick_INT_o_i [1] \$930 - connect \wrpick_INT_o_i [0] \$928 - connect \wrflag_alu0_o_0 \$926 - connect \spr_spr1__ren \$924 - connect \spr_spr1__addr \addr_en_SPR_spr1_spr0_0 [6:0] - connect \addr_en_SPR_spr1_spr0_0 \$922 - connect \rp_SPR_spr1_spr0_0 \$920 - connect \rdpick_SPR_spr1_i \pick_SPR_spr1_spr0_0 - connect \pick_SPR_spr1_spr0_0 \$918 - connect \rdflag_SPR_spr1_0 \core_spr1_ok - connect \fast_src2__ren \$910 - connect \fast_src2__addr \$908 - connect \addr_en_FAST_fast2_trap0_1 \$906 - connect \rp_FAST_fast2_trap0_1 \$904 - connect \pick_FAST_fast2_trap0_1 \$902 - connect \addr_en_FAST_fast2_branch0_0 \$894 - connect \rp_FAST_fast2_branch0_0 \$892 - connect \rdpick_FAST_fast2_i [1] \pick_FAST_fast2_trap0_1 - connect \rdpick_FAST_fast2_i [0] \pick_FAST_fast2_branch0_0 - connect \pick_FAST_fast2_branch0_0 \$890 - connect \rdflag_FAST_fast2_0 \core_fast2_ok - connect \fast_src1__ren \$882 - connect \fast_src1__addr \$880 - connect \addr_en_FAST_fast1_spr0_2 \$876 - connect \rp_FAST_fast1_spr0_2 \$874 - connect \pick_FAST_fast1_spr0_2 \$872 - connect \addr_en_FAST_fast1_trap0_1 \$864 - connect \rp_FAST_fast1_trap0_1 \$862 - connect \pick_FAST_fast1_trap0_1 \$860 - connect \addr_en_FAST_fast1_branch0_0 \$852 - connect \rp_FAST_fast1_branch0_0 \$850 - connect \rdpick_FAST_fast1_i [2] \pick_FAST_fast1_spr0_2 - connect \rdpick_FAST_fast1_i [1] \pick_FAST_fast1_trap0_1 - connect \rdpick_FAST_fast1_i [0] \pick_FAST_fast1_branch0_0 - connect \pick_FAST_fast1_branch0_0 \$848 - connect \rdflag_FAST_fast1_0 \core_fast1_ok - connect \cr_src3__ren \addr_en_CR_cr_c_cr0_0 [7:0] - connect \addr_en_CR_cr_c_cr0_0 \$840 - connect \rp_CR_cr_c_cr0_0 \$834 - connect \rdpick_CR_cr_c_i \pick_CR_cr_c_cr0_0 - connect \pick_CR_cr_c_cr0_0 \$832 - connect \rdflag_CR_cr_c_0 \core_cr_in2_ok$2 - connect \cr_src2__ren \addr_en_CR_cr_b_cr0_0 [7:0] - connect \addr_en_CR_cr_b_cr0_0 \$824 - connect \rp_CR_cr_b_cr0_0 \$818 - connect \rdpick_CR_cr_b_i \pick_CR_cr_b_cr0_0 - connect \pick_CR_cr_b_cr0_0 \$816 - connect \rdflag_CR_cr_b_0 \core_cr_in2_ok - connect \cr_src1__ren \$808 [7:0] - connect \addr_en_CR_cr_a_branch0_1 \$805 - connect \rp_CR_cr_a_branch0_1 \$799 - connect \fus_cu_rd__go_i$73 [1] \dp_FAST_fast2_branch0_0 - connect \fus_cu_rd__go_i$73 [0] \dp_FAST_fast1_branch0_0 - connect \fus_cu_rd__go_i$73 [2] \dp_CR_cr_a_branch0_1 - connect \pick_CR_cr_a_branch0_1 \$797 - connect \addr_en_CR_cr_a_cr0_0 \$789 - connect \rp_CR_cr_a_cr0_0 \$783 - connect \rdpick_CR_cr_a_i [1] \pick_CR_cr_a_branch0_1 - connect \rdpick_CR_cr_a_i [0] \pick_CR_cr_a_cr0_0 - connect \pick_CR_cr_a_cr0_0 \$781 - connect \rdflag_CR_cr_a_0 \core_cr_in1_ok - connect \cr_full_rd__ren \addr_en_CR_full_cr_cr0_0 - connect \addr_en_CR_full_cr_cr0_0 \$773 - connect \rp_CR_full_cr_cr0_0 \$771 - connect \rdpick_CR_full_cr_i \pick_CR_full_cr_cr0_0 - connect \pick_CR_full_cr_cr0_0 \$769 - connect \rdflag_CR_full_cr_0 \core_core_cr_rd_ok - connect \xer_src3__ren \addr_en_XER_xer_ov_spr0_0 - connect \addr_en_XER_xer_ov_spr0_0 \$761 - connect \rp_XER_xer_ov_spr0_0 \$759 - connect \rdpick_XER_xer_ov_i \pick_XER_xer_ov_spr0_0 - connect \pick_XER_xer_ov_spr0_0 \$757 - connect \rdflag_XER_xer_ov_0 \$749 - connect \xer_src2__ren \$737 - connect \addr_en_XER_xer_ca_shiftrot0_2 \$735 - connect \rp_XER_xer_ca_shiftrot0_2 \$733 - connect \pick_XER_xer_ca_shiftrot0_2 \$731 - connect \addr_en_XER_xer_ca_spr0_1 \$723 - connect \rp_XER_xer_ca_spr0_1 \$721 - connect \pick_XER_xer_ca_spr0_1 \$719 - connect \addr_en_XER_xer_ca_alu0_0 \$711 - connect \rp_XER_xer_ca_alu0_0 \$709 - connect \rdpick_XER_xer_ca_i [2] \pick_XER_xer_ca_shiftrot0_2 - connect \rdpick_XER_xer_ca_i [1] \pick_XER_xer_ca_spr0_1 - connect \rdpick_XER_xer_ca_i [0] \pick_XER_xer_ca_alu0_0 - connect \pick_XER_xer_ca_alu0_0 \$707 - connect \rdflag_XER_xer_ca_0 \$699 - connect \xer_src1__ren \$681 - connect \addr_en_XER_xer_so_shiftrot0_5 \$679 - connect \rp_XER_xer_so_shiftrot0_5 \$677 - connect \pick_XER_xer_so_shiftrot0_5 \$675 - connect \addr_en_XER_xer_so_mul0_4 \$667 - connect \rp_XER_xer_so_mul0_4 \$665 - connect \pick_XER_xer_so_mul0_4 \$663 - connect \addr_en_XER_xer_so_div0_3 \$655 - connect \rp_XER_xer_so_div0_3 \$653 - connect \pick_XER_xer_so_div0_3 \$651 - connect \addr_en_XER_xer_so_spr0_2 \$643 - connect \rp_XER_xer_so_spr0_2 \$641 - connect \pick_XER_xer_so_spr0_2 \$639 - connect \addr_en_XER_xer_so_logical0_1 \$631 - connect \rp_XER_xer_so_logical0_1 \$629 - connect \pick_XER_xer_so_logical0_1 \$627 - connect \addr_en_XER_xer_so_alu0_0 \$619 - connect \rp_XER_xer_so_alu0_0 \$617 - connect \rdpick_XER_xer_so_i [5] \pick_XER_xer_so_shiftrot0_5 - connect \rdpick_XER_xer_so_i [4] \pick_XER_xer_so_mul0_4 - connect \rdpick_XER_xer_so_i [3] \pick_XER_xer_so_div0_3 - connect \rdpick_XER_xer_so_i [2] \pick_XER_xer_so_spr0_2 - connect \rdpick_XER_xer_so_i [1] \pick_XER_xer_so_logical0_1 - connect \rdpick_XER_xer_so_i [0] \pick_XER_xer_so_alu0_0 - connect \pick_XER_xer_so_alu0_0 \$615 - connect \rdflag_XER_xer_so_0 \$607 - connect \int_src3__ren \$595 - connect \int_src3__addr \$593 - connect \addr_en_INT_rc_ldst0_1 \$591 - connect \rp_INT_rc_ldst0_1 \$589 - connect \pick_INT_rc_ldst0_1 \$587 - connect \addr_en_INT_rc_shiftrot0_0 \$579 - connect \rp_INT_rc_shiftrot0_0 \$577 - connect \rdpick_INT_rc_i [1] \pick_INT_rc_ldst0_1 - connect \rdpick_INT_rc_i [0] \pick_INT_rc_shiftrot0_0 - connect \pick_INT_rc_shiftrot0_0 \$575 - connect \rdflag_INT_rc_0 \core_reg3_ok - connect \int_src2__ren \$567 - connect \int_src2__addr \$565 - connect \addr_en_INT_rb_ldst0_7 \$551 - connect \rp_INT_rb_ldst0_7 \$549 - connect \pick_INT_rb_ldst0_7 \$547 - connect \addr_en_INT_rb_shiftrot0_6 \$539 - connect \rp_INT_rb_shiftrot0_6 \$537 - connect \pick_INT_rb_shiftrot0_6 \$535 - connect \addr_en_INT_rb_mul0_5 \$527 - connect \rp_INT_rb_mul0_5 \$525 - connect \pick_INT_rb_mul0_5 \$523 - connect \addr_en_INT_rb_div0_4 \$515 - connect \rp_INT_rb_div0_4 \$513 - connect \pick_INT_rb_div0_4 \$511 - connect \addr_en_INT_rb_logical0_3 \$503 - connect \rp_INT_rb_logical0_3 \$501 - connect \pick_INT_rb_logical0_3 \$499 - connect \addr_en_INT_rb_trap0_2 \$491 - connect \rp_INT_rb_trap0_2 \$489 - connect \pick_INT_rb_trap0_2 \$487 - connect \addr_en_INT_rb_cr0_1 \$479 - connect \rp_INT_rb_cr0_1 \$477 - connect \pick_INT_rb_cr0_1 \$475 - connect \addr_en_INT_rb_alu0_0 \$467 - connect \rp_INT_rb_alu0_0 \$465 - connect \rdpick_INT_rb_i [7] \pick_INT_rb_ldst0_7 - connect \rdpick_INT_rb_i [6] \pick_INT_rb_shiftrot0_6 - connect \rdpick_INT_rb_i [5] \pick_INT_rb_mul0_5 - connect \rdpick_INT_rb_i [4] \pick_INT_rb_div0_4 - connect \rdpick_INT_rb_i [3] \pick_INT_rb_logical0_3 - connect \rdpick_INT_rb_i [2] \pick_INT_rb_trap0_2 - connect \rdpick_INT_rb_i [1] \pick_INT_rb_cr0_1 - connect \rdpick_INT_rb_i [0] \pick_INT_rb_alu0_0 - connect \pick_INT_rb_alu0_0 \$463 - connect \rdflag_INT_rb_0 \core_reg2_ok - connect \int_src1__ren \$455 - connect \int_src1__addr \$453 - connect \addr_en_INT_ra_ldst0_8 \$437 - connect \rp_INT_ra_ldst0_8 \$435 - connect \fus_cu_rd__go_i$53 [2] \dp_INT_rc_ldst0_1 - connect \fus_cu_rd__go_i$53 [1] \dp_INT_rb_ldst0_7 - connect \fus_cu_rd__go_i$53 [0] \dp_INT_ra_ldst0_8 - connect \pick_INT_ra_ldst0_8 \$433 - connect \addr_en_INT_ra_shiftrot0_7 \$425 - connect \rp_INT_ra_shiftrot0_7 \$423 - connect \fus_cu_rd__go_i$50 [4] \dp_XER_xer_ca_shiftrot0_2 - connect \fus_cu_rd__go_i$50 [3] \dp_XER_xer_so_shiftrot0_5 - connect \fus_cu_rd__go_i$50 [2] \dp_INT_rc_shiftrot0_0 - connect \fus_cu_rd__go_i$50 [1] \dp_INT_rb_shiftrot0_6 - connect \fus_cu_rd__go_i$50 [0] \dp_INT_ra_shiftrot0_7 - connect \pick_INT_ra_shiftrot0_7 \$421 - connect \addr_en_INT_ra_mul0_6 \$413 - connect \rp_INT_ra_mul0_6 \$411 - connect \fus_cu_rd__go_i$47 [2] \dp_XER_xer_so_mul0_4 - connect \fus_cu_rd__go_i$47 [1] \dp_INT_rb_mul0_5 - connect \fus_cu_rd__go_i$47 [0] \dp_INT_ra_mul0_6 - connect \pick_INT_ra_mul0_6 \$409 - connect \addr_en_INT_ra_div0_5 \$401 - connect \rp_INT_ra_div0_5 \$399 - connect \fus_cu_rd__go_i$44 [2] \dp_XER_xer_so_div0_3 - connect \fus_cu_rd__go_i$44 [1] \dp_INT_rb_div0_4 - connect \fus_cu_rd__go_i$44 [0] \dp_INT_ra_div0_5 - connect \pick_INT_ra_div0_5 \$397 - connect \addr_en_INT_ra_spr0_4 \$389 - connect \rp_INT_ra_spr0_4 \$387 - connect \fus_cu_rd__go_i$41 [1] \dp_SPR_spr1_spr0_0 - connect \fus_cu_rd__go_i$41 [2] \dp_FAST_fast1_spr0_2 - connect \fus_cu_rd__go_i$41 [4] \dp_XER_xer_ov_spr0_0 - connect \fus_cu_rd__go_i$41 [5] \dp_XER_xer_ca_spr0_1 - connect \fus_cu_rd__go_i$41 [3] \dp_XER_xer_so_spr0_2 - connect \fus_cu_rd__go_i$41 [0] \dp_INT_ra_spr0_4 - connect \pick_INT_ra_spr0_4 \$385 - connect \addr_en_INT_ra_logical0_3 \$377 - connect \rp_INT_ra_logical0_3 \$375 - connect \fus_cu_rd__go_i$38 [2] \dp_XER_xer_so_logical0_1 - connect \fus_cu_rd__go_i$38 [1] \dp_INT_rb_logical0_3 - connect \fus_cu_rd__go_i$38 [0] \dp_INT_ra_logical0_3 - connect \pick_INT_ra_logical0_3 \$373 - connect \addr_en_INT_ra_trap0_2 \$365 - connect \rp_INT_ra_trap0_2 \$363 - connect \fus_cu_rd__go_i$35 [3] \dp_FAST_fast2_trap0_1 - connect \fus_cu_rd__go_i$35 [2] \dp_FAST_fast1_trap0_1 - connect \fus_cu_rd__go_i$35 [1] \dp_INT_rb_trap0_2 - connect \fus_cu_rd__go_i$35 [0] \dp_INT_ra_trap0_2 - connect \pick_INT_ra_trap0_2 \$361 - connect \addr_en_INT_ra_cr0_1 \$353 - connect \rp_INT_ra_cr0_1 \$351 - connect \fus_cu_rd__go_i$32 [5] \dp_CR_cr_c_cr0_0 - connect \fus_cu_rd__go_i$32 [4] \dp_CR_cr_b_cr0_0 - connect \fus_cu_rd__go_i$32 [3] \dp_CR_cr_a_cr0_0 - connect \fus_cu_rd__go_i$32 [2] \dp_CR_full_cr_cr0_0 - connect \fus_cu_rd__go_i$32 [1] \dp_INT_rb_cr0_1 - connect \fus_cu_rd__go_i$32 [0] \dp_INT_ra_cr0_1 - connect \pick_INT_ra_cr0_1 \$349 - connect \addr_en_INT_ra_alu0_0 \$341 - connect \rp_INT_ra_alu0_0 \$339 - connect \fus_cu_rd__go_i [3] \dp_XER_xer_ca_alu0_0 - connect \fus_cu_rd__go_i [2] \dp_XER_xer_so_alu0_0 - connect \fus_cu_rd__go_i [1] \dp_INT_rb_alu0_0 - connect \fus_cu_rd__go_i [0] \dp_INT_ra_alu0_0 - connect \rdpick_INT_ra_i [8] \pick_INT_ra_ldst0_8 - connect \rdpick_INT_ra_i [7] \pick_INT_ra_shiftrot0_7 - connect \rdpick_INT_ra_i [6] \pick_INT_ra_mul0_6 - connect \rdpick_INT_ra_i [5] \pick_INT_ra_div0_5 - connect \rdpick_INT_ra_i [4] \pick_INT_ra_spr0_4 - connect \rdpick_INT_ra_i [3] \pick_INT_ra_logical0_3 - connect \rdpick_INT_ra_i [2] \pick_INT_ra_trap0_2 - connect \rdpick_INT_ra_i [1] \pick_INT_ra_cr0_1 - connect \rdpick_INT_ra_i [0] \pick_INT_ra_alu0_0 - connect \pick_INT_ra_alu0_0 \$337 - connect \rdflag_INT_ra_0 \core_reg1_ok - connect \en_ldst0 \$196 - connect \en_shiftrot0 \$192 - connect \en_mul0 \$188 - connect \en_div0 \$184 - connect \en_spr0 \$180 - connect \en_logical0 \$176 - connect \en_trap0 \$172 - connect \en_branch0 \$168 - connect \en_cr0 \$164 - connect \fu_enable [9] \en_ldst0 - connect \fu_enable [8] \en_shiftrot0 - connect \fu_enable [7] \en_mul0 - connect \fu_enable [6] \en_div0 - connect \fu_enable [5] \en_spr0 - connect \fu_enable [4] \en_logical0 - connect \fu_enable [3] \en_trap0 - connect \fu_enable [2] \en_branch0 - connect \fu_enable [1] \en_cr0 - connect \fu_enable [0] \en_alu0 - connect \en_alu0 \$160 - connect \dec_LDST_bigendian \bigendian_i - connect \dec_LDST_raw_opcode_in \raw_insn_i - connect \dec_SHIFT_ROT_bigendian \bigendian_i - connect \dec_SHIFT_ROT_raw_opcode_in \raw_insn_i - connect \dec_MUL_bigendian \bigendian_i - connect \dec_MUL_raw_opcode_in \raw_insn_i - connect \dec_DIV_bigendian \bigendian_i - connect \dec_DIV_raw_opcode_in \raw_insn_i - connect \dec_SPR_bigendian \bigendian_i - connect \dec_SPR_raw_opcode_in \raw_insn_i - connect \dec_LOGICAL_bigendian \bigendian_i - connect \dec_LOGICAL_raw_opcode_in \raw_insn_i - connect \dec_BRANCH_bigendian \bigendian_i - connect \dec_BRANCH_raw_opcode_in \raw_insn_i - connect \dec_CR_bigendian \bigendian_i - connect \dec_CR_raw_opcode_in \raw_insn_i - connect \dec_ALU_bigendian \bigendian_i - connect \dec_ALU_raw_opcode_in \raw_insn_i -end -attribute \src "issuer_ls180.v:47603.1-48236.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.cr" -attribute \generator "nMigen" -module \cr - attribute \src "issuer_ls180.v:47604.7-47604.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:48150.3-48158.6" - wire width 8 $0\ren_delay$17$next[7:0]$2967 - attribute \src "issuer_ls180.v:47986.3-47987.43" - wire width 8 $0\ren_delay$17[7:0]$2964 - attribute \src "issuer_ls180.v:47932.13-47932.35" - wire width 8 $0\ren_delay$17[7:0]$2981 - attribute \src "issuer_ls180.v:48169.3-48177.6" - wire width 8 $0\ren_delay$34$next[7:0]$2971 - attribute \src "issuer_ls180.v:47984.3-47985.43" - wire width 8 $0\ren_delay$34[7:0]$2962 - attribute \src "issuer_ls180.v:47936.13-47936.35" - wire width 8 $0\ren_delay$34[7:0]$2983 - attribute \src "issuer_ls180.v:48188.3-48196.6" - wire width 8 $0\ren_delay$next[7:0]$2975 - attribute \src "issuer_ls180.v:47988.3-47989.35" - wire width 8 $0\ren_delay[7:0] - attribute \src "issuer_ls180.v:48197.3-48206.6" - wire width 4 $0\src1__data_o[3:0] - attribute \src "issuer_ls180.v:48159.3-48168.6" - wire width 4 $0\src2__data_o[3:0] - attribute \src "issuer_ls180.v:48178.3-48187.6" - wire width 4 $0\src3__data_o[3:0] - attribute \src "issuer_ls180.v:48150.3-48158.6" - wire width 8 $1\ren_delay$17$next[7:0]$2968 - attribute \src "issuer_ls180.v:48169.3-48177.6" - wire width 8 $1\ren_delay$34$next[7:0]$2972 - attribute \src "issuer_ls180.v:48188.3-48196.6" - wire width 8 $1\ren_delay$next[7:0]$2976 - attribute \src "issuer_ls180.v:47930.13-47930.30" - wire width 8 $1\ren_delay[7:0] - attribute \src "issuer_ls180.v:48197.3-48206.6" - wire width 4 $1\src1__data_o[3:0] - attribute \src "issuer_ls180.v:48159.3-48168.6" - wire width 4 $1\src2__data_o[3:0] - attribute \src "issuer_ls180.v:48178.3-48187.6" - wire width 4 $1\src3__data_o[3:0] - attribute \src "issuer_ls180.v:47960.17-47960.125" - wire width 4 $or$issuer_ls180.v:47960$2937_Y - attribute \src "issuer_ls180.v:47961.18-47961.126" - wire width 4 $or$issuer_ls180.v:47961$2938_Y - attribute \src "issuer_ls180.v:47962.18-47962.96" - wire width 4 $or$issuer_ls180.v:47962$2939_Y - attribute \src "issuer_ls180.v:47963.18-47963.96" - wire width 4 $or$issuer_ls180.v:47963$2940_Y - attribute \src "issuer_ls180.v:47966.18-47966.126" - wire width 4 $or$issuer_ls180.v:47966$2943_Y - attribute \src "issuer_ls180.v:47967.18-47967.126" - wire width 4 $or$issuer_ls180.v:47967$2944_Y - attribute \src "issuer_ls180.v:47968.18-47968.97" - wire width 4 $or$issuer_ls180.v:47968$2945_Y - attribute \src "issuer_ls180.v:47969.18-47969.126" - wire width 4 $or$issuer_ls180.v:47969$2946_Y - attribute \src "issuer_ls180.v:47970.18-47970.126" - wire width 4 $or$issuer_ls180.v:47970$2947_Y - attribute \src "issuer_ls180.v:47971.18-47971.97" - wire width 4 $or$issuer_ls180.v:47971$2948_Y - attribute \src "issuer_ls180.v:47972.18-47972.97" - wire width 4 $or$issuer_ls180.v:47972$2949_Y - attribute \src "issuer_ls180.v:47974.18-47974.126" - wire width 4 $or$issuer_ls180.v:47974$2951_Y - attribute \src "issuer_ls180.v:47975.17-47975.125" - wire width 4 $or$issuer_ls180.v:47975$2952_Y - attribute \src "issuer_ls180.v:47976.18-47976.126" - wire width 4 $or$issuer_ls180.v:47976$2953_Y - attribute \src "issuer_ls180.v:47977.18-47977.97" - wire width 4 $or$issuer_ls180.v:47977$2954_Y - attribute \src "issuer_ls180.v:47978.18-47978.126" - wire width 4 $or$issuer_ls180.v:47978$2955_Y - attribute \src "issuer_ls180.v:47979.18-47979.126" - wire width 4 $or$issuer_ls180.v:47979$2956_Y - attribute \src "issuer_ls180.v:47980.18-47980.97" - wire width 4 $or$issuer_ls180.v:47980$2957_Y - attribute \src "issuer_ls180.v:47981.18-47981.97" - wire width 4 $or$issuer_ls180.v:47981$2958_Y - attribute \src "issuer_ls180.v:47982.17-47982.125" - wire width 4 $or$issuer_ls180.v:47982$2959_Y - attribute \src "issuer_ls180.v:47983.17-47983.94" - wire width 4 $or$issuer_ls180.v:47983$2960_Y - attribute \src "issuer_ls180.v:47964.18-47964.100" - wire $reduce_or$issuer_ls180.v:47964$2941_Y - attribute \src "issuer_ls180.v:47965.17-47965.95" - wire $reduce_or$issuer_ls180.v:47965$2942_Y - attribute \src "issuer_ls180.v:47973.18-47973.100" - wire $reduce_or$issuer_ls180.v:47973$2950_Y - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire \$1 - attribute \src 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\reg_2_dest22__data_i - connect \dest22__wen \reg_2_dest22__wen - connect \r22__data_o \reg_2_r22__data_o - connect \r22__ren \reg_2_r22__ren - connect \r2__data_o \reg_2_r2__data_o - connect \r2__ren \reg_2_r2__ren - connect \src12__data_o \reg_2_src12__data_o - connect \src12__ren \reg_2_src12__ren - connect \src22__data_o \reg_2_src22__data_o - connect \src22__ren \reg_2_src22__ren - connect \src32__data_o \reg_2_src32__data_o - connect \src32__ren \reg_2_src32__ren - connect \w2__data_i \reg_2_w2__data_i - connect \w2__wen \reg_2_w2__wen - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:48050.9-48069.4" - cell \reg_3 \reg_3 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dest13__data_i \reg_3_dest13__data_i - connect \dest13__wen \reg_3_dest13__wen - connect \dest23__data_i \reg_3_dest23__data_i - connect \dest23__wen \reg_3_dest23__wen - connect \r23__data_o \reg_3_r23__data_o - connect \r23__ren \reg_3_r23__ren - connect \r3__data_o \reg_3_r3__data_o - connect \r3__ren \reg_3_r3__ren - connect \src13__data_o \reg_3_src13__data_o - connect \src13__ren \reg_3_src13__ren - connect \src23__data_o \reg_3_src23__data_o - connect \src23__ren \reg_3_src23__ren - connect \src33__data_o \reg_3_src33__data_o - connect \src33__ren \reg_3_src33__ren - connect \w3__data_i \reg_3_w3__data_i - connect \w3__wen \reg_3_w3__wen - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:48070.9-48089.4" - cell \reg_4 \reg_4 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dest14__data_i \reg_4_dest14__data_i - connect \dest14__wen \reg_4_dest14__wen - connect \dest24__data_i \reg_4_dest24__data_i - connect \dest24__wen \reg_4_dest24__wen - connect \r24__data_o \reg_4_r24__data_o - connect \r24__ren \reg_4_r24__ren - connect \r4__data_o \reg_4_r4__data_o - connect \r4__ren \reg_4_r4__ren - connect \src14__data_o \reg_4_src14__data_o - connect \src14__ren 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\src "issuer_ls180.v:47986.3-47987.43" - process $proc$issuer_ls180.v:47986$2963 - assign { } { } - assign $0\ren_delay$17[7:0]$2964 \ren_delay$17$next - sync posedge \coresync_clk - update \ren_delay$17 $0\ren_delay$17[7:0]$2964 - end - attribute \src "issuer_ls180.v:47988.3-47989.35" - process $proc$issuer_ls180.v:47988$2965 - assign { } { } - assign $0\ren_delay[7:0] \ren_delay$next - sync posedge \coresync_clk - update \ren_delay $0\ren_delay[7:0] - end - attribute \src "issuer_ls180.v:48150.3-48158.6" - process $proc$issuer_ls180.v:48150$2966 - assign { } { } - assign { } { } - assign $0\ren_delay$17$next[7:0]$2967 $1\ren_delay$17$next[7:0]$2968 - attribute \src "issuer_ls180.v:48151.5-48151.29" - switch \initial - attribute \src "issuer_ls180.v:48151.9-48151.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$17$next[7:0]$2968 8'00000000 - case - assign $1\ren_delay$17$next[7:0]$2968 \src2__ren - end - sync always - update \ren_delay$17$next $0\ren_delay$17$next[7:0]$2967 - end - attribute \src "issuer_ls180.v:48159.3-48168.6" - process $proc$issuer_ls180.v:48159$2969 - assign { } { } - assign { } { } - assign $0\src2__data_o[3:0] $1\src2__data_o[3:0] - attribute \src "issuer_ls180.v:48160.5-48160.29" - switch \initial - attribute \src "issuer_ls180.v:48160.9-48160.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch \$18 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src2__data_o[3:0] \$32 - case - assign $1\src2__data_o[3:0] 4'0000 - end - sync always - update \src2__data_o $0\src2__data_o[3:0] - end - attribute \src "issuer_ls180.v:48169.3-48177.6" - process $proc$issuer_ls180.v:48169$2970 - assign { } { } - assign { } { } - assign $0\ren_delay$34$next[7:0]$2971 $1\ren_delay$34$next[7:0]$2972 - attribute \src "issuer_ls180.v:48170.5-48170.29" - switch \initial - attribute \src "issuer_ls180.v:48170.9-48170.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$34$next[7:0]$2972 8'00000000 - case - assign $1\ren_delay$34$next[7:0]$2972 \src3__ren - end - sync always - update \ren_delay$34$next $0\ren_delay$34$next[7:0]$2971 - end - attribute \src "issuer_ls180.v:48178.3-48187.6" - process $proc$issuer_ls180.v:48178$2973 - assign { } { } - assign { } { } - assign $0\src3__data_o[3:0] $1\src3__data_o[3:0] - attribute \src "issuer_ls180.v:48179.5-48179.29" - switch \initial - attribute \src "issuer_ls180.v:48179.9-48179.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch \$35 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src3__data_o[3:0] \$49 - case - assign $1\src3__data_o[3:0] 4'0000 - end - sync always - update \src3__data_o $0\src3__data_o[3:0] - end - attribute \src "issuer_ls180.v:48188.3-48196.6" - process $proc$issuer_ls180.v:48188$2974 - assign { } { } - assign { } { } - assign $0\ren_delay$next[7:0]$2975 $1\ren_delay$next[7:0]$2976 - attribute \src "issuer_ls180.v:48189.5-48189.29" - switch \initial - attribute \src "issuer_ls180.v:48189.9-48189.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$next[7:0]$2976 8'00000000 - case - assign $1\ren_delay$next[7:0]$2976 \src1__ren - end - sync always - update \ren_delay$next $0\ren_delay$next[7:0]$2975 - end - attribute \src "issuer_ls180.v:48197.3-48206.6" - process $proc$issuer_ls180.v:48197$2977 - assign { } { } - assign { } { } - assign $0\src1__data_o[3:0] $1\src1__data_o[3:0] - attribute \src "issuer_ls180.v:48198.5-48198.29" - switch \initial - attribute \src "issuer_ls180.v:48198.9-48198.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src1__data_o[3:0] \$15 - case - assign $1\src1__data_o[3:0] 4'0000 - end - sync always - update \src1__data_o $0\src1__data_o[3:0] - end - connect \$9 $or$issuer_ls180.v:47960$2937_Y - connect \$11 $or$issuer_ls180.v:47961$2938_Y - connect \$13 $or$issuer_ls180.v:47962$2939_Y - connect \$15 $or$issuer_ls180.v:47963$2940_Y - connect \$18 $reduce_or$issuer_ls180.v:47964$2941_Y - connect \$1 $reduce_or$issuer_ls180.v:47965$2942_Y - connect \$20 $or$issuer_ls180.v:47966$2943_Y - connect \$22 $or$issuer_ls180.v:47967$2944_Y - connect \$24 $or$issuer_ls180.v:47968$2945_Y - connect \$26 $or$issuer_ls180.v:47969$2946_Y - connect \$28 $or$issuer_ls180.v:47970$2947_Y - connect \$30 $or$issuer_ls180.v:47971$2948_Y - connect \$32 $or$issuer_ls180.v:47972$2949_Y - connect \$35 $reduce_or$issuer_ls180.v:47973$2950_Y - connect \$37 $or$issuer_ls180.v:47974$2951_Y - connect \$3 $or$issuer_ls180.v:47975$2952_Y - connect \$39 $or$issuer_ls180.v:47976$2953_Y - connect \$41 $or$issuer_ls180.v:47977$2954_Y - connect \$43 $or$issuer_ls180.v:47978$2955_Y - connect \$45 $or$issuer_ls180.v:47979$2956_Y - connect \$47 $or$issuer_ls180.v:47980$2957_Y - connect \$49 $or$issuer_ls180.v:47981$2958_Y - connect \$5 $or$issuer_ls180.v:47982$2959_Y - connect \$7 $or$issuer_ls180.v:47983$2960_Y - connect \wen$51 8'00000000 - connect \data_i$52 4'0000 - connect { \reg_7_w7__wen \reg_6_w6__wen \reg_5_w5__wen \reg_4_w4__wen \reg_3_w3__wen \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen - connect { \reg_7_w7__data_i \reg_6_w6__data_i \reg_5_w5__data_i \reg_4_w4__data_i \reg_3_w3__data_i \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } \full_wr__data_i - connect { \reg_7_r27__ren \reg_6_r26__ren \reg_5_r25__ren \reg_4_r24__ren \reg_3_r23__ren \reg_2_r22__ren \reg_1_r21__ren \reg_0_r20__ren } \full_rd2__ren - connect \full_rd2__data_o { \reg_7_r27__data_o \reg_6_r26__data_o \reg_5_r25__data_o \reg_4_r24__data_o \reg_3_r23__data_o \reg_2_r22__data_o \reg_1_r21__data_o \reg_0_r20__data_o } - connect { \reg_7_r7__ren \reg_6_r6__ren \reg_5_r5__ren \reg_4_r4__ren \reg_3_r3__ren \reg_2_r2__ren \reg_1_r1__ren \reg_0_r0__ren } \full_rd__ren - connect \full_rd__data_o { \reg_7_r7__data_o \reg_6_r6__data_o \reg_5_r5__data_o \reg_4_r4__data_o \reg_3_r3__data_o \reg_2_r2__data_o \reg_1_r1__data_o \reg_0_r0__data_o } - connect \reg_7_dest27__data_i 4'0000 - connect \reg_6_dest26__data_i 4'0000 - connect \reg_5_dest25__data_i 4'0000 - connect \reg_4_dest24__data_i 4'0000 - connect \reg_3_dest23__data_i 4'0000 - connect \reg_2_dest22__data_i 4'0000 - connect \reg_1_dest21__data_i 4'0000 - connect \reg_0_dest20__data_i 4'0000 - connect { \reg_7_dest27__wen \reg_6_dest26__wen \reg_5_dest25__wen \reg_4_dest24__wen \reg_3_dest23__wen \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } 8'00000000 - connect \reg_7_dest17__data_i \data_i - connect \reg_6_dest16__data_i \data_i - connect \reg_5_dest15__data_i \data_i - connect \reg_4_dest14__data_i \data_i - connect \reg_3_dest13__data_i \data_i - connect \reg_2_dest12__data_i \data_i - connect \reg_1_dest11__data_i \data_i - connect \reg_0_dest10__data_i \data_i - connect { \reg_7_dest17__wen \reg_6_dest16__wen \reg_5_dest15__wen \reg_4_dest14__wen \reg_3_dest13__wen \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen - connect { \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren - connect { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren - connect { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren -end -attribute \src "issuer_ls180.v:48240.1-49291.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0" -attribute \generator "nMigen" -module \cr0 - attribute \src "issuer_ls180.v:48868.3-48869.25" - wire $0\all_rd_dly[0:0] - attribute \src "issuer_ls180.v:49065.3-49076.6" - wire width 12 $0\alu_cr0_cr_op__fn_unit$next[11:0]$3103 - attribute \src "issuer_ls180.v:48840.3-48841.61" - wire width 12 $0\alu_cr0_cr_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:49065.3-49076.6" - wire width 32 $0\alu_cr0_cr_op__insn$next[31:0]$3104 - attribute \src "issuer_ls180.v:48842.3-48843.55" - wire width 32 $0\alu_cr0_cr_op__insn[31:0] - attribute \src "issuer_ls180.v:49065.3-49076.6" - wire width 7 $0\alu_cr0_cr_op__insn_type$next[6:0]$3105 - attribute \src "issuer_ls180.v:48838.3-48839.65" - wire width 7 $0\alu_cr0_cr_op__insn_type[6:0] - attribute \src "issuer_ls180.v:48866.3-48867.39" - wire $0\alu_done_dly[0:0] - attribute \src "issuer_ls180.v:49212.3-49220.6" - wire $0\alu_l_r_alu$next[0:0]$3155 - attribute \src "issuer_ls180.v:48870.3-48871.39" - wire $0\alu_l_r_alu[0:0] - attribute \src "issuer_ls180.v:49203.3-49211.6" - wire $0\alui_l_r_alui$next[0:0]$3152 - attribute \src "issuer_ls180.v:48872.3-48873.43" - wire $0\alui_l_r_alui[0:0] - attribute \src "issuer_ls180.v:49077.3-49098.6" - wire width 64 $0\data_r0__o$next[63:0]$3110 - attribute \src "issuer_ls180.v:48834.3-48835.37" - wire width 64 $0\data_r0__o[63:0] - attribute \src "issuer_ls180.v:49077.3-49098.6" - wire $0\data_r0__o_ok$next[0:0]$3111 - attribute \src "issuer_ls180.v:48836.3-48837.43" - wire $0\data_r0__o_ok[0:0] - attribute \src "issuer_ls180.v:49099.3-49120.6" - wire width 32 $0\data_r1__full_cr$next[31:0]$3118 - attribute \src "issuer_ls180.v:48890.3-48891.49" - wire width 32 $0\data_r1__full_cr[31:0] - attribute \src "issuer_ls180.v:49099.3-49120.6" - wire $0\data_r1__full_cr_ok$next[0:0]$3119 - attribute \src "issuer_ls180.v:48892.3-48893.55" - wire $0\data_r1__full_cr_ok[0:0] - attribute \src "issuer_ls180.v:49121.3-49142.6" - wire width 4 $0\data_r2__cr_a$next[3:0]$3126 - attribute \src "issuer_ls180.v:48886.3-48887.43" - wire width 4 $0\data_r2__cr_a[3:0] - attribute \src "issuer_ls180.v:49121.3-49142.6" - wire $0\data_r2__cr_a_ok$next[0:0]$3127 - attribute \src "issuer_ls180.v:48888.3-48889.49" - wire $0\data_r2__cr_a_ok[0:0] - attribute \src "issuer_ls180.v:49221.3-49230.6" - wire width 64 $0\dest1_o[63:0] - attribute \src "issuer_ls180.v:49231.3-49240.6" - wire width 32 $0\dest2_o[31:0] - attribute \src "issuer_ls180.v:49241.3-49250.6" - wire width 4 $0\dest3_o[3:0] - attribute \src "issuer_ls180.v:48241.7-48241.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:49020.3-49028.6" - wire $0\opc_l_r_opc$next[0:0]$3088 - attribute \src "issuer_ls180.v:48852.3-48853.39" - wire $0\opc_l_r_opc[0:0] - attribute \src "issuer_ls180.v:49011.3-49019.6" - wire $0\opc_l_s_opc$next[0:0]$3085 - attribute \src "issuer_ls180.v:48854.3-48855.39" - wire $0\opc_l_s_opc[0:0] - attribute \src "issuer_ls180.v:49251.3-49259.6" - wire width 3 $0\prev_wr_go$next[2:0]$3161 - attribute \src "issuer_ls180.v:48864.3-48865.37" - wire width 3 $0\prev_wr_go[2:0] - attribute \src "issuer_ls180.v:48965.3-48974.6" - wire $0\req_done[0:0] - attribute \src "issuer_ls180.v:49056.3-49064.6" - wire width 3 $0\req_l_r_req$next[2:0]$3100 - attribute \src "issuer_ls180.v:48844.3-48845.39" - wire width 3 $0\req_l_r_req[2:0] - attribute \src "issuer_ls180.v:49047.3-49055.6" - wire width 3 $0\req_l_s_req$next[2:0]$3097 - attribute \src "issuer_ls180.v:48846.3-48847.39" - wire width 3 $0\req_l_s_req[2:0] - attribute \src "issuer_ls180.v:48984.3-48992.6" - wire $0\rok_l_r_rdok$next[0:0]$3076 - attribute \src "issuer_ls180.v:48860.3-48861.41" - wire $0\rok_l_r_rdok[0:0] - attribute \src "issuer_ls180.v:48975.3-48983.6" - wire $0\rok_l_s_rdok$next[0:0]$3073 - attribute \src "issuer_ls180.v:48862.3-48863.41" - wire $0\rok_l_s_rdok[0:0] - attribute \src "issuer_ls180.v:49002.3-49010.6" - wire $0\rst_l_r_rst$next[0:0]$3082 - attribute \src "issuer_ls180.v:48856.3-48857.39" - wire $0\rst_l_r_rst[0:0] - attribute \src "issuer_ls180.v:48993.3-49001.6" - wire $0\rst_l_s_rst$next[0:0]$3079 - attribute \src "issuer_ls180.v:48858.3-48859.39" - wire $0\rst_l_s_rst[0:0] - attribute \src "issuer_ls180.v:49038.3-49046.6" - wire width 6 $0\src_l_r_src$next[5:0]$3094 - attribute \src "issuer_ls180.v:48848.3-48849.39" - wire width 6 $0\src_l_r_src[5:0] - attribute \src "issuer_ls180.v:49029.3-49037.6" - wire width 6 $0\src_l_s_src$next[5:0]$3091 - attribute \src "issuer_ls180.v:48850.3-48851.39" - wire width 6 $0\src_l_s_src[5:0] - attribute \src "issuer_ls180.v:49143.3-49152.6" - wire width 64 $0\src_r0$next[63:0]$3134 - attribute \src "issuer_ls180.v:48884.3-48885.29" - wire width 64 $0\src_r0[63:0] - attribute \src "issuer_ls180.v:49153.3-49162.6" - wire width 64 $0\src_r1$next[63:0]$3137 - attribute \src "issuer_ls180.v:48882.3-48883.29" - wire width 64 $0\src_r1[63:0] - attribute \src "issuer_ls180.v:49163.3-49172.6" - wire width 32 $0\src_r2$next[31:0]$3140 - attribute \src "issuer_ls180.v:48880.3-48881.29" - wire width 32 $0\src_r2[31:0] - attribute \src "issuer_ls180.v:49173.3-49182.6" - wire width 4 $0\src_r3$next[3:0]$3143 - attribute \src "issuer_ls180.v:48878.3-48879.29" - wire width 4 $0\src_r3[3:0] - attribute \src "issuer_ls180.v:49183.3-49192.6" - wire width 4 $0\src_r4$next[3:0]$3146 - attribute \src "issuer_ls180.v:48876.3-48877.29" - wire width 4 $0\src_r4[3:0] - attribute \src "issuer_ls180.v:49193.3-49202.6" - wire width 4 $0\src_r5$next[3:0]$3149 - attribute \src "issuer_ls180.v:48874.3-48875.29" - wire width 4 $0\src_r5[3:0] - attribute \src "issuer_ls180.v:48359.7-48359.24" - wire $1\all_rd_dly[0:0] - attribute \src "issuer_ls180.v:49065.3-49076.6" - wire width 12 $1\alu_cr0_cr_op__fn_unit$next[11:0]$3106 - attribute \src "issuer_ls180.v:48388.14-48388.46" - wire width 12 $1\alu_cr0_cr_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:49065.3-49076.6" - wire width 32 $1\alu_cr0_cr_op__insn$next[31:0]$3107 - attribute \src "issuer_ls180.v:48392.14-48392.41" - wire width 32 $1\alu_cr0_cr_op__insn[31:0] - attribute \src "issuer_ls180.v:49065.3-49076.6" - wire width 7 $1\alu_cr0_cr_op__insn_type$next[6:0]$3108 - attribute \src "issuer_ls180.v:48470.13-48470.45" - wire width 7 $1\alu_cr0_cr_op__insn_type[6:0] - attribute \src "issuer_ls180.v:48494.7-48494.26" - wire $1\alu_done_dly[0:0] - attribute \src "issuer_ls180.v:49212.3-49220.6" - wire $1\alu_l_r_alu$next[0:0]$3156 - attribute \src "issuer_ls180.v:48502.7-48502.25" - wire $1\alu_l_r_alu[0:0] - attribute \src "issuer_ls180.v:49203.3-49211.6" - wire $1\alui_l_r_alui$next[0:0]$3153 - attribute \src "issuer_ls180.v:48514.7-48514.27" - wire $1\alui_l_r_alui[0:0] - attribute \src "issuer_ls180.v:49077.3-49098.6" - wire width 64 $1\data_r0__o$next[63:0]$3112 - attribute \src "issuer_ls180.v:48548.14-48548.47" - wire width 64 $1\data_r0__o[63:0] - attribute \src "issuer_ls180.v:49077.3-49098.6" - wire $1\data_r0__o_ok$next[0:0]$3113 - attribute \src "issuer_ls180.v:48552.7-48552.27" - wire $1\data_r0__o_ok[0:0] - attribute \src "issuer_ls180.v:49099.3-49120.6" - wire width 32 $1\data_r1__full_cr$next[31:0]$3120 - attribute \src "issuer_ls180.v:48556.14-48556.38" - wire width 32 $1\data_r1__full_cr[31:0] - attribute \src "issuer_ls180.v:49099.3-49120.6" - wire $1\data_r1__full_cr_ok$next[0:0]$3121 - attribute \src "issuer_ls180.v:48560.7-48560.33" - wire $1\data_r1__full_cr_ok[0:0] - attribute \src "issuer_ls180.v:49121.3-49142.6" - wire width 4 $1\data_r2__cr_a$next[3:0]$3128 - attribute \src "issuer_ls180.v:48564.13-48564.33" - wire width 4 $1\data_r2__cr_a[3:0] - attribute \src "issuer_ls180.v:49121.3-49142.6" - wire $1\data_r2__cr_a_ok$next[0:0]$3129 - attribute \src "issuer_ls180.v:48568.7-48568.30" - wire $1\data_r2__cr_a_ok[0:0] - attribute \src "issuer_ls180.v:49221.3-49230.6" - wire width 64 $1\dest1_o[63:0] - attribute \src "issuer_ls180.v:49231.3-49240.6" - wire width 32 $1\dest2_o[31:0] - attribute \src "issuer_ls180.v:49241.3-49250.6" - wire width 4 $1\dest3_o[3:0] - attribute \src "issuer_ls180.v:49020.3-49028.6" - wire $1\opc_l_r_opc$next[0:0]$3089 - attribute \src "issuer_ls180.v:48587.7-48587.25" - wire $1\opc_l_r_opc[0:0] - attribute \src "issuer_ls180.v:49011.3-49019.6" - wire $1\opc_l_s_opc$next[0:0]$3086 - attribute \src "issuer_ls180.v:48591.7-48591.25" - wire $1\opc_l_s_opc[0:0] - attribute \src "issuer_ls180.v:49251.3-49259.6" - wire width 3 $1\prev_wr_go$next[2:0]$3162 - attribute \src "issuer_ls180.v:48688.13-48688.30" - wire width 3 $1\prev_wr_go[2:0] - attribute \src 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parameter \Y_WIDTH 1 - connect \A \$53 - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:48810$3017_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$issuer_ls180.v:48815$3022 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_cr0_n_valid_o - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:48815$3022_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$issuer_ls180.v:48816$3023 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $and$issuer_ls180.v:48816$3023_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$issuer_ls180.v:48819$3026 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o_ok - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:48819$3026_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$issuer_ls180.v:48820$3027 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \full_cr_ok - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:48820$3027_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$issuer_ls180.v:48821$3028 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cr_a_ok - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:48821$3028_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$issuer_ls180.v:48829$3036 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_cr0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $and$issuer_ls180.v:48829$3036_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$issuer_ls180.v:48830$3037 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_cr0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $and$issuer_ls180.v:48830$3037_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$issuer_ls180.v:48831$3038 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$issuer_ls180.v:48831$3038_Y - end - attribute \src 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1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:48796$3003_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$issuer_ls180.v:48802$3009 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_cr0_n_ready_i - connect \Y $not$issuer_ls180.v:48802$3009_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$issuer_ls180.v:48817$3024 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_rd__rel_o - connect \Y $not$issuer_ls180.v:48817$3024_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$issuer_ls180.v:48833$3040 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_rdmaskn_i - connect \Y $not$issuer_ls180.v:48833$3040_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$issuer_ls180.v:48813$3020 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$issuer_ls180.v:48813$3020_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$issuer_ls180.v:48814$3021 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$issuer_ls180.v:48814$3021_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$issuer_ls180.v:48818$3025 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $or$issuer_ls180.v:48818$3025_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$issuer_ls180.v:48828$3035 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \$6 - connect \B \cu_rd__go_i - connect \Y $or$issuer_ls180.v:48828$3035_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$issuer_ls180.v:48777$2984 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $reduce_and$issuer_ls180.v:48777$2984_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$issuer_ls180.v:48795$3002 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \$27 - connect \Y $reduce_or$issuer_ls180.v:48795$3002_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$issuer_ls180.v:48798$3005 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $reduce_or$issuer_ls180.v:48798$3005_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$issuer_ls180.v:48799$3006 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $reduce_or$issuer_ls180.v:48799$3006_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:48822$3029 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src1_i - connect \S \src_l_q_src [0] - connect \Y $ternary$issuer_ls180.v:48822$3029_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:48823$3030 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src2_i - connect \S \src_l_q_src [1] - connect \Y $ternary$issuer_ls180.v:48823$3030_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:48824$3031 - parameter \WIDTH 32 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $ternary$issuer_ls180.v:48824$3031_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:48825$3032 - parameter \WIDTH 4 - connect \A \src_r3 - connect \B \src4_i - connect \S \src_l_q_src [3] - connect \Y $ternary$issuer_ls180.v:48825$3032_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:48826$3033 - parameter \WIDTH 4 - connect \A \src_r4 - connect \B \src5_i - connect \S \src_l_q_src [4] - connect \Y $ternary$issuer_ls180.v:48826$3033_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:48827$3034 - parameter \WIDTH 4 - connect \A \src_r5 - connect \B \src6_i - connect \S \src_l_q_src [5] - connect \Y $ternary$issuer_ls180.v:48827$3034_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:48894.11-48916.4" - cell \alu_cr0 \alu_cr0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \alu_cr0_cr_a - connect \cr_a$2 \alu_cr0_cr_a$2 - connect \cr_a_ok \cr_a_ok - connect \cr_b \alu_cr0_cr_b - connect \cr_c \alu_cr0_cr_c - connect \cr_op__fn_unit \alu_cr0_cr_op__fn_unit - connect \cr_op__insn \alu_cr0_cr_op__insn - connect \cr_op__insn_type \alu_cr0_cr_op__insn_type - connect \full_cr \alu_cr0_full_cr - connect \full_cr$1 \alu_cr0_full_cr$1 - connect \full_cr_ok \full_cr_ok - connect \n_ready_i \alu_cr0_n_ready_i - connect \n_valid_o \alu_cr0_n_valid_o - connect \o \alu_cr0_o - connect \o_ok \o_ok - connect \p_ready_o \alu_cr0_p_ready_o - connect \p_valid_i \alu_cr0_p_valid_i - connect \ra \alu_cr0_ra - connect \rb \alu_cr0_rb - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:48917.14-48923.4" - cell \alu_l$16 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:48924.15-48930.4" - cell \alui_l$15 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:48931.14-48937.4" - cell \opc_l$11 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_opc \opc_l_q_opc - connect \r_opc \opc_l_r_opc - connect \s_opc \opc_l_s_opc - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:48938.14-48944.4" - cell \req_l$12 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \r_req \req_l_r_req - connect \s_req \req_l_s_req - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:48945.14-48951.4" - cell \rok_l$14 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \r_rdok \rok_l_r_rdok - connect \s_rdok \rok_l_s_rdok - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:48952.14-48957.4" - cell \rst_l$13 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_rst \rst_l_r_rst - connect \s_rst \rst_l_s_rst - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:48958.14-48964.4" - cell \src_l$10 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_src \src_l_q_src - connect \r_src \src_l_r_src - connect \s_src \src_l_s_src - end - attribute \src "issuer_ls180.v:48241.7-48241.20" - process $proc$issuer_ls180.v:48241$3163 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:48359.7-48359.24" - process $proc$issuer_ls180.v:48359$3164 - assign { } { } - assign $1\all_rd_dly[0:0] 1'0 - sync always - sync init - update \all_rd_dly $1\all_rd_dly[0:0] - end - attribute \src "issuer_ls180.v:48388.14-48388.46" - process $proc$issuer_ls180.v:48388$3165 - assign { } { } - assign $1\alu_cr0_cr_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \alu_cr0_cr_op__fn_unit $1\alu_cr0_cr_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:48392.14-48392.41" - process $proc$issuer_ls180.v:48392$3166 - assign { } { } - assign $1\alu_cr0_cr_op__insn[31:0] 0 - sync always - sync init - update \alu_cr0_cr_op__insn $1\alu_cr0_cr_op__insn[31:0] - end - attribute \src "issuer_ls180.v:48470.13-48470.45" - process $proc$issuer_ls180.v:48470$3167 - assign { } { } - assign $1\alu_cr0_cr_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \alu_cr0_cr_op__insn_type $1\alu_cr0_cr_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:48494.7-48494.26" - process $proc$issuer_ls180.v:48494$3168 - assign { } { } - assign $1\alu_done_dly[0:0] 1'0 - sync always - sync init - update \alu_done_dly $1\alu_done_dly[0:0] - end - attribute \src "issuer_ls180.v:48502.7-48502.25" - process $proc$issuer_ls180.v:48502$3169 - assign { } { } - assign $1\alu_l_r_alu[0:0] 1'1 - sync always - sync init - update \alu_l_r_alu $1\alu_l_r_alu[0:0] - end - attribute \src "issuer_ls180.v:48514.7-48514.27" - process $proc$issuer_ls180.v:48514$3170 - assign { } { } - assign $1\alui_l_r_alui[0:0] 1'1 - sync always - sync init - update \alui_l_r_alui $1\alui_l_r_alui[0:0] - end - attribute \src "issuer_ls180.v:48548.14-48548.47" - process $proc$issuer_ls180.v:48548$3171 - assign { } { } - assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r0__o $1\data_r0__o[63:0] - end - attribute \src "issuer_ls180.v:48552.7-48552.27" - process $proc$issuer_ls180.v:48552$3172 - assign { } { } - assign $1\data_r0__o_ok[0:0] 1'0 - sync always - sync init - update \data_r0__o_ok $1\data_r0__o_ok[0:0] - end - attribute \src "issuer_ls180.v:48556.14-48556.38" - process $proc$issuer_ls180.v:48556$3173 - assign { } { } - assign $1\data_r1__full_cr[31:0] 0 - sync always - sync init - update \data_r1__full_cr $1\data_r1__full_cr[31:0] - end - attribute \src "issuer_ls180.v:48560.7-48560.33" - process $proc$issuer_ls180.v:48560$3174 - assign { } { } - assign $1\data_r1__full_cr_ok[0:0] 1'0 - sync always - sync init - update \data_r1__full_cr_ok $1\data_r1__full_cr_ok[0:0] - end - attribute \src "issuer_ls180.v:48564.13-48564.33" - process $proc$issuer_ls180.v:48564$3175 - assign { } { } - assign $1\data_r2__cr_a[3:0] 4'0000 - sync always - sync init - update \data_r2__cr_a $1\data_r2__cr_a[3:0] - end - attribute \src "issuer_ls180.v:48568.7-48568.30" - process $proc$issuer_ls180.v:48568$3176 - assign { } { } - assign $1\data_r2__cr_a_ok[0:0] 1'0 - sync always - sync init - update \data_r2__cr_a_ok $1\data_r2__cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:48587.7-48587.25" - process $proc$issuer_ls180.v:48587$3177 - assign { } { } - assign $1\opc_l_r_opc[0:0] 1'1 - sync always - sync init - update \opc_l_r_opc $1\opc_l_r_opc[0:0] - end - attribute \src "issuer_ls180.v:48591.7-48591.25" - process $proc$issuer_ls180.v:48591$3178 - assign { } { } - assign $1\opc_l_s_opc[0:0] 1'0 - sync always - sync init - update \opc_l_s_opc $1\opc_l_s_opc[0:0] - end - attribute \src "issuer_ls180.v:48688.13-48688.30" - process $proc$issuer_ls180.v:48688$3179 - assign { } { } - assign $1\prev_wr_go[2:0] 3'000 - sync always - sync init - update \prev_wr_go $1\prev_wr_go[2:0] - end - attribute \src "issuer_ls180.v:48696.13-48696.31" - process $proc$issuer_ls180.v:48696$3180 - assign { } { } - assign $1\req_l_r_req[2:0] 3'111 - sync always - sync init - update \req_l_r_req $1\req_l_r_req[2:0] - end - attribute \src "issuer_ls180.v:48700.13-48700.31" - process $proc$issuer_ls180.v:48700$3181 - assign { } { } - assign $1\req_l_s_req[2:0] 3'000 - sync always - sync init - update \req_l_s_req $1\req_l_s_req[2:0] - end - attribute \src "issuer_ls180.v:48712.7-48712.26" - process $proc$issuer_ls180.v:48712$3182 - assign { } { } - assign $1\rok_l_r_rdok[0:0] 1'1 - sync always - sync init - update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] - end - attribute \src "issuer_ls180.v:48716.7-48716.26" - process $proc$issuer_ls180.v:48716$3183 - assign { } { } - assign $1\rok_l_s_rdok[0:0] 1'0 - sync always - sync init - update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] - end - attribute \src "issuer_ls180.v:48720.7-48720.25" - process $proc$issuer_ls180.v:48720$3184 - assign { } { } - assign $1\rst_l_r_rst[0:0] 1'1 - sync always - sync init - update \rst_l_r_rst $1\rst_l_r_rst[0:0] - end - attribute \src "issuer_ls180.v:48724.7-48724.25" - process $proc$issuer_ls180.v:48724$3185 - assign { } { } - assign $1\rst_l_s_rst[0:0] 1'0 - sync always - sync init - update \rst_l_s_rst $1\rst_l_s_rst[0:0] - end - attribute \src "issuer_ls180.v:48744.13-48744.32" - process $proc$issuer_ls180.v:48744$3186 - assign { } { } - assign $1\src_l_r_src[5:0] 6'111111 - sync always - sync init - update \src_l_r_src $1\src_l_r_src[5:0] - end - attribute \src "issuer_ls180.v:48748.13-48748.32" - process $proc$issuer_ls180.v:48748$3187 - assign { } { } - assign $1\src_l_s_src[5:0] 6'000000 - sync always - sync init - update \src_l_s_src $1\src_l_s_src[5:0] - end - attribute \src "issuer_ls180.v:48752.14-48752.43" - process $proc$issuer_ls180.v:48752$3188 - assign { } { } - assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r0 $1\src_r0[63:0] - end - attribute \src "issuer_ls180.v:48756.14-48756.43" - process $proc$issuer_ls180.v:48756$3189 - assign { } { } - assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r1 $1\src_r1[63:0] - end - attribute \src "issuer_ls180.v:48760.14-48760.28" - process $proc$issuer_ls180.v:48760$3190 - assign { } { } - assign $1\src_r2[31:0] 0 - sync always - sync init - update \src_r2 $1\src_r2[31:0] - end - attribute \src "issuer_ls180.v:48764.13-48764.26" - process $proc$issuer_ls180.v:48764$3191 - assign { } { } - assign $1\src_r3[3:0] 4'0000 - sync always - sync init - update \src_r3 $1\src_r3[3:0] - end - attribute \src "issuer_ls180.v:48768.13-48768.26" - process $proc$issuer_ls180.v:48768$3192 - assign { } { } - assign $1\src_r4[3:0] 4'0000 - sync always - sync init - update \src_r4 $1\src_r4[3:0] - end - attribute \src "issuer_ls180.v:48772.13-48772.26" - process $proc$issuer_ls180.v:48772$3193 - assign { } { } - assign $1\src_r5[3:0] 4'0000 - sync always - sync init - update \src_r5 $1\src_r5[3:0] - end - attribute \src "issuer_ls180.v:48834.3-48835.37" - process $proc$issuer_ls180.v:48834$3041 - assign { } { } - assign $0\data_r0__o[63:0] \data_r0__o$next - sync posedge \coresync_clk - update \data_r0__o $0\data_r0__o[63:0] - end - attribute \src "issuer_ls180.v:48836.3-48837.43" - process $proc$issuer_ls180.v:48836$3042 - assign { } { } - assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next - sync posedge \coresync_clk - update \data_r0__o_ok $0\data_r0__o_ok[0:0] - end - attribute \src "issuer_ls180.v:48838.3-48839.65" - process $proc$issuer_ls180.v:48838$3043 - assign { } { } - assign $0\alu_cr0_cr_op__insn_type[6:0] \alu_cr0_cr_op__insn_type$next - sync posedge \coresync_clk - update \alu_cr0_cr_op__insn_type $0\alu_cr0_cr_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:48840.3-48841.61" - process $proc$issuer_ls180.v:48840$3044 - assign { } { } - assign $0\alu_cr0_cr_op__fn_unit[11:0] \alu_cr0_cr_op__fn_unit$next - sync posedge \coresync_clk - update \alu_cr0_cr_op__fn_unit $0\alu_cr0_cr_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:48842.3-48843.55" - process $proc$issuer_ls180.v:48842$3045 - assign { } { } - assign $0\alu_cr0_cr_op__insn[31:0] \alu_cr0_cr_op__insn$next - sync posedge \coresync_clk - update \alu_cr0_cr_op__insn $0\alu_cr0_cr_op__insn[31:0] - end - attribute \src "issuer_ls180.v:48844.3-48845.39" - process $proc$issuer_ls180.v:48844$3046 - assign { } { } - assign $0\req_l_r_req[2:0] \req_l_r_req$next - sync posedge \coresync_clk - update \req_l_r_req $0\req_l_r_req[2:0] - end - attribute \src "issuer_ls180.v:48846.3-48847.39" - process $proc$issuer_ls180.v:48846$3047 - assign { } { } - assign $0\req_l_s_req[2:0] \req_l_s_req$next - sync posedge \coresync_clk - update \req_l_s_req $0\req_l_s_req[2:0] - end - attribute \src "issuer_ls180.v:48848.3-48849.39" - process $proc$issuer_ls180.v:48848$3048 - assign { } { } - assign $0\src_l_r_src[5:0] \src_l_r_src$next - sync posedge \coresync_clk - update \src_l_r_src $0\src_l_r_src[5:0] - end - attribute \src "issuer_ls180.v:48850.3-48851.39" - process $proc$issuer_ls180.v:48850$3049 - assign { } { } - assign $0\src_l_s_src[5:0] \src_l_s_src$next - sync posedge \coresync_clk - update \src_l_s_src $0\src_l_s_src[5:0] - end - attribute \src "issuer_ls180.v:48852.3-48853.39" - process $proc$issuer_ls180.v:48852$3050 - assign { } { } - assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next - sync posedge \coresync_clk - update \opc_l_r_opc $0\opc_l_r_opc[0:0] - end - attribute \src "issuer_ls180.v:48854.3-48855.39" - process $proc$issuer_ls180.v:48854$3051 - assign { } { } - assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next - sync posedge \coresync_clk - update \opc_l_s_opc $0\opc_l_s_opc[0:0] - end - attribute \src "issuer_ls180.v:48856.3-48857.39" - process $proc$issuer_ls180.v:48856$3052 - assign { } { } - assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next - sync posedge \coresync_clk - update \rst_l_r_rst $0\rst_l_r_rst[0:0] - end - attribute \src "issuer_ls180.v:48858.3-48859.39" - process $proc$issuer_ls180.v:48858$3053 - assign { } { } - assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next - sync posedge \coresync_clk - update \rst_l_s_rst $0\rst_l_s_rst[0:0] - end - attribute \src "issuer_ls180.v:48860.3-48861.41" - process $proc$issuer_ls180.v:48860$3054 - assign { } { } - assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next - sync posedge \coresync_clk - update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] - end - attribute \src "issuer_ls180.v:48862.3-48863.41" - process $proc$issuer_ls180.v:48862$3055 - assign { } { } - assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next - sync posedge \coresync_clk - update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] - end - attribute \src "issuer_ls180.v:48864.3-48865.37" - process $proc$issuer_ls180.v:48864$3056 - assign { } { } - assign $0\prev_wr_go[2:0] \prev_wr_go$next - sync posedge \coresync_clk - update \prev_wr_go $0\prev_wr_go[2:0] - end - attribute \src "issuer_ls180.v:48866.3-48867.39" - process $proc$issuer_ls180.v:48866$3057 - assign { } { } - assign $0\alu_done_dly[0:0] \alu_cr0_n_valid_o - sync posedge \coresync_clk - update \alu_done_dly $0\alu_done_dly[0:0] - end - attribute \src "issuer_ls180.v:48868.3-48869.25" - process $proc$issuer_ls180.v:48868$3058 - assign { } { } - assign $0\all_rd_dly[0:0] \$11 - sync posedge \coresync_clk - update \all_rd_dly $0\all_rd_dly[0:0] - end - attribute \src "issuer_ls180.v:48870.3-48871.39" - process $proc$issuer_ls180.v:48870$3059 - assign { } { } - assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next - sync posedge \coresync_clk - update \alu_l_r_alu $0\alu_l_r_alu[0:0] - end - attribute \src "issuer_ls180.v:48872.3-48873.43" - process $proc$issuer_ls180.v:48872$3060 - assign { } { } - assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next - sync posedge \coresync_clk - update \alui_l_r_alui $0\alui_l_r_alui[0:0] - end - attribute \src "issuer_ls180.v:48874.3-48875.29" - process $proc$issuer_ls180.v:48874$3061 - assign { } { } - assign $0\src_r5[3:0] \src_r5$next - sync posedge \coresync_clk - update \src_r5 $0\src_r5[3:0] - end - attribute \src "issuer_ls180.v:48876.3-48877.29" - process $proc$issuer_ls180.v:48876$3062 - assign { } { } - assign $0\src_r4[3:0] \src_r4$next - sync posedge \coresync_clk - update \src_r4 $0\src_r4[3:0] - end - attribute \src "issuer_ls180.v:48878.3-48879.29" - process $proc$issuer_ls180.v:48878$3063 - assign { } { } - assign $0\src_r3[3:0] \src_r3$next - sync posedge \coresync_clk - update \src_r3 $0\src_r3[3:0] - end - attribute \src "issuer_ls180.v:48880.3-48881.29" - process $proc$issuer_ls180.v:48880$3064 - assign { } { } - assign $0\src_r2[31:0] \src_r2$next - sync posedge \coresync_clk - update \src_r2 $0\src_r2[31:0] - end - attribute \src "issuer_ls180.v:48882.3-48883.29" - process $proc$issuer_ls180.v:48882$3065 - assign { } { } - assign $0\src_r1[63:0] \src_r1$next - sync posedge \coresync_clk - update \src_r1 $0\src_r1[63:0] - end - attribute \src "issuer_ls180.v:48884.3-48885.29" - process $proc$issuer_ls180.v:48884$3066 - assign { } { } - assign $0\src_r0[63:0] \src_r0$next - sync posedge \coresync_clk - update \src_r0 $0\src_r0[63:0] - end - attribute \src "issuer_ls180.v:48886.3-48887.43" - process $proc$issuer_ls180.v:48886$3067 - assign { } { } - assign $0\data_r2__cr_a[3:0] \data_r2__cr_a$next - sync posedge \coresync_clk - update \data_r2__cr_a $0\data_r2__cr_a[3:0] - end - attribute \src "issuer_ls180.v:48888.3-48889.49" - process $proc$issuer_ls180.v:48888$3068 - assign { } { } - assign $0\data_r2__cr_a_ok[0:0] \data_r2__cr_a_ok$next - sync posedge \coresync_clk - update \data_r2__cr_a_ok $0\data_r2__cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:48890.3-48891.49" - process $proc$issuer_ls180.v:48890$3069 - assign { } { } - assign $0\data_r1__full_cr[31:0] \data_r1__full_cr$next - sync posedge \coresync_clk - update \data_r1__full_cr $0\data_r1__full_cr[31:0] - end - attribute \src "issuer_ls180.v:48892.3-48893.55" - process $proc$issuer_ls180.v:48892$3070 - assign { } { } - assign $0\data_r1__full_cr_ok[0:0] \data_r1__full_cr_ok$next - sync posedge \coresync_clk - update \data_r1__full_cr_ok $0\data_r1__full_cr_ok[0:0] - end - attribute \src "issuer_ls180.v:48965.3-48974.6" - process $proc$issuer_ls180.v:48965$3071 - assign { } { } - assign { } { } - assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "issuer_ls180.v:48966.5-48966.29" - switch \initial - attribute \src "issuer_ls180.v:48966.9-48966.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch \$55 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_done[0:0] 1'1 - case - assign $1\req_done[0:0] \$47 - end - sync always - update \req_done $0\req_done[0:0] - end - attribute \src "issuer_ls180.v:48975.3-48983.6" - process $proc$issuer_ls180.v:48975$3072 - assign { } { } - assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$3073 $1\rok_l_s_rdok$next[0:0]$3074 - attribute \src "issuer_ls180.v:48976.5-48976.29" - switch \initial - attribute \src "issuer_ls180.v:48976.9-48976.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$3074 1'0 - case - assign $1\rok_l_s_rdok$next[0:0]$3074 \cu_issue_i - end - sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$3073 - end - attribute \src "issuer_ls180.v:48984.3-48992.6" - process $proc$issuer_ls180.v:48984$3075 - assign { } { } - assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$3076 $1\rok_l_r_rdok$next[0:0]$3077 - attribute \src "issuer_ls180.v:48985.5-48985.29" - switch \initial - attribute \src "issuer_ls180.v:48985.9-48985.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$3077 1'1 - case - assign $1\rok_l_r_rdok$next[0:0]$3077 \$65 - end - sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$3076 - end - attribute \src "issuer_ls180.v:48993.3-49001.6" - process $proc$issuer_ls180.v:48993$3078 - assign { } { } - assign { } { } - assign $0\rst_l_s_rst$next[0:0]$3079 $1\rst_l_s_rst$next[0:0]$3080 - attribute \src "issuer_ls180.v:48994.5-48994.29" - switch \initial - attribute \src "issuer_ls180.v:48994.9-48994.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_s_rst$next[0:0]$3080 1'0 - case - assign $1\rst_l_s_rst$next[0:0]$3080 \all_rd - end - sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$3079 - end - attribute \src "issuer_ls180.v:49002.3-49010.6" - process $proc$issuer_ls180.v:49002$3081 - assign { } { } - assign { } { } - assign $0\rst_l_r_rst$next[0:0]$3082 $1\rst_l_r_rst$next[0:0]$3083 - attribute \src "issuer_ls180.v:49003.5-49003.29" - switch \initial - attribute \src "issuer_ls180.v:49003.9-49003.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_r_rst$next[0:0]$3083 1'1 - case - assign $1\rst_l_r_rst$next[0:0]$3083 \rst_r - end - sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$3082 - end - attribute \src "issuer_ls180.v:49011.3-49019.6" - process $proc$issuer_ls180.v:49011$3084 - assign { } { } - assign { } { } - assign $0\opc_l_s_opc$next[0:0]$3085 $1\opc_l_s_opc$next[0:0]$3086 - attribute \src "issuer_ls180.v:49012.5-49012.29" - switch \initial - attribute \src "issuer_ls180.v:49012.9-49012.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_s_opc$next[0:0]$3086 1'0 - case - assign $1\opc_l_s_opc$next[0:0]$3086 \cu_issue_i - end - sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$3085 - end - attribute \src "issuer_ls180.v:49020.3-49028.6" - process $proc$issuer_ls180.v:49020$3087 - assign { } { } - assign { } { } - assign $0\opc_l_r_opc$next[0:0]$3088 $1\opc_l_r_opc$next[0:0]$3089 - attribute \src "issuer_ls180.v:49021.5-49021.29" - switch \initial - attribute \src "issuer_ls180.v:49021.9-49021.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_r_opc$next[0:0]$3089 1'1 - case - assign $1\opc_l_r_opc$next[0:0]$3089 \req_done - end - sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$3088 - end - attribute \src "issuer_ls180.v:49029.3-49037.6" - process $proc$issuer_ls180.v:49029$3090 - assign { } { } - assign { } { } - assign $0\src_l_s_src$next[5:0]$3091 $1\src_l_s_src$next[5:0]$3092 - attribute \src "issuer_ls180.v:49030.5-49030.29" - switch \initial - attribute \src "issuer_ls180.v:49030.9-49030.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_s_src$next[5:0]$3092 6'000000 - case - assign $1\src_l_s_src$next[5:0]$3092 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } - end - sync always - update \src_l_s_src$next $0\src_l_s_src$next[5:0]$3091 - end - attribute \src "issuer_ls180.v:49038.3-49046.6" - process $proc$issuer_ls180.v:49038$3093 - assign { } { } - assign { } { } - assign $0\src_l_r_src$next[5:0]$3094 $1\src_l_r_src$next[5:0]$3095 - attribute \src "issuer_ls180.v:49039.5-49039.29" - switch \initial - attribute \src "issuer_ls180.v:49039.9-49039.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_r_src$next[5:0]$3095 6'111111 - case - assign $1\src_l_r_src$next[5:0]$3095 \reset_r - end - sync always - update \src_l_r_src$next $0\src_l_r_src$next[5:0]$3094 - end - attribute \src "issuer_ls180.v:49047.3-49055.6" - process $proc$issuer_ls180.v:49047$3096 - assign { } { } - assign { } { } - assign $0\req_l_s_req$next[2:0]$3097 $1\req_l_s_req$next[2:0]$3098 - attribute \src "issuer_ls180.v:49048.5-49048.29" - switch \initial - attribute \src "issuer_ls180.v:49048.9-49048.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_s_req$next[2:0]$3098 3'000 - case - assign $1\req_l_s_req$next[2:0]$3098 \$67 - end - sync always - update \req_l_s_req$next $0\req_l_s_req$next[2:0]$3097 - end - attribute \src "issuer_ls180.v:49056.3-49064.6" - process $proc$issuer_ls180.v:49056$3099 - assign { } { } - assign { } { } - assign $0\req_l_r_req$next[2:0]$3100 $1\req_l_r_req$next[2:0]$3101 - attribute \src "issuer_ls180.v:49057.5-49057.29" - switch \initial - attribute \src "issuer_ls180.v:49057.9-49057.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_r_req$next[2:0]$3101 3'111 - case - assign $1\req_l_r_req$next[2:0]$3101 \$69 - end - sync always - update \req_l_r_req$next $0\req_l_r_req$next[2:0]$3100 - end - attribute \src "issuer_ls180.v:49065.3-49076.6" - process $proc$issuer_ls180.v:49065$3102 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_cr0_cr_op__fn_unit$next[11:0]$3103 $1\alu_cr0_cr_op__fn_unit$next[11:0]$3106 - assign $0\alu_cr0_cr_op__insn$next[31:0]$3104 $1\alu_cr0_cr_op__insn$next[31:0]$3107 - assign $0\alu_cr0_cr_op__insn_type$next[6:0]$3105 $1\alu_cr0_cr_op__insn_type$next[6:0]$3108 - attribute \src "issuer_ls180.v:49066.5-49066.29" - switch \initial - attribute \src "issuer_ls180.v:49066.9-49066.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_cr0_cr_op__insn$next[31:0]$3107 $1\alu_cr0_cr_op__fn_unit$next[11:0]$3106 $1\alu_cr0_cr_op__insn_type$next[6:0]$3108 } { \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } - case - assign $1\alu_cr0_cr_op__fn_unit$next[11:0]$3106 \alu_cr0_cr_op__fn_unit - assign $1\alu_cr0_cr_op__insn$next[31:0]$3107 \alu_cr0_cr_op__insn - assign $1\alu_cr0_cr_op__insn_type$next[6:0]$3108 \alu_cr0_cr_op__insn_type - end - sync always - update \alu_cr0_cr_op__fn_unit$next $0\alu_cr0_cr_op__fn_unit$next[11:0]$3103 - update \alu_cr0_cr_op__insn$next $0\alu_cr0_cr_op__insn$next[31:0]$3104 - update \alu_cr0_cr_op__insn_type$next $0\alu_cr0_cr_op__insn_type$next[6:0]$3105 - end - attribute \src "issuer_ls180.v:49077.3-49098.6" - process $proc$issuer_ls180.v:49077$3109 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r0__o$next[63:0]$3110 $2\data_r0__o$next[63:0]$3114 - assign { } { } - assign $0\data_r0__o_ok$next[0:0]$3111 $3\data_r0__o_ok$next[0:0]$3116 - attribute \src "issuer_ls180.v:49078.5-49078.29" - switch \initial - attribute \src "issuer_ls180.v:49078.9-49078.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$3113 $1\data_r0__o$next[63:0]$3112 } { \o_ok \alu_cr0_o } - case - assign $1\data_r0__o$next[63:0]$3112 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$3113 \data_r0__o_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$3115 $2\data_r0__o$next[63:0]$3114 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r0__o$next[63:0]$3114 $1\data_r0__o$next[63:0]$3112 - assign $2\data_r0__o_ok$next[0:0]$3115 $1\data_r0__o_ok$next[0:0]$3113 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r0__o_ok$next[0:0]$3116 1'0 - case - assign $3\data_r0__o_ok$next[0:0]$3116 $2\data_r0__o_ok$next[0:0]$3115 - end - sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$3110 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$3111 - end - attribute \src "issuer_ls180.v:49099.3-49120.6" - process $proc$issuer_ls180.v:49099$3117 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r1__full_cr$next[31:0]$3118 $2\data_r1__full_cr$next[31:0]$3122 - assign { } { } - assign $0\data_r1__full_cr_ok$next[0:0]$3119 $3\data_r1__full_cr_ok$next[0:0]$3124 - attribute \src "issuer_ls180.v:49100.5-49100.29" - switch \initial - attribute \src "issuer_ls180.v:49100.9-49100.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r1__full_cr_ok$next[0:0]$3121 $1\data_r1__full_cr$next[31:0]$3120 } { \full_cr_ok \alu_cr0_full_cr } - case - assign $1\data_r1__full_cr$next[31:0]$3120 \data_r1__full_cr - assign $1\data_r1__full_cr_ok$next[0:0]$3121 \data_r1__full_cr_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r1__full_cr_ok$next[0:0]$3123 $2\data_r1__full_cr$next[31:0]$3122 } 33'000000000000000000000000000000000 - case - assign $2\data_r1__full_cr$next[31:0]$3122 $1\data_r1__full_cr$next[31:0]$3120 - assign $2\data_r1__full_cr_ok$next[0:0]$3123 $1\data_r1__full_cr_ok$next[0:0]$3121 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r1__full_cr_ok$next[0:0]$3124 1'0 - case - assign $3\data_r1__full_cr_ok$next[0:0]$3124 $2\data_r1__full_cr_ok$next[0:0]$3123 - end - sync always - update \data_r1__full_cr$next $0\data_r1__full_cr$next[31:0]$3118 - update \data_r1__full_cr_ok$next $0\data_r1__full_cr_ok$next[0:0]$3119 - end - attribute \src "issuer_ls180.v:49121.3-49142.6" - process $proc$issuer_ls180.v:49121$3125 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r2__cr_a$next[3:0]$3126 $2\data_r2__cr_a$next[3:0]$3130 - assign { } { } - assign $0\data_r2__cr_a_ok$next[0:0]$3127 $3\data_r2__cr_a_ok$next[0:0]$3132 - attribute \src "issuer_ls180.v:49122.5-49122.29" - switch \initial - attribute \src "issuer_ls180.v:49122.9-49122.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r2__cr_a_ok$next[0:0]$3129 $1\data_r2__cr_a$next[3:0]$3128 } { \cr_a_ok \alu_cr0_cr_a } - case - assign $1\data_r2__cr_a$next[3:0]$3128 \data_r2__cr_a - assign $1\data_r2__cr_a_ok$next[0:0]$3129 \data_r2__cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r2__cr_a_ok$next[0:0]$3131 $2\data_r2__cr_a$next[3:0]$3130 } 5'00000 - case - assign $2\data_r2__cr_a$next[3:0]$3130 $1\data_r2__cr_a$next[3:0]$3128 - assign $2\data_r2__cr_a_ok$next[0:0]$3131 $1\data_r2__cr_a_ok$next[0:0]$3129 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r2__cr_a_ok$next[0:0]$3132 1'0 - case - assign $3\data_r2__cr_a_ok$next[0:0]$3132 $2\data_r2__cr_a_ok$next[0:0]$3131 - end - sync always - update \data_r2__cr_a$next $0\data_r2__cr_a$next[3:0]$3126 - update \data_r2__cr_a_ok$next $0\data_r2__cr_a_ok$next[0:0]$3127 - end - attribute \src "issuer_ls180.v:49143.3-49152.6" - process $proc$issuer_ls180.v:49143$3133 - assign { } { } - assign { } { } - assign $0\src_r0$next[63:0]$3134 $1\src_r0$next[63:0]$3135 - attribute \src "issuer_ls180.v:49144.5-49144.29" - switch \initial - attribute \src "issuer_ls180.v:49144.9-49144.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r0$next[63:0]$3135 \src1_i - case - assign $1\src_r0$next[63:0]$3135 \src_r0 - end - sync always - update \src_r0$next $0\src_r0$next[63:0]$3134 - end - attribute \src "issuer_ls180.v:49153.3-49162.6" - process $proc$issuer_ls180.v:49153$3136 - assign { } { } - assign { } { } - assign $0\src_r1$next[63:0]$3137 $1\src_r1$next[63:0]$3138 - attribute \src "issuer_ls180.v:49154.5-49154.29" - switch \initial - attribute \src "issuer_ls180.v:49154.9-49154.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [1] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r1$next[63:0]$3138 \src2_i - case - assign $1\src_r1$next[63:0]$3138 \src_r1 - end - sync always - update \src_r1$next $0\src_r1$next[63:0]$3137 - end - attribute \src "issuer_ls180.v:49163.3-49172.6" - process $proc$issuer_ls180.v:49163$3139 - assign { } { } - assign { } { } - assign $0\src_r2$next[31:0]$3140 $1\src_r2$next[31:0]$3141 - attribute \src "issuer_ls180.v:49164.5-49164.29" - switch \initial - attribute \src "issuer_ls180.v:49164.9-49164.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r2$next[31:0]$3141 \src3_i - case - assign $1\src_r2$next[31:0]$3141 \src_r2 - end - sync always - update \src_r2$next $0\src_r2$next[31:0]$3140 - end - attribute \src "issuer_ls180.v:49173.3-49182.6" - process $proc$issuer_ls180.v:49173$3142 - assign { } { } - assign { } { } - assign $0\src_r3$next[3:0]$3143 $1\src_r3$next[3:0]$3144 - attribute \src "issuer_ls180.v:49174.5-49174.29" - switch \initial - attribute \src "issuer_ls180.v:49174.9-49174.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [3] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r3$next[3:0]$3144 \src4_i - case - assign $1\src_r3$next[3:0]$3144 \src_r3 - end - sync always - update \src_r3$next $0\src_r3$next[3:0]$3143 - end - attribute \src "issuer_ls180.v:49183.3-49192.6" - process $proc$issuer_ls180.v:49183$3145 - assign { } { } - assign { } { } - assign $0\src_r4$next[3:0]$3146 $1\src_r4$next[3:0]$3147 - attribute \src "issuer_ls180.v:49184.5-49184.29" - switch \initial - attribute \src "issuer_ls180.v:49184.9-49184.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [4] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r4$next[3:0]$3147 \src5_i - case - assign $1\src_r4$next[3:0]$3147 \src_r4 - end - sync always - update \src_r4$next $0\src_r4$next[3:0]$3146 - end - attribute \src "issuer_ls180.v:49193.3-49202.6" - process $proc$issuer_ls180.v:49193$3148 - assign { } { } - assign { } { } - assign $0\src_r5$next[3:0]$3149 $1\src_r5$next[3:0]$3150 - attribute \src "issuer_ls180.v:49194.5-49194.29" - switch \initial - attribute \src "issuer_ls180.v:49194.9-49194.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [5] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r5$next[3:0]$3150 \src6_i - case - assign $1\src_r5$next[3:0]$3150 \src_r5 - end - sync always - update \src_r5$next $0\src_r5$next[3:0]$3149 - end - attribute \src "issuer_ls180.v:49203.3-49211.6" - process $proc$issuer_ls180.v:49203$3151 - assign { } { } - assign { } { } - assign $0\alui_l_r_alui$next[0:0]$3152 $1\alui_l_r_alui$next[0:0]$3153 - attribute \src "issuer_ls180.v:49204.5-49204.29" - switch \initial - attribute \src "issuer_ls180.v:49204.9-49204.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alui_l_r_alui$next[0:0]$3153 1'1 - case - assign $1\alui_l_r_alui$next[0:0]$3153 \$89 - end - sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$3152 - end - attribute \src "issuer_ls180.v:49212.3-49220.6" - process $proc$issuer_ls180.v:49212$3154 - assign { } { } - assign { } { } - assign $0\alu_l_r_alu$next[0:0]$3155 $1\alu_l_r_alu$next[0:0]$3156 - attribute \src "issuer_ls180.v:49213.5-49213.29" - switch \initial - attribute \src "issuer_ls180.v:49213.9-49213.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alu_l_r_alu$next[0:0]$3156 1'1 - case - assign $1\alu_l_r_alu$next[0:0]$3156 \$91 - end - sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$3155 - end - attribute \src "issuer_ls180.v:49221.3-49230.6" - process $proc$issuer_ls180.v:49221$3157 - assign { } { } - assign { } { } - assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "issuer_ls180.v:49222.5-49222.29" - switch \initial - attribute \src "issuer_ls180.v:49222.9-49222.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest1_o[63:0] \data_r0__o - case - assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest1_o $0\dest1_o[63:0] - end - attribute \src "issuer_ls180.v:49231.3-49240.6" - process $proc$issuer_ls180.v:49231$3158 - assign { } { } - assign { } { } - assign $0\dest2_o[31:0] $1\dest2_o[31:0] - attribute \src "issuer_ls180.v:49232.5-49232.29" - switch \initial - attribute \src "issuer_ls180.v:49232.9-49232.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$113 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest2_o[31:0] \data_r1__full_cr - case - assign $1\dest2_o[31:0] 0 - end - sync always - update \dest2_o $0\dest2_o[31:0] - end - attribute \src "issuer_ls180.v:49241.3-49250.6" - process $proc$issuer_ls180.v:49241$3159 - assign { } { } - assign { } { } - assign $0\dest3_o[3:0] $1\dest3_o[3:0] - attribute \src "issuer_ls180.v:49242.5-49242.29" - switch \initial - attribute \src "issuer_ls180.v:49242.9-49242.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$115 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest3_o[3:0] \data_r2__cr_a - case - assign $1\dest3_o[3:0] 4'0000 - end - sync always - update \dest3_o $0\dest3_o[3:0] - end - attribute \src "issuer_ls180.v:49251.3-49259.6" - process $proc$issuer_ls180.v:49251$3160 - assign { } { } - assign { } { } - assign $0\prev_wr_go$next[2:0]$3161 $1\prev_wr_go$next[2:0]$3162 - attribute \src "issuer_ls180.v:49252.5-49252.29" - switch \initial - attribute \src "issuer_ls180.v:49252.9-49252.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\prev_wr_go$next[2:0]$3162 3'000 - case - assign $1\prev_wr_go$next[2:0]$3162 \$21 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[2:0]$3161 - end - connect \$5 $reduce_and$issuer_ls180.v:48777$2984_Y - connect \$99 $and$issuer_ls180.v:48778$2985_Y - connect \$101 $and$issuer_ls180.v:48779$2986_Y - connect \$103 $and$issuer_ls180.v:48780$2987_Y - connect \$105 $and$issuer_ls180.v:48781$2988_Y - connect \$107 $and$issuer_ls180.v:48782$2989_Y - connect \$109 $and$issuer_ls180.v:48783$2990_Y - connect \$111 $and$issuer_ls180.v:48784$2991_Y - connect \$113 $and$issuer_ls180.v:48785$2992_Y - connect \$115 $and$issuer_ls180.v:48786$2993_Y - connect \$11 $and$issuer_ls180.v:48787$2994_Y - connect \$13 $not$issuer_ls180.v:48788$2995_Y - connect \$15 $and$issuer_ls180.v:48789$2996_Y - connect \$17 $not$issuer_ls180.v:48790$2997_Y - connect \$19 $and$issuer_ls180.v:48791$2998_Y - connect \$21 $and$issuer_ls180.v:48792$2999_Y - connect \$25 $not$issuer_ls180.v:48793$3000_Y - connect \$27 $and$issuer_ls180.v:48794$3001_Y - connect \$24 $reduce_or$issuer_ls180.v:48795$3002_Y - connect \$23 $not$issuer_ls180.v:48796$3003_Y - connect \$31 $and$issuer_ls180.v:48797$3004_Y - connect \$33 $reduce_or$issuer_ls180.v:48798$3005_Y - connect \$35 $reduce_or$issuer_ls180.v:48799$3006_Y - connect \$37 $or$issuer_ls180.v:48800$3007_Y - connect \$3 $and$issuer_ls180.v:48801$3008_Y - connect \$39 $not$issuer_ls180.v:48802$3009_Y - connect \$41 $and$issuer_ls180.v:48803$3010_Y - connect \$43 $and$issuer_ls180.v:48804$3011_Y - connect \$45 $eq$issuer_ls180.v:48805$3012_Y - connect \$47 $and$issuer_ls180.v:48806$3013_Y - connect \$49 $eq$issuer_ls180.v:48807$3014_Y - connect \$51 $and$issuer_ls180.v:48808$3015_Y - connect \$53 $and$issuer_ls180.v:48809$3016_Y - connect \$55 $and$issuer_ls180.v:48810$3017_Y - connect \$57 $or$issuer_ls180.v:48811$3018_Y - connect \$59 $or$issuer_ls180.v:48812$3019_Y - connect \$61 $or$issuer_ls180.v:48813$3020_Y - connect \$63 $or$issuer_ls180.v:48814$3021_Y - connect \$65 $and$issuer_ls180.v:48815$3022_Y - connect \$67 $and$issuer_ls180.v:48816$3023_Y - connect \$6 $not$issuer_ls180.v:48817$3024_Y - connect \$69 $or$issuer_ls180.v:48818$3025_Y - connect \$71 $and$issuer_ls180.v:48819$3026_Y - connect \$73 $and$issuer_ls180.v:48820$3027_Y - connect \$75 $and$issuer_ls180.v:48821$3028_Y - connect \$77 $ternary$issuer_ls180.v:48822$3029_Y - connect \$79 $ternary$issuer_ls180.v:48823$3030_Y - connect \$81 $ternary$issuer_ls180.v:48824$3031_Y - connect \$83 $ternary$issuer_ls180.v:48825$3032_Y - connect \$85 $ternary$issuer_ls180.v:48826$3033_Y - connect \$87 $ternary$issuer_ls180.v:48827$3034_Y - connect \$8 $or$issuer_ls180.v:48828$3035_Y - connect \$89 $and$issuer_ls180.v:48829$3036_Y - connect \$91 $and$issuer_ls180.v:48830$3037_Y - connect \$93 $and$issuer_ls180.v:48831$3038_Y - connect \$95 $and$issuer_ls180.v:48832$3039_Y - connect \$97 $not$issuer_ls180.v:48833$3040_Y - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 - connect \cu_wr__rel_o \$109 - connect \cu_rd__rel_o \$99 - connect \cu_busy_o \opc_l_q_opc - connect \alu_l_s_alu \all_rd_pulse - connect \alu_cr0_n_ready_i \alu_l_q_alu - connect \alui_l_s_alui \all_rd_pulse - connect \alu_cr0_p_valid_i \alui_l_q_alui - connect \alu_cr0_cr_c \$87 - connect \alu_cr0_cr_b \$85 - connect \alu_cr0_cr_a$2 \$83 - connect \alu_cr0_full_cr$1 \$81 - connect \alu_cr0_rb \$79 - connect \alu_cr0_ra \$77 - connect \cu_wrmask_o { \$75 \$73 \$71 } - connect \reset_r \$63 - connect \reset_w \$61 - connect \rst_r \$59 - connect \reset \$57 - connect \wr_any \$37 - connect \cu_done_o \$31 - connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } - connect \alu_pulse \alu_done_rise - connect \alu_done_rise \$19 - connect \alu_done_dly$next \alu_done - connect \alu_done \alu_cr0_n_valid_o - connect \all_rd_pulse \all_rd_rise - connect \all_rd_rise \$15 - connect \all_rd_dly$next \all_rd - connect \all_rd \$11 -end -attribute \src "issuer_ls180.v:49295.1-49344.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.cyc_l" -attribute \generator "nMigen" -module \cyc_l - attribute \src "issuer_ls180.v:49296.7-49296.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:49332.3-49340.6" - wire $0\q_int$next[0:0]$3201 - attribute \src "issuer_ls180.v:49330.3-49331.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:49332.3-49340.6" - wire $1\q_int$next[0:0]$3202 - attribute \src "issuer_ls180.v:49314.7-49314.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:49327.17-49327.96" - wire $and$issuer_ls180.v:49327$3196_Y - attribute \src "issuer_ls180.v:49326.17-49326.92" - wire $not$issuer_ls180.v:49326$3195_Y - attribute \src "issuer_ls180.v:49329.17-49329.92" - wire $not$issuer_ls180.v:49329$3198_Y - attribute \src "issuer_ls180.v:49325.17-49325.98" - wire $or$issuer_ls180.v:49325$3194_Y - attribute \src "issuer_ls180.v:49328.17-49328.97" - wire $or$issuer_ls180.v:49328$3197_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:49296.7-49296.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:49327$3196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:49327$3196_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:49326$3195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_cyc - connect \Y $not$issuer_ls180.v:49326$3195_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:49329$3198 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_cyc - connect \Y $not$issuer_ls180.v:49329$3198_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:49325$3194 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_cyc - connect \B \q_int - connect \Y $or$issuer_ls180.v:49325$3194_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:49328$3197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_cyc - connect \Y $or$issuer_ls180.v:49328$3197_Y - end - attribute \src "issuer_ls180.v:49296.7-49296.20" - process $proc$issuer_ls180.v:49296$3203 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:49314.7-49314.19" - process $proc$issuer_ls180.v:49314$3204 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:49330.3-49331.27" - process $proc$issuer_ls180.v:49330$3199 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:49332.3-49340.6" - process $proc$issuer_ls180.v:49332$3200 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$3201 $1\q_int$next[0:0]$3202 - attribute \src "issuer_ls180.v:49333.5-49333.29" - switch \initial - attribute \src "issuer_ls180.v:49333.9-49333.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$3202 1'0 - case - assign $1\q_int$next[0:0]$3202 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$3201 - end - connect \$9 $or$issuer_ls180.v:49325$3194_Y - connect \$1 $not$issuer_ls180.v:49326$3195_Y - connect \$3 $and$issuer_ls180.v:49327$3196_Y - connect \$5 $or$issuer_ls180.v:49328$3197_Y - connect \$7 $not$issuer_ls180.v:49329$3198_Y - connect \qlq_cyc \$9 - connect \qn_cyc \$7 - connect \q_cyc \q_int -end -attribute \src "issuer_ls180.v:49348.1-50062.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dbg" -attribute \generator "nMigen" -module \dbg - attribute \src "issuer_ls180.v:49878.3-49887.6" - wire $0\d_cr_req[0:0] - attribute \src "issuer_ls180.v:49685.3-49694.6" - wire $0\d_gpr_req[0:0] - attribute \src "issuer_ls180.v:49888.3-49897.6" - wire $0\d_xer_req[0:0] - attribute \src "issuer_ls180.v:49667.3-49684.6" - wire $0\dmi_ack_o[0:0] - attribute \src "issuer_ls180.v:49898.3-49928.6" - wire width 64 $0\dmi_dout[63:0] - attribute \src "issuer_ls180.v:49869.3-49877.6" - wire $0\dmi_read_log_data$next[0:0]$3318 - attribute \src "issuer_ls180.v:49645.3-49646.51" - wire $0\dmi_read_log_data[0:0] - attribute \src "issuer_ls180.v:49860.3-49868.6" - wire $0\dmi_read_log_data_1$next[0:0]$3315 - attribute \src "issuer_ls180.v:49647.3-49648.55" - wire $0\dmi_read_log_data_1[0:0] - attribute \src "issuer_ls180.v:49695.3-49703.6" - wire $0\dmi_req_i_1$next[0:0]$3281 - attribute \src "issuer_ls180.v:49657.3-49658.39" - wire $0\dmi_req_i_1[0:0] - attribute \src "issuer_ls180.v:50019.3-50052.6" - wire $0\do_dmi_log_rd$next[0:0]$3345 - attribute \src "issuer_ls180.v:49659.3-49660.43" - wire $0\do_dmi_log_rd[0:0] - attribute \src "issuer_ls180.v:49989.3-50018.6" - wire $0\do_icreset$next[0:0]$3338 - attribute \src "issuer_ls180.v:49661.3-49662.37" - wire $0\do_icreset[0:0] - attribute \src "issuer_ls180.v:49959.3-49988.6" - wire $0\do_reset$next[0:0]$3331 - attribute \src "issuer_ls180.v:49663.3-49664.33" - wire $0\do_reset[0:0] - attribute \src "issuer_ls180.v:49929.3-49958.6" - wire $0\do_step$next[0:0]$3324 - attribute \src "issuer_ls180.v:49665.3-49666.31" - wire $0\do_step[0:0] - attribute \src "issuer_ls180.v:49798.3-49825.6" - wire width 7 $0\gspr_index$next[6:0]$3303 - attribute \src "issuer_ls180.v:49651.3-49652.37" - wire width 7 $0\gspr_index[6:0] - attribute \src "issuer_ls180.v:49349.7-49349.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:49826.3-49859.6" - wire width 32 $0\log_dmi_addr$next[31:0]$3309 - attribute \src "issuer_ls180.v:49649.3-49650.41" - wire width 32 $0\log_dmi_addr[31:0] - attribute \src "issuer_ls180.v:49754.3-49797.6" - wire $0\stopping$next[0:0]$3294 - attribute \src "issuer_ls180.v:49653.3-49654.33" - wire $0\stopping[0:0] - attribute \src "issuer_ls180.v:49704.3-49753.6" - wire $0\terminated$next[0:0]$3284 - attribute \src "issuer_ls180.v:49655.3-49656.37" - wire $0\terminated[0:0] - attribute \src "issuer_ls180.v:49878.3-49887.6" - wire $1\d_cr_req[0:0] - attribute \src "issuer_ls180.v:49685.3-49694.6" - wire $1\d_gpr_req[0:0] - attribute \src "issuer_ls180.v:49888.3-49897.6" - wire $1\d_xer_req[0:0] - attribute \src "issuer_ls180.v:49667.3-49684.6" - wire $1\dmi_ack_o[0:0] - attribute \src "issuer_ls180.v:49898.3-49928.6" - wire width 64 $1\dmi_dout[63:0] - attribute \src "issuer_ls180.v:49869.3-49877.6" - wire $1\dmi_read_log_data$next[0:0]$3319 - attribute \src "issuer_ls180.v:49522.7-49522.31" - wire $1\dmi_read_log_data[0:0] - attribute \src "issuer_ls180.v:49860.3-49868.6" - wire $1\dmi_read_log_data_1$next[0:0]$3316 - attribute \src "issuer_ls180.v:49526.7-49526.33" - wire $1\dmi_read_log_data_1[0:0] - attribute \src "issuer_ls180.v:49695.3-49703.6" - wire $1\dmi_req_i_1$next[0:0]$3282 - attribute \src "issuer_ls180.v:49532.7-49532.25" - wire $1\dmi_req_i_1[0:0] - attribute \src "issuer_ls180.v:50019.3-50052.6" - wire $1\do_dmi_log_rd$next[0:0]$3346 - attribute \src "issuer_ls180.v:49538.7-49538.27" - wire $1\do_dmi_log_rd[0:0] - attribute \src "issuer_ls180.v:49989.3-50018.6" - wire $1\do_icreset$next[0:0]$3339 - attribute \src "issuer_ls180.v:49542.7-49542.24" - wire $1\do_icreset[0:0] - attribute \src "issuer_ls180.v:49959.3-49988.6" - wire $1\do_reset$next[0:0]$3332 - attribute \src "issuer_ls180.v:49546.7-49546.22" - wire $1\do_reset[0:0] - attribute \src "issuer_ls180.v:49929.3-49958.6" - wire $1\do_step$next[0:0]$3325 - attribute \src "issuer_ls180.v:49550.7-49550.21" - wire $1\do_step[0:0] - attribute \src "issuer_ls180.v:49798.3-49825.6" - wire width 7 $1\gspr_index$next[6:0]$3304 - attribute \src "issuer_ls180.v:49554.13-49554.31" - wire width 7 $1\gspr_index[6:0] - attribute \src "issuer_ls180.v:49826.3-49859.6" - wire width 32 $1\log_dmi_addr$next[31:0]$3310 - attribute \src "issuer_ls180.v:49560.14-49560.34" - wire width 32 $1\log_dmi_addr[31:0] - attribute \src "issuer_ls180.v:49754.3-49797.6" - wire $1\stopping$next[0:0]$3295 - attribute \src "issuer_ls180.v:49572.7-49572.22" - wire $1\stopping[0:0] - attribute \src "issuer_ls180.v:49704.3-49753.6" - wire $1\terminated$next[0:0]$3285 - attribute \src "issuer_ls180.v:49578.7-49578.24" - wire $1\terminated[0:0] - attribute \src "issuer_ls180.v:50019.3-50052.6" - wire $2\do_dmi_log_rd$next[0:0]$3347 - attribute \src "issuer_ls180.v:49989.3-50018.6" - wire $2\do_icreset$next[0:0]$3340 - attribute \src "issuer_ls180.v:49959.3-49988.6" - wire $2\do_reset$next[0:0]$3333 - attribute \src "issuer_ls180.v:49929.3-49958.6" - wire $2\do_step$next[0:0]$3326 - attribute \src "issuer_ls180.v:49798.3-49825.6" - wire width 7 $2\gspr_index$next[6:0]$3305 - attribute \src "issuer_ls180.v:49826.3-49859.6" - wire width 32 $2\log_dmi_addr$next[31:0]$3311 - attribute \src "issuer_ls180.v:49754.3-49797.6" - wire $2\stopping$next[0:0]$3296 - attribute \src "issuer_ls180.v:49704.3-49753.6" - wire $2\terminated$next[0:0]$3286 - attribute \src "issuer_ls180.v:50019.3-50052.6" - wire $3\do_dmi_log_rd$next[0:0]$3348 - attribute \src "issuer_ls180.v:49989.3-50018.6" - wire $3\do_icreset$next[0:0]$3341 - attribute \src "issuer_ls180.v:49959.3-49988.6" - wire $3\do_reset$next[0:0]$3334 - attribute \src "issuer_ls180.v:49929.3-49958.6" - wire $3\do_step$next[0:0]$3327 - attribute \src "issuer_ls180.v:49798.3-49825.6" - wire width 7 $3\gspr_index$next[6:0]$3306 - attribute \src "issuer_ls180.v:49826.3-49859.6" - wire width 32 $3\log_dmi_addr$next[31:0]$3312 - attribute \src "issuer_ls180.v:49754.3-49797.6" - wire $3\stopping$next[0:0]$3297 - attribute \src "issuer_ls180.v:49704.3-49753.6" - wire $3\terminated$next[0:0]$3287 - attribute \src "issuer_ls180.v:50019.3-50052.6" - wire $4\do_dmi_log_rd$next[0:0]$3349 - attribute \src "issuer_ls180.v:49989.3-50018.6" - wire $4\do_icreset$next[0:0]$3342 - attribute \src "issuer_ls180.v:49959.3-49988.6" - wire $4\do_reset$next[0:0]$3335 - attribute \src "issuer_ls180.v:49929.3-49958.6" - wire $4\do_step$next[0:0]$3328 - attribute \src "issuer_ls180.v:49798.3-49825.6" - wire width 7 $4\gspr_index$next[6:0]$3307 - attribute \src "issuer_ls180.v:49826.3-49859.6" - wire width 32 $4\log_dmi_addr$next[31:0]$3313 - attribute \src "issuer_ls180.v:49754.3-49797.6" - wire $4\stopping$next[0:0]$3298 - attribute \src "issuer_ls180.v:49704.3-49753.6" - wire $4\terminated$next[0:0]$3288 - attribute \src "issuer_ls180.v:49989.3-50018.6" - wire $5\do_icreset$next[0:0]$3343 - attribute \src "issuer_ls180.v:49959.3-49988.6" - wire $5\do_reset$next[0:0]$3336 - attribute \src "issuer_ls180.v:49929.3-49958.6" - wire $5\do_step$next[0:0]$3329 - attribute \src "issuer_ls180.v:49754.3-49797.6" - wire $5\stopping$next[0:0]$3299 - attribute \src "issuer_ls180.v:49704.3-49753.6" - wire $5\terminated$next[0:0]$3289 - attribute \src "issuer_ls180.v:49754.3-49797.6" - wire $6\stopping$next[0:0]$3300 - attribute \src "issuer_ls180.v:49704.3-49753.6" - wire $6\terminated$next[0:0]$3290 - attribute \src "issuer_ls180.v:49754.3-49797.6" - wire $7\stopping$next[0:0]$3301 - attribute \src "issuer_ls180.v:49704.3-49753.6" - wire $7\terminated$next[0:0]$3291 - attribute \src "issuer_ls180.v:49704.3-49753.6" - wire $8\terminated$next[0:0]$3292 - attribute \src "issuer_ls180.v:49592.19-49592.110" - wire width 3 $add$issuer_ls180.v:49592$3214_Y - attribute \src "issuer_ls180.v:49583.17-49583.109" - wire $and$issuer_ls180.v:49583$3205_Y - attribute \src "issuer_ls180.v:49586.19-49586.103" - wire $and$issuer_ls180.v:49586$3208_Y - attribute \src "issuer_ls180.v:49588.19-49588.113" - wire $and$issuer_ls180.v:49588$3210_Y - attribute \src "issuer_ls180.v:49595.19-49595.103" - wire $and$issuer_ls180.v:49595$3217_Y - attribute \src "issuer_ls180.v:49597.19-49597.102" - wire $and$issuer_ls180.v:49597$3219_Y - attribute \src "issuer_ls180.v:49602.18-49602.101" - wire $and$issuer_ls180.v:49602$3224_Y - attribute \src "issuer_ls180.v:49604.18-49604.111" - wire $and$issuer_ls180.v:49604$3226_Y - attribute \src "issuer_ls180.v:49609.18-49609.101" - wire $and$issuer_ls180.v:49609$3231_Y - attribute \src "issuer_ls180.v:49611.18-49611.111" - wire $and$issuer_ls180.v:49611$3233_Y - attribute \src "issuer_ls180.v:49617.18-49617.101" - wire $and$issuer_ls180.v:49617$3239_Y - attribute \src "issuer_ls180.v:49619.18-49619.111" - wire $and$issuer_ls180.v:49619$3241_Y - attribute \src "issuer_ls180.v:49623.17-49623.99" - wire $and$issuer_ls180.v:49623$3245_Y - attribute \src "issuer_ls180.v:49625.18-49625.101" - wire $and$issuer_ls180.v:49625$3247_Y - attribute \src "issuer_ls180.v:49627.18-49627.111" - wire $and$issuer_ls180.v:49627$3249_Y - attribute \src "issuer_ls180.v:49632.18-49632.101" - wire $and$issuer_ls180.v:49632$3254_Y - attribute \src "issuer_ls180.v:49635.18-49635.111" - wire $and$issuer_ls180.v:49635$3257_Y - attribute \src "issuer_ls180.v:49640.18-49640.101" - wire $and$issuer_ls180.v:49640$3262_Y - attribute \src "issuer_ls180.v:49642.18-49642.111" - wire $and$issuer_ls180.v:49642$3264_Y - attribute \src "issuer_ls180.v:49584.18-49584.103" - wire $eq$issuer_ls180.v:49584$3206_Y - attribute \src "issuer_ls180.v:49589.19-49589.104" - wire $eq$issuer_ls180.v:49589$3211_Y - attribute \src "issuer_ls180.v:49590.19-49590.104" - wire $eq$issuer_ls180.v:49590$3212_Y - attribute \src "issuer_ls180.v:49591.19-49591.104" - wire $eq$issuer_ls180.v:49591$3213_Y - attribute \src "issuer_ls180.v:49593.19-49593.104" - wire $eq$issuer_ls180.v:49593$3215_Y - attribute \src "issuer_ls180.v:49594.18-49594.103" - wire $eq$issuer_ls180.v:49594$3216_Y - attribute \src "issuer_ls180.v:49598.18-49598.103" - wire $eq$issuer_ls180.v:49598$3220_Y - attribute \src "issuer_ls180.v:49599.18-49599.103" - wire $eq$issuer_ls180.v:49599$3221_Y - attribute \src "issuer_ls180.v:49605.18-49605.103" - wire $eq$issuer_ls180.v:49605$3227_Y - attribute \src "issuer_ls180.v:49606.18-49606.103" - wire $eq$issuer_ls180.v:49606$3228_Y - attribute \src "issuer_ls180.v:49607.18-49607.103" - wire $eq$issuer_ls180.v:49607$3229_Y - attribute \src "issuer_ls180.v:49613.18-49613.103" - wire $eq$issuer_ls180.v:49613$3235_Y - attribute \src "issuer_ls180.v:49614.18-49614.103" - wire $eq$issuer_ls180.v:49614$3236_Y - attribute \src "issuer_ls180.v:49615.18-49615.103" - wire $eq$issuer_ls180.v:49615$3237_Y - attribute \src "issuer_ls180.v:49620.18-49620.103" - wire $eq$issuer_ls180.v:49620$3242_Y - attribute \src "issuer_ls180.v:49621.18-49621.103" - wire $eq$issuer_ls180.v:49621$3243_Y - attribute \src "issuer_ls180.v:49622.18-49622.103" - wire $eq$issuer_ls180.v:49622$3244_Y - attribute \src "issuer_ls180.v:49628.18-49628.103" - wire $eq$issuer_ls180.v:49628$3250_Y - attribute \src "issuer_ls180.v:49629.18-49629.103" - wire $eq$issuer_ls180.v:49629$3251_Y - attribute \src "issuer_ls180.v:49630.18-49630.103" - wire $eq$issuer_ls180.v:49630$3252_Y - attribute \src "issuer_ls180.v:49636.18-49636.103" - wire $eq$issuer_ls180.v:49636$3258_Y - attribute \src "issuer_ls180.v:49637.18-49637.103" - wire $eq$issuer_ls180.v:49637$3259_Y - attribute \src "issuer_ls180.v:49638.18-49638.103" - wire $eq$issuer_ls180.v:49638$3260_Y - attribute \src "issuer_ls180.v:49643.18-49643.103" - wire $eq$issuer_ls180.v:49643$3265_Y - attribute \src "issuer_ls180.v:49644.18-49644.103" - wire $eq$issuer_ls180.v:49644$3266_Y - attribute \src "issuer_ls180.v:49585.19-49585.99" - wire $not$issuer_ls180.v:49585$3207_Y - attribute \src "issuer_ls180.v:49587.19-49587.105" - wire $not$issuer_ls180.v:49587$3209_Y - attribute \src "issuer_ls180.v:49596.19-49596.95" - wire $not$issuer_ls180.v:49596$3218_Y - attribute \src "issuer_ls180.v:49600.18-49600.98" - wire $not$issuer_ls180.v:49600$3222_Y - attribute \src "issuer_ls180.v:49603.18-49603.104" - wire $not$issuer_ls180.v:49603$3225_Y - attribute \src "issuer_ls180.v:49608.18-49608.98" - wire $not$issuer_ls180.v:49608$3230_Y - attribute \src "issuer_ls180.v:49610.18-49610.104" - wire $not$issuer_ls180.v:49610$3232_Y - attribute \src "issuer_ls180.v:49612.17-49612.97" - wire $not$issuer_ls180.v:49612$3234_Y - attribute \src "issuer_ls180.v:49616.18-49616.98" - wire $not$issuer_ls180.v:49616$3238_Y - attribute \src "issuer_ls180.v:49618.18-49618.104" - wire $not$issuer_ls180.v:49618$3240_Y - attribute \src "issuer_ls180.v:49624.18-49624.98" - wire $not$issuer_ls180.v:49624$3246_Y - attribute \src "issuer_ls180.v:49626.18-49626.104" - wire $not$issuer_ls180.v:49626$3248_Y - attribute \src "issuer_ls180.v:49631.18-49631.98" - wire $not$issuer_ls180.v:49631$3253_Y - attribute \src "issuer_ls180.v:49633.18-49633.104" - wire $not$issuer_ls180.v:49633$3255_Y - attribute \src "issuer_ls180.v:49634.17-49634.103" - wire $not$issuer_ls180.v:49634$3256_Y - attribute \src "issuer_ls180.v:49639.18-49639.98" - wire $not$issuer_ls180.v:49639$3261_Y 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"/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:229" - wire width 3 \$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:229" - wire width 3 \$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:246" - wire \$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:246" - wire \$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire \$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - wire \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - wire \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - wire \$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire \$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire \$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - wire \$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - wire \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - wire \$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - wire \$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - wire \$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - wire \$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire \$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire \$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - wire \$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - wire \$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - wire \$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire \$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire \$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire \$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - wire \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - wire \$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - wire \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:140" - wire input 24 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 input 4 \core_dbg_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 input 3 \core_dbg_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:90" - wire output 1 \core_rst_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:89" - wire output 5 \core_stop_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:95" - wire input 6 \core_stopped_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:69" - wire input 13 \d_cr_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:71" - wire width 64 input 12 \d_cr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:68" - wire output 11 \d_cr_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:69" - wire input 10 \d_gpr_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:70" - wire width 7 output 8 \d_gpr_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:71" - wire width 64 input 9 \d_gpr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:68" - wire output 7 \d_gpr_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:69" - wire input 16 \d_xer_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:71" - wire width 64 input 15 \d_xer_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:68" - wire output 14 \d_xer_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" - wire output 19 \dmi_ack_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - wire width 4 input 18 \dmi_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" - wire width 64 input 23 \dmi_din - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" - wire width 64 output 21 \dmi_dout - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" - wire \dmi_read_log_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" - wire \dmi_read_log_data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" - wire \dmi_read_log_data_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" - wire \dmi_read_log_data_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" - wire input 20 \dmi_req_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123" - wire \dmi_req_i_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123" - wire \dmi_req_i_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" - wire input 22 \dmi_we_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" - wire \do_dmi_log_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" - wire \do_dmi_log_rd$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" - wire \do_icreset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" - wire \do_icreset$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" - wire \do_reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" - wire \do_reset$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:130" - wire \do_step - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:130" - wire \do_step$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" - wire width 7 \gspr_index - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" - wire width 7 \gspr_index$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:91" - wire \icache_rst_o - attribute \src "issuer_ls180.v:49349.7-49349.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" - wire width 32 \log_dmi_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" - wire width 32 \log_dmi_addr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" - wire width 64 \log_dmi_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:111" - wire width 32 \log_write_addr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:140" - wire input 17 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:126" - wire width 64 \stat_reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:129" - wire \stopping - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:129" - wire \stopping$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:94" - wire input 2 \terminate_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:133" - wire \terminated - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:133" - wire \terminated$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:114" - wire \terminated_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:229" - cell $add $add$issuer_ls180.v:49592$3214 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \log_dmi_addr [1:0] - connect \B 1'1 - connect \Y $add$issuer_ls180.v:49592$3214_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $and $and$issuer_ls180.v:49583$3205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$7 - connect \Y $and$issuer_ls180.v:49583$3205_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $and $and$issuer_ls180.v:49586$3208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$101 - connect \Y $and$issuer_ls180.v:49586$3208_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $and $and$issuer_ls180.v:49588$3210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$105 - connect \Y $and$issuer_ls180.v:49588$3210_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$issuer_ls180.v:49595$3217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$118 - connect \Y $and$issuer_ls180.v:49595$3217_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:246" - cell $and $and$issuer_ls180.v:49597$3219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \stopping - connect \B \$122 - connect \Y $and$issuer_ls180.v:49597$3219_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $and $and$issuer_ls180.v:49602$3224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$17 - connect \Y $and$issuer_ls180.v:49602$3224_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $and $and$issuer_ls180.v:49604$3226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$21 - connect \Y $and$issuer_ls180.v:49604$3226_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $and $and$issuer_ls180.v:49609$3231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$31 - connect \Y $and$issuer_ls180.v:49609$3231_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $and $and$issuer_ls180.v:49611$3233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$35 - connect \Y $and$issuer_ls180.v:49611$3233_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $and $and$issuer_ls180.v:49617$3239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$45 - connect \Y $and$issuer_ls180.v:49617$3239_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $and $and$issuer_ls180.v:49619$3241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$49 - connect \Y $and$issuer_ls180.v:49619$3241_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $and $and$issuer_ls180.v:49623$3245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$3 - connect \Y $and$issuer_ls180.v:49623$3245_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $and $and$issuer_ls180.v:49625$3247 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$59 - connect \Y $and$issuer_ls180.v:49625$3247_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $and $and$issuer_ls180.v:49627$3249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$63 - connect \Y $and$issuer_ls180.v:49627$3249_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $and $and$issuer_ls180.v:49632$3254 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$73 - connect \Y $and$issuer_ls180.v:49632$3254_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $and $and$issuer_ls180.v:49635$3257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$77 - connect \Y $and$issuer_ls180.v:49635$3257_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $and $and$issuer_ls180.v:49640$3262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$87 - connect \Y $and$issuer_ls180.v:49640$3262_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $and $and$issuer_ls180.v:49642$3264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$91 - connect \Y $and$issuer_ls180.v:49642$3264_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - cell $eq $eq$issuer_ls180.v:49584$3206 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $eq$issuer_ls180.v:49584$3206_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - cell $eq $eq$issuer_ls180.v:49589$3211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $eq$issuer_ls180.v:49589$3211_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - cell $eq $eq$issuer_ls180.v:49590$3212 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$issuer_ls180.v:49590$3212_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - cell $eq $eq$issuer_ls180.v:49591$3213 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $eq$issuer_ls180.v:49591$3213_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $eq $eq$issuer_ls180.v:49593$3215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'111 - connect \Y $eq$issuer_ls180.v:49593$3215_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - cell $eq $eq$issuer_ls180.v:49594$3216 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $eq$issuer_ls180.v:49594$3216_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - cell $eq $eq$issuer_ls180.v:49598$3220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$issuer_ls180.v:49598$3220_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - cell $eq $eq$issuer_ls180.v:49599$3221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $eq$issuer_ls180.v:49599$3221_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - cell $eq $eq$issuer_ls180.v:49605$3227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $eq$issuer_ls180.v:49605$3227_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - cell $eq $eq$issuer_ls180.v:49606$3228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$issuer_ls180.v:49606$3228_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - cell $eq $eq$issuer_ls180.v:49607$3229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $eq$issuer_ls180.v:49607$3229_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - cell $eq $eq$issuer_ls180.v:49613$3235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $eq$issuer_ls180.v:49613$3235_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - cell $eq $eq$issuer_ls180.v:49614$3236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$issuer_ls180.v:49614$3236_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - cell $eq $eq$issuer_ls180.v:49615$3237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $eq$issuer_ls180.v:49615$3237_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - cell $eq $eq$issuer_ls180.v:49620$3242 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $eq$issuer_ls180.v:49620$3242_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - cell $eq $eq$issuer_ls180.v:49621$3243 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$issuer_ls180.v:49621$3243_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - cell $eq $eq$issuer_ls180.v:49622$3244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $eq$issuer_ls180.v:49622$3244_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - cell $eq $eq$issuer_ls180.v:49628$3250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $eq$issuer_ls180.v:49628$3250_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - cell $eq $eq$issuer_ls180.v:49629$3251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$issuer_ls180.v:49629$3251_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - cell $eq $eq$issuer_ls180.v:49630$3252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $eq$issuer_ls180.v:49630$3252_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - cell $eq $eq$issuer_ls180.v:49636$3258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $eq$issuer_ls180.v:49636$3258_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - cell $eq $eq$issuer_ls180.v:49637$3259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$issuer_ls180.v:49637$3259_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - cell $eq $eq$issuer_ls180.v:49638$3260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $eq$issuer_ls180.v:49638$3260_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - cell $eq $eq$issuer_ls180.v:49643$3265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $eq$issuer_ls180.v:49643$3265_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - cell $eq $eq$issuer_ls180.v:49644$3266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $eq$issuer_ls180.v:49644$3266_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $not $not$issuer_ls180.v:49585$3207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$issuer_ls180.v:49585$3207_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $not $not$issuer_ls180.v:49587$3209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$issuer_ls180.v:49587$3209_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:246" - cell $not $not$issuer_ls180.v:49596$3218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \do_step - connect \Y $not$issuer_ls180.v:49596$3218_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $not $not$issuer_ls180.v:49600$3222 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$issuer_ls180.v:49600$3222_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $not $not$issuer_ls180.v:49603$3225 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$issuer_ls180.v:49603$3225_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $not $not$issuer_ls180.v:49608$3230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$issuer_ls180.v:49608$3230_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $not $not$issuer_ls180.v:49610$3232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$issuer_ls180.v:49610$3232_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $not $not$issuer_ls180.v:49612$3234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$issuer_ls180.v:49612$3234_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $not $not$issuer_ls180.v:49616$3238 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$issuer_ls180.v:49616$3238_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $not $not$issuer_ls180.v:49618$3240 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$issuer_ls180.v:49618$3240_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $not $not$issuer_ls180.v:49624$3246 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$issuer_ls180.v:49624$3246_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $not $not$issuer_ls180.v:49626$3248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$issuer_ls180.v:49626$3248_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $not $not$issuer_ls180.v:49631$3253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$issuer_ls180.v:49631$3253_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $not $not$issuer_ls180.v:49633$3255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$issuer_ls180.v:49633$3255_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $not $not$issuer_ls180.v:49634$3256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$issuer_ls180.v:49634$3256_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $not $not$issuer_ls180.v:49639$3261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $not$issuer_ls180.v:49639$3261_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $not $not$issuer_ls180.v:49641$3263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $not$issuer_ls180.v:49641$3263_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:162" - cell $pos $pos$issuer_ls180.v:49601$3223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping } - connect \Y $pos$issuer_ls180.v:49601$3223_Y - end - attribute \src "issuer_ls180.v:49349.7-49349.20" - process $proc$issuer_ls180.v:49349$3350 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:49522.7-49522.31" - process $proc$issuer_ls180.v:49522$3351 - assign { } { } - assign $1\dmi_read_log_data[0:0] 1'0 - sync always - sync init - update \dmi_read_log_data $1\dmi_read_log_data[0:0] - end - attribute \src "issuer_ls180.v:49526.7-49526.33" - process $proc$issuer_ls180.v:49526$3352 - assign { } { } - assign $1\dmi_read_log_data_1[0:0] 1'0 - sync always - sync init - update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0] - end - attribute \src "issuer_ls180.v:49532.7-49532.25" - process $proc$issuer_ls180.v:49532$3353 - assign { } { } - assign $1\dmi_req_i_1[0:0] 1'0 - sync always - sync init - update \dmi_req_i_1 $1\dmi_req_i_1[0:0] - end - attribute \src "issuer_ls180.v:49538.7-49538.27" - process $proc$issuer_ls180.v:49538$3354 - assign { } { } - assign $1\do_dmi_log_rd[0:0] 1'0 - sync always - sync init - update \do_dmi_log_rd $1\do_dmi_log_rd[0:0] - end - attribute \src "issuer_ls180.v:49542.7-49542.24" - process $proc$issuer_ls180.v:49542$3355 - assign { } { } - assign $1\do_icreset[0:0] 1'0 - sync always - sync init - update \do_icreset $1\do_icreset[0:0] - end - attribute \src "issuer_ls180.v:49546.7-49546.22" - process $proc$issuer_ls180.v:49546$3356 - assign { } { } - assign $1\do_reset[0:0] 1'0 - sync always - sync init - update \do_reset $1\do_reset[0:0] - end - attribute \src "issuer_ls180.v:49550.7-49550.21" - process $proc$issuer_ls180.v:49550$3357 - assign { } { } - assign $1\do_step[0:0] 1'0 - sync always - sync init - update \do_step $1\do_step[0:0] - end - attribute \src "issuer_ls180.v:49554.13-49554.31" - process $proc$issuer_ls180.v:49554$3358 - assign { } { } - assign $1\gspr_index[6:0] 7'0000000 - sync always - sync init - update \gspr_index $1\gspr_index[6:0] - end - attribute \src "issuer_ls180.v:49560.14-49560.34" - process $proc$issuer_ls180.v:49560$3359 - assign { } { } - assign $1\log_dmi_addr[31:0] 0 - sync always - sync init - update \log_dmi_addr $1\log_dmi_addr[31:0] - end - attribute \src "issuer_ls180.v:49572.7-49572.22" - process $proc$issuer_ls180.v:49572$3360 - assign { } { } - assign $1\stopping[0:0] 1'0 - sync always - sync init - update \stopping $1\stopping[0:0] - end - attribute \src "issuer_ls180.v:49578.7-49578.24" - process $proc$issuer_ls180.v:49578$3361 - assign { } { } - assign $1\terminated[0:0] 1'0 - sync always - sync init - update \terminated $1\terminated[0:0] - end - attribute \src "issuer_ls180.v:49645.3-49646.51" - process $proc$issuer_ls180.v:49645$3267 - assign { } { } - assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next - sync posedge \clk - update \dmi_read_log_data $0\dmi_read_log_data[0:0] - end - attribute \src "issuer_ls180.v:49647.3-49648.55" - process $proc$issuer_ls180.v:49647$3268 - assign { } { } - assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next - sync posedge \clk - update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0] - end - attribute \src "issuer_ls180.v:49649.3-49650.41" - process $proc$issuer_ls180.v:49649$3269 - assign { } { } - assign $0\log_dmi_addr[31:0] \log_dmi_addr$next - sync posedge \clk - update \log_dmi_addr $0\log_dmi_addr[31:0] - end - attribute \src "issuer_ls180.v:49651.3-49652.37" - process $proc$issuer_ls180.v:49651$3270 - assign { } { } - assign $0\gspr_index[6:0] \gspr_index$next - sync posedge \clk - update \gspr_index $0\gspr_index[6:0] - end - attribute \src "issuer_ls180.v:49653.3-49654.33" - process $proc$issuer_ls180.v:49653$3271 - assign { } { } - assign $0\stopping[0:0] \stopping$next - sync posedge \clk - update \stopping $0\stopping[0:0] - end - attribute \src "issuer_ls180.v:49655.3-49656.37" - process $proc$issuer_ls180.v:49655$3272 - assign { } { } - assign $0\terminated[0:0] \terminated$next - sync posedge \clk - update \terminated $0\terminated[0:0] - end - attribute \src "issuer_ls180.v:49657.3-49658.39" - process $proc$issuer_ls180.v:49657$3273 - assign { } { } - assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next - sync posedge \clk - update \dmi_req_i_1 $0\dmi_req_i_1[0:0] - end - attribute \src "issuer_ls180.v:49659.3-49660.43" - process $proc$issuer_ls180.v:49659$3274 - assign { } { } - assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next - sync posedge \clk - update \do_dmi_log_rd $0\do_dmi_log_rd[0:0] - end - attribute \src "issuer_ls180.v:49661.3-49662.37" - process $proc$issuer_ls180.v:49661$3275 - assign { } { } - assign $0\do_icreset[0:0] \do_icreset$next - sync posedge \clk - update \do_icreset $0\do_icreset[0:0] - end - attribute \src "issuer_ls180.v:49663.3-49664.33" - process $proc$issuer_ls180.v:49663$3276 - assign { } { } - assign $0\do_reset[0:0] \do_reset$next - sync posedge \clk - update \do_reset $0\do_reset[0:0] - end - attribute \src "issuer_ls180.v:49665.3-49666.31" - process $proc$issuer_ls180.v:49665$3277 - assign { } { } - assign $0\do_step[0:0] \do_step$next - sync posedge \clk - update \do_step $0\do_step[0:0] - end - attribute \src "issuer_ls180.v:49667.3-49684.6" - process $proc$issuer_ls180.v:49667$3278 - assign { } { } - assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0] - attribute \src "issuer_ls180.v:49668.5-49668.29" - switch \initial - attribute \src "issuer_ls180.v:49668.9-49668.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" - switch \dmi_addr_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dmi_ack_o[0:0] \d_gpr_ack - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dmi_ack_o[0:0] \d_cr_ack - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dmi_ack_o[0:0] \d_xer_ack - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\dmi_ack_o[0:0] \dmi_req_i - end - sync always - update \dmi_ack_o $0\dmi_ack_o[0:0] - end - attribute \src "issuer_ls180.v:49685.3-49694.6" - process $proc$issuer_ls180.v:49685$3279 - assign { } { } - assign { } { } - assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0] - attribute \src "issuer_ls180.v:49686.5-49686.29" - switch \initial - attribute \src "issuer_ls180.v:49686.9-49686.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" - switch \dmi_addr_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\d_gpr_req[0:0] \dmi_req_i - case - assign $1\d_gpr_req[0:0] 1'0 - end - sync always - update \d_gpr_req $0\d_gpr_req[0:0] - end - attribute \src "issuer_ls180.v:49695.3-49703.6" - process $proc$issuer_ls180.v:49695$3280 - assign { } { } - assign { } { } - assign $0\dmi_req_i_1$next[0:0]$3281 $1\dmi_req_i_1$next[0:0]$3282 - attribute \src "issuer_ls180.v:49696.5-49696.29" - switch \initial - attribute \src "issuer_ls180.v:49696.9-49696.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi_req_i_1$next[0:0]$3282 1'0 - case - assign $1\dmi_req_i_1$next[0:0]$3282 \dmi_req_i - end - sync always - update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3281 - end - attribute \src "issuer_ls180.v:49704.3-49753.6" - process $proc$issuer_ls180.v:49704$3283 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\terminated$next[0:0]$3284 $8\terminated$next[0:0]$3292 - attribute \src "issuer_ls180.v:49705.5-49705.29" - switch \initial - attribute \src "issuer_ls180.v:49705.9-49705.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - switch { \$65 \$61 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\terminated$next[0:0]$3285 $2\terminated$next[0:0]$3286 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" - switch \dmi_we_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\terminated$next[0:0]$3286 $3\terminated$next[0:0]$3287 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - switch { \$71 \$69 \$67 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'--1 - assign { } { } - assign { } { } - assign { } { } - assign $3\terminated$next[0:0]$3287 $6\terminated$next[0:0]$3290 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch \dmi_din [1] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\terminated$next[0:0]$3288 1'0 - case - assign $4\terminated$next[0:0]$3288 \terminated - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:205" - switch \dmi_din [3] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\terminated$next[0:0]$3289 1'0 - case - assign $5\terminated$next[0:0]$3289 $4\terminated$next[0:0]$3288 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - switch \dmi_din [4] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\terminated$next[0:0]$3290 1'0 - case - assign $6\terminated$next[0:0]$3290 $5\terminated$next[0:0]$3289 - end - case - assign $3\terminated$next[0:0]$3287 \terminated - end - case - assign $2\terminated$next[0:0]$3286 \terminated - end - case - assign $1\terminated$next[0:0]$3285 \terminated - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:239" - switch \terminate_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\terminated$next[0:0]$3291 1'1 - case - assign $7\terminated$next[0:0]$3291 $1\terminated$next[0:0]$3285 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $8\terminated$next[0:0]$3292 1'0 - case - assign $8\terminated$next[0:0]$3292 $7\terminated$next[0:0]$3291 - end - sync always - update \terminated$next $0\terminated$next[0:0]$3284 - end - attribute \src "issuer_ls180.v:49754.3-49797.6" - process $proc$issuer_ls180.v:49754$3293 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\stopping$next[0:0]$3294 $7\stopping$next[0:0]$3301 - attribute \src "issuer_ls180.v:49755.5-49755.29" - switch \initial - attribute \src "issuer_ls180.v:49755.9-49755.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - switch { \$79 \$75 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\stopping$next[0:0]$3295 $2\stopping$next[0:0]$3296 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" - switch \dmi_we_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\stopping$next[0:0]$3296 $3\stopping$next[0:0]$3297 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - switch { \$85 \$83 \$81 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'--1 - assign { } { } - assign { } { } - assign $3\stopping$next[0:0]$3297 $5\stopping$next[0:0]$3299 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - switch \dmi_din [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\stopping$next[0:0]$3298 1'1 - case - assign $4\stopping$next[0:0]$3298 \stopping - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - switch \dmi_din [4] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\stopping$next[0:0]$3299 1'0 - case - assign $5\stopping$next[0:0]$3299 $4\stopping$next[0:0]$3298 - end - case - assign $3\stopping$next[0:0]$3297 \stopping - end - case - assign $2\stopping$next[0:0]$3296 \stopping - end - case - assign $1\stopping$next[0:0]$3295 \stopping - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:239" - switch \terminate_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\stopping$next[0:0]$3300 1'1 - case - assign $6\stopping$next[0:0]$3300 $1\stopping$next[0:0]$3295 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\stopping$next[0:0]$3301 1'0 - case - assign $7\stopping$next[0:0]$3301 $6\stopping$next[0:0]$3300 - end - sync always - update \stopping$next $0\stopping$next[0:0]$3294 - end - attribute \src "issuer_ls180.v:49798.3-49825.6" - process $proc$issuer_ls180.v:49798$3302 - assign { } { } - assign { } { } - assign { } { } - assign $0\gspr_index$next[6:0]$3303 $4\gspr_index$next[6:0]$3307 - attribute \src "issuer_ls180.v:49799.5-49799.29" - switch \initial - attribute \src "issuer_ls180.v:49799.9-49799.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - switch { \$93 \$89 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\gspr_index$next[6:0]$3304 $2\gspr_index$next[6:0]$3305 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" - switch \dmi_we_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\gspr_index$next[6:0]$3305 $3\gspr_index$next[6:0]$3306 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - switch { \$99 \$97 \$95 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'--1 - assign $3\gspr_index$next[6:0]$3306 \gspr_index - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $3\gspr_index$next[6:0]$3306 \dmi_din [6:0] - case - assign $3\gspr_index$next[6:0]$3306 \gspr_index - end - case - assign $2\gspr_index$next[6:0]$3305 \gspr_index - end - case - assign $1\gspr_index$next[6:0]$3304 \gspr_index - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\gspr_index$next[6:0]$3307 7'0000000 - case - assign $4\gspr_index$next[6:0]$3307 $1\gspr_index$next[6:0]$3304 - end - sync always - update \gspr_index$next $0\gspr_index$next[6:0]$3303 - end - attribute \src "issuer_ls180.v:49826.3-49859.6" - process $proc$issuer_ls180.v:49826$3308 - assign { } { } - assign { } { } - assign { } { } - assign $0\log_dmi_addr$next[31:0]$3309 $4\log_dmi_addr$next[31:0]$3313 - attribute \src "issuer_ls180.v:49827.5-49827.29" - switch \initial - attribute \src "issuer_ls180.v:49827.9-49827.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - switch { \$107 \$103 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\log_dmi_addr$next[31:0]$3310 $2\log_dmi_addr$next[31:0]$3311 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" - switch \dmi_we_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\log_dmi_addr$next[31:0]$3311 $3\log_dmi_addr$next[31:0]$3312 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - switch { \$113 \$111 \$109 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'--1 - assign $3\log_dmi_addr$next[31:0]$3312 \log_dmi_addr - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'-1- - assign $3\log_dmi_addr$next[31:0]$3312 \log_dmi_addr - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $3\log_dmi_addr$next[31:0]$3312 \dmi_din [31:0] - case - assign $3\log_dmi_addr$next[31:0]$3312 \log_dmi_addr - end - case - assign $2\log_dmi_addr$next[31:0]$3311 \log_dmi_addr - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign $1\log_dmi_addr$next[31:0]$3310 [31:2] \log_dmi_addr [31:2] - assign $1\log_dmi_addr$next[31:0]$3310 [1:0] \$115 [1:0] - case - assign $1\log_dmi_addr$next[31:0]$3310 \log_dmi_addr - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\log_dmi_addr$next[31:0]$3313 0 - case - assign $4\log_dmi_addr$next[31:0]$3313 $1\log_dmi_addr$next[31:0]$3310 - end - sync always - update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3309 - end - attribute \src "issuer_ls180.v:49860.3-49868.6" - process $proc$issuer_ls180.v:49860$3314 - assign { } { } - assign { } { } - assign $0\dmi_read_log_data_1$next[0:0]$3315 $1\dmi_read_log_data_1$next[0:0]$3316 - attribute \src "issuer_ls180.v:49861.5-49861.29" - switch \initial - attribute \src "issuer_ls180.v:49861.9-49861.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi_read_log_data_1$next[0:0]$3316 1'0 - case - assign $1\dmi_read_log_data_1$next[0:0]$3316 \dmi_read_log_data - end - sync always - update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3315 - end - attribute \src "issuer_ls180.v:49869.3-49877.6" - process $proc$issuer_ls180.v:49869$3317 - assign { } { } - assign { } { } - assign $0\dmi_read_log_data$next[0:0]$3318 $1\dmi_read_log_data$next[0:0]$3319 - attribute \src "issuer_ls180.v:49870.5-49870.29" - switch \initial - attribute \src "issuer_ls180.v:49870.9-49870.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi_read_log_data$next[0:0]$3319 1'0 - case - assign $1\dmi_read_log_data$next[0:0]$3319 \$120 - end - sync always - update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3318 - end - attribute \src "issuer_ls180.v:49878.3-49887.6" - process $proc$issuer_ls180.v:49878$3320 - assign { } { } - assign { } { } - assign $0\d_cr_req[0:0] $1\d_cr_req[0:0] - attribute \src "issuer_ls180.v:49879.5-49879.29" - switch \initial - attribute \src "issuer_ls180.v:49879.9-49879.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" - switch \dmi_addr_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\d_cr_req[0:0] \dmi_req_i - case - assign $1\d_cr_req[0:0] 1'0 - end - sync always - update \d_cr_req $0\d_cr_req[0:0] - end - attribute \src "issuer_ls180.v:49888.3-49897.6" - process $proc$issuer_ls180.v:49888$3321 - assign { } { } - assign { } { } - assign $0\d_xer_req[0:0] $1\d_xer_req[0:0] - attribute \src "issuer_ls180.v:49889.5-49889.29" - switch \initial - attribute \src "issuer_ls180.v:49889.9-49889.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" - switch \dmi_addr_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\d_xer_req[0:0] \dmi_req_i - case - assign $1\d_xer_req[0:0] 1'0 - end - sync always - update \d_xer_req $0\d_xer_req[0:0] - end - attribute \src "issuer_ls180.v:49898.3-49928.6" - process $proc$issuer_ls180.v:49898$3322 - assign { } { } - assign { } { } - assign $0\dmi_dout[63:0] $1\dmi_dout[63:0] - attribute \src "issuer_ls180.v:49899.5-49899.29" - switch \initial - attribute \src "issuer_ls180.v:49899.9-49899.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" - switch \dmi_addr_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dmi_dout[63:0] \stat_reg - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dmi_dout[63:0] \core_dbg_pc - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dmi_dout[63:0] \core_dbg_msr - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dmi_dout[63:0] \d_gpr_data - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dmi_dout[63:0] { \log_write_addr_o \log_dmi_addr } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dmi_dout[63:0] \log_dmi_data - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dmi_dout[63:0] \d_cr_data - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dmi_dout[63:0] \d_xer_data - case - assign $1\dmi_dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dmi_dout $0\dmi_dout[63:0] - end - attribute \src "issuer_ls180.v:49929.3-49958.6" - process $proc$issuer_ls180.v:49929$3323 - assign { } { } - assign { } { } - assign { } { } - assign $0\do_step$next[0:0]$3324 $5\do_step$next[0:0]$3329 - attribute \src "issuer_ls180.v:49930.5-49930.29" - switch \initial - attribute \src "issuer_ls180.v:49930.9-49930.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - switch { \$9 \$5 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\do_step$next[0:0]$3325 $2\do_step$next[0:0]$3326 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" - switch \dmi_we_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\do_step$next[0:0]$3326 $3\do_step$next[0:0]$3327 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - switch { \$15 \$13 \$11 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $3\do_step$next[0:0]$3327 $4\do_step$next[0:0]$3328 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:205" - switch \dmi_din [3] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\do_step$next[0:0]$3328 1'1 - case - assign $4\do_step$next[0:0]$3328 1'0 - end - case - assign $3\do_step$next[0:0]$3327 1'0 - end - case - assign $2\do_step$next[0:0]$3326 1'0 - end - case - assign $1\do_step$next[0:0]$3325 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\do_step$next[0:0]$3329 1'0 - case - assign $5\do_step$next[0:0]$3329 $1\do_step$next[0:0]$3325 - end - sync always - update \do_step$next $0\do_step$next[0:0]$3324 - end - attribute \src "issuer_ls180.v:49959.3-49988.6" - process $proc$issuer_ls180.v:49959$3330 - assign { } { } - assign { } { } - assign { } { } - assign $0\do_reset$next[0:0]$3331 $5\do_reset$next[0:0]$3336 - attribute \src "issuer_ls180.v:49960.5-49960.29" - switch \initial - attribute \src "issuer_ls180.v:49960.9-49960.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - switch { \$23 \$19 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\do_reset$next[0:0]$3332 $2\do_reset$next[0:0]$3333 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" - switch \dmi_we_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\do_reset$next[0:0]$3333 $3\do_reset$next[0:0]$3334 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - switch { \$29 \$27 \$25 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $3\do_reset$next[0:0]$3334 $4\do_reset$next[0:0]$3335 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch \dmi_din [1] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\do_reset$next[0:0]$3335 1'1 - case - assign $4\do_reset$next[0:0]$3335 1'0 - end - case - assign $3\do_reset$next[0:0]$3334 1'0 - end - case - assign $2\do_reset$next[0:0]$3333 1'0 - end - case - assign $1\do_reset$next[0:0]$3332 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\do_reset$next[0:0]$3336 1'0 - case - assign $5\do_reset$next[0:0]$3336 $1\do_reset$next[0:0]$3332 - end - sync always - update \do_reset$next $0\do_reset$next[0:0]$3331 - end - attribute \src "issuer_ls180.v:49989.3-50018.6" - process $proc$issuer_ls180.v:49989$3337 - assign { } { } - assign { } { } - assign { } { } - assign $0\do_icreset$next[0:0]$3338 $5\do_icreset$next[0:0]$3343 - attribute \src "issuer_ls180.v:49990.5-49990.29" - switch \initial - attribute \src "issuer_ls180.v:49990.9-49990.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - switch { \$37 \$33 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\do_icreset$next[0:0]$3339 $2\do_icreset$next[0:0]$3340 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" - switch \dmi_we_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\do_icreset$next[0:0]$3340 $3\do_icreset$next[0:0]$3341 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - switch { \$43 \$41 \$39 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $3\do_icreset$next[0:0]$3341 $4\do_icreset$next[0:0]$3342 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" - switch \dmi_din [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\do_icreset$next[0:0]$3342 1'1 - case - assign $4\do_icreset$next[0:0]$3342 1'0 - end - case - assign $3\do_icreset$next[0:0]$3341 1'0 - end - case - assign $2\do_icreset$next[0:0]$3340 1'0 - end - case - assign $1\do_icreset$next[0:0]$3339 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\do_icreset$next[0:0]$3343 1'0 - case - assign $5\do_icreset$next[0:0]$3343 $1\do_icreset$next[0:0]$3339 - end - sync always - update \do_icreset$next $0\do_icreset$next[0:0]$3338 - end - attribute \src "issuer_ls180.v:50019.3-50052.6" - process $proc$issuer_ls180.v:50019$3344 - assign { } { } - assign { } { } - assign { } { } - assign $0\do_dmi_log_rd$next[0:0]$3345 $4\do_dmi_log_rd$next[0:0]$3349 - attribute \src "issuer_ls180.v:50020.5-50020.29" - switch \initial - attribute \src "issuer_ls180.v:50020.9-50020.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - switch { \$51 \$47 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\do_dmi_log_rd$next[0:0]$3346 $2\do_dmi_log_rd$next[0:0]$3347 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" - switch \dmi_we_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\do_dmi_log_rd$next[0:0]$3347 $3\do_dmi_log_rd$next[0:0]$3348 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - switch { \$57 \$55 \$53 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'--1 - assign $3\do_dmi_log_rd$next[0:0]$3348 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'-1- - assign $3\do_dmi_log_rd$next[0:0]$3348 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $3\do_dmi_log_rd$next[0:0]$3348 1'1 - case - assign $3\do_dmi_log_rd$next[0:0]$3348 1'0 - end - case - assign $2\do_dmi_log_rd$next[0:0]$3347 1'0 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\do_dmi_log_rd$next[0:0]$3346 1'1 - case - assign $1\do_dmi_log_rd$next[0:0]$3346 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\do_dmi_log_rd$next[0:0]$3349 1'0 - case - assign $4\do_dmi_log_rd$next[0:0]$3349 $1\do_dmi_log_rd$next[0:0]$3346 - end - sync always - update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3345 - end - connect \$9 $and$issuer_ls180.v:49583$3205_Y - connect \$99 $eq$issuer_ls180.v:49584$3206_Y - connect \$101 $not$issuer_ls180.v:49585$3207_Y - connect \$103 $and$issuer_ls180.v:49586$3208_Y - connect \$105 $not$issuer_ls180.v:49587$3209_Y - connect \$107 $and$issuer_ls180.v:49588$3210_Y - connect \$109 $eq$issuer_ls180.v:49589$3211_Y - connect \$111 $eq$issuer_ls180.v:49590$3212_Y - connect \$113 $eq$issuer_ls180.v:49591$3213_Y - connect \$116 $add$issuer_ls180.v:49592$3214_Y - connect \$118 $eq$issuer_ls180.v:49593$3215_Y - connect \$11 $eq$issuer_ls180.v:49594$3216_Y - connect \$120 $and$issuer_ls180.v:49595$3217_Y - connect \$122 $not$issuer_ls180.v:49596$3218_Y - connect \$124 $and$issuer_ls180.v:49597$3219_Y - connect \$13 $eq$issuer_ls180.v:49598$3220_Y - connect \$15 $eq$issuer_ls180.v:49599$3221_Y - connect \$17 $not$issuer_ls180.v:49600$3222_Y - connect \$1 $pos$issuer_ls180.v:49601$3223_Y - connect \$19 $and$issuer_ls180.v:49602$3224_Y - connect \$21 $not$issuer_ls180.v:49603$3225_Y - connect \$23 $and$issuer_ls180.v:49604$3226_Y - connect \$25 $eq$issuer_ls180.v:49605$3227_Y - connect \$27 $eq$issuer_ls180.v:49606$3228_Y - connect \$29 $eq$issuer_ls180.v:49607$3229_Y - connect \$31 $not$issuer_ls180.v:49608$3230_Y - connect \$33 $and$issuer_ls180.v:49609$3231_Y - connect \$35 $not$issuer_ls180.v:49610$3232_Y - connect \$37 $and$issuer_ls180.v:49611$3233_Y - connect \$3 $not$issuer_ls180.v:49612$3234_Y - connect \$39 $eq$issuer_ls180.v:49613$3235_Y - connect \$41 $eq$issuer_ls180.v:49614$3236_Y - connect \$43 $eq$issuer_ls180.v:49615$3237_Y - connect \$45 $not$issuer_ls180.v:49616$3238_Y - connect \$47 $and$issuer_ls180.v:49617$3239_Y - connect \$49 $not$issuer_ls180.v:49618$3240_Y - connect \$51 $and$issuer_ls180.v:49619$3241_Y - connect \$53 $eq$issuer_ls180.v:49620$3242_Y - connect \$55 $eq$issuer_ls180.v:49621$3243_Y - connect \$57 $eq$issuer_ls180.v:49622$3244_Y - connect \$5 $and$issuer_ls180.v:49623$3245_Y - connect \$59 $not$issuer_ls180.v:49624$3246_Y - connect \$61 $and$issuer_ls180.v:49625$3247_Y - connect \$63 $not$issuer_ls180.v:49626$3248_Y - connect \$65 $and$issuer_ls180.v:49627$3249_Y - connect \$67 $eq$issuer_ls180.v:49628$3250_Y - connect \$69 $eq$issuer_ls180.v:49629$3251_Y - connect \$71 $eq$issuer_ls180.v:49630$3252_Y - connect \$73 $not$issuer_ls180.v:49631$3253_Y - connect \$75 $and$issuer_ls180.v:49632$3254_Y - connect \$77 $not$issuer_ls180.v:49633$3255_Y - connect \$7 $not$issuer_ls180.v:49634$3256_Y - connect \$79 $and$issuer_ls180.v:49635$3257_Y - connect \$81 $eq$issuer_ls180.v:49636$3258_Y - connect \$83 $eq$issuer_ls180.v:49637$3259_Y - connect \$85 $eq$issuer_ls180.v:49638$3260_Y - connect \$87 $not$issuer_ls180.v:49639$3261_Y - connect \$89 $and$issuer_ls180.v:49640$3262_Y - connect \$91 $not$issuer_ls180.v:49641$3263_Y - connect \$93 $and$issuer_ls180.v:49642$3264_Y - connect \$95 $eq$issuer_ls180.v:49643$3265_Y - connect \$97 $eq$issuer_ls180.v:49644$3266_Y - connect \$115 \$116 - connect \log_write_addr_o 0 - connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \terminated_o \terminated - connect \icache_rst_o \do_icreset - connect \core_rst_o \do_reset - connect \core_stop_o \$124 - connect \d_gpr_addr \gspr_index - connect \stat_reg \$1 -end -attribute \src "issuer_ls180.v:50066.1-52081.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec" -attribute \generator "nMigen" -module \dec - attribute \src "issuer_ls180.v:51649.3-51682.6" - wire width 3 $0\ALU_cr_in[2:0] - attribute \src "issuer_ls180.v:51683.3-51716.6" - wire width 3 $0\ALU_cr_out[2:0] - attribute \src "issuer_ls180.v:51309.3-51342.6" - wire width 2 $0\ALU_cry_in[1:0] - attribute \src "issuer_ls180.v:51411.3-51444.6" - wire $0\ALU_cry_out[0:0] - attribute \src "issuer_ls180.v:51513.3-51546.6" - wire width 12 $0\ALU_function_unit[11:0] - attribute \src "issuer_ls180.v:51581.3-51614.6" - wire width 3 $0\ALU_in1_sel[2:0] - attribute \src "issuer_ls180.v:51615.3-51648.6" - wire width 4 $0\ALU_in2_sel[3:0] - attribute \src "issuer_ls180.v:51547.3-51580.6" - wire width 7 $0\ALU_internal_op[6:0] - attribute \src "issuer_ls180.v:51343.3-51376.6" - wire $0\ALU_inv_a[0:0] - attribute \src "issuer_ls180.v:51377.3-51410.6" - wire $0\ALU_inv_out[0:0] - attribute \src "issuer_ls180.v:51445.3-51478.6" - wire $0\ALU_is_32b[0:0] - attribute \src "issuer_ls180.v:51717.3-51750.6" - wire width 4 $0\ALU_ldst_len[3:0] - attribute \src "issuer_ls180.v:51275.3-51308.6" - wire width 2 $0\ALU_rc_sel[1:0] - attribute \src "issuer_ls180.v:51479.3-51512.6" - wire $0\ALU_sgn[0:0] - attribute \src "issuer_ls180.v:50067.7-50067.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:51649.3-51682.6" - wire width 3 $1\ALU_cr_in[2:0] - attribute \src "issuer_ls180.v:51683.3-51716.6" - wire width 3 $1\ALU_cr_out[2:0] - attribute \src "issuer_ls180.v:51309.3-51342.6" - wire width 2 $1\ALU_cry_in[1:0] - attribute \src "issuer_ls180.v:51411.3-51444.6" - wire $1\ALU_cry_out[0:0] - attribute \src "issuer_ls180.v:51513.3-51546.6" - wire width 12 $1\ALU_function_unit[11:0] - attribute \src "issuer_ls180.v:51581.3-51614.6" - wire width 3 $1\ALU_in1_sel[2:0] - attribute \src "issuer_ls180.v:51615.3-51648.6" - wire width 4 $1\ALU_in2_sel[3:0] - attribute \src "issuer_ls180.v:51547.3-51580.6" - wire width 7 $1\ALU_internal_op[6:0] - attribute \src "issuer_ls180.v:51343.3-51376.6" - wire $1\ALU_inv_a[0:0] - attribute \src "issuer_ls180.v:51377.3-51410.6" - wire $1\ALU_inv_out[0:0] - attribute \src "issuer_ls180.v:51445.3-51478.6" - wire $1\ALU_is_32b[0:0] - attribute \src "issuer_ls180.v:51717.3-51750.6" - wire width 4 $1\ALU_ldst_len[3:0] - attribute \src "issuer_ls180.v:51275.3-51308.6" - wire width 2 $1\ALU_rc_sel[1:0] - attribute \src "issuer_ls180.v:51479.3-51512.6" - wire $1\ALU_sgn[0:0] - attribute \src "issuer_ls180.v:51240.17-51240.211" - wire width 32 $ternary$issuer_ls180.v:51240$3362_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" - wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \ALU_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 27 \ALU_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 26 \ALU_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 32 \ALU_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 output 25 \ALU_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 3 \ALU_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 2 \ALU_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 30 \ALU_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \ALU_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 28 \ALU_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 10 \ALU_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 \ALU_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 output 31 \ALU_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 output 29 \ALU_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \ALU_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 24 output 22 \ALU_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \ALU_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \ALU_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \ALU_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \ALU_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \ALU_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire output 24 \ALU_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 17 \ALU_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \ALU_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \ALU_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \ALU_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire output 23 \ALU_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \ALU_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 20 \ALU_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 output 18 \ALU_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 10 \ALU_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \ALU_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 output 19 \ALU_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 4 \ALU_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \ALU_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \ALU_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 14 \ALU_cry_out - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \ALU_dec19_ALU_dec19_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \ALU_dec19_ALU_dec19_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \ALU_dec19_ALU_dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \ALU_dec19_ALU_dec19_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \ALU_dec19_ALU_dec19_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \ALU_dec19_ALU_dec19_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \ALU_dec19_ALU_dec19_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \ALU_dec19_ALU_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \ALU_dec19_ALU_dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \ALU_dec19_ALU_dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \ALU_dec19_ALU_dec19_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \ALU_dec19_ALU_dec19_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \ALU_dec19_ALU_dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \ALU_dec19_ALU_dec19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \ALU_dec19_opcode_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \ALU_dec31_ALU_dec31_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \ALU_dec31_ALU_dec31_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \ALU_dec31_ALU_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \ALU_dec31_ALU_dec31_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \ALU_dec31_ALU_dec31_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \ALU_dec31_ALU_dec31_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \ALU_dec31_ALU_dec31_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \ALU_dec31_ALU_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \ALU_dec31_ALU_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \ALU_dec31_ALU_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \ALU_dec31_ALU_dec31_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \ALU_dec31_ALU_dec31_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \ALU_dec31_ALU_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \ALU_dec31_ALU_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \ALU_dec31_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 7 \ALU_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 8 \ALU_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 9 \ALU_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 6 \ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 11 \ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 12 \ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \ALU_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 10 \ALU_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 3 \ALU_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 6 output 21 \ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \TX_RA - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 output 35 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 output 33 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 output 34 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_L3 - attribute \src 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width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire input 1 \bigendian - attribute \src "issuer_ls180.v:50067.7-50067.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 input 36 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" - cell $mux $ternary$issuer_ls180.v:51240$3362 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $ternary$issuer_ls180.v:51240$3362_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:51241.13-51257.4" - cell \ALU_dec19 \ALU_dec19 - connect \ALU_dec19_cr_in \ALU_dec19_ALU_dec19_cr_in - connect \ALU_dec19_cr_out \ALU_dec19_ALU_dec19_cr_out - connect \ALU_dec19_cry_in \ALU_dec19_ALU_dec19_cry_in - connect \ALU_dec19_cry_out \ALU_dec19_ALU_dec19_cry_out - connect \ALU_dec19_function_unit \ALU_dec19_ALU_dec19_function_unit - connect \ALU_dec19_in1_sel \ALU_dec19_ALU_dec19_in1_sel - connect \ALU_dec19_in2_sel \ALU_dec19_ALU_dec19_in2_sel - connect \ALU_dec19_internal_op \ALU_dec19_ALU_dec19_internal_op - connect \ALU_dec19_inv_a \ALU_dec19_ALU_dec19_inv_a - connect \ALU_dec19_inv_out \ALU_dec19_ALU_dec19_inv_out - connect \ALU_dec19_is_32b \ALU_dec19_ALU_dec19_is_32b - connect \ALU_dec19_ldst_len \ALU_dec19_ALU_dec19_ldst_len - connect \ALU_dec19_rc_sel \ALU_dec19_ALU_dec19_rc_sel - connect \ALU_dec19_sgn \ALU_dec19_ALU_dec19_sgn - connect \opcode_in \ALU_dec19_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:51258.13-51274.4" - cell \ALU_dec31 \ALU_dec31 - connect \ALU_dec31_cr_in \ALU_dec31_ALU_dec31_cr_in - connect \ALU_dec31_cr_out \ALU_dec31_ALU_dec31_cr_out - connect \ALU_dec31_cry_in \ALU_dec31_ALU_dec31_cry_in - connect \ALU_dec31_cry_out \ALU_dec31_ALU_dec31_cry_out - connect \ALU_dec31_function_unit \ALU_dec31_ALU_dec31_function_unit - connect \ALU_dec31_in1_sel \ALU_dec31_ALU_dec31_in1_sel - connect \ALU_dec31_in2_sel \ALU_dec31_ALU_dec31_in2_sel - connect \ALU_dec31_internal_op \ALU_dec31_ALU_dec31_internal_op - connect \ALU_dec31_inv_a \ALU_dec31_ALU_dec31_inv_a - connect \ALU_dec31_inv_out \ALU_dec31_ALU_dec31_inv_out - connect \ALU_dec31_is_32b \ALU_dec31_ALU_dec31_is_32b - connect \ALU_dec31_ldst_len \ALU_dec31_ALU_dec31_ldst_len - connect \ALU_dec31_rc_sel \ALU_dec31_ALU_dec31_rc_sel - connect \ALU_dec31_sgn \ALU_dec31_ALU_dec31_sgn - connect \opcode_in \ALU_dec31_opcode_in - end - attribute \src "issuer_ls180.v:50067.7-50067.20" - process $proc$issuer_ls180.v:50067$3377 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:51275.3-51308.6" - process $proc$issuer_ls180.v:51275$3363 - assign { } { } - assign { } { } - assign $0\ALU_rc_sel[1:0] $1\ALU_rc_sel[1:0] - attribute \src "issuer_ls180.v:51276.5-51276.29" - switch \initial - attribute \src "issuer_ls180.v:51276.9-51276.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_rc_sel[1:0] \ALU_dec19_ALU_dec19_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_rc_sel[1:0] \ALU_dec31_ALU_dec31_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_rc_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_rc_sel[1:0] 2'00 - case - assign $1\ALU_rc_sel[1:0] 2'00 - end - sync always - update \ALU_rc_sel $0\ALU_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:51309.3-51342.6" - process $proc$issuer_ls180.v:51309$3364 - assign { } { } - assign { } { } - assign $0\ALU_cry_in[1:0] $1\ALU_cry_in[1:0] - attribute \src "issuer_ls180.v:51310.5-51310.29" - switch \initial - attribute \src "issuer_ls180.v:51310.9-51310.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_cry_in[1:0] \ALU_dec19_ALU_dec19_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_cry_in[1:0] \ALU_dec31_ALU_dec31_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_cry_in[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_cry_in[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_cry_in[1:0] 2'01 - case - assign $1\ALU_cry_in[1:0] 2'00 - end - sync always - update \ALU_cry_in $0\ALU_cry_in[1:0] - end - attribute \src "issuer_ls180.v:51343.3-51376.6" - process $proc$issuer_ls180.v:51343$3365 - assign { } { } - assign { } { } - assign $0\ALU_inv_a[0:0] $1\ALU_inv_a[0:0] - attribute \src "issuer_ls180.v:51344.5-51344.29" - switch \initial - attribute \src "issuer_ls180.v:51344.9-51344.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_inv_a[0:0] \ALU_dec19_ALU_dec19_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_inv_a[0:0] \ALU_dec31_ALU_dec31_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_inv_a[0:0] 1'1 - case - assign $1\ALU_inv_a[0:0] 1'0 - end - sync always - update \ALU_inv_a $0\ALU_inv_a[0:0] - end - attribute \src "issuer_ls180.v:51377.3-51410.6" - process $proc$issuer_ls180.v:51377$3366 - assign { } { } - assign { } { } - assign $0\ALU_inv_out[0:0] $1\ALU_inv_out[0:0] - attribute \src "issuer_ls180.v:51378.5-51378.29" - switch \initial - attribute \src "issuer_ls180.v:51378.9-51378.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_inv_out[0:0] \ALU_dec19_ALU_dec19_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_inv_out[0:0] \ALU_dec31_ALU_dec31_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_inv_out[0:0] 1'0 - case - assign $1\ALU_inv_out[0:0] 1'0 - end - sync always - update \ALU_inv_out $0\ALU_inv_out[0:0] - end - attribute \src "issuer_ls180.v:51411.3-51444.6" - process $proc$issuer_ls180.v:51411$3367 - assign { } { } - assign { } { } - assign $0\ALU_cry_out[0:0] $1\ALU_cry_out[0:0] - attribute \src "issuer_ls180.v:51412.5-51412.29" - switch \initial - attribute \src "issuer_ls180.v:51412.9-51412.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_cry_out[0:0] \ALU_dec19_ALU_dec19_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_cry_out[0:0] \ALU_dec31_ALU_dec31_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_cry_out[0:0] 1'1 - case - assign $1\ALU_cry_out[0:0] 1'0 - end - sync always - update \ALU_cry_out $0\ALU_cry_out[0:0] - end - attribute \src "issuer_ls180.v:51445.3-51478.6" - process $proc$issuer_ls180.v:51445$3368 - assign { } { } - assign { } { } - assign $0\ALU_is_32b[0:0] $1\ALU_is_32b[0:0] - attribute \src "issuer_ls180.v:51446.5-51446.29" - switch \initial - attribute \src "issuer_ls180.v:51446.9-51446.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_is_32b[0:0] \ALU_dec19_ALU_dec19_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_is_32b[0:0] \ALU_dec31_ALU_dec31_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_is_32b[0:0] 1'0 - case - assign $1\ALU_is_32b[0:0] 1'0 - end - sync always - update \ALU_is_32b $0\ALU_is_32b[0:0] - end - attribute \src "issuer_ls180.v:51479.3-51512.6" - process $proc$issuer_ls180.v:51479$3369 - assign { } { } - assign { } { } - assign $0\ALU_sgn[0:0] $1\ALU_sgn[0:0] - attribute \src "issuer_ls180.v:51480.5-51480.29" - switch \initial - attribute \src "issuer_ls180.v:51480.9-51480.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_sgn[0:0] \ALU_dec19_ALU_dec19_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_sgn[0:0] \ALU_dec31_ALU_dec31_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_sgn[0:0] 1'0 - case - assign $1\ALU_sgn[0:0] 1'0 - end - sync always - update \ALU_sgn $0\ALU_sgn[0:0] - end - attribute \src "issuer_ls180.v:51513.3-51546.6" - process $proc$issuer_ls180.v:51513$3370 - assign { } { } - assign { } { } - assign $0\ALU_function_unit[11:0] $1\ALU_function_unit[11:0] - attribute \src "issuer_ls180.v:51514.5-51514.29" - switch \initial - attribute \src "issuer_ls180.v:51514.9-51514.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_function_unit[11:0] \ALU_dec19_ALU_dec19_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_function_unit[11:0] \ALU_dec31_ALU_dec31_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_function_unit[11:0] 12'000000000010 - case - assign $1\ALU_function_unit[11:0] 12'000000000000 - end - sync always - update \ALU_function_unit $0\ALU_function_unit[11:0] - end - attribute \src "issuer_ls180.v:51547.3-51580.6" - process $proc$issuer_ls180.v:51547$3371 - assign { } { } - assign { } { } - assign $0\ALU_internal_op[6:0] $1\ALU_internal_op[6:0] - attribute \src "issuer_ls180.v:51548.5-51548.29" - switch \initial - attribute \src "issuer_ls180.v:51548.9-51548.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_internal_op[6:0] \ALU_dec19_ALU_dec19_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_internal_op[6:0] \ALU_dec31_ALU_dec31_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_internal_op[6:0] 7'0001010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_internal_op[6:0] 7'0001010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_internal_op[6:0] 7'0000010 - case - assign $1\ALU_internal_op[6:0] 7'0000000 - end - sync always - update \ALU_internal_op $0\ALU_internal_op[6:0] - end - attribute \src "issuer_ls180.v:51581.3-51614.6" - process $proc$issuer_ls180.v:51581$3372 - assign { } { } - assign { } { } - assign $0\ALU_in1_sel[2:0] $1\ALU_in1_sel[2:0] - attribute \src "issuer_ls180.v:51582.5-51582.29" - switch \initial - attribute \src "issuer_ls180.v:51582.9-51582.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_in1_sel[2:0] \ALU_dec19_ALU_dec19_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_in1_sel[2:0] \ALU_dec31_ALU_dec31_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_in1_sel[2:0] 3'001 - case - assign $1\ALU_in1_sel[2:0] 3'000 - end - sync always - update \ALU_in1_sel $0\ALU_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:51615.3-51648.6" - process $proc$issuer_ls180.v:51615$3373 - assign { } { } - assign { } { } - assign $0\ALU_in2_sel[3:0] $1\ALU_in2_sel[3:0] - attribute \src "issuer_ls180.v:51616.5-51616.29" - switch \initial - attribute \src "issuer_ls180.v:51616.9-51616.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_in2_sel[3:0] \ALU_dec19_ALU_dec19_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_in2_sel[3:0] \ALU_dec31_ALU_dec31_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_in2_sel[3:0] 4'0101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_in2_sel[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_in2_sel[3:0] 4'0011 - case - assign $1\ALU_in2_sel[3:0] 4'0000 - end - sync always - update \ALU_in2_sel $0\ALU_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:51649.3-51682.6" - process $proc$issuer_ls180.v:51649$3374 - assign { } { } - assign { } { } - assign $0\ALU_cr_in[2:0] $1\ALU_cr_in[2:0] - attribute \src "issuer_ls180.v:51650.5-51650.29" - switch \initial - attribute \src "issuer_ls180.v:51650.9-51650.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_cr_in[2:0] \ALU_dec19_ALU_dec19_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_cr_in[2:0] \ALU_dec31_ALU_dec31_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_cr_in[2:0] 3'000 - case - assign $1\ALU_cr_in[2:0] 3'000 - end - sync always - update \ALU_cr_in $0\ALU_cr_in[2:0] - end - attribute \src "issuer_ls180.v:51683.3-51716.6" - process $proc$issuer_ls180.v:51683$3375 - assign { } { } - assign { } { } - assign $0\ALU_cr_out[2:0] $1\ALU_cr_out[2:0] - attribute \src "issuer_ls180.v:51684.5-51684.29" - switch \initial - attribute \src "issuer_ls180.v:51684.9-51684.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_cr_out[2:0] \ALU_dec19_ALU_dec19_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_cr_out[2:0] \ALU_dec31_ALU_dec31_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_cr_out[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_cr_out[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_cr_out[2:0] 3'000 - case - assign $1\ALU_cr_out[2:0] 3'000 - end - sync always - update \ALU_cr_out $0\ALU_cr_out[2:0] - end - attribute \src "issuer_ls180.v:51717.3-51750.6" - process $proc$issuer_ls180.v:51717$3376 - assign { } { } - assign { } { } - assign $0\ALU_ldst_len[3:0] $1\ALU_ldst_len[3:0] - attribute \src "issuer_ls180.v:51718.5-51718.29" - switch \initial - attribute \src "issuer_ls180.v:51718.9-51718.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_ldst_len[3:0] \ALU_dec19_ALU_dec19_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_ldst_len[3:0] \ALU_dec31_ALU_dec31_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_ldst_len[3:0] 4'0000 - case - assign $1\ALU_ldst_len[3:0] 4'0000 - end - sync always - update \ALU_ldst_len $0\ALU_ldst_len[3:0] - end - connect \$1 $ternary$issuer_ls180.v:51240$3362_Y - connect \VC_XO \opcode_in [9:0] - connect \VC_VRT \opcode_in [25:21] - connect \VC_VRB \opcode_in [15:11] - connect \VC_VRA \opcode_in [20:16] - connect \VC_Rc \opcode_in [10] - connect \XS_XO \opcode_in [10:2] - connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } - connect \XS_RS \opcode_in [25:21] - connect \XS_Rc \opcode_in [0] - connect \XS_RA \opcode_in [20:16] - connect \VA_XO \opcode_in [5:0] - connect \VA_VRT \opcode_in [25:21] - connect \VA_VRC \opcode_in [10:6] - connect \VA_VRB \opcode_in [15:11] - connect \VA_VRA \opcode_in [20:16] - connect \VA_SHB \opcode_in [9:6] - connect \VA_RT \opcode_in [25:21] - connect \VA_RC \opcode_in [10:6] - connect \VA_RB \opcode_in [15:11] - connect \VA_RA \opcode_in [20:16] - connect \TX_XO \opcode_in [6:1] - connect \TX_XBI \opcode_in [10:7] - connect \TX_UI \opcode_in [15:11] - connect \TX_RA \opcode_in [20:16] - connect \DQE_XO \opcode_in [1:0] - connect \DQE_RT \opcode_in [25:21] - connect \DQE_RA \opcode_in [20:16] - connect \XO_XO \opcode_in [9:1] - connect \XO_RT \opcode_in [25:21] - connect \XO_Rc \opcode_in [0] - connect \XO_RB \opcode_in [15:11] - connect \XO_RA \opcode_in [20:16] - connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] - connect \MD_XO \opcode_in [4:2] - connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } - connect \MD_RS \opcode_in [25:21] - connect \MD_Rc \opcode_in [0] - connect \MD_RA \opcode_in [20:16] - connect \MD_me \opcode_in [10:5] - connect \MD_mb \opcode_in [10:5] - connect \M_SH \opcode_in [15:11] - connect \M_RS \opcode_in [25:21] - connect \M_Rc \opcode_in [0] - connect \M_RB \opcode_in [15:11] - connect \M_RA \opcode_in [20:16] - connect \M_ME \opcode_in [5:1] - connect \M_MB \opcode_in [10:6] - connect \SC_XO_1 \opcode_in [1:0] - connect \SC_XO \opcode_in [1] - connect \SC_LEV \opcode_in [11:5] - connect \MDS_XO \opcode_in [4:1] - connect \MDS_XBI_1 \opcode_in [10:7] - connect \MDS_XBI \opcode_in [10:7] - connect \MDS_RS \opcode_in [25:21] - connect \MDS_Rc \opcode_in [0] - connect \MDS_RB \opcode_in [15:11] - connect \MDS_RA \opcode_in [20:16] - connect \MDS_me \opcode_in [10:5] - connect \MDS_mb \opcode_in [10:5] - connect \MDS_IS \opcode_in [25:21] - connect \MDS_IB \opcode_in [15:11] - connect \Z23_XO \opcode_in [8:1] - connect \Z23_TE \opcode_in [20:16] - connect \Z23_RMC \opcode_in [10:9] - connect \Z23_Rc \opcode_in [0] - connect \Z23_R \opcode_in [16] - connect \Z23_FRTp \opcode_in [25:21] - connect \Z23_FRT \opcode_in [25:21] - connect \Z23_FRBp \opcode_in [15:11] - connect \Z23_FRB \opcode_in [15:11] - connect \Z23_FRAp \opcode_in [20:16] - connect \Z23_FRA \opcode_in [20:16] - connect \XFL_XO \opcode_in [10:1] - connect \XFL_W \opcode_in [16] - connect \XFL_Rc \opcode_in [0] - connect \XFL_L \opcode_in [25] - connect \XFL_FRB \opcode_in [15:11] - connect \XFL_FLM \opcode_in [24:17] - connect \VX_XO_1 \opcode_in [10:0] - connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } - connect \VX_VRT \opcode_in [25:21] - connect \VX_VRB \opcode_in [15:11] - connect \VX_VRA \opcode_in [20:16] - connect \VX_UIM_3 \opcode_in [17:16] - connect \VX_UIM_2 \opcode_in [18:16] - connect \VX_UIM_1 \opcode_in [19:16] - connect \VX_UIM \opcode_in [20:16] - connect \VX_SIM \opcode_in [20:16] - connect \VX_RT \opcode_in [25:21] - connect \VX_RA \opcode_in [20:16] - connect \VX_PS \opcode_in [9] - connect \VX_EO \opcode_in [20:16] - connect \DS_XO \opcode_in [1:0] - connect \DS_VRT \opcode_in [25:21] - connect \DS_VRS \opcode_in [25:21] - connect \DS_RT \opcode_in [25:21] - connect \DS_RSp \opcode_in [25:21] - connect \DS_RS \opcode_in [25:21] - connect \DS_RA \opcode_in [20:16] - connect \DS_FRTp \opcode_in [25:21] - connect \DS_FRSp \opcode_in [25:21] - connect \DS_DS \opcode_in [15:2] - connect \DQ_XO \opcode_in [2:0] - connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_T \opcode_in [25:21] - connect \DQ_TX \opcode_in [3] - connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_S \opcode_in [25:21] - connect \DQ_SX \opcode_in [3] - connect \DQ_RTp \opcode_in [25:21] - connect \DQ_RA \opcode_in [20:16] - connect \DQ_PT \opcode_in [3:0] - connect \DQ_DQ \opcode_in [15:4] - connect \DX_XO \opcode_in [5:1] - connect \DX_RT \opcode_in [25:21] - connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } - connect \DX_d2 \opcode_in [0] - connect \DX_d1 \opcode_in [20:16] - connect \DX_d0 \opcode_in [15:6] - connect \XFX_XO \opcode_in [10:1] - connect \XFX_SPR \opcode_in [20:11] - connect \XFX_RT \opcode_in [25:21] - connect \XFX_RS \opcode_in [25:21] - connect \XFX_FXM \opcode_in [19:12] - connect \XFX_DUIS \opcode_in [20:11] - connect \XFX_DUI \opcode_in [25:21] - connect \XFX_BHRBE \opcode_in [20:11] - connect \EVS_BFA \opcode_in [2:0] - connect \Z22_XO \opcode_in [9:1] - connect \Z22_SH \opcode_in [15:10] - connect \Z22_Rc \opcode_in [0] - connect \Z22_FRTp \opcode_in [25:21] - connect \Z22_FRT \opcode_in [25:21] - connect \Z22_FRAp \opcode_in [20:16] - connect \Z22_FRA \opcode_in [20:16] - connect \Z22_DGM \opcode_in [15:10] - connect \Z22_DCM \opcode_in [15:10] - connect \Z22_BF \opcode_in [25:23] - connect \XX2_XO_1 \opcode_in [10:2] - connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } - connect \XX2_UIM_1 \opcode_in [17:16] - connect \XX2_UIM \opcode_in [19:16] - connect \XX2_TX_T { \opcode_in [0] \opcode_in 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 output 18 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \XX2_XO - attribute \src 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wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire input 1 \bigendian - attribute \src "issuer_ls180.v:52086.7-52086.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 input 19 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" - cell $mux $ternary$issuer_ls180.v:53103$3378 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $ternary$issuer_ls180.v:53103$3378_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:53104.12-53111.4" - cell \CR_dec19 \CR_dec19 - connect \CR_dec19_cr_in \CR_dec19_CR_dec19_cr_in - connect \CR_dec19_cr_out \CR_dec19_CR_dec19_cr_out - connect \CR_dec19_function_unit \CR_dec19_CR_dec19_function_unit - connect \CR_dec19_internal_op \CR_dec19_CR_dec19_internal_op - connect \CR_dec19_rc_sel \CR_dec19_CR_dec19_rc_sel - connect \opcode_in \CR_dec19_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:53112.12-53119.4" - cell \CR_dec31 \CR_dec31 - connect \CR_dec31_cr_in \CR_dec31_CR_dec31_cr_in - connect \CR_dec31_cr_out \CR_dec31_CR_dec31_cr_out - connect \CR_dec31_function_unit \CR_dec31_CR_dec31_function_unit - connect \CR_dec31_internal_op \CR_dec31_CR_dec31_internal_op - connect \CR_dec31_rc_sel \CR_dec31_CR_dec31_rc_sel - connect \opcode_in \CR_dec31_opcode_in - end - attribute \src "issuer_ls180.v:52086.7-52086.20" - process $proc$issuer_ls180.v:52086$3384 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:53120.3-53132.6" - process $proc$issuer_ls180.v:53120$3379 - assign { } { } - assign { } { } - assign $0\CR_function_unit[11:0] $1\CR_function_unit[11:0] - attribute \src "issuer_ls180.v:53121.5-53121.29" - switch \initial - attribute \src "issuer_ls180.v:53121.9-53121.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\CR_function_unit[11:0] \CR_dec19_CR_dec19_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\CR_function_unit[11:0] \CR_dec31_CR_dec31_function_unit - case - assign $1\CR_function_unit[11:0] 12'000000000000 - end - sync always - update \CR_function_unit $0\CR_function_unit[11:0] - end - attribute \src "issuer_ls180.v:53133.3-53145.6" - process $proc$issuer_ls180.v:53133$3380 - assign { } { } - assign { } { } - assign $0\CR_internal_op[6:0] $1\CR_internal_op[6:0] - attribute \src "issuer_ls180.v:53134.5-53134.29" - switch \initial - attribute \src "issuer_ls180.v:53134.9-53134.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\CR_internal_op[6:0] \CR_dec19_CR_dec19_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\CR_internal_op[6:0] \CR_dec31_CR_dec31_internal_op - case - assign $1\CR_internal_op[6:0] 7'0000000 - end - sync always - update \CR_internal_op $0\CR_internal_op[6:0] - end - attribute \src "issuer_ls180.v:53146.3-53158.6" - process $proc$issuer_ls180.v:53146$3381 - assign { } { } - assign { } { } - assign $0\CR_cr_in[2:0] $1\CR_cr_in[2:0] - attribute \src "issuer_ls180.v:53147.5-53147.29" - switch \initial - attribute \src "issuer_ls180.v:53147.9-53147.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\CR_cr_in[2:0] \CR_dec19_CR_dec19_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\CR_cr_in[2:0] \CR_dec31_CR_dec31_cr_in - case - assign $1\CR_cr_in[2:0] 3'000 - end - sync always - update \CR_cr_in $0\CR_cr_in[2:0] - end - attribute \src "issuer_ls180.v:53159.3-53171.6" - process $proc$issuer_ls180.v:53159$3382 - assign { } { } - assign { } { } - assign $0\CR_cr_out[2:0] $1\CR_cr_out[2:0] - attribute \src "issuer_ls180.v:53160.5-53160.29" - switch \initial - attribute \src "issuer_ls180.v:53160.9-53160.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\CR_cr_out[2:0] \CR_dec19_CR_dec19_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\CR_cr_out[2:0] \CR_dec31_CR_dec31_cr_out - case - assign $1\CR_cr_out[2:0] 3'000 - end - sync always - update \CR_cr_out $0\CR_cr_out[2:0] - end - attribute \src "issuer_ls180.v:53172.3-53184.6" - process $proc$issuer_ls180.v:53172$3383 - assign { } { } - assign { } { } - assign $0\CR_rc_sel[1:0] $1\CR_rc_sel[1:0] - attribute \src "issuer_ls180.v:53173.5-53173.29" - switch \initial - attribute \src "issuer_ls180.v:53173.9-53173.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\CR_rc_sel[1:0] \CR_dec19_CR_dec19_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\CR_rc_sel[1:0] \CR_dec31_CR_dec31_rc_sel - case - assign $1\CR_rc_sel[1:0] 2'00 - end - sync always - update \CR_rc_sel $0\CR_rc_sel[1:0] - end - connect \$1 $ternary$issuer_ls180.v:53103$3378_Y - connect \VC_XO \opcode_in [9:0] - connect \VC_VRT \opcode_in [25:21] - connect \VC_VRB \opcode_in [15:11] - connect \VC_VRA \opcode_in [20:16] - connect \VC_Rc \opcode_in [10] - connect \XS_XO \opcode_in [10:2] - connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } - connect \XS_RS \opcode_in [25:21] - connect \XS_Rc \opcode_in [0] - connect \XS_RA \opcode_in [20:16] - connect \VA_XO \opcode_in [5:0] - connect \VA_VRT \opcode_in [25:21] - connect \VA_VRC \opcode_in [10:6] - connect \VA_VRB \opcode_in [15:11] - connect \VA_VRA \opcode_in [20:16] - connect \VA_SHB \opcode_in [9:6] - connect \VA_RT \opcode_in [25:21] - connect \VA_RC \opcode_in [10:6] - connect \VA_RB \opcode_in [15:11] - connect \VA_RA \opcode_in [20:16] - connect \TX_XO \opcode_in [6:1] - connect \TX_XBI \opcode_in [10:7] - connect \TX_UI \opcode_in [15:11] - connect \TX_RA \opcode_in [20:16] - connect \DQE_XO \opcode_in [1:0] - connect \DQE_RT \opcode_in [25:21] - connect \DQE_RA \opcode_in [20:16] - connect \XO_XO \opcode_in [9:1] - connect \XO_RT \opcode_in [25:21] - connect \XO_Rc \opcode_in [0] - connect \XO_RB \opcode_in [15:11] - connect \XO_RA \opcode_in [20:16] - connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] - connect \MD_XO \opcode_in [4:2] - connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } - connect \MD_RS \opcode_in [25:21] - connect \MD_Rc \opcode_in [0] - connect \MD_RA \opcode_in [20:16] - connect \MD_me \opcode_in [10:5] - connect \MD_mb \opcode_in [10:5] - connect \M_SH \opcode_in [15:11] - connect \M_RS \opcode_in [25:21] - connect \M_Rc \opcode_in [0] - connect \M_RB \opcode_in [15:11] - connect \M_RA \opcode_in [20:16] - connect \M_ME \opcode_in [5:1] - connect \M_MB \opcode_in [10:6] - connect \SC_XO_1 \opcode_in [1:0] - connect \SC_XO \opcode_in [1] - connect \SC_LEV \opcode_in [11:5] - connect \MDS_XO \opcode_in [4:1] - connect \MDS_XBI_1 \opcode_in [10:7] - connect \MDS_XBI \opcode_in [10:7] - connect \MDS_RS \opcode_in [25:21] - connect \MDS_Rc \opcode_in [0] - connect \MDS_RB \opcode_in [15:11] - connect \MDS_RA \opcode_in [20:16] - connect \MDS_me \opcode_in [10:5] - connect \MDS_mb \opcode_in [10:5] - connect \MDS_IS \opcode_in [25:21] - connect \MDS_IB \opcode_in [15:11] - connect \Z23_XO \opcode_in [8:1] - connect \Z23_TE \opcode_in [20:16] - connect \Z23_RMC \opcode_in [10:9] - connect \Z23_Rc \opcode_in [0] - connect \Z23_R \opcode_in [16] - connect \Z23_FRTp \opcode_in [25:21] - connect \Z23_FRT \opcode_in [25:21] - connect \Z23_FRBp \opcode_in [15:11] - connect \Z23_FRB \opcode_in [15:11] - connect \Z23_FRAp \opcode_in [20:16] - connect \Z23_FRA \opcode_in [20:16] - connect \XFL_XO \opcode_in [10:1] - connect \XFL_W \opcode_in [16] - connect \XFL_Rc \opcode_in [0] - connect \XFL_L \opcode_in [25] - connect \XFL_FRB \opcode_in [15:11] - connect \XFL_FLM \opcode_in [24:17] - connect \VX_XO_1 \opcode_in [10:0] - connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } - connect \VX_VRT \opcode_in [25:21] - connect \VX_VRB \opcode_in [15:11] - connect \VX_VRA \opcode_in [20:16] - connect \VX_UIM_3 \opcode_in [17:16] - connect \VX_UIM_2 \opcode_in [18:16] - connect \VX_UIM_1 \opcode_in [19:16] - connect \VX_UIM \opcode_in [20:16] - connect \VX_SIM \opcode_in [20:16] - connect \VX_RT \opcode_in [25:21] - connect \VX_RA \opcode_in [20:16] - connect \VX_PS \opcode_in [9] - connect \VX_EO \opcode_in [20:16] - connect \DS_XO \opcode_in [1:0] - connect \DS_VRT \opcode_in [25:21] - connect \DS_VRS \opcode_in [25:21] - connect \DS_RT \opcode_in [25:21] - connect \DS_RSp \opcode_in [25:21] - connect \DS_RS \opcode_in [25:21] - connect \DS_RA \opcode_in [20:16] - connect \DS_FRTp \opcode_in [25:21] - connect \DS_FRSp \opcode_in [25:21] - connect \DS_DS \opcode_in [15:2] - connect \DQ_XO \opcode_in [2:0] - connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_T \opcode_in [25:21] - connect \DQ_TX \opcode_in [3] - connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_S \opcode_in [25:21] - connect \DQ_SX \opcode_in [3] - connect \DQ_RTp \opcode_in [25:21] - connect \DQ_RA \opcode_in [20:16] - connect \DQ_PT \opcode_in [3:0] - connect \DQ_DQ \opcode_in [15:4] - connect \DX_XO \opcode_in [5:1] - connect \DX_RT \opcode_in [25:21] - connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } - connect \DX_d2 \opcode_in [0] - connect \DX_d1 \opcode_in [20:16] - connect \DX_d0 \opcode_in [15:6] - connect \XFX_XO \opcode_in [10:1] - connect \XFX_SPR \opcode_in [20:11] - connect \XFX_RT \opcode_in [25:21] - connect \XFX_RS \opcode_in [25:21] - connect \XFX_FXM \opcode_in [19:12] - connect \XFX_DUIS \opcode_in [20:11] - connect \XFX_DUI \opcode_in [25:21] - connect \XFX_BHRBE \opcode_in [20:11] - connect \EVS_BFA \opcode_in [2:0] - connect \Z22_XO \opcode_in [9:1] - connect \Z22_SH \opcode_in [15:10] - connect \Z22_Rc \opcode_in [0] - connect \Z22_FRTp \opcode_in [25:21] - connect \Z22_FRT \opcode_in [25:21] - connect \Z22_FRAp \opcode_in [20:16] - connect \Z22_FRA \opcode_in [20:16] - connect \Z22_DGM \opcode_in [15:10] - connect \Z22_DCM \opcode_in [15:10] - connect \Z22_BF \opcode_in [25:23] - connect \XX2_XO_1 \opcode_in [10:2] - connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } - connect \XX2_UIM_1 \opcode_in [17:16] - connect \XX2_UIM \opcode_in [19:16] - connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX2_T \opcode_in [25:21] - connect \XX2_TX \opcode_in [0] - connect \XX2_RT \opcode_in [25:21] - connect \XX2_EO \opcode_in [20:16] - connect \XX2_DCMX \opcode_in [22:16] - connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } - connect \XX2_dx \opcode_in [20:16] - connect \XX2_dm \opcode_in [2] - connect \XX2_dc \opcode_in [6] - connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX2_B \opcode_in [15:11] - connect \XX2_BX \opcode_in [1] - connect \XX2_BF \opcode_in [25:23] - connect \D_UI \opcode_in [15:0] - connect \D_TO \opcode_in [25:21] - connect \D_SI \opcode_in [15:0] - connect \D_RT \opcode_in [25:21] - connect \D_RS \opcode_in [25:21] - connect \D_RA \opcode_in [20:16] - connect \D_L \opcode_in [21] - connect \D_FRT \opcode_in [25:21] - connect \D_FRS \opcode_in [25:21] - connect \D_D \opcode_in [15:0] - connect \D_BF \opcode_in [25:23] - connect \A_XO \opcode_in [5:1] - connect \A_RT \opcode_in [25:21] - connect \A_Rc \opcode_in [0] - connect \A_RB \opcode_in [15:11] - connect \A_RA \opcode_in [20:16] - connect \A_FRT \opcode_in [25:21] - connect \A_FRC \opcode_in [10:6] - connect \A_FRB \opcode_in [15:11] - connect \A_FRA \opcode_in [20:16] - connect \A_BC \opcode_in [10:6] - connect \XL_XO \opcode_in [10:1] - connect \XL_S \opcode_in [11] - connect \XL_OC \opcode_in [25:11] - connect \XL_LK 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wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \BRANCH_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 21 \BRANCH_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 20 \BRANCH_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 26 \BRANCH_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 output 19 \BRANCH_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \BRANCH_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \BRANCH_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \BRANCH_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire output 17 \BRANCH_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \BRANCH_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 14 \BRANCH_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 output 12 \BRANCH_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 10 \BRANCH_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \BRANCH_TO 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire input 1 \bigendian - attribute \src "issuer_ls180.v:53520.7-53520.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 input 30 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" - cell $mux $ternary$issuer_ls180.v:54465$3385 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $ternary$issuer_ls180.v:54465$3385_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:54466.16-54476.4" - cell \BRANCH_dec19 \BRANCH_dec19 - connect \BRANCH_dec19_cr_in \BRANCH_dec19_BRANCH_dec19_cr_in - connect \BRANCH_dec19_cr_out \BRANCH_dec19_BRANCH_dec19_cr_out - connect \BRANCH_dec19_function_unit \BRANCH_dec19_BRANCH_dec19_function_unit - connect \BRANCH_dec19_in2_sel \BRANCH_dec19_BRANCH_dec19_in2_sel - connect \BRANCH_dec19_internal_op \BRANCH_dec19_BRANCH_dec19_internal_op - connect \BRANCH_dec19_is_32b \BRANCH_dec19_BRANCH_dec19_is_32b - connect \BRANCH_dec19_lk \BRANCH_dec19_BRANCH_dec19_lk - connect \BRANCH_dec19_rc_sel \BRANCH_dec19_BRANCH_dec19_rc_sel - connect \opcode_in \BRANCH_dec19_opcode_in - end - attribute \src "issuer_ls180.v:53520.7-53520.20" - process $proc$issuer_ls180.v:53520$3394 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:54477.3-54492.6" - process $proc$issuer_ls180.v:54477$3386 - assign { } { } - assign { } { } - assign $0\BRANCH_function_unit[11:0] $1\BRANCH_function_unit[11:0] - attribute \src "issuer_ls180.v:54478.5-54478.29" - switch \initial - attribute \src "issuer_ls180.v:54478.9-54478.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\BRANCH_function_unit[11:0] \BRANCH_dec19_BRANCH_dec19_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\BRANCH_function_unit[11:0] 12'000000100000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\BRANCH_function_unit[11:0] 12'000000100000 - case - assign $1\BRANCH_function_unit[11:0] 12'000000000000 - end - sync always - update \BRANCH_function_unit $0\BRANCH_function_unit[11:0] - end - attribute \src "issuer_ls180.v:54493.3-54508.6" - process $proc$issuer_ls180.v:54493$3387 - assign { } { } - assign { } { } - assign $0\BRANCH_internal_op[6:0] $1\BRANCH_internal_op[6:0] - attribute \src "issuer_ls180.v:54494.5-54494.29" - switch \initial - attribute \src "issuer_ls180.v:54494.9-54494.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\BRANCH_internal_op[6:0] \BRANCH_dec19_BRANCH_dec19_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\BRANCH_internal_op[6:0] 7'0000110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\BRANCH_internal_op[6:0] 7'0000111 - case - assign $1\BRANCH_internal_op[6:0] 7'0000000 - end - sync always - update \BRANCH_internal_op $0\BRANCH_internal_op[6:0] - end - attribute \src "issuer_ls180.v:54509.3-54524.6" - process $proc$issuer_ls180.v:54509$3388 - assign { } { } - assign { } { } - assign $0\BRANCH_in2_sel[3:0] $1\BRANCH_in2_sel[3:0] - attribute \src "issuer_ls180.v:54510.5-54510.29" - switch \initial - attribute \src "issuer_ls180.v:54510.9-54510.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\BRANCH_in2_sel[3:0] \BRANCH_dec19_BRANCH_dec19_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\BRANCH_in2_sel[3:0] 4'0110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\BRANCH_in2_sel[3:0] 4'0111 - case - assign $1\BRANCH_in2_sel[3:0] 4'0000 - end - sync always - update \BRANCH_in2_sel $0\BRANCH_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:54525.3-54540.6" - process $proc$issuer_ls180.v:54525$3389 - assign { } { } - assign { } { } - assign $0\BRANCH_cr_in[2:0] $1\BRANCH_cr_in[2:0] - attribute \src "issuer_ls180.v:54526.5-54526.29" - switch \initial - attribute \src "issuer_ls180.v:54526.9-54526.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\BRANCH_cr_in[2:0] \BRANCH_dec19_BRANCH_dec19_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\BRANCH_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\BRANCH_cr_in[2:0] 3'010 - case - assign $1\BRANCH_cr_in[2:0] 3'000 - end - sync always - update \BRANCH_cr_in $0\BRANCH_cr_in[2:0] - end - attribute \src "issuer_ls180.v:54541.3-54556.6" - process $proc$issuer_ls180.v:54541$3390 - assign { } { } - assign { } { } - assign $0\BRANCH_cr_out[2:0] $1\BRANCH_cr_out[2:0] - attribute \src "issuer_ls180.v:54542.5-54542.29" - switch \initial - attribute \src "issuer_ls180.v:54542.9-54542.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\BRANCH_cr_out[2:0] \BRANCH_dec19_BRANCH_dec19_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\BRANCH_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\BRANCH_cr_out[2:0] 3'000 - case - assign $1\BRANCH_cr_out[2:0] 3'000 - end - sync always - update \BRANCH_cr_out $0\BRANCH_cr_out[2:0] - end - attribute \src "issuer_ls180.v:54557.3-54572.6" - process $proc$issuer_ls180.v:54557$3391 - assign { } { } - assign { } { } - assign $0\BRANCH_rc_sel[1:0] $1\BRANCH_rc_sel[1:0] - attribute \src "issuer_ls180.v:54558.5-54558.29" - switch \initial - attribute \src "issuer_ls180.v:54558.9-54558.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\BRANCH_rc_sel[1:0] \BRANCH_dec19_BRANCH_dec19_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\BRANCH_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\BRANCH_rc_sel[1:0] 2'00 - case - assign $1\BRANCH_rc_sel[1:0] 2'00 - end - sync always - update \BRANCH_rc_sel $0\BRANCH_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:54573.3-54588.6" - process $proc$issuer_ls180.v:54573$3392 - assign { } { } - assign { } { } - assign $0\BRANCH_is_32b[0:0] $1\BRANCH_is_32b[0:0] - attribute \src "issuer_ls180.v:54574.5-54574.29" - switch \initial - attribute \src "issuer_ls180.v:54574.9-54574.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\BRANCH_is_32b[0:0] \BRANCH_dec19_BRANCH_dec19_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\BRANCH_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\BRANCH_is_32b[0:0] 1'0 - case - assign $1\BRANCH_is_32b[0:0] 1'0 - end - sync always - update \BRANCH_is_32b $0\BRANCH_is_32b[0:0] - end - attribute \src "issuer_ls180.v:54589.3-54604.6" - process $proc$issuer_ls180.v:54589$3393 - assign { } { } - assign { } { } - assign $0\BRANCH_lk[0:0] $1\BRANCH_lk[0:0] - attribute \src "issuer_ls180.v:54590.5-54590.29" - switch \initial - attribute \src "issuer_ls180.v:54590.9-54590.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\BRANCH_lk[0:0] \BRANCH_dec19_BRANCH_dec19_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\BRANCH_lk[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\BRANCH_lk[0:0] 1'1 - case - assign $1\BRANCH_lk[0:0] 1'0 - end - sync always - update \BRANCH_lk $0\BRANCH_lk[0:0] - end - connect \$1 $ternary$issuer_ls180.v:54465$3385_Y - connect \VC_XO \opcode_in [9:0] - connect \VC_VRT \opcode_in [25:21] - connect \VC_VRB \opcode_in [15:11] - connect \VC_VRA \opcode_in [20:16] - connect \VC_Rc \opcode_in [10] - connect \XS_XO \opcode_in [10:2] - connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } - connect \XS_RS \opcode_in [25:21] - connect \XS_Rc \opcode_in [0] - connect \XS_RA \opcode_in [20:16] - connect \VA_XO \opcode_in [5:0] - connect \VA_VRT \opcode_in [25:21] - connect \VA_VRC \opcode_in [10:6] - connect \VA_VRB \opcode_in [15:11] - connect \VA_VRA \opcode_in [20:16] - connect \VA_SHB \opcode_in [9:6] - connect \VA_RT \opcode_in [25:21] - connect \VA_RC \opcode_in [10:6] - connect \VA_RB \opcode_in [15:11] - connect \VA_RA \opcode_in [20:16] - connect \TX_XO \opcode_in [6:1] - connect \TX_XBI \opcode_in [10:7] - connect \TX_UI \opcode_in [15:11] - connect \TX_RA \opcode_in [20:16] - connect \DQE_XO \opcode_in [1:0] - connect \DQE_RT \opcode_in [25:21] - connect \DQE_RA \opcode_in [20:16] - connect \XO_XO \opcode_in [9:1] - connect \XO_RT \opcode_in [25:21] - connect \XO_Rc \opcode_in [0] - connect \XO_RB \opcode_in [15:11] - connect \XO_RA \opcode_in [20:16] - connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] - connect \MD_XO \opcode_in [4:2] - connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } - connect \MD_RS \opcode_in [25:21] - connect \MD_Rc \opcode_in [0] - connect \MD_RA \opcode_in [20:16] - connect \MD_me \opcode_in [10:5] - connect \MD_mb \opcode_in [10:5] - connect \M_SH \opcode_in [15:11] - connect \M_RS \opcode_in [25:21] - connect \M_Rc \opcode_in [0] - connect \M_RB \opcode_in [15:11] - connect \M_RA \opcode_in [20:16] - connect \M_ME \opcode_in [5:1] - connect \M_MB \opcode_in [10:6] - connect \SC_XO_1 \opcode_in [1:0] - connect \SC_XO \opcode_in [1] - connect \SC_LEV \opcode_in [11:5] - connect \MDS_XO \opcode_in [4:1] - connect \MDS_XBI_1 \opcode_in [10:7] - connect \MDS_XBI \opcode_in [10:7] - connect \MDS_RS \opcode_in [25:21] - connect \MDS_Rc \opcode_in [0] - connect \MDS_RB \opcode_in [15:11] - connect \MDS_RA \opcode_in [20:16] - connect \MDS_me \opcode_in [10:5] - connect \MDS_mb \opcode_in [10:5] - connect \MDS_IS \opcode_in [25:21] - connect \MDS_IB \opcode_in [15:11] - connect \Z23_XO \opcode_in [8:1] - connect \Z23_TE \opcode_in [20:16] - connect \Z23_RMC \opcode_in [10:9] - connect \Z23_Rc \opcode_in [0] - connect \Z23_R \opcode_in [16] - connect \Z23_FRTp \opcode_in [25:21] - connect \Z23_FRT \opcode_in [25:21] - connect \Z23_FRBp \opcode_in [15:11] - connect \Z23_FRB \opcode_in [15:11] - connect \Z23_FRAp \opcode_in [20:16] - connect \Z23_FRA \opcode_in [20:16] - connect \XFL_XO \opcode_in [10:1] - connect \XFL_W \opcode_in [16] - connect \XFL_Rc \opcode_in [0] - connect \XFL_L \opcode_in [25] - connect \XFL_FRB \opcode_in [15:11] - connect \XFL_FLM \opcode_in [24:17] - connect \VX_XO_1 \opcode_in [10:0] - connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } - connect \VX_VRT \opcode_in [25:21] - connect \VX_VRB \opcode_in [15:11] - connect \VX_VRA \opcode_in [20:16] - connect \VX_UIM_3 \opcode_in [17:16] - connect \VX_UIM_2 \opcode_in [18:16] - connect \VX_UIM_1 \opcode_in [19:16] - connect \VX_UIM \opcode_in [20:16] - connect \VX_SIM \opcode_in [20:16] - connect \VX_RT \opcode_in [25:21] - connect \VX_RA \opcode_in [20:16] - connect \VX_PS \opcode_in [9] - connect \VX_EO \opcode_in [20:16] - connect \DS_XO \opcode_in [1:0] - connect \DS_VRT \opcode_in [25:21] - connect \DS_VRS \opcode_in [25:21] - connect \DS_RT \opcode_in [25:21] - connect \DS_RSp \opcode_in [25:21] - connect \DS_RS \opcode_in [25:21] - connect \DS_RA \opcode_in [20:16] - connect \DS_FRTp \opcode_in [25:21] - connect \DS_FRSp \opcode_in [25:21] - connect \DS_DS \opcode_in [15:2] - connect \DQ_XO \opcode_in [2:0] - connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_T \opcode_in [25:21] - connect \DQ_TX \opcode_in [3] - connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_S \opcode_in [25:21] - connect \DQ_SX \opcode_in [3] - connect \DQ_RTp \opcode_in [25:21] - connect \DQ_RA \opcode_in [20:16] - connect \DQ_PT \opcode_in [3:0] - connect \DQ_DQ \opcode_in [15:4] - connect \DX_XO \opcode_in [5:1] - connect \DX_RT \opcode_in [25:21] - connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } - connect \DX_d2 \opcode_in [0] - connect \DX_d1 \opcode_in [20:16] - connect \DX_d0 \opcode_in [15:6] - connect \XFX_XO \opcode_in [10:1] - connect \XFX_SPR \opcode_in [20:11] - connect \XFX_RT \opcode_in [25:21] - connect \XFX_RS \opcode_in [25:21] - connect \XFX_FXM \opcode_in [19:12] - connect \XFX_DUIS \opcode_in [20:11] - connect \XFX_DUI \opcode_in [25:21] - connect \XFX_BHRBE \opcode_in [20:11] - connect \EVS_BFA \opcode_in [2:0] - connect \Z22_XO \opcode_in [9:1] - connect \Z22_SH \opcode_in [15:10] - connect \Z22_Rc \opcode_in [0] - connect \Z22_FRTp \opcode_in [25:21] - connect \Z22_FRT \opcode_in [25:21] - connect \Z22_FRAp \opcode_in [20:16] - connect \Z22_FRA \opcode_in [20:16] - connect \Z22_DGM \opcode_in [15:10] - connect \Z22_DCM \opcode_in [15:10] - connect \Z22_BF \opcode_in [25:23] - connect \XX2_XO_1 \opcode_in [10:2] - connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } - connect \XX2_UIM_1 \opcode_in [17:16] - connect \XX2_UIM \opcode_in [19:16] - connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX2_T \opcode_in [25:21] - connect \XX2_TX \opcode_in [0] - connect \XX2_RT \opcode_in [25:21] - connect \XX2_EO \opcode_in [20:16] - connect \XX2_DCMX \opcode_in [22:16] - connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } - connect \XX2_dx \opcode_in [20:16] - connect \XX2_dm \opcode_in [2] - connect \XX2_dc \opcode_in [6] - connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX2_B \opcode_in [15:11] - connect \XX2_BX \opcode_in [1] - connect \XX2_BF \opcode_in [25:23] - connect \D_UI \opcode_in [15:0] - connect \D_TO \opcode_in [25:21] - connect \D_SI \opcode_in [15:0] - connect \D_RT \opcode_in [25:21] - connect \D_RS \opcode_in [25:21] - connect \D_RA \opcode_in [20:16] - connect \D_L \opcode_in [21] - connect \D_FRT \opcode_in [25:21] - connect \D_FRS \opcode_in [25:21] - connect \D_D \opcode_in [15:0] - connect \D_BF \opcode_in [25:23] - connect \A_XO \opcode_in [5:1] - connect \A_RT \opcode_in [25:21] - connect \A_Rc \opcode_in [0] - connect \A_RB \opcode_in [15:11] - connect \A_RA \opcode_in [20:16] - connect \A_FRT \opcode_in [25:21] - connect \A_FRC \opcode_in [10:6] - connect \A_FRB \opcode_in [15:11] - connect \A_FRA \opcode_in [20:16] - connect \A_BC \opcode_in [10:6] - connect \XL_XO \opcode_in [10:1] - connect \XL_S \opcode_in [11] - connect \XL_OC \opcode_in [25:11] - connect \XL_LK \opcode_in [0] - connect \XL_BT \opcode_in [25:21] - connect \XL_BO_1 \opcode_in [25:21] - connect \XL_BO \opcode_in [25:21] - connect \XL_BI \opcode_in [20:16] - connect \XL_BH \opcode_in [12:11] - connect \XL_BFA \opcode_in [20:18] - connect \XL_BF \opcode_in [25:23] - connect \XL_BB \opcode_in [15:11] - connect \XL_BA \opcode_in [20:16] - connect \XX4_XO \opcode_in [5:4] - connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX4_T \opcode_in [25:21] - connect \XX4_TX \opcode_in [0] - connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } - connect \XX4_C \opcode_in [10:6] - connect \XX4_CX \opcode_in [3] - connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX4_B \opcode_in [15:11] - connect \XX4_BX \opcode_in [1] - connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX4_A \opcode_in [20:16] - connect \XX4_AX \opcode_in [2] - connect \XX3_XO_2 \opcode_in [9:1] - connect \XX3_XO_1 \opcode_in [10:3] - connect \XX3_XO \opcode_in [10:7] - connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX3_T \opcode_in [25:21] - connect \XX3_TX \opcode_in [0] - connect \XX3_SHW \opcode_in [9:8] - connect \XX3_Rc \opcode_in [10] - connect \XX3_DM \opcode_in [9:8] - connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX3_B \opcode_in [15:11] - connect \XX3_BX \opcode_in [1] - connect \XX3_BF \opcode_in [25:23] - connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX3_A \opcode_in [20:16] - connect \XX3_AX \opcode_in [2] - connect \I_LK \opcode_in [0] - connect \I_LI \opcode_in [25:2] - connect \I_AA \opcode_in [1] - connect \B_LK \opcode_in [0] - connect \B_BO \opcode_in [25:21] - connect \B_BI \opcode_in [20:16] - connect \B_BD \opcode_in [15:2] - connect \B_AA \opcode_in [1] - connect \X_XO_1 \opcode_in [8:1] - connect \X_XO \opcode_in [10:1] - connect \X_WC \opcode_in [22:21] - connect \X_W \opcode_in [16] - connect \X_VRT \opcode_in [25:21] - connect \X_VRS \opcode_in [25:21] - connect \X_UIM \opcode_in [20:16] - connect \X_U \opcode_in [15:12] - connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \X_TX \opcode_in [0] - connect \X_TO \opcode_in [25:21] - connect \X_TH \opcode_in [25:21] - connect \X_TBR \opcode_in [20:11] - connect \X_T \opcode_in [25:21] - connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } - connect \X_SX \opcode_in [0] - connect \X_SR \opcode_in [19:16] - connect \X_SP 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_RT - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 output 35 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 output 33 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 output 34 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire input 1 \bigendian - attribute \src "issuer_ls180.v:54939.7-54939.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 input 36 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" - cell $mux $ternary$issuer_ls180.v:55946$3395 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $ternary$issuer_ls180.v:55946$3395_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:55947.17-55963.4" - cell \LOGICAL_dec31 \LOGICAL_dec31 - connect \LOGICAL_dec31_cr_in \LOGICAL_dec31_LOGICAL_dec31_cr_in - connect \LOGICAL_dec31_cr_out \LOGICAL_dec31_LOGICAL_dec31_cr_out - connect \LOGICAL_dec31_cry_in \LOGICAL_dec31_LOGICAL_dec31_cry_in - connect \LOGICAL_dec31_cry_out \LOGICAL_dec31_LOGICAL_dec31_cry_out - connect \LOGICAL_dec31_function_unit \LOGICAL_dec31_LOGICAL_dec31_function_unit - connect \LOGICAL_dec31_in1_sel \LOGICAL_dec31_LOGICAL_dec31_in1_sel - connect \LOGICAL_dec31_in2_sel \LOGICAL_dec31_LOGICAL_dec31_in2_sel - connect \LOGICAL_dec31_internal_op \LOGICAL_dec31_LOGICAL_dec31_internal_op - connect \LOGICAL_dec31_inv_a \LOGICAL_dec31_LOGICAL_dec31_inv_a - connect \LOGICAL_dec31_inv_out \LOGICAL_dec31_LOGICAL_dec31_inv_out - connect \LOGICAL_dec31_is_32b \LOGICAL_dec31_LOGICAL_dec31_is_32b - connect \LOGICAL_dec31_ldst_len \LOGICAL_dec31_LOGICAL_dec31_ldst_len - connect \LOGICAL_dec31_rc_sel \LOGICAL_dec31_LOGICAL_dec31_rc_sel - connect \LOGICAL_dec31_sgn \LOGICAL_dec31_LOGICAL_dec31_sgn - connect \opcode_in \LOGICAL_dec31_opcode_in - end - attribute \src "issuer_ls180.v:54939.7-54939.20" - process $proc$issuer_ls180.v:54939$3410 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:55964.3-55991.6" - process $proc$issuer_ls180.v:55964$3396 - assign { } { } - assign { } { } - assign $0\LOGICAL_cry_in[1:0] $1\LOGICAL_cry_in[1:0] - attribute \src "issuer_ls180.v:55965.5-55965.29" - switch \initial - attribute \src "issuer_ls180.v:55965.9-55965.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_cry_in[1:0] \LOGICAL_dec31_LOGICAL_dec31_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_cry_in[1:0] 2'00 - case - assign $1\LOGICAL_cry_in[1:0] 2'00 - end - sync always - update \LOGICAL_cry_in $0\LOGICAL_cry_in[1:0] - end - attribute \src "issuer_ls180.v:55992.3-56019.6" - process $proc$issuer_ls180.v:55992$3397 - assign { } { } - assign { } { } - assign $0\LOGICAL_inv_a[0:0] $1\LOGICAL_inv_a[0:0] - attribute \src "issuer_ls180.v:55993.5-55993.29" - switch \initial - attribute \src "issuer_ls180.v:55993.9-55993.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_inv_a[0:0] \LOGICAL_dec31_LOGICAL_dec31_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_inv_a[0:0] 1'0 - case - assign $1\LOGICAL_inv_a[0:0] 1'0 - end - sync always - update \LOGICAL_inv_a $0\LOGICAL_inv_a[0:0] - end - attribute \src "issuer_ls180.v:56020.3-56047.6" - process $proc$issuer_ls180.v:56020$3398 - assign { } { } - assign { } { } - assign $0\LOGICAL_inv_out[0:0] $1\LOGICAL_inv_out[0:0] - attribute \src "issuer_ls180.v:56021.5-56021.29" - switch \initial - attribute \src "issuer_ls180.v:56021.9-56021.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_inv_out[0:0] \LOGICAL_dec31_LOGICAL_dec31_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_inv_out[0:0] 1'0 - case - assign $1\LOGICAL_inv_out[0:0] 1'0 - end - sync always - update \LOGICAL_inv_out $0\LOGICAL_inv_out[0:0] - end - attribute \src "issuer_ls180.v:56048.3-56075.6" - process $proc$issuer_ls180.v:56048$3399 - assign { } { } - assign { } { } - assign $0\LOGICAL_cry_out[0:0] $1\LOGICAL_cry_out[0:0] - attribute \src "issuer_ls180.v:56049.5-56049.29" - switch \initial - attribute \src "issuer_ls180.v:56049.9-56049.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_cry_out[0:0] \LOGICAL_dec31_LOGICAL_dec31_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_cry_out[0:0] 1'0 - case - assign $1\LOGICAL_cry_out[0:0] 1'0 - end - sync always - update \LOGICAL_cry_out $0\LOGICAL_cry_out[0:0] - end - attribute \src "issuer_ls180.v:56076.3-56103.6" - process $proc$issuer_ls180.v:56076$3400 - assign { } { } - assign { } { } - assign $0\LOGICAL_is_32b[0:0] $1\LOGICAL_is_32b[0:0] - attribute \src "issuer_ls180.v:56077.5-56077.29" - switch \initial - attribute \src "issuer_ls180.v:56077.9-56077.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_is_32b[0:0] \LOGICAL_dec31_LOGICAL_dec31_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_is_32b[0:0] 1'0 - case - assign $1\LOGICAL_is_32b[0:0] 1'0 - end - sync always - update \LOGICAL_is_32b $0\LOGICAL_is_32b[0:0] - end - attribute \src "issuer_ls180.v:56104.3-56131.6" - process $proc$issuer_ls180.v:56104$3401 - assign { } { } - assign { } { } - assign $0\LOGICAL_sgn[0:0] $1\LOGICAL_sgn[0:0] - attribute \src "issuer_ls180.v:56105.5-56105.29" - switch \initial - attribute \src "issuer_ls180.v:56105.9-56105.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_sgn[0:0] \LOGICAL_dec31_LOGICAL_dec31_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_sgn[0:0] 1'0 - case - assign $1\LOGICAL_sgn[0:0] 1'0 - end - sync always - update \LOGICAL_sgn $0\LOGICAL_sgn[0:0] - end - attribute \src "issuer_ls180.v:56132.3-56159.6" - process $proc$issuer_ls180.v:56132$3402 - assign { } { } - assign { } { } - assign $0\LOGICAL_function_unit[11:0] $1\LOGICAL_function_unit[11:0] - attribute \src "issuer_ls180.v:56133.5-56133.29" - switch \initial - attribute \src "issuer_ls180.v:56133.9-56133.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_function_unit[11:0] \LOGICAL_dec31_LOGICAL_dec31_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_function_unit[11:0] 12'000000010000 - case - assign $1\LOGICAL_function_unit[11:0] 12'000000000000 - end - sync always - update \LOGICAL_function_unit $0\LOGICAL_function_unit[11:0] - end - attribute \src "issuer_ls180.v:56160.3-56187.6" - process $proc$issuer_ls180.v:56160$3403 - assign { } { } - assign { } { } - assign $0\LOGICAL_internal_op[6:0] $1\LOGICAL_internal_op[6:0] - attribute \src "issuer_ls180.v:56161.5-56161.29" - switch \initial - attribute \src "issuer_ls180.v:56161.9-56161.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_internal_op[6:0] \LOGICAL_dec31_LOGICAL_dec31_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_internal_op[6:0] 7'0000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_internal_op[6:0] 7'0000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_internal_op[6:0] 7'0110101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_internal_op[6:0] 7'0110101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_internal_op[6:0] 7'1000011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_internal_op[6:0] 7'1000011 - case - assign $1\LOGICAL_internal_op[6:0] 7'0000000 - end - sync always - update \LOGICAL_internal_op $0\LOGICAL_internal_op[6:0] - end - attribute \src "issuer_ls180.v:56188.3-56215.6" - process $proc$issuer_ls180.v:56188$3404 - assign { } { } - assign { } { } - assign $0\LOGICAL_in1_sel[2:0] $1\LOGICAL_in1_sel[2:0] - attribute \src "issuer_ls180.v:56189.5-56189.29" - switch \initial - attribute \src "issuer_ls180.v:56189.9-56189.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_in1_sel[2:0] \LOGICAL_dec31_LOGICAL_dec31_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_in1_sel[2:0] 3'100 - case - assign $1\LOGICAL_in1_sel[2:0] 3'000 - end - sync always - update \LOGICAL_in1_sel $0\LOGICAL_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:56216.3-56243.6" - process $proc$issuer_ls180.v:56216$3405 - assign { } { } - assign { } { } - assign $0\LOGICAL_in2_sel[3:0] $1\LOGICAL_in2_sel[3:0] - attribute \src "issuer_ls180.v:56217.5-56217.29" - switch \initial - attribute \src "issuer_ls180.v:56217.9-56217.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_in2_sel[3:0] \LOGICAL_dec31_LOGICAL_dec31_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_in2_sel[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_in2_sel[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_in2_sel[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_in2_sel[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_in2_sel[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_in2_sel[3:0] 4'0100 - case - assign $1\LOGICAL_in2_sel[3:0] 4'0000 - end - sync always - update \LOGICAL_in2_sel $0\LOGICAL_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:56244.3-56271.6" - process $proc$issuer_ls180.v:56244$3406 - assign { } { } - assign { } { } - assign $0\LOGICAL_cr_in[2:0] $1\LOGICAL_cr_in[2:0] - attribute \src "issuer_ls180.v:56245.5-56245.29" - switch \initial - attribute \src "issuer_ls180.v:56245.9-56245.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_cr_in[2:0] \LOGICAL_dec31_LOGICAL_dec31_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_cr_in[2:0] 3'000 - case - assign $1\LOGICAL_cr_in[2:0] 3'000 - end - sync always - update \LOGICAL_cr_in $0\LOGICAL_cr_in[2:0] - end - attribute \src "issuer_ls180.v:56272.3-56299.6" - process $proc$issuer_ls180.v:56272$3407 - assign { } { } - assign { } { } - assign $0\LOGICAL_cr_out[2:0] $1\LOGICAL_cr_out[2:0] - attribute \src "issuer_ls180.v:56273.5-56273.29" - switch \initial - attribute \src "issuer_ls180.v:56273.9-56273.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_cr_out[2:0] \LOGICAL_dec31_LOGICAL_dec31_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_cr_out[2:0] 3'000 - case - assign $1\LOGICAL_cr_out[2:0] 3'000 - end - sync always - update \LOGICAL_cr_out $0\LOGICAL_cr_out[2:0] - end - attribute \src "issuer_ls180.v:56300.3-56327.6" - process $proc$issuer_ls180.v:56300$3408 - assign { } { } - assign { } { } - assign $0\LOGICAL_ldst_len[3:0] $1\LOGICAL_ldst_len[3:0] - attribute \src "issuer_ls180.v:56301.5-56301.29" - switch \initial - attribute \src "issuer_ls180.v:56301.9-56301.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_ldst_len[3:0] \LOGICAL_dec31_LOGICAL_dec31_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_ldst_len[3:0] 4'0000 - case - assign $1\LOGICAL_ldst_len[3:0] 4'0000 - end - sync always - update \LOGICAL_ldst_len $0\LOGICAL_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:56328.3-56355.6" - process $proc$issuer_ls180.v:56328$3409 - assign { } { } - assign { } { } - assign $0\LOGICAL_rc_sel[1:0] $1\LOGICAL_rc_sel[1:0] - attribute \src "issuer_ls180.v:56329.5-56329.29" - switch \initial - attribute \src "issuer_ls180.v:56329.9-56329.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_rc_sel[1:0] \LOGICAL_dec31_LOGICAL_dec31_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_rc_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_rc_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_rc_sel[1:0] 2'00 - case - assign $1\LOGICAL_rc_sel[1:0] 2'00 - end - sync always - update \LOGICAL_rc_sel $0\LOGICAL_rc_sel[1:0] - end - connect \$1 $ternary$issuer_ls180.v:55946$3395_Y - connect \VC_XO \opcode_in [9:0] - connect \VC_VRT \opcode_in [25:21] - connect \VC_VRB \opcode_in [15:11] - connect \VC_VRA \opcode_in [20:16] - connect \VC_Rc \opcode_in [10] - connect \XS_XO \opcode_in [10:2] - connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } - connect \XS_RS \opcode_in [25:21] - connect \XS_Rc \opcode_in [0] - connect \XS_RA \opcode_in [20:16] - connect \VA_XO \opcode_in [5:0] - connect \VA_VRT \opcode_in [25:21] - connect \VA_VRC \opcode_in [10:6] - connect \VA_VRB \opcode_in [15:11] - connect \VA_VRA \opcode_in [20:16] - connect \VA_SHB \opcode_in [9:6] - connect \VA_RT \opcode_in [25:21] - connect \VA_RC \opcode_in [10:6] - connect \VA_RB \opcode_in [15:11] - connect \VA_RA \opcode_in [20:16] - connect \TX_XO \opcode_in [6:1] - connect \TX_XBI \opcode_in [10:7] - connect \TX_UI \opcode_in [15:11] - connect \TX_RA \opcode_in [20:16] - connect \DQE_XO \opcode_in [1:0] - connect \DQE_RT \opcode_in [25:21] - connect \DQE_RA \opcode_in [20:16] - connect \XO_XO \opcode_in [9:1] - connect \XO_RT \opcode_in [25:21] - connect \XO_Rc \opcode_in [0] - connect \XO_RB \opcode_in [15:11] - connect \XO_RA \opcode_in [20:16] - connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] - connect \MD_XO \opcode_in [4:2] - connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } - connect \MD_RS \opcode_in [25:21] - connect \MD_Rc \opcode_in [0] - connect \MD_RA \opcode_in [20:16] - connect \MD_me \opcode_in [10:5] - connect \MD_mb \opcode_in [10:5] - connect \M_SH \opcode_in [15:11] - connect \M_RS \opcode_in [25:21] - connect \M_Rc \opcode_in [0] - connect \M_RB \opcode_in [15:11] - connect \M_RA \opcode_in [20:16] - connect \M_ME \opcode_in [5:1] - connect \M_MB \opcode_in [10:6] - connect \SC_XO_1 \opcode_in [1:0] - connect \SC_XO \opcode_in [1] - connect \SC_LEV \opcode_in [11:5] - connect \MDS_XO \opcode_in [4:1] - connect \MDS_XBI_1 \opcode_in [10:7] - connect \MDS_XBI \opcode_in [10:7] - connect \MDS_RS \opcode_in [25:21] - connect \MDS_Rc \opcode_in [0] - connect \MDS_RB \opcode_in [15:11] - connect \MDS_RA \opcode_in [20:16] - connect \MDS_me \opcode_in [10:5] - connect \MDS_mb \opcode_in [10:5] - connect \MDS_IS \opcode_in [25:21] - connect \MDS_IB \opcode_in [15:11] - connect \Z23_XO \opcode_in [8:1] - connect \Z23_TE \opcode_in [20:16] - connect \Z23_RMC \opcode_in [10:9] - connect \Z23_Rc \opcode_in [0] - connect \Z23_R \opcode_in [16] - connect \Z23_FRTp \opcode_in [25:21] - connect \Z23_FRT \opcode_in [25:21] - connect \Z23_FRBp \opcode_in [15:11] - connect \Z23_FRB \opcode_in [15:11] - connect \Z23_FRAp \opcode_in [20:16] - connect \Z23_FRA \opcode_in [20:16] - connect \XFL_XO \opcode_in [10:1] - connect \XFL_W \opcode_in [16] - connect \XFL_Rc \opcode_in [0] - connect \XFL_L \opcode_in [25] - connect \XFL_FRB \opcode_in [15:11] - connect \XFL_FLM \opcode_in [24:17] - connect \VX_XO_1 \opcode_in [10:0] - connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } - connect \VX_VRT \opcode_in [25:21] - connect \VX_VRB \opcode_in [15:11] - connect \VX_VRA \opcode_in [20:16] - connect \VX_UIM_3 \opcode_in [17:16] - connect \VX_UIM_2 \opcode_in [18:16] - connect \VX_UIM_1 \opcode_in [19:16] - connect \VX_UIM \opcode_in [20:16] - connect \VX_SIM \opcode_in [20:16] - connect \VX_RT \opcode_in [25:21] - connect \VX_RA \opcode_in [20:16] - connect \VX_PS \opcode_in [9] - connect \VX_EO \opcode_in [20:16] - connect \DS_XO \opcode_in [1:0] - connect \DS_VRT \opcode_in [25:21] - connect \DS_VRS \opcode_in [25:21] - connect \DS_RT \opcode_in [25:21] - connect \DS_RSp \opcode_in [25:21] - connect \DS_RS \opcode_in [25:21] - connect \DS_RA \opcode_in [20:16] - connect \DS_FRTp \opcode_in [25:21] - connect \DS_FRSp \opcode_in [25:21] - connect \DS_DS \opcode_in [15:2] - connect \DQ_XO \opcode_in [2:0] - connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_T \opcode_in [25:21] - connect \DQ_TX \opcode_in [3] - connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_S \opcode_in [25:21] - connect \DQ_SX \opcode_in [3] - connect \DQ_RTp \opcode_in [25:21] - connect \DQ_RA \opcode_in [20:16] - connect \DQ_PT \opcode_in [3:0] - connect \DQ_DQ \opcode_in [15:4] - connect \DX_XO \opcode_in [5:1] - connect \DX_RT \opcode_in [25:21] - connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } - connect \DX_d2 \opcode_in [0] - connect \DX_d1 \opcode_in [20:16] - connect \DX_d0 \opcode_in [15:6] - connect \XFX_XO \opcode_in [10:1] - connect \XFX_SPR \opcode_in [20:11] - connect \XFX_RT \opcode_in [25:21] - connect \XFX_RS \opcode_in [25:21] - connect \XFX_FXM \opcode_in [19:12] - connect \XFX_DUIS \opcode_in [20:11] - connect \XFX_DUI \opcode_in [25:21] - connect \XFX_BHRBE \opcode_in [20:11] - connect \EVS_BFA \opcode_in [2:0] - connect \Z22_XO \opcode_in [9:1] - connect \Z22_SH \opcode_in [15:10] - connect \Z22_Rc \opcode_in [0] - connect \Z22_FRTp \opcode_in [25:21] - connect \Z22_FRT \opcode_in [25:21] - connect \Z22_FRAp \opcode_in [20:16] - connect \Z22_FRA \opcode_in [20:16] - connect \Z22_DGM \opcode_in [15:10] - connect \Z22_DCM \opcode_in [15:10] - connect \Z22_BF \opcode_in [25:23] - connect \XX2_XO_1 \opcode_in [10:2] - connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } - connect \XX2_UIM_1 \opcode_in [17:16] - connect \XX2_UIM \opcode_in [19:16] - connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX2_T \opcode_in [25:21] - connect \XX2_TX \opcode_in [0] - connect \XX2_RT \opcode_in [25:21] - connect \XX2_EO \opcode_in [20:16] - connect \XX2_DCMX \opcode_in [22:16] - connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } - connect \XX2_dx \opcode_in [20:16] - connect \XX2_dm \opcode_in [2] - connect \XX2_dc \opcode_in [6] - connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX2_B \opcode_in [15:11] - connect \XX2_BX \opcode_in [1] - connect \XX2_BF \opcode_in [25:23] - connect \D_UI \opcode_in [15:0] - connect \D_TO \opcode_in [25:21] - connect \D_SI \opcode_in [15:0] - connect \D_RT \opcode_in [25:21] - connect \D_RS \opcode_in [25:21] - connect \D_RA \opcode_in [20:16] - connect \D_L \opcode_in [21] - connect \D_FRT \opcode_in [25:21] - connect \D_FRS \opcode_in [25:21] - connect \D_D \opcode_in [15:0] - connect \D_BF \opcode_in [25:23] - connect \A_XO \opcode_in [5:1] - connect \A_RT \opcode_in [25:21] - connect \A_Rc \opcode_in [0] - connect \A_RB \opcode_in [15:11] - connect \A_RA \opcode_in [20:16] - connect \A_FRT \opcode_in [25:21] - connect \A_FRC \opcode_in [10:6] - connect \A_FRB \opcode_in [15:11] - connect \A_FRA \opcode_in [20:16] - connect \A_BC \opcode_in [10:6] - connect \XL_XO \opcode_in [10:1] - connect \XL_S \opcode_in [11] - connect \XL_OC \opcode_in [25:11] - connect \XL_LK \opcode_in [0] - connect \XL_BT \opcode_in [25:21] - connect \XL_BO_1 \opcode_in [25:21] - connect \XL_BO \opcode_in [25:21] - connect \XL_BI \opcode_in [20:16] - connect \XL_BH \opcode_in [12:11] - connect \XL_BFA \opcode_in [20:18] - connect \XL_BF \opcode_in [25:23] - connect \XL_BB \opcode_in [15:11] - connect \XL_BA \opcode_in [20:16] - connect \XX4_XO \opcode_in [5:4] - connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX4_T \opcode_in [25:21] - connect \XX4_TX \opcode_in [0] - connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } - connect \XX4_C \opcode_in [10:6] - connect \XX4_CX \opcode_in [3] - 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attribute \src "issuer_ls180.v:56690.7-56690.20" - process $proc$issuer_ls180.v:56690$3418 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:57605.3-57614.6" - process $proc$issuer_ls180.v:57605$3412 - assign { } { } - assign { } { } - assign $0\SPR_function_unit[11:0] $1\SPR_function_unit[11:0] - attribute \src "issuer_ls180.v:57606.5-57606.29" - switch \initial - attribute \src "issuer_ls180.v:57606.9-57606.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SPR_function_unit[11:0] \SPR_dec31_SPR_dec31_function_unit - case - assign $1\SPR_function_unit[11:0] 12'000000000000 - end - sync always - update \SPR_function_unit $0\SPR_function_unit[11:0] - end - attribute \src "issuer_ls180.v:57615.3-57624.6" - process $proc$issuer_ls180.v:57615$3413 - assign { } { } - assign { } { } - assign $0\SPR_internal_op[6:0] $1\SPR_internal_op[6:0] - attribute \src "issuer_ls180.v:57616.5-57616.29" - switch \initial - attribute \src "issuer_ls180.v:57616.9-57616.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SPR_internal_op[6:0] \SPR_dec31_SPR_dec31_internal_op - case - assign $1\SPR_internal_op[6:0] 7'0000000 - end - sync always - update \SPR_internal_op $0\SPR_internal_op[6:0] - end - attribute \src "issuer_ls180.v:57625.3-57634.6" - process $proc$issuer_ls180.v:57625$3414 - assign { } { } - assign { } { } - assign $0\SPR_cr_in[2:0] $1\SPR_cr_in[2:0] - attribute \src "issuer_ls180.v:57626.5-57626.29" - switch \initial - attribute \src "issuer_ls180.v:57626.9-57626.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SPR_cr_in[2:0] \SPR_dec31_SPR_dec31_cr_in - case - assign $1\SPR_cr_in[2:0] 3'000 - end - sync always - update \SPR_cr_in $0\SPR_cr_in[2:0] - end - attribute \src "issuer_ls180.v:57635.3-57644.6" - process $proc$issuer_ls180.v:57635$3415 - assign { } { } - assign { } { } - assign $0\SPR_cr_out[2:0] $1\SPR_cr_out[2:0] - attribute \src "issuer_ls180.v:57636.5-57636.29" - switch \initial - attribute \src "issuer_ls180.v:57636.9-57636.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SPR_cr_out[2:0] \SPR_dec31_SPR_dec31_cr_out - case - assign $1\SPR_cr_out[2:0] 3'000 - end - sync always - update \SPR_cr_out $0\SPR_cr_out[2:0] - end - attribute \src "issuer_ls180.v:57645.3-57654.6" - process $proc$issuer_ls180.v:57645$3416 - assign { } { } - assign { } { } - assign $0\SPR_rc_sel[1:0] $1\SPR_rc_sel[1:0] - attribute \src "issuer_ls180.v:57646.5-57646.29" - switch \initial - attribute \src "issuer_ls180.v:57646.9-57646.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SPR_rc_sel[1:0] \SPR_dec31_SPR_dec31_rc_sel - case - assign $1\SPR_rc_sel[1:0] 2'00 - end - sync always - update \SPR_rc_sel $0\SPR_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:57655.3-57664.6" - process $proc$issuer_ls180.v:57655$3417 - assign { } { } - assign { } { } - assign $0\SPR_is_32b[0:0] $1\SPR_is_32b[0:0] - attribute \src "issuer_ls180.v:57656.5-57656.29" - switch \initial - attribute \src "issuer_ls180.v:57656.9-57656.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SPR_is_32b[0:0] \SPR_dec31_SPR_dec31_is_32b - case - assign $1\SPR_is_32b[0:0] 1'0 - end - sync always - update \SPR_is_32b $0\SPR_is_32b[0:0] - end - connect \$1 $ternary$issuer_ls180.v:57595$3411_Y - connect \VC_XO \opcode_in [9:0] - connect \VC_VRT \opcode_in [25:21] - connect \VC_VRB \opcode_in [15:11] - connect \VC_VRA \opcode_in [20:16] - connect \VC_Rc \opcode_in [10] - connect \XS_XO \opcode_in [10:2] - connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } - connect \XS_RS \opcode_in [25:21] - connect \XS_Rc \opcode_in [0] - connect \XS_RA \opcode_in [20:16] - connect \VA_XO \opcode_in [5:0] - connect \VA_VRT \opcode_in [25:21] - connect \VA_VRC \opcode_in [10:6] - connect \VA_VRB \opcode_in [15:11] - connect \VA_VRA \opcode_in [20:16] - connect \VA_SHB \opcode_in [9:6] - connect \VA_RT \opcode_in [25:21] - connect \VA_RC \opcode_in [10:6] - connect \VA_RB \opcode_in [15:11] - connect \VA_RA \opcode_in [20:16] - connect \TX_XO \opcode_in [6:1] - connect \TX_XBI \opcode_in [10:7] - connect \TX_UI \opcode_in [15:11] - connect \TX_RA \opcode_in [20:16] - connect \DQE_XO \opcode_in [1:0] - connect \DQE_RT \opcode_in [25:21] - connect \DQE_RA \opcode_in [20:16] - connect \XO_XO \opcode_in [9:1] - connect \XO_RT \opcode_in [25:21] - connect \XO_Rc \opcode_in [0] - connect \XO_RB \opcode_in [15:11] - connect \XO_RA \opcode_in [20:16] - connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] - connect \MD_XO \opcode_in [4:2] - connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } - connect \MD_RS \opcode_in [25:21] - connect \MD_Rc \opcode_in [0] - connect \MD_RA \opcode_in [20:16] - connect \MD_me \opcode_in [10:5] - connect \MD_mb \opcode_in [10:5] - connect \M_SH \opcode_in [15:11] - connect \M_RS \opcode_in [25:21] - connect \M_Rc \opcode_in [0] - connect \M_RB \opcode_in [15:11] - connect \M_RA \opcode_in [20:16] - connect \M_ME \opcode_in [5:1] - connect \M_MB \opcode_in [10:6] - connect \SC_XO_1 \opcode_in [1:0] - connect \SC_XO \opcode_in [1] - connect \SC_LEV \opcode_in [11:5] - connect \MDS_XO \opcode_in [4:1] - connect \MDS_XBI_1 \opcode_in [10:7] - connect \MDS_XBI \opcode_in [10:7] - connect \MDS_RS \opcode_in [25:21] - connect \MDS_Rc \opcode_in [0] - connect \MDS_RB \opcode_in [15:11] - connect \MDS_RA \opcode_in [20:16] - connect \MDS_me \opcode_in [10:5] - connect \MDS_mb \opcode_in [10:5] - connect \MDS_IS \opcode_in [25:21] - connect \MDS_IB \opcode_in [15:11] - connect \Z23_XO \opcode_in [8:1] - connect \Z23_TE \opcode_in [20:16] - connect \Z23_RMC \opcode_in [10:9] - connect \Z23_Rc \opcode_in [0] - connect \Z23_R \opcode_in [16] - connect \Z23_FRTp \opcode_in [25:21] - connect \Z23_FRT \opcode_in [25:21] - connect \Z23_FRBp \opcode_in [15:11] - connect \Z23_FRB \opcode_in [15:11] - connect \Z23_FRAp \opcode_in [20:16] - connect \Z23_FRA \opcode_in [20:16] - connect \XFL_XO \opcode_in [10:1] - connect \XFL_W \opcode_in [16] - connect \XFL_Rc \opcode_in [0] - connect \XFL_L \opcode_in [25] - connect \XFL_FRB \opcode_in [15:11] - connect \XFL_FLM \opcode_in [24:17] - connect \VX_XO_1 \opcode_in [10:0] - connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } - connect \VX_VRT \opcode_in [25:21] - connect \VX_VRB \opcode_in [15:11] - connect \VX_VRA \opcode_in [20:16] - connect \VX_UIM_3 \opcode_in [17:16] - connect \VX_UIM_2 \opcode_in [18:16] - connect \VX_UIM_1 \opcode_in [19:16] - connect \VX_UIM \opcode_in [20:16] - connect \VX_SIM \opcode_in [20:16] - connect \VX_RT \opcode_in [25:21] - connect \VX_RA \opcode_in [20:16] - connect \VX_PS \opcode_in [9] - connect \VX_EO \opcode_in [20:16] - connect \DS_XO \opcode_in [1:0] - connect \DS_VRT \opcode_in [25:21] - connect \DS_VRS \opcode_in [25:21] - connect \DS_RT \opcode_in [25:21] - connect \DS_RSp \opcode_in [25:21] - connect \DS_RS \opcode_in [25:21] - connect \DS_RA \opcode_in [20:16] - connect \DS_FRTp \opcode_in [25:21] - connect \DS_FRSp \opcode_in [25:21] - connect \DS_DS \opcode_in [15:2] - connect \DQ_XO \opcode_in [2:0] - connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_T \opcode_in [25:21] - connect \DQ_TX \opcode_in [3] - connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_S \opcode_in [25:21] - connect \DQ_SX \opcode_in [3] - connect \DQ_RTp \opcode_in [25:21] - connect \DQ_RA \opcode_in [20:16] - connect \DQ_PT \opcode_in [3:0] - connect \DQ_DQ \opcode_in [15:4] - connect \DX_XO \opcode_in [5:1] - connect \DX_RT \opcode_in [25:21] - connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } - connect \DX_d2 \opcode_in [0] - connect \DX_d1 \opcode_in [20:16] - connect \DX_d0 \opcode_in [15:6] - connect \XFX_XO \opcode_in [10:1] - connect \XFX_SPR \opcode_in [20:11] - connect \XFX_RT \opcode_in [25:21] - connect \XFX_RS \opcode_in [25:21] - connect \XFX_FXM \opcode_in [19:12] - connect \XFX_DUIS \opcode_in [20:11] - connect \XFX_DUI \opcode_in [25:21] - connect \XFX_BHRBE \opcode_in [20:11] - connect \EVS_BFA \opcode_in [2:0] - connect \Z22_XO \opcode_in [9:1] - connect \Z22_SH \opcode_in [15:10] - connect \Z22_Rc \opcode_in [0] - connect \Z22_FRTp \opcode_in [25:21] - connect \Z22_FRT \opcode_in [25:21] - connect \Z22_FRAp \opcode_in [20:16] - connect \Z22_FRA \opcode_in [20:16] - connect \Z22_DGM \opcode_in [15:10] - connect \Z22_DCM \opcode_in [15:10] - connect \Z22_BF \opcode_in [25:23] - connect \XX2_XO_1 \opcode_in [10:2] - connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } - connect \XX2_UIM_1 \opcode_in [17:16] - connect \XX2_UIM \opcode_in [19:16] - connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX2_T \opcode_in [25:21] - connect \XX2_TX \opcode_in [0] - connect \XX2_RT \opcode_in [25:21] - connect \XX2_EO \opcode_in [20:16] - connect \XX2_DCMX \opcode_in [22:16] - connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } - connect \XX2_dx \opcode_in [20:16] - connect \XX2_dm \opcode_in [2] - connect \XX2_dc \opcode_in [6] - connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX2_B \opcode_in [15:11] - connect \XX2_BX \opcode_in [1] - connect \XX2_BF \opcode_in [25:23] - connect \D_UI \opcode_in [15:0] - connect \D_TO \opcode_in [25:21] - connect \D_SI \opcode_in [15:0] - connect \D_RT \opcode_in [25:21] - connect \D_RS \opcode_in [25:21] - connect \D_RA \opcode_in [20:16] - connect \D_L \opcode_in [21] - connect \D_FRT \opcode_in [25:21] - connect \D_FRS \opcode_in [25:21] - connect \D_D \opcode_in [15:0] - connect \D_BF \opcode_in [25:23] - connect \A_XO \opcode_in [5:1] - connect \A_RT \opcode_in [25:21] - connect \A_Rc \opcode_in [0] - connect \A_RB \opcode_in [15:11] - connect \A_RA \opcode_in [20:16] - connect \A_FRT \opcode_in [25:21] - connect \A_FRC \opcode_in [10:6] - connect \A_FRB \opcode_in [15:11] - connect \A_FRA \opcode_in [20:16] - connect \A_BC \opcode_in [10:6] - connect \XL_XO \opcode_in [10:1] - connect \XL_S \opcode_in [11] - connect \XL_OC \opcode_in [25:11] - connect \XL_LK \opcode_in [0] - connect \XL_BT \opcode_in [25:21] - connect \XL_BO_1 \opcode_in [25:21] - connect \XL_BO \opcode_in [25:21] - connect \XL_BI \opcode_in [20:16] - connect \XL_BH \opcode_in [12:11] - connect \XL_BFA \opcode_in [20:18] - connect \XL_BF \opcode_in [25:23] - connect \XL_BB \opcode_in [15:11] - connect \XL_BA \opcode_in [20:16] - connect \XX4_XO \opcode_in [5:4] - connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX4_T \opcode_in [25:21] - connect \XX4_TX \opcode_in [0] - connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } - connect \XX4_C \opcode_in [10:6] - connect \XX4_CX \opcode_in [3] - connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX4_B \opcode_in [15:11] - connect \XX4_BX \opcode_in [1] - connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX4_A \opcode_in [20:16] - connect \XX4_AX \opcode_in [2] - connect \XX3_XO_2 \opcode_in [9:1] - connect \XX3_XO_1 \opcode_in [10:3] - connect \XX3_XO \opcode_in [10:7] - connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX3_T \opcode_in [25:21] - connect \XX3_TX \opcode_in [0] - connect \XX3_SHW \opcode_in [9:8] - connect \XX3_Rc \opcode_in [10] - connect \XX3_DM \opcode_in [9:8] - connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX3_B \opcode_in [15:11] - connect \XX3_BX \opcode_in [1] - connect \XX3_BF \opcode_in [25:23] - connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX3_A \opcode_in [20:16] - connect \XX3_AX \opcode_in [2] - connect \I_LK \opcode_in [0] - connect \I_LI \opcode_in [25:2] - connect \I_AA \opcode_in [1] - connect \B_LK \opcode_in [0] - connect \B_BO \opcode_in [25:21] - connect \B_BI \opcode_in [20:16] - connect \B_BD \opcode_in [15:2] - connect \B_AA \opcode_in [1] - connect \X_XO_1 \opcode_in [8:1] - connect \X_XO \opcode_in [10:1] - connect \X_WC \opcode_in [22:21] - connect \X_W \opcode_in [16] - connect \X_VRT \opcode_in [25:21] - connect \X_VRS \opcode_in [25:21] - connect \X_UIM \opcode_in [20:16] - connect \X_U \opcode_in [15:12] - connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \X_TX \opcode_in [0] - connect \X_TO \opcode_in [25:21] - connect \X_TH \opcode_in [25:21] - connect \X_TBR \opcode_in [20:11] - connect \X_T \opcode_in [25:21] - connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } - connect \X_SX \opcode_in [0] - connect \X_SR \opcode_in [19:16] - connect \X_SP \opcode_in [20:19] - connect \X_SI \opcode_in [15:11] - connect \X_SH \opcode_in [15:11] - connect \X_S \opcode_in [25:21] - connect \X_RTp \opcode_in [25:21] - connect \X_RT \opcode_in [25:21] - connect \X_RSp \opcode_in [25:21] - connect \X_RS \opcode_in [25:21] - connect \X_RO \opcode_in [0] - connect \X_RM \opcode_in [12:11] - connect \X_RIC \opcode_in [19:18] - connect \X_Rc \opcode_in [0] - connect \X_RB \opcode_in [15:11] - connect \X_RA \opcode_in [20:16] - connect \X_R_1 \opcode_in [16] - connect \X_R \opcode_in [21] - connect \X_PRS \opcode_in [17] - connect \X_NB \opcode_in [15:11] - connect \X_MO \opcode_in [25:21] - connect \X_L3 \opcode_in [17:16] - connect \X_L1 \opcode_in [16] - connect \X_L \opcode_in [21] - connect \X_L2 \opcode_in [22:21] - connect \X_IMM8 \opcode_in [18:11] - connect \X_IH \opcode_in [23:21] - connect \X_FRTp \opcode_in [25:21] - connect \X_FRT \opcode_in [25:21] - connect \X_FRSp \opcode_in [25:21] - connect \X_FRS \opcode_in [25:21] - connect \X_FRBp \opcode_in [15:11] - connect \X_FRB \opcode_in [15:11] - connect \X_FRAp \opcode_in [20:16] - connect \X_FRA \opcode_in [20:16] - connect \X_FC \opcode_in [15:11] - connect \X_EX \opcode_in [0] - connect \X_EO_1 \opcode_in [20:16] - connect \X_EO \opcode_in [20:19] - connect \X_E_1 \opcode_in [19:16] - connect \X_E \opcode_in [15] - connect \X_DRM \opcode_in [13:11] - connect \X_DCMX \opcode_in [22:16] - connect \X_CT \opcode_in [24:21] - connect \X_BO \opcode_in [25:21] - connect \X_BFA \opcode_in [20:18] - connect \X_BF \opcode_in [25:23] - connect \X_A \opcode_in [25] - connect \SPR_SPR \opcode_in [20:11] - connect \SPR_MB \opcode_in [10:6] - connect \SPR_ME \opcode_in [5:1] - connect \SPR_SH \opcode_in [15:11] - connect \SPR_BC \opcode_in [10:6] - connect \SPR_TO \opcode_in [25:21] - connect \SPR_DS \opcode_in [15:2] - connect \SPR_D \opcode_in [15:0] - connect \SPR_BH \opcode_in [12:11] - connect \SPR_BI \opcode_in [20:16] - connect \SPR_BO \opcode_in [25:21] - connect \SPR_FXM \opcode_in [19:12] - connect \SPR_BT \opcode_in [25:21] - connect \SPR_BA \opcode_in [20:16] - connect \SPR_BB \opcode_in [15:11] - connect \SPR_CR \opcode_in [10:1] - connect \SPR_BF \opcode_in [25:23] - connect \SPR_BD \opcode_in [15:2] - connect \SPR_OE \opcode_in [10] - connect \SPR_Rc \opcode_in [0] - connect \SPR_AA \opcode_in [1] - connect \SPR_LK \opcode_in [0] - connect \SPR_LI \opcode_in [25:2] - connect \SPR_ME32 \opcode_in [5:1] - connect \SPR_MB32 \opcode_in [10:6] - connect \SPR_sh { \opcode_in [1] \opcode_in [15:11] } - connect \SPR_SH32 \opcode_in [15:11] - connect \SPR_L \opcode_in [21] - connect \SPR_UI \opcode_in [15:0] - connect \SPR_SI \opcode_in [15:0] - connect \SPR_RB \opcode_in [15:11] - connect \SPR_RA \opcode_in [20:16] - connect \SPR_RT \opcode_in [25:21] - connect \SPR_RS \opcode_in [25:21] - connect \opcode_in \$1 - connect \SPR_dec31_opcode_in \opcode_in - connect \opcode_switch \opcode_in [31:26] -end -attribute \src "issuer_ls180.v:57998.1-59493.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec" -attribute \generator "nMigen" -module \dec$168 - attribute \src "issuer_ls180.v:59124.3-59133.6" - wire width 3 $0\DIV_cr_in[2:0] - attribute \src "issuer_ls180.v:59134.3-59143.6" - wire width 3 $0\DIV_cr_out[2:0] - attribute \src "issuer_ls180.v:59024.3-59033.6" - wire width 2 $0\DIV_cry_in[1:0] - attribute \src "issuer_ls180.v:59054.3-59063.6" - wire $0\DIV_cry_out[0:0] - attribute \src "issuer_ls180.v:59084.3-59093.6" - wire width 12 $0\DIV_function_unit[11:0] - attribute \src "issuer_ls180.v:59104.3-59113.6" - wire width 3 $0\DIV_in1_sel[2:0] - attribute \src "issuer_ls180.v:59114.3-59123.6" - wire width 4 $0\DIV_in2_sel[3:0] - attribute \src "issuer_ls180.v:59094.3-59103.6" - wire width 7 $0\DIV_internal_op[6:0] - attribute \src "issuer_ls180.v:59034.3-59043.6" - wire $0\DIV_inv_a[0:0] - attribute \src "issuer_ls180.v:59044.3-59053.6" - wire $0\DIV_inv_out[0:0] - attribute \src "issuer_ls180.v:59064.3-59073.6" - wire $0\DIV_is_32b[0:0] - attribute \src "issuer_ls180.v:59144.3-59153.6" - wire width 4 $0\DIV_ldst_len[3:0] - attribute \src "issuer_ls180.v:59154.3-59163.6" - wire width 2 $0\DIV_rc_sel[1:0] - attribute \src "issuer_ls180.v:59074.3-59083.6" - wire $0\DIV_sgn[0:0] - attribute \src "issuer_ls180.v:57999.7-57999.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:59124.3-59133.6" - wire width 3 $1\DIV_cr_in[2:0] - attribute \src "issuer_ls180.v:59134.3-59143.6" - wire width 3 $1\DIV_cr_out[2:0] - attribute \src "issuer_ls180.v:59024.3-59033.6" - wire width 2 $1\DIV_cry_in[1:0] - attribute \src "issuer_ls180.v:59054.3-59063.6" - wire $1\DIV_cry_out[0:0] - attribute \src "issuer_ls180.v:59084.3-59093.6" - wire width 12 $1\DIV_function_unit[11:0] - attribute \src "issuer_ls180.v:59104.3-59113.6" - wire width 3 $1\DIV_in1_sel[2:0] - attribute \src "issuer_ls180.v:59114.3-59123.6" - wire width 4 $1\DIV_in2_sel[3:0] - attribute \src "issuer_ls180.v:59094.3-59103.6" - wire width 7 $1\DIV_internal_op[6:0] - attribute \src "issuer_ls180.v:59034.3-59043.6" - wire $1\DIV_inv_a[0:0] - attribute \src "issuer_ls180.v:59044.3-59053.6" - wire $1\DIV_inv_out[0:0] - attribute \src "issuer_ls180.v:59064.3-59073.6" - wire $1\DIV_is_32b[0:0] - attribute \src "issuer_ls180.v:59144.3-59153.6" - wire width 4 $1\DIV_ldst_len[3:0] - attribute \src "issuer_ls180.v:59154.3-59163.6" - wire width 2 $1\DIV_rc_sel[1:0] - attribute \src "issuer_ls180.v:59074.3-59083.6" - wire $1\DIV_sgn[0:0] - attribute \src "issuer_ls180.v:59006.17-59006.211" - wire width 32 $ternary$issuer_ls180.v:59006$3419_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" - wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \DIV_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 27 \DIV_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 26 \DIV_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 32 \DIV_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 output 25 \DIV_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 3 \DIV_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 2 \DIV_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 30 \DIV_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \DIV_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 28 \DIV_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 10 \DIV_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 \DIV_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 output 31 \DIV_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 output 29 \DIV_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \DIV_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 24 output 22 \DIV_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \DIV_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \DIV_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \DIV_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \DIV_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \DIV_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire output 24 \DIV_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 17 \DIV_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \DIV_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \DIV_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \DIV_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire output 23 \DIV_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \DIV_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 20 \DIV_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 output 18 \DIV_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 10 \DIV_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \DIV_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 output 19 \DIV_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 4 \DIV_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \DIV_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \DIV_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 14 \DIV_cry_out - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \DIV_dec31_DIV_dec31_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \DIV_dec31_DIV_dec31_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \DIV_dec31_DIV_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \DIV_dec31_DIV_dec31_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \DIV_dec31_DIV_dec31_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \DIV_dec31_DIV_dec31_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \DIV_dec31_DIV_dec31_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \DIV_dec31_DIV_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \DIV_dec31_DIV_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \DIV_dec31_DIV_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \DIV_dec31_DIV_dec31_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \DIV_dec31_DIV_dec31_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \DIV_dec31_DIV_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \DIV_dec31_DIV_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \DIV_dec31_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 7 \DIV_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 8 \DIV_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 9 \DIV_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 6 \DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 11 \DIV_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 12 \DIV_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \DIV_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 10 \DIV_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 3 \DIV_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \DIV_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 6 output 21 \DIV_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 output 35 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_T - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire input 1 \bigendian - attribute \src "issuer_ls180.v:57999.7-57999.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 input 36 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" - cell $mux $ternary$issuer_ls180.v:59006$3419 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $ternary$issuer_ls180.v:59006$3419_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:59007.13-59023.4" - cell \DIV_dec31 \DIV_dec31 - connect \DIV_dec31_cr_in \DIV_dec31_DIV_dec31_cr_in - connect \DIV_dec31_cr_out \DIV_dec31_DIV_dec31_cr_out - connect \DIV_dec31_cry_in \DIV_dec31_DIV_dec31_cry_in - connect \DIV_dec31_cry_out \DIV_dec31_DIV_dec31_cry_out - connect \DIV_dec31_function_unit \DIV_dec31_DIV_dec31_function_unit - connect \DIV_dec31_in1_sel \DIV_dec31_DIV_dec31_in1_sel - connect \DIV_dec31_in2_sel \DIV_dec31_DIV_dec31_in2_sel - connect \DIV_dec31_internal_op \DIV_dec31_DIV_dec31_internal_op - connect \DIV_dec31_inv_a \DIV_dec31_DIV_dec31_inv_a - connect \DIV_dec31_inv_out \DIV_dec31_DIV_dec31_inv_out - connect \DIV_dec31_is_32b \DIV_dec31_DIV_dec31_is_32b - connect \DIV_dec31_ldst_len \DIV_dec31_DIV_dec31_ldst_len - connect \DIV_dec31_rc_sel \DIV_dec31_DIV_dec31_rc_sel - connect \DIV_dec31_sgn \DIV_dec31_DIV_dec31_sgn - connect \opcode_in \DIV_dec31_opcode_in - end - attribute \src "issuer_ls180.v:57999.7-57999.20" - process $proc$issuer_ls180.v:57999$3434 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:59024.3-59033.6" - process $proc$issuer_ls180.v:59024$3420 - assign { } { } - assign { } { } - assign $0\DIV_cry_in[1:0] $1\DIV_cry_in[1:0] - attribute \src "issuer_ls180.v:59025.5-59025.29" - switch \initial - attribute \src "issuer_ls180.v:59025.9-59025.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_cry_in[1:0] \DIV_dec31_DIV_dec31_cry_in - case - assign $1\DIV_cry_in[1:0] 2'00 - end - sync always - update \DIV_cry_in $0\DIV_cry_in[1:0] - end - attribute \src "issuer_ls180.v:59034.3-59043.6" - process $proc$issuer_ls180.v:59034$3421 - assign { } { } - assign { } { } - assign $0\DIV_inv_a[0:0] $1\DIV_inv_a[0:0] - attribute \src "issuer_ls180.v:59035.5-59035.29" - switch \initial - attribute \src "issuer_ls180.v:59035.9-59035.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_inv_a[0:0] \DIV_dec31_DIV_dec31_inv_a - case - assign $1\DIV_inv_a[0:0] 1'0 - end - sync always - update \DIV_inv_a $0\DIV_inv_a[0:0] - end - attribute \src "issuer_ls180.v:59044.3-59053.6" - process $proc$issuer_ls180.v:59044$3422 - assign { } { } - assign { } { } - assign $0\DIV_inv_out[0:0] $1\DIV_inv_out[0:0] - attribute \src "issuer_ls180.v:59045.5-59045.29" - switch \initial - attribute \src "issuer_ls180.v:59045.9-59045.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_inv_out[0:0] \DIV_dec31_DIV_dec31_inv_out - case - assign $1\DIV_inv_out[0:0] 1'0 - end - sync always - update \DIV_inv_out $0\DIV_inv_out[0:0] - end - attribute \src "issuer_ls180.v:59054.3-59063.6" - process $proc$issuer_ls180.v:59054$3423 - assign { } { } - assign { } { } - assign $0\DIV_cry_out[0:0] $1\DIV_cry_out[0:0] - attribute \src "issuer_ls180.v:59055.5-59055.29" - switch \initial - attribute \src "issuer_ls180.v:59055.9-59055.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_cry_out[0:0] \DIV_dec31_DIV_dec31_cry_out - case - assign $1\DIV_cry_out[0:0] 1'0 - end - sync always - update \DIV_cry_out $0\DIV_cry_out[0:0] - end - attribute \src "issuer_ls180.v:59064.3-59073.6" - process $proc$issuer_ls180.v:59064$3424 - assign { } { } - assign { } { } - assign $0\DIV_is_32b[0:0] $1\DIV_is_32b[0:0] - attribute \src "issuer_ls180.v:59065.5-59065.29" - switch \initial - attribute \src "issuer_ls180.v:59065.9-59065.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_is_32b[0:0] \DIV_dec31_DIV_dec31_is_32b - case - assign $1\DIV_is_32b[0:0] 1'0 - end - sync always - update \DIV_is_32b $0\DIV_is_32b[0:0] - end - attribute \src "issuer_ls180.v:59074.3-59083.6" - process $proc$issuer_ls180.v:59074$3425 - assign { } { } - assign { } { } - assign $0\DIV_sgn[0:0] $1\DIV_sgn[0:0] - attribute \src "issuer_ls180.v:59075.5-59075.29" - switch \initial - attribute \src "issuer_ls180.v:59075.9-59075.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_sgn[0:0] \DIV_dec31_DIV_dec31_sgn - case - assign $1\DIV_sgn[0:0] 1'0 - end - sync always - update \DIV_sgn $0\DIV_sgn[0:0] - end - attribute \src "issuer_ls180.v:59084.3-59093.6" - process $proc$issuer_ls180.v:59084$3426 - assign { } { } - assign { } { } - assign $0\DIV_function_unit[11:0] $1\DIV_function_unit[11:0] - attribute \src "issuer_ls180.v:59085.5-59085.29" - switch \initial - attribute \src "issuer_ls180.v:59085.9-59085.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_function_unit[11:0] \DIV_dec31_DIV_dec31_function_unit - case - assign $1\DIV_function_unit[11:0] 12'000000000000 - end - sync always - update \DIV_function_unit $0\DIV_function_unit[11:0] - end - attribute \src "issuer_ls180.v:59094.3-59103.6" - process $proc$issuer_ls180.v:59094$3427 - assign { } { } - assign { } { } - assign $0\DIV_internal_op[6:0] $1\DIV_internal_op[6:0] - attribute \src "issuer_ls180.v:59095.5-59095.29" - switch \initial - attribute \src "issuer_ls180.v:59095.9-59095.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_internal_op[6:0] \DIV_dec31_DIV_dec31_internal_op - case - assign $1\DIV_internal_op[6:0] 7'0000000 - end - sync always - update \DIV_internal_op $0\DIV_internal_op[6:0] - end - attribute \src "issuer_ls180.v:59104.3-59113.6" - process $proc$issuer_ls180.v:59104$3428 - assign { } { } - assign { } { } - assign $0\DIV_in1_sel[2:0] $1\DIV_in1_sel[2:0] - attribute \src "issuer_ls180.v:59105.5-59105.29" - switch \initial - attribute \src "issuer_ls180.v:59105.9-59105.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_in1_sel[2:0] \DIV_dec31_DIV_dec31_in1_sel - case - assign $1\DIV_in1_sel[2:0] 3'000 - end - sync always - update \DIV_in1_sel $0\DIV_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:59114.3-59123.6" - process $proc$issuer_ls180.v:59114$3429 - assign { } { } - assign { } { } - assign $0\DIV_in2_sel[3:0] $1\DIV_in2_sel[3:0] - attribute \src "issuer_ls180.v:59115.5-59115.29" - switch \initial - attribute \src "issuer_ls180.v:59115.9-59115.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_in2_sel[3:0] \DIV_dec31_DIV_dec31_in2_sel - case - assign $1\DIV_in2_sel[3:0] 4'0000 - end - sync always - update \DIV_in2_sel $0\DIV_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:59124.3-59133.6" - process $proc$issuer_ls180.v:59124$3430 - assign { } { } - assign { } { } - assign $0\DIV_cr_in[2:0] $1\DIV_cr_in[2:0] - attribute \src "issuer_ls180.v:59125.5-59125.29" - switch \initial - attribute \src "issuer_ls180.v:59125.9-59125.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_cr_in[2:0] \DIV_dec31_DIV_dec31_cr_in - case - assign $1\DIV_cr_in[2:0] 3'000 - end - sync always - update \DIV_cr_in $0\DIV_cr_in[2:0] - end - attribute \src "issuer_ls180.v:59134.3-59143.6" - process $proc$issuer_ls180.v:59134$3431 - assign { } { } - assign { } { } - assign $0\DIV_cr_out[2:0] $1\DIV_cr_out[2:0] - attribute \src "issuer_ls180.v:59135.5-59135.29" - switch \initial - attribute \src "issuer_ls180.v:59135.9-59135.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_cr_out[2:0] \DIV_dec31_DIV_dec31_cr_out - case - assign $1\DIV_cr_out[2:0] 3'000 - end - sync always - update \DIV_cr_out $0\DIV_cr_out[2:0] - end - attribute \src "issuer_ls180.v:59144.3-59153.6" - process $proc$issuer_ls180.v:59144$3432 - assign { } { } - assign { } { } - assign $0\DIV_ldst_len[3:0] $1\DIV_ldst_len[3:0] - attribute \src "issuer_ls180.v:59145.5-59145.29" - switch \initial - attribute \src "issuer_ls180.v:59145.9-59145.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_ldst_len[3:0] \DIV_dec31_DIV_dec31_ldst_len - case - assign $1\DIV_ldst_len[3:0] 4'0000 - end - sync always - update \DIV_ldst_len $0\DIV_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:59154.3-59163.6" - process $proc$issuer_ls180.v:59154$3433 - assign { } { } - assign { } { } - assign $0\DIV_rc_sel[1:0] $1\DIV_rc_sel[1:0] - attribute \src "issuer_ls180.v:59155.5-59155.29" - switch \initial - attribute \src "issuer_ls180.v:59155.9-59155.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_rc_sel[1:0] \DIV_dec31_DIV_dec31_rc_sel - case - assign $1\DIV_rc_sel[1:0] 2'00 - end - sync always - update \DIV_rc_sel $0\DIV_rc_sel[1:0] - end - connect \$1 $ternary$issuer_ls180.v:59006$3419_Y - connect \VC_XO \opcode_in [9:0] - connect \VC_VRT \opcode_in [25:21] - connect \VC_VRB \opcode_in [15:11] - connect \VC_VRA \opcode_in [20:16] - connect \VC_Rc \opcode_in [10] - connect \XS_XO \opcode_in [10:2] - connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } - connect \XS_RS \opcode_in [25:21] - connect \XS_Rc \opcode_in [0] - connect \XS_RA \opcode_in [20:16] - connect \VA_XO \opcode_in [5:0] - connect \VA_VRT \opcode_in [25:21] - connect \VA_VRC \opcode_in [10:6] - connect \VA_VRB \opcode_in [15:11] - connect \VA_VRA \opcode_in [20:16] - connect \VA_SHB \opcode_in [9:6] - connect \VA_RT \opcode_in [25:21] - connect \VA_RC \opcode_in [10:6] - connect \VA_RB \opcode_in [15:11] - connect \VA_RA \opcode_in [20:16] - connect \TX_XO \opcode_in [6:1] - connect \TX_XBI \opcode_in [10:7] - connect \TX_UI \opcode_in [15:11] - connect \TX_RA \opcode_in [20:16] - connect \DQE_XO \opcode_in [1:0] - connect \DQE_RT \opcode_in [25:21] - connect \DQE_RA \opcode_in [20:16] - connect \XO_XO \opcode_in [9:1] - connect \XO_RT \opcode_in [25:21] - connect \XO_Rc \opcode_in [0] - connect \XO_RB \opcode_in [15:11] - connect \XO_RA \opcode_in [20:16] - connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] - connect \MD_XO \opcode_in [4:2] - connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } - connect \MD_RS \opcode_in [25:21] - connect \MD_Rc \opcode_in [0] - connect \MD_RA \opcode_in [20:16] - connect \MD_me \opcode_in [10:5] - connect \MD_mb \opcode_in [10:5] - connect \M_SH \opcode_in [15:11] - connect \M_RS \opcode_in [25:21] - connect \M_Rc \opcode_in [0] - connect \M_RB \opcode_in [15:11] - connect \M_RA \opcode_in [20:16] - connect \M_ME \opcode_in [5:1] - connect \M_MB \opcode_in [10:6] - connect \SC_XO_1 \opcode_in [1:0] - connect \SC_XO \opcode_in [1] - connect \SC_LEV \opcode_in [11:5] - connect \MDS_XO \opcode_in [4:1] - connect \MDS_XBI_1 \opcode_in [10:7] - connect \MDS_XBI \opcode_in [10:7] - connect \MDS_RS \opcode_in [25:21] - connect \MDS_Rc \opcode_in [0] - connect \MDS_RB \opcode_in [15:11] - connect \MDS_RA \opcode_in [20:16] - connect \MDS_me \opcode_in [10:5] - connect \MDS_mb \opcode_in [10:5] - connect \MDS_IS \opcode_in [25:21] - connect \MDS_IB \opcode_in [15:11] - connect \Z23_XO \opcode_in [8:1] - connect \Z23_TE \opcode_in [20:16] - connect \Z23_RMC \opcode_in [10:9] - connect \Z23_Rc \opcode_in [0] - connect \Z23_R \opcode_in [16] - connect \Z23_FRTp \opcode_in [25:21] - connect \Z23_FRT \opcode_in [25:21] - connect \Z23_FRBp \opcode_in [15:11] - connect \Z23_FRB \opcode_in [15:11] - connect \Z23_FRAp \opcode_in [20:16] - connect \Z23_FRA \opcode_in [20:16] - connect \XFL_XO \opcode_in [10:1] - connect \XFL_W \opcode_in [16] - connect \XFL_Rc \opcode_in [0] - connect \XFL_L \opcode_in [25] - connect \XFL_FRB \opcode_in [15:11] - connect \XFL_FLM \opcode_in [24:17] - connect \VX_XO_1 \opcode_in [10:0] - connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } - connect \VX_VRT \opcode_in [25:21] - connect \VX_VRB \opcode_in [15:11] - connect \VX_VRA \opcode_in [20:16] - connect \VX_UIM_3 \opcode_in [17:16] - connect \VX_UIM_2 \opcode_in [18:16] - connect \VX_UIM_1 \opcode_in [19:16] - connect \VX_UIM \opcode_in [20:16] - connect \VX_SIM \opcode_in [20:16] - connect \VX_RT \opcode_in [25:21] - connect \VX_RA \opcode_in [20:16] - connect \VX_PS \opcode_in [9] - connect \VX_EO \opcode_in [20:16] - connect \DS_XO \opcode_in [1:0] - connect \DS_VRT \opcode_in [25:21] - connect \DS_VRS \opcode_in [25:21] - connect \DS_RT \opcode_in [25:21] - connect \DS_RSp \opcode_in [25:21] - connect \DS_RS \opcode_in [25:21] - connect \DS_RA \opcode_in [20:16] - connect \DS_FRTp \opcode_in [25:21] - connect \DS_FRSp \opcode_in [25:21] - connect \DS_DS \opcode_in [15:2] - connect \DQ_XO \opcode_in [2:0] - connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_T \opcode_in [25:21] - connect \DQ_TX \opcode_in [3] - connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_S \opcode_in [25:21] - connect \DQ_SX \opcode_in [3] - connect \DQ_RTp \opcode_in [25:21] - connect \DQ_RA \opcode_in [20:16] - connect \DQ_PT \opcode_in [3:0] - connect \DQ_DQ \opcode_in [15:4] - connect \DX_XO \opcode_in [5:1] - connect \DX_RT \opcode_in [25:21] - connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } - connect \DX_d2 \opcode_in [0] - connect \DX_d1 \opcode_in [20:16] - connect \DX_d0 \opcode_in [15:6] - connect \XFX_XO \opcode_in [10:1] - connect \XFX_SPR \opcode_in [20:11] - connect \XFX_RT \opcode_in [25:21] - connect \XFX_RS \opcode_in [25:21] - connect \XFX_FXM \opcode_in [19:12] - connect \XFX_DUIS \opcode_in [20:11] - connect \XFX_DUI \opcode_in [25:21] - connect \XFX_BHRBE \opcode_in [20:11] - connect \EVS_BFA \opcode_in [2:0] - connect \Z22_XO \opcode_in [9:1] - connect \Z22_SH \opcode_in [15:10] - connect \Z22_Rc \opcode_in [0] - connect \Z22_FRTp \opcode_in [25:21] - connect \Z22_FRT \opcode_in [25:21] - connect \Z22_FRAp \opcode_in [20:16] - connect \Z22_FRA \opcode_in [20:16] - connect \Z22_DGM \opcode_in [15:10] - connect \Z22_DCM \opcode_in [15:10] - connect \Z22_BF \opcode_in [25:23] - connect \XX2_XO_1 \opcode_in [10:2] - connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } - connect \XX2_UIM_1 \opcode_in [17:16] - connect \XX2_UIM \opcode_in [19:16] - connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX2_T \opcode_in [25:21] - connect \XX2_TX \opcode_in [0] - connect \XX2_RT \opcode_in [25:21] - connect \XX2_EO \opcode_in [20:16] - connect \XX2_DCMX \opcode_in [22:16] - connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } - connect \XX2_dx \opcode_in [20:16] - connect \XX2_dm \opcode_in [2] - connect \XX2_dc \opcode_in [6] - connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX2_B \opcode_in [15:11] - connect \XX2_BX \opcode_in [1] - connect \XX2_BF \opcode_in [25:23] - connect \D_UI \opcode_in [15:0] - connect \D_TO \opcode_in [25:21] - connect \D_SI \opcode_in [15:0] - connect \D_RT \opcode_in [25:21] - connect \D_RS \opcode_in [25:21] - connect \D_RA \opcode_in [20:16] - connect \D_L \opcode_in [21] - connect \D_FRT \opcode_in [25:21] - connect \D_FRS \opcode_in [25:21] - connect \D_D \opcode_in [15:0] - connect \D_BF \opcode_in [25:23] - connect \A_XO \opcode_in [5:1] - connect \A_RT \opcode_in [25:21] - connect \A_Rc \opcode_in [0] - connect \A_RB \opcode_in [15:11] - connect \A_RA \opcode_in [20:16] - connect \A_FRT \opcode_in [25:21] - connect \A_FRC \opcode_in [10:6] - connect \A_FRB \opcode_in [15:11] - connect \A_FRA \opcode_in [20:16] - connect \A_BC \opcode_in [10:6] - connect \XL_XO \opcode_in [10:1] - connect \XL_S \opcode_in [11] - connect \XL_OC \opcode_in [25:11] - connect \XL_LK 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \MUL_cr_out - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \MUL_dec31_MUL_dec31_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \MUL_dec31_MUL_dec31_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \MUL_dec31_MUL_dec31_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \MUL_dec31_MUL_dec31_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \MUL_dec31_MUL_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \MUL_dec31_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 7 \MUL_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 8 \MUL_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 6 \MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 9 \MUL_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 3 \MUL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \MUL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 6 output 14 \MUL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 output 28 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 output 26 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 output 27 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire input 1 \bigendian - attribute \src "issuer_ls180.v:59498.7-59498.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 input 29 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" - cell $mux $ternary$issuer_ls180.v:60443$3435 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $ternary$issuer_ls180.v:60443$3435_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:60444.13-60454.4" - cell \MUL_dec31 \MUL_dec31 - connect \MUL_dec31_cr_in \MUL_dec31_MUL_dec31_cr_in - connect \MUL_dec31_cr_out \MUL_dec31_MUL_dec31_cr_out - connect \MUL_dec31_function_unit \MUL_dec31_MUL_dec31_function_unit - connect \MUL_dec31_in2_sel \MUL_dec31_MUL_dec31_in2_sel - connect \MUL_dec31_internal_op \MUL_dec31_MUL_dec31_internal_op - connect \MUL_dec31_is_32b \MUL_dec31_MUL_dec31_is_32b - connect \MUL_dec31_rc_sel \MUL_dec31_MUL_dec31_rc_sel - connect \MUL_dec31_sgn \MUL_dec31_MUL_dec31_sgn - connect \opcode_in \MUL_dec31_opcode_in - end - attribute \src "issuer_ls180.v:59498.7-59498.20" - process $proc$issuer_ls180.v:59498$3444 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:60455.3-60467.6" - process $proc$issuer_ls180.v:60455$3436 - assign { } { } - assign { } { } - assign $0\MUL_function_unit[11:0] $1\MUL_function_unit[11:0] - attribute \src "issuer_ls180.v:60456.5-60456.29" - switch \initial - attribute \src "issuer_ls180.v:60456.9-60456.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\MUL_function_unit[11:0] \MUL_dec31_MUL_dec31_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\MUL_function_unit[11:0] 12'000100000000 - case - assign $1\MUL_function_unit[11:0] 12'000000000000 - end - sync always - update \MUL_function_unit $0\MUL_function_unit[11:0] - end - attribute \src "issuer_ls180.v:60468.3-60480.6" - process $proc$issuer_ls180.v:60468$3437 - assign { } { } - assign { } { } - assign $0\MUL_internal_op[6:0] $1\MUL_internal_op[6:0] - attribute \src "issuer_ls180.v:60469.5-60469.29" - switch \initial - attribute \src "issuer_ls180.v:60469.9-60469.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\MUL_internal_op[6:0] \MUL_dec31_MUL_dec31_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\MUL_internal_op[6:0] 7'0110010 - case - assign $1\MUL_internal_op[6:0] 7'0000000 - end - sync always - update \MUL_internal_op $0\MUL_internal_op[6:0] - end - attribute \src "issuer_ls180.v:60481.3-60493.6" - process $proc$issuer_ls180.v:60481$3438 - assign { } { } - assign { } { } - assign $0\MUL_in2_sel[3:0] $1\MUL_in2_sel[3:0] - attribute \src "issuer_ls180.v:60482.5-60482.29" - switch \initial - attribute \src "issuer_ls180.v:60482.9-60482.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\MUL_in2_sel[3:0] \MUL_dec31_MUL_dec31_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\MUL_in2_sel[3:0] 4'0011 - case - assign $1\MUL_in2_sel[3:0] 4'0000 - end - sync always - update \MUL_in2_sel $0\MUL_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:60494.3-60506.6" - process $proc$issuer_ls180.v:60494$3439 - assign { } { } - assign { } { } - assign $0\MUL_cr_in[2:0] $1\MUL_cr_in[2:0] - attribute \src "issuer_ls180.v:60495.5-60495.29" - switch \initial - attribute \src "issuer_ls180.v:60495.9-60495.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\MUL_cr_in[2:0] \MUL_dec31_MUL_dec31_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\MUL_cr_in[2:0] 3'000 - case - assign $1\MUL_cr_in[2:0] 3'000 - end - sync always - update \MUL_cr_in $0\MUL_cr_in[2:0] - end - attribute \src "issuer_ls180.v:60507.3-60519.6" - process $proc$issuer_ls180.v:60507$3440 - assign { } { } - assign { } { } - assign $0\MUL_cr_out[2:0] $1\MUL_cr_out[2:0] - attribute \src "issuer_ls180.v:60508.5-60508.29" - switch \initial - attribute \src "issuer_ls180.v:60508.9-60508.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\MUL_cr_out[2:0] \MUL_dec31_MUL_dec31_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\MUL_cr_out[2:0] 3'001 - case - assign $1\MUL_cr_out[2:0] 3'000 - end - sync always - update \MUL_cr_out $0\MUL_cr_out[2:0] - end - attribute \src "issuer_ls180.v:60520.3-60532.6" - process $proc$issuer_ls180.v:60520$3441 - assign { } { } - assign { } { } - assign $0\MUL_rc_sel[1:0] $1\MUL_rc_sel[1:0] - attribute \src "issuer_ls180.v:60521.5-60521.29" - switch \initial - attribute \src "issuer_ls180.v:60521.9-60521.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\MUL_rc_sel[1:0] \MUL_dec31_MUL_dec31_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\MUL_rc_sel[1:0] 2'00 - case - assign $1\MUL_rc_sel[1:0] 2'00 - end - sync always - update \MUL_rc_sel $0\MUL_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:60533.3-60545.6" - process $proc$issuer_ls180.v:60533$3442 - assign { } { } - assign { } { } - assign $0\MUL_is_32b[0:0] $1\MUL_is_32b[0:0] - attribute \src "issuer_ls180.v:60534.5-60534.29" - switch \initial - attribute \src "issuer_ls180.v:60534.9-60534.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\MUL_is_32b[0:0] \MUL_dec31_MUL_dec31_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\MUL_is_32b[0:0] 1'0 - case - assign $1\MUL_is_32b[0:0] 1'0 - end - sync always - update \MUL_is_32b $0\MUL_is_32b[0:0] - end - attribute \src "issuer_ls180.v:60546.3-60558.6" - process $proc$issuer_ls180.v:60546$3443 - assign { } { } - assign { } { } - assign $0\MUL_sgn[0:0] $1\MUL_sgn[0:0] - attribute \src "issuer_ls180.v:60547.5-60547.29" - switch \initial - attribute \src "issuer_ls180.v:60547.9-60547.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\MUL_sgn[0:0] \MUL_dec31_MUL_dec31_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\MUL_sgn[0:0] 1'1 - case - assign $1\MUL_sgn[0:0] 1'0 - end - sync always - update \MUL_sgn $0\MUL_sgn[0:0] - end - connect \$1 $ternary$issuer_ls180.v:60443$3435_Y - connect \VC_XO \opcode_in [9:0] - connect \VC_VRT \opcode_in [25:21] - connect \VC_VRB \opcode_in [15:11] - connect \VC_VRA \opcode_in [20:16] - connect \VC_Rc \opcode_in [10] - connect \XS_XO \opcode_in [10:2] - connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } - connect \XS_RS \opcode_in [25:21] - connect \XS_Rc \opcode_in [0] - connect \XS_RA \opcode_in [20:16] - connect \VA_XO \opcode_in [5:0] - connect \VA_VRT \opcode_in [25:21] - connect \VA_VRC \opcode_in [10:6] - connect \VA_VRB \opcode_in [15:11] - connect \VA_VRA \opcode_in [20:16] - connect \VA_SHB \opcode_in [9:6] - connect \VA_RT \opcode_in [25:21] - connect \VA_RC \opcode_in [10:6] - connect \VA_RB \opcode_in [15:11] - connect \VA_RA \opcode_in [20:16] - connect \TX_XO \opcode_in [6:1] - connect \TX_XBI \opcode_in [10:7] - connect \TX_UI \opcode_in [15:11] - connect \TX_RA \opcode_in [20:16] - connect \DQE_XO \opcode_in [1:0] - connect \DQE_RT \opcode_in [25:21] - connect \DQE_RA \opcode_in [20:16] - connect \XO_XO \opcode_in [9:1] - connect \XO_RT \opcode_in [25:21] - connect \XO_Rc \opcode_in [0] - connect \XO_RB \opcode_in [15:11] - connect \XO_RA \opcode_in [20:16] - connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] - connect \MD_XO \opcode_in [4:2] - connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } - connect \MD_RS \opcode_in [25:21] - connect \MD_Rc \opcode_in [0] - connect \MD_RA \opcode_in [20:16] - connect \MD_me \opcode_in [10:5] - connect \MD_mb \opcode_in [10:5] - connect \M_SH \opcode_in [15:11] - connect \M_RS \opcode_in [25:21] - connect \M_Rc \opcode_in [0] - connect \M_RB \opcode_in [15:11] - connect \M_RA \opcode_in [20:16] - connect \M_ME \opcode_in [5:1] - connect \M_MB \opcode_in [10:6] - connect \SC_XO_1 \opcode_in [1:0] - connect \SC_XO \opcode_in [1] - connect \SC_LEV \opcode_in [11:5] - connect \MDS_XO \opcode_in [4:1] - connect \MDS_XBI_1 \opcode_in [10:7] - connect \MDS_XBI \opcode_in [10:7] - connect \MDS_RS \opcode_in [25:21] - connect \MDS_Rc \opcode_in [0] - connect \MDS_RB \opcode_in [15:11] - connect \MDS_RA \opcode_in [20:16] - connect \MDS_me \opcode_in [10:5] - connect \MDS_mb \opcode_in [10:5] - connect \MDS_IS \opcode_in [25:21] - connect \MDS_IB \opcode_in [15:11] - connect \Z23_XO \opcode_in [8:1] - connect \Z23_TE \opcode_in [20:16] - connect \Z23_RMC \opcode_in [10:9] - connect \Z23_Rc \opcode_in [0] - connect \Z23_R \opcode_in [16] - connect \Z23_FRTp \opcode_in [25:21] - connect \Z23_FRT \opcode_in [25:21] - connect \Z23_FRBp \opcode_in [15:11] - connect \Z23_FRB \opcode_in [15:11] - connect \Z23_FRAp \opcode_in [20:16] - connect \Z23_FRA \opcode_in [20:16] - connect \XFL_XO \opcode_in [10:1] - connect \XFL_W \opcode_in [16] - connect \XFL_Rc \opcode_in [0] - connect \XFL_L \opcode_in [25] - connect \XFL_FRB \opcode_in [15:11] - connect \XFL_FLM \opcode_in [24:17] - connect \VX_XO_1 \opcode_in [10:0] - connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } - connect \VX_VRT \opcode_in [25:21] - connect \VX_VRB \opcode_in [15:11] - connect \VX_VRA \opcode_in [20:16] - connect \VX_UIM_3 \opcode_in [17:16] - connect \VX_UIM_2 \opcode_in [18:16] - connect \VX_UIM_1 \opcode_in [19:16] - connect \VX_UIM \opcode_in [20:16] - connect \VX_SIM \opcode_in [20:16] - connect \VX_RT \opcode_in [25:21] - connect \VX_RA \opcode_in [20:16] - connect \VX_PS \opcode_in [9] - connect \VX_EO \opcode_in [20:16] - connect \DS_XO \opcode_in [1:0] - connect \DS_VRT \opcode_in [25:21] - connect \DS_VRS \opcode_in [25:21] - connect \DS_RT \opcode_in [25:21] - connect \DS_RSp \opcode_in [25:21] - connect \DS_RS \opcode_in [25:21] - connect \DS_RA \opcode_in [20:16] - connect \DS_FRTp \opcode_in [25:21] - connect \DS_FRSp \opcode_in [25:21] - connect \DS_DS \opcode_in [15:2] - connect \DQ_XO \opcode_in [2:0] - connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_T \opcode_in [25:21] - connect \DQ_TX \opcode_in [3] - connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_S \opcode_in [25:21] - connect \DQ_SX \opcode_in [3] - connect \DQ_RTp \opcode_in [25:21] - connect \DQ_RA \opcode_in [20:16] - connect \DQ_PT \opcode_in [3:0] - connect \DQ_DQ \opcode_in [15:4] - connect \DX_XO \opcode_in [5:1] - connect \DX_RT \opcode_in [25:21] - connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } - connect \DX_d2 \opcode_in [0] - connect \DX_d1 \opcode_in [20:16] - connect \DX_d0 \opcode_in [15:6] - connect \XFX_XO \opcode_in [10:1] - connect \XFX_SPR \opcode_in [20:11] - connect \XFX_RT \opcode_in [25:21] - connect \XFX_RS \opcode_in [25:21] - connect \XFX_FXM \opcode_in [19:12] - connect \XFX_DUIS \opcode_in [20:11] - connect \XFX_DUI \opcode_in [25:21] - connect \XFX_BHRBE \opcode_in [20:11] - connect \EVS_BFA \opcode_in [2:0] - connect \Z22_XO \opcode_in [9:1] - connect \Z22_SH \opcode_in [15:10] - connect \Z22_Rc \opcode_in [0] - connect \Z22_FRTp \opcode_in [25:21] - connect \Z22_FRT \opcode_in [25:21] - connect \Z22_FRAp \opcode_in [20:16] - connect \Z22_FRA \opcode_in [20:16] - connect \Z22_DGM \opcode_in [15:10] - connect \Z22_DCM \opcode_in [15:10] - connect \Z22_BF \opcode_in [25:23] - connect \XX2_XO_1 \opcode_in [10:2] - connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } - connect \XX2_UIM_1 \opcode_in [17:16] - connect \XX2_UIM \opcode_in [19:16] - connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX2_T \opcode_in [25:21] - connect \XX2_TX \opcode_in [0] - connect \XX2_RT \opcode_in [25:21] - connect \XX2_EO \opcode_in [20:16] - connect \XX2_DCMX \opcode_in [22:16] - connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } - connect \XX2_dx \opcode_in [20:16] - connect \XX2_dm \opcode_in [2] - connect \XX2_dc \opcode_in [6] - connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX2_B \opcode_in [15:11] - connect \XX2_BX \opcode_in [1] - connect \XX2_BF \opcode_in [25:23] - connect \D_UI \opcode_in [15:0] - connect \D_TO \opcode_in [25:21] - connect \D_SI \opcode_in [15:0] - connect \D_RT \opcode_in [25:21] - connect \D_RS \opcode_in [25:21] - connect \D_RA \opcode_in [20:16] - connect \D_L \opcode_in [21] - connect \D_FRT \opcode_in [25:21] - connect \D_FRS \opcode_in [25:21] - connect \D_D \opcode_in [15:0] - connect \D_BF \opcode_in [25:23] - connect \A_XO \opcode_in [5:1] - connect \A_RT \opcode_in [25:21] - connect \A_Rc \opcode_in [0] - connect \A_RB \opcode_in [15:11] - connect \A_RA \opcode_in [20:16] - connect \A_FRT \opcode_in [25:21] - connect \A_FRC \opcode_in [10:6] - connect \A_FRB \opcode_in [15:11] - connect \A_FRA \opcode_in [20:16] - connect \A_BC \opcode_in [10:6] - connect \XL_XO \opcode_in [10:1] - connect \XL_S \opcode_in [11] - connect \XL_OC \opcode_in [25:11] - connect \XL_LK \opcode_in [0] - connect \XL_BT \opcode_in [25:21] - connect \XL_BO_1 \opcode_in [25:21] - connect \XL_BO \opcode_in [25:21] - connect \XL_BI \opcode_in [20:16] - connect \XL_BH \opcode_in [12:11] - connect \XL_BFA \opcode_in [20:18] - connect \XL_BF \opcode_in [25:23] - connect \XL_BB \opcode_in [15:11] - connect \XL_BA \opcode_in [20:16] - connect \XX4_XO \opcode_in [5:4] - connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX4_T \opcode_in [25:21] - connect \XX4_TX \opcode_in [0] - connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } - connect \XX4_C \opcode_in [10:6] - connect \XX4_CX \opcode_in [3] - connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX4_B \opcode_in [15:11] - connect \XX4_BX \opcode_in [1] - connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX4_A \opcode_in [20:16] - connect \XX4_AX \opcode_in [2] - connect \XX3_XO_2 \opcode_in [9:1] - connect \XX3_XO_1 \opcode_in [10:3] - connect \XX3_XO \opcode_in [10:7] - connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX3_T \opcode_in [25:21] - connect \XX3_TX \opcode_in [0] - connect \XX3_SHW \opcode_in [9:8] - connect \XX3_Rc \opcode_in [10] - connect \XX3_DM \opcode_in [9:8] - connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX3_B \opcode_in [15:11] - connect \XX3_BX \opcode_in [1] - connect \XX3_BF \opcode_in [25:23] - connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX3_A \opcode_in [20:16] - connect \XX3_AX \opcode_in [2] - connect \I_LK \opcode_in [0] - connect \I_LI \opcode_in [25:2] - connect \I_AA \opcode_in [1] - connect \B_LK \opcode_in [0] - connect \B_BO \opcode_in [25:21] - connect \B_BI \opcode_in [20:16] - connect \B_BD \opcode_in [15:2] - connect \B_AA \opcode_in [1] - connect \X_XO_1 \opcode_in [8:1] - connect \X_XO \opcode_in [10:1] - connect \X_WC \opcode_in [22:21] - connect \X_W \opcode_in [16] - connect \X_VRT \opcode_in [25:21] - connect \X_VRS \opcode_in [25:21] - connect \X_UIM \opcode_in [20:16] - connect \X_U \opcode_in [15:12] - connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \X_TX \opcode_in [0] - connect \X_TO \opcode_in [25:21] - connect \X_TH \opcode_in [25:21] - connect \X_TBR \opcode_in [20:11] - connect \X_T \opcode_in [25:21] - connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } - connect \X_SX \opcode_in [0] - connect \X_SR \opcode_in [19:16] - connect \X_SP \opcode_in [20:19] - connect \X_SI \opcode_in [15:11] - connect \X_SH \opcode_in [15:11] - connect \X_S \opcode_in [25:21] - connect \X_RTp \opcode_in [25:21] - connect \X_RT \opcode_in [25:21] - connect \X_RSp \opcode_in [25:21] - connect \X_RS \opcode_in [25:21] - connect \X_RO \opcode_in [0] - connect \X_RM \opcode_in [12:11] - connect \X_RIC \opcode_in [19:18] - connect \X_Rc \opcode_in [0] - connect \X_RB \opcode_in [15:11] - connect \X_RA \opcode_in [20:16] - connect \X_R_1 \opcode_in [16] - connect \X_R \opcode_in [21] - connect \X_PRS \opcode_in [17] - connect \X_NB \opcode_in [15:11] - connect \X_MO \opcode_in [25:21] - connect \X_L3 \opcode_in [17:16] - connect \X_L1 \opcode_in [16] - connect \X_L \opcode_in [21] - connect \X_L2 \opcode_in [22:21] - connect \X_IMM8 \opcode_in [18:11] - connect \X_IH \opcode_in [23:21] - connect \X_FRTp \opcode_in [25:21] - connect \X_FRT \opcode_in [25:21] - connect \X_FRSp \opcode_in [25:21] - connect \X_FRS \opcode_in [25:21] - connect \X_FRBp \opcode_in [15:11] - connect \X_FRB \opcode_in [15:11] - connect \X_FRAp \opcode_in [20:16] - connect \X_FRA \opcode_in [20:16] - connect \X_FC \opcode_in [15:11] - connect \X_EX \opcode_in [0] - connect \X_EO_1 \opcode_in [20:16] - connect \X_EO \opcode_in [20:19] - connect \X_E_1 \opcode_in [19:16] - connect \X_E \opcode_in [15] - connect \X_DRM \opcode_in [13:11] - connect \X_DCMX \opcode_in [22:16] - connect \X_CT \opcode_in [24:21] - connect \X_BO \opcode_in [25:21] - connect \X_BFA \opcode_in [20:18] - connect \X_BF \opcode_in [25:23] - connect \X_A \opcode_in [25] - connect \MUL_SPR \opcode_in [20:11] - connect \MUL_MB \opcode_in [10:6] - connect \MUL_ME \opcode_in [5:1] - connect \MUL_SH \opcode_in [15:11] - connect \MUL_BC \opcode_in [10:6] - connect \MUL_TO \opcode_in [25:21] - connect \MUL_DS \opcode_in [15:2] - connect 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_RA - attribute \src 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wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \SHIFT_ROT_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 22 \SHIFT_ROT_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 21 \SHIFT_ROT_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 27 \SHIFT_ROT_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 output 20 \SHIFT_ROT_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 3 \SHIFT_ROT_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 2 \SHIFT_ROT_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 25 \SHIFT_ROT_BI - attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \SHIFT_ROT_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire output 18 \SHIFT_ROT_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \SHIFT_ROT_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 15 \SHIFT_ROT_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 output 13 \SHIFT_ROT_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 10 \SHIFT_ROT_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \SHIFT_ROT_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 output 14 \SHIFT_ROT_UI - attribute \enum_base_type "CRInSel" - attribute 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\SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \SHIFT_ROT_dec30_opcode_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - 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attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute 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attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute 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"OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 6 \SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 11 \SHIFT_ROT_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 3 \SHIFT_ROT_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 12 \SHIFT_ROT_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 6 output 16 \SHIFT_ROT_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 output 30 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 output 28 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 output 29 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire input 1 \bigendian - attribute \src "issuer_ls180.v:60893.7-60893.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 input 31 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" - cell $mux $ternary$issuer_ls180.v:62002$3445 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $ternary$issuer_ls180.v:62002$3445_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:62003.19-62015.4" - cell \SHIFT_ROT_dec30 \SHIFT_ROT_dec30 - connect \SHIFT_ROT_dec30_cr_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in - connect \SHIFT_ROT_dec30_cr_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out - connect \SHIFT_ROT_dec30_cry_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in - connect \SHIFT_ROT_dec30_cry_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out - connect \SHIFT_ROT_dec30_function_unit \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit - connect \SHIFT_ROT_dec30_in2_sel \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel - connect \SHIFT_ROT_dec30_internal_op \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op - connect \SHIFT_ROT_dec30_is_32b \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b - connect \SHIFT_ROT_dec30_rc_sel \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel - connect \SHIFT_ROT_dec30_sgn \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn - connect \opcode_in \SHIFT_ROT_dec30_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:62016.19-62028.4" - cell \SHIFT_ROT_dec31 \SHIFT_ROT_dec31 - connect \SHIFT_ROT_dec31_cr_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in - connect \SHIFT_ROT_dec31_cr_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out - connect \SHIFT_ROT_dec31_cry_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in - connect \SHIFT_ROT_dec31_cry_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out - connect \SHIFT_ROT_dec31_function_unit \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit - connect \SHIFT_ROT_dec31_in2_sel \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel - connect \SHIFT_ROT_dec31_internal_op \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op - connect \SHIFT_ROT_dec31_is_32b \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b - connect \SHIFT_ROT_dec31_rc_sel \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel - connect \SHIFT_ROT_dec31_sgn \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn - connect \opcode_in \SHIFT_ROT_dec31_opcode_in - end - attribute \src "issuer_ls180.v:60893.7-60893.20" - process $proc$issuer_ls180.v:60893$3456 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:62029.3-62050.6" - process $proc$issuer_ls180.v:62029$3446 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_cry_out[0:0] $1\SHIFT_ROT_cry_out[0:0] - attribute \src "issuer_ls180.v:62030.5-62030.29" - switch \initial - attribute \src "issuer_ls180.v:62030.9-62030.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\SHIFT_ROT_cry_out[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SHIFT_ROT_cry_out[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\SHIFT_ROT_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\SHIFT_ROT_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\SHIFT_ROT_cry_out[0:0] 1'0 - case - assign $1\SHIFT_ROT_cry_out[0:0] 1'0 - end - sync always - update \SHIFT_ROT_cry_out $0\SHIFT_ROT_cry_out[0:0] - end - attribute \src "issuer_ls180.v:62051.3-62072.6" - process $proc$issuer_ls180.v:62051$3447 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_is_32b[0:0] $1\SHIFT_ROT_is_32b[0:0] - attribute \src "issuer_ls180.v:62052.5-62052.29" - switch \initial - attribute \src "issuer_ls180.v:62052.9-62052.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\SHIFT_ROT_is_32b[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SHIFT_ROT_is_32b[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\SHIFT_ROT_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\SHIFT_ROT_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\SHIFT_ROT_is_32b[0:0] 1'1 - case - assign $1\SHIFT_ROT_is_32b[0:0] 1'0 - end - sync always - update \SHIFT_ROT_is_32b $0\SHIFT_ROT_is_32b[0:0] - end - attribute \src "issuer_ls180.v:62073.3-62094.6" - process $proc$issuer_ls180.v:62073$3448 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_sgn[0:0] $1\SHIFT_ROT_sgn[0:0] - attribute \src "issuer_ls180.v:62074.5-62074.29" - switch \initial - attribute \src "issuer_ls180.v:62074.9-62074.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\SHIFT_ROT_sgn[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SHIFT_ROT_sgn[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\SHIFT_ROT_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\SHIFT_ROT_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\SHIFT_ROT_sgn[0:0] 1'0 - case - assign $1\SHIFT_ROT_sgn[0:0] 1'0 - end - sync always - update \SHIFT_ROT_sgn $0\SHIFT_ROT_sgn[0:0] - end - attribute \src "issuer_ls180.v:62095.3-62116.6" - process $proc$issuer_ls180.v:62095$3449 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_function_unit[11:0] $1\SHIFT_ROT_function_unit[11:0] - attribute \src "issuer_ls180.v:62096.5-62096.29" - switch \initial - attribute \src "issuer_ls180.v:62096.9-62096.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\SHIFT_ROT_function_unit[11:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SHIFT_ROT_function_unit[11:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\SHIFT_ROT_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\SHIFT_ROT_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\SHIFT_ROT_function_unit[11:0] 12'000000001000 - case - assign $1\SHIFT_ROT_function_unit[11:0] 12'000000000000 - end - sync always - update \SHIFT_ROT_function_unit $0\SHIFT_ROT_function_unit[11:0] - end - attribute \src "issuer_ls180.v:62117.3-62138.6" - process $proc$issuer_ls180.v:62117$3450 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_internal_op[6:0] $1\SHIFT_ROT_internal_op[6:0] - attribute \src "issuer_ls180.v:62118.5-62118.29" - switch \initial - attribute \src "issuer_ls180.v:62118.9-62118.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\SHIFT_ROT_internal_op[6:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SHIFT_ROT_internal_op[6:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\SHIFT_ROT_internal_op[6:0] 7'0111000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\SHIFT_ROT_internal_op[6:0] 7'0111000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\SHIFT_ROT_internal_op[6:0] 7'0111000 - case - assign $1\SHIFT_ROT_internal_op[6:0] 7'0000000 - end - sync always - update \SHIFT_ROT_internal_op $0\SHIFT_ROT_internal_op[6:0] - end - attribute \src "issuer_ls180.v:62139.3-62160.6" - process $proc$issuer_ls180.v:62139$3451 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_in2_sel[3:0] $1\SHIFT_ROT_in2_sel[3:0] - attribute \src "issuer_ls180.v:62140.5-62140.29" - switch \initial - attribute \src "issuer_ls180.v:62140.9-62140.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\SHIFT_ROT_in2_sel[3:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SHIFT_ROT_in2_sel[3:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\SHIFT_ROT_in2_sel[3:0] 4'1011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\SHIFT_ROT_in2_sel[3:0] 4'1011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\SHIFT_ROT_in2_sel[3:0] 4'0001 - case - assign $1\SHIFT_ROT_in2_sel[3:0] 4'0000 - end - sync always - update \SHIFT_ROT_in2_sel $0\SHIFT_ROT_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:62161.3-62182.6" - process $proc$issuer_ls180.v:62161$3452 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_cr_in[2:0] $1\SHIFT_ROT_cr_in[2:0] - attribute \src "issuer_ls180.v:62162.5-62162.29" - switch \initial - attribute \src "issuer_ls180.v:62162.9-62162.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\SHIFT_ROT_cr_in[2:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SHIFT_ROT_cr_in[2:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\SHIFT_ROT_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\SHIFT_ROT_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\SHIFT_ROT_cr_in[2:0] 3'000 - case - assign $1\SHIFT_ROT_cr_in[2:0] 3'000 - end - sync always - update \SHIFT_ROT_cr_in $0\SHIFT_ROT_cr_in[2:0] - end - attribute \src "issuer_ls180.v:62183.3-62204.6" - process $proc$issuer_ls180.v:62183$3453 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_cr_out[2:0] $1\SHIFT_ROT_cr_out[2:0] - attribute \src "issuer_ls180.v:62184.5-62184.29" - switch \initial - attribute \src "issuer_ls180.v:62184.9-62184.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\SHIFT_ROT_cr_out[2:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SHIFT_ROT_cr_out[2:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\SHIFT_ROT_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\SHIFT_ROT_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\SHIFT_ROT_cr_out[2:0] 3'000 - case - assign $1\SHIFT_ROT_cr_out[2:0] 3'000 - end - sync always - update \SHIFT_ROT_cr_out $0\SHIFT_ROT_cr_out[2:0] - end - attribute \src "issuer_ls180.v:62205.3-62226.6" - process $proc$issuer_ls180.v:62205$3454 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_rc_sel[1:0] $1\SHIFT_ROT_rc_sel[1:0] - attribute \src "issuer_ls180.v:62206.5-62206.29" - switch \initial - attribute \src "issuer_ls180.v:62206.9-62206.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\SHIFT_ROT_rc_sel[1:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SHIFT_ROT_rc_sel[1:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\SHIFT_ROT_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\SHIFT_ROT_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\SHIFT_ROT_rc_sel[1:0] 2'10 - case - assign $1\SHIFT_ROT_rc_sel[1:0] 2'00 - end - sync always - update \SHIFT_ROT_rc_sel $0\SHIFT_ROT_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:62227.3-62248.6" - process $proc$issuer_ls180.v:62227$3455 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_cry_in[1:0] $1\SHIFT_ROT_cry_in[1:0] - attribute \src "issuer_ls180.v:62228.5-62228.29" - switch \initial - attribute \src "issuer_ls180.v:62228.9-62228.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\SHIFT_ROT_cry_in[1:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SHIFT_ROT_cry_in[1:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\SHIFT_ROT_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\SHIFT_ROT_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\SHIFT_ROT_cry_in[1:0] 2'00 - case - assign $1\SHIFT_ROT_cry_in[1:0] 2'00 - end - sync always - update \SHIFT_ROT_cry_in $0\SHIFT_ROT_cry_in[1:0] - end - connect \$1 $ternary$issuer_ls180.v:62002$3445_Y - connect \VC_XO \opcode_in [9:0] - connect \VC_VRT \opcode_in [25:21] - connect \VC_VRB \opcode_in [15:11] - connect \VC_VRA \opcode_in [20:16] - connect \VC_Rc \opcode_in [10] - connect \XS_XO \opcode_in [10:2] - connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } - connect \XS_RS \opcode_in [25:21] - connect \XS_Rc \opcode_in [0] - connect \XS_RA \opcode_in [20:16] - connect \VA_XO \opcode_in [5:0] - connect \VA_VRT \opcode_in [25:21] - connect \VA_VRC \opcode_in [10:6] - connect \VA_VRB \opcode_in [15:11] - connect \VA_VRA \opcode_in [20:16] - connect \VA_SHB \opcode_in [9:6] - connect \VA_RT \opcode_in [25:21] - connect \VA_RC \opcode_in [10:6] - connect \VA_RB \opcode_in [15:11] - connect \VA_RA \opcode_in [20:16] - connect \TX_XO \opcode_in [6:1] - connect \TX_XBI \opcode_in [10:7] - connect \TX_UI \opcode_in [15:11] - connect \TX_RA \opcode_in [20:16] - connect \DQE_XO \opcode_in [1:0] - connect \DQE_RT \opcode_in [25:21] - connect \DQE_RA \opcode_in [20:16] - connect \XO_XO \opcode_in [9:1] - connect \XO_RT \opcode_in [25:21] - connect \XO_Rc \opcode_in [0] - connect \XO_RB \opcode_in [15:11] - connect \XO_RA \opcode_in [20:16] - connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] - connect \MD_XO \opcode_in [4:2] - connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } - connect \MD_RS \opcode_in [25:21] - connect \MD_Rc \opcode_in [0] - connect \MD_RA \opcode_in [20:16] - connect \MD_me \opcode_in [10:5] - connect \MD_mb \opcode_in [10:5] - connect \M_SH \opcode_in [15:11] - connect \M_RS \opcode_in [25:21] - connect \M_Rc \opcode_in [0] - connect \M_RB \opcode_in [15:11] - connect \M_RA \opcode_in [20:16] - connect \M_ME \opcode_in [5:1] - connect \M_MB \opcode_in [10:6] - connect \SC_XO_1 \opcode_in [1:0] - connect \SC_XO \opcode_in [1] - connect \SC_LEV \opcode_in [11:5] - connect \MDS_XO \opcode_in [4:1] - connect \MDS_XBI_1 \opcode_in [10:7] - connect \MDS_XBI \opcode_in [10:7] - connect \MDS_RS \opcode_in [25:21] - connect \MDS_Rc \opcode_in [0] - connect \MDS_RB \opcode_in [15:11] - connect \MDS_RA \opcode_in [20:16] - connect \MDS_me \opcode_in [10:5] - connect \MDS_mb \opcode_in [10:5] - connect \MDS_IS \opcode_in [25:21] - connect \MDS_IB \opcode_in [15:11] - connect \Z23_XO \opcode_in [8:1] - connect \Z23_TE \opcode_in [20:16] - connect \Z23_RMC \opcode_in [10:9] - connect \Z23_Rc \opcode_in [0] - connect \Z23_R \opcode_in [16] - connect \Z23_FRTp \opcode_in [25:21] - connect \Z23_FRT \opcode_in [25:21] - connect \Z23_FRBp \opcode_in [15:11] - connect \Z23_FRB \opcode_in [15:11] - connect \Z23_FRAp \opcode_in [20:16] - connect \Z23_FRA \opcode_in [20:16] - connect \XFL_XO \opcode_in [10:1] - connect \XFL_W \opcode_in [16] - connect \XFL_Rc \opcode_in [0] - connect \XFL_L \opcode_in [25] - connect \XFL_FRB \opcode_in [15:11] - connect \XFL_FLM \opcode_in [24:17] - connect \VX_XO_1 \opcode_in [10:0] - connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } - connect \VX_VRT \opcode_in [25:21] - connect \VX_VRB \opcode_in [15:11] - connect \VX_VRA \opcode_in [20:16] - connect \VX_UIM_3 \opcode_in [17:16] - connect \VX_UIM_2 \opcode_in [18:16] - connect \VX_UIM_1 \opcode_in [19:16] - connect \VX_UIM \opcode_in [20:16] - connect \VX_SIM \opcode_in [20:16] - connect \VX_RT \opcode_in [25:21] - connect \VX_RA \opcode_in [20:16] - connect \VX_PS \opcode_in [9] - connect \VX_EO \opcode_in [20:16] - connect \DS_XO \opcode_in [1:0] - connect \DS_VRT \opcode_in [25:21] - connect \DS_VRS \opcode_in [25:21] - connect \DS_RT \opcode_in [25:21] - connect \DS_RSp \opcode_in [25:21] - connect \DS_RS \opcode_in [25:21] - connect \DS_RA \opcode_in [20:16] - connect \DS_FRTp \opcode_in [25:21] - connect \DS_FRSp \opcode_in [25:21] - connect \DS_DS \opcode_in [15:2] - connect \DQ_XO \opcode_in [2:0] - connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_T \opcode_in [25:21] - connect \DQ_TX \opcode_in [3] - connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_S \opcode_in [25:21] - connect \DQ_SX \opcode_in [3] - connect \DQ_RTp \opcode_in [25:21] - connect \DQ_RA \opcode_in [20:16] - connect \DQ_PT \opcode_in [3:0] - connect \DQ_DQ \opcode_in [15:4] - connect \DX_XO \opcode_in [5:1] - connect \DX_RT \opcode_in [25:21] - connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } - connect \DX_d2 \opcode_in [0] - connect \DX_d1 \opcode_in [20:16] - connect \DX_d0 \opcode_in [15:6] - connect \XFX_XO \opcode_in [10:1] - connect \XFX_SPR \opcode_in [20:11] - connect \XFX_RT \opcode_in [25:21] - connect \XFX_RS \opcode_in [25:21] - connect \XFX_FXM \opcode_in [19:12] - connect \XFX_DUIS \opcode_in [20:11] - connect \XFX_DUI \opcode_in [25:21] - connect \XFX_BHRBE \opcode_in [20:11] - connect \EVS_BFA \opcode_in [2:0] - connect \Z22_XO \opcode_in [9:1] - connect \Z22_SH \opcode_in [15:10] - connect \Z22_Rc \opcode_in [0] - connect \Z22_FRTp \opcode_in [25:21] - connect \Z22_FRT \opcode_in [25:21] - connect \Z22_FRAp \opcode_in [20:16] - connect \Z22_FRA \opcode_in [20:16] - connect \Z22_DGM \opcode_in [15:10] - connect \Z22_DCM \opcode_in [15:10] - connect \Z22_BF \opcode_in [25:23] - connect \XX2_XO_1 \opcode_in [10:2] - connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } - connect \XX2_UIM_1 \opcode_in [17:16] - connect \XX2_UIM \opcode_in [19:16] - connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX2_T \opcode_in [25:21] - connect \XX2_TX \opcode_in [0] - connect \XX2_RT \opcode_in [25:21] - connect \XX2_EO \opcode_in [20:16] - connect \XX2_DCMX \opcode_in [22:16] - connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } - connect \XX2_dx \opcode_in [20:16] - connect \XX2_dm \opcode_in [2] - connect \XX2_dc \opcode_in [6] - connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX2_B \opcode_in [15:11] - connect \XX2_BX \opcode_in [1] - connect \XX2_BF \opcode_in [25:23] - connect \D_UI \opcode_in [15:0] - connect \D_TO \opcode_in [25:21] - connect \D_SI \opcode_in [15:0] - connect \D_RT \opcode_in [25:21] - connect \D_RS \opcode_in [25:21] - connect \D_RA \opcode_in [20:16] - connect \D_L \opcode_in [21] - connect \D_FRT \opcode_in [25:21] - connect \D_FRS \opcode_in [25:21] - connect \D_D \opcode_in [15:0] - connect \D_BF \opcode_in [25:23] - connect \A_XO \opcode_in [5:1] - connect \A_RT \opcode_in [25:21] - connect \A_Rc \opcode_in [0] - connect \A_RB \opcode_in [15:11] - connect \A_RA \opcode_in [20:16] - connect \A_FRT \opcode_in [25:21] - connect \A_FRC \opcode_in [10:6] - connect \A_FRB \opcode_in [15:11] - connect \A_FRA \opcode_in [20:16] - connect \A_BC \opcode_in [10:6] - connect \XL_XO \opcode_in [10:1] - connect \XL_S \opcode_in [11] - connect \XL_OC \opcode_in [25:11] - connect \XL_LK \opcode_in [0] - connect \XL_BT \opcode_in [25:21] - connect \XL_BO_1 \opcode_in [25:21] - connect \XL_BO \opcode_in [25:21] - connect \XL_BI \opcode_in [20:16] - connect \XL_BH \opcode_in [12:11] - connect \XL_BFA \opcode_in [20:18] - connect \XL_BF \opcode_in [25:23] - connect \XL_BB \opcode_in [15:11] - connect \XL_BA \opcode_in [20:16] - connect \XX4_XO \opcode_in [5:4] - connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX4_T \opcode_in [25:21] - connect \XX4_TX \opcode_in [0] - connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } - connect \XX4_C \opcode_in [10:6] - connect \XX4_CX \opcode_in [3] - connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX4_B \opcode_in [15:11] - connect \XX4_BX \opcode_in [1] - connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX4_A \opcode_in [20:16] - connect \XX4_AX \opcode_in [2] - connect \XX3_XO_2 \opcode_in [9:1] - connect \XX3_XO_1 \opcode_in [10:3] - connect \XX3_XO \opcode_in [10:7] - connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX3_T \opcode_in [25:21] - connect \XX3_TX \opcode_in [0] - connect \XX3_SHW \opcode_in [9:8] - connect \XX3_Rc \opcode_in [10] - connect \XX3_DM \opcode_in [9:8] - connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX3_B \opcode_in [15:11] - connect \XX3_BX \opcode_in [1] - connect \XX3_BF \opcode_in [25:23] - connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX3_A \opcode_in [20:16] - connect \XX3_AX \opcode_in [2] - connect \I_LK \opcode_in [0] - connect \I_LI \opcode_in [25:2] - connect \I_AA \opcode_in [1] - connect \B_LK \opcode_in [0] - connect \B_BO \opcode_in [25:21] - connect \B_BI \opcode_in [20:16] - connect \B_BD \opcode_in [15:2] - connect \B_AA \opcode_in [1] - connect \X_XO_1 \opcode_in [8:1] - connect \X_XO \opcode_in [10:1] - connect \X_WC \opcode_in [22:21] - connect \X_W \opcode_in [16] - connect \X_VRT \opcode_in [25:21] - connect \X_VRS \opcode_in [25:21] - connect \X_UIM \opcode_in [20:16] - connect \X_U \opcode_in [15:12] - connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \X_TX \opcode_in [0] - connect \X_TO \opcode_in [25:21] - connect \X_TH \opcode_in [25:21] - connect \X_TBR \opcode_in [20:11] - connect \X_T \opcode_in [25:21] - connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } - connect \X_SX \opcode_in [0] - connect \X_SR \opcode_in [19:16] - connect \X_SP \opcode_in [20:19] - connect \X_SI \opcode_in [15:11] - connect \X_SH \opcode_in [15:11] - connect \X_S \opcode_in [25:21] - connect \X_RTp \opcode_in [25:21] - connect \X_RT \opcode_in [25:21] - connect \X_RSp \opcode_in [25:21] - connect \X_RS \opcode_in [25:21] - connect \X_RO \opcode_in [0] - connect \X_RM \opcode_in [12:11] - connect \X_RIC \opcode_in [19:18] - connect \X_Rc \opcode_in [0] - connect \X_RB \opcode_in [15:11] - connect \X_RA \opcode_in [20:16] - connect \X_R_1 \opcode_in [16] - connect \X_R \opcode_in [21] - connect \X_PRS \opcode_in [17] - connect \X_NB \opcode_in [15:11] - connect \X_MO \opcode_in [25:21] - connect \X_L3 \opcode_in [17:16] - connect \X_L1 \opcode_in [16] - connect \X_L \opcode_in [21] - connect \X_L2 \opcode_in [22:21] - connect \X_IMM8 \opcode_in [18:11] - connect \X_IH \opcode_in [23:21] - connect \X_FRTp \opcode_in [25:21] - connect \X_FRT \opcode_in [25:21] - connect \X_FRSp \opcode_in [25:21] - connect \X_FRS \opcode_in [25:21] - connect \X_FRBp \opcode_in [15:11] - connect \X_FRB \opcode_in [15:11] - connect \X_FRAp \opcode_in [20:16] - connect \X_FRA \opcode_in [20:16] - connect \X_FC \opcode_in [15:11] - connect \X_EX \opcode_in [0] - connect \X_EO_1 \opcode_in [20:16] - connect \X_EO \opcode_in [20:19] - connect \X_E_1 \opcode_in [19:16] - connect \X_E \opcode_in [15] - connect \X_DRM \opcode_in [13:11] - connect \X_DCMX \opcode_in [22:16] - connect \X_CT \opcode_in [24:21] - connect \X_BO \opcode_in [25:21] - connect \X_BFA \opcode_in [20:18] - connect \X_BF \opcode_in [25:23] - connect \X_A \opcode_in [25] - connect \SHIFT_ROT_SPR \opcode_in [20:11] - connect \SHIFT_ROT_MB \opcode_in [10:6] - connect \SHIFT_ROT_ME \opcode_in [5:1] - connect \SHIFT_ROT_SH \opcode_in [15:11] - connect \SHIFT_ROT_BC \opcode_in [10:6] - connect \SHIFT_ROT_TO \opcode_in [25:21] - connect \SHIFT_ROT_DS \opcode_in [15:2] - connect \SHIFT_ROT_D \opcode_in [15:0] - connect \SHIFT_ROT_BH \opcode_in [12:11] - connect \SHIFT_ROT_BI \opcode_in [20:16] - connect \SHIFT_ROT_BO \opcode_in [25:21] - connect \SHIFT_ROT_FXM \opcode_in [19:12] - connect \SHIFT_ROT_BT \opcode_in [25:21] - connect \SHIFT_ROT_BA \opcode_in [20:16] - connect \SHIFT_ROT_BB \opcode_in [15:11] - connect \SHIFT_ROT_CR \opcode_in [10:1] - connect \SHIFT_ROT_BF \opcode_in [25:23] - connect \SHIFT_ROT_BD \opcode_in [15:2] - connect \SHIFT_ROT_OE \opcode_in [10] - connect \SHIFT_ROT_Rc \opcode_in [0] - connect \SHIFT_ROT_AA \opcode_in [1] - connect \SHIFT_ROT_LK \opcode_in [0] - connect \SHIFT_ROT_LI \opcode_in [25:2] - connect \SHIFT_ROT_ME32 \opcode_in [5:1] - connect \SHIFT_ROT_MB32 \opcode_in [10:6] - connect \SHIFT_ROT_sh { \opcode_in [1] \opcode_in [15:11] } - connect \SHIFT_ROT_SH32 \opcode_in [15:11] - connect \SHIFT_ROT_L \opcode_in [21] - connect \SHIFT_ROT_UI \opcode_in [15:0] - connect \SHIFT_ROT_SI \opcode_in [15:0] - connect \SHIFT_ROT_RB \opcode_in [15:11] - connect \SHIFT_ROT_RA \opcode_in [20:16] - connect \SHIFT_ROT_RT \opcode_in [25:21] - connect \SHIFT_ROT_RS \opcode_in [25:21] - connect \opcode_in \$1 - connect \SHIFT_ROT_dec31_opcode_in \opcode_in - connect \SHIFT_ROT_dec30_opcode_in \opcode_in - connect \opcode_switch \opcode_in [31:26] -end -attribute \src "issuer_ls180.v:62583.1-65052.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec" -attribute \generator "nMigen" -module \dec$193 - attribute \src "issuer_ls180.v:64141.3-64198.6" - wire $0\LDST_br[0:0] - attribute \src "issuer_ls180.v:64605.3-64662.6" - wire width 3 $0\LDST_cr_in[2:0] - attribute \src "issuer_ls180.v:64663.3-64720.6" - wire width 3 $0\LDST_cr_out[2:0] - attribute \src "issuer_ls180.v:64373.3-64430.6" - wire width 12 $0\LDST_function_unit[11:0] - attribute \src "issuer_ls180.v:64489.3-64546.6" - wire width 3 $0\LDST_in1_sel[2:0] - attribute \src "issuer_ls180.v:64547.3-64604.6" - wire width 4 $0\LDST_in2_sel[3:0] - attribute \src "issuer_ls180.v:64431.3-64488.6" - wire width 7 $0\LDST_internal_op[6:0] - attribute \src "issuer_ls180.v:64257.3-64314.6" - wire $0\LDST_is_32b[0:0] - attribute \src "issuer_ls180.v:63967.3-64024.6" - wire width 4 $0\LDST_ldst_len[3:0] - attribute \src "issuer_ls180.v:64083.3-64140.6" - wire width 2 $0\LDST_rc_sel[1:0] - attribute \src "issuer_ls180.v:64315.3-64372.6" - wire $0\LDST_sgn[0:0] - attribute \src "issuer_ls180.v:64199.3-64256.6" - wire $0\LDST_sgn_ext[0:0] - attribute \src "issuer_ls180.v:64025.3-64082.6" - wire width 2 $0\LDST_upd[1:0] - attribute \src "issuer_ls180.v:62584.7-62584.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:64141.3-64198.6" - wire $1\LDST_br[0:0] - attribute \src "issuer_ls180.v:64605.3-64662.6" - wire width 3 $1\LDST_cr_in[2:0] - attribute \src "issuer_ls180.v:64663.3-64720.6" - wire width 3 $1\LDST_cr_out[2:0] - attribute \src "issuer_ls180.v:64373.3-64430.6" - wire width 12 $1\LDST_function_unit[11:0] - attribute \src "issuer_ls180.v:64489.3-64546.6" - wire width 3 $1\LDST_in1_sel[2:0] - attribute \src "issuer_ls180.v:64547.3-64604.6" - wire width 4 $1\LDST_in2_sel[3:0] - attribute \src "issuer_ls180.v:64431.3-64488.6" - wire width 7 $1\LDST_internal_op[6:0] - attribute \src "issuer_ls180.v:64257.3-64314.6" - wire $1\LDST_is_32b[0:0] - attribute \src "issuer_ls180.v:63967.3-64024.6" - wire width 4 $1\LDST_ldst_len[3:0] - attribute \src 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\enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 10 \LDST_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 3 \LDST_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 12 \LDST_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 14 \LDST_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 6 output 20 \LDST_sh - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 15 \LDST_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 output 34 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 output 32 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 output 33 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire input 1 \bigendian - attribute \src "issuer_ls180.v:62584.7-62584.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 input 35 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" - cell $mux $ternary$issuer_ls180.v:63918$3457 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $ternary$issuer_ls180.v:63918$3457_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:63919.14-63934.4" - cell \LDST_dec31 \LDST_dec31 - connect \LDST_dec31_br \LDST_dec31_LDST_dec31_br - connect \LDST_dec31_cr_in \LDST_dec31_LDST_dec31_cr_in - connect \LDST_dec31_cr_out \LDST_dec31_LDST_dec31_cr_out - connect \LDST_dec31_function_unit \LDST_dec31_LDST_dec31_function_unit - connect \LDST_dec31_in1_sel \LDST_dec31_LDST_dec31_in1_sel - connect \LDST_dec31_in2_sel \LDST_dec31_LDST_dec31_in2_sel - connect \LDST_dec31_internal_op \LDST_dec31_LDST_dec31_internal_op - connect \LDST_dec31_is_32b \LDST_dec31_LDST_dec31_is_32b - connect \LDST_dec31_ldst_len \LDST_dec31_LDST_dec31_ldst_len - connect \LDST_dec31_rc_sel \LDST_dec31_LDST_dec31_rc_sel - connect \LDST_dec31_sgn \LDST_dec31_LDST_dec31_sgn - connect \LDST_dec31_sgn_ext \LDST_dec31_LDST_dec31_sgn_ext - connect \LDST_dec31_upd \LDST_dec31_LDST_dec31_upd - connect \opcode_in \LDST_dec31_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:63935.14-63950.4" - cell \LDST_dec58 \LDST_dec58 - connect \LDST_dec58_br \LDST_dec58_LDST_dec58_br - connect \LDST_dec58_cr_in \LDST_dec58_LDST_dec58_cr_in - connect \LDST_dec58_cr_out \LDST_dec58_LDST_dec58_cr_out - connect \LDST_dec58_function_unit \LDST_dec58_LDST_dec58_function_unit - connect \LDST_dec58_in1_sel \LDST_dec58_LDST_dec58_in1_sel - connect \LDST_dec58_in2_sel \LDST_dec58_LDST_dec58_in2_sel - connect \LDST_dec58_internal_op \LDST_dec58_LDST_dec58_internal_op - connect \LDST_dec58_is_32b \LDST_dec58_LDST_dec58_is_32b - connect \LDST_dec58_ldst_len \LDST_dec58_LDST_dec58_ldst_len - connect \LDST_dec58_rc_sel \LDST_dec58_LDST_dec58_rc_sel - connect \LDST_dec58_sgn \LDST_dec58_LDST_dec58_sgn - connect \LDST_dec58_sgn_ext \LDST_dec58_LDST_dec58_sgn_ext - connect \LDST_dec58_upd \LDST_dec58_LDST_dec58_upd - connect \opcode_in \LDST_dec58_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:63951.14-63966.4" - cell \LDST_dec62 \LDST_dec62 - connect \LDST_dec62_br \LDST_dec62_LDST_dec62_br - connect \LDST_dec62_cr_in \LDST_dec62_LDST_dec62_cr_in - connect \LDST_dec62_cr_out \LDST_dec62_LDST_dec62_cr_out - connect \LDST_dec62_function_unit \LDST_dec62_LDST_dec62_function_unit - connect \LDST_dec62_in1_sel \LDST_dec62_LDST_dec62_in1_sel - connect \LDST_dec62_in2_sel \LDST_dec62_LDST_dec62_in2_sel - connect \LDST_dec62_internal_op \LDST_dec62_LDST_dec62_internal_op - connect \LDST_dec62_is_32b \LDST_dec62_LDST_dec62_is_32b - connect \LDST_dec62_ldst_len \LDST_dec62_LDST_dec62_ldst_len - connect \LDST_dec62_rc_sel \LDST_dec62_LDST_dec62_rc_sel - connect \LDST_dec62_sgn \LDST_dec62_LDST_dec62_sgn - connect \LDST_dec62_sgn_ext \LDST_dec62_LDST_dec62_sgn_ext - connect \LDST_dec62_upd \LDST_dec62_LDST_dec62_upd - connect \opcode_in \LDST_dec62_opcode_in - end - attribute \src "issuer_ls180.v:62584.7-62584.20" - process $proc$issuer_ls180.v:62584$3471 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:63967.3-64024.6" - process $proc$issuer_ls180.v:63967$3458 - assign { } { } - assign { } { } - assign $0\LDST_ldst_len[3:0] $1\LDST_ldst_len[3:0] - attribute \src "issuer_ls180.v:63968.5-63968.29" - switch \initial - attribute \src "issuer_ls180.v:63968.9-63968.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_ldst_len[3:0] \LDST_dec31_LDST_dec31_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_ldst_len[3:0] \LDST_dec58_LDST_dec58_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_ldst_len[3:0] \LDST_dec62_LDST_dec62_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0100 - case - assign $1\LDST_ldst_len[3:0] 4'0000 - end - sync always - update \LDST_ldst_len $0\LDST_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:64025.3-64082.6" - process $proc$issuer_ls180.v:64025$3459 - assign { } { } - assign { } { } - assign $0\LDST_upd[1:0] $1\LDST_upd[1:0] - attribute \src "issuer_ls180.v:64026.5-64026.29" - switch \initial - attribute \src "issuer_ls180.v:64026.9-64026.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_upd[1:0] \LDST_dec31_LDST_dec31_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_upd[1:0] \LDST_dec58_LDST_dec58_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_upd[1:0] \LDST_dec62_LDST_dec62_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_upd[1:0] 2'01 - case - assign $1\LDST_upd[1:0] 2'00 - end - sync always - update \LDST_upd $0\LDST_upd[1:0] - end - attribute \src "issuer_ls180.v:64083.3-64140.6" - process $proc$issuer_ls180.v:64083$3460 - assign { } { } - assign { } { } - assign $0\LDST_rc_sel[1:0] $1\LDST_rc_sel[1:0] - attribute \src "issuer_ls180.v:64084.5-64084.29" - switch \initial - attribute \src "issuer_ls180.v:64084.9-64084.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_rc_sel[1:0] \LDST_dec31_LDST_dec31_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_rc_sel[1:0] \LDST_dec58_LDST_dec58_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_rc_sel[1:0] \LDST_dec62_LDST_dec62_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - case - assign $1\LDST_rc_sel[1:0] 2'00 - end - sync always - update \LDST_rc_sel $0\LDST_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:64141.3-64198.6" - process $proc$issuer_ls180.v:64141$3461 - assign { } { } - assign { } { } - assign $0\LDST_br[0:0] $1\LDST_br[0:0] - attribute \src "issuer_ls180.v:64142.5-64142.29" - switch \initial - attribute \src "issuer_ls180.v:64142.9-64142.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_br[0:0] \LDST_dec31_LDST_dec31_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_br[0:0] \LDST_dec58_LDST_dec58_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_br[0:0] \LDST_dec62_LDST_dec62_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - case - assign $1\LDST_br[0:0] 1'0 - end - sync always - update \LDST_br $0\LDST_br[0:0] - end - attribute \src "issuer_ls180.v:64199.3-64256.6" - process $proc$issuer_ls180.v:64199$3462 - assign { } { } - assign { } { } - assign $0\LDST_sgn_ext[0:0] $1\LDST_sgn_ext[0:0] - attribute \src "issuer_ls180.v:64200.5-64200.29" - switch \initial - attribute \src "issuer_ls180.v:64200.9-64200.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_sgn_ext[0:0] \LDST_dec31_LDST_dec31_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_sgn_ext[0:0] \LDST_dec58_LDST_dec58_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_sgn_ext[0:0] \LDST_dec62_LDST_dec62_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'0 - case - assign $1\LDST_sgn_ext[0:0] 1'0 - end - sync always - update \LDST_sgn_ext $0\LDST_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:64257.3-64314.6" - process $proc$issuer_ls180.v:64257$3463 - assign { } { } - assign { } { } - assign $0\LDST_is_32b[0:0] $1\LDST_is_32b[0:0] - attribute \src "issuer_ls180.v:64258.5-64258.29" - switch \initial - attribute \src "issuer_ls180.v:64258.9-64258.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_is_32b[0:0] \LDST_dec31_LDST_dec31_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_is_32b[0:0] \LDST_dec58_LDST_dec58_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_is_32b[0:0] \LDST_dec62_LDST_dec62_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - case - assign $1\LDST_is_32b[0:0] 1'0 - end - sync always - update \LDST_is_32b $0\LDST_is_32b[0:0] - end - attribute \src "issuer_ls180.v:64315.3-64372.6" - process $proc$issuer_ls180.v:64315$3464 - assign { } { } - assign { } { } - assign $0\LDST_sgn[0:0] $1\LDST_sgn[0:0] - attribute \src "issuer_ls180.v:64316.5-64316.29" - switch \initial - attribute \src "issuer_ls180.v:64316.9-64316.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_sgn[0:0] \LDST_dec31_LDST_dec31_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_sgn[0:0] \LDST_dec58_LDST_dec58_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_sgn[0:0] \LDST_dec62_LDST_dec62_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - case - assign $1\LDST_sgn[0:0] 1'0 - end - sync always - update \LDST_sgn $0\LDST_sgn[0:0] - end - attribute \src "issuer_ls180.v:64373.3-64430.6" - process $proc$issuer_ls180.v:64373$3465 - assign { } { } - assign { } { } - assign $0\LDST_function_unit[11:0] $1\LDST_function_unit[11:0] - attribute \src "issuer_ls180.v:64374.5-64374.29" - switch \initial - attribute \src "issuer_ls180.v:64374.9-64374.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_function_unit[11:0] \LDST_dec31_LDST_dec31_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_function_unit[11:0] \LDST_dec58_LDST_dec58_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_function_unit[11:0] \LDST_dec62_LDST_dec62_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - case - assign $1\LDST_function_unit[11:0] 12'000000000000 - end - sync always - update \LDST_function_unit $0\LDST_function_unit[11:0] - end - attribute \src "issuer_ls180.v:64431.3-64488.6" - process $proc$issuer_ls180.v:64431$3466 - assign { } { } - assign { } { } - assign $0\LDST_internal_op[6:0] $1\LDST_internal_op[6:0] - attribute \src "issuer_ls180.v:64432.5-64432.29" - switch \initial - attribute \src "issuer_ls180.v:64432.9-64432.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_internal_op[6:0] \LDST_dec31_LDST_dec31_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_internal_op[6:0] \LDST_dec58_LDST_dec58_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_internal_op[6:0] \LDST_dec62_LDST_dec62_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100110 - case - assign $1\LDST_internal_op[6:0] 7'0000000 - end - sync always - update \LDST_internal_op $0\LDST_internal_op[6:0] - end - attribute \src "issuer_ls180.v:64489.3-64546.6" - process $proc$issuer_ls180.v:64489$3467 - assign { } { } - assign { } { } - assign $0\LDST_in1_sel[2:0] $1\LDST_in1_sel[2:0] - attribute \src "issuer_ls180.v:64490.5-64490.29" - switch \initial - attribute \src "issuer_ls180.v:64490.9-64490.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_in1_sel[2:0] \LDST_dec31_LDST_dec31_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_in1_sel[2:0] \LDST_dec58_LDST_dec58_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_in1_sel[2:0] \LDST_dec62_LDST_dec62_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - case - assign $1\LDST_in1_sel[2:0] 3'000 - end - sync always - update \LDST_in1_sel $0\LDST_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:64547.3-64604.6" - process $proc$issuer_ls180.v:64547$3468 - assign { } { } - assign { } { } - assign $0\LDST_in2_sel[3:0] $1\LDST_in2_sel[3:0] - attribute \src "issuer_ls180.v:64548.5-64548.29" - switch \initial - attribute \src "issuer_ls180.v:64548.9-64548.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_in2_sel[3:0] \LDST_dec31_LDST_dec31_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_in2_sel[3:0] \LDST_dec58_LDST_dec58_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_in2_sel[3:0] \LDST_dec62_LDST_dec62_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - case - assign $1\LDST_in2_sel[3:0] 4'0000 - end - sync always - update \LDST_in2_sel $0\LDST_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:64605.3-64662.6" - process $proc$issuer_ls180.v:64605$3469 - assign { } { } - assign { } { } - assign $0\LDST_cr_in[2:0] $1\LDST_cr_in[2:0] - attribute \src "issuer_ls180.v:64606.5-64606.29" - switch \initial - attribute \src "issuer_ls180.v:64606.9-64606.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_cr_in[2:0] \LDST_dec31_LDST_dec31_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_cr_in[2:0] \LDST_dec58_LDST_dec58_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_cr_in[2:0] \LDST_dec62_LDST_dec62_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - case - assign $1\LDST_cr_in[2:0] 3'000 - end - sync always - update \LDST_cr_in $0\LDST_cr_in[2:0] - end - attribute \src "issuer_ls180.v:64663.3-64720.6" - process $proc$issuer_ls180.v:64663$3470 - assign { } { } - assign { } { } - assign $0\LDST_cr_out[2:0] $1\LDST_cr_out[2:0] - attribute \src "issuer_ls180.v:64664.5-64664.29" - switch \initial - attribute \src "issuer_ls180.v:64664.9-64664.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_cr_out[2:0] \LDST_dec31_LDST_dec31_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_cr_out[2:0] \LDST_dec58_LDST_dec58_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_cr_out[2:0] \LDST_dec62_LDST_dec62_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - case - assign $1\LDST_cr_out[2:0] 3'000 - end - sync always - update \LDST_cr_out $0\LDST_cr_out[2:0] - end - connect \$1 $ternary$issuer_ls180.v:63918$3457_Y - connect \VC_XO \opcode_in [9:0] - connect \VC_VRT \opcode_in [25:21] - connect \VC_VRB \opcode_in [15:11] - connect \VC_VRA \opcode_in [20:16] - connect \VC_Rc \opcode_in [10] - connect \XS_XO \opcode_in [10:2] - connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } - connect \XS_RS \opcode_in [25:21] - connect \XS_Rc \opcode_in [0] - connect \XS_RA \opcode_in [20:16] - connect \VA_XO \opcode_in [5:0] - connect \VA_VRT \opcode_in [25:21] - connect \VA_VRC \opcode_in [10:6] - connect \VA_VRB \opcode_in [15:11] - connect \VA_VRA \opcode_in [20:16] - connect \VA_SHB \opcode_in [9:6] - connect \VA_RT \opcode_in [25:21] - connect \VA_RC \opcode_in [10:6] - connect \VA_RB \opcode_in [15:11] - connect \VA_RA \opcode_in [20:16] - connect \TX_XO \opcode_in [6:1] - connect \TX_XBI \opcode_in [10:7] - connect \TX_UI \opcode_in [15:11] - connect \TX_RA \opcode_in [20:16] - connect \DQE_XO \opcode_in [1:0] - connect \DQE_RT \opcode_in [25:21] - connect \DQE_RA \opcode_in [20:16] - connect \XO_XO \opcode_in [9:1] - connect \XO_RT \opcode_in [25:21] - connect \XO_Rc \opcode_in [0] - connect \XO_RB \opcode_in [15:11] - connect \XO_RA \opcode_in [20:16] - connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] - connect \MD_XO \opcode_in [4:2] - connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } - connect \MD_RS \opcode_in [25:21] - connect \MD_Rc \opcode_in [0] - connect \MD_RA \opcode_in [20:16] - connect \MD_me \opcode_in [10:5] - connect \MD_mb \opcode_in [10:5] - connect \M_SH \opcode_in [15:11] - connect \M_RS \opcode_in [25:21] - connect \M_Rc \opcode_in [0] - connect \M_RB \opcode_in [15:11] - connect \M_RA \opcode_in [20:16] - connect \M_ME \opcode_in [5:1] - connect \M_MB \opcode_in [10:6] - connect \SC_XO_1 \opcode_in [1:0] - connect \SC_XO \opcode_in [1] - connect \SC_LEV \opcode_in [11:5] - connect \MDS_XO \opcode_in [4:1] - connect \MDS_XBI_1 \opcode_in [10:7] - connect \MDS_XBI \opcode_in [10:7] - connect \MDS_RS \opcode_in [25:21] - connect \MDS_Rc \opcode_in [0] - connect \MDS_RB \opcode_in [15:11] - connect \MDS_RA \opcode_in [20:16] - connect \MDS_me \opcode_in [10:5] - connect \MDS_mb \opcode_in [10:5] - connect \MDS_IS \opcode_in [25:21] - connect \MDS_IB \opcode_in [15:11] - connect \Z23_XO \opcode_in [8:1] - connect \Z23_TE \opcode_in [20:16] - connect \Z23_RMC \opcode_in [10:9] - connect \Z23_Rc \opcode_in [0] - connect \Z23_R \opcode_in [16] - connect \Z23_FRTp \opcode_in [25:21] - connect \Z23_FRT \opcode_in [25:21] - connect \Z23_FRBp \opcode_in [15:11] - connect \Z23_FRB \opcode_in [15:11] - connect \Z23_FRAp \opcode_in [20:16] - connect \Z23_FRA \opcode_in [20:16] - connect \XFL_XO \opcode_in [10:1] - connect \XFL_W \opcode_in [16] - connect \XFL_Rc \opcode_in [0] - connect \XFL_L \opcode_in [25] - connect \XFL_FRB \opcode_in [15:11] - connect \XFL_FLM \opcode_in [24:17] - connect \VX_XO_1 \opcode_in [10:0] - connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } - connect \VX_VRT \opcode_in [25:21] - connect \VX_VRB \opcode_in [15:11] - connect \VX_VRA \opcode_in [20:16] - connect \VX_UIM_3 \opcode_in [17:16] - connect \VX_UIM_2 \opcode_in [18:16] - connect \VX_UIM_1 \opcode_in [19:16] - connect \VX_UIM \opcode_in [20:16] - connect \VX_SIM \opcode_in [20:16] - connect \VX_RT \opcode_in [25:21] - connect \VX_RA \opcode_in [20:16] - connect \VX_PS \opcode_in [9] - connect \VX_EO \opcode_in [20:16] - connect \DS_XO \opcode_in [1:0] - connect \DS_VRT \opcode_in [25:21] - connect \DS_VRS \opcode_in [25:21] - connect \DS_RT \opcode_in [25:21] - connect \DS_RSp \opcode_in [25:21] - connect \DS_RS \opcode_in [25:21] - connect \DS_RA \opcode_in [20:16] - connect \DS_FRTp \opcode_in [25:21] - connect \DS_FRSp \opcode_in [25:21] - connect \DS_DS \opcode_in [15:2] - connect \DQ_XO \opcode_in [2:0] - connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_T \opcode_in [25:21] - connect \DQ_TX \opcode_in [3] - connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_S \opcode_in [25:21] - connect \DQ_SX \opcode_in [3] - connect \DQ_RTp \opcode_in [25:21] - connect \DQ_RA \opcode_in [20:16] - connect \DQ_PT \opcode_in [3:0] - connect \DQ_DQ \opcode_in [15:4] - connect \DX_XO \opcode_in [5:1] - connect \DX_RT \opcode_in [25:21] - connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } - connect \DX_d2 \opcode_in [0] - connect \DX_d1 \opcode_in [20:16] - connect \DX_d0 \opcode_in [15:6] - connect \XFX_XO \opcode_in [10:1] - connect \XFX_SPR \opcode_in [20:11] - connect \XFX_RT \opcode_in [25:21] - connect \XFX_RS \opcode_in [25:21] - connect \XFX_FXM \opcode_in [19:12] - connect \XFX_DUIS \opcode_in [20:11] - connect \XFX_DUI \opcode_in [25:21] - connect \XFX_BHRBE \opcode_in [20:11] - connect \EVS_BFA \opcode_in [2:0] - connect \Z22_XO \opcode_in [9:1] - connect \Z22_SH \opcode_in [15:10] - connect \Z22_Rc \opcode_in [0] - connect \Z22_FRTp \opcode_in [25:21] - connect \Z22_FRT \opcode_in [25:21] - connect \Z22_FRAp \opcode_in [20:16] - connect \Z22_FRA \opcode_in [20:16] - connect \Z22_DGM \opcode_in [15:10] - connect \Z22_DCM \opcode_in [15:10] - connect \Z22_BF \opcode_in [25:23] - connect \XX2_XO_1 \opcode_in [10:2] - connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } - connect \XX2_UIM_1 \opcode_in [17:16] - connect \XX2_UIM \opcode_in [19:16] - connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX2_T \opcode_in [25:21] - connect \XX2_TX \opcode_in [0] - connect \XX2_RT \opcode_in [25:21] - connect \XX2_EO \opcode_in [20:16] - connect \XX2_DCMX \opcode_in [22:16] - connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } - connect \XX2_dx \opcode_in [20:16] - connect \XX2_dm \opcode_in [2] - connect \XX2_dc \opcode_in [6] - connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX2_B \opcode_in [15:11] - connect \XX2_BX \opcode_in [1] - connect \XX2_BF \opcode_in [25:23] - connect \D_UI \opcode_in [15:0] - connect \D_TO \opcode_in [25:21] - connect \D_SI \opcode_in [15:0] - connect \D_RT \opcode_in [25:21] - connect \D_RS \opcode_in [25:21] - connect \D_RA \opcode_in [20:16] - connect \D_L \opcode_in [21] - connect \D_FRT \opcode_in [25:21] - connect \D_FRS \opcode_in [25:21] - connect \D_D \opcode_in [15:0] - connect \D_BF \opcode_in [25:23] - connect \A_XO \opcode_in [5:1] - connect \A_RT \opcode_in [25:21] - connect \A_Rc \opcode_in [0] - connect \A_RB \opcode_in [15:11] - connect \A_RA \opcode_in [20:16] - connect \A_FRT \opcode_in [25:21] - connect \A_FRC \opcode_in [10:6] - connect \A_FRB \opcode_in [15:11] - connect \A_FRA \opcode_in [20:16] - connect \A_BC \opcode_in [10:6] - connect \XL_XO \opcode_in [10:1] - connect \XL_S \opcode_in [11] - connect \XL_OC \opcode_in [25:11] - connect \XL_LK \opcode_in [0] - connect \XL_BT \opcode_in [25:21] - connect \XL_BO_1 \opcode_in [25:21] - connect \XL_BO \opcode_in [25:21] - connect \XL_BI \opcode_in [20:16] - connect \XL_BH \opcode_in [12:11] - connect \XL_BFA \opcode_in [20:18] - connect \XL_BF \opcode_in [25:23] - connect \XL_BB \opcode_in [15:11] - connect \XL_BA \opcode_in [20:16] - connect \XX4_XO \opcode_in [5:4] - connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX4_T \opcode_in [25:21] - connect \XX4_TX \opcode_in [0] - connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } - connect \XX4_C \opcode_in [10:6] - connect \XX4_CX \opcode_in [3] - connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX4_B \opcode_in [15:11] - connect \XX4_BX \opcode_in [1] - connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX4_A \opcode_in [20:16] - connect \XX4_AX \opcode_in [2] - connect \XX3_XO_2 \opcode_in [9:1] - connect \XX3_XO_1 \opcode_in [10:3] - connect \XX3_XO \opcode_in [10:7] - connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX3_T \opcode_in [25:21] - connect \XX3_TX \opcode_in [0] - connect \XX3_SHW \opcode_in [9:8] - connect \XX3_Rc \opcode_in [10] - connect \XX3_DM \opcode_in [9:8] - connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX3_B \opcode_in [15:11] - connect \XX3_BX \opcode_in [1] - connect \XX3_BF \opcode_in [25:23] - connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX3_A \opcode_in [20:16] - connect \XX3_AX \opcode_in [2] - connect \I_LK \opcode_in [0] - connect \I_LI \opcode_in [25:2] - connect \I_AA \opcode_in [1] - connect \B_LK \opcode_in [0] - connect \B_BO \opcode_in [25:21] - connect \B_BI \opcode_in [20:16] - connect \B_BD \opcode_in [15:2] - connect \B_AA \opcode_in [1] - connect \X_XO_1 \opcode_in [8:1] - connect \X_XO \opcode_in [10:1] - connect \X_WC \opcode_in [22:21] - connect \X_W \opcode_in [16] - connect \X_VRT \opcode_in [25:21] - connect \X_VRS \opcode_in [25:21] - connect \X_UIM \opcode_in [20:16] - connect \X_U \opcode_in [15:12] - connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \X_TX \opcode_in [0] - connect \X_TO \opcode_in [25:21] - connect \X_TH \opcode_in [25:21] - connect \X_TBR \opcode_in [20:11] - connect \X_T \opcode_in [25:21] - connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } - connect \X_SX \opcode_in [0] - connect \X_SR \opcode_in [19:16] - connect \X_SP \opcode_in [20:19] - connect \X_SI \opcode_in [15:11] - connect \X_SH \opcode_in [15:11] - connect \X_S \opcode_in [25:21] - connect \X_RTp \opcode_in [25:21] - connect \X_RT \opcode_in [25:21] - connect \X_RSp \opcode_in [25:21] - connect \X_RS \opcode_in [25:21] - connect \X_RO \opcode_in [0] - connect \X_RM \opcode_in [12:11] - connect \X_RIC \opcode_in [19:18] - connect \X_Rc \opcode_in [0] - connect \X_RB \opcode_in [15:11] - connect \X_RA \opcode_in [20:16] - connect \X_R_1 \opcode_in [16] - connect \X_R \opcode_in [21] - connect \X_PRS \opcode_in [17] - connect \X_NB \opcode_in [15:11] - connect \X_MO \opcode_in [25:21] - connect \X_L3 \opcode_in [17:16] - connect \X_L1 \opcode_in [16] - connect \X_L \opcode_in [21] - connect \X_L2 \opcode_in [22:21] - connect \X_IMM8 \opcode_in [18:11] - connect \X_IH \opcode_in [23:21] - connect \X_FRTp \opcode_in [25:21] - connect \X_FRT \opcode_in [25:21] - connect \X_FRSp \opcode_in [25:21] - connect \X_FRS \opcode_in [25:21] - connect \X_FRBp \opcode_in [15:11] - connect \X_FRB \opcode_in [15:11] - connect \X_FRAp \opcode_in [20:16] - connect \X_FRA \opcode_in [20:16] - connect \X_FC \opcode_in [15:11] - connect \X_EX \opcode_in [0] - connect \X_EO_1 \opcode_in [20:16] - connect \X_EO \opcode_in [20:19] - connect \X_E_1 \opcode_in [19:16] - connect \X_E \opcode_in [15] - connect \X_DRM \opcode_in [13:11] - connect \X_DCMX \opcode_in [22:16] - connect \X_CT \opcode_in [24:21] - connect \X_BO \opcode_in [25:21] - connect \X_BFA \opcode_in [20:18] - connect \X_BF \opcode_in [25:23] - connect \X_A \opcode_in [25] - connect \LDST_SPR \opcode_in [20:11] - connect \LDST_MB \opcode_in [10:6] - connect \LDST_ME \opcode_in [5:1] - connect \LDST_SH \opcode_in [15:11] - connect \LDST_BC \opcode_in [10:6] - connect \LDST_TO \opcode_in [25:21] - connect \LDST_DS \opcode_in [15:2] - connect \LDST_D \opcode_in [15:0] - connect \LDST_BH \opcode_in [12:11] - connect \LDST_BI \opcode_in [20:16] - connect \LDST_BO \opcode_in [25:21] - connect \LDST_FXM \opcode_in [19:12] - connect \LDST_BT \opcode_in [25:21] - connect \LDST_BA \opcode_in [20:16] - connect \LDST_BB \opcode_in [15:11] - connect \LDST_CR \opcode_in [10:1] - connect \LDST_BF \opcode_in [25:23] - connect \LDST_BD \opcode_in [15:2] - connect \LDST_OE \opcode_in [10] - connect \LDST_Rc \opcode_in [0] - connect \LDST_AA \opcode_in [1] - connect \LDST_LK \opcode_in [0] - connect \LDST_LI \opcode_in [25:2] - connect \LDST_ME32 \opcode_in [5:1] - connect \LDST_MB32 \opcode_in [10:6] - connect \LDST_sh { \opcode_in [1] \opcode_in [15:11] } - connect \LDST_SH32 \opcode_in [15:11] - connect \LDST_L \opcode_in [21] - connect \LDST_UI \opcode_in [15:0] - connect \LDST_SI \opcode_in [15:0] - connect \LDST_RB \opcode_in [15:11] - connect \LDST_RA \opcode_in [20:16] - connect \LDST_RT \opcode_in [25:21] - connect \LDST_RS \opcode_in [25:21] - connect \opcode_in \$1 - connect \LDST_dec62_opcode_in \opcode_in - connect \LDST_dec58_opcode_in \opcode_in - connect \LDST_dec31_opcode_in \opcode_in - connect \opcode_switch \opcode_in [31:26] -end -attribute \src "issuer_ls180.v:65056.1-70988.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec" -attribute \generator "nMigen" -module \dec$202 - attribute \src "issuer_ls180.v:67249.3-67387.6" - wire width 8 $0\asmcode[7:0] - attribute \src "issuer_ls180.v:69234.3-69375.6" - wire $0\br[0:0] - attribute \src "issuer_ls180.v:67956.3-68097.6" - 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 23 \BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 29 \BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 \BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 3 \BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 2 \BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 28 \BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 27 \BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 25 \BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 10 \CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 \D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 \DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 output 26 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 24 \LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire output 11 \LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire output 22 \OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 19 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 20 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 17 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 18 \RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire output 21 \Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 \SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 10 output 30 \SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 \UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 output 33 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 output 34 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 output 31 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 output 32 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire \Z23_Rc - attribute \src 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"RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 3 \rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 6 \sh - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 16 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" - cell $mux $ternary$issuer_ls180.v:67113$3472 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $ternary$issuer_ls180.v:67113$3472_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:67114.9-67140.4" - cell \dec19 \dec19 - connect \dec19_asmcode \dec19_dec19_asmcode - connect \dec19_br \dec19_dec19_br - connect \dec19_cr_in \dec19_dec19_cr_in - connect \dec19_cr_out \dec19_dec19_cr_out - connect \dec19_cry_in \dec19_dec19_cry_in - connect \dec19_cry_out \dec19_dec19_cry_out - connect \dec19_form \dec19_dec19_form - connect \dec19_function_unit \dec19_dec19_function_unit - connect \dec19_in1_sel \dec19_dec19_in1_sel - connect \dec19_in2_sel \dec19_dec19_in2_sel - connect \dec19_in3_sel \dec19_dec19_in3_sel - connect \dec19_internal_op \dec19_dec19_internal_op - connect \dec19_inv_a \dec19_dec19_inv_a - connect \dec19_inv_out \dec19_dec19_inv_out - connect \dec19_is_32b \dec19_dec19_is_32b - connect \dec19_ldst_len \dec19_dec19_ldst_len - connect \dec19_lk \dec19_dec19_lk - connect \dec19_out_sel \dec19_dec19_out_sel - connect \dec19_rc_sel \dec19_dec19_rc_sel - connect \dec19_rsrv \dec19_dec19_rsrv - connect \dec19_sgl_pipe \dec19_dec19_sgl_pipe - connect \dec19_sgn \dec19_dec19_sgn - connect \dec19_sgn_ext \dec19_dec19_sgn_ext - connect \dec19_upd \dec19_dec19_upd - connect \opcode_in \dec19_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:67141.9-67167.4" - cell \dec30 \dec30 - connect \dec30_asmcode \dec30_dec30_asmcode - connect \dec30_br \dec30_dec30_br - connect \dec30_cr_in \dec30_dec30_cr_in - connect \dec30_cr_out \dec30_dec30_cr_out - connect \dec30_cry_in \dec30_dec30_cry_in - connect \dec30_cry_out \dec30_dec30_cry_out - connect \dec30_form \dec30_dec30_form - connect \dec30_function_unit \dec30_dec30_function_unit - connect \dec30_in1_sel \dec30_dec30_in1_sel - connect \dec30_in2_sel \dec30_dec30_in2_sel - connect \dec30_in3_sel \dec30_dec30_in3_sel - connect \dec30_internal_op \dec30_dec30_internal_op - connect \dec30_inv_a \dec30_dec30_inv_a - connect \dec30_inv_out \dec30_dec30_inv_out - connect \dec30_is_32b \dec30_dec30_is_32b - connect \dec30_ldst_len \dec30_dec30_ldst_len - connect \dec30_lk \dec30_dec30_lk - connect \dec30_out_sel \dec30_dec30_out_sel - connect \dec30_rc_sel \dec30_dec30_rc_sel - connect \dec30_rsrv \dec30_dec30_rsrv - connect \dec30_sgl_pipe \dec30_dec30_sgl_pipe - connect \dec30_sgn \dec30_dec30_sgn - connect \dec30_sgn_ext \dec30_dec30_sgn_ext - connect \dec30_upd \dec30_dec30_upd - connect \opcode_in \dec30_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:67168.9-67194.4" - cell \dec31 \dec31 - connect \dec31_asmcode \dec31_dec31_asmcode - connect \dec31_br \dec31_dec31_br - connect \dec31_cr_in \dec31_dec31_cr_in - connect \dec31_cr_out \dec31_dec31_cr_out - connect \dec31_cry_in \dec31_dec31_cry_in - connect \dec31_cry_out \dec31_dec31_cry_out - connect \dec31_form \dec31_dec31_form - connect \dec31_function_unit \dec31_dec31_function_unit - connect \dec31_in1_sel \dec31_dec31_in1_sel - connect \dec31_in2_sel \dec31_dec31_in2_sel - connect \dec31_in3_sel \dec31_dec31_in3_sel - connect \dec31_internal_op \dec31_dec31_internal_op - connect \dec31_inv_a \dec31_dec31_inv_a - connect \dec31_inv_out \dec31_dec31_inv_out - connect \dec31_is_32b \dec31_dec31_is_32b - connect \dec31_ldst_len \dec31_dec31_ldst_len - connect \dec31_lk \dec31_dec31_lk - connect \dec31_out_sel \dec31_dec31_out_sel - connect \dec31_rc_sel \dec31_dec31_rc_sel - connect \dec31_rsrv \dec31_dec31_rsrv - connect \dec31_sgl_pipe \dec31_dec31_sgl_pipe - connect \dec31_sgn \dec31_dec31_sgn - connect \dec31_sgn_ext \dec31_dec31_sgn_ext - connect \dec31_upd \dec31_dec31_upd - connect \opcode_in \dec31_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:67195.9-67221.4" - cell \dec58 \dec58 - connect \dec58_asmcode \dec58_dec58_asmcode - connect \dec58_br \dec58_dec58_br - connect \dec58_cr_in \dec58_dec58_cr_in - connect \dec58_cr_out \dec58_dec58_cr_out - connect \dec58_cry_in \dec58_dec58_cry_in - connect \dec58_cry_out \dec58_dec58_cry_out - connect \dec58_form \dec58_dec58_form - connect \dec58_function_unit \dec58_dec58_function_unit - connect \dec58_in1_sel \dec58_dec58_in1_sel - connect \dec58_in2_sel \dec58_dec58_in2_sel - connect \dec58_in3_sel \dec58_dec58_in3_sel - connect \dec58_internal_op \dec58_dec58_internal_op - connect \dec58_inv_a \dec58_dec58_inv_a - connect \dec58_inv_out \dec58_dec58_inv_out - connect \dec58_is_32b \dec58_dec58_is_32b - connect \dec58_ldst_len \dec58_dec58_ldst_len - connect \dec58_lk \dec58_dec58_lk - connect \dec58_out_sel \dec58_dec58_out_sel - connect \dec58_rc_sel \dec58_dec58_rc_sel - connect \dec58_rsrv \dec58_dec58_rsrv - connect \dec58_sgl_pipe \dec58_dec58_sgl_pipe - connect \dec58_sgn \dec58_dec58_sgn - connect \dec58_sgn_ext \dec58_dec58_sgn_ext - connect \dec58_upd \dec58_dec58_upd - connect \opcode_in \dec58_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:67222.9-67248.4" - cell \dec62 \dec62 - connect \dec62_asmcode \dec62_dec62_asmcode - connect \dec62_br \dec62_dec62_br - connect \dec62_cr_in \dec62_dec62_cr_in - connect \dec62_cr_out \dec62_dec62_cr_out - connect \dec62_cry_in \dec62_dec62_cry_in - connect \dec62_cry_out \dec62_dec62_cry_out - connect \dec62_form \dec62_dec62_form - connect \dec62_function_unit \dec62_dec62_function_unit - connect \dec62_in1_sel \dec62_dec62_in1_sel - connect \dec62_in2_sel \dec62_dec62_in2_sel - connect \dec62_in3_sel \dec62_dec62_in3_sel - connect \dec62_internal_op \dec62_dec62_internal_op - connect \dec62_inv_a \dec62_dec62_inv_a - connect \dec62_inv_out \dec62_dec62_inv_out - connect \dec62_is_32b \dec62_dec62_is_32b - connect \dec62_ldst_len \dec62_dec62_ldst_len - connect \dec62_lk \dec62_dec62_lk - connect \dec62_out_sel \dec62_dec62_out_sel - connect \dec62_rc_sel \dec62_dec62_rc_sel - connect \dec62_rsrv \dec62_dec62_rsrv - connect \dec62_sgl_pipe \dec62_dec62_sgl_pipe - connect \dec62_sgn \dec62_dec62_sgn - connect \dec62_sgn_ext \dec62_dec62_sgn_ext - connect \dec62_upd \dec62_dec62_upd - connect \opcode_in \dec62_opcode_in - end - attribute \src "issuer_ls180.v:65057.7-65057.20" - process $proc$issuer_ls180.v:65057$3497 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:67249.3-67387.6" - process $proc$issuer_ls180.v:67249$3473 - assign { } { } - assign { } { } - assign { } { } - assign $0\asmcode[7:0] $2\asmcode[7:0] - attribute \src "issuer_ls180.v:67250.5-67250.29" - switch \initial - attribute \src "issuer_ls180.v:67250.9-67250.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\asmcode[7:0] \dec19_dec19_asmcode - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\asmcode[7:0] \dec30_dec30_asmcode - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\asmcode[7:0] \dec31_dec31_asmcode - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\asmcode[7:0] \dec58_dec58_asmcode - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\asmcode[7:0] \dec62_dec62_asmcode - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\asmcode[7:0] 8'00000111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\asmcode[7:0] 8'00001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\asmcode[7:0] 8'00000110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\asmcode[7:0] 8'00001001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\asmcode[7:0] 8'00010001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\asmcode[7:0] 8'00010010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\asmcode[7:0] 8'00010100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\asmcode[7:0] 8'00010101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\asmcode[7:0] 8'00011101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\asmcode[7:0] 8'00011111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\asmcode[7:0] 8'01001110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\asmcode[7:0] 8'01001111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\asmcode[7:0] 8'01011000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\asmcode[7:0] 8'01011010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\asmcode[7:0] 8'01011110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\asmcode[7:0] 8'01011111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\asmcode[7:0] 8'01100111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\asmcode[7:0] 8'01101001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\asmcode[7:0] 8'10000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\asmcode[7:0] 8'10001010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\asmcode[7:0] 8'10001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\asmcode[7:0] 8'10011000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\asmcode[7:0] 8'10011001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\asmcode[7:0] 8'10011010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\asmcode[7:0] 8'10100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\asmcode[7:0] 8'10101001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\asmcode[7:0] 8'10110010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\asmcode[7:0] 8'10110101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\asmcode[7:0] 8'10111000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\asmcode[7:0] 8'10111011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\asmcode[7:0] 8'11000011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\asmcode[7:0] 8'11001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\asmcode[7:0] 8'11001111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\asmcode[7:0] 8'11010001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\asmcode[7:0] 8'11010010 - case - assign $1\asmcode[7:0] 8'00000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\asmcode[7:0] 8'00010011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\asmcode[7:0] 8'10000110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\asmcode[7:0] 8'10011100 - case - assign $2\asmcode[7:0] $1\asmcode[7:0] - end - sync always - update \asmcode $0\asmcode[7:0] - end - attribute \src "issuer_ls180.v:67388.3-67529.6" - process $proc$issuer_ls180.v:67388$3474 - assign { } { } - assign { } { } - assign { } { } - assign $0\in1_sel[2:0] $2\in1_sel[2:0] - attribute \src "issuer_ls180.v:67389.5-67389.29" - switch \initial - attribute \src "issuer_ls180.v:67389.9-67389.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\in1_sel[2:0] \dec19_dec19_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\in1_sel[2:0] \dec30_dec30_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\in1_sel[2:0] \dec31_dec31_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\in1_sel[2:0] \dec58_dec58_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\in1_sel[2:0] \dec62_dec62_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\in1_sel[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\in1_sel[2:0] 3'100 - case - assign $1\in1_sel[2:0] 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\in1_sel[2:0] 3'000 - case - assign $2\in1_sel[2:0] $1\in1_sel[2:0] - end - sync always - update \in1_sel $0\in1_sel[2:0] - end - attribute \src "issuer_ls180.v:67530.3-67671.6" - process $proc$issuer_ls180.v:67530$3475 - assign { } { } - assign { } { } - assign { } { } - assign $0\in2_sel[3:0] $2\in2_sel[3:0] - attribute \src "issuer_ls180.v:67531.5-67531.29" - switch \initial - attribute \src "issuer_ls180.v:67531.9-67531.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\in2_sel[3:0] \dec19_dec19_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\in2_sel[3:0] \dec30_dec30_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\in2_sel[3:0] \dec31_dec31_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\in2_sel[3:0] \dec58_dec58_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\in2_sel[3:0] \dec62_dec62_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\in2_sel[3:0] 4'0101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\in2_sel[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\in2_sel[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\in2_sel[3:0] 4'0110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\in2_sel[3:0] 4'0111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\in2_sel[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\in2_sel[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\in2_sel[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\in2_sel[3:0] 4'1011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\in2_sel[3:0] 4'1011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\in2_sel[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\in2_sel[3:0] 4'0100 - case - assign $1\in2_sel[3:0] 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\in2_sel[3:0] 4'0000 - case - assign $2\in2_sel[3:0] $1\in2_sel[3:0] - end - sync always - update \in2_sel $0\in2_sel[3:0] - end - attribute \src "issuer_ls180.v:67672.3-67813.6" - process $proc$issuer_ls180.v:67672$3476 - assign { } { } - assign { } { } - assign { } { } - assign $0\in3_sel[1:0] $2\in3_sel[1:0] - attribute \src "issuer_ls180.v:67673.5-67673.29" - switch \initial - attribute \src "issuer_ls180.v:67673.9-67673.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\in3_sel[1:0] \dec19_dec19_in3_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\in3_sel[1:0] \dec30_dec30_in3_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\in3_sel[1:0] \dec31_dec31_in3_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\in3_sel[1:0] \dec58_dec58_in3_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\in3_sel[1:0] \dec62_dec62_in3_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - case - assign $1\in3_sel[1:0] 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\in3_sel[1:0] 2'00 - case - assign $2\in3_sel[1:0] $1\in3_sel[1:0] - end - sync always - update \in3_sel $0\in3_sel[1:0] - end - attribute \src "issuer_ls180.v:67814.3-67955.6" - process $proc$issuer_ls180.v:67814$3477 - assign { } { } - assign { } { } - assign { } { } - assign $0\out_sel[1:0] $2\out_sel[1:0] - attribute \src "issuer_ls180.v:67815.5-67815.29" - switch \initial - attribute \src "issuer_ls180.v:67815.9-67815.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\out_sel[1:0] \dec19_dec19_out_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\out_sel[1:0] \dec30_dec30_out_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\out_sel[1:0] \dec31_dec31_out_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\out_sel[1:0] \dec58_dec58_out_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\out_sel[1:0] \dec62_dec62_out_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\out_sel[1:0] 2'11 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\out_sel[1:0] 2'10 - case - assign $1\out_sel[1:0] 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\out_sel[1:0] 2'01 - case - assign $2\out_sel[1:0] $1\out_sel[1:0] - end - sync always - update \out_sel $0\out_sel[1:0] - end - attribute \src "issuer_ls180.v:67956.3-68097.6" - process $proc$issuer_ls180.v:67956$3478 - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_in[2:0] $2\cr_in[2:0] - attribute \src "issuer_ls180.v:67957.5-67957.29" - switch \initial - attribute \src "issuer_ls180.v:67957.9-67957.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\cr_in[2:0] \dec19_dec19_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\cr_in[2:0] \dec30_dec30_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\cr_in[2:0] \dec31_dec31_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\cr_in[2:0] \dec58_dec58_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\cr_in[2:0] \dec62_dec62_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\cr_in[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\cr_in[2:0] 3'000 - case - assign $1\cr_in[2:0] 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\cr_in[2:0] 3'000 - case - assign $2\cr_in[2:0] $1\cr_in[2:0] - end - sync always - update \cr_in $0\cr_in[2:0] - end - attribute \src "issuer_ls180.v:68098.3-68239.6" - process $proc$issuer_ls180.v:68098$3479 - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_out[2:0] $2\cr_out[2:0] - attribute \src "issuer_ls180.v:68099.5-68099.29" - switch \initial - attribute \src "issuer_ls180.v:68099.9-68099.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\cr_out[2:0] \dec19_dec19_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\cr_out[2:0] \dec30_dec30_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\cr_out[2:0] \dec31_dec31_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\cr_out[2:0] \dec58_dec58_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\cr_out[2:0] \dec62_dec62_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\cr_out[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\cr_out[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\cr_out[2:0] 3'000 - case - assign $1\cr_out[2:0] 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\cr_out[2:0] 3'000 - case - assign $2\cr_out[2:0] $1\cr_out[2:0] - end - sync always - update \cr_out $0\cr_out[2:0] - end - attribute \src "issuer_ls180.v:68240.3-68381.6" - process $proc$issuer_ls180.v:68240$3480 - assign { } { } - assign { } { } - assign { } { } - assign $0\ldst_len[3:0] $2\ldst_len[3:0] - attribute \src "issuer_ls180.v:68241.5-68241.29" - switch \initial - attribute \src "issuer_ls180.v:68241.9-68241.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ldst_len[3:0] \dec19_dec19_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\ldst_len[3:0] \dec30_dec30_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ldst_len[3:0] \dec31_dec31_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\ldst_len[3:0] \dec58_dec58_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\ldst_len[3:0] \dec62_dec62_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - case - assign $1\ldst_len[3:0] 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\ldst_len[3:0] 4'0000 - case - assign $2\ldst_len[3:0] $1\ldst_len[3:0] - end - sync always - update \ldst_len $0\ldst_len[3:0] - end - attribute \src "issuer_ls180.v:68382.3-68523.6" - process $proc$issuer_ls180.v:68382$3481 - assign { } { } - assign { } { } - assign { } { } - assign $0\upd[1:0] $2\upd[1:0] - attribute \src "issuer_ls180.v:68383.5-68383.29" - switch \initial - attribute \src "issuer_ls180.v:68383.9-68383.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\upd[1:0] \dec19_dec19_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\upd[1:0] \dec30_dec30_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\upd[1:0] \dec31_dec31_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\upd[1:0] \dec58_dec58_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\upd[1:0] \dec62_dec62_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\upd[1:0] 2'00 - case - assign $1\upd[1:0] 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\upd[1:0] 2'00 - case - assign $2\upd[1:0] $1\upd[1:0] - end - sync always - update \upd $0\upd[1:0] - end - attribute \src "issuer_ls180.v:68524.3-68665.6" - process $proc$issuer_ls180.v:68524$3482 - assign { } { } - assign { } { } - assign { } { } - assign $0\rc_sel[1:0] $2\rc_sel[1:0] - attribute \src "issuer_ls180.v:68525.5-68525.29" - switch \initial - attribute \src "issuer_ls180.v:68525.9-68525.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\rc_sel[1:0] \dec19_dec19_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\rc_sel[1:0] \dec30_dec30_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\rc_sel[1:0] \dec31_dec31_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\rc_sel[1:0] \dec58_dec58_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\rc_sel[1:0] \dec62_dec62_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\rc_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\rc_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\rc_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - case - assign $1\rc_sel[1:0] 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\rc_sel[1:0] 2'00 - case - assign $2\rc_sel[1:0] $1\rc_sel[1:0] - end - sync always - update \rc_sel $0\rc_sel[1:0] - end - attribute \src "issuer_ls180.v:68666.3-68807.6" - process $proc$issuer_ls180.v:68666$3483 - assign { } { } - assign { } { } - assign { } { } - assign $0\cry_in[1:0] $2\cry_in[1:0] - attribute \src "issuer_ls180.v:68667.5-68667.29" - switch \initial - attribute \src "issuer_ls180.v:68667.9-68667.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\cry_in[1:0] \dec19_dec19_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\cry_in[1:0] \dec30_dec30_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\cry_in[1:0] \dec31_dec31_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\cry_in[1:0] \dec58_dec58_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\cry_in[1:0] \dec62_dec62_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\cry_in[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\cry_in[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\cry_in[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\cry_in[1:0] 2'00 - case - assign $1\cry_in[1:0] 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\cry_in[1:0] 2'00 - case - assign $2\cry_in[1:0] $1\cry_in[1:0] - end - sync always - update \cry_in $0\cry_in[1:0] - end - attribute \src "issuer_ls180.v:68808.3-68949.6" - process $proc$issuer_ls180.v:68808$3484 - assign { } { } - assign { } { } - assign { } { } - assign $0\inv_a[0:0] $2\inv_a[0:0] - attribute \src "issuer_ls180.v:68809.5-68809.29" - switch \initial - attribute \src "issuer_ls180.v:68809.9-68809.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\inv_a[0:0] \dec19_dec19_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\inv_a[0:0] \dec30_dec30_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\inv_a[0:0] \dec31_dec31_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\inv_a[0:0] \dec58_dec58_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\inv_a[0:0] \dec62_dec62_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\inv_a[0:0] 1'0 - case - assign $1\inv_a[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\inv_a[0:0] 1'0 - case - assign $2\inv_a[0:0] $1\inv_a[0:0] - end - sync always - update \inv_a $0\inv_a[0:0] - end - attribute \src "issuer_ls180.v:68950.3-69091.6" - process $proc$issuer_ls180.v:68950$3485 - assign { } { } - assign { } { } - assign { } { } - assign $0\inv_out[0:0] $2\inv_out[0:0] - attribute \src "issuer_ls180.v:68951.5-68951.29" - switch \initial - attribute \src "issuer_ls180.v:68951.9-68951.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\inv_out[0:0] \dec19_dec19_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\inv_out[0:0] \dec30_dec30_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\inv_out[0:0] \dec31_dec31_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\inv_out[0:0] \dec58_dec58_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\inv_out[0:0] \dec62_dec62_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\inv_out[0:0] 1'0 - case - assign $1\inv_out[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\inv_out[0:0] 1'0 - case - assign $2\inv_out[0:0] $1\inv_out[0:0] - end - sync always - update \inv_out $0\inv_out[0:0] - end - attribute \src "issuer_ls180.v:69092.3-69233.6" - process $proc$issuer_ls180.v:69092$3486 - assign { } { } - assign { } { } - assign { } { } - assign $0\cry_out[0:0] $2\cry_out[0:0] - attribute \src "issuer_ls180.v:69093.5-69093.29" - switch \initial - attribute \src "issuer_ls180.v:69093.9-69093.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\cry_out[0:0] \dec19_dec19_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\cry_out[0:0] \dec30_dec30_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\cry_out[0:0] \dec31_dec31_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\cry_out[0:0] \dec58_dec58_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\cry_out[0:0] \dec62_dec62_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\cry_out[0:0] 1'0 - case - assign $1\cry_out[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\cry_out[0:0] 1'0 - case - assign $2\cry_out[0:0] $1\cry_out[0:0] - end - sync always - update \cry_out $0\cry_out[0:0] - end - attribute \src "issuer_ls180.v:69234.3-69375.6" - process $proc$issuer_ls180.v:69234$3487 - assign { } { } - assign { } { } - assign { } { } - assign $0\br[0:0] $2\br[0:0] - attribute \src "issuer_ls180.v:69235.5-69235.29" - switch \initial - attribute \src "issuer_ls180.v:69235.9-69235.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\br[0:0] \dec19_dec19_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\br[0:0] \dec30_dec30_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\br[0:0] \dec31_dec31_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\br[0:0] \dec58_dec58_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\br[0:0] \dec62_dec62_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\br[0:0] 1'0 - case - assign $1\br[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\br[0:0] 1'0 - case - assign $2\br[0:0] $1\br[0:0] - end - sync always - update \br $0\br[0:0] - end - attribute \src "issuer_ls180.v:69376.3-69517.6" - process $proc$issuer_ls180.v:69376$3488 - assign { } { } - assign { } { } - assign { } { } - assign $0\sgn_ext[0:0] $2\sgn_ext[0:0] - attribute \src "issuer_ls180.v:69377.5-69377.29" - switch \initial - attribute \src "issuer_ls180.v:69377.9-69377.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\sgn_ext[0:0] \dec19_dec19_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\sgn_ext[0:0] \dec30_dec30_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\sgn_ext[0:0] \dec31_dec31_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\sgn_ext[0:0] \dec58_dec58_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\sgn_ext[0:0] \dec62_dec62_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\sgn_ext[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\sgn_ext[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - case - assign $1\sgn_ext[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\sgn_ext[0:0] 1'0 - case - assign $2\sgn_ext[0:0] $1\sgn_ext[0:0] - end - sync always - update \sgn_ext $0\sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:69518.3-69659.6" - process $proc$issuer_ls180.v:69518$3489 - assign { } { } - assign { } { } - assign { } { } - assign $0\rsrv[0:0] $2\rsrv[0:0] - attribute \src "issuer_ls180.v:69519.5-69519.29" - switch \initial - attribute \src "issuer_ls180.v:69519.9-69519.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\rsrv[0:0] \dec19_dec19_rsrv - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\rsrv[0:0] \dec30_dec30_rsrv - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\rsrv[0:0] \dec31_dec31_rsrv - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\rsrv[0:0] \dec58_dec58_rsrv - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\rsrv[0:0] \dec62_dec62_rsrv - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\rsrv[0:0] 1'0 - case - assign $1\rsrv[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\rsrv[0:0] 1'0 - case - assign $2\rsrv[0:0] $1\rsrv[0:0] - end - sync always - update \rsrv $0\rsrv[0:0] - end - attribute \src "issuer_ls180.v:69660.3-69801.6" - process $proc$issuer_ls180.v:69660$3490 - assign { } { } - assign { } { } - assign { } { } - assign $0\is_32b[0:0] $2\is_32b[0:0] - attribute \src "issuer_ls180.v:69661.5-69661.29" - switch \initial - attribute \src "issuer_ls180.v:69661.9-69661.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\is_32b[0:0] \dec19_dec19_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\is_32b[0:0] \dec30_dec30_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\is_32b[0:0] \dec31_dec31_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\is_32b[0:0] \dec58_dec58_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\is_32b[0:0] \dec62_dec62_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\is_32b[0:0] 1'0 - case - assign $1\is_32b[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\is_32b[0:0] 1'0 - case - assign $2\is_32b[0:0] $1\is_32b[0:0] - end - sync always - update \is_32b $0\is_32b[0:0] - end - attribute \src "issuer_ls180.v:69802.3-69943.6" - process $proc$issuer_ls180.v:69802$3491 - assign { } { } - assign { } { } - assign { } { } - assign $0\sgn[0:0] $2\sgn[0:0] - attribute \src "issuer_ls180.v:69803.5-69803.29" - switch \initial - attribute \src "issuer_ls180.v:69803.9-69803.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\sgn[0:0] \dec19_dec19_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\sgn[0:0] \dec30_dec30_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\sgn[0:0] \dec31_dec31_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\sgn[0:0] \dec58_dec58_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\sgn[0:0] \dec62_dec62_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\sgn[0:0] 1'0 - case - assign $1\sgn[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\sgn[0:0] 1'0 - case - assign $2\sgn[0:0] $1\sgn[0:0] - end - sync always - update \sgn $0\sgn[0:0] - end - attribute \src "issuer_ls180.v:69944.3-70085.6" - process $proc$issuer_ls180.v:69944$3492 - assign { } { } - assign { } { } - assign { } { } - assign $0\lk[0:0] $2\lk[0:0] - attribute \src "issuer_ls180.v:69945.5-69945.29" - switch \initial - attribute \src "issuer_ls180.v:69945.9-69945.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\lk[0:0] \dec19_dec19_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\lk[0:0] \dec30_dec30_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\lk[0:0] \dec31_dec31_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\lk[0:0] \dec58_dec58_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\lk[0:0] \dec62_dec62_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\lk[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\lk[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\lk[0:0] 1'0 - case - assign $1\lk[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\lk[0:0] 1'0 - case - assign $2\lk[0:0] $1\lk[0:0] - end - sync always - update \lk $0\lk[0:0] - end - attribute \src "issuer_ls180.v:70086.3-70227.6" - process $proc$issuer_ls180.v:70086$3493 - assign { } { } - assign { } { } - assign { } { } - assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0] - attribute \src "issuer_ls180.v:70087.5-70087.29" - switch \initial - attribute \src "issuer_ls180.v:70087.9-70087.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\sgl_pipe[0:0] \dec19_dec19_sgl_pipe - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\sgl_pipe[0:0] \dec30_dec30_sgl_pipe - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\sgl_pipe[0:0] \dec31_dec31_sgl_pipe - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\sgl_pipe[0:0] \dec58_dec58_sgl_pipe - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\sgl_pipe[0:0] \dec62_dec62_sgl_pipe - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - case - assign $1\sgl_pipe[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\sgl_pipe[0:0] 1'1 - case - assign $2\sgl_pipe[0:0] $1\sgl_pipe[0:0] - end - sync always - update \sgl_pipe $0\sgl_pipe[0:0] - end - attribute \src "issuer_ls180.v:70228.3-70369.6" - process $proc$issuer_ls180.v:70228$3494 - assign { } { } - assign { } { } - assign { } { } - assign $0\function_unit[11:0] $2\function_unit[11:0] - attribute \src "issuer_ls180.v:70229.5-70229.29" - switch \initial - attribute \src "issuer_ls180.v:70229.9-70229.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\function_unit[11:0] \dec19_dec19_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\function_unit[11:0] \dec30_dec30_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\function_unit[11:0] \dec31_dec31_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\function_unit[11:0] \dec58_dec58_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\function_unit[11:0] \dec62_dec62_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\function_unit[11:0] 12'000010000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\function_unit[11:0] 12'000000100000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\function_unit[11:0] 12'000000100000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\function_unit[11:0] 12'000100000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\function_unit[11:0] 12'000010000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\function_unit[11:0] 12'000010000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\function_unit[11:0] 12'000000010000 - case - assign $1\function_unit[11:0] 12'000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\function_unit[11:0] 12'000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\function_unit[11:0] 12'000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\function_unit[11:0] 12'000000000000 - case - assign $2\function_unit[11:0] $1\function_unit[11:0] - end - sync always - update \function_unit $0\function_unit[11:0] - end - attribute \src "issuer_ls180.v:70370.3-70511.6" - process $proc$issuer_ls180.v:70370$3495 - assign { } { } - assign { } { } - assign { } { } - assign $0\internal_op[6:0] $2\internal_op[6:0] - attribute \src "issuer_ls180.v:70371.5-70371.29" - switch \initial - attribute \src "issuer_ls180.v:70371.9-70371.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\internal_op[6:0] \dec19_dec19_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\internal_op[6:0] \dec30_dec30_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\internal_op[6:0] \dec31_dec31_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\internal_op[6:0] \dec58_dec58_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\internal_op[6:0] \dec62_dec62_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\internal_op[6:0] 7'1001001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\internal_op[6:0] 7'0000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\internal_op[6:0] 7'0000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\internal_op[6:0] 7'0000110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\internal_op[6:0] 7'0000111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\internal_op[6:0] 7'0001010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\internal_op[6:0] 7'0001010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\internal_op[6:0] 7'0110010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\internal_op[6:0] 7'0110101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\internal_op[6:0] 7'0110101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\internal_op[6:0] 7'0111000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\internal_op[6:0] 7'0111000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\internal_op[6:0] 7'0111000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\internal_op[6:0] 7'0111111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\internal_op[6:0] 7'0111111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\internal_op[6:0] 7'1000011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\internal_op[6:0] 7'1000011 - case - assign $1\internal_op[6:0] 7'0000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\internal_op[6:0] 7'0000101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\internal_op[6:0] 7'0000001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\internal_op[6:0] 7'1000100 - case - assign $2\internal_op[6:0] $1\internal_op[6:0] - end - sync always - update \internal_op $0\internal_op[6:0] - end - attribute \src "issuer_ls180.v:70512.3-70653.6" - process $proc$issuer_ls180.v:70512$3496 - assign { } { } - assign { } { } - assign { } { } - assign $0\form[4:0] $2\form[4:0] - attribute \src "issuer_ls180.v:70513.5-70513.29" - switch \initial - attribute \src "issuer_ls180.v:70513.9-70513.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\form[4:0] \dec19_dec19_form - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\form[4:0] \dec30_dec30_form - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\form[4:0] \dec31_dec31_form - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\form[4:0] \dec58_dec58_form - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\form[4:0] \dec62_dec62_form - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\form[4:0] 5'00011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\form[4:0] 5'00010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\form[4:0] 5'00010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\form[4:0] 5'00001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\form[4:0] 5'00010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\form[4:0] 5'10011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\form[4:0] 5'10011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\form[4:0] 5'10011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\form[4:0] 5'00100 - case - assign $1\form[4:0] 5'00000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\form[4:0] 5'00000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\form[4:0] 5'00100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\form[4:0] 5'00000 - case - assign $2\form[4:0] $1\form[4:0] - end - sync always - update \form $0\form[4:0] - end - connect \$2 $ternary$issuer_ls180.v:67113$3472_Y - connect \VC_XO \opcode_in [9:0] - connect \VC_VRT \opcode_in [25:21] - connect \VC_VRB \opcode_in [15:11] - connect \VC_VRA \opcode_in [20:16] - connect \VC_Rc \opcode_in [10] - connect \XS_XO \opcode_in [10:2] - connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } - connect \XS_RS \opcode_in [25:21] - connect \XS_Rc \opcode_in [0] - connect \XS_RA \opcode_in [20:16] - connect \VA_XO \opcode_in [5:0] - connect \VA_VRT \opcode_in [25:21] - connect \VA_VRC \opcode_in [10:6] - connect \VA_VRB \opcode_in [15:11] - connect \VA_VRA \opcode_in [20:16] - connect \VA_SHB \opcode_in [9:6] - connect \VA_RT \opcode_in [25:21] - connect \VA_RC \opcode_in [10:6] - connect \VA_RB \opcode_in [15:11] - connect \VA_RA \opcode_in [20:16] - connect \TX_XO \opcode_in [6:1] - connect \TX_XBI \opcode_in [10:7] - connect \TX_UI \opcode_in [15:11] - connect \TX_RA \opcode_in [20:16] - connect \DQE_XO \opcode_in [1:0] - connect \DQE_RT \opcode_in [25:21] - connect \DQE_RA \opcode_in [20:16] - connect \XO_XO \opcode_in [9:1] - connect \XO_RT \opcode_in [25:21] - connect \XO_Rc \opcode_in [0] - connect \XO_RB \opcode_in [15:11] - connect \XO_RA \opcode_in [20:16] - connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] - connect \MD_XO \opcode_in [4:2] - connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } - connect \MD_RS \opcode_in [25:21] - connect \MD_Rc \opcode_in [0] - connect \MD_RA \opcode_in [20:16] - connect \MD_me \opcode_in [10:5] - connect \MD_mb \opcode_in [10:5] - connect \M_SH \opcode_in [15:11] - connect \M_RS \opcode_in [25:21] - connect \M_Rc \opcode_in [0] - connect \M_RB \opcode_in [15:11] - connect \M_RA \opcode_in [20:16] - connect \M_ME \opcode_in [5:1] - connect \M_MB \opcode_in [10:6] - connect \SC_XO_1 \opcode_in [1:0] - connect \SC_XO \opcode_in [1] - connect \SC_LEV \opcode_in [11:5] - connect \MDS_XO \opcode_in [4:1] - connect \MDS_XBI_1 \opcode_in [10:7] - connect \MDS_XBI \opcode_in [10:7] - connect \MDS_RS \opcode_in [25:21] - connect \MDS_Rc \opcode_in [0] - connect \MDS_RB \opcode_in [15:11] - connect \MDS_RA \opcode_in [20:16] - connect \MDS_me \opcode_in [10:5] - connect \MDS_mb \opcode_in [10:5] - connect \MDS_IS \opcode_in [25:21] - connect \MDS_IB \opcode_in [15:11] - connect \Z23_XO \opcode_in [8:1] - connect \Z23_TE \opcode_in [20:16] - connect \Z23_RMC \opcode_in [10:9] - connect \Z23_Rc \opcode_in [0] - connect \Z23_R \opcode_in [16] - connect \Z23_FRTp \opcode_in [25:21] - connect \Z23_FRT \opcode_in [25:21] - connect \Z23_FRBp \opcode_in [15:11] - connect \Z23_FRB \opcode_in [15:11] - connect \Z23_FRAp \opcode_in [20:16] - connect \Z23_FRA \opcode_in [20:16] - connect \XFL_XO \opcode_in [10:1] - connect \XFL_W \opcode_in [16] - connect \XFL_Rc \opcode_in [0] - connect \XFL_L \opcode_in [25] - connect \XFL_FRB \opcode_in [15:11] - connect \XFL_FLM \opcode_in [24:17] - connect \VX_XO_1 \opcode_in [10:0] - connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } - connect \VX_VRT \opcode_in [25:21] - connect \VX_VRB \opcode_in [15:11] - connect \VX_VRA \opcode_in [20:16] - connect \VX_UIM_3 \opcode_in [17:16] - connect \VX_UIM_2 \opcode_in [18:16] - connect \VX_UIM_1 \opcode_in [19:16] - connect \VX_UIM \opcode_in [20:16] - connect \VX_SIM \opcode_in [20:16] - connect \VX_RT \opcode_in [25:21] - connect \VX_RA \opcode_in [20:16] - connect \VX_PS \opcode_in [9] - connect \VX_EO \opcode_in [20:16] - connect \DS_XO \opcode_in [1:0] - connect \DS_VRT \opcode_in [25:21] - connect \DS_VRS \opcode_in [25:21] - connect \DS_RT \opcode_in [25:21] - connect \DS_RSp \opcode_in [25:21] - connect \DS_RS \opcode_in [25:21] - connect \DS_RA \opcode_in [20:16] - connect \DS_FRTp \opcode_in [25:21] - connect \DS_FRSp \opcode_in [25:21] - connect \DS_DS \opcode_in [15:2] - connect \DQ_XO \opcode_in [2:0] - connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_T \opcode_in [25:21] - connect \DQ_TX \opcode_in [3] - connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_S \opcode_in [25:21] - connect \DQ_SX \opcode_in [3] - connect \DQ_RTp \opcode_in [25:21] - connect \DQ_RA \opcode_in [20:16] - connect \DQ_PT \opcode_in [3:0] - connect \DQ_DQ \opcode_in [15:4] - connect \DX_XO \opcode_in [5:1] - connect \DX_RT \opcode_in [25:21] - connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } - connect \DX_d2 \opcode_in [0] - connect \DX_d1 \opcode_in [20:16] - connect \DX_d0 \opcode_in [15:6] - connect \XFX_XO \opcode_in [10:1] - connect \XFX_SPR \opcode_in [20:11] - connect \XFX_RT \opcode_in [25:21] - connect \XFX_RS \opcode_in [25:21] - connect \XFX_FXM \opcode_in [19:12] - connect \XFX_DUIS \opcode_in [20:11] - connect \XFX_DUI \opcode_in [25:21] - connect \XFX_BHRBE \opcode_in [20:11] - connect \EVS_BFA \opcode_in [2:0] - connect \Z22_XO \opcode_in [9:1] - connect \Z22_SH \opcode_in [15:10] - connect \Z22_Rc \opcode_in [0] - connect \Z22_FRTp \opcode_in [25:21] - connect \Z22_FRT \opcode_in [25:21] - connect \Z22_FRAp \opcode_in [20:16] - connect \Z22_FRA \opcode_in [20:16] - connect \Z22_DGM \opcode_in [15:10] - connect \Z22_DCM \opcode_in [15:10] - connect \Z22_BF \opcode_in [25:23] - connect \XX2_XO_1 \opcode_in [10:2] - connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } - connect \XX2_UIM_1 \opcode_in [17:16] - connect \XX2_UIM \opcode_in [19:16] - connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX2_T \opcode_in [25:21] - connect \XX2_TX \opcode_in [0] - connect \XX2_RT \opcode_in [25:21] - connect \XX2_EO \opcode_in [20:16] - connect \XX2_DCMX \opcode_in [22:16] - connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } - connect \XX2_dx \opcode_in [20:16] - connect \XX2_dm \opcode_in [2] - connect \XX2_dc \opcode_in [6] - connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX2_B \opcode_in [15:11] - connect \XX2_BX \opcode_in [1] - connect \XX2_BF \opcode_in [25:23] - connect \D_UI \opcode_in [15:0] - connect \D_TO \opcode_in [25:21] - connect \D_SI \opcode_in [15:0] - connect \D_RT \opcode_in [25:21] - connect \D_RS \opcode_in [25:21] - connect \D_RA \opcode_in [20:16] - connect \D_L \opcode_in [21] - connect \D_FRT \opcode_in [25:21] - connect \D_FRS \opcode_in [25:21] - connect \D_D \opcode_in [15:0] - connect \D_BF \opcode_in [25:23] - connect \A_XO \opcode_in [5:1] - connect \A_RT \opcode_in [25:21] - connect \A_Rc \opcode_in [0] - connect \A_RB \opcode_in [15:11] - connect \A_RA \opcode_in [20:16] - connect \A_FRT \opcode_in [25:21] - connect \A_FRC \opcode_in [10:6] - connect \A_FRB \opcode_in [15:11] - connect \A_FRA \opcode_in [20:16] - connect \A_BC \opcode_in [10:6] - connect \XL_XO \opcode_in [10:1] - connect \XL_S \opcode_in [11] - connect \XL_OC \opcode_in [25:11] - connect \XL_LK \opcode_in [0] - connect \XL_BT \opcode_in [25:21] - connect \XL_BO_1 \opcode_in [25:21] - connect \XL_BO \opcode_in [25:21] - connect \XL_BI \opcode_in [20:16] - connect \XL_BH \opcode_in [12:11] - connect \XL_BFA \opcode_in [20:18] - connect \XL_BF \opcode_in [25:23] - connect \XL_BB \opcode_in [15:11] - connect \XL_BA \opcode_in [20:16] - connect \XX4_XO \opcode_in [5:4] - connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX4_T \opcode_in [25:21] - connect \XX4_TX \opcode_in [0] - connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } - connect \XX4_C \opcode_in [10:6] - connect \XX4_CX \opcode_in [3] - connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX4_B \opcode_in [15:11] - connect \XX4_BX \opcode_in [1] - connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX4_A \opcode_in [20:16] - connect \XX4_AX \opcode_in [2] - connect \XX3_XO_2 \opcode_in [9:1] - connect \XX3_XO_1 \opcode_in [10:3] - connect \XX3_XO \opcode_in [10:7] - connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX3_T \opcode_in [25:21] - connect \XX3_TX \opcode_in [0] - connect \XX3_SHW \opcode_in [9:8] - connect \XX3_Rc \opcode_in [10] - connect \XX3_DM \opcode_in [9:8] - connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX3_B \opcode_in [15:11] - connect \XX3_BX \opcode_in [1] - connect \XX3_BF \opcode_in [25:23] - connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX3_A \opcode_in [20:16] - connect \XX3_AX \opcode_in [2] - connect \I_LK \opcode_in [0] - connect \I_LI \opcode_in [25:2] - connect \I_AA \opcode_in [1] - connect \B_LK \opcode_in [0] - connect \B_BO \opcode_in [25:21] - connect \B_BI \opcode_in [20:16] - connect \B_BD \opcode_in [15:2] - connect \B_AA \opcode_in [1] - connect \X_XO_1 \opcode_in [8:1] - connect \X_XO \opcode_in [10:1] - connect \X_WC \opcode_in [22:21] - connect \X_W \opcode_in [16] - connect \X_VRT \opcode_in [25:21] - connect \X_VRS \opcode_in [25:21] - connect \X_UIM \opcode_in [20:16] - connect \X_U \opcode_in [15:12] - connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \X_TX \opcode_in [0] - connect \X_TO \opcode_in [25:21] - connect \X_TH \opcode_in [25:21] - connect \X_TBR \opcode_in [20:11] - connect \X_T \opcode_in [25:21] - connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } - connect \X_SX \opcode_in [0] - connect \X_SR \opcode_in [19:16] - connect \X_SP \opcode_in [20:19] - connect \X_SI \opcode_in [15:11] - connect \X_SH \opcode_in [15:11] - connect \X_S \opcode_in [25:21] - connect \X_RTp \opcode_in [25:21] - connect \X_RT \opcode_in [25:21] - connect \X_RSp \opcode_in [25:21] - connect \X_RS \opcode_in [25:21] - connect \X_RO \opcode_in [0] - connect \X_RM \opcode_in [12:11] - connect \X_RIC \opcode_in [19:18] - connect \X_Rc \opcode_in [0] - connect \X_RB \opcode_in [15:11] - connect \X_RA \opcode_in [20:16] - connect \X_R_1 \opcode_in [16] - connect \X_R \opcode_in [21] - connect \X_PRS \opcode_in [17] - connect \X_NB \opcode_in [15:11] - connect \X_MO \opcode_in [25:21] - connect \X_L3 \opcode_in [17:16] - connect \X_L1 \opcode_in [16] - connect \X_L \opcode_in [21] - connect \X_L2 \opcode_in [22:21] - connect \X_IMM8 \opcode_in [18:11] - connect \X_IH \opcode_in [23:21] - connect \X_FRTp \opcode_in [25:21] - connect \X_FRT \opcode_in [25:21] - connect \X_FRSp \opcode_in [25:21] - connect \X_FRS \opcode_in [25:21] - connect \X_FRBp \opcode_in [15:11] - connect \X_FRB \opcode_in [15:11] - connect \X_FRAp \opcode_in [20:16] - connect \X_FRA \opcode_in [20:16] - connect \X_FC \opcode_in [15:11] - connect \X_EX \opcode_in [0] - connect \X_EO_1 \opcode_in [20:16] - connect \X_EO \opcode_in [20:19] - connect \X_E_1 \opcode_in [19:16] - connect \X_E \opcode_in [15] - connect \X_DRM \opcode_in [13:11] - connect \X_DCMX \opcode_in [22:16] - connect \X_CT \opcode_in [24:21] - connect \X_BO \opcode_in [25:21] - connect \X_BFA \opcode_in [20:18] - connect \X_BF \opcode_in [25:23] - connect \X_A \opcode_in [25] - connect \SPR \opcode_in [20:11] - connect \MB \opcode_in [10:6] - connect \ME \opcode_in [5:1] - connect \SH \opcode_in [15:11] - connect \BC \opcode_in [10:6] - connect \TO \opcode_in [25:21] - connect \DS \opcode_in [15:2] - connect \D \opcode_in [15:0] - connect \BH \opcode_in [12:11] - connect \BI \opcode_in [20:16] - connect \BO \opcode_in [25:21] - connect \FXM \opcode_in [19:12] - connect \BT \opcode_in [25:21] - connect \BA \opcode_in [20:16] - connect \BB \opcode_in [15:11] - connect \CR \opcode_in [10:1] - connect \BF \opcode_in [25:23] - connect \BD \opcode_in [15:2] - connect \OE \opcode_in [10] - connect \Rc \opcode_in [0] - connect \AA \opcode_in [1] - connect \LK \opcode_in [0] - connect \LI \opcode_in [25:2] - connect \ME32 \opcode_in [5:1] - connect \MB32 \opcode_in [10:6] - connect \sh { \opcode_in [1] \opcode_in [15:11] } - connect \SH32 \opcode_in [15:11] - connect \L \opcode_in [21] - connect \UI \opcode_in [15:0] - connect \SI \opcode_in [15:0] - connect \RB \opcode_in [15:11] - connect \RA \opcode_in [20:16] - connect \RT \opcode_in [25:21] - connect \RS \opcode_in [25:21] - connect \opcode_in \$2 - connect \opcode_switch$1 \opcode_in - connect \dec62_opcode_in \opcode_in - connect \dec58_opcode_in \opcode_in - connect \dec31_opcode_in \opcode_in - connect \dec30_opcode_in \opcode_in - connect \dec19_opcode_in \opcode_in - connect \opcode_switch \opcode_in [31:26] -end -attribute \src "issuer_ls180.v:70992.1-72499.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec19" -attribute \generator "nMigen" -module \dec19 - attribute \src "issuer_ls180.v:71510.3-71561.6" - wire width 8 $0\dec19_asmcode[7:0] - attribute \src "issuer_ls180.v:71718.3-71769.6" - wire $0\dec19_br[0:0] - attribute \src "issuer_ls180.v:72394.3-72445.6" - wire width 3 $0\dec19_cr_in[2:0] - attribute \src "issuer_ls180.v:72446.3-72497.6" - wire width 3 $0\dec19_cr_out[2:0] - attribute \src "issuer_ls180.v:71458.3-71509.6" - wire width 2 $0\dec19_cry_in[1:0] - attribute \src "issuer_ls180.v:71666.3-71717.6" - wire $0\dec19_cry_out[0:0] - attribute \src "issuer_ls180.v:72134.3-72185.6" - wire width 5 $0\dec19_form[4:0] - attribute \src "issuer_ls180.v:71250.3-71301.6" - wire width 12 $0\dec19_function_unit[11:0] - attribute \src "issuer_ls180.v:72186.3-72237.6" - wire width 3 $0\dec19_in1_sel[2:0] - attribute \src "issuer_ls180.v:72238.3-72289.6" - wire width 4 $0\dec19_in2_sel[3:0] - attribute \src "issuer_ls180.v:72290.3-72341.6" - wire width 2 $0\dec19_in3_sel[1:0] - attribute \src "issuer_ls180.v:71822.3-71873.6" - wire width 7 $0\dec19_internal_op[6:0] - attribute \src "issuer_ls180.v:71562.3-71613.6" - wire $0\dec19_inv_a[0:0] - attribute \src "issuer_ls180.v:71614.3-71665.6" - wire $0\dec19_inv_out[0:0] - attribute \src "issuer_ls180.v:71926.3-71977.6" - wire $0\dec19_is_32b[0:0] - attribute \src "issuer_ls180.v:71302.3-71353.6" - wire width 4 $0\dec19_ldst_len[3:0] - attribute \src "issuer_ls180.v:72030.3-72081.6" - wire $0\dec19_lk[0:0] - attribute \src "issuer_ls180.v:72342.3-72393.6" - wire width 2 $0\dec19_out_sel[1:0] - attribute \src "issuer_ls180.v:71406.3-71457.6" - wire width 2 $0\dec19_rc_sel[1:0] - attribute \src "issuer_ls180.v:71874.3-71925.6" - wire $0\dec19_rsrv[0:0] - attribute \src "issuer_ls180.v:72082.3-72133.6" - wire $0\dec19_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:71978.3-72029.6" - wire $0\dec19_sgn[0:0] - attribute \src "issuer_ls180.v:71770.3-71821.6" - wire $0\dec19_sgn_ext[0:0] - attribute \src "issuer_ls180.v:71354.3-71405.6" - wire width 2 $0\dec19_upd[1:0] - attribute \src "issuer_ls180.v:70993.7-70993.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:71510.3-71561.6" - wire width 8 $1\dec19_asmcode[7:0] - attribute \src "issuer_ls180.v:71718.3-71769.6" - wire $1\dec19_br[0:0] - attribute \src "issuer_ls180.v:72394.3-72445.6" - wire width 3 $1\dec19_cr_in[2:0] - attribute \src "issuer_ls180.v:72446.3-72497.6" - wire width 3 $1\dec19_cr_out[2:0] - attribute \src "issuer_ls180.v:71458.3-71509.6" - wire width 2 $1\dec19_cry_in[1:0] - attribute \src "issuer_ls180.v:71666.3-71717.6" - wire $1\dec19_cry_out[0:0] - attribute \src "issuer_ls180.v:72134.3-72185.6" - wire width 5 $1\dec19_form[4:0] - attribute \src "issuer_ls180.v:71250.3-71301.6" - wire width 12 $1\dec19_function_unit[11:0] - attribute \src "issuer_ls180.v:72186.3-72237.6" - wire width 3 $1\dec19_in1_sel[2:0] - attribute \src "issuer_ls180.v:72238.3-72289.6" - wire width 4 $1\dec19_in2_sel[3:0] - attribute \src "issuer_ls180.v:72290.3-72341.6" - wire width 2 $1\dec19_in3_sel[1:0] - attribute \src "issuer_ls180.v:71822.3-71873.6" - wire width 7 $1\dec19_internal_op[6:0] - attribute \src "issuer_ls180.v:71562.3-71613.6" - wire $1\dec19_inv_a[0:0] - attribute \src "issuer_ls180.v:71614.3-71665.6" - wire $1\dec19_inv_out[0:0] - attribute \src "issuer_ls180.v:71926.3-71977.6" - wire $1\dec19_is_32b[0:0] - attribute \src "issuer_ls180.v:71302.3-71353.6" - wire width 4 $1\dec19_ldst_len[3:0] - attribute \src "issuer_ls180.v:72030.3-72081.6" - wire $1\dec19_lk[0:0] - attribute \src "issuer_ls180.v:72342.3-72393.6" - wire width 2 $1\dec19_out_sel[1:0] - attribute \src "issuer_ls180.v:71406.3-71457.6" - wire width 2 $1\dec19_rc_sel[1:0] - attribute \src "issuer_ls180.v:71874.3-71925.6" - wire $1\dec19_rsrv[0:0] - attribute \src "issuer_ls180.v:72082.3-72133.6" - wire $1\dec19_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:71978.3-72029.6" - wire $1\dec19_sgn[0:0] - attribute \src "issuer_ls180.v:71770.3-71821.6" - wire $1\dec19_sgn_ext[0:0] - attribute \src "issuer_ls180.v:71354.3-71405.6" - wire width 2 $1\dec19_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec19_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec19_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec19_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec19_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec19_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec19_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec19_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec19_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec19_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec19_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec19_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec19_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec19_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec19_upd - attribute \src "issuer_ls180.v:70993.7-70993.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 10 \opcode_switch - attribute \src "issuer_ls180.v:70993.7-70993.20" - process $proc$issuer_ls180.v:70993$3522 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:71250.3-71301.6" - process $proc$issuer_ls180.v:71250$3498 - assign { } { } - assign { } { } - assign $0\dec19_function_unit[11:0] $1\dec19_function_unit[11:0] - attribute \src "issuer_ls180.v:71251.5-71251.29" - switch \initial - attribute \src "issuer_ls180.v:71251.9-71251.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000000100000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000000100000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000000100000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000010000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000010000000 - case - assign $1\dec19_function_unit[11:0] 12'000000000000 - end - sync always - update \dec19_function_unit $0\dec19_function_unit[11:0] - end - attribute \src "issuer_ls180.v:71302.3-71353.6" - process $proc$issuer_ls180.v:71302$3499 - assign { } { } - assign { } { } - assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0] - attribute \src "issuer_ls180.v:71303.5-71303.29" - switch \initial - attribute \src "issuer_ls180.v:71303.9-71303.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - case - assign $1\dec19_ldst_len[3:0] 4'0000 - end - sync always - update \dec19_ldst_len $0\dec19_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:71354.3-71405.6" - process $proc$issuer_ls180.v:71354$3500 - assign { } { } - assign { } { } - assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] - attribute \src "issuer_ls180.v:71355.5-71355.29" - switch \initial - attribute \src "issuer_ls180.v:71355.9-71355.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - case - assign $1\dec19_upd[1:0] 2'00 - end - sync always - update \dec19_upd $0\dec19_upd[1:0] - end - attribute \src "issuer_ls180.v:71406.3-71457.6" - process $proc$issuer_ls180.v:71406$3501 - assign { } { } - assign { } { } - assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0] - attribute \src "issuer_ls180.v:71407.5-71407.29" - switch \initial - attribute \src "issuer_ls180.v:71407.9-71407.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - case - assign $1\dec19_rc_sel[1:0] 2'00 - end - sync always - update \dec19_rc_sel $0\dec19_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:71458.3-71509.6" - process $proc$issuer_ls180.v:71458$3502 - assign { } { } - assign { } { } - assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0] - attribute \src "issuer_ls180.v:71459.5-71459.29" - switch \initial - attribute \src "issuer_ls180.v:71459.9-71459.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - case - assign $1\dec19_cry_in[1:0] 2'00 - end - sync always - update \dec19_cry_in $0\dec19_cry_in[1:0] - end - attribute \src "issuer_ls180.v:71510.3-71561.6" - process $proc$issuer_ls180.v:71510$3503 - assign { } { } - assign { } { } - assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0] - attribute \src "issuer_ls180.v:71511.5-71511.29" - switch \initial - attribute \src "issuer_ls180.v:71511.9-71511.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'01101100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00100111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00010110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00010111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00011000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'01001100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'10010001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'01001000 - case - assign $1\dec19_asmcode[7:0] 8'00000000 - end - sync always - update \dec19_asmcode $0\dec19_asmcode[7:0] - end - attribute \src "issuer_ls180.v:71562.3-71613.6" - process $proc$issuer_ls180.v:71562$3504 - assign { } { } - assign { } { } - assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0] - attribute \src "issuer_ls180.v:71563.5-71563.29" - switch \initial - attribute \src "issuer_ls180.v:71563.9-71563.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - case - assign $1\dec19_inv_a[0:0] 1'0 - end - sync always - update \dec19_inv_a $0\dec19_inv_a[0:0] - end - attribute \src "issuer_ls180.v:71614.3-71665.6" - process $proc$issuer_ls180.v:71614$3505 - assign { } { } - assign { } { } - assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0] - attribute \src "issuer_ls180.v:71615.5-71615.29" - switch \initial - attribute \src "issuer_ls180.v:71615.9-71615.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - case - assign $1\dec19_inv_out[0:0] 1'0 - end - sync always - update \dec19_inv_out $0\dec19_inv_out[0:0] - end - attribute \src "issuer_ls180.v:71666.3-71717.6" - process $proc$issuer_ls180.v:71666$3506 - assign { } { } - assign { } { } - assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0] - attribute \src "issuer_ls180.v:71667.5-71667.29" - switch \initial - attribute \src "issuer_ls180.v:71667.9-71667.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - case - assign $1\dec19_cry_out[0:0] 1'0 - end - sync always - update \dec19_cry_out $0\dec19_cry_out[0:0] - end - attribute \src "issuer_ls180.v:71718.3-71769.6" - process $proc$issuer_ls180.v:71718$3507 - assign { } { } - assign { } { } - assign $0\dec19_br[0:0] $1\dec19_br[0:0] - attribute \src "issuer_ls180.v:71719.5-71719.29" - switch \initial - attribute \src "issuer_ls180.v:71719.9-71719.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - case - assign $1\dec19_br[0:0] 1'0 - end - sync always - update \dec19_br $0\dec19_br[0:0] - end - attribute \src "issuer_ls180.v:71770.3-71821.6" - process $proc$issuer_ls180.v:71770$3508 - assign { } { } - assign { } { } - assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0] - attribute \src "issuer_ls180.v:71771.5-71771.29" - switch \initial - attribute \src "issuer_ls180.v:71771.9-71771.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - case - assign $1\dec19_sgn_ext[0:0] 1'0 - end - sync always - update \dec19_sgn_ext $0\dec19_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:71822.3-71873.6" - process $proc$issuer_ls180.v:71822$3509 - assign { } { } - assign { } { } - assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] - attribute \src "issuer_ls180.v:71823.5-71823.29" - switch \initial - attribute \src "issuer_ls180.v:71823.9-71823.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'0101010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'0001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'0001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'0001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'0100100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000110 - case - assign $1\dec19_internal_op[6:0] 7'0000000 - end - sync always - update \dec19_internal_op $0\dec19_internal_op[6:0] - end - attribute \src "issuer_ls180.v:71874.3-71925.6" - process $proc$issuer_ls180.v:71874$3510 - assign { } { } - assign { } { } - assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0] - attribute \src "issuer_ls180.v:71875.5-71875.29" - switch \initial - attribute \src "issuer_ls180.v:71875.9-71875.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - case - assign $1\dec19_rsrv[0:0] 1'0 - end - sync always - update \dec19_rsrv $0\dec19_rsrv[0:0] - end - attribute \src "issuer_ls180.v:71926.3-71977.6" - process $proc$issuer_ls180.v:71926$3511 - assign { } { } - assign { } { } - assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] - attribute \src "issuer_ls180.v:71927.5-71927.29" - switch \initial - attribute \src "issuer_ls180.v:71927.9-71927.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - case - assign $1\dec19_is_32b[0:0] 1'0 - end - sync always - update \dec19_is_32b $0\dec19_is_32b[0:0] - end - attribute \src "issuer_ls180.v:71978.3-72029.6" - process $proc$issuer_ls180.v:71978$3512 - assign { } { } - assign { } { } - assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0] - attribute \src "issuer_ls180.v:71979.5-71979.29" - switch \initial - attribute \src "issuer_ls180.v:71979.9-71979.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - case - assign $1\dec19_sgn[0:0] 1'0 - end - sync always - update \dec19_sgn $0\dec19_sgn[0:0] - end - attribute \src "issuer_ls180.v:72030.3-72081.6" - process $proc$issuer_ls180.v:72030$3513 - assign { } { } - assign { } { } - assign $0\dec19_lk[0:0] $1\dec19_lk[0:0] - attribute \src "issuer_ls180.v:72031.5-72031.29" - switch \initial - attribute \src "issuer_ls180.v:72031.9-72031.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_lk[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_lk[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_lk[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - case - assign $1\dec19_lk[0:0] 1'0 - end - sync always - update \dec19_lk $0\dec19_lk[0:0] - end - attribute \src "issuer_ls180.v:72082.3-72133.6" - process $proc$issuer_ls180.v:72082$3514 - assign { } { } - assign { } { } - assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:72083.5-72083.29" - switch \initial - attribute \src "issuer_ls180.v:72083.9-72083.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - case - assign $1\dec19_sgl_pipe[0:0] 1'0 - end - sync always - update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0] - end - attribute \src "issuer_ls180.v:72134.3-72185.6" - process $proc$issuer_ls180.v:72134$3515 - assign { } { } - assign { } { } - assign $0\dec19_form[4:0] $1\dec19_form[4:0] - attribute \src "issuer_ls180.v:72135.5-72135.29" - switch \initial - attribute \src "issuer_ls180.v:72135.9-72135.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - case - assign $1\dec19_form[4:0] 5'00000 - end - sync always - update \dec19_form $0\dec19_form[4:0] - end - attribute \src "issuer_ls180.v:72186.3-72237.6" - process $proc$issuer_ls180.v:72186$3516 - assign { } { } - assign { } { } - assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0] - attribute \src "issuer_ls180.v:72187.5-72187.29" - switch \initial - attribute \src "issuer_ls180.v:72187.9-72187.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 - case - assign $1\dec19_in1_sel[2:0] 3'000 - end - sync always - update \dec19_in1_sel $0\dec19_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:72238.3-72289.6" - process $proc$issuer_ls180.v:72238$3517 - assign { } { } - assign { } { } - assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0] - attribute \src "issuer_ls180.v:72239.5-72239.29" - switch \initial - attribute \src "issuer_ls180.v:72239.9-72239.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 - case - assign $1\dec19_in2_sel[3:0] 4'0000 - end - sync always - update \dec19_in2_sel $0\dec19_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:72290.3-72341.6" - process $proc$issuer_ls180.v:72290$3518 - assign { } { } - assign { } { } - assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0] - attribute \src "issuer_ls180.v:72291.5-72291.29" - switch \initial - attribute \src "issuer_ls180.v:72291.9-72291.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - case - assign $1\dec19_in3_sel[1:0] 2'00 - end - sync always - update \dec19_in3_sel $0\dec19_in3_sel[1:0] - end - attribute \src "issuer_ls180.v:72342.3-72393.6" - process $proc$issuer_ls180.v:72342$3519 - assign { } { } - assign { } { } - assign $0\dec19_out_sel[1:0] $1\dec19_out_sel[1:0] - attribute \src "issuer_ls180.v:72343.5-72343.29" - switch \initial - attribute \src "issuer_ls180.v:72343.9-72343.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'11 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'11 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'11 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - case - assign $1\dec19_out_sel[1:0] 2'00 - end - sync always - update \dec19_out_sel $0\dec19_out_sel[1:0] - end - attribute \src "issuer_ls180.v:72394.3-72445.6" - process $proc$issuer_ls180.v:72394$3520 - assign { } { } - assign { } { } - assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0] - attribute \src "issuer_ls180.v:72395.5-72395.29" - switch \initial - attribute \src "issuer_ls180.v:72395.9-72395.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'000 - case - assign $1\dec19_cr_in[2:0] 3'000 - end - sync always - update \dec19_cr_in $0\dec19_cr_in[2:0] - end - attribute \src "issuer_ls180.v:72446.3-72497.6" - process $proc$issuer_ls180.v:72446$3521 - assign { } { } - assign { } { } - assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0] - attribute \src "issuer_ls180.v:72447.5-72447.29" - switch \initial - attribute \src "issuer_ls180.v:72447.9-72447.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 - case - assign $1\dec19_cr_out[2:0] 3'000 - end - sync always - update \dec19_cr_out $0\dec19_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "issuer_ls180.v:72503.1-74386.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2" -attribute \generator "nMigen" -module \dec2 - attribute \src "issuer_ls180.v:74255.3-74333.6" - wire width 8 $0\asmcode[7:0] - attribute \src "issuer_ls180.v:74255.3-74333.6" - wire width 64 $0\cia[63:0] - attribute \src "issuer_ls180.v:74255.3-74333.6" - wire width 3 $0\cr_in1[2:0] - attribute \src "issuer_ls180.v:74255.3-74333.6" - wire $0\cr_in1_ok[0:0] - attribute \src "issuer_ls180.v:74255.3-74333.6" - wire width 3 $0\cr_in2$1[2:0]$3541 - attribute \src "issuer_ls180.v:74255.3-74333.6" - wire width 3 $0\cr_in2[2:0] - attribute \src "issuer_ls180.v:74255.3-74333.6" - wire $0\cr_in2_ok$2[0:0]$3542 - attribute \src "issuer_ls180.v:74255.3-74333.6" - wire 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"issuer_ls180.v:74047.18-74047.110" - wire $or$issuer_ls180.v:74047$3533_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:856" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:860" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:864" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:887" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:888" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:889" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:921" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:921" - wire \$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:930" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" - wire width 8 output 5 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" - wire width 64 output 39 \cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 30 \cr_in1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 31 \cr_in1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 32 \cr_in2 - attribute \src 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output 54 \cr_wr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" - wire width 64 input 56 \cur_dec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" - wire input 57 \cur_eint - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 input 3 \cur_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 input 2 \cur_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 \dec_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 10 \dec_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 \dec_XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_a_fast_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_a_fast_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \dec_a_reg_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_a_reg_a_ok - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:85" - wire width 3 \dec_a_sel_in - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \dec_a_spr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_a_spr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_b_fast_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_b_fast_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \dec_b_reg_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_b_reg_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - wire width 4 \dec_b_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \dec_c_reg_c - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_c_reg_c_ok - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" - wire width 2 \dec_c_sel_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_cr_in_cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_cr_in_cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_cr_in_cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_cr_in_cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_cr_in_cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_cr_in_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \dec_cr_in_cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_cr_in_cr_fxm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 \dec_cr_in_sel_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_cr_out_cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \dec_cr_out_cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_cr_out_cr_fxm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 \dec_cr_out_sel_in - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec_cry_in - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 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attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute 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\enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" - wire width 7 \tmp_tmp_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" - wire \tmp_tmp_is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire \tmp_tmp_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" - wire width 64 \tmp_tmp_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_tmp_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_tmp_oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_tmp_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_tmp_rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 13 \tmp_tmp_trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 7 \tmp_tmp_traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" - wire width 3 \tmp_xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" - wire \tmp_xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 13 output 50 \trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 7 output 49 \traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" - wire width 3 output 20 \xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" - wire output 21 \xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" - cell $and $and$issuer_ls180.v:74041$3527 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cur_eint - connect \B \cur_msr [15] - connect \Y $and$issuer_ls180.v:74041$3527_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:887" - cell $and $and$issuer_ls180.v:74042$3528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cur_dec [63] - connect \B \cur_msr [15] - connect \Y $and$issuer_ls180.v:74042$3528_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:888" - cell $and $and$issuer_ls180.v:74043$3529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_priv_insn - connect \B \cur_msr [14] - connect \Y $and$issuer_ls180.v:74043$3529_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:856" - cell $eq $eq$issuer_ls180.v:74037$3523 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0101110 - connect \Y $eq$issuer_ls180.v:74037$3523_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" - cell $eq $eq$issuer_ls180.v:74038$3524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0001010 - connect \Y $eq$issuer_ls180.v:74038$3524_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:860" - cell $eq $eq$issuer_ls180.v:74039$3525 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0110001 - connect \Y $eq$issuer_ls180.v:74039$3525_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:864" - cell $eq $eq$issuer_ls180.v:74040$3526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0111111 - connect \Y $eq$issuer_ls180.v:74040$3526_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:889" - cell $eq $eq$issuer_ls180.v:74044$3530 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0000000 - connect \Y $eq$issuer_ls180.v:74044$3530_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$issuer_ls180.v:74045$3531 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \insn_type - connect \B 7'0111111 - connect \Y $eq$issuer_ls180.v:74045$3531_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:921" - cell $eq $eq$issuer_ls180.v:74046$3532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \insn_type - connect \B 7'1001001 - connect \Y $eq$issuer_ls180.v:74046$3532_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:930" - cell $eq $eq$issuer_ls180.v:74048$3534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \insn_type - connect \B 7'1000110 - connect \Y $eq$issuer_ls180.v:74048$3534_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:921" - cell $or $or$issuer_ls180.v:74047$3533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$29 - connect \B \$31 - connect \Y $or$issuer_ls180.v:74047$3533_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:74049.13-74085.4" - cell \dec$202 \dec - connect \BA \dec_BA - connect \BB \dec_BB - connect \BC \dec_BC - connect \BI \dec_BI - connect \BO \dec_BO - connect \BT \dec_BT - connect \FXM \dec_FXM - connect \LK \dec_LK - connect \OE \dec_OE - connect \RA \dec_RA - connect \RB \dec_RB - connect \RS \dec_RS - connect \RT \dec_RT - connect \Rc \dec_Rc - connect \SPR \dec_SPR - connect \XL_BT \dec_XL_BT - connect \XL_XO \dec_XL_XO - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \bigendian \bigendian - connect \cr_in \dec_cr_in - connect \cr_out \dec_cr_out - connect \cry_in \dec_cry_in - connect \function_unit \dec_function_unit - connect \in1_sel \dec_in1_sel - connect \in2_sel \dec_in2_sel - connect \in3_sel \dec_in3_sel - connect \internal_op \dec_internal_op - connect \is_32b \dec_is_32b - connect \lk \dec_lk - connect \opcode_in \dec_opcode_in - connect \out_sel \dec_out_sel - connect \raw_opcode_in \raw_opcode_in - connect \rc_sel \dec_rc_sel - connect \upd \dec_upd - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:74086.9-74100.4" - cell \dec_a \dec_a - connect \BO \dec_BO - connect \RA \dec_RA - connect \RS \dec_RS - connect \SPR \dec_SPR - connect \XL_XO \dec_XL_XO - connect \fast_a \dec_a_fast_a - connect \fast_a_ok \dec_a_fast_a_ok - connect \internal_op \dec_internal_op - connect \reg_a \dec_a_reg_a - connect \reg_a_ok \dec_a_reg_a_ok - connect \sel_in \dec_a_sel_in - connect \spr_a \dec_a_spr_a - connect \spr_a_ok \dec_a_spr_a_ok - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:74101.9-74111.4" - cell \dec_b \dec_b - connect \RB \dec_RB - connect \RS \dec_RS - connect \XL_XO \dec_XL_XO - connect \fast_b \dec_b_fast_b - connect \fast_b_ok \dec_b_fast_b_ok - connect \internal_op \dec_internal_op - connect \reg_b \dec_b_reg_b - connect \reg_b_ok \dec_b_reg_b_ok - connect \sel_in \dec_b_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:74112.9-74118.4" - cell \dec_c \dec_c - connect \RB \dec_RB - connect \RS \dec_RS - connect \reg_c \dec_c_reg_c - connect \reg_c_ok \dec_c_reg_c_ok - connect \sel_in \dec_c_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:74119.19-74138.4" - cell \dec_cr_in$205 \dec_cr_in$3 - connect \BA \dec_BA - connect \BB \dec_BB - connect \BC \dec_BC - connect \BI \dec_BI - connect \BT \dec_BT - connect \FXM \dec_FXM - connect \X_BFA \dec_X_BFA - connect \cr_bitfield \dec_cr_in_cr_bitfield - connect \cr_bitfield_b \dec_cr_in_cr_bitfield_b - connect \cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b_ok - connect \cr_bitfield_o \dec_cr_in_cr_bitfield_o - connect \cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o_ok - connect \cr_bitfield_ok \dec_cr_in_cr_bitfield_ok - connect \cr_fxm \dec_cr_in_cr_fxm - connect \cr_fxm_ok \dec_cr_in_cr_fxm_ok - connect \insn_in \dec_cr_in_insn_in - connect \internal_op \dec_internal_op - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:74139.20-74151.4" - cell \dec_cr_out$207 \dec_cr_out$4 - connect \FXM \dec_FXM - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \cr_bitfield \dec_cr_out_cr_bitfield - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \cr_fxm \dec_cr_out_cr_fxm - connect \cr_fxm_ok \dec_cr_out_cr_fxm_ok - connect \insn_in \dec_cr_out_insn_in - connect \internal_op \dec_internal_op - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:74152.9-74165.4" - cell \dec_o \dec_o - connect \BO \dec_BO - connect \RA \dec_RA - connect \RT \dec_RT - connect \SPR \dec_SPR - connect \fast_o \dec_o_fast_o - connect \fast_o_ok \dec_o_fast_o_ok - connect \internal_op \dec_internal_op - connect \reg_o \dec_o_reg_o - connect \reg_o_ok \dec_o_reg_o_ok - connect \sel_in \dec_o_sel_in - connect \spr_o \dec_o_spr_o - connect \spr_o_ok \dec_o_spr_o_ok - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:74166.10-74175.4" - cell \dec_o2 \dec_o2 - connect \RA \dec_RA - connect \fast_o \dec_o2_fast_o - connect \fast_o_ok \dec_o2_fast_o_ok - connect \internal_op \dec_internal_op - connect \lk \dec_o2_lk - connect \reg_o \dec_o2_reg_o - connect \reg_o_ok \dec_o2_reg_o_ok - connect \upd \dec_upd - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:74176.16-74182.4" - cell \dec_oe$204 \dec_oe - connect \OE \dec_OE - connect \internal_op \dec_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \sel_in \dec_oe_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:74183.16-74188.4" - cell \dec_rc$203 \dec_rc - connect \Rc \dec_Rc - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \sel_in \dec_rc_sel_in - end - attribute \src "issuer_ls180.v:72504.7-72504.20" - process $proc$issuer_ls180.v:72504$3545 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:74189.3-74198.6" - process $proc$issuer_ls180.v:74189$3535 - assign { } { } - assign { } { } - assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0] - attribute \src "issuer_ls180.v:74190.5-74190.29" - switch \initial - attribute \src "issuer_ls180.v:74190.9-74190.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:756" - switch \dec_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\tmp_tmp_lk[0:0] \dec_LK - case - assign $1\tmp_tmp_lk[0:0] 1'0 - end - sync always - update \tmp_tmp_lk $0\tmp_tmp_lk[0:0] - end - attribute \src "issuer_ls180.v:74199.3-74214.6" - process $proc$issuer_ls180.v:74199$3536 - assign { } { } - assign { } { } - assign { } { } - assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0] - attribute \src "issuer_ls180.v:74200.5-74200.29" - switch \initial - attribute \src "issuer_ls180.v:74200.9-74200.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:856" - switch \$13 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\tmp_xer_in[2:0] 3'111 - case - assign $1\tmp_xer_in[2:0] 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" - switch \$15 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\tmp_xer_in[2:0] 3'001 - case - assign $2\tmp_xer_in[2:0] $1\tmp_xer_in[2:0] - end - sync always - update \tmp_xer_in $0\tmp_xer_in[2:0] - end - attribute \src "issuer_ls180.v:74215.3-74224.6" - process $proc$issuer_ls180.v:74215$3537 - assign { } { } - assign { } { } - assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0] - attribute \src "issuer_ls180.v:74216.5-74216.29" - switch \initial - attribute \src "issuer_ls180.v:74216.9-74216.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:860" - switch \$17 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\tmp_xer_out[0:0] 1'1 - case - assign $1\tmp_xer_out[0:0] 1'0 - end - sync always - update \tmp_xer_out $0\tmp_xer_out[0:0] - end - attribute \src "issuer_ls180.v:74225.3-74234.6" - process $proc$issuer_ls180.v:74225$3538 - assign { } { } - assign { } { } - assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0] - attribute \src "issuer_ls180.v:74226.5-74226.29" - switch \initial - attribute \src "issuer_ls180.v:74226.9-74226.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:864" - switch \$19 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\tmp_tmp_trapaddr[12:0] 13'0000001110000 - case - assign $1\tmp_tmp_trapaddr[12:0] 13'0000000000000 - end - sync always - update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0] - end - attribute \src "issuer_ls180.v:74235.3-74254.6" - process $proc$issuer_ls180.v:74235$3539 - assign { } { } - assign { } { } - assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0] - attribute \src "issuer_ls180.v:74236.5-74236.29" - switch \initial - attribute \src "issuer_ls180.v:74236.9-74236.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:42" - switch \dec_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000101 , 7'1000111 , 7'1001000 , 7'1001010 , 7'1000110 - assign { } { } - assign $1\is_priv_insn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0101110 , 7'0110001 - assign { } { } - assign $1\is_priv_insn[0:0] $2\is_priv_insn[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:49" - switch \tmp_tmp_insn [20] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\is_priv_insn[0:0] 1'1 - case - assign $2\is_priv_insn[0:0] 1'0 - end - case - assign $1\is_priv_insn[0:0] 1'0 - end - sync always - update \is_priv_insn $0\is_priv_insn[0:0] - end - attribute \src "issuer_ls180.v:74255.3-74333.6" - process $proc$issuer_ls180.v:74255$3540 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - assign $0\spr1[9:0] $1\spr1[9:0] - assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] - assign $0\msr[63:0] $1\msr[63:0] - assign $0\ea_ok[0:0] $1\ea_ok[0:0] - assign $0\ea[4:0] $1\ea[4:0] - assign $0\asmcode[7:0] $1\asmcode[7:0] - assign $0\cr_out[2:0] $1\cr_out[2:0] - assign $0\lk[0:0] $1\lk[0:0] - assign $0\cia[63:0] $1\cia[63:0] - assign $0\cr_in1[2:0] $1\cr_in1[2:0] - assign $0\cr_in1_ok[0:0] $1\cr_in1_ok[0:0] - assign $0\cr_in2[2:0] $1\cr_in2[2:0] - assign $0\cr_in2$1[2:0]$3541 $1\cr_in2$1[2:0]$3543 - assign $0\cr_in2_ok[0:0] $1\cr_in2_ok[0:0] - assign $0\cr_in2_ok$2[0:0]$3542 $1\cr_in2_ok$2[0:0]$3544 - assign $0\cr_out_ok[0:0] $1\cr_out_ok[0:0] - assign $0\cr_rd[7:0] $1\cr_rd[7:0] - assign $0\cr_rd_ok[0:0] $1\cr_rd_ok[0:0] - assign $0\cr_wr[7:0] $1\cr_wr[7:0] - assign $0\cr_wr_ok[0:0] $1\cr_wr_ok[0:0] - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fn_unit[11:0] $1\fn_unit[11:0] - assign $0\input_carry[1:0] $1\input_carry[1:0] - assign $0\insn[31:0] $1\insn[31:0] - assign $0\insn_type[6:0] $1\insn_type[6:0] - assign $0\is_32bit[0:0] $1\is_32bit[0:0] - assign $0\oe[0:0] $1\oe[0:0] - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - assign $0\reg1[4:0] $1\reg1[4:0] - assign $0\reg1_ok[0:0] $1\reg1_ok[0:0] - assign $0\reg2[4:0] $1\reg2[4:0] - assign $0\reg2_ok[0:0] $1\reg2_ok[0:0] - assign $0\reg3[4:0] $1\reg3[4:0] - assign $0\reg3_ok[0:0] $1\reg3_ok[0:0] - assign $0\rego[4:0] $1\rego[4:0] - assign $0\rego_ok[0:0] $1\rego_ok[0:0] - assign $0\spro[9:0] $1\spro[9:0] - assign $0\spro_ok[0:0] $1\spro_ok[0:0] - assign $0\trapaddr[12:0] $1\trapaddr[12:0] - assign $0\traptype[6:0] $1\traptype[6:0] - assign $0\xer_in[2:0] $1\xer_in[2:0] - assign $0\xer_out[0:0] $1\xer_out[0:0] - assign $0\fasto1[2:0] $2\fasto1[2:0] - assign $0\fasto1_ok[0:0] $2\fasto1_ok[0:0] - assign $0\fasto2[2:0] $2\fasto2[2:0] - assign $0\fasto2_ok[0:0] $2\fasto2_ok[0:0] - assign $0\fast1[2:0] $2\fast1[2:0] - assign $0\fast1_ok[0:0] $2\fast1_ok[0:0] - assign $0\fast2[2:0] $2\fast2[2:0] - assign $0\fast2_ok[0:0] $2\fast2_ok[0:0] - attribute \src "issuer_ls180.v:74256.5-74256.29" - switch \initial - attribute \src "issuer_ls180.v:74256.9-74256.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:892" - switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'---1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3544 $1\cr_in2$1[2:0]$3543 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $1\insn[31:0] \dec_opcode_in - assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[11:0] 12'000010000000 - assign $1\trapaddr[12:0] 13'0000010010000 - assign $1\traptype[6:0] 7'0100000 - assign $1\msr[63:0] \cur_msr - assign $1\cia[63:0] \cur_pc - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'--1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3544 $1\cr_in2$1[2:0]$3543 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $1\insn[31:0] \dec_opcode_in - assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[11:0] 12'000010000000 - assign $1\trapaddr[12:0] 13'0000001010000 - assign $1\traptype[6:0] 7'0010000 - assign $1\msr[63:0] \cur_msr - assign $1\cia[63:0] \cur_pc - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'-1-- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3544 $1\cr_in2$1[2:0]$3543 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $1\insn[31:0] \dec_opcode_in - assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[11:0] 12'000010000000 - assign $1\trapaddr[12:0] 13'0000001110000 - assign $1\traptype[6:0] 7'0000010 - assign $1\msr[63:0] \cur_msr - assign $1\cia[63:0] \cur_pc - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1--- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3544 $1\cr_in2$1[2:0]$3543 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $1\insn[31:0] \dec_opcode_in - assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[11:0] 12'000010000000 - assign $1\trapaddr[12:0] 13'0000001110000 - assign $1\traptype[6:0] 7'1000000 - assign $1\msr[63:0] \cur_msr - assign $1\cia[63:0] \cur_pc - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\traptype[6:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[11:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3544 $1\cr_in2$1[2:0]$3543 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$12 \tmp_cr_in2$11 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:921" - switch \$33 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\fasto1[2:0] 3'011 - assign $2\fasto1_ok[0:0] 1'1 - assign $2\fasto2[2:0] 3'100 - assign $2\fasto2_ok[0:0] 1'1 - case - assign $2\fasto1[2:0] $1\fasto1[2:0] - assign $2\fasto1_ok[0:0] $1\fasto1_ok[0:0] - assign $2\fasto2[2:0] $1\fasto2[2:0] - assign $2\fasto2_ok[0:0] $1\fasto2_ok[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:930" - switch \$35 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\fast1[2:0] 3'011 - assign $2\fast1_ok[0:0] 1'1 - assign $2\fast2[2:0] 3'100 - assign $2\fast2_ok[0:0] 1'1 - case - assign $2\fast1[2:0] $1\fast1[2:0] - assign $2\fast1_ok[0:0] $1\fast1_ok[0:0] - assign $2\fast2[2:0] $1\fast2[2:0] - assign $2\fast2_ok[0:0] $1\fast2_ok[0:0] - end - sync always - update \fast1 $0\fast1[2:0] - update \fast1_ok $0\fast1_ok[0:0] - update \fast2 $0\fast2[2:0] - update \fast2_ok $0\fast2_ok[0:0] - update \rc $0\rc[0:0] - update \spr1 $0\spr1[9:0] - update \spr1_ok $0\spr1_ok[0:0] - update \msr $0\msr[63:0] - update \ea_ok $0\ea_ok[0:0] - update \ea $0\ea[4:0] - update \asmcode $0\asmcode[7:0] - update \cr_out $0\cr_out[2:0] - update \lk $0\lk[0:0] - update \cia $0\cia[63:0] - update \cr_in1 $0\cr_in1[2:0] - update \cr_in1_ok $0\cr_in1_ok[0:0] - update \cr_in2 $0\cr_in2[2:0] - update \cr_in2$1 $0\cr_in2$1[2:0]$3541 - update \cr_in2_ok $0\cr_in2_ok[0:0] - update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$3542 - update \cr_out_ok $0\cr_out_ok[0:0] - update \cr_rd $0\cr_rd[7:0] - update \cr_rd_ok $0\cr_rd_ok[0:0] - update \cr_wr $0\cr_wr[7:0] - update \cr_wr_ok $0\cr_wr_ok[0:0] - update \fasto1 $0\fasto1[2:0] - update \fasto1_ok $0\fasto1_ok[0:0] - update \fasto2 $0\fasto2[2:0] - update \fasto2_ok $0\fasto2_ok[0:0] - update \fn_unit $0\fn_unit[11:0] - update \input_carry $0\input_carry[1:0] - update \insn $0\insn[31:0] - update \insn_type $0\insn_type[6:0] - update \is_32bit $0\is_32bit[0:0] - update \oe $0\oe[0:0] - update \oe_ok $0\oe_ok[0:0] - update \rc_ok $0\rc_ok[0:0] - update \reg1 $0\reg1[4:0] - update \reg1_ok $0\reg1_ok[0:0] - update \reg2 $0\reg2[4:0] - update \reg2_ok $0\reg2_ok[0:0] - update \reg3 $0\reg3[4:0] - update \reg3_ok $0\reg3_ok[0:0] - update \rego $0\rego[4:0] - update \rego_ok $0\rego_ok[0:0] - update \spro $0\spro[9:0] - update \spro_ok $0\spro_ok[0:0] - update \trapaddr $0\trapaddr[12:0] - update \traptype $0\traptype[6:0] - update \xer_in $0\xer_in[2:0] - update \xer_out $0\xer_out[0:0] - end - connect \$13 $eq$issuer_ls180.v:74037$3523_Y - connect \$15 $eq$issuer_ls180.v:74038$3524_Y - connect \$17 $eq$issuer_ls180.v:74039$3525_Y - connect \$19 $eq$issuer_ls180.v:74040$3526_Y - connect \$21 $and$issuer_ls180.v:74041$3527_Y - connect \$23 $and$issuer_ls180.v:74042$3528_Y - connect \$25 $and$issuer_ls180.v:74043$3529_Y - connect \$27 $eq$issuer_ls180.v:74044$3530_Y - connect \$29 $eq$issuer_ls180.v:74045$3531_Y - connect \$31 $eq$issuer_ls180.v:74046$3532_Y - connect \$33 $or$issuer_ls180.v:74047$3533_Y - connect \$35 $eq$issuer_ls180.v:74048$3534_Y - connect \tmp_asmcode 8'00000000 - connect \tmp_tmp_traptype 7'0000000 - connect \illeg_ok \$27 - connect \priv_ok \$25 - connect \dec_irq_ok \$23 - connect \ext_irq_ok \$21 - connect { \tmp_cr_out_ok \tmp_cr_out } { \dec_cr_out_cr_bitfield_ok \dec_cr_out_cr_bitfield } - connect { \tmp_cr_in2_ok$12 \tmp_cr_in2$11 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o } - connect { \tmp_cr_in2_ok \tmp_cr_in2 } { \dec_cr_in_cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b } - connect { \tmp_cr_in1_ok \tmp_cr_in1 } { \dec_cr_in_cr_bitfield_ok \dec_cr_in_cr_bitfield } - connect { \tmp_fasto2_ok \tmp_fasto2 } { \dec_o2_fast_o_ok \dec_o2_fast_o } - connect { \tmp_fasto1_ok \tmp_fasto1 } { \dec_o_fast_o_ok \dec_o_fast_o } - connect { \tmp_fast2_ok \tmp_fast2 } { \dec_b_fast_b_ok \dec_b_fast_b } - connect { \tmp_fast1_ok \tmp_fast1 } { \dec_a_fast_a_ok \dec_a_fast_a } - connect { \tmp_spro_ok \tmp_spro } { \dec_o_spr_o_ok \dec_o_spr_o } - connect { \tmp_spr1_ok \tmp_spr1 } { \dec_a_spr_a_ok \dec_a_spr_a } - connect { \tmp_ea_ok \tmp_ea } { \dec_o2_reg_o_ok \dec_o2_reg_o } - connect { \tmp_rego_ok \tmp_rego } { \dec_o_reg_o_ok \dec_o_reg_o } - connect { \tmp_reg3_ok \tmp_reg3 } { \dec_c_reg_c_ok \dec_c_reg_c } - connect { \tmp_reg2_ok \tmp_reg2 } { \dec_b_reg_b_ok \dec_b_reg_b } - connect { \tmp_reg1_ok \tmp_reg1 } { \dec_a_reg_a_ok \dec_a_reg_a } - connect \dec_o2_lk \tmp_tmp_lk - connect \sel_in \dec_out_sel - connect \dec_o_sel_in \dec_out_sel - connect \dec_c_sel_in \dec_in3_sel - connect \dec_b_sel_in \dec_in2_sel - connect \dec_a_sel_in \dec_in1_sel - connect \insn_in$10 \dec_opcode_in - connect \insn_in$9 \dec_opcode_in - connect \insn_in$8 \dec_opcode_in - connect \insn_in$7 \dec_opcode_in - connect \insn_in$6 \dec_opcode_in - connect \tmp_tmp_is_32bit \dec_is_32b - connect \tmp_tmp_input_carry \dec_cry_in - connect { \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr } { \dec_cr_out_cr_fxm_ok \dec_cr_out_cr_fxm } - connect { \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd } { \dec_cr_in_cr_fxm_ok \dec_cr_in_cr_fxm } - connect { \tmp_tmp_oe_ok \tmp_tmp_oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \tmp_tmp_rc_ok \tmp_tmp_rc } { \dec_rc_rc_ok \dec_rc_rc } - connect \tmp_tmp_fn_unit \dec_function_unit - connect \tmp_tmp_insn_type \dec_internal_op - connect \tmp_tmp_cia \cur_pc - connect \tmp_tmp_msr \cur_msr - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_cr_out - connect \dec_cr_in_sel_in \dec_cr_in - connect \dec_oe_sel_in \dec_rc_sel - connect \dec_rc_sel_in \dec_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in - connect \insn_in$5 \dec_opcode_in - connect \insn_in \dec_opcode_in - connect \tmp_tmp_insn \dec_opcode_in -end -attribute \src "issuer_ls180.v:74390.1-75537.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec30" -attribute \generator "nMigen" -module \dec30 - attribute \src "issuer_ls180.v:74833.3-74869.6" - wire width 8 $0\dec30_asmcode[7:0] - attribute \src "issuer_ls180.v:74981.3-75017.6" - wire $0\dec30_br[0:0] - attribute \src "issuer_ls180.v:75462.3-75498.6" - wire width 3 $0\dec30_cr_in[2:0] - attribute \src "issuer_ls180.v:75499.3-75535.6" - wire width 3 $0\dec30_cr_out[2:0] - attribute \src "issuer_ls180.v:74796.3-74832.6" - wire width 2 $0\dec30_cry_in[1:0] - attribute \src "issuer_ls180.v:74944.3-74980.6" - wire $0\dec30_cry_out[0:0] - attribute \src "issuer_ls180.v:75277.3-75313.6" - wire width 5 $0\dec30_form[4:0] - attribute \src "issuer_ls180.v:74648.3-74684.6" - wire width 12 $0\dec30_function_unit[11:0] - attribute \src "issuer_ls180.v:75314.3-75350.6" - wire width 3 $0\dec30_in1_sel[2:0] - attribute \src "issuer_ls180.v:75351.3-75387.6" - wire width 4 $0\dec30_in2_sel[3:0] - attribute \src "issuer_ls180.v:75388.3-75424.6" - wire width 2 $0\dec30_in3_sel[1:0] - attribute \src "issuer_ls180.v:75055.3-75091.6" - wire width 7 $0\dec30_internal_op[6:0] - attribute \src "issuer_ls180.v:74870.3-74906.6" - wire $0\dec30_inv_a[0:0] - attribute \src "issuer_ls180.v:74907.3-74943.6" - wire $0\dec30_inv_out[0:0] - attribute \src "issuer_ls180.v:75129.3-75165.6" - wire $0\dec30_is_32b[0:0] - attribute \src "issuer_ls180.v:74685.3-74721.6" - wire width 4 $0\dec30_ldst_len[3:0] - attribute \src "issuer_ls180.v:75203.3-75239.6" - wire $0\dec30_lk[0:0] - attribute \src "issuer_ls180.v:75425.3-75461.6" - wire width 2 $0\dec30_out_sel[1:0] - attribute \src "issuer_ls180.v:74759.3-74795.6" - wire width 2 $0\dec30_rc_sel[1:0] - attribute \src "issuer_ls180.v:75092.3-75128.6" - wire $0\dec30_rsrv[0:0] - attribute \src "issuer_ls180.v:75240.3-75276.6" - wire $0\dec30_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:75166.3-75202.6" - wire $0\dec30_sgn[0:0] - attribute \src "issuer_ls180.v:75018.3-75054.6" - wire $0\dec30_sgn_ext[0:0] - attribute \src "issuer_ls180.v:74722.3-74758.6" - wire width 2 $0\dec30_upd[1:0] - attribute \src "issuer_ls180.v:74391.7-74391.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:74833.3-74869.6" - wire width 8 $1\dec30_asmcode[7:0] - attribute \src "issuer_ls180.v:74981.3-75017.6" - wire $1\dec30_br[0:0] - attribute \src "issuer_ls180.v:75462.3-75498.6" - wire width 3 $1\dec30_cr_in[2:0] - attribute \src "issuer_ls180.v:75499.3-75535.6" - wire width 3 $1\dec30_cr_out[2:0] - attribute \src "issuer_ls180.v:74796.3-74832.6" - wire width 2 $1\dec30_cry_in[1:0] - attribute \src "issuer_ls180.v:74944.3-74980.6" - wire $1\dec30_cry_out[0:0] - attribute \src "issuer_ls180.v:75277.3-75313.6" - wire width 5 $1\dec30_form[4:0] - attribute \src "issuer_ls180.v:74648.3-74684.6" - wire width 12 $1\dec30_function_unit[11:0] - attribute \src "issuer_ls180.v:75314.3-75350.6" - wire width 3 $1\dec30_in1_sel[2:0] - attribute \src "issuer_ls180.v:75351.3-75387.6" - wire width 4 $1\dec30_in2_sel[3:0] - attribute \src "issuer_ls180.v:75388.3-75424.6" - wire width 2 $1\dec30_in3_sel[1:0] - attribute \src "issuer_ls180.v:75055.3-75091.6" - wire width 7 $1\dec30_internal_op[6:0] - attribute \src "issuer_ls180.v:74870.3-74906.6" - wire $1\dec30_inv_a[0:0] - attribute \src "issuer_ls180.v:74907.3-74943.6" - wire $1\dec30_inv_out[0:0] - attribute \src "issuer_ls180.v:75129.3-75165.6" - wire $1\dec30_is_32b[0:0] - attribute \src "issuer_ls180.v:74685.3-74721.6" - wire width 4 $1\dec30_ldst_len[3:0] - attribute \src "issuer_ls180.v:75203.3-75239.6" - wire $1\dec30_lk[0:0] - attribute \src "issuer_ls180.v:75425.3-75461.6" - wire width 2 $1\dec30_out_sel[1:0] - attribute \src "issuer_ls180.v:74759.3-74795.6" - wire width 2 $1\dec30_rc_sel[1:0] - attribute \src "issuer_ls180.v:75092.3-75128.6" - wire $1\dec30_rsrv[0:0] - attribute \src "issuer_ls180.v:75240.3-75276.6" - wire $1\dec30_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:75166.3-75202.6" - wire $1\dec30_sgn[0:0] - attribute \src "issuer_ls180.v:75018.3-75054.6" - wire $1\dec30_sgn_ext[0:0] - attribute \src "issuer_ls180.v:74722.3-74758.6" - wire width 2 $1\dec30_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec30_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec30_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec30_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec30_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec30_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec30_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec30_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec30_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec30_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec30_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec30_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec30_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec30_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec30_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec30_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec30_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec30_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec30_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec30_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec30_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec30_upd - attribute \src "issuer_ls180.v:74391.7-74391.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 4 \opcode_switch - attribute \src "issuer_ls180.v:74391.7-74391.20" - process $proc$issuer_ls180.v:74391$3570 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:74648.3-74684.6" - process $proc$issuer_ls180.v:74648$3546 - assign { } { } - assign { } { } - assign $0\dec30_function_unit[11:0] $1\dec30_function_unit[11:0] - attribute \src "issuer_ls180.v:74649.5-74649.29" - switch \initial - attribute \src "issuer_ls180.v:74649.9-74649.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - case - assign $1\dec30_function_unit[11:0] 12'000000000000 - end - sync always - update \dec30_function_unit $0\dec30_function_unit[11:0] - end - attribute \src "issuer_ls180.v:74685.3-74721.6" - process $proc$issuer_ls180.v:74685$3547 - assign { } { } - assign { } { } - assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0] - attribute \src "issuer_ls180.v:74686.5-74686.29" - switch \initial - attribute \src "issuer_ls180.v:74686.9-74686.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - case - assign $1\dec30_ldst_len[3:0] 4'0000 - end - sync always - update \dec30_ldst_len $0\dec30_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:74722.3-74758.6" - process $proc$issuer_ls180.v:74722$3548 - assign { } { } - assign { } { } - assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] - attribute \src "issuer_ls180.v:74723.5-74723.29" - switch \initial - attribute \src "issuer_ls180.v:74723.9-74723.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - case - assign $1\dec30_upd[1:0] 2'00 - end - sync always - update \dec30_upd $0\dec30_upd[1:0] - end - attribute \src "issuer_ls180.v:74759.3-74795.6" - process $proc$issuer_ls180.v:74759$3549 - assign { } { } - assign { } { } - assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0] - attribute \src "issuer_ls180.v:74760.5-74760.29" - switch \initial - attribute \src "issuer_ls180.v:74760.9-74760.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - case - assign $1\dec30_rc_sel[1:0] 2'00 - end - sync always - update \dec30_rc_sel $0\dec30_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:74796.3-74832.6" - process $proc$issuer_ls180.v:74796$3550 - assign { } { } - assign { } { } - assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0] - attribute \src "issuer_ls180.v:74797.5-74797.29" - switch \initial - attribute \src "issuer_ls180.v:74797.9-74797.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - case - assign $1\dec30_cry_in[1:0] 2'00 - end - sync always - update \dec30_cry_in $0\dec30_cry_in[1:0] - end - attribute \src "issuer_ls180.v:74833.3-74869.6" - process $proc$issuer_ls180.v:74833$3551 - assign { } { } - assign { } { } - assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0] - attribute \src "issuer_ls180.v:74834.5-74834.29" - switch \initial - attribute \src "issuer_ls180.v:74834.9-74834.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010011 - case - assign $1\dec30_asmcode[7:0] 8'00000000 - end - sync always - update \dec30_asmcode $0\dec30_asmcode[7:0] - end - attribute \src "issuer_ls180.v:74870.3-74906.6" - process $proc$issuer_ls180.v:74870$3552 - assign { } { } - assign { } { } - assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0] - attribute \src "issuer_ls180.v:74871.5-74871.29" - switch \initial - attribute \src "issuer_ls180.v:74871.9-74871.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - case - assign $1\dec30_inv_a[0:0] 1'0 - end - sync always - update \dec30_inv_a $0\dec30_inv_a[0:0] - end - attribute \src "issuer_ls180.v:74907.3-74943.6" - process $proc$issuer_ls180.v:74907$3553 - assign { } { } - assign { } { } - assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0] - attribute \src "issuer_ls180.v:74908.5-74908.29" - switch \initial - attribute \src "issuer_ls180.v:74908.9-74908.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - case - assign $1\dec30_inv_out[0:0] 1'0 - end - sync always - update \dec30_inv_out $0\dec30_inv_out[0:0] - end - attribute \src "issuer_ls180.v:74944.3-74980.6" - process $proc$issuer_ls180.v:74944$3554 - assign { } { } - assign { } { } - assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0] - attribute \src "issuer_ls180.v:74945.5-74945.29" - switch \initial - attribute \src "issuer_ls180.v:74945.9-74945.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - case - assign $1\dec30_cry_out[0:0] 1'0 - end - sync always - update \dec30_cry_out $0\dec30_cry_out[0:0] - end - attribute \src "issuer_ls180.v:74981.3-75017.6" - process $proc$issuer_ls180.v:74981$3555 - assign { } { } - assign { } { } - assign $0\dec30_br[0:0] $1\dec30_br[0:0] - attribute \src "issuer_ls180.v:74982.5-74982.29" - switch \initial - attribute \src "issuer_ls180.v:74982.9-74982.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - case - assign $1\dec30_br[0:0] 1'0 - end - sync always - update \dec30_br $0\dec30_br[0:0] - end - attribute \src "issuer_ls180.v:75018.3-75054.6" - process $proc$issuer_ls180.v:75018$3556 - assign { } { } - assign { } { } - assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0] - attribute \src "issuer_ls180.v:75019.5-75019.29" - switch \initial - attribute \src "issuer_ls180.v:75019.9-75019.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - case - assign $1\dec30_sgn_ext[0:0] 1'0 - end - sync always - update \dec30_sgn_ext $0\dec30_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:75055.3-75091.6" - process $proc$issuer_ls180.v:75055$3557 - assign { } { } - assign { } { } - assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] - attribute \src "issuer_ls180.v:75056.5-75056.29" - switch \initial - attribute \src "issuer_ls180.v:75056.9-75056.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111010 - case - assign $1\dec30_internal_op[6:0] 7'0000000 - end - sync always - update \dec30_internal_op $0\dec30_internal_op[6:0] - end - attribute \src "issuer_ls180.v:75092.3-75128.6" - process $proc$issuer_ls180.v:75092$3558 - assign { } { } - assign { } { } - assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0] - attribute \src "issuer_ls180.v:75093.5-75093.29" - switch \initial - attribute \src "issuer_ls180.v:75093.9-75093.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - case - assign $1\dec30_rsrv[0:0] 1'0 - end - sync always - update \dec30_rsrv $0\dec30_rsrv[0:0] - end - attribute \src "issuer_ls180.v:75129.3-75165.6" - process $proc$issuer_ls180.v:75129$3559 - assign { } { } - assign { } { } - assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] - attribute \src "issuer_ls180.v:75130.5-75130.29" - switch \initial - attribute \src "issuer_ls180.v:75130.9-75130.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - case - assign $1\dec30_is_32b[0:0] 1'0 - end - sync always - update \dec30_is_32b $0\dec30_is_32b[0:0] - end - attribute \src "issuer_ls180.v:75166.3-75202.6" - process $proc$issuer_ls180.v:75166$3560 - assign { } { } - assign { } { } - assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0] - attribute \src "issuer_ls180.v:75167.5-75167.29" - switch \initial - attribute \src "issuer_ls180.v:75167.9-75167.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - case - assign $1\dec30_sgn[0:0] 1'0 - end - sync always - update \dec30_sgn $0\dec30_sgn[0:0] - end - attribute \src "issuer_ls180.v:75203.3-75239.6" - process $proc$issuer_ls180.v:75203$3561 - assign { } { } - assign { } { } - assign $0\dec30_lk[0:0] $1\dec30_lk[0:0] - attribute \src "issuer_ls180.v:75204.5-75204.29" - switch \initial - attribute \src "issuer_ls180.v:75204.9-75204.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - case - assign $1\dec30_lk[0:0] 1'0 - end - sync always - update \dec30_lk $0\dec30_lk[0:0] - end - attribute \src "issuer_ls180.v:75240.3-75276.6" - process $proc$issuer_ls180.v:75240$3562 - assign { } { } - assign { } { } - assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:75241.5-75241.29" - switch \initial - attribute \src "issuer_ls180.v:75241.9-75241.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - case - assign $1\dec30_sgl_pipe[0:0] 1'0 - end - sync always - update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0] - end - attribute \src "issuer_ls180.v:75277.3-75313.6" - process $proc$issuer_ls180.v:75277$3563 - assign { } { } - assign { } { } - assign $0\dec30_form[4:0] $1\dec30_form[4:0] - attribute \src "issuer_ls180.v:75278.5-75278.29" - switch \initial - attribute \src "issuer_ls180.v:75278.9-75278.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_form[4:0] 5'10100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_form[4:0] 5'10100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_form[4:0] 5'10101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_form[4:0] 5'10101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_form[4:0] 5'10100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_form[4:0] 5'10100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_form[4:0] 5'10100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_form[4:0] 5'10100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_form[4:0] 5'10100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_form[4:0] 5'10100 - case - assign $1\dec30_form[4:0] 5'00000 - end - sync always - update \dec30_form $0\dec30_form[4:0] - end - attribute \src "issuer_ls180.v:75314.3-75350.6" - process $proc$issuer_ls180.v:75314$3564 - assign { } { } - assign { } { } - assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0] - attribute \src "issuer_ls180.v:75315.5-75315.29" - switch \initial - attribute \src "issuer_ls180.v:75315.9-75315.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 - case - assign $1\dec30_in1_sel[2:0] 3'000 - end - sync always - update \dec30_in1_sel $0\dec30_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:75351.3-75387.6" - process $proc$issuer_ls180.v:75351$3565 - assign { } { } - assign { } { } - assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0] - attribute \src "issuer_ls180.v:75352.5-75352.29" - switch \initial - attribute \src "issuer_ls180.v:75352.9-75352.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'0001 - case - assign $1\dec30_in2_sel[3:0] 4'0000 - end - sync always - update \dec30_in2_sel $0\dec30_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:75388.3-75424.6" - process $proc$issuer_ls180.v:75388$3566 - assign { } { } - assign { } { } - assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0] - attribute \src "issuer_ls180.v:75389.5-75389.29" - switch \initial - attribute \src "issuer_ls180.v:75389.9-75389.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - case - assign $1\dec30_in3_sel[1:0] 2'00 - end - sync always - update \dec30_in3_sel $0\dec30_in3_sel[1:0] - end - attribute \src "issuer_ls180.v:75425.3-75461.6" - process $proc$issuer_ls180.v:75425$3567 - assign { } { } - assign { } { } - assign $0\dec30_out_sel[1:0] $1\dec30_out_sel[1:0] - attribute \src "issuer_ls180.v:75426.5-75426.29" - switch \initial - attribute \src "issuer_ls180.v:75426.9-75426.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - case - assign $1\dec30_out_sel[1:0] 2'00 - end - sync always - update \dec30_out_sel $0\dec30_out_sel[1:0] - end - attribute \src "issuer_ls180.v:75462.3-75498.6" - process $proc$issuer_ls180.v:75462$3568 - assign { } { } - assign { } { } - assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0] - attribute \src "issuer_ls180.v:75463.5-75463.29" - switch \initial - attribute \src "issuer_ls180.v:75463.9-75463.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - case - assign $1\dec30_cr_in[2:0] 3'000 - end - sync always - update \dec30_cr_in $0\dec30_cr_in[2:0] - end - attribute \src "issuer_ls180.v:75499.3-75535.6" - process $proc$issuer_ls180.v:75499$3569 - assign { } { } - assign { } { } - assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0] - attribute \src "issuer_ls180.v:75500.5-75500.29" - switch \initial - attribute \src "issuer_ls180.v:75500.9-75500.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - case - assign $1\dec30_cr_out[2:0] 3'000 - end - sync always - update \dec30_cr_out $0\dec30_cr_out[2:0] - end - connect \opcode_switch \opcode_in [4:1] -end -attribute \src "issuer_ls180.v:75541.1-81911.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31" -attribute \generator "nMigen" -module \dec31 - attribute \src "issuer_ls180.v:80610.3-80670.6" - wire width 8 $0\dec31_asmcode[7:0] - attribute \src "issuer_ls180.v:81464.3-81524.6" - wire $0\dec31_br[0:0] - attribute \src "issuer_ls180.v:80915.3-80975.6" - wire width 3 $0\dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:80976.3-81036.6" - wire width 3 $0\dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:81220.3-81280.6" - wire width 2 $0\dec31_cry_in[1:0] - attribute \src "issuer_ls180.v:81403.3-81463.6" - wire $0\dec31_cry_out[0:0] - attribute \src "issuer_ls180.v:80549.3-80609.6" - wire width 5 $0\dec31_form[4:0] - attribute \src "issuer_ls180.v:80427.3-80487.6" - wire width 12 $0\dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:80671.3-80731.6" - wire width 3 $0\dec31_in1_sel[2:0] - attribute \src "issuer_ls180.v:80732.3-80792.6" - wire width 4 $0\dec31_in2_sel[3:0] - attribute \src "issuer_ls180.v:80793.3-80853.6" - wire width 2 $0\dec31_in3_sel[1:0] - attribute \src "issuer_ls180.v:80488.3-80548.6" - wire width 7 $0\dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:81281.3-81341.6" - wire $0\dec31_inv_a[0:0] - attribute \src "issuer_ls180.v:81342.3-81402.6" - wire $0\dec31_inv_out[0:0] - attribute \src "issuer_ls180.v:81647.3-81707.6" - wire $0\dec31_is_32b[0:0] - attribute \src "issuer_ls180.v:81037.3-81097.6" - wire width 4 $0\dec31_ldst_len[3:0] - attribute \src "issuer_ls180.v:81769.3-81829.6" - wire $0\dec31_lk[0:0] - attribute \src "issuer_ls180.v:80854.3-80914.6" - wire width 2 $0\dec31_out_sel[1:0] - attribute \src "issuer_ls180.v:81159.3-81219.6" - wire width 2 $0\dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:81586.3-81646.6" - wire $0\dec31_rsrv[0:0] - attribute \src "issuer_ls180.v:81830.3-81890.6" - wire $0\dec31_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:81708.3-81768.6" - wire $0\dec31_sgn[0:0] - attribute \src "issuer_ls180.v:81525.3-81585.6" - wire $0\dec31_sgn_ext[0:0] - attribute \src "issuer_ls180.v:81098.3-81158.6" - wire width 2 $0\dec31_upd[1:0] - attribute \src "issuer_ls180.v:75542.7-75542.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:80610.3-80670.6" - wire width 8 $1\dec31_asmcode[7:0] - attribute \src "issuer_ls180.v:81464.3-81524.6" - wire $1\dec31_br[0:0] - attribute \src "issuer_ls180.v:80915.3-80975.6" - wire width 3 $1\dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:80976.3-81036.6" - wire width 3 $1\dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:81220.3-81280.6" - wire width 2 $1\dec31_cry_in[1:0] - attribute \src "issuer_ls180.v:81403.3-81463.6" - wire $1\dec31_cry_out[0:0] - attribute \src "issuer_ls180.v:80549.3-80609.6" - wire width 5 $1\dec31_form[4:0] - attribute \src "issuer_ls180.v:80427.3-80487.6" - wire width 12 $1\dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:80671.3-80731.6" - wire width 3 $1\dec31_in1_sel[2:0] - attribute \src "issuer_ls180.v:80732.3-80792.6" - wire width 4 $1\dec31_in2_sel[3:0] - attribute \src "issuer_ls180.v:80793.3-80853.6" - wire width 2 $1\dec31_in3_sel[1:0] - attribute \src "issuer_ls180.v:80488.3-80548.6" - wire width 7 $1\dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:81281.3-81341.6" - wire $1\dec31_inv_a[0:0] - attribute \src "issuer_ls180.v:81342.3-81402.6" - wire $1\dec31_inv_out[0:0] - attribute \src "issuer_ls180.v:81647.3-81707.6" - wire $1\dec31_is_32b[0:0] - attribute \src "issuer_ls180.v:81037.3-81097.6" - wire width 4 $1\dec31_ldst_len[3:0] - attribute \src "issuer_ls180.v:81769.3-81829.6" - wire $1\dec31_lk[0:0] - attribute \src "issuer_ls180.v:80854.3-80914.6" - wire width 2 $1\dec31_out_sel[1:0] - attribute \src "issuer_ls180.v:81159.3-81219.6" - wire width 2 $1\dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:81586.3-81646.6" - wire $1\dec31_rsrv[0:0] - attribute \src "issuer_ls180.v:81830.3-81890.6" - wire $1\dec31_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:81708.3-81768.6" - wire $1\dec31_sgn[0:0] - attribute \src "issuer_ls180.v:81525.3-81585.6" - wire $1\dec31_sgn_ext[0:0] - attribute \src "issuer_ls180.v:81098.3-81158.6" - wire width 2 $1\dec31_upd[1:0] - attribute \src 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attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_upd - attribute \src "issuer_ls180.v:75542.7-75542.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" - wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 10 \opcode_switch - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:79941.18-79967.4" - cell \dec31_dec_sub0 \dec31_dec_sub0 - connect \dec31_dec_sub0_asmcode \dec31_dec_sub0_dec31_dec_sub0_asmcode - connect \dec31_dec_sub0_br \dec31_dec_sub0_dec31_dec_sub0_br - connect \dec31_dec_sub0_cr_in \dec31_dec_sub0_dec31_dec_sub0_cr_in - connect \dec31_dec_sub0_cr_out \dec31_dec_sub0_dec31_dec_sub0_cr_out - connect \dec31_dec_sub0_cry_in \dec31_dec_sub0_dec31_dec_sub0_cry_in - connect \dec31_dec_sub0_cry_out \dec31_dec_sub0_dec31_dec_sub0_cry_out - connect \dec31_dec_sub0_form \dec31_dec_sub0_dec31_dec_sub0_form - connect \dec31_dec_sub0_function_unit \dec31_dec_sub0_dec31_dec_sub0_function_unit - connect \dec31_dec_sub0_in1_sel \dec31_dec_sub0_dec31_dec_sub0_in1_sel - connect \dec31_dec_sub0_in2_sel \dec31_dec_sub0_dec31_dec_sub0_in2_sel - connect \dec31_dec_sub0_in3_sel \dec31_dec_sub0_dec31_dec_sub0_in3_sel - connect \dec31_dec_sub0_internal_op \dec31_dec_sub0_dec31_dec_sub0_internal_op - connect \dec31_dec_sub0_inv_a \dec31_dec_sub0_dec31_dec_sub0_inv_a - connect \dec31_dec_sub0_inv_out \dec31_dec_sub0_dec31_dec_sub0_inv_out - connect \dec31_dec_sub0_is_32b \dec31_dec_sub0_dec31_dec_sub0_is_32b - connect \dec31_dec_sub0_ldst_len \dec31_dec_sub0_dec31_dec_sub0_ldst_len - connect \dec31_dec_sub0_lk \dec31_dec_sub0_dec31_dec_sub0_lk - connect \dec31_dec_sub0_out_sel \dec31_dec_sub0_dec31_dec_sub0_out_sel - connect \dec31_dec_sub0_rc_sel \dec31_dec_sub0_dec31_dec_sub0_rc_sel - connect \dec31_dec_sub0_rsrv \dec31_dec_sub0_dec31_dec_sub0_rsrv - connect \dec31_dec_sub0_sgl_pipe \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe - connect \dec31_dec_sub0_sgn \dec31_dec_sub0_dec31_dec_sub0_sgn - connect \dec31_dec_sub0_sgn_ext \dec31_dec_sub0_dec31_dec_sub0_sgn_ext - connect \dec31_dec_sub0_upd \dec31_dec_sub0_dec31_dec_sub0_upd - connect \opcode_in \dec31_dec_sub0_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:79968.19-79994.4" - cell \dec31_dec_sub10 \dec31_dec_sub10 - connect \dec31_dec_sub10_asmcode \dec31_dec_sub10_dec31_dec_sub10_asmcode - connect \dec31_dec_sub10_br \dec31_dec_sub10_dec31_dec_sub10_br - connect \dec31_dec_sub10_cr_in \dec31_dec_sub10_dec31_dec_sub10_cr_in - connect \dec31_dec_sub10_cr_out \dec31_dec_sub10_dec31_dec_sub10_cr_out - connect \dec31_dec_sub10_cry_in \dec31_dec_sub10_dec31_dec_sub10_cry_in - connect \dec31_dec_sub10_cry_out \dec31_dec_sub10_dec31_dec_sub10_cry_out - connect \dec31_dec_sub10_form \dec31_dec_sub10_dec31_dec_sub10_form - connect \dec31_dec_sub10_function_unit \dec31_dec_sub10_dec31_dec_sub10_function_unit - connect \dec31_dec_sub10_in1_sel \dec31_dec_sub10_dec31_dec_sub10_in1_sel - connect \dec31_dec_sub10_in2_sel \dec31_dec_sub10_dec31_dec_sub10_in2_sel - connect \dec31_dec_sub10_in3_sel \dec31_dec_sub10_dec31_dec_sub10_in3_sel - connect \dec31_dec_sub10_internal_op \dec31_dec_sub10_dec31_dec_sub10_internal_op - connect \dec31_dec_sub10_inv_a \dec31_dec_sub10_dec31_dec_sub10_inv_a - connect \dec31_dec_sub10_inv_out \dec31_dec_sub10_dec31_dec_sub10_inv_out - connect \dec31_dec_sub10_is_32b \dec31_dec_sub10_dec31_dec_sub10_is_32b - connect \dec31_dec_sub10_ldst_len \dec31_dec_sub10_dec31_dec_sub10_ldst_len - connect \dec31_dec_sub10_lk \dec31_dec_sub10_dec31_dec_sub10_lk - connect \dec31_dec_sub10_out_sel \dec31_dec_sub10_dec31_dec_sub10_out_sel - connect \dec31_dec_sub10_rc_sel \dec31_dec_sub10_dec31_dec_sub10_rc_sel - connect \dec31_dec_sub10_rsrv \dec31_dec_sub10_dec31_dec_sub10_rsrv - connect \dec31_dec_sub10_sgl_pipe \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe - connect \dec31_dec_sub10_sgn \dec31_dec_sub10_dec31_dec_sub10_sgn - connect \dec31_dec_sub10_sgn_ext \dec31_dec_sub10_dec31_dec_sub10_sgn_ext - connect \dec31_dec_sub10_upd \dec31_dec_sub10_dec31_dec_sub10_upd - connect \opcode_in \dec31_dec_sub10_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:79995.19-80021.4" - cell \dec31_dec_sub11 \dec31_dec_sub11 - connect \dec31_dec_sub11_asmcode \dec31_dec_sub11_dec31_dec_sub11_asmcode - connect \dec31_dec_sub11_br \dec31_dec_sub11_dec31_dec_sub11_br - connect \dec31_dec_sub11_cr_in \dec31_dec_sub11_dec31_dec_sub11_cr_in - connect \dec31_dec_sub11_cr_out \dec31_dec_sub11_dec31_dec_sub11_cr_out - connect \dec31_dec_sub11_cry_in \dec31_dec_sub11_dec31_dec_sub11_cry_in - connect \dec31_dec_sub11_cry_out \dec31_dec_sub11_dec31_dec_sub11_cry_out - connect \dec31_dec_sub11_form \dec31_dec_sub11_dec31_dec_sub11_form - connect \dec31_dec_sub11_function_unit \dec31_dec_sub11_dec31_dec_sub11_function_unit - connect \dec31_dec_sub11_in1_sel \dec31_dec_sub11_dec31_dec_sub11_in1_sel - connect \dec31_dec_sub11_in2_sel \dec31_dec_sub11_dec31_dec_sub11_in2_sel - connect \dec31_dec_sub11_in3_sel \dec31_dec_sub11_dec31_dec_sub11_in3_sel - connect \dec31_dec_sub11_internal_op \dec31_dec_sub11_dec31_dec_sub11_internal_op - connect \dec31_dec_sub11_inv_a \dec31_dec_sub11_dec31_dec_sub11_inv_a - connect \dec31_dec_sub11_inv_out \dec31_dec_sub11_dec31_dec_sub11_inv_out - connect \dec31_dec_sub11_is_32b \dec31_dec_sub11_dec31_dec_sub11_is_32b - connect \dec31_dec_sub11_ldst_len \dec31_dec_sub11_dec31_dec_sub11_ldst_len - connect \dec31_dec_sub11_lk \dec31_dec_sub11_dec31_dec_sub11_lk - connect \dec31_dec_sub11_out_sel \dec31_dec_sub11_dec31_dec_sub11_out_sel - connect \dec31_dec_sub11_rc_sel \dec31_dec_sub11_dec31_dec_sub11_rc_sel - connect \dec31_dec_sub11_rsrv \dec31_dec_sub11_dec31_dec_sub11_rsrv - connect \dec31_dec_sub11_sgl_pipe \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe - connect \dec31_dec_sub11_sgn \dec31_dec_sub11_dec31_dec_sub11_sgn - connect \dec31_dec_sub11_sgn_ext \dec31_dec_sub11_dec31_dec_sub11_sgn_ext - connect \dec31_dec_sub11_upd \dec31_dec_sub11_dec31_dec_sub11_upd - connect \opcode_in \dec31_dec_sub11_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:80022.19-80048.4" - cell \dec31_dec_sub15 \dec31_dec_sub15 - connect \dec31_dec_sub15_asmcode \dec31_dec_sub15_dec31_dec_sub15_asmcode - connect \dec31_dec_sub15_br \dec31_dec_sub15_dec31_dec_sub15_br - connect \dec31_dec_sub15_cr_in \dec31_dec_sub15_dec31_dec_sub15_cr_in - connect \dec31_dec_sub15_cr_out \dec31_dec_sub15_dec31_dec_sub15_cr_out - connect \dec31_dec_sub15_cry_in \dec31_dec_sub15_dec31_dec_sub15_cry_in - connect \dec31_dec_sub15_cry_out \dec31_dec_sub15_dec31_dec_sub15_cry_out - connect \dec31_dec_sub15_form \dec31_dec_sub15_dec31_dec_sub15_form - connect \dec31_dec_sub15_function_unit \dec31_dec_sub15_dec31_dec_sub15_function_unit - connect \dec31_dec_sub15_in1_sel \dec31_dec_sub15_dec31_dec_sub15_in1_sel - connect \dec31_dec_sub15_in2_sel \dec31_dec_sub15_dec31_dec_sub15_in2_sel - connect \dec31_dec_sub15_in3_sel \dec31_dec_sub15_dec31_dec_sub15_in3_sel - connect \dec31_dec_sub15_internal_op \dec31_dec_sub15_dec31_dec_sub15_internal_op - connect \dec31_dec_sub15_inv_a \dec31_dec_sub15_dec31_dec_sub15_inv_a - connect \dec31_dec_sub15_inv_out \dec31_dec_sub15_dec31_dec_sub15_inv_out - connect \dec31_dec_sub15_is_32b \dec31_dec_sub15_dec31_dec_sub15_is_32b - connect \dec31_dec_sub15_ldst_len \dec31_dec_sub15_dec31_dec_sub15_ldst_len - connect \dec31_dec_sub15_lk \dec31_dec_sub15_dec31_dec_sub15_lk - connect \dec31_dec_sub15_out_sel \dec31_dec_sub15_dec31_dec_sub15_out_sel - connect \dec31_dec_sub15_rc_sel \dec31_dec_sub15_dec31_dec_sub15_rc_sel - connect \dec31_dec_sub15_rsrv \dec31_dec_sub15_dec31_dec_sub15_rsrv - connect \dec31_dec_sub15_sgl_pipe \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe - connect \dec31_dec_sub15_sgn \dec31_dec_sub15_dec31_dec_sub15_sgn - connect \dec31_dec_sub15_sgn_ext \dec31_dec_sub15_dec31_dec_sub15_sgn_ext - connect \dec31_dec_sub15_upd \dec31_dec_sub15_dec31_dec_sub15_upd - connect \opcode_in \dec31_dec_sub15_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:80049.19-80075.4" - cell \dec31_dec_sub16 \dec31_dec_sub16 - connect \dec31_dec_sub16_asmcode \dec31_dec_sub16_dec31_dec_sub16_asmcode - connect \dec31_dec_sub16_br \dec31_dec_sub16_dec31_dec_sub16_br - connect \dec31_dec_sub16_cr_in \dec31_dec_sub16_dec31_dec_sub16_cr_in - connect \dec31_dec_sub16_cr_out \dec31_dec_sub16_dec31_dec_sub16_cr_out - connect \dec31_dec_sub16_cry_in \dec31_dec_sub16_dec31_dec_sub16_cry_in - connect \dec31_dec_sub16_cry_out \dec31_dec_sub16_dec31_dec_sub16_cry_out - connect \dec31_dec_sub16_form \dec31_dec_sub16_dec31_dec_sub16_form - connect \dec31_dec_sub16_function_unit \dec31_dec_sub16_dec31_dec_sub16_function_unit - connect \dec31_dec_sub16_in1_sel \dec31_dec_sub16_dec31_dec_sub16_in1_sel - connect \dec31_dec_sub16_in2_sel \dec31_dec_sub16_dec31_dec_sub16_in2_sel - connect \dec31_dec_sub16_in3_sel \dec31_dec_sub16_dec31_dec_sub16_in3_sel - connect \dec31_dec_sub16_internal_op \dec31_dec_sub16_dec31_dec_sub16_internal_op - connect \dec31_dec_sub16_inv_a \dec31_dec_sub16_dec31_dec_sub16_inv_a - connect \dec31_dec_sub16_inv_out \dec31_dec_sub16_dec31_dec_sub16_inv_out - connect \dec31_dec_sub16_is_32b \dec31_dec_sub16_dec31_dec_sub16_is_32b - connect \dec31_dec_sub16_ldst_len \dec31_dec_sub16_dec31_dec_sub16_ldst_len - connect \dec31_dec_sub16_lk \dec31_dec_sub16_dec31_dec_sub16_lk - connect \dec31_dec_sub16_out_sel \dec31_dec_sub16_dec31_dec_sub16_out_sel - connect \dec31_dec_sub16_rc_sel \dec31_dec_sub16_dec31_dec_sub16_rc_sel - connect \dec31_dec_sub16_rsrv \dec31_dec_sub16_dec31_dec_sub16_rsrv - connect \dec31_dec_sub16_sgl_pipe \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe - connect \dec31_dec_sub16_sgn \dec31_dec_sub16_dec31_dec_sub16_sgn - connect \dec31_dec_sub16_sgn_ext \dec31_dec_sub16_dec31_dec_sub16_sgn_ext - connect \dec31_dec_sub16_upd \dec31_dec_sub16_dec31_dec_sub16_upd - connect \opcode_in \dec31_dec_sub16_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:80076.19-80102.4" - cell \dec31_dec_sub18 \dec31_dec_sub18 - connect \dec31_dec_sub18_asmcode \dec31_dec_sub18_dec31_dec_sub18_asmcode - connect \dec31_dec_sub18_br \dec31_dec_sub18_dec31_dec_sub18_br - connect \dec31_dec_sub18_cr_in \dec31_dec_sub18_dec31_dec_sub18_cr_in - connect \dec31_dec_sub18_cr_out \dec31_dec_sub18_dec31_dec_sub18_cr_out - connect \dec31_dec_sub18_cry_in \dec31_dec_sub18_dec31_dec_sub18_cry_in - connect \dec31_dec_sub18_cry_out \dec31_dec_sub18_dec31_dec_sub18_cry_out - connect \dec31_dec_sub18_form \dec31_dec_sub18_dec31_dec_sub18_form - connect \dec31_dec_sub18_function_unit \dec31_dec_sub18_dec31_dec_sub18_function_unit - connect \dec31_dec_sub18_in1_sel \dec31_dec_sub18_dec31_dec_sub18_in1_sel - connect \dec31_dec_sub18_in2_sel \dec31_dec_sub18_dec31_dec_sub18_in2_sel - connect \dec31_dec_sub18_in3_sel \dec31_dec_sub18_dec31_dec_sub18_in3_sel - connect \dec31_dec_sub18_internal_op \dec31_dec_sub18_dec31_dec_sub18_internal_op - connect \dec31_dec_sub18_inv_a \dec31_dec_sub18_dec31_dec_sub18_inv_a - connect \dec31_dec_sub18_inv_out \dec31_dec_sub18_dec31_dec_sub18_inv_out - connect \dec31_dec_sub18_is_32b \dec31_dec_sub18_dec31_dec_sub18_is_32b - connect \dec31_dec_sub18_ldst_len \dec31_dec_sub18_dec31_dec_sub18_ldst_len - connect \dec31_dec_sub18_lk \dec31_dec_sub18_dec31_dec_sub18_lk - connect \dec31_dec_sub18_out_sel \dec31_dec_sub18_dec31_dec_sub18_out_sel - connect \dec31_dec_sub18_rc_sel \dec31_dec_sub18_dec31_dec_sub18_rc_sel - connect \dec31_dec_sub18_rsrv \dec31_dec_sub18_dec31_dec_sub18_rsrv - connect \dec31_dec_sub18_sgl_pipe \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe - connect \dec31_dec_sub18_sgn \dec31_dec_sub18_dec31_dec_sub18_sgn - connect \dec31_dec_sub18_sgn_ext \dec31_dec_sub18_dec31_dec_sub18_sgn_ext - connect \dec31_dec_sub18_upd \dec31_dec_sub18_dec31_dec_sub18_upd - connect \opcode_in \dec31_dec_sub18_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:80103.19-80129.4" - cell \dec31_dec_sub19 \dec31_dec_sub19 - connect \dec31_dec_sub19_asmcode \dec31_dec_sub19_dec31_dec_sub19_asmcode - connect \dec31_dec_sub19_br \dec31_dec_sub19_dec31_dec_sub19_br - connect \dec31_dec_sub19_cr_in \dec31_dec_sub19_dec31_dec_sub19_cr_in - connect \dec31_dec_sub19_cr_out \dec31_dec_sub19_dec31_dec_sub19_cr_out - connect \dec31_dec_sub19_cry_in \dec31_dec_sub19_dec31_dec_sub19_cry_in - connect \dec31_dec_sub19_cry_out \dec31_dec_sub19_dec31_dec_sub19_cry_out - connect \dec31_dec_sub19_form \dec31_dec_sub19_dec31_dec_sub19_form - connect \dec31_dec_sub19_function_unit \dec31_dec_sub19_dec31_dec_sub19_function_unit - connect \dec31_dec_sub19_in1_sel \dec31_dec_sub19_dec31_dec_sub19_in1_sel - connect \dec31_dec_sub19_in2_sel \dec31_dec_sub19_dec31_dec_sub19_in2_sel - connect \dec31_dec_sub19_in3_sel \dec31_dec_sub19_dec31_dec_sub19_in3_sel - connect \dec31_dec_sub19_internal_op \dec31_dec_sub19_dec31_dec_sub19_internal_op - connect \dec31_dec_sub19_inv_a \dec31_dec_sub19_dec31_dec_sub19_inv_a - connect \dec31_dec_sub19_inv_out \dec31_dec_sub19_dec31_dec_sub19_inv_out - connect \dec31_dec_sub19_is_32b \dec31_dec_sub19_dec31_dec_sub19_is_32b - connect \dec31_dec_sub19_ldst_len \dec31_dec_sub19_dec31_dec_sub19_ldst_len - connect \dec31_dec_sub19_lk \dec31_dec_sub19_dec31_dec_sub19_lk - connect \dec31_dec_sub19_out_sel \dec31_dec_sub19_dec31_dec_sub19_out_sel - connect \dec31_dec_sub19_rc_sel \dec31_dec_sub19_dec31_dec_sub19_rc_sel - connect \dec31_dec_sub19_rsrv \dec31_dec_sub19_dec31_dec_sub19_rsrv - connect \dec31_dec_sub19_sgl_pipe \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe - connect \dec31_dec_sub19_sgn \dec31_dec_sub19_dec31_dec_sub19_sgn - connect \dec31_dec_sub19_sgn_ext \dec31_dec_sub19_dec31_dec_sub19_sgn_ext - connect \dec31_dec_sub19_upd \dec31_dec_sub19_dec31_dec_sub19_upd - connect \opcode_in \dec31_dec_sub19_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:80130.19-80156.4" - cell \dec31_dec_sub20 \dec31_dec_sub20 - connect \dec31_dec_sub20_asmcode \dec31_dec_sub20_dec31_dec_sub20_asmcode - connect \dec31_dec_sub20_br \dec31_dec_sub20_dec31_dec_sub20_br - connect \dec31_dec_sub20_cr_in \dec31_dec_sub20_dec31_dec_sub20_cr_in - connect \dec31_dec_sub20_cr_out \dec31_dec_sub20_dec31_dec_sub20_cr_out - connect \dec31_dec_sub20_cry_in \dec31_dec_sub20_dec31_dec_sub20_cry_in - connect \dec31_dec_sub20_cry_out \dec31_dec_sub20_dec31_dec_sub20_cry_out - connect \dec31_dec_sub20_form \dec31_dec_sub20_dec31_dec_sub20_form - connect \dec31_dec_sub20_function_unit \dec31_dec_sub20_dec31_dec_sub20_function_unit - connect \dec31_dec_sub20_in1_sel \dec31_dec_sub20_dec31_dec_sub20_in1_sel - connect \dec31_dec_sub20_in2_sel \dec31_dec_sub20_dec31_dec_sub20_in2_sel - connect \dec31_dec_sub20_in3_sel \dec31_dec_sub20_dec31_dec_sub20_in3_sel - connect \dec31_dec_sub20_internal_op \dec31_dec_sub20_dec31_dec_sub20_internal_op - connect \dec31_dec_sub20_inv_a \dec31_dec_sub20_dec31_dec_sub20_inv_a - connect \dec31_dec_sub20_inv_out \dec31_dec_sub20_dec31_dec_sub20_inv_out - connect \dec31_dec_sub20_is_32b \dec31_dec_sub20_dec31_dec_sub20_is_32b - connect \dec31_dec_sub20_ldst_len \dec31_dec_sub20_dec31_dec_sub20_ldst_len - connect \dec31_dec_sub20_lk \dec31_dec_sub20_dec31_dec_sub20_lk - connect \dec31_dec_sub20_out_sel \dec31_dec_sub20_dec31_dec_sub20_out_sel - connect \dec31_dec_sub20_rc_sel \dec31_dec_sub20_dec31_dec_sub20_rc_sel - connect \dec31_dec_sub20_rsrv \dec31_dec_sub20_dec31_dec_sub20_rsrv - connect \dec31_dec_sub20_sgl_pipe \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe - connect \dec31_dec_sub20_sgn \dec31_dec_sub20_dec31_dec_sub20_sgn - connect \dec31_dec_sub20_sgn_ext \dec31_dec_sub20_dec31_dec_sub20_sgn_ext - connect \dec31_dec_sub20_upd \dec31_dec_sub20_dec31_dec_sub20_upd - connect \opcode_in \dec31_dec_sub20_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:80157.19-80183.4" - cell \dec31_dec_sub21 \dec31_dec_sub21 - connect \dec31_dec_sub21_asmcode \dec31_dec_sub21_dec31_dec_sub21_asmcode - connect \dec31_dec_sub21_br \dec31_dec_sub21_dec31_dec_sub21_br - connect \dec31_dec_sub21_cr_in \dec31_dec_sub21_dec31_dec_sub21_cr_in - connect \dec31_dec_sub21_cr_out \dec31_dec_sub21_dec31_dec_sub21_cr_out - connect \dec31_dec_sub21_cry_in \dec31_dec_sub21_dec31_dec_sub21_cry_in - connect \dec31_dec_sub21_cry_out \dec31_dec_sub21_dec31_dec_sub21_cry_out - connect \dec31_dec_sub21_form \dec31_dec_sub21_dec31_dec_sub21_form - connect \dec31_dec_sub21_function_unit \dec31_dec_sub21_dec31_dec_sub21_function_unit - connect \dec31_dec_sub21_in1_sel \dec31_dec_sub21_dec31_dec_sub21_in1_sel - connect \dec31_dec_sub21_in2_sel \dec31_dec_sub21_dec31_dec_sub21_in2_sel - connect \dec31_dec_sub21_in3_sel \dec31_dec_sub21_dec31_dec_sub21_in3_sel - connect \dec31_dec_sub21_internal_op \dec31_dec_sub21_dec31_dec_sub21_internal_op - connect \dec31_dec_sub21_inv_a \dec31_dec_sub21_dec31_dec_sub21_inv_a - connect \dec31_dec_sub21_inv_out \dec31_dec_sub21_dec31_dec_sub21_inv_out - connect \dec31_dec_sub21_is_32b \dec31_dec_sub21_dec31_dec_sub21_is_32b - connect \dec31_dec_sub21_ldst_len \dec31_dec_sub21_dec31_dec_sub21_ldst_len - connect \dec31_dec_sub21_lk \dec31_dec_sub21_dec31_dec_sub21_lk - connect \dec31_dec_sub21_out_sel \dec31_dec_sub21_dec31_dec_sub21_out_sel - connect \dec31_dec_sub21_rc_sel \dec31_dec_sub21_dec31_dec_sub21_rc_sel - connect \dec31_dec_sub21_rsrv \dec31_dec_sub21_dec31_dec_sub21_rsrv - connect \dec31_dec_sub21_sgl_pipe \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe - connect \dec31_dec_sub21_sgn \dec31_dec_sub21_dec31_dec_sub21_sgn - connect \dec31_dec_sub21_sgn_ext \dec31_dec_sub21_dec31_dec_sub21_sgn_ext - connect \dec31_dec_sub21_upd \dec31_dec_sub21_dec31_dec_sub21_upd - connect \opcode_in \dec31_dec_sub21_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:80184.19-80210.4" - cell \dec31_dec_sub22 \dec31_dec_sub22 - connect \dec31_dec_sub22_asmcode \dec31_dec_sub22_dec31_dec_sub22_asmcode - connect \dec31_dec_sub22_br \dec31_dec_sub22_dec31_dec_sub22_br - connect \dec31_dec_sub22_cr_in \dec31_dec_sub22_dec31_dec_sub22_cr_in - connect \dec31_dec_sub22_cr_out \dec31_dec_sub22_dec31_dec_sub22_cr_out - connect \dec31_dec_sub22_cry_in \dec31_dec_sub22_dec31_dec_sub22_cry_in - connect \dec31_dec_sub22_cry_out \dec31_dec_sub22_dec31_dec_sub22_cry_out - connect \dec31_dec_sub22_form \dec31_dec_sub22_dec31_dec_sub22_form - connect \dec31_dec_sub22_function_unit \dec31_dec_sub22_dec31_dec_sub22_function_unit - connect \dec31_dec_sub22_in1_sel \dec31_dec_sub22_dec31_dec_sub22_in1_sel - connect \dec31_dec_sub22_in2_sel \dec31_dec_sub22_dec31_dec_sub22_in2_sel - connect \dec31_dec_sub22_in3_sel \dec31_dec_sub22_dec31_dec_sub22_in3_sel - connect \dec31_dec_sub22_internal_op \dec31_dec_sub22_dec31_dec_sub22_internal_op - connect \dec31_dec_sub22_inv_a \dec31_dec_sub22_dec31_dec_sub22_inv_a - connect \dec31_dec_sub22_inv_out \dec31_dec_sub22_dec31_dec_sub22_inv_out - connect \dec31_dec_sub22_is_32b \dec31_dec_sub22_dec31_dec_sub22_is_32b - connect \dec31_dec_sub22_ldst_len \dec31_dec_sub22_dec31_dec_sub22_ldst_len - connect \dec31_dec_sub22_lk \dec31_dec_sub22_dec31_dec_sub22_lk - connect \dec31_dec_sub22_out_sel \dec31_dec_sub22_dec31_dec_sub22_out_sel - connect \dec31_dec_sub22_rc_sel \dec31_dec_sub22_dec31_dec_sub22_rc_sel - connect \dec31_dec_sub22_rsrv \dec31_dec_sub22_dec31_dec_sub22_rsrv - connect \dec31_dec_sub22_sgl_pipe \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe - connect \dec31_dec_sub22_sgn \dec31_dec_sub22_dec31_dec_sub22_sgn - connect \dec31_dec_sub22_sgn_ext \dec31_dec_sub22_dec31_dec_sub22_sgn_ext - connect \dec31_dec_sub22_upd \dec31_dec_sub22_dec31_dec_sub22_upd - connect \opcode_in \dec31_dec_sub22_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:80211.19-80237.4" - cell \dec31_dec_sub23 \dec31_dec_sub23 - connect \dec31_dec_sub23_asmcode \dec31_dec_sub23_dec31_dec_sub23_asmcode - connect \dec31_dec_sub23_br \dec31_dec_sub23_dec31_dec_sub23_br - connect \dec31_dec_sub23_cr_in \dec31_dec_sub23_dec31_dec_sub23_cr_in - connect \dec31_dec_sub23_cr_out \dec31_dec_sub23_dec31_dec_sub23_cr_out - connect \dec31_dec_sub23_cry_in \dec31_dec_sub23_dec31_dec_sub23_cry_in - connect \dec31_dec_sub23_cry_out \dec31_dec_sub23_dec31_dec_sub23_cry_out - connect \dec31_dec_sub23_form \dec31_dec_sub23_dec31_dec_sub23_form - connect \dec31_dec_sub23_function_unit \dec31_dec_sub23_dec31_dec_sub23_function_unit - connect \dec31_dec_sub23_in1_sel \dec31_dec_sub23_dec31_dec_sub23_in1_sel - connect \dec31_dec_sub23_in2_sel \dec31_dec_sub23_dec31_dec_sub23_in2_sel - connect \dec31_dec_sub23_in3_sel \dec31_dec_sub23_dec31_dec_sub23_in3_sel - connect \dec31_dec_sub23_internal_op \dec31_dec_sub23_dec31_dec_sub23_internal_op - connect \dec31_dec_sub23_inv_a \dec31_dec_sub23_dec31_dec_sub23_inv_a - connect \dec31_dec_sub23_inv_out \dec31_dec_sub23_dec31_dec_sub23_inv_out - connect \dec31_dec_sub23_is_32b \dec31_dec_sub23_dec31_dec_sub23_is_32b - connect \dec31_dec_sub23_ldst_len \dec31_dec_sub23_dec31_dec_sub23_ldst_len - connect \dec31_dec_sub23_lk \dec31_dec_sub23_dec31_dec_sub23_lk - connect \dec31_dec_sub23_out_sel \dec31_dec_sub23_dec31_dec_sub23_out_sel - connect \dec31_dec_sub23_rc_sel \dec31_dec_sub23_dec31_dec_sub23_rc_sel - connect \dec31_dec_sub23_rsrv \dec31_dec_sub23_dec31_dec_sub23_rsrv - connect \dec31_dec_sub23_sgl_pipe \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe - connect \dec31_dec_sub23_sgn \dec31_dec_sub23_dec31_dec_sub23_sgn - connect \dec31_dec_sub23_sgn_ext \dec31_dec_sub23_dec31_dec_sub23_sgn_ext - connect \dec31_dec_sub23_upd \dec31_dec_sub23_dec31_dec_sub23_upd - connect \opcode_in \dec31_dec_sub23_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:80238.19-80264.4" - cell \dec31_dec_sub24 \dec31_dec_sub24 - connect \dec31_dec_sub24_asmcode \dec31_dec_sub24_dec31_dec_sub24_asmcode - connect \dec31_dec_sub24_br \dec31_dec_sub24_dec31_dec_sub24_br - connect \dec31_dec_sub24_cr_in \dec31_dec_sub24_dec31_dec_sub24_cr_in - connect \dec31_dec_sub24_cr_out \dec31_dec_sub24_dec31_dec_sub24_cr_out - connect \dec31_dec_sub24_cry_in \dec31_dec_sub24_dec31_dec_sub24_cry_in - connect \dec31_dec_sub24_cry_out \dec31_dec_sub24_dec31_dec_sub24_cry_out - connect \dec31_dec_sub24_form \dec31_dec_sub24_dec31_dec_sub24_form - connect \dec31_dec_sub24_function_unit \dec31_dec_sub24_dec31_dec_sub24_function_unit - connect \dec31_dec_sub24_in1_sel \dec31_dec_sub24_dec31_dec_sub24_in1_sel - connect \dec31_dec_sub24_in2_sel \dec31_dec_sub24_dec31_dec_sub24_in2_sel - connect \dec31_dec_sub24_in3_sel \dec31_dec_sub24_dec31_dec_sub24_in3_sel - connect \dec31_dec_sub24_internal_op \dec31_dec_sub24_dec31_dec_sub24_internal_op - connect \dec31_dec_sub24_inv_a \dec31_dec_sub24_dec31_dec_sub24_inv_a - connect \dec31_dec_sub24_inv_out \dec31_dec_sub24_dec31_dec_sub24_inv_out - connect \dec31_dec_sub24_is_32b \dec31_dec_sub24_dec31_dec_sub24_is_32b - connect \dec31_dec_sub24_ldst_len \dec31_dec_sub24_dec31_dec_sub24_ldst_len - connect \dec31_dec_sub24_lk \dec31_dec_sub24_dec31_dec_sub24_lk - connect \dec31_dec_sub24_out_sel \dec31_dec_sub24_dec31_dec_sub24_out_sel - connect \dec31_dec_sub24_rc_sel \dec31_dec_sub24_dec31_dec_sub24_rc_sel - connect \dec31_dec_sub24_rsrv \dec31_dec_sub24_dec31_dec_sub24_rsrv - connect \dec31_dec_sub24_sgl_pipe \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe - connect \dec31_dec_sub24_sgn \dec31_dec_sub24_dec31_dec_sub24_sgn - connect \dec31_dec_sub24_sgn_ext \dec31_dec_sub24_dec31_dec_sub24_sgn_ext - connect \dec31_dec_sub24_upd \dec31_dec_sub24_dec31_dec_sub24_upd - connect \opcode_in \dec31_dec_sub24_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:80265.19-80291.4" - cell \dec31_dec_sub26 \dec31_dec_sub26 - connect \dec31_dec_sub26_asmcode \dec31_dec_sub26_dec31_dec_sub26_asmcode - connect \dec31_dec_sub26_br \dec31_dec_sub26_dec31_dec_sub26_br - connect \dec31_dec_sub26_cr_in \dec31_dec_sub26_dec31_dec_sub26_cr_in - connect \dec31_dec_sub26_cr_out \dec31_dec_sub26_dec31_dec_sub26_cr_out - connect \dec31_dec_sub26_cry_in \dec31_dec_sub26_dec31_dec_sub26_cry_in - connect \dec31_dec_sub26_cry_out \dec31_dec_sub26_dec31_dec_sub26_cry_out - connect \dec31_dec_sub26_form \dec31_dec_sub26_dec31_dec_sub26_form - connect \dec31_dec_sub26_function_unit \dec31_dec_sub26_dec31_dec_sub26_function_unit - connect \dec31_dec_sub26_in1_sel \dec31_dec_sub26_dec31_dec_sub26_in1_sel - connect \dec31_dec_sub26_in2_sel \dec31_dec_sub26_dec31_dec_sub26_in2_sel - connect \dec31_dec_sub26_in3_sel \dec31_dec_sub26_dec31_dec_sub26_in3_sel - connect \dec31_dec_sub26_internal_op \dec31_dec_sub26_dec31_dec_sub26_internal_op - connect \dec31_dec_sub26_inv_a \dec31_dec_sub26_dec31_dec_sub26_inv_a - connect \dec31_dec_sub26_inv_out \dec31_dec_sub26_dec31_dec_sub26_inv_out - connect \dec31_dec_sub26_is_32b \dec31_dec_sub26_dec31_dec_sub26_is_32b - connect \dec31_dec_sub26_ldst_len \dec31_dec_sub26_dec31_dec_sub26_ldst_len - connect \dec31_dec_sub26_lk \dec31_dec_sub26_dec31_dec_sub26_lk - connect \dec31_dec_sub26_out_sel \dec31_dec_sub26_dec31_dec_sub26_out_sel - connect \dec31_dec_sub26_rc_sel \dec31_dec_sub26_dec31_dec_sub26_rc_sel - connect \dec31_dec_sub26_rsrv \dec31_dec_sub26_dec31_dec_sub26_rsrv - connect \dec31_dec_sub26_sgl_pipe \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe - connect \dec31_dec_sub26_sgn \dec31_dec_sub26_dec31_dec_sub26_sgn - connect \dec31_dec_sub26_sgn_ext \dec31_dec_sub26_dec31_dec_sub26_sgn_ext - connect \dec31_dec_sub26_upd \dec31_dec_sub26_dec31_dec_sub26_upd - connect \opcode_in \dec31_dec_sub26_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:80292.19-80318.4" - cell \dec31_dec_sub27 \dec31_dec_sub27 - connect \dec31_dec_sub27_asmcode \dec31_dec_sub27_dec31_dec_sub27_asmcode - connect \dec31_dec_sub27_br \dec31_dec_sub27_dec31_dec_sub27_br - connect \dec31_dec_sub27_cr_in \dec31_dec_sub27_dec31_dec_sub27_cr_in - connect \dec31_dec_sub27_cr_out \dec31_dec_sub27_dec31_dec_sub27_cr_out - connect \dec31_dec_sub27_cry_in \dec31_dec_sub27_dec31_dec_sub27_cry_in - connect \dec31_dec_sub27_cry_out \dec31_dec_sub27_dec31_dec_sub27_cry_out - connect \dec31_dec_sub27_form \dec31_dec_sub27_dec31_dec_sub27_form - connect \dec31_dec_sub27_function_unit \dec31_dec_sub27_dec31_dec_sub27_function_unit - connect \dec31_dec_sub27_in1_sel \dec31_dec_sub27_dec31_dec_sub27_in1_sel - connect \dec31_dec_sub27_in2_sel \dec31_dec_sub27_dec31_dec_sub27_in2_sel - connect \dec31_dec_sub27_in3_sel \dec31_dec_sub27_dec31_dec_sub27_in3_sel - connect \dec31_dec_sub27_internal_op \dec31_dec_sub27_dec31_dec_sub27_internal_op - connect \dec31_dec_sub27_inv_a \dec31_dec_sub27_dec31_dec_sub27_inv_a - connect \dec31_dec_sub27_inv_out \dec31_dec_sub27_dec31_dec_sub27_inv_out - connect \dec31_dec_sub27_is_32b \dec31_dec_sub27_dec31_dec_sub27_is_32b - connect \dec31_dec_sub27_ldst_len \dec31_dec_sub27_dec31_dec_sub27_ldst_len - connect \dec31_dec_sub27_lk \dec31_dec_sub27_dec31_dec_sub27_lk - connect \dec31_dec_sub27_out_sel \dec31_dec_sub27_dec31_dec_sub27_out_sel - connect \dec31_dec_sub27_rc_sel \dec31_dec_sub27_dec31_dec_sub27_rc_sel - connect \dec31_dec_sub27_rsrv \dec31_dec_sub27_dec31_dec_sub27_rsrv - connect \dec31_dec_sub27_sgl_pipe \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe - connect \dec31_dec_sub27_sgn \dec31_dec_sub27_dec31_dec_sub27_sgn - connect \dec31_dec_sub27_sgn_ext \dec31_dec_sub27_dec31_dec_sub27_sgn_ext - connect \dec31_dec_sub27_upd \dec31_dec_sub27_dec31_dec_sub27_upd - connect \opcode_in \dec31_dec_sub27_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:80319.19-80345.4" - cell \dec31_dec_sub28 \dec31_dec_sub28 - connect \dec31_dec_sub28_asmcode \dec31_dec_sub28_dec31_dec_sub28_asmcode - connect \dec31_dec_sub28_br \dec31_dec_sub28_dec31_dec_sub28_br - connect \dec31_dec_sub28_cr_in \dec31_dec_sub28_dec31_dec_sub28_cr_in - connect \dec31_dec_sub28_cr_out \dec31_dec_sub28_dec31_dec_sub28_cr_out - connect \dec31_dec_sub28_cry_in \dec31_dec_sub28_dec31_dec_sub28_cry_in - connect \dec31_dec_sub28_cry_out \dec31_dec_sub28_dec31_dec_sub28_cry_out - connect \dec31_dec_sub28_form \dec31_dec_sub28_dec31_dec_sub28_form - connect \dec31_dec_sub28_function_unit \dec31_dec_sub28_dec31_dec_sub28_function_unit - connect \dec31_dec_sub28_in1_sel \dec31_dec_sub28_dec31_dec_sub28_in1_sel - connect \dec31_dec_sub28_in2_sel \dec31_dec_sub28_dec31_dec_sub28_in2_sel - connect \dec31_dec_sub28_in3_sel \dec31_dec_sub28_dec31_dec_sub28_in3_sel - connect \dec31_dec_sub28_internal_op \dec31_dec_sub28_dec31_dec_sub28_internal_op - connect \dec31_dec_sub28_inv_a \dec31_dec_sub28_dec31_dec_sub28_inv_a - connect \dec31_dec_sub28_inv_out \dec31_dec_sub28_dec31_dec_sub28_inv_out - connect \dec31_dec_sub28_is_32b \dec31_dec_sub28_dec31_dec_sub28_is_32b - connect \dec31_dec_sub28_ldst_len \dec31_dec_sub28_dec31_dec_sub28_ldst_len - connect \dec31_dec_sub28_lk \dec31_dec_sub28_dec31_dec_sub28_lk - connect \dec31_dec_sub28_out_sel \dec31_dec_sub28_dec31_dec_sub28_out_sel - connect \dec31_dec_sub28_rc_sel \dec31_dec_sub28_dec31_dec_sub28_rc_sel - connect \dec31_dec_sub28_rsrv \dec31_dec_sub28_dec31_dec_sub28_rsrv - connect \dec31_dec_sub28_sgl_pipe \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe - connect \dec31_dec_sub28_sgn \dec31_dec_sub28_dec31_dec_sub28_sgn - connect \dec31_dec_sub28_sgn_ext \dec31_dec_sub28_dec31_dec_sub28_sgn_ext - connect \dec31_dec_sub28_upd \dec31_dec_sub28_dec31_dec_sub28_upd - connect \opcode_in \dec31_dec_sub28_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:80346.18-80372.4" - cell \dec31_dec_sub4 \dec31_dec_sub4 - connect \dec31_dec_sub4_asmcode \dec31_dec_sub4_dec31_dec_sub4_asmcode - connect \dec31_dec_sub4_br \dec31_dec_sub4_dec31_dec_sub4_br - connect \dec31_dec_sub4_cr_in \dec31_dec_sub4_dec31_dec_sub4_cr_in - connect \dec31_dec_sub4_cr_out \dec31_dec_sub4_dec31_dec_sub4_cr_out - connect \dec31_dec_sub4_cry_in \dec31_dec_sub4_dec31_dec_sub4_cry_in - connect \dec31_dec_sub4_cry_out \dec31_dec_sub4_dec31_dec_sub4_cry_out - connect \dec31_dec_sub4_form \dec31_dec_sub4_dec31_dec_sub4_form - connect \dec31_dec_sub4_function_unit \dec31_dec_sub4_dec31_dec_sub4_function_unit - connect \dec31_dec_sub4_in1_sel \dec31_dec_sub4_dec31_dec_sub4_in1_sel - connect \dec31_dec_sub4_in2_sel \dec31_dec_sub4_dec31_dec_sub4_in2_sel - connect \dec31_dec_sub4_in3_sel \dec31_dec_sub4_dec31_dec_sub4_in3_sel - connect \dec31_dec_sub4_internal_op \dec31_dec_sub4_dec31_dec_sub4_internal_op - connect \dec31_dec_sub4_inv_a \dec31_dec_sub4_dec31_dec_sub4_inv_a - connect \dec31_dec_sub4_inv_out \dec31_dec_sub4_dec31_dec_sub4_inv_out - connect \dec31_dec_sub4_is_32b \dec31_dec_sub4_dec31_dec_sub4_is_32b - connect \dec31_dec_sub4_ldst_len \dec31_dec_sub4_dec31_dec_sub4_ldst_len - connect \dec31_dec_sub4_lk \dec31_dec_sub4_dec31_dec_sub4_lk - connect \dec31_dec_sub4_out_sel \dec31_dec_sub4_dec31_dec_sub4_out_sel - connect \dec31_dec_sub4_rc_sel \dec31_dec_sub4_dec31_dec_sub4_rc_sel - connect \dec31_dec_sub4_rsrv \dec31_dec_sub4_dec31_dec_sub4_rsrv - connect \dec31_dec_sub4_sgl_pipe \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe - connect \dec31_dec_sub4_sgn \dec31_dec_sub4_dec31_dec_sub4_sgn - connect \dec31_dec_sub4_sgn_ext \dec31_dec_sub4_dec31_dec_sub4_sgn_ext - connect \dec31_dec_sub4_upd \dec31_dec_sub4_dec31_dec_sub4_upd - connect \opcode_in \dec31_dec_sub4_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:80373.18-80399.4" - cell \dec31_dec_sub8 \dec31_dec_sub8 - connect \dec31_dec_sub8_asmcode \dec31_dec_sub8_dec31_dec_sub8_asmcode - connect \dec31_dec_sub8_br \dec31_dec_sub8_dec31_dec_sub8_br - connect \dec31_dec_sub8_cr_in \dec31_dec_sub8_dec31_dec_sub8_cr_in - connect \dec31_dec_sub8_cr_out \dec31_dec_sub8_dec31_dec_sub8_cr_out - connect \dec31_dec_sub8_cry_in \dec31_dec_sub8_dec31_dec_sub8_cry_in - connect \dec31_dec_sub8_cry_out \dec31_dec_sub8_dec31_dec_sub8_cry_out - connect \dec31_dec_sub8_form \dec31_dec_sub8_dec31_dec_sub8_form - connect \dec31_dec_sub8_function_unit \dec31_dec_sub8_dec31_dec_sub8_function_unit - connect \dec31_dec_sub8_in1_sel \dec31_dec_sub8_dec31_dec_sub8_in1_sel - connect \dec31_dec_sub8_in2_sel \dec31_dec_sub8_dec31_dec_sub8_in2_sel - connect \dec31_dec_sub8_in3_sel \dec31_dec_sub8_dec31_dec_sub8_in3_sel - connect \dec31_dec_sub8_internal_op \dec31_dec_sub8_dec31_dec_sub8_internal_op - connect \dec31_dec_sub8_inv_a \dec31_dec_sub8_dec31_dec_sub8_inv_a - connect \dec31_dec_sub8_inv_out \dec31_dec_sub8_dec31_dec_sub8_inv_out - connect \dec31_dec_sub8_is_32b \dec31_dec_sub8_dec31_dec_sub8_is_32b - connect \dec31_dec_sub8_ldst_len \dec31_dec_sub8_dec31_dec_sub8_ldst_len - connect \dec31_dec_sub8_lk \dec31_dec_sub8_dec31_dec_sub8_lk - connect \dec31_dec_sub8_out_sel \dec31_dec_sub8_dec31_dec_sub8_out_sel - connect \dec31_dec_sub8_rc_sel \dec31_dec_sub8_dec31_dec_sub8_rc_sel - connect \dec31_dec_sub8_rsrv \dec31_dec_sub8_dec31_dec_sub8_rsrv - connect \dec31_dec_sub8_sgl_pipe \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe - connect \dec31_dec_sub8_sgn \dec31_dec_sub8_dec31_dec_sub8_sgn - connect \dec31_dec_sub8_sgn_ext \dec31_dec_sub8_dec31_dec_sub8_sgn_ext - connect \dec31_dec_sub8_upd \dec31_dec_sub8_dec31_dec_sub8_upd - connect \opcode_in \dec31_dec_sub8_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:80400.18-80426.4" - cell \dec31_dec_sub9 \dec31_dec_sub9 - connect \dec31_dec_sub9_asmcode \dec31_dec_sub9_dec31_dec_sub9_asmcode - connect \dec31_dec_sub9_br \dec31_dec_sub9_dec31_dec_sub9_br - connect \dec31_dec_sub9_cr_in \dec31_dec_sub9_dec31_dec_sub9_cr_in - connect \dec31_dec_sub9_cr_out \dec31_dec_sub9_dec31_dec_sub9_cr_out - connect \dec31_dec_sub9_cry_in \dec31_dec_sub9_dec31_dec_sub9_cry_in - connect \dec31_dec_sub9_cry_out \dec31_dec_sub9_dec31_dec_sub9_cry_out - connect \dec31_dec_sub9_form \dec31_dec_sub9_dec31_dec_sub9_form - connect \dec31_dec_sub9_function_unit \dec31_dec_sub9_dec31_dec_sub9_function_unit - connect \dec31_dec_sub9_in1_sel \dec31_dec_sub9_dec31_dec_sub9_in1_sel - connect \dec31_dec_sub9_in2_sel \dec31_dec_sub9_dec31_dec_sub9_in2_sel - connect \dec31_dec_sub9_in3_sel \dec31_dec_sub9_dec31_dec_sub9_in3_sel - connect \dec31_dec_sub9_internal_op \dec31_dec_sub9_dec31_dec_sub9_internal_op - connect \dec31_dec_sub9_inv_a \dec31_dec_sub9_dec31_dec_sub9_inv_a - connect \dec31_dec_sub9_inv_out \dec31_dec_sub9_dec31_dec_sub9_inv_out - connect \dec31_dec_sub9_is_32b \dec31_dec_sub9_dec31_dec_sub9_is_32b - connect \dec31_dec_sub9_ldst_len \dec31_dec_sub9_dec31_dec_sub9_ldst_len - connect \dec31_dec_sub9_lk \dec31_dec_sub9_dec31_dec_sub9_lk - connect \dec31_dec_sub9_out_sel \dec31_dec_sub9_dec31_dec_sub9_out_sel - connect \dec31_dec_sub9_rc_sel \dec31_dec_sub9_dec31_dec_sub9_rc_sel - connect \dec31_dec_sub9_rsrv \dec31_dec_sub9_dec31_dec_sub9_rsrv - connect \dec31_dec_sub9_sgl_pipe \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe - connect \dec31_dec_sub9_sgn \dec31_dec_sub9_dec31_dec_sub9_sgn - connect \dec31_dec_sub9_sgn_ext \dec31_dec_sub9_dec31_dec_sub9_sgn_ext - connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd - connect \opcode_in \dec31_dec_sub9_opcode_in - end - attribute \src "issuer_ls180.v:75542.7-75542.20" - process $proc$issuer_ls180.v:75542$3595 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:80427.3-80487.6" - process $proc$issuer_ls180.v:80427$3571 - assign { } { } - assign { } { } - assign $0\dec31_function_unit[11:0] $1\dec31_function_unit[11:0] - attribute \src "issuer_ls180.v:80428.5-80428.29" - switch \initial - attribute \src "issuer_ls180.v:80428.9-80428.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub10_dec31_dec_sub10_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub28_dec31_dec_sub28_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub0_dec31_dec_sub0_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub26_dec31_dec_sub26_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub19_dec31_dec_sub19_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub22_dec31_dec_sub22_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub9_dec31_dec_sub9_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub11_dec31_dec_sub11_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub27_dec31_dec_sub27_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub15_dec31_dec_sub15_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub20_dec31_dec_sub20_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub21_dec31_dec_sub21_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub23_dec31_dec_sub23_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub16_dec31_dec_sub16_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub18_dec31_dec_sub18_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub8_dec31_dec_sub8_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub24_dec31_dec_sub24_function_unit - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub4_dec31_dec_sub4_function_unit - case - assign $1\dec31_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_function_unit $0\dec31_function_unit[11:0] - end - attribute \src "issuer_ls180.v:80488.3-80548.6" - process $proc$issuer_ls180.v:80488$3572 - assign { } { } - assign { } { } - assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0] - attribute \src "issuer_ls180.v:80489.5-80489.29" - switch \initial - attribute \src "issuer_ls180.v:80489.9-80489.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub10_dec31_dec_sub10_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub28_dec31_dec_sub28_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub0_dec31_dec_sub0_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub26_dec31_dec_sub26_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub19_dec31_dec_sub19_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub22_dec31_dec_sub22_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub9_dec31_dec_sub9_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub11_dec31_dec_sub11_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub27_dec31_dec_sub27_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub15_dec31_dec_sub15_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub20_dec31_dec_sub20_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub21_dec31_dec_sub21_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub23_dec31_dec_sub23_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub16_dec31_dec_sub16_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub18_dec31_dec_sub18_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub8_dec31_dec_sub8_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub24_dec31_dec_sub24_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub4_dec31_dec_sub4_internal_op - case - assign $1\dec31_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_internal_op $0\dec31_internal_op[6:0] - end - attribute \src "issuer_ls180.v:80549.3-80609.6" - process $proc$issuer_ls180.v:80549$3573 - assign { } { } - assign { } { } - assign $0\dec31_form[4:0] $1\dec31_form[4:0] - attribute \src "issuer_ls180.v:80550.5-80550.29" - switch \initial - attribute \src "issuer_ls180.v:80550.9-80550.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub10_dec31_dec_sub10_form - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub28_dec31_dec_sub28_form - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub0_dec31_dec_sub0_form - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub26_dec31_dec_sub26_form - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub19_dec31_dec_sub19_form - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub22_dec31_dec_sub22_form - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub9_dec31_dec_sub9_form - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub11_dec31_dec_sub11_form - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub27_dec31_dec_sub27_form - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub15_dec31_dec_sub15_form - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub20_dec31_dec_sub20_form - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub21_dec31_dec_sub21_form - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub23_dec31_dec_sub23_form - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub16_dec31_dec_sub16_form - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub18_dec31_dec_sub18_form - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub8_dec31_dec_sub8_form - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub24_dec31_dec_sub24_form - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub4_dec31_dec_sub4_form - case - assign $1\dec31_form[4:0] 5'00000 - end - sync always - update \dec31_form $0\dec31_form[4:0] - end - attribute \src "issuer_ls180.v:80610.3-80670.6" - process $proc$issuer_ls180.v:80610$3574 - assign { } { } - assign { } { } - assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0] - attribute \src "issuer_ls180.v:80611.5-80611.29" - switch \initial - attribute \src "issuer_ls180.v:80611.9-80611.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub10_dec31_dec_sub10_asmcode - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub28_dec31_dec_sub28_asmcode - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub0_dec31_dec_sub0_asmcode - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub26_dec31_dec_sub26_asmcode - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub19_dec31_dec_sub19_asmcode - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub22_dec31_dec_sub22_asmcode - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub9_dec31_dec_sub9_asmcode - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub11_dec31_dec_sub11_asmcode - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub27_dec31_dec_sub27_asmcode - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub15_dec31_dec_sub15_asmcode - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub20_dec31_dec_sub20_asmcode - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub21_dec31_dec_sub21_asmcode - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub23_dec31_dec_sub23_asmcode - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub16_dec31_dec_sub16_asmcode - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub18_dec31_dec_sub18_asmcode - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub8_dec31_dec_sub8_asmcode - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub24_dec31_dec_sub24_asmcode - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub4_dec31_dec_sub4_asmcode - case - assign $1\dec31_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_asmcode $0\dec31_asmcode[7:0] - end - attribute \src "issuer_ls180.v:80671.3-80731.6" - process $proc$issuer_ls180.v:80671$3575 - assign { } { } - assign { } { } - assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0] - attribute \src "issuer_ls180.v:80672.5-80672.29" - switch \initial - attribute \src "issuer_ls180.v:80672.9-80672.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub10_dec31_dec_sub10_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub28_dec31_dec_sub28_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub0_dec31_dec_sub0_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub26_dec31_dec_sub26_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub19_dec31_dec_sub19_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub22_dec31_dec_sub22_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub9_dec31_dec_sub9_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub11_dec31_dec_sub11_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub27_dec31_dec_sub27_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub15_dec31_dec_sub15_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub20_dec31_dec_sub20_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub21_dec31_dec_sub21_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub23_dec31_dec_sub23_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub16_dec31_dec_sub16_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub18_dec31_dec_sub18_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub8_dec31_dec_sub8_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub24_dec31_dec_sub24_in1_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub4_dec31_dec_sub4_in1_sel - case - assign $1\dec31_in1_sel[2:0] 3'000 - end - sync always - update \dec31_in1_sel $0\dec31_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:80732.3-80792.6" - process $proc$issuer_ls180.v:80732$3576 - assign { } { } - assign { } { } - assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0] - attribute \src "issuer_ls180.v:80733.5-80733.29" - switch \initial - attribute \src "issuer_ls180.v:80733.9-80733.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub10_dec31_dec_sub10_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub28_dec31_dec_sub28_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub0_dec31_dec_sub0_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub26_dec31_dec_sub26_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub19_dec31_dec_sub19_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub22_dec31_dec_sub22_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub9_dec31_dec_sub9_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub11_dec31_dec_sub11_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub27_dec31_dec_sub27_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub15_dec31_dec_sub15_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub20_dec31_dec_sub20_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub21_dec31_dec_sub21_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub23_dec31_dec_sub23_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub16_dec31_dec_sub16_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub18_dec31_dec_sub18_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub8_dec31_dec_sub8_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub24_dec31_dec_sub24_in2_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub4_dec31_dec_sub4_in2_sel - case - assign $1\dec31_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_in2_sel $0\dec31_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:80793.3-80853.6" - process $proc$issuer_ls180.v:80793$3577 - assign { } { } - assign { } { } - assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0] - attribute \src "issuer_ls180.v:80794.5-80794.29" - switch \initial - attribute \src "issuer_ls180.v:80794.9-80794.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_in3_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_in3_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_in3_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_in3_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_in3_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_in3_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_in3_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_in3_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_in3_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_in3_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_in3_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_in3_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_in3_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_in3_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_in3_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_in3_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_in3_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_in3_sel - case - assign $1\dec31_in3_sel[1:0] 2'00 - end - sync always - update \dec31_in3_sel $0\dec31_in3_sel[1:0] - end - attribute \src "issuer_ls180.v:80854.3-80914.6" - process $proc$issuer_ls180.v:80854$3578 - assign { } { } - assign { } { } - assign $0\dec31_out_sel[1:0] $1\dec31_out_sel[1:0] - attribute \src "issuer_ls180.v:80855.5-80855.29" - switch \initial - attribute \src "issuer_ls180.v:80855.9-80855.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_out_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_out_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_out_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_out_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_out_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_out_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_out_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_out_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_out_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_out_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_out_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_out_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_out_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_out_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_out_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_out_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_out_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_out_sel - case - assign $1\dec31_out_sel[1:0] 2'00 - end - sync always - update \dec31_out_sel $0\dec31_out_sel[1:0] - end - attribute \src "issuer_ls180.v:80915.3-80975.6" - process $proc$issuer_ls180.v:80915$3579 - assign { } { } - assign { } { } - assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0] - attribute \src "issuer_ls180.v:80916.5-80916.29" - switch \initial - attribute \src "issuer_ls180.v:80916.9-80916.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_in - case - assign $1\dec31_cr_in[2:0] 3'000 - end - sync always - update \dec31_cr_in $0\dec31_cr_in[2:0] - end - attribute \src "issuer_ls180.v:80976.3-81036.6" - process $proc$issuer_ls180.v:80976$3580 - assign { } { } - assign { } { } - assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0] - attribute \src "issuer_ls180.v:80977.5-80977.29" - switch \initial - attribute \src "issuer_ls180.v:80977.9-80977.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_out - case - assign $1\dec31_cr_out[2:0] 3'000 - end - sync always - update \dec31_cr_out $0\dec31_cr_out[2:0] - end - attribute \src "issuer_ls180.v:81037.3-81097.6" - process $proc$issuer_ls180.v:81037$3581 - assign { } { } - assign { } { } - assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0] - attribute \src "issuer_ls180.v:81038.5-81038.29" - switch \initial - attribute \src "issuer_ls180.v:81038.9-81038.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub10_dec31_dec_sub10_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub28_dec31_dec_sub28_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub0_dec31_dec_sub0_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub26_dec31_dec_sub26_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub19_dec31_dec_sub19_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub22_dec31_dec_sub22_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub9_dec31_dec_sub9_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub11_dec31_dec_sub11_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub27_dec31_dec_sub27_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub15_dec31_dec_sub15_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub20_dec31_dec_sub20_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub21_dec31_dec_sub21_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub23_dec31_dec_sub23_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub16_dec31_dec_sub16_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub18_dec31_dec_sub18_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub8_dec31_dec_sub8_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub24_dec31_dec_sub24_ldst_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub4_dec31_dec_sub4_ldst_len - case - assign $1\dec31_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_ldst_len $0\dec31_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:81098.3-81158.6" - process $proc$issuer_ls180.v:81098$3582 - assign { } { } - assign { } { } - assign $0\dec31_upd[1:0] $1\dec31_upd[1:0] - attribute \src "issuer_ls180.v:81099.5-81099.29" - switch \initial - attribute \src "issuer_ls180.v:81099.9-81099.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub10_dec31_dec_sub10_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub28_dec31_dec_sub28_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub0_dec31_dec_sub0_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub26_dec31_dec_sub26_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub19_dec31_dec_sub19_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub22_dec31_dec_sub22_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub9_dec31_dec_sub9_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub11_dec31_dec_sub11_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub27_dec31_dec_sub27_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub15_dec31_dec_sub15_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub20_dec31_dec_sub20_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub21_dec31_dec_sub21_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub23_dec31_dec_sub23_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub16_dec31_dec_sub16_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub18_dec31_dec_sub18_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub8_dec31_dec_sub8_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub24_dec31_dec_sub24_upd - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub4_dec31_dec_sub4_upd - case - assign $1\dec31_upd[1:0] 2'00 - end - sync always - update \dec31_upd $0\dec31_upd[1:0] - end - attribute \src "issuer_ls180.v:81159.3-81219.6" - process $proc$issuer_ls180.v:81159$3583 - assign { } { } - assign { } { } - assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0] - attribute \src "issuer_ls180.v:81160.5-81160.29" - switch \initial - attribute \src "issuer_ls180.v:81160.9-81160.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_rc_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_rc_sel - case - assign $1\dec31_rc_sel[1:0] 2'00 - end - sync always - update \dec31_rc_sel $0\dec31_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:81220.3-81280.6" - process $proc$issuer_ls180.v:81220$3584 - assign { } { } - assign { } { } - assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0] - attribute \src "issuer_ls180.v:81221.5-81221.29" - switch \initial - attribute \src "issuer_ls180.v:81221.9-81221.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub10_dec31_dec_sub10_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub28_dec31_dec_sub28_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub0_dec31_dec_sub0_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub26_dec31_dec_sub26_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub19_dec31_dec_sub19_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub22_dec31_dec_sub22_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub9_dec31_dec_sub9_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub11_dec31_dec_sub11_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub27_dec31_dec_sub27_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub15_dec31_dec_sub15_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub20_dec31_dec_sub20_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub21_dec31_dec_sub21_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub23_dec31_dec_sub23_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub16_dec31_dec_sub16_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub18_dec31_dec_sub18_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub8_dec31_dec_sub8_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub24_dec31_dec_sub24_cry_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub4_dec31_dec_sub4_cry_in - case - assign $1\dec31_cry_in[1:0] 2'00 - end - sync always - update \dec31_cry_in $0\dec31_cry_in[1:0] - end - attribute \src "issuer_ls180.v:81281.3-81341.6" - process $proc$issuer_ls180.v:81281$3585 - assign { } { } - assign { } { } - assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0] - attribute \src "issuer_ls180.v:81282.5-81282.29" - switch \initial - attribute \src "issuer_ls180.v:81282.9-81282.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_a - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_a - case - assign $1\dec31_inv_a[0:0] 1'0 - end - sync always - update \dec31_inv_a $0\dec31_inv_a[0:0] - end - attribute \src "issuer_ls180.v:81342.3-81402.6" - process $proc$issuer_ls180.v:81342$3586 - assign { } { } - assign { } { } - assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0] - attribute \src "issuer_ls180.v:81343.5-81343.29" - switch \initial - attribute \src "issuer_ls180.v:81343.9-81343.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_out - case - assign $1\dec31_inv_out[0:0] 1'0 - end - sync always - update \dec31_inv_out $0\dec31_inv_out[0:0] - end - attribute \src "issuer_ls180.v:81403.3-81463.6" - process $proc$issuer_ls180.v:81403$3587 - assign { } { } - assign { } { } - assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0] - attribute \src "issuer_ls180.v:81404.5-81404.29" - switch \initial - attribute \src "issuer_ls180.v:81404.9-81404.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_cry_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_cry_out - case - assign $1\dec31_cry_out[0:0] 1'0 - end - sync always - update \dec31_cry_out $0\dec31_cry_out[0:0] - end - attribute \src "issuer_ls180.v:81464.3-81524.6" - process $proc$issuer_ls180.v:81464$3588 - assign { } { } - assign { } { } - assign $0\dec31_br[0:0] $1\dec31_br[0:0] - attribute \src "issuer_ls180.v:81465.5-81465.29" - switch \initial - attribute \src "issuer_ls180.v:81465.9-81465.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub10_dec31_dec_sub10_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub28_dec31_dec_sub28_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub0_dec31_dec_sub0_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub26_dec31_dec_sub26_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub19_dec31_dec_sub19_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub22_dec31_dec_sub22_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub9_dec31_dec_sub9_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub11_dec31_dec_sub11_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub27_dec31_dec_sub27_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub15_dec31_dec_sub15_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub20_dec31_dec_sub20_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub21_dec31_dec_sub21_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub23_dec31_dec_sub23_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub16_dec31_dec_sub16_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub18_dec31_dec_sub18_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub8_dec31_dec_sub8_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub24_dec31_dec_sub24_br - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub4_dec31_dec_sub4_br - case - assign $1\dec31_br[0:0] 1'0 - end - sync always - update \dec31_br $0\dec31_br[0:0] - end - attribute \src "issuer_ls180.v:81525.3-81585.6" - process $proc$issuer_ls180.v:81525$3589 - assign { } { } - assign { } { } - assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0] - attribute \src "issuer_ls180.v:81526.5-81526.29" - switch \initial - attribute \src "issuer_ls180.v:81526.9-81526.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn_ext - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn_ext - case - assign $1\dec31_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_sgn_ext $0\dec31_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:81586.3-81646.6" - process $proc$issuer_ls180.v:81586$3590 - assign { } { } - assign { } { } - assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0] - attribute \src "issuer_ls180.v:81587.5-81587.29" - switch \initial - attribute \src "issuer_ls180.v:81587.9-81587.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub10_dec31_dec_sub10_rsrv - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub28_dec31_dec_sub28_rsrv - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub0_dec31_dec_sub0_rsrv - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub26_dec31_dec_sub26_rsrv - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub19_dec31_dec_sub19_rsrv - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub22_dec31_dec_sub22_rsrv - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub9_dec31_dec_sub9_rsrv - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub11_dec31_dec_sub11_rsrv - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub27_dec31_dec_sub27_rsrv - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub15_dec31_dec_sub15_rsrv - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub20_dec31_dec_sub20_rsrv - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub21_dec31_dec_sub21_rsrv - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub23_dec31_dec_sub23_rsrv - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub16_dec31_dec_sub16_rsrv - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub18_dec31_dec_sub18_rsrv - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub8_dec31_dec_sub8_rsrv - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub24_dec31_dec_sub24_rsrv - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub4_dec31_dec_sub4_rsrv - case - assign $1\dec31_rsrv[0:0] 1'0 - end - sync always - update \dec31_rsrv $0\dec31_rsrv[0:0] - end - attribute \src "issuer_ls180.v:81647.3-81707.6" - process $proc$issuer_ls180.v:81647$3591 - assign { } { } - assign { } { } - assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0] - attribute \src "issuer_ls180.v:81648.5-81648.29" - switch \initial - attribute \src "issuer_ls180.v:81648.9-81648.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub10_dec31_dec_sub10_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub28_dec31_dec_sub28_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub0_dec31_dec_sub0_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub26_dec31_dec_sub26_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub19_dec31_dec_sub19_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub22_dec31_dec_sub22_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub9_dec31_dec_sub9_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub11_dec31_dec_sub11_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub27_dec31_dec_sub27_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub15_dec31_dec_sub15_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub20_dec31_dec_sub20_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub21_dec31_dec_sub21_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub23_dec31_dec_sub23_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub16_dec31_dec_sub16_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub18_dec31_dec_sub18_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub8_dec31_dec_sub8_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub24_dec31_dec_sub24_is_32b - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub4_dec31_dec_sub4_is_32b - case - assign $1\dec31_is_32b[0:0] 1'0 - end - sync always - update \dec31_is_32b $0\dec31_is_32b[0:0] - end - attribute \src "issuer_ls180.v:81708.3-81768.6" - process $proc$issuer_ls180.v:81708$3592 - assign { } { } - assign { } { } - assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0] - attribute \src "issuer_ls180.v:81709.5-81709.29" - switch \initial - attribute \src "issuer_ls180.v:81709.9-81709.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn - case - assign $1\dec31_sgn[0:0] 1'0 - end - sync always - update \dec31_sgn $0\dec31_sgn[0:0] - end - attribute \src "issuer_ls180.v:81769.3-81829.6" - process $proc$issuer_ls180.v:81769$3593 - assign { } { } - assign { } { } - assign $0\dec31_lk[0:0] $1\dec31_lk[0:0] - attribute \src "issuer_ls180.v:81770.5-81770.29" - switch \initial - attribute \src "issuer_ls180.v:81770.9-81770.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub10_dec31_dec_sub10_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub28_dec31_dec_sub28_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub0_dec31_dec_sub0_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub26_dec31_dec_sub26_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub19_dec31_dec_sub19_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub22_dec31_dec_sub22_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub9_dec31_dec_sub9_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub11_dec31_dec_sub11_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub27_dec31_dec_sub27_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub15_dec31_dec_sub15_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub20_dec31_dec_sub20_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub21_dec31_dec_sub21_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub23_dec31_dec_sub23_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub16_dec31_dec_sub16_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub18_dec31_dec_sub18_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub8_dec31_dec_sub8_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub24_dec31_dec_sub24_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub4_dec31_dec_sub4_lk - case - assign $1\dec31_lk[0:0] 1'0 - end - sync always - update \dec31_lk $0\dec31_lk[0:0] - end - attribute \src "issuer_ls180.v:81830.3-81890.6" - process $proc$issuer_ls180.v:81830$3594 - assign { } { } - assign { } { } - assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:81831.5-81831.29" - switch \initial - attribute \src "issuer_ls180.v:81831.9-81831.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe - case - assign $1\dec31_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_sgl_pipe $0\dec31_sgl_pipe[0:0] - end - connect \dec31_dec_sub4_opcode_in \opcode_in - connect \dec31_dec_sub24_opcode_in \opcode_in - connect \dec31_dec_sub8_opcode_in \opcode_in - connect \dec31_dec_sub18_opcode_in \opcode_in - connect \dec31_dec_sub16_opcode_in \opcode_in - connect \dec31_dec_sub23_opcode_in \opcode_in - connect \dec31_dec_sub21_opcode_in \opcode_in - connect \dec31_dec_sub20_opcode_in \opcode_in - connect \dec31_dec_sub15_opcode_in \opcode_in - connect \dec31_dec_sub27_opcode_in \opcode_in - connect \dec31_dec_sub11_opcode_in \opcode_in - connect \dec31_dec_sub9_opcode_in \opcode_in - connect \dec31_dec_sub22_opcode_in \opcode_in - connect \dec31_dec_sub19_opcode_in \opcode_in - connect \dec31_dec_sub26_opcode_in \opcode_in - connect \dec31_dec_sub0_opcode_in \opcode_in - connect \dec31_dec_sub28_opcode_in \opcode_in - connect \dec31_dec_sub10_opcode_in \opcode_in - connect \opc_in \opcode_switch [4:0] - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "issuer_ls180.v:81915.1-82630.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub0" -attribute \generator "nMigen" -module \dec31_dec_sub0 - attribute \src "issuer_ls180.v:82268.3-82286.6" - wire width 8 $0\dec31_dec_sub0_asmcode[7:0] - attribute \src "issuer_ls180.v:82344.3-82362.6" - wire $0\dec31_dec_sub0_br[0:0] - attribute \src "issuer_ls180.v:82591.3-82609.6" - wire width 3 $0\dec31_dec_sub0_cr_in[2:0] - attribute \src "issuer_ls180.v:82610.3-82628.6" - wire width 3 $0\dec31_dec_sub0_cr_out[2:0] - attribute \src "issuer_ls180.v:82249.3-82267.6" - wire width 2 $0\dec31_dec_sub0_cry_in[1:0] - attribute \src "issuer_ls180.v:82325.3-82343.6" - wire $0\dec31_dec_sub0_cry_out[0:0] - attribute \src "issuer_ls180.v:82496.3-82514.6" - wire width 5 $0\dec31_dec_sub0_form[4:0] - attribute \src "issuer_ls180.v:82173.3-82191.6" - wire width 12 $0\dec31_dec_sub0_function_unit[11:0] - attribute \src "issuer_ls180.v:82515.3-82533.6" - wire width 3 $0\dec31_dec_sub0_in1_sel[2:0] - attribute \src "issuer_ls180.v:82534.3-82552.6" - wire width 4 $0\dec31_dec_sub0_in2_sel[3:0] - attribute \src "issuer_ls180.v:82553.3-82571.6" - wire width 2 $0\dec31_dec_sub0_in3_sel[1:0] - attribute \src "issuer_ls180.v:82382.3-82400.6" - wire width 7 $0\dec31_dec_sub0_internal_op[6:0] - attribute \src "issuer_ls180.v:82287.3-82305.6" - wire $0\dec31_dec_sub0_inv_a[0:0] - attribute \src "issuer_ls180.v:82306.3-82324.6" - wire $0\dec31_dec_sub0_inv_out[0:0] - attribute \src "issuer_ls180.v:82420.3-82438.6" - wire $0\dec31_dec_sub0_is_32b[0:0] - attribute \src "issuer_ls180.v:82192.3-82210.6" - wire width 4 $0\dec31_dec_sub0_ldst_len[3:0] - attribute \src "issuer_ls180.v:82458.3-82476.6" - wire $0\dec31_dec_sub0_lk[0:0] - attribute \src "issuer_ls180.v:82572.3-82590.6" - wire width 2 $0\dec31_dec_sub0_out_sel[1:0] - attribute \src "issuer_ls180.v:82230.3-82248.6" - wire width 2 $0\dec31_dec_sub0_rc_sel[1:0] - attribute \src "issuer_ls180.v:82401.3-82419.6" - wire $0\dec31_dec_sub0_rsrv[0:0] - attribute \src "issuer_ls180.v:82477.3-82495.6" - wire $0\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:82439.3-82457.6" - wire $0\dec31_dec_sub0_sgn[0:0] - attribute \src "issuer_ls180.v:82363.3-82381.6" - wire $0\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "issuer_ls180.v:82211.3-82229.6" - wire width 2 $0\dec31_dec_sub0_upd[1:0] - attribute \src "issuer_ls180.v:81916.7-81916.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:82268.3-82286.6" - wire width 8 $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "issuer_ls180.v:82344.3-82362.6" - wire $1\dec31_dec_sub0_br[0:0] - attribute \src "issuer_ls180.v:82591.3-82609.6" - wire width 3 $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "issuer_ls180.v:82610.3-82628.6" - wire width 3 $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "issuer_ls180.v:82249.3-82267.6" - wire width 2 $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "issuer_ls180.v:82325.3-82343.6" - wire $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "issuer_ls180.v:82496.3-82514.6" - wire width 5 $1\dec31_dec_sub0_form[4:0] - attribute \src "issuer_ls180.v:82173.3-82191.6" - wire width 12 $1\dec31_dec_sub0_function_unit[11:0] - attribute \src "issuer_ls180.v:82515.3-82533.6" - wire width 3 $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "issuer_ls180.v:82534.3-82552.6" - wire width 4 $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "issuer_ls180.v:82553.3-82571.6" - wire width 2 $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "issuer_ls180.v:82382.3-82400.6" - wire width 7 $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "issuer_ls180.v:82287.3-82305.6" - wire $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "issuer_ls180.v:82306.3-82324.6" - wire $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "issuer_ls180.v:82420.3-82438.6" - wire $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "issuer_ls180.v:82192.3-82210.6" - wire width 4 $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "issuer_ls180.v:82458.3-82476.6" - wire $1\dec31_dec_sub0_lk[0:0] - attribute \src "issuer_ls180.v:82572.3-82590.6" - wire width 2 $1\dec31_dec_sub0_out_sel[1:0] - attribute \src "issuer_ls180.v:82230.3-82248.6" - wire width 2 $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "issuer_ls180.v:82401.3-82419.6" - wire $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "issuer_ls180.v:82477.3-82495.6" - wire $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:82439.3-82457.6" - wire $1\dec31_dec_sub0_sgn[0:0] - attribute \src "issuer_ls180.v:82363.3-82381.6" - wire $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "issuer_ls180.v:82211.3-82229.6" - wire width 2 $1\dec31_dec_sub0_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub0_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub0_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub0_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub0_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub0_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub0_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub0_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub0_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub0_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub0_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub0_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub0_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub0_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub0_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub0_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub0_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub0_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub0_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub0_upd - attribute \src "issuer_ls180.v:81916.7-81916.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:81916.7-81916.20" - process $proc$issuer_ls180.v:81916$3620 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:82173.3-82191.6" - process $proc$issuer_ls180.v:82173$3596 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_function_unit[11:0] $1\dec31_dec_sub0_function_unit[11:0] - attribute \src "issuer_ls180.v:82174.5-82174.29" - switch \initial - attribute \src "issuer_ls180.v:82174.9-82174.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_function_unit[11:0] 12'000001000000 - case - assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[11:0] - end - attribute \src "issuer_ls180.v:82192.3-82210.6" - process $proc$issuer_ls180.v:82192$3597 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "issuer_ls180.v:82193.5-82193.29" - switch \initial - attribute \src "issuer_ls180.v:82193.9-82193.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:82211.3-82229.6" - process $proc$issuer_ls180.v:82211$3598 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0] - attribute \src "issuer_ls180.v:82212.5-82212.29" - switch \initial - attribute \src "issuer_ls180.v:82212.9-82212.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub0_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0] - end - attribute \src "issuer_ls180.v:82230.3-82248.6" - process $proc$issuer_ls180.v:82230$3599 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "issuer_ls180.v:82231.5-82231.29" - switch \initial - attribute \src "issuer_ls180.v:82231.9-82231.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:82249.3-82267.6" - process $proc$issuer_ls180.v:82249$3600 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "issuer_ls180.v:82250.5-82250.29" - switch \initial - attribute \src "issuer_ls180.v:82250.9-82250.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0] - end - attribute \src "issuer_ls180.v:82268.3-82286.6" - process $proc$issuer_ls180.v:82268$3601 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "issuer_ls180.v:82269.5-82269.29" - switch \initial - attribute \src "issuer_ls180.v:82269.9-82269.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_asmcode[7:0] 8'10011011 - case - assign $1\dec31_dec_sub0_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0] - end - attribute \src "issuer_ls180.v:82287.3-82305.6" - process $proc$issuer_ls180.v:82287$3602 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "issuer_ls180.v:82288.5-82288.29" - switch \initial - attribute \src "issuer_ls180.v:82288.9-82288.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0] - end - attribute \src "issuer_ls180.v:82306.3-82324.6" - process $proc$issuer_ls180.v:82306$3603 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "issuer_ls180.v:82307.5-82307.29" - switch \initial - attribute \src "issuer_ls180.v:82307.9-82307.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0] - end - attribute \src "issuer_ls180.v:82325.3-82343.6" - process $proc$issuer_ls180.v:82325$3604 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "issuer_ls180.v:82326.5-82326.29" - switch \initial - attribute \src "issuer_ls180.v:82326.9-82326.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0] - end - attribute \src "issuer_ls180.v:82344.3-82362.6" - process $proc$issuer_ls180.v:82344$3605 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0] - attribute \src "issuer_ls180.v:82345.5-82345.29" - switch \initial - attribute \src "issuer_ls180.v:82345.9-82345.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_br[0:0] 1'0 - case - assign $1\dec31_dec_sub0_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0] - end - attribute \src "issuer_ls180.v:82363.3-82381.6" - process $proc$issuer_ls180.v:82363$3606 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "issuer_ls180.v:82364.5-82364.29" - switch \initial - attribute \src "issuer_ls180.v:82364.9-82364.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:82382.3-82400.6" - process $proc$issuer_ls180.v:82382$3607 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "issuer_ls180.v:82383.5-82383.29" - switch \initial - attribute \src "issuer_ls180.v:82383.9-82383.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0111011 - case - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] - end - attribute \src "issuer_ls180.v:82401.3-82419.6" - process $proc$issuer_ls180.v:82401$3608 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "issuer_ls180.v:82402.5-82402.29" - switch \initial - attribute \src "issuer_ls180.v:82402.9-82402.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0] - end - attribute \src "issuer_ls180.v:82420.3-82438.6" - process $proc$issuer_ls180.v:82420$3609 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "issuer_ls180.v:82421.5-82421.29" - switch \initial - attribute \src "issuer_ls180.v:82421.9-82421.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] - end - attribute \src "issuer_ls180.v:82439.3-82457.6" - process $proc$issuer_ls180.v:82439$3610 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0] - attribute \src "issuer_ls180.v:82440.5-82440.29" - switch \initial - attribute \src "issuer_ls180.v:82440.9-82440.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub0_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0] - end - attribute \src "issuer_ls180.v:82458.3-82476.6" - process $proc$issuer_ls180.v:82458$3611 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0] - attribute \src "issuer_ls180.v:82459.5-82459.29" - switch \initial - attribute \src "issuer_ls180.v:82459.9-82459.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub0_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0] - end - attribute \src "issuer_ls180.v:82477.3-82495.6" - process $proc$issuer_ls180.v:82477$3612 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:82478.5-82478.29" - switch \initial - attribute \src "issuer_ls180.v:82478.9-82478.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0] - end - attribute \src "issuer_ls180.v:82496.3-82514.6" - process $proc$issuer_ls180.v:82496$3613 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] - attribute \src "issuer_ls180.v:82497.5-82497.29" - switch \initial - attribute \src "issuer_ls180.v:82497.9-82497.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'11000 - case - assign $1\dec31_dec_sub0_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] - end - attribute \src "issuer_ls180.v:82515.3-82533.6" - process $proc$issuer_ls180.v:82515$3614 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "issuer_ls180.v:82516.5-82516.29" - switch \initial - attribute \src "issuer_ls180.v:82516.9-82516.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 - case - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:82534.3-82552.6" - process $proc$issuer_ls180.v:82534$3615 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "issuer_ls180.v:82535.5-82535.29" - switch \initial - attribute \src "issuer_ls180.v:82535.9-82535.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 - case - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:82553.3-82571.6" - process $proc$issuer_ls180.v:82553$3616 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "issuer_ls180.v:82554.5-82554.29" - switch \initial - attribute \src "issuer_ls180.v:82554.9-82554.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0] - end - attribute \src "issuer_ls180.v:82572.3-82590.6" - process $proc$issuer_ls180.v:82572$3617 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_out_sel[1:0] $1\dec31_dec_sub0_out_sel[1:0] - attribute \src "issuer_ls180.v:82573.5-82573.29" - switch \initial - attribute \src "issuer_ls180.v:82573.9-82573.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_out_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub0_out_sel $0\dec31_dec_sub0_out_sel[1:0] - end - attribute \src "issuer_ls180.v:82591.3-82609.6" - process $proc$issuer_ls180.v:82591$3618 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "issuer_ls180.v:82592.5-82592.29" - switch \initial - attribute \src "issuer_ls180.v:82592.9-82592.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_cr_in[2:0] 3'011 - case - assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0] - end - attribute \src "issuer_ls180.v:82610.3-82628.6" - process $proc$issuer_ls180.v:82610$3619 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "issuer_ls180.v:82611.5-82611.29" - switch \initial - attribute \src "issuer_ls180.v:82611.9-82611.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:82634.1-83781.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub10" -attribute \generator "nMigen" -module \dec31_dec_sub10 - attribute \src "issuer_ls180.v:83077.3-83113.6" - wire width 8 $0\dec31_dec_sub10_asmcode[7:0] - attribute \src "issuer_ls180.v:83225.3-83261.6" - wire $0\dec31_dec_sub10_br[0:0] - attribute \src "issuer_ls180.v:83706.3-83742.6" - wire width 3 $0\dec31_dec_sub10_cr_in[2:0] - attribute \src "issuer_ls180.v:83743.3-83779.6" - wire width 3 $0\dec31_dec_sub10_cr_out[2:0] - attribute \src "issuer_ls180.v:83040.3-83076.6" - wire width 2 $0\dec31_dec_sub10_cry_in[1:0] - attribute \src "issuer_ls180.v:83188.3-83224.6" - wire $0\dec31_dec_sub10_cry_out[0:0] - attribute \src "issuer_ls180.v:83521.3-83557.6" - wire width 5 $0\dec31_dec_sub10_form[4:0] - attribute \src "issuer_ls180.v:82892.3-82928.6" - wire width 12 $0\dec31_dec_sub10_function_unit[11:0] - attribute \src "issuer_ls180.v:83558.3-83594.6" - wire width 3 $0\dec31_dec_sub10_in1_sel[2:0] - attribute \src "issuer_ls180.v:83595.3-83631.6" - wire width 4 $0\dec31_dec_sub10_in2_sel[3:0] - attribute \src "issuer_ls180.v:83632.3-83668.6" - wire width 2 $0\dec31_dec_sub10_in3_sel[1:0] - attribute \src "issuer_ls180.v:83299.3-83335.6" - wire width 7 $0\dec31_dec_sub10_internal_op[6:0] - attribute \src "issuer_ls180.v:83114.3-83150.6" - wire $0\dec31_dec_sub10_inv_a[0:0] - attribute \src "issuer_ls180.v:83151.3-83187.6" - wire $0\dec31_dec_sub10_inv_out[0:0] - attribute \src "issuer_ls180.v:83373.3-83409.6" - wire $0\dec31_dec_sub10_is_32b[0:0] - attribute \src "issuer_ls180.v:82929.3-82965.6" - wire width 4 $0\dec31_dec_sub10_ldst_len[3:0] - attribute \src "issuer_ls180.v:83447.3-83483.6" - wire $0\dec31_dec_sub10_lk[0:0] - attribute \src "issuer_ls180.v:83669.3-83705.6" - wire width 2 $0\dec31_dec_sub10_out_sel[1:0] - attribute \src "issuer_ls180.v:83003.3-83039.6" - wire width 2 $0\dec31_dec_sub10_rc_sel[1:0] - attribute \src "issuer_ls180.v:83336.3-83372.6" - wire $0\dec31_dec_sub10_rsrv[0:0] - attribute \src "issuer_ls180.v:83484.3-83520.6" - wire $0\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:83410.3-83446.6" - wire $0\dec31_dec_sub10_sgn[0:0] - attribute \src "issuer_ls180.v:83262.3-83298.6" - wire $0\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "issuer_ls180.v:82966.3-83002.6" - wire width 2 $0\dec31_dec_sub10_upd[1:0] - attribute \src "issuer_ls180.v:82635.7-82635.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:83077.3-83113.6" - wire width 8 $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "issuer_ls180.v:83225.3-83261.6" - wire $1\dec31_dec_sub10_br[0:0] - attribute \src "issuer_ls180.v:83706.3-83742.6" - wire width 3 $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "issuer_ls180.v:83743.3-83779.6" - wire width 3 $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "issuer_ls180.v:83040.3-83076.6" - wire width 2 $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "issuer_ls180.v:83188.3-83224.6" - wire $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "issuer_ls180.v:83521.3-83557.6" - wire width 5 $1\dec31_dec_sub10_form[4:0] - attribute \src "issuer_ls180.v:82892.3-82928.6" - wire width 12 $1\dec31_dec_sub10_function_unit[11:0] - attribute \src "issuer_ls180.v:83558.3-83594.6" - wire width 3 $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "issuer_ls180.v:83595.3-83631.6" - wire width 4 $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "issuer_ls180.v:83632.3-83668.6" - wire width 2 $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "issuer_ls180.v:83299.3-83335.6" - wire width 7 $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "issuer_ls180.v:83114.3-83150.6" - wire $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "issuer_ls180.v:83151.3-83187.6" - wire $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "issuer_ls180.v:83373.3-83409.6" - wire $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "issuer_ls180.v:82929.3-82965.6" - wire width 4 $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "issuer_ls180.v:83447.3-83483.6" - wire $1\dec31_dec_sub10_lk[0:0] - attribute \src "issuer_ls180.v:83669.3-83705.6" - wire width 2 $1\dec31_dec_sub10_out_sel[1:0] - attribute \src "issuer_ls180.v:83003.3-83039.6" - wire width 2 $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "issuer_ls180.v:83336.3-83372.6" - wire $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "issuer_ls180.v:83484.3-83520.6" - wire $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:83410.3-83446.6" - wire $1\dec31_dec_sub10_sgn[0:0] - attribute \src "issuer_ls180.v:83262.3-83298.6" - wire $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "issuer_ls180.v:82966.3-83002.6" - wire width 2 $1\dec31_dec_sub10_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub10_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub10_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub10_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub10_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub10_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub10_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub10_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub10_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub10_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub10_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub10_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub10_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub10_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub10_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub10_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub10_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub10_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub10_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub10_upd - attribute \src "issuer_ls180.v:82635.7-82635.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:82635.7-82635.20" - process $proc$issuer_ls180.v:82635$3645 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:82892.3-82928.6" - process $proc$issuer_ls180.v:82892$3621 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_function_unit[11:0] $1\dec31_dec_sub10_function_unit[11:0] - attribute \src "issuer_ls180.v:82893.5-82893.29" - switch \initial - attribute \src "issuer_ls180.v:82893.9-82893.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - case - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[11:0] - end - attribute \src "issuer_ls180.v:82929.3-82965.6" - process $proc$issuer_ls180.v:82929$3622 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "issuer_ls180.v:82930.5-82930.29" - switch \initial - attribute \src "issuer_ls180.v:82930.9-82930.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:82966.3-83002.6" - process $proc$issuer_ls180.v:82966$3623 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] - attribute \src "issuer_ls180.v:82967.5-82967.29" - switch \initial - attribute \src "issuer_ls180.v:82967.9-82967.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] - end - attribute \src "issuer_ls180.v:83003.3-83039.6" - process $proc$issuer_ls180.v:83003$3624 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "issuer_ls180.v:83004.5-83004.29" - switch \initial - attribute \src "issuer_ls180.v:83004.9-83004.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:83040.3-83076.6" - process $proc$issuer_ls180.v:83040$3625 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "issuer_ls180.v:83041.5-83041.29" - switch \initial - attribute \src "issuer_ls180.v:83041.9-83041.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 - case - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0] - end - attribute \src "issuer_ls180.v:83077.3-83113.6" - process $proc$issuer_ls180.v:83077$3626 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "issuer_ls180.v:83078.5-83078.29" - switch \initial - attribute \src "issuer_ls180.v:83078.9-83078.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001110 - case - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0] - end - attribute \src "issuer_ls180.v:83114.3-83150.6" - process $proc$issuer_ls180.v:83114$3627 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "issuer_ls180.v:83115.5-83115.29" - switch \initial - attribute \src "issuer_ls180.v:83115.9-83115.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0] - end - attribute \src "issuer_ls180.v:83151.3-83187.6" - process $proc$issuer_ls180.v:83151$3628 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "issuer_ls180.v:83152.5-83152.29" - switch \initial - attribute \src "issuer_ls180.v:83152.9-83152.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0] - end - attribute \src "issuer_ls180.v:83188.3-83224.6" - process $proc$issuer_ls180.v:83188$3629 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "issuer_ls180.v:83189.5-83189.29" - switch \initial - attribute \src "issuer_ls180.v:83189.9-83189.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - case - assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0] - end - attribute \src "issuer_ls180.v:83225.3-83261.6" - process $proc$issuer_ls180.v:83225$3630 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0] - attribute \src "issuer_ls180.v:83226.5-83226.29" - switch \initial - attribute \src "issuer_ls180.v:83226.9-83226.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - case - assign $1\dec31_dec_sub10_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0] - end - attribute \src "issuer_ls180.v:83262.3-83298.6" - process $proc$issuer_ls180.v:83262$3631 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "issuer_ls180.v:83263.5-83263.29" - switch \initial - attribute \src "issuer_ls180.v:83263.9-83263.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:83299.3-83335.6" - process $proc$issuer_ls180.v:83299$3632 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "issuer_ls180.v:83300.5-83300.29" - switch \initial - attribute \src "issuer_ls180.v:83300.9-83300.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - case - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] - end - attribute \src "issuer_ls180.v:83336.3-83372.6" - process $proc$issuer_ls180.v:83336$3633 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "issuer_ls180.v:83337.5-83337.29" - switch \initial - attribute \src "issuer_ls180.v:83337.9-83337.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0] - end - attribute \src "issuer_ls180.v:83373.3-83409.6" - process $proc$issuer_ls180.v:83373$3634 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "issuer_ls180.v:83374.5-83374.29" - switch \initial - attribute \src "issuer_ls180.v:83374.9-83374.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] - end - attribute \src "issuer_ls180.v:83410.3-83446.6" - process $proc$issuer_ls180.v:83410$3635 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0] - attribute \src "issuer_ls180.v:83411.5-83411.29" - switch \initial - attribute \src "issuer_ls180.v:83411.9-83411.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0] - end - attribute \src "issuer_ls180.v:83447.3-83483.6" - process $proc$issuer_ls180.v:83447$3636 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0] - attribute \src "issuer_ls180.v:83448.5-83448.29" - switch \initial - attribute \src "issuer_ls180.v:83448.9-83448.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0] - end - attribute \src "issuer_ls180.v:83484.3-83520.6" - process $proc$issuer_ls180.v:83484$3637 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:83485.5-83485.29" - switch \initial - attribute \src "issuer_ls180.v:83485.9-83485.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0] - end - attribute \src "issuer_ls180.v:83521.3-83557.6" - process $proc$issuer_ls180.v:83521$3638 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] - attribute \src "issuer_ls180.v:83522.5-83522.29" - switch \initial - attribute \src "issuer_ls180.v:83522.9-83522.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - case - assign $1\dec31_dec_sub10_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] - end - attribute \src "issuer_ls180.v:83558.3-83594.6" - process $proc$issuer_ls180.v:83558$3639 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "issuer_ls180.v:83559.5-83559.29" - switch \initial - attribute \src "issuer_ls180.v:83559.9-83559.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - case - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:83595.3-83631.6" - process $proc$issuer_ls180.v:83595$3640 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "issuer_ls180.v:83596.5-83596.29" - switch \initial - attribute \src "issuer_ls180.v:83596.9-83596.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 - case - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:83632.3-83668.6" - process $proc$issuer_ls180.v:83632$3641 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "issuer_ls180.v:83633.5-83633.29" - switch \initial - attribute \src "issuer_ls180.v:83633.9-83633.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0] - end - attribute \src "issuer_ls180.v:83669.3-83705.6" - process $proc$issuer_ls180.v:83669$3642 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_out_sel[1:0] $1\dec31_dec_sub10_out_sel[1:0] - attribute \src "issuer_ls180.v:83670.5-83670.29" - switch \initial - attribute \src "issuer_ls180.v:83670.9-83670.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub10_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub10_out_sel $0\dec31_dec_sub10_out_sel[1:0] - end - attribute \src "issuer_ls180.v:83706.3-83742.6" - process $proc$issuer_ls180.v:83706$3643 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "issuer_ls180.v:83707.5-83707.29" - switch \initial - attribute \src "issuer_ls180.v:83707.9-83707.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0] - end - attribute \src "issuer_ls180.v:83743.3-83779.6" - process $proc$issuer_ls180.v:83743$3644 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "issuer_ls180.v:83744.5-83744.29" - switch \initial - attribute \src "issuer_ls180.v:83744.9-83744.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub10_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:83785.1-85364.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub11" -attribute \generator "nMigen" -module \dec31_dec_sub11 - attribute \src "issuer_ls180.v:84318.3-84372.6" - wire width 8 $0\dec31_dec_sub11_asmcode[7:0] - attribute \src "issuer_ls180.v:84538.3-84592.6" - wire $0\dec31_dec_sub11_br[0:0] - attribute \src "issuer_ls180.v:85253.3-85307.6" - wire width 3 $0\dec31_dec_sub11_cr_in[2:0] - attribute \src "issuer_ls180.v:85308.3-85362.6" - wire width 3 $0\dec31_dec_sub11_cr_out[2:0] - attribute \src "issuer_ls180.v:84263.3-84317.6" - wire width 2 $0\dec31_dec_sub11_cry_in[1:0] - attribute \src "issuer_ls180.v:84483.3-84537.6" - wire $0\dec31_dec_sub11_cry_out[0:0] - attribute \src "issuer_ls180.v:84978.3-85032.6" - wire width 5 $0\dec31_dec_sub11_form[4:0] - attribute \src "issuer_ls180.v:84043.3-84097.6" - wire width 12 $0\dec31_dec_sub11_function_unit[11:0] - attribute \src "issuer_ls180.v:85033.3-85087.6" - wire width 3 $0\dec31_dec_sub11_in1_sel[2:0] - attribute \src "issuer_ls180.v:85088.3-85142.6" - wire width 4 $0\dec31_dec_sub11_in2_sel[3:0] - attribute \src "issuer_ls180.v:85143.3-85197.6" - wire width 2 $0\dec31_dec_sub11_in3_sel[1:0] - attribute \src "issuer_ls180.v:84648.3-84702.6" - wire width 7 $0\dec31_dec_sub11_internal_op[6:0] - attribute \src "issuer_ls180.v:84373.3-84427.6" - wire $0\dec31_dec_sub11_inv_a[0:0] - attribute \src "issuer_ls180.v:84428.3-84482.6" - wire $0\dec31_dec_sub11_inv_out[0:0] - attribute \src "issuer_ls180.v:84758.3-84812.6" - wire $0\dec31_dec_sub11_is_32b[0:0] - attribute \src "issuer_ls180.v:84098.3-84152.6" - wire width 4 $0\dec31_dec_sub11_ldst_len[3:0] - attribute \src "issuer_ls180.v:84868.3-84922.6" - wire $0\dec31_dec_sub11_lk[0:0] - attribute \src "issuer_ls180.v:85198.3-85252.6" - wire width 2 $0\dec31_dec_sub11_out_sel[1:0] - attribute \src "issuer_ls180.v:84208.3-84262.6" - wire width 2 $0\dec31_dec_sub11_rc_sel[1:0] - attribute \src "issuer_ls180.v:84703.3-84757.6" - wire $0\dec31_dec_sub11_rsrv[0:0] - attribute \src "issuer_ls180.v:84923.3-84977.6" - wire $0\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:84813.3-84867.6" - wire $0\dec31_dec_sub11_sgn[0:0] - attribute \src "issuer_ls180.v:84593.3-84647.6" - wire $0\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "issuer_ls180.v:84153.3-84207.6" - wire width 2 $0\dec31_dec_sub11_upd[1:0] - attribute \src "issuer_ls180.v:83786.7-83786.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:84318.3-84372.6" - wire width 8 $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "issuer_ls180.v:84538.3-84592.6" - wire $1\dec31_dec_sub11_br[0:0] - attribute \src "issuer_ls180.v:85253.3-85307.6" - wire width 3 $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "issuer_ls180.v:85308.3-85362.6" - wire width 3 $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "issuer_ls180.v:84263.3-84317.6" - wire width 2 $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "issuer_ls180.v:84483.3-84537.6" - wire $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "issuer_ls180.v:84978.3-85032.6" - wire width 5 $1\dec31_dec_sub11_form[4:0] - attribute \src "issuer_ls180.v:84043.3-84097.6" - wire width 12 $1\dec31_dec_sub11_function_unit[11:0] - attribute \src "issuer_ls180.v:85033.3-85087.6" - wire width 3 $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "issuer_ls180.v:85088.3-85142.6" - wire width 4 $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "issuer_ls180.v:85143.3-85197.6" - wire width 2 $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "issuer_ls180.v:84648.3-84702.6" - wire width 7 $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "issuer_ls180.v:84373.3-84427.6" - wire $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "issuer_ls180.v:84428.3-84482.6" - wire $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "issuer_ls180.v:84758.3-84812.6" - wire $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "issuer_ls180.v:84098.3-84152.6" - wire width 4 $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "issuer_ls180.v:84868.3-84922.6" - wire $1\dec31_dec_sub11_lk[0:0] - attribute \src "issuer_ls180.v:85198.3-85252.6" - wire width 2 $1\dec31_dec_sub11_out_sel[1:0] - attribute \src "issuer_ls180.v:84208.3-84262.6" - wire width 2 $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "issuer_ls180.v:84703.3-84757.6" - wire $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "issuer_ls180.v:84923.3-84977.6" - wire $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:84813.3-84867.6" - wire $1\dec31_dec_sub11_sgn[0:0] - attribute \src "issuer_ls180.v:84593.3-84647.6" - wire $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "issuer_ls180.v:84153.3-84207.6" - wire width 2 $1\dec31_dec_sub11_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub11_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub11_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub11_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub11_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub11_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub11_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub11_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub11_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub11_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub11_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub11_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub11_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub11_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub11_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub11_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub11_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub11_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub11_upd - attribute \src "issuer_ls180.v:83786.7-83786.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:83786.7-83786.20" - process $proc$issuer_ls180.v:83786$3670 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:84043.3-84097.6" - process $proc$issuer_ls180.v:84043$3646 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_function_unit[11:0] $1\dec31_dec_sub11_function_unit[11:0] - attribute \src "issuer_ls180.v:84044.5-84044.29" - switch \initial - attribute \src "issuer_ls180.v:84044.9-84044.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 - case - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[11:0] - end - attribute \src "issuer_ls180.v:84098.3-84152.6" - process $proc$issuer_ls180.v:84098$3647 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "issuer_ls180.v:84099.5-84099.29" - switch \initial - attribute \src "issuer_ls180.v:84099.9-84099.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:84153.3-84207.6" - process $proc$issuer_ls180.v:84153$3648 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] - attribute \src "issuer_ls180.v:84154.5-84154.29" - switch \initial - attribute \src "issuer_ls180.v:84154.9-84154.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] - end - attribute \src "issuer_ls180.v:84208.3-84262.6" - process $proc$issuer_ls180.v:84208$3649 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "issuer_ls180.v:84209.5-84209.29" - switch \initial - attribute \src "issuer_ls180.v:84209.9-84209.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:84263.3-84317.6" - process $proc$issuer_ls180.v:84263$3650 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "issuer_ls180.v:84264.5-84264.29" - switch \initial - attribute \src "issuer_ls180.v:84264.9-84264.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0] - end - attribute \src "issuer_ls180.v:84318.3-84372.6" - process $proc$issuer_ls180.v:84318$3651 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "issuer_ls180.v:84319.5-84319.29" - switch \initial - attribute \src "issuer_ls180.v:84319.9-84319.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000010 - case - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0] - end - attribute \src "issuer_ls180.v:84373.3-84427.6" - process $proc$issuer_ls180.v:84373$3652 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "issuer_ls180.v:84374.5-84374.29" - switch \initial - attribute \src "issuer_ls180.v:84374.9-84374.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0] - end - attribute \src "issuer_ls180.v:84428.3-84482.6" - process $proc$issuer_ls180.v:84428$3653 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "issuer_ls180.v:84429.5-84429.29" - switch \initial - attribute \src "issuer_ls180.v:84429.9-84429.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0] - end - attribute \src "issuer_ls180.v:84483.3-84537.6" - process $proc$issuer_ls180.v:84483$3654 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "issuer_ls180.v:84484.5-84484.29" - switch \initial - attribute \src "issuer_ls180.v:84484.9-84484.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0] - end - attribute \src "issuer_ls180.v:84538.3-84592.6" - process $proc$issuer_ls180.v:84538$3655 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0] - attribute \src "issuer_ls180.v:84539.5-84539.29" - switch \initial - attribute \src "issuer_ls180.v:84539.9-84539.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - case - assign $1\dec31_dec_sub11_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0] - end - attribute \src "issuer_ls180.v:84593.3-84647.6" - process $proc$issuer_ls180.v:84593$3656 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "issuer_ls180.v:84594.5-84594.29" - switch \initial - attribute \src "issuer_ls180.v:84594.9-84594.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:84648.3-84702.6" - process $proc$issuer_ls180.v:84648$3657 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "issuer_ls180.v:84649.5-84649.29" - switch \initial - attribute \src "issuer_ls180.v:84649.9-84649.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 - case - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] - end - attribute \src "issuer_ls180.v:84703.3-84757.6" - process $proc$issuer_ls180.v:84703$3658 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "issuer_ls180.v:84704.5-84704.29" - switch \initial - attribute \src "issuer_ls180.v:84704.9-84704.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0] - end - attribute \src "issuer_ls180.v:84758.3-84812.6" - process $proc$issuer_ls180.v:84758$3659 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "issuer_ls180.v:84759.5-84759.29" - switch \initial - attribute \src "issuer_ls180.v:84759.9-84759.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - case - assign $1\dec31_dec_sub11_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] - end - attribute \src "issuer_ls180.v:84813.3-84867.6" - process $proc$issuer_ls180.v:84813$3660 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0] - attribute \src "issuer_ls180.v:84814.5-84814.29" - switch \initial - attribute \src "issuer_ls180.v:84814.9-84814.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - case - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0] - end - attribute \src "issuer_ls180.v:84868.3-84922.6" - process $proc$issuer_ls180.v:84868$3661 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0] - attribute \src "issuer_ls180.v:84869.5-84869.29" - switch \initial - attribute \src "issuer_ls180.v:84869.9-84869.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0] - end - attribute \src "issuer_ls180.v:84923.3-84977.6" - process $proc$issuer_ls180.v:84923$3662 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:84924.5-84924.29" - switch \initial - attribute \src "issuer_ls180.v:84924.9-84924.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0] - end - attribute \src "issuer_ls180.v:84978.3-85032.6" - process $proc$issuer_ls180.v:84978$3663 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] - attribute \src "issuer_ls180.v:84979.5-84979.29" - switch \initial - attribute \src "issuer_ls180.v:84979.9-84979.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - case - assign $1\dec31_dec_sub11_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] - end - attribute \src "issuer_ls180.v:85033.3-85087.6" - process $proc$issuer_ls180.v:85033$3664 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "issuer_ls180.v:85034.5-85034.29" - switch \initial - attribute \src "issuer_ls180.v:85034.9-85034.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - case - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:85088.3-85142.6" - process $proc$issuer_ls180.v:85088$3665 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "issuer_ls180.v:85089.5-85089.29" - switch \initial - attribute \src "issuer_ls180.v:85089.9-85089.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:85143.3-85197.6" - process $proc$issuer_ls180.v:85143$3666 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "issuer_ls180.v:85144.5-85144.29" - switch \initial - attribute \src "issuer_ls180.v:85144.9-85144.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0] - end - attribute \src "issuer_ls180.v:85198.3-85252.6" - process $proc$issuer_ls180.v:85198$3667 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_out_sel[1:0] $1\dec31_dec_sub11_out_sel[1:0] - attribute \src "issuer_ls180.v:85199.5-85199.29" - switch \initial - attribute \src "issuer_ls180.v:85199.9-85199.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub11_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub11_out_sel $0\dec31_dec_sub11_out_sel[1:0] - end - attribute \src "issuer_ls180.v:85253.3-85307.6" - process $proc$issuer_ls180.v:85253$3668 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "issuer_ls180.v:85254.5-85254.29" - switch \initial - attribute \src "issuer_ls180.v:85254.9-85254.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0] - end - attribute \src "issuer_ls180.v:85308.3-85362.6" - process $proc$issuer_ls180.v:85308$3669 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "issuer_ls180.v:85309.5-85309.29" - switch \initial - attribute \src "issuer_ls180.v:85309.9-85309.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:85368.1-88099.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub15" -attribute \generator "nMigen" -module \dec31_dec_sub15 - attribute \src "issuer_ls180.v:86141.3-86243.6" - wire width 8 $0\dec31_dec_sub15_asmcode[7:0] - attribute \src "issuer_ls180.v:86553.3-86655.6" - wire $0\dec31_dec_sub15_br[0:0] - attribute \src "issuer_ls180.v:87892.3-87994.6" - wire width 3 $0\dec31_dec_sub15_cr_in[2:0] - attribute \src "issuer_ls180.v:87995.3-88097.6" - wire width 3 $0\dec31_dec_sub15_cr_out[2:0] - attribute \src "issuer_ls180.v:86038.3-86140.6" - wire width 2 $0\dec31_dec_sub15_cry_in[1:0] - attribute \src "issuer_ls180.v:86450.3-86552.6" - wire $0\dec31_dec_sub15_cry_out[0:0] - attribute \src "issuer_ls180.v:87377.3-87479.6" - wire width 5 $0\dec31_dec_sub15_form[4:0] - attribute \src "issuer_ls180.v:85626.3-85728.6" - wire width 12 $0\dec31_dec_sub15_function_unit[11:0] - attribute \src "issuer_ls180.v:87480.3-87582.6" - wire width 3 $0\dec31_dec_sub15_in1_sel[2:0] - attribute \src "issuer_ls180.v:87583.3-87685.6" - wire width 4 $0\dec31_dec_sub15_in2_sel[3:0] - attribute \src "issuer_ls180.v:87686.3-87788.6" - wire width 2 $0\dec31_dec_sub15_in3_sel[1:0] - attribute \src "issuer_ls180.v:86759.3-86861.6" - wire width 7 $0\dec31_dec_sub15_internal_op[6:0] - attribute \src "issuer_ls180.v:86244.3-86346.6" - wire $0\dec31_dec_sub15_inv_a[0:0] - attribute \src "issuer_ls180.v:86347.3-86449.6" - wire $0\dec31_dec_sub15_inv_out[0:0] - attribute \src "issuer_ls180.v:86965.3-87067.6" - wire $0\dec31_dec_sub15_is_32b[0:0] - attribute \src "issuer_ls180.v:85729.3-85831.6" - wire width 4 $0\dec31_dec_sub15_ldst_len[3:0] - attribute \src "issuer_ls180.v:87171.3-87273.6" - wire $0\dec31_dec_sub15_lk[0:0] - attribute \src "issuer_ls180.v:87789.3-87891.6" - wire width 2 $0\dec31_dec_sub15_out_sel[1:0] - attribute \src "issuer_ls180.v:85935.3-86037.6" - wire width 2 $0\dec31_dec_sub15_rc_sel[1:0] - attribute \src "issuer_ls180.v:86862.3-86964.6" - wire $0\dec31_dec_sub15_rsrv[0:0] - attribute \src "issuer_ls180.v:87274.3-87376.6" - wire $0\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:87068.3-87170.6" - wire $0\dec31_dec_sub15_sgn[0:0] - attribute \src "issuer_ls180.v:86656.3-86758.6" - wire $0\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "issuer_ls180.v:85832.3-85934.6" - wire width 2 $0\dec31_dec_sub15_upd[1:0] - attribute \src "issuer_ls180.v:85369.7-85369.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:86141.3-86243.6" - wire width 8 $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "issuer_ls180.v:86553.3-86655.6" - wire $1\dec31_dec_sub15_br[0:0] - attribute \src "issuer_ls180.v:87892.3-87994.6" - wire width 3 $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "issuer_ls180.v:87995.3-88097.6" - wire width 3 $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "issuer_ls180.v:86038.3-86140.6" - wire width 2 $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "issuer_ls180.v:86450.3-86552.6" - wire $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "issuer_ls180.v:87377.3-87479.6" - wire width 5 $1\dec31_dec_sub15_form[4:0] - attribute \src "issuer_ls180.v:85626.3-85728.6" - wire width 12 $1\dec31_dec_sub15_function_unit[11:0] - attribute \src "issuer_ls180.v:87480.3-87582.6" - wire width 3 $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "issuer_ls180.v:87583.3-87685.6" - wire width 4 $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "issuer_ls180.v:87686.3-87788.6" - wire width 2 $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "issuer_ls180.v:86759.3-86861.6" - wire width 7 $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "issuer_ls180.v:86244.3-86346.6" - wire $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "issuer_ls180.v:86347.3-86449.6" - wire $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "issuer_ls180.v:86965.3-87067.6" - wire $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "issuer_ls180.v:85729.3-85831.6" - wire width 4 $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "issuer_ls180.v:87171.3-87273.6" - wire $1\dec31_dec_sub15_lk[0:0] - attribute \src "issuer_ls180.v:87789.3-87891.6" - wire width 2 $1\dec31_dec_sub15_out_sel[1:0] - attribute \src "issuer_ls180.v:85935.3-86037.6" - wire width 2 $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "issuer_ls180.v:86862.3-86964.6" - wire $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "issuer_ls180.v:87274.3-87376.6" - wire $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:87068.3-87170.6" - wire $1\dec31_dec_sub15_sgn[0:0] - attribute \src "issuer_ls180.v:86656.3-86758.6" - wire $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "issuer_ls180.v:85832.3-85934.6" - wire width 2 $1\dec31_dec_sub15_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub15_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub15_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub15_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub15_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub15_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub15_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub15_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub15_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub15_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub15_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub15_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub15_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub15_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub15_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub15_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub15_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub15_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub15_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub15_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub15_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub15_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub15_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub15_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub15_upd - attribute \src "issuer_ls180.v:85369.7-85369.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:85369.7-85369.20" - process $proc$issuer_ls180.v:85369$3695 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:85626.3-85728.6" - process $proc$issuer_ls180.v:85626$3671 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_function_unit[11:0] $1\dec31_dec_sub15_function_unit[11:0] - attribute \src "issuer_ls180.v:85627.5-85627.29" - switch \initial - attribute \src "issuer_ls180.v:85627.9-85627.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - case - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[11:0] - end - attribute \src "issuer_ls180.v:85729.3-85831.6" - process $proc$issuer_ls180.v:85729$3672 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "issuer_ls180.v:85730.5-85730.29" - switch \initial - attribute \src "issuer_ls180.v:85730.9-85730.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:85832.3-85934.6" - process $proc$issuer_ls180.v:85832$3673 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] - attribute \src "issuer_ls180.v:85833.5-85833.29" - switch \initial - attribute \src "issuer_ls180.v:85833.9-85833.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] - end - attribute \src "issuer_ls180.v:85935.3-86037.6" - process $proc$issuer_ls180.v:85935$3674 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "issuer_ls180.v:85936.5-85936.29" - switch \initial - attribute \src "issuer_ls180.v:85936.9-85936.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:86038.3-86140.6" - process $proc$issuer_ls180.v:86038$3675 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "issuer_ls180.v:86039.5-86039.29" - switch \initial - attribute \src "issuer_ls180.v:86039.9-86039.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0] - end - attribute \src "issuer_ls180.v:86141.3-86243.6" - process $proc$issuer_ls180.v:86141$3676 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "issuer_ls180.v:86142.5-86142.29" - switch \initial - attribute \src "issuer_ls180.v:86142.9-86142.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - case - assign $1\dec31_dec_sub15_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0] - end - attribute \src "issuer_ls180.v:86244.3-86346.6" - process $proc$issuer_ls180.v:86244$3677 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "issuer_ls180.v:86245.5-86245.29" - switch \initial - attribute \src "issuer_ls180.v:86245.9-86245.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0] - end - attribute \src "issuer_ls180.v:86347.3-86449.6" - process $proc$issuer_ls180.v:86347$3678 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "issuer_ls180.v:86348.5-86348.29" - switch \initial - attribute \src "issuer_ls180.v:86348.9-86348.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0] - end - attribute \src "issuer_ls180.v:86450.3-86552.6" - process $proc$issuer_ls180.v:86450$3679 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "issuer_ls180.v:86451.5-86451.29" - switch \initial - attribute \src "issuer_ls180.v:86451.9-86451.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0] - end - attribute \src "issuer_ls180.v:86553.3-86655.6" - process $proc$issuer_ls180.v:86553$3680 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0] - attribute \src "issuer_ls180.v:86554.5-86554.29" - switch \initial - attribute \src "issuer_ls180.v:86554.9-86554.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - case - assign $1\dec31_dec_sub15_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0] - end - attribute \src "issuer_ls180.v:86656.3-86758.6" - process $proc$issuer_ls180.v:86656$3681 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "issuer_ls180.v:86657.5-86657.29" - switch \initial - attribute \src "issuer_ls180.v:86657.9-86657.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:86759.3-86861.6" - process $proc$issuer_ls180.v:86759$3682 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "issuer_ls180.v:86760.5-86760.29" - switch \initial - attribute \src "issuer_ls180.v:86760.9-86760.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - case - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] - end - attribute \src "issuer_ls180.v:86862.3-86964.6" - process $proc$issuer_ls180.v:86862$3683 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "issuer_ls180.v:86863.5-86863.29" - switch \initial - attribute \src "issuer_ls180.v:86863.9-86863.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0] - end - attribute \src "issuer_ls180.v:86965.3-87067.6" - process $proc$issuer_ls180.v:86965$3684 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "issuer_ls180.v:86966.5-86966.29" - switch \initial - attribute \src "issuer_ls180.v:86966.9-86966.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] - end - attribute \src "issuer_ls180.v:87068.3-87170.6" - process $proc$issuer_ls180.v:87068$3685 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0] - attribute \src "issuer_ls180.v:87069.5-87069.29" - switch \initial - attribute \src "issuer_ls180.v:87069.9-87069.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0] - end - attribute \src "issuer_ls180.v:87171.3-87273.6" - process $proc$issuer_ls180.v:87171$3686 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0] - attribute \src "issuer_ls180.v:87172.5-87172.29" - switch \initial - attribute \src "issuer_ls180.v:87172.9-87172.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0] - end - attribute \src "issuer_ls180.v:87274.3-87376.6" - process $proc$issuer_ls180.v:87274$3687 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:87275.5-87275.29" - switch \initial - attribute \src "issuer_ls180.v:87275.9-87275.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - case - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0] - end - attribute \src "issuer_ls180.v:87377.3-87479.6" - process $proc$issuer_ls180.v:87377$3688 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] - attribute \src "issuer_ls180.v:87378.5-87378.29" - switch \initial - attribute \src "issuer_ls180.v:87378.9-87378.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - case - assign $1\dec31_dec_sub15_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] - end - attribute \src "issuer_ls180.v:87480.3-87582.6" - process $proc$issuer_ls180.v:87480$3689 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "issuer_ls180.v:87481.5-87481.29" - switch \initial - attribute \src "issuer_ls180.v:87481.9-87481.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - case - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:87583.3-87685.6" - process $proc$issuer_ls180.v:87583$3690 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "issuer_ls180.v:87584.5-87584.29" - switch \initial - attribute \src "issuer_ls180.v:87584.9-87584.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:87686.3-87788.6" - process $proc$issuer_ls180.v:87686$3691 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "issuer_ls180.v:87687.5-87687.29" - switch \initial - attribute \src "issuer_ls180.v:87687.9-87687.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0] - end - attribute \src "issuer_ls180.v:87789.3-87891.6" - process $proc$issuer_ls180.v:87789$3692 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_out_sel[1:0] $1\dec31_dec_sub15_out_sel[1:0] - attribute \src "issuer_ls180.v:87790.5-87790.29" - switch \initial - attribute \src "issuer_ls180.v:87790.9-87790.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub15_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub15_out_sel $0\dec31_dec_sub15_out_sel[1:0] - end - attribute \src "issuer_ls180.v:87892.3-87994.6" - process $proc$issuer_ls180.v:87892$3693 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "issuer_ls180.v:87893.5-87893.29" - switch \initial - attribute \src "issuer_ls180.v:87893.9-87893.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - case - assign $1\dec31_dec_sub15_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0] - end - attribute \src "issuer_ls180.v:87995.3-88097.6" - process $proc$issuer_ls180.v:87995$3694 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "issuer_ls180.v:87996.5-87996.29" - switch \initial - attribute \src "issuer_ls180.v:87996.9-87996.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:88103.1-88602.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub16" -attribute \generator "nMigen" -module \dec31_dec_sub16 - attribute \src "issuer_ls180.v:88411.3-88420.6" - wire width 8 $0\dec31_dec_sub16_asmcode[7:0] - attribute \src "issuer_ls180.v:88451.3-88460.6" - wire $0\dec31_dec_sub16_br[0:0] - attribute \src "issuer_ls180.v:88581.3-88590.6" - wire width 3 $0\dec31_dec_sub16_cr_in[2:0] - attribute \src "issuer_ls180.v:88591.3-88600.6" - wire width 3 $0\dec31_dec_sub16_cr_out[2:0] - attribute \src "issuer_ls180.v:88401.3-88410.6" - wire width 2 $0\dec31_dec_sub16_cry_in[1:0] - attribute \src "issuer_ls180.v:88441.3-88450.6" - wire $0\dec31_dec_sub16_cry_out[0:0] - attribute \src "issuer_ls180.v:88531.3-88540.6" - wire width 5 $0\dec31_dec_sub16_form[4:0] - attribute \src "issuer_ls180.v:88361.3-88370.6" - wire width 12 $0\dec31_dec_sub16_function_unit[11:0] - attribute \src "issuer_ls180.v:88541.3-88550.6" - wire width 3 $0\dec31_dec_sub16_in1_sel[2:0] - attribute \src "issuer_ls180.v:88551.3-88560.6" - wire width 4 $0\dec31_dec_sub16_in2_sel[3:0] - attribute \src "issuer_ls180.v:88561.3-88570.6" - wire width 2 $0\dec31_dec_sub16_in3_sel[1:0] - attribute \src "issuer_ls180.v:88471.3-88480.6" - wire width 7 $0\dec31_dec_sub16_internal_op[6:0] - attribute \src "issuer_ls180.v:88421.3-88430.6" - wire $0\dec31_dec_sub16_inv_a[0:0] - attribute \src "issuer_ls180.v:88431.3-88440.6" - wire $0\dec31_dec_sub16_inv_out[0:0] - attribute \src "issuer_ls180.v:88491.3-88500.6" - wire $0\dec31_dec_sub16_is_32b[0:0] - attribute \src "issuer_ls180.v:88371.3-88380.6" - wire width 4 $0\dec31_dec_sub16_ldst_len[3:0] - attribute \src "issuer_ls180.v:88511.3-88520.6" - wire $0\dec31_dec_sub16_lk[0:0] - attribute \src "issuer_ls180.v:88571.3-88580.6" - wire width 2 $0\dec31_dec_sub16_out_sel[1:0] - attribute \src "issuer_ls180.v:88391.3-88400.6" - wire width 2 $0\dec31_dec_sub16_rc_sel[1:0] - attribute \src "issuer_ls180.v:88481.3-88490.6" - wire $0\dec31_dec_sub16_rsrv[0:0] - attribute \src "issuer_ls180.v:88521.3-88530.6" - wire $0\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:88501.3-88510.6" - wire $0\dec31_dec_sub16_sgn[0:0] - attribute \src "issuer_ls180.v:88461.3-88470.6" - wire $0\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "issuer_ls180.v:88381.3-88390.6" - wire width 2 $0\dec31_dec_sub16_upd[1:0] - attribute \src "issuer_ls180.v:88104.7-88104.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:88411.3-88420.6" - wire width 8 $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "issuer_ls180.v:88451.3-88460.6" - wire $1\dec31_dec_sub16_br[0:0] - attribute \src "issuer_ls180.v:88581.3-88590.6" - wire width 3 $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "issuer_ls180.v:88591.3-88600.6" - wire width 3 $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "issuer_ls180.v:88401.3-88410.6" - wire width 2 $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "issuer_ls180.v:88441.3-88450.6" - wire $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "issuer_ls180.v:88531.3-88540.6" - wire width 5 $1\dec31_dec_sub16_form[4:0] - attribute \src "issuer_ls180.v:88361.3-88370.6" - wire width 12 $1\dec31_dec_sub16_function_unit[11:0] - attribute \src "issuer_ls180.v:88541.3-88550.6" - wire width 3 $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "issuer_ls180.v:88551.3-88560.6" - wire width 4 $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "issuer_ls180.v:88561.3-88570.6" - wire width 2 $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "issuer_ls180.v:88471.3-88480.6" - wire width 7 $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "issuer_ls180.v:88421.3-88430.6" - wire $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "issuer_ls180.v:88431.3-88440.6" - wire $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "issuer_ls180.v:88491.3-88500.6" - wire $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "issuer_ls180.v:88371.3-88380.6" - wire width 4 $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "issuer_ls180.v:88511.3-88520.6" - wire $1\dec31_dec_sub16_lk[0:0] - attribute \src "issuer_ls180.v:88571.3-88580.6" - wire width 2 $1\dec31_dec_sub16_out_sel[1:0] - attribute \src "issuer_ls180.v:88391.3-88400.6" - wire width 2 $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "issuer_ls180.v:88481.3-88490.6" - wire $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "issuer_ls180.v:88521.3-88530.6" - wire $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:88501.3-88510.6" - wire $1\dec31_dec_sub16_sgn[0:0] - attribute \src "issuer_ls180.v:88461.3-88470.6" - wire $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "issuer_ls180.v:88381.3-88390.6" - wire width 2 $1\dec31_dec_sub16_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub16_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub16_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub16_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub16_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub16_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub16_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub16_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub16_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub16_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub16_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub16_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub16_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub16_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub16_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub16_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub16_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub16_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub16_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub16_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub16_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub16_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub16_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub16_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub16_upd - attribute \src "issuer_ls180.v:88104.7-88104.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:88104.7-88104.20" - process $proc$issuer_ls180.v:88104$3720 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:88361.3-88370.6" - process $proc$issuer_ls180.v:88361$3696 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_function_unit[11:0] $1\dec31_dec_sub16_function_unit[11:0] - attribute \src "issuer_ls180.v:88362.5-88362.29" - switch \initial - attribute \src "issuer_ls180.v:88362.9-88362.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_function_unit[11:0] 12'000001000000 - case - assign $1\dec31_dec_sub16_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[11:0] - end - attribute \src "issuer_ls180.v:88371.3-88380.6" - process $proc$issuer_ls180.v:88371$3697 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "issuer_ls180.v:88372.5-88372.29" - switch \initial - attribute \src "issuer_ls180.v:88372.9-88372.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:88381.3-88390.6" - process $proc$issuer_ls180.v:88381$3698 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] - attribute \src "issuer_ls180.v:88382.5-88382.29" - switch \initial - attribute \src "issuer_ls180.v:88382.9-88382.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub16_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] - end - attribute \src "issuer_ls180.v:88391.3-88400.6" - process $proc$issuer_ls180.v:88391$3699 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "issuer_ls180.v:88392.5-88392.29" - switch \initial - attribute \src "issuer_ls180.v:88392.9-88392.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:88401.3-88410.6" - process $proc$issuer_ls180.v:88401$3700 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "issuer_ls180.v:88402.5-88402.29" - switch \initial - attribute \src "issuer_ls180.v:88402.9-88402.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0] - end - attribute \src "issuer_ls180.v:88411.3-88420.6" - process $proc$issuer_ls180.v:88411$3701 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "issuer_ls180.v:88412.5-88412.29" - switch \initial - attribute \src "issuer_ls180.v:88412.9-88412.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_asmcode[7:0] 8'01110110 - case - assign $1\dec31_dec_sub16_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0] - end - attribute \src "issuer_ls180.v:88421.3-88430.6" - process $proc$issuer_ls180.v:88421$3702 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "issuer_ls180.v:88422.5-88422.29" - switch \initial - attribute \src "issuer_ls180.v:88422.9-88422.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0] - end - attribute \src "issuer_ls180.v:88431.3-88440.6" - process $proc$issuer_ls180.v:88431$3703 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "issuer_ls180.v:88432.5-88432.29" - switch \initial - attribute \src "issuer_ls180.v:88432.9-88432.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0] - end - attribute \src "issuer_ls180.v:88441.3-88450.6" - process $proc$issuer_ls180.v:88441$3704 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "issuer_ls180.v:88442.5-88442.29" - switch \initial - attribute \src "issuer_ls180.v:88442.9-88442.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0] - end - attribute \src "issuer_ls180.v:88451.3-88460.6" - process $proc$issuer_ls180.v:88451$3705 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0] - attribute \src "issuer_ls180.v:88452.5-88452.29" - switch \initial - attribute \src "issuer_ls180.v:88452.9-88452.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_br[0:0] 1'0 - case - assign $1\dec31_dec_sub16_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0] - end - attribute \src "issuer_ls180.v:88461.3-88470.6" - process $proc$issuer_ls180.v:88461$3706 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "issuer_ls180.v:88462.5-88462.29" - switch \initial - attribute \src "issuer_ls180.v:88462.9-88462.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:88471.3-88480.6" - process $proc$issuer_ls180.v:88471$3707 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "issuer_ls180.v:88472.5-88472.29" - switch \initial - attribute \src "issuer_ls180.v:88472.9-88472.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_internal_op[6:0] 7'0110000 - case - assign $1\dec31_dec_sub16_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] - end - attribute \src "issuer_ls180.v:88481.3-88490.6" - process $proc$issuer_ls180.v:88481$3708 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "issuer_ls180.v:88482.5-88482.29" - switch \initial - attribute \src "issuer_ls180.v:88482.9-88482.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0] - end - attribute \src "issuer_ls180.v:88491.3-88500.6" - process $proc$issuer_ls180.v:88491$3709 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "issuer_ls180.v:88492.5-88492.29" - switch \initial - attribute \src "issuer_ls180.v:88492.9-88492.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] - end - attribute \src "issuer_ls180.v:88501.3-88510.6" - process $proc$issuer_ls180.v:88501$3710 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0] - attribute \src "issuer_ls180.v:88502.5-88502.29" - switch \initial - attribute \src "issuer_ls180.v:88502.9-88502.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub16_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0] - end - attribute \src "issuer_ls180.v:88511.3-88520.6" - process $proc$issuer_ls180.v:88511$3711 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0] - attribute \src "issuer_ls180.v:88512.5-88512.29" - switch \initial - attribute \src "issuer_ls180.v:88512.9-88512.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub16_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0] - end - attribute \src "issuer_ls180.v:88521.3-88530.6" - process $proc$issuer_ls180.v:88521$3712 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:88522.5-88522.29" - switch \initial - attribute \src "issuer_ls180.v:88522.9-88522.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0] - end - attribute \src "issuer_ls180.v:88531.3-88540.6" - process $proc$issuer_ls180.v:88531$3713 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] - attribute \src "issuer_ls180.v:88532.5-88532.29" - switch \initial - attribute \src "issuer_ls180.v:88532.9-88532.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_form[4:0] 5'01010 - case - assign $1\dec31_dec_sub16_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] - end - attribute \src "issuer_ls180.v:88541.3-88550.6" - process $proc$issuer_ls180.v:88541$3714 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "issuer_ls180.v:88542.5-88542.29" - switch \initial - attribute \src "issuer_ls180.v:88542.9-88542.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_in1_sel[2:0] 3'100 - case - assign $1\dec31_dec_sub16_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:88551.3-88560.6" - process $proc$issuer_ls180.v:88551$3715 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "issuer_ls180.v:88552.5-88552.29" - switch \initial - attribute \src "issuer_ls180.v:88552.9-88552.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 - case - assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:88561.3-88570.6" - process $proc$issuer_ls180.v:88561$3716 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "issuer_ls180.v:88562.5-88562.29" - switch \initial - attribute \src "issuer_ls180.v:88562.9-88562.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0] - end - attribute \src "issuer_ls180.v:88571.3-88580.6" - process $proc$issuer_ls180.v:88571$3717 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_out_sel[1:0] $1\dec31_dec_sub16_out_sel[1:0] - attribute \src "issuer_ls180.v:88572.5-88572.29" - switch \initial - attribute \src "issuer_ls180.v:88572.9-88572.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub16_out_sel $0\dec31_dec_sub16_out_sel[1:0] - end - attribute \src "issuer_ls180.v:88581.3-88590.6" - process $proc$issuer_ls180.v:88581$3718 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "issuer_ls180.v:88582.5-88582.29" - switch \initial - attribute \src "issuer_ls180.v:88582.9-88582.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_cr_in[2:0] 3'110 - case - assign $1\dec31_dec_sub16_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0] - end - attribute \src "issuer_ls180.v:88591.3-88600.6" - process $proc$issuer_ls180.v:88591$3719 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "issuer_ls180.v:88592.5-88592.29" - switch \initial - attribute \src "issuer_ls180.v:88592.9-88592.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_cr_out[2:0] 3'100 - case - assign $1\dec31_dec_sub16_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:88606.1-89177.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub18" -attribute \generator "nMigen" -module \dec31_dec_sub18 - attribute \src "issuer_ls180.v:88929.3-88941.6" - wire width 8 $0\dec31_dec_sub18_asmcode[7:0] - attribute \src "issuer_ls180.v:88981.3-88993.6" - wire $0\dec31_dec_sub18_br[0:0] - attribute \src "issuer_ls180.v:89150.3-89162.6" - wire width 3 $0\dec31_dec_sub18_cr_in[2:0] - attribute \src "issuer_ls180.v:89163.3-89175.6" - wire width 3 $0\dec31_dec_sub18_cr_out[2:0] - attribute \src "issuer_ls180.v:88916.3-88928.6" - wire width 2 $0\dec31_dec_sub18_cry_in[1:0] - attribute \src "issuer_ls180.v:88968.3-88980.6" - wire $0\dec31_dec_sub18_cry_out[0:0] - attribute \src "issuer_ls180.v:89085.3-89097.6" - wire width 5 $0\dec31_dec_sub18_form[4:0] - attribute \src "issuer_ls180.v:88864.3-88876.6" - wire width 12 $0\dec31_dec_sub18_function_unit[11:0] - attribute \src "issuer_ls180.v:89098.3-89110.6" - wire width 3 $0\dec31_dec_sub18_in1_sel[2:0] - attribute \src "issuer_ls180.v:89111.3-89123.6" - wire width 4 $0\dec31_dec_sub18_in2_sel[3:0] - attribute \src "issuer_ls180.v:89124.3-89136.6" - wire width 2 $0\dec31_dec_sub18_in3_sel[1:0] - attribute \src "issuer_ls180.v:89007.3-89019.6" - wire width 7 $0\dec31_dec_sub18_internal_op[6:0] - attribute \src "issuer_ls180.v:88942.3-88954.6" - wire $0\dec31_dec_sub18_inv_a[0:0] - attribute \src "issuer_ls180.v:88955.3-88967.6" - wire $0\dec31_dec_sub18_inv_out[0:0] - attribute \src "issuer_ls180.v:89033.3-89045.6" - wire $0\dec31_dec_sub18_is_32b[0:0] - attribute \src "issuer_ls180.v:88877.3-88889.6" - wire width 4 $0\dec31_dec_sub18_ldst_len[3:0] - attribute \src "issuer_ls180.v:89059.3-89071.6" - wire $0\dec31_dec_sub18_lk[0:0] - attribute \src "issuer_ls180.v:89137.3-89149.6" - wire width 2 $0\dec31_dec_sub18_out_sel[1:0] - attribute \src "issuer_ls180.v:88903.3-88915.6" - wire width 2 $0\dec31_dec_sub18_rc_sel[1:0] - attribute \src "issuer_ls180.v:89020.3-89032.6" - wire $0\dec31_dec_sub18_rsrv[0:0] - attribute \src "issuer_ls180.v:89072.3-89084.6" - wire $0\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:89046.3-89058.6" - wire $0\dec31_dec_sub18_sgn[0:0] - attribute \src "issuer_ls180.v:88994.3-89006.6" - wire $0\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "issuer_ls180.v:88890.3-88902.6" - wire width 2 $0\dec31_dec_sub18_upd[1:0] - attribute \src "issuer_ls180.v:88607.7-88607.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:88929.3-88941.6" - wire width 8 $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "issuer_ls180.v:88981.3-88993.6" - wire $1\dec31_dec_sub18_br[0:0] - attribute \src "issuer_ls180.v:89150.3-89162.6" - wire width 3 $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "issuer_ls180.v:89163.3-89175.6" - wire width 3 $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "issuer_ls180.v:88916.3-88928.6" - wire width 2 $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "issuer_ls180.v:88968.3-88980.6" - wire $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "issuer_ls180.v:89085.3-89097.6" - wire width 5 $1\dec31_dec_sub18_form[4:0] - attribute \src "issuer_ls180.v:88864.3-88876.6" - wire width 12 $1\dec31_dec_sub18_function_unit[11:0] - attribute \src "issuer_ls180.v:89098.3-89110.6" - wire width 3 $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "issuer_ls180.v:89111.3-89123.6" - wire width 4 $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "issuer_ls180.v:89124.3-89136.6" - wire width 2 $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "issuer_ls180.v:89007.3-89019.6" - wire width 7 $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "issuer_ls180.v:88942.3-88954.6" - wire $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "issuer_ls180.v:88955.3-88967.6" - wire $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "issuer_ls180.v:89033.3-89045.6" - wire $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "issuer_ls180.v:88877.3-88889.6" - wire width 4 $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "issuer_ls180.v:89059.3-89071.6" - wire $1\dec31_dec_sub18_lk[0:0] - attribute \src "issuer_ls180.v:89137.3-89149.6" - wire width 2 $1\dec31_dec_sub18_out_sel[1:0] - attribute \src "issuer_ls180.v:88903.3-88915.6" - wire width 2 $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "issuer_ls180.v:89020.3-89032.6" - wire $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "issuer_ls180.v:89072.3-89084.6" - wire $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:89046.3-89058.6" - wire $1\dec31_dec_sub18_sgn[0:0] - attribute \src "issuer_ls180.v:88994.3-89006.6" - wire $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "issuer_ls180.v:88890.3-88902.6" - wire width 2 $1\dec31_dec_sub18_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub18_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub18_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub18_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub18_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub18_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub18_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub18_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub18_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub18_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub18_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub18_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub18_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub18_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub18_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub18_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub18_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub18_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub18_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub18_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub18_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub18_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub18_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub18_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub18_upd - attribute \src "issuer_ls180.v:88607.7-88607.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:88607.7-88607.20" - process $proc$issuer_ls180.v:88607$3745 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:88864.3-88876.6" - process $proc$issuer_ls180.v:88864$3721 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_function_unit[11:0] $1\dec31_dec_sub18_function_unit[11:0] - attribute \src "issuer_ls180.v:88865.5-88865.29" - switch \initial - attribute \src "issuer_ls180.v:88865.9-88865.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000 - case - assign $1\dec31_dec_sub18_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[11:0] - end - attribute \src "issuer_ls180.v:88877.3-88889.6" - process $proc$issuer_ls180.v:88877$3722 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "issuer_ls180.v:88878.5-88878.29" - switch \initial - attribute \src "issuer_ls180.v:88878.9-88878.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:88890.3-88902.6" - process $proc$issuer_ls180.v:88890$3723 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] - attribute \src "issuer_ls180.v:88891.5-88891.29" - switch \initial - attribute \src "issuer_ls180.v:88891.9-88891.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] - end - attribute \src "issuer_ls180.v:88903.3-88915.6" - process $proc$issuer_ls180.v:88903$3724 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "issuer_ls180.v:88904.5-88904.29" - switch \initial - attribute \src "issuer_ls180.v:88904.9-88904.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:88916.3-88928.6" - process $proc$issuer_ls180.v:88916$3725 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "issuer_ls180.v:88917.5-88917.29" - switch \initial - attribute \src "issuer_ls180.v:88917.9-88917.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] - end - attribute \src "issuer_ls180.v:88929.3-88941.6" - process $proc$issuer_ls180.v:88929$3726 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "issuer_ls180.v:88930.5-88930.29" - switch \initial - attribute \src "issuer_ls180.v:88930.9-88930.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_asmcode[7:0] 8'01111000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_asmcode[7:0] 8'01110111 - case - assign $1\dec31_dec_sub18_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0] - end - attribute \src "issuer_ls180.v:88942.3-88954.6" - process $proc$issuer_ls180.v:88942$3727 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "issuer_ls180.v:88943.5-88943.29" - switch \initial - attribute \src "issuer_ls180.v:88943.9-88943.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0] - end - attribute \src "issuer_ls180.v:88955.3-88967.6" - process $proc$issuer_ls180.v:88955$3728 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "issuer_ls180.v:88956.5-88956.29" - switch \initial - attribute \src "issuer_ls180.v:88956.9-88956.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0] - end - attribute \src "issuer_ls180.v:88968.3-88980.6" - process $proc$issuer_ls180.v:88968$3729 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "issuer_ls180.v:88969.5-88969.29" - switch \initial - attribute \src "issuer_ls180.v:88969.9-88969.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0] - end - attribute \src "issuer_ls180.v:88981.3-88993.6" - process $proc$issuer_ls180.v:88981$3730 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0] - attribute \src "issuer_ls180.v:88982.5-88982.29" - switch \initial - attribute \src "issuer_ls180.v:88982.9-88982.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_br[0:0] 1'0 - case - assign $1\dec31_dec_sub18_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0] - end - attribute \src "issuer_ls180.v:88994.3-89006.6" - process $proc$issuer_ls180.v:88994$3731 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "issuer_ls180.v:88995.5-88995.29" - switch \initial - attribute \src "issuer_ls180.v:88995.9-88995.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:89007.3-89019.6" - process $proc$issuer_ls180.v:89007$3732 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "issuer_ls180.v:89008.5-89008.29" - switch \initial - attribute \src "issuer_ls180.v:89008.9-89008.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010 - case - assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] - end - attribute \src "issuer_ls180.v:89020.3-89032.6" - process $proc$issuer_ls180.v:89020$3733 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "issuer_ls180.v:89021.5-89021.29" - switch \initial - attribute \src "issuer_ls180.v:89021.9-89021.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0] - end - attribute \src "issuer_ls180.v:89033.3-89045.6" - process $proc$issuer_ls180.v:89033$3734 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "issuer_ls180.v:89034.5-89034.29" - switch \initial - attribute \src "issuer_ls180.v:89034.9-89034.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] - end - attribute \src "issuer_ls180.v:89046.3-89058.6" - process $proc$issuer_ls180.v:89046$3735 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0] - attribute \src "issuer_ls180.v:89047.5-89047.29" - switch \initial - attribute \src "issuer_ls180.v:89047.9-89047.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0] - end - attribute \src "issuer_ls180.v:89059.3-89071.6" - process $proc$issuer_ls180.v:89059$3736 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0] - attribute \src "issuer_ls180.v:89060.5-89060.29" - switch \initial - attribute \src "issuer_ls180.v:89060.9-89060.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub18_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0] - end - attribute \src "issuer_ls180.v:89072.3-89084.6" - process $proc$issuer_ls180.v:89072$3737 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:89073.5-89073.29" - switch \initial - attribute \src "issuer_ls180.v:89073.9-89073.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 - case - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0] - end - attribute \src "issuer_ls180.v:89085.3-89097.6" - process $proc$issuer_ls180.v:89085$3738 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] - attribute \src "issuer_ls180.v:89086.5-89086.29" - switch \initial - attribute \src "issuer_ls180.v:89086.9-89086.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub18_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] - end - attribute \src "issuer_ls180.v:89098.3-89110.6" - process $proc$issuer_ls180.v:89098$3739 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "issuer_ls180.v:89099.5-89099.29" - switch \initial - attribute \src "issuer_ls180.v:89099.9-89099.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 - case - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:89111.3-89123.6" - process $proc$issuer_ls180.v:89111$3740 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "issuer_ls180.v:89112.5-89112.29" - switch \initial - attribute \src "issuer_ls180.v:89112.9-89112.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 - case - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:89124.3-89136.6" - process $proc$issuer_ls180.v:89124$3741 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "issuer_ls180.v:89125.5-89125.29" - switch \initial - attribute \src "issuer_ls180.v:89125.9-89125.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0] - end - attribute \src "issuer_ls180.v:89137.3-89149.6" - process $proc$issuer_ls180.v:89137$3742 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_out_sel[1:0] $1\dec31_dec_sub18_out_sel[1:0] - attribute \src "issuer_ls180.v:89138.5-89138.29" - switch \initial - attribute \src "issuer_ls180.v:89138.9-89138.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[1:0] - end - attribute \src "issuer_ls180.v:89150.3-89162.6" - process $proc$issuer_ls180.v:89150$3743 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "issuer_ls180.v:89151.5-89151.29" - switch \initial - attribute \src "issuer_ls180.v:89151.9-89151.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] - end - attribute \src "issuer_ls180.v:89163.3-89175.6" - process $proc$issuer_ls180.v:89163$3744 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "issuer_ls180.v:89164.5-89164.29" - switch \initial - attribute \src "issuer_ls180.v:89164.9-89164.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:89181.1-89896.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub19" -attribute \generator "nMigen" -module \dec31_dec_sub19 - attribute \src "issuer_ls180.v:89534.3-89552.6" - wire width 8 $0\dec31_dec_sub19_asmcode[7:0] - attribute \src "issuer_ls180.v:89610.3-89628.6" - wire $0\dec31_dec_sub19_br[0:0] - attribute \src "issuer_ls180.v:89857.3-89875.6" - wire width 3 $0\dec31_dec_sub19_cr_in[2:0] - attribute \src "issuer_ls180.v:89876.3-89894.6" - wire width 3 $0\dec31_dec_sub19_cr_out[2:0] - attribute \src "issuer_ls180.v:89515.3-89533.6" - wire width 2 $0\dec31_dec_sub19_cry_in[1:0] - attribute \src "issuer_ls180.v:89591.3-89609.6" - wire $0\dec31_dec_sub19_cry_out[0:0] - attribute \src "issuer_ls180.v:89762.3-89780.6" - wire width 5 $0\dec31_dec_sub19_form[4:0] - attribute \src "issuer_ls180.v:89439.3-89457.6" - wire width 12 $0\dec31_dec_sub19_function_unit[11:0] - attribute \src "issuer_ls180.v:89781.3-89799.6" - wire width 3 $0\dec31_dec_sub19_in1_sel[2:0] - attribute \src "issuer_ls180.v:89800.3-89818.6" - wire width 4 $0\dec31_dec_sub19_in2_sel[3:0] - attribute \src "issuer_ls180.v:89819.3-89837.6" - wire width 2 $0\dec31_dec_sub19_in3_sel[1:0] - attribute \src "issuer_ls180.v:89648.3-89666.6" - wire width 7 $0\dec31_dec_sub19_internal_op[6:0] - attribute \src "issuer_ls180.v:89553.3-89571.6" - wire $0\dec31_dec_sub19_inv_a[0:0] - attribute \src "issuer_ls180.v:89572.3-89590.6" - wire $0\dec31_dec_sub19_inv_out[0:0] - attribute \src "issuer_ls180.v:89686.3-89704.6" - wire $0\dec31_dec_sub19_is_32b[0:0] - attribute \src "issuer_ls180.v:89458.3-89476.6" - wire width 4 $0\dec31_dec_sub19_ldst_len[3:0] - attribute \src "issuer_ls180.v:89724.3-89742.6" - wire $0\dec31_dec_sub19_lk[0:0] - attribute \src "issuer_ls180.v:89838.3-89856.6" - wire width 2 $0\dec31_dec_sub19_out_sel[1:0] - attribute \src "issuer_ls180.v:89496.3-89514.6" - wire width 2 $0\dec31_dec_sub19_rc_sel[1:0] - attribute \src "issuer_ls180.v:89667.3-89685.6" - wire $0\dec31_dec_sub19_rsrv[0:0] - attribute \src "issuer_ls180.v:89743.3-89761.6" - wire $0\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:89705.3-89723.6" - wire $0\dec31_dec_sub19_sgn[0:0] - attribute \src "issuer_ls180.v:89629.3-89647.6" - wire $0\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "issuer_ls180.v:89477.3-89495.6" - wire width 2 $0\dec31_dec_sub19_upd[1:0] - attribute \src "issuer_ls180.v:89182.7-89182.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:89534.3-89552.6" - wire width 8 $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "issuer_ls180.v:89610.3-89628.6" - wire $1\dec31_dec_sub19_br[0:0] - attribute \src "issuer_ls180.v:89857.3-89875.6" - wire width 3 $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "issuer_ls180.v:89876.3-89894.6" - wire width 3 $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "issuer_ls180.v:89515.3-89533.6" - wire width 2 $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "issuer_ls180.v:89591.3-89609.6" - wire $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "issuer_ls180.v:89762.3-89780.6" - wire width 5 $1\dec31_dec_sub19_form[4:0] - attribute \src "issuer_ls180.v:89439.3-89457.6" - wire width 12 $1\dec31_dec_sub19_function_unit[11:0] - attribute \src "issuer_ls180.v:89781.3-89799.6" - wire width 3 $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "issuer_ls180.v:89800.3-89818.6" - wire width 4 $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "issuer_ls180.v:89819.3-89837.6" - wire width 2 $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "issuer_ls180.v:89648.3-89666.6" - wire width 7 $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "issuer_ls180.v:89553.3-89571.6" - wire $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "issuer_ls180.v:89572.3-89590.6" - wire $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "issuer_ls180.v:89686.3-89704.6" - wire $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "issuer_ls180.v:89458.3-89476.6" - wire width 4 $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "issuer_ls180.v:89724.3-89742.6" - wire $1\dec31_dec_sub19_lk[0:0] - attribute \src "issuer_ls180.v:89838.3-89856.6" - wire width 2 $1\dec31_dec_sub19_out_sel[1:0] - attribute \src "issuer_ls180.v:89496.3-89514.6" - wire width 2 $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "issuer_ls180.v:89667.3-89685.6" - wire $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "issuer_ls180.v:89743.3-89761.6" - wire $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:89705.3-89723.6" - wire $1\dec31_dec_sub19_sgn[0:0] - attribute \src "issuer_ls180.v:89629.3-89647.6" - wire $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "issuer_ls180.v:89477.3-89495.6" - wire width 2 $1\dec31_dec_sub19_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub19_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub19_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub19_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub19_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub19_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub19_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub19_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub19_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub19_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub19_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub19_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub19_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub19_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub19_upd - attribute \src "issuer_ls180.v:89182.7-89182.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:89182.7-89182.20" - process $proc$issuer_ls180.v:89182$3770 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:89439.3-89457.6" - process $proc$issuer_ls180.v:89439$3746 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_function_unit[11:0] $1\dec31_dec_sub19_function_unit[11:0] - attribute \src "issuer_ls180.v:89440.5-89440.29" - switch \initial - attribute \src "issuer_ls180.v:89440.9-89440.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_function_unit[11:0] 12'000001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_function_unit[11:0] 12'000010000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000 - case - assign $1\dec31_dec_sub19_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[11:0] - end - attribute \src "issuer_ls180.v:89458.3-89476.6" - process $proc$issuer_ls180.v:89458$3747 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "issuer_ls180.v:89459.5-89459.29" - switch \initial - attribute \src "issuer_ls180.v:89459.9-89459.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:89477.3-89495.6" - process $proc$issuer_ls180.v:89477$3748 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] - attribute \src "issuer_ls180.v:89478.5-89478.29" - switch \initial - attribute \src "issuer_ls180.v:89478.9-89478.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub19_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] - end - attribute \src "issuer_ls180.v:89496.3-89514.6" - process $proc$issuer_ls180.v:89496$3749 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "issuer_ls180.v:89497.5-89497.29" - switch \initial - attribute \src "issuer_ls180.v:89497.9-89497.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:89515.3-89533.6" - process $proc$issuer_ls180.v:89515$3750 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "issuer_ls180.v:89516.5-89516.29" - switch \initial - attribute \src "issuer_ls180.v:89516.9-89516.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0] - end - attribute \src "issuer_ls180.v:89534.3-89552.6" - process $proc$issuer_ls180.v:89534$3751 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "issuer_ls180.v:89535.5-89535.29" - switch \initial - attribute \src "issuer_ls180.v:89535.9-89535.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_asmcode[7:0] 8'01101111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_asmcode[7:0] 8'01111001 - case - assign $1\dec31_dec_sub19_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0] - end - attribute \src "issuer_ls180.v:89553.3-89571.6" - process $proc$issuer_ls180.v:89553$3752 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "issuer_ls180.v:89554.5-89554.29" - switch \initial - attribute \src "issuer_ls180.v:89554.9-89554.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0] - end - attribute \src "issuer_ls180.v:89572.3-89590.6" - process $proc$issuer_ls180.v:89572$3753 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "issuer_ls180.v:89573.5-89573.29" - switch \initial - attribute \src "issuer_ls180.v:89573.9-89573.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0] - end - attribute \src "issuer_ls180.v:89591.3-89609.6" - process $proc$issuer_ls180.v:89591$3754 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "issuer_ls180.v:89592.5-89592.29" - switch \initial - attribute \src "issuer_ls180.v:89592.9-89592.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0] - end - attribute \src "issuer_ls180.v:89610.3-89628.6" - process $proc$issuer_ls180.v:89610$3755 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0] - attribute \src "issuer_ls180.v:89611.5-89611.29" - switch \initial - attribute \src "issuer_ls180.v:89611.9-89611.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_br[0:0] 1'0 - case - assign $1\dec31_dec_sub19_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0] - end - attribute \src "issuer_ls180.v:89629.3-89647.6" - process $proc$issuer_ls180.v:89629$3756 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "issuer_ls180.v:89630.5-89630.29" - switch \initial - attribute \src "issuer_ls180.v:89630.9-89630.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:89648.3-89666.6" - process $proc$issuer_ls180.v:89648$3757 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "issuer_ls180.v:89649.5-89649.29" - switch \initial - attribute \src "issuer_ls180.v:89649.9-89649.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'1000111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0110001 - case - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] - end - attribute \src "issuer_ls180.v:89667.3-89685.6" - process $proc$issuer_ls180.v:89667$3758 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "issuer_ls180.v:89668.5-89668.29" - switch \initial - attribute \src "issuer_ls180.v:89668.9-89668.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0] - end - attribute \src "issuer_ls180.v:89686.3-89704.6" - process $proc$issuer_ls180.v:89686$3759 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "issuer_ls180.v:89687.5-89687.29" - switch \initial - attribute \src "issuer_ls180.v:89687.9-89687.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] - end - attribute \src "issuer_ls180.v:89705.3-89723.6" - process $proc$issuer_ls180.v:89705$3760 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0] - attribute \src "issuer_ls180.v:89706.5-89706.29" - switch \initial - attribute \src "issuer_ls180.v:89706.9-89706.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0] - end - attribute \src "issuer_ls180.v:89724.3-89742.6" - process $proc$issuer_ls180.v:89724$3761 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0] - attribute \src "issuer_ls180.v:89725.5-89725.29" - switch \initial - attribute \src "issuer_ls180.v:89725.9-89725.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub19_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0] - end - attribute \src "issuer_ls180.v:89743.3-89761.6" - process $proc$issuer_ls180.v:89743$3762 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:89744.5-89744.29" - switch \initial - attribute \src "issuer_ls180.v:89744.9-89744.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0] - end - attribute \src "issuer_ls180.v:89762.3-89780.6" - process $proc$issuer_ls180.v:89762$3763 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] - attribute \src "issuer_ls180.v:89763.5-89763.29" - switch \initial - attribute \src "issuer_ls180.v:89763.9-89763.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01010 - case - assign $1\dec31_dec_sub19_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] - end - attribute \src "issuer_ls180.v:89781.3-89799.6" - process $proc$issuer_ls180.v:89781$3764 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "issuer_ls180.v:89782.5-89782.29" - switch \initial - attribute \src "issuer_ls180.v:89782.9-89782.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'100 - case - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:89800.3-89818.6" - process $proc$issuer_ls180.v:89800$3765 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "issuer_ls180.v:89801.5-89801.29" - switch \initial - attribute \src "issuer_ls180.v:89801.9-89801.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 - case - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:89819.3-89837.6" - process $proc$issuer_ls180.v:89819$3766 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "issuer_ls180.v:89820.5-89820.29" - switch \initial - attribute \src "issuer_ls180.v:89820.9-89820.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0] - end - attribute \src "issuer_ls180.v:89838.3-89856.6" - process $proc$issuer_ls180.v:89838$3767 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_out_sel[1:0] $1\dec31_dec_sub19_out_sel[1:0] - attribute \src "issuer_ls180.v:89839.5-89839.29" - switch \initial - attribute \src "issuer_ls180.v:89839.9-89839.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_out_sel[1:0] 2'11 - case - assign $1\dec31_dec_sub19_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[1:0] - end - attribute \src "issuer_ls180.v:89857.3-89875.6" - process $proc$issuer_ls180.v:89857$3768 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "issuer_ls180.v:89858.5-89858.29" - switch \initial - attribute \src "issuer_ls180.v:89858.9-89858.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_cr_in[2:0] 3'110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] - end - attribute \src "issuer_ls180.v:89876.3-89894.6" - process $proc$issuer_ls180.v:89876$3769 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "issuer_ls180.v:89877.5-89877.29" - switch \initial - attribute \src "issuer_ls180.v:89877.9-89877.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:89900.1-90759.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub20" -attribute \generator "nMigen" -module \dec31_dec_sub20 - attribute \src "issuer_ls180.v:90283.3-90307.6" - wire width 8 $0\dec31_dec_sub20_asmcode[7:0] - attribute \src "issuer_ls180.v:90383.3-90407.6" - wire $0\dec31_dec_sub20_br[0:0] - attribute \src "issuer_ls180.v:90708.3-90732.6" - wire width 3 $0\dec31_dec_sub20_cr_in[2:0] - attribute \src "issuer_ls180.v:90733.3-90757.6" - wire width 3 $0\dec31_dec_sub20_cr_out[2:0] - attribute \src "issuer_ls180.v:90258.3-90282.6" - wire width 2 $0\dec31_dec_sub20_cry_in[1:0] - attribute \src "issuer_ls180.v:90358.3-90382.6" - wire $0\dec31_dec_sub20_cry_out[0:0] - attribute \src "issuer_ls180.v:90583.3-90607.6" - wire width 5 $0\dec31_dec_sub20_form[4:0] - attribute \src "issuer_ls180.v:90158.3-90182.6" - wire width 12 $0\dec31_dec_sub20_function_unit[11:0] - attribute \src "issuer_ls180.v:90608.3-90632.6" - wire width 3 $0\dec31_dec_sub20_in1_sel[2:0] - attribute \src "issuer_ls180.v:90633.3-90657.6" - wire width 4 $0\dec31_dec_sub20_in2_sel[3:0] - attribute \src "issuer_ls180.v:90658.3-90682.6" - wire width 2 $0\dec31_dec_sub20_in3_sel[1:0] - attribute \src "issuer_ls180.v:90433.3-90457.6" - wire width 7 $0\dec31_dec_sub20_internal_op[6:0] - attribute \src "issuer_ls180.v:90308.3-90332.6" - wire $0\dec31_dec_sub20_inv_a[0:0] - attribute \src "issuer_ls180.v:90333.3-90357.6" - wire $0\dec31_dec_sub20_inv_out[0:0] - attribute \src "issuer_ls180.v:90483.3-90507.6" - wire $0\dec31_dec_sub20_is_32b[0:0] - attribute \src "issuer_ls180.v:90183.3-90207.6" - wire width 4 $0\dec31_dec_sub20_ldst_len[3:0] - attribute \src "issuer_ls180.v:90533.3-90557.6" - wire $0\dec31_dec_sub20_lk[0:0] - attribute \src "issuer_ls180.v:90683.3-90707.6" - wire width 2 $0\dec31_dec_sub20_out_sel[1:0] - attribute \src "issuer_ls180.v:90233.3-90257.6" - wire width 2 $0\dec31_dec_sub20_rc_sel[1:0] - attribute \src "issuer_ls180.v:90458.3-90482.6" - wire $0\dec31_dec_sub20_rsrv[0:0] - attribute \src "issuer_ls180.v:90558.3-90582.6" - wire $0\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:90508.3-90532.6" - wire $0\dec31_dec_sub20_sgn[0:0] - attribute \src "issuer_ls180.v:90408.3-90432.6" - wire $0\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "issuer_ls180.v:90208.3-90232.6" - wire width 2 $0\dec31_dec_sub20_upd[1:0] - attribute \src "issuer_ls180.v:89901.7-89901.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:90283.3-90307.6" - wire width 8 $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "issuer_ls180.v:90383.3-90407.6" - wire $1\dec31_dec_sub20_br[0:0] - attribute \src "issuer_ls180.v:90708.3-90732.6" - wire width 3 $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "issuer_ls180.v:90733.3-90757.6" - wire width 3 $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "issuer_ls180.v:90258.3-90282.6" - wire width 2 $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "issuer_ls180.v:90358.3-90382.6" - wire $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "issuer_ls180.v:90583.3-90607.6" - wire width 5 $1\dec31_dec_sub20_form[4:0] - attribute \src "issuer_ls180.v:90158.3-90182.6" - wire width 12 $1\dec31_dec_sub20_function_unit[11:0] - attribute \src "issuer_ls180.v:90608.3-90632.6" - wire width 3 $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "issuer_ls180.v:90633.3-90657.6" - wire width 4 $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "issuer_ls180.v:90658.3-90682.6" - wire width 2 $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "issuer_ls180.v:90433.3-90457.6" - wire width 7 $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "issuer_ls180.v:90308.3-90332.6" - wire $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "issuer_ls180.v:90333.3-90357.6" - wire $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "issuer_ls180.v:90483.3-90507.6" - wire $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "issuer_ls180.v:90183.3-90207.6" - wire width 4 $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "issuer_ls180.v:90533.3-90557.6" - wire $1\dec31_dec_sub20_lk[0:0] - attribute \src "issuer_ls180.v:90683.3-90707.6" - wire width 2 $1\dec31_dec_sub20_out_sel[1:0] - attribute \src "issuer_ls180.v:90233.3-90257.6" - wire width 2 $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "issuer_ls180.v:90458.3-90482.6" - wire $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "issuer_ls180.v:90558.3-90582.6" - wire $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:90508.3-90532.6" - wire $1\dec31_dec_sub20_sgn[0:0] - attribute \src "issuer_ls180.v:90408.3-90432.6" - wire $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "issuer_ls180.v:90208.3-90232.6" - wire width 2 $1\dec31_dec_sub20_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub20_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub20_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub20_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub20_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub20_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub20_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub20_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub20_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub20_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub20_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub20_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub20_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub20_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub20_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub20_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub20_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub20_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub20_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub20_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub20_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub20_upd - attribute \src "issuer_ls180.v:89901.7-89901.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:89901.7-89901.20" - process $proc$issuer_ls180.v:89901$3795 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:90158.3-90182.6" - process $proc$issuer_ls180.v:90158$3771 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_function_unit[11:0] $1\dec31_dec_sub20_function_unit[11:0] - attribute \src "issuer_ls180.v:90159.5-90159.29" - switch \initial - attribute \src "issuer_ls180.v:90159.9-90159.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 - case - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[11:0] - end - attribute \src "issuer_ls180.v:90183.3-90207.6" - process $proc$issuer_ls180.v:90183$3772 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "issuer_ls180.v:90184.5-90184.29" - switch \initial - attribute \src "issuer_ls180.v:90184.9-90184.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 - case - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:90208.3-90232.6" - process $proc$issuer_ls180.v:90208$3773 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] - attribute \src "issuer_ls180.v:90209.5-90209.29" - switch \initial - attribute \src "issuer_ls180.v:90209.9-90209.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] - end - attribute \src "issuer_ls180.v:90233.3-90257.6" - process $proc$issuer_ls180.v:90233$3774 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "issuer_ls180.v:90234.5-90234.29" - switch \initial - attribute \src "issuer_ls180.v:90234.9-90234.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:90258.3-90282.6" - process $proc$issuer_ls180.v:90258$3775 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "issuer_ls180.v:90259.5-90259.29" - switch \initial - attribute \src "issuer_ls180.v:90259.9-90259.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0] - end - attribute \src "issuer_ls180.v:90283.3-90307.6" - process $proc$issuer_ls180.v:90283$3776 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "issuer_ls180.v:90284.5-90284.29" - switch \initial - attribute \src "issuer_ls180.v:90284.9-90284.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01001101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01011001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'10101101 - case - assign $1\dec31_dec_sub20_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0] - end - attribute \src "issuer_ls180.v:90308.3-90332.6" - process $proc$issuer_ls180.v:90308$3777 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "issuer_ls180.v:90309.5-90309.29" - switch \initial - attribute \src "issuer_ls180.v:90309.9-90309.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0] - end - attribute \src "issuer_ls180.v:90333.3-90357.6" - process $proc$issuer_ls180.v:90333$3778 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "issuer_ls180.v:90334.5-90334.29" - switch \initial - attribute \src "issuer_ls180.v:90334.9-90334.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0] - end - attribute \src "issuer_ls180.v:90358.3-90382.6" - process $proc$issuer_ls180.v:90358$3779 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "issuer_ls180.v:90359.5-90359.29" - switch \initial - attribute \src "issuer_ls180.v:90359.9-90359.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0] - end - attribute \src "issuer_ls180.v:90383.3-90407.6" - process $proc$issuer_ls180.v:90383$3780 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0] - attribute \src "issuer_ls180.v:90384.5-90384.29" - switch \initial - attribute \src "issuer_ls180.v:90384.9-90384.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'1 - case - assign $1\dec31_dec_sub20_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0] - end - attribute \src "issuer_ls180.v:90408.3-90432.6" - process $proc$issuer_ls180.v:90408$3781 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "issuer_ls180.v:90409.5-90409.29" - switch \initial - attribute \src "issuer_ls180.v:90409.9-90409.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:90433.3-90457.6" - process $proc$issuer_ls180.v:90433$3782 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "issuer_ls180.v:90434.5-90434.29" - switch \initial - attribute \src "issuer_ls180.v:90434.9-90434.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100110 - case - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] - end - attribute \src "issuer_ls180.v:90458.3-90482.6" - process $proc$issuer_ls180.v:90458$3783 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "issuer_ls180.v:90459.5-90459.29" - switch \initial - attribute \src "issuer_ls180.v:90459.9-90459.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0] - end - attribute \src "issuer_ls180.v:90483.3-90507.6" - process $proc$issuer_ls180.v:90483$3784 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "issuer_ls180.v:90484.5-90484.29" - switch \initial - attribute \src "issuer_ls180.v:90484.9-90484.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] - end - attribute \src "issuer_ls180.v:90508.3-90532.6" - process $proc$issuer_ls180.v:90508$3785 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] - attribute \src "issuer_ls180.v:90509.5-90509.29" - switch \initial - attribute \src "issuer_ls180.v:90509.9-90509.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] - end - attribute \src "issuer_ls180.v:90533.3-90557.6" - process $proc$issuer_ls180.v:90533$3786 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] - attribute \src "issuer_ls180.v:90534.5-90534.29" - switch \initial - attribute \src "issuer_ls180.v:90534.9-90534.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] - end - attribute \src "issuer_ls180.v:90558.3-90582.6" - process $proc$issuer_ls180.v:90558$3787 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:90559.5-90559.29" - switch \initial - attribute \src "issuer_ls180.v:90559.9-90559.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - case - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] - end - attribute \src "issuer_ls180.v:90583.3-90607.6" - process $proc$issuer_ls180.v:90583$3788 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] - attribute \src "issuer_ls180.v:90584.5-90584.29" - switch \initial - attribute \src "issuer_ls180.v:90584.9-90584.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub20_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] - end - attribute \src "issuer_ls180.v:90608.3-90632.6" - process $proc$issuer_ls180.v:90608$3789 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "issuer_ls180.v:90609.5-90609.29" - switch \initial - attribute \src "issuer_ls180.v:90609.9-90609.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - case - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:90633.3-90657.6" - process $proc$issuer_ls180.v:90633$3790 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "issuer_ls180.v:90634.5-90634.29" - switch \initial - attribute \src "issuer_ls180.v:90634.9-90634.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:90658.3-90682.6" - process $proc$issuer_ls180.v:90658$3791 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "issuer_ls180.v:90659.5-90659.29" - switch \initial - attribute \src "issuer_ls180.v:90659.9-90659.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] - end - attribute \src "issuer_ls180.v:90683.3-90707.6" - process $proc$issuer_ls180.v:90683$3792 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_out_sel[1:0] $1\dec31_dec_sub20_out_sel[1:0] - attribute \src "issuer_ls180.v:90684.5-90684.29" - switch \initial - attribute \src "issuer_ls180.v:90684.9-90684.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub20_out_sel $0\dec31_dec_sub20_out_sel[1:0] - end - attribute \src "issuer_ls180.v:90708.3-90732.6" - process $proc$issuer_ls180.v:90708$3793 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "issuer_ls180.v:90709.5-90709.29" - switch \initial - attribute \src "issuer_ls180.v:90709.9-90709.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0] - end - attribute \src "issuer_ls180.v:90733.3-90757.6" - process $proc$issuer_ls180.v:90733$3794 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "issuer_ls180.v:90734.5-90734.29" - switch \initial - attribute \src "issuer_ls180.v:90734.9-90734.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:90763.1-92180.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub21" -attribute \generator "nMigen" -module \dec31_dec_sub21 - attribute \src "issuer_ls180.v:91805.3-91835.6" - wire width 8 $0\dec31_dec_sub21_asmcode[7:0] - attribute \src "issuer_ls180.v:91413.3-91461.6" - wire $0\dec31_dec_sub21_br[0:0] - attribute \src "issuer_ls180.v:92081.3-92129.6" - wire width 3 $0\dec31_dec_sub21_cr_in[2:0] - attribute \src "issuer_ls180.v:92130.3-92178.6" - wire width 3 $0\dec31_dec_sub21_cr_out[2:0] - attribute \src "issuer_ls180.v:91217.3-91265.6" - wire width 2 $0\dec31_dec_sub21_cry_in[1:0] - attribute \src "issuer_ls180.v:91364.3-91412.6" - wire $0\dec31_dec_sub21_cry_out[0:0] - attribute \src "issuer_ls180.v:91836.3-91884.6" - wire width 5 $0\dec31_dec_sub21_form[4:0] - attribute \src "issuer_ls180.v:91021.3-91069.6" - wire width 12 $0\dec31_dec_sub21_function_unit[11:0] - attribute \src "issuer_ls180.v:91885.3-91933.6" - wire width 3 $0\dec31_dec_sub21_in1_sel[2:0] - attribute \src "issuer_ls180.v:91934.3-91982.6" - wire width 4 $0\dec31_dec_sub21_in2_sel[3:0] - attribute \src "issuer_ls180.v:91983.3-92031.6" - wire width 2 $0\dec31_dec_sub21_in3_sel[1:0] - attribute \src "issuer_ls180.v:91560.3-91608.6" - wire width 7 $0\dec31_dec_sub21_internal_op[6:0] - attribute \src "issuer_ls180.v:91266.3-91314.6" - wire $0\dec31_dec_sub21_inv_a[0:0] - attribute \src "issuer_ls180.v:91315.3-91363.6" - wire $0\dec31_dec_sub21_inv_out[0:0] - attribute \src "issuer_ls180.v:91609.3-91657.6" - wire $0\dec31_dec_sub21_is_32b[0:0] - attribute \src "issuer_ls180.v:91070.3-91118.6" - wire width 4 $0\dec31_dec_sub21_ldst_len[3:0] - attribute \src "issuer_ls180.v:91707.3-91755.6" - wire $0\dec31_dec_sub21_lk[0:0] - attribute \src "issuer_ls180.v:92032.3-92080.6" - wire width 2 $0\dec31_dec_sub21_out_sel[1:0] - attribute \src "issuer_ls180.v:91168.3-91216.6" - wire width 2 $0\dec31_dec_sub21_rc_sel[1:0] - attribute \src "issuer_ls180.v:91511.3-91559.6" - wire $0\dec31_dec_sub21_rsrv[0:0] - attribute \src "issuer_ls180.v:91756.3-91804.6" - wire $0\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:91658.3-91706.6" - wire $0\dec31_dec_sub21_sgn[0:0] - attribute \src "issuer_ls180.v:91462.3-91510.6" - wire $0\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "issuer_ls180.v:91119.3-91167.6" - wire width 2 $0\dec31_dec_sub21_upd[1:0] - attribute \src "issuer_ls180.v:90764.7-90764.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:91805.3-91835.6" - wire width 8 $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "issuer_ls180.v:91413.3-91461.6" - wire $1\dec31_dec_sub21_br[0:0] - attribute \src "issuer_ls180.v:92081.3-92129.6" - wire width 3 $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "issuer_ls180.v:92130.3-92178.6" - wire width 3 $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "issuer_ls180.v:91217.3-91265.6" - wire width 2 $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "issuer_ls180.v:91364.3-91412.6" - wire $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "issuer_ls180.v:91836.3-91884.6" - wire width 5 $1\dec31_dec_sub21_form[4:0] - attribute \src "issuer_ls180.v:91021.3-91069.6" - wire width 12 $1\dec31_dec_sub21_function_unit[11:0] - attribute \src "issuer_ls180.v:91885.3-91933.6" - wire width 3 $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "issuer_ls180.v:91934.3-91982.6" - wire width 4 $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "issuer_ls180.v:91983.3-92031.6" - wire width 2 $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "issuer_ls180.v:91560.3-91608.6" - wire width 7 $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "issuer_ls180.v:91266.3-91314.6" - wire $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "issuer_ls180.v:91315.3-91363.6" - wire $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "issuer_ls180.v:91609.3-91657.6" - wire $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "issuer_ls180.v:91070.3-91118.6" - wire width 4 $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "issuer_ls180.v:91707.3-91755.6" - wire $1\dec31_dec_sub21_lk[0:0] - attribute \src "issuer_ls180.v:92032.3-92080.6" - wire width 2 $1\dec31_dec_sub21_out_sel[1:0] - attribute \src "issuer_ls180.v:91168.3-91216.6" - wire width 2 $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "issuer_ls180.v:91511.3-91559.6" - wire $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "issuer_ls180.v:91756.3-91804.6" - wire $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:91658.3-91706.6" - wire $1\dec31_dec_sub21_sgn[0:0] - attribute \src "issuer_ls180.v:91462.3-91510.6" - wire $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "issuer_ls180.v:91119.3-91167.6" - wire width 2 $1\dec31_dec_sub21_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub21_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub21_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub21_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub21_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub21_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub21_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub21_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub21_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub21_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub21_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub21_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub21_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub21_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub21_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub21_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub21_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub21_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub21_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub21_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub21_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub21_upd - attribute \src "issuer_ls180.v:90764.7-90764.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:90764.7-90764.20" - process $proc$issuer_ls180.v:90764$3820 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:91021.3-91069.6" - process $proc$issuer_ls180.v:91021$3796 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_function_unit[11:0] $1\dec31_dec_sub21_function_unit[11:0] - attribute \src "issuer_ls180.v:91022.5-91022.29" - switch \initial - attribute \src "issuer_ls180.v:91022.9-91022.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - case - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[11:0] - end - attribute \src "issuer_ls180.v:91070.3-91118.6" - process $proc$issuer_ls180.v:91070$3797 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "issuer_ls180.v:91071.5-91071.29" - switch \initial - attribute \src "issuer_ls180.v:91071.9-91071.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 - case - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:91119.3-91167.6" - process $proc$issuer_ls180.v:91119$3798 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] - attribute \src "issuer_ls180.v:91120.5-91120.29" - switch \initial - attribute \src "issuer_ls180.v:91120.9-91120.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - case - assign $1\dec31_dec_sub21_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] - end - attribute \src "issuer_ls180.v:91168.3-91216.6" - process $proc$issuer_ls180.v:91168$3799 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "issuer_ls180.v:91169.5-91169.29" - switch \initial - attribute \src "issuer_ls180.v:91169.9-91169.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:91217.3-91265.6" - process $proc$issuer_ls180.v:91217$3800 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "issuer_ls180.v:91218.5-91218.29" - switch \initial - attribute \src "issuer_ls180.v:91218.9-91218.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0] - end - attribute \src "issuer_ls180.v:91266.3-91314.6" - process $proc$issuer_ls180.v:91266$3801 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "issuer_ls180.v:91267.5-91267.29" - switch \initial - attribute \src "issuer_ls180.v:91267.9-91267.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0] - end - attribute \src "issuer_ls180.v:91315.3-91363.6" - process $proc$issuer_ls180.v:91315$3802 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "issuer_ls180.v:91316.5-91316.29" - switch \initial - attribute \src "issuer_ls180.v:91316.9-91316.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0] - end - attribute \src "issuer_ls180.v:91364.3-91412.6" - process $proc$issuer_ls180.v:91364$3803 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "issuer_ls180.v:91365.5-91365.29" - switch \initial - attribute \src "issuer_ls180.v:91365.9-91365.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0] - end - attribute \src "issuer_ls180.v:91413.3-91461.6" - process $proc$issuer_ls180.v:91413$3804 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0] - attribute \src "issuer_ls180.v:91414.5-91414.29" - switch \initial - attribute \src "issuer_ls180.v:91414.9-91414.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - case - assign $1\dec31_dec_sub21_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0] - end - attribute \src "issuer_ls180.v:91462.3-91510.6" - process $proc$issuer_ls180.v:91462$3805 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "issuer_ls180.v:91463.5-91463.29" - switch \initial - attribute \src "issuer_ls180.v:91463.9-91463.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:91511.3-91559.6" - process $proc$issuer_ls180.v:91511$3806 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "issuer_ls180.v:91512.5-91512.29" - switch \initial - attribute \src "issuer_ls180.v:91512.9-91512.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0] - end - attribute \src "issuer_ls180.v:91560.3-91608.6" - process $proc$issuer_ls180.v:91560$3807 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "issuer_ls180.v:91561.5-91561.29" - switch \initial - attribute \src "issuer_ls180.v:91561.9-91561.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 - case - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] - end - attribute \src "issuer_ls180.v:91609.3-91657.6" - process $proc$issuer_ls180.v:91609$3808 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "issuer_ls180.v:91610.5-91610.29" - switch \initial - attribute \src "issuer_ls180.v:91610.9-91610.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0] - end - attribute \src "issuer_ls180.v:91658.3-91706.6" - process $proc$issuer_ls180.v:91658$3809 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] - attribute \src "issuer_ls180.v:91659.5-91659.29" - switch \initial - attribute \src "issuer_ls180.v:91659.9-91659.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] - end - attribute \src "issuer_ls180.v:91707.3-91755.6" - process $proc$issuer_ls180.v:91707$3810 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0] - attribute \src "issuer_ls180.v:91708.5-91708.29" - switch \initial - attribute \src "issuer_ls180.v:91708.9-91708.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0] - end - attribute \src "issuer_ls180.v:91756.3-91804.6" - process $proc$issuer_ls180.v:91756$3811 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:91757.5-91757.29" - switch \initial - attribute \src "issuer_ls180.v:91757.9-91757.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - case - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0] - end - attribute \src "issuer_ls180.v:91805.3-91835.6" - process $proc$issuer_ls180.v:91805$3812 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "issuer_ls180.v:91806.5-91806.29" - switch \initial - attribute \src "issuer_ls180.v:91806.9-91806.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01101000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'10100111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110001 - case - assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0] - end - attribute \src "issuer_ls180.v:91836.3-91884.6" - process $proc$issuer_ls180.v:91836$3813 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] - attribute \src "issuer_ls180.v:91837.5-91837.29" - switch \initial - attribute \src "issuer_ls180.v:91837.9-91837.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub21_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] - end - attribute \src "issuer_ls180.v:91885.3-91933.6" - process $proc$issuer_ls180.v:91885$3814 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "issuer_ls180.v:91886.5-91886.29" - switch \initial - attribute \src "issuer_ls180.v:91886.9-91886.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - case - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:91934.3-91982.6" - process $proc$issuer_ls180.v:91934$3815 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "issuer_ls180.v:91935.5-91935.29" - switch \initial - attribute \src "issuer_ls180.v:91935.9-91935.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:91983.3-92031.6" - process $proc$issuer_ls180.v:91983$3816 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "issuer_ls180.v:91984.5-91984.29" - switch \initial - attribute \src "issuer_ls180.v:91984.9-91984.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0] - end - attribute \src "issuer_ls180.v:92032.3-92080.6" - process $proc$issuer_ls180.v:92032$3817 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_out_sel[1:0] $1\dec31_dec_sub21_out_sel[1:0] - attribute \src "issuer_ls180.v:92033.5-92033.29" - switch \initial - attribute \src "issuer_ls180.v:92033.9-92033.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub21_out_sel $0\dec31_dec_sub21_out_sel[1:0] - end - attribute \src "issuer_ls180.v:92081.3-92129.6" - process $proc$issuer_ls180.v:92081$3818 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "issuer_ls180.v:92082.5-92082.29" - switch \initial - attribute \src "issuer_ls180.v:92082.9-92082.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0] - end - attribute \src "issuer_ls180.v:92130.3-92178.6" - process $proc$issuer_ls180.v:92130$3819 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "issuer_ls180.v:92131.5-92131.29" - switch \initial - attribute \src "issuer_ls180.v:92131.9-92131.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:92184.1-93763.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub22" -attribute \generator "nMigen" -module \dec31_dec_sub22 - attribute \src "issuer_ls180.v:92717.3-92771.6" - wire width 8 $0\dec31_dec_sub22_asmcode[7:0] - attribute \src "issuer_ls180.v:92937.3-92991.6" - wire $0\dec31_dec_sub22_br[0:0] - attribute \src "issuer_ls180.v:93652.3-93706.6" - wire width 3 $0\dec31_dec_sub22_cr_in[2:0] - attribute \src "issuer_ls180.v:93707.3-93761.6" - wire width 3 $0\dec31_dec_sub22_cr_out[2:0] - attribute \src "issuer_ls180.v:92662.3-92716.6" - wire width 2 $0\dec31_dec_sub22_cry_in[1:0] - attribute \src "issuer_ls180.v:92882.3-92936.6" - wire $0\dec31_dec_sub22_cry_out[0:0] - attribute \src "issuer_ls180.v:93377.3-93431.6" - wire width 5 $0\dec31_dec_sub22_form[4:0] - attribute \src "issuer_ls180.v:92442.3-92496.6" - wire width 12 $0\dec31_dec_sub22_function_unit[11:0] - attribute \src "issuer_ls180.v:93432.3-93486.6" - wire width 3 $0\dec31_dec_sub22_in1_sel[2:0] - attribute \src "issuer_ls180.v:93487.3-93541.6" - wire width 4 $0\dec31_dec_sub22_in2_sel[3:0] - attribute \src "issuer_ls180.v:93542.3-93596.6" - wire width 2 $0\dec31_dec_sub22_in3_sel[1:0] - attribute \src "issuer_ls180.v:93047.3-93101.6" - wire width 7 $0\dec31_dec_sub22_internal_op[6:0] - attribute \src "issuer_ls180.v:92772.3-92826.6" - wire $0\dec31_dec_sub22_inv_a[0:0] - attribute \src "issuer_ls180.v:92827.3-92881.6" - wire $0\dec31_dec_sub22_inv_out[0:0] - attribute \src "issuer_ls180.v:93157.3-93211.6" - wire $0\dec31_dec_sub22_is_32b[0:0] - attribute \src "issuer_ls180.v:92497.3-92551.6" - wire width 4 $0\dec31_dec_sub22_ldst_len[3:0] - attribute \src "issuer_ls180.v:93267.3-93321.6" - wire $0\dec31_dec_sub22_lk[0:0] - attribute \src "issuer_ls180.v:93597.3-93651.6" - wire width 2 $0\dec31_dec_sub22_out_sel[1:0] - attribute \src "issuer_ls180.v:92607.3-92661.6" - wire width 2 $0\dec31_dec_sub22_rc_sel[1:0] - attribute \src "issuer_ls180.v:93102.3-93156.6" - wire $0\dec31_dec_sub22_rsrv[0:0] - attribute \src "issuer_ls180.v:93322.3-93376.6" - wire $0\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:93212.3-93266.6" - wire $0\dec31_dec_sub22_sgn[0:0] - attribute \src "issuer_ls180.v:92992.3-93046.6" - wire $0\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "issuer_ls180.v:92552.3-92606.6" - wire width 2 $0\dec31_dec_sub22_upd[1:0] - attribute \src "issuer_ls180.v:92185.7-92185.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:92717.3-92771.6" - wire width 8 $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "issuer_ls180.v:92937.3-92991.6" - wire $1\dec31_dec_sub22_br[0:0] - attribute \src "issuer_ls180.v:93652.3-93706.6" - wire width 3 $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "issuer_ls180.v:93707.3-93761.6" - wire width 3 $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "issuer_ls180.v:92662.3-92716.6" - wire width 2 $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "issuer_ls180.v:92882.3-92936.6" - wire $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "issuer_ls180.v:93377.3-93431.6" - wire width 5 $1\dec31_dec_sub22_form[4:0] - attribute \src "issuer_ls180.v:92442.3-92496.6" - wire width 12 $1\dec31_dec_sub22_function_unit[11:0] - attribute \src "issuer_ls180.v:93432.3-93486.6" - wire width 3 $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "issuer_ls180.v:93487.3-93541.6" - wire width 4 $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "issuer_ls180.v:93542.3-93596.6" - wire width 2 $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "issuer_ls180.v:93047.3-93101.6" - wire width 7 $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "issuer_ls180.v:92772.3-92826.6" - wire $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "issuer_ls180.v:92827.3-92881.6" - wire $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "issuer_ls180.v:93157.3-93211.6" - wire $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "issuer_ls180.v:92497.3-92551.6" - wire width 4 $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "issuer_ls180.v:93267.3-93321.6" - wire $1\dec31_dec_sub22_lk[0:0] - attribute \src "issuer_ls180.v:93597.3-93651.6" - wire width 2 $1\dec31_dec_sub22_out_sel[1:0] - attribute \src "issuer_ls180.v:92607.3-92661.6" - wire width 2 $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "issuer_ls180.v:93102.3-93156.6" - wire $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "issuer_ls180.v:93322.3-93376.6" - wire $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:93212.3-93266.6" - wire $1\dec31_dec_sub22_sgn[0:0] - attribute \src "issuer_ls180.v:92992.3-93046.6" - wire $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "issuer_ls180.v:92552.3-92606.6" - wire width 2 $1\dec31_dec_sub22_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub22_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub22_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub22_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub22_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub22_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub22_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub22_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub22_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub22_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub22_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub22_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub22_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub22_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub22_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub22_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub22_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub22_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub22_upd - attribute \src "issuer_ls180.v:92185.7-92185.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:92185.7-92185.20" - process $proc$issuer_ls180.v:92185$3845 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:92442.3-92496.6" - process $proc$issuer_ls180.v:92442$3821 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_function_unit[11:0] $1\dec31_dec_sub22_function_unit[11:0] - attribute \src "issuer_ls180.v:92443.5-92443.29" - switch \initial - attribute \src "issuer_ls180.v:92443.9-92443.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - case - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[11:0] - end - attribute \src "issuer_ls180.v:92497.3-92551.6" - process $proc$issuer_ls180.v:92497$3822 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "issuer_ls180.v:92498.5-92498.29" - switch \initial - attribute \src "issuer_ls180.v:92498.9-92498.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:92552.3-92606.6" - process $proc$issuer_ls180.v:92552$3823 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] - attribute \src "issuer_ls180.v:92553.5-92553.29" - switch \initial - attribute \src "issuer_ls180.v:92553.9-92553.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] - end - attribute \src "issuer_ls180.v:92607.3-92661.6" - process $proc$issuer_ls180.v:92607$3824 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "issuer_ls180.v:92608.5-92608.29" - switch \initial - attribute \src "issuer_ls180.v:92608.9-92608.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:92662.3-92716.6" - process $proc$issuer_ls180.v:92662$3825 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "issuer_ls180.v:92663.5-92663.29" - switch \initial - attribute \src "issuer_ls180.v:92663.9-92663.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0] - end - attribute \src "issuer_ls180.v:92717.3-92771.6" - process $proc$issuer_ls180.v:92717$3826 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "issuer_ls180.v:92718.5-92718.29" - switch \initial - attribute \src "issuer_ls180.v:92718.9-92718.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'01011101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'01100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'11001001 - case - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0] - end - attribute \src "issuer_ls180.v:92772.3-92826.6" - process $proc$issuer_ls180.v:92772$3827 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "issuer_ls180.v:92773.5-92773.29" - switch \initial - attribute \src "issuer_ls180.v:92773.9-92773.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0] - end - attribute \src "issuer_ls180.v:92827.3-92881.6" - process $proc$issuer_ls180.v:92827$3828 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "issuer_ls180.v:92828.5-92828.29" - switch \initial - attribute \src "issuer_ls180.v:92828.9-92828.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0] - end - attribute \src "issuer_ls180.v:92882.3-92936.6" - process $proc$issuer_ls180.v:92882$3829 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "issuer_ls180.v:92883.5-92883.29" - switch \initial - attribute \src "issuer_ls180.v:92883.9-92883.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0] - end - attribute \src "issuer_ls180.v:92937.3-92991.6" - process $proc$issuer_ls180.v:92937$3830 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0] - attribute \src "issuer_ls180.v:92938.5-92938.29" - switch \initial - attribute \src "issuer_ls180.v:92938.9-92938.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - case - assign $1\dec31_dec_sub22_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0] - end - attribute \src "issuer_ls180.v:92992.3-93046.6" - process $proc$issuer_ls180.v:92992$3831 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "issuer_ls180.v:92993.5-92993.29" - switch \initial - attribute \src "issuer_ls180.v:92993.9-92993.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:93047.3-93101.6" - process $proc$issuer_ls180.v:93047$3832 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "issuer_ls180.v:93048.5-93048.29" - switch \initial - attribute \src "issuer_ls180.v:93048.9-93048.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0011100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 - case - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] - end - attribute \src "issuer_ls180.v:93102.3-93156.6" - process $proc$issuer_ls180.v:93102$3833 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "issuer_ls180.v:93103.5-93103.29" - switch \initial - attribute \src "issuer_ls180.v:93103.9-93103.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0] - end - attribute \src "issuer_ls180.v:93157.3-93211.6" - process $proc$issuer_ls180.v:93157$3834 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "issuer_ls180.v:93158.5-93158.29" - switch \initial - attribute \src "issuer_ls180.v:93158.9-93158.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] - end - attribute \src "issuer_ls180.v:93212.3-93266.6" - process $proc$issuer_ls180.v:93212$3835 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0] - attribute \src "issuer_ls180.v:93213.5-93213.29" - switch \initial - attribute \src "issuer_ls180.v:93213.9-93213.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0] - end - attribute \src "issuer_ls180.v:93267.3-93321.6" - process $proc$issuer_ls180.v:93267$3836 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0] - attribute \src "issuer_ls180.v:93268.5-93268.29" - switch \initial - attribute \src "issuer_ls180.v:93268.9-93268.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0] - end - attribute \src "issuer_ls180.v:93322.3-93376.6" - process $proc$issuer_ls180.v:93322$3837 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:93323.5-93323.29" - switch \initial - attribute \src "issuer_ls180.v:93323.9-93323.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - case - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0] - end - attribute \src "issuer_ls180.v:93377.3-93431.6" - process $proc$issuer_ls180.v:93377$3838 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] - attribute \src "issuer_ls180.v:93378.5-93378.29" - switch \initial - attribute \src "issuer_ls180.v:93378.9-93378.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub22_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] - end - attribute \src "issuer_ls180.v:93432.3-93486.6" - process $proc$issuer_ls180.v:93432$3839 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "issuer_ls180.v:93433.5-93433.29" - switch \initial - attribute \src "issuer_ls180.v:93433.9-93433.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - case - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:93487.3-93541.6" - process $proc$issuer_ls180.v:93487$3840 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "issuer_ls180.v:93488.5-93488.29" - switch \initial - attribute \src "issuer_ls180.v:93488.9-93488.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - case - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:93542.3-93596.6" - process $proc$issuer_ls180.v:93542$3841 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "issuer_ls180.v:93543.5-93543.29" - switch \initial - attribute \src "issuer_ls180.v:93543.9-93543.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0] - end - attribute \src "issuer_ls180.v:93597.3-93651.6" - process $proc$issuer_ls180.v:93597$3842 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_out_sel[1:0] $1\dec31_dec_sub22_out_sel[1:0] - attribute \src "issuer_ls180.v:93598.5-93598.29" - switch \initial - attribute \src "issuer_ls180.v:93598.9-93598.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub22_out_sel $0\dec31_dec_sub22_out_sel[1:0] - end - attribute \src "issuer_ls180.v:93652.3-93706.6" - process $proc$issuer_ls180.v:93652$3843 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "issuer_ls180.v:93653.5-93653.29" - switch \initial - attribute \src "issuer_ls180.v:93653.9-93653.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0] - end - attribute \src "issuer_ls180.v:93707.3-93761.6" - process $proc$issuer_ls180.v:93707$3844 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "issuer_ls180.v:93708.5-93708.29" - switch \initial - attribute \src "issuer_ls180.v:93708.9-93708.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:93767.1-95202.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub23" -attribute \generator "nMigen" -module \dec31_dec_sub23 - attribute \src "issuer_ls180.v:94270.3-94318.6" - wire width 8 $0\dec31_dec_sub23_asmcode[7:0] - attribute \src "issuer_ls180.v:94466.3-94514.6" - wire $0\dec31_dec_sub23_br[0:0] - attribute \src "issuer_ls180.v:95103.3-95151.6" - wire width 3 $0\dec31_dec_sub23_cr_in[2:0] - attribute \src "issuer_ls180.v:95152.3-95200.6" - wire width 3 $0\dec31_dec_sub23_cr_out[2:0] - attribute \src "issuer_ls180.v:94221.3-94269.6" - wire width 2 $0\dec31_dec_sub23_cry_in[1:0] - attribute \src "issuer_ls180.v:94417.3-94465.6" - wire $0\dec31_dec_sub23_cry_out[0:0] - attribute \src "issuer_ls180.v:94858.3-94906.6" - wire width 5 $0\dec31_dec_sub23_form[4:0] - attribute \src "issuer_ls180.v:94025.3-94073.6" - wire width 12 $0\dec31_dec_sub23_function_unit[11:0] - attribute \src "issuer_ls180.v:94907.3-94955.6" - wire width 3 $0\dec31_dec_sub23_in1_sel[2:0] - attribute \src "issuer_ls180.v:94956.3-95004.6" - wire width 4 $0\dec31_dec_sub23_in2_sel[3:0] - attribute \src "issuer_ls180.v:95005.3-95053.6" - wire width 2 $0\dec31_dec_sub23_in3_sel[1:0] - attribute \src "issuer_ls180.v:94564.3-94612.6" - wire width 7 $0\dec31_dec_sub23_internal_op[6:0] - attribute \src "issuer_ls180.v:94319.3-94367.6" - wire $0\dec31_dec_sub23_inv_a[0:0] - attribute \src "issuer_ls180.v:94368.3-94416.6" - wire $0\dec31_dec_sub23_inv_out[0:0] - attribute \src "issuer_ls180.v:94662.3-94710.6" - wire $0\dec31_dec_sub23_is_32b[0:0] - attribute \src "issuer_ls180.v:94074.3-94122.6" - wire width 4 $0\dec31_dec_sub23_ldst_len[3:0] - attribute \src "issuer_ls180.v:94760.3-94808.6" - wire $0\dec31_dec_sub23_lk[0:0] - attribute \src "issuer_ls180.v:95054.3-95102.6" - wire width 2 $0\dec31_dec_sub23_out_sel[1:0] - attribute \src "issuer_ls180.v:94172.3-94220.6" - wire width 2 $0\dec31_dec_sub23_rc_sel[1:0] - attribute \src "issuer_ls180.v:94613.3-94661.6" - wire $0\dec31_dec_sub23_rsrv[0:0] - attribute \src "issuer_ls180.v:94809.3-94857.6" - wire $0\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:94711.3-94759.6" - wire $0\dec31_dec_sub23_sgn[0:0] - attribute \src "issuer_ls180.v:94515.3-94563.6" - wire $0\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "issuer_ls180.v:94123.3-94171.6" - wire width 2 $0\dec31_dec_sub23_upd[1:0] - attribute \src "issuer_ls180.v:93768.7-93768.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:94270.3-94318.6" - wire width 8 $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "issuer_ls180.v:94466.3-94514.6" - wire $1\dec31_dec_sub23_br[0:0] - attribute \src "issuer_ls180.v:95103.3-95151.6" - wire width 3 $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "issuer_ls180.v:95152.3-95200.6" - wire width 3 $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "issuer_ls180.v:94221.3-94269.6" - wire width 2 $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "issuer_ls180.v:94417.3-94465.6" - wire $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "issuer_ls180.v:94858.3-94906.6" - wire width 5 $1\dec31_dec_sub23_form[4:0] - attribute \src "issuer_ls180.v:94025.3-94073.6" - wire width 12 $1\dec31_dec_sub23_function_unit[11:0] - attribute \src "issuer_ls180.v:94907.3-94955.6" - wire width 3 $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "issuer_ls180.v:94956.3-95004.6" - wire width 4 $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "issuer_ls180.v:95005.3-95053.6" - wire width 2 $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "issuer_ls180.v:94564.3-94612.6" - wire width 7 $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "issuer_ls180.v:94319.3-94367.6" - wire $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "issuer_ls180.v:94368.3-94416.6" - wire $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "issuer_ls180.v:94662.3-94710.6" - wire $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "issuer_ls180.v:94074.3-94122.6" - wire width 4 $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "issuer_ls180.v:94760.3-94808.6" - wire $1\dec31_dec_sub23_lk[0:0] - attribute \src "issuer_ls180.v:95054.3-95102.6" - wire width 2 $1\dec31_dec_sub23_out_sel[1:0] - attribute \src "issuer_ls180.v:94172.3-94220.6" - wire width 2 $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "issuer_ls180.v:94613.3-94661.6" - wire $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "issuer_ls180.v:94809.3-94857.6" - wire $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:94711.3-94759.6" - wire $1\dec31_dec_sub23_sgn[0:0] - attribute \src "issuer_ls180.v:94515.3-94563.6" - wire $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "issuer_ls180.v:94123.3-94171.6" - wire width 2 $1\dec31_dec_sub23_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub23_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub23_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub23_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub23_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub23_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub23_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub23_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub23_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub23_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub23_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub23_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub23_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub23_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub23_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub23_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub23_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub23_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub23_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub23_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub23_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub23_upd - attribute \src "issuer_ls180.v:93768.7-93768.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:93768.7-93768.20" - process $proc$issuer_ls180.v:93768$3870 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:94025.3-94073.6" - process $proc$issuer_ls180.v:94025$3846 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_function_unit[11:0] $1\dec31_dec_sub23_function_unit[11:0] - attribute \src "issuer_ls180.v:94026.5-94026.29" - switch \initial - attribute \src "issuer_ls180.v:94026.9-94026.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - case - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[11:0] - end - attribute \src "issuer_ls180.v:94074.3-94122.6" - process $proc$issuer_ls180.v:94074$3847 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "issuer_ls180.v:94075.5-94075.29" - switch \initial - attribute \src "issuer_ls180.v:94075.9-94075.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 - case - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:94123.3-94171.6" - process $proc$issuer_ls180.v:94123$3848 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] - attribute \src "issuer_ls180.v:94124.5-94124.29" - switch \initial - attribute \src "issuer_ls180.v:94124.9-94124.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] - end - attribute \src "issuer_ls180.v:94172.3-94220.6" - process $proc$issuer_ls180.v:94172$3849 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "issuer_ls180.v:94173.5-94173.29" - switch \initial - attribute \src "issuer_ls180.v:94173.9-94173.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:94221.3-94269.6" - process $proc$issuer_ls180.v:94221$3850 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "issuer_ls180.v:94222.5-94222.29" - switch \initial - attribute \src "issuer_ls180.v:94222.9-94222.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0] - end - attribute \src "issuer_ls180.v:94270.3-94318.6" - process $proc$issuer_ls180.v:94270$3851 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "issuer_ls180.v:94271.5-94271.29" - switch \initial - attribute \src "issuer_ls180.v:94271.9-94271.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111101 - case - assign $1\dec31_dec_sub23_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0] - end - attribute \src "issuer_ls180.v:94319.3-94367.6" - process $proc$issuer_ls180.v:94319$3852 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "issuer_ls180.v:94320.5-94320.29" - switch \initial - attribute \src "issuer_ls180.v:94320.9-94320.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0] - end - attribute \src "issuer_ls180.v:94368.3-94416.6" - process $proc$issuer_ls180.v:94368$3853 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "issuer_ls180.v:94369.5-94369.29" - switch \initial - attribute \src "issuer_ls180.v:94369.9-94369.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0] - end - attribute \src "issuer_ls180.v:94417.3-94465.6" - process $proc$issuer_ls180.v:94417$3854 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "issuer_ls180.v:94418.5-94418.29" - switch \initial - attribute \src "issuer_ls180.v:94418.9-94418.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0] - end - attribute \src "issuer_ls180.v:94466.3-94514.6" - process $proc$issuer_ls180.v:94466$3855 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0] - attribute \src "issuer_ls180.v:94467.5-94467.29" - switch \initial - attribute \src "issuer_ls180.v:94467.9-94467.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - case - assign $1\dec31_dec_sub23_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0] - end - attribute \src "issuer_ls180.v:94515.3-94563.6" - process $proc$issuer_ls180.v:94515$3856 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "issuer_ls180.v:94516.5-94516.29" - switch \initial - attribute \src "issuer_ls180.v:94516.9-94516.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:94564.3-94612.6" - process $proc$issuer_ls180.v:94564$3857 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "issuer_ls180.v:94565.5-94565.29" - switch \initial - attribute \src "issuer_ls180.v:94565.9-94565.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 - case - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] - end - attribute \src "issuer_ls180.v:94613.3-94661.6" - process $proc$issuer_ls180.v:94613$3858 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "issuer_ls180.v:94614.5-94614.29" - switch \initial - attribute \src "issuer_ls180.v:94614.9-94614.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0] - end - attribute \src "issuer_ls180.v:94662.3-94710.6" - process $proc$issuer_ls180.v:94662$3859 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "issuer_ls180.v:94663.5-94663.29" - switch \initial - attribute \src "issuer_ls180.v:94663.9-94663.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] - end - attribute \src "issuer_ls180.v:94711.3-94759.6" - process $proc$issuer_ls180.v:94711$3860 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0] - attribute \src "issuer_ls180.v:94712.5-94712.29" - switch \initial - attribute \src "issuer_ls180.v:94712.9-94712.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0] - end - attribute \src "issuer_ls180.v:94760.3-94808.6" - process $proc$issuer_ls180.v:94760$3861 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0] - attribute \src "issuer_ls180.v:94761.5-94761.29" - switch \initial - attribute \src "issuer_ls180.v:94761.9-94761.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0] - end - attribute \src "issuer_ls180.v:94809.3-94857.6" - process $proc$issuer_ls180.v:94809$3862 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:94810.5-94810.29" - switch \initial - attribute \src "issuer_ls180.v:94810.9-94810.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - case - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0] - end - attribute \src "issuer_ls180.v:94858.3-94906.6" - process $proc$issuer_ls180.v:94858$3863 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] - attribute \src "issuer_ls180.v:94859.5-94859.29" - switch \initial - attribute \src "issuer_ls180.v:94859.9-94859.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub23_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] - end - attribute \src "issuer_ls180.v:94907.3-94955.6" - process $proc$issuer_ls180.v:94907$3864 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "issuer_ls180.v:94908.5-94908.29" - switch \initial - attribute \src "issuer_ls180.v:94908.9-94908.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - case - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:94956.3-95004.6" - process $proc$issuer_ls180.v:94956$3865 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "issuer_ls180.v:94957.5-94957.29" - switch \initial - attribute \src "issuer_ls180.v:94957.9-94957.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:95005.3-95053.6" - process $proc$issuer_ls180.v:95005$3866 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "issuer_ls180.v:95006.5-95006.29" - switch \initial - attribute \src "issuer_ls180.v:95006.9-95006.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0] - end - attribute \src "issuer_ls180.v:95054.3-95102.6" - process $proc$issuer_ls180.v:95054$3867 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_out_sel[1:0] $1\dec31_dec_sub23_out_sel[1:0] - attribute \src "issuer_ls180.v:95055.5-95055.29" - switch \initial - attribute \src "issuer_ls180.v:95055.9-95055.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub23_out_sel $0\dec31_dec_sub23_out_sel[1:0] - end - attribute \src "issuer_ls180.v:95103.3-95151.6" - process $proc$issuer_ls180.v:95103$3868 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "issuer_ls180.v:95104.5-95104.29" - switch \initial - attribute \src "issuer_ls180.v:95104.9-95104.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0] - end - attribute \src "issuer_ls180.v:95152.3-95200.6" - process $proc$issuer_ls180.v:95152$3869 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "issuer_ls180.v:95153.5-95153.29" - switch \initial - attribute \src "issuer_ls180.v:95153.9-95153.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:95206.1-95921.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub24" -attribute \generator "nMigen" -module \dec31_dec_sub24 - attribute \src "issuer_ls180.v:95559.3-95577.6" - wire width 8 $0\dec31_dec_sub24_asmcode[7:0] - attribute \src "issuer_ls180.v:95635.3-95653.6" - wire $0\dec31_dec_sub24_br[0:0] - attribute \src "issuer_ls180.v:95882.3-95900.6" - wire width 3 $0\dec31_dec_sub24_cr_in[2:0] - attribute \src "issuer_ls180.v:95901.3-95919.6" - wire width 3 $0\dec31_dec_sub24_cr_out[2:0] - attribute \src "issuer_ls180.v:95540.3-95558.6" - wire width 2 $0\dec31_dec_sub24_cry_in[1:0] - attribute \src "issuer_ls180.v:95616.3-95634.6" - wire $0\dec31_dec_sub24_cry_out[0:0] - attribute \src "issuer_ls180.v:95787.3-95805.6" - wire width 5 $0\dec31_dec_sub24_form[4:0] - attribute \src "issuer_ls180.v:95464.3-95482.6" - wire width 12 $0\dec31_dec_sub24_function_unit[11:0] - attribute \src "issuer_ls180.v:95806.3-95824.6" - wire width 3 $0\dec31_dec_sub24_in1_sel[2:0] - attribute \src "issuer_ls180.v:95825.3-95843.6" - wire width 4 $0\dec31_dec_sub24_in2_sel[3:0] - attribute \src "issuer_ls180.v:95844.3-95862.6" - wire width 2 $0\dec31_dec_sub24_in3_sel[1:0] - attribute \src "issuer_ls180.v:95673.3-95691.6" - wire width 7 $0\dec31_dec_sub24_internal_op[6:0] - attribute \src "issuer_ls180.v:95578.3-95596.6" - wire $0\dec31_dec_sub24_inv_a[0:0] - attribute \src "issuer_ls180.v:95597.3-95615.6" - wire $0\dec31_dec_sub24_inv_out[0:0] - attribute \src "issuer_ls180.v:95711.3-95729.6" - wire $0\dec31_dec_sub24_is_32b[0:0] - attribute \src "issuer_ls180.v:95483.3-95501.6" - wire width 4 $0\dec31_dec_sub24_ldst_len[3:0] - attribute \src "issuer_ls180.v:95749.3-95767.6" - wire $0\dec31_dec_sub24_lk[0:0] - attribute \src "issuer_ls180.v:95863.3-95881.6" - wire width 2 $0\dec31_dec_sub24_out_sel[1:0] - attribute \src "issuer_ls180.v:95521.3-95539.6" - wire width 2 $0\dec31_dec_sub24_rc_sel[1:0] - attribute \src "issuer_ls180.v:95692.3-95710.6" - wire $0\dec31_dec_sub24_rsrv[0:0] - attribute \src "issuer_ls180.v:95768.3-95786.6" - wire $0\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:95730.3-95748.6" - wire $0\dec31_dec_sub24_sgn[0:0] - attribute \src "issuer_ls180.v:95654.3-95672.6" - wire $0\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "issuer_ls180.v:95502.3-95520.6" - wire width 2 $0\dec31_dec_sub24_upd[1:0] - attribute \src "issuer_ls180.v:95207.7-95207.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:95559.3-95577.6" - wire width 8 $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "issuer_ls180.v:95635.3-95653.6" - wire $1\dec31_dec_sub24_br[0:0] - attribute \src "issuer_ls180.v:95882.3-95900.6" - wire width 3 $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "issuer_ls180.v:95901.3-95919.6" - wire width 3 $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "issuer_ls180.v:95540.3-95558.6" - wire width 2 $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "issuer_ls180.v:95616.3-95634.6" - wire $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "issuer_ls180.v:95787.3-95805.6" - wire width 5 $1\dec31_dec_sub24_form[4:0] - attribute \src "issuer_ls180.v:95464.3-95482.6" - wire width 12 $1\dec31_dec_sub24_function_unit[11:0] - attribute \src "issuer_ls180.v:95806.3-95824.6" - wire width 3 $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "issuer_ls180.v:95825.3-95843.6" - wire width 4 $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "issuer_ls180.v:95844.3-95862.6" - wire width 2 $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "issuer_ls180.v:95673.3-95691.6" - wire width 7 $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "issuer_ls180.v:95578.3-95596.6" - wire $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "issuer_ls180.v:95597.3-95615.6" - wire $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "issuer_ls180.v:95711.3-95729.6" - wire $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "issuer_ls180.v:95483.3-95501.6" - wire width 4 $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "issuer_ls180.v:95749.3-95767.6" - wire $1\dec31_dec_sub24_lk[0:0] - attribute \src "issuer_ls180.v:95863.3-95881.6" - wire width 2 $1\dec31_dec_sub24_out_sel[1:0] - attribute \src "issuer_ls180.v:95521.3-95539.6" - wire width 2 $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "issuer_ls180.v:95692.3-95710.6" - wire $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "issuer_ls180.v:95768.3-95786.6" - wire $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:95730.3-95748.6" - wire $1\dec31_dec_sub24_sgn[0:0] - attribute \src "issuer_ls180.v:95654.3-95672.6" - wire $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "issuer_ls180.v:95502.3-95520.6" - wire width 2 $1\dec31_dec_sub24_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub24_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub24_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub24_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub24_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub24_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub24_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub24_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub24_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub24_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub24_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub24_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub24_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub24_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub24_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub24_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub24_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub24_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub24_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub24_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub24_upd - attribute \src "issuer_ls180.v:95207.7-95207.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:95207.7-95207.20" - process $proc$issuer_ls180.v:95207$3895 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:95464.3-95482.6" - process $proc$issuer_ls180.v:95464$3871 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_function_unit[11:0] $1\dec31_dec_sub24_function_unit[11:0] - attribute \src "issuer_ls180.v:95465.5-95465.29" - switch \initial - attribute \src "issuer_ls180.v:95465.9-95465.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 - case - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[11:0] - end - attribute \src "issuer_ls180.v:95483.3-95501.6" - process $proc$issuer_ls180.v:95483$3872 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "issuer_ls180.v:95484.5-95484.29" - switch \initial - attribute \src "issuer_ls180.v:95484.9-95484.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:95502.3-95520.6" - process $proc$issuer_ls180.v:95502$3873 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] - attribute \src "issuer_ls180.v:95503.5-95503.29" - switch \initial - attribute \src "issuer_ls180.v:95503.9-95503.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub24_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] - end - attribute \src "issuer_ls180.v:95521.3-95539.6" - process $proc$issuer_ls180.v:95521$3874 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "issuer_ls180.v:95522.5-95522.29" - switch \initial - attribute \src "issuer_ls180.v:95522.9-95522.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:95540.3-95558.6" - process $proc$issuer_ls180.v:95540$3875 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "issuer_ls180.v:95541.5-95541.29" - switch \initial - attribute \src "issuer_ls180.v:95541.9-95541.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0] - end - attribute \src "issuer_ls180.v:95559.3-95577.6" - process $proc$issuer_ls180.v:95559$3876 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "issuer_ls180.v:95560.5-95560.29" - switch \initial - attribute \src "issuer_ls180.v:95560.9-95560.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_asmcode[7:0] 8'10011111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100101 - case - assign $1\dec31_dec_sub24_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0] - end - attribute \src "issuer_ls180.v:95578.3-95596.6" - process $proc$issuer_ls180.v:95578$3877 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "issuer_ls180.v:95579.5-95579.29" - switch \initial - attribute \src "issuer_ls180.v:95579.9-95579.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0] - end - attribute \src "issuer_ls180.v:95597.3-95615.6" - process $proc$issuer_ls180.v:95597$3878 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "issuer_ls180.v:95598.5-95598.29" - switch \initial - attribute \src "issuer_ls180.v:95598.9-95598.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0] - end - attribute \src "issuer_ls180.v:95616.3-95634.6" - process $proc$issuer_ls180.v:95616$3879 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "issuer_ls180.v:95617.5-95617.29" - switch \initial - attribute \src "issuer_ls180.v:95617.9-95617.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0] - end - attribute \src "issuer_ls180.v:95635.3-95653.6" - process $proc$issuer_ls180.v:95635$3880 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0] - attribute \src "issuer_ls180.v:95636.5-95636.29" - switch \initial - attribute \src "issuer_ls180.v:95636.9-95636.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_br[0:0] 1'0 - case - assign $1\dec31_dec_sub24_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0] - end - attribute \src "issuer_ls180.v:95654.3-95672.6" - process $proc$issuer_ls180.v:95654$3881 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "issuer_ls180.v:95655.5-95655.29" - switch \initial - attribute \src "issuer_ls180.v:95655.9-95655.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:95673.3-95691.6" - process $proc$issuer_ls180.v:95673$3882 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "issuer_ls180.v:95674.5-95674.29" - switch \initial - attribute \src "issuer_ls180.v:95674.9-95674.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 - case - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] - end - attribute \src "issuer_ls180.v:95692.3-95710.6" - process $proc$issuer_ls180.v:95692$3883 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "issuer_ls180.v:95693.5-95693.29" - switch \initial - attribute \src "issuer_ls180.v:95693.9-95693.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0] - end - attribute \src "issuer_ls180.v:95711.3-95729.6" - process $proc$issuer_ls180.v:95711$3884 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "issuer_ls180.v:95712.5-95712.29" - switch \initial - attribute \src "issuer_ls180.v:95712.9-95712.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 - case - assign $1\dec31_dec_sub24_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] - end - attribute \src "issuer_ls180.v:95730.3-95748.6" - process $proc$issuer_ls180.v:95730$3885 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0] - attribute \src "issuer_ls180.v:95731.5-95731.29" - switch \initial - attribute \src "issuer_ls180.v:95731.9-95731.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub24_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0] - end - attribute \src "issuer_ls180.v:95749.3-95767.6" - process $proc$issuer_ls180.v:95749$3886 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0] - attribute \src "issuer_ls180.v:95750.5-95750.29" - switch \initial - attribute \src "issuer_ls180.v:95750.9-95750.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub24_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0] - end - attribute \src "issuer_ls180.v:95768.3-95786.6" - process $proc$issuer_ls180.v:95768$3887 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:95769.5-95769.29" - switch \initial - attribute \src "issuer_ls180.v:95769.9-95769.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0] - end - attribute \src "issuer_ls180.v:95787.3-95805.6" - process $proc$issuer_ls180.v:95787$3888 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] - attribute \src "issuer_ls180.v:95788.5-95788.29" - switch \initial - attribute \src "issuer_ls180.v:95788.9-95788.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub24_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] - end - attribute \src "issuer_ls180.v:95806.3-95824.6" - process $proc$issuer_ls180.v:95806$3889 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "issuer_ls180.v:95807.5-95807.29" - switch \initial - attribute \src "issuer_ls180.v:95807.9-95807.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 - case - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:95825.3-95843.6" - process $proc$issuer_ls180.v:95825$3890 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "issuer_ls180.v:95826.5-95826.29" - switch \initial - attribute \src "issuer_ls180.v:95826.9-95826.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'1011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:95844.3-95862.6" - process $proc$issuer_ls180.v:95844$3891 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "issuer_ls180.v:95845.5-95845.29" - switch \initial - attribute \src "issuer_ls180.v:95845.9-95845.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0] - end - attribute \src "issuer_ls180.v:95863.3-95881.6" - process $proc$issuer_ls180.v:95863$3892 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_out_sel[1:0] $1\dec31_dec_sub24_out_sel[1:0] - attribute \src "issuer_ls180.v:95864.5-95864.29" - switch \initial - attribute \src "issuer_ls180.v:95864.9-95864.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub24_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub24_out_sel $0\dec31_dec_sub24_out_sel[1:0] - end - attribute \src "issuer_ls180.v:95882.3-95900.6" - process $proc$issuer_ls180.v:95882$3893 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "issuer_ls180.v:95883.5-95883.29" - switch \initial - attribute \src "issuer_ls180.v:95883.9-95883.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0] - end - attribute \src "issuer_ls180.v:95901.3-95919.6" - process $proc$issuer_ls180.v:95901$3894 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "issuer_ls180.v:95902.5-95902.29" - switch \initial - attribute \src "issuer_ls180.v:95902.9-95902.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub24_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:95925.1-97432.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub26" -attribute \generator "nMigen" -module \dec31_dec_sub26 - attribute \src "issuer_ls180.v:96443.3-96494.6" - wire width 8 $0\dec31_dec_sub26_asmcode[7:0] - attribute \src "issuer_ls180.v:96651.3-96702.6" - wire $0\dec31_dec_sub26_br[0:0] - attribute \src "issuer_ls180.v:97327.3-97378.6" - wire width 3 $0\dec31_dec_sub26_cr_in[2:0] - attribute \src "issuer_ls180.v:97379.3-97430.6" - wire width 3 $0\dec31_dec_sub26_cr_out[2:0] - attribute \src "issuer_ls180.v:96391.3-96442.6" - wire width 2 $0\dec31_dec_sub26_cry_in[1:0] - attribute \src "issuer_ls180.v:96599.3-96650.6" - wire $0\dec31_dec_sub26_cry_out[0:0] - attribute \src "issuer_ls180.v:97067.3-97118.6" - wire width 5 $0\dec31_dec_sub26_form[4:0] - attribute \src "issuer_ls180.v:96183.3-96234.6" - wire width 12 $0\dec31_dec_sub26_function_unit[11:0] - attribute \src "issuer_ls180.v:97119.3-97170.6" - wire width 3 $0\dec31_dec_sub26_in1_sel[2:0] - attribute \src "issuer_ls180.v:97171.3-97222.6" - wire width 4 $0\dec31_dec_sub26_in2_sel[3:0] - attribute \src "issuer_ls180.v:97223.3-97274.6" - wire width 2 $0\dec31_dec_sub26_in3_sel[1:0] - attribute \src "issuer_ls180.v:96755.3-96806.6" - wire width 7 $0\dec31_dec_sub26_internal_op[6:0] - attribute \src "issuer_ls180.v:96495.3-96546.6" - wire $0\dec31_dec_sub26_inv_a[0:0] - attribute \src "issuer_ls180.v:96547.3-96598.6" - wire $0\dec31_dec_sub26_inv_out[0:0] - attribute \src "issuer_ls180.v:96859.3-96910.6" - wire $0\dec31_dec_sub26_is_32b[0:0] - attribute \src "issuer_ls180.v:96235.3-96286.6" - wire width 4 $0\dec31_dec_sub26_ldst_len[3:0] - attribute \src "issuer_ls180.v:96963.3-97014.6" - wire $0\dec31_dec_sub26_lk[0:0] - attribute \src "issuer_ls180.v:97275.3-97326.6" - wire width 2 $0\dec31_dec_sub26_out_sel[1:0] - attribute \src "issuer_ls180.v:96339.3-96390.6" - wire width 2 $0\dec31_dec_sub26_rc_sel[1:0] - attribute \src "issuer_ls180.v:96807.3-96858.6" - wire $0\dec31_dec_sub26_rsrv[0:0] - attribute \src "issuer_ls180.v:97015.3-97066.6" - wire $0\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:96911.3-96962.6" - wire $0\dec31_dec_sub26_sgn[0:0] - attribute \src "issuer_ls180.v:96703.3-96754.6" - wire $0\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "issuer_ls180.v:96287.3-96338.6" - wire width 2 $0\dec31_dec_sub26_upd[1:0] - attribute \src "issuer_ls180.v:95926.7-95926.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:96443.3-96494.6" - wire width 8 $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "issuer_ls180.v:96651.3-96702.6" - wire $1\dec31_dec_sub26_br[0:0] - attribute \src "issuer_ls180.v:97327.3-97378.6" - wire width 3 $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "issuer_ls180.v:97379.3-97430.6" - wire width 3 $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "issuer_ls180.v:96391.3-96442.6" - wire width 2 $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "issuer_ls180.v:96599.3-96650.6" - wire $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "issuer_ls180.v:97067.3-97118.6" - wire width 5 $1\dec31_dec_sub26_form[4:0] - attribute \src "issuer_ls180.v:96183.3-96234.6" - wire width 12 $1\dec31_dec_sub26_function_unit[11:0] - attribute \src "issuer_ls180.v:97119.3-97170.6" - wire width 3 $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "issuer_ls180.v:97171.3-97222.6" - wire width 4 $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "issuer_ls180.v:97223.3-97274.6" - wire width 2 $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "issuer_ls180.v:96755.3-96806.6" - wire width 7 $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "issuer_ls180.v:96495.3-96546.6" - wire $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "issuer_ls180.v:96547.3-96598.6" - wire $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "issuer_ls180.v:96859.3-96910.6" - wire $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "issuer_ls180.v:96235.3-96286.6" - wire width 4 $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "issuer_ls180.v:96963.3-97014.6" - wire $1\dec31_dec_sub26_lk[0:0] - attribute \src "issuer_ls180.v:97275.3-97326.6" - wire width 2 $1\dec31_dec_sub26_out_sel[1:0] - attribute \src "issuer_ls180.v:96339.3-96390.6" - wire width 2 $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "issuer_ls180.v:96807.3-96858.6" - wire $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "issuer_ls180.v:97015.3-97066.6" - wire $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:96911.3-96962.6" - wire $1\dec31_dec_sub26_sgn[0:0] - attribute \src "issuer_ls180.v:96703.3-96754.6" - wire $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "issuer_ls180.v:96287.3-96338.6" - wire width 2 $1\dec31_dec_sub26_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub26_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub26_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub26_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub26_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub26_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub26_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub26_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub26_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub26_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub26_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub26_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub26_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub26_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub26_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub26_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub26_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub26_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub26_upd - attribute \src "issuer_ls180.v:95926.7-95926.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:95926.7-95926.20" - process $proc$issuer_ls180.v:95926$3920 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:96183.3-96234.6" - process $proc$issuer_ls180.v:96183$3896 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_function_unit[11:0] $1\dec31_dec_sub26_function_unit[11:0] - attribute \src "issuer_ls180.v:96184.5-96184.29" - switch \initial - attribute \src "issuer_ls180.v:96184.9-96184.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 - case - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[11:0] - end - attribute \src "issuer_ls180.v:96235.3-96286.6" - process $proc$issuer_ls180.v:96235$3897 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "issuer_ls180.v:96236.5-96236.29" - switch \initial - attribute \src "issuer_ls180.v:96236.9-96236.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:96287.3-96338.6" - process $proc$issuer_ls180.v:96287$3898 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] - attribute \src "issuer_ls180.v:96288.5-96288.29" - switch \initial - attribute \src "issuer_ls180.v:96288.9-96288.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] - end - attribute \src "issuer_ls180.v:96339.3-96390.6" - process $proc$issuer_ls180.v:96339$3899 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "issuer_ls180.v:96340.5-96340.29" - switch \initial - attribute \src "issuer_ls180.v:96340.9-96340.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:96391.3-96442.6" - process $proc$issuer_ls180.v:96391$3900 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "issuer_ls180.v:96392.5-96392.29" - switch \initial - attribute \src "issuer_ls180.v:96392.9-96392.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0] - end - attribute \src "issuer_ls180.v:96443.3-96494.6" - process $proc$issuer_ls180.v:96443$3901 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "issuer_ls180.v:96444.5-96444.29" - switch \initial - attribute \src "issuer_ls180.v:96444.9-96444.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100001 - case - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0] - end - attribute \src "issuer_ls180.v:96495.3-96546.6" - process $proc$issuer_ls180.v:96495$3902 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "issuer_ls180.v:96496.5-96496.29" - switch \initial - attribute \src "issuer_ls180.v:96496.9-96496.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0] - end - attribute \src "issuer_ls180.v:96547.3-96598.6" - process $proc$issuer_ls180.v:96547$3903 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "issuer_ls180.v:96548.5-96548.29" - switch \initial - attribute \src "issuer_ls180.v:96548.9-96548.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0] - end - attribute \src "issuer_ls180.v:96599.3-96650.6" - process $proc$issuer_ls180.v:96599$3904 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "issuer_ls180.v:96600.5-96600.29" - switch \initial - attribute \src "issuer_ls180.v:96600.9-96600.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 - case - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0] - end - attribute \src "issuer_ls180.v:96651.3-96702.6" - process $proc$issuer_ls180.v:96651$3905 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0] - attribute \src "issuer_ls180.v:96652.5-96652.29" - switch \initial - attribute \src "issuer_ls180.v:96652.9-96652.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - case - assign $1\dec31_dec_sub26_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0] - end - attribute \src "issuer_ls180.v:96703.3-96754.6" - process $proc$issuer_ls180.v:96703$3906 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "issuer_ls180.v:96704.5-96704.29" - switch \initial - attribute \src "issuer_ls180.v:96704.9-96704.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:96755.3-96806.6" - process $proc$issuer_ls180.v:96755$3907 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "issuer_ls180.v:96756.5-96756.29" - switch \initial - attribute \src "issuer_ls180.v:96756.9-96756.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0100000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 - case - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] - end - attribute \src "issuer_ls180.v:96807.3-96858.6" - process $proc$issuer_ls180.v:96807$3908 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "issuer_ls180.v:96808.5-96808.29" - switch \initial - attribute \src "issuer_ls180.v:96808.9-96808.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0] - end - attribute \src "issuer_ls180.v:96859.3-96910.6" - process $proc$issuer_ls180.v:96859$3909 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "issuer_ls180.v:96860.5-96860.29" - switch \initial - attribute \src "issuer_ls180.v:96860.9-96860.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] - end - attribute \src "issuer_ls180.v:96911.3-96962.6" - process $proc$issuer_ls180.v:96911$3910 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0] - attribute \src "issuer_ls180.v:96912.5-96912.29" - switch \initial - attribute \src "issuer_ls180.v:96912.9-96912.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'1 - case - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0] - end - attribute \src "issuer_ls180.v:96963.3-97014.6" - process $proc$issuer_ls180.v:96963$3911 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0] - attribute \src "issuer_ls180.v:96964.5-96964.29" - switch \initial - attribute \src "issuer_ls180.v:96964.9-96964.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0] - end - attribute \src "issuer_ls180.v:97015.3-97066.6" - process $proc$issuer_ls180.v:97015$3912 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:97016.5-97016.29" - switch \initial - attribute \src "issuer_ls180.v:97016.9-97016.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0] - end - attribute \src "issuer_ls180.v:97067.3-97118.6" - process $proc$issuer_ls180.v:97067$3913 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] - attribute \src "issuer_ls180.v:97068.5-97068.29" - switch \initial - attribute \src "issuer_ls180.v:97068.9-97068.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'10000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'10000 - case - assign $1\dec31_dec_sub26_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] - end - attribute \src "issuer_ls180.v:97119.3-97170.6" - process $proc$issuer_ls180.v:97119$3914 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "issuer_ls180.v:97120.5-97120.29" - switch \initial - attribute \src "issuer_ls180.v:97120.9-97120.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 - case - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:97171.3-97222.6" - process $proc$issuer_ls180.v:97171$3915 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "issuer_ls180.v:97172.5-97172.29" - switch \initial - attribute \src "issuer_ls180.v:97172.9-97172.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 - case - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:97223.3-97274.6" - process $proc$issuer_ls180.v:97223$3916 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "issuer_ls180.v:97224.5-97224.29" - switch \initial - attribute \src "issuer_ls180.v:97224.9-97224.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0] - end - attribute \src "issuer_ls180.v:97275.3-97326.6" - process $proc$issuer_ls180.v:97275$3917 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_out_sel[1:0] $1\dec31_dec_sub26_out_sel[1:0] - attribute \src "issuer_ls180.v:97276.5-97276.29" - switch \initial - attribute \src "issuer_ls180.v:97276.9-97276.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub26_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub26_out_sel $0\dec31_dec_sub26_out_sel[1:0] - end - attribute \src "issuer_ls180.v:97327.3-97378.6" - process $proc$issuer_ls180.v:97327$3918 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "issuer_ls180.v:97328.5-97328.29" - switch \initial - attribute \src "issuer_ls180.v:97328.9-97328.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0] - end - attribute \src "issuer_ls180.v:97379.3-97430.6" - process $proc$issuer_ls180.v:97379$3919 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "issuer_ls180.v:97380.5-97380.29" - switch \initial - attribute \src "issuer_ls180.v:97380.9-97380.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:97436.1-98151.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub27" -attribute \generator "nMigen" -module \dec31_dec_sub27 - attribute \src "issuer_ls180.v:97789.3-97807.6" - wire width 8 $0\dec31_dec_sub27_asmcode[7:0] - attribute \src "issuer_ls180.v:97865.3-97883.6" - wire $0\dec31_dec_sub27_br[0:0] - attribute \src "issuer_ls180.v:98112.3-98130.6" - wire width 3 $0\dec31_dec_sub27_cr_in[2:0] - attribute \src "issuer_ls180.v:98131.3-98149.6" - wire width 3 $0\dec31_dec_sub27_cr_out[2:0] - attribute \src "issuer_ls180.v:97770.3-97788.6" - wire width 2 $0\dec31_dec_sub27_cry_in[1:0] - attribute \src "issuer_ls180.v:97846.3-97864.6" - wire $0\dec31_dec_sub27_cry_out[0:0] - attribute \src "issuer_ls180.v:98017.3-98035.6" - wire width 5 $0\dec31_dec_sub27_form[4:0] - attribute \src "issuer_ls180.v:97694.3-97712.6" - wire width 12 $0\dec31_dec_sub27_function_unit[11:0] - attribute \src "issuer_ls180.v:98036.3-98054.6" - wire width 3 $0\dec31_dec_sub27_in1_sel[2:0] - attribute \src "issuer_ls180.v:98055.3-98073.6" - wire width 4 $0\dec31_dec_sub27_in2_sel[3:0] - attribute \src "issuer_ls180.v:98074.3-98092.6" - wire width 2 $0\dec31_dec_sub27_in3_sel[1:0] - attribute \src "issuer_ls180.v:97903.3-97921.6" - wire width 7 $0\dec31_dec_sub27_internal_op[6:0] - attribute \src "issuer_ls180.v:97808.3-97826.6" - wire $0\dec31_dec_sub27_inv_a[0:0] - attribute \src "issuer_ls180.v:97827.3-97845.6" - wire $0\dec31_dec_sub27_inv_out[0:0] - attribute \src "issuer_ls180.v:97941.3-97959.6" - wire $0\dec31_dec_sub27_is_32b[0:0] - attribute \src "issuer_ls180.v:97713.3-97731.6" - wire width 4 $0\dec31_dec_sub27_ldst_len[3:0] - attribute \src "issuer_ls180.v:97979.3-97997.6" - wire $0\dec31_dec_sub27_lk[0:0] - attribute \src "issuer_ls180.v:98093.3-98111.6" - wire width 2 $0\dec31_dec_sub27_out_sel[1:0] - attribute \src "issuer_ls180.v:97751.3-97769.6" - wire width 2 $0\dec31_dec_sub27_rc_sel[1:0] - attribute \src "issuer_ls180.v:97922.3-97940.6" - wire $0\dec31_dec_sub27_rsrv[0:0] - attribute \src "issuer_ls180.v:97998.3-98016.6" - wire $0\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:97960.3-97978.6" - wire $0\dec31_dec_sub27_sgn[0:0] - attribute \src "issuer_ls180.v:97884.3-97902.6" - wire $0\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "issuer_ls180.v:97732.3-97750.6" - wire width 2 $0\dec31_dec_sub27_upd[1:0] - attribute \src "issuer_ls180.v:97437.7-97437.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:97789.3-97807.6" - wire width 8 $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "issuer_ls180.v:97865.3-97883.6" - wire $1\dec31_dec_sub27_br[0:0] - attribute \src "issuer_ls180.v:98112.3-98130.6" - wire width 3 $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "issuer_ls180.v:98131.3-98149.6" - wire width 3 $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "issuer_ls180.v:97770.3-97788.6" - wire width 2 $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "issuer_ls180.v:97846.3-97864.6" - wire $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "issuer_ls180.v:98017.3-98035.6" - wire width 5 $1\dec31_dec_sub27_form[4:0] - attribute \src "issuer_ls180.v:97694.3-97712.6" - wire width 12 $1\dec31_dec_sub27_function_unit[11:0] - attribute \src "issuer_ls180.v:98036.3-98054.6" - wire width 3 $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "issuer_ls180.v:98055.3-98073.6" - wire width 4 $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "issuer_ls180.v:98074.3-98092.6" - wire width 2 $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "issuer_ls180.v:97903.3-97921.6" - wire width 7 $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "issuer_ls180.v:97808.3-97826.6" - wire $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "issuer_ls180.v:97827.3-97845.6" - wire $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "issuer_ls180.v:97941.3-97959.6" - wire $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "issuer_ls180.v:97713.3-97731.6" - wire width 4 $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "issuer_ls180.v:97979.3-97997.6" - wire $1\dec31_dec_sub27_lk[0:0] - attribute \src "issuer_ls180.v:98093.3-98111.6" - wire width 2 $1\dec31_dec_sub27_out_sel[1:0] - attribute \src "issuer_ls180.v:97751.3-97769.6" - wire width 2 $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "issuer_ls180.v:97922.3-97940.6" - wire $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "issuer_ls180.v:97998.3-98016.6" - wire $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:97960.3-97978.6" - wire $1\dec31_dec_sub27_sgn[0:0] - attribute \src "issuer_ls180.v:97884.3-97902.6" - wire $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "issuer_ls180.v:97732.3-97750.6" - wire width 2 $1\dec31_dec_sub27_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub27_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub27_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub27_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub27_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub27_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub27_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub27_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub27_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub27_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub27_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub27_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub27_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub27_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub27_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub27_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub27_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub27_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub27_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub27_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub27_upd - attribute \src "issuer_ls180.v:97437.7-97437.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:97437.7-97437.20" - process $proc$issuer_ls180.v:97437$3945 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:97694.3-97712.6" - process $proc$issuer_ls180.v:97694$3921 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_function_unit[11:0] $1\dec31_dec_sub27_function_unit[11:0] - attribute \src "issuer_ls180.v:97695.5-97695.29" - switch \initial - attribute \src "issuer_ls180.v:97695.9-97695.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 - case - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[11:0] - end - attribute \src "issuer_ls180.v:97713.3-97731.6" - process $proc$issuer_ls180.v:97713$3922 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "issuer_ls180.v:97714.5-97714.29" - switch \initial - attribute \src "issuer_ls180.v:97714.9-97714.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:97732.3-97750.6" - process $proc$issuer_ls180.v:97732$3923 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] - attribute \src "issuer_ls180.v:97733.5-97733.29" - switch \initial - attribute \src "issuer_ls180.v:97733.9-97733.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub27_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] - end - attribute \src "issuer_ls180.v:97751.3-97769.6" - process $proc$issuer_ls180.v:97751$3924 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "issuer_ls180.v:97752.5-97752.29" - switch \initial - attribute \src "issuer_ls180.v:97752.9-97752.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:97770.3-97788.6" - process $proc$issuer_ls180.v:97770$3925 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "issuer_ls180.v:97771.5-97771.29" - switch \initial - attribute \src "issuer_ls180.v:97771.9-97771.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0] - end - attribute \src "issuer_ls180.v:97789.3-97807.6" - process $proc$issuer_ls180.v:97789$3926 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "issuer_ls180.v:97790.5-97790.29" - switch \initial - attribute \src "issuer_ls180.v:97790.9-97790.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_asmcode[7:0] 8'01000111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_asmcode[7:0] 8'10011110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100100 - case - assign $1\dec31_dec_sub27_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0] - end - attribute \src "issuer_ls180.v:97808.3-97826.6" - process $proc$issuer_ls180.v:97808$3927 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "issuer_ls180.v:97809.5-97809.29" - switch \initial - attribute \src "issuer_ls180.v:97809.9-97809.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0] - end - attribute \src "issuer_ls180.v:97827.3-97845.6" - process $proc$issuer_ls180.v:97827$3928 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "issuer_ls180.v:97828.5-97828.29" - switch \initial - attribute \src "issuer_ls180.v:97828.9-97828.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0] - end - attribute \src "issuer_ls180.v:97846.3-97864.6" - process $proc$issuer_ls180.v:97846$3929 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "issuer_ls180.v:97847.5-97847.29" - switch \initial - attribute \src "issuer_ls180.v:97847.9-97847.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0] - end - attribute \src "issuer_ls180.v:97865.3-97883.6" - process $proc$issuer_ls180.v:97865$3930 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0] - attribute \src "issuer_ls180.v:97866.5-97866.29" - switch \initial - attribute \src "issuer_ls180.v:97866.9-97866.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_br[0:0] 1'0 - case - assign $1\dec31_dec_sub27_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0] - end - attribute \src "issuer_ls180.v:97884.3-97902.6" - process $proc$issuer_ls180.v:97884$3931 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "issuer_ls180.v:97885.5-97885.29" - switch \initial - attribute \src "issuer_ls180.v:97885.9-97885.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:97903.3-97921.6" - process $proc$issuer_ls180.v:97903$3932 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "issuer_ls180.v:97904.5-97904.29" - switch \initial - attribute \src "issuer_ls180.v:97904.9-97904.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0100000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 - case - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] - end - attribute \src "issuer_ls180.v:97922.3-97940.6" - process $proc$issuer_ls180.v:97922$3933 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "issuer_ls180.v:97923.5-97923.29" - switch \initial - attribute \src "issuer_ls180.v:97923.9-97923.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0] - end - attribute \src "issuer_ls180.v:97941.3-97959.6" - process $proc$issuer_ls180.v:97941$3934 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "issuer_ls180.v:97942.5-97942.29" - switch \initial - attribute \src "issuer_ls180.v:97942.9-97942.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] - end - attribute \src "issuer_ls180.v:97960.3-97978.6" - process $proc$issuer_ls180.v:97960$3935 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0] - attribute \src "issuer_ls180.v:97961.5-97961.29" - switch \initial - attribute \src "issuer_ls180.v:97961.9-97961.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub27_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0] - end - attribute \src "issuer_ls180.v:97979.3-97997.6" - process $proc$issuer_ls180.v:97979$3936 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0] - attribute \src "issuer_ls180.v:97980.5-97980.29" - switch \initial - attribute \src "issuer_ls180.v:97980.9-97980.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub27_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0] - end - attribute \src "issuer_ls180.v:97998.3-98016.6" - process $proc$issuer_ls180.v:97998$3937 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:97999.5-97999.29" - switch \initial - attribute \src "issuer_ls180.v:97999.9-97999.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0] - end - attribute \src "issuer_ls180.v:98017.3-98035.6" - process $proc$issuer_ls180.v:98017$3938 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] - attribute \src "issuer_ls180.v:98018.5-98018.29" - switch \initial - attribute \src "issuer_ls180.v:98018.9-98018.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'10000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'10000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub27_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] - end - attribute \src "issuer_ls180.v:98036.3-98054.6" - process $proc$issuer_ls180.v:98036$3939 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "issuer_ls180.v:98037.5-98037.29" - switch \initial - attribute \src "issuer_ls180.v:98037.9-98037.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 - case - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:98055.3-98073.6" - process $proc$issuer_ls180.v:98055$3940 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "issuer_ls180.v:98056.5-98056.29" - switch \initial - attribute \src "issuer_ls180.v:98056.9-98056.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:98074.3-98092.6" - process $proc$issuer_ls180.v:98074$3941 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "issuer_ls180.v:98075.5-98075.29" - switch \initial - attribute \src "issuer_ls180.v:98075.9-98075.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0] - end - attribute \src "issuer_ls180.v:98093.3-98111.6" - process $proc$issuer_ls180.v:98093$3942 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_out_sel[1:0] $1\dec31_dec_sub27_out_sel[1:0] - attribute \src "issuer_ls180.v:98094.5-98094.29" - switch \initial - attribute \src "issuer_ls180.v:98094.9-98094.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub27_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub27_out_sel $0\dec31_dec_sub27_out_sel[1:0] - end - attribute \src "issuer_ls180.v:98112.3-98130.6" - process $proc$issuer_ls180.v:98112$3943 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "issuer_ls180.v:98113.5-98113.29" - switch \initial - attribute \src "issuer_ls180.v:98113.9-98113.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0] - end - attribute \src "issuer_ls180.v:98131.3-98149.6" - process $proc$issuer_ls180.v:98131$3944 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "issuer_ls180.v:98132.5-98132.29" - switch \initial - attribute \src "issuer_ls180.v:98132.9-98132.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub27_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:98155.1-99302.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub28" -attribute \generator "nMigen" -module \dec31_dec_sub28 - attribute \src "issuer_ls180.v:98598.3-98634.6" - wire width 8 $0\dec31_dec_sub28_asmcode[7:0] - attribute \src "issuer_ls180.v:98746.3-98782.6" - wire $0\dec31_dec_sub28_br[0:0] - attribute \src "issuer_ls180.v:99227.3-99263.6" - wire width 3 $0\dec31_dec_sub28_cr_in[2:0] - attribute \src "issuer_ls180.v:99264.3-99300.6" - wire width 3 $0\dec31_dec_sub28_cr_out[2:0] - attribute \src "issuer_ls180.v:98561.3-98597.6" - wire width 2 $0\dec31_dec_sub28_cry_in[1:0] - attribute \src "issuer_ls180.v:98709.3-98745.6" - wire $0\dec31_dec_sub28_cry_out[0:0] - attribute \src "issuer_ls180.v:99042.3-99078.6" - wire width 5 $0\dec31_dec_sub28_form[4:0] - attribute \src "issuer_ls180.v:98413.3-98449.6" - wire width 12 $0\dec31_dec_sub28_function_unit[11:0] - attribute \src "issuer_ls180.v:99079.3-99115.6" - wire width 3 $0\dec31_dec_sub28_in1_sel[2:0] - attribute \src "issuer_ls180.v:99116.3-99152.6" - wire width 4 $0\dec31_dec_sub28_in2_sel[3:0] - attribute \src "issuer_ls180.v:99153.3-99189.6" - wire width 2 $0\dec31_dec_sub28_in3_sel[1:0] - attribute \src "issuer_ls180.v:98820.3-98856.6" - wire width 7 $0\dec31_dec_sub28_internal_op[6:0] - attribute \src "issuer_ls180.v:98635.3-98671.6" - wire $0\dec31_dec_sub28_inv_a[0:0] - attribute \src "issuer_ls180.v:98672.3-98708.6" - wire $0\dec31_dec_sub28_inv_out[0:0] - attribute \src "issuer_ls180.v:98894.3-98930.6" - wire $0\dec31_dec_sub28_is_32b[0:0] - attribute \src "issuer_ls180.v:98450.3-98486.6" - wire width 4 $0\dec31_dec_sub28_ldst_len[3:0] - attribute \src "issuer_ls180.v:98968.3-99004.6" - wire $0\dec31_dec_sub28_lk[0:0] - attribute \src "issuer_ls180.v:99190.3-99226.6" - wire width 2 $0\dec31_dec_sub28_out_sel[1:0] - attribute \src "issuer_ls180.v:98524.3-98560.6" - wire width 2 $0\dec31_dec_sub28_rc_sel[1:0] - attribute \src "issuer_ls180.v:98857.3-98893.6" - wire $0\dec31_dec_sub28_rsrv[0:0] - attribute \src "issuer_ls180.v:99005.3-99041.6" - wire $0\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:98931.3-98967.6" - wire $0\dec31_dec_sub28_sgn[0:0] - attribute \src "issuer_ls180.v:98783.3-98819.6" - wire $0\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "issuer_ls180.v:98487.3-98523.6" - wire width 2 $0\dec31_dec_sub28_upd[1:0] - attribute \src "issuer_ls180.v:98156.7-98156.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:98598.3-98634.6" - wire width 8 $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "issuer_ls180.v:98746.3-98782.6" - wire $1\dec31_dec_sub28_br[0:0] - attribute \src "issuer_ls180.v:99227.3-99263.6" - wire width 3 $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "issuer_ls180.v:99264.3-99300.6" - wire width 3 $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "issuer_ls180.v:98561.3-98597.6" - wire width 2 $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "issuer_ls180.v:98709.3-98745.6" - wire $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "issuer_ls180.v:99042.3-99078.6" - wire width 5 $1\dec31_dec_sub28_form[4:0] - attribute \src "issuer_ls180.v:98413.3-98449.6" - wire width 12 $1\dec31_dec_sub28_function_unit[11:0] - attribute \src "issuer_ls180.v:99079.3-99115.6" - wire width 3 $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "issuer_ls180.v:99116.3-99152.6" - wire width 4 $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "issuer_ls180.v:99153.3-99189.6" - wire width 2 $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "issuer_ls180.v:98820.3-98856.6" - wire width 7 $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "issuer_ls180.v:98635.3-98671.6" - wire $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "issuer_ls180.v:98672.3-98708.6" - wire $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "issuer_ls180.v:98894.3-98930.6" - wire $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "issuer_ls180.v:98450.3-98486.6" - wire width 4 $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "issuer_ls180.v:98968.3-99004.6" - wire $1\dec31_dec_sub28_lk[0:0] - attribute \src "issuer_ls180.v:99190.3-99226.6" - wire width 2 $1\dec31_dec_sub28_out_sel[1:0] - attribute \src "issuer_ls180.v:98524.3-98560.6" - wire width 2 $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "issuer_ls180.v:98857.3-98893.6" - wire $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "issuer_ls180.v:99005.3-99041.6" - wire $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:98931.3-98967.6" - wire $1\dec31_dec_sub28_sgn[0:0] - attribute \src "issuer_ls180.v:98783.3-98819.6" - wire $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "issuer_ls180.v:98487.3-98523.6" - wire width 2 $1\dec31_dec_sub28_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub28_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub28_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub28_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub28_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub28_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub28_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub28_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub28_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub28_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub28_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub28_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub28_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub28_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub28_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub28_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub28_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub28_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub28_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub28_upd - attribute \src "issuer_ls180.v:98156.7-98156.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:98156.7-98156.20" - process $proc$issuer_ls180.v:98156$3970 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:98413.3-98449.6" - process $proc$issuer_ls180.v:98413$3946 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_function_unit[11:0] $1\dec31_dec_sub28_function_unit[11:0] - attribute \src "issuer_ls180.v:98414.5-98414.29" - switch \initial - attribute \src "issuer_ls180.v:98414.9-98414.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - case - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[11:0] - end - attribute \src "issuer_ls180.v:98450.3-98486.6" - process $proc$issuer_ls180.v:98450$3947 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "issuer_ls180.v:98451.5-98451.29" - switch \initial - attribute \src "issuer_ls180.v:98451.9-98451.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:98487.3-98523.6" - process $proc$issuer_ls180.v:98487$3948 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] - attribute \src "issuer_ls180.v:98488.5-98488.29" - switch \initial - attribute \src "issuer_ls180.v:98488.9-98488.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] - end - attribute \src "issuer_ls180.v:98524.3-98560.6" - process $proc$issuer_ls180.v:98524$3949 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "issuer_ls180.v:98525.5-98525.29" - switch \initial - attribute \src "issuer_ls180.v:98525.9-98525.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:98561.3-98597.6" - process $proc$issuer_ls180.v:98561$3950 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "issuer_ls180.v:98562.5-98562.29" - switch \initial - attribute \src "issuer_ls180.v:98562.9-98562.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0] - end - attribute \src "issuer_ls180.v:98598.3-98634.6" - process $proc$issuer_ls180.v:98598$3951 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "issuer_ls180.v:98599.5-98599.29" - switch \initial - attribute \src "issuer_ls180.v:98599.9-98599.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00001111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'01000011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'11010000 - case - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0] - end - attribute \src "issuer_ls180.v:98635.3-98671.6" - process $proc$issuer_ls180.v:98635$3952 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "issuer_ls180.v:98636.5-98636.29" - switch \initial - attribute \src "issuer_ls180.v:98636.9-98636.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0] - end - attribute \src "issuer_ls180.v:98672.3-98708.6" - process $proc$issuer_ls180.v:98672$3953 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "issuer_ls180.v:98673.5-98673.29" - switch \initial - attribute \src "issuer_ls180.v:98673.9-98673.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0] - end - attribute \src "issuer_ls180.v:98709.3-98745.6" - process $proc$issuer_ls180.v:98709$3954 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "issuer_ls180.v:98710.5-98710.29" - switch \initial - attribute \src "issuer_ls180.v:98710.9-98710.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0] - end - attribute \src "issuer_ls180.v:98746.3-98782.6" - process $proc$issuer_ls180.v:98746$3955 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0] - attribute \src "issuer_ls180.v:98747.5-98747.29" - switch \initial - attribute \src "issuer_ls180.v:98747.9-98747.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - case - assign $1\dec31_dec_sub28_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0] - end - attribute \src "issuer_ls180.v:98783.3-98819.6" - process $proc$issuer_ls180.v:98783$3956 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "issuer_ls180.v:98784.5-98784.29" - switch \initial - attribute \src "issuer_ls180.v:98784.9-98784.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:98820.3-98856.6" - process $proc$issuer_ls180.v:98820$3957 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "issuer_ls180.v:98821.5-98821.29" - switch \initial - attribute \src "issuer_ls180.v:98821.9-98821.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 - case - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] - end - attribute \src "issuer_ls180.v:98857.3-98893.6" - process $proc$issuer_ls180.v:98857$3958 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "issuer_ls180.v:98858.5-98858.29" - switch \initial - attribute \src "issuer_ls180.v:98858.9-98858.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0] - end - attribute \src "issuer_ls180.v:98894.3-98930.6" - process $proc$issuer_ls180.v:98894$3959 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "issuer_ls180.v:98895.5-98895.29" - switch \initial - attribute \src "issuer_ls180.v:98895.9-98895.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] - end - attribute \src "issuer_ls180.v:98931.3-98967.6" - process $proc$issuer_ls180.v:98931$3960 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0] - attribute \src "issuer_ls180.v:98932.5-98932.29" - switch \initial - attribute \src "issuer_ls180.v:98932.9-98932.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0] - end - attribute \src "issuer_ls180.v:98968.3-99004.6" - process $proc$issuer_ls180.v:98968$3961 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0] - attribute \src "issuer_ls180.v:98969.5-98969.29" - switch \initial - attribute \src "issuer_ls180.v:98969.9-98969.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0] - end - attribute \src "issuer_ls180.v:99005.3-99041.6" - process $proc$issuer_ls180.v:99005$3962 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:99006.5-99006.29" - switch \initial - attribute \src "issuer_ls180.v:99006.9-99006.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0] - end - attribute \src "issuer_ls180.v:99042.3-99078.6" - process $proc$issuer_ls180.v:99042$3963 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] - attribute \src "issuer_ls180.v:99043.5-99043.29" - switch \initial - attribute \src "issuer_ls180.v:99043.9-99043.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub28_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] - end - attribute \src "issuer_ls180.v:99079.3-99115.6" - process $proc$issuer_ls180.v:99079$3964 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "issuer_ls180.v:99080.5-99080.29" - switch \initial - attribute \src "issuer_ls180.v:99080.9-99080.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - case - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:99116.3-99152.6" - process $proc$issuer_ls180.v:99116$3965 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "issuer_ls180.v:99117.5-99117.29" - switch \initial - attribute \src "issuer_ls180.v:99117.9-99117.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:99153.3-99189.6" - process $proc$issuer_ls180.v:99153$3966 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "issuer_ls180.v:99154.5-99154.29" - switch \initial - attribute \src "issuer_ls180.v:99154.9-99154.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0] - end - attribute \src "issuer_ls180.v:99190.3-99226.6" - process $proc$issuer_ls180.v:99190$3967 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_out_sel[1:0] $1\dec31_dec_sub28_out_sel[1:0] - attribute \src "issuer_ls180.v:99191.5-99191.29" - switch \initial - attribute \src "issuer_ls180.v:99191.9-99191.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub28_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub28_out_sel $0\dec31_dec_sub28_out_sel[1:0] - end - attribute \src "issuer_ls180.v:99227.3-99263.6" - process $proc$issuer_ls180.v:99227$3968 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "issuer_ls180.v:99228.5-99228.29" - switch \initial - attribute \src "issuer_ls180.v:99228.9-99228.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0] - end - attribute \src "issuer_ls180.v:99264.3-99300.6" - process $proc$issuer_ls180.v:99264$3969 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "issuer_ls180.v:99265.5-99265.29" - switch \initial - attribute \src "issuer_ls180.v:99265.9-99265.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:99306.1-99877.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub4" -attribute \generator "nMigen" -module \dec31_dec_sub4 - attribute \src "issuer_ls180.v:99629.3-99641.6" - wire width 8 $0\dec31_dec_sub4_asmcode[7:0] - attribute \src "issuer_ls180.v:99681.3-99693.6" - wire $0\dec31_dec_sub4_br[0:0] - attribute \src "issuer_ls180.v:99850.3-99862.6" - wire width 3 $0\dec31_dec_sub4_cr_in[2:0] - attribute \src "issuer_ls180.v:99863.3-99875.6" - wire width 3 $0\dec31_dec_sub4_cr_out[2:0] - attribute \src "issuer_ls180.v:99616.3-99628.6" - wire width 2 $0\dec31_dec_sub4_cry_in[1:0] - attribute \src "issuer_ls180.v:99668.3-99680.6" - wire $0\dec31_dec_sub4_cry_out[0:0] - attribute \src "issuer_ls180.v:99785.3-99797.6" - wire width 5 $0\dec31_dec_sub4_form[4:0] - attribute \src "issuer_ls180.v:99564.3-99576.6" - wire width 12 $0\dec31_dec_sub4_function_unit[11:0] - attribute \src "issuer_ls180.v:99798.3-99810.6" - wire width 3 $0\dec31_dec_sub4_in1_sel[2:0] - attribute \src "issuer_ls180.v:99811.3-99823.6" - wire width 4 $0\dec31_dec_sub4_in2_sel[3:0] - attribute \src "issuer_ls180.v:99824.3-99836.6" - wire width 2 $0\dec31_dec_sub4_in3_sel[1:0] - attribute \src "issuer_ls180.v:99707.3-99719.6" - wire width 7 $0\dec31_dec_sub4_internal_op[6:0] - attribute \src "issuer_ls180.v:99642.3-99654.6" - wire $0\dec31_dec_sub4_inv_a[0:0] - attribute \src "issuer_ls180.v:99655.3-99667.6" - wire $0\dec31_dec_sub4_inv_out[0:0] - attribute \src "issuer_ls180.v:99733.3-99745.6" - wire $0\dec31_dec_sub4_is_32b[0:0] - attribute \src "issuer_ls180.v:99577.3-99589.6" - wire width 4 $0\dec31_dec_sub4_ldst_len[3:0] - attribute \src "issuer_ls180.v:99759.3-99771.6" - wire $0\dec31_dec_sub4_lk[0:0] - attribute \src "issuer_ls180.v:99837.3-99849.6" - wire width 2 $0\dec31_dec_sub4_out_sel[1:0] - attribute \src "issuer_ls180.v:99603.3-99615.6" - wire width 2 $0\dec31_dec_sub4_rc_sel[1:0] - attribute \src "issuer_ls180.v:99720.3-99732.6" - wire $0\dec31_dec_sub4_rsrv[0:0] - attribute \src "issuer_ls180.v:99772.3-99784.6" - wire $0\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:99746.3-99758.6" - wire $0\dec31_dec_sub4_sgn[0:0] - attribute \src "issuer_ls180.v:99694.3-99706.6" - wire $0\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "issuer_ls180.v:99590.3-99602.6" - wire width 2 $0\dec31_dec_sub4_upd[1:0] - attribute \src "issuer_ls180.v:99307.7-99307.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:99629.3-99641.6" - wire width 8 $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "issuer_ls180.v:99681.3-99693.6" - wire $1\dec31_dec_sub4_br[0:0] - attribute \src "issuer_ls180.v:99850.3-99862.6" - wire width 3 $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "issuer_ls180.v:99863.3-99875.6" - wire width 3 $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "issuer_ls180.v:99616.3-99628.6" - wire width 2 $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "issuer_ls180.v:99668.3-99680.6" - wire $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "issuer_ls180.v:99785.3-99797.6" - wire width 5 $1\dec31_dec_sub4_form[4:0] - attribute \src "issuer_ls180.v:99564.3-99576.6" - wire width 12 $1\dec31_dec_sub4_function_unit[11:0] - attribute \src "issuer_ls180.v:99798.3-99810.6" - wire width 3 $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "issuer_ls180.v:99811.3-99823.6" - wire width 4 $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "issuer_ls180.v:99824.3-99836.6" - wire width 2 $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "issuer_ls180.v:99707.3-99719.6" - wire width 7 $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "issuer_ls180.v:99642.3-99654.6" - wire $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "issuer_ls180.v:99655.3-99667.6" - wire $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "issuer_ls180.v:99733.3-99745.6" - wire $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "issuer_ls180.v:99577.3-99589.6" - wire width 4 $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "issuer_ls180.v:99759.3-99771.6" - wire $1\dec31_dec_sub4_lk[0:0] - attribute \src "issuer_ls180.v:99837.3-99849.6" - wire width 2 $1\dec31_dec_sub4_out_sel[1:0] - attribute \src "issuer_ls180.v:99603.3-99615.6" - wire width 2 $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "issuer_ls180.v:99720.3-99732.6" - wire $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "issuer_ls180.v:99772.3-99784.6" - wire $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:99746.3-99758.6" - wire $1\dec31_dec_sub4_sgn[0:0] - attribute \src "issuer_ls180.v:99694.3-99706.6" - wire $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "issuer_ls180.v:99590.3-99602.6" - wire width 2 $1\dec31_dec_sub4_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub4_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub4_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub4_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub4_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub4_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub4_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub4_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub4_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub4_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub4_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub4_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub4_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub4_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub4_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub4_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub4_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub4_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub4_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub4_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub4_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub4_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub4_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub4_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub4_upd - attribute \src "issuer_ls180.v:99307.7-99307.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:99307.7-99307.20" - process $proc$issuer_ls180.v:99307$3995 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:99564.3-99576.6" - process $proc$issuer_ls180.v:99564$3971 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_function_unit[11:0] $1\dec31_dec_sub4_function_unit[11:0] - attribute \src "issuer_ls180.v:99565.5-99565.29" - switch \initial - attribute \src "issuer_ls180.v:99565.9-99565.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000 - case - assign $1\dec31_dec_sub4_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[11:0] - end - attribute \src "issuer_ls180.v:99577.3-99589.6" - process $proc$issuer_ls180.v:99577$3972 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "issuer_ls180.v:99578.5-99578.29" - switch \initial - attribute \src "issuer_ls180.v:99578.9-99578.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:99590.3-99602.6" - process $proc$issuer_ls180.v:99590$3973 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] - attribute \src "issuer_ls180.v:99591.5-99591.29" - switch \initial - attribute \src "issuer_ls180.v:99591.9-99591.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub4_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] - end - attribute \src "issuer_ls180.v:99603.3-99615.6" - process $proc$issuer_ls180.v:99603$3974 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "issuer_ls180.v:99604.5-99604.29" - switch \initial - attribute \src "issuer_ls180.v:99604.9-99604.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:99616.3-99628.6" - process $proc$issuer_ls180.v:99616$3975 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "issuer_ls180.v:99617.5-99617.29" - switch \initial - attribute \src "issuer_ls180.v:99617.9-99617.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0] - end - attribute \src "issuer_ls180.v:99629.3-99641.6" - process $proc$issuer_ls180.v:99629$3976 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "issuer_ls180.v:99630.5-99630.29" - switch \initial - attribute \src "issuer_ls180.v:99630.9-99630.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001110 - case - assign $1\dec31_dec_sub4_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0] - end - attribute \src "issuer_ls180.v:99642.3-99654.6" - process $proc$issuer_ls180.v:99642$3977 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "issuer_ls180.v:99643.5-99643.29" - switch \initial - attribute \src "issuer_ls180.v:99643.9-99643.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0] - end - attribute \src "issuer_ls180.v:99655.3-99667.6" - process $proc$issuer_ls180.v:99655$3978 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "issuer_ls180.v:99656.5-99656.29" - switch \initial - attribute \src "issuer_ls180.v:99656.9-99656.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0] - end - attribute \src "issuer_ls180.v:99668.3-99680.6" - process $proc$issuer_ls180.v:99668$3979 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "issuer_ls180.v:99669.5-99669.29" - switch \initial - attribute \src "issuer_ls180.v:99669.9-99669.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0] - end - attribute \src "issuer_ls180.v:99681.3-99693.6" - process $proc$issuer_ls180.v:99681$3980 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0] - attribute \src "issuer_ls180.v:99682.5-99682.29" - switch \initial - attribute \src "issuer_ls180.v:99682.9-99682.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_br[0:0] 1'0 - case - assign $1\dec31_dec_sub4_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0] - end - attribute \src "issuer_ls180.v:99694.3-99706.6" - process $proc$issuer_ls180.v:99694$3981 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "issuer_ls180.v:99695.5-99695.29" - switch \initial - attribute \src "issuer_ls180.v:99695.9-99695.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:99707.3-99719.6" - process $proc$issuer_ls180.v:99707$3982 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "issuer_ls180.v:99708.5-99708.29" - switch \initial - attribute \src "issuer_ls180.v:99708.9-99708.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 - case - assign $1\dec31_dec_sub4_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] - end - attribute \src "issuer_ls180.v:99720.3-99732.6" - process $proc$issuer_ls180.v:99720$3983 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "issuer_ls180.v:99721.5-99721.29" - switch \initial - attribute \src "issuer_ls180.v:99721.9-99721.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0] - end - attribute \src "issuer_ls180.v:99733.3-99745.6" - process $proc$issuer_ls180.v:99733$3984 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "issuer_ls180.v:99734.5-99734.29" - switch \initial - attribute \src "issuer_ls180.v:99734.9-99734.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_is_32b[0:0] 1'1 - case - assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] - end - attribute \src "issuer_ls180.v:99746.3-99758.6" - process $proc$issuer_ls180.v:99746$3985 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0] - attribute \src "issuer_ls180.v:99747.5-99747.29" - switch \initial - attribute \src "issuer_ls180.v:99747.9-99747.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub4_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0] - end - attribute \src "issuer_ls180.v:99759.3-99771.6" - process $proc$issuer_ls180.v:99759$3986 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0] - attribute \src "issuer_ls180.v:99760.5-99760.29" - switch \initial - attribute \src "issuer_ls180.v:99760.9-99760.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub4_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0] - end - attribute \src "issuer_ls180.v:99772.3-99784.6" - process $proc$issuer_ls180.v:99772$3987 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:99773.5-99773.29" - switch \initial - attribute \src "issuer_ls180.v:99773.9-99773.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 - case - assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0] - end - attribute \src "issuer_ls180.v:99785.3-99797.6" - process $proc$issuer_ls180.v:99785$3988 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] - attribute \src "issuer_ls180.v:99786.5-99786.29" - switch \initial - attribute \src "issuer_ls180.v:99786.9-99786.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub4_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] - end - attribute \src "issuer_ls180.v:99798.3-99810.6" - process $proc$issuer_ls180.v:99798$3989 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "issuer_ls180.v:99799.5-99799.29" - switch \initial - attribute \src "issuer_ls180.v:99799.9-99799.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 - case - assign $1\dec31_dec_sub4_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:99811.3-99823.6" - process $proc$issuer_ls180.v:99811$3990 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "issuer_ls180.v:99812.5-99812.29" - switch \initial - attribute \src "issuer_ls180.v:99812.9-99812.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:99824.3-99836.6" - process $proc$issuer_ls180.v:99824$3991 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "issuer_ls180.v:99825.5-99825.29" - switch \initial - attribute \src "issuer_ls180.v:99825.9-99825.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0] - end - attribute \src "issuer_ls180.v:99837.3-99849.6" - process $proc$issuer_ls180.v:99837$3992 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_out_sel[1:0] $1\dec31_dec_sub4_out_sel[1:0] - attribute \src "issuer_ls180.v:99838.5-99838.29" - switch \initial - attribute \src "issuer_ls180.v:99838.9-99838.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub4_out_sel $0\dec31_dec_sub4_out_sel[1:0] - end - attribute \src "issuer_ls180.v:99850.3-99862.6" - process $proc$issuer_ls180.v:99850$3993 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "issuer_ls180.v:99851.5-99851.29" - switch \initial - attribute \src "issuer_ls180.v:99851.9-99851.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0] - end - attribute \src "issuer_ls180.v:99863.3-99875.6" - process $proc$issuer_ls180.v:99863$3994 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "issuer_ls180.v:99864.5-99864.29" - switch \initial - attribute \src "issuer_ls180.v:99864.9-99864.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:99881.1-101172.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub8" -attribute \generator "nMigen" -module \dec31_dec_sub8 - attribute \src "issuer_ls180.v:100354.3-100396.6" - wire width 8 $0\dec31_dec_sub8_asmcode[7:0] - attribute \src "issuer_ls180.v:100526.3-100568.6" - wire $0\dec31_dec_sub8_br[0:0] - attribute \src "issuer_ls180.v:101085.3-101127.6" - wire width 3 $0\dec31_dec_sub8_cr_in[2:0] - attribute \src "issuer_ls180.v:101128.3-101170.6" - wire width 3 $0\dec31_dec_sub8_cr_out[2:0] - attribute \src "issuer_ls180.v:100311.3-100353.6" - wire width 2 $0\dec31_dec_sub8_cry_in[1:0] - attribute \src "issuer_ls180.v:100483.3-100525.6" - wire $0\dec31_dec_sub8_cry_out[0:0] - attribute \src "issuer_ls180.v:100870.3-100912.6" - wire width 5 $0\dec31_dec_sub8_form[4:0] - attribute \src "issuer_ls180.v:100139.3-100181.6" - wire width 12 $0\dec31_dec_sub8_function_unit[11:0] - attribute \src "issuer_ls180.v:100913.3-100955.6" - wire width 3 $0\dec31_dec_sub8_in1_sel[2:0] - attribute \src "issuer_ls180.v:100956.3-100998.6" - wire width 4 $0\dec31_dec_sub8_in2_sel[3:0] - attribute \src "issuer_ls180.v:100999.3-101041.6" - wire width 2 $0\dec31_dec_sub8_in3_sel[1:0] - attribute \src "issuer_ls180.v:100612.3-100654.6" - wire width 7 $0\dec31_dec_sub8_internal_op[6:0] - attribute \src "issuer_ls180.v:100397.3-100439.6" - wire $0\dec31_dec_sub8_inv_a[0:0] - attribute \src "issuer_ls180.v:100440.3-100482.6" - wire $0\dec31_dec_sub8_inv_out[0:0] - attribute \src "issuer_ls180.v:100698.3-100740.6" - wire $0\dec31_dec_sub8_is_32b[0:0] - attribute \src "issuer_ls180.v:100182.3-100224.6" - wire width 4 $0\dec31_dec_sub8_ldst_len[3:0] - attribute \src "issuer_ls180.v:100784.3-100826.6" - wire $0\dec31_dec_sub8_lk[0:0] - attribute \src "issuer_ls180.v:101042.3-101084.6" - wire width 2 $0\dec31_dec_sub8_out_sel[1:0] - attribute \src "issuer_ls180.v:100268.3-100310.6" - wire width 2 $0\dec31_dec_sub8_rc_sel[1:0] - attribute \src "issuer_ls180.v:100655.3-100697.6" - wire $0\dec31_dec_sub8_rsrv[0:0] - attribute \src "issuer_ls180.v:100827.3-100869.6" - wire $0\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:100741.3-100783.6" - wire $0\dec31_dec_sub8_sgn[0:0] - attribute \src "issuer_ls180.v:100569.3-100611.6" - wire $0\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "issuer_ls180.v:100225.3-100267.6" - wire width 2 $0\dec31_dec_sub8_upd[1:0] - attribute \src "issuer_ls180.v:99882.7-99882.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:100354.3-100396.6" - wire width 8 $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "issuer_ls180.v:100526.3-100568.6" - wire $1\dec31_dec_sub8_br[0:0] - attribute \src "issuer_ls180.v:101085.3-101127.6" - wire width 3 $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "issuer_ls180.v:101128.3-101170.6" - wire width 3 $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "issuer_ls180.v:100311.3-100353.6" - wire width 2 $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "issuer_ls180.v:100483.3-100525.6" - wire $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "issuer_ls180.v:100870.3-100912.6" - wire width 5 $1\dec31_dec_sub8_form[4:0] - attribute \src "issuer_ls180.v:100139.3-100181.6" - wire width 12 $1\dec31_dec_sub8_function_unit[11:0] - attribute \src "issuer_ls180.v:100913.3-100955.6" - wire width 3 $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "issuer_ls180.v:100956.3-100998.6" - wire width 4 $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "issuer_ls180.v:100999.3-101041.6" - wire width 2 $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "issuer_ls180.v:100612.3-100654.6" - wire width 7 $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "issuer_ls180.v:100397.3-100439.6" - wire $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "issuer_ls180.v:100440.3-100482.6" - wire $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "issuer_ls180.v:100698.3-100740.6" - wire $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "issuer_ls180.v:100182.3-100224.6" - wire width 4 $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "issuer_ls180.v:100784.3-100826.6" - wire $1\dec31_dec_sub8_lk[0:0] - attribute \src "issuer_ls180.v:101042.3-101084.6" - wire width 2 $1\dec31_dec_sub8_out_sel[1:0] - attribute \src "issuer_ls180.v:100268.3-100310.6" - wire width 2 $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "issuer_ls180.v:100655.3-100697.6" - wire $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "issuer_ls180.v:100827.3-100869.6" - wire $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:100741.3-100783.6" - wire $1\dec31_dec_sub8_sgn[0:0] - attribute \src "issuer_ls180.v:100569.3-100611.6" - wire $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "issuer_ls180.v:100225.3-100267.6" - wire width 2 $1\dec31_dec_sub8_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub8_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub8_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub8_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub8_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub8_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub8_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub8_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub8_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub8_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub8_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub8_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub8_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub8_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub8_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub8_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub8_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub8_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub8_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub8_upd - attribute \src "issuer_ls180.v:99882.7-99882.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:100139.3-100181.6" - process $proc$issuer_ls180.v:100139$3996 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_function_unit[11:0] $1\dec31_dec_sub8_function_unit[11:0] - attribute \src "issuer_ls180.v:100140.5-100140.29" - switch \initial - attribute \src "issuer_ls180.v:100140.9-100140.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - case - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[11:0] - end - attribute \src "issuer_ls180.v:100182.3-100224.6" - process $proc$issuer_ls180.v:100182$3997 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "issuer_ls180.v:100183.5-100183.29" - switch \initial - attribute \src "issuer_ls180.v:100183.9-100183.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:100225.3-100267.6" - process $proc$issuer_ls180.v:100225$3998 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] - attribute \src "issuer_ls180.v:100226.5-100226.29" - switch \initial - attribute \src "issuer_ls180.v:100226.9-100226.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] - end - attribute \src "issuer_ls180.v:100268.3-100310.6" - process $proc$issuer_ls180.v:100268$3999 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "issuer_ls180.v:100269.5-100269.29" - switch \initial - attribute \src "issuer_ls180.v:100269.9-100269.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:100311.3-100353.6" - process $proc$issuer_ls180.v:100311$4000 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "issuer_ls180.v:100312.5-100312.29" - switch \initial - attribute \src "issuer_ls180.v:100312.9-100312.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 - case - assign $1\dec31_dec_sub8_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0] - end - attribute \src "issuer_ls180.v:100354.3-100396.6" - process $proc$issuer_ls180.v:100354$4001 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "issuer_ls180.v:100355.5-100355.29" - switch \initial - attribute \src "issuer_ls180.v:100355.9-100355.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11001000 - case - assign $1\dec31_dec_sub8_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0] - end - attribute \src "issuer_ls180.v:100397.3-100439.6" - process $proc$issuer_ls180.v:100397$4002 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "issuer_ls180.v:100398.5-100398.29" - switch \initial - attribute \src "issuer_ls180.v:100398.9-100398.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - case - assign $1\dec31_dec_sub8_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0] - end - attribute \src "issuer_ls180.v:100440.3-100482.6" - process $proc$issuer_ls180.v:100440$4003 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "issuer_ls180.v:100441.5-100441.29" - switch \initial - attribute \src "issuer_ls180.v:100441.9-100441.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0] - end - attribute \src "issuer_ls180.v:100483.3-100525.6" - process $proc$issuer_ls180.v:100483$4004 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "issuer_ls180.v:100484.5-100484.29" - switch \initial - attribute \src "issuer_ls180.v:100484.9-100484.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - case - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0] - end - attribute \src "issuer_ls180.v:100526.3-100568.6" - process $proc$issuer_ls180.v:100526$4005 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0] - attribute \src "issuer_ls180.v:100527.5-100527.29" - switch \initial - attribute \src "issuer_ls180.v:100527.9-100527.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - case - assign $1\dec31_dec_sub8_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0] - end - attribute \src "issuer_ls180.v:100569.3-100611.6" - process $proc$issuer_ls180.v:100569$4006 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "issuer_ls180.v:100570.5-100570.29" - switch \initial - attribute \src "issuer_ls180.v:100570.9-100570.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:100612.3-100654.6" - process $proc$issuer_ls180.v:100612$4007 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "issuer_ls180.v:100613.5-100613.29" - switch \initial - attribute \src "issuer_ls180.v:100613.9-100613.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - case - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] - end - attribute \src "issuer_ls180.v:100655.3-100697.6" - process $proc$issuer_ls180.v:100655$4008 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "issuer_ls180.v:100656.5-100656.29" - switch \initial - attribute \src "issuer_ls180.v:100656.9-100656.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0] - end - attribute \src "issuer_ls180.v:100698.3-100740.6" - process $proc$issuer_ls180.v:100698$4009 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "issuer_ls180.v:100699.5-100699.29" - switch \initial - attribute \src "issuer_ls180.v:100699.9-100699.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] - end - attribute \src "issuer_ls180.v:100741.3-100783.6" - process $proc$issuer_ls180.v:100741$4010 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0] - attribute \src "issuer_ls180.v:100742.5-100742.29" - switch \initial - attribute \src "issuer_ls180.v:100742.9-100742.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0] - end - attribute \src "issuer_ls180.v:100784.3-100826.6" - process $proc$issuer_ls180.v:100784$4011 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0] - attribute \src "issuer_ls180.v:100785.5-100785.29" - switch \initial - attribute \src "issuer_ls180.v:100785.9-100785.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0] - end - attribute \src "issuer_ls180.v:100827.3-100869.6" - process $proc$issuer_ls180.v:100827$4012 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:100828.5-100828.29" - switch \initial - attribute \src "issuer_ls180.v:100828.9-100828.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0] - end - attribute \src "issuer_ls180.v:100870.3-100912.6" - process $proc$issuer_ls180.v:100870$4013 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] - attribute \src "issuer_ls180.v:100871.5-100871.29" - switch \initial - attribute \src "issuer_ls180.v:100871.9-100871.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - case - assign $1\dec31_dec_sub8_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] - end - attribute \src "issuer_ls180.v:100913.3-100955.6" - process $proc$issuer_ls180.v:100913$4014 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "issuer_ls180.v:100914.5-100914.29" - switch \initial - attribute \src "issuer_ls180.v:100914.9-100914.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - case - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:100956.3-100998.6" - process $proc$issuer_ls180.v:100956$4015 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "issuer_ls180.v:100957.5-100957.29" - switch \initial - attribute \src "issuer_ls180.v:100957.9-100957.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 - case - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:100999.3-101041.6" - process $proc$issuer_ls180.v:100999$4016 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "issuer_ls180.v:101000.5-101000.29" - switch \initial - attribute \src "issuer_ls180.v:101000.9-101000.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0] - end - attribute \src "issuer_ls180.v:101042.3-101084.6" - process $proc$issuer_ls180.v:101042$4017 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_out_sel[1:0] $1\dec31_dec_sub8_out_sel[1:0] - attribute \src "issuer_ls180.v:101043.5-101043.29" - switch \initial - attribute \src "issuer_ls180.v:101043.9-101043.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub8_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub8_out_sel $0\dec31_dec_sub8_out_sel[1:0] - end - attribute \src "issuer_ls180.v:101085.3-101127.6" - process $proc$issuer_ls180.v:101085$4018 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "issuer_ls180.v:101086.5-101086.29" - switch \initial - attribute \src "issuer_ls180.v:101086.9-101086.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0] - end - attribute \src "issuer_ls180.v:101128.3-101170.6" - process $proc$issuer_ls180.v:101128$4019 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "issuer_ls180.v:101129.5-101129.29" - switch \initial - attribute \src "issuer_ls180.v:101129.9-101129.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0] - end - attribute \src "issuer_ls180.v:99882.7-99882.20" - process $proc$issuer_ls180.v:99882$4020 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:101176.1-102755.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub9" -attribute \generator "nMigen" -module \dec31_dec_sub9 - attribute \src "issuer_ls180.v:101709.3-101763.6" - wire width 8 $0\dec31_dec_sub9_asmcode[7:0] - attribute \src "issuer_ls180.v:101929.3-101983.6" - wire $0\dec31_dec_sub9_br[0:0] - attribute \src "issuer_ls180.v:102644.3-102698.6" - wire width 3 $0\dec31_dec_sub9_cr_in[2:0] - attribute \src "issuer_ls180.v:102699.3-102753.6" - wire width 3 $0\dec31_dec_sub9_cr_out[2:0] - attribute \src "issuer_ls180.v:101654.3-101708.6" - wire width 2 $0\dec31_dec_sub9_cry_in[1:0] - attribute \src "issuer_ls180.v:101874.3-101928.6" - wire $0\dec31_dec_sub9_cry_out[0:0] - attribute \src "issuer_ls180.v:102369.3-102423.6" - wire width 5 $0\dec31_dec_sub9_form[4:0] - attribute \src "issuer_ls180.v:101434.3-101488.6" - wire width 12 $0\dec31_dec_sub9_function_unit[11:0] - attribute \src "issuer_ls180.v:102424.3-102478.6" - wire width 3 $0\dec31_dec_sub9_in1_sel[2:0] - attribute \src "issuer_ls180.v:102479.3-102533.6" - wire width 4 $0\dec31_dec_sub9_in2_sel[3:0] - attribute \src "issuer_ls180.v:102534.3-102588.6" - wire width 2 $0\dec31_dec_sub9_in3_sel[1:0] - attribute \src "issuer_ls180.v:102039.3-102093.6" - wire width 7 $0\dec31_dec_sub9_internal_op[6:0] - attribute \src "issuer_ls180.v:101764.3-101818.6" - wire $0\dec31_dec_sub9_inv_a[0:0] - attribute \src "issuer_ls180.v:101819.3-101873.6" - wire $0\dec31_dec_sub9_inv_out[0:0] - attribute \src "issuer_ls180.v:102149.3-102203.6" - wire $0\dec31_dec_sub9_is_32b[0:0] - attribute \src "issuer_ls180.v:101489.3-101543.6" - wire width 4 $0\dec31_dec_sub9_ldst_len[3:0] - attribute \src "issuer_ls180.v:102259.3-102313.6" - wire $0\dec31_dec_sub9_lk[0:0] - attribute \src "issuer_ls180.v:102589.3-102643.6" - wire width 2 $0\dec31_dec_sub9_out_sel[1:0] - attribute \src "issuer_ls180.v:101599.3-101653.6" - wire width 2 $0\dec31_dec_sub9_rc_sel[1:0] - attribute \src "issuer_ls180.v:102094.3-102148.6" - wire $0\dec31_dec_sub9_rsrv[0:0] - attribute \src "issuer_ls180.v:102314.3-102368.6" - wire $0\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:102204.3-102258.6" - wire $0\dec31_dec_sub9_sgn[0:0] - attribute \src "issuer_ls180.v:101984.3-102038.6" - wire $0\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "issuer_ls180.v:101544.3-101598.6" - wire width 2 $0\dec31_dec_sub9_upd[1:0] - attribute \src "issuer_ls180.v:101177.7-101177.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:101709.3-101763.6" - wire width 8 $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "issuer_ls180.v:101929.3-101983.6" - wire $1\dec31_dec_sub9_br[0:0] - attribute \src "issuer_ls180.v:102644.3-102698.6" - wire width 3 $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "issuer_ls180.v:102699.3-102753.6" - wire width 3 $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "issuer_ls180.v:101654.3-101708.6" - wire width 2 $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "issuer_ls180.v:101874.3-101928.6" - wire $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "issuer_ls180.v:102369.3-102423.6" - wire width 5 $1\dec31_dec_sub9_form[4:0] - attribute \src "issuer_ls180.v:101434.3-101488.6" - wire width 12 $1\dec31_dec_sub9_function_unit[11:0] - attribute \src "issuer_ls180.v:102424.3-102478.6" - wire width 3 $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "issuer_ls180.v:102479.3-102533.6" - wire width 4 $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "issuer_ls180.v:102534.3-102588.6" - wire width 2 $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "issuer_ls180.v:102039.3-102093.6" - wire width 7 $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "issuer_ls180.v:101764.3-101818.6" - wire $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "issuer_ls180.v:101819.3-101873.6" - wire $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "issuer_ls180.v:102149.3-102203.6" - wire $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "issuer_ls180.v:101489.3-101543.6" - wire width 4 $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "issuer_ls180.v:102259.3-102313.6" - wire $1\dec31_dec_sub9_lk[0:0] - attribute \src "issuer_ls180.v:102589.3-102643.6" - wire width 2 $1\dec31_dec_sub9_out_sel[1:0] - attribute \src "issuer_ls180.v:101599.3-101653.6" - wire width 2 $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "issuer_ls180.v:102094.3-102148.6" - wire $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "issuer_ls180.v:102314.3-102368.6" - wire $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:102204.3-102258.6" - wire $1\dec31_dec_sub9_sgn[0:0] - attribute \src "issuer_ls180.v:101984.3-102038.6" - wire $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "issuer_ls180.v:101544.3-101598.6" - wire width 2 $1\dec31_dec_sub9_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec31_dec_sub9_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec31_dec_sub9_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec31_dec_sub9_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec31_dec_sub9_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec31_dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec31_dec_sub9_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec31_dec_sub9_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec31_dec_sub9_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec31_dec_sub9_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec31_dec_sub9_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec31_dec_sub9_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec31_dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec31_dec_sub9_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec31_dec_sub9_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec31_dec_sub9_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec31_dec_sub9_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec31_dec_sub9_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec31_dec_sub9_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec31_dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec31_dec_sub9_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec31_dec_sub9_upd - attribute \src "issuer_ls180.v:101177.7-101177.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 5 \opcode_switch - attribute \src "issuer_ls180.v:101177.7-101177.20" - process $proc$issuer_ls180.v:101177$4045 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:101434.3-101488.6" - process $proc$issuer_ls180.v:101434$4021 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_function_unit[11:0] $1\dec31_dec_sub9_function_unit[11:0] - attribute \src "issuer_ls180.v:101435.5-101435.29" - switch \initial - attribute \src "issuer_ls180.v:101435.9-101435.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - case - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[11:0] - end - attribute \src "issuer_ls180.v:101489.3-101543.6" - process $proc$issuer_ls180.v:101489$4022 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "issuer_ls180.v:101490.5-101490.29" - switch \initial - attribute \src "issuer_ls180.v:101490.9-101490.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:101544.3-101598.6" - process $proc$issuer_ls180.v:101544$4023 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] - attribute \src "issuer_ls180.v:101545.5-101545.29" - switch \initial - attribute \src "issuer_ls180.v:101545.9-101545.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] - end - attribute \src "issuer_ls180.v:101599.3-101653.6" - process $proc$issuer_ls180.v:101599$4024 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "issuer_ls180.v:101600.5-101600.29" - switch \initial - attribute \src "issuer_ls180.v:101600.9-101600.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:101654.3-101708.6" - process $proc$issuer_ls180.v:101654$4025 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "issuer_ls180.v:101655.5-101655.29" - switch \initial - attribute \src "issuer_ls180.v:101655.9-101655.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0] - end - attribute \src "issuer_ls180.v:101709.3-101763.6" - process $proc$issuer_ls180.v:101709$4026 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "issuer_ls180.v:101710.5-101710.29" - switch \initial - attribute \src "issuer_ls180.v:101710.9-101710.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111111 - case - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0] - end - attribute \src "issuer_ls180.v:101764.3-101818.6" - process $proc$issuer_ls180.v:101764$4027 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "issuer_ls180.v:101765.5-101765.29" - switch \initial - attribute \src "issuer_ls180.v:101765.9-101765.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0] - end - attribute \src "issuer_ls180.v:101819.3-101873.6" - process $proc$issuer_ls180.v:101819$4028 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "issuer_ls180.v:101820.5-101820.29" - switch \initial - attribute \src "issuer_ls180.v:101820.9-101820.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0] - end - attribute \src "issuer_ls180.v:101874.3-101928.6" - process $proc$issuer_ls180.v:101874$4029 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "issuer_ls180.v:101875.5-101875.29" - switch \initial - attribute \src "issuer_ls180.v:101875.9-101875.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0] - end - attribute \src "issuer_ls180.v:101929.3-101983.6" - process $proc$issuer_ls180.v:101929$4030 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0] - attribute \src "issuer_ls180.v:101930.5-101930.29" - switch \initial - attribute \src "issuer_ls180.v:101930.9-101930.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - case - assign $1\dec31_dec_sub9_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0] - end - attribute \src "issuer_ls180.v:101984.3-102038.6" - process $proc$issuer_ls180.v:101984$4031 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "issuer_ls180.v:101985.5-101985.29" - switch \initial - attribute \src "issuer_ls180.v:101985.9-101985.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:102039.3-102093.6" - process $proc$issuer_ls180.v:102039$4032 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "issuer_ls180.v:102040.5-102040.29" - switch \initial - attribute \src "issuer_ls180.v:102040.9-102040.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 - case - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] - end - attribute \src "issuer_ls180.v:102094.3-102148.6" - process $proc$issuer_ls180.v:102094$4033 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "issuer_ls180.v:102095.5-102095.29" - switch \initial - attribute \src "issuer_ls180.v:102095.9-102095.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0] - end - attribute \src "issuer_ls180.v:102149.3-102203.6" - process $proc$issuer_ls180.v:102149$4034 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "issuer_ls180.v:102150.5-102150.29" - switch \initial - attribute \src "issuer_ls180.v:102150.9-102150.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] - end - attribute \src "issuer_ls180.v:102204.3-102258.6" - process $proc$issuer_ls180.v:102204$4035 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0] - attribute \src "issuer_ls180.v:102205.5-102205.29" - switch \initial - attribute \src "issuer_ls180.v:102205.9-102205.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - case - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0] - end - attribute \src "issuer_ls180.v:102259.3-102313.6" - process $proc$issuer_ls180.v:102259$4036 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0] - attribute \src "issuer_ls180.v:102260.5-102260.29" - switch \initial - attribute \src "issuer_ls180.v:102260.9-102260.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0] - end - attribute \src "issuer_ls180.v:102314.3-102368.6" - process $proc$issuer_ls180.v:102314$4037 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:102315.5-102315.29" - switch \initial - attribute \src "issuer_ls180.v:102315.9-102315.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0] - end - attribute \src "issuer_ls180.v:102369.3-102423.6" - process $proc$issuer_ls180.v:102369$4038 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] - attribute \src "issuer_ls180.v:102370.5-102370.29" - switch \initial - attribute \src "issuer_ls180.v:102370.9-102370.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'01000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - case - assign $1\dec31_dec_sub9_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] - end - attribute \src "issuer_ls180.v:102424.3-102478.6" - process $proc$issuer_ls180.v:102424$4039 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "issuer_ls180.v:102425.5-102425.29" - switch \initial - attribute \src "issuer_ls180.v:102425.9-102425.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - case - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:102479.3-102533.6" - process $proc$issuer_ls180.v:102479$4040 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "issuer_ls180.v:102480.5-102480.29" - switch \initial - attribute \src "issuer_ls180.v:102480.9-102480.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:102534.3-102588.6" - process $proc$issuer_ls180.v:102534$4041 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "issuer_ls180.v:102535.5-102535.29" - switch \initial - attribute \src "issuer_ls180.v:102535.9-102535.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0] - end - attribute \src "issuer_ls180.v:102589.3-102643.6" - process $proc$issuer_ls180.v:102589$4042 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_out_sel[1:0] $1\dec31_dec_sub9_out_sel[1:0] - attribute \src "issuer_ls180.v:102590.5-102590.29" - switch \initial - attribute \src "issuer_ls180.v:102590.9-102590.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub9_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub9_out_sel $0\dec31_dec_sub9_out_sel[1:0] - end - attribute \src "issuer_ls180.v:102644.3-102698.6" - process $proc$issuer_ls180.v:102644$4043 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "issuer_ls180.v:102645.5-102645.29" - switch \initial - attribute \src "issuer_ls180.v:102645.9-102645.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0] - end - attribute \src "issuer_ls180.v:102699.3-102753.6" - process $proc$issuer_ls180.v:102699$4044 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "issuer_ls180.v:102700.5-102700.29" - switch \initial - attribute \src "issuer_ls180.v:102700.9-102700.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "issuer_ls180.v:102759.1-103402.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec58" -attribute \generator "nMigen" -module \dec58 - attribute \src "issuer_ls180.v:103097.3-103112.6" - wire width 8 $0\dec58_asmcode[7:0] - attribute \src "issuer_ls180.v:103161.3-103176.6" - wire $0\dec58_br[0:0] - attribute \src "issuer_ls180.v:103369.3-103384.6" - wire width 3 $0\dec58_cr_in[2:0] - attribute \src "issuer_ls180.v:103385.3-103400.6" - wire width 3 $0\dec58_cr_out[2:0] - attribute \src "issuer_ls180.v:103081.3-103096.6" - wire width 2 $0\dec58_cry_in[1:0] - attribute \src "issuer_ls180.v:103145.3-103160.6" - wire $0\dec58_cry_out[0:0] - attribute \src "issuer_ls180.v:103289.3-103304.6" - wire width 5 $0\dec58_form[4:0] - attribute \src "issuer_ls180.v:103017.3-103032.6" - wire width 12 $0\dec58_function_unit[11:0] - attribute \src "issuer_ls180.v:103305.3-103320.6" - wire width 3 $0\dec58_in1_sel[2:0] - attribute \src "issuer_ls180.v:103321.3-103336.6" - wire width 4 $0\dec58_in2_sel[3:0] - attribute \src "issuer_ls180.v:103337.3-103352.6" - wire width 2 $0\dec58_in3_sel[1:0] - attribute \src "issuer_ls180.v:103193.3-103208.6" - wire width 7 $0\dec58_internal_op[6:0] - attribute \src "issuer_ls180.v:103113.3-103128.6" - wire $0\dec58_inv_a[0:0] - attribute \src "issuer_ls180.v:103129.3-103144.6" - wire $0\dec58_inv_out[0:0] - attribute \src "issuer_ls180.v:103225.3-103240.6" - wire $0\dec58_is_32b[0:0] - attribute \src "issuer_ls180.v:103033.3-103048.6" - wire width 4 $0\dec58_ldst_len[3:0] - attribute \src "issuer_ls180.v:103257.3-103272.6" - wire $0\dec58_lk[0:0] - attribute \src "issuer_ls180.v:103353.3-103368.6" - wire width 2 $0\dec58_out_sel[1:0] - attribute \src "issuer_ls180.v:103065.3-103080.6" - wire width 2 $0\dec58_rc_sel[1:0] - attribute \src "issuer_ls180.v:103209.3-103224.6" - wire $0\dec58_rsrv[0:0] - attribute \src "issuer_ls180.v:103273.3-103288.6" - wire $0\dec58_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:103241.3-103256.6" - wire $0\dec58_sgn[0:0] - attribute \src "issuer_ls180.v:103177.3-103192.6" - wire $0\dec58_sgn_ext[0:0] - attribute \src "issuer_ls180.v:103049.3-103064.6" - wire width 2 $0\dec58_upd[1:0] - attribute \src "issuer_ls180.v:102760.7-102760.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:103097.3-103112.6" - wire width 8 $1\dec58_asmcode[7:0] - attribute \src "issuer_ls180.v:103161.3-103176.6" - wire $1\dec58_br[0:0] - attribute \src "issuer_ls180.v:103369.3-103384.6" - wire width 3 $1\dec58_cr_in[2:0] - attribute \src "issuer_ls180.v:103385.3-103400.6" - wire width 3 $1\dec58_cr_out[2:0] - attribute \src "issuer_ls180.v:103081.3-103096.6" - wire width 2 $1\dec58_cry_in[1:0] - attribute \src "issuer_ls180.v:103145.3-103160.6" - wire $1\dec58_cry_out[0:0] - attribute \src "issuer_ls180.v:103289.3-103304.6" - wire width 5 $1\dec58_form[4:0] - attribute \src "issuer_ls180.v:103017.3-103032.6" - wire width 12 $1\dec58_function_unit[11:0] - attribute \src "issuer_ls180.v:103305.3-103320.6" - wire width 3 $1\dec58_in1_sel[2:0] - attribute \src "issuer_ls180.v:103321.3-103336.6" - wire width 4 $1\dec58_in2_sel[3:0] - attribute \src "issuer_ls180.v:103337.3-103352.6" - wire width 2 $1\dec58_in3_sel[1:0] - attribute \src "issuer_ls180.v:103193.3-103208.6" - wire width 7 $1\dec58_internal_op[6:0] - attribute \src "issuer_ls180.v:103113.3-103128.6" - wire $1\dec58_inv_a[0:0] - attribute \src "issuer_ls180.v:103129.3-103144.6" - wire $1\dec58_inv_out[0:0] - attribute \src "issuer_ls180.v:103225.3-103240.6" - wire $1\dec58_is_32b[0:0] - attribute \src "issuer_ls180.v:103033.3-103048.6" - wire width 4 $1\dec58_ldst_len[3:0] - attribute \src "issuer_ls180.v:103257.3-103272.6" - wire $1\dec58_lk[0:0] - attribute \src "issuer_ls180.v:103353.3-103368.6" - wire width 2 $1\dec58_out_sel[1:0] - attribute \src "issuer_ls180.v:103065.3-103080.6" - wire width 2 $1\dec58_rc_sel[1:0] - attribute \src "issuer_ls180.v:103209.3-103224.6" - wire $1\dec58_rsrv[0:0] - attribute \src "issuer_ls180.v:103273.3-103288.6" - wire $1\dec58_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:103241.3-103256.6" - wire $1\dec58_sgn[0:0] - attribute \src "issuer_ls180.v:103177.3-103192.6" - wire $1\dec58_sgn_ext[0:0] - attribute \src "issuer_ls180.v:103049.3-103064.6" - wire width 2 $1\dec58_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec58_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec58_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec58_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec58_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec58_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec58_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec58_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec58_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec58_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec58_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec58_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec58_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec58_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec58_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec58_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec58_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec58_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec58_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec58_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec58_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec58_upd - attribute \src "issuer_ls180.v:102760.7-102760.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 2 \opcode_switch - attribute \src "issuer_ls180.v:102760.7-102760.20" - process $proc$issuer_ls180.v:102760$4070 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:103017.3-103032.6" - process $proc$issuer_ls180.v:103017$4046 - assign { } { } - assign { } { } - assign $0\dec58_function_unit[11:0] $1\dec58_function_unit[11:0] - attribute \src "issuer_ls180.v:103018.5-103018.29" - switch \initial - attribute \src "issuer_ls180.v:103018.9-103018.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_function_unit[11:0] 12'000000000100 - case - assign $1\dec58_function_unit[11:0] 12'000000000000 - end - sync always - update \dec58_function_unit $0\dec58_function_unit[11:0] - end - attribute \src "issuer_ls180.v:103033.3-103048.6" - process $proc$issuer_ls180.v:103033$4047 - assign { } { } - assign { } { } - assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0] - attribute \src "issuer_ls180.v:103034.5-103034.29" - switch \initial - attribute \src "issuer_ls180.v:103034.9-103034.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_ldst_len[3:0] 4'0100 - case - assign $1\dec58_ldst_len[3:0] 4'0000 - end - sync always - update \dec58_ldst_len $0\dec58_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:103049.3-103064.6" - process $proc$issuer_ls180.v:103049$4048 - assign { } { } - assign { } { } - assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] - attribute \src "issuer_ls180.v:103050.5-103050.29" - switch \initial - attribute \src "issuer_ls180.v:103050.9-103050.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_upd[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_upd[1:0] 2'00 - case - assign $1\dec58_upd[1:0] 2'00 - end - sync always - update \dec58_upd $0\dec58_upd[1:0] - end - attribute \src "issuer_ls180.v:103065.3-103080.6" - process $proc$issuer_ls180.v:103065$4049 - assign { } { } - assign { } { } - assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0] - attribute \src "issuer_ls180.v:103066.5-103066.29" - switch \initial - attribute \src "issuer_ls180.v:103066.9-103066.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_rc_sel[1:0] 2'00 - case - assign $1\dec58_rc_sel[1:0] 2'00 - end - sync always - update \dec58_rc_sel $0\dec58_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:103081.3-103096.6" - process $proc$issuer_ls180.v:103081$4050 - assign { } { } - assign { } { } - assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0] - attribute \src "issuer_ls180.v:103082.5-103082.29" - switch \initial - attribute \src "issuer_ls180.v:103082.9-103082.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_cry_in[1:0] 2'00 - case - assign $1\dec58_cry_in[1:0] 2'00 - end - sync always - update \dec58_cry_in $0\dec58_cry_in[1:0] - end - attribute \src "issuer_ls180.v:103097.3-103112.6" - process $proc$issuer_ls180.v:103097$4051 - assign { } { } - assign { } { } - assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0] - attribute \src "issuer_ls180.v:103098.5-103098.29" - switch \initial - attribute \src "issuer_ls180.v:103098.9-103098.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_asmcode[7:0] 8'01010010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_asmcode[7:0] 8'01010101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_asmcode[7:0] 8'01100010 - case - assign $1\dec58_asmcode[7:0] 8'00000000 - end - sync always - update \dec58_asmcode $0\dec58_asmcode[7:0] - end - attribute \src "issuer_ls180.v:103113.3-103128.6" - process $proc$issuer_ls180.v:103113$4052 - assign { } { } - assign { } { } - assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0] - attribute \src "issuer_ls180.v:103114.5-103114.29" - switch \initial - attribute \src "issuer_ls180.v:103114.9-103114.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_inv_a[0:0] 1'0 - case - assign $1\dec58_inv_a[0:0] 1'0 - end - sync always - update \dec58_inv_a $0\dec58_inv_a[0:0] - end - attribute \src "issuer_ls180.v:103129.3-103144.6" - process $proc$issuer_ls180.v:103129$4053 - assign { } { } - assign { } { } - assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0] - attribute \src "issuer_ls180.v:103130.5-103130.29" - switch \initial - attribute \src "issuer_ls180.v:103130.9-103130.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_inv_out[0:0] 1'0 - case - assign $1\dec58_inv_out[0:0] 1'0 - end - sync always - update \dec58_inv_out $0\dec58_inv_out[0:0] - end - attribute \src "issuer_ls180.v:103145.3-103160.6" - process $proc$issuer_ls180.v:103145$4054 - assign { } { } - assign { } { } - assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0] - attribute \src "issuer_ls180.v:103146.5-103146.29" - switch \initial - attribute \src "issuer_ls180.v:103146.9-103146.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_cry_out[0:0] 1'0 - case - assign $1\dec58_cry_out[0:0] 1'0 - end - sync always - update \dec58_cry_out $0\dec58_cry_out[0:0] - end - attribute \src "issuer_ls180.v:103161.3-103176.6" - process $proc$issuer_ls180.v:103161$4055 - assign { } { } - assign { } { } - assign $0\dec58_br[0:0] $1\dec58_br[0:0] - attribute \src "issuer_ls180.v:103162.5-103162.29" - switch \initial - attribute \src "issuer_ls180.v:103162.9-103162.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_br[0:0] 1'0 - case - assign $1\dec58_br[0:0] 1'0 - end - sync always - update \dec58_br $0\dec58_br[0:0] - end - attribute \src "issuer_ls180.v:103177.3-103192.6" - process $proc$issuer_ls180.v:103177$4056 - assign { } { } - assign { } { } - assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0] - attribute \src "issuer_ls180.v:103178.5-103178.29" - switch \initial - attribute \src "issuer_ls180.v:103178.9-103178.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_sgn_ext[0:0] 1'1 - case - assign $1\dec58_sgn_ext[0:0] 1'0 - end - sync always - update \dec58_sgn_ext $0\dec58_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:103193.3-103208.6" - process $proc$issuer_ls180.v:103193$4057 - assign { } { } - assign { } { } - assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] - attribute \src "issuer_ls180.v:103194.5-103194.29" - switch \initial - attribute \src "issuer_ls180.v:103194.9-103194.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_internal_op[6:0] 7'0100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_internal_op[6:0] 7'0100101 - case - assign $1\dec58_internal_op[6:0] 7'0000000 - end - sync always - update \dec58_internal_op $0\dec58_internal_op[6:0] - end - attribute \src "issuer_ls180.v:103209.3-103224.6" - process $proc$issuer_ls180.v:103209$4058 - assign { } { } - assign { } { } - assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0] - attribute \src "issuer_ls180.v:103210.5-103210.29" - switch \initial - attribute \src "issuer_ls180.v:103210.9-103210.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_rsrv[0:0] 1'0 - case - assign $1\dec58_rsrv[0:0] 1'0 - end - sync always - update \dec58_rsrv $0\dec58_rsrv[0:0] - end - attribute \src "issuer_ls180.v:103225.3-103240.6" - process $proc$issuer_ls180.v:103225$4059 - assign { } { } - assign { } { } - assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] - attribute \src "issuer_ls180.v:103226.5-103226.29" - switch \initial - attribute \src "issuer_ls180.v:103226.9-103226.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_is_32b[0:0] 1'0 - case - assign $1\dec58_is_32b[0:0] 1'0 - end - sync always - update \dec58_is_32b $0\dec58_is_32b[0:0] - end - attribute \src "issuer_ls180.v:103241.3-103256.6" - process $proc$issuer_ls180.v:103241$4060 - assign { } { } - assign { } { } - assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0] - attribute \src "issuer_ls180.v:103242.5-103242.29" - switch \initial - attribute \src "issuer_ls180.v:103242.9-103242.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_sgn[0:0] 1'0 - case - assign $1\dec58_sgn[0:0] 1'0 - end - sync always - update \dec58_sgn $0\dec58_sgn[0:0] - end - attribute \src "issuer_ls180.v:103257.3-103272.6" - process $proc$issuer_ls180.v:103257$4061 - assign { } { } - assign { } { } - assign $0\dec58_lk[0:0] $1\dec58_lk[0:0] - attribute \src "issuer_ls180.v:103258.5-103258.29" - switch \initial - attribute \src "issuer_ls180.v:103258.9-103258.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_lk[0:0] 1'0 - case - assign $1\dec58_lk[0:0] 1'0 - end - sync always - update \dec58_lk $0\dec58_lk[0:0] - end - attribute \src "issuer_ls180.v:103273.3-103288.6" - process $proc$issuer_ls180.v:103273$4062 - assign { } { } - assign { } { } - assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:103274.5-103274.29" - switch \initial - attribute \src "issuer_ls180.v:103274.9-103274.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_sgl_pipe[0:0] 1'1 - case - assign $1\dec58_sgl_pipe[0:0] 1'0 - end - sync always - update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0] - end - attribute \src "issuer_ls180.v:103289.3-103304.6" - process $proc$issuer_ls180.v:103289$4063 - assign { } { } - assign { } { } - assign $0\dec58_form[4:0] $1\dec58_form[4:0] - attribute \src "issuer_ls180.v:103290.5-103290.29" - switch \initial - attribute \src "issuer_ls180.v:103290.9-103290.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_form[4:0] 5'00101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_form[4:0] 5'00101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_form[4:0] 5'00101 - case - assign $1\dec58_form[4:0] 5'00000 - end - sync always - update \dec58_form $0\dec58_form[4:0] - end - attribute \src "issuer_ls180.v:103305.3-103320.6" - process $proc$issuer_ls180.v:103305$4064 - assign { } { } - assign { } { } - assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0] - attribute \src "issuer_ls180.v:103306.5-103306.29" - switch \initial - attribute \src "issuer_ls180.v:103306.9-103306.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_in1_sel[2:0] 3'010 - case - assign $1\dec58_in1_sel[2:0] 3'000 - end - sync always - update \dec58_in1_sel $0\dec58_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:103321.3-103336.6" - process $proc$issuer_ls180.v:103321$4065 - assign { } { } - assign { } { } - assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0] - attribute \src "issuer_ls180.v:103322.5-103322.29" - switch \initial - attribute \src "issuer_ls180.v:103322.9-103322.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_in2_sel[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_in2_sel[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_in2_sel[3:0] 4'1000 - case - assign $1\dec58_in2_sel[3:0] 4'0000 - end - sync always - update \dec58_in2_sel $0\dec58_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:103337.3-103352.6" - process $proc$issuer_ls180.v:103337$4066 - assign { } { } - assign { } { } - assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0] - attribute \src "issuer_ls180.v:103338.5-103338.29" - switch \initial - attribute \src "issuer_ls180.v:103338.9-103338.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_in3_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_in3_sel[1:0] 2'00 - case - assign $1\dec58_in3_sel[1:0] 2'00 - end - sync always - update \dec58_in3_sel $0\dec58_in3_sel[1:0] - end - attribute \src "issuer_ls180.v:103353.3-103368.6" - process $proc$issuer_ls180.v:103353$4067 - assign { } { } - assign { } { } - assign $0\dec58_out_sel[1:0] $1\dec58_out_sel[1:0] - attribute \src "issuer_ls180.v:103354.5-103354.29" - switch \initial - attribute \src "issuer_ls180.v:103354.9-103354.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_out_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_out_sel[1:0] 2'01 - case - assign $1\dec58_out_sel[1:0] 2'00 - end - sync always - update \dec58_out_sel $0\dec58_out_sel[1:0] - end - attribute \src "issuer_ls180.v:103369.3-103384.6" - process $proc$issuer_ls180.v:103369$4068 - assign { } { } - assign { } { } - assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0] - attribute \src "issuer_ls180.v:103370.5-103370.29" - switch \initial - attribute \src "issuer_ls180.v:103370.9-103370.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_cr_in[2:0] 3'000 - case - assign $1\dec58_cr_in[2:0] 3'000 - end - sync always - update \dec58_cr_in $0\dec58_cr_in[2:0] - end - attribute \src "issuer_ls180.v:103385.3-103400.6" - process $proc$issuer_ls180.v:103385$4069 - assign { } { } - assign { } { } - assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0] - attribute \src "issuer_ls180.v:103386.5-103386.29" - switch \initial - attribute \src "issuer_ls180.v:103386.9-103386.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_cr_out[2:0] 3'000 - case - assign $1\dec58_cr_out[2:0] 3'000 - end - sync always - update \dec58_cr_out $0\dec58_cr_out[2:0] - end - connect \opcode_switch \opcode_in [1:0] -end -attribute \src "issuer_ls180.v:103406.1-103977.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec62" -attribute \generator "nMigen" -module \dec62 - attribute \src "issuer_ls180.v:103729.3-103741.6" - wire width 8 $0\dec62_asmcode[7:0] - attribute \src "issuer_ls180.v:103781.3-103793.6" - wire $0\dec62_br[0:0] - attribute \src "issuer_ls180.v:103950.3-103962.6" - wire width 3 $0\dec62_cr_in[2:0] - attribute \src "issuer_ls180.v:103963.3-103975.6" - wire width 3 $0\dec62_cr_out[2:0] - attribute \src "issuer_ls180.v:103716.3-103728.6" - wire width 2 $0\dec62_cry_in[1:0] - attribute \src "issuer_ls180.v:103768.3-103780.6" - wire $0\dec62_cry_out[0:0] - attribute \src "issuer_ls180.v:103885.3-103897.6" - wire width 5 $0\dec62_form[4:0] - attribute \src "issuer_ls180.v:103664.3-103676.6" - wire width 12 $0\dec62_function_unit[11:0] - attribute \src "issuer_ls180.v:103898.3-103910.6" - wire width 3 $0\dec62_in1_sel[2:0] - attribute \src "issuer_ls180.v:103911.3-103923.6" - wire width 4 $0\dec62_in2_sel[3:0] - attribute \src "issuer_ls180.v:103924.3-103936.6" - wire width 2 $0\dec62_in3_sel[1:0] - attribute \src "issuer_ls180.v:103807.3-103819.6" - wire width 7 $0\dec62_internal_op[6:0] - attribute \src "issuer_ls180.v:103742.3-103754.6" - wire $0\dec62_inv_a[0:0] - attribute \src "issuer_ls180.v:103755.3-103767.6" - wire $0\dec62_inv_out[0:0] - attribute \src "issuer_ls180.v:103833.3-103845.6" - wire $0\dec62_is_32b[0:0] - attribute \src "issuer_ls180.v:103677.3-103689.6" - wire width 4 $0\dec62_ldst_len[3:0] - attribute \src "issuer_ls180.v:103859.3-103871.6" - wire $0\dec62_lk[0:0] - attribute \src "issuer_ls180.v:103937.3-103949.6" - wire width 2 $0\dec62_out_sel[1:0] - attribute \src "issuer_ls180.v:103703.3-103715.6" - wire width 2 $0\dec62_rc_sel[1:0] - attribute \src "issuer_ls180.v:103820.3-103832.6" - wire $0\dec62_rsrv[0:0] - attribute \src "issuer_ls180.v:103872.3-103884.6" - wire $0\dec62_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:103846.3-103858.6" - wire $0\dec62_sgn[0:0] - attribute \src "issuer_ls180.v:103794.3-103806.6" - wire $0\dec62_sgn_ext[0:0] - attribute \src "issuer_ls180.v:103690.3-103702.6" - wire width 2 $0\dec62_upd[1:0] - attribute \src "issuer_ls180.v:103407.7-103407.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:103729.3-103741.6" - wire width 8 $1\dec62_asmcode[7:0] - attribute \src "issuer_ls180.v:103781.3-103793.6" - wire $1\dec62_br[0:0] - attribute \src "issuer_ls180.v:103950.3-103962.6" - wire width 3 $1\dec62_cr_in[2:0] - attribute \src "issuer_ls180.v:103963.3-103975.6" - wire width 3 $1\dec62_cr_out[2:0] - attribute \src "issuer_ls180.v:103716.3-103728.6" - wire width 2 $1\dec62_cry_in[1:0] - attribute \src "issuer_ls180.v:103768.3-103780.6" - wire $1\dec62_cry_out[0:0] - attribute \src "issuer_ls180.v:103885.3-103897.6" - wire width 5 $1\dec62_form[4:0] - attribute \src "issuer_ls180.v:103664.3-103676.6" - wire width 12 $1\dec62_function_unit[11:0] - attribute \src "issuer_ls180.v:103898.3-103910.6" - wire width 3 $1\dec62_in1_sel[2:0] - attribute \src "issuer_ls180.v:103911.3-103923.6" - wire width 4 $1\dec62_in2_sel[3:0] - attribute \src "issuer_ls180.v:103924.3-103936.6" - wire width 2 $1\dec62_in3_sel[1:0] - attribute \src "issuer_ls180.v:103807.3-103819.6" - wire width 7 $1\dec62_internal_op[6:0] - attribute \src "issuer_ls180.v:103742.3-103754.6" - wire $1\dec62_inv_a[0:0] - attribute \src "issuer_ls180.v:103755.3-103767.6" - wire $1\dec62_inv_out[0:0] - attribute \src "issuer_ls180.v:103833.3-103845.6" - wire $1\dec62_is_32b[0:0] - attribute \src "issuer_ls180.v:103677.3-103689.6" - wire width 4 $1\dec62_ldst_len[3:0] - attribute \src "issuer_ls180.v:103859.3-103871.6" - wire $1\dec62_lk[0:0] - attribute \src "issuer_ls180.v:103937.3-103949.6" - wire width 2 $1\dec62_out_sel[1:0] - attribute \src "issuer_ls180.v:103703.3-103715.6" - wire width 2 $1\dec62_rc_sel[1:0] - attribute \src "issuer_ls180.v:103820.3-103832.6" - wire $1\dec62_rsrv[0:0] - attribute \src "issuer_ls180.v:103872.3-103884.6" - wire $1\dec62_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:103846.3-103858.6" - wire $1\dec62_sgn[0:0] - attribute \src "issuer_ls180.v:103794.3-103806.6" - wire $1\dec62_sgn_ext[0:0] - attribute \src "issuer_ls180.v:103690.3-103702.6" - wire width 2 $1\dec62_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 8 output 4 \dec62_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 18 \dec62_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 9 \dec62_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 10 \dec62_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 14 \dec62_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 17 \dec62_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 5 output 3 \dec62_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 output 1 \dec62_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 output 5 \dec62_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 6 \dec62_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 7 \dec62_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 output 2 \dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 15 \dec62_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 16 \dec62_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 21 \dec62_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 output 11 \dec62_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 23 \dec62_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 8 \dec62_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 13 \dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 20 \dec62_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 24 \dec62_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 22 \dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 19 \dec62_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 12 \dec62_upd - attribute \src "issuer_ls180.v:103407.7-103407.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" - wire width 2 \opcode_switch - attribute \src "issuer_ls180.v:103407.7-103407.20" - process $proc$issuer_ls180.v:103407$4095 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:103664.3-103676.6" - process $proc$issuer_ls180.v:103664$4071 - assign { } { } - assign { } { } - assign $0\dec62_function_unit[11:0] $1\dec62_function_unit[11:0] - attribute \src "issuer_ls180.v:103665.5-103665.29" - switch \initial - attribute \src "issuer_ls180.v:103665.9-103665.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_function_unit[11:0] 12'000000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_function_unit[11:0] 12'000000000100 - case - assign $1\dec62_function_unit[11:0] 12'000000000000 - end - sync always - update \dec62_function_unit $0\dec62_function_unit[11:0] - end - attribute \src "issuer_ls180.v:103677.3-103689.6" - process $proc$issuer_ls180.v:103677$4072 - assign { } { } - assign { } { } - assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0] - attribute \src "issuer_ls180.v:103678.5-103678.29" - switch \initial - attribute \src "issuer_ls180.v:103678.9-103678.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_ldst_len[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_ldst_len[3:0] 4'1000 - case - assign $1\dec62_ldst_len[3:0] 4'0000 - end - sync always - update \dec62_ldst_len $0\dec62_ldst_len[3:0] - end - attribute \src "issuer_ls180.v:103690.3-103702.6" - process $proc$issuer_ls180.v:103690$4073 - assign { } { } - assign { } { } - assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] - attribute \src "issuer_ls180.v:103691.5-103691.29" - switch \initial - attribute \src "issuer_ls180.v:103691.9-103691.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_upd[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_upd[1:0] 2'01 - case - assign $1\dec62_upd[1:0] 2'00 - end - sync always - update \dec62_upd $0\dec62_upd[1:0] - end - attribute \src "issuer_ls180.v:103703.3-103715.6" - process $proc$issuer_ls180.v:103703$4074 - assign { } { } - assign { } { } - assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0] - attribute \src "issuer_ls180.v:103704.5-103704.29" - switch \initial - attribute \src "issuer_ls180.v:103704.9-103704.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_rc_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_rc_sel[1:0] 2'00 - case - assign $1\dec62_rc_sel[1:0] 2'00 - end - sync always - update \dec62_rc_sel $0\dec62_rc_sel[1:0] - end - attribute \src "issuer_ls180.v:103716.3-103728.6" - process $proc$issuer_ls180.v:103716$4075 - assign { } { } - assign { } { } - assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0] - attribute \src "issuer_ls180.v:103717.5-103717.29" - switch \initial - attribute \src "issuer_ls180.v:103717.9-103717.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_cry_in[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_cry_in[1:0] 2'00 - case - assign $1\dec62_cry_in[1:0] 2'00 - end - sync always - update \dec62_cry_in $0\dec62_cry_in[1:0] - end - attribute \src "issuer_ls180.v:103729.3-103741.6" - process $proc$issuer_ls180.v:103729$4076 - assign { } { } - assign { } { } - assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0] - attribute \src "issuer_ls180.v:103730.5-103730.29" - switch \initial - attribute \src "issuer_ls180.v:103730.9-103730.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_asmcode[7:0] 8'10101100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_asmcode[7:0] 8'10101111 - case - assign $1\dec62_asmcode[7:0] 8'00000000 - end - sync always - update \dec62_asmcode $0\dec62_asmcode[7:0] - end - attribute \src "issuer_ls180.v:103742.3-103754.6" - process $proc$issuer_ls180.v:103742$4077 - assign { } { } - assign { } { } - assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0] - attribute \src "issuer_ls180.v:103743.5-103743.29" - switch \initial - attribute \src "issuer_ls180.v:103743.9-103743.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_inv_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_inv_a[0:0] 1'0 - case - assign $1\dec62_inv_a[0:0] 1'0 - end - sync always - update \dec62_inv_a $0\dec62_inv_a[0:0] - end - attribute \src "issuer_ls180.v:103755.3-103767.6" - process $proc$issuer_ls180.v:103755$4078 - assign { } { } - assign { } { } - assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0] - attribute \src "issuer_ls180.v:103756.5-103756.29" - switch \initial - attribute \src "issuer_ls180.v:103756.9-103756.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_inv_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_inv_out[0:0] 1'0 - case - assign $1\dec62_inv_out[0:0] 1'0 - end - sync always - update \dec62_inv_out $0\dec62_inv_out[0:0] - end - attribute \src "issuer_ls180.v:103768.3-103780.6" - process $proc$issuer_ls180.v:103768$4079 - assign { } { } - assign { } { } - assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0] - attribute \src "issuer_ls180.v:103769.5-103769.29" - switch \initial - attribute \src "issuer_ls180.v:103769.9-103769.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_cry_out[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_cry_out[0:0] 1'0 - case - assign $1\dec62_cry_out[0:0] 1'0 - end - sync always - update \dec62_cry_out $0\dec62_cry_out[0:0] - end - attribute \src "issuer_ls180.v:103781.3-103793.6" - process $proc$issuer_ls180.v:103781$4080 - assign { } { } - assign { } { } - assign $0\dec62_br[0:0] $1\dec62_br[0:0] - attribute \src "issuer_ls180.v:103782.5-103782.29" - switch \initial - attribute \src "issuer_ls180.v:103782.9-103782.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_br[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_br[0:0] 1'0 - case - assign $1\dec62_br[0:0] 1'0 - end - sync always - update \dec62_br $0\dec62_br[0:0] - end - attribute \src "issuer_ls180.v:103794.3-103806.6" - process $proc$issuer_ls180.v:103794$4081 - assign { } { } - assign { } { } - assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0] - attribute \src "issuer_ls180.v:103795.5-103795.29" - switch \initial - attribute \src "issuer_ls180.v:103795.9-103795.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_sgn_ext[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_sgn_ext[0:0] 1'0 - case - assign $1\dec62_sgn_ext[0:0] 1'0 - end - sync always - update \dec62_sgn_ext $0\dec62_sgn_ext[0:0] - end - attribute \src "issuer_ls180.v:103807.3-103819.6" - process $proc$issuer_ls180.v:103807$4082 - assign { } { } - assign { } { } - assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] - attribute \src "issuer_ls180.v:103808.5-103808.29" - switch \initial - attribute \src "issuer_ls180.v:103808.9-103808.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_internal_op[6:0] 7'0100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_internal_op[6:0] 7'0100110 - case - assign $1\dec62_internal_op[6:0] 7'0000000 - end - sync always - update \dec62_internal_op $0\dec62_internal_op[6:0] - end - attribute \src "issuer_ls180.v:103820.3-103832.6" - process $proc$issuer_ls180.v:103820$4083 - assign { } { } - assign { } { } - assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0] - attribute \src "issuer_ls180.v:103821.5-103821.29" - switch \initial - attribute \src "issuer_ls180.v:103821.9-103821.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_rsrv[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_rsrv[0:0] 1'0 - case - assign $1\dec62_rsrv[0:0] 1'0 - end - sync always - update \dec62_rsrv $0\dec62_rsrv[0:0] - end - attribute \src "issuer_ls180.v:103833.3-103845.6" - process $proc$issuer_ls180.v:103833$4084 - assign { } { } - assign { } { } - assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] - attribute \src "issuer_ls180.v:103834.5-103834.29" - switch \initial - attribute \src "issuer_ls180.v:103834.9-103834.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_is_32b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_is_32b[0:0] 1'0 - case - assign $1\dec62_is_32b[0:0] 1'0 - end - sync always - update \dec62_is_32b $0\dec62_is_32b[0:0] - end - attribute \src "issuer_ls180.v:103846.3-103858.6" - process $proc$issuer_ls180.v:103846$4085 - assign { } { } - assign { } { } - assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0] - attribute \src "issuer_ls180.v:103847.5-103847.29" - switch \initial - attribute \src "issuer_ls180.v:103847.9-103847.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_sgn[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_sgn[0:0] 1'0 - case - assign $1\dec62_sgn[0:0] 1'0 - end - sync always - update \dec62_sgn $0\dec62_sgn[0:0] - end - attribute \src "issuer_ls180.v:103859.3-103871.6" - process $proc$issuer_ls180.v:103859$4086 - assign { } { } - assign { } { } - assign $0\dec62_lk[0:0] $1\dec62_lk[0:0] - attribute \src "issuer_ls180.v:103860.5-103860.29" - switch \initial - attribute \src "issuer_ls180.v:103860.9-103860.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_lk[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_lk[0:0] 1'0 - case - assign $1\dec62_lk[0:0] 1'0 - end - sync always - update \dec62_lk $0\dec62_lk[0:0] - end - attribute \src "issuer_ls180.v:103872.3-103884.6" - process $proc$issuer_ls180.v:103872$4087 - assign { } { } - assign { } { } - assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0] - attribute \src "issuer_ls180.v:103873.5-103873.29" - switch \initial - attribute \src "issuer_ls180.v:103873.9-103873.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_sgl_pipe[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_sgl_pipe[0:0] 1'1 - case - assign $1\dec62_sgl_pipe[0:0] 1'0 - end - sync always - update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0] - end - attribute \src "issuer_ls180.v:103885.3-103897.6" - process $proc$issuer_ls180.v:103885$4088 - assign { } { } - assign { } { } - assign $0\dec62_form[4:0] $1\dec62_form[4:0] - attribute \src "issuer_ls180.v:103886.5-103886.29" - switch \initial - attribute \src "issuer_ls180.v:103886.9-103886.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_form[4:0] 5'00101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_form[4:0] 5'00101 - case - assign $1\dec62_form[4:0] 5'00000 - end - sync always - update \dec62_form $0\dec62_form[4:0] - end - attribute \src "issuer_ls180.v:103898.3-103910.6" - process $proc$issuer_ls180.v:103898$4089 - assign { } { } - assign { } { } - assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0] - attribute \src "issuer_ls180.v:103899.5-103899.29" - switch \initial - attribute \src "issuer_ls180.v:103899.9-103899.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_in1_sel[2:0] 3'010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_in1_sel[2:0] 3'010 - case - assign $1\dec62_in1_sel[2:0] 3'000 - end - sync always - update \dec62_in1_sel $0\dec62_in1_sel[2:0] - end - attribute \src "issuer_ls180.v:103911.3-103923.6" - process $proc$issuer_ls180.v:103911$4090 - assign { } { } - assign { } { } - assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0] - attribute \src "issuer_ls180.v:103912.5-103912.29" - switch \initial - attribute \src "issuer_ls180.v:103912.9-103912.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_in2_sel[3:0] 4'1000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_in2_sel[3:0] 4'1000 - case - assign $1\dec62_in2_sel[3:0] 4'0000 - end - sync always - update \dec62_in2_sel $0\dec62_in2_sel[3:0] - end - attribute \src "issuer_ls180.v:103924.3-103936.6" - process $proc$issuer_ls180.v:103924$4091 - assign { } { } - assign { } { } - assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0] - attribute \src "issuer_ls180.v:103925.5-103925.29" - switch \initial - attribute \src "issuer_ls180.v:103925.9-103925.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_in3_sel[1:0] 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_in3_sel[1:0] 2'01 - case - assign $1\dec62_in3_sel[1:0] 2'00 - end - sync always - update \dec62_in3_sel $0\dec62_in3_sel[1:0] - end - attribute \src "issuer_ls180.v:103937.3-103949.6" - process $proc$issuer_ls180.v:103937$4092 - assign { } { } - assign { } { } - assign $0\dec62_out_sel[1:0] $1\dec62_out_sel[1:0] - attribute \src "issuer_ls180.v:103938.5-103938.29" - switch \initial - attribute \src "issuer_ls180.v:103938.9-103938.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_out_sel[1:0] 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_out_sel[1:0] 2'00 - case - assign $1\dec62_out_sel[1:0] 2'00 - end - sync always - update \dec62_out_sel $0\dec62_out_sel[1:0] - end - attribute \src "issuer_ls180.v:103950.3-103962.6" - process $proc$issuer_ls180.v:103950$4093 - assign { } { } - assign { } { } - assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0] - attribute \src "issuer_ls180.v:103951.5-103951.29" - switch \initial - attribute \src "issuer_ls180.v:103951.9-103951.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_cr_in[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_cr_in[2:0] 3'000 - case - assign $1\dec62_cr_in[2:0] 3'000 - end - sync always - update \dec62_cr_in $0\dec62_cr_in[2:0] - end - attribute \src "issuer_ls180.v:103963.3-103975.6" - process $proc$issuer_ls180.v:103963$4094 - assign { } { } - assign { } { } - assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0] - attribute \src "issuer_ls180.v:103964.5-103964.29" - switch \initial - attribute \src "issuer_ls180.v:103964.9-103964.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_cr_out[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_cr_out[2:0] 3'000 - case - assign $1\dec62_cr_out[2:0] 3'000 - end - sync always - update \dec62_cr_out $0\dec62_cr_out[2:0] - end - connect \opcode_switch \opcode_in [1:0] -end -attribute \src "issuer_ls180.v:103981.1-104514.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU" -attribute \generator "nMigen" -module \dec_ALU - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 18 \ALU_ALU__data_len - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \ALU_ALU__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \ALU_ALU__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \ALU_ALU__imm_data__ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 14 \ALU_ALU__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 19 \ALU_ALU__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \ALU_ALU__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \ALU_ALU__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \ALU_ALU__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \ALU_ALU__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \ALU_ALU__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \ALU_ALU__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \ALU_ALU__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \ALU_ALU__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \ALU_ALU__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \ALU_ALU__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \ALU_ALU__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \ALU_ALU__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_ALU_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_ALU_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_ALU_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 \dec_ALU_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_ALU_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_ALU_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 \dec_ALU_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 \dec_ALU_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 24 \dec_ALU_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_ALU_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_ALU_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_ALU_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_ALU_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 \dec_ALU_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 \dec_ALU_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_ALU_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_ALU_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec_ALU_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec_ALU_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec_ALU_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_ALU_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec_ALU_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec_ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec_ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec_ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec_ALU_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec_ALU_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec_ALU_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec_ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 6 \dec_ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" - wire \dec_ai_immz_out - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" - wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_bi_imm_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_oe_oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_rc_rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" - wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" - wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 input 20 \raw_opcode_in - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:104398.7-104435.4" - cell \dec \dec - connect \ALU_BA \dec_ALU_BA - connect \ALU_BB \dec_ALU_BB - connect \ALU_BC \dec_ALU_BC - connect \ALU_BD \dec_ALU_BD - connect \ALU_BI \dec_ALU_BI - connect \ALU_BT \dec_ALU_BT - connect \ALU_DS \dec_ALU_DS - connect \ALU_FXM \dec_ALU_FXM - connect \ALU_LI \dec_ALU_LI - connect \ALU_OE \dec_ALU_OE - connect \ALU_RA \dec_ALU_RA - connect \ALU_Rc \dec_ALU_Rc - connect \ALU_SH32 \dec_ALU_SH32 - connect \ALU_SI \dec_ALU_SI - connect \ALU_UI \dec_ALU_UI - connect \ALU_cr_in \dec_ALU_cr_in - connect \ALU_cr_out \dec_ALU_cr_out - connect \ALU_cry_in \dec_ALU_cry_in - connect \ALU_cry_out \dec_ALU_cry_out - connect \ALU_function_unit \dec_ALU_function_unit - connect \ALU_in1_sel \dec_ALU_in1_sel - connect \ALU_in2_sel \dec_ALU_in2_sel - connect \ALU_internal_op \dec_ALU_internal_op - connect \ALU_inv_a \dec_ALU_inv_a - connect \ALU_inv_out \dec_ALU_inv_out - connect \ALU_is_32b \dec_ALU_is_32b - connect \ALU_ldst_len \dec_ALU_ldst_len - connect \ALU_rc_sel \dec_ALU_rc_sel - connect \ALU_sgn \dec_ALU_sgn - connect \ALU_sh \dec_ALU_sh - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \raw_opcode_in \raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:104436.10-104440.4" - cell \dec_ai \dec_ai - connect \ALU_RA \dec_ALU_RA - connect \immz_out \dec_ai_immz_out - connect \sel_in \dec_ai_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:104441.10-104452.4" - cell \dec_bi \dec_bi - connect \ALU_BD \dec_ALU_BD - connect \ALU_DS \dec_ALU_DS - connect \ALU_LI \dec_ALU_LI - connect \ALU_SH32 \dec_ALU_SH32 - connect \ALU_SI \dec_ALU_SI - connect \ALU_UI \dec_ALU_UI - connect \ALU_sh \dec_ALU_sh - connect \imm_b \dec_bi_imm_b - connect \imm_b_ok \dec_bi_imm_b_ok - connect \sel_in \dec_bi_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:104453.13-104464.4" - cell \dec_cr_in \dec_cr_in - connect \ALU_BA \dec_ALU_BA - connect \ALU_BB \dec_ALU_BB - connect \ALU_BC \dec_ALU_BC - connect \ALU_BI \dec_ALU_BI - connect \ALU_BT \dec_ALU_BT - connect \ALU_FXM \dec_ALU_FXM - connect \ALU_internal_op \dec_ALU_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:104465.14-104474.4" - cell \dec_cr_out \dec_cr_out - connect \ALU_FXM \dec_ALU_FXM - connect \ALU_internal_op \dec_ALU_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:104475.10-104481.4" - cell \dec_oe \dec_oe - connect \ALU_OE \dec_ALU_OE - connect \ALU_internal_op \dec_ALU_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \sel_in \dec_oe_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:104482.10-104487.4" - cell \dec_rc \dec_rc - connect \ALU_Rc \dec_ALU_Rc - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \sel_in \dec_rc_sel_in - end - connect \ALU_ALU__is_signed \dec_ALU_sgn - connect \ALU_ALU__is_32bit \dec_ALU_is_32b - connect \ALU_ALU__output_carry \dec_ALU_cry_out - connect \ALU_ALU__input_carry \dec_ALU_cry_in - connect \ALU_ALU__invert_out \dec_ALU_inv_out - connect \ALU_ALU__invert_in \dec_ALU_inv_a - connect \ALU_ALU__data_len \dec_ALU_ldst_len - connect \ALU_ALU__write_cr0 \dec_cr_out_cr_bitfield_ok - connect { \ALU_ALU__oe__ok \ALU_ALU__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \ALU_ALU__rc__ok \ALU_ALU__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - connect { \ALU_ALU__imm_data__ok \ALU_ALU__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } - connect \dec_bi_sel_in \dec_ALU_in2_sel - connect \ALU_ALU__zero_a \dec_ai_immz_out - connect \dec_ai_sel_in \dec_ALU_in1_sel - connect \ALU_ALU__fn_unit \dec_ALU_function_unit - connect \ALU_ALU__insn_type \dec_ALU_internal_op - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_ALU_cr_out - connect \dec_cr_in_sel_in \dec_ALU_cr_in - connect \dec_oe_sel_in \dec_ALU_rc_sel - connect \dec_rc_sel_in \dec_ALU_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in - connect \insn_in$1 \dec_opcode_in - connect \insn_in \dec_opcode_in - connect \ALU_ALU__insn \dec_opcode_in -end -attribute \src "issuer_ls180.v:104518.1-104970.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH" -attribute \generator "nMigen" -module \dec_BRANCH - attribute \src "issuer_ls180.v:104944.3-104953.6" - wire $0\BRANCH_BRANCH__lk[0:0] - attribute \src "issuer_ls180.v:104519.7-104519.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:104944.3-104953.6" - wire $1\BRANCH_BRANCH__lk[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 3 \BRANCH_BRANCH__cia - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 5 \BRANCH_BRANCH__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \BRANCH_BRANCH__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \BRANCH_BRANCH__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 6 \BRANCH_BRANCH__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 4 \BRANCH_BRANCH__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \BRANCH_BRANCH__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \BRANCH_BRANCH__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire input 2 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 input 11 \core_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_BRANCH_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_BRANCH_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_BRANCH_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 \dec_BRANCH_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_BRANCH_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_BRANCH_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 \dec_BRANCH_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 \dec_BRANCH_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 24 \dec_BRANCH_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_BRANCH_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_BRANCH_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_BRANCH_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_BRANCH_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 \dec_BRANCH_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 \dec_BRANCH_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_BRANCH_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_BRANCH_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec_BRANCH_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec_BRANCH_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec_BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec_BRANCH_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec_BRANCH_lk - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec_BRANCH_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 6 \dec_BRANCH_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_bi_imm_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 \dec_cr_out_sel_in - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_rc_rc - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 \dec_rc_sel_in - attribute \src "issuer_ls180.v:104519.7-104519.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" - wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" - wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 input 1 \raw_opcode_in - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:104869.13-104900.4" - cell \dec$144 \dec - connect \BRANCH_BA \dec_BRANCH_BA - connect \BRANCH_BB \dec_BRANCH_BB - connect \BRANCH_BC \dec_BRANCH_BC - connect \BRANCH_BD \dec_BRANCH_BD - connect \BRANCH_BI \dec_BRANCH_BI - connect \BRANCH_BT \dec_BRANCH_BT - connect \BRANCH_DS \dec_BRANCH_DS - connect \BRANCH_FXM \dec_BRANCH_FXM - connect \BRANCH_LI \dec_BRANCH_LI - connect \BRANCH_LK \dec_BRANCH_LK - connect \BRANCH_OE \dec_BRANCH_OE - connect \BRANCH_Rc \dec_BRANCH_Rc - connect \BRANCH_SH32 \dec_BRANCH_SH32 - connect \BRANCH_SI \dec_BRANCH_SI - connect \BRANCH_UI \dec_BRANCH_UI - connect \BRANCH_cr_in \dec_BRANCH_cr_in - connect \BRANCH_cr_out \dec_BRANCH_cr_out - connect \BRANCH_function_unit \dec_BRANCH_function_unit - connect \BRANCH_in2_sel \dec_BRANCH_in2_sel - connect \BRANCH_internal_op \dec_BRANCH_internal_op - connect \BRANCH_is_32b \dec_BRANCH_is_32b - connect \BRANCH_lk \dec_BRANCH_lk - connect \BRANCH_rc_sel \dec_BRANCH_rc_sel - connect \BRANCH_sh \dec_BRANCH_sh - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \raw_opcode_in \raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:104901.16-104912.4" - cell \dec_bi$151 \dec_bi - connect \BRANCH_BD \dec_BRANCH_BD - connect \BRANCH_DS \dec_BRANCH_DS - connect \BRANCH_LI \dec_BRANCH_LI - connect \BRANCH_SH32 \dec_BRANCH_SH32 - connect \BRANCH_SI \dec_BRANCH_SI - connect \BRANCH_UI \dec_BRANCH_UI - connect \BRANCH_sh \dec_BRANCH_sh - connect \imm_b \dec_bi_imm_b - connect \imm_b_ok \dec_bi_imm_b_ok - connect \sel_in \dec_bi_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:104913.19-104924.4" - cell \dec_cr_in$147 \dec_cr_in - connect \BRANCH_BA \dec_BRANCH_BA - connect \BRANCH_BB \dec_BRANCH_BB - connect \BRANCH_BC \dec_BRANCH_BC - connect \BRANCH_BI \dec_BRANCH_BI - connect \BRANCH_BT \dec_BRANCH_BT - connect \BRANCH_FXM \dec_BRANCH_FXM - connect \BRANCH_internal_op \dec_BRANCH_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:104925.20-104933.4" - cell \dec_cr_out$149 \dec_cr_out - connect \BRANCH_FXM \dec_BRANCH_FXM - connect \BRANCH_internal_op \dec_BRANCH_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:104934.16-104938.4" - cell \dec_oe$146 \dec_oe - connect \BRANCH_OE \dec_BRANCH_OE - connect \BRANCH_internal_op \dec_BRANCH_internal_op - connect \sel_in \dec_oe_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:104939.16-104943.4" - cell \dec_rc$145 \dec_rc - connect \BRANCH_Rc \dec_BRANCH_Rc - connect \rc \dec_rc_rc - connect \sel_in \dec_rc_sel_in - end - attribute \src "issuer_ls180.v:104519.7-104519.20" - process $proc$issuer_ls180.v:104519$4097 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:104944.3-104953.6" - process $proc$issuer_ls180.v:104944$4096 - assign { } { } - assign { } { } - assign $0\BRANCH_BRANCH__lk[0:0] $1\BRANCH_BRANCH__lk[0:0] - attribute \src "issuer_ls180.v:104945.5-104945.29" - switch \initial - attribute \src "issuer_ls180.v:104945.9-104945.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:756" - switch \dec_BRANCH_lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\BRANCH_BRANCH__lk[0:0] \dec_BRANCH_LK - case - assign $1\BRANCH_BRANCH__lk[0:0] 1'0 - end - sync always - update \BRANCH_BRANCH__lk $0\BRANCH_BRANCH__lk[0:0] - end - connect \BRANCH_BRANCH__is_32bit \dec_BRANCH_is_32b - connect { \BRANCH_BRANCH__imm_data__ok \BRANCH_BRANCH__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } - connect \dec_bi_sel_in \dec_BRANCH_in2_sel - connect \BRANCH_BRANCH__fn_unit \dec_BRANCH_function_unit - connect \BRANCH_BRANCH__insn_type \dec_BRANCH_internal_op - connect \BRANCH_BRANCH__cia \core_pc - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_BRANCH_cr_out - connect \dec_cr_in_sel_in \dec_BRANCH_cr_in - connect \dec_oe_sel_in \dec_BRANCH_rc_sel - connect \dec_rc_sel_in \dec_BRANCH_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in - connect \insn_in$1 \dec_opcode_in - connect \insn_in \dec_opcode_in - connect \BRANCH_BRANCH__insn \dec_opcode_in -end -attribute \src "issuer_ls180.v:104974.1-105317.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR" -attribute \generator "nMigen" -module \dec_CR - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \CR_CR__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 4 \CR_CR__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute 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\dec_CR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_CR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 \dec_CR_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_CR_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_CR_Rc - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_CR_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 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\dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_CR_cr_out - connect \dec_cr_in_sel_in \dec_CR_cr_in - connect \dec_oe_sel_in \dec_CR_rc_sel - connect \dec_rc_sel_in \dec_CR_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in - connect \insn_in$1 \dec_opcode_in - connect \insn_in \dec_opcode_in - connect \CR_CR__insn \dec_opcode_in -end -attribute \src "issuer_ls180.v:105321.1-105854.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV" -attribute \generator "nMigen" -module \dec_DIV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 18 \DIV_DIV__data_len - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \DIV_DIV__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \DIV_DIV__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \DIV_DIV__imm_data__ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 12 \DIV_DIV__input_carry - attribute \src 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attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute 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\enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \DIV_DIV__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \DIV_DIV__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \DIV_DIV__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \DIV_DIV__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \DIV_DIV__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \DIV_DIV__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \DIV_DIV__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \DIV_DIV__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \DIV_DIV__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \DIV_DIV__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \DIV_DIV__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \DIV_DIV__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_DIV_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_DIV_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_DIV_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 \dec_DIV_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_DIV_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_DIV_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 \dec_DIV_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 \dec_DIV_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 24 \dec_DIV_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_DIV_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_DIV_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_DIV_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_DIV_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 \dec_DIV_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 \dec_DIV_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_DIV_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 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\enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 16 \LDST_LDST__ldst_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \LDST_LDST__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \LDST_LDST__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \LDST_LDST__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \LDST_LDST__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \LDST_LDST__sign_extend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \LDST_LDST__zero_a - attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 24 \dec_LDST_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_LDST_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_LDST_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_LDST_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_LDST_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 \dec_LDST_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 \dec_LDST_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec_LDST_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_LDST_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_LDST_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec_LDST_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_LDST_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec_LDST_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec_LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec_LDST_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec_LDST_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec_LDST_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec_LDST_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec_LDST_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 6 \dec_LDST_sh - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec_LDST_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" - wire \dec_ai_immz_out - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" - wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_bi_imm_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_oe_oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_rc_rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" - wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" - wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 input 18 \raw_opcode_in - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:106269.13-106305.4" - cell \dec$193 \dec - connect \LDST_BA \dec_LDST_BA - connect \LDST_BB \dec_LDST_BB - connect \LDST_BC \dec_LDST_BC - connect \LDST_BD \dec_LDST_BD - connect \LDST_BI \dec_LDST_BI - connect \LDST_BT \dec_LDST_BT - connect \LDST_DS \dec_LDST_DS - connect \LDST_FXM \dec_LDST_FXM - connect \LDST_LI \dec_LDST_LI - connect \LDST_OE \dec_LDST_OE - connect \LDST_RA \dec_LDST_RA - connect \LDST_Rc \dec_LDST_Rc - connect \LDST_SH32 \dec_LDST_SH32 - connect \LDST_SI \dec_LDST_SI - connect \LDST_UI \dec_LDST_UI - connect \LDST_br \dec_LDST_br - connect \LDST_cr_in \dec_LDST_cr_in - connect \LDST_cr_out \dec_LDST_cr_out - connect \LDST_function_unit \dec_LDST_function_unit - connect \LDST_in1_sel \dec_LDST_in1_sel - connect \LDST_in2_sel \dec_LDST_in2_sel - connect \LDST_internal_op \dec_LDST_internal_op - connect \LDST_is_32b \dec_LDST_is_32b - connect \LDST_ldst_len \dec_LDST_ldst_len - connect \LDST_rc_sel \dec_LDST_rc_sel - connect \LDST_sgn \dec_LDST_sgn - connect \LDST_sgn_ext \dec_LDST_sgn_ext - connect \LDST_sh \dec_LDST_sh - connect \LDST_upd \dec_LDST_upd - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \raw_opcode_in \raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:106306.16-106310.4" - cell \dec_ai$200 \dec_ai - connect \LDST_RA \dec_LDST_RA - connect \immz_out \dec_ai_immz_out - connect \sel_in \dec_ai_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:106311.16-106322.4" - cell \dec_bi$201 \dec_bi - connect \LDST_BD \dec_LDST_BD - connect \LDST_DS \dec_LDST_DS - connect \LDST_LI \dec_LDST_LI - connect \LDST_SH32 \dec_LDST_SH32 - connect \LDST_SI \dec_LDST_SI - connect \LDST_UI \dec_LDST_UI - connect \LDST_sh \dec_LDST_sh - connect \imm_b \dec_bi_imm_b - connect \imm_b_ok \dec_bi_imm_b_ok - connect \sel_in \dec_bi_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:106323.19-106334.4" - cell \dec_cr_in$196 \dec_cr_in - connect \LDST_BA \dec_LDST_BA - connect \LDST_BB \dec_LDST_BB - connect \LDST_BC \dec_LDST_BC - connect \LDST_BI \dec_LDST_BI - connect \LDST_BT \dec_LDST_BT - connect \LDST_FXM \dec_LDST_FXM - connect \LDST_internal_op \dec_LDST_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:106335.20-106343.4" - cell \dec_cr_out$198 \dec_cr_out - connect \LDST_FXM \dec_LDST_FXM - connect \LDST_internal_op \dec_LDST_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:106344.16-106350.4" - cell \dec_oe$195 \dec_oe - connect \LDST_OE \dec_LDST_OE - connect \LDST_internal_op \dec_LDST_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \sel_in \dec_oe_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:106351.16-106356.4" - cell \dec_rc$194 \dec_rc - connect \LDST_Rc \dec_LDST_Rc - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \sel_in \dec_rc_sel_in - end - connect \LDST_LDST__ldst_mode \dec_LDST_upd - connect \LDST_LDST__sign_extend \dec_LDST_sgn_ext - connect \LDST_LDST__byte_reverse \dec_LDST_br - connect \LDST_LDST__is_signed \dec_LDST_sgn - connect \LDST_LDST__is_32bit \dec_LDST_is_32b - connect \LDST_LDST__data_len \dec_LDST_ldst_len - connect { \LDST_LDST__oe__ok \LDST_LDST__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \LDST_LDST__rc__ok \LDST_LDST__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - connect { \LDST_LDST__imm_data__ok \LDST_LDST__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } - connect \dec_bi_sel_in \dec_LDST_in2_sel - connect \LDST_LDST__zero_a \dec_ai_immz_out - connect \dec_ai_sel_in \dec_LDST_in1_sel - connect \LDST_LDST__fn_unit \dec_LDST_function_unit - connect \LDST_LDST__insn_type \dec_LDST_internal_op - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_LDST_cr_out - connect \dec_cr_in_sel_in \dec_LDST_cr_in - connect \dec_oe_sel_in \dec_LDST_rc_sel - connect \dec_rc_sel_in \dec_LDST_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in - connect \insn_in$1 \dec_opcode_in - connect \insn_in \dec_opcode_in - connect \LDST_LDST__insn \dec_opcode_in -end -attribute \src "issuer_ls180.v:106385.1-106918.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL" -attribute \generator "nMigen" -module \dec_LOGICAL - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 18 \LOGICAL_LOGICAL__data_len - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \LOGICAL_LOGICAL__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \LOGICAL_LOGICAL__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \LOGICAL_LOGICAL__imm_data__ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 12 \LOGICAL_LOGICAL__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 19 \LOGICAL_LOGICAL__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \LOGICAL_LOGICAL__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \LOGICAL_LOGICAL__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \LOGICAL_LOGICAL__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \LOGICAL_LOGICAL__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \LOGICAL_LOGICAL__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \LOGICAL_LOGICAL__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \LOGICAL_LOGICAL__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \LOGICAL_LOGICAL__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \LOGICAL_LOGICAL__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \LOGICAL_LOGICAL__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \LOGICAL_LOGICAL__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \LOGICAL_LOGICAL__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_LOGICAL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_LOGICAL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_LOGICAL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 \dec_LOGICAL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_LOGICAL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_LOGICAL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 \dec_LOGICAL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 \dec_LOGICAL_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 24 \dec_LOGICAL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_LOGICAL_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_LOGICAL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_LOGICAL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_LOGICAL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 \dec_LOGICAL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 \dec_LOGICAL_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_LOGICAL_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_LOGICAL_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec_LOGICAL_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec_LOGICAL_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec_LOGICAL_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_LOGICAL_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec_LOGICAL_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec_LOGICAL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec_LOGICAL_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec_LOGICAL_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec_LOGICAL_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec_LOGICAL_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec_LOGICAL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec_LOGICAL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 6 \dec_LOGICAL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" - wire \dec_ai_immz_out - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" - wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_bi_imm_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_oe_oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_rc_rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" - wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" - wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 input 20 \raw_opcode_in - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:106802.13-106839.4" - cell \dec$152 \dec - connect \LOGICAL_BA \dec_LOGICAL_BA - connect \LOGICAL_BB \dec_LOGICAL_BB - connect \LOGICAL_BC \dec_LOGICAL_BC - connect \LOGICAL_BD \dec_LOGICAL_BD - connect \LOGICAL_BI \dec_LOGICAL_BI - connect \LOGICAL_BT \dec_LOGICAL_BT - connect \LOGICAL_DS \dec_LOGICAL_DS - connect \LOGICAL_FXM \dec_LOGICAL_FXM - connect \LOGICAL_LI \dec_LOGICAL_LI - connect \LOGICAL_OE \dec_LOGICAL_OE - connect \LOGICAL_RA \dec_LOGICAL_RA - connect \LOGICAL_Rc \dec_LOGICAL_Rc - connect \LOGICAL_SH32 \dec_LOGICAL_SH32 - connect \LOGICAL_SI \dec_LOGICAL_SI - connect \LOGICAL_UI \dec_LOGICAL_UI - connect \LOGICAL_cr_in \dec_LOGICAL_cr_in - connect \LOGICAL_cr_out \dec_LOGICAL_cr_out - connect \LOGICAL_cry_in \dec_LOGICAL_cry_in - connect \LOGICAL_cry_out \dec_LOGICAL_cry_out - connect \LOGICAL_function_unit \dec_LOGICAL_function_unit - connect \LOGICAL_in1_sel \dec_LOGICAL_in1_sel - connect \LOGICAL_in2_sel \dec_LOGICAL_in2_sel - connect \LOGICAL_internal_op \dec_LOGICAL_internal_op - connect \LOGICAL_inv_a \dec_LOGICAL_inv_a - connect \LOGICAL_inv_out \dec_LOGICAL_inv_out - connect \LOGICAL_is_32b \dec_LOGICAL_is_32b - connect \LOGICAL_ldst_len \dec_LOGICAL_ldst_len - connect \LOGICAL_rc_sel \dec_LOGICAL_rc_sel - connect \LOGICAL_sgn \dec_LOGICAL_sgn - connect \LOGICAL_sh \dec_LOGICAL_sh - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \raw_opcode_in \raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:106840.16-106844.4" - cell \dec_ai$159 \dec_ai - connect \LOGICAL_RA \dec_LOGICAL_RA - connect \immz_out \dec_ai_immz_out - connect \sel_in \dec_ai_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:106845.16-106856.4" - cell \dec_bi$160 \dec_bi - connect \LOGICAL_BD \dec_LOGICAL_BD - connect \LOGICAL_DS \dec_LOGICAL_DS - connect \LOGICAL_LI \dec_LOGICAL_LI - connect \LOGICAL_SH32 \dec_LOGICAL_SH32 - connect \LOGICAL_SI \dec_LOGICAL_SI - connect \LOGICAL_UI \dec_LOGICAL_UI - connect \LOGICAL_sh \dec_LOGICAL_sh - connect \imm_b \dec_bi_imm_b - connect \imm_b_ok \dec_bi_imm_b_ok - connect \sel_in \dec_bi_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:106857.19-106868.4" - cell \dec_cr_in$155 \dec_cr_in - connect \LOGICAL_BA \dec_LOGICAL_BA - connect \LOGICAL_BB \dec_LOGICAL_BB - connect \LOGICAL_BC \dec_LOGICAL_BC - connect \LOGICAL_BI \dec_LOGICAL_BI - connect \LOGICAL_BT \dec_LOGICAL_BT - connect \LOGICAL_FXM \dec_LOGICAL_FXM - connect \LOGICAL_internal_op \dec_LOGICAL_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:106869.20-106878.4" - cell \dec_cr_out$157 \dec_cr_out - connect \LOGICAL_FXM \dec_LOGICAL_FXM - connect \LOGICAL_internal_op \dec_LOGICAL_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:106879.16-106885.4" - cell \dec_oe$154 \dec_oe - connect \LOGICAL_OE \dec_LOGICAL_OE - connect \LOGICAL_internal_op \dec_LOGICAL_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \sel_in \dec_oe_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:106886.16-106891.4" - cell \dec_rc$153 \dec_rc - connect \LOGICAL_Rc \dec_LOGICAL_Rc - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \sel_in \dec_rc_sel_in - end - connect \LOGICAL_LOGICAL__is_signed \dec_LOGICAL_sgn - connect \LOGICAL_LOGICAL__is_32bit \dec_LOGICAL_is_32b - connect \LOGICAL_LOGICAL__output_carry \dec_LOGICAL_cry_out - connect \LOGICAL_LOGICAL__input_carry \dec_LOGICAL_cry_in - connect \LOGICAL_LOGICAL__invert_out \dec_LOGICAL_inv_out - connect \LOGICAL_LOGICAL__invert_in \dec_LOGICAL_inv_a - connect \LOGICAL_LOGICAL__data_len \dec_LOGICAL_ldst_len - connect \LOGICAL_LOGICAL__write_cr0 \dec_cr_out_cr_bitfield_ok - connect { \LOGICAL_LOGICAL__oe__ok \LOGICAL_LOGICAL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \LOGICAL_LOGICAL__rc__ok \LOGICAL_LOGICAL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - connect { \LOGICAL_LOGICAL__imm_data__ok \LOGICAL_LOGICAL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } - connect \dec_bi_sel_in \dec_LOGICAL_in2_sel - connect \LOGICAL_LOGICAL__zero_a \dec_ai_immz_out - connect \dec_ai_sel_in \dec_LOGICAL_in1_sel - connect \LOGICAL_LOGICAL__fn_unit \dec_LOGICAL_function_unit - connect \LOGICAL_LOGICAL__insn_type \dec_LOGICAL_internal_op - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_LOGICAL_cr_out - connect \dec_cr_in_sel_in \dec_LOGICAL_cr_in - connect \dec_oe_sel_in \dec_LOGICAL_rc_sel - connect \dec_rc_sel_in \dec_LOGICAL_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in - connect \insn_in$1 \dec_opcode_in - connect \insn_in \dec_opcode_in - connect \LOGICAL_LOGICAL__insn \dec_opcode_in -end -attribute \src "issuer_ls180.v:106922.1-107380.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL" -attribute \generator "nMigen" -module \dec_MUL - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \MUL_MUL__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \MUL_MUL__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \MUL_MUL__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 13 \MUL_MUL__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \MUL_MUL__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \MUL_MUL__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \MUL_MUL__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \MUL_MUL__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \MUL_MUL__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \MUL_MUL__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \MUL_MUL__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \MUL_MUL__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_MUL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_MUL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_MUL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 \dec_MUL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_MUL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_MUL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 \dec_MUL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 \dec_MUL_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 24 \dec_MUL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_MUL_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_MUL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_MUL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 \dec_MUL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 \dec_MUL_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_MUL_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_MUL_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec_MUL_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec_MUL_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec_MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec_MUL_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec_MUL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec_MUL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 6 \dec_MUL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_bi_imm_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_oe_oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_rc_rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" - wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" - wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 input 14 \raw_opcode_in - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:107283.13-107313.4" - cell \dec$177 \dec - connect \MUL_BA \dec_MUL_BA - connect \MUL_BB \dec_MUL_BB - connect \MUL_BC \dec_MUL_BC - connect \MUL_BD \dec_MUL_BD - connect \MUL_BI \dec_MUL_BI - connect \MUL_BT \dec_MUL_BT - connect \MUL_DS \dec_MUL_DS - connect \MUL_FXM \dec_MUL_FXM - connect \MUL_LI \dec_MUL_LI - connect \MUL_OE \dec_MUL_OE - connect \MUL_Rc \dec_MUL_Rc - connect \MUL_SH32 \dec_MUL_SH32 - connect \MUL_SI \dec_MUL_SI - connect \MUL_UI \dec_MUL_UI - connect \MUL_cr_in \dec_MUL_cr_in - connect \MUL_cr_out \dec_MUL_cr_out - connect \MUL_function_unit \dec_MUL_function_unit - connect \MUL_in2_sel \dec_MUL_in2_sel - connect \MUL_internal_op \dec_MUL_internal_op - connect \MUL_is_32b \dec_MUL_is_32b - connect \MUL_rc_sel \dec_MUL_rc_sel - connect \MUL_sgn \dec_MUL_sgn - connect \MUL_sh \dec_MUL_sh - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \raw_opcode_in \raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:107314.16-107325.4" - cell \dec_bi$184 \dec_bi - connect \MUL_BD \dec_MUL_BD - connect \MUL_DS \dec_MUL_DS - connect \MUL_LI \dec_MUL_LI - connect \MUL_SH32 \dec_MUL_SH32 - connect \MUL_SI \dec_MUL_SI - connect \MUL_UI \dec_MUL_UI - connect \MUL_sh \dec_MUL_sh - connect \imm_b \dec_bi_imm_b - connect \imm_b_ok \dec_bi_imm_b_ok - connect \sel_in \dec_bi_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:107326.19-107337.4" - cell \dec_cr_in$180 \dec_cr_in - connect \MUL_BA \dec_MUL_BA - connect \MUL_BB \dec_MUL_BB - connect \MUL_BC \dec_MUL_BC - connect \MUL_BI \dec_MUL_BI - connect \MUL_BT \dec_MUL_BT - connect \MUL_FXM \dec_MUL_FXM - connect \MUL_internal_op \dec_MUL_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:107338.20-107347.4" - cell \dec_cr_out$182 \dec_cr_out - connect \MUL_FXM \dec_MUL_FXM - connect \MUL_internal_op \dec_MUL_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:107348.16-107354.4" - cell \dec_oe$179 \dec_oe - connect \MUL_OE \dec_MUL_OE - connect \MUL_internal_op \dec_MUL_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \sel_in \dec_oe_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:107355.16-107360.4" - cell \dec_rc$178 \dec_rc - connect \MUL_Rc \dec_MUL_Rc - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \sel_in \dec_rc_sel_in - end - connect \MUL_MUL__is_signed \dec_MUL_sgn - connect \MUL_MUL__is_32bit \dec_MUL_is_32b - connect \MUL_MUL__write_cr0 \dec_cr_out_cr_bitfield_ok - connect { \MUL_MUL__oe__ok \MUL_MUL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \MUL_MUL__rc__ok \MUL_MUL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - connect { \MUL_MUL__imm_data__ok \MUL_MUL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } - connect \dec_bi_sel_in \dec_MUL_in2_sel - connect \MUL_MUL__fn_unit \dec_MUL_function_unit - connect \MUL_MUL__insn_type \dec_MUL_internal_op - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_MUL_cr_out - connect \dec_cr_in_sel_in \dec_MUL_cr_in - connect \dec_oe_sel_in \dec_MUL_rc_sel - connect \dec_rc_sel_in \dec_MUL_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in - connect \insn_in$1 \dec_opcode_in - connect \insn_in \dec_opcode_in - connect \MUL_MUL__insn \dec_opcode_in -end -attribute \src "issuer_ls180.v:107384.1-107868.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT" -attribute \generator "nMigen" -module \dec_SHIFT_ROT - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \SHIFT_ROT_SHIFT_ROT__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \SHIFT_ROT_SHIFT_ROT__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \SHIFT_ROT_SHIFT_ROT__imm_data__ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 11 \SHIFT_ROT_SHIFT_ROT__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \SHIFT_ROT_SHIFT_ROT__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 17 \SHIFT_ROT_SHIFT_ROT__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \SHIFT_ROT_SHIFT_ROT__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \SHIFT_ROT_SHIFT_ROT__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \SHIFT_ROT_SHIFT_ROT__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \SHIFT_ROT_SHIFT_ROT__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \SHIFT_ROT_SHIFT_ROT__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \SHIFT_ROT_SHIFT_ROT__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \SHIFT_ROT_SHIFT_ROT__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \SHIFT_ROT_SHIFT_ROT__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \SHIFT_ROT_SHIFT_ROT__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \SHIFT_ROT_SHIFT_ROT__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_SHIFT_ROT_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_SHIFT_ROT_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_SHIFT_ROT_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 \dec_SHIFT_ROT_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_SHIFT_ROT_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_SHIFT_ROT_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 \dec_SHIFT_ROT_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 \dec_SHIFT_ROT_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 24 \dec_SHIFT_ROT_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_SHIFT_ROT_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_SHIFT_ROT_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_SHIFT_ROT_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 \dec_SHIFT_ROT_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 \dec_SHIFT_ROT_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_SHIFT_ROT_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_SHIFT_ROT_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec_SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec_SHIFT_ROT_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec_SHIFT_ROT_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 4 \dec_SHIFT_ROT_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 \dec_SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec_SHIFT_ROT_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 \dec_SHIFT_ROT_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire \dec_SHIFT_ROT_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 6 \dec_SHIFT_ROT_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_bi_imm_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_oe_oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec_rc_rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" - wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" - wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 input 18 \raw_opcode_in - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:107765.13-107797.4" - cell \dec$185 \dec - connect \SHIFT_ROT_BA \dec_SHIFT_ROT_BA - connect \SHIFT_ROT_BB \dec_SHIFT_ROT_BB - connect \SHIFT_ROT_BC \dec_SHIFT_ROT_BC - connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD - connect \SHIFT_ROT_BI \dec_SHIFT_ROT_BI - connect \SHIFT_ROT_BT \dec_SHIFT_ROT_BT - connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS - connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM - connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI - connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE - connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc - connect \SHIFT_ROT_SH32 \dec_SHIFT_ROT_SH32 - connect \SHIFT_ROT_SI \dec_SHIFT_ROT_SI - connect \SHIFT_ROT_UI \dec_SHIFT_ROT_UI - connect \SHIFT_ROT_cr_in \dec_SHIFT_ROT_cr_in - connect \SHIFT_ROT_cr_out \dec_SHIFT_ROT_cr_out - connect \SHIFT_ROT_cry_in \dec_SHIFT_ROT_cry_in - connect \SHIFT_ROT_cry_out \dec_SHIFT_ROT_cry_out - connect \SHIFT_ROT_function_unit \dec_SHIFT_ROT_function_unit - connect \SHIFT_ROT_in2_sel \dec_SHIFT_ROT_in2_sel - connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op - connect \SHIFT_ROT_is_32b \dec_SHIFT_ROT_is_32b - connect \SHIFT_ROT_rc_sel \dec_SHIFT_ROT_rc_sel - connect \SHIFT_ROT_sgn \dec_SHIFT_ROT_sgn - connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \raw_opcode_in \raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:107798.16-107809.4" - cell \dec_bi$192 \dec_bi - connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD - connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS - connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI - connect \SHIFT_ROT_SH32 \dec_SHIFT_ROT_SH32 - connect \SHIFT_ROT_SI \dec_SHIFT_ROT_SI - connect \SHIFT_ROT_UI \dec_SHIFT_ROT_UI - connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh - connect \imm_b \dec_bi_imm_b - connect \imm_b_ok \dec_bi_imm_b_ok - connect \sel_in \dec_bi_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:107810.19-107821.4" - cell \dec_cr_in$188 \dec_cr_in - connect \SHIFT_ROT_BA \dec_SHIFT_ROT_BA - connect \SHIFT_ROT_BB \dec_SHIFT_ROT_BB - connect \SHIFT_ROT_BC \dec_SHIFT_ROT_BC - connect \SHIFT_ROT_BI \dec_SHIFT_ROT_BI - connect \SHIFT_ROT_BT \dec_SHIFT_ROT_BT - connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM - connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:107822.20-107831.4" - cell \dec_cr_out$190 \dec_cr_out - connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM - connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:107832.16-107838.4" - cell \dec_oe$187 \dec_oe - connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE - connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \sel_in \dec_oe_sel_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:107839.16-107844.4" - cell \dec_rc$186 \dec_rc - connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \sel_in \dec_rc_sel_in - end - connect \SHIFT_ROT_SHIFT_ROT__is_signed \dec_SHIFT_ROT_sgn - connect \SHIFT_ROT_SHIFT_ROT__is_32bit \dec_SHIFT_ROT_is_32b - connect \SHIFT_ROT_SHIFT_ROT__output_carry \dec_SHIFT_ROT_cry_out - connect \SHIFT_ROT_SHIFT_ROT__input_carry \dec_SHIFT_ROT_cry_in - connect \SHIFT_ROT_SHIFT_ROT__output_cr \dec_SHIFT_ROT_cr_out [0] - connect \SHIFT_ROT_SHIFT_ROT__input_cr \dec_SHIFT_ROT_cr_in [0] - connect \SHIFT_ROT_SHIFT_ROT__write_cr0 \dec_cr_out_cr_bitfield_ok - connect { \SHIFT_ROT_SHIFT_ROT__oe__ok \SHIFT_ROT_SHIFT_ROT__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \SHIFT_ROT_SHIFT_ROT__rc__ok \SHIFT_ROT_SHIFT_ROT__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - connect { \SHIFT_ROT_SHIFT_ROT__imm_data__ok \SHIFT_ROT_SHIFT_ROT__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } - connect \dec_bi_sel_in \dec_SHIFT_ROT_in2_sel - connect \SHIFT_ROT_SHIFT_ROT__fn_unit \dec_SHIFT_ROT_function_unit - connect \SHIFT_ROT_SHIFT_ROT__insn_type \dec_SHIFT_ROT_internal_op - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_SHIFT_ROT_cr_out - connect \dec_cr_in_sel_in \dec_SHIFT_ROT_cr_in - connect \dec_oe_sel_in \dec_SHIFT_ROT_rc_sel - connect \dec_rc_sel_in \dec_SHIFT_ROT_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in - connect \insn_in$1 \dec_opcode_in - connect \insn_in \dec_opcode_in - connect \SHIFT_ROT_SHIFT_ROT__insn \dec_opcode_in -end -attribute \src "issuer_ls180.v:107872.1-108221.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR" -attribute \generator "nMigen" -module \dec_SPR - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \SPR_SPR__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 4 \SPR_SPR__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \SPR_SPR__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \SPR_SPR__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_SPR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_SPR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_SPR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_SPR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 \dec_SPR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 \dec_SPR_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_SPR_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire \dec_SPR_Rc - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_SPR_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 3 \dec_SPR_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 12 \dec_SPR_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 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1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - switch \$21 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg_a_ok[0:0] 1'1 - case - assign $1\reg_a_ok[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" - switch \$23 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reg_a_ok[0:0] 1'1 - case - assign $2\reg_a_ok[0:0] $1\reg_a_ok[0:0] - end - sync always - update \reg_a_ok $0\reg_a_ok[0:0] - end - attribute \src "issuer_ls180.v:108659.3-108694.6" - process $proc$issuer_ls180.v:108659$4115 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fast_a[2:0] $1\fast_a[2:0] - assign $0\fast_a_ok[0:0] $1\fast_a_ok[0:0] - attribute \src "issuer_ls180.v:108660.5-108660.29" - switch \initial - attribute \src "issuer_ls180.v:108660.9-108660.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - switch \internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000111 - assign { } { } - assign { } { } - assign $1\fast_a[2:0] $2\fast_a[2:0] - assign $1\fast_a_ok[0:0] $2\fast_a_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" - switch \$25 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $2\fast_a[2:0] 3'000 - assign $2\fast_a_ok[0:0] 1'1 - case - assign $2\fast_a[2:0] 3'000 - assign $2\fast_a_ok[0:0] 1'0 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001000 - assign { } { } - assign { } { } - assign $1\fast_a[2:0] $3\fast_a[2:0] - assign $1\fast_a_ok[0:0] $3\fast_a_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" - switch \$29 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $3\fast_a[2:0] 3'000 - assign $3\fast_a_ok[0:0] 1'1 - case - assign $3\fast_a[2:0] 3'000 - assign $3\fast_a_ok[0:0] 1'0 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0101110 - assign { } { } - assign { } { } - assign { $1\fast_a_ok[0:0] $1\fast_a[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } - case - assign $1\fast_a[2:0] 3'000 - assign $1\fast_a_ok[0:0] 1'0 - end - sync always - update \fast_a $0\fast_a[2:0] - update \fast_a_ok $0\fast_a_ok[0:0] - end - attribute \src "issuer_ls180.v:108695.3-108705.6" - process $proc$issuer_ls180.v:108695$4116 - assign { } { } - assign { } { } - assign $0\spr[9:0] $1\spr[9:0] - attribute \src "issuer_ls180.v:108696.5-108696.29" - switch \initial - attribute \src "issuer_ls180.v:108696.9-108696.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - switch \internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0101110 - assign { } { } - assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } - case - assign $1\spr[9:0] 10'0000000000 - end - sync always - update \spr $0\spr[9:0] - end - attribute \src "issuer_ls180.v:108706.3-108716.6" - process $proc$issuer_ls180.v:108706$4117 - assign { } { } - assign { } { } - assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] - attribute \src "issuer_ls180.v:108707.5-108707.29" - switch \initial - attribute \src "issuer_ls180.v:108707.9-108707.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - switch \internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0101110 - assign { } { } - assign $1\sprmap_spr_i[9:0] \spr - case - assign $1\sprmap_spr_i[9:0] 10'0000000000 - end - sync always - update \sprmap_spr_i $0\sprmap_spr_i[9:0] - end - attribute \src "issuer_ls180.v:108717.3-108728.6" - process $proc$issuer_ls180.v:108717$4118 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\spr_a[9:0] $1\spr_a[9:0] - assign $0\spr_a_ok[0:0] $1\spr_a_ok[0:0] - attribute \src "issuer_ls180.v:108718.5-108718.29" - switch \initial - attribute \src "issuer_ls180.v:108718.9-108718.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - switch \internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0101110 - assign { } { } - assign { } { } - assign { $1\spr_a_ok[0:0] $1\spr_a[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } - case - assign $1\spr_a[9:0] 10'0000000000 - assign $1\spr_a_ok[0:0] 1'0 - end - sync always - update \spr_a $0\spr_a[9:0] - update \spr_a_ok $0\spr_a_ok[0:0] - end - connect \$9 $or$issuer_ls180.v:108605$4098_Y - connect \$11 $eq$issuer_ls180.v:108606$4099_Y - connect \$13 $eq$issuer_ls180.v:108607$4100_Y - connect \$15 $eq$issuer_ls180.v:108608$4101_Y - connect \$17 $ne$issuer_ls180.v:108609$4102_Y - connect \$1 $eq$issuer_ls180.v:108610$4103_Y - connect \$19 $and$issuer_ls180.v:108611$4104_Y - connect \$21 $or$issuer_ls180.v:108612$4105_Y - connect \$23 $eq$issuer_ls180.v:108613$4106_Y - connect \$25 $not$issuer_ls180.v:108614$4107_Y - connect \$27 $not$issuer_ls180.v:108615$4108_Y - connect \$29 $and$issuer_ls180.v:108616$4109_Y - connect \$3 $eq$issuer_ls180.v:108617$4110_Y - connect \$5 $ne$issuer_ls180.v:108618$4111_Y - connect \$7 $and$issuer_ls180.v:108619$4112_Y - connect \ra \RA -end -attribute \src "issuer_ls180.v:108734.1-108771.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_ai" -attribute \generator "nMigen" -module \dec_ai - attribute \src "issuer_ls180.v:108760.3-108769.6" - wire $0\immz_out[0:0] - attribute \src "issuer_ls180.v:108735.7-108735.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:108760.3-108769.6" - wire $1\immz_out[0:0] - attribute \src "issuer_ls180.v:108759.17-108759.107" - wire $and$issuer_ls180.v:108759$4122_Y - attribute \src "issuer_ls180.v:108757.17-108757.111" - wire $eq$issuer_ls180.v:108757$4120_Y - attribute \src "issuer_ls180.v:108758.17-108758.108" - wire $eq$issuer_ls180.v:108758$4121_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 2 \ALU_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" - wire output 1 \immz_out - attribute \src "issuer_ls180.v:108735.7-108735.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:156" - wire width 5 \ra - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" - wire width 3 input 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $and $and$issuer_ls180.v:108759$4122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \$3 - connect \Y $and$issuer_ls180.v:108759$4122_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $eq $eq$issuer_ls180.v:108757$4120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'010 - connect \Y $eq$issuer_ls180.v:108757$4120_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $eq $eq$issuer_ls180.v:108758$4121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \ra - connect \B 5'00000 - connect \Y $eq$issuer_ls180.v:108758$4121_Y - end - attribute \src "issuer_ls180.v:108735.7-108735.20" - process $proc$issuer_ls180.v:108735$4124 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:108760.3-108769.6" - process $proc$issuer_ls180.v:108760$4123 - assign { } { } - assign { } { } - assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "issuer_ls180.v:108761.5-108761.29" - switch \initial - attribute \src "issuer_ls180.v:108761.9-108761.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - switch \$5 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\immz_out[0:0] 1'1 - case - assign $1\immz_out[0:0] 1'0 - end - sync always - update \immz_out $0\immz_out[0:0] - end - connect \$1 $eq$issuer_ls180.v:108757$4120_Y - connect \$3 $eq$issuer_ls180.v:108758$4121_Y - connect \$5 $and$issuer_ls180.v:108759$4122_Y - connect \ra \ALU_RA -end -attribute \src "issuer_ls180.v:108775.1-108812.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_ai" -attribute \generator "nMigen" -module \dec_ai$159 - attribute \src "issuer_ls180.v:108801.3-108810.6" - wire $0\immz_out[0:0] - attribute \src "issuer_ls180.v:108776.7-108776.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:108801.3-108810.6" - wire $1\immz_out[0:0] - attribute \src "issuer_ls180.v:108800.17-108800.107" - wire $and$issuer_ls180.v:108800$4127_Y - attribute \src "issuer_ls180.v:108798.17-108798.111" - wire $eq$issuer_ls180.v:108798$4125_Y - attribute \src "issuer_ls180.v:108799.17-108799.108" - wire $eq$issuer_ls180.v:108799$4126_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 2 \LOGICAL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" - wire output 1 \immz_out - attribute \src "issuer_ls180.v:108776.7-108776.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:156" - wire width 5 \ra - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" - wire width 3 input 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $and $and$issuer_ls180.v:108800$4127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \$3 - connect \Y $and$issuer_ls180.v:108800$4127_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $eq $eq$issuer_ls180.v:108798$4125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'010 - connect \Y $eq$issuer_ls180.v:108798$4125_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $eq $eq$issuer_ls180.v:108799$4126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \ra - connect \B 5'00000 - connect \Y $eq$issuer_ls180.v:108799$4126_Y - end - attribute \src "issuer_ls180.v:108776.7-108776.20" - process $proc$issuer_ls180.v:108776$4129 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:108801.3-108810.6" - process $proc$issuer_ls180.v:108801$4128 - assign { } { } - assign { } { } - assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "issuer_ls180.v:108802.5-108802.29" - switch \initial - attribute \src "issuer_ls180.v:108802.9-108802.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - switch \$5 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\immz_out[0:0] 1'1 - case - assign $1\immz_out[0:0] 1'0 - end - sync always - update \immz_out $0\immz_out[0:0] - end - connect \$1 $eq$issuer_ls180.v:108798$4125_Y - connect \$3 $eq$issuer_ls180.v:108799$4126_Y - connect \$5 $and$issuer_ls180.v:108800$4127_Y - connect \ra \LOGICAL_RA -end -attribute \src "issuer_ls180.v:108816.1-108853.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_ai" -attribute \generator "nMigen" -module \dec_ai$175 - attribute \src "issuer_ls180.v:108842.3-108851.6" - wire $0\immz_out[0:0] - attribute \src "issuer_ls180.v:108817.7-108817.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:108842.3-108851.6" - wire $1\immz_out[0:0] - attribute \src "issuer_ls180.v:108841.17-108841.107" - wire $and$issuer_ls180.v:108841$4132_Y - attribute \src "issuer_ls180.v:108839.17-108839.111" - wire $eq$issuer_ls180.v:108839$4130_Y - attribute \src "issuer_ls180.v:108840.17-108840.108" - wire $eq$issuer_ls180.v:108840$4131_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 2 \DIV_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" - wire output 1 \immz_out - attribute \src "issuer_ls180.v:108817.7-108817.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:156" - wire width 5 \ra - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" - wire width 3 input 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $and $and$issuer_ls180.v:108841$4132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \$3 - connect \Y $and$issuer_ls180.v:108841$4132_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $eq $eq$issuer_ls180.v:108839$4130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'010 - connect \Y $eq$issuer_ls180.v:108839$4130_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $eq $eq$issuer_ls180.v:108840$4131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \ra - connect \B 5'00000 - connect \Y $eq$issuer_ls180.v:108840$4131_Y - end - attribute \src "issuer_ls180.v:108817.7-108817.20" - process $proc$issuer_ls180.v:108817$4134 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:108842.3-108851.6" - process $proc$issuer_ls180.v:108842$4133 - assign { } { } - assign { } { } - assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "issuer_ls180.v:108843.5-108843.29" - switch \initial - attribute \src "issuer_ls180.v:108843.9-108843.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - switch \$5 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\immz_out[0:0] 1'1 - case - assign $1\immz_out[0:0] 1'0 - end - sync always - update \immz_out $0\immz_out[0:0] - end - connect \$1 $eq$issuer_ls180.v:108839$4130_Y - connect \$3 $eq$issuer_ls180.v:108840$4131_Y - connect \$5 $and$issuer_ls180.v:108841$4132_Y - connect \ra \DIV_RA -end -attribute \src "issuer_ls180.v:108857.1-108894.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_ai" -attribute \generator "nMigen" -module \dec_ai$200 - attribute \src "issuer_ls180.v:108883.3-108892.6" - wire $0\immz_out[0:0] - attribute \src "issuer_ls180.v:108858.7-108858.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:108883.3-108892.6" - wire $1\immz_out[0:0] - attribute \src "issuer_ls180.v:108882.17-108882.107" - wire $and$issuer_ls180.v:108882$4137_Y - attribute \src "issuer_ls180.v:108880.17-108880.111" - wire $eq$issuer_ls180.v:108880$4135_Y - attribute \src "issuer_ls180.v:108881.17-108881.108" - wire $eq$issuer_ls180.v:108881$4136_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 2 \LDST_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" - wire output 1 \immz_out - attribute \src "issuer_ls180.v:108858.7-108858.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:156" - wire width 5 \ra - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" - wire width 3 input 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $and $and$issuer_ls180.v:108882$4137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \$3 - connect \Y $and$issuer_ls180.v:108882$4137_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $eq $eq$issuer_ls180.v:108880$4135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - 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attribute \src "issuer_ls180.v:109038.3-109052.6" - wire $0\reg_b_ok[0:0] - attribute \src "issuer_ls180.v:109053.3-109070.6" - wire width 3 $1\fast_b[2:0] - attribute \src "issuer_ls180.v:109071.3-109088.6" - wire $1\fast_b_ok[0:0] - attribute \src "issuer_ls180.v:109023.3-109037.6" - wire width 5 $1\reg_b[4:0] - attribute \src "issuer_ls180.v:109038.3-109052.6" - wire $1\reg_b_ok[0:0] - attribute \src "issuer_ls180.v:109053.3-109070.6" - wire width 3 $2\fast_b[2:0] - attribute \src "issuer_ls180.v:109071.3-109088.6" - wire $2\fast_b_ok[0:0] - attribute \src "issuer_ls180.v:109019.17-109019.117" - wire $eq$issuer_ls180.v:109019$4140_Y - attribute \src "issuer_ls180.v:109021.17-109021.117" - wire $eq$issuer_ls180.v:109021$4142_Y - attribute \src "issuer_ls180.v:109020.17-109020.107" - wire $not$issuer_ls180.v:109020$4141_Y - attribute \src "issuer_ls180.v:109022.17-109022.107" - wire $not$issuer_ls180.v:109022$4143_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 7 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 6 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 10 input 8 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 4 \fast_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 5 \fast_b_ok - attribute \src "issuer_ls180.v:108899.7-108899.15" - wire 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\enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 9 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 output 2 \reg_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \reg_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - wire width 4 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" - cell $eq $eq$issuer_ls180.v:109019$4140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0001000 - connect \Y $eq$issuer_ls180.v:109019$4140_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" - cell $eq $eq$issuer_ls180.v:109021$4142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0001000 - connect \Y $eq$issuer_ls180.v:109021$4142_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - cell $not $not$issuer_ls180.v:109020$4141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [9] - connect \Y $not$issuer_ls180.v:109020$4141_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - cell $not $not$issuer_ls180.v:109022$4143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [9] - connect \Y $not$issuer_ls180.v:109022$4143_Y - end - attribute \src "issuer_ls180.v:108899.7-108899.20" - process $proc$issuer_ls180.v:108899$4148 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:109023.3-109037.6" - process $proc$issuer_ls180.v:109023$4144 - assign { } { } - assign { } { } - assign $0\reg_b[4:0] $1\reg_b[4:0] - attribute \src "issuer_ls180.v:109024.5-109024.29" - switch \initial - attribute \src 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"issuer_ls180.v:0.0-0.0" - case 4'1101 - assign { } { } - assign $1\reg_b_ok[0:0] 1'1 - case - assign $1\reg_b_ok[0:0] 1'0 - end - sync always - update \reg_b_ok $0\reg_b_ok[0:0] - end - attribute \src "issuer_ls180.v:109053.3-109070.6" - process $proc$issuer_ls180.v:109053$4146 - assign { } { } - assign { } { } - assign $0\fast_b[2:0] $1\fast_b[2:0] - attribute \src "issuer_ls180.v:109054.5-109054.29" - switch \initial - attribute \src "issuer_ls180.v:109054.9-109054.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fast_b[2:0] $2\fast_b[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - switch { \XL_XO [5] \$3 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\fast_b[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - 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wire width 27 $sshl$issuer_ls180.v:109175$4154_Y - attribute \src "issuer_ls180.v:109177.18-109177.113" - wire width 17 $sshl$issuer_ls180.v:109177$4157_Y - attribute \src "issuer_ls180.v:109178.18-109178.113" - wire width 17 $sshl$issuer_ls180.v:109178$4158_Y - attribute \src "issuer_ls180.v:109179.17-109179.109" - wire width 47 $sshl$issuer_ls180.v:109179$4159_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" - wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 input 8 \ALU_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 input 9 \ALU_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 24 input 7 \ALU_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 5 \ALU_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 input 3 \ALU_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 input 4 \ALU_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 6 input 6 \ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" - wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \imm_b_ok - attribute \src "issuer_ls180.v:109094.7-109094.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 26 \li - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" - wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$issuer_ls180.v:109172$4149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \ALU_sh - connect \Y $extend$issuer_ls180.v:109172$4149_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$issuer_ls180.v:109173$4151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \ALU_SH32 - connect \Y $extend$issuer_ls180.v:109173$4151_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$issuer_ls180.v:109176$4155 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \ALU_UI - connect \Y $extend$issuer_ls180.v:109176$4155_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $extend$issuer_ls180.v:109180$4160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A \$4 - connect \Y $extend$issuer_ls180.v:109180$4160_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$issuer_ls180.v:109172$4150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:109172$4149_Y - connect \Y $pos$issuer_ls180.v:109172$4150_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$issuer_ls180.v:109173$4152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:109173$4151_Y - connect \Y $pos$issuer_ls180.v:109173$4152_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$issuer_ls180.v:109176$4156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:109176$4155_Y - connect \Y $pos$issuer_ls180.v:109176$4156_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $pos$issuer_ls180.v:109180$4161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:109180$4160_Y - connect \Y $pos$issuer_ls180.v:109180$4161_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - cell $sshl $sshl$issuer_ls180.v:109174$4153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ALU_SI - connect \B 5'10000 - connect \Y $sshl$issuer_ls180.v:109174$4153_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - cell $sshl $sshl$issuer_ls180.v:109175$4154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \ALU_LI - connect \B 2'10 - connect \Y $sshl$issuer_ls180.v:109175$4154_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $sshl$issuer_ls180.v:109177$4157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \ALU_BD - connect \B 2'10 - connect \Y $sshl$issuer_ls180.v:109177$4157_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$issuer_ls180.v:109178$4158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \ALU_DS - connect \B 2'10 - connect \Y $sshl$issuer_ls180.v:109178$4158_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $sshl $sshl$issuer_ls180.v:109179$4159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $sshl$issuer_ls180.v:109179$4159_Y - end - attribute \src "issuer_ls180.v:109094.7-109094.20" - process $proc$issuer_ls180.v:109094$4170 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:109182.3-109228.6" - process $proc$issuer_ls180.v:109182$4162 - assign { } { } - assign { } { } - assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "issuer_ls180.v:109183.5-109183.29" - switch \initial - attribute \src "issuer_ls180.v:109183.9-109183.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b[63:0] \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b[63:0] \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b[63:0] \$7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b[63:0] \$9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b[63:0] \$11 - case - assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \imm_b $0\imm_b[63:0] - end - attribute \src "issuer_ls180.v:109229.3-109275.6" - process $proc$issuer_ls180.v:109229$4163 - assign { } { } - assign { } { } - assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "issuer_ls180.v:109230.5-109230.29" - switch \initial - attribute \src "issuer_ls180.v:109230.9-109230.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - case - assign $1\imm_b_ok[0:0] 1'0 - end - sync always - update \imm_b_ok $0\imm_b_ok[0:0] - end - attribute \src "issuer_ls180.v:109276.3-109286.6" - process $proc$issuer_ls180.v:109276$4164 - assign { } { } - assign { } { } - assign $0\si[15:0] $1\si[15:0] - attribute \src "issuer_ls180.v:109277.5-109277.29" - switch \initial - attribute \src "issuer_ls180.v:109277.9-109277.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\si[15:0] \ALU_SI - case - assign $1\si[15:0] 16'0000000000000000 - end - sync always - update \si $0\si[15:0] - end - attribute \src "issuer_ls180.v:109287.3-109297.6" - process $proc$issuer_ls180.v:109287$4165 - assign { } { } - assign { } { } - assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "issuer_ls180.v:109288.5-109288.29" - switch \initial - attribute \src "issuer_ls180.v:109288.9-109288.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\si_hi[31:0] \$13 [31:0] - case - assign $1\si_hi[31:0] 0 - end - sync always - update \si_hi $0\si_hi[31:0] - end - attribute \src "issuer_ls180.v:109298.3-109308.6" - process $proc$issuer_ls180.v:109298$4166 - assign { } { } - assign { } { } - assign $0\ui[15:0] $1\ui[15:0] - attribute \src "issuer_ls180.v:109299.5-109299.29" - switch \initial - attribute \src "issuer_ls180.v:109299.9-109299.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\ui[15:0] \ALU_UI - case - assign $1\ui[15:0] 16'0000000000000000 - end - sync always - update \ui $0\ui[15:0] - end - attribute \src "issuer_ls180.v:109309.3-109319.6" - process $proc$issuer_ls180.v:109309$4167 - assign { } { } - assign { } { } - assign $0\li[25:0] $1\li[25:0] - attribute \src "issuer_ls180.v:109310.5-109310.29" - switch \initial - attribute \src "issuer_ls180.v:109310.9-109310.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\li[25:0] \$16 [25:0] - case - assign $1\li[25:0] 26'00000000000000000000000000 - end - sync always - update \li $0\li[25:0] - end - attribute \src "issuer_ls180.v:109320.3-109330.6" - process $proc$issuer_ls180.v:109320$4168 - assign { } { } - assign { } { } - assign $0\bd[15:0] $1\bd[15:0] - attribute \src "issuer_ls180.v:109321.5-109321.29" - switch \initial - attribute \src "issuer_ls180.v:109321.9-109321.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\bd[15:0] \$19 [15:0] - case - assign $1\bd[15:0] 16'0000000000000000 - end - sync always - update \bd $0\bd[15:0] - end - attribute \src "issuer_ls180.v:109331.3-109341.6" - process $proc$issuer_ls180.v:109331$4169 - assign { } { } - assign { } { } - assign $0\ds[15:0] $1\ds[15:0] - attribute \src "issuer_ls180.v:109332.5-109332.29" - switch \initial - attribute \src "issuer_ls180.v:109332.9-109332.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\ds[15:0] \$22 [15:0] - case - assign $1\ds[15:0] 16'0000000000000000 - end - sync always - update \ds $0\ds[15:0] - end - connect \$9 $pos$issuer_ls180.v:109172$4150_Y - connect \$11 $pos$issuer_ls180.v:109173$4152_Y - connect \$14 $sshl$issuer_ls180.v:109174$4153_Y - connect \$17 $sshl$issuer_ls180.v:109175$4154_Y - connect \$1 $pos$issuer_ls180.v:109176$4156_Y - connect \$20 $sshl$issuer_ls180.v:109177$4157_Y - connect \$23 $sshl$issuer_ls180.v:109178$4158_Y - connect \$4 $sshl$issuer_ls180.v:109179$4159_Y - connect \$3 $pos$issuer_ls180.v:109180$4161_Y - connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 - connect \$13 \$14 - connect \$16 \$17 - connect \$19 \$20 - connect \$22 \$23 -end -attribute \src "issuer_ls180.v:109350.1-109603.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_bi" -attribute \generator "nMigen" -module \dec_bi$151 - attribute \src "issuer_ls180.v:109577.3-109587.6" - wire width 16 $0\bd[15:0] - attribute \src "issuer_ls180.v:109588.3-109598.6" - wire width 16 $0\ds[15:0] - attribute \src "issuer_ls180.v:109439.3-109485.6" - wire width 64 $0\imm_b[63:0] - attribute \src "issuer_ls180.v:109486.3-109532.6" - wire $0\imm_b_ok[0:0] - attribute \src "issuer_ls180.v:109351.7-109351.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:109566.3-109576.6" - wire width 26 $0\li[25:0] - attribute \src "issuer_ls180.v:109533.3-109543.6" - wire width 16 $0\si[15:0] - attribute \src "issuer_ls180.v:109544.3-109554.6" - wire width 32 $0\si_hi[31:0] - attribute \src "issuer_ls180.v:109555.3-109565.6" - wire width 16 $0\ui[15:0] - attribute \src "issuer_ls180.v:109577.3-109587.6" - wire width 16 $1\bd[15:0] - attribute \src "issuer_ls180.v:109588.3-109598.6" - wire width 16 $1\ds[15:0] - attribute \src "issuer_ls180.v:109439.3-109485.6" - wire width 64 $1\imm_b[63:0] - attribute \src "issuer_ls180.v:109486.3-109532.6" - wire $1\imm_b_ok[0:0] - attribute \src "issuer_ls180.v:109566.3-109576.6" - wire width 26 $1\li[25:0] - attribute \src "issuer_ls180.v:109533.3-109543.6" - wire width 16 $1\si[15:0] - attribute \src "issuer_ls180.v:109544.3-109554.6" - wire width 32 $1\si_hi[31:0] - attribute \src "issuer_ls180.v:109555.3-109565.6" - wire width 16 $1\ui[15:0] - attribute \src "issuer_ls180.v:109429.17-109429.107" - wire width 64 $extend$issuer_ls180.v:109429$4171_Y - attribute \src "issuer_ls180.v:109430.18-109430.110" - wire width 64 $extend$issuer_ls180.v:109430$4173_Y - attribute \src "issuer_ls180.v:109433.17-109433.107" - wire width 64 $extend$issuer_ls180.v:109433$4177_Y - attribute \src "issuer_ls180.v:109437.17-109437.102" - wire width 64 $extend$issuer_ls180.v:109437$4182_Y - attribute \src "issuer_ls180.v:109429.17-109429.107" - wire width 64 $pos$issuer_ls180.v:109429$4172_Y - attribute \src "issuer_ls180.v:109430.18-109430.110" - wire width 64 $pos$issuer_ls180.v:109430$4174_Y - attribute \src "issuer_ls180.v:109433.17-109433.107" - wire width 64 $pos$issuer_ls180.v:109433$4178_Y - attribute \src "issuer_ls180.v:109437.17-109437.102" - wire width 64 $pos$issuer_ls180.v:109437$4183_Y - attribute \src "issuer_ls180.v:109431.18-109431.117" - wire width 47 $sshl$issuer_ls180.v:109431$4175_Y - attribute \src "issuer_ls180.v:109432.18-109432.116" - wire width 27 $sshl$issuer_ls180.v:109432$4176_Y - attribute \src "issuer_ls180.v:109434.18-109434.116" - wire width 17 $sshl$issuer_ls180.v:109434$4179_Y - attribute \src "issuer_ls180.v:109435.18-109435.116" - wire width 17 $sshl$issuer_ls180.v:109435$4180_Y - attribute \src "issuer_ls180.v:109436.17-109436.109" - wire width 47 $sshl$issuer_ls180.v:109436$4181_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" - wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 input 8 \BRANCH_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 input 9 \BRANCH_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 24 input 7 \BRANCH_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 5 \BRANCH_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 input 3 \BRANCH_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 input 4 \BRANCH_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 6 input 6 \BRANCH_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" - wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \imm_b_ok - attribute \src "issuer_ls180.v:109351.7-109351.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 26 \li - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" - wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$issuer_ls180.v:109429$4171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \BRANCH_sh - connect \Y $extend$issuer_ls180.v:109429$4171_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$issuer_ls180.v:109430$4173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \BRANCH_SH32 - connect \Y $extend$issuer_ls180.v:109430$4173_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$issuer_ls180.v:109433$4177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \BRANCH_UI - connect \Y $extend$issuer_ls180.v:109433$4177_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $extend$issuer_ls180.v:109437$4182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A \$4 - connect \Y $extend$issuer_ls180.v:109437$4182_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$issuer_ls180.v:109429$4172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:109429$4171_Y - connect \Y $pos$issuer_ls180.v:109429$4172_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$issuer_ls180.v:109430$4174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:109430$4173_Y - connect \Y $pos$issuer_ls180.v:109430$4174_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$issuer_ls180.v:109433$4178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:109433$4177_Y - connect \Y $pos$issuer_ls180.v:109433$4178_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $pos$issuer_ls180.v:109437$4183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:109437$4182_Y - connect \Y $pos$issuer_ls180.v:109437$4183_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - cell $sshl $sshl$issuer_ls180.v:109431$4175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \BRANCH_SI - connect \B 5'10000 - connect \Y $sshl$issuer_ls180.v:109431$4175_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - cell $sshl $sshl$issuer_ls180.v:109432$4176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \BRANCH_LI - connect \B 2'10 - connect \Y $sshl$issuer_ls180.v:109432$4176_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $sshl$issuer_ls180.v:109434$4179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \BRANCH_BD - connect \B 2'10 - connect \Y $sshl$issuer_ls180.v:109434$4179_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$issuer_ls180.v:109435$4180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \BRANCH_DS - connect \B 2'10 - connect \Y $sshl$issuer_ls180.v:109435$4180_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $sshl $sshl$issuer_ls180.v:109436$4181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $sshl$issuer_ls180.v:109436$4181_Y - end - attribute \src "issuer_ls180.v:109351.7-109351.20" - process $proc$issuer_ls180.v:109351$4192 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:109439.3-109485.6" - process $proc$issuer_ls180.v:109439$4184 - assign { } { } - assign { } { } - assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "issuer_ls180.v:109440.5-109440.29" - switch \initial - attribute \src "issuer_ls180.v:109440.9-109440.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b[63:0] \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b[63:0] \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b[63:0] \$7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b[63:0] \$9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b[63:0] \$11 - case - assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \imm_b $0\imm_b[63:0] - end - attribute \src "issuer_ls180.v:109486.3-109532.6" - process $proc$issuer_ls180.v:109486$4185 - assign { } { } - assign { } { } - assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "issuer_ls180.v:109487.5-109487.29" - switch \initial - attribute \src "issuer_ls180.v:109487.9-109487.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - case - assign $1\imm_b_ok[0:0] 1'0 - end - sync always - update \imm_b_ok $0\imm_b_ok[0:0] - end - attribute \src "issuer_ls180.v:109533.3-109543.6" - process $proc$issuer_ls180.v:109533$4186 - assign { } { } - assign { } { } - assign $0\si[15:0] $1\si[15:0] - attribute \src "issuer_ls180.v:109534.5-109534.29" - switch \initial - attribute \src "issuer_ls180.v:109534.9-109534.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\si[15:0] \BRANCH_SI - case - assign $1\si[15:0] 16'0000000000000000 - end - sync always - update \si $0\si[15:0] - end - attribute \src "issuer_ls180.v:109544.3-109554.6" - process $proc$issuer_ls180.v:109544$4187 - assign { } { } - assign { } { } - assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "issuer_ls180.v:109545.5-109545.29" - switch \initial - attribute \src "issuer_ls180.v:109545.9-109545.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\si_hi[31:0] \$13 [31:0] - case - assign $1\si_hi[31:0] 0 - end - sync always - update \si_hi $0\si_hi[31:0] - end - attribute \src "issuer_ls180.v:109555.3-109565.6" - process $proc$issuer_ls180.v:109555$4188 - assign { } { } - assign { } { } - assign $0\ui[15:0] $1\ui[15:0] - attribute \src "issuer_ls180.v:109556.5-109556.29" - switch \initial - attribute \src "issuer_ls180.v:109556.9-109556.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\ui[15:0] \BRANCH_UI - case - assign $1\ui[15:0] 16'0000000000000000 - end - sync always - update \ui $0\ui[15:0] - end - attribute \src "issuer_ls180.v:109566.3-109576.6" - process $proc$issuer_ls180.v:109566$4189 - assign { } { } - assign { } { } - assign $0\li[25:0] $1\li[25:0] - attribute \src "issuer_ls180.v:109567.5-109567.29" - switch \initial - attribute \src "issuer_ls180.v:109567.9-109567.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\li[25:0] \$16 [25:0] - case - assign $1\li[25:0] 26'00000000000000000000000000 - end - sync always - update \li $0\li[25:0] - end - attribute \src "issuer_ls180.v:109577.3-109587.6" - process $proc$issuer_ls180.v:109577$4190 - assign { } { } - assign { } { } - assign $0\bd[15:0] $1\bd[15:0] - attribute \src "issuer_ls180.v:109578.5-109578.29" - switch \initial - attribute \src "issuer_ls180.v:109578.9-109578.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\bd[15:0] \$19 [15:0] - case - assign $1\bd[15:0] 16'0000000000000000 - end - sync always - update \bd $0\bd[15:0] - end - attribute \src "issuer_ls180.v:109588.3-109598.6" - process $proc$issuer_ls180.v:109588$4191 - assign { } { } - assign { } { } - assign $0\ds[15:0] $1\ds[15:0] - attribute \src "issuer_ls180.v:109589.5-109589.29" - switch \initial - attribute \src "issuer_ls180.v:109589.9-109589.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\ds[15:0] \$22 [15:0] - case - assign $1\ds[15:0] 16'0000000000000000 - end - sync always - update \ds $0\ds[15:0] - end - connect \$9 $pos$issuer_ls180.v:109429$4172_Y - connect \$11 $pos$issuer_ls180.v:109430$4174_Y - connect \$14 $sshl$issuer_ls180.v:109431$4175_Y - connect \$17 $sshl$issuer_ls180.v:109432$4176_Y - connect \$1 $pos$issuer_ls180.v:109433$4178_Y - connect \$20 $sshl$issuer_ls180.v:109434$4179_Y - connect \$23 $sshl$issuer_ls180.v:109435$4180_Y - connect \$4 $sshl$issuer_ls180.v:109436$4181_Y - connect \$3 $pos$issuer_ls180.v:109437$4183_Y - connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 - connect \$13 \$14 - connect \$16 \$17 - connect \$19 \$20 - connect \$22 \$23 -end -attribute \src "issuer_ls180.v:109607.1-109860.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_bi" -attribute \generator "nMigen" -module \dec_bi$160 - attribute \src "issuer_ls180.v:109834.3-109844.6" - wire width 16 $0\bd[15:0] - attribute \src "issuer_ls180.v:109845.3-109855.6" - wire width 16 $0\ds[15:0] - attribute \src "issuer_ls180.v:109696.3-109742.6" - wire width 64 $0\imm_b[63:0] - attribute \src "issuer_ls180.v:109743.3-109789.6" - wire $0\imm_b_ok[0:0] - attribute \src "issuer_ls180.v:109608.7-109608.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:109823.3-109833.6" - wire width 26 $0\li[25:0] - attribute \src "issuer_ls180.v:109790.3-109800.6" - wire width 16 $0\si[15:0] - attribute \src "issuer_ls180.v:109801.3-109811.6" - wire width 32 $0\si_hi[31:0] - attribute \src "issuer_ls180.v:109812.3-109822.6" - wire width 16 $0\ui[15:0] - attribute \src "issuer_ls180.v:109834.3-109844.6" - wire width 16 $1\bd[15:0] - attribute \src "issuer_ls180.v:109845.3-109855.6" - wire width 16 $1\ds[15:0] - attribute \src "issuer_ls180.v:109696.3-109742.6" - wire width 64 $1\imm_b[63:0] - attribute \src "issuer_ls180.v:109743.3-109789.6" - wire $1\imm_b_ok[0:0] - attribute \src "issuer_ls180.v:109823.3-109833.6" - wire width 26 $1\li[25:0] - attribute \src "issuer_ls180.v:109790.3-109800.6" - wire width 16 $1\si[15:0] - attribute \src "issuer_ls180.v:109801.3-109811.6" - wire width 32 $1\si_hi[31:0] - attribute \src "issuer_ls180.v:109812.3-109822.6" - wire width 16 $1\ui[15:0] - attribute \src "issuer_ls180.v:109686.17-109686.108" - wire width 64 $extend$issuer_ls180.v:109686$4193_Y - attribute \src "issuer_ls180.v:109687.18-109687.111" - wire width 64 $extend$issuer_ls180.v:109687$4195_Y - attribute \src "issuer_ls180.v:109690.17-109690.108" - wire width 64 $extend$issuer_ls180.v:109690$4199_Y - attribute \src "issuer_ls180.v:109694.17-109694.102" - wire width 64 $extend$issuer_ls180.v:109694$4204_Y - attribute \src "issuer_ls180.v:109686.17-109686.108" - wire width 64 $pos$issuer_ls180.v:109686$4194_Y - attribute \src "issuer_ls180.v:109687.18-109687.111" - wire width 64 $pos$issuer_ls180.v:109687$4196_Y - attribute \src "issuer_ls180.v:109690.17-109690.108" - wire width 64 $pos$issuer_ls180.v:109690$4200_Y - attribute \src "issuer_ls180.v:109694.17-109694.102" - wire width 64 $pos$issuer_ls180.v:109694$4205_Y - attribute \src "issuer_ls180.v:109688.18-109688.118" - wire width 47 $sshl$issuer_ls180.v:109688$4197_Y - attribute \src "issuer_ls180.v:109689.18-109689.117" - wire width 27 $sshl$issuer_ls180.v:109689$4198_Y - attribute \src "issuer_ls180.v:109691.18-109691.117" - wire width 17 $sshl$issuer_ls180.v:109691$4201_Y - attribute \src "issuer_ls180.v:109692.18-109692.117" - wire width 17 $sshl$issuer_ls180.v:109692$4202_Y - attribute \src "issuer_ls180.v:109693.17-109693.109" - wire width 47 $sshl$issuer_ls180.v:109693$4203_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" - wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 input 8 \LOGICAL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 input 9 \LOGICAL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 24 input 7 \LOGICAL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 5 \LOGICAL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 input 3 \LOGICAL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 input 4 \LOGICAL_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 6 input 6 \LOGICAL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" - wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \imm_b_ok - attribute \src "issuer_ls180.v:109608.7-109608.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 26 \li - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" - wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$issuer_ls180.v:109686$4193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \LOGICAL_sh - connect \Y $extend$issuer_ls180.v:109686$4193_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$issuer_ls180.v:109687$4195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \LOGICAL_SH32 - connect \Y $extend$issuer_ls180.v:109687$4195_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$issuer_ls180.v:109690$4199 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \LOGICAL_UI - connect \Y $extend$issuer_ls180.v:109690$4199_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $extend$issuer_ls180.v:109694$4204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A \$4 - connect \Y $extend$issuer_ls180.v:109694$4204_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$issuer_ls180.v:109686$4194 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:109686$4193_Y - connect \Y $pos$issuer_ls180.v:109686$4194_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$issuer_ls180.v:109687$4196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:109687$4195_Y - connect \Y $pos$issuer_ls180.v:109687$4196_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$issuer_ls180.v:109690$4200 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:109690$4199_Y - connect \Y $pos$issuer_ls180.v:109690$4200_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $pos$issuer_ls180.v:109694$4205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:109694$4204_Y - connect \Y $pos$issuer_ls180.v:109694$4205_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - cell $sshl $sshl$issuer_ls180.v:109688$4197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \LOGICAL_SI - connect \B 5'10000 - connect \Y $sshl$issuer_ls180.v:109688$4197_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - cell $sshl $sshl$issuer_ls180.v:109689$4198 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \LOGICAL_LI - connect \B 2'10 - connect \Y $sshl$issuer_ls180.v:109689$4198_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $sshl$issuer_ls180.v:109691$4201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \LOGICAL_BD - connect \B 2'10 - connect \Y $sshl$issuer_ls180.v:109691$4201_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$issuer_ls180.v:109692$4202 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \LOGICAL_DS - connect \B 2'10 - connect \Y $sshl$issuer_ls180.v:109692$4202_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $sshl $sshl$issuer_ls180.v:109693$4203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $sshl$issuer_ls180.v:109693$4203_Y - end - attribute \src "issuer_ls180.v:109608.7-109608.20" - process $proc$issuer_ls180.v:109608$4214 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:109696.3-109742.6" - process $proc$issuer_ls180.v:109696$4206 - assign { } { } - assign { } { } - assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "issuer_ls180.v:109697.5-109697.29" - switch \initial - attribute \src "issuer_ls180.v:109697.9-109697.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b[63:0] \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b[63:0] \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b[63:0] \$7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b[63:0] \$9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b[63:0] \$11 - case - assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \imm_b $0\imm_b[63:0] - end - attribute \src "issuer_ls180.v:109743.3-109789.6" - process $proc$issuer_ls180.v:109743$4207 - assign { } { } - assign { } { } - assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "issuer_ls180.v:109744.5-109744.29" - switch \initial - attribute \src "issuer_ls180.v:109744.9-109744.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - case - assign $1\imm_b_ok[0:0] 1'0 - end - sync always - update \imm_b_ok $0\imm_b_ok[0:0] - end - attribute \src "issuer_ls180.v:109790.3-109800.6" - process $proc$issuer_ls180.v:109790$4208 - assign { } { } - assign { } { } - assign $0\si[15:0] $1\si[15:0] - attribute \src "issuer_ls180.v:109791.5-109791.29" - switch \initial - attribute \src "issuer_ls180.v:109791.9-109791.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\si[15:0] \LOGICAL_SI - case - assign $1\si[15:0] 16'0000000000000000 - end - sync always - update \si $0\si[15:0] - end - attribute \src "issuer_ls180.v:109801.3-109811.6" - process $proc$issuer_ls180.v:109801$4209 - assign { } { } - assign { } { } - assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "issuer_ls180.v:109802.5-109802.29" - switch \initial - attribute \src "issuer_ls180.v:109802.9-109802.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\si_hi[31:0] \$13 [31:0] - case - assign $1\si_hi[31:0] 0 - end - sync always - update \si_hi $0\si_hi[31:0] - end - attribute \src "issuer_ls180.v:109812.3-109822.6" - process $proc$issuer_ls180.v:109812$4210 - assign { } { } - assign { } { } - assign $0\ui[15:0] $1\ui[15:0] - attribute \src "issuer_ls180.v:109813.5-109813.29" - switch \initial - attribute \src "issuer_ls180.v:109813.9-109813.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\ui[15:0] \LOGICAL_UI - case - assign $1\ui[15:0] 16'0000000000000000 - end - sync always - update \ui $0\ui[15:0] - end - attribute \src "issuer_ls180.v:109823.3-109833.6" - process $proc$issuer_ls180.v:109823$4211 - assign { } { } - assign { } { } - assign $0\li[25:0] $1\li[25:0] - attribute \src "issuer_ls180.v:109824.5-109824.29" - switch \initial - attribute \src "issuer_ls180.v:109824.9-109824.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\li[25:0] \$16 [25:0] - case - assign $1\li[25:0] 26'00000000000000000000000000 - end - sync always - update \li $0\li[25:0] - end - attribute \src "issuer_ls180.v:109834.3-109844.6" - process $proc$issuer_ls180.v:109834$4212 - assign { } { } - assign { } { } - assign $0\bd[15:0] $1\bd[15:0] - attribute \src "issuer_ls180.v:109835.5-109835.29" - switch \initial - attribute \src "issuer_ls180.v:109835.9-109835.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\bd[15:0] \$19 [15:0] - case - assign $1\bd[15:0] 16'0000000000000000 - end - sync always - update \bd $0\bd[15:0] - end - attribute \src "issuer_ls180.v:109845.3-109855.6" - process $proc$issuer_ls180.v:109845$4213 - assign { } { } - assign { } { } - assign $0\ds[15:0] $1\ds[15:0] - attribute \src "issuer_ls180.v:109846.5-109846.29" - switch \initial - attribute \src "issuer_ls180.v:109846.9-109846.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\ds[15:0] \$22 [15:0] - case - assign $1\ds[15:0] 16'0000000000000000 - end - sync always - update \ds $0\ds[15:0] - end - connect \$9 $pos$issuer_ls180.v:109686$4194_Y - connect \$11 $pos$issuer_ls180.v:109687$4196_Y - connect \$14 $sshl$issuer_ls180.v:109688$4197_Y - connect \$17 $sshl$issuer_ls180.v:109689$4198_Y - connect \$1 $pos$issuer_ls180.v:109690$4200_Y - connect \$20 $sshl$issuer_ls180.v:109691$4201_Y - connect \$23 $sshl$issuer_ls180.v:109692$4202_Y - connect \$4 $sshl$issuer_ls180.v:109693$4203_Y - connect \$3 $pos$issuer_ls180.v:109694$4205_Y - connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 - connect \$13 \$14 - connect \$16 \$17 - connect \$19 \$20 - connect \$22 \$23 -end -attribute \src "issuer_ls180.v:109864.1-110117.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_bi" -attribute \generator "nMigen" -module \dec_bi$176 - attribute \src "issuer_ls180.v:110091.3-110101.6" - wire width 16 $0\bd[15:0] - attribute \src "issuer_ls180.v:110102.3-110112.6" - wire width 16 $0\ds[15:0] - attribute \src "issuer_ls180.v:109953.3-109999.6" - wire width 64 $0\imm_b[63:0] - attribute \src "issuer_ls180.v:110000.3-110046.6" - wire $0\imm_b_ok[0:0] - attribute \src "issuer_ls180.v:109865.7-109865.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:110080.3-110090.6" - wire width 26 $0\li[25:0] - attribute \src "issuer_ls180.v:110047.3-110057.6" - wire width 16 $0\si[15:0] - attribute \src "issuer_ls180.v:110058.3-110068.6" - wire width 32 $0\si_hi[31:0] - attribute \src "issuer_ls180.v:110069.3-110079.6" - wire width 16 $0\ui[15:0] - attribute \src "issuer_ls180.v:110091.3-110101.6" - wire width 16 $1\bd[15:0] - attribute \src "issuer_ls180.v:110102.3-110112.6" - wire width 16 $1\ds[15:0] - attribute \src "issuer_ls180.v:109953.3-109999.6" - wire width 64 $1\imm_b[63:0] - attribute \src "issuer_ls180.v:110000.3-110046.6" - wire $1\imm_b_ok[0:0] - attribute \src "issuer_ls180.v:110080.3-110090.6" - wire width 26 $1\li[25:0] - attribute \src "issuer_ls180.v:110047.3-110057.6" - wire width 16 $1\si[15:0] - attribute \src "issuer_ls180.v:110058.3-110068.6" - wire width 32 $1\si_hi[31:0] - attribute \src "issuer_ls180.v:110069.3-110079.6" - wire width 16 $1\ui[15:0] - attribute \src "issuer_ls180.v:109943.17-109943.104" - wire width 64 $extend$issuer_ls180.v:109943$4215_Y - attribute \src "issuer_ls180.v:109944.18-109944.107" - wire width 64 $extend$issuer_ls180.v:109944$4217_Y - attribute \src "issuer_ls180.v:109947.17-109947.104" - wire width 64 $extend$issuer_ls180.v:109947$4221_Y - attribute \src "issuer_ls180.v:109951.17-109951.102" - wire width 64 $extend$issuer_ls180.v:109951$4226_Y - attribute \src "issuer_ls180.v:109943.17-109943.104" - wire width 64 $pos$issuer_ls180.v:109943$4216_Y - attribute \src "issuer_ls180.v:109944.18-109944.107" - wire width 64 $pos$issuer_ls180.v:109944$4218_Y - attribute \src "issuer_ls180.v:109947.17-109947.104" - wire width 64 $pos$issuer_ls180.v:109947$4222_Y - attribute \src "issuer_ls180.v:109951.17-109951.102" - wire width 64 $pos$issuer_ls180.v:109951$4227_Y - attribute \src "issuer_ls180.v:109945.18-109945.114" - wire width 47 $sshl$issuer_ls180.v:109945$4219_Y - attribute \src "issuer_ls180.v:109946.18-109946.113" - wire width 27 $sshl$issuer_ls180.v:109946$4220_Y - attribute \src "issuer_ls180.v:109948.18-109948.113" - wire width 17 $sshl$issuer_ls180.v:109948$4223_Y - attribute \src "issuer_ls180.v:109949.18-109949.113" - wire width 17 $sshl$issuer_ls180.v:109949$4224_Y - attribute \src "issuer_ls180.v:109950.17-109950.109" - wire width 47 $sshl$issuer_ls180.v:109950$4225_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" - wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 input 8 \DIV_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 input 9 \DIV_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 24 input 7 \DIV_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 5 \DIV_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 input 3 \DIV_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 input 4 \DIV_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 6 input 6 \DIV_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" - wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \imm_b_ok - attribute \src "issuer_ls180.v:109865.7-109865.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 26 \li - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" - wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$issuer_ls180.v:109943$4215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \DIV_sh - connect \Y $extend$issuer_ls180.v:109943$4215_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$issuer_ls180.v:109944$4217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \DIV_SH32 - connect \Y $extend$issuer_ls180.v:109944$4217_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$issuer_ls180.v:109947$4221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \DIV_UI - connect \Y $extend$issuer_ls180.v:109947$4221_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $extend$issuer_ls180.v:109951$4226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A \$4 - connect \Y $extend$issuer_ls180.v:109951$4226_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$issuer_ls180.v:109943$4216 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:109943$4215_Y - connect \Y $pos$issuer_ls180.v:109943$4216_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$issuer_ls180.v:109944$4218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:109944$4217_Y - connect \Y $pos$issuer_ls180.v:109944$4218_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$issuer_ls180.v:109947$4222 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:109947$4221_Y - connect \Y $pos$issuer_ls180.v:109947$4222_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $pos$issuer_ls180.v:109951$4227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:109951$4226_Y - connect \Y $pos$issuer_ls180.v:109951$4227_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - cell $sshl $sshl$issuer_ls180.v:109945$4219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \DIV_SI - connect \B 5'10000 - connect \Y $sshl$issuer_ls180.v:109945$4219_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - cell $sshl $sshl$issuer_ls180.v:109946$4220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \DIV_LI - connect \B 2'10 - connect \Y $sshl$issuer_ls180.v:109946$4220_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $sshl$issuer_ls180.v:109948$4223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \DIV_BD - connect \B 2'10 - connect \Y $sshl$issuer_ls180.v:109948$4223_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$issuer_ls180.v:109949$4224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \DIV_DS - connect \B 2'10 - connect \Y $sshl$issuer_ls180.v:109949$4224_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $sshl $sshl$issuer_ls180.v:109950$4225 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $sshl$issuer_ls180.v:109950$4225_Y - end - attribute \src "issuer_ls180.v:109865.7-109865.20" - process $proc$issuer_ls180.v:109865$4236 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:109953.3-109999.6" - process $proc$issuer_ls180.v:109953$4228 - assign { } { } - assign { } { } - assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "issuer_ls180.v:109954.5-109954.29" - switch \initial - attribute \src "issuer_ls180.v:109954.9-109954.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b[63:0] \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b[63:0] \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b[63:0] \$7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b[63:0] \$9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b[63:0] \$11 - case - assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \imm_b $0\imm_b[63:0] - end - attribute \src "issuer_ls180.v:110000.3-110046.6" - process $proc$issuer_ls180.v:110000$4229 - assign { } { } - assign { } { } - assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "issuer_ls180.v:110001.5-110001.29" - switch \initial - attribute \src "issuer_ls180.v:110001.9-110001.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - case - assign $1\imm_b_ok[0:0] 1'0 - end - sync always - update \imm_b_ok $0\imm_b_ok[0:0] - end - attribute \src "issuer_ls180.v:110047.3-110057.6" - process $proc$issuer_ls180.v:110047$4230 - assign { } { } - assign { } { } - assign $0\si[15:0] $1\si[15:0] - attribute \src "issuer_ls180.v:110048.5-110048.29" - switch \initial - attribute \src "issuer_ls180.v:110048.9-110048.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\si[15:0] \DIV_SI - case - assign $1\si[15:0] 16'0000000000000000 - end - sync always - update \si $0\si[15:0] - end - attribute \src "issuer_ls180.v:110058.3-110068.6" - process $proc$issuer_ls180.v:110058$4231 - assign { } { } - assign { } { } - assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "issuer_ls180.v:110059.5-110059.29" - switch \initial - attribute \src "issuer_ls180.v:110059.9-110059.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\si_hi[31:0] \$13 [31:0] - case - assign $1\si_hi[31:0] 0 - end - sync always - update \si_hi $0\si_hi[31:0] - end - attribute \src "issuer_ls180.v:110069.3-110079.6" - process $proc$issuer_ls180.v:110069$4232 - assign { } { } - assign { } { } - assign $0\ui[15:0] $1\ui[15:0] - attribute \src "issuer_ls180.v:110070.5-110070.29" - switch \initial - attribute \src "issuer_ls180.v:110070.9-110070.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\ui[15:0] \DIV_UI - case - assign $1\ui[15:0] 16'0000000000000000 - end - sync always - update \ui $0\ui[15:0] - end - attribute \src "issuer_ls180.v:110080.3-110090.6" - process $proc$issuer_ls180.v:110080$4233 - assign { } { } - assign { } { } - assign $0\li[25:0] $1\li[25:0] - attribute \src "issuer_ls180.v:110081.5-110081.29" - switch \initial - attribute \src "issuer_ls180.v:110081.9-110081.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\li[25:0] \$16 [25:0] - case - assign $1\li[25:0] 26'00000000000000000000000000 - end - sync always - update \li $0\li[25:0] - end - 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\ds[15:0] \$22 [15:0] - case - assign $1\ds[15:0] 16'0000000000000000 - end - sync always - update \ds $0\ds[15:0] - end - connect \$9 $pos$issuer_ls180.v:109943$4216_Y - connect \$11 $pos$issuer_ls180.v:109944$4218_Y - connect \$14 $sshl$issuer_ls180.v:109945$4219_Y - connect \$17 $sshl$issuer_ls180.v:109946$4220_Y - connect \$1 $pos$issuer_ls180.v:109947$4222_Y - connect \$20 $sshl$issuer_ls180.v:109948$4223_Y - connect \$23 $sshl$issuer_ls180.v:109949$4224_Y - connect \$4 $sshl$issuer_ls180.v:109950$4225_Y - connect \$3 $pos$issuer_ls180.v:109951$4227_Y - connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 - connect \$13 \$14 - connect \$16 \$17 - connect \$19 \$20 - connect \$22 \$23 -end -attribute \src "issuer_ls180.v:110121.1-110374.10" -attribute \cells_not_processed 1 -attribute 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"issuer_ls180.v:110210.3-110256.6" - wire width 64 $1\imm_b[63:0] - attribute \src "issuer_ls180.v:110257.3-110303.6" - wire $1\imm_b_ok[0:0] - attribute \src "issuer_ls180.v:110337.3-110347.6" - wire width 26 $1\li[25:0] - attribute \src "issuer_ls180.v:110304.3-110314.6" - wire width 16 $1\si[15:0] - attribute \src "issuer_ls180.v:110315.3-110325.6" - wire width 32 $1\si_hi[31:0] - attribute \src "issuer_ls180.v:110326.3-110336.6" - wire width 16 $1\ui[15:0] - attribute \src "issuer_ls180.v:110200.17-110200.104" - wire width 64 $extend$issuer_ls180.v:110200$4237_Y - attribute \src "issuer_ls180.v:110201.18-110201.107" - wire width 64 $extend$issuer_ls180.v:110201$4239_Y - attribute \src "issuer_ls180.v:110204.17-110204.104" - wire width 64 $extend$issuer_ls180.v:110204$4243_Y - attribute \src "issuer_ls180.v:110208.17-110208.102" - wire width 64 $extend$issuer_ls180.v:110208$4248_Y - attribute \src "issuer_ls180.v:110200.17-110200.104" - wire width 64 $pos$issuer_ls180.v:110200$4238_Y - attribute \src "issuer_ls180.v:110201.18-110201.107" - wire width 64 $pos$issuer_ls180.v:110201$4240_Y - attribute \src "issuer_ls180.v:110204.17-110204.104" - wire width 64 $pos$issuer_ls180.v:110204$4244_Y - attribute \src "issuer_ls180.v:110208.17-110208.102" - wire width 64 $pos$issuer_ls180.v:110208$4249_Y - attribute \src "issuer_ls180.v:110202.18-110202.114" - wire width 47 $sshl$issuer_ls180.v:110202$4241_Y - attribute \src "issuer_ls180.v:110203.18-110203.113" - wire width 27 $sshl$issuer_ls180.v:110203$4242_Y - attribute \src "issuer_ls180.v:110205.18-110205.113" - wire width 17 $sshl$issuer_ls180.v:110205$4245_Y - attribute \src "issuer_ls180.v:110206.18-110206.113" - wire width 17 $sshl$issuer_ls180.v:110206$4246_Y - attribute \src "issuer_ls180.v:110207.17-110207.109" - wire width 47 $sshl$issuer_ls180.v:110207$4247_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" - wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 input 8 \MUL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 input 9 \MUL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 24 input 7 \MUL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 5 \MUL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 input 3 \MUL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 input 4 \MUL_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 6 input 6 \MUL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" - wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \imm_b_ok - attribute \src "issuer_ls180.v:110122.7-110122.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 26 \li - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" - wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$issuer_ls180.v:110200$4237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \MUL_sh - connect \Y $extend$issuer_ls180.v:110200$4237_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$issuer_ls180.v:110201$4239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \MUL_SH32 - connect \Y $extend$issuer_ls180.v:110201$4239_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$issuer_ls180.v:110204$4243 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \MUL_UI - connect \Y $extend$issuer_ls180.v:110204$4243_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $extend$issuer_ls180.v:110208$4248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A \$4 - connect \Y $extend$issuer_ls180.v:110208$4248_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$issuer_ls180.v:110200$4238 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:110200$4237_Y - connect \Y $pos$issuer_ls180.v:110200$4238_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$issuer_ls180.v:110201$4240 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:110201$4239_Y - connect \Y $pos$issuer_ls180.v:110201$4240_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$issuer_ls180.v:110204$4244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:110204$4243_Y - connect \Y $pos$issuer_ls180.v:110204$4244_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $pos$issuer_ls180.v:110208$4249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:110208$4248_Y - connect \Y $pos$issuer_ls180.v:110208$4249_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - cell $sshl $sshl$issuer_ls180.v:110202$4241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \MUL_SI - connect \B 5'10000 - connect \Y $sshl$issuer_ls180.v:110202$4241_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - cell $sshl $sshl$issuer_ls180.v:110203$4242 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \MUL_LI - connect \B 2'10 - connect \Y $sshl$issuer_ls180.v:110203$4242_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $sshl$issuer_ls180.v:110205$4245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \MUL_BD - connect \B 2'10 - connect \Y $sshl$issuer_ls180.v:110205$4245_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$issuer_ls180.v:110206$4246 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \MUL_DS - connect \B 2'10 - connect \Y $sshl$issuer_ls180.v:110206$4246_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $sshl $sshl$issuer_ls180.v:110207$4247 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $sshl$issuer_ls180.v:110207$4247_Y - end - attribute \src "issuer_ls180.v:110122.7-110122.20" - process $proc$issuer_ls180.v:110122$4258 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:110210.3-110256.6" - process $proc$issuer_ls180.v:110210$4250 - assign { } { } - assign { } { } - assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "issuer_ls180.v:110211.5-110211.29" - switch \initial - attribute \src "issuer_ls180.v:110211.9-110211.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b[63:0] \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b[63:0] \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b[63:0] \$7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b[63:0] \$9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b[63:0] \$11 - case - assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \imm_b $0\imm_b[63:0] - end - attribute \src "issuer_ls180.v:110257.3-110303.6" - process $proc$issuer_ls180.v:110257$4251 - assign { } { } - assign { } { } - assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "issuer_ls180.v:110258.5-110258.29" - switch \initial - attribute \src "issuer_ls180.v:110258.9-110258.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - case - assign $1\imm_b_ok[0:0] 1'0 - end - sync always - update \imm_b_ok $0\imm_b_ok[0:0] - end - attribute \src "issuer_ls180.v:110304.3-110314.6" - process $proc$issuer_ls180.v:110304$4252 - assign { } { } - assign { } { } - assign $0\si[15:0] $1\si[15:0] - attribute \src "issuer_ls180.v:110305.5-110305.29" - switch \initial - attribute \src "issuer_ls180.v:110305.9-110305.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\si[15:0] \MUL_SI - case - assign $1\si[15:0] 16'0000000000000000 - end - sync always - update \si $0\si[15:0] - end - attribute \src "issuer_ls180.v:110315.3-110325.6" - process $proc$issuer_ls180.v:110315$4253 - assign { } { } - assign { } { } - assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "issuer_ls180.v:110316.5-110316.29" - switch \initial - attribute \src "issuer_ls180.v:110316.9-110316.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\si_hi[31:0] \$13 [31:0] - case - assign $1\si_hi[31:0] 0 - end - sync always - update \si_hi $0\si_hi[31:0] - end - attribute \src "issuer_ls180.v:110326.3-110336.6" - process $proc$issuer_ls180.v:110326$4254 - assign { } { } - assign { } { } - assign $0\ui[15:0] $1\ui[15:0] - attribute \src "issuer_ls180.v:110327.5-110327.29" - switch \initial - attribute \src "issuer_ls180.v:110327.9-110327.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\ui[15:0] \MUL_UI - case - assign $1\ui[15:0] 16'0000000000000000 - end - sync always - update \ui $0\ui[15:0] - end - attribute \src "issuer_ls180.v:110337.3-110347.6" - process $proc$issuer_ls180.v:110337$4255 - assign { } { } - assign { } { } - assign $0\li[25:0] $1\li[25:0] - attribute \src "issuer_ls180.v:110338.5-110338.29" - switch \initial - attribute \src "issuer_ls180.v:110338.9-110338.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\li[25:0] \$16 [25:0] - case - assign $1\li[25:0] 26'00000000000000000000000000 - end - sync always - update \li $0\li[25:0] - end - attribute \src "issuer_ls180.v:110348.3-110358.6" - process $proc$issuer_ls180.v:110348$4256 - assign { } { } - assign { } { } - assign $0\bd[15:0] $1\bd[15:0] - attribute \src "issuer_ls180.v:110349.5-110349.29" - switch \initial - attribute \src "issuer_ls180.v:110349.9-110349.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\bd[15:0] \$19 [15:0] - case - assign $1\bd[15:0] 16'0000000000000000 - end - sync always - update \bd $0\bd[15:0] - end - attribute \src "issuer_ls180.v:110359.3-110369.6" - process $proc$issuer_ls180.v:110359$4257 - assign { } { } - assign { } { } - assign $0\ds[15:0] $1\ds[15:0] - attribute \src "issuer_ls180.v:110360.5-110360.29" - switch \initial - attribute \src "issuer_ls180.v:110360.9-110360.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\ds[15:0] \$22 [15:0] - case - assign $1\ds[15:0] 16'0000000000000000 - end - sync always - update \ds $0\ds[15:0] - end - connect \$9 $pos$issuer_ls180.v:110200$4238_Y - connect \$11 $pos$issuer_ls180.v:110201$4240_Y - connect \$14 $sshl$issuer_ls180.v:110202$4241_Y - connect \$17 $sshl$issuer_ls180.v:110203$4242_Y - connect \$1 $pos$issuer_ls180.v:110204$4244_Y - connect \$20 $sshl$issuer_ls180.v:110205$4245_Y - connect \$23 $sshl$issuer_ls180.v:110206$4246_Y - connect \$4 $sshl$issuer_ls180.v:110207$4247_Y - connect \$3 $pos$issuer_ls180.v:110208$4249_Y - connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 - connect \$13 \$14 - connect \$16 \$17 - connect \$19 \$20 - connect \$22 \$23 -end -attribute \src "issuer_ls180.v:110378.1-110631.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_bi" -attribute \generator "nMigen" -module \dec_bi$192 - attribute \src "issuer_ls180.v:110605.3-110615.6" - wire width 16 $0\bd[15:0] - attribute \src "issuer_ls180.v:110616.3-110626.6" - wire width 16 $0\ds[15:0] - attribute \src "issuer_ls180.v:110467.3-110513.6" - wire width 64 $0\imm_b[63:0] - attribute \src "issuer_ls180.v:110514.3-110560.6" - wire $0\imm_b_ok[0:0] - attribute \src "issuer_ls180.v:110379.7-110379.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:110594.3-110604.6" - wire width 26 $0\li[25:0] - attribute \src "issuer_ls180.v:110561.3-110571.6" - wire width 16 $0\si[15:0] - attribute \src "issuer_ls180.v:110572.3-110582.6" - wire width 32 $0\si_hi[31:0] - attribute \src "issuer_ls180.v:110583.3-110593.6" - wire width 16 $0\ui[15:0] - attribute \src "issuer_ls180.v:110605.3-110615.6" - wire width 16 $1\bd[15:0] - attribute \src "issuer_ls180.v:110616.3-110626.6" - wire width 16 $1\ds[15:0] - attribute \src "issuer_ls180.v:110467.3-110513.6" - wire width 64 $1\imm_b[63:0] - attribute \src "issuer_ls180.v:110514.3-110560.6" - wire $1\imm_b_ok[0:0] - attribute \src "issuer_ls180.v:110594.3-110604.6" - wire width 26 $1\li[25:0] - attribute \src "issuer_ls180.v:110561.3-110571.6" - wire width 16 $1\si[15:0] - attribute \src "issuer_ls180.v:110572.3-110582.6" - wire width 32 $1\si_hi[31:0] - attribute \src "issuer_ls180.v:110583.3-110593.6" - wire width 16 $1\ui[15:0] - attribute \src "issuer_ls180.v:110457.17-110457.110" - wire width 64 $extend$issuer_ls180.v:110457$4259_Y - attribute \src "issuer_ls180.v:110458.18-110458.113" - wire width 64 $extend$issuer_ls180.v:110458$4261_Y - attribute \src "issuer_ls180.v:110461.17-110461.110" - wire width 64 $extend$issuer_ls180.v:110461$4265_Y - attribute \src "issuer_ls180.v:110465.17-110465.102" - wire width 64 $extend$issuer_ls180.v:110465$4270_Y - attribute \src "issuer_ls180.v:110457.17-110457.110" - wire width 64 $pos$issuer_ls180.v:110457$4260_Y - attribute \src "issuer_ls180.v:110458.18-110458.113" - wire width 64 $pos$issuer_ls180.v:110458$4262_Y - attribute \src "issuer_ls180.v:110461.17-110461.110" - wire width 64 $pos$issuer_ls180.v:110461$4266_Y - attribute \src "issuer_ls180.v:110465.17-110465.102" - wire width 64 $pos$issuer_ls180.v:110465$4271_Y - attribute \src "issuer_ls180.v:110459.18-110459.120" - wire width 47 $sshl$issuer_ls180.v:110459$4263_Y - attribute \src "issuer_ls180.v:110460.18-110460.119" - wire width 27 $sshl$issuer_ls180.v:110460$4264_Y - attribute \src "issuer_ls180.v:110462.18-110462.119" - wire width 17 $sshl$issuer_ls180.v:110462$4267_Y - attribute \src "issuer_ls180.v:110463.18-110463.119" - wire width 17 $sshl$issuer_ls180.v:110463$4268_Y - attribute \src "issuer_ls180.v:110464.17-110464.109" - wire width 47 $sshl$issuer_ls180.v:110464$4269_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" - wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 input 8 \SHIFT_ROT_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 input 9 \SHIFT_ROT_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 24 input 7 \SHIFT_ROT_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 5 \SHIFT_ROT_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 input 3 \SHIFT_ROT_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 input 4 \SHIFT_ROT_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 6 input 6 \SHIFT_ROT_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" - wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \imm_b_ok - attribute \src "issuer_ls180.v:110379.7-110379.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 26 \li - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" - wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$issuer_ls180.v:110457$4259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \SHIFT_ROT_sh - connect \Y $extend$issuer_ls180.v:110457$4259_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$issuer_ls180.v:110458$4261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \SHIFT_ROT_SH32 - connect \Y $extend$issuer_ls180.v:110458$4261_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$issuer_ls180.v:110461$4265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \SHIFT_ROT_UI - connect \Y $extend$issuer_ls180.v:110461$4265_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $extend$issuer_ls180.v:110465$4270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A \$4 - connect \Y $extend$issuer_ls180.v:110465$4270_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$issuer_ls180.v:110457$4260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:110457$4259_Y - connect \Y $pos$issuer_ls180.v:110457$4260_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$issuer_ls180.v:110458$4262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:110458$4261_Y - connect \Y $pos$issuer_ls180.v:110458$4262_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$issuer_ls180.v:110461$4266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:110461$4265_Y - connect \Y $pos$issuer_ls180.v:110461$4266_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $pos$issuer_ls180.v:110465$4271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:110465$4270_Y - connect \Y $pos$issuer_ls180.v:110465$4271_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - cell $sshl $sshl$issuer_ls180.v:110459$4263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \SHIFT_ROT_SI - connect \B 5'10000 - connect \Y $sshl$issuer_ls180.v:110459$4263_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - cell $sshl $sshl$issuer_ls180.v:110460$4264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \SHIFT_ROT_LI - connect \B 2'10 - connect \Y $sshl$issuer_ls180.v:110460$4264_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $sshl$issuer_ls180.v:110462$4267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \SHIFT_ROT_BD - connect \B 2'10 - connect \Y $sshl$issuer_ls180.v:110462$4267_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$issuer_ls180.v:110463$4268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \SHIFT_ROT_DS - connect \B 2'10 - connect \Y $sshl$issuer_ls180.v:110463$4268_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $sshl $sshl$issuer_ls180.v:110464$4269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $sshl$issuer_ls180.v:110464$4269_Y - end - attribute \src "issuer_ls180.v:110379.7-110379.20" - process $proc$issuer_ls180.v:110379$4280 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:110467.3-110513.6" - process $proc$issuer_ls180.v:110467$4272 - assign { } { } - assign { } { } - assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "issuer_ls180.v:110468.5-110468.29" - switch \initial - attribute \src "issuer_ls180.v:110468.9-110468.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b[63:0] \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b[63:0] \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b[63:0] \$7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b[63:0] \$9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b[63:0] \$11 - case - assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \imm_b $0\imm_b[63:0] - end - attribute \src "issuer_ls180.v:110514.3-110560.6" - process $proc$issuer_ls180.v:110514$4273 - assign { } { } - assign { } { } - assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "issuer_ls180.v:110515.5-110515.29" - switch \initial - attribute \src "issuer_ls180.v:110515.9-110515.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - case - assign $1\imm_b_ok[0:0] 1'0 - end - sync always - update \imm_b_ok $0\imm_b_ok[0:0] - end - attribute \src "issuer_ls180.v:110561.3-110571.6" - process $proc$issuer_ls180.v:110561$4274 - assign { } { } - assign { } { } - assign $0\si[15:0] $1\si[15:0] - attribute \src "issuer_ls180.v:110562.5-110562.29" - switch \initial - attribute \src "issuer_ls180.v:110562.9-110562.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\si[15:0] \SHIFT_ROT_SI - case - assign $1\si[15:0] 16'0000000000000000 - end - sync always - update \si $0\si[15:0] - end - attribute \src "issuer_ls180.v:110572.3-110582.6" - process $proc$issuer_ls180.v:110572$4275 - assign { } { } - assign { } { } - assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "issuer_ls180.v:110573.5-110573.29" - switch \initial - attribute \src "issuer_ls180.v:110573.9-110573.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\si_hi[31:0] \$13 [31:0] - case - assign $1\si_hi[31:0] 0 - end - sync always - update \si_hi $0\si_hi[31:0] - end - attribute \src "issuer_ls180.v:110583.3-110593.6" - process $proc$issuer_ls180.v:110583$4276 - assign { } { } - assign { } { } - assign $0\ui[15:0] $1\ui[15:0] - attribute \src "issuer_ls180.v:110584.5-110584.29" - switch \initial - attribute \src "issuer_ls180.v:110584.9-110584.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\ui[15:0] \SHIFT_ROT_UI - case - assign $1\ui[15:0] 16'0000000000000000 - end - sync always - update \ui $0\ui[15:0] - end - attribute \src "issuer_ls180.v:110594.3-110604.6" - process $proc$issuer_ls180.v:110594$4277 - assign { } { } - assign { } { } - assign $0\li[25:0] $1\li[25:0] - attribute \src "issuer_ls180.v:110595.5-110595.29" - switch \initial - attribute \src "issuer_ls180.v:110595.9-110595.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\li[25:0] \$16 [25:0] - case - assign $1\li[25:0] 26'00000000000000000000000000 - end - sync always - update \li $0\li[25:0] - end - attribute \src "issuer_ls180.v:110605.3-110615.6" - process $proc$issuer_ls180.v:110605$4278 - assign { } { } - assign { } { } - assign $0\bd[15:0] $1\bd[15:0] - attribute \src "issuer_ls180.v:110606.5-110606.29" - switch \initial - attribute \src "issuer_ls180.v:110606.9-110606.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\bd[15:0] \$19 [15:0] - case - assign $1\bd[15:0] 16'0000000000000000 - end - sync always - update \bd $0\bd[15:0] - end - attribute \src "issuer_ls180.v:110616.3-110626.6" - process $proc$issuer_ls180.v:110616$4279 - assign { } { } - assign { } { } - assign $0\ds[15:0] $1\ds[15:0] - attribute \src "issuer_ls180.v:110617.5-110617.29" - switch \initial - attribute \src "issuer_ls180.v:110617.9-110617.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\ds[15:0] \$22 [15:0] - case - assign $1\ds[15:0] 16'0000000000000000 - end - sync always - update \ds $0\ds[15:0] - end - connect \$9 $pos$issuer_ls180.v:110457$4260_Y - connect \$11 $pos$issuer_ls180.v:110458$4262_Y - connect \$14 $sshl$issuer_ls180.v:110459$4263_Y - connect \$17 $sshl$issuer_ls180.v:110460$4264_Y - connect \$1 $pos$issuer_ls180.v:110461$4266_Y - connect \$20 $sshl$issuer_ls180.v:110462$4267_Y - connect \$23 $sshl$issuer_ls180.v:110463$4268_Y - connect \$4 $sshl$issuer_ls180.v:110464$4269_Y - connect \$3 $pos$issuer_ls180.v:110465$4271_Y - connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 - connect \$13 \$14 - connect \$16 \$17 - connect \$19 \$20 - connect \$22 \$23 -end -attribute \src "issuer_ls180.v:110635.1-110888.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_bi" -attribute \generator "nMigen" -module \dec_bi$201 - attribute \src "issuer_ls180.v:110862.3-110872.6" - wire width 16 $0\bd[15:0] - attribute \src "issuer_ls180.v:110873.3-110883.6" - wire width 16 $0\ds[15:0] - attribute \src "issuer_ls180.v:110724.3-110770.6" - wire width 64 $0\imm_b[63:0] - attribute \src "issuer_ls180.v:110771.3-110817.6" - wire $0\imm_b_ok[0:0] - attribute \src "issuer_ls180.v:110636.7-110636.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:110851.3-110861.6" - wire width 26 $0\li[25:0] - attribute \src "issuer_ls180.v:110818.3-110828.6" - wire width 16 $0\si[15:0] - attribute \src "issuer_ls180.v:110829.3-110839.6" - wire width 32 $0\si_hi[31:0] - attribute \src "issuer_ls180.v:110840.3-110850.6" - wire width 16 $0\ui[15:0] - attribute \src "issuer_ls180.v:110862.3-110872.6" - wire width 16 $1\bd[15:0] - attribute \src "issuer_ls180.v:110873.3-110883.6" - wire width 16 $1\ds[15:0] - attribute \src "issuer_ls180.v:110724.3-110770.6" - wire width 64 $1\imm_b[63:0] - attribute \src "issuer_ls180.v:110771.3-110817.6" - wire $1\imm_b_ok[0:0] - attribute \src "issuer_ls180.v:110851.3-110861.6" - wire width 26 $1\li[25:0] - attribute \src "issuer_ls180.v:110818.3-110828.6" - wire width 16 $1\si[15:0] - attribute \src "issuer_ls180.v:110829.3-110839.6" - wire width 32 $1\si_hi[31:0] - attribute \src "issuer_ls180.v:110840.3-110850.6" - wire width 16 $1\ui[15:0] - attribute \src "issuer_ls180.v:110714.17-110714.105" - wire width 64 $extend$issuer_ls180.v:110714$4281_Y - attribute \src "issuer_ls180.v:110715.18-110715.108" - wire width 64 $extend$issuer_ls180.v:110715$4283_Y - attribute \src "issuer_ls180.v:110718.17-110718.105" - wire width 64 $extend$issuer_ls180.v:110718$4287_Y - attribute \src "issuer_ls180.v:110722.17-110722.102" - wire width 64 $extend$issuer_ls180.v:110722$4292_Y - attribute \src "issuer_ls180.v:110714.17-110714.105" - wire width 64 $pos$issuer_ls180.v:110714$4282_Y - attribute \src "issuer_ls180.v:110715.18-110715.108" - wire width 64 $pos$issuer_ls180.v:110715$4284_Y - attribute \src "issuer_ls180.v:110718.17-110718.105" - wire width 64 $pos$issuer_ls180.v:110718$4288_Y - attribute \src "issuer_ls180.v:110722.17-110722.102" - wire width 64 $pos$issuer_ls180.v:110722$4293_Y - attribute \src "issuer_ls180.v:110716.18-110716.115" - wire width 47 $sshl$issuer_ls180.v:110716$4285_Y - attribute \src "issuer_ls180.v:110717.18-110717.114" - wire width 27 $sshl$issuer_ls180.v:110717$4286_Y - attribute \src "issuer_ls180.v:110719.18-110719.114" - wire width 17 $sshl$issuer_ls180.v:110719$4289_Y - attribute \src "issuer_ls180.v:110720.18-110720.114" - wire width 17 $sshl$issuer_ls180.v:110720$4290_Y - attribute \src "issuer_ls180.v:110721.17-110721.109" - wire width 47 $sshl$issuer_ls180.v:110721$4291_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" - wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 input 8 \LDST_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 input 9 \LDST_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 24 input 7 \LDST_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 5 \LDST_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 input 3 \LDST_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 input 4 \LDST_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 6 input 6 \LDST_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" - wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \imm_b_ok - attribute \src "issuer_ls180.v:110636.7-110636.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 26 \li - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" - wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$issuer_ls180.v:110714$4281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \LDST_sh - connect \Y $extend$issuer_ls180.v:110714$4281_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$issuer_ls180.v:110715$4283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \LDST_SH32 - connect \Y $extend$issuer_ls180.v:110715$4283_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$issuer_ls180.v:110718$4287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \LDST_UI - connect \Y $extend$issuer_ls180.v:110718$4287_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $extend$issuer_ls180.v:110722$4292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A \$4 - connect \Y $extend$issuer_ls180.v:110722$4292_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$issuer_ls180.v:110714$4282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:110714$4281_Y - connect \Y $pos$issuer_ls180.v:110714$4282_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$issuer_ls180.v:110715$4284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:110715$4283_Y - connect \Y $pos$issuer_ls180.v:110715$4284_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$issuer_ls180.v:110718$4288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:110718$4287_Y - connect \Y $pos$issuer_ls180.v:110718$4288_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $pos$issuer_ls180.v:110722$4293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:110722$4292_Y - connect \Y $pos$issuer_ls180.v:110722$4293_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - cell $sshl $sshl$issuer_ls180.v:110716$4285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \LDST_SI - connect \B 5'10000 - connect \Y $sshl$issuer_ls180.v:110716$4285_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - cell $sshl $sshl$issuer_ls180.v:110717$4286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \LDST_LI - connect \B 2'10 - connect \Y $sshl$issuer_ls180.v:110717$4286_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $sshl$issuer_ls180.v:110719$4289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \LDST_BD - connect \B 2'10 - connect \Y $sshl$issuer_ls180.v:110719$4289_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$issuer_ls180.v:110720$4290 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \LDST_DS - connect \B 2'10 - connect \Y $sshl$issuer_ls180.v:110720$4290_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $sshl $sshl$issuer_ls180.v:110721$4291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $sshl$issuer_ls180.v:110721$4291_Y - end - attribute \src "issuer_ls180.v:110636.7-110636.20" - process $proc$issuer_ls180.v:110636$4302 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:110724.3-110770.6" - process $proc$issuer_ls180.v:110724$4294 - assign { } { } - assign { } { } - assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "issuer_ls180.v:110725.5-110725.29" - switch \initial - attribute \src "issuer_ls180.v:110725.9-110725.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b[63:0] \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b[63:0] \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b[63:0] \$7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b[63:0] \$9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b[63:0] \$11 - case - assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \imm_b $0\imm_b[63:0] - end - attribute \src "issuer_ls180.v:110771.3-110817.6" - process $proc$issuer_ls180.v:110771$4295 - assign { } { } - assign { } { } - assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "issuer_ls180.v:110772.5-110772.29" - switch \initial - attribute \src "issuer_ls180.v:110772.9-110772.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - case - assign $1\imm_b_ok[0:0] 1'0 - end - sync always - update \imm_b_ok $0\imm_b_ok[0:0] - end - attribute \src "issuer_ls180.v:110818.3-110828.6" - process $proc$issuer_ls180.v:110818$4296 - assign { } { } - assign { } { } - assign $0\si[15:0] $1\si[15:0] - attribute \src "issuer_ls180.v:110819.5-110819.29" - switch \initial - attribute \src "issuer_ls180.v:110819.9-110819.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\si[15:0] \LDST_SI - case - assign $1\si[15:0] 16'0000000000000000 - end - sync always - update \si $0\si[15:0] - end - attribute \src "issuer_ls180.v:110829.3-110839.6" - process $proc$issuer_ls180.v:110829$4297 - assign { } { } - assign { } { } - assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "issuer_ls180.v:110830.5-110830.29" - switch \initial - attribute \src "issuer_ls180.v:110830.9-110830.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\si_hi[31:0] \$13 [31:0] - case - assign $1\si_hi[31:0] 0 - end - sync always - update \si_hi $0\si_hi[31:0] - end - attribute \src "issuer_ls180.v:110840.3-110850.6" - process $proc$issuer_ls180.v:110840$4298 - assign { } { } - assign { } { } - assign $0\ui[15:0] $1\ui[15:0] - attribute \src "issuer_ls180.v:110841.5-110841.29" - switch \initial - attribute \src "issuer_ls180.v:110841.9-110841.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\ui[15:0] \LDST_UI - case - assign $1\ui[15:0] 16'0000000000000000 - end - sync always - update \ui $0\ui[15:0] - end - attribute \src "issuer_ls180.v:110851.3-110861.6" - process $proc$issuer_ls180.v:110851$4299 - assign { } { } - assign { } { } - assign $0\li[25:0] $1\li[25:0] - attribute \src "issuer_ls180.v:110852.5-110852.29" - switch \initial - attribute \src "issuer_ls180.v:110852.9-110852.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\li[25:0] \$16 [25:0] - case - assign $1\li[25:0] 26'00000000000000000000000000 - end - sync always - update \li $0\li[25:0] - end - attribute \src "issuer_ls180.v:110862.3-110872.6" - process $proc$issuer_ls180.v:110862$4300 - assign { } { } - assign { } { } - assign $0\bd[15:0] $1\bd[15:0] - attribute \src "issuer_ls180.v:110863.5-110863.29" - switch \initial - attribute \src "issuer_ls180.v:110863.9-110863.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\bd[15:0] \$19 [15:0] - case - assign $1\bd[15:0] 16'0000000000000000 - end - sync always - update \bd $0\bd[15:0] - end - attribute \src "issuer_ls180.v:110873.3-110883.6" - process $proc$issuer_ls180.v:110873$4301 - assign { } { } - assign { } { } - assign $0\ds[15:0] $1\ds[15:0] - attribute \src "issuer_ls180.v:110874.5-110874.29" - switch \initial - attribute \src "issuer_ls180.v:110874.9-110874.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\ds[15:0] \$22 [15:0] - case - assign $1\ds[15:0] 16'0000000000000000 - end - sync always - update \ds $0\ds[15:0] - end - connect \$9 $pos$issuer_ls180.v:110714$4282_Y - connect \$11 $pos$issuer_ls180.v:110715$4284_Y - connect \$14 $sshl$issuer_ls180.v:110716$4285_Y - connect \$17 $sshl$issuer_ls180.v:110717$4286_Y - connect \$1 $pos$issuer_ls180.v:110718$4288_Y - connect \$20 $sshl$issuer_ls180.v:110719$4289_Y - connect \$23 $sshl$issuer_ls180.v:110720$4290_Y - connect \$4 $sshl$issuer_ls180.v:110721$4291_Y - connect \$3 $pos$issuer_ls180.v:110722$4293_Y - connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 - connect \$13 \$14 - connect \$16 \$17 - connect \$19 \$20 - connect \$22 \$23 -end -attribute \src "issuer_ls180.v:110892.1-110940.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec_c" -attribute \generator "nMigen" -module \dec_c - attribute \src "issuer_ls180.v:110893.7-110893.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:110910.3-110924.6" - wire width 5 $0\reg_c[4:0] - attribute \src "issuer_ls180.v:110925.3-110939.6" - wire $0\reg_c_ok[0:0] - attribute \src "issuer_ls180.v:110910.3-110924.6" - wire width 5 $1\reg_c[4:0] - attribute \src "issuer_ls180.v:110925.3-110939.6" - wire $1\reg_c_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 4 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 3 \RS - attribute \src "issuer_ls180.v:110893.7-110893.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 output 1 \reg_c - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \reg_c_ok - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" - wire width 2 input 5 \sel_in - attribute \src "issuer_ls180.v:110893.7-110893.20" - process $proc$issuer_ls180.v:110893$4305 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:110910.3-110924.6" - process $proc$issuer_ls180.v:110910$4303 - assign { } { } - assign { } { } - assign $0\reg_c[4:0] $1\reg_c[4:0] - attribute \src "issuer_ls180.v:110911.5-110911.29" - switch \initial - attribute \src "issuer_ls180.v:110911.9-110911.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\reg_c[4:0] \RB - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\reg_c[4:0] \RS - case - assign $1\reg_c[4:0] 5'00000 - end - sync always - update \reg_c $0\reg_c[4:0] - end - attribute \src "issuer_ls180.v:110925.3-110939.6" - process $proc$issuer_ls180.v:110925$4304 - assign { } { } - assign { } { } - assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0] - attribute \src "issuer_ls180.v:110926.5-110926.29" - switch \initial - attribute \src "issuer_ls180.v:110926.9-110926.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\reg_c_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\reg_c_ok[0:0] 1'1 - case - assign $1\reg_c_ok[0:0] 1'0 - end - sync always - update \reg_c_ok $0\reg_c_ok[0:0] - end -end -attribute \src "issuer_ls180.v:110944.1-111241.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_cr_in" -attribute \generator "nMigen" -module \dec_cr_in - attribute \src "issuer_ls180.v:111135.3-111161.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:111162.3-111172.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:111113.3-111123.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:111173.3-111183.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:111184.3-111194.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:111086.3-111112.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:111222.3-111240.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "issuer_ls180.v:111124.3-111134.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:110945.7-110945.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:111195.3-111205.6" - wire $0\move_one[0:0] - attribute \src "issuer_ls180.v:111206.3-111221.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "issuer_ls180.v:111135.3-111161.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:111162.3-111172.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:111113.3-111123.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:111173.3-111183.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:111184.3-111194.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:111086.3-111112.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:111222.3-111240.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:111124.3-111134.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:111195.3-111205.6" - wire $1\move_one[0:0] - attribute \src "issuer_ls180.v:111206.3-111221.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:111222.3-111240.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "issuer_ls180.v:111206.3-111221.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "issuer_ls180.v:111079.17-111079.112" - wire $and$issuer_ls180.v:111079$4307_Y - attribute \src "issuer_ls180.v:111081.17-111081.112" - wire $and$issuer_ls180.v:111081$4309_Y - attribute \src "issuer_ls180.v:111078.17-111078.121" - wire $eq$issuer_ls180.v:111078$4306_Y - attribute \src "issuer_ls180.v:111080.17-111080.121" - wire $eq$issuer_ls180.v:111080$4308_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 4 \ALU_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 3 \ALU_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 8 \ALU_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 7 \ALU_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 5 \ALU_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 input 6 \ALU_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 2 \ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_fxm_ok - attribute \src "issuer_ls180.v:110945.7-110945.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $and$issuer_ls180.v:111079$4307 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$issuer_ls180.v:111079$4307_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $and$issuer_ls180.v:111081$4309 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$issuer_ls180.v:111081$4309_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $eq$issuer_ls180.v:111078$4306 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \ALU_internal_op - connect \B 7'0101101 - connect \Y $eq$issuer_ls180.v:111078$4306_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $eq$issuer_ls180.v:111080$4308 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \ALU_internal_op - connect \B 7'0101101 - connect \Y $eq$issuer_ls180.v:111080$4308_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:111082.9-111085.4" - cell \ppick \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "issuer_ls180.v:110945.7-110945.20" - process $proc$issuer_ls180.v:110945$4320 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:111086.3-111112.6" - process $proc$issuer_ls180.v:111086$4310 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:111087.5-111087.29" - switch \initial - attribute \src "issuer_ls180.v:111087.9-111087.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "issuer_ls180.v:111113.3-111123.6" - process $proc$issuer_ls180.v:111113$4311 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:111114.5-111114.29" - switch \initial - attribute \src "issuer_ls180.v:111114.9-111114.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "issuer_ls180.v:111124.3-111134.6" - process $proc$issuer_ls180.v:111124$4312 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:111125.5-111125.29" - switch \initial - attribute \src "issuer_ls180.v:111125.9-111125.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "issuer_ls180.v:111135.3-111161.6" - process $proc$issuer_ls180.v:111135$4313 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:111136.5-111136.29" - switch \initial - attribute \src "issuer_ls180.v:111136.9-111136.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \ALU_BI [4:2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \ALU_BA [4:2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \ALU_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "issuer_ls180.v:111162.3-111172.6" - process $proc$issuer_ls180.v:111162$4314 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:111163.5-111163.29" - switch \initial - attribute \src "issuer_ls180.v:111163.9-111163.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \ALU_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "issuer_ls180.v:111173.3-111183.6" - process $proc$issuer_ls180.v:111173$4315 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:111174.5-111174.29" - switch \initial - attribute \src "issuer_ls180.v:111174.9-111174.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \ALU_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "issuer_ls180.v:111184.3-111194.6" - process $proc$issuer_ls180.v:111184$4316 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:111185.5-111185.29" - switch \initial - attribute \src "issuer_ls180.v:111185.9-111185.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "issuer_ls180.v:111195.3-111205.6" - process $proc$issuer_ls180.v:111195$4317 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "issuer_ls180.v:111196.5-111196.29" - switch \initial - attribute \src "issuer_ls180.v:111196.9-111196.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "issuer_ls180.v:111206.3-111221.6" - process $proc$issuer_ls180.v:111206$4318 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:111207.5-111207.29" - switch \initial - attribute \src "issuer_ls180.v:111207.9-111207.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \ALU_FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "issuer_ls180.v:111222.3-111240.6" - process $proc$issuer_ls180.v:111222$4319 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:111223.5-111223.29" - switch \initial - attribute \src "issuer_ls180.v:111223.9-111223.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch \$7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$issuer_ls180.v:111078$4306_Y - connect \$3 $and$issuer_ls180.v:111079$4307_Y - connect \$5 $eq$issuer_ls180.v:111080$4308_Y - connect \$7 $and$issuer_ls180.v:111081$4309_Y -end -attribute \src "issuer_ls180.v:111245.1-111542.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_cr_in" -attribute \generator "nMigen" -module \dec_cr_in$140 - attribute \src "issuer_ls180.v:111436.3-111462.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:111463.3-111473.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:111414.3-111424.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:111474.3-111484.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:111485.3-111495.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:111387.3-111413.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:111523.3-111541.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "issuer_ls180.v:111425.3-111435.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:111246.7-111246.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:111496.3-111506.6" - wire $0\move_one[0:0] - attribute \src "issuer_ls180.v:111507.3-111522.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "issuer_ls180.v:111436.3-111462.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:111463.3-111473.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:111414.3-111424.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:111474.3-111484.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:111485.3-111495.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:111387.3-111413.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:111523.3-111541.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:111425.3-111435.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:111496.3-111506.6" - wire $1\move_one[0:0] - attribute \src "issuer_ls180.v:111507.3-111522.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:111523.3-111541.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "issuer_ls180.v:111507.3-111522.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "issuer_ls180.v:111380.17-111380.112" - wire $and$issuer_ls180.v:111380$4322_Y - attribute \src "issuer_ls180.v:111382.17-111382.112" - wire $and$issuer_ls180.v:111382$4324_Y - attribute \src "issuer_ls180.v:111379.17-111379.120" - wire $eq$issuer_ls180.v:111379$4321_Y - attribute \src "issuer_ls180.v:111381.17-111381.120" - wire $eq$issuer_ls180.v:111381$4323_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 4 \CR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 3 \CR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 8 \CR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 7 \CR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 5 \CR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 input 6 \CR_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 2 \CR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_fxm_ok - attribute \src "issuer_ls180.v:111246.7-111246.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $and$issuer_ls180.v:111380$4322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$issuer_ls180.v:111380$4322_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $and$issuer_ls180.v:111382$4324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$issuer_ls180.v:111382$4324_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $eq$issuer_ls180.v:111379$4321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \CR_internal_op - connect \B 7'0101101 - connect \Y $eq$issuer_ls180.v:111379$4321_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $eq$issuer_ls180.v:111381$4323 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \CR_internal_op - connect \B 7'0101101 - connect \Y $eq$issuer_ls180.v:111381$4323_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:111383.15-111386.4" - cell \ppick$141 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "issuer_ls180.v:111246.7-111246.20" - process $proc$issuer_ls180.v:111246$4335 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:111387.3-111413.6" - process $proc$issuer_ls180.v:111387$4325 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:111388.5-111388.29" - switch \initial - attribute \src "issuer_ls180.v:111388.9-111388.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "issuer_ls180.v:111414.3-111424.6" - process $proc$issuer_ls180.v:111414$4326 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:111415.5-111415.29" - switch \initial - attribute \src "issuer_ls180.v:111415.9-111415.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "issuer_ls180.v:111425.3-111435.6" - process $proc$issuer_ls180.v:111425$4327 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:111426.5-111426.29" - switch \initial - attribute \src "issuer_ls180.v:111426.9-111426.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "issuer_ls180.v:111436.3-111462.6" - process $proc$issuer_ls180.v:111436$4328 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:111437.5-111437.29" - switch \initial - attribute \src "issuer_ls180.v:111437.9-111437.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \CR_BI [4:2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \CR_BA [4:2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \CR_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "issuer_ls180.v:111463.3-111473.6" - process $proc$issuer_ls180.v:111463$4329 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:111464.5-111464.29" - switch \initial - attribute \src "issuer_ls180.v:111464.9-111464.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \CR_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "issuer_ls180.v:111474.3-111484.6" - process $proc$issuer_ls180.v:111474$4330 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:111475.5-111475.29" - switch \initial - attribute \src "issuer_ls180.v:111475.9-111475.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \CR_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "issuer_ls180.v:111485.3-111495.6" - process $proc$issuer_ls180.v:111485$4331 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:111486.5-111486.29" - switch \initial - attribute \src "issuer_ls180.v:111486.9-111486.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "issuer_ls180.v:111496.3-111506.6" - process $proc$issuer_ls180.v:111496$4332 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "issuer_ls180.v:111497.5-111497.29" - switch \initial - attribute \src "issuer_ls180.v:111497.9-111497.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "issuer_ls180.v:111507.3-111522.6" - process $proc$issuer_ls180.v:111507$4333 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:111508.5-111508.29" - switch \initial - attribute \src "issuer_ls180.v:111508.9-111508.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \CR_FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "issuer_ls180.v:111523.3-111541.6" - process $proc$issuer_ls180.v:111523$4334 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:111524.5-111524.29" - switch \initial - attribute \src "issuer_ls180.v:111524.9-111524.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch \$7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$issuer_ls180.v:111379$4321_Y - connect \$3 $and$issuer_ls180.v:111380$4322_Y - connect \$5 $eq$issuer_ls180.v:111381$4323_Y - connect \$7 $and$issuer_ls180.v:111382$4324_Y -end -attribute \src "issuer_ls180.v:111546.1-111843.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_cr_in" -attribute \generator "nMigen" -module \dec_cr_in$147 - attribute \src "issuer_ls180.v:111737.3-111763.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:111764.3-111774.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:111715.3-111725.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:111775.3-111785.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:111786.3-111796.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:111688.3-111714.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:111824.3-111842.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "issuer_ls180.v:111726.3-111736.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:111547.7-111547.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:111797.3-111807.6" - wire $0\move_one[0:0] - attribute \src "issuer_ls180.v:111808.3-111823.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "issuer_ls180.v:111737.3-111763.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:111764.3-111774.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:111715.3-111725.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:111775.3-111785.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:111786.3-111796.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:111688.3-111714.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:111824.3-111842.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:111726.3-111736.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:111797.3-111807.6" - wire $1\move_one[0:0] - attribute \src "issuer_ls180.v:111808.3-111823.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:111824.3-111842.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "issuer_ls180.v:111808.3-111823.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "issuer_ls180.v:111681.17-111681.112" - wire $and$issuer_ls180.v:111681$4337_Y - attribute \src "issuer_ls180.v:111683.17-111683.112" - wire $and$issuer_ls180.v:111683$4339_Y - attribute \src "issuer_ls180.v:111680.17-111680.124" - wire $eq$issuer_ls180.v:111680$4336_Y - attribute \src "issuer_ls180.v:111682.17-111682.124" - wire $eq$issuer_ls180.v:111682$4338_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 4 \BRANCH_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 3 \BRANCH_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 8 \BRANCH_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 7 \BRANCH_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 5 \BRANCH_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 input 6 \BRANCH_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 2 \BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_fxm_ok - attribute \src "issuer_ls180.v:111547.7-111547.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $and$issuer_ls180.v:111681$4337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$issuer_ls180.v:111681$4337_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $and$issuer_ls180.v:111683$4339 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$issuer_ls180.v:111683$4339_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $eq$issuer_ls180.v:111680$4336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \BRANCH_internal_op - connect \B 7'0101101 - connect \Y $eq$issuer_ls180.v:111680$4336_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $eq$issuer_ls180.v:111682$4338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \BRANCH_internal_op - connect \B 7'0101101 - connect \Y $eq$issuer_ls180.v:111682$4338_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:111684.15-111687.4" - cell \ppick$148 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "issuer_ls180.v:111547.7-111547.20" - process $proc$issuer_ls180.v:111547$4350 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:111688.3-111714.6" - process $proc$issuer_ls180.v:111688$4340 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:111689.5-111689.29" - switch \initial - attribute \src "issuer_ls180.v:111689.9-111689.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "issuer_ls180.v:111715.3-111725.6" - process $proc$issuer_ls180.v:111715$4341 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:111716.5-111716.29" - switch \initial - attribute \src "issuer_ls180.v:111716.9-111716.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "issuer_ls180.v:111726.3-111736.6" - process $proc$issuer_ls180.v:111726$4342 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:111727.5-111727.29" - switch \initial - attribute \src "issuer_ls180.v:111727.9-111727.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "issuer_ls180.v:111737.3-111763.6" - process $proc$issuer_ls180.v:111737$4343 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:111738.5-111738.29" - switch \initial - attribute \src "issuer_ls180.v:111738.9-111738.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \BRANCH_BI [4:2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \BRANCH_BA [4:2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \BRANCH_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "issuer_ls180.v:111764.3-111774.6" - process $proc$issuer_ls180.v:111764$4344 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:111765.5-111765.29" - switch \initial - attribute \src "issuer_ls180.v:111765.9-111765.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \BRANCH_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "issuer_ls180.v:111775.3-111785.6" - process $proc$issuer_ls180.v:111775$4345 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:111776.5-111776.29" - switch \initial - attribute \src "issuer_ls180.v:111776.9-111776.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \BRANCH_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "issuer_ls180.v:111786.3-111796.6" - process $proc$issuer_ls180.v:111786$4346 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:111787.5-111787.29" - switch \initial - attribute \src "issuer_ls180.v:111787.9-111787.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "issuer_ls180.v:111797.3-111807.6" - process $proc$issuer_ls180.v:111797$4347 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "issuer_ls180.v:111798.5-111798.29" - switch \initial - attribute \src "issuer_ls180.v:111798.9-111798.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "issuer_ls180.v:111808.3-111823.6" - process $proc$issuer_ls180.v:111808$4348 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:111809.5-111809.29" - switch \initial - attribute \src "issuer_ls180.v:111809.9-111809.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \BRANCH_FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "issuer_ls180.v:111824.3-111842.6" - process $proc$issuer_ls180.v:111824$4349 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:111825.5-111825.29" - switch \initial - attribute \src "issuer_ls180.v:111825.9-111825.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch \$7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$issuer_ls180.v:111680$4336_Y - connect \$3 $and$issuer_ls180.v:111681$4337_Y - connect \$5 $eq$issuer_ls180.v:111682$4338_Y - connect \$7 $and$issuer_ls180.v:111683$4339_Y -end -attribute \src "issuer_ls180.v:111847.1-112144.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_cr_in" -attribute \generator "nMigen" -module \dec_cr_in$155 - attribute \src "issuer_ls180.v:112038.3-112064.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:112065.3-112075.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:112016.3-112026.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:112076.3-112086.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:112087.3-112097.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:111989.3-112015.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:112125.3-112143.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "issuer_ls180.v:112027.3-112037.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:111848.7-111848.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:112098.3-112108.6" - wire $0\move_one[0:0] - attribute \src "issuer_ls180.v:112109.3-112124.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "issuer_ls180.v:112038.3-112064.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:112065.3-112075.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:112016.3-112026.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:112076.3-112086.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:112087.3-112097.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:111989.3-112015.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:112125.3-112143.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:112027.3-112037.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:112098.3-112108.6" - wire $1\move_one[0:0] - attribute \src "issuer_ls180.v:112109.3-112124.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:112125.3-112143.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "issuer_ls180.v:112109.3-112124.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "issuer_ls180.v:111982.17-111982.112" - wire $and$issuer_ls180.v:111982$4352_Y - attribute \src "issuer_ls180.v:111984.17-111984.112" - wire $and$issuer_ls180.v:111984$4354_Y - attribute \src "issuer_ls180.v:111981.17-111981.125" - wire $eq$issuer_ls180.v:111981$4351_Y - attribute \src "issuer_ls180.v:111983.17-111983.125" - wire $eq$issuer_ls180.v:111983$4353_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 4 \LOGICAL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 3 \LOGICAL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 8 \LOGICAL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 7 \LOGICAL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 5 \LOGICAL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 input 6 \LOGICAL_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 2 \LOGICAL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_fxm_ok - attribute \src "issuer_ls180.v:111848.7-111848.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $and$issuer_ls180.v:111982$4352 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$issuer_ls180.v:111982$4352_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $and$issuer_ls180.v:111984$4354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$issuer_ls180.v:111984$4354_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $eq$issuer_ls180.v:111981$4351 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LOGICAL_internal_op - connect \B 7'0101101 - connect \Y $eq$issuer_ls180.v:111981$4351_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $eq$issuer_ls180.v:111983$4353 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LOGICAL_internal_op - connect \B 7'0101101 - connect \Y $eq$issuer_ls180.v:111983$4353_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:111985.15-111988.4" - cell \ppick$156 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "issuer_ls180.v:111848.7-111848.20" - process $proc$issuer_ls180.v:111848$4365 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:111989.3-112015.6" - process $proc$issuer_ls180.v:111989$4355 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:111990.5-111990.29" - switch \initial - attribute \src "issuer_ls180.v:111990.9-111990.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "issuer_ls180.v:112016.3-112026.6" - process $proc$issuer_ls180.v:112016$4356 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:112017.5-112017.29" - switch \initial - attribute \src "issuer_ls180.v:112017.9-112017.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "issuer_ls180.v:112027.3-112037.6" - process $proc$issuer_ls180.v:112027$4357 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:112028.5-112028.29" - switch \initial - attribute \src "issuer_ls180.v:112028.9-112028.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "issuer_ls180.v:112038.3-112064.6" - process $proc$issuer_ls180.v:112038$4358 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:112039.5-112039.29" - switch \initial - attribute \src "issuer_ls180.v:112039.9-112039.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \LOGICAL_BI [4:2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \LOGICAL_BA [4:2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \LOGICAL_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "issuer_ls180.v:112065.3-112075.6" - process $proc$issuer_ls180.v:112065$4359 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:112066.5-112066.29" - switch \initial - attribute \src "issuer_ls180.v:112066.9-112066.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \LOGICAL_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "issuer_ls180.v:112076.3-112086.6" - process $proc$issuer_ls180.v:112076$4360 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:112077.5-112077.29" - switch \initial - attribute \src "issuer_ls180.v:112077.9-112077.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \LOGICAL_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "issuer_ls180.v:112087.3-112097.6" - process $proc$issuer_ls180.v:112087$4361 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:112088.5-112088.29" - switch \initial - attribute \src "issuer_ls180.v:112088.9-112088.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "issuer_ls180.v:112098.3-112108.6" - process $proc$issuer_ls180.v:112098$4362 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "issuer_ls180.v:112099.5-112099.29" - switch \initial - attribute \src "issuer_ls180.v:112099.9-112099.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "issuer_ls180.v:112109.3-112124.6" - process $proc$issuer_ls180.v:112109$4363 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:112110.5-112110.29" - switch \initial - attribute \src "issuer_ls180.v:112110.9-112110.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \LOGICAL_FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "issuer_ls180.v:112125.3-112143.6" - process $proc$issuer_ls180.v:112125$4364 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:112126.5-112126.29" - switch \initial - attribute \src "issuer_ls180.v:112126.9-112126.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch \$7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$issuer_ls180.v:111981$4351_Y - connect \$3 $and$issuer_ls180.v:111982$4352_Y - connect \$5 $eq$issuer_ls180.v:111983$4353_Y - connect \$7 $and$issuer_ls180.v:111984$4354_Y -end -attribute \src "issuer_ls180.v:112148.1-112445.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_cr_in" -attribute \generator "nMigen" -module \dec_cr_in$164 - attribute \src "issuer_ls180.v:112339.3-112365.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:112366.3-112376.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:112317.3-112327.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:112377.3-112387.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:112388.3-112398.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:112290.3-112316.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:112426.3-112444.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "issuer_ls180.v:112328.3-112338.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:112149.7-112149.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:112399.3-112409.6" - wire $0\move_one[0:0] - attribute \src "issuer_ls180.v:112410.3-112425.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "issuer_ls180.v:112339.3-112365.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:112366.3-112376.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:112317.3-112327.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:112377.3-112387.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:112388.3-112398.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:112290.3-112316.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:112426.3-112444.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:112328.3-112338.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:112399.3-112409.6" - wire $1\move_one[0:0] - attribute \src "issuer_ls180.v:112410.3-112425.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:112426.3-112444.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "issuer_ls180.v:112410.3-112425.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "issuer_ls180.v:112283.17-112283.112" - wire $and$issuer_ls180.v:112283$4367_Y - attribute \src "issuer_ls180.v:112285.17-112285.112" - wire $and$issuer_ls180.v:112285$4369_Y - attribute \src "issuer_ls180.v:112282.17-112282.121" - wire $eq$issuer_ls180.v:112282$4366_Y - attribute \src "issuer_ls180.v:112284.17-112284.121" - wire $eq$issuer_ls180.v:112284$4368_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 4 \SPR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 3 \SPR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 8 \SPR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 7 \SPR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 5 \SPR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 input 6 \SPR_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 2 \SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_fxm_ok - attribute \src "issuer_ls180.v:112149.7-112149.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $and$issuer_ls180.v:112283$4367 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$issuer_ls180.v:112283$4367_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $and$issuer_ls180.v:112285$4369 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$issuer_ls180.v:112285$4369_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $eq$issuer_ls180.v:112282$4366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SPR_internal_op - connect \B 7'0101101 - connect \Y $eq$issuer_ls180.v:112282$4366_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $eq$issuer_ls180.v:112284$4368 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SPR_internal_op - connect \B 7'0101101 - connect \Y $eq$issuer_ls180.v:112284$4368_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:112286.15-112289.4" - cell \ppick$165 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "issuer_ls180.v:112149.7-112149.20" - process $proc$issuer_ls180.v:112149$4380 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:112290.3-112316.6" - process $proc$issuer_ls180.v:112290$4370 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:112291.5-112291.29" - switch \initial - attribute \src "issuer_ls180.v:112291.9-112291.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "issuer_ls180.v:112317.3-112327.6" - process $proc$issuer_ls180.v:112317$4371 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:112318.5-112318.29" - switch \initial - attribute \src "issuer_ls180.v:112318.9-112318.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "issuer_ls180.v:112328.3-112338.6" - process $proc$issuer_ls180.v:112328$4372 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:112329.5-112329.29" - switch \initial - attribute \src "issuer_ls180.v:112329.9-112329.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "issuer_ls180.v:112339.3-112365.6" - process $proc$issuer_ls180.v:112339$4373 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:112340.5-112340.29" - switch \initial - attribute \src "issuer_ls180.v:112340.9-112340.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \SPR_BI [4:2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \SPR_BA [4:2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \SPR_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "issuer_ls180.v:112366.3-112376.6" - process $proc$issuer_ls180.v:112366$4374 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:112367.5-112367.29" - switch \initial - attribute \src "issuer_ls180.v:112367.9-112367.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \SPR_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "issuer_ls180.v:112377.3-112387.6" - process $proc$issuer_ls180.v:112377$4375 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:112378.5-112378.29" - switch \initial - attribute \src "issuer_ls180.v:112378.9-112378.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \SPR_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "issuer_ls180.v:112388.3-112398.6" - process $proc$issuer_ls180.v:112388$4376 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:112389.5-112389.29" - switch \initial - attribute \src "issuer_ls180.v:112389.9-112389.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "issuer_ls180.v:112399.3-112409.6" - process $proc$issuer_ls180.v:112399$4377 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "issuer_ls180.v:112400.5-112400.29" - switch \initial - attribute \src "issuer_ls180.v:112400.9-112400.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "issuer_ls180.v:112410.3-112425.6" - process $proc$issuer_ls180.v:112410$4378 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:112411.5-112411.29" - switch \initial - attribute \src "issuer_ls180.v:112411.9-112411.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \SPR_FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "issuer_ls180.v:112426.3-112444.6" - process $proc$issuer_ls180.v:112426$4379 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:112427.5-112427.29" - switch \initial - attribute \src "issuer_ls180.v:112427.9-112427.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch \$7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$issuer_ls180.v:112282$4366_Y - connect \$3 $and$issuer_ls180.v:112283$4367_Y - connect \$5 $eq$issuer_ls180.v:112284$4368_Y - connect \$7 $and$issuer_ls180.v:112285$4369_Y -end -attribute \src "issuer_ls180.v:112449.1-112746.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_cr_in" -attribute \generator "nMigen" -module \dec_cr_in$171 - attribute \src "issuer_ls180.v:112640.3-112666.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:112667.3-112677.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:112618.3-112628.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:112678.3-112688.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:112689.3-112699.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:112591.3-112617.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:112727.3-112745.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "issuer_ls180.v:112629.3-112639.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:112450.7-112450.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:112700.3-112710.6" - wire $0\move_one[0:0] - attribute \src "issuer_ls180.v:112711.3-112726.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "issuer_ls180.v:112640.3-112666.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:112667.3-112677.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:112618.3-112628.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:112678.3-112688.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:112689.3-112699.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:112591.3-112617.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:112727.3-112745.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:112629.3-112639.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:112700.3-112710.6" - wire $1\move_one[0:0] - attribute \src "issuer_ls180.v:112711.3-112726.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:112727.3-112745.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "issuer_ls180.v:112711.3-112726.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "issuer_ls180.v:112584.17-112584.112" - wire $and$issuer_ls180.v:112584$4382_Y - attribute \src "issuer_ls180.v:112586.17-112586.112" - wire $and$issuer_ls180.v:112586$4384_Y - attribute \src "issuer_ls180.v:112583.17-112583.121" - wire $eq$issuer_ls180.v:112583$4381_Y - attribute \src "issuer_ls180.v:112585.17-112585.121" - wire $eq$issuer_ls180.v:112585$4383_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 4 \DIV_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 3 \DIV_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 8 \DIV_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 7 \DIV_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 5 \DIV_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 input 6 \DIV_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 2 \DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_fxm_ok - attribute \src "issuer_ls180.v:112450.7-112450.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $and$issuer_ls180.v:112584$4382 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$issuer_ls180.v:112584$4382_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $and$issuer_ls180.v:112586$4384 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$issuer_ls180.v:112586$4384_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $eq$issuer_ls180.v:112583$4381 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \DIV_internal_op - connect \B 7'0101101 - connect \Y $eq$issuer_ls180.v:112583$4381_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $eq$issuer_ls180.v:112585$4383 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \DIV_internal_op - connect \B 7'0101101 - connect \Y $eq$issuer_ls180.v:112585$4383_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:112587.15-112590.4" - cell \ppick$172 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "issuer_ls180.v:112450.7-112450.20" - process $proc$issuer_ls180.v:112450$4395 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:112591.3-112617.6" - process $proc$issuer_ls180.v:112591$4385 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:112592.5-112592.29" - switch \initial - attribute \src "issuer_ls180.v:112592.9-112592.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "issuer_ls180.v:112618.3-112628.6" - process $proc$issuer_ls180.v:112618$4386 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:112619.5-112619.29" - switch \initial - attribute \src "issuer_ls180.v:112619.9-112619.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "issuer_ls180.v:112629.3-112639.6" - process $proc$issuer_ls180.v:112629$4387 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:112630.5-112630.29" - switch \initial - attribute \src "issuer_ls180.v:112630.9-112630.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "issuer_ls180.v:112640.3-112666.6" - process $proc$issuer_ls180.v:112640$4388 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:112641.5-112641.29" - switch \initial - attribute \src "issuer_ls180.v:112641.9-112641.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \DIV_BI [4:2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \DIV_BA [4:2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \DIV_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "issuer_ls180.v:112667.3-112677.6" - process $proc$issuer_ls180.v:112667$4389 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:112668.5-112668.29" - switch \initial - attribute \src "issuer_ls180.v:112668.9-112668.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \DIV_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "issuer_ls180.v:112678.3-112688.6" - process $proc$issuer_ls180.v:112678$4390 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:112679.5-112679.29" - switch \initial - attribute \src "issuer_ls180.v:112679.9-112679.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \DIV_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "issuer_ls180.v:112689.3-112699.6" - process $proc$issuer_ls180.v:112689$4391 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:112690.5-112690.29" - switch \initial - attribute \src "issuer_ls180.v:112690.9-112690.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "issuer_ls180.v:112700.3-112710.6" - process $proc$issuer_ls180.v:112700$4392 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "issuer_ls180.v:112701.5-112701.29" - switch \initial - attribute \src "issuer_ls180.v:112701.9-112701.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "issuer_ls180.v:112711.3-112726.6" - process $proc$issuer_ls180.v:112711$4393 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:112712.5-112712.29" - switch \initial - attribute \src "issuer_ls180.v:112712.9-112712.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \DIV_FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "issuer_ls180.v:112727.3-112745.6" - process $proc$issuer_ls180.v:112727$4394 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:112728.5-112728.29" - switch \initial - attribute \src "issuer_ls180.v:112728.9-112728.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch \$7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$issuer_ls180.v:112583$4381_Y - connect \$3 $and$issuer_ls180.v:112584$4382_Y - connect \$5 $eq$issuer_ls180.v:112585$4383_Y - connect \$7 $and$issuer_ls180.v:112586$4384_Y -end -attribute \src "issuer_ls180.v:112750.1-113047.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_cr_in" -attribute \generator "nMigen" -module \dec_cr_in$180 - attribute \src "issuer_ls180.v:112941.3-112967.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:112968.3-112978.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:112919.3-112929.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:112979.3-112989.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:112990.3-113000.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:112892.3-112918.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:113028.3-113046.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "issuer_ls180.v:112930.3-112940.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:112751.7-112751.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:113001.3-113011.6" - wire $0\move_one[0:0] - attribute \src "issuer_ls180.v:113012.3-113027.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "issuer_ls180.v:112941.3-112967.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:112968.3-112978.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:112919.3-112929.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:112979.3-112989.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:112990.3-113000.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:112892.3-112918.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:113028.3-113046.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:112930.3-112940.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:113001.3-113011.6" - wire $1\move_one[0:0] - attribute \src "issuer_ls180.v:113012.3-113027.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:113028.3-113046.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "issuer_ls180.v:113012.3-113027.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "issuer_ls180.v:112885.17-112885.112" - wire $and$issuer_ls180.v:112885$4397_Y - attribute \src "issuer_ls180.v:112887.17-112887.112" - wire $and$issuer_ls180.v:112887$4399_Y - attribute \src "issuer_ls180.v:112884.17-112884.121" - wire $eq$issuer_ls180.v:112884$4396_Y - attribute \src "issuer_ls180.v:112886.17-112886.121" - wire $eq$issuer_ls180.v:112886$4398_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 4 \MUL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 3 \MUL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 8 \MUL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 7 \MUL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 5 \MUL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 input 6 \MUL_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 2 \MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_fxm_ok - attribute \src "issuer_ls180.v:112751.7-112751.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $and$issuer_ls180.v:112885$4397 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$issuer_ls180.v:112885$4397_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $and$issuer_ls180.v:112887$4399 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$issuer_ls180.v:112887$4399_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $eq$issuer_ls180.v:112884$4396 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \MUL_internal_op - connect \B 7'0101101 - connect \Y $eq$issuer_ls180.v:112884$4396_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $eq$issuer_ls180.v:112886$4398 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \MUL_internal_op - connect \B 7'0101101 - connect \Y $eq$issuer_ls180.v:112886$4398_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:112888.15-112891.4" - cell \ppick$181 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "issuer_ls180.v:112751.7-112751.20" - process $proc$issuer_ls180.v:112751$4410 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:112892.3-112918.6" - process $proc$issuer_ls180.v:112892$4400 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:112893.5-112893.29" - switch \initial - attribute \src "issuer_ls180.v:112893.9-112893.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "issuer_ls180.v:112919.3-112929.6" - process $proc$issuer_ls180.v:112919$4401 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:112920.5-112920.29" - switch \initial - attribute \src "issuer_ls180.v:112920.9-112920.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "issuer_ls180.v:112930.3-112940.6" - process $proc$issuer_ls180.v:112930$4402 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:112931.5-112931.29" - switch \initial - attribute \src "issuer_ls180.v:112931.9-112931.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "issuer_ls180.v:112941.3-112967.6" - process $proc$issuer_ls180.v:112941$4403 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:112942.5-112942.29" - switch \initial - attribute \src "issuer_ls180.v:112942.9-112942.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \MUL_BI [4:2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \MUL_BA [4:2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \MUL_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "issuer_ls180.v:112968.3-112978.6" - process $proc$issuer_ls180.v:112968$4404 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:112969.5-112969.29" - switch \initial - attribute \src "issuer_ls180.v:112969.9-112969.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \MUL_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "issuer_ls180.v:112979.3-112989.6" - process $proc$issuer_ls180.v:112979$4405 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:112980.5-112980.29" - switch \initial - attribute \src "issuer_ls180.v:112980.9-112980.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \MUL_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "issuer_ls180.v:112990.3-113000.6" - process $proc$issuer_ls180.v:112990$4406 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:112991.5-112991.29" - switch \initial - attribute \src "issuer_ls180.v:112991.9-112991.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "issuer_ls180.v:113001.3-113011.6" - process $proc$issuer_ls180.v:113001$4407 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "issuer_ls180.v:113002.5-113002.29" - switch \initial - attribute \src "issuer_ls180.v:113002.9-113002.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "issuer_ls180.v:113012.3-113027.6" - process $proc$issuer_ls180.v:113012$4408 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:113013.5-113013.29" - switch \initial - attribute \src "issuer_ls180.v:113013.9-113013.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \MUL_FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "issuer_ls180.v:113028.3-113046.6" - process $proc$issuer_ls180.v:113028$4409 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:113029.5-113029.29" - switch \initial - attribute \src "issuer_ls180.v:113029.9-113029.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch \$7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$issuer_ls180.v:112884$4396_Y - connect \$3 $and$issuer_ls180.v:112885$4397_Y - connect \$5 $eq$issuer_ls180.v:112886$4398_Y - connect \$7 $and$issuer_ls180.v:112887$4399_Y -end -attribute \src "issuer_ls180.v:113051.1-113348.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_cr_in" -attribute \generator "nMigen" -module \dec_cr_in$188 - attribute \src "issuer_ls180.v:113242.3-113268.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:113269.3-113279.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:113220.3-113230.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:113280.3-113290.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:113291.3-113301.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:113193.3-113219.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:113329.3-113347.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "issuer_ls180.v:113231.3-113241.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:113052.7-113052.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:113302.3-113312.6" - wire $0\move_one[0:0] - attribute \src "issuer_ls180.v:113313.3-113328.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "issuer_ls180.v:113242.3-113268.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:113269.3-113279.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:113220.3-113230.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:113280.3-113290.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:113291.3-113301.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:113193.3-113219.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:113329.3-113347.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:113231.3-113241.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:113302.3-113312.6" - wire $1\move_one[0:0] - attribute \src "issuer_ls180.v:113313.3-113328.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:113329.3-113347.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "issuer_ls180.v:113313.3-113328.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "issuer_ls180.v:113186.17-113186.112" - wire $and$issuer_ls180.v:113186$4412_Y - attribute \src "issuer_ls180.v:113188.17-113188.112" - wire $and$issuer_ls180.v:113188$4414_Y - attribute \src "issuer_ls180.v:113185.17-113185.127" - wire $eq$issuer_ls180.v:113185$4411_Y - attribute \src "issuer_ls180.v:113187.17-113187.127" - wire $eq$issuer_ls180.v:113187$4413_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 4 \SHIFT_ROT_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 3 \SHIFT_ROT_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 8 \SHIFT_ROT_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 7 \SHIFT_ROT_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 5 \SHIFT_ROT_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 input 6 \SHIFT_ROT_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 2 \SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_fxm_ok - attribute \src "issuer_ls180.v:113052.7-113052.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $and$issuer_ls180.v:113186$4412 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$issuer_ls180.v:113186$4412_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $and$issuer_ls180.v:113188$4414 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$issuer_ls180.v:113188$4414_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $eq$issuer_ls180.v:113185$4411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SHIFT_ROT_internal_op - connect \B 7'0101101 - connect \Y $eq$issuer_ls180.v:113185$4411_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $eq$issuer_ls180.v:113187$4413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SHIFT_ROT_internal_op - connect \B 7'0101101 - connect \Y $eq$issuer_ls180.v:113187$4413_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:113189.15-113192.4" - cell \ppick$189 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "issuer_ls180.v:113052.7-113052.20" - process $proc$issuer_ls180.v:113052$4425 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:113193.3-113219.6" - process $proc$issuer_ls180.v:113193$4415 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:113194.5-113194.29" - switch \initial - attribute \src "issuer_ls180.v:113194.9-113194.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "issuer_ls180.v:113220.3-113230.6" - process $proc$issuer_ls180.v:113220$4416 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:113221.5-113221.29" - switch \initial - attribute \src "issuer_ls180.v:113221.9-113221.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "issuer_ls180.v:113231.3-113241.6" - process $proc$issuer_ls180.v:113231$4417 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:113232.5-113232.29" - switch \initial - attribute \src "issuer_ls180.v:113232.9-113232.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "issuer_ls180.v:113242.3-113268.6" - process $proc$issuer_ls180.v:113242$4418 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:113243.5-113243.29" - switch \initial - attribute \src "issuer_ls180.v:113243.9-113243.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \SHIFT_ROT_BI [4:2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \SHIFT_ROT_BA [4:2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \SHIFT_ROT_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "issuer_ls180.v:113269.3-113279.6" - process $proc$issuer_ls180.v:113269$4419 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:113270.5-113270.29" - switch \initial - attribute \src "issuer_ls180.v:113270.9-113270.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \SHIFT_ROT_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "issuer_ls180.v:113280.3-113290.6" - process $proc$issuer_ls180.v:113280$4420 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:113281.5-113281.29" - switch \initial - attribute \src "issuer_ls180.v:113281.9-113281.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \SHIFT_ROT_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "issuer_ls180.v:113291.3-113301.6" - process $proc$issuer_ls180.v:113291$4421 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:113292.5-113292.29" - switch \initial - attribute \src "issuer_ls180.v:113292.9-113292.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "issuer_ls180.v:113302.3-113312.6" - process $proc$issuer_ls180.v:113302$4422 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "issuer_ls180.v:113303.5-113303.29" - switch \initial - attribute \src "issuer_ls180.v:113303.9-113303.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "issuer_ls180.v:113313.3-113328.6" - process $proc$issuer_ls180.v:113313$4423 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:113314.5-113314.29" - switch \initial - attribute \src "issuer_ls180.v:113314.9-113314.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \SHIFT_ROT_FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "issuer_ls180.v:113329.3-113347.6" - process $proc$issuer_ls180.v:113329$4424 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:113330.5-113330.29" - switch \initial - attribute \src "issuer_ls180.v:113330.9-113330.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch \$7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$issuer_ls180.v:113185$4411_Y - connect \$3 $and$issuer_ls180.v:113186$4412_Y - connect \$5 $eq$issuer_ls180.v:113187$4413_Y - connect \$7 $and$issuer_ls180.v:113188$4414_Y -end -attribute \src "issuer_ls180.v:113352.1-113649.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_cr_in" -attribute \generator "nMigen" -module \dec_cr_in$196 - attribute \src "issuer_ls180.v:113543.3-113569.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:113570.3-113580.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:113521.3-113531.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:113581.3-113591.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:113592.3-113602.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:113494.3-113520.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:113630.3-113648.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "issuer_ls180.v:113532.3-113542.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:113353.7-113353.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:113603.3-113613.6" - wire $0\move_one[0:0] - attribute \src "issuer_ls180.v:113614.3-113629.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "issuer_ls180.v:113543.3-113569.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:113570.3-113580.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:113521.3-113531.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:113581.3-113591.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:113592.3-113602.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:113494.3-113520.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:113630.3-113648.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:113532.3-113542.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:113603.3-113613.6" - wire $1\move_one[0:0] - attribute \src "issuer_ls180.v:113614.3-113629.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:113630.3-113648.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "issuer_ls180.v:113614.3-113629.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "issuer_ls180.v:113487.17-113487.112" - wire $and$issuer_ls180.v:113487$4427_Y - attribute \src "issuer_ls180.v:113489.17-113489.112" - wire $and$issuer_ls180.v:113489$4429_Y - attribute \src "issuer_ls180.v:113486.17-113486.122" - wire $eq$issuer_ls180.v:113486$4426_Y - attribute \src "issuer_ls180.v:113488.17-113488.122" - wire $eq$issuer_ls180.v:113488$4428_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 4 \LDST_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 3 \LDST_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 8 \LDST_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 7 \LDST_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 5 \LDST_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 input 6 \LDST_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 2 \LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_fxm_ok - attribute \src "issuer_ls180.v:113353.7-113353.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $and$issuer_ls180.v:113487$4427 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$issuer_ls180.v:113487$4427_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $and$issuer_ls180.v:113489$4429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$issuer_ls180.v:113489$4429_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $eq$issuer_ls180.v:113486$4426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LDST_internal_op - connect \B 7'0101101 - connect \Y $eq$issuer_ls180.v:113486$4426_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $eq$issuer_ls180.v:113488$4428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LDST_internal_op - connect \B 7'0101101 - connect \Y $eq$issuer_ls180.v:113488$4428_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:113490.15-113493.4" - cell \ppick$197 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "issuer_ls180.v:113353.7-113353.20" - process $proc$issuer_ls180.v:113353$4440 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:113494.3-113520.6" - process $proc$issuer_ls180.v:113494$4430 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:113495.5-113495.29" - switch \initial - attribute \src "issuer_ls180.v:113495.9-113495.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "issuer_ls180.v:113521.3-113531.6" - process $proc$issuer_ls180.v:113521$4431 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:113522.5-113522.29" - switch \initial - attribute \src "issuer_ls180.v:113522.9-113522.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "issuer_ls180.v:113532.3-113542.6" - process $proc$issuer_ls180.v:113532$4432 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:113533.5-113533.29" - switch \initial - attribute \src "issuer_ls180.v:113533.9-113533.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "issuer_ls180.v:113543.3-113569.6" - process $proc$issuer_ls180.v:113543$4433 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:113544.5-113544.29" - switch \initial - attribute \src "issuer_ls180.v:113544.9-113544.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \LDST_BI [4:2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \LDST_BA [4:2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \LDST_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "issuer_ls180.v:113570.3-113580.6" - process $proc$issuer_ls180.v:113570$4434 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:113571.5-113571.29" - switch \initial - attribute \src "issuer_ls180.v:113571.9-113571.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \LDST_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "issuer_ls180.v:113581.3-113591.6" - process $proc$issuer_ls180.v:113581$4435 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:113582.5-113582.29" - switch \initial - attribute \src "issuer_ls180.v:113582.9-113582.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \LDST_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "issuer_ls180.v:113592.3-113602.6" - process $proc$issuer_ls180.v:113592$4436 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:113593.5-113593.29" - switch \initial - attribute \src "issuer_ls180.v:113593.9-113593.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "issuer_ls180.v:113603.3-113613.6" - process $proc$issuer_ls180.v:113603$4437 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "issuer_ls180.v:113604.5-113604.29" - switch \initial - attribute \src "issuer_ls180.v:113604.9-113604.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "issuer_ls180.v:113614.3-113629.6" - process $proc$issuer_ls180.v:113614$4438 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:113615.5-113615.29" - switch \initial - attribute \src "issuer_ls180.v:113615.9-113615.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \LDST_FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "issuer_ls180.v:113630.3-113648.6" - process $proc$issuer_ls180.v:113630$4439 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:113631.5-113631.29" - switch \initial - attribute \src "issuer_ls180.v:113631.9-113631.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch \$7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$issuer_ls180.v:113486$4426_Y - connect \$3 $and$issuer_ls180.v:113487$4427_Y - connect \$5 $eq$issuer_ls180.v:113488$4428_Y - connect \$7 $and$issuer_ls180.v:113489$4429_Y -end -attribute \src "issuer_ls180.v:113653.1-113958.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_in" -attribute \generator "nMigen" -module \dec_cr_in$205 - attribute \src "issuer_ls180.v:113852.3-113878.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:113879.3-113889.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:113830.3-113840.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:113890.3-113900.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:113901.3-113911.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:113803.3-113829.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:113939.3-113957.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "issuer_ls180.v:113841.3-113851.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:113654.7-113654.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:113912.3-113922.6" - wire $0\move_one[0:0] - attribute \src "issuer_ls180.v:113923.3-113938.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "issuer_ls180.v:113852.3-113878.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:113879.3-113889.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:113830.3-113840.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:113890.3-113900.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:113901.3-113911.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:113803.3-113829.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:113939.3-113957.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:113841.3-113851.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:113912.3-113922.6" - wire $1\move_one[0:0] - attribute \src "issuer_ls180.v:113923.3-113938.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:113939.3-113957.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "issuer_ls180.v:113923.3-113938.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "issuer_ls180.v:113796.17-113796.112" - wire $and$issuer_ls180.v:113796$4442_Y - attribute \src "issuer_ls180.v:113798.17-113798.112" - wire $and$issuer_ls180.v:113798$4444_Y - attribute \src "issuer_ls180.v:113795.17-113795.117" - wire $eq$issuer_ls180.v:113795$4441_Y - attribute \src "issuer_ls180.v:113797.17-113797.117" - wire $eq$issuer_ls180.v:113797$4443_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 12 \BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 11 \BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 16 \BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 15 \BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 13 \BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 input 14 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 input 17 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 5 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 7 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 8 \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 9 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 10 \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 6 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 output 3 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 4 \cr_fxm_ok - attribute \src "issuer_ls180.v:113654.7-113654.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 input 18 \insn_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 2 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $and$issuer_ls180.v:113796$4442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$issuer_ls180.v:113796$4442_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $and$issuer_ls180.v:113798$4444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$issuer_ls180.v:113798$4444_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $eq$issuer_ls180.v:113795$4441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0101101 - connect \Y $eq$issuer_ls180.v:113795$4441_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $eq$issuer_ls180.v:113797$4443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0101101 - connect \Y $eq$issuer_ls180.v:113797$4443_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:113799.15-113802.4" - cell \ppick$206 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "issuer_ls180.v:113654.7-113654.20" - process $proc$issuer_ls180.v:113654$4455 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:113803.3-113829.6" - process $proc$issuer_ls180.v:113803$4445 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:113804.5-113804.29" - switch \initial - attribute \src "issuer_ls180.v:113804.9-113804.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "issuer_ls180.v:113830.3-113840.6" - process $proc$issuer_ls180.v:113830$4446 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "issuer_ls180.v:113831.5-113831.29" - switch \initial - attribute \src "issuer_ls180.v:113831.9-113831.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "issuer_ls180.v:113841.3-113851.6" - process $proc$issuer_ls180.v:113841$4447 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:113842.5-113842.29" - switch \initial - attribute \src "issuer_ls180.v:113842.9-113842.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "issuer_ls180.v:113852.3-113878.6" - process $proc$issuer_ls180.v:113852$4448 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:113853.5-113853.29" - switch \initial - attribute \src "issuer_ls180.v:113853.9-113853.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \BI [4:2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \BA [4:2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "issuer_ls180.v:113879.3-113889.6" - process $proc$issuer_ls180.v:113879$4449 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "issuer_ls180.v:113880.5-113880.29" - switch \initial - attribute \src "issuer_ls180.v:113880.9-113880.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "issuer_ls180.v:113890.3-113900.6" - process $proc$issuer_ls180.v:113890$4450 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "issuer_ls180.v:113891.5-113891.29" - switch \initial - attribute \src "issuer_ls180.v:113891.9-113891.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "issuer_ls180.v:113901.3-113911.6" - process $proc$issuer_ls180.v:113901$4451 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "issuer_ls180.v:113902.5-113902.29" - switch \initial - attribute \src "issuer_ls180.v:113902.9-113902.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "issuer_ls180.v:113912.3-113922.6" - process $proc$issuer_ls180.v:113912$4452 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "issuer_ls180.v:113913.5-113913.29" - switch \initial - attribute \src "issuer_ls180.v:113913.9-113913.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "issuer_ls180.v:113923.3-113938.6" - process $proc$issuer_ls180.v:113923$4453 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:113924.5-113924.29" - switch \initial - attribute \src "issuer_ls180.v:113924.9-113924.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "issuer_ls180.v:113939.3-113957.6" - process $proc$issuer_ls180.v:113939$4454 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:113940.5-113940.29" - switch \initial - attribute \src "issuer_ls180.v:113940.9-113940.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch \$7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$issuer_ls180.v:113795$4441_Y - connect \$3 $and$issuer_ls180.v:113796$4442_Y - connect \$5 $eq$issuer_ls180.v:113797$4443_Y - connect \$7 $and$issuer_ls180.v:113798$4444_Y -end -attribute \src "issuer_ls180.v:113962.1-114202.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_cr_out" -attribute \generator "nMigen" -module \dec_cr_out - attribute \src "issuer_ls180.v:114116.3-114134.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:114086.3-114104.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:114167.3-114201.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "issuer_ls180.v:114105.3-114115.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:113963.7-113963.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:114135.3-114145.6" - wire $0\move_one[0:0] - attribute \src "issuer_ls180.v:114146.3-114166.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "issuer_ls180.v:114116.3-114134.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:114086.3-114104.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:114167.3-114201.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:114105.3-114115.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:114135.3-114145.6" - wire $1\move_one[0:0] - attribute \src "issuer_ls180.v:114146.3-114166.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:114167.3-114201.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "issuer_ls180.v:114146.3-114166.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "issuer_ls180.v:114167.3-114201.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "issuer_ls180.v:114146.3-114166.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "issuer_ls180.v:114167.3-114201.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "issuer_ls180.v:114079.17-114079.121" - wire $eq$issuer_ls180.v:114079$4456_Y - attribute \src "issuer_ls180.v:114080.17-114080.121" - wire $eq$issuer_ls180.v:114080$4457_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 input 5 \ALU_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 3 \ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 input 7 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 input 6 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 4 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_fxm_ok - attribute \src "issuer_ls180.v:113963.7-113963.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 input 8 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $eq$issuer_ls180.v:114079$4456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \ALU_internal_op - connect \B 7'0110000 - connect \Y $eq$issuer_ls180.v:114079$4456_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $eq$issuer_ls180.v:114080$4457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \ALU_internal_op - connect \B 7'0110000 - connect \Y $eq$issuer_ls180.v:114080$4457_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:114081.15-114085.4" - cell \ppick$136 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "issuer_ls180.v:113963.7-113963.20" - process $proc$issuer_ls180.v:113963$4464 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:114086.3-114104.6" - process $proc$issuer_ls180.v:114086$4458 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:114087.5-114087.29" - switch \initial - attribute \src "issuer_ls180.v:114087.9-114087.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "issuer_ls180.v:114105.3-114115.6" - process $proc$issuer_ls180.v:114105$4459 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:114106.5-114106.29" - switch \initial - attribute \src "issuer_ls180.v:114106.9-114106.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "issuer_ls180.v:114116.3-114134.6" - process $proc$issuer_ls180.v:114116$4460 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:114117.5-114117.29" - switch \initial - attribute \src "issuer_ls180.v:114117.9-114117.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "issuer_ls180.v:114135.3-114145.6" - process $proc$issuer_ls180.v:114135$4461 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "issuer_ls180.v:114136.5-114136.29" - switch \initial - attribute \src "issuer_ls180.v:114136.9-114136.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "issuer_ls180.v:114146.3-114166.6" - process $proc$issuer_ls180.v:114146$4462 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:114147.5-114147.29" - switch \initial - attribute \src "issuer_ls180.v:114147.9-114147.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch \move_one - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \ALU_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "issuer_ls180.v:114167.3-114201.6" - process $proc$issuer_ls180.v:114167$4463 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:114168.5-114168.29" - switch \initial - attribute \src "issuer_ls180.v:114168.9-114168.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch \move_one - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \ppick_en_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \ALU_FXM - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$issuer_ls180.v:114079$4456_Y - connect \$3 $eq$issuer_ls180.v:114080$4457_Y -end -attribute \src "issuer_ls180.v:114206.1-114445.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_cr_out" -attribute \generator "nMigen" -module \dec_cr_out$142 - attribute \src "issuer_ls180.v:114359.3-114377.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:114329.3-114347.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:114410.3-114444.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "issuer_ls180.v:114348.3-114358.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:114207.7-114207.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:114378.3-114388.6" - wire $0\move_one[0:0] - attribute \src "issuer_ls180.v:114389.3-114409.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "issuer_ls180.v:114359.3-114377.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:114329.3-114347.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:114410.3-114444.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:114348.3-114358.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:114378.3-114388.6" - wire $1\move_one[0:0] - attribute \src "issuer_ls180.v:114389.3-114409.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:114410.3-114444.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "issuer_ls180.v:114389.3-114409.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "issuer_ls180.v:114410.3-114444.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "issuer_ls180.v:114389.3-114409.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "issuer_ls180.v:114410.3-114444.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "issuer_ls180.v:114322.17-114322.120" - wire $eq$issuer_ls180.v:114322$4465_Y - attribute \src "issuer_ls180.v:114323.17-114323.120" - wire $eq$issuer_ls180.v:114323$4466_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 input 4 \CR_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 3 \CR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 input 6 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 input 5 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_fxm_ok - attribute \src "issuer_ls180.v:114207.7-114207.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 input 7 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $eq$issuer_ls180.v:114322$4465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \CR_internal_op - connect \B 7'0110000 - connect \Y $eq$issuer_ls180.v:114322$4465_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $eq$issuer_ls180.v:114323$4466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \CR_internal_op - connect \B 7'0110000 - connect \Y $eq$issuer_ls180.v:114323$4466_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:114324.15-114328.4" - cell \ppick$143 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "issuer_ls180.v:114207.7-114207.20" - process $proc$issuer_ls180.v:114207$4473 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:114329.3-114347.6" - process $proc$issuer_ls180.v:114329$4467 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:114330.5-114330.29" - switch \initial - attribute \src "issuer_ls180.v:114330.9-114330.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "issuer_ls180.v:114348.3-114358.6" - process $proc$issuer_ls180.v:114348$4468 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:114349.5-114349.29" - switch \initial - attribute \src "issuer_ls180.v:114349.9-114349.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "issuer_ls180.v:114359.3-114377.6" - process $proc$issuer_ls180.v:114359$4469 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:114360.5-114360.29" - switch \initial - attribute \src "issuer_ls180.v:114360.9-114360.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "issuer_ls180.v:114378.3-114388.6" - process $proc$issuer_ls180.v:114378$4470 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "issuer_ls180.v:114379.5-114379.29" - switch \initial - attribute \src "issuer_ls180.v:114379.9-114379.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "issuer_ls180.v:114389.3-114409.6" - process $proc$issuer_ls180.v:114389$4471 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:114390.5-114390.29" - switch \initial - attribute \src "issuer_ls180.v:114390.9-114390.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch \move_one - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \CR_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "issuer_ls180.v:114410.3-114444.6" - process $proc$issuer_ls180.v:114410$4472 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:114411.5-114411.29" - switch \initial - attribute \src "issuer_ls180.v:114411.9-114411.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch \move_one - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \ppick_en_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \CR_FXM - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$issuer_ls180.v:114322$4465_Y - connect \$3 $eq$issuer_ls180.v:114323$4466_Y -end -attribute \src "issuer_ls180.v:114449.1-114688.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_cr_out" -attribute \generator "nMigen" -module \dec_cr_out$149 - attribute \src "issuer_ls180.v:114602.3-114620.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:114572.3-114590.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:114653.3-114687.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "issuer_ls180.v:114591.3-114601.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:114450.7-114450.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:114621.3-114631.6" - wire $0\move_one[0:0] - attribute \src "issuer_ls180.v:114632.3-114652.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "issuer_ls180.v:114602.3-114620.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:114572.3-114590.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:114653.3-114687.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:114591.3-114601.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:114621.3-114631.6" - wire $1\move_one[0:0] - attribute \src "issuer_ls180.v:114632.3-114652.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:114653.3-114687.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "issuer_ls180.v:114632.3-114652.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "issuer_ls180.v:114653.3-114687.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "issuer_ls180.v:114632.3-114652.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "issuer_ls180.v:114653.3-114687.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "issuer_ls180.v:114565.17-114565.124" - wire $eq$issuer_ls180.v:114565$4474_Y - attribute \src "issuer_ls180.v:114566.17-114566.124" - wire $eq$issuer_ls180.v:114566$4475_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 input 4 \BRANCH_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 3 \BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 input 6 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 input 5 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_fxm_ok - attribute \src "issuer_ls180.v:114450.7-114450.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 input 7 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $eq$issuer_ls180.v:114565$4474 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \BRANCH_internal_op - connect \B 7'0110000 - connect \Y $eq$issuer_ls180.v:114565$4474_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $eq$issuer_ls180.v:114566$4475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \BRANCH_internal_op - connect \B 7'0110000 - connect \Y $eq$issuer_ls180.v:114566$4475_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:114567.15-114571.4" - cell \ppick$150 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "issuer_ls180.v:114450.7-114450.20" - process $proc$issuer_ls180.v:114450$4482 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:114572.3-114590.6" - process $proc$issuer_ls180.v:114572$4476 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:114573.5-114573.29" - switch \initial - attribute \src "issuer_ls180.v:114573.9-114573.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "issuer_ls180.v:114591.3-114601.6" - process $proc$issuer_ls180.v:114591$4477 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:114592.5-114592.29" - switch \initial - attribute \src "issuer_ls180.v:114592.9-114592.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "issuer_ls180.v:114602.3-114620.6" - process $proc$issuer_ls180.v:114602$4478 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:114603.5-114603.29" - switch \initial - attribute \src "issuer_ls180.v:114603.9-114603.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "issuer_ls180.v:114621.3-114631.6" - process $proc$issuer_ls180.v:114621$4479 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "issuer_ls180.v:114622.5-114622.29" - switch \initial - attribute \src "issuer_ls180.v:114622.9-114622.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "issuer_ls180.v:114632.3-114652.6" - process $proc$issuer_ls180.v:114632$4480 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:114633.5-114633.29" - switch \initial - attribute \src "issuer_ls180.v:114633.9-114633.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch \move_one - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \BRANCH_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "issuer_ls180.v:114653.3-114687.6" - process $proc$issuer_ls180.v:114653$4481 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:114654.5-114654.29" - switch \initial - attribute \src "issuer_ls180.v:114654.9-114654.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch \move_one - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \ppick_en_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \BRANCH_FXM - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$issuer_ls180.v:114565$4474_Y - connect \$3 $eq$issuer_ls180.v:114566$4475_Y -end -attribute \src "issuer_ls180.v:114692.1-114932.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_cr_out" -attribute \generator "nMigen" -module \dec_cr_out$157 - attribute \src "issuer_ls180.v:114846.3-114864.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:114816.3-114834.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:114897.3-114931.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "issuer_ls180.v:114835.3-114845.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:114693.7-114693.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:114865.3-114875.6" - wire $0\move_one[0:0] - attribute \src "issuer_ls180.v:114876.3-114896.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "issuer_ls180.v:114846.3-114864.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:114816.3-114834.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:114897.3-114931.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:114835.3-114845.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:114865.3-114875.6" - wire $1\move_one[0:0] - attribute \src "issuer_ls180.v:114876.3-114896.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:114897.3-114931.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "issuer_ls180.v:114876.3-114896.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "issuer_ls180.v:114897.3-114931.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "issuer_ls180.v:114876.3-114896.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "issuer_ls180.v:114897.3-114931.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "issuer_ls180.v:114809.17-114809.125" - wire $eq$issuer_ls180.v:114809$4483_Y - attribute \src "issuer_ls180.v:114810.17-114810.125" - wire $eq$issuer_ls180.v:114810$4484_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 input 5 \LOGICAL_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 3 \LOGICAL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 input 7 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 input 6 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 4 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_fxm_ok - attribute \src "issuer_ls180.v:114693.7-114693.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 input 8 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $eq$issuer_ls180.v:114809$4483 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LOGICAL_internal_op - connect \B 7'0110000 - connect \Y $eq$issuer_ls180.v:114809$4483_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $eq$issuer_ls180.v:114810$4484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LOGICAL_internal_op - connect \B 7'0110000 - connect \Y $eq$issuer_ls180.v:114810$4484_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:114811.15-114815.4" - cell \ppick$158 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "issuer_ls180.v:114693.7-114693.20" - process $proc$issuer_ls180.v:114693$4491 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:114816.3-114834.6" - process $proc$issuer_ls180.v:114816$4485 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:114817.5-114817.29" - switch \initial - attribute \src "issuer_ls180.v:114817.9-114817.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "issuer_ls180.v:114835.3-114845.6" - process $proc$issuer_ls180.v:114835$4486 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:114836.5-114836.29" - switch \initial - attribute \src "issuer_ls180.v:114836.9-114836.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "issuer_ls180.v:114846.3-114864.6" - process $proc$issuer_ls180.v:114846$4487 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:114847.5-114847.29" - switch \initial - attribute \src "issuer_ls180.v:114847.9-114847.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "issuer_ls180.v:114865.3-114875.6" - process $proc$issuer_ls180.v:114865$4488 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "issuer_ls180.v:114866.5-114866.29" - switch \initial - attribute \src "issuer_ls180.v:114866.9-114866.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "issuer_ls180.v:114876.3-114896.6" - process $proc$issuer_ls180.v:114876$4489 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:114877.5-114877.29" - switch \initial - attribute \src "issuer_ls180.v:114877.9-114877.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch \move_one - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \LOGICAL_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "issuer_ls180.v:114897.3-114931.6" - process $proc$issuer_ls180.v:114897$4490 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:114898.5-114898.29" - switch \initial - attribute \src "issuer_ls180.v:114898.9-114898.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch \move_one - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \ppick_en_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \LOGICAL_FXM - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$issuer_ls180.v:114809$4483_Y - connect \$3 $eq$issuer_ls180.v:114810$4484_Y -end -attribute \src "issuer_ls180.v:114936.1-115175.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_cr_out" -attribute \generator "nMigen" -module \dec_cr_out$166 - attribute \src "issuer_ls180.v:115089.3-115107.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:115059.3-115077.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:115140.3-115174.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "issuer_ls180.v:115078.3-115088.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:114937.7-114937.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:115108.3-115118.6" - wire $0\move_one[0:0] - attribute \src "issuer_ls180.v:115119.3-115139.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "issuer_ls180.v:115089.3-115107.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:115059.3-115077.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:115140.3-115174.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:115078.3-115088.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:115108.3-115118.6" - wire $1\move_one[0:0] - attribute \src "issuer_ls180.v:115119.3-115139.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:115140.3-115174.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "issuer_ls180.v:115119.3-115139.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "issuer_ls180.v:115140.3-115174.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "issuer_ls180.v:115119.3-115139.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "issuer_ls180.v:115140.3-115174.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "issuer_ls180.v:115052.17-115052.121" - wire $eq$issuer_ls180.v:115052$4492_Y - attribute \src "issuer_ls180.v:115053.17-115053.121" - wire $eq$issuer_ls180.v:115053$4493_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 input 4 \SPR_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 3 \SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 input 6 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 input 5 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_fxm_ok - attribute \src "issuer_ls180.v:114937.7-114937.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 input 7 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $eq$issuer_ls180.v:115052$4492 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SPR_internal_op - connect \B 7'0110000 - connect \Y $eq$issuer_ls180.v:115052$4492_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $eq$issuer_ls180.v:115053$4493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SPR_internal_op - connect \B 7'0110000 - connect \Y $eq$issuer_ls180.v:115053$4493_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:115054.15-115058.4" - cell \ppick$167 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "issuer_ls180.v:114937.7-114937.20" - process $proc$issuer_ls180.v:114937$4500 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:115059.3-115077.6" - process $proc$issuer_ls180.v:115059$4494 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:115060.5-115060.29" - switch \initial - attribute \src "issuer_ls180.v:115060.9-115060.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "issuer_ls180.v:115078.3-115088.6" - process $proc$issuer_ls180.v:115078$4495 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:115079.5-115079.29" - switch \initial - attribute \src "issuer_ls180.v:115079.9-115079.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "issuer_ls180.v:115089.3-115107.6" - process $proc$issuer_ls180.v:115089$4496 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:115090.5-115090.29" - switch \initial - attribute \src "issuer_ls180.v:115090.9-115090.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "issuer_ls180.v:115108.3-115118.6" - process $proc$issuer_ls180.v:115108$4497 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "issuer_ls180.v:115109.5-115109.29" - switch \initial - attribute \src "issuer_ls180.v:115109.9-115109.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "issuer_ls180.v:115119.3-115139.6" - process $proc$issuer_ls180.v:115119$4498 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:115120.5-115120.29" - switch \initial - attribute \src "issuer_ls180.v:115120.9-115120.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch \move_one - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \SPR_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "issuer_ls180.v:115140.3-115174.6" - process $proc$issuer_ls180.v:115140$4499 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:115141.5-115141.29" - switch \initial - attribute \src "issuer_ls180.v:115141.9-115141.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch \move_one - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \ppick_en_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \SPR_FXM - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$issuer_ls180.v:115052$4492_Y - connect \$3 $eq$issuer_ls180.v:115053$4493_Y -end -attribute \src "issuer_ls180.v:115179.1-115419.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_cr_out" -attribute \generator "nMigen" -module \dec_cr_out$173 - attribute \src "issuer_ls180.v:115333.3-115351.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:115303.3-115321.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:115384.3-115418.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "issuer_ls180.v:115322.3-115332.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:115180.7-115180.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:115352.3-115362.6" - wire $0\move_one[0:0] - attribute \src "issuer_ls180.v:115363.3-115383.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "issuer_ls180.v:115333.3-115351.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:115303.3-115321.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:115384.3-115418.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:115322.3-115332.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:115352.3-115362.6" - wire $1\move_one[0:0] - attribute \src "issuer_ls180.v:115363.3-115383.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:115384.3-115418.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "issuer_ls180.v:115363.3-115383.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "issuer_ls180.v:115384.3-115418.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "issuer_ls180.v:115363.3-115383.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "issuer_ls180.v:115384.3-115418.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "issuer_ls180.v:115296.17-115296.121" - wire $eq$issuer_ls180.v:115296$4501_Y - attribute \src "issuer_ls180.v:115297.17-115297.121" - wire $eq$issuer_ls180.v:115297$4502_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 input 5 \DIV_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 3 \DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 input 7 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 input 6 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 4 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_fxm_ok - attribute \src "issuer_ls180.v:115180.7-115180.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 input 8 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $eq$issuer_ls180.v:115296$4501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \DIV_internal_op - connect \B 7'0110000 - connect \Y $eq$issuer_ls180.v:115296$4501_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $eq$issuer_ls180.v:115297$4502 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \DIV_internal_op - connect \B 7'0110000 - connect \Y $eq$issuer_ls180.v:115297$4502_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:115298.15-115302.4" - cell \ppick$174 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "issuer_ls180.v:115180.7-115180.20" - process $proc$issuer_ls180.v:115180$4509 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:115303.3-115321.6" - process $proc$issuer_ls180.v:115303$4503 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:115304.5-115304.29" - switch \initial - attribute \src "issuer_ls180.v:115304.9-115304.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "issuer_ls180.v:115322.3-115332.6" - process $proc$issuer_ls180.v:115322$4504 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:115323.5-115323.29" - switch \initial - attribute \src "issuer_ls180.v:115323.9-115323.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "issuer_ls180.v:115333.3-115351.6" - process $proc$issuer_ls180.v:115333$4505 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:115334.5-115334.29" - switch \initial - attribute \src "issuer_ls180.v:115334.9-115334.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "issuer_ls180.v:115352.3-115362.6" - process $proc$issuer_ls180.v:115352$4506 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "issuer_ls180.v:115353.5-115353.29" - switch \initial - attribute \src "issuer_ls180.v:115353.9-115353.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "issuer_ls180.v:115363.3-115383.6" - process $proc$issuer_ls180.v:115363$4507 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:115364.5-115364.29" - switch \initial - attribute \src "issuer_ls180.v:115364.9-115364.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch \move_one - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \DIV_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "issuer_ls180.v:115384.3-115418.6" - process $proc$issuer_ls180.v:115384$4508 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:115385.5-115385.29" - switch \initial - attribute \src "issuer_ls180.v:115385.9-115385.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch \move_one - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \ppick_en_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \DIV_FXM - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$issuer_ls180.v:115296$4501_Y - connect \$3 $eq$issuer_ls180.v:115297$4502_Y -end -attribute \src "issuer_ls180.v:115423.1-115663.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_cr_out" -attribute \generator "nMigen" -module \dec_cr_out$182 - attribute \src "issuer_ls180.v:115577.3-115595.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:115547.3-115565.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:115628.3-115662.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "issuer_ls180.v:115566.3-115576.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:115424.7-115424.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:115596.3-115606.6" - wire $0\move_one[0:0] - attribute \src "issuer_ls180.v:115607.3-115627.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "issuer_ls180.v:115577.3-115595.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:115547.3-115565.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:115628.3-115662.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:115566.3-115576.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:115596.3-115606.6" - wire $1\move_one[0:0] - attribute \src "issuer_ls180.v:115607.3-115627.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:115628.3-115662.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "issuer_ls180.v:115607.3-115627.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "issuer_ls180.v:115628.3-115662.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "issuer_ls180.v:115607.3-115627.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "issuer_ls180.v:115628.3-115662.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "issuer_ls180.v:115540.17-115540.121" - wire $eq$issuer_ls180.v:115540$4510_Y - attribute \src "issuer_ls180.v:115541.17-115541.121" - wire $eq$issuer_ls180.v:115541$4511_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 input 5 \MUL_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 3 \MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 input 7 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 input 6 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 4 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_fxm_ok - attribute \src "issuer_ls180.v:115424.7-115424.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 input 8 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $eq$issuer_ls180.v:115540$4510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \MUL_internal_op - connect \B 7'0110000 - connect \Y $eq$issuer_ls180.v:115540$4510_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $eq$issuer_ls180.v:115541$4511 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \MUL_internal_op - connect \B 7'0110000 - connect \Y $eq$issuer_ls180.v:115541$4511_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:115542.15-115546.4" - cell \ppick$183 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "issuer_ls180.v:115424.7-115424.20" - process $proc$issuer_ls180.v:115424$4518 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:115547.3-115565.6" - process $proc$issuer_ls180.v:115547$4512 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:115548.5-115548.29" - switch \initial - attribute \src "issuer_ls180.v:115548.9-115548.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "issuer_ls180.v:115566.3-115576.6" - process $proc$issuer_ls180.v:115566$4513 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:115567.5-115567.29" - switch \initial - attribute \src "issuer_ls180.v:115567.9-115567.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "issuer_ls180.v:115577.3-115595.6" - process $proc$issuer_ls180.v:115577$4514 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:115578.5-115578.29" - switch \initial - attribute \src "issuer_ls180.v:115578.9-115578.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "issuer_ls180.v:115596.3-115606.6" - process $proc$issuer_ls180.v:115596$4515 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "issuer_ls180.v:115597.5-115597.29" - switch \initial - attribute \src "issuer_ls180.v:115597.9-115597.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "issuer_ls180.v:115607.3-115627.6" - process $proc$issuer_ls180.v:115607$4516 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:115608.5-115608.29" - switch \initial - attribute \src "issuer_ls180.v:115608.9-115608.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch \move_one - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \MUL_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "issuer_ls180.v:115628.3-115662.6" - process $proc$issuer_ls180.v:115628$4517 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:115629.5-115629.29" - switch \initial - attribute \src "issuer_ls180.v:115629.9-115629.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch \move_one - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \ppick_en_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \MUL_FXM - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$issuer_ls180.v:115540$4510_Y - connect \$3 $eq$issuer_ls180.v:115541$4511_Y -end -attribute \src "issuer_ls180.v:115667.1-115907.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_cr_out" -attribute \generator "nMigen" -module \dec_cr_out$190 - attribute \src "issuer_ls180.v:115821.3-115839.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:115791.3-115809.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:115872.3-115906.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "issuer_ls180.v:115810.3-115820.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:115668.7-115668.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:115840.3-115850.6" - wire $0\move_one[0:0] - attribute \src "issuer_ls180.v:115851.3-115871.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "issuer_ls180.v:115821.3-115839.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:115791.3-115809.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:115872.3-115906.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:115810.3-115820.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:115840.3-115850.6" - wire $1\move_one[0:0] - attribute \src "issuer_ls180.v:115851.3-115871.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:115872.3-115906.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "issuer_ls180.v:115851.3-115871.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "issuer_ls180.v:115872.3-115906.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "issuer_ls180.v:115851.3-115871.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "issuer_ls180.v:115872.3-115906.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "issuer_ls180.v:115784.17-115784.127" - wire $eq$issuer_ls180.v:115784$4519_Y - attribute \src "issuer_ls180.v:115785.17-115785.127" - wire $eq$issuer_ls180.v:115785$4520_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 input 5 \SHIFT_ROT_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 3 \SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 input 7 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 input 6 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 4 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_fxm_ok - attribute \src "issuer_ls180.v:115668.7-115668.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 input 8 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $eq$issuer_ls180.v:115784$4519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SHIFT_ROT_internal_op - connect \B 7'0110000 - connect \Y $eq$issuer_ls180.v:115784$4519_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $eq$issuer_ls180.v:115785$4520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SHIFT_ROT_internal_op - connect \B 7'0110000 - connect \Y $eq$issuer_ls180.v:115785$4520_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:115786.15-115790.4" - cell \ppick$191 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "issuer_ls180.v:115668.7-115668.20" - process $proc$issuer_ls180.v:115668$4527 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:115791.3-115809.6" - process $proc$issuer_ls180.v:115791$4521 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:115792.5-115792.29" - switch \initial - attribute \src "issuer_ls180.v:115792.9-115792.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "issuer_ls180.v:115810.3-115820.6" - process $proc$issuer_ls180.v:115810$4522 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:115811.5-115811.29" - switch \initial - attribute \src "issuer_ls180.v:115811.9-115811.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "issuer_ls180.v:115821.3-115839.6" - process $proc$issuer_ls180.v:115821$4523 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:115822.5-115822.29" - switch \initial - attribute \src "issuer_ls180.v:115822.9-115822.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "issuer_ls180.v:115840.3-115850.6" - process $proc$issuer_ls180.v:115840$4524 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "issuer_ls180.v:115841.5-115841.29" - switch \initial - attribute \src "issuer_ls180.v:115841.9-115841.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "issuer_ls180.v:115851.3-115871.6" - process $proc$issuer_ls180.v:115851$4525 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:115852.5-115852.29" - switch \initial - attribute \src "issuer_ls180.v:115852.9-115852.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch \move_one - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \SHIFT_ROT_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "issuer_ls180.v:115872.3-115906.6" - process $proc$issuer_ls180.v:115872$4526 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:115873.5-115873.29" - switch \initial - attribute \src "issuer_ls180.v:115873.9-115873.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch \move_one - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \ppick_en_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \SHIFT_ROT_FXM - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$issuer_ls180.v:115784$4519_Y - connect \$3 $eq$issuer_ls180.v:115785$4520_Y -end -attribute \src "issuer_ls180.v:115911.1-116150.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_cr_out" -attribute \generator "nMigen" -module \dec_cr_out$198 - attribute \src "issuer_ls180.v:116064.3-116082.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:116034.3-116052.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:116115.3-116149.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "issuer_ls180.v:116053.3-116063.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:115912.7-115912.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:116083.3-116093.6" - wire $0\move_one[0:0] - attribute \src "issuer_ls180.v:116094.3-116114.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "issuer_ls180.v:116064.3-116082.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:116034.3-116052.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:116115.3-116149.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:116053.3-116063.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:116083.3-116093.6" - wire $1\move_one[0:0] - attribute \src "issuer_ls180.v:116094.3-116114.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:116115.3-116149.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "issuer_ls180.v:116094.3-116114.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "issuer_ls180.v:116115.3-116149.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "issuer_ls180.v:116094.3-116114.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "issuer_ls180.v:116115.3-116149.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "issuer_ls180.v:116027.17-116027.122" - wire $eq$issuer_ls180.v:116027$4528_Y - attribute \src "issuer_ls180.v:116028.17-116028.122" - wire $eq$issuer_ls180.v:116028$4529_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 input 4 \LDST_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 3 \LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 input 6 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 input 5 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_fxm_ok - attribute \src "issuer_ls180.v:115912.7-115912.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 input 7 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $eq$issuer_ls180.v:116027$4528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LDST_internal_op - connect \B 7'0110000 - connect \Y $eq$issuer_ls180.v:116027$4528_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $eq$issuer_ls180.v:116028$4529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LDST_internal_op - connect \B 7'0110000 - connect \Y $eq$issuer_ls180.v:116028$4529_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:116029.15-116033.4" - cell \ppick$199 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "issuer_ls180.v:115912.7-115912.20" - process $proc$issuer_ls180.v:115912$4536 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:116034.3-116052.6" - process $proc$issuer_ls180.v:116034$4530 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:116035.5-116035.29" - switch \initial - attribute \src "issuer_ls180.v:116035.9-116035.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "issuer_ls180.v:116053.3-116063.6" - process $proc$issuer_ls180.v:116053$4531 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:116054.5-116054.29" - switch \initial - attribute \src "issuer_ls180.v:116054.9-116054.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "issuer_ls180.v:116064.3-116082.6" - process $proc$issuer_ls180.v:116064$4532 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:116065.5-116065.29" - switch \initial - attribute \src "issuer_ls180.v:116065.9-116065.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "issuer_ls180.v:116083.3-116093.6" - process $proc$issuer_ls180.v:116083$4533 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "issuer_ls180.v:116084.5-116084.29" - switch \initial - attribute \src "issuer_ls180.v:116084.9-116084.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "issuer_ls180.v:116094.3-116114.6" - process $proc$issuer_ls180.v:116094$4534 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:116095.5-116095.29" - switch \initial - attribute \src "issuer_ls180.v:116095.9-116095.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch \move_one - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \LDST_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "issuer_ls180.v:116115.3-116149.6" - process $proc$issuer_ls180.v:116115$4535 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:116116.5-116116.29" - switch \initial - attribute \src "issuer_ls180.v:116116.9-116116.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch \move_one - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \ppick_en_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \LDST_FXM - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$issuer_ls180.v:116027$4528_Y - connect \$3 $eq$issuer_ls180.v:116028$4529_Y -end -attribute \src "issuer_ls180.v:116154.1-116397.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_out" -attribute \generator "nMigen" -module \dec_cr_out$207 - attribute \src "issuer_ls180.v:116311.3-116329.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:116281.3-116299.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:116362.3-116396.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "issuer_ls180.v:116300.3-116310.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:116155.7-116155.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:116330.3-116340.6" - wire $0\move_one[0:0] - attribute \src "issuer_ls180.v:116341.3-116361.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "issuer_ls180.v:116311.3-116329.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:116281.3-116299.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:116362.3-116396.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:116300.3-116310.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:116330.3-116340.6" - wire $1\move_one[0:0] - attribute \src "issuer_ls180.v:116341.3-116361.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:116362.3-116396.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "issuer_ls180.v:116341.3-116361.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "issuer_ls180.v:116362.3-116396.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "issuer_ls180.v:116341.3-116361.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "issuer_ls180.v:116362.3-116396.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "issuer_ls180.v:116274.17-116274.117" - wire $eq$issuer_ls180.v:116274$4537_Y - attribute \src "issuer_ls180.v:116275.17-116275.117" - wire $eq$issuer_ls180.v:116275$4538_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 input 8 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 input 10 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 input 9 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 6 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 7 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 output 4 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 5 \cr_fxm_ok - attribute \src "issuer_ls180.v:116155.7-116155.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 input 11 \insn_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 3 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $eq$issuer_ls180.v:116274$4537 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110000 - connect \Y $eq$issuer_ls180.v:116274$4537_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $eq$issuer_ls180.v:116275$4538 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110000 - connect \Y $eq$issuer_ls180.v:116275$4538_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:116276.15-116280.4" - cell \ppick$208 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "issuer_ls180.v:116155.7-116155.20" - process $proc$issuer_ls180.v:116155$4545 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:116281.3-116299.6" - process $proc$issuer_ls180.v:116281$4539 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "issuer_ls180.v:116282.5-116282.29" - switch \initial - attribute \src "issuer_ls180.v:116282.9-116282.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "issuer_ls180.v:116300.3-116310.6" - process $proc$issuer_ls180.v:116300$4540 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "issuer_ls180.v:116301.5-116301.29" - switch \initial - attribute \src "issuer_ls180.v:116301.9-116301.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "issuer_ls180.v:116311.3-116329.6" - process $proc$issuer_ls180.v:116311$4541 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "issuer_ls180.v:116312.5-116312.29" - switch \initial - attribute \src "issuer_ls180.v:116312.9-116312.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "issuer_ls180.v:116330.3-116340.6" - process $proc$issuer_ls180.v:116330$4542 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "issuer_ls180.v:116331.5-116331.29" - switch \initial - attribute \src "issuer_ls180.v:116331.9-116331.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "issuer_ls180.v:116341.3-116361.6" - process $proc$issuer_ls180.v:116341$4543 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "issuer_ls180.v:116342.5-116342.29" - switch \initial - attribute \src "issuer_ls180.v:116342.9-116342.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch \move_one - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "issuer_ls180.v:116362.3-116396.6" - process $proc$issuer_ls180.v:116362$4544 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "issuer_ls180.v:116363.5-116363.29" - switch \initial - attribute \src "issuer_ls180.v:116363.9-116363.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch \move_one - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \ppick_en_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \FXM - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$issuer_ls180.v:116274$4537_Y - connect \$3 $eq$issuer_ls180.v:116275$4538_Y -end -attribute \src "issuer_ls180.v:116401.1-116878.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec_o" -attribute \generator "nMigen" -module \dec_o - attribute \src "issuer_ls180.v:116839.3-116877.6" - wire width 3 $0\fast_o[2:0] - attribute \src "issuer_ls180.v:116839.3-116877.6" - wire $0\fast_o_ok[0:0] - attribute \src "issuer_ls180.v:116402.7-116402.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:116765.3-116779.6" - wire width 5 $0\reg_o[4:0] - attribute \src "issuer_ls180.v:116780.3-116794.6" - wire $0\reg_o_ok[0:0] - attribute \src "issuer_ls180.v:116795.3-116805.6" - wire width 10 $0\spr[9:0] - attribute \src "issuer_ls180.v:116822.3-116838.6" - wire width 10 $0\spr_o[9:0] - attribute \src "issuer_ls180.v:116822.3-116838.6" - wire $0\spr_o_ok[0:0] - attribute \src "issuer_ls180.v:116806.3-116821.6" - wire width 10 $0\sprmap_spr_i[9:0] - attribute \src "issuer_ls180.v:116839.3-116877.6" - wire width 3 $1\fast_o[2:0] - attribute \src "issuer_ls180.v:116839.3-116877.6" - wire $1\fast_o_ok[0:0] - attribute \src "issuer_ls180.v:116765.3-116779.6" - wire width 5 $1\reg_o[4:0] - attribute \src "issuer_ls180.v:116780.3-116794.6" - wire $1\reg_o_ok[0:0] - attribute \src "issuer_ls180.v:116795.3-116805.6" - wire width 10 $1\spr[9:0] - attribute \src "issuer_ls180.v:116822.3-116838.6" - wire width 10 $1\spr_o[9:0] - attribute \src "issuer_ls180.v:116822.3-116838.6" - wire $1\spr_o_ok[0:0] - attribute \src "issuer_ls180.v:116806.3-116821.6" - wire width 10 $1\sprmap_spr_i[9:0] - attribute \src "issuer_ls180.v:116839.3-116877.6" - wire width 3 $2\fast_o[2:0] - attribute \src "issuer_ls180.v:116839.3-116877.6" - wire $2\fast_o_ok[0:0] - attribute \src "issuer_ls180.v:116822.3-116838.6" - wire width 10 $2\spr_o[9:0] - attribute \src "issuer_ls180.v:116822.3-116838.6" - wire $2\spr_o_ok[0:0] - attribute \src "issuer_ls180.v:116806.3-116821.6" - wire width 10 $2\sprmap_spr_i[9:0] - attribute \src "issuer_ls180.v:116839.3-116877.6" - wire width 3 $3\fast_o[2:0] - attribute \src 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$eq$issuer_ls180.v:116756$4548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110001 - connect \Y $eq$issuer_ls180.v:116756$4548_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" - cell $not $not$issuer_ls180.v:116757$4549 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \BO [2] - connect \Y $not$issuer_ls180.v:116757$4549_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:116758.16-116764.4" - cell \sprmap$209 \sprmap - connect \fast_o \sprmap_fast_o - connect \fast_o_ok \sprmap_fast_o_ok - connect \spr_i \sprmap_spr_i - connect \spr_o \sprmap_spr_o - connect \spr_o_ok \sprmap_spr_o_ok - end - attribute \src "issuer_ls180.v:116402.7-116402.20" - process $proc$issuer_ls180.v:116402$4556 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:116765.3-116779.6" - process $proc$issuer_ls180.v:116765$4550 - assign { } { } - assign { } { } - assign $0\reg_o[4:0] $1\reg_o[4:0] - attribute \src "issuer_ls180.v:116766.5-116766.29" - switch \initial - attribute \src "issuer_ls180.v:116766.9-116766.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\reg_o[4:0] \RT - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\reg_o[4:0] \RA - case - assign $1\reg_o[4:0] 5'00000 - end - sync always - update \reg_o $0\reg_o[4:0] - end - attribute \src "issuer_ls180.v:116780.3-116794.6" - process $proc$issuer_ls180.v:116780$4551 - assign { } { } - assign { } { } - assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] - attribute \src "issuer_ls180.v:116781.5-116781.29" - switch \initial - attribute \src "issuer_ls180.v:116781.9-116781.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\reg_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\reg_o_ok[0:0] 1'1 - case - assign $1\reg_o_ok[0:0] 1'0 - end - sync always - update \reg_o_ok $0\reg_o_ok[0:0] - end - attribute \src "issuer_ls180.v:116795.3-116805.6" - process $proc$issuer_ls180.v:116795$4552 - assign { } { } - assign { } { } - assign $0\spr[9:0] $1\spr[9:0] - attribute \src "issuer_ls180.v:116796.5-116796.29" - switch \initial - attribute \src "issuer_ls180.v:116796.9-116796.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } - case - assign $1\spr[9:0] 10'0000000000 - end - sync always - update \spr $0\spr[9:0] - end - attribute \src "issuer_ls180.v:116806.3-116821.6" - process $proc$issuer_ls180.v:116806$4553 - assign { } { } - assign { } { } - assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] - attribute \src "issuer_ls180.v:116807.5-116807.29" - switch \initial - attribute \src "issuer_ls180.v:116807.9-116807.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\sprmap_spr_i[9:0] $2\sprmap_spr_i[9:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\sprmap_spr_i[9:0] \spr - case - assign $2\sprmap_spr_i[9:0] 10'0000000000 - end - case - assign $1\sprmap_spr_i[9:0] 10'0000000000 - end - sync always - update \sprmap_spr_i $0\sprmap_spr_i[9:0] - end - attribute \src "issuer_ls180.v:116822.3-116838.6" - process $proc$issuer_ls180.v:116822$4554 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\spr_o[9:0] $1\spr_o[9:0] - assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "issuer_ls180.v:116823.5-116823.29" - switch \initial - attribute \src "issuer_ls180.v:116823.9-116823.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'11 - assign { } { } - assign { } { } - assign $1\spr_o[9:0] $2\spr_o[9:0] - assign $1\spr_o_ok[0:0] $2\spr_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\spr_o_ok[0:0] $2\spr_o[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } - case - assign $2\spr_o[9:0] 10'0000000000 - assign $2\spr_o_ok[0:0] 1'0 - end - case - assign $1\spr_o[9:0] 10'0000000000 - assign $1\spr_o_ok[0:0] 1'0 - end - sync always - update \spr_o $0\spr_o[9:0] - update \spr_o_ok $0\spr_o_ok[0:0] - end - attribute \src "issuer_ls180.v:116839.3-116877.6" - process $proc$issuer_ls180.v:116839$4555 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fast_o[2:0] $3\fast_o[2:0] - assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0] - attribute \src "issuer_ls180.v:116840.5-116840.29" - switch \initial - attribute \src "issuer_ls180.v:116840.9-116840.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'11 - assign { } { } - assign { } { } - assign $1\fast_o[2:0] $2\fast_o[2:0] - assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - switch \$5 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\fast_o_ok[0:0] $2\fast_o[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } - case - assign $2\fast_o[2:0] 3'000 - assign $2\fast_o_ok[0:0] 1'0 - end - case - assign $1\fast_o[2:0] 3'000 - assign $1\fast_o_ok[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:337" - switch \internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000111 , 7'0001000 - assign { } { } - assign { } { } - assign $3\fast_o[2:0] $4\fast_o[2:0] - assign $3\fast_o_ok[0:0] $4\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" - switch \$7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $4\fast_o[2:0] 3'000 - assign $4\fast_o_ok[0:0] 1'1 - case - assign $4\fast_o[2:0] $1\fast_o[2:0] - assign $4\fast_o_ok[0:0] $1\fast_o_ok[0:0] - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000110 - assign { } { } - assign { } { } - assign $3\fast_o[2:0] 3'011 - assign $3\fast_o_ok[0:0] 1'1 - case - assign $3\fast_o[2:0] $1\fast_o[2:0] - assign $3\fast_o_ok[0:0] $1\fast_o_ok[0:0] - end - sync always - update \fast_o $0\fast_o[2:0] - update \fast_o_ok $0\fast_o_ok[0:0] - end - connect \$1 $eq$issuer_ls180.v:116754$4546_Y - connect \$3 $eq$issuer_ls180.v:116755$4547_Y - connect \$5 $eq$issuer_ls180.v:116756$4548_Y - connect \$7 $not$issuer_ls180.v:116757$4549_Y -end -attribute \src "issuer_ls180.v:116882.1-117043.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec_o2" -attribute \generator "nMigen" -module \dec_o2 - attribute \src "issuer_ls180.v:117003.3-117022.6" - wire width 3 $0\fast_o[2:0] - attribute \src "issuer_ls180.v:117023.3-117042.6" - wire $0\fast_o_ok[0:0] - attribute \src "issuer_ls180.v:116883.7-116883.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:116989.3-117002.6" - wire width 5 $0\reg_o[4:0] - attribute \src "issuer_ls180.v:116989.3-117002.6" - wire $0\reg_o_ok[0:0] - attribute \src "issuer_ls180.v:117003.3-117022.6" - wire width 3 $1\fast_o[2:0] - attribute \src "issuer_ls180.v:117023.3-117042.6" - wire $1\fast_o_ok[0:0] - attribute \src "issuer_ls180.v:116989.3-117002.6" - wire width 5 $1\reg_o[4:0] - attribute \src "issuer_ls180.v:116989.3-117002.6" - wire $1\reg_o_ok[0:0] - attribute \src "issuer_ls180.v:117003.3-117022.6" - wire width 3 $2\fast_o[2:0] - attribute \src "issuer_ls180.v:117023.3-117042.6" - wire $2\fast_o_ok[0:0] - attribute \src "issuer_ls180.v:116987.17-116987.108" - wire $eq$issuer_ls180.v:116987$4557_Y - attribute \src "issuer_ls180.v:116988.17-116988.100" - wire width 6 $extend$issuer_ls180.v:116988$4558_Y - attribute \src "issuer_ls180.v:116988.17-116988.100" - wire width 6 $pos$issuer_ls180.v:116988$4559_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 6 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 input 7 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 4 \fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 5 \fast_o_ok - attribute \src "issuer_ls180.v:116883.7-116883.15" - wire \initial - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 8 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363" - wire input 1 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 output 2 \reg_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \reg_o_ok - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 input 6 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" - cell $eq $eq$issuer_ls180.v:116987$4557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \upd - connect \B 2'01 - connect \Y $eq$issuer_ls180.v:116987$4557_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$issuer_ls180.v:116988$4558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 6 - connect \A \RA - connect \Y $extend$issuer_ls180.v:116988$4558_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$issuer_ls180.v:116988$4559 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $extend$issuer_ls180.v:116988$4558_Y - connect \Y $pos$issuer_ls180.v:116988$4559_Y - end - attribute \src "issuer_ls180.v:116883.7-116883.20" - process $proc$issuer_ls180.v:116883$4563 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:116989.3-117002.6" - process $proc$issuer_ls180.v:116989$4560 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg_o[4:0] $1\reg_o[4:0] - assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] - attribute \src "issuer_ls180.v:116990.5-116990.29" - switch \initial - attribute \src "issuer_ls180.v:116990.9-116990.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\reg_o[4:0] \$3 [4:0] - assign $1\reg_o_ok[0:0] 1'1 - case - assign $1\reg_o[4:0] 5'00000 - assign $1\reg_o_ok[0:0] 1'0 - end - sync always - update \reg_o $0\reg_o[4:0] - update \reg_o_ok $0\reg_o_ok[0:0] - end - attribute \src "issuer_ls180.v:117003.3-117022.6" - process $proc$issuer_ls180.v:117003$4561 - assign { } { } - assign { } { } - assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "issuer_ls180.v:117004.5-117004.29" - switch \initial - attribute \src "issuer_ls180.v:117004.9-117004.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:380" - switch \internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000111 , 7'0000110 , 7'0001000 - assign { } { } - assign $1\fast_o[2:0] $2\fast_o[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" - switch \lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fast_o[2:0] 3'001 - case - assign $2\fast_o[2:0] 3'000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000110 - assign { } { } - assign $1\fast_o[2:0] 3'100 - case - assign $1\fast_o[2:0] 3'000 - end - sync always - update \fast_o $0\fast_o[2:0] - end - attribute \src "issuer_ls180.v:117023.3-117042.6" - process $proc$issuer_ls180.v:117023$4562 - assign { } { } - assign { } { } - assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "issuer_ls180.v:117024.5-117024.29" - switch \initial - attribute \src "issuer_ls180.v:117024.9-117024.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:380" - switch \internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000111 , 7'0000110 , 7'0001000 - assign { } { } - assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" - switch \lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fast_o_ok[0:0] 1'1 - case - assign $2\fast_o_ok[0:0] 1'0 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000110 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - case - assign $1\fast_o_ok[0:0] 1'0 - end - sync always - update \fast_o_ok $0\fast_o_ok[0:0] - end - connect \$1 $eq$issuer_ls180.v:116987$4557_Y - connect \$3 $pos$issuer_ls180.v:116988$4559_Y -end -attribute \src "issuer_ls180.v:117047.1-117181.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_oe" -attribute \generator "nMigen" -module \dec_oe - attribute \src "issuer_ls180.v:117048.7-117048.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:117139.3-117159.6" - wire $0\oe[0:0] - attribute \src "issuer_ls180.v:117160.3-117180.6" - wire $0\oe_ok[0:0] - attribute \src "issuer_ls180.v:117139.3-117159.6" - wire $1\oe[0:0] - attribute \src "issuer_ls180.v:117160.3-117180.6" - wire $1\oe_ok[0:0] - attribute \src "issuer_ls180.v:117139.3-117159.6" - wire $2\oe[0:0] - attribute \src "issuer_ls180.v:117160.3-117180.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire input 4 \ALU_OE - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 1 \ALU_internal_op - attribute \src "issuer_ls180.v:117048.7-117048.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 input 5 \sel_in - attribute \src "issuer_ls180.v:117048.7-117048.20" - process $proc$issuer_ls180.v:117048$4566 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:117139.3-117159.6" - process $proc$issuer_ls180.v:117139$4564 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "issuer_ls180.v:117140.5-117140.29" - switch \initial - attribute \src "issuer_ls180.v:117140.9-117140.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \ALU_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \ALU_OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "issuer_ls180.v:117160.3-117180.6" - process $proc$issuer_ls180.v:117160$4565 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "issuer_ls180.v:117161.5-117161.29" - switch \initial - attribute \src "issuer_ls180.v:117161.9-117161.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \ALU_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "issuer_ls180.v:117185.1-117317.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_oe" -attribute \generator "nMigen" -module \dec_oe$139 - attribute \src "issuer_ls180.v:117186.7-117186.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:117275.3-117295.6" - wire $0\oe[0:0] - attribute \src "issuer_ls180.v:117296.3-117316.6" - wire $0\oe_ok[0:0] - attribute \src "issuer_ls180.v:117275.3-117295.6" - wire $1\oe[0:0] - attribute \src "issuer_ls180.v:117296.3-117316.6" - wire $1\oe_ok[0:0] - attribute \src "issuer_ls180.v:117275.3-117295.6" - wire $2\oe[0:0] - attribute \src "issuer_ls180.v:117296.3-117316.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire input 2 \CR_OE - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 1 \CR_internal_op - attribute \src "issuer_ls180.v:117186.7-117186.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 input 3 \sel_in - attribute \src "issuer_ls180.v:117186.7-117186.20" - process $proc$issuer_ls180.v:117186$4569 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:117275.3-117295.6" - process $proc$issuer_ls180.v:117275$4567 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "issuer_ls180.v:117276.5-117276.29" - switch \initial - attribute \src "issuer_ls180.v:117276.9-117276.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \CR_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \CR_OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "issuer_ls180.v:117296.3-117316.6" - process $proc$issuer_ls180.v:117296$4568 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "issuer_ls180.v:117297.5-117297.29" - switch \initial - attribute \src "issuer_ls180.v:117297.9-117297.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \CR_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "issuer_ls180.v:117321.1-117453.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_oe" -attribute \generator "nMigen" -module \dec_oe$146 - attribute \src "issuer_ls180.v:117322.7-117322.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:117411.3-117431.6" - wire $0\oe[0:0] - attribute \src "issuer_ls180.v:117432.3-117452.6" - wire $0\oe_ok[0:0] - attribute \src "issuer_ls180.v:117411.3-117431.6" - wire $1\oe[0:0] - attribute \src "issuer_ls180.v:117432.3-117452.6" - wire $1\oe_ok[0:0] - attribute \src "issuer_ls180.v:117411.3-117431.6" - wire $2\oe[0:0] - attribute \src "issuer_ls180.v:117432.3-117452.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire input 2 \BRANCH_OE - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 1 \BRANCH_internal_op - attribute \src "issuer_ls180.v:117322.7-117322.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 input 3 \sel_in - attribute \src "issuer_ls180.v:117322.7-117322.20" - process $proc$issuer_ls180.v:117322$4572 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:117411.3-117431.6" - process $proc$issuer_ls180.v:117411$4570 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "issuer_ls180.v:117412.5-117412.29" - switch \initial - attribute \src "issuer_ls180.v:117412.9-117412.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \BRANCH_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \BRANCH_OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "issuer_ls180.v:117432.3-117452.6" - process $proc$issuer_ls180.v:117432$4571 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "issuer_ls180.v:117433.5-117433.29" - switch \initial - attribute \src "issuer_ls180.v:117433.9-117433.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \BRANCH_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "issuer_ls180.v:117457.1-117591.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_oe" -attribute \generator "nMigen" -module \dec_oe$154 - attribute \src "issuer_ls180.v:117458.7-117458.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:117549.3-117569.6" - wire $0\oe[0:0] - attribute \src "issuer_ls180.v:117570.3-117590.6" - wire $0\oe_ok[0:0] - attribute \src "issuer_ls180.v:117549.3-117569.6" - wire $1\oe[0:0] - attribute \src "issuer_ls180.v:117570.3-117590.6" - wire $1\oe_ok[0:0] - attribute \src "issuer_ls180.v:117549.3-117569.6" - wire $2\oe[0:0] - attribute \src "issuer_ls180.v:117570.3-117590.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire input 4 \LOGICAL_OE - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 1 \LOGICAL_internal_op - attribute \src "issuer_ls180.v:117458.7-117458.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 input 5 \sel_in - attribute \src "issuer_ls180.v:117458.7-117458.20" - process $proc$issuer_ls180.v:117458$4575 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:117549.3-117569.6" - process $proc$issuer_ls180.v:117549$4573 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "issuer_ls180.v:117550.5-117550.29" - switch \initial - attribute \src "issuer_ls180.v:117550.9-117550.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \LOGICAL_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \LOGICAL_OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "issuer_ls180.v:117570.3-117590.6" - process $proc$issuer_ls180.v:117570$4574 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "issuer_ls180.v:117571.5-117571.29" - switch \initial - attribute \src "issuer_ls180.v:117571.9-117571.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \LOGICAL_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "issuer_ls180.v:117595.1-117727.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_oe" -attribute \generator "nMigen" -module \dec_oe$163 - attribute \src "issuer_ls180.v:117596.7-117596.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:117685.3-117705.6" - wire $0\oe[0:0] - attribute \src "issuer_ls180.v:117706.3-117726.6" - wire $0\oe_ok[0:0] - attribute \src "issuer_ls180.v:117685.3-117705.6" - wire $1\oe[0:0] - attribute \src "issuer_ls180.v:117706.3-117726.6" - wire $1\oe_ok[0:0] - attribute \src "issuer_ls180.v:117685.3-117705.6" - wire $2\oe[0:0] - attribute \src "issuer_ls180.v:117706.3-117726.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire input 2 \SPR_OE - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 1 \SPR_internal_op - attribute \src "issuer_ls180.v:117596.7-117596.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 input 3 \sel_in - attribute \src "issuer_ls180.v:117596.7-117596.20" - process $proc$issuer_ls180.v:117596$4578 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:117685.3-117705.6" - process $proc$issuer_ls180.v:117685$4576 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "issuer_ls180.v:117686.5-117686.29" - switch \initial - attribute \src "issuer_ls180.v:117686.9-117686.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \SPR_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \SPR_OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "issuer_ls180.v:117706.3-117726.6" - process $proc$issuer_ls180.v:117706$4577 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "issuer_ls180.v:117707.5-117707.29" - switch \initial - attribute \src "issuer_ls180.v:117707.9-117707.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \SPR_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "issuer_ls180.v:117731.1-117865.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_oe" -attribute \generator "nMigen" -module \dec_oe$170 - attribute \src "issuer_ls180.v:117732.7-117732.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:117823.3-117843.6" - wire $0\oe[0:0] - attribute \src "issuer_ls180.v:117844.3-117864.6" - wire $0\oe_ok[0:0] - attribute \src "issuer_ls180.v:117823.3-117843.6" - wire $1\oe[0:0] - attribute \src "issuer_ls180.v:117844.3-117864.6" - wire $1\oe_ok[0:0] - attribute \src "issuer_ls180.v:117823.3-117843.6" - wire $2\oe[0:0] - attribute \src "issuer_ls180.v:117844.3-117864.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire input 4 \DIV_OE - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 1 \DIV_internal_op - attribute \src "issuer_ls180.v:117732.7-117732.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 input 5 \sel_in - attribute \src "issuer_ls180.v:117732.7-117732.20" - process $proc$issuer_ls180.v:117732$4581 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:117823.3-117843.6" - process $proc$issuer_ls180.v:117823$4579 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "issuer_ls180.v:117824.5-117824.29" - switch \initial - attribute \src "issuer_ls180.v:117824.9-117824.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \DIV_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \DIV_OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "issuer_ls180.v:117844.3-117864.6" - process $proc$issuer_ls180.v:117844$4580 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "issuer_ls180.v:117845.5-117845.29" - switch \initial - attribute \src "issuer_ls180.v:117845.9-117845.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \DIV_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "issuer_ls180.v:117869.1-118003.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_oe" -attribute \generator "nMigen" -module \dec_oe$179 - attribute \src "issuer_ls180.v:117870.7-117870.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:117961.3-117981.6" - wire $0\oe[0:0] - attribute \src "issuer_ls180.v:117982.3-118002.6" - wire $0\oe_ok[0:0] - attribute \src "issuer_ls180.v:117961.3-117981.6" - wire $1\oe[0:0] - attribute \src "issuer_ls180.v:117982.3-118002.6" - wire $1\oe_ok[0:0] - attribute \src "issuer_ls180.v:117961.3-117981.6" - wire $2\oe[0:0] - attribute \src "issuer_ls180.v:117982.3-118002.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire input 4 \MUL_OE - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 1 \MUL_internal_op - attribute \src "issuer_ls180.v:117870.7-117870.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 input 5 \sel_in - attribute \src "issuer_ls180.v:117870.7-117870.20" - process $proc$issuer_ls180.v:117870$4584 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:117961.3-117981.6" - process $proc$issuer_ls180.v:117961$4582 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "issuer_ls180.v:117962.5-117962.29" - switch \initial - attribute \src "issuer_ls180.v:117962.9-117962.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \MUL_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \MUL_OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "issuer_ls180.v:117982.3-118002.6" - process $proc$issuer_ls180.v:117982$4583 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "issuer_ls180.v:117983.5-117983.29" - switch \initial - attribute \src "issuer_ls180.v:117983.9-117983.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \MUL_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "issuer_ls180.v:118007.1-118141.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_oe" -attribute \generator "nMigen" -module \dec_oe$187 - attribute \src "issuer_ls180.v:118008.7-118008.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:118099.3-118119.6" - wire $0\oe[0:0] - attribute \src "issuer_ls180.v:118120.3-118140.6" - wire $0\oe_ok[0:0] - attribute \src "issuer_ls180.v:118099.3-118119.6" - wire $1\oe[0:0] - attribute \src "issuer_ls180.v:118120.3-118140.6" - wire $1\oe_ok[0:0] - attribute \src "issuer_ls180.v:118099.3-118119.6" - wire $2\oe[0:0] - attribute \src "issuer_ls180.v:118120.3-118140.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire input 4 \SHIFT_ROT_OE - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 1 \SHIFT_ROT_internal_op - attribute \src "issuer_ls180.v:118008.7-118008.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 input 5 \sel_in - attribute \src "issuer_ls180.v:118008.7-118008.20" - process $proc$issuer_ls180.v:118008$4587 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:118099.3-118119.6" - process $proc$issuer_ls180.v:118099$4585 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "issuer_ls180.v:118100.5-118100.29" - switch \initial - attribute \src "issuer_ls180.v:118100.9-118100.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \SHIFT_ROT_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \SHIFT_ROT_OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "issuer_ls180.v:118120.3-118140.6" - process $proc$issuer_ls180.v:118120$4586 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "issuer_ls180.v:118121.5-118121.29" - switch \initial - attribute \src "issuer_ls180.v:118121.9-118121.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \SHIFT_ROT_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "issuer_ls180.v:118145.1-118279.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_oe" -attribute \generator "nMigen" -module \dec_oe$195 - attribute \src "issuer_ls180.v:118146.7-118146.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:118237.3-118257.6" - wire $0\oe[0:0] - attribute \src "issuer_ls180.v:118258.3-118278.6" - wire $0\oe_ok[0:0] - attribute \src "issuer_ls180.v:118237.3-118257.6" - wire $1\oe[0:0] - attribute \src "issuer_ls180.v:118258.3-118278.6" - wire $1\oe_ok[0:0] - attribute \src "issuer_ls180.v:118237.3-118257.6" - wire $2\oe[0:0] - attribute \src "issuer_ls180.v:118258.3-118278.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire input 4 \LDST_OE - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 1 \LDST_internal_op - attribute \src "issuer_ls180.v:118146.7-118146.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 input 5 \sel_in - attribute \src "issuer_ls180.v:118146.7-118146.20" - process $proc$issuer_ls180.v:118146$4590 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:118237.3-118257.6" - process $proc$issuer_ls180.v:118237$4588 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "issuer_ls180.v:118238.5-118238.29" - switch \initial - attribute \src "issuer_ls180.v:118238.9-118238.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \LDST_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \LDST_OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "issuer_ls180.v:118258.3-118278.6" - process $proc$issuer_ls180.v:118258$4589 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "issuer_ls180.v:118259.5-118259.29" - switch \initial - attribute \src "issuer_ls180.v:118259.9-118259.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \LDST_internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "issuer_ls180.v:118283.1-118417.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec_oe" -attribute \generator "nMigen" -module \dec_oe$204 - attribute \src "issuer_ls180.v:118284.7-118284.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:118375.3-118395.6" - wire $0\oe[0:0] - attribute \src "issuer_ls180.v:118396.3-118416.6" - wire $0\oe_ok[0:0] - attribute \src "issuer_ls180.v:118375.3-118395.6" - wire $1\oe[0:0] - attribute \src "issuer_ls180.v:118396.3-118416.6" - wire $1\oe_ok[0:0] - attribute \src "issuer_ls180.v:118375.3-118395.6" - wire $2\oe[0:0] - attribute \src "issuer_ls180.v:118396.3-118416.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire input 4 \OE - attribute \src "issuer_ls180.v:118284.7-118284.15" - wire \initial - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 7 input 1 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 input 5 \sel_in - attribute \src "issuer_ls180.v:118284.7-118284.20" - process $proc$issuer_ls180.v:118284$4593 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:118375.3-118395.6" - process $proc$issuer_ls180.v:118375$4591 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "issuer_ls180.v:118376.5-118376.29" - switch \initial - attribute \src "issuer_ls180.v:118376.9-118376.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "issuer_ls180.v:118396.3-118416.6" - process $proc$issuer_ls180.v:118396$4592 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "issuer_ls180.v:118397.5-118397.29" - switch \initial - attribute \src "issuer_ls180.v:118397.9-118397.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \internal_op - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "issuer_ls180.v:118421.1-118475.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_rc" -attribute \generator "nMigen" -module \dec_rc - attribute \src "issuer_ls180.v:118422.7-118422.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:118437.3-118455.6" - wire $0\rc[0:0] - attribute \src "issuer_ls180.v:118456.3-118474.6" - wire $0\rc_ok[0:0] - attribute \src "issuer_ls180.v:118437.3-118455.6" - wire $1\rc[0:0] - attribute \src "issuer_ls180.v:118456.3-118474.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire input 3 \ALU_Rc - attribute \src "issuer_ls180.v:118422.7-118422.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 input 4 \sel_in - attribute \src "issuer_ls180.v:118422.7-118422.20" - process $proc$issuer_ls180.v:118422$4596 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:118437.3-118455.6" - process $proc$issuer_ls180.v:118437$4594 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "issuer_ls180.v:118438.5-118438.29" - switch \initial - attribute \src "issuer_ls180.v:118438.9-118438.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \ALU_Rc - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] - end - attribute \src "issuer_ls180.v:118456.3-118474.6" - process $proc$issuer_ls180.v:118456$4595 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "issuer_ls180.v:118457.5-118457.29" - switch \initial - attribute \src "issuer_ls180.v:118457.9-118457.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] - end -end -attribute \src "issuer_ls180.v:118479.1-118532.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_rc" -attribute \generator "nMigen" -module \dec_rc$138 - attribute \src "issuer_ls180.v:118480.7-118480.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:118494.3-118512.6" - wire $0\rc[0:0] - attribute \src "issuer_ls180.v:118513.3-118531.6" - wire $0\rc_ok[0:0] - attribute \src "issuer_ls180.v:118494.3-118512.6" - wire $1\rc[0:0] - attribute \src "issuer_ls180.v:118513.3-118531.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire input 2 \CR_Rc - attribute \src "issuer_ls180.v:118480.7-118480.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 input 3 \sel_in - attribute \src "issuer_ls180.v:118480.7-118480.20" - process $proc$issuer_ls180.v:118480$4599 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:118494.3-118512.6" - process $proc$issuer_ls180.v:118494$4597 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "issuer_ls180.v:118495.5-118495.29" - switch \initial - attribute \src "issuer_ls180.v:118495.9-118495.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \CR_Rc - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] - end - attribute \src "issuer_ls180.v:118513.3-118531.6" - process $proc$issuer_ls180.v:118513$4598 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "issuer_ls180.v:118514.5-118514.29" - switch \initial - attribute \src "issuer_ls180.v:118514.9-118514.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] - end -end -attribute \src "issuer_ls180.v:118536.1-118589.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_rc" -attribute \generator "nMigen" -module \dec_rc$145 - attribute \src "issuer_ls180.v:118537.7-118537.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:118551.3-118569.6" - wire $0\rc[0:0] - attribute \src "issuer_ls180.v:118570.3-118588.6" - wire $0\rc_ok[0:0] - attribute \src "issuer_ls180.v:118551.3-118569.6" - wire $1\rc[0:0] - attribute \src "issuer_ls180.v:118570.3-118588.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire input 2 \BRANCH_Rc - attribute \src "issuer_ls180.v:118537.7-118537.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 input 3 \sel_in - attribute \src "issuer_ls180.v:118537.7-118537.20" - process $proc$issuer_ls180.v:118537$4602 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:118551.3-118569.6" - process $proc$issuer_ls180.v:118551$4600 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "issuer_ls180.v:118552.5-118552.29" - switch \initial - attribute \src "issuer_ls180.v:118552.9-118552.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \BRANCH_Rc - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] - end - attribute \src "issuer_ls180.v:118570.3-118588.6" - process $proc$issuer_ls180.v:118570$4601 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "issuer_ls180.v:118571.5-118571.29" - switch \initial - attribute \src "issuer_ls180.v:118571.9-118571.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] - end -end -attribute \src "issuer_ls180.v:118593.1-118647.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_rc" -attribute \generator "nMigen" -module \dec_rc$153 - attribute \src "issuer_ls180.v:118594.7-118594.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:118609.3-118627.6" - wire $0\rc[0:0] - attribute \src "issuer_ls180.v:118628.3-118646.6" - wire $0\rc_ok[0:0] - attribute \src "issuer_ls180.v:118609.3-118627.6" - wire $1\rc[0:0] - attribute \src "issuer_ls180.v:118628.3-118646.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire input 3 \LOGICAL_Rc - attribute \src "issuer_ls180.v:118594.7-118594.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 input 4 \sel_in - attribute \src "issuer_ls180.v:118594.7-118594.20" - process $proc$issuer_ls180.v:118594$4605 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:118609.3-118627.6" - process $proc$issuer_ls180.v:118609$4603 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "issuer_ls180.v:118610.5-118610.29" - switch \initial - attribute \src "issuer_ls180.v:118610.9-118610.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \LOGICAL_Rc - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] - end - attribute \src "issuer_ls180.v:118628.3-118646.6" - process $proc$issuer_ls180.v:118628$4604 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "issuer_ls180.v:118629.5-118629.29" - switch \initial - attribute \src "issuer_ls180.v:118629.9-118629.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] - end -end -attribute \src "issuer_ls180.v:118651.1-118704.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_rc" -attribute \generator "nMigen" -module \dec_rc$162 - attribute \src "issuer_ls180.v:118652.7-118652.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:118666.3-118684.6" - wire $0\rc[0:0] - attribute \src "issuer_ls180.v:118685.3-118703.6" - wire $0\rc_ok[0:0] - attribute \src "issuer_ls180.v:118666.3-118684.6" - wire $1\rc[0:0] - attribute \src "issuer_ls180.v:118685.3-118703.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire input 2 \SPR_Rc - attribute \src "issuer_ls180.v:118652.7-118652.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 input 3 \sel_in - attribute \src "issuer_ls180.v:118652.7-118652.20" - process $proc$issuer_ls180.v:118652$4608 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:118666.3-118684.6" - process $proc$issuer_ls180.v:118666$4606 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "issuer_ls180.v:118667.5-118667.29" - switch \initial - attribute \src "issuer_ls180.v:118667.9-118667.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \SPR_Rc - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] - end - attribute \src "issuer_ls180.v:118685.3-118703.6" - process $proc$issuer_ls180.v:118685$4607 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "issuer_ls180.v:118686.5-118686.29" - switch \initial - attribute \src "issuer_ls180.v:118686.9-118686.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] - end -end -attribute \src "issuer_ls180.v:118708.1-118762.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_rc" -attribute \generator "nMigen" -module \dec_rc$169 - attribute \src "issuer_ls180.v:118709.7-118709.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:118724.3-118742.6" - wire $0\rc[0:0] - attribute \src "issuer_ls180.v:118743.3-118761.6" - wire $0\rc_ok[0:0] - attribute \src "issuer_ls180.v:118724.3-118742.6" - wire $1\rc[0:0] - attribute \src "issuer_ls180.v:118743.3-118761.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire input 3 \DIV_Rc - attribute \src "issuer_ls180.v:118709.7-118709.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 input 4 \sel_in - attribute \src "issuer_ls180.v:118709.7-118709.20" - process $proc$issuer_ls180.v:118709$4611 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:118724.3-118742.6" - process $proc$issuer_ls180.v:118724$4609 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "issuer_ls180.v:118725.5-118725.29" - switch \initial - attribute \src "issuer_ls180.v:118725.9-118725.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \DIV_Rc - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] - end - attribute \src "issuer_ls180.v:118743.3-118761.6" - process $proc$issuer_ls180.v:118743$4610 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "issuer_ls180.v:118744.5-118744.29" - switch \initial - attribute \src "issuer_ls180.v:118744.9-118744.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] - end -end -attribute \src "issuer_ls180.v:118766.1-118820.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_rc" -attribute \generator "nMigen" -module \dec_rc$178 - attribute \src "issuer_ls180.v:118767.7-118767.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:118782.3-118800.6" - wire $0\rc[0:0] - attribute \src "issuer_ls180.v:118801.3-118819.6" - wire $0\rc_ok[0:0] - attribute \src "issuer_ls180.v:118782.3-118800.6" - wire $1\rc[0:0] - attribute \src "issuer_ls180.v:118801.3-118819.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire input 3 \MUL_Rc - attribute \src "issuer_ls180.v:118767.7-118767.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 input 4 \sel_in - attribute \src "issuer_ls180.v:118767.7-118767.20" - process $proc$issuer_ls180.v:118767$4614 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:118782.3-118800.6" - process $proc$issuer_ls180.v:118782$4612 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "issuer_ls180.v:118783.5-118783.29" - switch \initial - attribute \src "issuer_ls180.v:118783.9-118783.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \MUL_Rc - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] - end - attribute \src "issuer_ls180.v:118801.3-118819.6" - process $proc$issuer_ls180.v:118801$4613 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "issuer_ls180.v:118802.5-118802.29" - switch \initial - attribute \src "issuer_ls180.v:118802.9-118802.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] - end -end -attribute \src "issuer_ls180.v:118824.1-118878.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_rc" -attribute \generator "nMigen" -module \dec_rc$186 - attribute \src "issuer_ls180.v:118825.7-118825.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:118840.3-118858.6" - wire $0\rc[0:0] - attribute \src "issuer_ls180.v:118859.3-118877.6" - wire $0\rc_ok[0:0] - attribute \src "issuer_ls180.v:118840.3-118858.6" - wire $1\rc[0:0] - attribute \src "issuer_ls180.v:118859.3-118877.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire input 3 \SHIFT_ROT_Rc - attribute \src "issuer_ls180.v:118825.7-118825.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 input 4 \sel_in - attribute \src "issuer_ls180.v:118825.7-118825.20" - process $proc$issuer_ls180.v:118825$4617 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:118840.3-118858.6" - process $proc$issuer_ls180.v:118840$4615 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "issuer_ls180.v:118841.5-118841.29" - switch \initial - attribute \src "issuer_ls180.v:118841.9-118841.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \SHIFT_ROT_Rc - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] - end - attribute \src "issuer_ls180.v:118859.3-118877.6" - process $proc$issuer_ls180.v:118859$4616 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "issuer_ls180.v:118860.5-118860.29" - switch \initial - attribute \src "issuer_ls180.v:118860.9-118860.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] - end -end -attribute \src "issuer_ls180.v:118882.1-118936.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_rc" -attribute \generator "nMigen" -module \dec_rc$194 - attribute \src "issuer_ls180.v:118883.7-118883.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:118898.3-118916.6" - wire $0\rc[0:0] - attribute \src "issuer_ls180.v:118917.3-118935.6" - wire $0\rc_ok[0:0] - attribute \src "issuer_ls180.v:118898.3-118916.6" - wire $1\rc[0:0] - attribute \src "issuer_ls180.v:118917.3-118935.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire input 3 \LDST_Rc - attribute \src "issuer_ls180.v:118883.7-118883.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 input 4 \sel_in - attribute \src "issuer_ls180.v:118883.7-118883.20" - process $proc$issuer_ls180.v:118883$4620 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:118898.3-118916.6" - process $proc$issuer_ls180.v:118898$4618 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "issuer_ls180.v:118899.5-118899.29" - switch \initial - attribute \src "issuer_ls180.v:118899.9-118899.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \LDST_Rc - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] - end - attribute \src "issuer_ls180.v:118917.3-118935.6" - process $proc$issuer_ls180.v:118917$4619 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "issuer_ls180.v:118918.5-118918.29" - switch \initial - attribute \src "issuer_ls180.v:118918.9-118918.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] - end -end -attribute \src "issuer_ls180.v:118940.1-118994.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec_rc" -attribute \generator "nMigen" -module \dec_rc$203 - attribute \src "issuer_ls180.v:118941.7-118941.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:118956.3-118974.6" - wire $0\rc[0:0] - attribute \src "issuer_ls180.v:118975.3-118993.6" - wire $0\rc_ok[0:0] - attribute \src "issuer_ls180.v:118956.3-118974.6" - wire $1\rc[0:0] - attribute \src "issuer_ls180.v:118975.3-118993.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire input 3 \Rc - attribute \src "issuer_ls180.v:118941.7-118941.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 input 4 \sel_in - attribute \src "issuer_ls180.v:118941.7-118941.20" - process $proc$issuer_ls180.v:118941$4623 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:118956.3-118974.6" - process $proc$issuer_ls180.v:118956$4621 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "issuer_ls180.v:118957.5-118957.29" - switch \initial - attribute \src "issuer_ls180.v:118957.9-118957.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \Rc - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] - end - attribute \src "issuer_ls180.v:118975.3-118993.6" - process $proc$issuer_ls180.v:118975$4622 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "issuer_ls180.v:118976.5-118976.29" - switch \initial - attribute \src "issuer_ls180.v:118976.9-118976.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] - end -end -attribute \src "issuer_ls180.v:118998.1-120236.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0" -attribute \generator "nMigen" -module \div0 - attribute \src "issuer_ls180.v:119793.3-119794.25" - wire $0\all_rd_dly[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$4763 - attribute \src "issuer_ls180.v:119765.3-119766.75" - wire width 4 $0\alu_div0_logical_op__data_len[3:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire width 12 $0\alu_div0_logical_op__fn_unit$next[11:0]$4764 - attribute \src "issuer_ls180.v:119735.3-119736.73" - wire width 12 $0\alu_div0_logical_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$4765 - attribute \src "issuer_ls180.v:119737.3-119738.87" - wire width 64 $0\alu_div0_logical_op__imm_data__data[63:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$4766 - attribute \src "issuer_ls180.v:119739.3-119740.83" - wire $0\alu_div0_logical_op__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$4767 - attribute \src "issuer_ls180.v:119753.3-119754.81" - wire width 2 $0\alu_div0_logical_op__input_carry[1:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$4768 - attribute \src "issuer_ls180.v:119767.3-119768.67" - wire width 32 $0\alu_div0_logical_op__insn[31:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$4769 - attribute \src "issuer_ls180.v:119733.3-119734.77" - wire width 7 $0\alu_div0_logical_op__insn_type[6:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $0\alu_div0_logical_op__invert_in$next[0:0]$4770 - attribute \src "issuer_ls180.v:119749.3-119750.77" - wire $0\alu_div0_logical_op__invert_in[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $0\alu_div0_logical_op__invert_out$next[0:0]$4771 - attribute \src "issuer_ls180.v:119755.3-119756.79" - wire $0\alu_div0_logical_op__invert_out[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $0\alu_div0_logical_op__is_32bit$next[0:0]$4772 - attribute \src "issuer_ls180.v:119761.3-119762.75" - wire $0\alu_div0_logical_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $0\alu_div0_logical_op__is_signed$next[0:0]$4773 - attribute \src "issuer_ls180.v:119763.3-119764.77" - wire $0\alu_div0_logical_op__is_signed[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $0\alu_div0_logical_op__oe__oe$next[0:0]$4774 - attribute \src "issuer_ls180.v:119745.3-119746.71" - wire $0\alu_div0_logical_op__oe__oe[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $0\alu_div0_logical_op__oe__ok$next[0:0]$4775 - attribute \src "issuer_ls180.v:119747.3-119748.71" - wire $0\alu_div0_logical_op__oe__ok[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $0\alu_div0_logical_op__output_carry$next[0:0]$4776 - attribute \src "issuer_ls180.v:119759.3-119760.83" - wire $0\alu_div0_logical_op__output_carry[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $0\alu_div0_logical_op__rc__ok$next[0:0]$4777 - attribute \src "issuer_ls180.v:119743.3-119744.71" - wire $0\alu_div0_logical_op__rc__ok[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $0\alu_div0_logical_op__rc__rc$next[0:0]$4778 - attribute \src "issuer_ls180.v:119741.3-119742.71" - wire $0\alu_div0_logical_op__rc__rc[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $0\alu_div0_logical_op__write_cr0$next[0:0]$4779 - attribute \src "issuer_ls180.v:119757.3-119758.77" - wire $0\alu_div0_logical_op__write_cr0[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $0\alu_div0_logical_op__zero_a$next[0:0]$4780 - attribute \src "issuer_ls180.v:119751.3-119752.71" - wire $0\alu_div0_logical_op__zero_a[0:0] - attribute \src "issuer_ls180.v:119791.3-119792.40" - wire $0\alu_done_dly[0:0] - attribute \src "issuer_ls180.v:120146.3-120154.6" - wire $0\alu_l_r_alu$next[0:0]$4850 - attribute \src "issuer_ls180.v:119707.3-119708.39" - wire $0\alu_l_r_alu[0:0] - attribute \src "issuer_ls180.v:120137.3-120145.6" - wire $0\alui_l_r_alui$next[0:0]$4847 - attribute \src "issuer_ls180.v:119709.3-119710.43" - wire $0\alui_l_r_alui[0:0] - attribute \src "issuer_ls180.v:120019.3-120040.6" - wire width 64 $0\data_r0__o$next[63:0]$4806 - attribute \src "issuer_ls180.v:119729.3-119730.37" - wire width 64 $0\data_r0__o[63:0] - attribute \src "issuer_ls180.v:120019.3-120040.6" - wire $0\data_r0__o_ok$next[0:0]$4807 - attribute \src "issuer_ls180.v:119731.3-119732.43" - wire $0\data_r0__o_ok[0:0] - attribute \src "issuer_ls180.v:120041.3-120062.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$4814 - attribute \src "issuer_ls180.v:119725.3-119726.43" - wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "issuer_ls180.v:120041.3-120062.6" - wire $0\data_r1__cr_a_ok$next[0:0]$4815 - attribute \src "issuer_ls180.v:119727.3-119728.49" - wire $0\data_r1__cr_a_ok[0:0] - attribute \src "issuer_ls180.v:120063.3-120084.6" - wire width 2 $0\data_r2__xer_ov$next[1:0]$4822 - attribute \src "issuer_ls180.v:119721.3-119722.47" - wire width 2 $0\data_r2__xer_ov[1:0] - attribute \src "issuer_ls180.v:120063.3-120084.6" - wire $0\data_r2__xer_ov_ok$next[0:0]$4823 - attribute \src "issuer_ls180.v:119723.3-119724.53" - wire $0\data_r2__xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:120085.3-120106.6" - wire $0\data_r3__xer_so$next[0:0]$4830 - attribute \src "issuer_ls180.v:119717.3-119718.47" - wire $0\data_r3__xer_so[0:0] - attribute \src "issuer_ls180.v:120085.3-120106.6" - wire $0\data_r3__xer_so_ok$next[0:0]$4831 - attribute \src "issuer_ls180.v:119719.3-119720.53" - wire $0\data_r3__xer_so_ok[0:0] - attribute \src "issuer_ls180.v:120155.3-120164.6" - wire width 64 $0\dest1_o[63:0] - attribute \src "issuer_ls180.v:120165.3-120174.6" - wire width 4 $0\dest2_o[3:0] - attribute \src "issuer_ls180.v:120175.3-120184.6" - wire width 2 $0\dest3_o[1:0] - attribute \src "issuer_ls180.v:120185.3-120194.6" - wire $0\dest4_o[0:0] - attribute \src "issuer_ls180.v:118999.7-118999.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:119935.3-119943.6" - wire $0\opc_l_r_opc$next[0:0]$4748 - attribute \src "issuer_ls180.v:119777.3-119778.39" - wire $0\opc_l_r_opc[0:0] - attribute \src "issuer_ls180.v:119926.3-119934.6" - wire $0\opc_l_s_opc$next[0:0]$4745 - attribute \src "issuer_ls180.v:119779.3-119780.39" - wire $0\opc_l_s_opc[0:0] - attribute \src "issuer_ls180.v:120195.3-120203.6" - wire width 4 $0\prev_wr_go$next[3:0]$4857 - attribute \src "issuer_ls180.v:119789.3-119790.37" - wire width 4 $0\prev_wr_go[3:0] - attribute \src "issuer_ls180.v:119880.3-119889.6" - wire $0\req_done[0:0] - attribute \src "issuer_ls180.v:119971.3-119979.6" - wire width 4 $0\req_l_r_req$next[3:0]$4760 - attribute \src "issuer_ls180.v:119769.3-119770.39" - wire width 4 $0\req_l_r_req[3:0] - attribute \src "issuer_ls180.v:119962.3-119970.6" - wire width 4 $0\req_l_s_req$next[3:0]$4757 - attribute \src "issuer_ls180.v:119771.3-119772.39" - wire width 4 $0\req_l_s_req[3:0] - attribute \src "issuer_ls180.v:119899.3-119907.6" - wire $0\rok_l_r_rdok$next[0:0]$4736 - attribute \src "issuer_ls180.v:119785.3-119786.41" - wire $0\rok_l_r_rdok[0:0] - attribute \src "issuer_ls180.v:119890.3-119898.6" - wire $0\rok_l_s_rdok$next[0:0]$4733 - attribute \src "issuer_ls180.v:119787.3-119788.41" - wire $0\rok_l_s_rdok[0:0] - attribute \src "issuer_ls180.v:119917.3-119925.6" - wire $0\rst_l_r_rst$next[0:0]$4742 - attribute \src "issuer_ls180.v:119781.3-119782.39" - wire $0\rst_l_r_rst[0:0] - attribute \src "issuer_ls180.v:119908.3-119916.6" - wire $0\rst_l_s_rst$next[0:0]$4739 - attribute \src "issuer_ls180.v:119783.3-119784.39" - wire $0\rst_l_s_rst[0:0] - attribute \src "issuer_ls180.v:119953.3-119961.6" - wire width 3 $0\src_l_r_src$next[2:0]$4754 - attribute \src "issuer_ls180.v:119773.3-119774.39" - wire width 3 $0\src_l_r_src[2:0] - attribute \src "issuer_ls180.v:119944.3-119952.6" - wire width 3 $0\src_l_s_src$next[2:0]$4751 - attribute \src "issuer_ls180.v:119775.3-119776.39" - wire width 3 $0\src_l_s_src[2:0] - attribute \src "issuer_ls180.v:120107.3-120116.6" - wire width 64 $0\src_r0$next[63:0]$4838 - attribute \src "issuer_ls180.v:119715.3-119716.29" - wire width 64 $0\src_r0[63:0] - attribute \src "issuer_ls180.v:120117.3-120126.6" - wire width 64 $0\src_r1$next[63:0]$4841 - attribute \src "issuer_ls180.v:119713.3-119714.29" - wire width 64 $0\src_r1[63:0] - attribute \src "issuer_ls180.v:120127.3-120136.6" - wire $0\src_r2$next[0:0]$4844 - attribute \src "issuer_ls180.v:119711.3-119712.29" - wire $0\src_r2[0:0] - attribute \src "issuer_ls180.v:119129.7-119129.24" - wire $1\all_rd_dly[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$4781 - attribute \src "issuer_ls180.v:119139.13-119139.49" - wire width 4 $1\alu_div0_logical_op__data_len[3:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire width 12 $1\alu_div0_logical_op__fn_unit$next[11:0]$4782 - attribute \src "issuer_ls180.v:119156.14-119156.52" - wire width 12 $1\alu_div0_logical_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$4783 - attribute \src "issuer_ls180.v:119160.14-119160.72" - wire width 64 $1\alu_div0_logical_op__imm_data__data[63:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4784 - attribute \src "issuer_ls180.v:119164.7-119164.47" - wire $1\alu_div0_logical_op__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$4785 - attribute \src "issuer_ls180.v:119172.13-119172.52" - wire width 2 $1\alu_div0_logical_op__input_carry[1:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$4786 - attribute \src "issuer_ls180.v:119176.14-119176.47" - wire width 32 $1\alu_div0_logical_op__insn[31:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$4787 - attribute \src "issuer_ls180.v:119254.13-119254.51" - wire width 7 $1\alu_div0_logical_op__insn_type[6:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $1\alu_div0_logical_op__invert_in$next[0:0]$4788 - attribute \src "issuer_ls180.v:119258.7-119258.44" - wire $1\alu_div0_logical_op__invert_in[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $1\alu_div0_logical_op__invert_out$next[0:0]$4789 - attribute \src "issuer_ls180.v:119262.7-119262.45" - wire $1\alu_div0_logical_op__invert_out[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $1\alu_div0_logical_op__is_32bit$next[0:0]$4790 - attribute \src "issuer_ls180.v:119266.7-119266.43" - wire $1\alu_div0_logical_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $1\alu_div0_logical_op__is_signed$next[0:0]$4791 - attribute \src "issuer_ls180.v:119270.7-119270.44" - wire $1\alu_div0_logical_op__is_signed[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $1\alu_div0_logical_op__oe__oe$next[0:0]$4792 - attribute \src "issuer_ls180.v:119274.7-119274.41" - wire $1\alu_div0_logical_op__oe__oe[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $1\alu_div0_logical_op__oe__ok$next[0:0]$4793 - attribute \src "issuer_ls180.v:119278.7-119278.41" - wire $1\alu_div0_logical_op__oe__ok[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $1\alu_div0_logical_op__output_carry$next[0:0]$4794 - attribute \src "issuer_ls180.v:119282.7-119282.47" - wire $1\alu_div0_logical_op__output_carry[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $1\alu_div0_logical_op__rc__ok$next[0:0]$4795 - attribute \src "issuer_ls180.v:119286.7-119286.41" - wire $1\alu_div0_logical_op__rc__ok[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $1\alu_div0_logical_op__rc__rc$next[0:0]$4796 - attribute \src "issuer_ls180.v:119290.7-119290.41" - wire $1\alu_div0_logical_op__rc__rc[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $1\alu_div0_logical_op__write_cr0$next[0:0]$4797 - attribute \src "issuer_ls180.v:119294.7-119294.44" - wire $1\alu_div0_logical_op__write_cr0[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $1\alu_div0_logical_op__zero_a$next[0:0]$4798 - attribute \src "issuer_ls180.v:119298.7-119298.41" - wire $1\alu_div0_logical_op__zero_a[0:0] - attribute \src "issuer_ls180.v:119324.7-119324.26" - wire $1\alu_done_dly[0:0] - attribute \src "issuer_ls180.v:120146.3-120154.6" - wire $1\alu_l_r_alu$next[0:0]$4851 - attribute \src "issuer_ls180.v:119332.7-119332.25" - wire $1\alu_l_r_alu[0:0] - attribute \src "issuer_ls180.v:120137.3-120145.6" - wire $1\alui_l_r_alui$next[0:0]$4848 - attribute \src "issuer_ls180.v:119344.7-119344.27" - wire $1\alui_l_r_alui[0:0] - attribute \src "issuer_ls180.v:120019.3-120040.6" - wire width 64 $1\data_r0__o$next[63:0]$4808 - attribute \src "issuer_ls180.v:119378.14-119378.47" - wire width 64 $1\data_r0__o[63:0] - attribute \src "issuer_ls180.v:120019.3-120040.6" - wire $1\data_r0__o_ok$next[0:0]$4809 - attribute \src "issuer_ls180.v:119382.7-119382.27" - wire $1\data_r0__o_ok[0:0] - attribute \src "issuer_ls180.v:120041.3-120062.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$4816 - attribute \src "issuer_ls180.v:119386.13-119386.33" - wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "issuer_ls180.v:120041.3-120062.6" - wire $1\data_r1__cr_a_ok$next[0:0]$4817 - attribute \src "issuer_ls180.v:119390.7-119390.30" - wire $1\data_r1__cr_a_ok[0:0] - attribute \src "issuer_ls180.v:120063.3-120084.6" - wire width 2 $1\data_r2__xer_ov$next[1:0]$4824 - attribute \src "issuer_ls180.v:119394.13-119394.35" - wire width 2 $1\data_r2__xer_ov[1:0] - attribute \src "issuer_ls180.v:120063.3-120084.6" - wire $1\data_r2__xer_ov_ok$next[0:0]$4825 - attribute \src "issuer_ls180.v:119398.7-119398.32" - wire $1\data_r2__xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:120085.3-120106.6" - wire $1\data_r3__xer_so$next[0:0]$4832 - attribute \src "issuer_ls180.v:119402.7-119402.29" - wire $1\data_r3__xer_so[0:0] - attribute \src "issuer_ls180.v:120085.3-120106.6" - wire $1\data_r3__xer_so_ok$next[0:0]$4833 - attribute \src "issuer_ls180.v:119406.7-119406.32" - wire $1\data_r3__xer_so_ok[0:0] - attribute \src "issuer_ls180.v:120155.3-120164.6" - wire width 64 $1\dest1_o[63:0] - attribute \src "issuer_ls180.v:120165.3-120174.6" - wire width 4 $1\dest2_o[3:0] - attribute \src "issuer_ls180.v:120175.3-120184.6" - wire width 2 $1\dest3_o[1:0] - attribute \src "issuer_ls180.v:120185.3-120194.6" - wire $1\dest4_o[0:0] - attribute \src "issuer_ls180.v:119935.3-119943.6" - wire $1\opc_l_r_opc$next[0:0]$4749 - attribute \src "issuer_ls180.v:119426.7-119426.25" - wire $1\opc_l_r_opc[0:0] - attribute \src "issuer_ls180.v:119926.3-119934.6" - wire $1\opc_l_s_opc$next[0:0]$4746 - attribute \src "issuer_ls180.v:119430.7-119430.25" - wire $1\opc_l_s_opc[0:0] - attribute \src "issuer_ls180.v:120195.3-120203.6" - wire width 4 $1\prev_wr_go$next[3:0]$4858 - attribute \src "issuer_ls180.v:119561.13-119561.30" - wire width 4 $1\prev_wr_go[3:0] - attribute \src "issuer_ls180.v:119880.3-119889.6" - wire $1\req_done[0:0] - attribute \src "issuer_ls180.v:119971.3-119979.6" - wire width 4 $1\req_l_r_req$next[3:0]$4761 - attribute \src "issuer_ls180.v:119569.13-119569.31" - wire width 4 $1\req_l_r_req[3:0] - attribute \src "issuer_ls180.v:119962.3-119970.6" - wire width 4 $1\req_l_s_req$next[3:0]$4758 - attribute \src "issuer_ls180.v:119573.13-119573.31" - wire width 4 $1\req_l_s_req[3:0] - attribute \src "issuer_ls180.v:119899.3-119907.6" - wire $1\rok_l_r_rdok$next[0:0]$4737 - attribute \src "issuer_ls180.v:119585.7-119585.26" - wire $1\rok_l_r_rdok[0:0] - attribute \src "issuer_ls180.v:119890.3-119898.6" - wire $1\rok_l_s_rdok$next[0:0]$4734 - attribute \src "issuer_ls180.v:119589.7-119589.26" - wire $1\rok_l_s_rdok[0:0] - attribute \src "issuer_ls180.v:119917.3-119925.6" - wire $1\rst_l_r_rst$next[0:0]$4743 - attribute \src "issuer_ls180.v:119593.7-119593.25" - wire $1\rst_l_r_rst[0:0] - attribute \src "issuer_ls180.v:119908.3-119916.6" - wire $1\rst_l_s_rst$next[0:0]$4740 - attribute \src "issuer_ls180.v:119597.7-119597.25" - wire $1\rst_l_s_rst[0:0] - attribute \src "issuer_ls180.v:119953.3-119961.6" - wire width 3 $1\src_l_r_src$next[2:0]$4755 - attribute \src "issuer_ls180.v:119611.13-119611.31" - wire width 3 $1\src_l_r_src[2:0] - attribute \src "issuer_ls180.v:119944.3-119952.6" - wire width 3 $1\src_l_s_src$next[2:0]$4752 - attribute \src "issuer_ls180.v:119615.13-119615.31" - wire width 3 $1\src_l_s_src[2:0] - attribute \src "issuer_ls180.v:120107.3-120116.6" - wire width 64 $1\src_r0$next[63:0]$4839 - attribute \src "issuer_ls180.v:119623.14-119623.43" - wire width 64 $1\src_r0[63:0] - attribute \src "issuer_ls180.v:120117.3-120126.6" - wire width 64 $1\src_r1$next[63:0]$4842 - attribute \src "issuer_ls180.v:119627.14-119627.43" - wire width 64 $1\src_r1[63:0] - attribute \src "issuer_ls180.v:120127.3-120136.6" - wire $1\src_r2$next[0:0]$4845 - attribute \src "issuer_ls180.v:119631.7-119631.20" - wire $1\src_r2[0:0] - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$4799 - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4800 - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $2\alu_div0_logical_op__oe__oe$next[0:0]$4801 - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $2\alu_div0_logical_op__oe__ok$next[0:0]$4802 - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $2\alu_div0_logical_op__rc__ok$next[0:0]$4803 - attribute \src "issuer_ls180.v:119980.3-120018.6" - wire $2\alu_div0_logical_op__rc__rc$next[0:0]$4804 - attribute \src "issuer_ls180.v:120019.3-120040.6" - wire width 64 $2\data_r0__o$next[63:0]$4810 - attribute \src "issuer_ls180.v:120019.3-120040.6" - wire $2\data_r0__o_ok$next[0:0]$4811 - attribute \src "issuer_ls180.v:120041.3-120062.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$4818 - attribute \src "issuer_ls180.v:120041.3-120062.6" - wire $2\data_r1__cr_a_ok$next[0:0]$4819 - attribute \src "issuer_ls180.v:120063.3-120084.6" - wire width 2 $2\data_r2__xer_ov$next[1:0]$4826 - attribute \src "issuer_ls180.v:120063.3-120084.6" - wire $2\data_r2__xer_ov_ok$next[0:0]$4827 - attribute \src "issuer_ls180.v:120085.3-120106.6" - wire $2\data_r3__xer_so$next[0:0]$4834 - attribute \src "issuer_ls180.v:120085.3-120106.6" - wire $2\data_r3__xer_so_ok$next[0:0]$4835 - attribute \src "issuer_ls180.v:120019.3-120040.6" - wire $3\data_r0__o_ok$next[0:0]$4812 - attribute \src "issuer_ls180.v:120041.3-120062.6" - wire $3\data_r1__cr_a_ok$next[0:0]$4820 - attribute \src "issuer_ls180.v:120063.3-120084.6" - wire $3\data_r2__xer_ov_ok$next[0:0]$4828 - attribute \src "issuer_ls180.v:120085.3-120106.6" - wire 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"OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_div0_logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_div0_logical_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__invert_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__invert_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \alu_div0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \alu_div0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_div0_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \alu_div0_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \alu_div0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_div0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_div0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \alu_div0_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \alu_div0_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \alu_div0_xer_so$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" - wire \alu_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \alu_done_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \alu_l_s_alu - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 4 \alu_pulsem - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 38 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 37 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 31 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 20 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 19 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 23 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 22 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 21 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" - wire \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 29 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 28 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 4 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r0__o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r1__cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r2__xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r2__xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r2__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r2__xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r3__xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r3__xer_so$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r3__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r3__xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 30 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 32 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 34 \dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire output 36 \dest4_o - attribute \src "issuer_ls180.v:118999.7-118999.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 27 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \oper_i_alu_div0__data_len - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \oper_i_alu_div0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \oper_i_alu_div0__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \oper_i_alu_div0__imm_data__ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \oper_i_alu_div0__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \oper_i_alu_div0__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \oper_i_alu_div0__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \oper_i_alu_div0__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \oper_i_alu_div0__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \oper_i_alu_div0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \oper_i_alu_div0__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \oper_i_alu_div0__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \oper_i_alu_div0__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \oper_i_alu_div0__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \oper_i_alu_div0__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \oper_i_alu_div0__rc__rc - attribute \src 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\A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_ov_ok - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:119693$4673_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$issuer_ls180.v:119694$4674 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_so_ok - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:119694$4674_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$issuer_ls180.v:119704$4684 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_div0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $and$issuer_ls180.v:119704$4684_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$issuer_ls180.v:119705$4685 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_div0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $and$issuer_ls180.v:119705$4685_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$issuer_ls180.v:119706$4686 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$issuer_ls180.v:119706$4686_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$issuer_ls180.v:119677$4657 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$42 - connect \B 1'0 - connect \Y $eq$issuer_ls180.v:119677$4657_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$issuer_ls180.v:119679$4659 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o - connect \B 1'0 - connect \Y $eq$issuer_ls180.v:119679$4659_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$issuer_ls180.v:119644$4624 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_div0_logical_op__zero_a - connect \Y $not$issuer_ls180.v:119644$4624_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$issuer_ls180.v:119645$4625 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_div0_logical_op__imm_data__ok - connect \Y $not$issuer_ls180.v:119645$4625_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$issuer_ls180.v:119647$4627 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rdmaskn_i - connect \Y $not$issuer_ls180.v:119647$4627_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:119660$4640 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $not$issuer_ls180.v:119660$4640_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:119662$4642 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $not$issuer_ls180.v:119662$4642_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$issuer_ls180.v:119665$4645 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wrmask_o - connect \Y $not$issuer_ls180.v:119665$4645_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$issuer_ls180.v:119668$4648 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$23 - connect \Y $not$issuer_ls180.v:119668$4648_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$issuer_ls180.v:119674$4654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_div0_n_ready_i - connect \Y $not$issuer_ls180.v:119674$4654_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$issuer_ls180.v:119685$4665 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__rel_o - connect \Y $not$issuer_ls180.v:119685$4665_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$issuer_ls180.v:119673$4653 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$32 - connect \B \$34 - connect \Y $or$issuer_ls180.v:119673$4653_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$issuer_ls180.v:119683$4663 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $or$issuer_ls180.v:119683$4663_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$issuer_ls180.v:119684$4664 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $or$issuer_ls180.v:119684$4664_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$issuer_ls180.v:119686$4666 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$issuer_ls180.v:119686$4666_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$issuer_ls180.v:119687$4667 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$issuer_ls180.v:119687$4667_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$issuer_ls180.v:119690$4670 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $or$issuer_ls180.v:119690$4670_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$issuer_ls180.v:119696$4676 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$5 - connect \B \cu_rd__go_i - connect \Y $or$issuer_ls180.v:119696$4676_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$issuer_ls180.v:119701$4681 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \$7 - connect \Y $reduce_and$issuer_ls180.v:119701$4681_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$issuer_ls180.v:119667$4647 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \$26 - connect \Y $reduce_or$issuer_ls180.v:119667$4647_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$issuer_ls180.v:119671$4651 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $reduce_or$issuer_ls180.v:119671$4651_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$issuer_ls180.v:119672$4652 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $reduce_or$issuer_ls180.v:119672$4652_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$issuer_ls180.v:119695$4675 - parameter \WIDTH 1 - connect \A \src_l_q_src [0] - connect \B \opc_l_q_opc - connect \S \alu_div0_logical_op__zero_a - connect \Y $ternary$issuer_ls180.v:119695$4675_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$issuer_ls180.v:119697$4677 - parameter \WIDTH 64 - connect \A \src1_i - connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \S \alu_div0_logical_op__zero_a - connect \Y $ternary$issuer_ls180.v:119697$4677_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$issuer_ls180.v:119698$4678 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \alu_div0_logical_op__imm_data__ok - connect \Y $ternary$issuer_ls180.v:119698$4678_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$issuer_ls180.v:119699$4679 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \alu_div0_logical_op__imm_data__data - connect \S \alu_div0_logical_op__imm_data__ok - connect \Y $ternary$issuer_ls180.v:119699$4679_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:119700$4680 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $ternary$issuer_ls180.v:119700$4680_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:119702$4682 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm$85 - connect \S \src_sel$82 - connect \Y $ternary$issuer_ls180.v:119702$4682_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:119703$4683 - parameter \WIDTH 1 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $ternary$issuer_ls180.v:119703$4683_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:119795.12-119831.4" - cell \alu_div0 \alu_div0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \alu_div0_cr_a - connect \cr_a_ok \cr_a_ok - connect \logical_op__data_len \alu_div0_logical_op__data_len - connect \logical_op__fn_unit \alu_div0_logical_op__fn_unit - connect \logical_op__imm_data__data \alu_div0_logical_op__imm_data__data - connect \logical_op__imm_data__ok \alu_div0_logical_op__imm_data__ok - connect \logical_op__input_carry \alu_div0_logical_op__input_carry - connect \logical_op__insn \alu_div0_logical_op__insn - connect \logical_op__insn_type \alu_div0_logical_op__insn_type - connect \logical_op__invert_in \alu_div0_logical_op__invert_in - connect \logical_op__invert_out \alu_div0_logical_op__invert_out - connect \logical_op__is_32bit \alu_div0_logical_op__is_32bit - connect \logical_op__is_signed \alu_div0_logical_op__is_signed - connect \logical_op__oe__oe \alu_div0_logical_op__oe__oe - connect \logical_op__oe__ok \alu_div0_logical_op__oe__ok - connect \logical_op__output_carry \alu_div0_logical_op__output_carry - connect \logical_op__rc__ok \alu_div0_logical_op__rc__ok - connect \logical_op__rc__rc \alu_div0_logical_op__rc__rc - connect \logical_op__write_cr0 \alu_div0_logical_op__write_cr0 - connect \logical_op__zero_a \alu_div0_logical_op__zero_a - connect \n_ready_i \alu_div0_n_ready_i - connect \n_valid_o \alu_div0_n_valid_o - connect \o \alu_div0_o - connect \o_ok \o_ok - connect \p_ready_o \alu_div0_p_ready_o - connect \p_valid_i \alu_div0_p_valid_i - connect \ra \alu_div0_ra - connect \rb \alu_div0_rb - connect \xer_ov \alu_div0_xer_ov - connect \xer_ov_ok \xer_ov_ok - connect \xer_so \alu_div0_xer_so - connect \xer_so$1 \alu_div0_xer_so$1 - connect \xer_so_ok \xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:119832.14-119838.4" - cell \alu_l$87 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:119839.15-119845.4" - cell \alui_l$86 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:119846.14-119852.4" - cell \opc_l$82 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_opc \opc_l_q_opc - connect \r_opc \opc_l_r_opc - connect \s_opc \opc_l_s_opc - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:119853.14-119859.4" - cell \req_l$83 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \r_req \req_l_r_req - connect \s_req \req_l_s_req - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:119860.14-119866.4" - cell \rok_l$85 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \r_rdok \rok_l_r_rdok - connect \s_rdok \rok_l_s_rdok - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:119867.14-119872.4" - cell \rst_l$84 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_rst \rst_l_r_rst - connect \s_rst \rst_l_s_rst - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:119873.14-119879.4" - cell \src_l$81 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_src \src_l_q_src - connect \r_src \src_l_r_src - connect \s_src \src_l_s_src - end - attribute \src "issuer_ls180.v:118999.7-118999.20" - process $proc$issuer_ls180.v:118999$4859 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:119129.7-119129.24" - process $proc$issuer_ls180.v:119129$4860 - assign { } { } - assign $1\all_rd_dly[0:0] 1'0 - sync always - sync init - update \all_rd_dly $1\all_rd_dly[0:0] - end - attribute \src "issuer_ls180.v:119139.13-119139.49" - process $proc$issuer_ls180.v:119139$4861 - assign { } { } - assign $1\alu_div0_logical_op__data_len[3:0] 4'0000 - sync always - sync init - update \alu_div0_logical_op__data_len $1\alu_div0_logical_op__data_len[3:0] - end - attribute \src "issuer_ls180.v:119156.14-119156.52" - process $proc$issuer_ls180.v:119156$4862 - assign { } { } - assign $1\alu_div0_logical_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \alu_div0_logical_op__fn_unit $1\alu_div0_logical_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:119160.14-119160.72" - process $proc$issuer_ls180.v:119160$4863 - assign { } { } - assign $1\alu_div0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_div0_logical_op__imm_data__data $1\alu_div0_logical_op__imm_data__data[63:0] - end - attribute \src "issuer_ls180.v:119164.7-119164.47" - process $proc$issuer_ls180.v:119164$4864 - assign { } { } - assign $1\alu_div0_logical_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__imm_data__ok $1\alu_div0_logical_op__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:119172.13-119172.52" - process $proc$issuer_ls180.v:119172$4865 - assign { } { } - assign $1\alu_div0_logical_op__input_carry[1:0] 2'00 - sync always - sync init - update \alu_div0_logical_op__input_carry $1\alu_div0_logical_op__input_carry[1:0] - end - attribute \src "issuer_ls180.v:119176.14-119176.47" - process $proc$issuer_ls180.v:119176$4866 - assign { } { } - assign $1\alu_div0_logical_op__insn[31:0] 0 - sync always - sync init - update \alu_div0_logical_op__insn $1\alu_div0_logical_op__insn[31:0] - end - attribute \src "issuer_ls180.v:119254.13-119254.51" - process $proc$issuer_ls180.v:119254$4867 - assign { } { } - assign $1\alu_div0_logical_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \alu_div0_logical_op__insn_type $1\alu_div0_logical_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:119258.7-119258.44" - process $proc$issuer_ls180.v:119258$4868 - assign { } { } - assign $1\alu_div0_logical_op__invert_in[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__invert_in $1\alu_div0_logical_op__invert_in[0:0] - end - attribute \src "issuer_ls180.v:119262.7-119262.45" - process $proc$issuer_ls180.v:119262$4869 - assign { } { } - assign $1\alu_div0_logical_op__invert_out[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__invert_out $1\alu_div0_logical_op__invert_out[0:0] - end - attribute \src "issuer_ls180.v:119266.7-119266.43" - process $proc$issuer_ls180.v:119266$4870 - assign { } { } - assign $1\alu_div0_logical_op__is_32bit[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__is_32bit $1\alu_div0_logical_op__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:119270.7-119270.44" - process $proc$issuer_ls180.v:119270$4871 - assign { } { } - assign $1\alu_div0_logical_op__is_signed[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__is_signed $1\alu_div0_logical_op__is_signed[0:0] - end - attribute \src "issuer_ls180.v:119274.7-119274.41" - process $proc$issuer_ls180.v:119274$4872 - assign { } { } - assign $1\alu_div0_logical_op__oe__oe[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__oe__oe $1\alu_div0_logical_op__oe__oe[0:0] - end - attribute \src "issuer_ls180.v:119278.7-119278.41" - process $proc$issuer_ls180.v:119278$4873 - assign { } { } - assign $1\alu_div0_logical_op__oe__ok[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__oe__ok $1\alu_div0_logical_op__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:119282.7-119282.47" - process $proc$issuer_ls180.v:119282$4874 - assign { } { } - assign $1\alu_div0_logical_op__output_carry[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__output_carry $1\alu_div0_logical_op__output_carry[0:0] - end - attribute \src "issuer_ls180.v:119286.7-119286.41" - process $proc$issuer_ls180.v:119286$4875 - assign { } { } - assign $1\alu_div0_logical_op__rc__ok[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__rc__ok $1\alu_div0_logical_op__rc__ok[0:0] - end - attribute \src "issuer_ls180.v:119290.7-119290.41" - process $proc$issuer_ls180.v:119290$4876 - assign { } { } - assign $1\alu_div0_logical_op__rc__rc[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__rc__rc $1\alu_div0_logical_op__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:119294.7-119294.44" - process $proc$issuer_ls180.v:119294$4877 - assign { } { } - assign $1\alu_div0_logical_op__write_cr0[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__write_cr0 $1\alu_div0_logical_op__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:119298.7-119298.41" - process $proc$issuer_ls180.v:119298$4878 - assign { } { } - assign $1\alu_div0_logical_op__zero_a[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__zero_a $1\alu_div0_logical_op__zero_a[0:0] - end - attribute \src "issuer_ls180.v:119324.7-119324.26" - process $proc$issuer_ls180.v:119324$4879 - assign { } { } - assign $1\alu_done_dly[0:0] 1'0 - sync always - sync init - update \alu_done_dly $1\alu_done_dly[0:0] - end - attribute \src "issuer_ls180.v:119332.7-119332.25" - process $proc$issuer_ls180.v:119332$4880 - assign { } { } - assign $1\alu_l_r_alu[0:0] 1'1 - sync always - sync init - update \alu_l_r_alu $1\alu_l_r_alu[0:0] - end - attribute \src "issuer_ls180.v:119344.7-119344.27" - process $proc$issuer_ls180.v:119344$4881 - assign { } { } - assign $1\alui_l_r_alui[0:0] 1'1 - sync always - sync init - update \alui_l_r_alui $1\alui_l_r_alui[0:0] - end - attribute \src "issuer_ls180.v:119378.14-119378.47" - process $proc$issuer_ls180.v:119378$4882 - assign { } { } - assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r0__o $1\data_r0__o[63:0] - end - attribute \src "issuer_ls180.v:119382.7-119382.27" - process $proc$issuer_ls180.v:119382$4883 - assign { } { } - assign $1\data_r0__o_ok[0:0] 1'0 - sync always - sync init - update \data_r0__o_ok $1\data_r0__o_ok[0:0] - end - attribute \src "issuer_ls180.v:119386.13-119386.33" - process $proc$issuer_ls180.v:119386$4884 - assign { } { } - assign $1\data_r1__cr_a[3:0] 4'0000 - sync always - sync init - update \data_r1__cr_a $1\data_r1__cr_a[3:0] - end - attribute \src "issuer_ls180.v:119390.7-119390.30" - process $proc$issuer_ls180.v:119390$4885 - assign { } { } - assign $1\data_r1__cr_a_ok[0:0] 1'0 - sync always - sync init - update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:119394.13-119394.35" - process $proc$issuer_ls180.v:119394$4886 - assign { } { } - assign $1\data_r2__xer_ov[1:0] 2'00 - sync always - sync init - update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] - end - attribute \src "issuer_ls180.v:119398.7-119398.32" - process $proc$issuer_ls180.v:119398$4887 - assign { } { } - assign $1\data_r2__xer_ov_ok[0:0] 1'0 - sync always - sync init - update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] - end - attribute \src "issuer_ls180.v:119402.7-119402.29" - process $proc$issuer_ls180.v:119402$4888 - assign { } { } - assign $1\data_r3__xer_so[0:0] 1'0 - sync always - sync init - update \data_r3__xer_so $1\data_r3__xer_so[0:0] - end - attribute \src "issuer_ls180.v:119406.7-119406.32" - process $proc$issuer_ls180.v:119406$4889 - assign { } { } - assign $1\data_r3__xer_so_ok[0:0] 1'0 - sync always - sync init - update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] - end - attribute \src "issuer_ls180.v:119426.7-119426.25" - process $proc$issuer_ls180.v:119426$4890 - assign { } { } - assign $1\opc_l_r_opc[0:0] 1'1 - sync always - sync init - update \opc_l_r_opc $1\opc_l_r_opc[0:0] - end - attribute \src "issuer_ls180.v:119430.7-119430.25" - process $proc$issuer_ls180.v:119430$4891 - assign { } { } - assign $1\opc_l_s_opc[0:0] 1'0 - sync always - sync init - update \opc_l_s_opc $1\opc_l_s_opc[0:0] - end - attribute \src "issuer_ls180.v:119561.13-119561.30" - process $proc$issuer_ls180.v:119561$4892 - assign { } { } - assign $1\prev_wr_go[3:0] 4'0000 - sync always - sync init - update \prev_wr_go $1\prev_wr_go[3:0] - end - attribute \src "issuer_ls180.v:119569.13-119569.31" - process $proc$issuer_ls180.v:119569$4893 - assign { } { } - assign $1\req_l_r_req[3:0] 4'1111 - sync always - sync init - update \req_l_r_req $1\req_l_r_req[3:0] - end - attribute \src "issuer_ls180.v:119573.13-119573.31" - process $proc$issuer_ls180.v:119573$4894 - assign { } { } - assign $1\req_l_s_req[3:0] 4'0000 - sync always - sync init - update \req_l_s_req $1\req_l_s_req[3:0] - end - attribute \src "issuer_ls180.v:119585.7-119585.26" - process $proc$issuer_ls180.v:119585$4895 - assign { } { } - assign $1\rok_l_r_rdok[0:0] 1'1 - sync always - sync init - update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] - end - attribute \src "issuer_ls180.v:119589.7-119589.26" - process $proc$issuer_ls180.v:119589$4896 - assign { } { } - assign $1\rok_l_s_rdok[0:0] 1'0 - sync always - sync init - update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] - end - attribute \src "issuer_ls180.v:119593.7-119593.25" - process $proc$issuer_ls180.v:119593$4897 - assign { } { } - assign $1\rst_l_r_rst[0:0] 1'1 - sync always - sync init - update \rst_l_r_rst $1\rst_l_r_rst[0:0] - end - attribute \src "issuer_ls180.v:119597.7-119597.25" - process $proc$issuer_ls180.v:119597$4898 - assign { } { } - assign $1\rst_l_s_rst[0:0] 1'0 - sync always - sync init - update \rst_l_s_rst $1\rst_l_s_rst[0:0] - end - attribute \src "issuer_ls180.v:119611.13-119611.31" - process $proc$issuer_ls180.v:119611$4899 - assign { } { } - assign $1\src_l_r_src[2:0] 3'111 - sync always - sync init - update \src_l_r_src $1\src_l_r_src[2:0] - end - attribute \src "issuer_ls180.v:119615.13-119615.31" - process $proc$issuer_ls180.v:119615$4900 - assign { } { } - assign $1\src_l_s_src[2:0] 3'000 - sync always - sync init - update \src_l_s_src $1\src_l_s_src[2:0] - end - attribute \src "issuer_ls180.v:119623.14-119623.43" - process $proc$issuer_ls180.v:119623$4901 - assign { } { } - assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r0 $1\src_r0[63:0] - end - attribute \src "issuer_ls180.v:119627.14-119627.43" - process $proc$issuer_ls180.v:119627$4902 - assign { } { } - assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r1 $1\src_r1[63:0] - end - attribute \src "issuer_ls180.v:119631.7-119631.20" - process $proc$issuer_ls180.v:119631$4903 - assign { } { } - assign $1\src_r2[0:0] 1'0 - sync always - sync init - update \src_r2 $1\src_r2[0:0] - end - attribute \src "issuer_ls180.v:119707.3-119708.39" - process $proc$issuer_ls180.v:119707$4687 - assign { } { } - assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next - sync posedge \coresync_clk - update \alu_l_r_alu $0\alu_l_r_alu[0:0] - end - attribute \src "issuer_ls180.v:119709.3-119710.43" - process $proc$issuer_ls180.v:119709$4688 - assign { } { } - assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next - sync posedge \coresync_clk - update \alui_l_r_alui $0\alui_l_r_alui[0:0] - end - attribute \src "issuer_ls180.v:119711.3-119712.29" - process $proc$issuer_ls180.v:119711$4689 - assign { } { } - assign $0\src_r2[0:0] \src_r2$next - sync posedge \coresync_clk - update \src_r2 $0\src_r2[0:0] - end - attribute \src "issuer_ls180.v:119713.3-119714.29" - process $proc$issuer_ls180.v:119713$4690 - assign { } { } - assign $0\src_r1[63:0] \src_r1$next - sync posedge \coresync_clk - update \src_r1 $0\src_r1[63:0] - end - attribute \src "issuer_ls180.v:119715.3-119716.29" - process $proc$issuer_ls180.v:119715$4691 - assign { } { } - assign $0\src_r0[63:0] \src_r0$next - sync posedge \coresync_clk - update \src_r0 $0\src_r0[63:0] - end - attribute \src "issuer_ls180.v:119717.3-119718.47" - process $proc$issuer_ls180.v:119717$4692 - assign { } { } - assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next - sync posedge \coresync_clk - update \data_r3__xer_so $0\data_r3__xer_so[0:0] - end - attribute \src "issuer_ls180.v:119719.3-119720.53" - process $proc$issuer_ls180.v:119719$4693 - assign { } { } - assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next - sync posedge \coresync_clk - update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] - end - attribute \src "issuer_ls180.v:119721.3-119722.47" - process $proc$issuer_ls180.v:119721$4694 - assign { } { } - assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next - sync posedge \coresync_clk - update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] - end - attribute \src "issuer_ls180.v:119723.3-119724.53" - process $proc$issuer_ls180.v:119723$4695 - assign { } { } - assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next - sync posedge \coresync_clk - update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] - end - attribute \src "issuer_ls180.v:119725.3-119726.43" - process $proc$issuer_ls180.v:119725$4696 - assign { } { } - assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next - sync posedge \coresync_clk - update \data_r1__cr_a $0\data_r1__cr_a[3:0] - end - attribute \src "issuer_ls180.v:119727.3-119728.49" - process $proc$issuer_ls180.v:119727$4697 - assign { } { } - assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next - sync posedge \coresync_clk - update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:119729.3-119730.37" - process $proc$issuer_ls180.v:119729$4698 - assign { } { } - assign $0\data_r0__o[63:0] \data_r0__o$next - sync posedge \coresync_clk - update \data_r0__o $0\data_r0__o[63:0] - end - attribute \src "issuer_ls180.v:119731.3-119732.43" - process $proc$issuer_ls180.v:119731$4699 - assign { } { } - assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next - sync posedge \coresync_clk - update \data_r0__o_ok $0\data_r0__o_ok[0:0] - end - attribute \src "issuer_ls180.v:119733.3-119734.77" - process $proc$issuer_ls180.v:119733$4700 - assign { } { } - assign $0\alu_div0_logical_op__insn_type[6:0] \alu_div0_logical_op__insn_type$next - sync posedge \coresync_clk - update \alu_div0_logical_op__insn_type $0\alu_div0_logical_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:119735.3-119736.73" - process $proc$issuer_ls180.v:119735$4701 - assign { } { } - assign $0\alu_div0_logical_op__fn_unit[11:0] \alu_div0_logical_op__fn_unit$next - sync posedge \coresync_clk - update \alu_div0_logical_op__fn_unit $0\alu_div0_logical_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:119737.3-119738.87" - process $proc$issuer_ls180.v:119737$4702 - assign { } { } - assign $0\alu_div0_logical_op__imm_data__data[63:0] \alu_div0_logical_op__imm_data__data$next - sync posedge \coresync_clk - update \alu_div0_logical_op__imm_data__data $0\alu_div0_logical_op__imm_data__data[63:0] - end - attribute \src "issuer_ls180.v:119739.3-119740.83" - process $proc$issuer_ls180.v:119739$4703 - assign { } { } - assign $0\alu_div0_logical_op__imm_data__ok[0:0] \alu_div0_logical_op__imm_data__ok$next - sync posedge \coresync_clk - update \alu_div0_logical_op__imm_data__ok $0\alu_div0_logical_op__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:119741.3-119742.71" - process $proc$issuer_ls180.v:119741$4704 - assign { } { } - assign $0\alu_div0_logical_op__rc__rc[0:0] \alu_div0_logical_op__rc__rc$next - sync posedge \coresync_clk - update \alu_div0_logical_op__rc__rc $0\alu_div0_logical_op__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:119743.3-119744.71" - process $proc$issuer_ls180.v:119743$4705 - assign { } { } - assign $0\alu_div0_logical_op__rc__ok[0:0] \alu_div0_logical_op__rc__ok$next - sync posedge \coresync_clk - update \alu_div0_logical_op__rc__ok $0\alu_div0_logical_op__rc__ok[0:0] - end - attribute \src "issuer_ls180.v:119745.3-119746.71" - process $proc$issuer_ls180.v:119745$4706 - assign { } { } - assign $0\alu_div0_logical_op__oe__oe[0:0] \alu_div0_logical_op__oe__oe$next - sync posedge \coresync_clk - update \alu_div0_logical_op__oe__oe $0\alu_div0_logical_op__oe__oe[0:0] - end - attribute \src "issuer_ls180.v:119747.3-119748.71" - process $proc$issuer_ls180.v:119747$4707 - assign { } { } - assign $0\alu_div0_logical_op__oe__ok[0:0] \alu_div0_logical_op__oe__ok$next - sync posedge \coresync_clk - update \alu_div0_logical_op__oe__ok $0\alu_div0_logical_op__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:119749.3-119750.77" - process $proc$issuer_ls180.v:119749$4708 - assign { } { } - assign $0\alu_div0_logical_op__invert_in[0:0] \alu_div0_logical_op__invert_in$next - sync posedge \coresync_clk - update \alu_div0_logical_op__invert_in $0\alu_div0_logical_op__invert_in[0:0] - end - attribute \src "issuer_ls180.v:119751.3-119752.71" - process $proc$issuer_ls180.v:119751$4709 - assign { } { } - assign $0\alu_div0_logical_op__zero_a[0:0] \alu_div0_logical_op__zero_a$next - sync posedge \coresync_clk - update \alu_div0_logical_op__zero_a $0\alu_div0_logical_op__zero_a[0:0] - end - attribute \src "issuer_ls180.v:119753.3-119754.81" - process $proc$issuer_ls180.v:119753$4710 - assign { } { } - assign $0\alu_div0_logical_op__input_carry[1:0] \alu_div0_logical_op__input_carry$next - sync posedge \coresync_clk - update \alu_div0_logical_op__input_carry $0\alu_div0_logical_op__input_carry[1:0] - end - attribute \src "issuer_ls180.v:119755.3-119756.79" - process $proc$issuer_ls180.v:119755$4711 - assign { } { } - assign $0\alu_div0_logical_op__invert_out[0:0] \alu_div0_logical_op__invert_out$next - sync posedge \coresync_clk - update \alu_div0_logical_op__invert_out $0\alu_div0_logical_op__invert_out[0:0] - end - attribute \src "issuer_ls180.v:119757.3-119758.77" - process $proc$issuer_ls180.v:119757$4712 - assign { } { } - assign $0\alu_div0_logical_op__write_cr0[0:0] \alu_div0_logical_op__write_cr0$next - sync posedge \coresync_clk - update \alu_div0_logical_op__write_cr0 $0\alu_div0_logical_op__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:119759.3-119760.83" - process $proc$issuer_ls180.v:119759$4713 - assign { } { } - assign $0\alu_div0_logical_op__output_carry[0:0] \alu_div0_logical_op__output_carry$next - sync posedge \coresync_clk - update \alu_div0_logical_op__output_carry $0\alu_div0_logical_op__output_carry[0:0] - end - attribute \src "issuer_ls180.v:119761.3-119762.75" - process $proc$issuer_ls180.v:119761$4714 - assign { } { } - assign $0\alu_div0_logical_op__is_32bit[0:0] \alu_div0_logical_op__is_32bit$next - sync posedge \coresync_clk - update \alu_div0_logical_op__is_32bit $0\alu_div0_logical_op__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:119763.3-119764.77" - process $proc$issuer_ls180.v:119763$4715 - assign { } { } - assign $0\alu_div0_logical_op__is_signed[0:0] \alu_div0_logical_op__is_signed$next - sync posedge \coresync_clk - update \alu_div0_logical_op__is_signed $0\alu_div0_logical_op__is_signed[0:0] - end - attribute \src "issuer_ls180.v:119765.3-119766.75" - process $proc$issuer_ls180.v:119765$4716 - assign { } { } - assign $0\alu_div0_logical_op__data_len[3:0] \alu_div0_logical_op__data_len$next - sync posedge \coresync_clk - update \alu_div0_logical_op__data_len $0\alu_div0_logical_op__data_len[3:0] - end - attribute \src "issuer_ls180.v:119767.3-119768.67" - process $proc$issuer_ls180.v:119767$4717 - assign { } { } - assign $0\alu_div0_logical_op__insn[31:0] \alu_div0_logical_op__insn$next - sync posedge \coresync_clk - update \alu_div0_logical_op__insn $0\alu_div0_logical_op__insn[31:0] - end - attribute \src "issuer_ls180.v:119769.3-119770.39" - process $proc$issuer_ls180.v:119769$4718 - assign { } { } - assign $0\req_l_r_req[3:0] \req_l_r_req$next - sync posedge \coresync_clk - update \req_l_r_req $0\req_l_r_req[3:0] - end - attribute \src "issuer_ls180.v:119771.3-119772.39" - process $proc$issuer_ls180.v:119771$4719 - assign { } { } - assign $0\req_l_s_req[3:0] \req_l_s_req$next - sync posedge \coresync_clk - update \req_l_s_req $0\req_l_s_req[3:0] - end - attribute \src "issuer_ls180.v:119773.3-119774.39" - process $proc$issuer_ls180.v:119773$4720 - assign { } { } - assign $0\src_l_r_src[2:0] \src_l_r_src$next - sync posedge \coresync_clk - update \src_l_r_src $0\src_l_r_src[2:0] - end - attribute \src "issuer_ls180.v:119775.3-119776.39" - process $proc$issuer_ls180.v:119775$4721 - assign { } { } - assign $0\src_l_s_src[2:0] \src_l_s_src$next - sync posedge \coresync_clk - update \src_l_s_src $0\src_l_s_src[2:0] - end - attribute \src "issuer_ls180.v:119777.3-119778.39" - process $proc$issuer_ls180.v:119777$4722 - assign { } { } - assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next - sync posedge \coresync_clk - update \opc_l_r_opc $0\opc_l_r_opc[0:0] - end - attribute \src "issuer_ls180.v:119779.3-119780.39" - process $proc$issuer_ls180.v:119779$4723 - assign { } { } - assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next - sync posedge \coresync_clk - update \opc_l_s_opc $0\opc_l_s_opc[0:0] - end - attribute \src "issuer_ls180.v:119781.3-119782.39" - process $proc$issuer_ls180.v:119781$4724 - assign { } { } - assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next - sync posedge \coresync_clk - update \rst_l_r_rst $0\rst_l_r_rst[0:0] - end - attribute \src "issuer_ls180.v:119783.3-119784.39" - process $proc$issuer_ls180.v:119783$4725 - assign { } { } - assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next - sync posedge \coresync_clk - update \rst_l_s_rst $0\rst_l_s_rst[0:0] - end - attribute \src "issuer_ls180.v:119785.3-119786.41" - process $proc$issuer_ls180.v:119785$4726 - assign { } { } - assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next - sync posedge \coresync_clk - update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] - end - attribute \src "issuer_ls180.v:119787.3-119788.41" - process $proc$issuer_ls180.v:119787$4727 - assign { } { } - assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next - sync posedge \coresync_clk - update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] - end - attribute \src "issuer_ls180.v:119789.3-119790.37" - process $proc$issuer_ls180.v:119789$4728 - assign { } { } - assign $0\prev_wr_go[3:0] \prev_wr_go$next - sync posedge \coresync_clk - update \prev_wr_go $0\prev_wr_go[3:0] - end - attribute \src "issuer_ls180.v:119791.3-119792.40" - process $proc$issuer_ls180.v:119791$4729 - assign { } { } - assign $0\alu_done_dly[0:0] \alu_div0_n_valid_o - sync posedge \coresync_clk - update \alu_done_dly $0\alu_done_dly[0:0] - end - attribute \src "issuer_ls180.v:119793.3-119794.25" - process $proc$issuer_ls180.v:119793$4730 - assign { } { } - assign $0\all_rd_dly[0:0] \$10 - sync posedge \coresync_clk - update \all_rd_dly $0\all_rd_dly[0:0] - end - attribute \src "issuer_ls180.v:119880.3-119889.6" - process $proc$issuer_ls180.v:119880$4731 - assign { } { } - assign { } { } - assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "issuer_ls180.v:119881.5-119881.29" - switch \initial - attribute \src "issuer_ls180.v:119881.9-119881.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch \$54 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_done[0:0] 1'1 - case - assign $1\req_done[0:0] \$46 - end - sync always - update \req_done $0\req_done[0:0] - end - attribute \src "issuer_ls180.v:119890.3-119898.6" - process $proc$issuer_ls180.v:119890$4732 - assign { } { } - assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$4733 $1\rok_l_s_rdok$next[0:0]$4734 - attribute \src "issuer_ls180.v:119891.5-119891.29" - switch \initial - attribute \src "issuer_ls180.v:119891.9-119891.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$4734 1'0 - case - assign $1\rok_l_s_rdok$next[0:0]$4734 \cu_issue_i - end - sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$4733 - end - attribute \src "issuer_ls180.v:119899.3-119907.6" - process $proc$issuer_ls180.v:119899$4735 - assign { } { } - assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$4736 $1\rok_l_r_rdok$next[0:0]$4737 - attribute \src "issuer_ls180.v:119900.5-119900.29" - switch \initial - attribute \src "issuer_ls180.v:119900.9-119900.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$4737 1'1 - case - assign $1\rok_l_r_rdok$next[0:0]$4737 \$64 - end - sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$4736 - end - attribute \src "issuer_ls180.v:119908.3-119916.6" - process $proc$issuer_ls180.v:119908$4738 - assign { } { } - assign { } { } - assign $0\rst_l_s_rst$next[0:0]$4739 $1\rst_l_s_rst$next[0:0]$4740 - attribute \src "issuer_ls180.v:119909.5-119909.29" - switch \initial - attribute \src "issuer_ls180.v:119909.9-119909.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_s_rst$next[0:0]$4740 1'0 - case - assign $1\rst_l_s_rst$next[0:0]$4740 \all_rd - end - sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$4739 - end - attribute \src "issuer_ls180.v:119917.3-119925.6" - process $proc$issuer_ls180.v:119917$4741 - assign { } { } - assign { } { } - assign $0\rst_l_r_rst$next[0:0]$4742 $1\rst_l_r_rst$next[0:0]$4743 - attribute \src "issuer_ls180.v:119918.5-119918.29" - switch \initial - attribute \src "issuer_ls180.v:119918.9-119918.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_r_rst$next[0:0]$4743 1'1 - case - assign $1\rst_l_r_rst$next[0:0]$4743 \rst_r - end - sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$4742 - end - attribute \src "issuer_ls180.v:119926.3-119934.6" - process $proc$issuer_ls180.v:119926$4744 - assign { } { } - assign { } { } - assign $0\opc_l_s_opc$next[0:0]$4745 $1\opc_l_s_opc$next[0:0]$4746 - attribute \src "issuer_ls180.v:119927.5-119927.29" - switch \initial - attribute \src "issuer_ls180.v:119927.9-119927.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_s_opc$next[0:0]$4746 1'0 - case - assign $1\opc_l_s_opc$next[0:0]$4746 \cu_issue_i - end - sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$4745 - end - attribute \src "issuer_ls180.v:119935.3-119943.6" - process $proc$issuer_ls180.v:119935$4747 - assign { } { } - assign { } { } - assign $0\opc_l_r_opc$next[0:0]$4748 $1\opc_l_r_opc$next[0:0]$4749 - attribute \src "issuer_ls180.v:119936.5-119936.29" - switch \initial - attribute \src "issuer_ls180.v:119936.9-119936.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_r_opc$next[0:0]$4749 1'1 - case - assign $1\opc_l_r_opc$next[0:0]$4749 \req_done - end - sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$4748 - end - attribute \src "issuer_ls180.v:119944.3-119952.6" - process $proc$issuer_ls180.v:119944$4750 - assign { } { } - assign { } { } - assign $0\src_l_s_src$next[2:0]$4751 $1\src_l_s_src$next[2:0]$4752 - attribute \src "issuer_ls180.v:119945.5-119945.29" - switch \initial - attribute \src "issuer_ls180.v:119945.9-119945.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_s_src$next[2:0]$4752 3'000 - case - assign $1\src_l_s_src$next[2:0]$4752 { \cu_issue_i \cu_issue_i \cu_issue_i } - end - sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$4751 - end - attribute \src "issuer_ls180.v:119953.3-119961.6" - process $proc$issuer_ls180.v:119953$4753 - assign { } { } - assign { } { } - assign $0\src_l_r_src$next[2:0]$4754 $1\src_l_r_src$next[2:0]$4755 - attribute \src "issuer_ls180.v:119954.5-119954.29" - switch \initial - attribute \src "issuer_ls180.v:119954.9-119954.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_r_src$next[2:0]$4755 3'111 - case - assign $1\src_l_r_src$next[2:0]$4755 \reset_r - end - sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$4754 - end - attribute \src "issuer_ls180.v:119962.3-119970.6" - process $proc$issuer_ls180.v:119962$4756 - assign { } { } - assign { } { } - assign $0\req_l_s_req$next[3:0]$4757 $1\req_l_s_req$next[3:0]$4758 - attribute \src "issuer_ls180.v:119963.5-119963.29" - switch \initial - attribute \src "issuer_ls180.v:119963.9-119963.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_s_req$next[3:0]$4758 4'0000 - case - assign $1\req_l_s_req$next[3:0]$4758 \$66 - end - sync always - update \req_l_s_req$next $0\req_l_s_req$next[3:0]$4757 - end - attribute \src "issuer_ls180.v:119971.3-119979.6" - process $proc$issuer_ls180.v:119971$4759 - assign { } { } - assign { } { } - assign $0\req_l_r_req$next[3:0]$4760 $1\req_l_r_req$next[3:0]$4761 - attribute \src "issuer_ls180.v:119972.5-119972.29" - switch \initial - attribute \src "issuer_ls180.v:119972.9-119972.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_r_req$next[3:0]$4761 4'1111 - case - assign $1\req_l_r_req$next[3:0]$4761 \$68 - end - sync always - update \req_l_r_req$next $0\req_l_r_req$next[3:0]$4760 - end - attribute \src "issuer_ls180.v:119980.3-120018.6" - process $proc$issuer_ls180.v:119980$4762 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_div0_logical_op__data_len$next[3:0]$4763 $1\alu_div0_logical_op__data_len$next[3:0]$4781 - assign $0\alu_div0_logical_op__fn_unit$next[11:0]$4764 $1\alu_div0_logical_op__fn_unit$next[11:0]$4782 - assign { } { } - assign { } { } - assign $0\alu_div0_logical_op__input_carry$next[1:0]$4767 $1\alu_div0_logical_op__input_carry$next[1:0]$4785 - assign $0\alu_div0_logical_op__insn$next[31:0]$4768 $1\alu_div0_logical_op__insn$next[31:0]$4786 - assign $0\alu_div0_logical_op__insn_type$next[6:0]$4769 $1\alu_div0_logical_op__insn_type$next[6:0]$4787 - assign $0\alu_div0_logical_op__invert_in$next[0:0]$4770 $1\alu_div0_logical_op__invert_in$next[0:0]$4788 - assign $0\alu_div0_logical_op__invert_out$next[0:0]$4771 $1\alu_div0_logical_op__invert_out$next[0:0]$4789 - assign $0\alu_div0_logical_op__is_32bit$next[0:0]$4772 $1\alu_div0_logical_op__is_32bit$next[0:0]$4790 - assign $0\alu_div0_logical_op__is_signed$next[0:0]$4773 $1\alu_div0_logical_op__is_signed$next[0:0]$4791 - assign { } { } - assign { } { } - assign $0\alu_div0_logical_op__output_carry$next[0:0]$4776 $1\alu_div0_logical_op__output_carry$next[0:0]$4794 - assign { } { } - assign { } { } - assign $0\alu_div0_logical_op__write_cr0$next[0:0]$4779 $1\alu_div0_logical_op__write_cr0$next[0:0]$4797 - assign $0\alu_div0_logical_op__zero_a$next[0:0]$4780 $1\alu_div0_logical_op__zero_a$next[0:0]$4798 - assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$4765 $2\alu_div0_logical_op__imm_data__data$next[63:0]$4799 - assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$4766 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4800 - assign $0\alu_div0_logical_op__oe__oe$next[0:0]$4774 $2\alu_div0_logical_op__oe__oe$next[0:0]$4801 - assign $0\alu_div0_logical_op__oe__ok$next[0:0]$4775 $2\alu_div0_logical_op__oe__ok$next[0:0]$4802 - assign $0\alu_div0_logical_op__rc__ok$next[0:0]$4777 $2\alu_div0_logical_op__rc__ok$next[0:0]$4803 - assign $0\alu_div0_logical_op__rc__rc$next[0:0]$4778 $2\alu_div0_logical_op__rc__rc$next[0:0]$4804 - attribute \src "issuer_ls180.v:119981.5-119981.29" - switch \initial - attribute \src "issuer_ls180.v:119981.9-119981.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_div0_logical_op__insn$next[31:0]$4786 $1\alu_div0_logical_op__data_len$next[3:0]$4781 $1\alu_div0_logical_op__is_signed$next[0:0]$4791 $1\alu_div0_logical_op__is_32bit$next[0:0]$4790 $1\alu_div0_logical_op__output_carry$next[0:0]$4794 $1\alu_div0_logical_op__write_cr0$next[0:0]$4797 $1\alu_div0_logical_op__invert_out$next[0:0]$4789 $1\alu_div0_logical_op__input_carry$next[1:0]$4785 $1\alu_div0_logical_op__zero_a$next[0:0]$4798 $1\alu_div0_logical_op__invert_in$next[0:0]$4788 $1\alu_div0_logical_op__oe__ok$next[0:0]$4793 $1\alu_div0_logical_op__oe__oe$next[0:0]$4792 $1\alu_div0_logical_op__rc__ok$next[0:0]$4795 $1\alu_div0_logical_op__rc__rc$next[0:0]$4796 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4784 $1\alu_div0_logical_op__imm_data__data$next[63:0]$4783 $1\alu_div0_logical_op__fn_unit$next[11:0]$4782 $1\alu_div0_logical_op__insn_type$next[6:0]$4787 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } - case - assign $1\alu_div0_logical_op__data_len$next[3:0]$4781 \alu_div0_logical_op__data_len - assign $1\alu_div0_logical_op__fn_unit$next[11:0]$4782 \alu_div0_logical_op__fn_unit - assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$4783 \alu_div0_logical_op__imm_data__data - assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4784 \alu_div0_logical_op__imm_data__ok - assign $1\alu_div0_logical_op__input_carry$next[1:0]$4785 \alu_div0_logical_op__input_carry - assign $1\alu_div0_logical_op__insn$next[31:0]$4786 \alu_div0_logical_op__insn - assign $1\alu_div0_logical_op__insn_type$next[6:0]$4787 \alu_div0_logical_op__insn_type - assign $1\alu_div0_logical_op__invert_in$next[0:0]$4788 \alu_div0_logical_op__invert_in - assign $1\alu_div0_logical_op__invert_out$next[0:0]$4789 \alu_div0_logical_op__invert_out - assign $1\alu_div0_logical_op__is_32bit$next[0:0]$4790 \alu_div0_logical_op__is_32bit - assign $1\alu_div0_logical_op__is_signed$next[0:0]$4791 \alu_div0_logical_op__is_signed - assign $1\alu_div0_logical_op__oe__oe$next[0:0]$4792 \alu_div0_logical_op__oe__oe - assign $1\alu_div0_logical_op__oe__ok$next[0:0]$4793 \alu_div0_logical_op__oe__ok - assign $1\alu_div0_logical_op__output_carry$next[0:0]$4794 \alu_div0_logical_op__output_carry - assign $1\alu_div0_logical_op__rc__ok$next[0:0]$4795 \alu_div0_logical_op__rc__ok - assign $1\alu_div0_logical_op__rc__rc$next[0:0]$4796 \alu_div0_logical_op__rc__rc - assign $1\alu_div0_logical_op__write_cr0$next[0:0]$4797 \alu_div0_logical_op__write_cr0 - assign $1\alu_div0_logical_op__zero_a$next[0:0]$4798 \alu_div0_logical_op__zero_a - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$4799 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4800 1'0 - assign $2\alu_div0_logical_op__rc__rc$next[0:0]$4804 1'0 - assign $2\alu_div0_logical_op__rc__ok$next[0:0]$4803 1'0 - assign $2\alu_div0_logical_op__oe__oe$next[0:0]$4801 1'0 - assign $2\alu_div0_logical_op__oe__ok$next[0:0]$4802 1'0 - case - assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$4799 $1\alu_div0_logical_op__imm_data__data$next[63:0]$4783 - assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4800 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4784 - assign $2\alu_div0_logical_op__oe__oe$next[0:0]$4801 $1\alu_div0_logical_op__oe__oe$next[0:0]$4792 - assign $2\alu_div0_logical_op__oe__ok$next[0:0]$4802 $1\alu_div0_logical_op__oe__ok$next[0:0]$4793 - assign $2\alu_div0_logical_op__rc__ok$next[0:0]$4803 $1\alu_div0_logical_op__rc__ok$next[0:0]$4795 - assign $2\alu_div0_logical_op__rc__rc$next[0:0]$4804 $1\alu_div0_logical_op__rc__rc$next[0:0]$4796 - end - sync always - update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$4763 - update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[11:0]$4764 - update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$4765 - update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$4766 - update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$4767 - update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$4768 - update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$4769 - update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$4770 - update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$4771 - update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$4772 - update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$4773 - update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$4774 - update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$4775 - update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$4776 - update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$4777 - update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$4778 - update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$4779 - update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$4780 - end - attribute \src "issuer_ls180.v:120019.3-120040.6" - process $proc$issuer_ls180.v:120019$4805 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r0__o$next[63:0]$4806 $2\data_r0__o$next[63:0]$4810 - assign { } { } - assign $0\data_r0__o_ok$next[0:0]$4807 $3\data_r0__o_ok$next[0:0]$4812 - attribute \src "issuer_ls180.v:120020.5-120020.29" - switch \initial - attribute \src "issuer_ls180.v:120020.9-120020.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$4809 $1\data_r0__o$next[63:0]$4808 } { \o_ok \alu_div0_o } - case - assign $1\data_r0__o$next[63:0]$4808 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$4809 \data_r0__o_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$4811 $2\data_r0__o$next[63:0]$4810 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r0__o$next[63:0]$4810 $1\data_r0__o$next[63:0]$4808 - assign $2\data_r0__o_ok$next[0:0]$4811 $1\data_r0__o_ok$next[0:0]$4809 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r0__o_ok$next[0:0]$4812 1'0 - case - assign $3\data_r0__o_ok$next[0:0]$4812 $2\data_r0__o_ok$next[0:0]$4811 - end - sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$4806 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$4807 - end - attribute \src "issuer_ls180.v:120041.3-120062.6" - process $proc$issuer_ls180.v:120041$4813 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r1__cr_a$next[3:0]$4814 $2\data_r1__cr_a$next[3:0]$4818 - assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$4815 $3\data_r1__cr_a_ok$next[0:0]$4820 - attribute \src "issuer_ls180.v:120042.5-120042.29" - switch \initial - attribute \src "issuer_ls180.v:120042.9-120042.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$4817 $1\data_r1__cr_a$next[3:0]$4816 } { \cr_a_ok \alu_div0_cr_a } - case - assign $1\data_r1__cr_a$next[3:0]$4816 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$4817 \data_r1__cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$4819 $2\data_r1__cr_a$next[3:0]$4818 } 5'00000 - case - assign $2\data_r1__cr_a$next[3:0]$4818 $1\data_r1__cr_a$next[3:0]$4816 - assign $2\data_r1__cr_a_ok$next[0:0]$4819 $1\data_r1__cr_a_ok$next[0:0]$4817 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$4820 1'0 - case - assign $3\data_r1__cr_a_ok$next[0:0]$4820 $2\data_r1__cr_a_ok$next[0:0]$4819 - end - sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$4814 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$4815 - end - attribute \src "issuer_ls180.v:120063.3-120084.6" - process $proc$issuer_ls180.v:120063$4821 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r2__xer_ov$next[1:0]$4822 $2\data_r2__xer_ov$next[1:0]$4826 - assign { } { } - assign $0\data_r2__xer_ov_ok$next[0:0]$4823 $3\data_r2__xer_ov_ok$next[0:0]$4828 - attribute \src "issuer_ls180.v:120064.5-120064.29" - switch \initial - attribute \src "issuer_ls180.v:120064.9-120064.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r2__xer_ov_ok$next[0:0]$4825 $1\data_r2__xer_ov$next[1:0]$4824 } { \xer_ov_ok \alu_div0_xer_ov } - case - assign $1\data_r2__xer_ov$next[1:0]$4824 \data_r2__xer_ov - assign $1\data_r2__xer_ov_ok$next[0:0]$4825 \data_r2__xer_ov_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r2__xer_ov_ok$next[0:0]$4827 $2\data_r2__xer_ov$next[1:0]$4826 } 3'000 - case - assign $2\data_r2__xer_ov$next[1:0]$4826 $1\data_r2__xer_ov$next[1:0]$4824 - assign $2\data_r2__xer_ov_ok$next[0:0]$4827 $1\data_r2__xer_ov_ok$next[0:0]$4825 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r2__xer_ov_ok$next[0:0]$4828 1'0 - case - assign $3\data_r2__xer_ov_ok$next[0:0]$4828 $2\data_r2__xer_ov_ok$next[0:0]$4827 - end - sync always - update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$4822 - update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$4823 - end - attribute \src "issuer_ls180.v:120085.3-120106.6" - process $proc$issuer_ls180.v:120085$4829 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r3__xer_so$next[0:0]$4830 $2\data_r3__xer_so$next[0:0]$4834 - assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$4831 $3\data_r3__xer_so_ok$next[0:0]$4836 - attribute \src "issuer_ls180.v:120086.5-120086.29" - switch \initial - attribute \src "issuer_ls180.v:120086.9-120086.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$4833 $1\data_r3__xer_so$next[0:0]$4832 } { \xer_so_ok \alu_div0_xer_so } - case - assign $1\data_r3__xer_so$next[0:0]$4832 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$4833 \data_r3__xer_so_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$4835 $2\data_r3__xer_so$next[0:0]$4834 } 2'00 - case - assign $2\data_r3__xer_so$next[0:0]$4834 $1\data_r3__xer_so$next[0:0]$4832 - assign $2\data_r3__xer_so_ok$next[0:0]$4835 $1\data_r3__xer_so_ok$next[0:0]$4833 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$4836 1'0 - case - assign $3\data_r3__xer_so_ok$next[0:0]$4836 $2\data_r3__xer_so_ok$next[0:0]$4835 - end - sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$4830 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$4831 - end - attribute \src "issuer_ls180.v:120107.3-120116.6" - process $proc$issuer_ls180.v:120107$4837 - assign { } { } - assign { } { } - assign $0\src_r0$next[63:0]$4838 $1\src_r0$next[63:0]$4839 - attribute \src "issuer_ls180.v:120108.5-120108.29" - switch \initial - attribute \src "issuer_ls180.v:120108.9-120108.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r0$next[63:0]$4839 \src_or_imm - case - assign $1\src_r0$next[63:0]$4839 \src_r0 - end - sync always - update \src_r0$next $0\src_r0$next[63:0]$4838 - end - attribute \src "issuer_ls180.v:120117.3-120126.6" - process $proc$issuer_ls180.v:120117$4840 - assign { } { } - assign { } { } - assign $0\src_r1$next[63:0]$4841 $1\src_r1$next[63:0]$4842 - attribute \src "issuer_ls180.v:120118.5-120118.29" - switch \initial - attribute \src "issuer_ls180.v:120118.9-120118.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_sel$82 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r1$next[63:0]$4842 \src_or_imm$85 - case - assign $1\src_r1$next[63:0]$4842 \src_r1 - end - sync always - update \src_r1$next $0\src_r1$next[63:0]$4841 - end - attribute \src "issuer_ls180.v:120127.3-120136.6" - process $proc$issuer_ls180.v:120127$4843 - assign { } { } - assign { } { } - assign $0\src_r2$next[0:0]$4844 $1\src_r2$next[0:0]$4845 - attribute \src "issuer_ls180.v:120128.5-120128.29" - switch \initial - attribute \src "issuer_ls180.v:120128.9-120128.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r2$next[0:0]$4845 \src3_i - case - assign $1\src_r2$next[0:0]$4845 \src_r2 - end - sync always - update \src_r2$next $0\src_r2$next[0:0]$4844 - end - attribute \src "issuer_ls180.v:120137.3-120145.6" - process $proc$issuer_ls180.v:120137$4846 - assign { } { } - assign { } { } - assign $0\alui_l_r_alui$next[0:0]$4847 $1\alui_l_r_alui$next[0:0]$4848 - attribute \src "issuer_ls180.v:120138.5-120138.29" - switch \initial - attribute \src "issuer_ls180.v:120138.9-120138.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alui_l_r_alui$next[0:0]$4848 1'1 - case - assign $1\alui_l_r_alui$next[0:0]$4848 \$94 - end - sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$4847 - end - attribute \src "issuer_ls180.v:120146.3-120154.6" - process $proc$issuer_ls180.v:120146$4849 - assign { } { } - assign { } { } - assign $0\alu_l_r_alu$next[0:0]$4850 $1\alu_l_r_alu$next[0:0]$4851 - attribute \src "issuer_ls180.v:120147.5-120147.29" - switch \initial - attribute \src "issuer_ls180.v:120147.9-120147.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alu_l_r_alu$next[0:0]$4851 1'1 - case - assign $1\alu_l_r_alu$next[0:0]$4851 \$96 - end - sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$4850 - end - attribute \src "issuer_ls180.v:120155.3-120164.6" - process $proc$issuer_ls180.v:120155$4852 - assign { } { } - assign { } { } - assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "issuer_ls180.v:120156.5-120156.29" - switch \initial - attribute \src "issuer_ls180.v:120156.9-120156.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$122 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest1_o[63:0] \data_r0__o - case - assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest1_o $0\dest1_o[63:0] - end - attribute \src "issuer_ls180.v:120165.3-120174.6" - process $proc$issuer_ls180.v:120165$4853 - assign { } { } - assign { } { } - assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "issuer_ls180.v:120166.5-120166.29" - switch \initial - attribute \src "issuer_ls180.v:120166.9-120166.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$124 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest2_o[3:0] \data_r1__cr_a - case - assign $1\dest2_o[3:0] 4'0000 - end - sync always - update \dest2_o $0\dest2_o[3:0] - end - attribute \src "issuer_ls180.v:120175.3-120184.6" - process $proc$issuer_ls180.v:120175$4854 - assign { } { } - assign { } { } - assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "issuer_ls180.v:120176.5-120176.29" - switch \initial - attribute \src "issuer_ls180.v:120176.9-120176.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$126 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest3_o[1:0] \data_r2__xer_ov - case - assign $1\dest3_o[1:0] 2'00 - end - sync always - update \dest3_o $0\dest3_o[1:0] - end - attribute \src "issuer_ls180.v:120185.3-120194.6" - process $proc$issuer_ls180.v:120185$4855 - assign { } { } - assign { } { } - assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "issuer_ls180.v:120186.5-120186.29" - switch \initial - attribute \src "issuer_ls180.v:120186.9-120186.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$128 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest4_o[0:0] \data_r3__xer_so - case - assign $1\dest4_o[0:0] 1'0 - end - sync always - update \dest4_o $0\dest4_o[0:0] - end - attribute \src "issuer_ls180.v:120195.3-120203.6" - process $proc$issuer_ls180.v:120195$4856 - assign { } { } - assign { } { } - assign $0\prev_wr_go$next[3:0]$4857 $1\prev_wr_go$next[3:0]$4858 - attribute \src "issuer_ls180.v:120196.5-120196.29" - switch \initial - attribute \src "issuer_ls180.v:120196.9-120196.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\prev_wr_go$next[3:0]$4858 4'0000 - case - assign $1\prev_wr_go$next[3:0]$4858 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[3:0]$4857 - end - connect \$100 $not$issuer_ls180.v:119644$4624_Y - connect \$102 $not$issuer_ls180.v:119645$4625_Y - connect \$104 $and$issuer_ls180.v:119646$4626_Y - connect \$106 $not$issuer_ls180.v:119647$4627_Y - connect \$108 $and$issuer_ls180.v:119648$4628_Y - connect \$10 $and$issuer_ls180.v:119649$4629_Y - connect \$110 $and$issuer_ls180.v:119650$4630_Y - connect \$112 $and$issuer_ls180.v:119651$4631_Y - connect \$114 $and$issuer_ls180.v:119652$4632_Y - connect \$116 $and$issuer_ls180.v:119653$4633_Y - connect \$118 $and$issuer_ls180.v:119654$4634_Y - connect \$120 $and$issuer_ls180.v:119655$4635_Y - connect \$122 $and$issuer_ls180.v:119656$4636_Y - connect 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\o_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" - wire width 7 output 1 \o_q_bits_known - connect \o_dividend_quotient \dividend - connect \o_q_bits_known 7'0000000 -end -attribute \src "issuer_ls180.v:120253.1-120335.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.div_state_next" -attribute \generator "nMigen" -module \div_state_next - attribute \src "issuer_ls180.v:120254.7-120254.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:120319.3-120330.6" - wire width 128 $0\o_dividend_quotient[127:0] - attribute \src "issuer_ls180.v:120307.3-120318.6" - wire width 7 $0\o_q_bits_known[6:0] - attribute \src "issuer_ls180.v:120295.3-120306.6" - wire width 128 $0\value[127:0] - attribute \src "issuer_ls180.v:120319.3-120330.6" - wire width 128 $1\o_dividend_quotient[127:0] - attribute \src "issuer_ls180.v:120307.3-120318.6" - wire width 7 $1\o_q_bits_known[6:0] - attribute \src "issuer_ls180.v:120295.3-120306.6" - wire width 128 $1\value[127:0] - attribute \src "issuer_ls180.v:120289.18-120289.106" - wire width 8 $add$issuer_ls180.v:120289$4904_Y - attribute \src "issuer_ls180.v:120290.18-120290.109" - wire $eq$issuer_ls180.v:120290$4905_Y - attribute \src "issuer_ls180.v:120294.17-120294.108" - wire $eq$issuer_ls180.v:120294$4909_Y - attribute \src "issuer_ls180.v:120293.17-120293.101" - wire $not$issuer_ls180.v:120293$4908_Y - attribute \src "issuer_ls180.v:120291.17-120291.101" - wire width 127 $sshl$issuer_ls180.v:120291$4906_Y - attribute \src "issuer_ls180.v:120292.17-120292.109" - wire width 129 $sub$issuer_ls180.v:120292$4907_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - wire width 129 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" - wire width 8 \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" - wire width 8 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:109" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - wire width 127 \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - wire width 129 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" - wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:109" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:64" - wire width 128 \difference - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:59" - wire width 64 input 4 \divisor - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" - wire width 128 input 3 \i_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" - wire width 7 input 2 \i_q_bits_known - attribute \src "issuer_ls180.v:120254.7-120254.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:68" - wire \next_quotient_bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" - wire width 128 output 5 \o_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" - wire width 7 output 1 \o_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:71" - wire width 128 \value - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" - cell $add $add$issuer_ls180.v:120289$4904 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \i_q_bits_known - connect \B 1'1 - connect \Y $add$issuer_ls180.v:120289$4904_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:109" - cell $eq $eq$issuer_ls180.v:120290$4905 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \i_q_bits_known - connect \B 7'1000000 - connect \Y $eq$issuer_ls180.v:120290$4905_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:109" - cell $eq $eq$issuer_ls180.v:120294$4909 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \i_q_bits_known - connect \B 7'1000000 - connect \Y $eq$issuer_ls180.v:120294$4909_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" - cell $not $not$issuer_ls180.v:120293$4908 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \difference [127] - connect \Y $not$issuer_ls180.v:120293$4908_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - cell $sshl $sshl$issuer_ls180.v:120291$4906 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 127 - connect \A \divisor - connect \B 6'111111 - connect \Y $sshl$issuer_ls180.v:120291$4906_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - cell $sub $sub$issuer_ls180.v:120292$4907 - parameter \A_SIGNED 0 - parameter \A_WIDTH 128 - parameter \B_SIGNED 0 - parameter \B_WIDTH 127 - parameter \Y_WIDTH 129 - connect \A \i_dividend_quotient - connect \B \$2 - connect \Y $sub$issuer_ls180.v:120292$4907_Y - end - attribute \src "issuer_ls180.v:120254.7-120254.20" - process $proc$issuer_ls180.v:120254$4913 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:120295.3-120306.6" - process $proc$issuer_ls180.v:120295$4910 - assign { } { } - assign $0\value[127:0] $1\value[127:0] - attribute \src "issuer_ls180.v:120296.5-120296.29" - switch \initial - attribute \src "issuer_ls180.v:120296.9-120296.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:72" - switch \next_quotient_bit - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\value[127:0] \difference - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\value[127:0] \i_dividend_quotient - end - sync always - update \value $0\value[127:0] - end - attribute \src "issuer_ls180.v:120307.3-120318.6" - process $proc$issuer_ls180.v:120307$4911 - assign { } { } - assign $0\o_q_bits_known[6:0] $1\o_q_bits_known[6:0] - attribute \src "issuer_ls180.v:120308.5-120308.29" - switch \initial - attribute \src "issuer_ls180.v:120308.9-120308.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" - switch \$8 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\o_q_bits_known[6:0] \i_q_bits_known - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\o_q_bits_known[6:0] \$10 [6:0] - end - sync always - update \o_q_bits_known $0\o_q_bits_known[6:0] - end - attribute \src "issuer_ls180.v:120319.3-120330.6" - process $proc$issuer_ls180.v:120319$4912 - assign { } { } - assign $0\o_dividend_quotient[127:0] $1\o_dividend_quotient[127:0] - attribute \src "issuer_ls180.v:120320.5-120320.29" - switch \initial - attribute \src "issuer_ls180.v:120320.9-120320.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" - switch \$13 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\o_dividend_quotient[127:0] \i_dividend_quotient - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\o_dividend_quotient[127:0] { \value [126:0] \next_quotient_bit } - end - sync always - update \o_dividend_quotient $0\o_dividend_quotient[127:0] - end - connect \$11 $add$issuer_ls180.v:120289$4904_Y - connect \$13 $eq$issuer_ls180.v:120290$4905_Y - connect \$2 $sshl$issuer_ls180.v:120291$4906_Y - connect \$4 $sub$issuer_ls180.v:120292$4907_Y - connect \$6 $not$issuer_ls180.v:120293$4908_Y - connect \$8 $eq$issuer_ls180.v:120294$4909_Y - connect \$1 \$4 - connect \$10 \$11 - connect \next_quotient_bit \$6 - connect \difference \$4 [127:0] -end -attribute \src "issuer_ls180.v:120339.1-120510.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fast" -attribute \generator "nMigen" -module \fast - attribute \src "issuer_ls180.v:120434.3-120440.6" - wire width 3 $0$memwr$\memory$issuer_ls180.v:120438$4922_ADDR[2:0]$4930 - attribute \src "issuer_ls180.v:120434.3-120440.6" - wire width 64 $0$memwr$\memory$issuer_ls180.v:120438$4922_DATA[63:0]$4931 - attribute \src "issuer_ls180.v:120434.3-120440.6" - wire width 64 $0$memwr$\memory$issuer_ls180.v:120438$4922_EN[63:0]$4932 - attribute \src "issuer_ls180.v:120434.3-120440.6" - wire width 3 $0$memwr$\memory$issuer_ls180.v:120439$4923_ADDR[2:0]$4933 - attribute \src "issuer_ls180.v:120434.3-120440.6" - wire width 64 $0$memwr$\memory$issuer_ls180.v:120439$4923_DATA[63:0]$4934 - attribute \src "issuer_ls180.v:120434.3-120440.6" - wire width 64 $0$memwr$\memory$issuer_ls180.v:120439$4923_EN[63:0]$4935 - attribute \src "issuer_ls180.v:120434.3-120440.6" - wire width 3 $0\_0_[2:0] - attribute \src "issuer_ls180.v:120434.3-120440.6" - wire width 3 $0\_1_[2:0] - attribute \src "issuer_ls180.v:120434.3-120440.6" - wire width 3 $0\_2_[2:0] - attribute \src "issuer_ls180.v:120340.7-120340.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:120491.3-120500.6" - wire width 64 $0\issue__data_o[63:0] - attribute \src "issuer_ls180.v:120463.3-120471.6" - wire $0\ren_delay$10$next[0:0]$4944 - attribute \src "issuer_ls180.v:120416.3-120417.43" - wire $0\ren_delay$10[0:0]$4927 - attribute \src "issuer_ls180.v:120391.7-120391.28" - wire $0\ren_delay$10[0:0]$4964 - attribute \src "issuer_ls180.v:120482.3-120490.6" - wire $0\ren_delay$11$next[0:0]$4948 - attribute \src "issuer_ls180.v:120414.3-120415.43" - wire $0\ren_delay$11[0:0]$4925 - attribute \src "issuer_ls180.v:120395.7-120395.28" - wire $0\ren_delay$11[0:0]$4966 - attribute \src "issuer_ls180.v:120444.3-120452.6" - wire $0\ren_delay$next[0:0]$4940 - attribute \src "issuer_ls180.v:120418.3-120419.35" - wire $0\ren_delay[0:0] - attribute \src "issuer_ls180.v:120453.3-120462.6" - wire width 64 $0\src1__data_o[63:0] - attribute \src "issuer_ls180.v:120472.3-120481.6" - wire width 64 $0\src2__data_o[63:0] - attribute \src "issuer_ls180.v:120491.3-120500.6" - wire width 64 $1\issue__data_o[63:0] - attribute \src "issuer_ls180.v:120463.3-120471.6" - wire $1\ren_delay$10$next[0:0]$4945 - attribute \src "issuer_ls180.v:120482.3-120490.6" - wire $1\ren_delay$11$next[0:0]$4949 - attribute \src "issuer_ls180.v:120444.3-120452.6" - wire $1\ren_delay$next[0:0]$4941 - attribute \src "issuer_ls180.v:120389.7-120389.23" - wire $1\ren_delay[0:0] - attribute \src "issuer_ls180.v:120453.3-120462.6" - wire width 64 $1\src1__data_o[63:0] - attribute \src "issuer_ls180.v:120472.3-120481.6" - wire width 64 $1\src2__data_o[63:0] - attribute \src "issuer_ls180.v:120441.26-120441.32" - wire width 64 $memrd$\memory$issuer_ls180.v:120441$4936_DATA - attribute \src "issuer_ls180.v:120442.30-120442.36" - wire width 64 $memrd$\memory$issuer_ls180.v:120442$4937_DATA - attribute \src "issuer_ls180.v:120443.30-120443.36" - wire width 64 $memrd$\memory$issuer_ls180.v:120443$4938_DATA - attribute \src "issuer_ls180.v:0.0-0.0" - wire width 3 $memwr$\memory$issuer_ls180.v:120438$4922_ADDR - attribute \src "issuer_ls180.v:0.0-0.0" - wire width 64 $memwr$\memory$issuer_ls180.v:120438$4922_DATA - attribute \src "issuer_ls180.v:0.0-0.0" - wire width 64 $memwr$\memory$issuer_ls180.v:120438$4922_EN - attribute \src "issuer_ls180.v:0.0-0.0" - wire width 3 $memwr$\memory$issuer_ls180.v:120439$4923_ADDR - attribute \src "issuer_ls180.v:0.0-0.0" - wire width 64 $memwr$\memory$issuer_ls180.v:120439$4923_DATA - attribute \src "issuer_ls180.v:0.0-0.0" - wire width 64 $memwr$\memory$issuer_ls180.v:120439$4923_EN - attribute \src "issuer_ls180.v:120431.13-120431.16" - wire width 3 \_0_ - attribute \src "issuer_ls180.v:120432.13-120432.16" - wire width 3 \_1_ - attribute \src "issuer_ls180.v:120433.13-120433.16" - wire width 3 \_2_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 17 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 16 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 14 \dest1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 13 \dest1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \dest1__wen - attribute \src "issuer_ls180.v:120340.7-120340.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 1 \issue__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 4 \issue__addr$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 6 \issue__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \issue__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \issue__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 5 \issue__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 3 \memory_r_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 3 \memory_r_addr$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 3 \memory_r_addr$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 3 \memory_w_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 3 \memory_w_addr$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 64 \memory_w_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 64 \memory_w_data$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire \memory_w_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire \memory_w_en$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 8 \src1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 7 \src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 9 \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 11 \src2__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 10 \src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 12 \src2__ren - attribute \src "issuer_ls180.v:120420.14-120420.20" - memory width 64 size 8 \memory - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$4951 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 4951 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 0 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$4952 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 4952 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 1 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$4953 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 4953 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 2 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$4954 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 4954 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 3 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$4955 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 4955 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 4 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$4956 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 4956 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 5 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$4957 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 4957 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 6 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$4958 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 4958 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 7 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:120441.26-120441.32" - cell $memrd $memrd$\memory$issuer_ls180.v:120441$4936 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_0_ - connect \CLK 1'x - connect \DATA $memrd$\memory$issuer_ls180.v:120441$4936_DATA - connect \EN 1'x - end - attribute \src "issuer_ls180.v:120442.30-120442.36" - cell $memrd $memrd$\memory$issuer_ls180.v:120442$4937 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_1_ - connect \CLK 1'x - connect \DATA $memrd$\memory$issuer_ls180.v:120442$4937_DATA - connect \EN 1'x - end - attribute \src "issuer_ls180.v:120443.30-120443.36" - cell $memrd $memrd$\memory$issuer_ls180.v:120443$4938 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_2_ - connect \CLK 1'x - connect \DATA $memrd$\memory$issuer_ls180.v:120443$4938_DATA - connect \EN 1'x - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $memwr $memwr$\memory$issuer_ls180.v:0$4959 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \PRIORITY 4959 - parameter \WIDTH 64 - connect \ADDR $memwr$\memory$issuer_ls180.v:120438$4922_ADDR - connect \CLK 1'x - connect \DATA $memwr$\memory$issuer_ls180.v:120438$4922_DATA - connect \EN $memwr$\memory$issuer_ls180.v:120438$4922_EN - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $memwr $memwr$\memory$issuer_ls180.v:0$4960 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \PRIORITY 4960 - parameter \WIDTH 64 - connect \ADDR $memwr$\memory$issuer_ls180.v:120439$4923_ADDR - connect \CLK 1'x - connect \DATA $memwr$\memory$issuer_ls180.v:120439$4923_DATA - connect \EN $memwr$\memory$issuer_ls180.v:120439$4923_EN - end - attribute \src "issuer_ls180.v:0.0-0.0" - process $proc$issuer_ls180.v:0$4967 - sync always - sync init - end - attribute \src "issuer_ls180.v:120340.7-120340.20" - process $proc$issuer_ls180.v:120340$4961 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:120389.7-120389.23" - process $proc$issuer_ls180.v:120389$4962 - assign { } { } - assign $1\ren_delay[0:0] 1'0 - sync always - sync init - update \ren_delay $1\ren_delay[0:0] - end - attribute \src "issuer_ls180.v:120391.7-120391.28" - process $proc$issuer_ls180.v:120391$4963 - assign { } { } - assign $0\ren_delay$10[0:0]$4964 1'0 - sync always - sync init - update \ren_delay$10 $0\ren_delay$10[0:0]$4964 - end - attribute \src "issuer_ls180.v:120395.7-120395.28" - process $proc$issuer_ls180.v:120395$4965 - assign { } { } - assign $0\ren_delay$11[0:0]$4966 1'0 - sync always - sync init - update \ren_delay$11 $0\ren_delay$11[0:0]$4966 - end - attribute \src "issuer_ls180.v:120414.3-120415.43" - process $proc$issuer_ls180.v:120414$4924 - assign { } { } - assign $0\ren_delay$11[0:0]$4925 \ren_delay$11$next - sync posedge \coresync_clk - update \ren_delay$11 $0\ren_delay$11[0:0]$4925 - end - attribute \src "issuer_ls180.v:120416.3-120417.43" - process $proc$issuer_ls180.v:120416$4926 - assign { } { } - assign $0\ren_delay$10[0:0]$4927 \ren_delay$10$next - sync posedge \coresync_clk - update \ren_delay$10 $0\ren_delay$10[0:0]$4927 - end - attribute \src "issuer_ls180.v:120418.3-120419.35" - process $proc$issuer_ls180.v:120418$4928 - assign { } { } - assign $0\ren_delay[0:0] \ren_delay$next - sync posedge \coresync_clk - update \ren_delay $0\ren_delay[0:0] - end - attribute \src "issuer_ls180.v:120434.3-120440.6" - process $proc$issuer_ls180.v:120434$4929 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\memory$issuer_ls180.v:120439$4923_ADDR[2:0]$4933 3'xxx - assign $0$memwr$\memory$issuer_ls180.v:120439$4923_DATA[63:0]$4934 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$issuer_ls180.v:120439$4923_EN[63:0]$4935 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\memory$issuer_ls180.v:120438$4922_ADDR[2:0]$4930 3'xxx - assign $0$memwr$\memory$issuer_ls180.v:120438$4922_DATA[63:0]$4931 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$issuer_ls180.v:120438$4922_EN[63:0]$4932 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\_0_[2:0] \src1__addr - assign $0\_1_[2:0] \src2__addr - assign $0\_2_[2:0] \issue__addr - attribute \src "issuer_ls180.v:120438.5-120438.62" - switch \issue__wen - attribute \src "issuer_ls180.v:120438.9-120438.19" - case 1'1 - assign $0$memwr$\memory$issuer_ls180.v:120438$4922_ADDR[2:0]$4930 \issue__addr$1 - assign $0$memwr$\memory$issuer_ls180.v:120438$4922_DATA[63:0]$4931 \issue__data_i - assign $0$memwr$\memory$issuer_ls180.v:120438$4922_EN[63:0]$4932 64'1111111111111111111111111111111111111111111111111111111111111111 - case - end - attribute \src "issuer_ls180.v:120439.5-120439.58" - switch \dest1__wen - attribute \src "issuer_ls180.v:120439.9-120439.19" - case 1'1 - assign $0$memwr$\memory$issuer_ls180.v:120439$4923_ADDR[2:0]$4933 \dest1__addr - assign $0$memwr$\memory$issuer_ls180.v:120439$4923_DATA[63:0]$4934 \dest1__data_i - assign $0$memwr$\memory$issuer_ls180.v:120439$4923_EN[63:0]$4935 64'1111111111111111111111111111111111111111111111111111111111111111 - case - end - sync posedge \coresync_clk - update \_0_ $0\_0_[2:0] - update \_1_ $0\_1_[2:0] - update \_2_ $0\_2_[2:0] - update $memwr$\memory$issuer_ls180.v:120438$4922_ADDR $0$memwr$\memory$issuer_ls180.v:120438$4922_ADDR[2:0]$4930 - update $memwr$\memory$issuer_ls180.v:120438$4922_DATA $0$memwr$\memory$issuer_ls180.v:120438$4922_DATA[63:0]$4931 - update $memwr$\memory$issuer_ls180.v:120438$4922_EN $0$memwr$\memory$issuer_ls180.v:120438$4922_EN[63:0]$4932 - update $memwr$\memory$issuer_ls180.v:120439$4923_ADDR $0$memwr$\memory$issuer_ls180.v:120439$4923_ADDR[2:0]$4933 - update $memwr$\memory$issuer_ls180.v:120439$4923_DATA $0$memwr$\memory$issuer_ls180.v:120439$4923_DATA[63:0]$4934 - update $memwr$\memory$issuer_ls180.v:120439$4923_EN $0$memwr$\memory$issuer_ls180.v:120439$4923_EN[63:0]$4935 - end - attribute \src "issuer_ls180.v:120444.3-120452.6" - process $proc$issuer_ls180.v:120444$4939 - assign { } { } - assign { } { } - assign $0\ren_delay$next[0:0]$4940 $1\ren_delay$next[0:0]$4941 - attribute \src "issuer_ls180.v:120445.5-120445.29" - switch \initial - attribute \src "issuer_ls180.v:120445.9-120445.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$next[0:0]$4941 1'0 - case - assign $1\ren_delay$next[0:0]$4941 \src1__ren - end - sync always - update \ren_delay$next $0\ren_delay$next[0:0]$4940 - end - attribute \src "issuer_ls180.v:120453.3-120462.6" - process $proc$issuer_ls180.v:120453$4942 - assign { } { } - assign { } { } - assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] - attribute \src "issuer_ls180.v:120454.5-120454.29" - switch \initial - attribute \src "issuer_ls180.v:120454.9-120454.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src1__data_o[63:0] \memory_r_data - case - assign $1\src1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \src1__data_o $0\src1__data_o[63:0] - end - attribute \src "issuer_ls180.v:120463.3-120471.6" - process $proc$issuer_ls180.v:120463$4943 - assign { } { } - assign { } { } - assign $0\ren_delay$10$next[0:0]$4944 $1\ren_delay$10$next[0:0]$4945 - attribute \src "issuer_ls180.v:120464.5-120464.29" - switch \initial - attribute \src "issuer_ls180.v:120464.9-120464.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$10$next[0:0]$4945 1'0 - case - assign $1\ren_delay$10$next[0:0]$4945 \src2__ren - end - sync always - update \ren_delay$10$next $0\ren_delay$10$next[0:0]$4944 - end - attribute \src "issuer_ls180.v:120472.3-120481.6" - process $proc$issuer_ls180.v:120472$4946 - assign { } { } - assign { } { } - assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] - attribute \src "issuer_ls180.v:120473.5-120473.29" - switch \initial - attribute \src "issuer_ls180.v:120473.9-120473.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src2__data_o[63:0] \memory_r_data$4 - case - assign $1\src2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \src2__data_o $0\src2__data_o[63:0] - end - attribute \src "issuer_ls180.v:120482.3-120490.6" - process $proc$issuer_ls180.v:120482$4947 - assign { } { } - assign { } { } - assign $0\ren_delay$11$next[0:0]$4948 $1\ren_delay$11$next[0:0]$4949 - attribute \src "issuer_ls180.v:120483.5-120483.29" - switch \initial - attribute \src "issuer_ls180.v:120483.9-120483.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$11$next[0:0]$4949 1'0 - case - assign $1\ren_delay$11$next[0:0]$4949 \issue__ren - end - sync always - update \ren_delay$11$next $0\ren_delay$11$next[0:0]$4948 - end - attribute \src "issuer_ls180.v:120491.3-120500.6" - process $proc$issuer_ls180.v:120491$4950 - assign { } { } - assign { } { } - assign $0\issue__data_o[63:0] $1\issue__data_o[63:0] - attribute \src "issuer_ls180.v:120492.5-120492.29" - switch \initial - attribute \src "issuer_ls180.v:120492.9-120492.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$11 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\issue__data_o[63:0] \memory_r_data$6 - case - assign $1\issue__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \issue__data_o $0\issue__data_o[63:0] - end - connect \memory_r_data $memrd$\memory$issuer_ls180.v:120441$4936_DATA - connect \memory_r_data$4 $memrd$\memory$issuer_ls180.v:120442$4937_DATA - connect \memory_r_data$6 $memrd$\memory$issuer_ls180.v:120443$4938_DATA - connect \memory_w_data$9 \issue__data_i - connect \memory_w_en$7 \issue__wen - connect \memory_w_addr$8 \issue__addr$1 - connect \memory_w_data \dest1__data_i - connect \memory_w_en \dest1__wen - connect \memory_w_addr \dest1__addr - connect \memory_r_addr$5 \issue__addr - connect \memory_r_addr$3 \src2__addr - connect \memory_r_addr \src1__addr -end -attribute \src "issuer_ls180.v:120514.1-122407.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus" -attribute \generator "nMigen" -module \fus - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 321 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 308 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 254 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 255 \cr_a_ok$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 256 \cr_a_ok$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 257 \cr_a_ok$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 258 \cr_a_ok$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 259 \cr_a_ok$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire input 2 \cu_ad__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire output 3 \cu_ad__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 24 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 73 \cu_busy_o$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 80 \cu_busy_o$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 101 \cu_busy_o$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 30 \cu_busy_o$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 116 \cu_busy_o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 135 \cu_busy_o$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 154 \cu_busy_o$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 41 \cu_busy_o$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 52 \cu_busy_o$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 23 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 29 \cu_issue_i$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 72 \cu_issue_i$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 79 \cu_issue_i$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 100 \cu_issue_i$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 115 \cu_issue_i$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 134 \cu_issue_i$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 153 \cu_issue_i$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 40 \cu_issue_i$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 51 \cu_issue_i$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 157 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 input 160 \cu_rd__go_i$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 163 \cu_rd__go_i$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 166 \cu_rd__go_i$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 input 169 \cu_rd__go_i$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 172 \cu_rd__go_i$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 175 \cu_rd__go_i$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 input 178 \cu_rd__go_i$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 181 \cu_rd__go_i$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 206 \cu_rd__go_i$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 156 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 output 159 \cu_rd__rel_o$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 162 \cu_rd__rel_o$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 165 \cu_rd__rel_o$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 output 168 \cu_rd__rel_o$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 171 \cu_rd__rel_o$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 174 \cu_rd__rel_o$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 output 177 \cu_rd__rel_o$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 180 \cu_rd__rel_o$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 205 \cu_rd__rel_o$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 4 input 25 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 74 \cu_rdmaskn_i$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 6 input 81 \cu_rdmaskn_i$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 102 \cu_rdmaskn_i$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 117 \cu_rdmaskn_i$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 5 input 136 \cu_rdmaskn_i$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 155 \cu_rdmaskn_i$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 6 input 31 \cu_rdmaskn_i$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 42 \cu_rdmaskn_i$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 4 input 53 \cu_rdmaskn_i$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire input 4 \cu_st__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire output 1 \cu_st__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 input 218 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 239 \cu_wr__go_i$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 input 241 \cu_wr__go_i$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 290 \cu_wr__go_i$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 221 \cu_wr__go_i$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 input 224 \cu_wr__go_i$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 input 227 \cu_wr__go_i$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 input 230 \cu_wr__go_i$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 233 \cu_wr__go_i$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 236 \cu_wr__go_i$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 output 217 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 output 240 \cu_wr__rel_o$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 289 \cu_wr__rel_o$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 220 \cu_wr__rel_o$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 output 223 \cu_wr__rel_o$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 output 226 \cu_wr__rel_o$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 output 229 \cu_wr__rel_o$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 232 \cu_wr__rel_o$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 235 \cu_wr__rel_o$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 238 \cu_wr__rel_o$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 242 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 243 \dest1_o$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 244 \dest1_o$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 245 \dest1_o$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 246 \dest1_o$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 247 \dest1_o$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 248 \dest1_o$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 249 \dest1_o$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 295 \dest1_o$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 32 output 253 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 260 \dest2_o$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 262 \dest2_o$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 263 \dest2_o$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 264 \dest2_o$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 265 \dest2_o$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 296 \dest2_o$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 298 \dest2_o$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 307 \dest2_o$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 261 \dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 269 \dest3_o$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 271 \dest3_o$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 278 \dest3_o$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 279 \dest3_o$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 297 \dest3_o$143 - attribute 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\enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 137 \oper_i_ldst_ldst0__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 146 \oper_i_ldst_ldst0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 147 \oper_i_ldst_ldst0__is_signed - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 151 \oper_i_ldst_ldst0__ldst_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 144 \oper_i_ldst_ldst0__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 145 \oper_i_ldst_ldst0__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 143 \oper_i_ldst_ldst0__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 142 \oper_i_ldst_ldst0__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 150 \oper_i_ldst_ldst0__sign_extend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 141 \oper_i_ldst_ldst0__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 306 \spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 158 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 161 \src1_i$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 164 \src1_i$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 167 \src1_i$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 170 \src1_i$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 173 \src1_i$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 176 \src1_i$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 179 \src1_i$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 182 \src1_i$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 210 \src1_i$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 183 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 184 \src2_i$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 185 \src2_i$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 186 \src2_i$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 187 \src2_i$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 188 \src2_i$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 189 \src2_i$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 190 \src2_i$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 213 \src2_i$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 215 \src2_i$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 191 \src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 192 \src3_i$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 193 \src3_i$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 194 \src3_i$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 196 \src3_i$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 197 \src3_i$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 32 input 203 \src3_i$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 207 \src3_i$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 211 \src3_i$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 212 \src3_i$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 195 \src4_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 198 \src4_i$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 199 \src4_i$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 204 \src4_i$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 214 \src4_i$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 201 \src5_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 202 \src5_i$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 208 \src5_i$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 200 \src6_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 209 \src6_i$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 266 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 267 \xer_ca_ok$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 268 \xer_ca_ok$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 272 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 273 \xer_ov_ok$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 274 \xer_ov_ok$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 275 \xer_ov_ok$126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 280 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 281 \xer_so_ok$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 282 \xer_so_ok$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 283 \xer_so_ok$131 - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:122048.8-122090.4" - cell \alu0 \alu0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a_ok \cr_a_ok - connect \cu_busy_o \cu_busy_o - connect \cu_issue_i \cu_issue_i - connect \cu_rd__go_i \cu_rd__go_i - connect \cu_rd__rel_o \cu_rd__rel_o - connect \cu_rdmaskn_i \cu_rdmaskn_i - connect \cu_wr__go_i \cu_wr__go_i - connect \cu_wr__rel_o \cu_wr__rel_o - connect \dest1_o \dest1_o - connect \dest2_o \dest2_o$115 - connect \dest3_o \dest3_o$122 - connect \dest4_o \dest4_o - connect \dest5_o \dest5_o$132 - connect \o_ok \o_ok - connect \oper_i_alu_alu0__data_len \oper_i_alu_alu0__data_len - connect \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__fn_unit - connect \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__imm_data__data - connect \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__ok - connect \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__input_carry - connect \oper_i_alu_alu0__insn \oper_i_alu_alu0__insn - connect \oper_i_alu_alu0__insn_type \oper_i_alu_alu0__insn_type - connect \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__invert_in - connect \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__invert_out - connect \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__is_32bit - connect \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_signed - connect \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__oe__oe - connect \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__ok - connect \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__output_carry - connect \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__ok - connect \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__rc__rc - connect \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__write_cr0 - connect \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__zero_a - connect \src1_i \src1_i - connect \src2_i \src2_i - connect \src3_i \src3_i$60 - connect \src4_i \src4_i$65 - connect \xer_ca_ok \xer_ca_ok - connect \xer_ov_ok \xer_ov_ok - connect \xer_so_ok \xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:122091.11-122118.4" - cell \branch0 \branch0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cu_busy_o \cu_busy_o$5 - connect \cu_issue_i \cu_issue_i$4 - connect \cu_rd__go_i \cu_rd__go_i$70 - connect \cu_rd__rel_o \cu_rd__rel_o$69 - connect \cu_rdmaskn_i \cu_rdmaskn_i$6 - connect \cu_wr__go_i \cu_wr__go_i$137 - connect \cu_wr__rel_o \cu_wr__rel_o$136 - connect \dest1_o \dest1_o$141 - connect \dest2_o \dest2_o$144 - connect \dest3_o \dest3_o$147 - connect \fast1_ok \fast1_ok - connect \fast2_ok \fast2_ok - connect \nia_ok \nia_ok - connect \oper_i_alu_branch0__cia \oper_i_alu_branch0__cia - connect \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__fn_unit - connect \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__imm_data__data - connect \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__ok - connect \oper_i_alu_branch0__insn \oper_i_alu_branch0__insn - connect \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__insn_type - connect \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__is_32bit - connect \oper_i_alu_branch0__lk \oper_i_alu_branch0__lk - connect \src1_i \src1_i$74 - connect \src2_i \src2_i$77 - connect \src3_i \src3_i$71 - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:122119.7-122144.4" - cell \cr0 \cr0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a_ok \cr_a_ok$110 - connect \cu_busy_o \cu_busy_o$2 - connect \cu_issue_i \cu_issue_i$1 - connect \cu_rd__go_i \cu_rd__go_i$29 - connect \cu_rd__rel_o \cu_rd__rel_o$28 - connect \cu_rdmaskn_i \cu_rdmaskn_i$3 - connect \cu_wr__go_i \cu_wr__go_i$82 - connect \cu_wr__rel_o \cu_wr__rel_o$81 - connect \dest1_o \dest1_o$103 - connect \dest2_o \dest2_o - connect \dest3_o \dest3_o - connect \full_cr_ok \full_cr_ok - connect \o_ok \o_ok$80 - connect \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__fn_unit - connect \oper_i_alu_cr0__insn \oper_i_alu_cr0__insn - connect \oper_i_alu_cr0__insn_type \oper_i_alu_cr0__insn_type - connect \src1_i \src1_i$30 - connect \src2_i \src2_i$52 - connect \src3_i \src3_i$67 - connect \src4_i \src4_i$68 - connect \src5_i \src5_i$72 - connect \src6_i \src6_i$73 - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:122145.8-122184.4" - cell \div0 \div0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a_ok \cr_a_ok$112 - connect \cu_busy_o \cu_busy_o$17 - connect \cu_issue_i \cu_issue_i$16 - connect \cu_rd__go_i \cu_rd__go_i$41 - connect \cu_rd__rel_o \cu_rd__rel_o$40 - connect \cu_rdmaskn_i \cu_rdmaskn_i$18 - connect \cu_wr__go_i \cu_wr__go_i$94 - connect \cu_wr__rel_o \cu_wr__rel_o$93 - connect \dest1_o \dest1_o$107 - connect \dest2_o \dest2_o$117 - connect \dest3_o \dest3_o$127 - connect \dest4_o \dest4_o$134 - connect \o_ok \o_ok$92 - connect \oper_i_alu_div0__data_len \oper_i_alu_div0__data_len - connect \oper_i_alu_div0__fn_unit \oper_i_alu_div0__fn_unit - connect \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__imm_data__data - connect \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__ok - connect \oper_i_alu_div0__input_carry \oper_i_alu_div0__input_carry - connect \oper_i_alu_div0__insn \oper_i_alu_div0__insn - connect \oper_i_alu_div0__insn_type \oper_i_alu_div0__insn_type - connect \oper_i_alu_div0__invert_in \oper_i_alu_div0__invert_in - connect \oper_i_alu_div0__invert_out \oper_i_alu_div0__invert_out - connect \oper_i_alu_div0__is_32bit \oper_i_alu_div0__is_32bit - connect \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_signed - connect \oper_i_alu_div0__oe__oe \oper_i_alu_div0__oe__oe - connect \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__ok - connect \oper_i_alu_div0__output_carry \oper_i_alu_div0__output_carry - connect \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__ok - connect \oper_i_alu_div0__rc__rc \oper_i_alu_div0__rc__rc - connect \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__write_cr0 - connect \oper_i_alu_div0__zero_a \oper_i_alu_div0__zero_a - connect \src1_i \src1_i$42 - connect \src2_i \src2_i$55 - connect \src3_i \src3_i$62 - connect \xer_ov_ok \xer_ov_ok$125 - connect \xer_so_ok \xer_so_ok$130 - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:122185.9-122232.4" - cell \ldst0 \ldst0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cu_ad__go_i \cu_ad__go_i - connect \cu_ad__rel_o \cu_ad__rel_o - connect \cu_busy_o \cu_busy_o$26 - connect \cu_issue_i \cu_issue_i$25 - connect \cu_rd__go_i \cu_rd__go_i$50 - connect \cu_rd__rel_o \cu_rd__rel_o$49 - connect \cu_rdmaskn_i \cu_rdmaskn_i$27 - connect \cu_st__go_i \cu_st__go_i - connect \cu_st__rel_o \cu_st__rel_o - connect \cu_wr__go_i \cu_wr__go_i$102 - connect \cu_wr__rel_o \cu_wr__rel_o$101 - connect \ea \ea - connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o - connect \ldst_port0_addr_i \ldst_port0_addr_i - connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok - connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o - connect \ldst_port0_busy_o \ldst_port0_busy_o - connect \ldst_port0_data_len \ldst_port0_data_len - connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i - connect \ldst_port0_is_st_i \ldst_port0_is_st_i - connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i \ldst_port0_st_data_i - connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok - connect \o \o - connect \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__byte_reverse - connect \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__data_len - connect \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__fn_unit - connect \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__imm_data__data - connect \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__ok - connect \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__insn - connect \oper_i_ldst_ldst0__insn_type \oper_i_ldst_ldst0__insn_type - connect \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__is_32bit - connect \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_signed - connect \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__ldst_mode - connect \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__oe__oe - connect \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__ok - connect \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__ok - connect \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__rc__rc - connect \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__sign_extend - connect \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__zero_a - connect \src1_i \src1_i$51 - connect \src2_i \src2_i$58 - connect \src3_i \src3_i$59 - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:122233.12-122268.4" - cell \logical0 \logical0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a_ok \cr_a_ok$111 - connect \cu_busy_o \cu_busy_o$11 - connect \cu_issue_i \cu_issue_i$10 - connect \cu_rd__go_i \cu_rd__go_i$35 - connect \cu_rd__rel_o \cu_rd__rel_o$34 - connect \cu_rdmaskn_i \cu_rdmaskn_i$12 - connect \cu_wr__go_i \cu_wr__go_i$88 - connect \cu_wr__rel_o \cu_wr__rel_o$87 - connect \dest1_o \dest1_o$105 - connect \dest2_o \dest2_o$116 - connect \o_ok \o_ok$86 - connect \oper_i_alu_logical0__data_len \oper_i_alu_logical0__data_len - connect \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__fn_unit - connect \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__imm_data__data - connect \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__ok - connect \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__input_carry - connect \oper_i_alu_logical0__insn \oper_i_alu_logical0__insn - connect \oper_i_alu_logical0__insn_type \oper_i_alu_logical0__insn_type - connect \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__invert_in - connect \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__invert_out - connect \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__is_32bit - connect \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_signed - connect \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__oe__oe - connect \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__ok - connect \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__output_carry - connect \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__ok - connect \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__rc__rc - connect \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__write_cr0 - connect \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__zero_a - connect \src1_i \src1_i$36 - connect \src2_i \src2_i$54 - connect \src3_i \src3_i$61 - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:122269.8-122302.4" - cell \mul0 \mul0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a_ok \cr_a_ok$113 - connect \cu_busy_o \cu_busy_o$20 - connect \cu_issue_i \cu_issue_i$19 - connect \cu_rd__go_i \cu_rd__go_i$44 - connect \cu_rd__rel_o \cu_rd__rel_o$43 - connect \cu_rdmaskn_i \cu_rdmaskn_i$21 - connect \cu_wr__go_i \cu_wr__go_i$97 - connect \cu_wr__rel_o \cu_wr__rel_o$96 - connect \dest1_o \dest1_o$108 - connect \dest2_o \dest2_o$118 - connect \dest3_o \dest3_o$128 - connect \dest4_o \dest4_o$135 - connect \o_ok \o_ok$95 - connect \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__fn_unit - connect \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__imm_data__data - connect \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__ok - connect \oper_i_alu_mul0__insn \oper_i_alu_mul0__insn - connect \oper_i_alu_mul0__insn_type \oper_i_alu_mul0__insn_type - connect \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__is_32bit - connect \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_signed - connect \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__oe__oe - connect \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__ok - connect \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__ok - connect \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__rc__rc - connect \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__write_cr0 - connect \src1_i \src1_i$45 - connect \src2_i \src2_i$56 - connect \src3_i \src3_i$63 - connect \xer_ov_ok \xer_ov_ok$126 - connect \xer_so_ok \xer_so_ok$131 - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:122303.13-122340.4" - cell \shiftrot0 \shiftrot0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a_ok \cr_a_ok$114 - connect \cu_busy_o \cu_busy_o$23 - connect \cu_issue_i \cu_issue_i$22 - connect \cu_rd__go_i \cu_rd__go_i$47 - connect \cu_rd__rel_o \cu_rd__rel_o$46 - connect \cu_rdmaskn_i \cu_rdmaskn_i$24 - connect \cu_wr__go_i \cu_wr__go_i$100 - connect \cu_wr__rel_o \cu_wr__rel_o$99 - connect \dest1_o \dest1_o$109 - connect \dest2_o \dest2_o$119 - connect \dest3_o \dest3_o$123 - connect \o_ok \o_ok$98 - connect \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__fn_unit - connect \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__imm_data__data - connect \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__ok - connect \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__input_carry - connect \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__input_cr - connect \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__insn - connect \oper_i_alu_shift_rot0__insn_type \oper_i_alu_shift_rot0__insn_type - connect \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__is_32bit - connect \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_signed - connect \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__oe__oe - connect \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__ok - connect \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__output_carry - connect \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__output_cr - connect \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__ok - connect \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__rc__rc - connect \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__write_cr0 - connect \src1_i \src1_i$48 - connect \src2_i \src2_i$57 - connect \src3_i \src3_i - connect \src4_i \src4_i$64 - connect \src5_i \src5_i - connect \xer_ca_ok \xer_ca_ok$121 - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:122341.8-122373.4" - cell \spr0 \spr0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cu_busy_o \cu_busy_o$14 - connect \cu_issue_i \cu_issue_i$13 - connect \cu_rd__go_i \cu_rd__go_i$38 - connect \cu_rd__rel_o \cu_rd__rel_o$37 - connect \cu_rdmaskn_i \cu_rdmaskn_i$15 - connect \cu_wr__go_i \cu_wr__go_i$91 - connect \cu_wr__rel_o \cu_wr__rel_o$90 - connect \dest1_o \dest1_o$106 - connect \dest2_o \dest2_o$150 - connect \dest3_o \dest3_o$143 - connect \dest4_o \dest4_o$133 - connect \dest5_o \dest5_o - connect \dest6_o \dest6_o - connect \fast1_ok \fast1_ok$139 - connect \o_ok \o_ok$89 - connect \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__fn_unit - connect \oper_i_alu_spr0__insn \oper_i_alu_spr0__insn - connect \oper_i_alu_spr0__insn_type \oper_i_alu_spr0__insn_type - connect \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__is_32bit - connect \spr1_ok \spr1_ok - connect \src1_i \src1_i$39 - connect \src2_i \src2_i$79 - connect \src3_i \src3_i$76 - connect \src4_i \src4_i - connect \src5_i \src5_i$66 - connect \src6_i \src6_i - connect \xer_ca_ok \xer_ca_ok$120 - connect \xer_ov_ok \xer_ov_ok$124 - connect \xer_so_ok \xer_so_ok$129 - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:122374.9-122406.4" - cell \trap0 \trap0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cu_busy_o \cu_busy_o$8 - connect \cu_issue_i \cu_issue_i$7 - connect \cu_rd__go_i \cu_rd__go_i$32 - connect \cu_rd__rel_o \cu_rd__rel_o$31 - connect \cu_rdmaskn_i \cu_rdmaskn_i$9 - connect \cu_wr__go_i \cu_wr__go_i$85 - connect \cu_wr__rel_o \cu_wr__rel_o$84 - connect \dest1_o \dest1_o$104 - connect \dest2_o \dest2_o$142 - connect \dest3_o \dest3_o$145 - connect \dest4_o \dest4_o$148 - connect \dest5_o \dest5_o$149 - connect \fast1_ok \fast1_ok$138 - connect \fast2_ok \fast2_ok$140 - connect \msr_ok \msr_ok - connect \nia_ok \nia_ok$146 - connect \o_ok \o_ok$83 - connect \oper_i_alu_trap0__cia \oper_i_alu_trap0__cia - connect \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__fn_unit - connect \oper_i_alu_trap0__insn \oper_i_alu_trap0__insn - connect \oper_i_alu_trap0__insn_type \oper_i_alu_trap0__insn_type - connect \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__is_32bit - connect \oper_i_alu_trap0__msr \oper_i_alu_trap0__msr - connect \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__trapaddr - connect \oper_i_alu_trap0__traptype \oper_i_alu_trap0__traptype - connect \src1_i \src1_i$33 - connect \src2_i \src2_i$53 - connect \src3_i \src3_i$75 - connect \src4_i \src4_i$78 - end -end -attribute \src "issuer_ls180.v:122411.1-122469.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.l0.idx_l" -attribute \generator "nMigen" -module \idx_l - attribute \src "issuer_ls180.v:122412.7-122412.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:122457.3-122465.6" - wire $0\q_int$next[0:0]$4978 - attribute \src "issuer_ls180.v:122455.3-122456.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:122457.3-122465.6" - wire $1\q_int$next[0:0]$4979 - attribute \src "issuer_ls180.v:122436.7-122436.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:122447.17-122447.96" - wire $and$issuer_ls180.v:122447$4968_Y - attribute \src "issuer_ls180.v:122452.17-122452.96" - wire $and$issuer_ls180.v:122452$4973_Y - attribute \src "issuer_ls180.v:122449.18-122449.95" - wire $not$issuer_ls180.v:122449$4970_Y - attribute \src "issuer_ls180.v:122451.17-122451.94" - wire $not$issuer_ls180.v:122451$4972_Y - attribute \src "issuer_ls180.v:122454.17-122454.94" - wire $not$issuer_ls180.v:122454$4975_Y - attribute \src "issuer_ls180.v:122448.18-122448.100" - wire $or$issuer_ls180.v:122448$4969_Y - attribute \src "issuer_ls180.v:122450.18-122450.101" - wire $or$issuer_ls180.v:122450$4971_Y - attribute \src "issuer_ls180.v:122453.17-122453.99" - wire $or$issuer_ls180.v:122453$4974_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:122412.7-122412.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 4 \r_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 3 \s_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:122447$4968 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:122447$4968_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:122452$4973 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:122452$4973_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:122449$4970 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_idx_l - connect \Y $not$issuer_ls180.v:122449$4970_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:122451$4972 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_idx_l - connect \Y $not$issuer_ls180.v:122451$4972_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:122454$4975 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_idx_l - connect \Y $not$issuer_ls180.v:122454$4975_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:122448$4969 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_idx_l - connect \Y $or$issuer_ls180.v:122448$4969_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:122450$4971 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_idx_l - connect \B \q_int - connect \Y $or$issuer_ls180.v:122450$4971_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:122453$4974 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_idx_l - connect \Y $or$issuer_ls180.v:122453$4974_Y - end - attribute \src "issuer_ls180.v:122412.7-122412.20" - process $proc$issuer_ls180.v:122412$4980 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:122436.7-122436.19" - process $proc$issuer_ls180.v:122436$4981 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:122455.3-122456.27" - process $proc$issuer_ls180.v:122455$4976 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:122457.3-122465.6" - process $proc$issuer_ls180.v:122457$4977 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$4978 $1\q_int$next[0:0]$4979 - attribute \src "issuer_ls180.v:122458.5-122458.29" - switch \initial - attribute \src "issuer_ls180.v:122458.9-122458.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$4979 1'0 - case - assign $1\q_int$next[0:0]$4979 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$4978 - end - connect \$9 $and$issuer_ls180.v:122447$4968_Y - connect \$11 $or$issuer_ls180.v:122448$4969_Y - connect \$13 $not$issuer_ls180.v:122449$4970_Y - connect \$15 $or$issuer_ls180.v:122450$4971_Y - connect \$1 $not$issuer_ls180.v:122451$4972_Y - connect \$3 $and$issuer_ls180.v:122452$4973_Y - connect \$5 $or$issuer_ls180.v:122453$4974_Y - connect \$7 $not$issuer_ls180.v:122454$4975_Y - connect \qlq_idx_l \$15 - connect \qn_idx_l \$13 - connect \q_idx_l \$11 -end -attribute \src "issuer_ls180.v:122473.1-122795.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.imem" -attribute \generator "nMigen" -module \imem - attribute \src "issuer_ls180.v:122752.3-122766.6" - wire width 45 $0\f_badaddr_o$next[44:0]$5044 - attribute \src "issuer_ls180.v:122613.3-122614.39" - wire width 45 $0\f_badaddr_o[44:0] - attribute \src "issuer_ls180.v:122767.3-122778.6" - wire $0\f_busy_o[0:0] - attribute \src "issuer_ls180.v:122734.3-122751.6" - wire $0\f_fetch_err_o$next[0:0]$5040 - attribute \src "issuer_ls180.v:122615.3-122616.43" - wire $0\f_fetch_err_o[0:0] - attribute \src "issuer_ls180.v:122779.3-122791.6" - wire width 64 $0\f_instr_o[63:0] - attribute \src "issuer_ls180.v:122716.3-122733.6" - wire width 45 $0\ibus__adr$next[44:0]$5036 - attribute \src "issuer_ls180.v:122617.3-122618.35" - wire width 45 $0\ibus__adr[44:0] - attribute \src "issuer_ls180.v:122627.3-122649.6" - wire $0\ibus__cyc$next[0:0]$5016 - attribute \src "issuer_ls180.v:122625.3-122626.35" - wire $0\ibus__cyc[0:0] - attribute \src "issuer_ls180.v:122673.3-122695.6" - wire width 8 $0\ibus__sel$next[7:0]$5026 - attribute \src "issuer_ls180.v:122621.3-122622.35" - wire width 8 $0\ibus__sel[7:0] - attribute \src "issuer_ls180.v:122650.3-122672.6" - wire $0\ibus__stb$next[0:0]$5021 - attribute \src "issuer_ls180.v:122623.3-122624.35" - wire $0\ibus__stb[0:0] - attribute \src "issuer_ls180.v:122696.3-122715.6" - wire width 64 $0\ibus_rdata$next[63:0]$5031 - attribute \src "issuer_ls180.v:122619.3-122620.37" - wire width 64 $0\ibus_rdata[63:0] - attribute \src "issuer_ls180.v:122474.7-122474.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:122752.3-122766.6" - wire width 45 $1\f_badaddr_o$next[44:0]$5045 - attribute \src "issuer_ls180.v:122538.14-122538.44" - wire width 45 $1\f_badaddr_o[44:0] - attribute \src "issuer_ls180.v:122767.3-122778.6" - wire $1\f_busy_o[0:0] - attribute \src "issuer_ls180.v:122734.3-122751.6" - wire $1\f_fetch_err_o$next[0:0]$5041 - attribute \src "issuer_ls180.v:122545.7-122545.27" - wire $1\f_fetch_err_o[0:0] - attribute \src "issuer_ls180.v:122779.3-122791.6" - wire width 64 $1\f_instr_o[63:0] - attribute \src "issuer_ls180.v:122716.3-122733.6" - wire width 45 $1\ibus__adr$next[44:0]$5037 - attribute \src "issuer_ls180.v:122559.14-122559.42" - wire width 45 $1\ibus__adr[44:0] - attribute \src "issuer_ls180.v:122627.3-122649.6" - wire $1\ibus__cyc$next[0:0]$5017 - attribute \src "issuer_ls180.v:122564.7-122564.23" - wire $1\ibus__cyc[0:0] - attribute \src "issuer_ls180.v:122673.3-122695.6" - wire width 8 $1\ibus__sel$next[7:0]$5027 - attribute \src "issuer_ls180.v:122573.13-122573.30" - wire width 8 $1\ibus__sel[7:0] - attribute \src "issuer_ls180.v:122650.3-122672.6" - wire $1\ibus__stb$next[0:0]$5022 - attribute \src "issuer_ls180.v:122578.7-122578.23" - wire $1\ibus__stb[0:0] - attribute \src "issuer_ls180.v:122696.3-122715.6" - wire width 64 $1\ibus_rdata$next[63:0]$5032 - attribute \src "issuer_ls180.v:122582.14-122582.47" - wire width 64 $1\ibus_rdata[63:0] - attribute \src "issuer_ls180.v:122752.3-122766.6" - wire width 45 $2\f_badaddr_o$next[44:0]$5046 - attribute \src "issuer_ls180.v:122734.3-122751.6" - wire $2\f_fetch_err_o$next[0:0]$5042 - attribute \src "issuer_ls180.v:122716.3-122733.6" - wire width 45 $2\ibus__adr$next[44:0]$5038 - attribute \src "issuer_ls180.v:122627.3-122649.6" - wire $2\ibus__cyc$next[0:0]$5018 - attribute \src "issuer_ls180.v:122673.3-122695.6" - wire width 8 $2\ibus__sel$next[7:0]$5028 - attribute \src "issuer_ls180.v:122650.3-122672.6" - wire $2\ibus__stb$next[0:0]$5023 - attribute \src "issuer_ls180.v:122696.3-122715.6" - wire width 64 $2\ibus_rdata$next[63:0]$5033 - attribute \src "issuer_ls180.v:122627.3-122649.6" - wire $3\ibus__cyc$next[0:0]$5019 - attribute \src "issuer_ls180.v:122673.3-122695.6" - wire width 8 $3\ibus__sel$next[7:0]$5029 - attribute \src "issuer_ls180.v:122650.3-122672.6" - wire $3\ibus__stb$next[0:0]$5024 - attribute \src "issuer_ls180.v:122696.3-122715.6" - wire width 64 $3\ibus_rdata$next[63:0]$5034 - attribute \src "issuer_ls180.v:122589.18-122589.110" - wire $and$issuer_ls180.v:122589$4984_Y - attribute \src "issuer_ls180.v:122595.18-122595.110" - wire $and$issuer_ls180.v:122595$4990_Y - attribute \src "issuer_ls180.v:122600.18-122600.110" - wire $and$issuer_ls180.v:122600$4995_Y - attribute \src "issuer_ls180.v:122603.17-122603.108" - wire $and$issuer_ls180.v:122603$4998_Y - attribute \src "issuer_ls180.v:122606.18-122606.110" - wire $and$issuer_ls180.v:122606$5001_Y - attribute \src "issuer_ls180.v:122607.18-122607.115" - wire $and$issuer_ls180.v:122607$5002_Y - attribute \src "issuer_ls180.v:122609.18-122609.115" - wire $and$issuer_ls180.v:122609$5004_Y - attribute \src "issuer_ls180.v:122588.18-122588.105" - wire $not$issuer_ls180.v:122588$4983_Y - attribute \src "issuer_ls180.v:122591.18-122591.105" - wire $not$issuer_ls180.v:122591$4986_Y - attribute \src "issuer_ls180.v:122592.17-122592.104" - wire $not$issuer_ls180.v:122592$4987_Y - attribute \src "issuer_ls180.v:122594.18-122594.105" - wire $not$issuer_ls180.v:122594$4989_Y - attribute \src "issuer_ls180.v:122597.18-122597.105" - wire $not$issuer_ls180.v:122597$4992_Y - attribute \src "issuer_ls180.v:122599.18-122599.105" - wire $not$issuer_ls180.v:122599$4994_Y - attribute \src "issuer_ls180.v:122602.18-122602.105" - wire $not$issuer_ls180.v:122602$4997_Y - attribute \src "issuer_ls180.v:122605.18-122605.105" - wire $not$issuer_ls180.v:122605$5000_Y - attribute \src "issuer_ls180.v:122608.18-122608.105" - wire $not$issuer_ls180.v:122608$5003_Y - attribute \src "issuer_ls180.v:122610.18-122610.105" - wire $not$issuer_ls180.v:122610$5005_Y - attribute \src "issuer_ls180.v:122612.17-122612.104" - wire $not$issuer_ls180.v:122612$5007_Y - attribute \src "issuer_ls180.v:122587.17-122587.103" - wire $or$issuer_ls180.v:122587$4982_Y - attribute \src "issuer_ls180.v:122590.18-122590.115" - wire $or$issuer_ls180.v:122590$4985_Y - attribute \src "issuer_ls180.v:122593.18-122593.106" - wire $or$issuer_ls180.v:122593$4988_Y - attribute \src "issuer_ls180.v:122596.18-122596.115" - wire $or$issuer_ls180.v:122596$4991_Y - attribute \src "issuer_ls180.v:122598.18-122598.106" - wire $or$issuer_ls180.v:122598$4993_Y - attribute \src "issuer_ls180.v:122601.18-122601.115" - wire $or$issuer_ls180.v:122601$4996_Y - attribute \src "issuer_ls180.v:122604.18-122604.106" - wire $or$issuer_ls180.v:122604$4999_Y - attribute \src "issuer_ls180.v:122611.17-122611.114" - wire $or$issuer_ls180.v:122611$5006_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire \$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire \$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - wire \$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" - wire \$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" - wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31" - wire \a_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" - wire width 48 input 1 \a_pc_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25" - wire \a_stall_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" - wire input 2 \a_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:140" - wire input 14 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" - wire width 45 \f_badaddr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" - wire width 45 \f_badaddr_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" - wire output 4 \f_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" - wire \f_fetch_err_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" - wire \f_fetch_err_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" - wire width 64 output 5 \f_instr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27" - wire \f_stall_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" - wire input 3 \f_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 8 \ibus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 output 13 \ibus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 \ibus__adr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 7 \ibus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire \ibus__cyc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 12 \ibus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 9 \ibus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 output 11 \ibus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 \ibus__sel$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 10 \ibus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire \ibus__stb$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59" - wire width 64 \ibus_rdata - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59" - wire width 64 \ibus_rdata$next - attribute \src "issuer_ls180.v:122474.7-122474.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:140" - wire input 6 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $and$issuer_ls180.v:122589$4984 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B \$11 - connect \Y $and$issuer_ls180.v:122589$4984_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $and$issuer_ls180.v:122595$4990 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B \$21 - connect \Y $and$issuer_ls180.v:122595$4990_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $and$issuer_ls180.v:122600$4995 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B \$31 - connect \Y $and$issuer_ls180.v:122600$4995_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $and$issuer_ls180.v:122603$4998 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B \$1 - connect \Y $and$issuer_ls180.v:122603$4998_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $and$issuer_ls180.v:122606$5001 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B \$41 - connect \Y $and$issuer_ls180.v:122606$5001_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - cell $and $and$issuer_ls180.v:122607$5002 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__cyc - connect \B \ibus__err - connect \Y $and$issuer_ls180.v:122607$5002_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - cell $and $and$issuer_ls180.v:122609$5004 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__cyc - connect \B \ibus__err - connect \Y $and$issuer_ls180.v:122609$5004_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $not$issuer_ls180.v:122588$4983 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$issuer_ls180.v:122588$4983_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $not $not$issuer_ls180.v:122591$4986 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $not$issuer_ls180.v:122591$4986_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $not$issuer_ls180.v:122592$4987 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$issuer_ls180.v:122592$4987_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $not$issuer_ls180.v:122594$4989 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$issuer_ls180.v:122594$4989_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $not $not$issuer_ls180.v:122597$4992 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $not$issuer_ls180.v:122597$4992_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $not$issuer_ls180.v:122599$4994 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$issuer_ls180.v:122599$4994_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $not $not$issuer_ls180.v:122602$4997 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $not$issuer_ls180.v:122602$4997_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $not$issuer_ls180.v:122605$5000 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$issuer_ls180.v:122605$5000_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" - cell $not $not$issuer_ls180.v:122608$5003 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_stall_i - connect \Y $not$issuer_ls180.v:122608$5003_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" - cell $not $not$issuer_ls180.v:122610$5005 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_stall_i - connect \Y $not$issuer_ls180.v:122610$5005_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $not $not$issuer_ls180.v:122612$5007 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $not$issuer_ls180.v:122612$5007_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $or$issuer_ls180.v:122587$4982 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \$7 - connect \Y $or$issuer_ls180.v:122587$4982_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $or$issuer_ls180.v:122590$4985 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $or$issuer_ls180.v:122590$4985_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $or$issuer_ls180.v:122593$4988 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$15 - connect \B \$17 - connect \Y $or$issuer_ls180.v:122593$4988_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $or$issuer_ls180.v:122596$4991 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $or$issuer_ls180.v:122596$4991_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $or$issuer_ls180.v:122598$4993 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$25 - connect \B \$27 - connect \Y $or$issuer_ls180.v:122598$4993_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $or$issuer_ls180.v:122601$4996 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $or$issuer_ls180.v:122601$4996_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $or$issuer_ls180.v:122604$4999 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$35 - connect \B \$37 - connect \Y $or$issuer_ls180.v:122604$4999_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $or$issuer_ls180.v:122611$5006 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $or$issuer_ls180.v:122611$5006_Y - end - attribute \src "issuer_ls180.v:122474.7-122474.20" - process $proc$issuer_ls180.v:122474$5049 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:122538.14-122538.44" - process $proc$issuer_ls180.v:122538$5050 - assign { } { } - assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 - sync always - sync init - update \f_badaddr_o $1\f_badaddr_o[44:0] - end - attribute \src "issuer_ls180.v:122545.7-122545.27" - process $proc$issuer_ls180.v:122545$5051 - assign { } { } - assign $1\f_fetch_err_o[0:0] 1'0 - sync always - sync init - update \f_fetch_err_o $1\f_fetch_err_o[0:0] - end - attribute \src "issuer_ls180.v:122559.14-122559.42" - process $proc$issuer_ls180.v:122559$5052 - assign { } { } - assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000 - sync always - sync init - update \ibus__adr $1\ibus__adr[44:0] - end - attribute \src "issuer_ls180.v:122564.7-122564.23" - process $proc$issuer_ls180.v:122564$5053 - assign { } { } - assign $1\ibus__cyc[0:0] 1'0 - sync always - sync init - update \ibus__cyc $1\ibus__cyc[0:0] - end - attribute \src "issuer_ls180.v:122573.13-122573.30" - process $proc$issuer_ls180.v:122573$5054 - assign { } { } - assign $1\ibus__sel[7:0] 8'00000000 - sync always - sync init - update \ibus__sel $1\ibus__sel[7:0] - end - attribute \src "issuer_ls180.v:122578.7-122578.23" - process $proc$issuer_ls180.v:122578$5055 - assign { } { } - assign $1\ibus__stb[0:0] 1'0 - sync always - sync init - update \ibus__stb $1\ibus__stb[0:0] - end - attribute \src "issuer_ls180.v:122582.14-122582.47" - process $proc$issuer_ls180.v:122582$5056 - assign { } { } - assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \ibus_rdata $1\ibus_rdata[63:0] - end - attribute \src "issuer_ls180.v:122613.3-122614.39" - process $proc$issuer_ls180.v:122613$5008 - assign { } { } - assign $0\f_badaddr_o[44:0] \f_badaddr_o$next - sync posedge \clk - update \f_badaddr_o $0\f_badaddr_o[44:0] - end - attribute \src "issuer_ls180.v:122615.3-122616.43" - process $proc$issuer_ls180.v:122615$5009 - assign { } { } - assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next - sync posedge \clk - update \f_fetch_err_o $0\f_fetch_err_o[0:0] - end - attribute \src "issuer_ls180.v:122617.3-122618.35" - process $proc$issuer_ls180.v:122617$5010 - assign { } { } - assign $0\ibus__adr[44:0] \ibus__adr$next - sync posedge \clk - update \ibus__adr $0\ibus__adr[44:0] - end - attribute \src "issuer_ls180.v:122619.3-122620.37" - process $proc$issuer_ls180.v:122619$5011 - assign { } { } - assign $0\ibus_rdata[63:0] \ibus_rdata$next - sync posedge \clk - update \ibus_rdata $0\ibus_rdata[63:0] - end - attribute \src "issuer_ls180.v:122621.3-122622.35" - process $proc$issuer_ls180.v:122621$5012 - assign { } { } - assign $0\ibus__sel[7:0] \ibus__sel$next - sync posedge \clk - update \ibus__sel $0\ibus__sel[7:0] - end - attribute \src "issuer_ls180.v:122623.3-122624.35" - process $proc$issuer_ls180.v:122623$5013 - assign { } { } - assign $0\ibus__stb[0:0] \ibus__stb$next - sync posedge \clk - update \ibus__stb $0\ibus__stb[0:0] - end - attribute \src "issuer_ls180.v:122625.3-122626.35" - process $proc$issuer_ls180.v:122625$5014 - assign { } { } - assign $0\ibus__cyc[0:0] \ibus__cyc$next - sync posedge \clk - update \ibus__cyc $0\ibus__cyc[0:0] - end - attribute \src "issuer_ls180.v:122627.3-122649.6" - process $proc$issuer_ls180.v:122627$5015 - assign { } { } - assign { } { } - assign { } { } - assign $0\ibus__cyc$next[0:0]$5016 $3\ibus__cyc$next[0:0]$5019 - attribute \src "issuer_ls180.v:122628.5-122628.29" - switch \initial - attribute \src "issuer_ls180.v:122628.9-122628.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { \$3 \ibus__cyc } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\ibus__cyc$next[0:0]$5017 $2\ibus__cyc$next[0:0]$5018 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - switch \$9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ibus__cyc$next[0:0]$5018 1'0 - case - assign $2\ibus__cyc$next[0:0]$5018 \ibus__cyc - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\ibus__cyc$next[0:0]$5017 1'1 - case - assign $1\ibus__cyc$next[0:0]$5017 \ibus__cyc - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ibus__cyc$next[0:0]$5019 1'0 - case - assign $3\ibus__cyc$next[0:0]$5019 $1\ibus__cyc$next[0:0]$5017 - end - sync always - update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5016 - end - attribute \src "issuer_ls180.v:122650.3-122672.6" - process $proc$issuer_ls180.v:122650$5020 - assign { } { } - assign { } { } - assign { } { } - assign $0\ibus__stb$next[0:0]$5021 $3\ibus__stb$next[0:0]$5024 - attribute \src "issuer_ls180.v:122651.5-122651.29" - switch \initial - attribute \src "issuer_ls180.v:122651.9-122651.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { \$13 \ibus__cyc } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\ibus__stb$next[0:0]$5022 $2\ibus__stb$next[0:0]$5023 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - switch \$19 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ibus__stb$next[0:0]$5023 1'0 - case - assign $2\ibus__stb$next[0:0]$5023 \ibus__stb - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\ibus__stb$next[0:0]$5022 1'1 - case - assign $1\ibus__stb$next[0:0]$5022 \ibus__stb - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ibus__stb$next[0:0]$5024 1'0 - case - assign $3\ibus__stb$next[0:0]$5024 $1\ibus__stb$next[0:0]$5022 - end - sync always - update \ibus__stb$next $0\ibus__stb$next[0:0]$5021 - end - attribute \src "issuer_ls180.v:122673.3-122695.6" - process $proc$issuer_ls180.v:122673$5025 - assign { } { } - assign { } { } - assign { } { } - assign $0\ibus__sel$next[7:0]$5026 $3\ibus__sel$next[7:0]$5029 - attribute \src "issuer_ls180.v:122674.5-122674.29" - switch \initial - attribute \src "issuer_ls180.v:122674.9-122674.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { \$23 \ibus__cyc } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\ibus__sel$next[7:0]$5027 $2\ibus__sel$next[7:0]$5028 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - switch \$29 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ibus__sel$next[7:0]$5028 8'00000000 - case - assign $2\ibus__sel$next[7:0]$5028 \ibus__sel - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\ibus__sel$next[7:0]$5027 8'11111111 - case - assign $1\ibus__sel$next[7:0]$5027 \ibus__sel - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ibus__sel$next[7:0]$5029 8'00000000 - case - assign $3\ibus__sel$next[7:0]$5029 $1\ibus__sel$next[7:0]$5027 - end - sync always - update \ibus__sel$next $0\ibus__sel$next[7:0]$5026 - end - attribute \src "issuer_ls180.v:122696.3-122715.6" - process $proc$issuer_ls180.v:122696$5030 - assign { } { } - assign { } { } - assign { } { } - assign $0\ibus_rdata$next[63:0]$5031 $3\ibus_rdata$next[63:0]$5034 - attribute \src "issuer_ls180.v:122697.5-122697.29" - switch \initial - attribute \src "issuer_ls180.v:122697.9-122697.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { \$33 \ibus__cyc } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\ibus_rdata$next[63:0]$5032 $2\ibus_rdata$next[63:0]$5033 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - switch \$39 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ibus_rdata$next[63:0]$5033 \ibus__dat_r - case - assign $2\ibus_rdata$next[63:0]$5033 \ibus_rdata - end - case - assign $1\ibus_rdata$next[63:0]$5032 \ibus_rdata - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ibus_rdata$next[63:0]$5034 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\ibus_rdata$next[63:0]$5034 $1\ibus_rdata$next[63:0]$5032 - end - sync always - update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5031 - end - attribute \src "issuer_ls180.v:122716.3-122733.6" - process $proc$issuer_ls180.v:122716$5035 - assign { } { } - assign { } { } - assign { } { } - assign $0\ibus__adr$next[44:0]$5036 $2\ibus__adr$next[44:0]$5038 - attribute \src "issuer_ls180.v:122717.5-122717.29" - switch \initial - attribute \src "issuer_ls180.v:122717.9-122717.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { \$43 \ibus__cyc } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign $1\ibus__adr$next[44:0]$5037 \ibus__adr - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\ibus__adr$next[44:0]$5037 \a_pc_i [47:3] - case - assign $1\ibus__adr$next[44:0]$5037 \ibus__adr - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ibus__adr$next[44:0]$5038 45'000000000000000000000000000000000000000000000 - case - assign $2\ibus__adr$next[44:0]$5038 $1\ibus__adr$next[44:0]$5037 - end - sync always - update \ibus__adr$next $0\ibus__adr$next[44:0]$5036 - end - attribute \src "issuer_ls180.v:122734.3-122751.6" - process $proc$issuer_ls180.v:122734$5039 - assign { } { } - assign { } { } - assign { } { } - assign $0\f_fetch_err_o$next[0:0]$5040 $2\f_fetch_err_o$next[0:0]$5042 - attribute \src "issuer_ls180.v:122735.5-122735.29" - switch \initial - attribute \src "issuer_ls180.v:122735.9-122735.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - switch { \$47 \$45 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\f_fetch_err_o$next[0:0]$5041 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\f_fetch_err_o$next[0:0]$5041 1'0 - case - assign $1\f_fetch_err_o$next[0:0]$5041 \f_fetch_err_o - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\f_fetch_err_o$next[0:0]$5042 1'0 - case - assign $2\f_fetch_err_o$next[0:0]$5042 $1\f_fetch_err_o$next[0:0]$5041 - end - sync always - update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5040 - end - attribute \src "issuer_ls180.v:122752.3-122766.6" - process $proc$issuer_ls180.v:122752$5043 - assign { } { } - assign { } { } - assign { } { } - assign $0\f_badaddr_o$next[44:0]$5044 $2\f_badaddr_o$next[44:0]$5046 - attribute \src "issuer_ls180.v:122753.5-122753.29" - switch \initial - attribute \src "issuer_ls180.v:122753.9-122753.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - switch { \$51 \$49 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\f_badaddr_o$next[44:0]$5045 \ibus__adr - case - assign $1\f_badaddr_o$next[44:0]$5045 \f_badaddr_o - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\f_badaddr_o$next[44:0]$5046 45'000000000000000000000000000000000000000000000 - case - assign $2\f_badaddr_o$next[44:0]$5046 $1\f_badaddr_o$next[44:0]$5045 - end - sync always - update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5044 - end - attribute \src "issuer_ls180.v:122767.3-122778.6" - process $proc$issuer_ls180.v:122767$5047 - assign { } { } - assign $0\f_busy_o[0:0] $1\f_busy_o[0:0] - attribute \src "issuer_ls180.v:122768.5-122768.29" - switch \initial - attribute \src "issuer_ls180.v:122768.9-122768.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - switch \f_fetch_err_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\f_busy_o[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\f_busy_o[0:0] \ibus__cyc - end - sync always - update \f_busy_o $0\f_busy_o[0:0] - end - attribute \src "issuer_ls180.v:122779.3-122791.6" - process $proc$issuer_ls180.v:122779$5048 - assign { } { } - assign { } { } - assign $0\f_instr_o[63:0] $1\f_instr_o[63:0] - attribute \src "issuer_ls180.v:122780.5-122780.29" - switch \initial - attribute \src "issuer_ls180.v:122780.9-122780.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - switch \f_fetch_err_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign $1\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\f_instr_o[63:0] \ibus_rdata - end - sync always - update \f_instr_o $0\f_instr_o[63:0] - end - connect \$9 $or$issuer_ls180.v:122587$4982_Y - connect \$11 $not$issuer_ls180.v:122588$4983_Y - connect \$13 $and$issuer_ls180.v:122589$4984_Y - connect \$15 $or$issuer_ls180.v:122590$4985_Y - connect \$17 $not$issuer_ls180.v:122591$4986_Y - connect \$1 $not$issuer_ls180.v:122592$4987_Y - connect \$19 $or$issuer_ls180.v:122593$4988_Y - connect \$21 $not$issuer_ls180.v:122594$4989_Y - connect \$23 $and$issuer_ls180.v:122595$4990_Y - connect \$25 $or$issuer_ls180.v:122596$4991_Y - connect \$27 $not$issuer_ls180.v:122597$4992_Y - connect \$29 $or$issuer_ls180.v:122598$4993_Y - connect \$31 $not$issuer_ls180.v:122599$4994_Y - connect \$33 $and$issuer_ls180.v:122600$4995_Y - connect \$35 $or$issuer_ls180.v:122601$4996_Y - connect \$37 $not$issuer_ls180.v:122602$4997_Y - connect \$3 $and$issuer_ls180.v:122603$4998_Y - connect \$39 $or$issuer_ls180.v:122604$4999_Y - connect \$41 $not$issuer_ls180.v:122605$5000_Y - connect \$43 $and$issuer_ls180.v:122606$5001_Y - connect \$45 $and$issuer_ls180.v:122607$5002_Y - connect \$47 $not$issuer_ls180.v:122608$5003_Y - connect \$49 $and$issuer_ls180.v:122609$5004_Y - connect \$51 $not$issuer_ls180.v:122610$5005_Y - connect \$5 $or$issuer_ls180.v:122611$5006_Y - connect \$7 $not$issuer_ls180.v:122612$5007_Y - connect \a_stall_i 1'0 - connect \f_stall_i 1'0 - connect \a_busy_o \ibus__cyc -end -attribute \src "issuer_ls180.v:122799.1-123120.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1.input" -attribute \generator "nMigen" -module \input - attribute \src "issuer_ls180.v:123083.3-123094.6" - wire width 64 $0\a[63:0] - attribute \src "issuer_ls180.v:122800.7-122800.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:123095.3-123113.6" - wire width 2 $0\xer_ca$23[1:0]$5060 - attribute \src "issuer_ls180.v:123083.3-123094.6" - wire width 64 $1\a[63:0] - attribute \src "issuer_ls180.v:123095.3-123113.6" - wire width 2 $1\xer_ca$23[1:0]$5061 - attribute \src "issuer_ls180.v:123082.18-123082.100" - wire width 64 $not$issuer_ls180.v:123082$5057_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - wire width 64 \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" - wire width 64 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 40 \alu_op__data_len$18 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \alu_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 25 \alu_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 26 \alu_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \alu_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 13 \alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 36 \alu_op__input_carry$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 41 \alu_op__insn$19 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \alu_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 24 \alu_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \alu_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \alu_op__invert_out$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \alu_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \alu_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \alu_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \alu_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \alu_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \alu_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \alu_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \alu_op__write_cr0$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \alu_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" - wire width 64 \b - attribute \src "issuer_ls180.v:122800.7-122800.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 46 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 23 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 42 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 43 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 22 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 output 45 \xer_ca$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 44 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$issuer_ls180.v:123082$5057 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \Y $not$issuer_ls180.v:123082$5057_Y - end - attribute \src "issuer_ls180.v:122800.7-122800.20" - process $proc$issuer_ls180.v:122800$5062 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:123083.3-123094.6" - process $proc$issuer_ls180.v:123083$5058 - assign { } { } - assign $0\a[63:0] $1\a[63:0] - attribute \src "issuer_ls180.v:123084.5-123084.29" - switch \initial - attribute \src "issuer_ls180.v:123084.9-123084.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" - switch \alu_op__invert_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\a[63:0] \$24 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\a[63:0] \ra - end - sync always - update \a $0\a[63:0] - end - attribute \src "issuer_ls180.v:123095.3-123113.6" - process $proc$issuer_ls180.v:123095$5059 - assign { } { } - assign { } { } - assign $0\xer_ca$23[1:0]$5060 $1\xer_ca$23[1:0]$5061 - attribute \src "issuer_ls180.v:123096.5-123096.29" - switch \initial - attribute \src "issuer_ls180.v:123096.9-123096.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" - switch \alu_op__input_carry - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\xer_ca$23[1:0]$5061 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\xer_ca$23[1:0]$5061 2'11 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\xer_ca$23[1:0]$5061 \xer_ca - case - assign $1\xer_ca$23[1:0]$5061 2'00 - end - sync always - update \xer_ca$23 $0\xer_ca$23[1:0]$5060 - end - connect \$24 $not$issuer_ls180.v:123082$5057_Y - connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } - connect \muxid$1 \muxid - connect \xer_so$22 \xer_so - connect \rb$21 \rb - connect \b \rb - connect \ra$20 \a -end -attribute \src "issuer_ls180.v:123124.1-123428.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" -attribute \generator "nMigen" -module \input$110 - attribute \src "issuer_ls180.v:123125.7-123125.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:123401.3-123419.6" - wire width 2 $0\xer_ca$22[1:0]$5064 - attribute \src "issuer_ls180.v:123401.3-123419.6" - wire width 2 $1\xer_ca$22[1:0]$5065 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" - wire width 64 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" - wire width 64 \b - attribute \src "issuer_ls180.v:123125.7-123125.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 44 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 22 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 17 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 39 \ra$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 18 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 40 \rb$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 41 \rc$20 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \sr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 24 \sr_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 25 \sr_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \sr_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 10 \sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 32 \sr_op__input_carry$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \sr_op__input_cr$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 16 \sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 38 \sr_op__insn$17 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \sr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 23 \sr_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \sr_op__is_32bit$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \sr_op__is_signed$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \sr_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \sr_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \sr_op__output_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \sr_op__output_cr$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \sr_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \sr_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \sr_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \sr_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 21 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 output 43 \xer_ca$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 20 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 42 \xer_so$21 - attribute \src "issuer_ls180.v:123125.7-123125.20" - process $proc$issuer_ls180.v:123125$5066 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:123401.3-123419.6" - process $proc$issuer_ls180.v:123401$5063 - assign { } { } - assign { } { } - assign $0\xer_ca$22[1:0]$5064 $1\xer_ca$22[1:0]$5065 - attribute \src "issuer_ls180.v:123402.5-123402.29" - switch \initial - attribute \src "issuer_ls180.v:123402.9-123402.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" - switch \sr_op__input_carry - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\xer_ca$22[1:0]$5065 2'00 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\xer_ca$22[1:0]$5065 2'11 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\xer_ca$22[1:0]$5065 \xer_ca - case - assign $1\xer_ca$22[1:0]$5065 2'00 - end - sync always - update \xer_ca$22 $0\xer_ca$22[1:0]$5064 - end - connect \rc$20 \rc - connect { \sr_op__insn$17 \sr_op__is_signed$16 \sr_op__is_32bit$15 \sr_op__output_cr$14 \sr_op__input_cr$13 \sr_op__output_carry$12 \sr_op__input_carry$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } - connect \muxid$1 \muxid - connect \xer_so$21 \xer_so - connect \rb$19 \b - connect \b \rb - connect \ra$18 \a - connect \a \ra -end -attribute \src "issuer_ls180.v:123432.1-123729.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.input" -attribute \generator "nMigen" -module \input$47 - attribute \src "issuer_ls180.v:123711.3-123722.6" - wire width 64 $0\b[63:0] - attribute \src "issuer_ls180.v:123433.7-123433.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:123711.3-123722.6" - wire width 64 $1\b[63:0] - attribute \src "issuer_ls180.v:123710.18-123710.100" - wire width 64 $not$issuer_ls180.v:123710$5067_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" - wire width 64 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" - wire width 64 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" - wire width 64 \b - attribute \src "issuer_ls180.v:123433.7-123433.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 39 \logical_op__data_len$18 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute 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\src "issuer_ls180.v:123433.7-123433.20" - process $proc$issuer_ls180.v:123433$5069 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:123711.3-123722.6" - process $proc$issuer_ls180.v:123711$5068 - assign { } { } - assign $0\b[63:0] $1\b[63:0] - attribute \src "issuer_ls180.v:123712.5-123712.29" - switch \initial - attribute \src "issuer_ls180.v:123712.9-123712.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:42" - switch \logical_op__invert_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\b[63:0] \$23 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\b[63:0] \rb - end - sync always - update \b $0\b[63:0] - end - connect \$23 $not$issuer_ls180.v:123710$5067_Y - connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 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"test_issuer.core.fus.div0.alu_div0.pipe_start.input" -attribute \generator "nMigen" -module \input$75 - attribute \src "issuer_ls180.v:124012.3-124023.6" - wire width 64 $0\a[63:0] - attribute \src "issuer_ls180.v:123734.7-123734.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:124012.3-124023.6" - wire width 64 $1\a[63:0] - attribute \src "issuer_ls180.v:124011.18-124011.100" - wire width 64 $not$issuer_ls180.v:124011$5070_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - wire width 64 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" - wire width 64 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" - wire width 64 \b - attribute \src "issuer_ls180.v:123734.7-123734.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src 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\enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 24 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 25 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \logical_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 33 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 40 \logical_op__insn$19 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 23 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 44 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 22 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 41 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 42 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 43 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$issuer_ls180.v:124011$5070 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \Y $not$issuer_ls180.v:124011$5070_Y - end - attribute \src "issuer_ls180.v:123734.7-123734.20" - process $proc$issuer_ls180.v:123734$5072 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:124012.3-124023.6" - process $proc$issuer_ls180.v:124012$5071 - assign { } { } - assign $0\a[63:0] $1\a[63:0] - attribute \src "issuer_ls180.v:124013.5-124013.29" - switch \initial - attribute \src "issuer_ls180.v:124013.9-124013.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" - switch \logical_op__invert_in - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\a[63:0] \$23 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\a[63:0] \ra - end - sync always - update \a $0\a[63:0] - end - connect \$23 $not$issuer_ls180.v:124011$5070_Y - connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - connect \muxid$1 \muxid - connect \xer_so$22 \xer_so - connect \rb$21 \rb - connect \b \rb - connect \ra$20 \a -end -attribute \src "issuer_ls180.v:124034.1-124284.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.input" -attribute \generator "nMigen" -module \input$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" - wire width 64 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" - wire width 64 \b - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \mul_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 18 \mul_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 19 \mul_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \mul_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 12 \mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 28 \mul_op__insn$13 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \mul_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 17 \mul_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \mul_op__is_32bit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \mul_op__is_signed$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 23 \mul_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 24 \mul_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 22 \mul_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 21 \mul_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 25 \mul_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 32 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 16 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 13 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 29 \ra$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 14 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 30 \rb$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 15 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 31 \xer_so$16 - connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } - connect \muxid$1 \muxid - connect \xer_so$16 \xer_so - connect \rb$15 \rb - connect \b \rb - connect \ra$14 \a - connect \a \ra -end -attribute \src "issuer_ls180.v:124288.1-124507.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.int" -attribute \generator "nMigen" -module \int - attribute \src "issuer_ls180.v:124413.3-124419.6" - wire width 5 $0$memwr$\memory$issuer_ls180.v:124418$5105_ADDR[4:0]$5114 - attribute \src "issuer_ls180.v:124413.3-124419.6" - wire width 64 $0$memwr$\memory$issuer_ls180.v:124418$5105_DATA[63:0]$5115 - attribute \src "issuer_ls180.v:124413.3-124419.6" - wire width 64 $0$memwr$\memory$issuer_ls180.v:124418$5105_EN[63:0]$5116 - attribute \src "issuer_ls180.v:124413.3-124419.6" - wire width 5 $0\_0_[4:0] - attribute \src "issuer_ls180.v:124413.3-124419.6" - wire width 5 $0\_1_[4:0] - attribute \src "issuer_ls180.v:124413.3-124419.6" - wire width 5 $0\_2_[4:0] - attribute \src "issuer_ls180.v:124413.3-124419.6" - wire width 5 $0\_3_[4:0] - attribute \src "issuer_ls180.v:124442.3-124451.6" - wire width 64 $0\dmi__data_o[63:0] - attribute \src "issuer_ls180.v:124289.7-124289.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:124433.3-124441.6" - wire $0\ren_delay$10$next[0:0]$5125 - attribute \src "issuer_ls180.v:124366.3-124367.43" - wire $0\ren_delay$10[0:0]$5107 - attribute \src "issuer_ls180.v:124332.7-124332.28" - wire $0\ren_delay$10[0:0]$5173 - attribute \src "issuer_ls180.v:124462.3-124470.6" - wire $0\ren_delay$8$next[0:0]$5130 - attribute \src "issuer_ls180.v:124370.3-124371.41" - wire $0\ren_delay$8[0:0]$5111 - attribute \src "issuer_ls180.v:124336.7-124336.27" - wire $0\ren_delay$8[0:0]$5175 - attribute \src "issuer_ls180.v:124481.3-124489.6" - wire $0\ren_delay$9$next[0:0]$5134 - attribute \src "issuer_ls180.v:124368.3-124369.41" - wire $0\ren_delay$9[0:0]$5109 - attribute \src "issuer_ls180.v:124340.7-124340.27" - wire $0\ren_delay$9[0:0]$5177 - attribute \src "issuer_ls180.v:124424.3-124432.6" - wire $0\ren_delay$next[0:0]$5122 - attribute \src "issuer_ls180.v:124372.3-124373.35" - wire $0\ren_delay[0:0] - attribute \src "issuer_ls180.v:124452.3-124461.6" - wire width 64 $0\src1__data_o[63:0] - attribute \src "issuer_ls180.v:124471.3-124480.6" - wire width 64 $0\src2__data_o[63:0] - attribute \src "issuer_ls180.v:124490.3-124499.6" - wire width 64 $0\src3__data_o[63:0] - attribute \src "issuer_ls180.v:124442.3-124451.6" - wire width 64 $1\dmi__data_o[63:0] - attribute \src "issuer_ls180.v:124433.3-124441.6" - wire $1\ren_delay$10$next[0:0]$5126 - attribute \src "issuer_ls180.v:124462.3-124470.6" - wire $1\ren_delay$8$next[0:0]$5131 - attribute \src "issuer_ls180.v:124481.3-124489.6" - wire $1\ren_delay$9$next[0:0]$5135 - attribute \src "issuer_ls180.v:124424.3-124432.6" - wire $1\ren_delay$next[0:0]$5123 - attribute \src "issuer_ls180.v:124330.7-124330.23" - wire $1\ren_delay[0:0] - attribute \src "issuer_ls180.v:124452.3-124461.6" - wire width 64 $1\src1__data_o[63:0] - attribute \src "issuer_ls180.v:124471.3-124480.6" - wire width 64 $1\src2__data_o[63:0] - attribute \src "issuer_ls180.v:124490.3-124499.6" - wire width 64 $1\src3__data_o[63:0] - attribute \src "issuer_ls180.v:124420.26-124420.32" - wire width 64 $memrd$\memory$issuer_ls180.v:124420$5117_DATA - attribute \src "issuer_ls180.v:124421.30-124421.36" - wire width 64 $memrd$\memory$issuer_ls180.v:124421$5118_DATA - attribute \src "issuer_ls180.v:124422.30-124422.36" - wire width 64 $memrd$\memory$issuer_ls180.v:124422$5119_DATA - attribute \src "issuer_ls180.v:124423.30-124423.36" - wire width 64 $memrd$\memory$issuer_ls180.v:124423$5120_DATA - attribute \src "issuer_ls180.v:0.0-0.0" - wire width 5 $memwr$\memory$issuer_ls180.v:124418$5105_ADDR - attribute \src "issuer_ls180.v:0.0-0.0" - wire width 64 $memwr$\memory$issuer_ls180.v:124418$5105_DATA - attribute \src "issuer_ls180.v:0.0-0.0" - wire width 64 $memwr$\memory$issuer_ls180.v:124418$5105_EN - attribute \src "issuer_ls180.v:124409.13-124409.16" - wire width 5 \_0_ - attribute \src "issuer_ls180.v:124410.13-124410.16" - wire width 5 \_1_ - attribute \src "issuer_ls180.v:124411.13-124411.16" - wire width 5 \_2_ - attribute \src "issuer_ls180.v:124412.13-124412.16" - wire width 5 \_3_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 17 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 16 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 14 \dest1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 13 \dest1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \dest1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 1 \dmi__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \dmi__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \dmi__ren - attribute \src "issuer_ls180.v:124289.7-124289.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 5 \memory_r_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 5 \memory_r_addr$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 5 \memory_r_addr$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 5 \memory_r_addr$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 5 \memory_w_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 64 \memory_w_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire \memory_w_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 5 \src1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 4 \src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 8 \src2__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 7 \src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 9 \src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 11 \src3__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 10 \src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 12 \src3__ren - attribute \src "issuer_ls180.v:124374.14-124374.20" - memory width 64 size 32 \memory - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5137 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5137 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 0 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5138 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5138 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 1 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5139 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5139 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 2 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5140 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5140 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 3 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5141 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5141 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 4 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5142 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5142 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 5 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5143 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5143 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 6 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5144 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5144 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 7 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5145 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5145 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 8 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5146 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5146 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 9 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5147 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5147 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 10 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5148 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5148 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 11 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5149 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5149 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 12 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5150 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5150 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 13 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5151 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5151 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 14 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5152 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5152 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 15 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5153 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5153 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 16 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5154 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5154 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 17 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5155 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5155 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 18 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5156 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5156 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 19 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5157 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5157 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 20 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5158 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5158 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 21 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5159 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5159 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 22 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5160 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5160 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 23 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5161 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5161 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 24 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5162 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5162 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 25 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5163 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5163 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 26 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5164 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5164 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 27 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5165 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5165 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 28 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5166 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5166 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 29 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5167 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5167 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 30 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$5168 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5168 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 31 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:124420.26-124420.32" - cell $memrd $memrd$\memory$issuer_ls180.v:124420$5117 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_0_ - connect \CLK 1'x - connect \DATA $memrd$\memory$issuer_ls180.v:124420$5117_DATA - connect \EN 1'x - end - attribute \src "issuer_ls180.v:124421.30-124421.36" - cell $memrd $memrd$\memory$issuer_ls180.v:124421$5118 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_1_ - connect \CLK 1'x - connect \DATA $memrd$\memory$issuer_ls180.v:124421$5118_DATA - connect \EN 1'x - end - attribute \src "issuer_ls180.v:124422.30-124422.36" - cell $memrd $memrd$\memory$issuer_ls180.v:124422$5119 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_2_ - connect \CLK 1'x - connect \DATA $memrd$\memory$issuer_ls180.v:124422$5119_DATA - connect \EN 1'x - end - attribute \src "issuer_ls180.v:124423.30-124423.36" - cell $memrd $memrd$\memory$issuer_ls180.v:124423$5120 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_3_ - connect \CLK 1'x - connect \DATA $memrd$\memory$issuer_ls180.v:124423$5120_DATA - connect \EN 1'x - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $memwr $memwr$\memory$issuer_ls180.v:0$5169 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \PRIORITY 5169 - parameter \WIDTH 64 - connect \ADDR $memwr$\memory$issuer_ls180.v:124418$5105_ADDR - connect \CLK 1'x - connect \DATA $memwr$\memory$issuer_ls180.v:124418$5105_DATA - connect \EN $memwr$\memory$issuer_ls180.v:124418$5105_EN - end - attribute \src "issuer_ls180.v:0.0-0.0" - process $proc$issuer_ls180.v:0$5178 - sync always - sync init - end - attribute \src "issuer_ls180.v:124289.7-124289.20" - process $proc$issuer_ls180.v:124289$5170 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:124330.7-124330.23" - process $proc$issuer_ls180.v:124330$5171 - assign { } { } - assign $1\ren_delay[0:0] 1'0 - sync always - sync init - update \ren_delay $1\ren_delay[0:0] - end - attribute \src "issuer_ls180.v:124332.7-124332.28" - process $proc$issuer_ls180.v:124332$5172 - assign { } { } - assign $0\ren_delay$10[0:0]$5173 1'0 - sync always - sync init - update \ren_delay$10 $0\ren_delay$10[0:0]$5173 - end - attribute \src "issuer_ls180.v:124336.7-124336.27" - process $proc$issuer_ls180.v:124336$5174 - assign { } { } - assign $0\ren_delay$8[0:0]$5175 1'0 - sync always - sync init - update \ren_delay$8 $0\ren_delay$8[0:0]$5175 - end - attribute \src "issuer_ls180.v:124340.7-124340.27" - process $proc$issuer_ls180.v:124340$5176 - assign { } { } - assign $0\ren_delay$9[0:0]$5177 1'0 - sync always - sync init - update \ren_delay$9 $0\ren_delay$9[0:0]$5177 - end - attribute \src "issuer_ls180.v:124366.3-124367.43" - process $proc$issuer_ls180.v:124366$5106 - assign { } { } - assign $0\ren_delay$10[0:0]$5107 \ren_delay$10$next - sync posedge \coresync_clk - update \ren_delay$10 $0\ren_delay$10[0:0]$5107 - end - attribute \src "issuer_ls180.v:124368.3-124369.41" - process $proc$issuer_ls180.v:124368$5108 - assign { } { } - assign $0\ren_delay$9[0:0]$5109 \ren_delay$9$next - sync posedge \coresync_clk - update \ren_delay$9 $0\ren_delay$9[0:0]$5109 - end - attribute \src "issuer_ls180.v:124370.3-124371.41" - process $proc$issuer_ls180.v:124370$5110 - assign { } { } - assign $0\ren_delay$8[0:0]$5111 \ren_delay$8$next - sync posedge \coresync_clk - update \ren_delay$8 $0\ren_delay$8[0:0]$5111 - end - attribute \src "issuer_ls180.v:124372.3-124373.35" - process $proc$issuer_ls180.v:124372$5112 - assign { } { } - assign $0\ren_delay[0:0] \ren_delay$next - sync posedge \coresync_clk - update \ren_delay $0\ren_delay[0:0] - end - attribute \src "issuer_ls180.v:124413.3-124419.6" - process $proc$issuer_ls180.v:124413$5113 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\memory$issuer_ls180.v:124418$5105_ADDR[4:0]$5114 5'xxxxx - assign $0$memwr$\memory$issuer_ls180.v:124418$5105_DATA[63:0]$5115 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$issuer_ls180.v:124418$5105_EN[63:0]$5116 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\_0_[4:0] \src1__addr - assign $0\_1_[4:0] \src2__addr - assign $0\_2_[4:0] \src3__addr - assign $0\_3_[4:0] \dmi__addr - attribute \src "issuer_ls180.v:124418.5-124418.58" - switch \dest1__wen - attribute \src "issuer_ls180.v:124418.9-124418.19" - case 1'1 - assign $0$memwr$\memory$issuer_ls180.v:124418$5105_ADDR[4:0]$5114 \dest1__addr - assign $0$memwr$\memory$issuer_ls180.v:124418$5105_DATA[63:0]$5115 \dest1__data_i - assign $0$memwr$\memory$issuer_ls180.v:124418$5105_EN[63:0]$5116 64'1111111111111111111111111111111111111111111111111111111111111111 - case - end - sync posedge \coresync_clk - update \_0_ $0\_0_[4:0] - update \_1_ $0\_1_[4:0] - update \_2_ $0\_2_[4:0] - update \_3_ $0\_3_[4:0] - update $memwr$\memory$issuer_ls180.v:124418$5105_ADDR $0$memwr$\memory$issuer_ls180.v:124418$5105_ADDR[4:0]$5114 - update $memwr$\memory$issuer_ls180.v:124418$5105_DATA $0$memwr$\memory$issuer_ls180.v:124418$5105_DATA[63:0]$5115 - update $memwr$\memory$issuer_ls180.v:124418$5105_EN $0$memwr$\memory$issuer_ls180.v:124418$5105_EN[63:0]$5116 - end - attribute \src "issuer_ls180.v:124424.3-124432.6" - process $proc$issuer_ls180.v:124424$5121 - assign { } { } - assign { } { } - assign $0\ren_delay$next[0:0]$5122 $1\ren_delay$next[0:0]$5123 - attribute \src "issuer_ls180.v:124425.5-124425.29" - switch \initial - attribute \src "issuer_ls180.v:124425.9-124425.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$next[0:0]$5123 1'0 - case - assign $1\ren_delay$next[0:0]$5123 \src1__ren - end - sync always - update \ren_delay$next $0\ren_delay$next[0:0]$5122 - end - attribute \src "issuer_ls180.v:124433.3-124441.6" - process $proc$issuer_ls180.v:124433$5124 - assign { } { } - assign { } { } - assign $0\ren_delay$10$next[0:0]$5125 $1\ren_delay$10$next[0:0]$5126 - attribute \src "issuer_ls180.v:124434.5-124434.29" - switch \initial - attribute \src "issuer_ls180.v:124434.9-124434.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$10$next[0:0]$5126 1'0 - case - assign $1\ren_delay$10$next[0:0]$5126 \dmi__ren - end - sync always - update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5125 - end - attribute \src "issuer_ls180.v:124442.3-124451.6" - process $proc$issuer_ls180.v:124442$5127 - assign { } { } - assign { } { } - assign $0\dmi__data_o[63:0] $1\dmi__data_o[63:0] - attribute \src "issuer_ls180.v:124443.5-124443.29" - switch \initial - attribute \src "issuer_ls180.v:124443.9-124443.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi__data_o[63:0] \memory_r_data$7 - case - assign $1\dmi__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dmi__data_o $0\dmi__data_o[63:0] - end - attribute \src "issuer_ls180.v:124452.3-124461.6" - process $proc$issuer_ls180.v:124452$5128 - assign { } { } - assign { } { } - assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] - attribute \src "issuer_ls180.v:124453.5-124453.29" - switch \initial - attribute \src "issuer_ls180.v:124453.9-124453.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src1__data_o[63:0] \memory_r_data - case - assign $1\src1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \src1__data_o $0\src1__data_o[63:0] - end - attribute \src "issuer_ls180.v:124462.3-124470.6" - process $proc$issuer_ls180.v:124462$5129 - assign { } { } - assign { } { } - assign $0\ren_delay$8$next[0:0]$5130 $1\ren_delay$8$next[0:0]$5131 - attribute \src "issuer_ls180.v:124463.5-124463.29" - switch \initial - attribute \src "issuer_ls180.v:124463.9-124463.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$8$next[0:0]$5131 1'0 - case - assign $1\ren_delay$8$next[0:0]$5131 \src2__ren - end - sync always - update \ren_delay$8$next $0\ren_delay$8$next[0:0]$5130 - end - attribute \src "issuer_ls180.v:124471.3-124480.6" - process $proc$issuer_ls180.v:124471$5132 - assign { } { } - assign { } { } - assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] - attribute \src "issuer_ls180.v:124472.5-124472.29" - switch \initial - attribute \src "issuer_ls180.v:124472.9-124472.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$8 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src2__data_o[63:0] \memory_r_data$3 - case - assign $1\src2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \src2__data_o $0\src2__data_o[63:0] - end - attribute \src "issuer_ls180.v:124481.3-124489.6" - process $proc$issuer_ls180.v:124481$5133 - assign { } { } - assign { } { } - assign $0\ren_delay$9$next[0:0]$5134 $1\ren_delay$9$next[0:0]$5135 - attribute \src "issuer_ls180.v:124482.5-124482.29" - switch \initial - attribute \src "issuer_ls180.v:124482.9-124482.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$9$next[0:0]$5135 1'0 - case - assign $1\ren_delay$9$next[0:0]$5135 \src3__ren - end - sync always - update \ren_delay$9$next $0\ren_delay$9$next[0:0]$5134 - end - attribute \src "issuer_ls180.v:124490.3-124499.6" - process $proc$issuer_ls180.v:124490$5136 - assign { } { } - assign { } { } - assign $0\src3__data_o[63:0] $1\src3__data_o[63:0] - attribute \src "issuer_ls180.v:124491.5-124491.29" - switch \initial - attribute \src "issuer_ls180.v:124491.9-124491.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src3__data_o[63:0] \memory_r_data$5 - case - assign $1\src3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \src3__data_o $0\src3__data_o[63:0] - end - connect \memory_r_data $memrd$\memory$issuer_ls180.v:124420$5117_DATA - connect \memory_r_data$3 $memrd$\memory$issuer_ls180.v:124421$5118_DATA - connect \memory_r_data$5 $memrd$\memory$issuer_ls180.v:124422$5119_DATA - connect \memory_r_data$7 $memrd$\memory$issuer_ls180.v:124423$5120_DATA - connect \memory_w_data \dest1__data_i - connect \memory_w_en \dest1__wen - connect \memory_w_addr \dest1__addr - connect \memory_r_addr$6 \dmi__addr - connect \memory_r_addr$4 \src3__addr - connect \memory_r_addr$2 \src2__addr - connect \memory_r_addr \src1__addr -end -attribute \src "issuer_ls180.v:124511.1-124676.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0" -attribute \generator "nMigen" -module \l0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 23 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 15 \dbus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 output 20 \dbus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 14 \dbus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 input 19 \dbus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 output 22 \dbus__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 16 \dbus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 8 output 18 \dbus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 17 \dbus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 21 \dbus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" - wire output 8 \ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 96 input 6 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 7 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire output 9 \ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire output 2 \ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 input 5 \ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire input 3 \ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire input 4 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 10 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 11 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 12 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 13 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" - wire \pimem_ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 48 \pimem_ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pimem_ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire \pimem_ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire \pimem_ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 \pimem_ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire \pimem_ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire \pimem_ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pimem_ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pimem_ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pimem_ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pimem_ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:62" - wire width 64 \pimem_m_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" - wire \pimem_m_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43" - wire width 48 \pimem_x_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:59" - wire \pimem_x_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45" - wire \pimem_x_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:44" - wire width 8 \pimem_x_mask_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:47" - wire width 64 \pimem_x_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:46" - wire \pimem_x_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" - wire \pimem_x_valid_i - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:124600.12-124627.4" - cell \l0$127 \l0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o - connect \ldst_port0_addr_exc_o$12 \pimem_ldst_port0_addr_exc_o - connect \ldst_port0_addr_i \ldst_port0_addr_i - connect \ldst_port0_addr_i$5 \pimem_ldst_port0_addr_i - connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok - connect \ldst_port0_addr_i_ok$6 \pimem_ldst_port0_addr_i_ok - connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o - connect \ldst_port0_addr_ok_o$7 \pimem_ldst_port0_addr_ok_o - connect \ldst_port0_busy_o \ldst_port0_busy_o - connect \ldst_port0_busy_o$3 \pimem_ldst_port0_busy_o - connect \ldst_port0_data_len \ldst_port0_data_len - connect \ldst_port0_data_len$4 \pimem_ldst_port0_data_len - connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i - connect \ldst_port0_is_ld_i$1 \pimem_ldst_port0_is_ld_i - connect \ldst_port0_is_st_i \ldst_port0_is_st_i - connect \ldst_port0_is_st_i$2 \pimem_ldst_port0_is_st_i - connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o$8 \pimem_ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok - connect \ldst_port0_ld_data_o_ok$9 \pimem_ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i \ldst_port0_st_data_i - connect \ldst_port0_st_data_i$11 \pimem_ldst_port0_st_data_i - connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok - connect \ldst_port0_st_data_i_ok$10 \pimem_ldst_port0_st_data_i_ok - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:124628.9-124649.4" - cell \lsmem \lsmem - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dbus__ack \dbus__ack - connect \dbus__adr \dbus__adr - connect \dbus__cyc \dbus__cyc - connect \dbus__dat_r \dbus__dat_r - connect \dbus__dat_w \dbus__dat_w - connect \dbus__err \dbus__err - connect \dbus__sel \dbus__sel - connect \dbus__stb \dbus__stb - connect \dbus__we \dbus__we - connect \m_ld_data_o \pimem_m_ld_data_o - connect \m_valid_i \pimem_m_valid_i - connect \x_addr_i \pimem_x_addr_i - connect \x_busy_o \pimem_x_busy_o - connect \x_ld_i \pimem_x_ld_i - connect \x_mask_i \pimem_x_mask_i - connect \x_st_data_i \pimem_x_st_data_i - connect \x_st_i \pimem_x_st_i - connect \x_valid_i \pimem_x_valid_i - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:124650.9-124674.4" - cell \pimem \pimem - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \ldst_port0_addr_exc_o \pimem_ldst_port0_addr_exc_o - connect \ldst_port0_addr_i \pimem_ldst_port0_addr_i - connect \ldst_port0_addr_i_ok \pimem_ldst_port0_addr_i_ok - connect \ldst_port0_addr_ok_o \pimem_ldst_port0_addr_ok_o - connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o - connect \ldst_port0_data_len \pimem_ldst_port0_data_len - connect \ldst_port0_is_ld_i \pimem_ldst_port0_is_ld_i - connect \ldst_port0_is_st_i \pimem_ldst_port0_is_st_i - connect \ldst_port0_ld_data_o \pimem_ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok \pimem_ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i \pimem_ldst_port0_st_data_i - connect \ldst_port0_st_data_i_ok \pimem_ldst_port0_st_data_i_ok - connect \m_ld_data_o \pimem_m_ld_data_o - connect \m_valid_i \pimem_m_valid_i - connect \x_addr_i \pimem_x_addr_i - connect \x_busy_o \pimem_x_busy_o - connect \x_ld_i \pimem_x_ld_i - connect \x_mask_i \pimem_x_mask_i - connect \x_st_data_i \pimem_x_st_data_i - connect \x_st_i \pimem_x_st_i - connect \x_valid_i \pimem_x_valid_i - end - connect \pimem_ldst_port0_addr_exc_o 1'0 -end -attribute \src "issuer_ls180.v:124680.1-124994.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.l0" -attribute \generator "nMigen" -module \l0$127 - attribute \src "issuer_ls180.v:124889.3-124903.6" - wire $0\idx_l$16$next[0:0]$5202 - attribute \src "issuer_ls180.v:124796.3-124797.35" - wire $0\idx_l$16[0:0]$5185 - attribute \src "issuer_ls180.v:124701.7-124701.24" - wire $0\idx_l$16[0:0]$5221 - attribute \src "issuer_ls180.v:124904.3-124913.6" - wire $0\idx_l_r_idx_l[0:0] - attribute \src "issuer_ls180.v:124914.3-124923.6" - wire $0\idx_l_s_idx_l[0:0] - attribute \src "issuer_ls180.v:124681.7-124681.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:124879.3-124888.6" - wire $0\ldst_port0_addr_exc_o[0:0] - attribute \src "issuer_ls180.v:124817.3-124826.6" - wire width 48 $0\ldst_port0_addr_i$5[47:0]$5187 - attribute \src "issuer_ls180.v:124827.3-124836.6" - wire $0\ldst_port0_addr_i_ok$6[0:0]$5190 - attribute \src "issuer_ls180.v:124869.3-124878.6" - wire $0\ldst_port0_addr_ok_o[0:0] - attribute \src "issuer_ls180.v:124859.3-124868.6" - wire $0\ldst_port0_busy_o[0:0] - attribute \src "issuer_ls180.v:124969.3-124978.6" - wire width 4 $0\ldst_port0_data_len$4[3:0]$5216 - attribute \src "issuer_ls180.v:124979.3-124988.6" - wire $0\ldst_port0_go_die_i[0:0] - attribute \src "issuer_ls180.v:124949.3-124958.6" - wire $0\ldst_port0_is_ld_i$1[0:0]$5210 - attribute \src "issuer_ls180.v:124959.3-124968.6" - wire $0\ldst_port0_is_st_i$2[0:0]$5213 - attribute \src "issuer_ls180.v:124848.3-124858.6" - wire width 64 $0\ldst_port0_ld_data_o[63:0] - attribute \src "issuer_ls180.v:124848.3-124858.6" - wire $0\ldst_port0_ld_data_o_ok[0:0] - attribute \src "issuer_ls180.v:124837.3-124847.6" - wire width 64 $0\ldst_port0_st_data_i$11[63:0]$5193 - attribute \src "issuer_ls180.v:124837.3-124847.6" - wire $0\ldst_port0_st_data_i_ok$10[0:0]$5194 - attribute \src "issuer_ls180.v:124794.3-124795.36" - wire $0\reset_delay[0:0] - attribute \src "issuer_ls180.v:124939.3-124948.6" - wire $0\reset_l_r_reset[0:0] - attribute \src "issuer_ls180.v:124924.3-124938.6" - wire $0\reset_l_s_reset[0:0] - attribute \src "issuer_ls180.v:124889.3-124903.6" - wire $1\idx_l$16$next[0:0]$5203 - attribute \src "issuer_ls180.v:124904.3-124913.6" - wire $1\idx_l_r_idx_l[0:0] - attribute \src "issuer_ls180.v:124914.3-124923.6" - wire $1\idx_l_s_idx_l[0:0] - attribute \src "issuer_ls180.v:124879.3-124888.6" - wire $1\ldst_port0_addr_exc_o[0:0] - attribute \src "issuer_ls180.v:124817.3-124826.6" - wire width 48 $1\ldst_port0_addr_i$5[47:0]$5188 - attribute \src "issuer_ls180.v:124827.3-124836.6" - wire $1\ldst_port0_addr_i_ok$6[0:0]$5191 - attribute \src "issuer_ls180.v:124869.3-124878.6" - wire $1\ldst_port0_addr_ok_o[0:0] - attribute \src "issuer_ls180.v:124859.3-124868.6" - wire $1\ldst_port0_busy_o[0:0] - attribute \src "issuer_ls180.v:124969.3-124978.6" - wire width 4 $1\ldst_port0_data_len$4[3:0]$5217 - attribute \src "issuer_ls180.v:124979.3-124988.6" - wire $1\ldst_port0_go_die_i[0:0] - attribute \src "issuer_ls180.v:124949.3-124958.6" - wire $1\ldst_port0_is_ld_i$1[0:0]$5211 - attribute \src "issuer_ls180.v:124959.3-124968.6" - wire $1\ldst_port0_is_st_i$2[0:0]$5214 - attribute \src "issuer_ls180.v:124848.3-124858.6" - wire width 64 $1\ldst_port0_ld_data_o[63:0] - attribute \src "issuer_ls180.v:124848.3-124858.6" - wire $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "issuer_ls180.v:124837.3-124847.6" - wire width 64 $1\ldst_port0_st_data_i$11[63:0]$5195 - attribute \src "issuer_ls180.v:124837.3-124847.6" - wire $1\ldst_port0_st_data_i_ok$10[0:0]$5196 - attribute \src "issuer_ls180.v:124781.7-124781.25" - wire $1\reset_delay[0:0] - attribute \src "issuer_ls180.v:124939.3-124948.6" - wire $1\reset_l_r_reset[0:0] - attribute \src "issuer_ls180.v:124924.3-124938.6" - wire $1\reset_l_s_reset[0:0] - attribute \src "issuer_ls180.v:124889.3-124903.6" - wire $2\idx_l$16$next[0:0]$5204 - attribute \src "issuer_ls180.v:124924.3-124938.6" - wire $2\reset_l_s_reset[0:0] - attribute \src "issuer_ls180.v:124792.18-124792.103" - wire $not$issuer_ls180.v:124792$5181_Y - attribute \src "issuer_ls180.v:124793.18-124793.117" - wire $not$issuer_ls180.v:124793$5182_Y - attribute \src "issuer_ls180.v:124790.18-124790.134" - wire $or$issuer_ls180.v:124790$5179_Y - attribute \src "issuer_ls180.v:124791.18-124791.120" - wire $ternary$issuer_ls180.v:124791$5180_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" - wire width 96 \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" - wire width 96 \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 26 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire \idx_l$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire \idx_l$16$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \idx_l_q_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \idx_l_r_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \idx_l_s_idx_l - attribute \src "issuer_ls180.v:124681.7-124681.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" - wire output 8 \ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" - wire input 25 \ldst_port0_addr_exc_o$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 96 input 6 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 48 output 18 \ldst_port0_addr_i$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 7 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 19 \ldst_port0_addr_i_ok$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire output 9 \ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire input 20 \ldst_port0_addr_ok_o$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire output 2 \ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire input 16 \ldst_port0_busy_o$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 input 5 \ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 output 17 \ldst_port0_data_len$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire \ldst_port0_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire \ldst_port0_go_die_i$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire input 3 \ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire output 14 \ldst_port0_is_ld_i$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire input 4 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire output 15 \ldst_port0_is_st_i$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 10 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 21 \ldst_port0_ld_data_o$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 11 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 22 \ldst_port0_ld_data_o_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 12 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 24 \ldst_port0_st_data_i$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 13 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 23 \ldst_port0_st_data_i_ok$10 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire \pick_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire \pick_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire \pick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" - wire \reset_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" - wire \reset_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \reset_l_q_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \reset_l_r_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \reset_l_s_reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" - cell $not $not$issuer_ls180.v:124792$5181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pick_n - connect \Y $not$issuer_ls180.v:124792$5181_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" - cell $not $not$issuer_ls180.v:124793$5182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_busy_o$3 - connect \Y $not$issuer_ls180.v:124793$5182_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" - cell $or $or$issuer_ls180.v:124790$5179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_is_ld_i - connect \B \ldst_port0_is_st_i - connect \Y $or$issuer_ls180.v:124790$5179_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:124791$5180 - parameter \WIDTH 1 - connect \A \idx_l$16 - connect \B \pick_o - connect \S \idx_l_q_idx_l - connect \Y $ternary$issuer_ls180.v:124791$5180_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:124798.9-124804.4" - cell \idx_l \idx_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_idx_l \idx_l_q_idx_l - connect \r_idx_l \idx_l_r_idx_l - connect \s_idx_l \idx_l_s_idx_l - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:124805.8-124809.4" - cell \pick \pick - connect \i \pick_i - connect \n \pick_n - connect \o \pick_o - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:124810.17-124816.4" - cell \reset_l$128 \reset_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_reset \reset_l_q_reset - connect \r_reset \reset_l_r_reset - connect \s_reset \reset_l_s_reset - end - attribute \src "issuer_ls180.v:124681.7-124681.20" - process $proc$issuer_ls180.v:124681$5219 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:124701.7-124701.24" - process $proc$issuer_ls180.v:124701$5220 - assign { } { } - assign $0\idx_l$16[0:0]$5221 1'0 - sync always - sync init - update \idx_l$16 $0\idx_l$16[0:0]$5221 - end - attribute \src "issuer_ls180.v:124781.7-124781.25" - process $proc$issuer_ls180.v:124781$5222 - assign { } { } - assign $1\reset_delay[0:0] 1'0 - sync always - sync init - update \reset_delay $1\reset_delay[0:0] - end - attribute \src "issuer_ls180.v:124794.3-124795.36" - process $proc$issuer_ls180.v:124794$5183 - assign { } { } - assign $0\reset_delay[0:0] \reset_l_q_reset - sync posedge \coresync_clk - update \reset_delay $0\reset_delay[0:0] - end - attribute \src "issuer_ls180.v:124796.3-124797.35" - process $proc$issuer_ls180.v:124796$5184 - assign { } { } - assign $0\idx_l$16[0:0]$5185 \idx_l$16$next - sync posedge \coresync_clk - update \idx_l$16 $0\idx_l$16[0:0]$5185 - end - attribute \src "issuer_ls180.v:124817.3-124826.6" - process $proc$issuer_ls180.v:124817$5186 - assign { } { } - assign { } { } - assign $0\ldst_port0_addr_i$5[47:0]$5187 $1\ldst_port0_addr_i$5[47:0]$5188 - attribute \src "issuer_ls180.v:124818.5-124818.29" - switch \initial - attribute \src "issuer_ls180.v:124818.9-124818.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_addr_i$5[47:0]$5188 \$25 [47:0] - case - assign $1\ldst_port0_addr_i$5[47:0]$5188 48'000000000000000000000000000000000000000000000000 - end - sync always - update \ldst_port0_addr_i$5 $0\ldst_port0_addr_i$5[47:0]$5187 - end - attribute \src "issuer_ls180.v:124827.3-124836.6" - process $proc$issuer_ls180.v:124827$5189 - assign { } { } - assign { } { } - assign $0\ldst_port0_addr_i_ok$6[0:0]$5190 $1\ldst_port0_addr_i_ok$6[0:0]$5191 - attribute \src "issuer_ls180.v:124828.5-124828.29" - switch \initial - attribute \src "issuer_ls180.v:124828.9-124828.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_addr_i_ok$6[0:0]$5191 \ldst_port0_addr_i_ok - case - assign $1\ldst_port0_addr_i_ok$6[0:0]$5191 1'0 - end - sync always - update \ldst_port0_addr_i_ok$6 $0\ldst_port0_addr_i_ok$6[0:0]$5190 - end - attribute \src "issuer_ls180.v:124837.3-124847.6" - process $proc$issuer_ls180.v:124837$5192 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\ldst_port0_st_data_i$11[63:0]$5193 $1\ldst_port0_st_data_i$11[63:0]$5195 - assign $0\ldst_port0_st_data_i_ok$10[0:0]$5194 $1\ldst_port0_st_data_i_ok$10[0:0]$5196 - attribute \src "issuer_ls180.v:124838.5-124838.29" - switch \initial - attribute \src "issuer_ls180.v:124838.9-124838.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\ldst_port0_st_data_i_ok$10[0:0]$5196 $1\ldst_port0_st_data_i$11[63:0]$5195 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } - case - assign $1\ldst_port0_st_data_i$11[63:0]$5195 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\ldst_port0_st_data_i_ok$10[0:0]$5196 1'0 - end - sync always - update \ldst_port0_st_data_i$11 $0\ldst_port0_st_data_i$11[63:0]$5193 - update \ldst_port0_st_data_i_ok$10 $0\ldst_port0_st_data_i_ok$10[0:0]$5194 - end - attribute \src "issuer_ls180.v:124848.3-124858.6" - process $proc$issuer_ls180.v:124848$5197 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] - assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "issuer_ls180.v:124849.5-124849.29" - switch \initial - attribute \src "issuer_ls180.v:124849.9-124849.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o[63:0] } { \ldst_port0_ld_data_o_ok$9 \ldst_port0_ld_data_o$8 } - case - assign $1\ldst_port0_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\ldst_port0_ld_data_o_ok[0:0] 1'0 - end - sync always - update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] - update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] - end - attribute \src "issuer_ls180.v:124859.3-124868.6" - process $proc$issuer_ls180.v:124859$5198 - assign { } { } - assign { } { } - assign $0\ldst_port0_busy_o[0:0] $1\ldst_port0_busy_o[0:0] - attribute \src "issuer_ls180.v:124860.5-124860.29" - switch \initial - attribute \src "issuer_ls180.v:124860.9-124860.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_busy_o[0:0] \ldst_port0_busy_o$3 - case - assign $1\ldst_port0_busy_o[0:0] 1'0 - end - sync always - update \ldst_port0_busy_o $0\ldst_port0_busy_o[0:0] - end - attribute \src "issuer_ls180.v:124869.3-124878.6" - process $proc$issuer_ls180.v:124869$5199 - assign { } { } - assign { } { } - assign $0\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] - attribute \src "issuer_ls180.v:124870.5-124870.29" - switch \initial - attribute \src "issuer_ls180.v:124870.9-124870.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_addr_ok_o[0:0] \ldst_port0_addr_ok_o$7 - case - assign $1\ldst_port0_addr_ok_o[0:0] 1'0 - end - sync always - update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] - end - attribute \src "issuer_ls180.v:124879.3-124888.6" - process $proc$issuer_ls180.v:124879$5200 - assign { } { } - assign { } { } - assign $0\ldst_port0_addr_exc_o[0:0] $1\ldst_port0_addr_exc_o[0:0] - attribute \src "issuer_ls180.v:124880.5-124880.29" - switch \initial - attribute \src "issuer_ls180.v:124880.9-124880.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_addr_exc_o[0:0] \ldst_port0_addr_exc_o$12 - case - assign $1\ldst_port0_addr_exc_o[0:0] 1'0 - end - sync always - update \ldst_port0_addr_exc_o $0\ldst_port0_addr_exc_o[0:0] - end - attribute \src "issuer_ls180.v:124889.3-124903.6" - process $proc$issuer_ls180.v:124889$5201 - assign { } { } - assign { } { } - assign { } { } - assign $0\idx_l$16$next[0:0]$5202 $2\idx_l$16$next[0:0]$5204 - attribute \src "issuer_ls180.v:124890.5-124890.29" - switch \initial - attribute \src "issuer_ls180.v:124890.9-124890.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \idx_l_q_idx_l - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\idx_l$16$next[0:0]$5203 \pick_o - case - assign $1\idx_l$16$next[0:0]$5203 \idx_l$16 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\idx_l$16$next[0:0]$5204 1'0 - case - assign $2\idx_l$16$next[0:0]$5204 $1\idx_l$16$next[0:0]$5203 - end - sync always - update \idx_l$16$next $0\idx_l$16$next[0:0]$5202 - end - attribute \src "issuer_ls180.v:124904.3-124913.6" - process $proc$issuer_ls180.v:124904$5205 - assign { } { } - assign { } { } - assign $0\idx_l_r_idx_l[0:0] $1\idx_l_r_idx_l[0:0] - attribute \src "issuer_ls180.v:124905.5-124905.29" - switch \initial - attribute \src "issuer_ls180.v:124905.9-124905.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" - switch \reset_l_q_reset - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\idx_l_r_idx_l[0:0] 1'1 - case - assign $1\idx_l_r_idx_l[0:0] 1'1 - end - sync always - update \idx_l_r_idx_l $0\idx_l_r_idx_l[0:0] - end - attribute \src "issuer_ls180.v:124914.3-124923.6" - process $proc$issuer_ls180.v:124914$5206 - assign { } { } - assign { } { } - assign $0\idx_l_s_idx_l[0:0] $1\idx_l_s_idx_l[0:0] - attribute \src "issuer_ls180.v:124915.5-124915.29" - switch \initial - attribute \src "issuer_ls180.v:124915.9-124915.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" - switch \$19 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\idx_l_s_idx_l[0:0] 1'1 - case - assign $1\idx_l_s_idx_l[0:0] 1'0 - end - sync always - update \idx_l_s_idx_l $0\idx_l_s_idx_l[0:0] - end - attribute \src "issuer_ls180.v:124924.3-124938.6" - process $proc$issuer_ls180.v:124924$5207 - assign { } { } - assign { } { } - assign $0\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] - attribute \src "issuer_ls180.v:124925.5-124925.29" - switch \initial - attribute \src "issuer_ls180.v:124925.9-124925.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" - switch \$21 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reset_l_s_reset[0:0] 1'1 - case - assign $2\reset_l_s_reset[0:0] 1'0 - end - case - assign $1\reset_l_s_reset[0:0] 1'0 - end - sync always - update \reset_l_s_reset $0\reset_l_s_reset[0:0] - end - attribute \src "issuer_ls180.v:124939.3-124948.6" - process $proc$issuer_ls180.v:124939$5208 - assign { } { } - assign { } { } - assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] - attribute \src "issuer_ls180.v:124940.5-124940.29" - switch \initial - attribute \src "issuer_ls180.v:124940.9-124940.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" - switch \reset_l_q_reset - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reset_l_r_reset[0:0] 1'1 - case - assign $1\reset_l_r_reset[0:0] 1'0 - end - sync always - update \reset_l_r_reset $0\reset_l_r_reset[0:0] - end - attribute \src "issuer_ls180.v:124949.3-124958.6" - process $proc$issuer_ls180.v:124949$5209 - assign { } { } - assign { } { } - assign $0\ldst_port0_is_ld_i$1[0:0]$5210 $1\ldst_port0_is_ld_i$1[0:0]$5211 - attribute \src "issuer_ls180.v:124950.5-124950.29" - switch \initial - attribute \src "issuer_ls180.v:124950.9-124950.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_is_ld_i$1[0:0]$5211 \ldst_port0_is_ld_i - case - assign $1\ldst_port0_is_ld_i$1[0:0]$5211 1'0 - end - sync always - update \ldst_port0_is_ld_i$1 $0\ldst_port0_is_ld_i$1[0:0]$5210 - end - attribute \src "issuer_ls180.v:124959.3-124968.6" - process $proc$issuer_ls180.v:124959$5212 - assign { } { } - assign { } { } - assign $0\ldst_port0_is_st_i$2[0:0]$5213 $1\ldst_port0_is_st_i$2[0:0]$5214 - attribute \src "issuer_ls180.v:124960.5-124960.29" - switch \initial - attribute \src "issuer_ls180.v:124960.9-124960.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_is_st_i$2[0:0]$5214 \ldst_port0_is_st_i - case - assign $1\ldst_port0_is_st_i$2[0:0]$5214 1'0 - end - sync always - update \ldst_port0_is_st_i$2 $0\ldst_port0_is_st_i$2[0:0]$5213 - end - attribute \src "issuer_ls180.v:124969.3-124978.6" - process $proc$issuer_ls180.v:124969$5215 - assign { } { } - assign { } { } - assign $0\ldst_port0_data_len$4[3:0]$5216 $1\ldst_port0_data_len$4[3:0]$5217 - attribute \src "issuer_ls180.v:124970.5-124970.29" - switch \initial - attribute \src "issuer_ls180.v:124970.9-124970.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_data_len$4[3:0]$5217 \ldst_port0_data_len - case - assign $1\ldst_port0_data_len$4[3:0]$5217 4'0000 - end - sync always - update \ldst_port0_data_len$4 $0\ldst_port0_data_len$4[3:0]$5216 - end - attribute \src "issuer_ls180.v:124979.3-124988.6" - process $proc$issuer_ls180.v:124979$5218 - assign { } { } - assign { } { } - assign $0\ldst_port0_go_die_i[0:0] $1\ldst_port0_go_die_i[0:0] - attribute \src "issuer_ls180.v:124980.5-124980.29" - switch \initial - attribute \src "issuer_ls180.v:124980.9-124980.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_go_die_i[0:0] \ldst_port0_go_die_i$23 - case - assign $1\ldst_port0_go_die_i[0:0] 1'0 - end - sync always - update \ldst_port0_go_die_i $0\ldst_port0_go_die_i[0:0] - end - connect \$13 $or$issuer_ls180.v:124790$5179_Y - connect \$17 $ternary$issuer_ls180.v:124791$5180_Y - connect \$19 $not$issuer_ls180.v:124792$5181_Y - connect \$21 $not$issuer_ls180.v:124793$5182_Y - connect \$15 \$17 - connect \$25 \ldst_port0_addr_i - connect \ldst_port0_go_die_i$23 1'0 - connect \reset_delay$next \reset_l_q_reset - connect \pick_i \$13 -end -attribute \src "issuer_ls180.v:124998.1-125056.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.ld_active" -attribute \generator "nMigen" -module \ld_active - attribute \src "issuer_ls180.v:124999.7-124999.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:125044.3-125052.6" - wire $0\q_int$next[0:0]$5233 - attribute \src "issuer_ls180.v:125042.3-125043.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:125044.3-125052.6" - wire $1\q_int$next[0:0]$5234 - attribute \src "issuer_ls180.v:125021.7-125021.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:125034.17-125034.96" - wire $and$issuer_ls180.v:125034$5223_Y - attribute \src "issuer_ls180.v:125039.17-125039.96" - wire $and$issuer_ls180.v:125039$5228_Y - attribute \src "issuer_ls180.v:125036.18-125036.99" - wire $not$issuer_ls180.v:125036$5225_Y - attribute \src "issuer_ls180.v:125038.17-125038.98" - wire $not$issuer_ls180.v:125038$5227_Y - attribute \src "issuer_ls180.v:125041.17-125041.98" - wire $not$issuer_ls180.v:125041$5230_Y - attribute \src "issuer_ls180.v:125035.18-125035.104" - wire $or$issuer_ls180.v:125035$5224_Y - attribute \src "issuer_ls180.v:125037.18-125037.105" - wire $or$issuer_ls180.v:125037$5226_Y - attribute \src "issuer_ls180.v:125040.17-125040.103" - wire $or$issuer_ls180.v:125040$5229_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:124999.7-124999.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 2 \r_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 3 \s_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:125034$5223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:125034$5223_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:125039$5228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:125039$5228_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:125036$5225 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_ld_active - connect \Y $not$issuer_ls180.v:125036$5225_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:125038$5227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_ld_active - connect \Y $not$issuer_ls180.v:125038$5227_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:125041$5230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_ld_active - connect \Y $not$issuer_ls180.v:125041$5230_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:125035$5224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_ld_active - connect \Y $or$issuer_ls180.v:125035$5224_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:125037$5226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_ld_active - connect \B \q_int - connect \Y $or$issuer_ls180.v:125037$5226_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:125040$5229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_ld_active - connect \Y $or$issuer_ls180.v:125040$5229_Y - end - attribute \src "issuer_ls180.v:124999.7-124999.20" - process $proc$issuer_ls180.v:124999$5235 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:125021.7-125021.19" - process $proc$issuer_ls180.v:125021$5236 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:125042.3-125043.27" - process $proc$issuer_ls180.v:125042$5231 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:125044.3-125052.6" - process $proc$issuer_ls180.v:125044$5232 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$5233 $1\q_int$next[0:0]$5234 - attribute \src "issuer_ls180.v:125045.5-125045.29" - switch \initial - attribute \src "issuer_ls180.v:125045.9-125045.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$5234 1'0 - case - assign $1\q_int$next[0:0]$5234 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$5233 - end - connect \$9 $and$issuer_ls180.v:125034$5223_Y - connect \$11 $or$issuer_ls180.v:125035$5224_Y - connect \$13 $not$issuer_ls180.v:125036$5225_Y - connect \$15 $or$issuer_ls180.v:125037$5226_Y - connect \$1 $not$issuer_ls180.v:125038$5227_Y - connect \$3 $and$issuer_ls180.v:125039$5228_Y - connect \$5 $or$issuer_ls180.v:125040$5229_Y - connect \$7 $not$issuer_ls180.v:125041$5230_Y - connect \qlq_ld_active \$15 - connect \qn_ld_active \$13 - connect \q_ld_active \$11 -end -attribute \src "issuer_ls180.v:125060.1-126389.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0" -attribute \generator "nMigen" -module \ldst0 - attribute \src "issuer_ls180.v:126044.3-126052.6" - wire $0\adr_l_r_adr$next[0:0]$5379 - attribute \src "issuer_ls180.v:125926.3-125927.39" - wire $0\adr_l_r_adr[0:0] - attribute \src "issuer_ls180.v:125872.3-125873.21" - wire $0\alu_ok[0:0] - attribute \src "issuer_ls180.v:126209.3-126218.6" - wire width 64 $0\dest1_o[63:0] - attribute \src "issuer_ls180.v:126219.3-126228.6" - wire width 64 $0\dest2_o[63:0] - attribute \src "issuer_ls180.v:126199.3-126208.6" - wire width 64 $0\ea_r$next[63:0]$5467 - attribute \src "issuer_ls180.v:125874.3-125875.25" - wire width 64 $0\ea_r[63:0] - attribute \src "issuer_ls180.v:125061.7-125061.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:126274.3-126293.6" - wire width 64 $0\ldd_o[63:0] - attribute \src "issuer_ls180.v:126238.3-126261.6" - wire width 64 $0\lddata_r[63:0] - attribute \src "issuer_ls180.v:126141.3-126150.6" - wire width 64 $0\ldo_r$next[63:0]$5452 - attribute \src "issuer_ls180.v:125882.3-125883.27" - wire width 64 $0\ldo_r[63:0] - attribute \src "issuer_ls180.v:125870.3-125871.33" - wire width 96 $0\ldst_port0_addr_i[95:0] - attribute \src "issuer_ls180.v:126229.3-126237.6" - wire $0\ldst_port0_addr_i_ok$next[0:0]$5472 - attribute \src "issuer_ls180.v:125868.3-125869.57" - wire $0\ldst_port0_addr_i_ok[0:0] - attribute \src "issuer_ls180.v:126318.3-126329.6" - wire width 64 $0\ldst_port0_st_data_i[63:0] - attribute \src "issuer_ls180.v:126089.3-126097.6" - wire $0\lsd_l_r_lsd$next[0:0]$5394 - attribute \src "issuer_ls180.v:125916.3-125917.39" - wire $0\lsd_l_r_lsd[0:0] - attribute \src "issuer_ls180.v:126017.3-126025.6" - wire $0\opc_l_r_opc$next[0:0]$5370 - attribute \src "issuer_ls180.v:125932.3-125933.39" - wire $0\opc_l_r_opc[0:0] - attribute \src "issuer_ls180.v:126008.3-126016.6" - wire $0\opc_l_s_opc$next[0:0]$5367 - attribute \src "issuer_ls180.v:125934.3-125935.39" - wire $0\opc_l_s_opc[0:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $0\oper_r__byte_reverse$next[0:0]$5397 - attribute \src "issuer_ls180.v:125908.3-125909.57" - wire $0\oper_r__byte_reverse[0:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire width 4 $0\oper_r__data_len$next[3:0]$5398 - attribute \src "issuer_ls180.v:125906.3-125907.49" - wire width 4 $0\oper_r__data_len[3:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire width 12 $0\oper_r__fn_unit$next[11:0]$5399 - attribute \src "issuer_ls180.v:125886.3-125887.47" - wire width 12 $0\oper_r__fn_unit[11:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire width 64 $0\oper_r__imm_data__data$next[63:0]$5400 - attribute \src "issuer_ls180.v:125888.3-125889.61" - wire width 64 $0\oper_r__imm_data__data[63:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $0\oper_r__imm_data__ok$next[0:0]$5401 - attribute \src "issuer_ls180.v:125890.3-125891.57" - wire $0\oper_r__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire width 32 $0\oper_r__insn$next[31:0]$5402 - attribute \src "issuer_ls180.v:125914.3-125915.41" - wire width 32 $0\oper_r__insn[31:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire width 7 $0\oper_r__insn_type$next[6:0]$5403 - attribute \src "issuer_ls180.v:125884.3-125885.51" - wire width 7 $0\oper_r__insn_type[6:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $0\oper_r__is_32bit$next[0:0]$5404 - attribute \src "issuer_ls180.v:125902.3-125903.49" - wire $0\oper_r__is_32bit[0:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $0\oper_r__is_signed$next[0:0]$5405 - attribute \src "issuer_ls180.v:125904.3-125905.51" - wire $0\oper_r__is_signed[0:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire width 2 $0\oper_r__ldst_mode$next[1:0]$5406 - attribute \src "issuer_ls180.v:125912.3-125913.51" - wire width 2 $0\oper_r__ldst_mode[1:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $0\oper_r__oe__oe$next[0:0]$5407 - attribute \src "issuer_ls180.v:125898.3-125899.45" - wire $0\oper_r__oe__oe[0:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $0\oper_r__oe__ok$next[0:0]$5408 - attribute \src "issuer_ls180.v:125900.3-125901.45" - wire $0\oper_r__oe__ok[0:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $0\oper_r__rc__ok$next[0:0]$5409 - attribute \src "issuer_ls180.v:125896.3-125897.45" - wire $0\oper_r__rc__ok[0:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $0\oper_r__rc__rc$next[0:0]$5410 - attribute \src "issuer_ls180.v:125894.3-125895.45" - wire $0\oper_r__rc__rc[0:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $0\oper_r__sign_extend$next[0:0]$5411 - attribute \src "issuer_ls180.v:125910.3-125911.55" - wire $0\oper_r__sign_extend[0:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $0\oper_r__zero_a$next[0:0]$5412 - attribute \src "issuer_ls180.v:125892.3-125893.45" - wire $0\oper_r__zero_a[0:0] - attribute \src "issuer_ls180.v:125936.3-125937.28" - wire $0\p_st_go[0:0] - attribute \src "issuer_ls180.v:126262.3-126273.6" - wire width 64 $0\revnorev[63:0] - attribute \src "issuer_ls180.v:126035.3-126043.6" - wire width 3 $0\src_l_r_src$next[2:0]$5376 - attribute \src "issuer_ls180.v:125928.3-125929.39" - wire width 3 $0\src_l_r_src[2:0] - attribute \src "issuer_ls180.v:126026.3-126034.6" - wire width 3 $0\src_l_s_src$next[2:0]$5373 - attribute \src "issuer_ls180.v:125930.3-125931.39" - wire width 3 $0\src_l_s_src[2:0] - attribute \src "issuer_ls180.v:126151.3-126166.6" - wire width 64 $0\src_r0$next[63:0]$5455 - attribute \src "issuer_ls180.v:125880.3-125881.29" - wire width 64 $0\src_r0[63:0] - attribute \src "issuer_ls180.v:126167.3-126182.6" - wire width 64 $0\src_r1$next[63:0]$5459 - attribute \src "issuer_ls180.v:125878.3-125879.29" - wire width 64 $0\src_r1[63:0] - attribute \src "issuer_ls180.v:126183.3-126198.6" - wire width 64 $0\src_r2$next[63:0]$5463 - attribute \src "issuer_ls180.v:125876.3-125877.29" - wire width 64 $0\src_r2[63:0] - attribute \src "issuer_ls180.v:126294.3-126317.6" - wire width 64 $0\stdata_r[63:0] - attribute \src "issuer_ls180.v:126080.3-126088.6" - wire $0\sto_l_r_sto$next[0:0]$5391 - attribute \src "issuer_ls180.v:125918.3-125919.39" - wire $0\sto_l_r_sto[0:0] - attribute \src "issuer_ls180.v:126071.3-126079.6" - wire $0\upd_l_r_upd$next[0:0]$5388 - attribute \src "issuer_ls180.v:125920.3-125921.39" - wire $0\upd_l_r_upd[0:0] - attribute \src "issuer_ls180.v:126062.3-126070.6" - wire $0\upd_l_s_upd$next[0:0]$5385 - attribute \src "issuer_ls180.v:125922.3-125923.39" - wire $0\upd_l_s_upd[0:0] - attribute \src "issuer_ls180.v:126053.3-126061.6" - wire $0\wri_l_r_wri$next[0:0]$5382 - attribute \src "issuer_ls180.v:125924.3-125925.39" - wire $0\wri_l_r_wri[0:0] - attribute \src "issuer_ls180.v:126044.3-126052.6" - wire $1\adr_l_r_adr$next[0:0]$5380 - attribute \src "issuer_ls180.v:125259.7-125259.25" - wire $1\adr_l_r_adr[0:0] - attribute \src "issuer_ls180.v:125273.7-125273.20" - wire $1\alu_ok[0:0] - attribute \src "issuer_ls180.v:126209.3-126218.6" - wire width 64 $1\dest1_o[63:0] - attribute \src "issuer_ls180.v:126219.3-126228.6" - wire width 64 $1\dest2_o[63:0] - attribute \src "issuer_ls180.v:126199.3-126208.6" - wire width 64 $1\ea_r$next[63:0]$5468 - attribute \src "issuer_ls180.v:125319.14-125319.41" - wire width 64 $1\ea_r[63:0] - attribute \src "issuer_ls180.v:126274.3-126293.6" - wire width 64 $1\ldd_o[63:0] - attribute \src "issuer_ls180.v:126238.3-126261.6" - wire width 64 $1\lddata_r[63:0] - attribute \src "issuer_ls180.v:126141.3-126150.6" - wire width 64 $1\ldo_r$next[63:0]$5453 - attribute \src "issuer_ls180.v:125333.14-125333.42" - wire width 64 $1\ldo_r[63:0] - attribute \src "issuer_ls180.v:125340.14-125340.62" - wire width 96 $1\ldst_port0_addr_i[95:0] - attribute \src "issuer_ls180.v:126229.3-126237.6" - wire $1\ldst_port0_addr_i_ok$next[0:0]$5473 - attribute \src "issuer_ls180.v:125345.7-125345.34" - wire $1\ldst_port0_addr_i_ok[0:0] - attribute \src "issuer_ls180.v:126318.3-126329.6" - wire width 64 $1\ldst_port0_st_data_i[63:0] - attribute \src "issuer_ls180.v:126089.3-126097.6" - wire $1\lsd_l_r_lsd$next[0:0]$5395 - attribute \src "issuer_ls180.v:125378.7-125378.25" - wire $1\lsd_l_r_lsd[0:0] - attribute \src "issuer_ls180.v:126017.3-126025.6" - wire $1\opc_l_r_opc$next[0:0]$5371 - attribute \src "issuer_ls180.v:125392.7-125392.25" - wire $1\opc_l_r_opc[0:0] - attribute \src "issuer_ls180.v:126008.3-126016.6" - wire $1\opc_l_s_opc$next[0:0]$5368 - attribute \src "issuer_ls180.v:125396.7-125396.25" - wire $1\opc_l_s_opc[0:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $1\oper_r__byte_reverse$next[0:0]$5413 - attribute \src "issuer_ls180.v:125524.7-125524.34" - wire $1\oper_r__byte_reverse[0:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire width 4 $1\oper_r__data_len$next[3:0]$5414 - attribute \src "issuer_ls180.v:125528.13-125528.36" - wire width 4 $1\oper_r__data_len[3:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire width 12 $1\oper_r__fn_unit$next[11:0]$5415 - attribute \src "issuer_ls180.v:125545.14-125545.39" - wire width 12 $1\oper_r__fn_unit[11:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire width 64 $1\oper_r__imm_data__data$next[63:0]$5416 - attribute \src "issuer_ls180.v:125549.14-125549.59" - wire width 64 $1\oper_r__imm_data__data[63:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $1\oper_r__imm_data__ok$next[0:0]$5417 - attribute \src "issuer_ls180.v:125553.7-125553.34" - wire $1\oper_r__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire width 32 $1\oper_r__insn$next[31:0]$5418 - attribute \src "issuer_ls180.v:125557.14-125557.34" - wire width 32 $1\oper_r__insn[31:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire width 7 $1\oper_r__insn_type$next[6:0]$5419 - attribute \src "issuer_ls180.v:125635.13-125635.38" - wire width 7 $1\oper_r__insn_type[6:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $1\oper_r__is_32bit$next[0:0]$5420 - attribute \src "issuer_ls180.v:125639.7-125639.30" - wire $1\oper_r__is_32bit[0:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $1\oper_r__is_signed$next[0:0]$5421 - attribute \src "issuer_ls180.v:125643.7-125643.31" - wire $1\oper_r__is_signed[0:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire width 2 $1\oper_r__ldst_mode$next[1:0]$5422 - attribute \src "issuer_ls180.v:125652.13-125652.37" - wire width 2 $1\oper_r__ldst_mode[1:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $1\oper_r__oe__oe$next[0:0]$5423 - attribute \src "issuer_ls180.v:125656.7-125656.28" - wire $1\oper_r__oe__oe[0:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $1\oper_r__oe__ok$next[0:0]$5424 - attribute \src "issuer_ls180.v:125660.7-125660.28" - wire $1\oper_r__oe__ok[0:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $1\oper_r__rc__ok$next[0:0]$5425 - attribute \src "issuer_ls180.v:125664.7-125664.28" - wire $1\oper_r__rc__ok[0:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $1\oper_r__rc__rc$next[0:0]$5426 - attribute \src "issuer_ls180.v:125668.7-125668.28" - wire $1\oper_r__rc__rc[0:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $1\oper_r__sign_extend$next[0:0]$5427 - attribute \src "issuer_ls180.v:125672.7-125672.33" - wire $1\oper_r__sign_extend[0:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $1\oper_r__zero_a$next[0:0]$5428 - attribute \src "issuer_ls180.v:125676.7-125676.28" - wire $1\oper_r__zero_a[0:0] - attribute \src "issuer_ls180.v:125680.7-125680.21" - wire $1\p_st_go[0:0] - attribute \src "issuer_ls180.v:126262.3-126273.6" - wire width 64 $1\revnorev[63:0] - attribute \src "issuer_ls180.v:126035.3-126043.6" - wire width 3 $1\src_l_r_src$next[2:0]$5377 - attribute \src "issuer_ls180.v:125722.13-125722.31" - wire width 3 $1\src_l_r_src[2:0] - attribute \src "issuer_ls180.v:126026.3-126034.6" - wire width 3 $1\src_l_s_src$next[2:0]$5374 - attribute \src "issuer_ls180.v:125726.13-125726.31" - wire width 3 $1\src_l_s_src[2:0] - attribute \src "issuer_ls180.v:126151.3-126166.6" - wire width 64 $1\src_r0$next[63:0]$5456 - attribute \src "issuer_ls180.v:125730.14-125730.43" - wire width 64 $1\src_r0[63:0] - attribute \src "issuer_ls180.v:126167.3-126182.6" - wire width 64 $1\src_r1$next[63:0]$5460 - attribute \src "issuer_ls180.v:125734.14-125734.43" - wire width 64 $1\src_r1[63:0] - attribute \src "issuer_ls180.v:126183.3-126198.6" - wire width 64 $1\src_r2$next[63:0]$5464 - attribute \src "issuer_ls180.v:125738.14-125738.43" - wire width 64 $1\src_r2[63:0] - attribute \src "issuer_ls180.v:126294.3-126317.6" - wire width 64 $1\stdata_r[63:0] - attribute \src "issuer_ls180.v:126080.3-126088.6" - wire $1\sto_l_r_sto$next[0:0]$5392 - attribute \src "issuer_ls180.v:125748.7-125748.25" - wire $1\sto_l_r_sto[0:0] - attribute \src "issuer_ls180.v:126071.3-126079.6" - wire $1\upd_l_r_upd$next[0:0]$5389 - attribute \src "issuer_ls180.v:125758.7-125758.25" - wire $1\upd_l_r_upd[0:0] - attribute \src "issuer_ls180.v:126062.3-126070.6" - wire $1\upd_l_s_upd$next[0:0]$5386 - attribute \src "issuer_ls180.v:125762.7-125762.25" - wire $1\upd_l_s_upd[0:0] - attribute \src "issuer_ls180.v:126053.3-126061.6" - wire $1\wri_l_r_wri$next[0:0]$5383 - attribute \src "issuer_ls180.v:125772.7-125772.25" - wire $1\wri_l_r_wri[0:0] - attribute \src "issuer_ls180.v:126274.3-126293.6" - wire width 64 $2\ldd_o[63:0] - attribute \src "issuer_ls180.v:126238.3-126261.6" - wire width 64 $2\lddata_r[63:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $2\oper_r__byte_reverse$next[0:0]$5429 - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire width 4 $2\oper_r__data_len$next[3:0]$5430 - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire width 12 $2\oper_r__fn_unit$next[11:0]$5431 - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire width 64 $2\oper_r__imm_data__data$next[63:0]$5432 - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $2\oper_r__imm_data__ok$next[0:0]$5433 - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire width 32 $2\oper_r__insn$next[31:0]$5434 - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire width 7 $2\oper_r__insn_type$next[6:0]$5435 - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $2\oper_r__is_32bit$next[0:0]$5436 - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $2\oper_r__is_signed$next[0:0]$5437 - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire width 2 $2\oper_r__ldst_mode$next[1:0]$5438 - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $2\oper_r__oe__oe$next[0:0]$5439 - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $2\oper_r__oe__ok$next[0:0]$5440 - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $2\oper_r__rc__ok$next[0:0]$5441 - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $2\oper_r__rc__rc$next[0:0]$5442 - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $2\oper_r__sign_extend$next[0:0]$5443 - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $2\oper_r__zero_a$next[0:0]$5444 - attribute \src "issuer_ls180.v:126151.3-126166.6" - wire width 64 $2\src_r0$next[63:0]$5457 - attribute \src "issuer_ls180.v:126167.3-126182.6" - wire width 64 $2\src_r1$next[63:0]$5461 - attribute \src "issuer_ls180.v:126183.3-126198.6" - wire width 64 $2\src_r2$next[63:0]$5465 - attribute \src "issuer_ls180.v:126294.3-126317.6" - wire width 64 $2\stdata_r[63:0] - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire width 64 $3\oper_r__imm_data__data$next[63:0]$5445 - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $3\oper_r__imm_data__ok$next[0:0]$5446 - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $3\oper_r__oe__oe$next[0:0]$5447 - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $3\oper_r__oe__ok$next[0:0]$5448 - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $3\oper_r__rc__ok$next[0:0]$5449 - attribute \src "issuer_ls180.v:126098.3-126140.6" - wire $3\oper_r__rc__rc$next[0:0]$5450 - attribute \src "issuer_ls180.v:125851.18-125851.124" - wire width 65 $add$issuer_ls180.v:125851$5314_Y - attribute \src "issuer_ls180.v:125778.18-125778.124" - wire $and$issuer_ls180.v:125778$5238_Y - attribute \src "issuer_ls180.v:125779.19-125779.117" - wire $and$issuer_ls180.v:125779$5239_Y - attribute \src "issuer_ls180.v:125780.19-125780.119" - wire $and$issuer_ls180.v:125780$5240_Y - attribute \src "issuer_ls180.v:125781.19-125781.123" - wire $and$issuer_ls180.v:125781$5241_Y - attribute \src "issuer_ls180.v:125782.19-125782.123" - wire $and$issuer_ls180.v:125782$5242_Y - attribute \src "issuer_ls180.v:125783.19-125783.120" - wire $and$issuer_ls180.v:125783$5243_Y - attribute \src "issuer_ls180.v:125784.19-125784.123" - wire $and$issuer_ls180.v:125784$5244_Y - attribute \src "issuer_ls180.v:125785.19-125785.119" - wire $and$issuer_ls180.v:125785$5245_Y - attribute \src "issuer_ls180.v:125786.19-125786.123" - wire $and$issuer_ls180.v:125786$5246_Y - attribute \src "issuer_ls180.v:125787.19-125787.125" - wire $and$issuer_ls180.v:125787$5247_Y - attribute \src "issuer_ls180.v:125790.19-125790.116" - wire $and$issuer_ls180.v:125790$5250_Y - attribute \src "issuer_ls180.v:125791.19-125791.120" - wire $and$issuer_ls180.v:125791$5251_Y - attribute \src "issuer_ls180.v:125792.19-125792.123" - wire $and$issuer_ls180.v:125792$5252_Y - attribute \src "issuer_ls180.v:125796.19-125796.125" - wire $and$issuer_ls180.v:125796$5256_Y - attribute \src "issuer_ls180.v:125797.19-125797.123" - wire $and$issuer_ls180.v:125797$5257_Y - attribute \src "issuer_ls180.v:125802.19-125802.116" - wire $and$issuer_ls180.v:125802$5262_Y - attribute \src "issuer_ls180.v:125804.19-125804.116" - wire $and$issuer_ls180.v:125804$5264_Y - attribute \src "issuer_ls180.v:125807.19-125807.118" - wire $and$issuer_ls180.v:125807$5267_Y - attribute \src "issuer_ls180.v:125809.19-125809.125" - wire $and$issuer_ls180.v:125809$5269_Y - attribute \src "issuer_ls180.v:125812.19-125812.160" - wire width 3 $and$issuer_ls180.v:125812$5272_Y - attribute \src "issuer_ls180.v:125813.19-125813.122" - wire $and$issuer_ls180.v:125813$5273_Y - attribute \src "issuer_ls180.v:125814.19-125814.122" - wire $and$issuer_ls180.v:125814$5274_Y - attribute \src "issuer_ls180.v:125816.19-125816.122" - wire $and$issuer_ls180.v:125816$5277_Y - attribute \src "issuer_ls180.v:125826.18-125826.123" - wire $and$issuer_ls180.v:125826$5289_Y - attribute \src "issuer_ls180.v:125827.18-125827.123" - wire $and$issuer_ls180.v:125827$5290_Y - attribute \src "issuer_ls180.v:125829.18-125829.114" - wire $and$issuer_ls180.v:125829$5292_Y - attribute \src "issuer_ls180.v:125831.18-125831.113" - wire $and$issuer_ls180.v:125831$5294_Y - attribute \src "issuer_ls180.v:125834.18-125834.113" - wire $and$issuer_ls180.v:125834$5297_Y - attribute \src "issuer_ls180.v:125839.18-125839.113" - wire $and$issuer_ls180.v:125839$5302_Y - attribute \src "issuer_ls180.v:125842.18-125842.119" - wire $and$issuer_ls180.v:125842$5305_Y - attribute \src "issuer_ls180.v:125852.18-125852.150" - wire width 3 $and$issuer_ls180.v:125852$5315_Y - attribute \src "issuer_ls180.v:125854.18-125854.113" - wire width 3 $and$issuer_ls180.v:125854$5317_Y - attribute \src "issuer_ls180.v:125856.18-125856.113" - wire width 3 $and$issuer_ls180.v:125856$5319_Y - attribute \src "issuer_ls180.v:125858.18-125858.127" - wire $and$issuer_ls180.v:125858$5321_Y - attribute \src "issuer_ls180.v:125859.18-125859.117" - wire $and$issuer_ls180.v:125859$5322_Y - attribute \src "issuer_ls180.v:125863.18-125863.117" - wire $and$issuer_ls180.v:125863$5326_Y - attribute \src "issuer_ls180.v:125865.18-125865.117" - wire $and$issuer_ls180.v:125865$5328_Y - attribute \src "issuer_ls180.v:125866.18-125866.124" - wire $and$issuer_ls180.v:125866$5329_Y - attribute \src "issuer_ls180.v:125867.18-125867.118" - wire $and$issuer_ls180.v:125867$5330_Y - attribute \src "issuer_ls180.v:125789.19-125789.127" - wire $eq$issuer_ls180.v:125789$5249_Y - attribute \src "issuer_ls180.v:125808.19-125808.127" - wire $eq$issuer_ls180.v:125808$5268_Y - attribute \src "issuer_ls180.v:125810.18-125810.127" - wire $eq$issuer_ls180.v:125810$5270_Y - attribute \src "issuer_ls180.v:125811.19-125811.127" - wire $eq$issuer_ls180.v:125811$5271_Y - attribute \src "issuer_ls180.v:125820.19-125820.126" - wire $eq$issuer_ls180.v:125820$5282_Y - attribute \src "issuer_ls180.v:125821.18-125821.127" - wire $eq$issuer_ls180.v:125821$5283_Y - attribute \src "issuer_ls180.v:125833.18-125833.126" - wire $eq$issuer_ls180.v:125833$5296_Y - attribute \src "issuer_ls180.v:125838.18-125838.126" - wire $eq$issuer_ls180.v:125838$5301_Y - attribute \src "issuer_ls180.v:125815.19-125815.110" - wire width 96 $extend$issuer_ls180.v:125815$5275_Y - attribute \src "issuer_ls180.v:125817.19-125817.116" - wire width 64 $extend$issuer_ls180.v:125817$5278_Y - attribute \src "issuer_ls180.v:125822.19-125822.102" - wire width 64 $extend$issuer_ls180.v:125822$5284_Y - attribute \src "issuer_ls180.v:125801.19-125801.109" - wire $not$issuer_ls180.v:125801$5261_Y - attribute \src "issuer_ls180.v:125805.19-125805.121" - wire $not$issuer_ls180.v:125805$5265_Y - attribute \src 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\src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271" - wire \addr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" - wire width 64 \addr_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \adr_l_q_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \adr_l_r_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \adr_l_r_adr$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \adr_l_s_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \alu_l_s_alu - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:279" - wire width 64 \alu_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" - wire \alu_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" - wire \alu_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:269" - wire \alu_valid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 46 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 33 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire input 2 \cu_ad__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire output 3 \cu_ad__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 22 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 21 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 25 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 24 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 23 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" - wire \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire input 4 \cu_st__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire output 1 \cu_st__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 input 30 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 output 29 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 2 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 32 \ea - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \ea_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \ea_r$next - attribute \src "issuer_ls180.v:125061.7-125061.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:109" - wire \ld_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:272" - wire \ld_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:280" - wire width 64 \ldd_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:384" - wire width 64 \ldd_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11" - wire width 64 \lddata_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \ldo_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \ldo_r$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" - wire input 40 \ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 96 output 38 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 96 \ldst_port0_addr_i$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 39 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \ldst_port0_addr_i_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire input 41 \ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire input 34 \ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 output 37 \ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire output 35 \ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire output 36 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 42 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 43 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 44 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 45 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113" - wire \load_mem_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \lod_l_qn_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \lod_l_r_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \lod_l_s_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \lsd_l_q_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \lsd_l_r_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \lsd_l_r_lsd$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \lsd_l_s_lsd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 31 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:265" - wire \op_is_ld - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:266" - wire \op_is_st - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \oper_i_ldst_ldst0__byte_reverse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 16 \oper_i_ldst_ldst0__data_len - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \oper_i_ldst_ldst0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \oper_i_ldst_ldst0__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \oper_i_ldst_ldst0__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 20 \oper_i_ldst_ldst0__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \oper_i_ldst_ldst0__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \oper_i_ldst_ldst0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \oper_i_ldst_ldst0__is_signed - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 19 \oper_i_ldst_ldst0__ldst_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \oper_i_ldst_ldst0__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \oper_i_ldst_ldst0__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \oper_i_ldst_ldst0__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \oper_i_ldst_ldst0__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \oper_i_ldst_ldst0__sign_extend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \oper_i_ldst_ldst0__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__byte_reverse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__byte_reverse$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \oper_r__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \oper_r__data_len$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \oper_r__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \oper_r__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \oper_r__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \oper_r__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__imm_data__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \oper_r__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \oper_r__insn$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute 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"OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \oper_r__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \oper_r__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__is_signed$next - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \oper_r__ldst_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \oper_r__ldst_mode$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__sign_extend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__sign_extend$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__zero_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:302" - wire \p_st_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:302" - wire \p_st_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:275" - wire \rd_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:274" - wire \rda_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:289" - wire \reset_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:290" - wire \reset_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:286" - wire \reset_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:291" - wire width 3 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:292" - wire \reset_s - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:288" - wire \reset_u - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:287" - wire \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:498" - wire width 64 \revnorev - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \rst_l_q_rst - attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" - wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" - wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" - wire width 64 \src_r2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" - wire width 64 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110" - wire \st_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11" - wire width 64 \stdata_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \sto_l_q_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \sto_l_r_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \sto_l_r_sto$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \sto_l_s_sto - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:114" - wire \stwd_mem_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \upd_l_q_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \upd_l_r_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \upd_l_r_upd$next - attribute \src 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\Y_WIDTH 65 - connect \A \src1_or_z - connect \B \src2_or_imm - connect \Y $add$issuer_ls180.v:125851$5314_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" - cell $and $and$issuer_ls180.v:125778$5238 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sto_l_q_sto - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:125778$5238_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" - cell $and $and$issuer_ls180.v:125779$5239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$99 - connect \B \rd_done - connect \Y $and$issuer_ls180.v:125779$5239_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" - cell $and $and$issuer_ls180.v:125780$5240 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter 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\A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$107 - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:125783$5243_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - cell $and $and$issuer_ls180.v:125784$5244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$109 - connect \B \lod_l_qn_lod - connect \Y $and$issuer_ls180.v:125784$5244_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - cell $and $and$issuer_ls180.v:125785$5245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$111 - connect \B \op_is_ld - connect \Y $and$issuer_ls180.v:125785$5245_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - cell $and 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\A \src_l_q_src [2] - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:125858$5321_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436" - cell $and $and$issuer_ls180.v:125859$5322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$79 - connect \B \op_is_st - connect \Y $and$issuer_ls180.v:125859$5322_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" - cell $and $and$issuer_ls180.v:125863$5326 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \$85 - connect \Y $and$issuer_ls180.v:125863$5326_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" - cell $and $and$issuer_ls180.v:125865$5328 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_valid - connect \B \$91 - connect \Y $and$issuer_ls180.v:125865$5328_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" - cell $and $and$issuer_ls180.v:125866$5329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_valid - connect \B \adr_l_q_adr - connect \Y $and$issuer_ls180.v:125866$5329_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" - cell $and $and$issuer_ls180.v:125867$5330 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$95 - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:125867$5330_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - cell $eq $eq$issuer_ls180.v:125789$5249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \oper_r__ldst_mode - connect \B 2'01 - connect \Y $eq$issuer_ls180.v:125789$5249_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - cell $eq $eq$issuer_ls180.v:125808$5268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \oper_r__ldst_mode - connect \B 2'01 - connect \Y $eq$issuer_ls180.v:125808$5268_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:307" - cell $eq $eq$issuer_ls180.v:125810$5270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \oper_r__insn_type - connect \B 7'0100110 - connect \Y $eq$issuer_ls180.v:125810$5270_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - cell $eq $eq$issuer_ls180.v:125811$5271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \oper_r__ldst_mode - connect \B 2'01 - connect \Y $eq$issuer_ls180.v:125811$5271_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:510" - cell $eq $eq$issuer_ls180.v:125820$5282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \oper_r__data_len - connect \B 2'10 - connect \Y $eq$issuer_ls180.v:125820$5282_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" - cell $eq $eq$issuer_ls180.v:125821$5283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \oper_r__insn_type - connect \B 7'0100101 - connect \Y $eq$issuer_ls180.v:125821$5283_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - cell $eq $eq$issuer_ls180.v:125833$5296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \oper_r__ldst_mode - connect \B 2'01 - connect \Y $eq$issuer_ls180.v:125833$5296_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - cell $eq $eq$issuer_ls180.v:125838$5301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \oper_r__ldst_mode - connect \B 2'01 - connect \Y $eq$issuer_ls180.v:125838$5301_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" - cell $pos $extend$issuer_ls180.v:125815$5275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 96 - connect \A \addr_r - connect \Y $extend$issuer_ls180.v:125815$5275_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $extend$issuer_ls180.v:125817$5278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 64 - connect \A \ldst_port0_ld_data_o [7:0] - connect \Y $extend$issuer_ls180.v:125817$5278_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $extend$issuer_ls180.v:125822$5284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 64 - connect \A \src_r2 [7:0] - connect \Y $extend$issuer_ls180.v:125822$5284_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" - cell $not $not$issuer_ls180.v:125801$5261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$140 - connect \Y $not$issuer_ls180.v:125801$5261_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" - cell $not $not$issuer_ls180.v:125805$5265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_busy_o - connect \Y $not$issuer_ls180.v:125805$5265_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" - cell $not $not$issuer_ls180.v:125828$5291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_valid - connect \Y $not$issuer_ls180.v:125828$5291_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" - cell $not $not$issuer_ls180.v:125830$5293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rda_any - connect \Y $not$issuer_ls180.v:125830$5293_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - cell $not $not$issuer_ls180.v:125832$5295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_busy_o - connect \Y $not$issuer_ls180.v:125832$5295_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - cell $not $not$issuer_ls180.v:125837$5300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_busy_o - connect \Y $not$issuer_ls180.v:125837$5300_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" - cell $not $not$issuer_ls180.v:125853$5316 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A { \oper_r__imm_data__ok \oper_r__zero_a } - connect \Y $not$issuer_ls180.v:125853$5316_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" - cell $not $not$issuer_ls180.v:125855$5318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rdmaskn_i - connect \Y $not$issuer_ls180.v:125855$5318_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" - cell $not $not$issuer_ls180.v:125862$5325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$86 - connect \Y $not$issuer_ls180.v:125862$5325_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" - cell $not $not$issuer_ls180.v:125864$5327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_rd__rel_o [2] - connect \Y $not$issuer_ls180.v:125864$5327_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" - cell $or $or$issuer_ls180.v:125777$5237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_st__go_i - connect \B \cu_go_die_i - connect \Y $or$issuer_ls180.v:125777$5237_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" - cell $or $or$issuer_ls180.v:125788$5248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$issuer_ls180.v:125788$5248_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" - cell $or $or$issuer_ls180.v:125793$5253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_st__go_i - connect \B \p_st_go - connect \Y $or$issuer_ls180.v:125793$5253_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" - cell $or $or$issuer_ls180.v:125794$5254 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$127 - connect \B \cu_wr__go_i [0] - connect \Y $or$issuer_ls180.v:125794$5254_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" - cell $or $or$issuer_ls180.v:125795$5255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$129 - connect \B \cu_wr__go_i [1] - connect \Y $or$issuer_ls180.v:125795$5255_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" - cell $or $or$issuer_ls180.v:125798$5258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_st__rel_o - connect \B \cu_wr__rel_o [0] - connect \Y $or$issuer_ls180.v:125798$5258_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" - cell $or $or$issuer_ls180.v:125799$5259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_ad__go_i - connect \B \cu_go_die_i - connect \Y $or$issuer_ls180.v:125799$5259_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" - cell $or $or$issuer_ls180.v:125800$5260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$138 - connect \B \cu_wr__rel_o [1] - connect \Y $or$issuer_ls180.v:125800$5260_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $or $or$issuer_ls180.v:125803$5263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \lod_l_qn_lod - connect \B \op_is_st - connect \Y $or$issuer_ls180.v:125803$5263_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" - cell $or $or$issuer_ls180.v:125806$5266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$149 - connect \B \op_is_ld - connect \Y $or$issuer_ls180.v:125806$5266_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:294" - cell $or $or$issuer_ls180.v:125825$5288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $or$issuer_ls180.v:125825$5288_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - cell $or $or$issuer_ls180.v:125835$5298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_reset - connect \B \$36 - connect \Y $or$issuer_ls180.v:125835$5298_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" - cell $or $or$issuer_ls180.v:125836$5299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_done_o - connect \B \cu_go_die_i - connect \Y $or$issuer_ls180.v:125836$5299_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - cell $or $or$issuer_ls180.v:125840$5303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_reset - connect \B \$44 - connect \Y $or$issuer_ls180.v:125840$5303_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:359" - cell $or $or$issuer_ls180.v:125841$5304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reset_w - connect \B { \$38 \$46 } - connect \Y $or$issuer_ls180.v:125841$5304_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" - cell $or $or$issuer_ls180.v:125843$5306 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \reset_s - connect \B \p_st_go - connect \Y $or$issuer_ls180.v:125843$5306_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:371" - cell $or $or$issuer_ls180.v:125844$5307 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \reset_s - connect \B \p_st_go - connect \Y $or$issuer_ls180.v:125844$5307_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:371" - cell $or $or$issuer_ls180.v:125845$5308 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$54 - connect \B \ld_ok - connect \Y $or$issuer_ls180.v:125845$5308_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" - cell $or $or$issuer_ls180.v:125847$5310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_go_die_i - connect \Y $or$issuer_ls180.v:125847$5310_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" - cell $or $or$issuer_ls180.v:125857$5320 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] - connect \B \cu_go_die_i - connect \Y $or$issuer_ls180.v:125857$5320_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:430" - cell $or $or$issuer_ls180.v:125860$5323 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_rd__go_i [0] - connect \B \cu_rd__go_i [1] - connect \Y $or$issuer_ls180.v:125860$5323_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" - cell $or $or$issuer_ls180.v:125861$5324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_rd__rel_o [0] - connect \B \cu_rd__rel_o [1] - connect \Y $or$issuer_ls180.v:125861$5324_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" - cell $pos $pos$issuer_ls180.v:125815$5276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 96 - parameter \Y_WIDTH 96 - connect \A $extend$issuer_ls180.v:125815$5275_Y - connect \Y $pos$issuer_ls180.v:125815$5276_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $pos$issuer_ls180.v:125817$5279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:125817$5278_Y - connect \Y $pos$issuer_ls180.v:125817$5279_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $pos$issuer_ls180.v:125818$5280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 48'000000000000000000000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] } - connect \Y $pos$issuer_ls180.v:125818$5280_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $pos$issuer_ls180.v:125819$5281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] } - connect \Y $pos$issuer_ls180.v:125819$5281_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $pos$issuer_ls180.v:125822$5285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:125822$5284_Y - connect \Y $pos$issuer_ls180.v:125822$5285_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $pos$issuer_ls180.v:125823$5286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 48'000000000000000000000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] } - connect \Y $pos$issuer_ls180.v:125823$5286_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $pos$issuer_ls180.v:125824$5287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] } - connect \Y $pos$issuer_ls180.v:125824$5287_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:125846$5309 - parameter \WIDTH 64 - connect \A \ldo_r - connect \B \ldd_o - connect \S \ld_ok - connect \Y $ternary$issuer_ls180.v:125846$5309_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:125848$5311 - parameter \WIDTH 64 - connect \A \ea_r - connect \B \alu_o - connect \S \alu_l_q_alu - connect \Y $ternary$issuer_ls180.v:125848$5311_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:405" - cell $mux $ternary$issuer_ls180.v:125849$5312 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \S \oper_r__zero_a - connect \Y $ternary$issuer_ls180.v:125849$5312_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" - cell $mux $ternary$issuer_ls180.v:125850$5313 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \oper_r__imm_data__data - connect \S \oper_r__imm_data__ok - connect \Y $ternary$issuer_ls180.v:125850$5313_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:125938.9-125944.4" - cell \adr_l \adr_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_adr \adr_l_q_adr - connect \r_adr \adr_l_r_adr - connect \s_adr \adr_l_s_adr - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:125945.15-125951.4" - cell \alu_l$125 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:125952.9-125958.4" - cell \lod_l \lod_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \qn_lod \lod_l_qn_lod - connect \r_lod \lod_l_r_lod - connect \s_lod \lod_l_s_lod - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:125959.9-125965.4" - cell \lsd_l \lsd_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_lsd \lsd_l_q_lsd - connect \r_lsd \lsd_l_r_lsd - connect \s_lsd \lsd_l_s_lsd - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:125966.15-125972.4" - cell \opc_l$123 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_opc \opc_l_q_opc - connect \r_opc \opc_l_r_opc - connect \s_opc \opc_l_s_opc - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:125973.15-125979.4" - cell \rst_l$126 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rst \rst_l_q_rst - connect \r_rst \rst_l_r_rst - connect \s_rst \rst_l_s_rst - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:125980.15-125986.4" - cell \src_l$124 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_src \src_l_q_src - connect \r_src \src_l_r_src - connect \s_src \src_l_s_src - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:125987.9-125993.4" - cell \sto_l \sto_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_sto \sto_l_q_sto - connect \r_sto \sto_l_r_sto - connect \s_sto \sto_l_s_sto - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:125994.9-126000.4" - cell \upd_l \upd_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_upd \upd_l_q_upd - connect \r_upd \upd_l_r_upd - connect \s_upd \upd_l_s_upd - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:126001.9-126007.4" - cell \wri_l \wri_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_wri \wri_l_q_wri - connect \r_wri \wri_l_r_wri - connect \s_wri \wri_l_s_wri - end - attribute \src "issuer_ls180.v:125061.7-125061.20" - process $proc$issuer_ls180.v:125061$5479 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:125259.7-125259.25" - process $proc$issuer_ls180.v:125259$5480 - assign { } { } - assign $1\adr_l_r_adr[0:0] 1'1 - sync always - sync init - update \adr_l_r_adr $1\adr_l_r_adr[0:0] - end - attribute \src "issuer_ls180.v:125273.7-125273.20" - process $proc$issuer_ls180.v:125273$5481 - assign { } { } - assign $1\alu_ok[0:0] 1'0 - sync always - sync init - update \alu_ok $1\alu_ok[0:0] - end - attribute \src "issuer_ls180.v:125319.14-125319.41" - process $proc$issuer_ls180.v:125319$5482 - assign { } { } - assign $1\ea_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \ea_r $1\ea_r[63:0] - end - attribute \src "issuer_ls180.v:125333.14-125333.42" - process $proc$issuer_ls180.v:125333$5483 - assign { } { } - assign $1\ldo_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \ldo_r $1\ldo_r[63:0] - end - attribute \src "issuer_ls180.v:125340.14-125340.62" - process $proc$issuer_ls180.v:125340$5484 - assign { } { } - assign $1\ldst_port0_addr_i[95:0] 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \ldst_port0_addr_i $1\ldst_port0_addr_i[95:0] - end - attribute \src "issuer_ls180.v:125345.7-125345.34" - process $proc$issuer_ls180.v:125345$5485 - assign { } { } - assign $1\ldst_port0_addr_i_ok[0:0] 1'0 - sync always - sync init - update \ldst_port0_addr_i_ok $1\ldst_port0_addr_i_ok[0:0] - end - attribute \src "issuer_ls180.v:125378.7-125378.25" - process $proc$issuer_ls180.v:125378$5486 - assign { } { } - assign $1\lsd_l_r_lsd[0:0] 1'1 - sync always - sync init - update \lsd_l_r_lsd $1\lsd_l_r_lsd[0:0] - end - attribute \src "issuer_ls180.v:125392.7-125392.25" - process $proc$issuer_ls180.v:125392$5487 - assign { } { } - assign $1\opc_l_r_opc[0:0] 1'1 - sync always - sync init - update \opc_l_r_opc $1\opc_l_r_opc[0:0] - end - attribute \src "issuer_ls180.v:125396.7-125396.25" - process $proc$issuer_ls180.v:125396$5488 - assign { } { } - assign $1\opc_l_s_opc[0:0] 1'0 - sync always - sync init - update \opc_l_s_opc $1\opc_l_s_opc[0:0] - end - attribute \src "issuer_ls180.v:125524.7-125524.34" - process $proc$issuer_ls180.v:125524$5489 - assign { } { } - assign $1\oper_r__byte_reverse[0:0] 1'0 - sync always - sync init - update \oper_r__byte_reverse $1\oper_r__byte_reverse[0:0] - end - attribute \src "issuer_ls180.v:125528.13-125528.36" - process $proc$issuer_ls180.v:125528$5490 - assign { } { } - assign $1\oper_r__data_len[3:0] 4'0000 - sync always - sync init - update \oper_r__data_len $1\oper_r__data_len[3:0] - end - attribute \src "issuer_ls180.v:125545.14-125545.39" - process $proc$issuer_ls180.v:125545$5491 - assign { } { } - assign $1\oper_r__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \oper_r__fn_unit $1\oper_r__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:125549.14-125549.59" - process $proc$issuer_ls180.v:125549$5492 - assign { } { } - assign $1\oper_r__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \oper_r__imm_data__data $1\oper_r__imm_data__data[63:0] - end - attribute \src "issuer_ls180.v:125553.7-125553.34" - process $proc$issuer_ls180.v:125553$5493 - assign { } { } - assign $1\oper_r__imm_data__ok[0:0] 1'0 - sync always - sync init - update \oper_r__imm_data__ok $1\oper_r__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:125557.14-125557.34" - process $proc$issuer_ls180.v:125557$5494 - assign { } { } - assign $1\oper_r__insn[31:0] 0 - sync always - sync init - update \oper_r__insn $1\oper_r__insn[31:0] - end - attribute \src "issuer_ls180.v:125635.13-125635.38" - process $proc$issuer_ls180.v:125635$5495 - assign { } { } - assign $1\oper_r__insn_type[6:0] 7'0000000 - sync always - sync init - update \oper_r__insn_type $1\oper_r__insn_type[6:0] - end - attribute \src "issuer_ls180.v:125639.7-125639.30" - process $proc$issuer_ls180.v:125639$5496 - assign { } { } - assign $1\oper_r__is_32bit[0:0] 1'0 - sync always - sync init - update \oper_r__is_32bit $1\oper_r__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:125643.7-125643.31" - process $proc$issuer_ls180.v:125643$5497 - assign { } { } - assign $1\oper_r__is_signed[0:0] 1'0 - sync always - sync init - update \oper_r__is_signed $1\oper_r__is_signed[0:0] - end - attribute \src "issuer_ls180.v:125652.13-125652.37" - process $proc$issuer_ls180.v:125652$5498 - assign { } { } - assign $1\oper_r__ldst_mode[1:0] 2'00 - sync always - sync init - update \oper_r__ldst_mode $1\oper_r__ldst_mode[1:0] - end - attribute \src "issuer_ls180.v:125656.7-125656.28" - process $proc$issuer_ls180.v:125656$5499 - assign { } { } - assign $1\oper_r__oe__oe[0:0] 1'0 - sync always - sync init - update \oper_r__oe__oe $1\oper_r__oe__oe[0:0] - end - attribute \src "issuer_ls180.v:125660.7-125660.28" - process $proc$issuer_ls180.v:125660$5500 - assign { } { } - assign $1\oper_r__oe__ok[0:0] 1'0 - sync always - sync init - update \oper_r__oe__ok $1\oper_r__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:125664.7-125664.28" - process $proc$issuer_ls180.v:125664$5501 - assign { } { } - assign $1\oper_r__rc__ok[0:0] 1'0 - sync always - sync init - update \oper_r__rc__ok $1\oper_r__rc__ok[0:0] - end - attribute \src "issuer_ls180.v:125668.7-125668.28" - process $proc$issuer_ls180.v:125668$5502 - assign { } { } - assign $1\oper_r__rc__rc[0:0] 1'0 - sync always - sync init - update \oper_r__rc__rc $1\oper_r__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:125672.7-125672.33" - process $proc$issuer_ls180.v:125672$5503 - assign { } { } - assign $1\oper_r__sign_extend[0:0] 1'0 - sync always - sync init - update \oper_r__sign_extend $1\oper_r__sign_extend[0:0] - end - attribute \src "issuer_ls180.v:125676.7-125676.28" - process $proc$issuer_ls180.v:125676$5504 - assign { } { } - assign $1\oper_r__zero_a[0:0] 1'0 - sync always - sync init - update \oper_r__zero_a $1\oper_r__zero_a[0:0] - end - attribute \src "issuer_ls180.v:125680.7-125680.21" - process $proc$issuer_ls180.v:125680$5505 - assign { } { } - assign $1\p_st_go[0:0] 1'0 - sync always - sync init - update \p_st_go $1\p_st_go[0:0] - end - attribute \src "issuer_ls180.v:125722.13-125722.31" - process $proc$issuer_ls180.v:125722$5506 - assign { } { } - assign $1\src_l_r_src[2:0] 3'111 - sync always - sync init - update \src_l_r_src $1\src_l_r_src[2:0] - end - attribute \src "issuer_ls180.v:125726.13-125726.31" - process $proc$issuer_ls180.v:125726$5507 - assign { } { } - assign $1\src_l_s_src[2:0] 3'000 - sync always - sync init - update \src_l_s_src $1\src_l_s_src[2:0] - end - attribute \src "issuer_ls180.v:125730.14-125730.43" - process $proc$issuer_ls180.v:125730$5508 - assign { } { } - assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r0 $1\src_r0[63:0] - end - attribute \src "issuer_ls180.v:125734.14-125734.43" - process $proc$issuer_ls180.v:125734$5509 - assign { } { } - assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r1 $1\src_r1[63:0] - end - attribute \src "issuer_ls180.v:125738.14-125738.43" - process $proc$issuer_ls180.v:125738$5510 - assign { } { } - assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r2 $1\src_r2[63:0] - end - attribute \src "issuer_ls180.v:125748.7-125748.25" - process $proc$issuer_ls180.v:125748$5511 - assign { } { } - assign $1\sto_l_r_sto[0:0] 1'1 - sync always - sync init - update \sto_l_r_sto $1\sto_l_r_sto[0:0] - end - attribute \src "issuer_ls180.v:125758.7-125758.25" - process $proc$issuer_ls180.v:125758$5512 - assign { } { } - assign $1\upd_l_r_upd[0:0] 1'1 - sync always - sync init - update \upd_l_r_upd $1\upd_l_r_upd[0:0] - end - attribute \src "issuer_ls180.v:125762.7-125762.25" - process $proc$issuer_ls180.v:125762$5513 - assign { } { } - assign $1\upd_l_s_upd[0:0] 1'0 - sync always - sync init - update \upd_l_s_upd $1\upd_l_s_upd[0:0] - end - attribute \src "issuer_ls180.v:125772.7-125772.25" - process $proc$issuer_ls180.v:125772$5514 - assign { } { } - assign $1\wri_l_r_wri[0:0] 1'1 - sync always - sync init - update \wri_l_r_wri $1\wri_l_r_wri[0:0] - end - attribute \src "issuer_ls180.v:125868.3-125869.57" - process $proc$issuer_ls180.v:125868$5331 - assign { } { } - assign $0\ldst_port0_addr_i_ok[0:0] \ldst_port0_addr_i_ok$next - sync posedge \coresync_clk - update \ldst_port0_addr_i_ok $0\ldst_port0_addr_i_ok[0:0] - end - attribute \src "issuer_ls180.v:125870.3-125871.33" - process $proc$issuer_ls180.v:125870$5332 - assign { } { } - assign $0\ldst_port0_addr_i[95:0] \$168 - sync posedge \coresync_clk - update \ldst_port0_addr_i $0\ldst_port0_addr_i[95:0] - end - attribute \src "issuer_ls180.v:125872.3-125873.21" - process $proc$issuer_ls180.v:125872$5333 - assign { } { } - assign $0\alu_ok[0:0] \$89 - sync posedge \coresync_clk - update \alu_ok $0\alu_ok[0:0] - end - attribute \src "issuer_ls180.v:125874.3-125875.25" - process $proc$issuer_ls180.v:125874$5334 - assign { } { } - assign $0\ea_r[63:0] \ea_r$next - sync posedge \coresync_clk - update \ea_r $0\ea_r[63:0] - end - attribute \src "issuer_ls180.v:125876.3-125877.29" - process $proc$issuer_ls180.v:125876$5335 - assign { } { } - assign $0\src_r2[63:0] \src_r2$next - sync posedge \coresync_clk - update \src_r2 $0\src_r2[63:0] - end - attribute \src "issuer_ls180.v:125878.3-125879.29" - process $proc$issuer_ls180.v:125878$5336 - assign { } { } - assign $0\src_r1[63:0] \src_r1$next - sync posedge \coresync_clk - update \src_r1 $0\src_r1[63:0] - end - attribute \src "issuer_ls180.v:125880.3-125881.29" - process $proc$issuer_ls180.v:125880$5337 - assign { } { } - assign $0\src_r0[63:0] \src_r0$next - sync posedge \coresync_clk - update \src_r0 $0\src_r0[63:0] - end - attribute \src "issuer_ls180.v:125882.3-125883.27" - process $proc$issuer_ls180.v:125882$5338 - assign { } { } - assign $0\ldo_r[63:0] \ldo_r$next - sync posedge \coresync_clk - update \ldo_r $0\ldo_r[63:0] - end - attribute \src "issuer_ls180.v:125884.3-125885.51" - process $proc$issuer_ls180.v:125884$5339 - assign { } { } - assign $0\oper_r__insn_type[6:0] \oper_r__insn_type$next - sync posedge \coresync_clk - update \oper_r__insn_type $0\oper_r__insn_type[6:0] - end - attribute \src "issuer_ls180.v:125886.3-125887.47" - process $proc$issuer_ls180.v:125886$5340 - assign { } { } - assign $0\oper_r__fn_unit[11:0] \oper_r__fn_unit$next - sync posedge \coresync_clk - update \oper_r__fn_unit $0\oper_r__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:125888.3-125889.61" - process $proc$issuer_ls180.v:125888$5341 - assign { } { } - assign $0\oper_r__imm_data__data[63:0] \oper_r__imm_data__data$next - sync posedge \coresync_clk - update \oper_r__imm_data__data $0\oper_r__imm_data__data[63:0] - end - attribute \src "issuer_ls180.v:125890.3-125891.57" - process $proc$issuer_ls180.v:125890$5342 - assign { } { } - assign $0\oper_r__imm_data__ok[0:0] \oper_r__imm_data__ok$next - sync posedge \coresync_clk - update \oper_r__imm_data__ok $0\oper_r__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:125892.3-125893.45" - process $proc$issuer_ls180.v:125892$5343 - assign { } { } - assign $0\oper_r__zero_a[0:0] \oper_r__zero_a$next - sync posedge \coresync_clk - update \oper_r__zero_a $0\oper_r__zero_a[0:0] - end - attribute \src "issuer_ls180.v:125894.3-125895.45" - process $proc$issuer_ls180.v:125894$5344 - assign { } { } - assign $0\oper_r__rc__rc[0:0] \oper_r__rc__rc$next - sync posedge \coresync_clk - update \oper_r__rc__rc $0\oper_r__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:125896.3-125897.45" - process $proc$issuer_ls180.v:125896$5345 - assign { } { } - assign $0\oper_r__rc__ok[0:0] \oper_r__rc__ok$next - sync posedge \coresync_clk - update \oper_r__rc__ok $0\oper_r__rc__ok[0:0] - end - attribute \src "issuer_ls180.v:125898.3-125899.45" - process $proc$issuer_ls180.v:125898$5346 - assign { } { } - assign $0\oper_r__oe__oe[0:0] \oper_r__oe__oe$next - sync posedge \coresync_clk - update \oper_r__oe__oe $0\oper_r__oe__oe[0:0] - end - attribute \src "issuer_ls180.v:125900.3-125901.45" - process $proc$issuer_ls180.v:125900$5347 - assign { } { } - assign $0\oper_r__oe__ok[0:0] \oper_r__oe__ok$next - sync posedge \coresync_clk - update \oper_r__oe__ok $0\oper_r__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:125902.3-125903.49" - process $proc$issuer_ls180.v:125902$5348 - assign { } { } - assign $0\oper_r__is_32bit[0:0] \oper_r__is_32bit$next - sync posedge \coresync_clk - update \oper_r__is_32bit $0\oper_r__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:125904.3-125905.51" - process $proc$issuer_ls180.v:125904$5349 - assign { } { } - assign $0\oper_r__is_signed[0:0] \oper_r__is_signed$next - sync posedge \coresync_clk - update \oper_r__is_signed $0\oper_r__is_signed[0:0] - end - attribute \src "issuer_ls180.v:125906.3-125907.49" - process $proc$issuer_ls180.v:125906$5350 - assign { } { } - assign $0\oper_r__data_len[3:0] \oper_r__data_len$next - sync posedge \coresync_clk - update \oper_r__data_len $0\oper_r__data_len[3:0] - end - attribute \src "issuer_ls180.v:125908.3-125909.57" - process $proc$issuer_ls180.v:125908$5351 - assign { } { } - assign $0\oper_r__byte_reverse[0:0] \oper_r__byte_reverse$next - sync posedge \coresync_clk - update \oper_r__byte_reverse $0\oper_r__byte_reverse[0:0] - end - attribute \src "issuer_ls180.v:125910.3-125911.55" - process $proc$issuer_ls180.v:125910$5352 - assign { } { } - assign $0\oper_r__sign_extend[0:0] \oper_r__sign_extend$next - sync posedge \coresync_clk - update \oper_r__sign_extend $0\oper_r__sign_extend[0:0] - end - attribute \src "issuer_ls180.v:125912.3-125913.51" - process $proc$issuer_ls180.v:125912$5353 - assign { } { } - assign $0\oper_r__ldst_mode[1:0] \oper_r__ldst_mode$next - sync posedge \coresync_clk - update \oper_r__ldst_mode $0\oper_r__ldst_mode[1:0] - end - attribute \src "issuer_ls180.v:125914.3-125915.41" - process $proc$issuer_ls180.v:125914$5354 - assign { } { } - assign $0\oper_r__insn[31:0] \oper_r__insn$next - sync posedge \coresync_clk - update \oper_r__insn $0\oper_r__insn[31:0] - end - attribute \src "issuer_ls180.v:125916.3-125917.39" - process $proc$issuer_ls180.v:125916$5355 - assign { } { } - assign $0\lsd_l_r_lsd[0:0] \lsd_l_r_lsd$next - sync posedge \coresync_clk - update \lsd_l_r_lsd $0\lsd_l_r_lsd[0:0] - end - attribute \src "issuer_ls180.v:125918.3-125919.39" - process $proc$issuer_ls180.v:125918$5356 - assign { } { } - assign $0\sto_l_r_sto[0:0] \sto_l_r_sto$next - sync posedge \coresync_clk - update \sto_l_r_sto $0\sto_l_r_sto[0:0] - end - attribute \src "issuer_ls180.v:125920.3-125921.39" - process $proc$issuer_ls180.v:125920$5357 - assign { } { } - assign $0\upd_l_r_upd[0:0] \upd_l_r_upd$next - sync posedge \coresync_clk - update \upd_l_r_upd $0\upd_l_r_upd[0:0] - end - attribute \src "issuer_ls180.v:125922.3-125923.39" - process $proc$issuer_ls180.v:125922$5358 - assign { } { } - assign $0\upd_l_s_upd[0:0] \upd_l_s_upd$next - sync posedge \coresync_clk - update \upd_l_s_upd $0\upd_l_s_upd[0:0] - end - attribute \src "issuer_ls180.v:125924.3-125925.39" - process $proc$issuer_ls180.v:125924$5359 - assign { } { } - assign $0\wri_l_r_wri[0:0] \wri_l_r_wri$next - sync posedge \coresync_clk - update \wri_l_r_wri $0\wri_l_r_wri[0:0] - end - attribute \src "issuer_ls180.v:125926.3-125927.39" - process $proc$issuer_ls180.v:125926$5360 - assign { } { } - assign $0\adr_l_r_adr[0:0] \adr_l_r_adr$next - sync posedge \coresync_clk - update \adr_l_r_adr $0\adr_l_r_adr[0:0] - end - attribute \src "issuer_ls180.v:125928.3-125929.39" - process $proc$issuer_ls180.v:125928$5361 - assign { } { } - assign $0\src_l_r_src[2:0] \src_l_r_src$next - sync posedge \coresync_clk - update \src_l_r_src $0\src_l_r_src[2:0] - end - attribute \src "issuer_ls180.v:125930.3-125931.39" - process $proc$issuer_ls180.v:125930$5362 - assign { } { } - assign $0\src_l_s_src[2:0] \src_l_s_src$next - sync posedge \coresync_clk - update \src_l_s_src $0\src_l_s_src[2:0] - end - attribute \src "issuer_ls180.v:125932.3-125933.39" - process $proc$issuer_ls180.v:125932$5363 - assign { } { } - assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next - sync posedge \coresync_clk - update \opc_l_r_opc $0\opc_l_r_opc[0:0] - end - attribute \src "issuer_ls180.v:125934.3-125935.39" - process $proc$issuer_ls180.v:125934$5364 - assign { } { } - assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next - sync posedge \coresync_clk - update \opc_l_s_opc $0\opc_l_s_opc[0:0] - end - attribute \src "issuer_ls180.v:125936.3-125937.28" - process $proc$issuer_ls180.v:125936$5365 - assign { } { } - assign $0\p_st_go[0:0] \cu_st__go_i - sync posedge \coresync_clk - update \p_st_go $0\p_st_go[0:0] - end - attribute \src "issuer_ls180.v:126008.3-126016.6" - process $proc$issuer_ls180.v:126008$5366 - assign { } { } - assign { } { } - assign $0\opc_l_s_opc$next[0:0]$5367 $1\opc_l_s_opc$next[0:0]$5368 - attribute \src "issuer_ls180.v:126009.5-126009.29" - switch \initial - attribute \src "issuer_ls180.v:126009.9-126009.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_s_opc$next[0:0]$5368 1'0 - case - assign $1\opc_l_s_opc$next[0:0]$5368 \cu_issue_i - end - sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5367 - end - attribute \src "issuer_ls180.v:126017.3-126025.6" - process $proc$issuer_ls180.v:126017$5369 - assign { } { } - assign { } { } - assign $0\opc_l_r_opc$next[0:0]$5370 $1\opc_l_r_opc$next[0:0]$5371 - attribute \src "issuer_ls180.v:126018.5-126018.29" - switch \initial - attribute \src "issuer_ls180.v:126018.9-126018.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_r_opc$next[0:0]$5371 1'1 - case - assign $1\opc_l_r_opc$next[0:0]$5371 \reset_o - end - sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5370 - end - attribute \src "issuer_ls180.v:126026.3-126034.6" - process $proc$issuer_ls180.v:126026$5372 - assign { } { } - assign { } { } - assign $0\src_l_s_src$next[2:0]$5373 $1\src_l_s_src$next[2:0]$5374 - attribute \src "issuer_ls180.v:126027.5-126027.29" - switch \initial - attribute \src "issuer_ls180.v:126027.9-126027.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_s_src$next[2:0]$5374 3'000 - case - assign $1\src_l_s_src$next[2:0]$5374 { \cu_issue_i \cu_issue_i \cu_issue_i } - end - sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5373 - end - attribute \src "issuer_ls180.v:126035.3-126043.6" - process $proc$issuer_ls180.v:126035$5375 - assign { } { } - assign { } { } - assign $0\src_l_r_src$next[2:0]$5376 $1\src_l_r_src$next[2:0]$5377 - attribute \src "issuer_ls180.v:126036.5-126036.29" - switch \initial - attribute \src "issuer_ls180.v:126036.9-126036.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_r_src$next[2:0]$5377 3'111 - case - assign $1\src_l_r_src$next[2:0]$5377 \reset_r - end - sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5376 - end - attribute \src "issuer_ls180.v:126044.3-126052.6" - process $proc$issuer_ls180.v:126044$5378 - assign { } { } - assign { } { } - assign $0\adr_l_r_adr$next[0:0]$5379 $1\adr_l_r_adr$next[0:0]$5380 - attribute \src "issuer_ls180.v:126045.5-126045.29" - switch \initial - attribute \src "issuer_ls180.v:126045.9-126045.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\adr_l_r_adr$next[0:0]$5380 1'1 - case - assign $1\adr_l_r_adr$next[0:0]$5380 \reset_a - end - sync always - update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$5379 - end - attribute \src "issuer_ls180.v:126053.3-126061.6" - process $proc$issuer_ls180.v:126053$5381 - assign { } { } - assign { } { } - assign $0\wri_l_r_wri$next[0:0]$5382 $1\wri_l_r_wri$next[0:0]$5383 - attribute \src "issuer_ls180.v:126054.5-126054.29" - switch \initial - attribute \src "issuer_ls180.v:126054.9-126054.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wri_l_r_wri$next[0:0]$5383 1'1 - case - assign $1\wri_l_r_wri$next[0:0]$5383 \$31 [0] - end - sync always - update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$5382 - end - attribute \src "issuer_ls180.v:126062.3-126070.6" - process $proc$issuer_ls180.v:126062$5384 - assign { } { } - assign { } { } - assign $0\upd_l_s_upd$next[0:0]$5385 $1\upd_l_s_upd$next[0:0]$5386 - attribute \src "issuer_ls180.v:126063.5-126063.29" - switch \initial - attribute \src "issuer_ls180.v:126063.9-126063.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\upd_l_s_upd$next[0:0]$5386 1'0 - case - assign $1\upd_l_s_upd$next[0:0]$5386 \reset_i - end - sync always - update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$5385 - end - attribute \src "issuer_ls180.v:126071.3-126079.6" - process $proc$issuer_ls180.v:126071$5387 - assign { } { } - assign { } { } - assign $0\upd_l_r_upd$next[0:0]$5388 $1\upd_l_r_upd$next[0:0]$5389 - attribute \src "issuer_ls180.v:126072.5-126072.29" - switch \initial - attribute \src "issuer_ls180.v:126072.9-126072.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\upd_l_r_upd$next[0:0]$5389 1'1 - case - assign $1\upd_l_r_upd$next[0:0]$5389 \reset_u - end - sync always - update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$5388 - end - attribute \src "issuer_ls180.v:126080.3-126088.6" - process $proc$issuer_ls180.v:126080$5390 - assign { } { } - assign { } { } - assign $0\sto_l_r_sto$next[0:0]$5391 $1\sto_l_r_sto$next[0:0]$5392 - attribute \src "issuer_ls180.v:126081.5-126081.29" - switch \initial - attribute \src "issuer_ls180.v:126081.9-126081.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sto_l_r_sto$next[0:0]$5392 1'1 - case - assign $1\sto_l_r_sto$next[0:0]$5392 \$52 - end - sync always - update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$5391 - end - attribute \src "issuer_ls180.v:126089.3-126097.6" - process $proc$issuer_ls180.v:126089$5393 - assign { } { } - assign { } { } - assign $0\lsd_l_r_lsd$next[0:0]$5394 $1\lsd_l_r_lsd$next[0:0]$5395 - attribute \src "issuer_ls180.v:126090.5-126090.29" - switch \initial - attribute \src "issuer_ls180.v:126090.9-126090.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\lsd_l_r_lsd$next[0:0]$5395 1'1 - case - assign $1\lsd_l_r_lsd$next[0:0]$5395 \$56 - end - sync always - update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$5394 - end - attribute \src "issuer_ls180.v:126098.3-126140.6" - process $proc$issuer_ls180.v:126098$5396 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\oper_r__byte_reverse$next[0:0]$5397 $2\oper_r__byte_reverse$next[0:0]$5429 - assign $0\oper_r__data_len$next[3:0]$5398 $2\oper_r__data_len$next[3:0]$5430 - assign $0\oper_r__fn_unit$next[11:0]$5399 $2\oper_r__fn_unit$next[11:0]$5431 - assign { } { } - assign { } { } - assign $0\oper_r__insn$next[31:0]$5402 $2\oper_r__insn$next[31:0]$5434 - assign $0\oper_r__insn_type$next[6:0]$5403 $2\oper_r__insn_type$next[6:0]$5435 - assign $0\oper_r__is_32bit$next[0:0]$5404 $2\oper_r__is_32bit$next[0:0]$5436 - assign $0\oper_r__is_signed$next[0:0]$5405 $2\oper_r__is_signed$next[0:0]$5437 - assign $0\oper_r__ldst_mode$next[1:0]$5406 $2\oper_r__ldst_mode$next[1:0]$5438 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\oper_r__sign_extend$next[0:0]$5411 $2\oper_r__sign_extend$next[0:0]$5443 - assign $0\oper_r__zero_a$next[0:0]$5412 $2\oper_r__zero_a$next[0:0]$5444 - assign $0\oper_r__imm_data__data$next[63:0]$5400 $3\oper_r__imm_data__data$next[63:0]$5445 - assign $0\oper_r__imm_data__ok$next[0:0]$5401 $3\oper_r__imm_data__ok$next[0:0]$5446 - assign $0\oper_r__oe__oe$next[0:0]$5407 $3\oper_r__oe__oe$next[0:0]$5447 - assign $0\oper_r__oe__ok$next[0:0]$5408 $3\oper_r__oe__ok$next[0:0]$5448 - assign $0\oper_r__rc__ok$next[0:0]$5409 $3\oper_r__rc__ok$next[0:0]$5449 - assign $0\oper_r__rc__rc$next[0:0]$5410 $3\oper_r__rc__rc$next[0:0]$5450 - attribute \src "issuer_ls180.v:126099.5-126099.29" - switch \initial - attribute \src "issuer_ls180.v:126099.9-126099.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\oper_r__insn$next[31:0]$5418 $1\oper_r__ldst_mode$next[1:0]$5422 $1\oper_r__sign_extend$next[0:0]$5427 $1\oper_r__byte_reverse$next[0:0]$5413 $1\oper_r__data_len$next[3:0]$5414 $1\oper_r__is_signed$next[0:0]$5421 $1\oper_r__is_32bit$next[0:0]$5420 $1\oper_r__oe__ok$next[0:0]$5424 $1\oper_r__oe__oe$next[0:0]$5423 $1\oper_r__rc__ok$next[0:0]$5425 $1\oper_r__rc__rc$next[0:0]$5426 $1\oper_r__zero_a$next[0:0]$5428 $1\oper_r__imm_data__ok$next[0:0]$5417 $1\oper_r__imm_data__data$next[63:0]$5416 $1\oper_r__fn_unit$next[11:0]$5415 $1\oper_r__insn_type$next[6:0]$5419 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } - case - assign $1\oper_r__byte_reverse$next[0:0]$5413 \oper_r__byte_reverse - assign $1\oper_r__data_len$next[3:0]$5414 \oper_r__data_len - assign $1\oper_r__fn_unit$next[11:0]$5415 \oper_r__fn_unit - assign $1\oper_r__imm_data__data$next[63:0]$5416 \oper_r__imm_data__data - assign $1\oper_r__imm_data__ok$next[0:0]$5417 \oper_r__imm_data__ok - assign $1\oper_r__insn$next[31:0]$5418 \oper_r__insn - assign $1\oper_r__insn_type$next[6:0]$5419 \oper_r__insn_type - assign $1\oper_r__is_32bit$next[0:0]$5420 \oper_r__is_32bit - assign $1\oper_r__is_signed$next[0:0]$5421 \oper_r__is_signed - assign $1\oper_r__ldst_mode$next[1:0]$5422 \oper_r__ldst_mode - assign $1\oper_r__oe__oe$next[0:0]$5423 \oper_r__oe__oe - assign $1\oper_r__oe__ok$next[0:0]$5424 \oper_r__oe__ok - assign $1\oper_r__rc__ok$next[0:0]$5425 \oper_r__rc__ok - assign $1\oper_r__rc__rc$next[0:0]$5426 \oper_r__rc__rc - assign $1\oper_r__sign_extend$next[0:0]$5427 \oper_r__sign_extend - assign $1\oper_r__zero_a$next[0:0]$5428 \oper_r__zero_a - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:380" - switch \cu_done_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $2\oper_r__insn$next[31:0]$5434 $2\oper_r__ldst_mode$next[1:0]$5438 $2\oper_r__sign_extend$next[0:0]$5443 $2\oper_r__byte_reverse$next[0:0]$5429 $2\oper_r__data_len$next[3:0]$5430 $2\oper_r__is_signed$next[0:0]$5437 $2\oper_r__is_32bit$next[0:0]$5436 $2\oper_r__oe__ok$next[0:0]$5440 $2\oper_r__oe__oe$next[0:0]$5439 $2\oper_r__rc__ok$next[0:0]$5441 $2\oper_r__rc__rc$next[0:0]$5442 $2\oper_r__zero_a$next[0:0]$5444 $2\oper_r__imm_data__ok$next[0:0]$5433 $2\oper_r__imm_data__data$next[63:0]$5432 $2\oper_r__fn_unit$next[11:0]$5431 $2\oper_r__insn_type$next[6:0]$5435 } 131'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\oper_r__byte_reverse$next[0:0]$5429 $1\oper_r__byte_reverse$next[0:0]$5413 - assign $2\oper_r__data_len$next[3:0]$5430 $1\oper_r__data_len$next[3:0]$5414 - assign $2\oper_r__fn_unit$next[11:0]$5431 $1\oper_r__fn_unit$next[11:0]$5415 - assign $2\oper_r__imm_data__data$next[63:0]$5432 $1\oper_r__imm_data__data$next[63:0]$5416 - assign $2\oper_r__imm_data__ok$next[0:0]$5433 $1\oper_r__imm_data__ok$next[0:0]$5417 - assign $2\oper_r__insn$next[31:0]$5434 $1\oper_r__insn$next[31:0]$5418 - assign $2\oper_r__insn_type$next[6:0]$5435 $1\oper_r__insn_type$next[6:0]$5419 - assign $2\oper_r__is_32bit$next[0:0]$5436 $1\oper_r__is_32bit$next[0:0]$5420 - assign $2\oper_r__is_signed$next[0:0]$5437 $1\oper_r__is_signed$next[0:0]$5421 - assign $2\oper_r__ldst_mode$next[1:0]$5438 $1\oper_r__ldst_mode$next[1:0]$5422 - assign $2\oper_r__oe__oe$next[0:0]$5439 $1\oper_r__oe__oe$next[0:0]$5423 - assign $2\oper_r__oe__ok$next[0:0]$5440 $1\oper_r__oe__ok$next[0:0]$5424 - assign $2\oper_r__rc__ok$next[0:0]$5441 $1\oper_r__rc__ok$next[0:0]$5425 - assign $2\oper_r__rc__rc$next[0:0]$5442 $1\oper_r__rc__rc$next[0:0]$5426 - assign $2\oper_r__sign_extend$next[0:0]$5443 $1\oper_r__sign_extend$next[0:0]$5427 - assign $2\oper_r__zero_a$next[0:0]$5444 $1\oper_r__zero_a$next[0:0]$5428 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $3\oper_r__imm_data__data$next[63:0]$5445 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\oper_r__imm_data__ok$next[0:0]$5446 1'0 - assign $3\oper_r__rc__rc$next[0:0]$5450 1'0 - assign $3\oper_r__rc__ok$next[0:0]$5449 1'0 - assign $3\oper_r__oe__oe$next[0:0]$5447 1'0 - assign $3\oper_r__oe__ok$next[0:0]$5448 1'0 - case - assign $3\oper_r__imm_data__data$next[63:0]$5445 $2\oper_r__imm_data__data$next[63:0]$5432 - assign $3\oper_r__imm_data__ok$next[0:0]$5446 $2\oper_r__imm_data__ok$next[0:0]$5433 - assign $3\oper_r__oe__oe$next[0:0]$5447 $2\oper_r__oe__oe$next[0:0]$5439 - assign $3\oper_r__oe__ok$next[0:0]$5448 $2\oper_r__oe__ok$next[0:0]$5440 - assign $3\oper_r__rc__ok$next[0:0]$5449 $2\oper_r__rc__ok$next[0:0]$5441 - assign $3\oper_r__rc__rc$next[0:0]$5450 $2\oper_r__rc__rc$next[0:0]$5442 - end - sync always - update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$5397 - update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$5398 - update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[11:0]$5399 - update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$5400 - update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$5401 - update \oper_r__insn$next $0\oper_r__insn$next[31:0]$5402 - update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$5403 - update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$5404 - update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$5405 - update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$5406 - update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$5407 - update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$5408 - update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$5409 - update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$5410 - update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$5411 - update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$5412 - end - attribute \src "issuer_ls180.v:126141.3-126150.6" - process $proc$issuer_ls180.v:126141$5451 - assign { } { } - assign { } { } - assign $0\ldo_r$next[63:0]$5452 $1\ldo_r$next[63:0]$5453 - attribute \src "issuer_ls180.v:126142.5-126142.29" - switch \initial - attribute \src "issuer_ls180.v:126142.9-126142.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \ld_ok - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldo_r$next[63:0]$5453 \ldd_o - case - assign $1\ldo_r$next[63:0]$5453 \ldo_r - end - sync always - update \ldo_r$next $0\ldo_r$next[63:0]$5452 - end - attribute \src "issuer_ls180.v:126151.3-126166.6" - process $proc$issuer_ls180.v:126151$5454 - assign { } { } - assign { } { } - assign { } { } - assign $0\src_r0$next[63:0]$5455 $2\src_r0$next[63:0]$5457 - attribute \src "issuer_ls180.v:126152.5-126152.29" - switch \initial - attribute \src "issuer_ls180.v:126152.9-126152.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" - switch \cu_rd__go_i [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r0$next[63:0]$5456 \src1_i - case - assign $1\src_r0$next[63:0]$5456 \src_r0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src_r0$next[63:0]$5457 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\src_r0$next[63:0]$5457 $1\src_r0$next[63:0]$5456 - end - sync always - update \src_r0$next $0\src_r0$next[63:0]$5455 - end - attribute \src "issuer_ls180.v:126167.3-126182.6" - process $proc$issuer_ls180.v:126167$5458 - assign { } { } - assign { } { } - assign { } { } - assign $0\src_r1$next[63:0]$5459 $2\src_r1$next[63:0]$5461 - attribute \src "issuer_ls180.v:126168.5-126168.29" - switch \initial - attribute \src "issuer_ls180.v:126168.9-126168.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" - switch \cu_rd__go_i [1] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r1$next[63:0]$5460 \src2_i - case - assign $1\src_r1$next[63:0]$5460 \src_r1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src_r1$next[63:0]$5461 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\src_r1$next[63:0]$5461 $1\src_r1$next[63:0]$5460 - end - sync always - update \src_r1$next $0\src_r1$next[63:0]$5459 - end - attribute \src "issuer_ls180.v:126183.3-126198.6" - process $proc$issuer_ls180.v:126183$5462 - assign { } { } - assign { } { } - assign { } { } - assign $0\src_r2$next[63:0]$5463 $2\src_r2$next[63:0]$5465 - attribute \src "issuer_ls180.v:126184.5-126184.29" - switch \initial - attribute \src "issuer_ls180.v:126184.9-126184.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" - switch \cu_rd__go_i [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r2$next[63:0]$5464 \src3_i - case - assign $1\src_r2$next[63:0]$5464 \src_r2 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src_r2$next[63:0]$5465 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\src_r2$next[63:0]$5465 $1\src_r2$next[63:0]$5464 - end - sync always - update \src_r2$next $0\src_r2$next[63:0]$5463 - end - attribute \src "issuer_ls180.v:126199.3-126208.6" - process $proc$issuer_ls180.v:126199$5466 - assign { } { } - assign { } { } - assign $0\ea_r$next[63:0]$5467 $1\ea_r$next[63:0]$5468 - attribute \src "issuer_ls180.v:126200.5-126200.29" - switch \initial - attribute \src "issuer_ls180.v:126200.9-126200.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \alu_l_q_alu - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ea_r$next[63:0]$5468 \alu_o - case - assign $1\ea_r$next[63:0]$5468 \ea_r - end - sync always - update \ea_r$next $0\ea_r$next[63:0]$5467 - end - attribute \src "issuer_ls180.v:126209.3-126218.6" - process $proc$issuer_ls180.v:126209$5469 - assign { } { } - assign { } { } - assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "issuer_ls180.v:126210.5-126210.29" - switch \initial - attribute \src "issuer_ls180.v:126210.9-126210.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:471" - switch \cu_wr__go_i [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest1_o[63:0] \ldd_r - case - assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest1_o $0\dest1_o[63:0] - end - attribute \src "issuer_ls180.v:126219.3-126228.6" - process $proc$issuer_ls180.v:126219$5470 - assign { } { } - assign { } { } - assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "issuer_ls180.v:126220.5-126220.29" - switch \initial - attribute \src "issuer_ls180.v:126220.9-126220.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:476" - switch \$157 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest2_o[63:0] \addr_r - case - assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest2_o $0\dest2_o[63:0] - end - attribute \src "issuer_ls180.v:126229.3-126237.6" - process $proc$issuer_ls180.v:126229$5471 - assign { } { } - assign { } { } - assign $0\ldst_port0_addr_i_ok$next[0:0]$5472 $1\ldst_port0_addr_i_ok$next[0:0]$5473 - attribute \src "issuer_ls180.v:126230.5-126230.29" - switch \initial - attribute \src "issuer_ls180.v:126230.9-126230.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_addr_i_ok$next[0:0]$5473 1'0 - case - assign $1\ldst_port0_addr_i_ok$next[0:0]$5473 \$170 - end - sync always - update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$5472 - end - attribute \src "issuer_ls180.v:126238.3-126261.6" - process $proc$issuer_ls180.v:126238$5474 - assign { } { } - assign { } { } - assign $0\lddata_r[63:0] $1\lddata_r[63:0] - attribute \src "issuer_ls180.v:126239.5-126239.29" - switch \initial - attribute \src "issuer_ls180.v:126239.9-126239.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" - switch \oper_r__byte_reverse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\lddata_r[63:0] $2\lddata_r[63:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:22" - switch \oper_r__data_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $2\lddata_r[63:0] \$172 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $2\lddata_r[63:0] \$174 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $2\lddata_r[63:0] \$176 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $2\lddata_r[63:0] { \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] \ldst_port0_ld_data_o [39:32] \ldst_port0_ld_data_o [47:40] \ldst_port0_ld_data_o [55:48] \ldst_port0_ld_data_o [63:56] } - case - assign $2\lddata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\lddata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \lddata_r $0\lddata_r[63:0] - end - attribute \src "issuer_ls180.v:126262.3-126273.6" - process $proc$issuer_ls180.v:126262$5475 - assign { } { } - assign $0\revnorev[63:0] $1\revnorev[63:0] - attribute \src "issuer_ls180.v:126263.5-126263.29" - switch \initial - attribute \src "issuer_ls180.v:126263.9-126263.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" - switch \oper_r__byte_reverse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\revnorev[63:0] \lddata_r - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\revnorev[63:0] \ldst_port0_ld_data_o - end - sync always - update \revnorev $0\revnorev[63:0] - end - attribute \src "issuer_ls180.v:126274.3-126293.6" - process $proc$issuer_ls180.v:126274$5476 - assign { } { } - assign $0\ldd_o[63:0] $1\ldd_o[63:0] - attribute \src "issuer_ls180.v:126275.5-126275.29" - switch \initial - attribute \src "issuer_ls180.v:126275.9-126275.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:508" - switch \oper_r__sign_extend - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldd_o[63:0] $2\ldd_o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:510" - switch \$178 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ldd_o[63:0] { \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15:0] } - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\ldd_o[63:0] { \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31:0] } - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\ldd_o[63:0] \revnorev - end - sync always - update \ldd_o $0\ldd_o[63:0] - end - attribute \src "issuer_ls180.v:126294.3-126317.6" - process $proc$issuer_ls180.v:126294$5477 - assign { } { } - assign { } { } - assign $0\stdata_r[63:0] $1\stdata_r[63:0] - attribute \src "issuer_ls180.v:126295.5-126295.29" - switch \initial - attribute \src "issuer_ls180.v:126295.9-126295.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:522" - switch \oper_r__byte_reverse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\stdata_r[63:0] $2\stdata_r[63:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:22" - switch \oper_r__data_len - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $2\stdata_r[63:0] \$180 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $2\stdata_r[63:0] \$182 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $2\stdata_r[63:0] \$184 - attribute \src "issuer_ls180.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $2\stdata_r[63:0] { \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] \src_r2 [39:32] \src_r2 [47:40] \src_r2 [55:48] \src_r2 [63:56] } - case - assign $2\stdata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\stdata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \stdata_r $0\stdata_r[63:0] - end - attribute \src "issuer_ls180.v:126318.3-126329.6" - process $proc$issuer_ls180.v:126318$5478 - assign { } { } - assign $0\ldst_port0_st_data_i[63:0] $1\ldst_port0_st_data_i[63:0] - attribute \src "issuer_ls180.v:126319.5-126319.29" - switch \initial - attribute \src "issuer_ls180.v:126319.9-126319.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:522" - switch \oper_r__byte_reverse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_st_data_i[63:0] \stdata_r - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\ldst_port0_st_data_i[63:0] \src_r2 - end - sync always - update \ldst_port0_st_data_i $0\ldst_port0_st_data_i[63:0] - end - connect \$9 $or$issuer_ls180.v:125777$5237_Y - connect \$99 $and$issuer_ls180.v:125778$5238_Y - connect \$101 $and$issuer_ls180.v:125779$5239_Y - connect \$103 $and$issuer_ls180.v:125780$5240_Y - connect \$105 $and$issuer_ls180.v:125781$5241_Y - connect \$107 $and$issuer_ls180.v:125782$5242_Y - connect \$109 $and$issuer_ls180.v:125783$5243_Y - connect \$111 $and$issuer_ls180.v:125784$5244_Y - connect \$113 $and$issuer_ls180.v:125785$5245_Y - connect \$115 $and$issuer_ls180.v:125786$5246_Y - connect \$117 $and$issuer_ls180.v:125787$5247_Y - connect \$11 $or$issuer_ls180.v:125788$5248_Y - connect \$119 $eq$issuer_ls180.v:125789$5249_Y - connect \$121 $and$issuer_ls180.v:125790$5250_Y - connect \$123 $and$issuer_ls180.v:125791$5251_Y - connect \$125 $and$issuer_ls180.v:125792$5252_Y - connect \$127 $or$issuer_ls180.v:125793$5253_Y - connect \$129 $or$issuer_ls180.v:125794$5254_Y - connect \$131 $or$issuer_ls180.v:125795$5255_Y - connect \$133 $and$issuer_ls180.v:125796$5256_Y - connect \$135 $and$issuer_ls180.v:125797$5257_Y - connect \$138 $or$issuer_ls180.v:125798$5258_Y - connect \$13 $or$issuer_ls180.v:125799$5259_Y - connect \$140 $or$issuer_ls180.v:125800$5260_Y - connect \$137 $not$issuer_ls180.v:125801$5261_Y - connect \$143 $and$issuer_ls180.v:125802$5262_Y - connect \$145 $or$issuer_ls180.v:125803$5263_Y - connect \$147 $and$issuer_ls180.v:125804$5264_Y - connect \$149 $not$issuer_ls180.v:125805$5265_Y - connect \$151 $or$issuer_ls180.v:125806$5266_Y - connect \$153 $and$issuer_ls180.v:125807$5267_Y - connect \$155 $eq$issuer_ls180.v:125808$5268_Y - connect \$157 $and$issuer_ls180.v:125809$5269_Y - connect \$15 $eq$issuer_ls180.v:125810$5270_Y - connect \$160 $eq$issuer_ls180.v:125811$5271_Y - connect \$162 $and$issuer_ls180.v:125812$5272_Y - connect \$164 $and$issuer_ls180.v:125813$5273_Y - connect \$166 $and$issuer_ls180.v:125814$5274_Y - connect \$168 $pos$issuer_ls180.v:125815$5276_Y - connect \$170 $and$issuer_ls180.v:125816$5277_Y - connect \$172 $pos$issuer_ls180.v:125817$5279_Y - connect \$174 $pos$issuer_ls180.v:125818$5280_Y - connect \$176 $pos$issuer_ls180.v:125819$5281_Y - connect \$178 $eq$issuer_ls180.v:125820$5282_Y - connect \$17 $eq$issuer_ls180.v:125821$5283_Y - connect \$180 $pos$issuer_ls180.v:125822$5285_Y - connect \$182 $pos$issuer_ls180.v:125823$5286_Y - connect \$184 $pos$issuer_ls180.v:125824$5287_Y - connect \$1 $or$issuer_ls180.v:125825$5288_Y - connect \$19 $and$issuer_ls180.v:125826$5289_Y - connect \$21 $and$issuer_ls180.v:125827$5290_Y - connect \$23 $not$issuer_ls180.v:125828$5291_Y - connect \$25 $and$issuer_ls180.v:125829$5292_Y - connect \$27 $not$issuer_ls180.v:125830$5293_Y - connect \$29 $and$issuer_ls180.v:125831$5294_Y - connect \$32 $not$issuer_ls180.v:125832$5295_Y - connect \$34 $eq$issuer_ls180.v:125833$5296_Y - connect \$36 $and$issuer_ls180.v:125834$5297_Y - connect \$38 $or$issuer_ls180.v:125835$5298_Y - connect \$3 $or$issuer_ls180.v:125836$5299_Y - connect \$40 $not$issuer_ls180.v:125837$5300_Y - connect \$42 $eq$issuer_ls180.v:125838$5301_Y - connect \$44 $and$issuer_ls180.v:125839$5302_Y - connect \$46 $or$issuer_ls180.v:125840$5303_Y - connect \$48 $or$issuer_ls180.v:125841$5304_Y - connect \$50 $and$issuer_ls180.v:125842$5305_Y - connect \$52 $or$issuer_ls180.v:125843$5306_Y - connect \$54 $or$issuer_ls180.v:125844$5307_Y - connect \$56 $or$issuer_ls180.v:125845$5308_Y - connect \$58 $ternary$issuer_ls180.v:125846$5309_Y - connect \$5 $or$issuer_ls180.v:125847$5310_Y - connect \$60 $ternary$issuer_ls180.v:125848$5311_Y - connect \$62 $ternary$issuer_ls180.v:125849$5312_Y - connect \$64 $ternary$issuer_ls180.v:125850$5313_Y - connect \$67 $add$issuer_ls180.v:125851$5314_Y - connect \$69 $and$issuer_ls180.v:125852$5315_Y - connect \$71 $not$issuer_ls180.v:125853$5316_Y - connect \$73 $and$issuer_ls180.v:125854$5317_Y - connect \$75 $not$issuer_ls180.v:125855$5318_Y - connect \$77 $and$issuer_ls180.v:125856$5319_Y - connect \$7 $or$issuer_ls180.v:125857$5320_Y - connect \$79 $and$issuer_ls180.v:125858$5321_Y - connect \$81 $and$issuer_ls180.v:125859$5322_Y - connect \$83 $or$issuer_ls180.v:125860$5323_Y - connect \$86 $or$issuer_ls180.v:125861$5324_Y - connect \$85 $not$issuer_ls180.v:125862$5325_Y - connect \$89 $and$issuer_ls180.v:125863$5326_Y - connect \$91 $not$issuer_ls180.v:125864$5327_Y - connect \$93 $and$issuer_ls180.v:125865$5328_Y - connect \$95 $and$issuer_ls180.v:125866$5329_Y - connect \$97 $and$issuer_ls180.v:125867$5330_Y - connect \$31 \$48 - connect \$66 \$67 - connect \$159 \$162 - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 - connect \ldst_port0_st_data_i_ok \cu_st__go_i - connect \ld_ok \ldst_port0_ld_data_o_ok - connect \addr_ok \ldst_port0_addr_ok_o - connect \addr_exc_o \ldst_port0_addr_exc_o - connect \ldst_port0_addr_i$next \$168 - connect \ldst_port0_data_len \oper_r__data_len - connect \ldst_port0_is_st_i \$166 - connect \ldst_port0_is_ld_i \$164 - connect \cu_wrmask_o \$162 [1:0] - connect \ea \dest2_o - connect \o \dest1_o - connect \cu_done_o \$153 - connect \wr_reset \$147 - connect \wr_any \$131 - connect \cu_wr__rel_o [1] \$125 - connect \cu_wr__rel_o [0] \$115 - connect \cu_st__rel_o \$105 - connect \cu_ad__rel_o \$97 - connect \rd_done \$93 - connect \alu_valid \$89 - connect \rda_any \$83 - connect \cu_rd__rel_o [2] \$81 - connect \cu_rd__rel_o [1:0] \$77 [1:0] - connect \cu_busy_o \opc_l_q_opc - connect \alu_ok$next \alu_valid - connect \alu_o \$67 [63:0] - connect \src2_or_imm \$64 - connect \src1_or_z \$62 - connect \addr_r \$60 - connect \ldd_r \$58 - connect \rst_l_r_rst \cu_issue_i - connect \rst_l_s_rst \addr_ok - connect \lsd_l_s_lsd \cu_issue_i - connect \sto_l_s_sto \$50 - connect \wri_l_s_wri \cu_issue_i - connect \lod_l_r_lod \ld_ok - connect \lod_l_s_lod \reset_i - connect \adr_l_s_adr \reset_i - connect \alu_l_r_alu \$29 - connect \alu_l_s_alu \reset_i - connect \st_o \op_is_st - connect \ld_o \op_is_ld - connect \stwd_mem_o \$21 - connect \load_mem_o \$19 - connect \op_is_ld \$17 - connect \op_is_st \$15 - connect \p_st_go$next \cu_st__go_i - connect \reset_a \$13 - connect \reset_r \$11 - connect \reset_s \$9 - connect \reset_u \$7 - connect \reset_w \$5 - connect \reset_o \$3 - connect \reset_i \$1 -end -attribute \src "issuer_ls180.v:126393.1-126980.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" -attribute \generator "nMigen" -module \left_mask - attribute \src "issuer_ls180.v:126394.7-126394.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire width 64 $0\mask[63:0] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $10\mask[9:9] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $11\mask[10:10] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $12\mask[11:11] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $13\mask[12:12] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $14\mask[13:13] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $15\mask[14:14] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $16\mask[15:15] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $17\mask[16:16] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $18\mask[17:17] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $19\mask[18:18] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $1\mask[0:0] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $20\mask[19:19] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $21\mask[20:20] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $22\mask[21:21] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $23\mask[22:22] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $24\mask[23:23] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $25\mask[24:24] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $26\mask[25:25] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $27\mask[26:26] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $28\mask[27:27] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $29\mask[28:28] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $2\mask[1:1] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $30\mask[29:29] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $31\mask[30:30] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $32\mask[31:31] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $33\mask[32:32] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $34\mask[33:33] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $35\mask[34:34] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $36\mask[35:35] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $37\mask[36:36] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $38\mask[37:37] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $39\mask[38:38] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $3\mask[2:2] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $40\mask[39:39] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $41\mask[40:40] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $42\mask[41:41] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $43\mask[42:42] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $44\mask[43:43] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $45\mask[44:44] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $46\mask[45:45] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $47\mask[46:46] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $48\mask[47:47] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $49\mask[48:48] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $4\mask[3:3] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $50\mask[49:49] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $51\mask[50:50] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $52\mask[51:51] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $53\mask[52:52] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $54\mask[53:53] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $55\mask[54:54] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $56\mask[55:55] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $57\mask[56:56] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $58\mask[57:57] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $59\mask[58:58] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $5\mask[4:4] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $60\mask[59:59] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $61\mask[60:60] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $62\mask[61:61] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $63\mask[62:62] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $64\mask[63:63] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $6\mask[5:5] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $7\mask[6:6] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $8\mask[7:7] - attribute \src "issuer_ls180.v:126592.3-126979.6" - wire $9\mask[8:8] - attribute \src "issuer_ls180.v:126528.17-126528.96" - wire $gt$issuer_ls180.v:126528$5515_Y - attribute \src "issuer_ls180.v:126529.18-126529.98" - wire $gt$issuer_ls180.v:126529$5516_Y - attribute \src "issuer_ls180.v:126530.19-126530.99" - wire $gt$issuer_ls180.v:126530$5517_Y - attribute \src "issuer_ls180.v:126531.19-126531.99" - wire $gt$issuer_ls180.v:126531$5518_Y - attribute \src "issuer_ls180.v:126532.19-126532.99" - wire $gt$issuer_ls180.v:126532$5519_Y - attribute \src "issuer_ls180.v:126533.19-126533.99" - wire $gt$issuer_ls180.v:126533$5520_Y - attribute \src "issuer_ls180.v:126534.19-126534.99" - wire $gt$issuer_ls180.v:126534$5521_Y - attribute \src "issuer_ls180.v:126535.19-126535.99" - wire $gt$issuer_ls180.v:126535$5522_Y - attribute \src "issuer_ls180.v:126536.19-126536.99" - wire $gt$issuer_ls180.v:126536$5523_Y - attribute \src "issuer_ls180.v:126537.19-126537.99" - wire $gt$issuer_ls180.v:126537$5524_Y - attribute \src "issuer_ls180.v:126538.19-126538.99" - wire $gt$issuer_ls180.v:126538$5525_Y - attribute \src "issuer_ls180.v:126539.18-126539.97" - wire $gt$issuer_ls180.v:126539$5526_Y - attribute \src "issuer_ls180.v:126540.19-126540.99" - wire $gt$issuer_ls180.v:126540$5527_Y - attribute \src "issuer_ls180.v:126541.19-126541.99" - wire $gt$issuer_ls180.v:126541$5528_Y - attribute \src "issuer_ls180.v:126542.19-126542.99" - wire $gt$issuer_ls180.v:126542$5529_Y - attribute \src "issuer_ls180.v:126543.19-126543.99" - wire $gt$issuer_ls180.v:126543$5530_Y - attribute \src "issuer_ls180.v:126544.19-126544.99" - wire $gt$issuer_ls180.v:126544$5531_Y - attribute \src "issuer_ls180.v:126545.18-126545.97" - wire $gt$issuer_ls180.v:126545$5532_Y - attribute \src "issuer_ls180.v:126546.18-126546.97" - wire $gt$issuer_ls180.v:126546$5533_Y - attribute \src "issuer_ls180.v:126547.18-126547.97" - wire $gt$issuer_ls180.v:126547$5534_Y - attribute \src "issuer_ls180.v:126548.17-126548.96" - wire $gt$issuer_ls180.v:126548$5535_Y - attribute \src "issuer_ls180.v:126549.18-126549.97" - wire $gt$issuer_ls180.v:126549$5536_Y - attribute \src "issuer_ls180.v:126550.18-126550.97" - wire $gt$issuer_ls180.v:126550$5537_Y - attribute \src "issuer_ls180.v:126551.18-126551.97" - wire $gt$issuer_ls180.v:126551$5538_Y - attribute \src "issuer_ls180.v:126552.18-126552.97" - wire $gt$issuer_ls180.v:126552$5539_Y - attribute \src "issuer_ls180.v:126553.18-126553.97" - wire $gt$issuer_ls180.v:126553$5540_Y - attribute \src "issuer_ls180.v:126554.18-126554.97" - wire $gt$issuer_ls180.v:126554$5541_Y - attribute \src "issuer_ls180.v:126555.18-126555.97" - wire $gt$issuer_ls180.v:126555$5542_Y - attribute \src "issuer_ls180.v:126556.18-126556.98" - wire $gt$issuer_ls180.v:126556$5543_Y - attribute \src "issuer_ls180.v:126557.18-126557.98" - wire $gt$issuer_ls180.v:126557$5544_Y - attribute \src "issuer_ls180.v:126558.18-126558.98" - wire $gt$issuer_ls180.v:126558$5545_Y - attribute \src "issuer_ls180.v:126559.17-126559.96" - wire $gt$issuer_ls180.v:126559$5546_Y - attribute \src "issuer_ls180.v:126560.18-126560.98" - wire $gt$issuer_ls180.v:126560$5547_Y - attribute \src "issuer_ls180.v:126561.18-126561.98" - wire $gt$issuer_ls180.v:126561$5548_Y - attribute \src "issuer_ls180.v:126562.18-126562.98" - wire $gt$issuer_ls180.v:126562$5549_Y - attribute \src "issuer_ls180.v:126563.18-126563.98" - wire $gt$issuer_ls180.v:126563$5550_Y - attribute \src "issuer_ls180.v:126564.18-126564.98" - wire $gt$issuer_ls180.v:126564$5551_Y - attribute \src "issuer_ls180.v:126565.18-126565.98" - wire $gt$issuer_ls180.v:126565$5552_Y - attribute \src "issuer_ls180.v:126566.18-126566.98" - wire $gt$issuer_ls180.v:126566$5553_Y - attribute \src "issuer_ls180.v:126567.18-126567.98" - wire $gt$issuer_ls180.v:126567$5554_Y - attribute \src "issuer_ls180.v:126568.18-126568.98" - wire $gt$issuer_ls180.v:126568$5555_Y - attribute \src "issuer_ls180.v:126569.18-126569.98" - wire $gt$issuer_ls180.v:126569$5556_Y - attribute \src "issuer_ls180.v:126570.17-126570.96" - wire $gt$issuer_ls180.v:126570$5557_Y - attribute \src "issuer_ls180.v:126571.18-126571.98" - wire $gt$issuer_ls180.v:126571$5558_Y - attribute \src "issuer_ls180.v:126572.18-126572.98" - wire $gt$issuer_ls180.v:126572$5559_Y - attribute \src "issuer_ls180.v:126573.18-126573.98" - wire $gt$issuer_ls180.v:126573$5560_Y - attribute \src "issuer_ls180.v:126574.18-126574.98" - wire $gt$issuer_ls180.v:126574$5561_Y - attribute \src "issuer_ls180.v:126575.18-126575.98" - wire $gt$issuer_ls180.v:126575$5562_Y - attribute \src "issuer_ls180.v:126576.18-126576.98" - wire $gt$issuer_ls180.v:126576$5563_Y - attribute \src "issuer_ls180.v:126577.18-126577.98" - wire $gt$issuer_ls180.v:126577$5564_Y - attribute \src "issuer_ls180.v:126578.18-126578.98" - wire $gt$issuer_ls180.v:126578$5565_Y - attribute \src "issuer_ls180.v:126579.18-126579.98" - wire $gt$issuer_ls180.v:126579$5566_Y - attribute \src "issuer_ls180.v:126580.18-126580.98" - wire $gt$issuer_ls180.v:126580$5567_Y - attribute \src "issuer_ls180.v:126581.17-126581.96" - wire $gt$issuer_ls180.v:126581$5568_Y - attribute \src "issuer_ls180.v:126582.18-126582.98" - wire $gt$issuer_ls180.v:126582$5569_Y - attribute \src "issuer_ls180.v:126583.18-126583.98" - wire $gt$issuer_ls180.v:126583$5570_Y - attribute \src "issuer_ls180.v:126584.18-126584.98" - wire $gt$issuer_ls180.v:126584$5571_Y - attribute \src "issuer_ls180.v:126585.18-126585.98" - wire $gt$issuer_ls180.v:126585$5572_Y - attribute \src "issuer_ls180.v:126586.18-126586.98" - wire $gt$issuer_ls180.v:126586$5573_Y - attribute \src "issuer_ls180.v:126587.18-126587.98" - wire $gt$issuer_ls180.v:126587$5574_Y - attribute \src "issuer_ls180.v:126588.18-126588.98" - wire $gt$issuer_ls180.v:126588$5575_Y - attribute \src "issuer_ls180.v:126589.18-126589.98" - wire $gt$issuer_ls180.v:126589$5576_Y - attribute \src "issuer_ls180.v:126590.18-126590.98" - wire $gt$issuer_ls180.v:126590$5577_Y - attribute \src "issuer_ls180.v:126591.18-126591.98" - wire $gt$issuer_ls180.v:126591$5578_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$1 - attribute \src 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\$121 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$123 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$125 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$127 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$37 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$39 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$41 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$43 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$45 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$47 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$53 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$55 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$57 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$59 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$61 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$63 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$65 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$67 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$69 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$71 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$73 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$75 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$77 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$79 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$83 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$85 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$87 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$89 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$91 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$93 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$95 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$97 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$99 - attribute \src "issuer_ls180.v:126394.7-126394.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:12" - wire width 64 output 1 \mask - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:11" - wire width 7 input 2 \shift - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126528$5515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 3'100 - connect \Y $gt$issuer_ls180.v:126528$5515_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126529$5516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110001 - connect \Y $gt$issuer_ls180.v:126529$5516_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126530$5517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110010 - connect \Y $gt$issuer_ls180.v:126530$5517_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126531$5518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110011 - connect \Y $gt$issuer_ls180.v:126531$5518_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126532$5519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110100 - connect \Y $gt$issuer_ls180.v:126532$5519_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126533$5520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110101 - connect \Y $gt$issuer_ls180.v:126533$5520_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126534$5521 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110110 - connect \Y $gt$issuer_ls180.v:126534$5521_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126535$5522 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110111 - connect \Y $gt$issuer_ls180.v:126535$5522_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126536$5523 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111000 - connect \Y $gt$issuer_ls180.v:126536$5523_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126537$5524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111001 - connect \Y $gt$issuer_ls180.v:126537$5524_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126538$5525 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111010 - connect \Y $gt$issuer_ls180.v:126538$5525_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126539$5526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 3'101 - connect \Y $gt$issuer_ls180.v:126539$5526_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126540$5527 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111011 - connect \Y $gt$issuer_ls180.v:126540$5527_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126541$5528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111100 - connect \Y $gt$issuer_ls180.v:126541$5528_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126542$5529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111101 - connect \Y $gt$issuer_ls180.v:126542$5529_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126543$5530 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111110 - connect \Y $gt$issuer_ls180.v:126543$5530_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126544$5531 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111111 - connect \Y $gt$issuer_ls180.v:126544$5531_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126545$5532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 3'110 - connect \Y $gt$issuer_ls180.v:126545$5532_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126546$5533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 3'111 - connect \Y $gt$issuer_ls180.v:126546$5533_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126547$5534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1000 - connect \Y $gt$issuer_ls180.v:126547$5534_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126548$5535 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 1'0 - connect \Y $gt$issuer_ls180.v:126548$5535_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126549$5536 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1001 - connect \Y $gt$issuer_ls180.v:126549$5536_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126550$5537 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1010 - connect \Y $gt$issuer_ls180.v:126550$5537_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126551$5538 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1011 - connect \Y $gt$issuer_ls180.v:126551$5538_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126552$5539 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1100 - connect \Y $gt$issuer_ls180.v:126552$5539_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126553$5540 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1101 - connect \Y $gt$issuer_ls180.v:126553$5540_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126554$5541 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1110 - connect \Y $gt$issuer_ls180.v:126554$5541_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126555$5542 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1111 - connect \Y $gt$issuer_ls180.v:126555$5542_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126556$5543 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10000 - connect \Y $gt$issuer_ls180.v:126556$5543_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126557$5544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10001 - connect \Y $gt$issuer_ls180.v:126557$5544_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126558$5545 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10010 - connect \Y $gt$issuer_ls180.v:126558$5545_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126559$5546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 1'1 - connect \Y $gt$issuer_ls180.v:126559$5546_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126560$5547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10011 - connect \Y $gt$issuer_ls180.v:126560$5547_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126561$5548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10100 - connect \Y $gt$issuer_ls180.v:126561$5548_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126562$5549 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10101 - connect \Y $gt$issuer_ls180.v:126562$5549_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126563$5550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10110 - connect \Y $gt$issuer_ls180.v:126563$5550_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126564$5551 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10111 - connect \Y $gt$issuer_ls180.v:126564$5551_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126565$5552 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11000 - connect \Y $gt$issuer_ls180.v:126565$5552_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126566$5553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11001 - connect \Y $gt$issuer_ls180.v:126566$5553_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126567$5554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11010 - connect \Y $gt$issuer_ls180.v:126567$5554_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126568$5555 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11011 - connect \Y $gt$issuer_ls180.v:126568$5555_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126569$5556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11100 - connect \Y $gt$issuer_ls180.v:126569$5556_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126570$5557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 2'10 - connect \Y $gt$issuer_ls180.v:126570$5557_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126571$5558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11101 - connect \Y $gt$issuer_ls180.v:126571$5558_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126572$5559 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11110 - connect \Y $gt$issuer_ls180.v:126572$5559_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126573$5560 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11111 - connect \Y $gt$issuer_ls180.v:126573$5560_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126574$5561 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100000 - connect \Y $gt$issuer_ls180.v:126574$5561_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126575$5562 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100001 - connect \Y $gt$issuer_ls180.v:126575$5562_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126576$5563 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100010 - connect \Y $gt$issuer_ls180.v:126576$5563_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126577$5564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100011 - connect \Y $gt$issuer_ls180.v:126577$5564_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126578$5565 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100100 - connect \Y $gt$issuer_ls180.v:126578$5565_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126579$5566 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100101 - connect \Y $gt$issuer_ls180.v:126579$5566_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126580$5567 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100110 - connect \Y $gt$issuer_ls180.v:126580$5567_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126581$5568 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 2'11 - connect \Y $gt$issuer_ls180.v:126581$5568_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126582$5569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100111 - connect \Y $gt$issuer_ls180.v:126582$5569_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126583$5570 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101000 - connect \Y $gt$issuer_ls180.v:126583$5570_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126584$5571 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101001 - connect \Y $gt$issuer_ls180.v:126584$5571_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126585$5572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101010 - connect \Y $gt$issuer_ls180.v:126585$5572_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126586$5573 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101011 - connect \Y $gt$issuer_ls180.v:126586$5573_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126587$5574 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101100 - connect \Y $gt$issuer_ls180.v:126587$5574_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126588$5575 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101101 - connect \Y $gt$issuer_ls180.v:126588$5575_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126589$5576 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101110 - connect \Y $gt$issuer_ls180.v:126589$5576_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126590$5577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101111 - connect \Y $gt$issuer_ls180.v:126590$5577_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:126591$5578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110000 - connect \Y $gt$issuer_ls180.v:126591$5578_Y - end - attribute \src "issuer_ls180.v:126394.7-126394.20" - process $proc$issuer_ls180.v:126394$5580 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:126592.3-126979.6" - process $proc$issuer_ls180.v:126592$5579 - assign { } { } - assign { } { } - assign $0\mask[63:0] [0] $1\mask[0:0] - assign $0\mask[63:0] [1] $2\mask[1:1] - assign $0\mask[63:0] [2] $3\mask[2:2] - assign $0\mask[63:0] [3] $4\mask[3:3] - assign $0\mask[63:0] [4] $5\mask[4:4] - assign $0\mask[63:0] [5] $6\mask[5:5] - assign $0\mask[63:0] [6] $7\mask[6:6] - assign $0\mask[63:0] [7] $8\mask[7:7] - assign $0\mask[63:0] [8] $9\mask[8:8] - assign $0\mask[63:0] [9] $10\mask[9:9] - assign $0\mask[63:0] [10] $11\mask[10:10] - assign $0\mask[63:0] [11] $12\mask[11:11] - assign $0\mask[63:0] [12] $13\mask[12:12] - assign $0\mask[63:0] [13] $14\mask[13:13] - assign $0\mask[63:0] [14] $15\mask[14:14] - assign $0\mask[63:0] [15] $16\mask[15:15] - assign $0\mask[63:0] [16] $17\mask[16:16] - assign $0\mask[63:0] [17] $18\mask[17:17] - assign $0\mask[63:0] [18] $19\mask[18:18] - assign $0\mask[63:0] [19] $20\mask[19:19] - assign $0\mask[63:0] [20] $21\mask[20:20] - assign $0\mask[63:0] [21] $22\mask[21:21] - assign $0\mask[63:0] [22] $23\mask[22:22] - assign $0\mask[63:0] [23] $24\mask[23:23] - assign $0\mask[63:0] [24] $25\mask[24:24] - assign $0\mask[63:0] [25] $26\mask[25:25] - assign $0\mask[63:0] [26] $27\mask[26:26] - assign $0\mask[63:0] [27] $28\mask[27:27] - assign $0\mask[63:0] [28] $29\mask[28:28] - assign $0\mask[63:0] [29] $30\mask[29:29] - assign $0\mask[63:0] [30] $31\mask[30:30] - assign $0\mask[63:0] [31] $32\mask[31:31] - assign $0\mask[63:0] [32] $33\mask[32:32] - assign $0\mask[63:0] [33] $34\mask[33:33] - assign $0\mask[63:0] [34] $35\mask[34:34] - assign $0\mask[63:0] [35] $36\mask[35:35] - assign $0\mask[63:0] [36] $37\mask[36:36] - assign $0\mask[63:0] [37] $38\mask[37:37] - assign $0\mask[63:0] [38] $39\mask[38:38] - assign $0\mask[63:0] [39] $40\mask[39:39] - assign $0\mask[63:0] [40] $41\mask[40:40] - assign $0\mask[63:0] [41] $42\mask[41:41] - assign $0\mask[63:0] [42] $43\mask[42:42] - assign $0\mask[63:0] [43] $44\mask[43:43] - assign $0\mask[63:0] [44] $45\mask[44:44] - assign $0\mask[63:0] [45] $46\mask[45:45] - assign $0\mask[63:0] [46] $47\mask[46:46] - assign $0\mask[63:0] [47] $48\mask[47:47] - assign $0\mask[63:0] [48] $49\mask[48:48] - assign $0\mask[63:0] [49] $50\mask[49:49] - assign $0\mask[63:0] [50] $51\mask[50:50] - assign $0\mask[63:0] [51] $52\mask[51:51] - assign $0\mask[63:0] [52] $53\mask[52:52] - assign $0\mask[63:0] [53] $54\mask[53:53] - assign $0\mask[63:0] [54] $55\mask[54:54] - assign $0\mask[63:0] [55] $56\mask[55:55] - assign $0\mask[63:0] [56] $57\mask[56:56] - assign $0\mask[63:0] [57] $58\mask[57:57] - assign $0\mask[63:0] [58] $59\mask[58:58] - assign $0\mask[63:0] [59] $60\mask[59:59] - assign $0\mask[63:0] [60] $61\mask[60:60] - assign $0\mask[63:0] [61] $62\mask[61:61] - assign $0\mask[63:0] [62] $63\mask[62:62] - assign $0\mask[63:0] [63] $64\mask[63:63] - attribute \src "issuer_ls180.v:126593.5-126593.29" - switch \initial - attribute \src "issuer_ls180.v:126593.9-126593.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\mask[0:0] 1'1 - case - assign $1\mask[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\mask[1:1] 1'1 - case - assign $2\mask[1:1] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$5 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\mask[2:2] 1'1 - case - assign $3\mask[2:2] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\mask[3:3] 1'1 - case - assign $4\mask[3:3] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\mask[4:4] 1'1 - case - assign $5\mask[4:4] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$11 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\mask[5:5] 1'1 - case - assign $6\mask[5:5] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$13 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\mask[6:6] 1'1 - case - assign $7\mask[6:6] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$15 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $8\mask[7:7] 1'1 - case - assign $8\mask[7:7] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$17 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $9\mask[8:8] 1'1 - case - assign $9\mask[8:8] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$19 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $10\mask[9:9] 1'1 - case - assign $10\mask[9:9] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$21 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $11\mask[10:10] 1'1 - case - assign $11\mask[10:10] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$23 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $12\mask[11:11] 1'1 - case - assign $12\mask[11:11] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$25 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $13\mask[12:12] 1'1 - case - assign $13\mask[12:12] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$27 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $14\mask[13:13] 1'1 - case - assign $14\mask[13:13] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$29 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $15\mask[14:14] 1'1 - case - assign $15\mask[14:14] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$31 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $16\mask[15:15] 1'1 - case - assign $16\mask[15:15] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$33 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $17\mask[16:16] 1'1 - case - assign $17\mask[16:16] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$35 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $18\mask[17:17] 1'1 - case - assign $18\mask[17:17] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$37 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $19\mask[18:18] 1'1 - case - assign $19\mask[18:18] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$39 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $20\mask[19:19] 1'1 - case - assign $20\mask[19:19] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$41 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $21\mask[20:20] 1'1 - case - assign $21\mask[20:20] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$43 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $22\mask[21:21] 1'1 - case - assign $22\mask[21:21] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$45 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $23\mask[22:22] 1'1 - case - assign $23\mask[22:22] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$47 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $24\mask[23:23] 1'1 - case - assign $24\mask[23:23] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$49 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $25\mask[24:24] 1'1 - case - assign $25\mask[24:24] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$51 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $26\mask[25:25] 1'1 - case - assign $26\mask[25:25] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$53 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $27\mask[26:26] 1'1 - case - assign $27\mask[26:26] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$55 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $28\mask[27:27] 1'1 - case - assign $28\mask[27:27] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$57 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $29\mask[28:28] 1'1 - case - assign $29\mask[28:28] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$59 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $30\mask[29:29] 1'1 - case - assign $30\mask[29:29] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$61 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $31\mask[30:30] 1'1 - case - assign $31\mask[30:30] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$63 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $32\mask[31:31] 1'1 - case - assign $32\mask[31:31] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$65 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $33\mask[32:32] 1'1 - case - assign $33\mask[32:32] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$67 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $34\mask[33:33] 1'1 - case - assign $34\mask[33:33] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$69 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $35\mask[34:34] 1'1 - case - assign $35\mask[34:34] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$71 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $36\mask[35:35] 1'1 - case - assign $36\mask[35:35] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$73 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $37\mask[36:36] 1'1 - case - assign $37\mask[36:36] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$75 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $38\mask[37:37] 1'1 - case - assign $38\mask[37:37] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$77 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $39\mask[38:38] 1'1 - case - assign $39\mask[38:38] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$79 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $40\mask[39:39] 1'1 - case - assign $40\mask[39:39] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$81 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $41\mask[40:40] 1'1 - case - assign $41\mask[40:40] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$83 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $42\mask[41:41] 1'1 - case - assign $42\mask[41:41] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$85 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $43\mask[42:42] 1'1 - case - assign $43\mask[42:42] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$87 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $44\mask[43:43] 1'1 - case - assign $44\mask[43:43] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$89 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $45\mask[44:44] 1'1 - case - assign $45\mask[44:44] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$91 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $46\mask[45:45] 1'1 - case - assign $46\mask[45:45] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$93 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $47\mask[46:46] 1'1 - case - assign $47\mask[46:46] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$95 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $48\mask[47:47] 1'1 - case - assign $48\mask[47:47] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$97 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $49\mask[48:48] 1'1 - case - assign $49\mask[48:48] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$99 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $50\mask[49:49] 1'1 - case - assign $50\mask[49:49] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $51\mask[50:50] 1'1 - case - assign $51\mask[50:50] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$103 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $52\mask[51:51] 1'1 - case - assign $52\mask[51:51] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$105 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $53\mask[52:52] 1'1 - case - assign $53\mask[52:52] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$107 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $54\mask[53:53] 1'1 - case - assign $54\mask[53:53] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$109 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $55\mask[54:54] 1'1 - case - assign $55\mask[54:54] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $56\mask[55:55] 1'1 - case - assign $56\mask[55:55] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$113 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $57\mask[56:56] 1'1 - case - assign $57\mask[56:56] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$115 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $58\mask[57:57] 1'1 - case - assign $58\mask[57:57] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$117 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $59\mask[58:58] 1'1 - case - assign $59\mask[58:58] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$119 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $60\mask[59:59] 1'1 - case - assign $60\mask[59:59] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$121 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $61\mask[60:60] 1'1 - case - assign $61\mask[60:60] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$123 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $62\mask[61:61] 1'1 - case - assign $62\mask[61:61] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$125 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $63\mask[62:62] 1'1 - case - assign $63\mask[62:62] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$127 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $64\mask[63:63] 1'1 - case - assign $64\mask[63:63] 1'0 - end - sync always - update \mask $0\mask[63:0] - end - connect \$9 $gt$issuer_ls180.v:126528$5515_Y - connect \$99 $gt$issuer_ls180.v:126529$5516_Y - connect \$101 $gt$issuer_ls180.v:126530$5517_Y - connect \$103 $gt$issuer_ls180.v:126531$5518_Y - connect \$105 $gt$issuer_ls180.v:126532$5519_Y - connect \$107 $gt$issuer_ls180.v:126533$5520_Y - connect \$109 $gt$issuer_ls180.v:126534$5521_Y - connect \$111 $gt$issuer_ls180.v:126535$5522_Y - connect \$113 $gt$issuer_ls180.v:126536$5523_Y - connect \$115 $gt$issuer_ls180.v:126537$5524_Y - connect \$117 $gt$issuer_ls180.v:126538$5525_Y - connect \$11 $gt$issuer_ls180.v:126539$5526_Y - connect \$119 $gt$issuer_ls180.v:126540$5527_Y - connect \$121 $gt$issuer_ls180.v:126541$5528_Y - connect \$123 $gt$issuer_ls180.v:126542$5529_Y - connect \$125 $gt$issuer_ls180.v:126543$5530_Y - connect \$127 $gt$issuer_ls180.v:126544$5531_Y - connect \$13 $gt$issuer_ls180.v:126545$5532_Y - connect \$15 $gt$issuer_ls180.v:126546$5533_Y - connect \$17 $gt$issuer_ls180.v:126547$5534_Y - connect \$1 $gt$issuer_ls180.v:126548$5535_Y - connect \$19 $gt$issuer_ls180.v:126549$5536_Y - connect \$21 $gt$issuer_ls180.v:126550$5537_Y - connect \$23 $gt$issuer_ls180.v:126551$5538_Y - connect \$25 $gt$issuer_ls180.v:126552$5539_Y - connect \$27 $gt$issuer_ls180.v:126553$5540_Y - connect \$29 $gt$issuer_ls180.v:126554$5541_Y - connect \$31 $gt$issuer_ls180.v:126555$5542_Y - connect \$33 $gt$issuer_ls180.v:126556$5543_Y - connect \$35 $gt$issuer_ls180.v:126557$5544_Y - connect \$37 $gt$issuer_ls180.v:126558$5545_Y - connect \$3 $gt$issuer_ls180.v:126559$5546_Y - connect \$39 $gt$issuer_ls180.v:126560$5547_Y - connect \$41 $gt$issuer_ls180.v:126561$5548_Y - connect \$43 $gt$issuer_ls180.v:126562$5549_Y - connect \$45 $gt$issuer_ls180.v:126563$5550_Y - connect \$47 $gt$issuer_ls180.v:126564$5551_Y - connect \$49 $gt$issuer_ls180.v:126565$5552_Y - connect \$51 $gt$issuer_ls180.v:126566$5553_Y - connect \$53 $gt$issuer_ls180.v:126567$5554_Y - connect \$55 $gt$issuer_ls180.v:126568$5555_Y - connect \$57 $gt$issuer_ls180.v:126569$5556_Y - connect \$5 $gt$issuer_ls180.v:126570$5557_Y - connect \$59 $gt$issuer_ls180.v:126571$5558_Y - connect \$61 $gt$issuer_ls180.v:126572$5559_Y - connect \$63 $gt$issuer_ls180.v:126573$5560_Y - connect \$65 $gt$issuer_ls180.v:126574$5561_Y - connect \$67 $gt$issuer_ls180.v:126575$5562_Y - connect \$69 $gt$issuer_ls180.v:126576$5563_Y - connect \$71 $gt$issuer_ls180.v:126577$5564_Y - connect \$73 $gt$issuer_ls180.v:126578$5565_Y - connect \$75 $gt$issuer_ls180.v:126579$5566_Y - connect \$77 $gt$issuer_ls180.v:126580$5567_Y - connect \$7 $gt$issuer_ls180.v:126581$5568_Y - connect \$79 $gt$issuer_ls180.v:126582$5569_Y - connect \$81 $gt$issuer_ls180.v:126583$5570_Y - connect \$83 $gt$issuer_ls180.v:126584$5571_Y - connect \$85 $gt$issuer_ls180.v:126585$5572_Y - connect \$87 $gt$issuer_ls180.v:126586$5573_Y - connect \$89 $gt$issuer_ls180.v:126587$5574_Y - connect \$91 $gt$issuer_ls180.v:126588$5575_Y - connect \$93 $gt$issuer_ls180.v:126589$5576_Y - connect \$95 $gt$issuer_ls180.v:126590$5577_Y - connect \$97 $gt$issuer_ls180.v:126591$5578_Y -end -attribute \src "issuer_ls180.v:126984.1-127013.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.lenexp" -attribute \generator "nMigen" -module \lenexp - attribute \src "issuer_ls180.v:127008.17-127008.101" - wire width 64 $extend$issuer_ls180.v:127008$5584_Y - attribute \src "issuer_ls180.v:127008.17-127008.101" - wire width 64 $pos$issuer_ls180.v:127008$5585_Y - attribute \src "issuer_ls180.v:127005.17-127005.111" - wire width 20 $sshl$issuer_ls180.v:127005$5581_Y - attribute \src "issuer_ls180.v:127007.17-127007.113" - wire width 32 $sshl$issuer_ls180.v:127007$5583_Y - attribute \src "issuer_ls180.v:127006.17-127006.107" - wire width 21 $sub$issuer_ls180.v:127006$5582_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - wire width 21 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - wire width 20 \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - wire width 21 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - wire width 64 \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - wire width 32 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" - wire width 4 input 1 \addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:148" - wire width 17 \binlen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130" - wire width 4 input 4 \len_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132" - wire width 64 output 2 \lexp_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" - wire width 176 output 3 \rexp_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $extend$issuer_ls180.v:127008$5584 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \$7 - connect \Y $extend$issuer_ls180.v:127008$5584_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $pos$issuer_ls180.v:127008$5585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:127008$5584_Y - connect \Y $pos$issuer_ls180.v:127008$5585_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sshl $sshl$issuer_ls180.v:127005$5581 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 20 - connect \A 5'00001 - connect \B \len_i - connect \Y $sshl$issuer_ls180.v:127005$5581_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $sshl $sshl$issuer_ls180.v:127007$5583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 17 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 32 - connect \A \binlen - connect \B \addr_i - connect \Y $sshl$issuer_ls180.v:127007$5583_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sub $sub$issuer_ls180.v:127006$5582 - parameter \A_SIGNED 0 - parameter \A_WIDTH 20 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 21 - connect \A \$2 - connect \B 1'1 - connect \Y $sub$issuer_ls180.v:127006$5582_Y - end - connect \$2 $sshl$issuer_ls180.v:127005$5581_Y - connect \$4 $sub$issuer_ls180.v:127006$5582_Y - connect \$7 $sshl$issuer_ls180.v:127007$5583_Y - connect \$6 $pos$issuer_ls180.v:127008$5585_Y - connect \$1 \$4 - connect \rexp_o { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21:20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20:19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19:18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18:17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17:16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16:15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15:14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14:13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13:12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12:11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11:10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10:9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9:8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8:7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7:6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6:5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5:4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4:3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3:2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2:1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1:0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } - connect \lexp_o \$6 - connect \binlen \$4 [16:0] -end -attribute \src "issuer_ls180.v:127017.1-127075.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.lod_l" -attribute \generator "nMigen" -module \lod_l - attribute \src "issuer_ls180.v:127018.7-127018.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:127063.3-127071.6" - wire $0\q_int$next[0:0]$5596 - attribute \src "issuer_ls180.v:127061.3-127062.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:127063.3-127071.6" - wire $1\q_int$next[0:0]$5597 - attribute \src "issuer_ls180.v:127040.7-127040.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:127053.17-127053.96" - wire $and$issuer_ls180.v:127053$5586_Y - attribute \src "issuer_ls180.v:127058.17-127058.96" - wire $and$issuer_ls180.v:127058$5591_Y - attribute \src "issuer_ls180.v:127055.18-127055.93" - wire $not$issuer_ls180.v:127055$5588_Y - attribute \src "issuer_ls180.v:127057.17-127057.92" - wire $not$issuer_ls180.v:127057$5590_Y - attribute \src "issuer_ls180.v:127060.17-127060.92" - wire $not$issuer_ls180.v:127060$5593_Y - attribute \src "issuer_ls180.v:127054.18-127054.98" - wire $or$issuer_ls180.v:127054$5587_Y - attribute \src "issuer_ls180.v:127056.18-127056.99" - wire $or$issuer_ls180.v:127056$5589_Y - attribute \src "issuer_ls180.v:127059.17-127059.97" - wire $or$issuer_ls180.v:127059$5592_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:127018.7-127018.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \q_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire output 4 \qn_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:127053$5586 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:127053$5586_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:127058$5591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:127058$5591_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:127055$5588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_lod - connect \Y $not$issuer_ls180.v:127055$5588_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:127057$5590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_lod - connect \Y $not$issuer_ls180.v:127057$5590_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:127060$5593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_lod - connect \Y $not$issuer_ls180.v:127060$5593_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:127054$5587 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_lod - connect \Y $or$issuer_ls180.v:127054$5587_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:127056$5589 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_lod - connect \B \q_int - connect \Y $or$issuer_ls180.v:127056$5589_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:127059$5592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_lod - connect \Y $or$issuer_ls180.v:127059$5592_Y - end - attribute \src "issuer_ls180.v:127018.7-127018.20" - process $proc$issuer_ls180.v:127018$5598 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:127040.7-127040.19" - process $proc$issuer_ls180.v:127040$5599 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:127061.3-127062.27" - process $proc$issuer_ls180.v:127061$5594 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:127063.3-127071.6" - process $proc$issuer_ls180.v:127063$5595 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$5596 $1\q_int$next[0:0]$5597 - attribute \src "issuer_ls180.v:127064.5-127064.29" - switch \initial - attribute \src "issuer_ls180.v:127064.9-127064.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$5597 1'0 - case - assign $1\q_int$next[0:0]$5597 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$5596 - end - connect \$9 $and$issuer_ls180.v:127053$5586_Y - connect \$11 $or$issuer_ls180.v:127054$5587_Y - connect \$13 $not$issuer_ls180.v:127055$5588_Y - connect \$15 $or$issuer_ls180.v:127056$5589_Y - connect \$1 $not$issuer_ls180.v:127057$5590_Y - connect \$3 $and$issuer_ls180.v:127058$5591_Y - connect \$5 $or$issuer_ls180.v:127059$5592_Y - connect \$7 $not$issuer_ls180.v:127060$5593_Y - connect \qlq_lod \$15 - connect \qn_lod \$13 - connect \q_lod \$11 -end -attribute \src "issuer_ls180.v:127079.1-128193.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0" -attribute \generator "nMigen" -module \logical0 - attribute \src "issuer_ls180.v:127818.3-127819.24" - wire $0\all_rd_dly[0:0] - attribute \src "issuer_ls180.v:127816.3-127817.44" - wire $0\alu_done_dly[0:0] - attribute \src "issuer_ls180.v:128123.3-128131.6" - wire $0\alu_l_r_alu$next[0:0]$5800 - attribute \src "issuer_ls180.v:127740.3-127741.39" - wire $0\alu_l_r_alu[0:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$5729 - attribute \src "issuer_ls180.v:127790.3-127791.83" - wire width 4 $0\alu_logical0_logical_op__data_len[3:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire width 12 $0\alu_logical0_logical_op__fn_unit$next[11:0]$5730 - attribute \src "issuer_ls180.v:127760.3-127761.81" - wire width 12 $0\alu_logical0_logical_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$5731 - attribute \src "issuer_ls180.v:127762.3-127763.95" - wire width 64 $0\alu_logical0_logical_op__imm_data__data[63:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$5732 - attribute \src "issuer_ls180.v:127764.3-127765.91" - wire $0\alu_logical0_logical_op__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$5733 - attribute \src "issuer_ls180.v:127778.3-127779.89" - wire width 2 $0\alu_logical0_logical_op__input_carry[1:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$5734 - attribute \src "issuer_ls180.v:127792.3-127793.75" - wire width 32 $0\alu_logical0_logical_op__insn[31:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$5735 - attribute \src "issuer_ls180.v:127758.3-127759.85" - wire width 7 $0\alu_logical0_logical_op__insn_type[6:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire $0\alu_logical0_logical_op__invert_in$next[0:0]$5736 - attribute \src "issuer_ls180.v:127774.3-127775.85" - wire $0\alu_logical0_logical_op__invert_in[0:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire $0\alu_logical0_logical_op__invert_out$next[0:0]$5737 - attribute \src "issuer_ls180.v:127780.3-127781.87" - wire $0\alu_logical0_logical_op__invert_out[0:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$5738 - attribute \src "issuer_ls180.v:127786.3-127787.83" - wire $0\alu_logical0_logical_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire $0\alu_logical0_logical_op__is_signed$next[0:0]$5739 - attribute \src "issuer_ls180.v:127788.3-127789.85" - wire $0\alu_logical0_logical_op__is_signed[0:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$5740 - attribute \src "issuer_ls180.v:127770.3-127771.79" - wire $0\alu_logical0_logical_op__oe__oe[0:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$5741 - attribute \src "issuer_ls180.v:127772.3-127773.79" - wire $0\alu_logical0_logical_op__oe__ok[0:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire $0\alu_logical0_logical_op__output_carry$next[0:0]$5742 - attribute \src "issuer_ls180.v:127784.3-127785.91" - wire $0\alu_logical0_logical_op__output_carry[0:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$5743 - attribute \src "issuer_ls180.v:127768.3-127769.79" - wire $0\alu_logical0_logical_op__rc__ok[0:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$5744 - attribute \src "issuer_ls180.v:127766.3-127767.79" - wire $0\alu_logical0_logical_op__rc__rc[0:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$5745 - attribute \src "issuer_ls180.v:127782.3-127783.85" - wire $0\alu_logical0_logical_op__write_cr0[0:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire $0\alu_logical0_logical_op__zero_a$next[0:0]$5746 - attribute \src "issuer_ls180.v:127776.3-127777.79" - wire $0\alu_logical0_logical_op__zero_a[0:0] - attribute \src "issuer_ls180.v:128114.3-128122.6" - wire $0\alui_l_r_alui$next[0:0]$5797 - attribute \src "issuer_ls180.v:127742.3-127743.43" - wire $0\alui_l_r_alui[0:0] - attribute \src "issuer_ls180.v:128040.3-128061.6" - wire width 64 $0\data_r0__o$next[63:0]$5772 - attribute \src "issuer_ls180.v:127754.3-127755.37" - wire width 64 $0\data_r0__o[63:0] - attribute \src "issuer_ls180.v:128040.3-128061.6" - wire $0\data_r0__o_ok$next[0:0]$5773 - attribute \src "issuer_ls180.v:127756.3-127757.43" - wire $0\data_r0__o_ok[0:0] - attribute \src "issuer_ls180.v:128062.3-128083.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$5780 - attribute \src "issuer_ls180.v:127750.3-127751.43" - wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "issuer_ls180.v:128062.3-128083.6" - wire $0\data_r1__cr_a_ok$next[0:0]$5781 - attribute \src "issuer_ls180.v:127752.3-127753.49" - wire $0\data_r1__cr_a_ok[0:0] - attribute \src "issuer_ls180.v:128132.3-128141.6" - wire width 64 $0\dest1_o[63:0] - attribute \src "issuer_ls180.v:128142.3-128151.6" - wire width 4 $0\dest2_o[3:0] - attribute \src "issuer_ls180.v:127080.7-127080.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:127956.3-127964.6" - wire $0\opc_l_r_opc$next[0:0]$5714 - attribute \src "issuer_ls180.v:127802.3-127803.39" - wire $0\opc_l_r_opc[0:0] - attribute \src "issuer_ls180.v:127947.3-127955.6" - wire $0\opc_l_s_opc$next[0:0]$5711 - attribute \src "issuer_ls180.v:127804.3-127805.39" - wire $0\opc_l_s_opc[0:0] - attribute \src "issuer_ls180.v:128152.3-128160.6" - wire width 2 $0\prev_wr_go$next[1:0]$5805 - attribute \src "issuer_ls180.v:127814.3-127815.37" - wire width 2 $0\prev_wr_go[1:0] - attribute \src "issuer_ls180.v:127901.3-127910.6" - wire $0\req_done[0:0] - attribute \src "issuer_ls180.v:127992.3-128000.6" - wire width 2 $0\req_l_r_req$next[1:0]$5726 - attribute \src "issuer_ls180.v:127794.3-127795.39" - wire width 2 $0\req_l_r_req[1:0] - attribute \src "issuer_ls180.v:127983.3-127991.6" - wire width 2 $0\req_l_s_req$next[1:0]$5723 - attribute \src "issuer_ls180.v:127796.3-127797.39" - wire width 2 $0\req_l_s_req[1:0] - attribute \src "issuer_ls180.v:127920.3-127928.6" - wire $0\rok_l_r_rdok$next[0:0]$5702 - attribute \src "issuer_ls180.v:127810.3-127811.41" - wire $0\rok_l_r_rdok[0:0] - attribute \src "issuer_ls180.v:127911.3-127919.6" - wire $0\rok_l_s_rdok$next[0:0]$5699 - attribute \src "issuer_ls180.v:127812.3-127813.41" - wire $0\rok_l_s_rdok[0:0] - attribute \src "issuer_ls180.v:127938.3-127946.6" - wire $0\rst_l_r_rst$next[0:0]$5708 - attribute \src "issuer_ls180.v:127806.3-127807.39" - wire $0\rst_l_r_rst[0:0] - attribute \src "issuer_ls180.v:127929.3-127937.6" - wire $0\rst_l_s_rst$next[0:0]$5705 - attribute \src "issuer_ls180.v:127808.3-127809.39" - wire $0\rst_l_s_rst[0:0] - attribute \src "issuer_ls180.v:127974.3-127982.6" - wire width 3 $0\src_l_r_src$next[2:0]$5720 - attribute \src "issuer_ls180.v:127798.3-127799.39" - wire width 3 $0\src_l_r_src[2:0] - attribute \src "issuer_ls180.v:127965.3-127973.6" - wire width 3 $0\src_l_s_src$next[2:0]$5717 - attribute \src "issuer_ls180.v:127800.3-127801.39" - wire width 3 $0\src_l_s_src[2:0] - attribute \src "issuer_ls180.v:128084.3-128093.6" - wire width 64 $0\src_r0$next[63:0]$5788 - attribute \src "issuer_ls180.v:127748.3-127749.29" - wire width 64 $0\src_r0[63:0] - attribute \src "issuer_ls180.v:128094.3-128103.6" - wire width 64 $0\src_r1$next[63:0]$5791 - attribute \src "issuer_ls180.v:127746.3-127747.29" - wire width 64 $0\src_r1[63:0] - attribute \src "issuer_ls180.v:128104.3-128113.6" - wire $0\src_r2$next[0:0]$5794 - attribute \src "issuer_ls180.v:127744.3-127745.29" - wire $0\src_r2[0:0] - attribute \src "issuer_ls180.v:127198.7-127198.24" - wire $1\all_rd_dly[0:0] - attribute \src "issuer_ls180.v:127208.7-127208.26" - wire $1\alu_done_dly[0:0] - attribute \src "issuer_ls180.v:128123.3-128131.6" - wire $1\alu_l_r_alu$next[0:0]$5801 - attribute \src "issuer_ls180.v:127216.7-127216.25" - wire $1\alu_l_r_alu[0:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$5747 - attribute \src "issuer_ls180.v:127224.13-127224.53" - wire width 4 $1\alu_logical0_logical_op__data_len[3:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire width 12 $1\alu_logical0_logical_op__fn_unit$next[11:0]$5748 - attribute \src "issuer_ls180.v:127241.14-127241.56" - wire width 12 $1\alu_logical0_logical_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$5749 - attribute \src "issuer_ls180.v:127245.14-127245.76" - wire width 64 $1\alu_logical0_logical_op__imm_data__data[63:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$5750 - attribute \src "issuer_ls180.v:127249.7-127249.51" - wire $1\alu_logical0_logical_op__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$5751 - attribute \src "issuer_ls180.v:127257.13-127257.56" - wire width 2 $1\alu_logical0_logical_op__input_carry[1:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$5752 - attribute \src "issuer_ls180.v:127261.14-127261.51" - wire width 32 $1\alu_logical0_logical_op__insn[31:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$5753 - attribute \src "issuer_ls180.v:127339.13-127339.55" - wire width 7 $1\alu_logical0_logical_op__insn_type[6:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire $1\alu_logical0_logical_op__invert_in$next[0:0]$5754 - attribute \src "issuer_ls180.v:127343.7-127343.48" - wire $1\alu_logical0_logical_op__invert_in[0:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire $1\alu_logical0_logical_op__invert_out$next[0:0]$5755 - attribute \src "issuer_ls180.v:127347.7-127347.49" - wire $1\alu_logical0_logical_op__invert_out[0:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$5756 - attribute \src "issuer_ls180.v:127351.7-127351.47" - wire $1\alu_logical0_logical_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire $1\alu_logical0_logical_op__is_signed$next[0:0]$5757 - attribute \src "issuer_ls180.v:127355.7-127355.48" - wire $1\alu_logical0_logical_op__is_signed[0:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$5758 - attribute \src "issuer_ls180.v:127359.7-127359.45" - wire $1\alu_logical0_logical_op__oe__oe[0:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$5759 - attribute \src "issuer_ls180.v:127363.7-127363.45" - wire $1\alu_logical0_logical_op__oe__ok[0:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire $1\alu_logical0_logical_op__output_carry$next[0:0]$5760 - attribute \src "issuer_ls180.v:127367.7-127367.51" - wire $1\alu_logical0_logical_op__output_carry[0:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$5761 - attribute \src "issuer_ls180.v:127371.7-127371.45" - wire $1\alu_logical0_logical_op__rc__ok[0:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$5762 - attribute \src "issuer_ls180.v:127375.7-127375.45" - wire $1\alu_logical0_logical_op__rc__rc[0:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$5763 - attribute \src "issuer_ls180.v:127379.7-127379.48" - wire $1\alu_logical0_logical_op__write_cr0[0:0] - attribute \src "issuer_ls180.v:128001.3-128039.6" - wire $1\alu_logical0_logical_op__zero_a$next[0:0]$5764 - attribute \src "issuer_ls180.v:127383.7-127383.45" - wire $1\alu_logical0_logical_op__zero_a[0:0] - attribute \src "issuer_ls180.v:128114.3-128122.6" - wire $1\alui_l_r_alui$next[0:0]$5798 - attribute \src "issuer_ls180.v:127409.7-127409.27" - wire $1\alui_l_r_alui[0:0] - attribute \src "issuer_ls180.v:128040.3-128061.6" - wire width 64 $1\data_r0__o$next[63:0]$5774 - attribute \src "issuer_ls180.v:127443.14-127443.47" - wire width 64 $1\data_r0__o[63:0] - attribute \src "issuer_ls180.v:128040.3-128061.6" - wire $1\data_r0__o_ok$next[0:0]$5775 - attribute \src "issuer_ls180.v:127447.7-127447.27" - wire $1\data_r0__o_ok[0:0] - attribute \src "issuer_ls180.v:128062.3-128083.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$5782 - attribute \src "issuer_ls180.v:127451.13-127451.33" - wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "issuer_ls180.v:128062.3-128083.6" - wire $1\data_r1__cr_a_ok$next[0:0]$5783 - attribute \src "issuer_ls180.v:127455.7-127455.30" - wire $1\data_r1__cr_a_ok[0:0] - attribute \src "issuer_ls180.v:128132.3-128141.6" - wire width 64 $1\dest1_o[63:0] - attribute \src "issuer_ls180.v:128142.3-128151.6" - wire width 4 $1\dest2_o[3:0] - attribute \src "issuer_ls180.v:127956.3-127964.6" - wire $1\opc_l_r_opc$next[0:0]$5715 - attribute \src "issuer_ls180.v:127469.7-127469.25" - wire $1\opc_l_r_opc[0:0] - attribute \src "issuer_ls180.v:127947.3-127955.6" - wire $1\opc_l_s_opc$next[0:0]$5712 - attribute \src "issuer_ls180.v:127473.7-127473.25" - wire $1\opc_l_s_opc[0:0] - attribute \src "issuer_ls180.v:128152.3-128160.6" - wire width 2 $1\prev_wr_go$next[1:0]$5806 - attribute \src "issuer_ls180.v:127604.13-127604.30" - wire width 2 $1\prev_wr_go[1:0] - attribute \src "issuer_ls180.v:127901.3-127910.6" - wire $1\req_done[0:0] - attribute \src "issuer_ls180.v:127992.3-128000.6" - wire width 2 $1\req_l_r_req$next[1:0]$5727 - attribute \src "issuer_ls180.v:127612.13-127612.31" - wire width 2 $1\req_l_r_req[1:0] - attribute \src "issuer_ls180.v:127983.3-127991.6" - wire width 2 $1\req_l_s_req$next[1:0]$5724 - attribute \src "issuer_ls180.v:127616.13-127616.31" - wire width 2 $1\req_l_s_req[1:0] - attribute \src "issuer_ls180.v:127920.3-127928.6" - wire $1\rok_l_r_rdok$next[0:0]$5703 - attribute \src "issuer_ls180.v:127628.7-127628.26" - wire $1\rok_l_r_rdok[0:0] - attribute \src "issuer_ls180.v:127911.3-127919.6" - wire $1\rok_l_s_rdok$next[0:0]$5700 - attribute \src "issuer_ls180.v:127632.7-127632.26" - wire $1\rok_l_s_rdok[0:0] - attribute \src "issuer_ls180.v:127938.3-127946.6" - wire $1\rst_l_r_rst$next[0:0]$5709 - attribute \src "issuer_ls180.v:127636.7-127636.25" - wire $1\rst_l_r_rst[0:0] - attribute \src "issuer_ls180.v:127929.3-127937.6" - wire $1\rst_l_s_rst$next[0:0]$5706 - attribute \src "issuer_ls180.v:127640.7-127640.25" - wire $1\rst_l_s_rst[0:0] - attribute \src "issuer_ls180.v:127974.3-127982.6" - wire width 3 $1\src_l_r_src$next[2:0]$5721 - attribute \src "issuer_ls180.v:127654.13-127654.31" - wire width 3 $1\src_l_r_src[2:0] - attribute \src "issuer_ls180.v:127965.3-127973.6" - wire width 3 $1\src_l_s_src$next[2:0]$5718 - attribute \src "issuer_ls180.v:127658.13-127658.31" - wire width 3 $1\src_l_s_src[2:0] - attribute \src "issuer_ls180.v:128084.3-128093.6" - wire width 64 $1\src_r0$next[63:0]$5789 - attribute \src "issuer_ls180.v:127666.14-127666.43" - wire width 64 $1\src_r0[63:0] - attribute \src "issuer_ls180.v:128094.3-128103.6" - wire width 64 $1\src_r1$next[63:0]$5792 - attribute \src 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\alu_logical0_logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__imm_data__ok$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_logical0_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_logical0_logical_op__input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_logical0_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_logical0_logical_op__insn$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute 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\enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_logical0_logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_logical0_logical_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__invert_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__invert_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \alu_logical0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \alu_logical0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_logical0_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \alu_logical0_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \alu_logical0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_logical0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_logical0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \alu_logical0_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 2 \alu_pulsem - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 33 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 31 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 20 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 19 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 23 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 22 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 21 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" - wire \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 input 29 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 output 28 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 2 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r0__o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r1__cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 30 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 32 \dest2_o - attribute \src "issuer_ls180.v:127080.7-127080.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 27 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \oper_i_alu_logical0__data_len - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \oper_i_alu_logical0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \oper_i_alu_logical0__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \oper_i_alu_logical0__imm_data__ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \oper_i_alu_logical0__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \oper_i_alu_logical0__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute 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\enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \oper_i_alu_logical0__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \oper_i_alu_logical0__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \oper_i_alu_logical0__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \oper_i_alu_logical0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \oper_i_alu_logical0__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \oper_i_alu_logical0__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \oper_i_alu_logical0__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \oper_i_alu_logical0__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \oper_i_alu_logical0__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \oper_i_alu_logical0__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \oper_i_alu_logical0__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \oper_i_alu_logical0__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 2 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 2 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" - wire \req_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 2 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 2 \req_l_r_req - attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 \src_l_q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 64 \src_or_imm$80 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0$next - attribute \src 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$and$issuer_ls180.v:127683$5600_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$issuer_ls180.v:127684$5601 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$93 - connect \B { 1'1 \$97 \$95 } - connect \Y $and$issuer_ls180.v:127684$5601_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$issuer_ls180.v:127686$5603 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$99 - connect \B \$101 - connect \Y $and$issuer_ls180.v:127686$5603_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$issuer_ls180.v:127687$5604 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o 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parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \$109 - connect \B \cu_wrmask_o - connect \Y $and$issuer_ls180.v:127690$5607_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$issuer_ls180.v:127691$5608 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:127691$5608_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$issuer_ls180.v:127692$5609 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:127692$5609_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:127694$5611 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd - connect \B \$11 - connect \Y $and$issuer_ls180.v:127694$5611_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:127696$5613 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done - connect \B \$15 - connect \Y $and$issuer_ls180.v:127696$5613_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$issuer_ls180.v:127697$5614 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \rok_l_q_rdok - connect \Y $and$issuer_ls180.v:127697$5614_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$issuer_ls180.v:127698$5615 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o } - connect \Y $and$issuer_ls180.v:127698$5615_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$issuer_ls180.v:127700$5617 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \cu_wr__rel_o - connect \B \$23 - connect \Y $and$issuer_ls180.v:127700$5617_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$issuer_ls180.v:127703$5620 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \$21 - connect \Y $and$issuer_ls180.v:127703$5620_Y - end - attribute \src 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$and$issuer_ls180.v:127711$5628_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$issuer_ls180.v:127714$5631 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$47 - connect \B \alu_logical0_n_ready_i - connect \Y $and$issuer_ls180.v:127714$5631_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$issuer_ls180.v:127715$5632 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$49 - connect \B \alu_logical0_n_valid_o - connect \Y $and$issuer_ls180.v:127715$5632_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$issuer_ls180.v:127716$5633 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 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\B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o_ok - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:127725$5642_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$issuer_ls180.v:127726$5643 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cr_a_ok - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:127726$5643_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$issuer_ls180.v:127735$5652 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_logical0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $and$issuer_ls180.v:127735$5652_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$issuer_ls180.v:127736$5653 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_logical0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $and$issuer_ls180.v:127736$5653_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$issuer_ls180.v:127737$5654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$issuer_ls180.v:127737$5654_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$issuer_ls180.v:127710$5627 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$41 - connect \B 1'0 - connect \Y $eq$issuer_ls180.v:127710$5627_Y - end - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$issuer_ls180.v:127713$5630 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__rel_o - connect \Y $not$issuer_ls180.v:127713$5630_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$issuer_ls180.v:127738$5655 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_logical0_logical_op__zero_a - connect \Y $not$issuer_ls180.v:127738$5655_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$issuer_ls180.v:127739$5656 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_logical0_logical_op__imm_data__ok - connect \Y $not$issuer_ls180.v:127739$5656_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$issuer_ls180.v:127706$5623 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$31 - connect \B \$33 - connect \Y $or$issuer_ls180.v:127706$5623_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$issuer_ls180.v:127717$5634 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $or$issuer_ls180.v:127717$5634_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$issuer_ls180.v:127718$5635 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $or$issuer_ls180.v:127718$5635_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$issuer_ls180.v:127719$5636 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i } - connect \Y $or$issuer_ls180.v:127719$5636_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$issuer_ls180.v:127720$5637 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$issuer_ls180.v:127720$5637_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$issuer_ls180.v:127723$5640 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $or$issuer_ls180.v:127723$5640_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$issuer_ls180.v:127724$5641 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$4 - connect \B \cu_rd__go_i - connect \Y $or$issuer_ls180.v:127724$5641_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$issuer_ls180.v:127730$5647 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \$6 - connect \Y $reduce_and$issuer_ls180.v:127730$5647_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$issuer_ls180.v:127701$5618 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \$25 - connect \Y $reduce_or$issuer_ls180.v:127701$5618_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$issuer_ls180.v:127704$5621 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $reduce_or$issuer_ls180.v:127704$5621_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$issuer_ls180.v:127705$5622 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $reduce_or$issuer_ls180.v:127705$5622_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$issuer_ls180.v:127727$5644 - parameter \WIDTH 1 - connect \A \src_l_q_src [0] - connect \B \opc_l_q_opc - connect \S \alu_logical0_logical_op__zero_a - connect \Y $ternary$issuer_ls180.v:127727$5644_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$issuer_ls180.v:127728$5645 - parameter \WIDTH 64 - connect \A \src1_i - connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \S \alu_logical0_logical_op__zero_a - connect \Y $ternary$issuer_ls180.v:127728$5645_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$issuer_ls180.v:127729$5646 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $ternary$issuer_ls180.v:127729$5646_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$issuer_ls180.v:127731$5648 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \alu_logical0_logical_op__imm_data__data - connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $ternary$issuer_ls180.v:127731$5648_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:127732$5649 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $ternary$issuer_ls180.v:127732$5649_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:127733$5650 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm$80 - connect \S \src_sel$77 - connect \Y $ternary$issuer_ls180.v:127733$5650_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:127734$5651 - parameter \WIDTH 1 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $ternary$issuer_ls180.v:127734$5651_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:127820.14-127826.4" - cell \alu_l$58 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:127827.16-127859.4" - cell \alu_logical0 \alu_logical0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \alu_logical0_cr_a - connect \cr_a_ok \cr_a_ok - connect \logical_op__data_len \alu_logical0_logical_op__data_len - connect \logical_op__fn_unit \alu_logical0_logical_op__fn_unit - connect \logical_op__imm_data__data \alu_logical0_logical_op__imm_data__data - connect \logical_op__imm_data__ok \alu_logical0_logical_op__imm_data__ok - connect \logical_op__input_carry \alu_logical0_logical_op__input_carry - connect \logical_op__insn \alu_logical0_logical_op__insn - connect \logical_op__insn_type \alu_logical0_logical_op__insn_type - connect \logical_op__invert_in \alu_logical0_logical_op__invert_in - connect \logical_op__invert_out \alu_logical0_logical_op__invert_out - connect \logical_op__is_32bit \alu_logical0_logical_op__is_32bit - connect \logical_op__is_signed \alu_logical0_logical_op__is_signed - connect \logical_op__oe__oe \alu_logical0_logical_op__oe__oe - connect \logical_op__oe__ok \alu_logical0_logical_op__oe__ok - connect \logical_op__output_carry \alu_logical0_logical_op__output_carry - connect \logical_op__rc__ok \alu_logical0_logical_op__rc__ok - connect \logical_op__rc__rc \alu_logical0_logical_op__rc__rc - connect \logical_op__write_cr0 \alu_logical0_logical_op__write_cr0 - connect \logical_op__zero_a \alu_logical0_logical_op__zero_a - connect \n_ready_i \alu_logical0_n_ready_i - connect \n_valid_o \alu_logical0_n_valid_o - connect \o \alu_logical0_o - connect \o_ok \o_ok - connect \p_ready_o \alu_logical0_p_ready_o - connect \p_valid_i \alu_logical0_p_valid_i - connect \ra \alu_logical0_ra - connect \rb \alu_logical0_rb - connect \xer_so \alu_logical0_xer_so - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:127860.15-127866.4" - cell \alui_l$57 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:127867.14-127873.4" - cell \opc_l$53 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_opc \opc_l_q_opc - connect \r_opc \opc_l_r_opc - connect \s_opc \opc_l_s_opc - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:127874.14-127880.4" - cell \req_l$54 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \r_req \req_l_r_req - connect \s_req \req_l_s_req - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:127881.14-127887.4" - cell \rok_l$56 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \r_rdok \rok_l_r_rdok - connect \s_rdok \rok_l_s_rdok - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:127888.14-127893.4" - cell \rst_l$55 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_rst \rst_l_r_rst - connect \s_rst \rst_l_s_rst - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:127894.14-127900.4" - cell \src_l$52 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_src \src_l_q_src - connect \r_src \src_l_r_src - connect \s_src \src_l_s_src - end - attribute \src "issuer_ls180.v:127080.7-127080.20" - process $proc$issuer_ls180.v:127080$5807 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:127198.7-127198.24" - process $proc$issuer_ls180.v:127198$5808 - assign { } { } - assign $1\all_rd_dly[0:0] 1'0 - sync always - sync init - update \all_rd_dly $1\all_rd_dly[0:0] - end - attribute \src "issuer_ls180.v:127208.7-127208.26" - process $proc$issuer_ls180.v:127208$5809 - assign { } { } - assign $1\alu_done_dly[0:0] 1'0 - sync always - sync init - update \alu_done_dly $1\alu_done_dly[0:0] - end - attribute \src "issuer_ls180.v:127216.7-127216.25" - process $proc$issuer_ls180.v:127216$5810 - assign { } { } - assign $1\alu_l_r_alu[0:0] 1'1 - sync always - sync init - update \alu_l_r_alu $1\alu_l_r_alu[0:0] - end - attribute \src "issuer_ls180.v:127224.13-127224.53" - process $proc$issuer_ls180.v:127224$5811 - assign { } { } - assign $1\alu_logical0_logical_op__data_len[3:0] 4'0000 - sync always - sync init - update \alu_logical0_logical_op__data_len $1\alu_logical0_logical_op__data_len[3:0] - end - attribute \src "issuer_ls180.v:127241.14-127241.56" - process $proc$issuer_ls180.v:127241$5812 - assign { } { } - assign $1\alu_logical0_logical_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \alu_logical0_logical_op__fn_unit $1\alu_logical0_logical_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:127245.14-127245.76" - process $proc$issuer_ls180.v:127245$5813 - assign { } { } - assign $1\alu_logical0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_logical0_logical_op__imm_data__data $1\alu_logical0_logical_op__imm_data__data[63:0] - end - attribute \src "issuer_ls180.v:127249.7-127249.51" - process $proc$issuer_ls180.v:127249$5814 - assign { } { } - assign $1\alu_logical0_logical_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__imm_data__ok $1\alu_logical0_logical_op__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:127257.13-127257.56" - process $proc$issuer_ls180.v:127257$5815 - assign { } { } - assign $1\alu_logical0_logical_op__input_carry[1:0] 2'00 - sync always - sync init - update \alu_logical0_logical_op__input_carry $1\alu_logical0_logical_op__input_carry[1:0] - end - attribute \src "issuer_ls180.v:127261.14-127261.51" - process $proc$issuer_ls180.v:127261$5816 - assign { } { } - assign $1\alu_logical0_logical_op__insn[31:0] 0 - sync always - sync init - update \alu_logical0_logical_op__insn $1\alu_logical0_logical_op__insn[31:0] - end - attribute \src "issuer_ls180.v:127339.13-127339.55" - process $proc$issuer_ls180.v:127339$5817 - assign { } { } - assign $1\alu_logical0_logical_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \alu_logical0_logical_op__insn_type $1\alu_logical0_logical_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:127343.7-127343.48" - process $proc$issuer_ls180.v:127343$5818 - assign { } { } - assign $1\alu_logical0_logical_op__invert_in[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__invert_in $1\alu_logical0_logical_op__invert_in[0:0] - end - attribute \src "issuer_ls180.v:127347.7-127347.49" - process $proc$issuer_ls180.v:127347$5819 - assign { } { } - assign $1\alu_logical0_logical_op__invert_out[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__invert_out $1\alu_logical0_logical_op__invert_out[0:0] - end - attribute \src "issuer_ls180.v:127351.7-127351.47" - process $proc$issuer_ls180.v:127351$5820 - assign { } { } - assign $1\alu_logical0_logical_op__is_32bit[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__is_32bit $1\alu_logical0_logical_op__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:127355.7-127355.48" - process $proc$issuer_ls180.v:127355$5821 - assign { } { } - assign $1\alu_logical0_logical_op__is_signed[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__is_signed $1\alu_logical0_logical_op__is_signed[0:0] - end - attribute \src "issuer_ls180.v:127359.7-127359.45" - process $proc$issuer_ls180.v:127359$5822 - assign { } { } - assign $1\alu_logical0_logical_op__oe__oe[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__oe__oe $1\alu_logical0_logical_op__oe__oe[0:0] - end - attribute \src "issuer_ls180.v:127363.7-127363.45" - process $proc$issuer_ls180.v:127363$5823 - assign { } { } - assign $1\alu_logical0_logical_op__oe__ok[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__oe__ok $1\alu_logical0_logical_op__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:127367.7-127367.51" - process $proc$issuer_ls180.v:127367$5824 - assign { } { } - assign $1\alu_logical0_logical_op__output_carry[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__output_carry $1\alu_logical0_logical_op__output_carry[0:0] - end - attribute \src "issuer_ls180.v:127371.7-127371.45" - process $proc$issuer_ls180.v:127371$5825 - assign { } { } - assign $1\alu_logical0_logical_op__rc__ok[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__rc__ok $1\alu_logical0_logical_op__rc__ok[0:0] - end - attribute \src "issuer_ls180.v:127375.7-127375.45" - process $proc$issuer_ls180.v:127375$5826 - assign { } { } - assign $1\alu_logical0_logical_op__rc__rc[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__rc__rc $1\alu_logical0_logical_op__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:127379.7-127379.48" - process $proc$issuer_ls180.v:127379$5827 - assign { } { } - assign $1\alu_logical0_logical_op__write_cr0[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__write_cr0 $1\alu_logical0_logical_op__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:127383.7-127383.45" - process $proc$issuer_ls180.v:127383$5828 - assign { } { } - assign $1\alu_logical0_logical_op__zero_a[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__zero_a $1\alu_logical0_logical_op__zero_a[0:0] - end - attribute \src "issuer_ls180.v:127409.7-127409.27" - process $proc$issuer_ls180.v:127409$5829 - assign { } { } - assign $1\alui_l_r_alui[0:0] 1'1 - sync always - sync init - update \alui_l_r_alui $1\alui_l_r_alui[0:0] - end - attribute \src "issuer_ls180.v:127443.14-127443.47" - process $proc$issuer_ls180.v:127443$5830 - assign { } { } - assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r0__o $1\data_r0__o[63:0] - end - attribute \src "issuer_ls180.v:127447.7-127447.27" - process $proc$issuer_ls180.v:127447$5831 - assign { } { } - assign $1\data_r0__o_ok[0:0] 1'0 - sync always - sync init - update \data_r0__o_ok $1\data_r0__o_ok[0:0] - end - attribute \src "issuer_ls180.v:127451.13-127451.33" - process $proc$issuer_ls180.v:127451$5832 - assign { } { } - assign $1\data_r1__cr_a[3:0] 4'0000 - sync always - sync init - update \data_r1__cr_a $1\data_r1__cr_a[3:0] - end - attribute \src "issuer_ls180.v:127455.7-127455.30" - process $proc$issuer_ls180.v:127455$5833 - assign { } { } - assign $1\data_r1__cr_a_ok[0:0] 1'0 - sync always - sync init - update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:127469.7-127469.25" - process $proc$issuer_ls180.v:127469$5834 - assign { } { } - assign $1\opc_l_r_opc[0:0] 1'1 - sync always - sync init - update \opc_l_r_opc $1\opc_l_r_opc[0:0] - end - attribute \src "issuer_ls180.v:127473.7-127473.25" - process $proc$issuer_ls180.v:127473$5835 - assign { } { } - assign $1\opc_l_s_opc[0:0] 1'0 - sync always - sync init - update \opc_l_s_opc $1\opc_l_s_opc[0:0] - end - attribute \src "issuer_ls180.v:127604.13-127604.30" - process $proc$issuer_ls180.v:127604$5836 - assign { } { } - assign $1\prev_wr_go[1:0] 2'00 - sync always - sync init - update \prev_wr_go $1\prev_wr_go[1:0] - end - attribute \src "issuer_ls180.v:127612.13-127612.31" - process $proc$issuer_ls180.v:127612$5837 - assign { } { } - assign $1\req_l_r_req[1:0] 2'11 - sync always - sync init - update \req_l_r_req $1\req_l_r_req[1:0] - end - attribute \src "issuer_ls180.v:127616.13-127616.31" - process $proc$issuer_ls180.v:127616$5838 - assign { } { } - assign $1\req_l_s_req[1:0] 2'00 - sync always - sync init - update \req_l_s_req $1\req_l_s_req[1:0] - end - attribute \src "issuer_ls180.v:127628.7-127628.26" - process $proc$issuer_ls180.v:127628$5839 - assign { } { } - assign $1\rok_l_r_rdok[0:0] 1'1 - sync always - sync init - update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] - end - attribute \src "issuer_ls180.v:127632.7-127632.26" - process $proc$issuer_ls180.v:127632$5840 - assign { } { } - assign $1\rok_l_s_rdok[0:0] 1'0 - sync always - sync init - update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] - end - attribute \src "issuer_ls180.v:127636.7-127636.25" - process $proc$issuer_ls180.v:127636$5841 - assign { } { } - assign $1\rst_l_r_rst[0:0] 1'1 - sync always - sync init - update \rst_l_r_rst $1\rst_l_r_rst[0:0] - end - attribute \src "issuer_ls180.v:127640.7-127640.25" - process $proc$issuer_ls180.v:127640$5842 - assign { } { } - assign $1\rst_l_s_rst[0:0] 1'0 - sync always - sync init - update \rst_l_s_rst $1\rst_l_s_rst[0:0] - end - attribute \src "issuer_ls180.v:127654.13-127654.31" - process $proc$issuer_ls180.v:127654$5843 - assign { } { } - assign $1\src_l_r_src[2:0] 3'111 - sync always - sync init - update \src_l_r_src $1\src_l_r_src[2:0] - end - attribute \src "issuer_ls180.v:127658.13-127658.31" - process $proc$issuer_ls180.v:127658$5844 - assign { } { } - assign $1\src_l_s_src[2:0] 3'000 - sync always - sync init - update \src_l_s_src $1\src_l_s_src[2:0] - end - attribute \src "issuer_ls180.v:127666.14-127666.43" - process $proc$issuer_ls180.v:127666$5845 - assign { } { } - assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r0 $1\src_r0[63:0] - end - attribute \src "issuer_ls180.v:127670.14-127670.43" - process $proc$issuer_ls180.v:127670$5846 - assign { } { } - assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r1 $1\src_r1[63:0] - end - attribute \src "issuer_ls180.v:127674.7-127674.20" - process $proc$issuer_ls180.v:127674$5847 - assign { } { } - assign $1\src_r2[0:0] 1'0 - sync always - sync init - update \src_r2 $1\src_r2[0:0] - end - attribute \src "issuer_ls180.v:127740.3-127741.39" - process $proc$issuer_ls180.v:127740$5657 - assign { } { } - assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next - sync posedge \coresync_clk - update \alu_l_r_alu $0\alu_l_r_alu[0:0] - end - attribute \src "issuer_ls180.v:127742.3-127743.43" - process $proc$issuer_ls180.v:127742$5658 - assign { } { } - assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next - sync posedge \coresync_clk - update \alui_l_r_alui $0\alui_l_r_alui[0:0] - end - attribute \src "issuer_ls180.v:127744.3-127745.29" - process $proc$issuer_ls180.v:127744$5659 - assign { } { } - assign $0\src_r2[0:0] \src_r2$next - sync posedge \coresync_clk - update \src_r2 $0\src_r2[0:0] - end - attribute \src "issuer_ls180.v:127746.3-127747.29" - process $proc$issuer_ls180.v:127746$5660 - assign { } { } - assign $0\src_r1[63:0] \src_r1$next - sync posedge \coresync_clk - update \src_r1 $0\src_r1[63:0] - end - attribute \src "issuer_ls180.v:127748.3-127749.29" - process $proc$issuer_ls180.v:127748$5661 - assign { } { } - assign $0\src_r0[63:0] \src_r0$next - sync posedge \coresync_clk - update \src_r0 $0\src_r0[63:0] - end - attribute \src "issuer_ls180.v:127750.3-127751.43" - process $proc$issuer_ls180.v:127750$5662 - assign { } { } - assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next - sync posedge \coresync_clk - update \data_r1__cr_a $0\data_r1__cr_a[3:0] - end - attribute \src "issuer_ls180.v:127752.3-127753.49" - process $proc$issuer_ls180.v:127752$5663 - assign { } { } - assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next - sync posedge \coresync_clk - update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:127754.3-127755.37" - process $proc$issuer_ls180.v:127754$5664 - assign { } { } - assign $0\data_r0__o[63:0] \data_r0__o$next - sync posedge \coresync_clk - update \data_r0__o $0\data_r0__o[63:0] - end - attribute \src "issuer_ls180.v:127756.3-127757.43" - process $proc$issuer_ls180.v:127756$5665 - assign { } { } - assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next - sync posedge \coresync_clk - update \data_r0__o_ok $0\data_r0__o_ok[0:0] - end - attribute \src "issuer_ls180.v:127758.3-127759.85" - process $proc$issuer_ls180.v:127758$5666 - assign { } { } - assign $0\alu_logical0_logical_op__insn_type[6:0] \alu_logical0_logical_op__insn_type$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__insn_type $0\alu_logical0_logical_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:127760.3-127761.81" - process $proc$issuer_ls180.v:127760$5667 - assign { } { } - assign $0\alu_logical0_logical_op__fn_unit[11:0] \alu_logical0_logical_op__fn_unit$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__fn_unit $0\alu_logical0_logical_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:127762.3-127763.95" - process $proc$issuer_ls180.v:127762$5668 - assign { } { } - assign $0\alu_logical0_logical_op__imm_data__data[63:0] \alu_logical0_logical_op__imm_data__data$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__imm_data__data $0\alu_logical0_logical_op__imm_data__data[63:0] - end - attribute \src "issuer_ls180.v:127764.3-127765.91" - process $proc$issuer_ls180.v:127764$5669 - assign { } { } - assign $0\alu_logical0_logical_op__imm_data__ok[0:0] \alu_logical0_logical_op__imm_data__ok$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__imm_data__ok $0\alu_logical0_logical_op__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:127766.3-127767.79" - process $proc$issuer_ls180.v:127766$5670 - assign { } { } - assign $0\alu_logical0_logical_op__rc__rc[0:0] \alu_logical0_logical_op__rc__rc$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__rc__rc $0\alu_logical0_logical_op__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:127768.3-127769.79" - process $proc$issuer_ls180.v:127768$5671 - assign { } { } - assign $0\alu_logical0_logical_op__rc__ok[0:0] \alu_logical0_logical_op__rc__ok$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__rc__ok $0\alu_logical0_logical_op__rc__ok[0:0] - end - attribute \src "issuer_ls180.v:127770.3-127771.79" - process $proc$issuer_ls180.v:127770$5672 - assign { } { } - assign $0\alu_logical0_logical_op__oe__oe[0:0] \alu_logical0_logical_op__oe__oe$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__oe__oe $0\alu_logical0_logical_op__oe__oe[0:0] - end - attribute \src "issuer_ls180.v:127772.3-127773.79" - process $proc$issuer_ls180.v:127772$5673 - assign { } { } - assign $0\alu_logical0_logical_op__oe__ok[0:0] \alu_logical0_logical_op__oe__ok$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__oe__ok $0\alu_logical0_logical_op__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:127774.3-127775.85" - process $proc$issuer_ls180.v:127774$5674 - assign { } { } - assign $0\alu_logical0_logical_op__invert_in[0:0] \alu_logical0_logical_op__invert_in$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__invert_in $0\alu_logical0_logical_op__invert_in[0:0] - end - attribute \src "issuer_ls180.v:127776.3-127777.79" - process $proc$issuer_ls180.v:127776$5675 - assign { } { } - assign $0\alu_logical0_logical_op__zero_a[0:0] \alu_logical0_logical_op__zero_a$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__zero_a $0\alu_logical0_logical_op__zero_a[0:0] - end - attribute \src "issuer_ls180.v:127778.3-127779.89" - process $proc$issuer_ls180.v:127778$5676 - assign { } { } - assign $0\alu_logical0_logical_op__input_carry[1:0] \alu_logical0_logical_op__input_carry$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__input_carry $0\alu_logical0_logical_op__input_carry[1:0] - end - attribute \src "issuer_ls180.v:127780.3-127781.87" - process $proc$issuer_ls180.v:127780$5677 - assign { } { } - assign $0\alu_logical0_logical_op__invert_out[0:0] \alu_logical0_logical_op__invert_out$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__invert_out $0\alu_logical0_logical_op__invert_out[0:0] - end - attribute \src "issuer_ls180.v:127782.3-127783.85" - process $proc$issuer_ls180.v:127782$5678 - assign { } { } - assign $0\alu_logical0_logical_op__write_cr0[0:0] \alu_logical0_logical_op__write_cr0$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__write_cr0 $0\alu_logical0_logical_op__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:127784.3-127785.91" - process $proc$issuer_ls180.v:127784$5679 - assign { } { } - assign $0\alu_logical0_logical_op__output_carry[0:0] \alu_logical0_logical_op__output_carry$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__output_carry $0\alu_logical0_logical_op__output_carry[0:0] - end - attribute \src "issuer_ls180.v:127786.3-127787.83" - process $proc$issuer_ls180.v:127786$5680 - assign { } { } - assign $0\alu_logical0_logical_op__is_32bit[0:0] \alu_logical0_logical_op__is_32bit$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__is_32bit $0\alu_logical0_logical_op__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:127788.3-127789.85" - process $proc$issuer_ls180.v:127788$5681 - assign { } { } - assign $0\alu_logical0_logical_op__is_signed[0:0] \alu_logical0_logical_op__is_signed$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__is_signed $0\alu_logical0_logical_op__is_signed[0:0] - end - attribute \src "issuer_ls180.v:127790.3-127791.83" - process $proc$issuer_ls180.v:127790$5682 - assign { } { } - assign $0\alu_logical0_logical_op__data_len[3:0] \alu_logical0_logical_op__data_len$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__data_len $0\alu_logical0_logical_op__data_len[3:0] - end - attribute \src "issuer_ls180.v:127792.3-127793.75" - process $proc$issuer_ls180.v:127792$5683 - assign { } { } - assign $0\alu_logical0_logical_op__insn[31:0] \alu_logical0_logical_op__insn$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__insn $0\alu_logical0_logical_op__insn[31:0] - end - attribute \src "issuer_ls180.v:127794.3-127795.39" - process $proc$issuer_ls180.v:127794$5684 - assign { } { } - assign $0\req_l_r_req[1:0] \req_l_r_req$next - sync posedge \coresync_clk - update \req_l_r_req $0\req_l_r_req[1:0] - end - attribute \src "issuer_ls180.v:127796.3-127797.39" - process $proc$issuer_ls180.v:127796$5685 - assign { } { } - assign $0\req_l_s_req[1:0] \req_l_s_req$next - sync posedge \coresync_clk - update \req_l_s_req $0\req_l_s_req[1:0] - end - attribute \src "issuer_ls180.v:127798.3-127799.39" - process $proc$issuer_ls180.v:127798$5686 - assign { } { } - assign $0\src_l_r_src[2:0] \src_l_r_src$next - sync posedge \coresync_clk - update \src_l_r_src $0\src_l_r_src[2:0] - end - attribute \src "issuer_ls180.v:127800.3-127801.39" - process $proc$issuer_ls180.v:127800$5687 - assign { } { } - assign $0\src_l_s_src[2:0] \src_l_s_src$next - sync posedge \coresync_clk - update \src_l_s_src $0\src_l_s_src[2:0] - end - attribute \src "issuer_ls180.v:127802.3-127803.39" - process $proc$issuer_ls180.v:127802$5688 - assign { } { } - assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next - sync posedge \coresync_clk - update \opc_l_r_opc $0\opc_l_r_opc[0:0] - end - attribute \src "issuer_ls180.v:127804.3-127805.39" - process $proc$issuer_ls180.v:127804$5689 - assign { } { } - assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next - sync posedge \coresync_clk - update \opc_l_s_opc $0\opc_l_s_opc[0:0] - end - attribute \src "issuer_ls180.v:127806.3-127807.39" - process $proc$issuer_ls180.v:127806$5690 - assign { } { } - assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next - sync posedge \coresync_clk - update \rst_l_r_rst $0\rst_l_r_rst[0:0] - end - attribute \src "issuer_ls180.v:127808.3-127809.39" - process $proc$issuer_ls180.v:127808$5691 - assign { } { } - assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next - sync posedge \coresync_clk - update \rst_l_s_rst $0\rst_l_s_rst[0:0] - end - attribute \src "issuer_ls180.v:127810.3-127811.41" - process $proc$issuer_ls180.v:127810$5692 - assign { } { } - assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next - sync posedge \coresync_clk - update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] - end - attribute \src "issuer_ls180.v:127812.3-127813.41" - process $proc$issuer_ls180.v:127812$5693 - assign { } { } - assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next - sync posedge \coresync_clk - update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] - end - attribute \src "issuer_ls180.v:127814.3-127815.37" - process $proc$issuer_ls180.v:127814$5694 - assign { } { } - assign $0\prev_wr_go[1:0] \prev_wr_go$next - sync posedge \coresync_clk - update \prev_wr_go $0\prev_wr_go[1:0] - end - attribute \src "issuer_ls180.v:127816.3-127817.44" - process $proc$issuer_ls180.v:127816$5695 - assign { } { } - assign $0\alu_done_dly[0:0] \alu_logical0_n_valid_o - sync posedge \coresync_clk - update \alu_done_dly $0\alu_done_dly[0:0] - end - attribute \src "issuer_ls180.v:127818.3-127819.24" - process $proc$issuer_ls180.v:127818$5696 - assign { } { } - assign $0\all_rd_dly[0:0] \$9 - sync posedge \coresync_clk - update \all_rd_dly $0\all_rd_dly[0:0] - end - attribute \src "issuer_ls180.v:127901.3-127910.6" - process $proc$issuer_ls180.v:127901$5697 - assign { } { } - assign { } { } - assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "issuer_ls180.v:127902.5-127902.29" - switch \initial - attribute \src "issuer_ls180.v:127902.9-127902.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch \$53 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_done[0:0] 1'1 - case - assign $1\req_done[0:0] \$45 - end - sync always - update \req_done $0\req_done[0:0] - end - attribute \src "issuer_ls180.v:127911.3-127919.6" - process $proc$issuer_ls180.v:127911$5698 - assign { } { } - assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$5699 $1\rok_l_s_rdok$next[0:0]$5700 - attribute \src "issuer_ls180.v:127912.5-127912.29" - switch \initial - attribute \src "issuer_ls180.v:127912.9-127912.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$5700 1'0 - case - assign $1\rok_l_s_rdok$next[0:0]$5700 \cu_issue_i - end - sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$5699 - end - attribute \src "issuer_ls180.v:127920.3-127928.6" - process $proc$issuer_ls180.v:127920$5701 - assign { } { } - assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$5702 $1\rok_l_r_rdok$next[0:0]$5703 - attribute \src "issuer_ls180.v:127921.5-127921.29" - switch \initial - attribute \src "issuer_ls180.v:127921.9-127921.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$5703 1'1 - case - assign $1\rok_l_r_rdok$next[0:0]$5703 \$63 - end - sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$5702 - end - attribute \src "issuer_ls180.v:127929.3-127937.6" - process $proc$issuer_ls180.v:127929$5704 - assign { } { } - assign { } { } - assign $0\rst_l_s_rst$next[0:0]$5705 $1\rst_l_s_rst$next[0:0]$5706 - attribute \src "issuer_ls180.v:127930.5-127930.29" - switch \initial - attribute \src "issuer_ls180.v:127930.9-127930.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_s_rst$next[0:0]$5706 1'0 - case - assign $1\rst_l_s_rst$next[0:0]$5706 \all_rd - end - sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$5705 - end - attribute \src "issuer_ls180.v:127938.3-127946.6" - process $proc$issuer_ls180.v:127938$5707 - assign { } { } - assign { } { } - assign $0\rst_l_r_rst$next[0:0]$5708 $1\rst_l_r_rst$next[0:0]$5709 - attribute \src "issuer_ls180.v:127939.5-127939.29" - switch \initial - attribute \src "issuer_ls180.v:127939.9-127939.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_r_rst$next[0:0]$5709 1'1 - case - assign $1\rst_l_r_rst$next[0:0]$5709 \rst_r - end - sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$5708 - end - attribute \src "issuer_ls180.v:127947.3-127955.6" - process $proc$issuer_ls180.v:127947$5710 - assign { } { } - assign { } { } - assign $0\opc_l_s_opc$next[0:0]$5711 $1\opc_l_s_opc$next[0:0]$5712 - attribute \src "issuer_ls180.v:127948.5-127948.29" - switch \initial - attribute \src "issuer_ls180.v:127948.9-127948.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_s_opc$next[0:0]$5712 1'0 - case - assign $1\opc_l_s_opc$next[0:0]$5712 \cu_issue_i - end - sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5711 - end - attribute \src "issuer_ls180.v:127956.3-127964.6" - process $proc$issuer_ls180.v:127956$5713 - assign { } { } - assign { } { } - assign $0\opc_l_r_opc$next[0:0]$5714 $1\opc_l_r_opc$next[0:0]$5715 - attribute \src "issuer_ls180.v:127957.5-127957.29" - switch \initial - attribute \src "issuer_ls180.v:127957.9-127957.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_r_opc$next[0:0]$5715 1'1 - case - assign $1\opc_l_r_opc$next[0:0]$5715 \req_done - end - sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5714 - end - attribute \src "issuer_ls180.v:127965.3-127973.6" - process $proc$issuer_ls180.v:127965$5716 - assign { } { } - assign { } { } - assign $0\src_l_s_src$next[2:0]$5717 $1\src_l_s_src$next[2:0]$5718 - attribute \src "issuer_ls180.v:127966.5-127966.29" - switch \initial - attribute \src "issuer_ls180.v:127966.9-127966.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_s_src$next[2:0]$5718 3'000 - case - assign $1\src_l_s_src$next[2:0]$5718 { \cu_issue_i \cu_issue_i \cu_issue_i } - end - sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5717 - end - attribute \src "issuer_ls180.v:127974.3-127982.6" - process $proc$issuer_ls180.v:127974$5719 - assign { } { } - assign { } { } - assign $0\src_l_r_src$next[2:0]$5720 $1\src_l_r_src$next[2:0]$5721 - attribute \src "issuer_ls180.v:127975.5-127975.29" - switch \initial - attribute \src "issuer_ls180.v:127975.9-127975.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_r_src$next[2:0]$5721 3'111 - case - assign $1\src_l_r_src$next[2:0]$5721 \reset_r - end - sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5720 - end - attribute \src "issuer_ls180.v:127983.3-127991.6" - process $proc$issuer_ls180.v:127983$5722 - assign { } { } - assign { } { } - assign $0\req_l_s_req$next[1:0]$5723 $1\req_l_s_req$next[1:0]$5724 - attribute \src "issuer_ls180.v:127984.5-127984.29" - switch \initial - attribute \src "issuer_ls180.v:127984.9-127984.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_s_req$next[1:0]$5724 2'00 - case - assign $1\req_l_s_req$next[1:0]$5724 \$65 - end - sync always - update \req_l_s_req$next $0\req_l_s_req$next[1:0]$5723 - end - attribute \src "issuer_ls180.v:127992.3-128000.6" - process $proc$issuer_ls180.v:127992$5725 - assign { } { } - assign { } { } - assign $0\req_l_r_req$next[1:0]$5726 $1\req_l_r_req$next[1:0]$5727 - attribute \src "issuer_ls180.v:127993.5-127993.29" - switch \initial - attribute \src "issuer_ls180.v:127993.9-127993.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_r_req$next[1:0]$5727 2'11 - case - assign $1\req_l_r_req$next[1:0]$5727 \$67 - end - sync always - update \req_l_r_req$next $0\req_l_r_req$next[1:0]$5726 - end - attribute \src "issuer_ls180.v:128001.3-128039.6" - process $proc$issuer_ls180.v:128001$5728 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_logical0_logical_op__data_len$next[3:0]$5729 $1\alu_logical0_logical_op__data_len$next[3:0]$5747 - assign $0\alu_logical0_logical_op__fn_unit$next[11:0]$5730 $1\alu_logical0_logical_op__fn_unit$next[11:0]$5748 - assign { } { } - assign { } { } - assign $0\alu_logical0_logical_op__input_carry$next[1:0]$5733 $1\alu_logical0_logical_op__input_carry$next[1:0]$5751 - assign $0\alu_logical0_logical_op__insn$next[31:0]$5734 $1\alu_logical0_logical_op__insn$next[31:0]$5752 - assign $0\alu_logical0_logical_op__insn_type$next[6:0]$5735 $1\alu_logical0_logical_op__insn_type$next[6:0]$5753 - assign $0\alu_logical0_logical_op__invert_in$next[0:0]$5736 $1\alu_logical0_logical_op__invert_in$next[0:0]$5754 - assign $0\alu_logical0_logical_op__invert_out$next[0:0]$5737 $1\alu_logical0_logical_op__invert_out$next[0:0]$5755 - assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$5738 $1\alu_logical0_logical_op__is_32bit$next[0:0]$5756 - assign $0\alu_logical0_logical_op__is_signed$next[0:0]$5739 $1\alu_logical0_logical_op__is_signed$next[0:0]$5757 - assign { } { } - assign { } { } - assign $0\alu_logical0_logical_op__output_carry$next[0:0]$5742 $1\alu_logical0_logical_op__output_carry$next[0:0]$5760 - assign { } { } - assign { } { } - assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$5745 $1\alu_logical0_logical_op__write_cr0$next[0:0]$5763 - assign $0\alu_logical0_logical_op__zero_a$next[0:0]$5746 $1\alu_logical0_logical_op__zero_a$next[0:0]$5764 - assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$5731 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$5765 - assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$5732 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$5766 - assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$5740 $2\alu_logical0_logical_op__oe__oe$next[0:0]$5767 - assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$5741 $2\alu_logical0_logical_op__oe__ok$next[0:0]$5768 - assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$5743 $2\alu_logical0_logical_op__rc__ok$next[0:0]$5769 - assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$5744 $2\alu_logical0_logical_op__rc__rc$next[0:0]$5770 - attribute \src "issuer_ls180.v:128002.5-128002.29" - switch \initial - attribute \src "issuer_ls180.v:128002.9-128002.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_logical0_logical_op__insn$next[31:0]$5752 $1\alu_logical0_logical_op__data_len$next[3:0]$5747 $1\alu_logical0_logical_op__is_signed$next[0:0]$5757 $1\alu_logical0_logical_op__is_32bit$next[0:0]$5756 $1\alu_logical0_logical_op__output_carry$next[0:0]$5760 $1\alu_logical0_logical_op__write_cr0$next[0:0]$5763 $1\alu_logical0_logical_op__invert_out$next[0:0]$5755 $1\alu_logical0_logical_op__input_carry$next[1:0]$5751 $1\alu_logical0_logical_op__zero_a$next[0:0]$5764 $1\alu_logical0_logical_op__invert_in$next[0:0]$5754 $1\alu_logical0_logical_op__oe__ok$next[0:0]$5759 $1\alu_logical0_logical_op__oe__oe$next[0:0]$5758 $1\alu_logical0_logical_op__rc__ok$next[0:0]$5761 $1\alu_logical0_logical_op__rc__rc$next[0:0]$5762 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$5750 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$5749 $1\alu_logical0_logical_op__fn_unit$next[11:0]$5748 $1\alu_logical0_logical_op__insn_type$next[6:0]$5753 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } - case - assign $1\alu_logical0_logical_op__data_len$next[3:0]$5747 \alu_logical0_logical_op__data_len - assign $1\alu_logical0_logical_op__fn_unit$next[11:0]$5748 \alu_logical0_logical_op__fn_unit - assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$5749 \alu_logical0_logical_op__imm_data__data - assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$5750 \alu_logical0_logical_op__imm_data__ok - assign $1\alu_logical0_logical_op__input_carry$next[1:0]$5751 \alu_logical0_logical_op__input_carry - assign $1\alu_logical0_logical_op__insn$next[31:0]$5752 \alu_logical0_logical_op__insn - assign $1\alu_logical0_logical_op__insn_type$next[6:0]$5753 \alu_logical0_logical_op__insn_type - assign $1\alu_logical0_logical_op__invert_in$next[0:0]$5754 \alu_logical0_logical_op__invert_in - assign $1\alu_logical0_logical_op__invert_out$next[0:0]$5755 \alu_logical0_logical_op__invert_out - assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$5756 \alu_logical0_logical_op__is_32bit - assign $1\alu_logical0_logical_op__is_signed$next[0:0]$5757 \alu_logical0_logical_op__is_signed - assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$5758 \alu_logical0_logical_op__oe__oe - assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$5759 \alu_logical0_logical_op__oe__ok - assign $1\alu_logical0_logical_op__output_carry$next[0:0]$5760 \alu_logical0_logical_op__output_carry - assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$5761 \alu_logical0_logical_op__rc__ok - assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$5762 \alu_logical0_logical_op__rc__rc - assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$5763 \alu_logical0_logical_op__write_cr0 - assign $1\alu_logical0_logical_op__zero_a$next[0:0]$5764 \alu_logical0_logical_op__zero_a - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$5765 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$5766 1'0 - assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$5770 1'0 - assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$5769 1'0 - assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$5767 1'0 - assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$5768 1'0 - case - assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$5765 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$5749 - assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$5766 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$5750 - assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$5767 $1\alu_logical0_logical_op__oe__oe$next[0:0]$5758 - assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$5768 $1\alu_logical0_logical_op__oe__ok$next[0:0]$5759 - assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$5769 $1\alu_logical0_logical_op__rc__ok$next[0:0]$5761 - assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$5770 $1\alu_logical0_logical_op__rc__rc$next[0:0]$5762 - end - sync always - update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$5729 - update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[11:0]$5730 - update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$5731 - update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$5732 - update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$5733 - update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$5734 - update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$5735 - update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$5736 - update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$5737 - update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$5738 - update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$5739 - update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$5740 - update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$5741 - update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$5742 - update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$5743 - update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$5744 - update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$5745 - update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$5746 - end - attribute \src "issuer_ls180.v:128040.3-128061.6" - process $proc$issuer_ls180.v:128040$5771 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r0__o$next[63:0]$5772 $2\data_r0__o$next[63:0]$5776 - assign { } { } - assign $0\data_r0__o_ok$next[0:0]$5773 $3\data_r0__o_ok$next[0:0]$5778 - attribute \src "issuer_ls180.v:128041.5-128041.29" - switch \initial - attribute \src "issuer_ls180.v:128041.9-128041.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$5775 $1\data_r0__o$next[63:0]$5774 } { \o_ok \alu_logical0_o } - case - assign $1\data_r0__o$next[63:0]$5774 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$5775 \data_r0__o_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$5777 $2\data_r0__o$next[63:0]$5776 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r0__o$next[63:0]$5776 $1\data_r0__o$next[63:0]$5774 - assign $2\data_r0__o_ok$next[0:0]$5777 $1\data_r0__o_ok$next[0:0]$5775 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r0__o_ok$next[0:0]$5778 1'0 - case - assign $3\data_r0__o_ok$next[0:0]$5778 $2\data_r0__o_ok$next[0:0]$5777 - end - sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$5772 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$5773 - end - attribute \src "issuer_ls180.v:128062.3-128083.6" - process $proc$issuer_ls180.v:128062$5779 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r1__cr_a$next[3:0]$5780 $2\data_r1__cr_a$next[3:0]$5784 - assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$5781 $3\data_r1__cr_a_ok$next[0:0]$5786 - attribute \src "issuer_ls180.v:128063.5-128063.29" - switch \initial - attribute \src "issuer_ls180.v:128063.9-128063.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$5783 $1\data_r1__cr_a$next[3:0]$5782 } { \cr_a_ok \alu_logical0_cr_a } - case - assign $1\data_r1__cr_a$next[3:0]$5782 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$5783 \data_r1__cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$5785 $2\data_r1__cr_a$next[3:0]$5784 } 5'00000 - case - assign $2\data_r1__cr_a$next[3:0]$5784 $1\data_r1__cr_a$next[3:0]$5782 - assign $2\data_r1__cr_a_ok$next[0:0]$5785 $1\data_r1__cr_a_ok$next[0:0]$5783 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$5786 1'0 - case - assign $3\data_r1__cr_a_ok$next[0:0]$5786 $2\data_r1__cr_a_ok$next[0:0]$5785 - end - sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$5780 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$5781 - end - attribute \src "issuer_ls180.v:128084.3-128093.6" - process $proc$issuer_ls180.v:128084$5787 - assign { } { } - assign { } { } - assign $0\src_r0$next[63:0]$5788 $1\src_r0$next[63:0]$5789 - attribute \src "issuer_ls180.v:128085.5-128085.29" - switch \initial - attribute \src "issuer_ls180.v:128085.9-128085.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r0$next[63:0]$5789 \src_or_imm - case - assign $1\src_r0$next[63:0]$5789 \src_r0 - end - sync always - update \src_r0$next $0\src_r0$next[63:0]$5788 - end - attribute \src "issuer_ls180.v:128094.3-128103.6" - process $proc$issuer_ls180.v:128094$5790 - assign { } { } - assign { } { } - assign $0\src_r1$next[63:0]$5791 $1\src_r1$next[63:0]$5792 - attribute \src "issuer_ls180.v:128095.5-128095.29" - switch \initial - attribute \src "issuer_ls180.v:128095.9-128095.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_sel$77 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r1$next[63:0]$5792 \src_or_imm$80 - case - assign $1\src_r1$next[63:0]$5792 \src_r1 - end - sync always - update \src_r1$next $0\src_r1$next[63:0]$5791 - end - attribute \src "issuer_ls180.v:128104.3-128113.6" - process $proc$issuer_ls180.v:128104$5793 - assign { } { } - assign { } { } - assign $0\src_r2$next[0:0]$5794 $1\src_r2$next[0:0]$5795 - attribute \src "issuer_ls180.v:128105.5-128105.29" - switch \initial - attribute \src "issuer_ls180.v:128105.9-128105.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r2$next[0:0]$5795 \src3_i - case - assign $1\src_r2$next[0:0]$5795 \src_r2 - end - sync always - update \src_r2$next $0\src_r2$next[0:0]$5794 - end - attribute \src "issuer_ls180.v:128114.3-128122.6" - process $proc$issuer_ls180.v:128114$5796 - assign { } { } - assign { } { } - assign $0\alui_l_r_alui$next[0:0]$5797 $1\alui_l_r_alui$next[0:0]$5798 - attribute \src "issuer_ls180.v:128115.5-128115.29" - switch \initial - attribute \src "issuer_ls180.v:128115.9-128115.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alui_l_r_alui$next[0:0]$5798 1'1 - case - assign $1\alui_l_r_alui$next[0:0]$5798 \$89 - end - sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$5797 - end - attribute \src "issuer_ls180.v:128123.3-128131.6" - process $proc$issuer_ls180.v:128123$5799 - assign { } { } - assign { } { } - assign $0\alu_l_r_alu$next[0:0]$5800 $1\alu_l_r_alu$next[0:0]$5801 - attribute \src "issuer_ls180.v:128124.5-128124.29" - switch \initial - attribute \src "issuer_ls180.v:128124.9-128124.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alu_l_r_alu$next[0:0]$5801 1'1 - case - assign $1\alu_l_r_alu$next[0:0]$5801 \$91 - end - sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$5800 - end - attribute \src "issuer_ls180.v:128132.3-128141.6" - process $proc$issuer_ls180.v:128132$5802 - assign { } { } - assign { } { } - assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "issuer_ls180.v:128133.5-128133.29" - switch \initial - attribute \src "issuer_ls180.v:128133.9-128133.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$113 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest1_o[63:0] \data_r0__o - case - assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest1_o $0\dest1_o[63:0] - end - attribute \src "issuer_ls180.v:128142.3-128151.6" - process $proc$issuer_ls180.v:128142$5803 - assign { } { } - assign { } { } - assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "issuer_ls180.v:128143.5-128143.29" - switch \initial - attribute \src "issuer_ls180.v:128143.9-128143.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$115 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest2_o[3:0] \data_r1__cr_a - case - assign $1\dest2_o[3:0] 4'0000 - end - sync always - update \dest2_o $0\dest2_o[3:0] - end - attribute \src "issuer_ls180.v:128152.3-128160.6" - process $proc$issuer_ls180.v:128152$5804 - assign { } { } - assign { } { } - assign $0\prev_wr_go$next[1:0]$5805 $1\prev_wr_go$next[1:0]$5806 - attribute \src "issuer_ls180.v:128153.5-128153.29" - switch \initial - attribute \src "issuer_ls180.v:128153.9-128153.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\prev_wr_go$next[1:0]$5806 2'00 - case - assign $1\prev_wr_go$next[1:0]$5806 \$19 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[1:0]$5805 - end - connect \$9 $and$issuer_ls180.v:127683$5600_Y - connect \$99 $and$issuer_ls180.v:127684$5601_Y - connect \$101 $not$issuer_ls180.v:127685$5602_Y - connect \$103 $and$issuer_ls180.v:127686$5603_Y - connect \$105 $and$issuer_ls180.v:127687$5604_Y - connect \$107 $and$issuer_ls180.v:127688$5605_Y - connect \$109 $and$issuer_ls180.v:127689$5606_Y - connect \$111 $and$issuer_ls180.v:127690$5607_Y - connect \$113 $and$issuer_ls180.v:127691$5608_Y - connect \$115 $and$issuer_ls180.v:127692$5609_Y - connect \$11 $not$issuer_ls180.v:127693$5610_Y - connect \$13 $and$issuer_ls180.v:127694$5611_Y - connect \$15 $not$issuer_ls180.v:127695$5612_Y - connect \$17 $and$issuer_ls180.v:127696$5613_Y - connect \$1 $and$issuer_ls180.v:127697$5614_Y - connect \$19 $and$issuer_ls180.v:127698$5615_Y - connect \$23 $not$issuer_ls180.v:127699$5616_Y - connect \$25 $and$issuer_ls180.v:127700$5617_Y - connect \$22 $reduce_or$issuer_ls180.v:127701$5618_Y - connect \$21 $not$issuer_ls180.v:127702$5619_Y - connect \$29 $and$issuer_ls180.v:127703$5620_Y - connect \$31 $reduce_or$issuer_ls180.v:127704$5621_Y - connect \$33 $reduce_or$issuer_ls180.v:127705$5622_Y - connect \$35 $or$issuer_ls180.v:127706$5623_Y - connect \$37 $not$issuer_ls180.v:127707$5624_Y - connect \$39 $and$issuer_ls180.v:127708$5625_Y - connect \$41 $and$issuer_ls180.v:127709$5626_Y - connect \$43 $eq$issuer_ls180.v:127710$5627_Y - connect \$45 $and$issuer_ls180.v:127711$5628_Y - connect \$47 $eq$issuer_ls180.v:127712$5629_Y - connect \$4 $not$issuer_ls180.v:127713$5630_Y - connect \$49 $and$issuer_ls180.v:127714$5631_Y - connect \$51 $and$issuer_ls180.v:127715$5632_Y - connect \$53 $and$issuer_ls180.v:127716$5633_Y - connect \$55 $or$issuer_ls180.v:127717$5634_Y - connect \$57 $or$issuer_ls180.v:127718$5635_Y - connect \$59 $or$issuer_ls180.v:127719$5636_Y - connect \$61 $or$issuer_ls180.v:127720$5637_Y - connect \$63 $and$issuer_ls180.v:127721$5638_Y - connect \$65 $and$issuer_ls180.v:127722$5639_Y - connect \$67 $or$issuer_ls180.v:127723$5640_Y - connect \$6 $or$issuer_ls180.v:127724$5641_Y - connect \$69 $and$issuer_ls180.v:127725$5642_Y - connect \$71 $and$issuer_ls180.v:127726$5643_Y - connect \$73 $ternary$issuer_ls180.v:127727$5644_Y - connect \$75 $ternary$issuer_ls180.v:127728$5645_Y - connect \$78 $ternary$issuer_ls180.v:127729$5646_Y - connect \$3 $reduce_and$issuer_ls180.v:127730$5647_Y - connect \$81 $ternary$issuer_ls180.v:127731$5648_Y - connect \$83 $ternary$issuer_ls180.v:127732$5649_Y - connect \$85 $ternary$issuer_ls180.v:127733$5650_Y - connect \$87 $ternary$issuer_ls180.v:127734$5651_Y - connect \$89 $and$issuer_ls180.v:127735$5652_Y - connect \$91 $and$issuer_ls180.v:127736$5653_Y - connect \$93 $and$issuer_ls180.v:127737$5654_Y - connect \$95 $not$issuer_ls180.v:127738$5655_Y - connect \$97 $not$issuer_ls180.v:127739$5656_Y - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 - connect \cu_wr__rel_o \$111 - connect \cu_rd__rel_o \$103 - connect \cu_busy_o \opc_l_q_opc - connect \alu_l_s_alu \all_rd_pulse - connect \alu_logical0_n_ready_i \alu_l_q_alu - connect \alui_l_s_alui \all_rd_pulse - connect \alu_logical0_p_valid_i \alui_l_q_alui - connect \alu_logical0_xer_so \$87 - connect \alu_logical0_rb \$85 - connect \alu_logical0_ra \$83 - connect \src_or_imm$80 \$81 - connect \src_sel$77 \$78 - connect \src_or_imm \$75 - connect \src_sel \$73 - connect \cu_wrmask_o { \$71 \$69 } - connect \reset_r \$61 - connect \reset_w \$59 - connect \rst_r \$57 - connect \reset \$55 - connect \wr_any \$35 - connect \cu_done_o \$29 - connect \alu_pulsem { \alu_pulse \alu_pulse } - connect \alu_pulse \alu_done_rise - connect \alu_done_rise \$17 - connect \alu_done_dly$next \alu_done - connect \alu_done \alu_logical0_n_valid_o - connect \all_rd_pulse \all_rd_rise - connect \all_rd_rise \$13 - connect \all_rd_dly$next \all_rd - connect \all_rd \$9 -end -attribute \src "issuer_ls180.v:128197.1-129567.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1" -attribute \generator "nMigen" -module \logical_pipe1 - attribute \src "issuer_ls180.v:129506.3-129524.6" - wire width 4 $0\cr_a$next[3:0]$5932 - attribute \src "issuer_ls180.v:129266.3-129267.25" - wire width 4 $0\cr_a[3:0] - attribute \src "issuer_ls180.v:129506.3-129524.6" - wire $0\cr_a_ok$next[0:0]$5933 - attribute \src "issuer_ls180.v:129268.3-129269.31" - wire $0\cr_a_ok[0:0] - attribute \src "issuer_ls180.v:128198.7-128198.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire width 4 $0\logical_op__data_len$next[3:0]$5883 - attribute \src "issuer_ls180.v:129306.3-129307.57" - wire width 4 $0\logical_op__data_len[3:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire width 12 $0\logical_op__fn_unit$next[11:0]$5884 - attribute \src "issuer_ls180.v:129276.3-129277.55" - wire width 12 $0\logical_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire width 64 $0\logical_op__imm_data__data$next[63:0]$5885 - attribute \src "issuer_ls180.v:129278.3-129279.69" - wire width 64 $0\logical_op__imm_data__data[63:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $0\logical_op__imm_data__ok$next[0:0]$5886 - attribute \src "issuer_ls180.v:129280.3-129281.65" - wire $0\logical_op__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire width 2 $0\logical_op__input_carry$next[1:0]$5887 - attribute \src "issuer_ls180.v:129294.3-129295.63" - wire width 2 $0\logical_op__input_carry[1:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire width 32 $0\logical_op__insn$next[31:0]$5888 - attribute \src "issuer_ls180.v:129308.3-129309.49" - wire width 32 $0\logical_op__insn[31:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire width 7 $0\logical_op__insn_type$next[6:0]$5889 - attribute \src "issuer_ls180.v:129274.3-129275.59" - wire width 7 $0\logical_op__insn_type[6:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $0\logical_op__invert_in$next[0:0]$5890 - attribute \src "issuer_ls180.v:129290.3-129291.59" - wire $0\logical_op__invert_in[0:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $0\logical_op__invert_out$next[0:0]$5891 - attribute \src "issuer_ls180.v:129296.3-129297.61" - wire $0\logical_op__invert_out[0:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $0\logical_op__is_32bit$next[0:0]$5892 - attribute \src "issuer_ls180.v:129302.3-129303.57" - wire $0\logical_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $0\logical_op__is_signed$next[0:0]$5893 - attribute \src "issuer_ls180.v:129304.3-129305.59" - wire $0\logical_op__is_signed[0:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $0\logical_op__oe__oe$next[0:0]$5894 - attribute \src "issuer_ls180.v:129286.3-129287.53" - wire $0\logical_op__oe__oe[0:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $0\logical_op__oe__ok$next[0:0]$5895 - attribute \src "issuer_ls180.v:129288.3-129289.53" - wire $0\logical_op__oe__ok[0:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $0\logical_op__output_carry$next[0:0]$5896 - attribute \src "issuer_ls180.v:129300.3-129301.65" - wire $0\logical_op__output_carry[0:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $0\logical_op__rc__ok$next[0:0]$5897 - attribute \src "issuer_ls180.v:129284.3-129285.53" - wire $0\logical_op__rc__ok[0:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $0\logical_op__rc__rc$next[0:0]$5898 - attribute \src "issuer_ls180.v:129282.3-129283.53" - wire $0\logical_op__rc__rc[0:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $0\logical_op__write_cr0$next[0:0]$5899 - attribute \src "issuer_ls180.v:129298.3-129299.59" - wire $0\logical_op__write_cr0[0:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $0\logical_op__zero_a$next[0:0]$5900 - attribute \src "issuer_ls180.v:129292.3-129293.53" - wire $0\logical_op__zero_a[0:0] - attribute \src "issuer_ls180.v:129432.3-129444.6" - wire width 2 $0\muxid$next[1:0]$5880 - attribute \src "issuer_ls180.v:129310.3-129311.27" - wire width 2 $0\muxid[1:0] - attribute \src "issuer_ls180.v:129487.3-129505.6" - wire width 64 $0\o$next[63:0]$5926 - attribute \src "issuer_ls180.v:129270.3-129271.19" - wire width 64 $0\o[63:0] - attribute \src "issuer_ls180.v:129487.3-129505.6" - wire $0\o_ok$next[0:0]$5927 - attribute \src "issuer_ls180.v:129272.3-129273.25" - wire $0\o_ok[0:0] - attribute \src "issuer_ls180.v:129414.3-129431.6" - wire $0\r_busy$next[0:0]$5876 - attribute \src "issuer_ls180.v:129312.3-129313.29" - wire $0\r_busy[0:0] - attribute \src "issuer_ls180.v:129525.3-129543.6" - wire $0\xer_so$next[0:0]$5938 - attribute \src "issuer_ls180.v:129262.3-129263.29" - wire $0\xer_so[0:0] - attribute \src "issuer_ls180.v:129525.3-129543.6" - wire $0\xer_so_ok$next[0:0]$5939 - attribute \src "issuer_ls180.v:129264.3-129265.35" - wire $0\xer_so_ok[0:0] - attribute \src "issuer_ls180.v:129506.3-129524.6" - wire width 4 $1\cr_a$next[3:0]$5934 - attribute \src "issuer_ls180.v:128207.13-128207.24" - wire width 4 $1\cr_a[3:0] - attribute \src "issuer_ls180.v:129506.3-129524.6" - wire $1\cr_a_ok$next[0:0]$5935 - attribute \src "issuer_ls180.v:128216.7-128216.21" - wire $1\cr_a_ok[0:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire width 4 $1\logical_op__data_len$next[3:0]$5901 - attribute \src "issuer_ls180.v:128495.13-128495.40" - wire width 4 $1\logical_op__data_len[3:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire width 12 $1\logical_op__fn_unit$next[11:0]$5902 - attribute \src "issuer_ls180.v:128517.14-128517.43" - wire width 12 $1\logical_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire width 64 $1\logical_op__imm_data__data$next[63:0]$5903 - attribute \src "issuer_ls180.v:128552.14-128552.63" - wire width 64 $1\logical_op__imm_data__data[63:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $1\logical_op__imm_data__ok$next[0:0]$5904 - attribute \src "issuer_ls180.v:128561.7-128561.38" - wire $1\logical_op__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire width 2 $1\logical_op__input_carry$next[1:0]$5905 - attribute \src "issuer_ls180.v:128574.13-128574.43" - wire width 2 $1\logical_op__input_carry[1:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire width 32 $1\logical_op__insn$next[31:0]$5906 - attribute \src "issuer_ls180.v:128591.14-128591.38" - wire width 32 $1\logical_op__insn[31:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire width 7 $1\logical_op__insn_type$next[6:0]$5907 - attribute \src "issuer_ls180.v:128674.13-128674.42" - wire width 7 $1\logical_op__insn_type[6:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $1\logical_op__invert_in$next[0:0]$5908 - attribute \src "issuer_ls180.v:128831.7-128831.35" - wire $1\logical_op__invert_in[0:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $1\logical_op__invert_out$next[0:0]$5909 - attribute \src "issuer_ls180.v:128840.7-128840.36" - wire $1\logical_op__invert_out[0:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $1\logical_op__is_32bit$next[0:0]$5910 - attribute \src "issuer_ls180.v:128849.7-128849.34" - wire $1\logical_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $1\logical_op__is_signed$next[0:0]$5911 - attribute \src "issuer_ls180.v:128858.7-128858.35" - wire $1\logical_op__is_signed[0:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $1\logical_op__oe__oe$next[0:0]$5912 - attribute \src "issuer_ls180.v:128867.7-128867.32" - wire $1\logical_op__oe__oe[0:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $1\logical_op__oe__ok$next[0:0]$5913 - attribute \src "issuer_ls180.v:128876.7-128876.32" - wire $1\logical_op__oe__ok[0:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $1\logical_op__output_carry$next[0:0]$5914 - attribute \src "issuer_ls180.v:128885.7-128885.38" - wire $1\logical_op__output_carry[0:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $1\logical_op__rc__ok$next[0:0]$5915 - attribute \src "issuer_ls180.v:128894.7-128894.32" - wire $1\logical_op__rc__ok[0:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $1\logical_op__rc__rc$next[0:0]$5916 - attribute \src "issuer_ls180.v:128903.7-128903.32" - wire $1\logical_op__rc__rc[0:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $1\logical_op__write_cr0$next[0:0]$5917 - attribute \src "issuer_ls180.v:128912.7-128912.35" - wire $1\logical_op__write_cr0[0:0] - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $1\logical_op__zero_a$next[0:0]$5918 - attribute \src "issuer_ls180.v:128921.7-128921.32" - wire $1\logical_op__zero_a[0:0] - attribute \src "issuer_ls180.v:129432.3-129444.6" - wire width 2 $1\muxid$next[1:0]$5881 - attribute \src "issuer_ls180.v:129200.13-129200.25" - wire width 2 $1\muxid[1:0] - attribute \src "issuer_ls180.v:129487.3-129505.6" - wire width 64 $1\o$next[63:0]$5928 - attribute \src "issuer_ls180.v:129215.14-129215.38" - wire width 64 $1\o[63:0] - attribute \src "issuer_ls180.v:129487.3-129505.6" - wire $1\o_ok$next[0:0]$5929 - attribute \src "issuer_ls180.v:129222.7-129222.18" - wire $1\o_ok[0:0] - attribute \src "issuer_ls180.v:129414.3-129431.6" - wire $1\r_busy$next[0:0]$5877 - attribute \src "issuer_ls180.v:129236.7-129236.20" - wire $1\r_busy[0:0] - attribute \src "issuer_ls180.v:129525.3-129543.6" - wire $1\xer_so$next[0:0]$5940 - attribute \src "issuer_ls180.v:129245.7-129245.20" - wire $1\xer_so[0:0] - attribute \src "issuer_ls180.v:129525.3-129543.6" - wire $1\xer_so_ok$next[0:0]$5941 - attribute \src "issuer_ls180.v:129254.7-129254.23" - wire $1\xer_so_ok[0:0] - attribute \src "issuer_ls180.v:129506.3-129524.6" - wire $2\cr_a_ok$next[0:0]$5936 - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire width 64 $2\logical_op__imm_data__data$next[63:0]$5919 - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $2\logical_op__imm_data__ok$next[0:0]$5920 - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $2\logical_op__oe__oe$next[0:0]$5921 - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $2\logical_op__oe__ok$next[0:0]$5922 - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $2\logical_op__rc__ok$next[0:0]$5923 - attribute \src "issuer_ls180.v:129445.3-129486.6" - wire $2\logical_op__rc__rc$next[0:0]$5924 - attribute \src "issuer_ls180.v:129487.3-129505.6" - wire $2\o_ok$next[0:0]$5930 - attribute \src "issuer_ls180.v:129414.3-129431.6" - wire $2\r_busy$next[0:0]$5878 - attribute \src "issuer_ls180.v:129525.3-129543.6" - wire $2\xer_so_ok$next[0:0]$5942 - attribute \src "issuer_ls180.v:129261.18-129261.118" - wire $and$issuer_ls180.v:129261$5848_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 53 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 26 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$next - attribute \src "issuer_ls180.v:128198.7-128198.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_logical_op__data_len$38 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_logical_op__fn_unit$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_logical_op__imm_data__data$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__imm_data__ok$25 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_logical_op__input_carry$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_logical_op__insn$39 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute 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"OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 40 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 43 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 46 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 47 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 38 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 39 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 18 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 45 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 37 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 36 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 44 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 41 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \main_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \main_logical_op__data_len$60 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_logical_op__fn_unit$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_logical_op__imm_data__data$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__imm_data__ok$47 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_logical_op__input_carry$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_logical_op__insn$61 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_logical_op__insn_type$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__invert_in$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__invert_out$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__is_32bit$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__is_signed$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__oe__oe$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__oe__ok$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__output_carry$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__rc__ok$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__rc__rc$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__write_cr0$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__zero_a$53 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \main_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_xer_so$62 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 31 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$66 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 3 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 23 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 24 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 30 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 29 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$63 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 50 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 51 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 27 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 52 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 28 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$issuer_ls180.v:129261$5848 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$63 - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:129261$5848_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:129314.14-129359.4" - cell \input$47 \input - connect \logical_op__data_len \input_logical_op__data_len - connect \logical_op__data_len$18 \input_logical_op__data_len$38 - connect \logical_op__fn_unit \input_logical_op__fn_unit - connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$23 - connect \logical_op__imm_data__data \input_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \input_logical_op__imm_data__data$24 - connect \logical_op__imm_data__ok \input_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \input_logical_op__imm_data__ok$25 - connect \logical_op__input_carry \input_logical_op__input_carry - connect \logical_op__input_carry$12 \input_logical_op__input_carry$32 - connect \logical_op__insn \input_logical_op__insn - connect \logical_op__insn$19 \input_logical_op__insn$39 - connect \logical_op__insn_type \input_logical_op__insn_type - connect \logical_op__insn_type$2 \input_logical_op__insn_type$22 - connect \logical_op__invert_in \input_logical_op__invert_in - connect \logical_op__invert_in$10 \input_logical_op__invert_in$30 - connect \logical_op__invert_out \input_logical_op__invert_out - connect \logical_op__invert_out$13 \input_logical_op__invert_out$33 - connect \logical_op__is_32bit \input_logical_op__is_32bit - connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$36 - connect \logical_op__is_signed \input_logical_op__is_signed - connect \logical_op__is_signed$17 \input_logical_op__is_signed$37 - connect \logical_op__oe__oe \input_logical_op__oe__oe - connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$28 - connect \logical_op__oe__ok \input_logical_op__oe__ok - connect \logical_op__oe__ok$9 \input_logical_op__oe__ok$29 - connect \logical_op__output_carry \input_logical_op__output_carry - connect \logical_op__output_carry$15 \input_logical_op__output_carry$35 - connect \logical_op__rc__ok \input_logical_op__rc__ok - connect \logical_op__rc__ok$7 \input_logical_op__rc__ok$27 - connect \logical_op__rc__rc \input_logical_op__rc__rc - connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$26 - connect \logical_op__write_cr0 \input_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$34 - connect \logical_op__zero_a \input_logical_op__zero_a - connect \logical_op__zero_a$11 \input_logical_op__zero_a$31 - connect \muxid \input_muxid - connect \muxid$1 \input_muxid$21 - connect \ra \input_ra - connect \ra$20 \input_ra$40 - connect \rb \input_rb - connect \rb$21 \input_rb$41 - connect \xer_so \input_xer_so - connect \xer_so$22 \input_xer_so$42 - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:129360.13-129405.4" - cell \main$48 \main - connect \logical_op__data_len \main_logical_op__data_len - connect \logical_op__data_len$18 \main_logical_op__data_len$60 - connect \logical_op__fn_unit \main_logical_op__fn_unit - connect \logical_op__fn_unit$3 \main_logical_op__fn_unit$45 - connect \logical_op__imm_data__data \main_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \main_logical_op__imm_data__data$46 - connect \logical_op__imm_data__ok \main_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \main_logical_op__imm_data__ok$47 - connect \logical_op__input_carry \main_logical_op__input_carry - connect \logical_op__input_carry$12 \main_logical_op__input_carry$54 - connect \logical_op__insn \main_logical_op__insn - connect \logical_op__insn$19 \main_logical_op__insn$61 - connect \logical_op__insn_type \main_logical_op__insn_type - connect \logical_op__insn_type$2 \main_logical_op__insn_type$44 - connect \logical_op__invert_in \main_logical_op__invert_in - connect \logical_op__invert_in$10 \main_logical_op__invert_in$52 - connect \logical_op__invert_out \main_logical_op__invert_out - connect \logical_op__invert_out$13 \main_logical_op__invert_out$55 - connect \logical_op__is_32bit \main_logical_op__is_32bit - connect \logical_op__is_32bit$16 \main_logical_op__is_32bit$58 - connect \logical_op__is_signed \main_logical_op__is_signed - connect \logical_op__is_signed$17 \main_logical_op__is_signed$59 - connect \logical_op__oe__oe \main_logical_op__oe__oe - connect \logical_op__oe__oe$8 \main_logical_op__oe__oe$50 - connect \logical_op__oe__ok \main_logical_op__oe__ok - connect \logical_op__oe__ok$9 \main_logical_op__oe__ok$51 - connect \logical_op__output_carry \main_logical_op__output_carry - connect \logical_op__output_carry$15 \main_logical_op__output_carry$57 - connect \logical_op__rc__ok \main_logical_op__rc__ok - connect \logical_op__rc__ok$7 \main_logical_op__rc__ok$49 - connect \logical_op__rc__rc \main_logical_op__rc__rc - connect \logical_op__rc__rc$6 \main_logical_op__rc__rc$48 - connect \logical_op__write_cr0 \main_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \main_logical_op__write_cr0$56 - connect \logical_op__zero_a \main_logical_op__zero_a - connect \logical_op__zero_a$11 \main_logical_op__zero_a$53 - connect \muxid \main_muxid - connect \muxid$1 \main_muxid$43 - connect \o \main_o - connect \o_ok \main_o_ok - connect \ra \main_ra - connect \rb \main_rb - connect \xer_so \main_xer_so - connect \xer_so$20 \main_xer_so$62 - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:129406.10-129409.4" - cell \n$46 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:129410.10-129413.4" - cell \p$45 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "issuer_ls180.v:128198.7-128198.20" - process $proc$issuer_ls180.v:128198$5943 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:128207.13-128207.24" - process $proc$issuer_ls180.v:128207$5944 - assign { } { } - assign $1\cr_a[3:0] 4'0000 - sync always - sync init - update \cr_a $1\cr_a[3:0] - end - attribute \src "issuer_ls180.v:128216.7-128216.21" - process $proc$issuer_ls180.v:128216$5945 - assign { } { } - assign $1\cr_a_ok[0:0] 1'0 - sync always - sync init - update \cr_a_ok $1\cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:128495.13-128495.40" - process $proc$issuer_ls180.v:128495$5946 - assign { } { } - assign $1\logical_op__data_len[3:0] 4'0000 - sync always - sync init - update \logical_op__data_len $1\logical_op__data_len[3:0] - end - attribute \src "issuer_ls180.v:128517.14-128517.43" - process $proc$issuer_ls180.v:128517$5947 - assign { } { } - assign $1\logical_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \logical_op__fn_unit $1\logical_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:128552.14-128552.63" - process $proc$issuer_ls180.v:128552$5948 - assign { } { } - assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] - end - attribute \src "issuer_ls180.v:128561.7-128561.38" - process $proc$issuer_ls180.v:128561$5949 - assign { } { } - assign $1\logical_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:128574.13-128574.43" - process $proc$issuer_ls180.v:128574$5950 - assign { } { } - assign $1\logical_op__input_carry[1:0] 2'00 - sync always - sync init - update \logical_op__input_carry $1\logical_op__input_carry[1:0] - end - attribute \src "issuer_ls180.v:128591.14-128591.38" - process $proc$issuer_ls180.v:128591$5951 - assign { } { } - assign $1\logical_op__insn[31:0] 0 - sync always - sync init - update \logical_op__insn $1\logical_op__insn[31:0] - end - attribute \src "issuer_ls180.v:128674.13-128674.42" - process $proc$issuer_ls180.v:128674$5952 - assign { } { } - assign $1\logical_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \logical_op__insn_type $1\logical_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:128831.7-128831.35" - process $proc$issuer_ls180.v:128831$5953 - assign { } { } - assign $1\logical_op__invert_in[0:0] 1'0 - sync always - sync init - update \logical_op__invert_in $1\logical_op__invert_in[0:0] - end - attribute \src "issuer_ls180.v:128840.7-128840.36" - process $proc$issuer_ls180.v:128840$5954 - assign { } { } - assign $1\logical_op__invert_out[0:0] 1'0 - sync always - sync init - update \logical_op__invert_out $1\logical_op__invert_out[0:0] - end - attribute \src "issuer_ls180.v:128849.7-128849.34" - process $proc$issuer_ls180.v:128849$5955 - assign { } { } - assign $1\logical_op__is_32bit[0:0] 1'0 - sync always - sync init - update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:128858.7-128858.35" - process $proc$issuer_ls180.v:128858$5956 - assign { } { } - assign $1\logical_op__is_signed[0:0] 1'0 - sync always - sync init - update \logical_op__is_signed $1\logical_op__is_signed[0:0] - end - attribute \src "issuer_ls180.v:128867.7-128867.32" - process $proc$issuer_ls180.v:128867$5957 - assign { } { } - assign $1\logical_op__oe__oe[0:0] 1'0 - sync always - sync init - update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] - end - attribute \src "issuer_ls180.v:128876.7-128876.32" - process $proc$issuer_ls180.v:128876$5958 - assign { } { } - assign $1\logical_op__oe__ok[0:0] 1'0 - sync always - sync init - update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:128885.7-128885.38" - process $proc$issuer_ls180.v:128885$5959 - assign { } { } - assign $1\logical_op__output_carry[0:0] 1'0 - sync always - sync init - update \logical_op__output_carry $1\logical_op__output_carry[0:0] - end - attribute \src "issuer_ls180.v:128894.7-128894.32" - process $proc$issuer_ls180.v:128894$5960 - assign { } { } - assign $1\logical_op__rc__ok[0:0] 1'0 - sync always - sync init - update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] - end - attribute \src "issuer_ls180.v:128903.7-128903.32" - process $proc$issuer_ls180.v:128903$5961 - assign { } { } - assign $1\logical_op__rc__rc[0:0] 1'0 - sync always - sync init - update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:128912.7-128912.35" - process $proc$issuer_ls180.v:128912$5962 - assign { } { } - assign $1\logical_op__write_cr0[0:0] 1'0 - sync always - sync init - update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:128921.7-128921.32" - process $proc$issuer_ls180.v:128921$5963 - assign { } { } - assign $1\logical_op__zero_a[0:0] 1'0 - sync always - sync init - update \logical_op__zero_a $1\logical_op__zero_a[0:0] - end - attribute \src "issuer_ls180.v:129200.13-129200.25" - process $proc$issuer_ls180.v:129200$5964 - assign { } { } - assign $1\muxid[1:0] 2'00 - sync always - sync init - update \muxid $1\muxid[1:0] - end - attribute \src "issuer_ls180.v:129215.14-129215.38" - process $proc$issuer_ls180.v:129215$5965 - assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o $1\o[63:0] - end - attribute \src "issuer_ls180.v:129222.7-129222.18" - process $proc$issuer_ls180.v:129222$5966 - assign { } { } - assign $1\o_ok[0:0] 1'0 - sync always - sync init - update \o_ok $1\o_ok[0:0] - end - attribute \src "issuer_ls180.v:129236.7-129236.20" - process $proc$issuer_ls180.v:129236$5967 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "issuer_ls180.v:129245.7-129245.20" - process $proc$issuer_ls180.v:129245$5968 - assign { } { } - assign $1\xer_so[0:0] 1'0 - sync always - sync init - update \xer_so $1\xer_so[0:0] - end - attribute \src "issuer_ls180.v:129254.7-129254.23" - process $proc$issuer_ls180.v:129254$5969 - assign { } { } - assign $1\xer_so_ok[0:0] 1'0 - sync always - sync init - update \xer_so_ok $1\xer_so_ok[0:0] - end - attribute \src "issuer_ls180.v:129262.3-129263.29" - process $proc$issuer_ls180.v:129262$5849 - assign { } { } - assign $0\xer_so[0:0] \xer_so$next - sync posedge \coresync_clk - update \xer_so $0\xer_so[0:0] - end - attribute \src "issuer_ls180.v:129264.3-129265.35" - process $proc$issuer_ls180.v:129264$5850 - assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next - sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] - end - attribute \src "issuer_ls180.v:129266.3-129267.25" - process $proc$issuer_ls180.v:129266$5851 - assign { } { } - assign $0\cr_a[3:0] \cr_a$next - sync posedge \coresync_clk - update \cr_a $0\cr_a[3:0] - end - attribute \src "issuer_ls180.v:129268.3-129269.31" - process $proc$issuer_ls180.v:129268$5852 - assign { } { } - assign $0\cr_a_ok[0:0] \cr_a_ok$next - sync posedge \coresync_clk - update \cr_a_ok $0\cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:129270.3-129271.19" - process $proc$issuer_ls180.v:129270$5853 - assign { } { } - assign $0\o[63:0] \o$next - sync posedge \coresync_clk - update \o $0\o[63:0] - end - attribute \src "issuer_ls180.v:129272.3-129273.25" - process $proc$issuer_ls180.v:129272$5854 - assign { } { } - assign $0\o_ok[0:0] \o_ok$next - sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] - end - attribute \src "issuer_ls180.v:129274.3-129275.59" - process $proc$issuer_ls180.v:129274$5855 - assign { } { } - assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next - sync posedge \coresync_clk - update \logical_op__insn_type $0\logical_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:129276.3-129277.55" - process $proc$issuer_ls180.v:129276$5856 - assign { } { } - assign $0\logical_op__fn_unit[11:0] \logical_op__fn_unit$next - sync posedge \coresync_clk - update \logical_op__fn_unit $0\logical_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:129278.3-129279.69" - process $proc$issuer_ls180.v:129278$5857 - assign { } { } - assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next - sync posedge \coresync_clk - update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] - end - attribute \src "issuer_ls180.v:129280.3-129281.65" - process $proc$issuer_ls180.v:129280$5858 - assign { } { } - assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next - sync posedge \coresync_clk - update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:129282.3-129283.53" - process $proc$issuer_ls180.v:129282$5859 - assign { } { } - assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next - sync posedge \coresync_clk - update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:129284.3-129285.53" - process $proc$issuer_ls180.v:129284$5860 - assign { } { } - assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next - sync posedge \coresync_clk - update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] - end - attribute \src "issuer_ls180.v:129286.3-129287.53" - process $proc$issuer_ls180.v:129286$5861 - assign { } { } - assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next - sync posedge \coresync_clk - update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] - end - attribute \src "issuer_ls180.v:129288.3-129289.53" - process $proc$issuer_ls180.v:129288$5862 - assign { } { } - assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next - sync posedge \coresync_clk - update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:129290.3-129291.59" - process $proc$issuer_ls180.v:129290$5863 - assign { } { } - assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next - sync posedge \coresync_clk - update \logical_op__invert_in $0\logical_op__invert_in[0:0] - end - attribute \src "issuer_ls180.v:129292.3-129293.53" - process $proc$issuer_ls180.v:129292$5864 - assign { } { } - assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next - sync posedge \coresync_clk - update \logical_op__zero_a $0\logical_op__zero_a[0:0] - end - attribute \src "issuer_ls180.v:129294.3-129295.63" - process $proc$issuer_ls180.v:129294$5865 - assign { } { } - assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next - sync posedge \coresync_clk - update \logical_op__input_carry $0\logical_op__input_carry[1:0] - end - attribute \src "issuer_ls180.v:129296.3-129297.61" - process $proc$issuer_ls180.v:129296$5866 - assign { } { } - assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next - sync posedge \coresync_clk - update \logical_op__invert_out $0\logical_op__invert_out[0:0] - end - attribute \src "issuer_ls180.v:129298.3-129299.59" - process $proc$issuer_ls180.v:129298$5867 - assign { } { } - assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next - sync posedge \coresync_clk - update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:129300.3-129301.65" - process $proc$issuer_ls180.v:129300$5868 - assign { } { } - assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next - sync posedge \coresync_clk - update \logical_op__output_carry $0\logical_op__output_carry[0:0] - end - attribute \src "issuer_ls180.v:129302.3-129303.57" - process $proc$issuer_ls180.v:129302$5869 - assign { } { } - assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next - sync posedge \coresync_clk - update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:129304.3-129305.59" - process $proc$issuer_ls180.v:129304$5870 - assign { } { } - assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next - sync posedge \coresync_clk - update \logical_op__is_signed $0\logical_op__is_signed[0:0] - end - attribute \src "issuer_ls180.v:129306.3-129307.57" - process $proc$issuer_ls180.v:129306$5871 - assign { } { } - assign $0\logical_op__data_len[3:0] \logical_op__data_len$next - sync posedge \coresync_clk - update \logical_op__data_len $0\logical_op__data_len[3:0] - end - attribute \src "issuer_ls180.v:129308.3-129309.49" - process $proc$issuer_ls180.v:129308$5872 - assign { } { } - assign $0\logical_op__insn[31:0] \logical_op__insn$next - sync posedge \coresync_clk - update \logical_op__insn $0\logical_op__insn[31:0] - end - attribute \src "issuer_ls180.v:129310.3-129311.27" - process $proc$issuer_ls180.v:129310$5873 - assign { } { } - assign $0\muxid[1:0] \muxid$next - sync posedge \coresync_clk - update \muxid $0\muxid[1:0] - end - attribute \src "issuer_ls180.v:129312.3-129313.29" - process $proc$issuer_ls180.v:129312$5874 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "issuer_ls180.v:129414.3-129431.6" - process $proc$issuer_ls180.v:129414$5875 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$5876 $2\r_busy$next[0:0]$5878 - attribute \src "issuer_ls180.v:129415.5-129415.29" - switch \initial - attribute \src "issuer_ls180.v:129415.9-129415.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$5877 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\r_busy$next[0:0]$5877 1'0 - case - assign $1\r_busy$next[0:0]$5877 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$5878 1'0 - case - assign $2\r_busy$next[0:0]$5878 $1\r_busy$next[0:0]$5877 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$5876 - end - attribute \src "issuer_ls180.v:129432.3-129444.6" - process $proc$issuer_ls180.v:129432$5879 - assign { } { } - assign { } { } - assign $0\muxid$next[1:0]$5880 $1\muxid$next[1:0]$5881 - attribute \src "issuer_ls180.v:129433.5-129433.29" - switch \initial - attribute \src "issuer_ls180.v:129433.9-129433.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$next[1:0]$5881 \muxid$66 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$next[1:0]$5881 \muxid$66 - case - assign $1\muxid$next[1:0]$5881 \muxid - end - sync always - update \muxid$next $0\muxid$next[1:0]$5880 - end - attribute \src "issuer_ls180.v:129445.3-129486.6" - process $proc$issuer_ls180.v:129445$5882 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\logical_op__data_len$next[3:0]$5883 $1\logical_op__data_len$next[3:0]$5901 - assign $0\logical_op__fn_unit$next[11:0]$5884 $1\logical_op__fn_unit$next[11:0]$5902 - assign { } { } - assign { } { } - assign $0\logical_op__input_carry$next[1:0]$5887 $1\logical_op__input_carry$next[1:0]$5905 - assign $0\logical_op__insn$next[31:0]$5888 $1\logical_op__insn$next[31:0]$5906 - assign $0\logical_op__insn_type$next[6:0]$5889 $1\logical_op__insn_type$next[6:0]$5907 - assign $0\logical_op__invert_in$next[0:0]$5890 $1\logical_op__invert_in$next[0:0]$5908 - assign $0\logical_op__invert_out$next[0:0]$5891 $1\logical_op__invert_out$next[0:0]$5909 - assign $0\logical_op__is_32bit$next[0:0]$5892 $1\logical_op__is_32bit$next[0:0]$5910 - assign $0\logical_op__is_signed$next[0:0]$5893 $1\logical_op__is_signed$next[0:0]$5911 - assign { } { } - assign { } { } - assign $0\logical_op__output_carry$next[0:0]$5896 $1\logical_op__output_carry$next[0:0]$5914 - assign { } { } - assign { } { } - assign $0\logical_op__write_cr0$next[0:0]$5899 $1\logical_op__write_cr0$next[0:0]$5917 - assign $0\logical_op__zero_a$next[0:0]$5900 $1\logical_op__zero_a$next[0:0]$5918 - assign $0\logical_op__imm_data__data$next[63:0]$5885 $2\logical_op__imm_data__data$next[63:0]$5919 - assign $0\logical_op__imm_data__ok$next[0:0]$5886 $2\logical_op__imm_data__ok$next[0:0]$5920 - assign $0\logical_op__oe__oe$next[0:0]$5894 $2\logical_op__oe__oe$next[0:0]$5921 - assign $0\logical_op__oe__ok$next[0:0]$5895 $2\logical_op__oe__ok$next[0:0]$5922 - assign $0\logical_op__rc__ok$next[0:0]$5897 $2\logical_op__rc__ok$next[0:0]$5923 - assign $0\logical_op__rc__rc$next[0:0]$5898 $2\logical_op__rc__rc$next[0:0]$5924 - attribute \src "issuer_ls180.v:129446.5-129446.29" - switch \initial - attribute \src "issuer_ls180.v:129446.9-129446.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\logical_op__insn$next[31:0]$5906 $1\logical_op__data_len$next[3:0]$5901 $1\logical_op__is_signed$next[0:0]$5911 $1\logical_op__is_32bit$next[0:0]$5910 $1\logical_op__output_carry$next[0:0]$5914 $1\logical_op__write_cr0$next[0:0]$5917 $1\logical_op__invert_out$next[0:0]$5909 $1\logical_op__input_carry$next[1:0]$5905 $1\logical_op__zero_a$next[0:0]$5918 $1\logical_op__invert_in$next[0:0]$5908 $1\logical_op__oe__ok$next[0:0]$5913 $1\logical_op__oe__oe$next[0:0]$5912 $1\logical_op__rc__ok$next[0:0]$5915 $1\logical_op__rc__rc$next[0:0]$5916 $1\logical_op__imm_data__ok$next[0:0]$5904 $1\logical_op__imm_data__data$next[63:0]$5903 $1\logical_op__fn_unit$next[11:0]$5902 $1\logical_op__insn_type$next[6:0]$5907 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\logical_op__insn$next[31:0]$5906 $1\logical_op__data_len$next[3:0]$5901 $1\logical_op__is_signed$next[0:0]$5911 $1\logical_op__is_32bit$next[0:0]$5910 $1\logical_op__output_carry$next[0:0]$5914 $1\logical_op__write_cr0$next[0:0]$5917 $1\logical_op__invert_out$next[0:0]$5909 $1\logical_op__input_carry$next[1:0]$5905 $1\logical_op__zero_a$next[0:0]$5918 $1\logical_op__invert_in$next[0:0]$5908 $1\logical_op__oe__ok$next[0:0]$5913 $1\logical_op__oe__oe$next[0:0]$5912 $1\logical_op__rc__ok$next[0:0]$5915 $1\logical_op__rc__rc$next[0:0]$5916 $1\logical_op__imm_data__ok$next[0:0]$5904 $1\logical_op__imm_data__data$next[63:0]$5903 $1\logical_op__fn_unit$next[11:0]$5902 $1\logical_op__insn_type$next[6:0]$5907 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } - case - assign $1\logical_op__data_len$next[3:0]$5901 \logical_op__data_len - assign $1\logical_op__fn_unit$next[11:0]$5902 \logical_op__fn_unit - assign $1\logical_op__imm_data__data$next[63:0]$5903 \logical_op__imm_data__data - assign $1\logical_op__imm_data__ok$next[0:0]$5904 \logical_op__imm_data__ok - assign $1\logical_op__input_carry$next[1:0]$5905 \logical_op__input_carry - assign $1\logical_op__insn$next[31:0]$5906 \logical_op__insn - assign $1\logical_op__insn_type$next[6:0]$5907 \logical_op__insn_type - assign $1\logical_op__invert_in$next[0:0]$5908 \logical_op__invert_in - assign $1\logical_op__invert_out$next[0:0]$5909 \logical_op__invert_out - assign $1\logical_op__is_32bit$next[0:0]$5910 \logical_op__is_32bit - assign $1\logical_op__is_signed$next[0:0]$5911 \logical_op__is_signed - assign $1\logical_op__oe__oe$next[0:0]$5912 \logical_op__oe__oe - assign $1\logical_op__oe__ok$next[0:0]$5913 \logical_op__oe__ok - assign $1\logical_op__output_carry$next[0:0]$5914 \logical_op__output_carry - assign $1\logical_op__rc__ok$next[0:0]$5915 \logical_op__rc__ok - assign $1\logical_op__rc__rc$next[0:0]$5916 \logical_op__rc__rc - assign $1\logical_op__write_cr0$next[0:0]$5917 \logical_op__write_cr0 - assign $1\logical_op__zero_a$next[0:0]$5918 \logical_op__zero_a - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\logical_op__imm_data__data$next[63:0]$5919 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$next[0:0]$5920 1'0 - assign $2\logical_op__rc__rc$next[0:0]$5924 1'0 - assign $2\logical_op__rc__ok$next[0:0]$5923 1'0 - assign $2\logical_op__oe__oe$next[0:0]$5921 1'0 - assign $2\logical_op__oe__ok$next[0:0]$5922 1'0 - case - assign $2\logical_op__imm_data__data$next[63:0]$5919 $1\logical_op__imm_data__data$next[63:0]$5903 - assign $2\logical_op__imm_data__ok$next[0:0]$5920 $1\logical_op__imm_data__ok$next[0:0]$5904 - assign $2\logical_op__oe__oe$next[0:0]$5921 $1\logical_op__oe__oe$next[0:0]$5912 - assign $2\logical_op__oe__ok$next[0:0]$5922 $1\logical_op__oe__ok$next[0:0]$5913 - assign $2\logical_op__rc__ok$next[0:0]$5923 $1\logical_op__rc__ok$next[0:0]$5915 - assign $2\logical_op__rc__rc$next[0:0]$5924 $1\logical_op__rc__rc$next[0:0]$5916 - end - sync always - update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$5883 - update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[11:0]$5884 - update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$5885 - update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$5886 - update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$5887 - update \logical_op__insn$next $0\logical_op__insn$next[31:0]$5888 - update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$5889 - update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$5890 - update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$5891 - update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$5892 - update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$5893 - update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$5894 - update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$5895 - update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$5896 - update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$5897 - update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$5898 - update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$5899 - update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$5900 - end - attribute \src "issuer_ls180.v:129487.3-129505.6" - process $proc$issuer_ls180.v:129487$5925 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$next[63:0]$5926 $1\o$next[63:0]$5928 - assign { } { } - assign $0\o_ok$next[0:0]$5927 $2\o_ok$next[0:0]$5930 - attribute \src "issuer_ls180.v:129488.5-129488.29" - switch \initial - attribute \src "issuer_ls180.v:129488.9-129488.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$5929 $1\o$next[63:0]$5928 } { \o_ok$86 \o$85 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$5929 $1\o$next[63:0]$5928 } { \o_ok$86 \o$85 } - case - assign $1\o$next[63:0]$5928 \o - assign $1\o_ok$next[0:0]$5929 \o_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o_ok$next[0:0]$5930 1'0 - case - assign $2\o_ok$next[0:0]$5930 $1\o_ok$next[0:0]$5929 - end - sync always - update \o$next $0\o$next[63:0]$5926 - update \o_ok$next $0\o_ok$next[0:0]$5927 - end - attribute \src "issuer_ls180.v:129506.3-129524.6" - process $proc$issuer_ls180.v:129506$5931 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$next[3:0]$5932 $1\cr_a$next[3:0]$5934 - assign { } { } - assign $0\cr_a_ok$next[0:0]$5933 $2\cr_a_ok$next[0:0]$5936 - attribute \src "issuer_ls180.v:129507.5-129507.29" - switch \initial - attribute \src "issuer_ls180.v:129507.9-129507.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$5935 $1\cr_a$next[3:0]$5934 } { \cr_a_ok$88 \cr_a$87 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$5935 $1\cr_a$next[3:0]$5934 } { \cr_a_ok$88 \cr_a$87 } - case - assign $1\cr_a$next[3:0]$5934 \cr_a - assign $1\cr_a_ok$next[0:0]$5935 \cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_a_ok$next[0:0]$5936 1'0 - case - assign $2\cr_a_ok$next[0:0]$5936 $1\cr_a_ok$next[0:0]$5935 - end - sync always - update \cr_a$next $0\cr_a$next[3:0]$5932 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$5933 - end - attribute \src "issuer_ls180.v:129525.3-129543.6" - process $proc$issuer_ls180.v:129525$5937 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_so$next[0:0]$5938 $1\xer_so$next[0:0]$5940 - assign { } { } - assign $0\xer_so_ok$next[0:0]$5939 $2\xer_so_ok$next[0:0]$5942 - attribute \src "issuer_ls180.v:129526.5-129526.29" - switch \initial - attribute \src "issuer_ls180.v:129526.9-129526.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_so_ok$next[0:0]$5941 $1\xer_so$next[0:0]$5940 } { \xer_so_ok$92 \xer_so$91 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_so_ok$next[0:0]$5941 $1\xer_so$next[0:0]$5940 } { \xer_so_ok$92 \xer_so$91 } - case - assign $1\xer_so$next[0:0]$5940 \xer_so - assign $1\xer_so_ok$next[0:0]$5941 \xer_so_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_so_ok$next[0:0]$5942 1'0 - case - assign $2\xer_so_ok$next[0:0]$5942 $1\xer_so_ok$next[0:0]$5941 - end - sync always - update \xer_so$next $0\xer_so$next[0:0]$5938 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$5939 - end - connect \$64 $and$issuer_ls180.v:129261$5848_Y - connect \cr_a$89 4'0000 - connect \cr_a_ok$90 1'0 - connect \xer_so_ok$93 1'0 - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \xer_so_ok$92 \xer_so$91 } { 1'0 \main_xer_so$62 } - connect { \cr_a_ok$88 \cr_a$87 } 5'00000 - connect { \o_ok$86 \o$85 } { \main_o_ok \main_o } - connect { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } { \main_logical_op__insn$61 \main_logical_op__data_len$60 \main_logical_op__is_signed$59 \main_logical_op__is_32bit$58 \main_logical_op__output_carry$57 \main_logical_op__write_cr0$56 \main_logical_op__invert_out$55 \main_logical_op__input_carry$54 \main_logical_op__zero_a$53 \main_logical_op__invert_in$52 \main_logical_op__oe__ok$51 \main_logical_op__oe__oe$50 \main_logical_op__rc__ok$49 \main_logical_op__rc__rc$48 \main_logical_op__imm_data__ok$47 \main_logical_op__imm_data__data$46 \main_logical_op__fn_unit$45 \main_logical_op__insn_type$44 } - connect \muxid$66 \main_muxid$43 - connect \p_valid_i_p_ready_o \$64 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$63 \p_valid_i - connect \main_xer_so \input_xer_so$42 - connect \main_rb \input_rb$41 - connect \main_ra \input_ra$40 - connect { \main_logical_op__insn \main_logical_op__data_len \main_logical_op__is_signed \main_logical_op__is_32bit \main_logical_op__output_carry \main_logical_op__write_cr0 \main_logical_op__invert_out \main_logical_op__input_carry \main_logical_op__zero_a \main_logical_op__invert_in \main_logical_op__oe__ok \main_logical_op__oe__oe \main_logical_op__rc__ok \main_logical_op__rc__rc \main_logical_op__imm_data__ok \main_logical_op__imm_data__data \main_logical_op__fn_unit \main_logical_op__insn_type } { \input_logical_op__insn$39 \input_logical_op__data_len$38 \input_logical_op__is_signed$37 \input_logical_op__is_32bit$36 \input_logical_op__output_carry$35 \input_logical_op__write_cr0$34 \input_logical_op__invert_out$33 \input_logical_op__input_carry$32 \input_logical_op__zero_a$31 \input_logical_op__invert_in$30 \input_logical_op__oe__ok$29 \input_logical_op__oe__oe$28 \input_logical_op__rc__ok$27 \input_logical_op__rc__rc$26 \input_logical_op__imm_data__ok$25 \input_logical_op__imm_data__data$24 \input_logical_op__fn_unit$23 \input_logical_op__insn_type$22 } - connect \main_muxid \input_muxid$21 - connect \input_xer_so \xer_so$20 - connect \input_rb \rb - connect \input_ra \ra - connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } - connect \input_muxid \muxid$1 -end -attribute \src "issuer_ls180.v:129571.1-130589.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe2" -attribute \generator "nMigen" -module \logical_pipe2 - attribute \src "issuer_ls180.v:130556.3-130574.6" - wire width 4 $0\cr_a$22$next[3:0]$6075 - attribute \src "issuer_ls180.v:130360.3-130361.33" - wire width 4 $0\cr_a$22[3:0]$5972 - attribute \src "issuer_ls180.v:129583.13-129583.29" - wire width 4 $0\cr_a$22[3:0]$6082 - attribute \src "issuer_ls180.v:130556.3-130574.6" - wire $0\cr_a_ok$23$next[0:0]$6076 - attribute \src "issuer_ls180.v:130362.3-130363.39" - wire $0\cr_a_ok$23[0:0]$5974 - attribute \src "issuer_ls180.v:129592.7-129592.26" - wire $0\cr_a_ok$23[0:0]$6084 - attribute \src "issuer_ls180.v:129572.7-129572.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire width 4 $0\logical_op__data_len$18$next[3:0]$6026 - attribute \src "issuer_ls180.v:130400.3-130401.65" - wire width 4 $0\logical_op__data_len$18[3:0]$6012 - attribute \src "issuer_ls180.v:129603.13-129603.45" - wire width 4 $0\logical_op__data_len$18[3:0]$6086 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire width 12 $0\logical_op__fn_unit$3$next[11:0]$6027 - attribute \src "issuer_ls180.v:130370.3-130371.61" - wire width 12 $0\logical_op__fn_unit$3[11:0]$5982 - attribute \src "issuer_ls180.v:129638.14-129638.47" - wire width 12 $0\logical_op__fn_unit$3[11:0]$6088 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$6028 - attribute \src "issuer_ls180.v:130372.3-130373.75" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$5984 - attribute \src "issuer_ls180.v:129660.14-129660.67" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$6090 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $0\logical_op__imm_data__ok$5$next[0:0]$6029 - attribute \src "issuer_ls180.v:130374.3-130375.71" - wire $0\logical_op__imm_data__ok$5[0:0]$5986 - attribute \src "issuer_ls180.v:129669.7-129669.42" - wire $0\logical_op__imm_data__ok$5[0:0]$6092 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire width 2 $0\logical_op__input_carry$12$next[1:0]$6030 - attribute \src "issuer_ls180.v:130388.3-130389.71" - wire width 2 $0\logical_op__input_carry$12[1:0]$6000 - attribute \src "issuer_ls180.v:129686.13-129686.48" - wire width 2 $0\logical_op__input_carry$12[1:0]$6094 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire width 32 $0\logical_op__insn$19$next[31:0]$6031 - attribute \src "issuer_ls180.v:130402.3-130403.57" - wire width 32 $0\logical_op__insn$19[31:0]$6014 - attribute \src "issuer_ls180.v:129699.14-129699.43" - wire width 32 $0\logical_op__insn$19[31:0]$6096 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire width 7 $0\logical_op__insn_type$2$next[6:0]$6032 - attribute \src "issuer_ls180.v:130368.3-130369.65" - wire width 7 $0\logical_op__insn_type$2[6:0]$5980 - attribute \src "issuer_ls180.v:129856.13-129856.46" - wire width 7 $0\logical_op__insn_type$2[6:0]$6098 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $0\logical_op__invert_in$10$next[0:0]$6033 - attribute \src "issuer_ls180.v:130384.3-130385.67" - wire $0\logical_op__invert_in$10[0:0]$5996 - attribute \src "issuer_ls180.v:129939.7-129939.40" - wire $0\logical_op__invert_in$10[0:0]$6100 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $0\logical_op__invert_out$13$next[0:0]$6034 - attribute \src "issuer_ls180.v:130390.3-130391.69" - wire $0\logical_op__invert_out$13[0:0]$6002 - attribute \src "issuer_ls180.v:129948.7-129948.41" - wire $0\logical_op__invert_out$13[0:0]$6102 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $0\logical_op__is_32bit$16$next[0:0]$6035 - attribute \src "issuer_ls180.v:130396.3-130397.65" - wire $0\logical_op__is_32bit$16[0:0]$6008 - attribute \src "issuer_ls180.v:129957.7-129957.39" - wire $0\logical_op__is_32bit$16[0:0]$6104 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $0\logical_op__is_signed$17$next[0:0]$6036 - attribute \src "issuer_ls180.v:130398.3-130399.67" - wire $0\logical_op__is_signed$17[0:0]$6010 - attribute \src "issuer_ls180.v:129966.7-129966.40" - wire $0\logical_op__is_signed$17[0:0]$6106 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $0\logical_op__oe__oe$8$next[0:0]$6037 - attribute \src "issuer_ls180.v:130380.3-130381.59" - wire $0\logical_op__oe__oe$8[0:0]$5992 - attribute \src "issuer_ls180.v:129977.7-129977.36" - wire $0\logical_op__oe__oe$8[0:0]$6108 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $0\logical_op__oe__ok$9$next[0:0]$6038 - attribute \src "issuer_ls180.v:130382.3-130383.59" - wire $0\logical_op__oe__ok$9[0:0]$5994 - attribute \src "issuer_ls180.v:129986.7-129986.36" - wire $0\logical_op__oe__ok$9[0:0]$6110 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $0\logical_op__output_carry$15$next[0:0]$6039 - attribute \src "issuer_ls180.v:130394.3-130395.73" - wire $0\logical_op__output_carry$15[0:0]$6006 - attribute \src "issuer_ls180.v:129993.7-129993.43" - wire $0\logical_op__output_carry$15[0:0]$6112 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $0\logical_op__rc__ok$7$next[0:0]$6040 - attribute \src "issuer_ls180.v:130378.3-130379.59" - wire $0\logical_op__rc__ok$7[0:0]$5990 - attribute \src "issuer_ls180.v:130004.7-130004.36" - wire $0\logical_op__rc__ok$7[0:0]$6114 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $0\logical_op__rc__rc$6$next[0:0]$6041 - attribute \src "issuer_ls180.v:130376.3-130377.59" - wire $0\logical_op__rc__rc$6[0:0]$5988 - attribute \src "issuer_ls180.v:130013.7-130013.36" - wire $0\logical_op__rc__rc$6[0:0]$6116 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $0\logical_op__write_cr0$14$next[0:0]$6042 - attribute \src "issuer_ls180.v:130392.3-130393.67" - wire $0\logical_op__write_cr0$14[0:0]$6004 - attribute \src "issuer_ls180.v:130020.7-130020.40" - wire $0\logical_op__write_cr0$14[0:0]$6118 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $0\logical_op__zero_a$11$next[0:0]$6043 - attribute \src "issuer_ls180.v:130386.3-130387.61" - wire $0\logical_op__zero_a$11[0:0]$5998 - attribute \src "issuer_ls180.v:130029.7-130029.37" - wire $0\logical_op__zero_a$11[0:0]$6120 - attribute \src "issuer_ls180.v:130482.3-130494.6" - wire width 2 $0\muxid$1$next[1:0]$6023 - attribute \src "issuer_ls180.v:130404.3-130405.33" - wire width 2 $0\muxid$1[1:0]$6016 - attribute \src "issuer_ls180.v:130038.13-130038.29" - wire width 2 $0\muxid$1[1:0]$6122 - attribute \src "issuer_ls180.v:130537.3-130555.6" - wire width 64 $0\o$20$next[63:0]$6069 - attribute \src "issuer_ls180.v:130364.3-130365.27" - wire width 64 $0\o$20[63:0]$5976 - attribute \src "issuer_ls180.v:130053.14-130053.43" - wire width 64 $0\o$20[63:0]$6124 - attribute \src "issuer_ls180.v:130537.3-130555.6" - wire $0\o_ok$21$next[0:0]$6070 - attribute \src "issuer_ls180.v:130366.3-130367.33" - wire $0\o_ok$21[0:0]$5978 - attribute \src "issuer_ls180.v:130062.7-130062.23" - wire $0\o_ok$21[0:0]$6126 - attribute \src "issuer_ls180.v:130464.3-130481.6" - wire $0\r_busy$next[0:0]$6019 - attribute \src "issuer_ls180.v:130406.3-130407.29" - wire $0\r_busy[0:0] - attribute \src "issuer_ls180.v:130556.3-130574.6" - wire width 4 $1\cr_a$22$next[3:0]$6077 - attribute \src "issuer_ls180.v:130556.3-130574.6" - wire $1\cr_a_ok$23$next[0:0]$6078 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire width 4 $1\logical_op__data_len$18$next[3:0]$6044 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire width 12 $1\logical_op__fn_unit$3$next[11:0]$6045 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$6046 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $1\logical_op__imm_data__ok$5$next[0:0]$6047 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire width 2 $1\logical_op__input_carry$12$next[1:0]$6048 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire width 32 $1\logical_op__insn$19$next[31:0]$6049 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire width 7 $1\logical_op__insn_type$2$next[6:0]$6050 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $1\logical_op__invert_in$10$next[0:0]$6051 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $1\logical_op__invert_out$13$next[0:0]$6052 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $1\logical_op__is_32bit$16$next[0:0]$6053 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $1\logical_op__is_signed$17$next[0:0]$6054 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $1\logical_op__oe__oe$8$next[0:0]$6055 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $1\logical_op__oe__ok$9$next[0:0]$6056 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $1\logical_op__output_carry$15$next[0:0]$6057 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $1\logical_op__rc__ok$7$next[0:0]$6058 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $1\logical_op__rc__rc$6$next[0:0]$6059 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $1\logical_op__write_cr0$14$next[0:0]$6060 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $1\logical_op__zero_a$11$next[0:0]$6061 - attribute \src "issuer_ls180.v:130482.3-130494.6" - wire width 2 $1\muxid$1$next[1:0]$6024 - attribute \src "issuer_ls180.v:130537.3-130555.6" - wire width 64 $1\o$20$next[63:0]$6071 - attribute \src "issuer_ls180.v:130537.3-130555.6" - wire $1\o_ok$21$next[0:0]$6072 - attribute \src "issuer_ls180.v:130464.3-130481.6" - wire $1\r_busy$next[0:0]$6020 - attribute \src "issuer_ls180.v:130350.7-130350.20" - wire $1\r_busy[0:0] - attribute \src "issuer_ls180.v:130556.3-130574.6" - wire $2\cr_a_ok$23$next[0:0]$6079 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$6062 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $2\logical_op__imm_data__ok$5$next[0:0]$6063 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $2\logical_op__oe__oe$8$next[0:0]$6064 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $2\logical_op__oe__ok$9$next[0:0]$6065 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $2\logical_op__rc__ok$7$next[0:0]$6066 - attribute \src "issuer_ls180.v:130495.3-130536.6" - wire $2\logical_op__rc__rc$6$next[0:0]$6067 - attribute \src "issuer_ls180.v:130537.3-130555.6" - wire $2\o_ok$21$next[0:0]$6073 - attribute \src "issuer_ls180.v:130464.3-130481.6" - wire $2\r_busy$next[0:0]$6021 - attribute \src "issuer_ls180.v:130359.18-130359.118" - wire $and$issuer_ls180.v:130359$5970_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 54 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 input 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 52 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 26 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 53 \cr_a_ok$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$73 - attribute \src "issuer_ls180.v:129572.7-129572.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 48 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$68 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 33 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$3$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 34 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \logical_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$55 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 42 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$12$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 49 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$69 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 32 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$2$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 43 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 46 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 47 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 45 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 44 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 41 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$61 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 31 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 30 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 29 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 23 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 50 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 24 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 51 \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$21$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_logical_op__data_len$41 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_logical_op__fn_unit$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_logical_op__imm_data__data$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__imm_data__ok$28 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_logical_op__input_carry$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_logical_op__insn$42 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_logical_op__insn_type$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__invert_in$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__invert_out$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__is_32bit$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__is_signed$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__oe__oe$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__oe__ok$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__output_carry$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__ok$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__rc$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__write_cr0$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__zero_a$34 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_o$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_o_ok$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$48 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 27 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 28 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$47 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$issuer_ls180.v:130359$5970 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$48 - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:130359$5970_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:130408.10-130411.4" - cell \n$50 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:130412.15-130459.4" - cell \output$51 \output - connect \cr_a \output_cr_a - connect \cr_a$22 \output_cr_a$45 - connect \cr_a_ok \output_cr_a_ok - connect \logical_op__data_len \output_logical_op__data_len - connect \logical_op__data_len$18 \output_logical_op__data_len$41 - connect \logical_op__fn_unit \output_logical_op__fn_unit - connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$26 - connect \logical_op__imm_data__data \output_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \output_logical_op__imm_data__data$27 - connect \logical_op__imm_data__ok \output_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \output_logical_op__imm_data__ok$28 - connect \logical_op__input_carry \output_logical_op__input_carry - connect \logical_op__input_carry$12 \output_logical_op__input_carry$35 - connect \logical_op__insn \output_logical_op__insn - connect \logical_op__insn$19 \output_logical_op__insn$42 - connect \logical_op__insn_type \output_logical_op__insn_type - connect \logical_op__insn_type$2 \output_logical_op__insn_type$25 - connect \logical_op__invert_in \output_logical_op__invert_in - connect \logical_op__invert_in$10 \output_logical_op__invert_in$33 - connect \logical_op__invert_out \output_logical_op__invert_out - connect \logical_op__invert_out$13 \output_logical_op__invert_out$36 - connect \logical_op__is_32bit \output_logical_op__is_32bit - connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$39 - connect \logical_op__is_signed \output_logical_op__is_signed - connect \logical_op__is_signed$17 \output_logical_op__is_signed$40 - connect \logical_op__oe__oe \output_logical_op__oe__oe - connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$31 - connect \logical_op__oe__ok \output_logical_op__oe__ok - connect \logical_op__oe__ok$9 \output_logical_op__oe__ok$32 - connect \logical_op__output_carry \output_logical_op__output_carry - connect \logical_op__output_carry$15 \output_logical_op__output_carry$38 - connect \logical_op__rc__ok \output_logical_op__rc__ok - connect \logical_op__rc__ok$7 \output_logical_op__rc__ok$30 - connect \logical_op__rc__rc \output_logical_op__rc__rc - connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$29 - connect \logical_op__write_cr0 \output_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$37 - connect \logical_op__zero_a \output_logical_op__zero_a - connect \logical_op__zero_a$11 \output_logical_op__zero_a$34 - connect \muxid \output_muxid - connect \muxid$1 \output_muxid$24 - connect \o \output_o - connect \o$20 \output_o$43 - connect \o_ok \output_o_ok - connect \o_ok$21 \output_o_ok$44 - connect \xer_so \output_xer_so - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:130460.10-130463.4" - cell \p$49 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "issuer_ls180.v:129572.7-129572.20" - process $proc$issuer_ls180.v:129572$6080 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:129583.13-129583.29" - process $proc$issuer_ls180.v:129583$6081 - assign { } { } - assign $0\cr_a$22[3:0]$6082 4'0000 - sync always - sync init - update \cr_a$22 $0\cr_a$22[3:0]$6082 - end - attribute \src "issuer_ls180.v:129592.7-129592.26" - process $proc$issuer_ls180.v:129592$6083 - assign { } { } - assign $0\cr_a_ok$23[0:0]$6084 1'0 - sync always - sync init - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6084 - end - attribute \src "issuer_ls180.v:129603.13-129603.45" - process $proc$issuer_ls180.v:129603$6085 - assign { } { } - assign $0\logical_op__data_len$18[3:0]$6086 4'0000 - sync always - sync init - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6086 - end - attribute \src "issuer_ls180.v:129638.14-129638.47" - process $proc$issuer_ls180.v:129638$6087 - assign { } { } - assign $0\logical_op__fn_unit$3[11:0]$6088 12'000000000000 - sync always - sync init - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$6088 - end - attribute \src "issuer_ls180.v:129660.14-129660.67" - process $proc$issuer_ls180.v:129660$6089 - assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$6090 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6090 - end - attribute \src "issuer_ls180.v:129669.7-129669.42" - process $proc$issuer_ls180.v:129669$6091 - assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$6092 1'0 - sync always - sync init - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6092 - end - attribute \src "issuer_ls180.v:129686.13-129686.48" - process $proc$issuer_ls180.v:129686$6093 - assign { } { } - assign $0\logical_op__input_carry$12[1:0]$6094 2'00 - sync always - sync init - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6094 - end - attribute \src "issuer_ls180.v:129699.14-129699.43" - process $proc$issuer_ls180.v:129699$6095 - assign { } { } - assign $0\logical_op__insn$19[31:0]$6096 0 - sync always - sync init - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6096 - end - attribute \src "issuer_ls180.v:129856.13-129856.46" - process $proc$issuer_ls180.v:129856$6097 - assign { } { } - assign $0\logical_op__insn_type$2[6:0]$6098 7'0000000 - sync always - sync init - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6098 - end - attribute \src "issuer_ls180.v:129939.7-129939.40" - process $proc$issuer_ls180.v:129939$6099 - assign { } { } - assign $0\logical_op__invert_in$10[0:0]$6100 1'0 - sync always - sync init - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6100 - end - attribute \src "issuer_ls180.v:129948.7-129948.41" - process $proc$issuer_ls180.v:129948$6101 - assign { } { } - assign $0\logical_op__invert_out$13[0:0]$6102 1'0 - sync always - sync init - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6102 - end - attribute \src "issuer_ls180.v:129957.7-129957.39" - process $proc$issuer_ls180.v:129957$6103 - assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$6104 1'0 - sync always - sync init - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6104 - end - attribute \src "issuer_ls180.v:129966.7-129966.40" - process $proc$issuer_ls180.v:129966$6105 - assign { } { } - assign $0\logical_op__is_signed$17[0:0]$6106 1'0 - sync always - sync init - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6106 - end - attribute \src "issuer_ls180.v:129977.7-129977.36" - process $proc$issuer_ls180.v:129977$6107 - assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$6108 1'0 - sync always - sync init - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6108 - end - attribute \src "issuer_ls180.v:129986.7-129986.36" - process $proc$issuer_ls180.v:129986$6109 - assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$6110 1'0 - sync always - sync init - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6110 - end - attribute \src "issuer_ls180.v:129993.7-129993.43" - process $proc$issuer_ls180.v:129993$6111 - assign { } { } - assign $0\logical_op__output_carry$15[0:0]$6112 1'0 - sync always - sync init - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6112 - end - attribute \src "issuer_ls180.v:130004.7-130004.36" - process $proc$issuer_ls180.v:130004$6113 - assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$6114 1'0 - sync always - sync init - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6114 - end - attribute \src "issuer_ls180.v:130013.7-130013.36" - process $proc$issuer_ls180.v:130013$6115 - assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$6116 1'0 - sync always - sync init - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6116 - end - attribute \src "issuer_ls180.v:130020.7-130020.40" - process $proc$issuer_ls180.v:130020$6117 - assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$6118 1'0 - sync always - sync init - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6118 - end - attribute \src "issuer_ls180.v:130029.7-130029.37" - process $proc$issuer_ls180.v:130029$6119 - assign { } { } - assign $0\logical_op__zero_a$11[0:0]$6120 1'0 - sync always - sync init - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6120 - end - attribute \src "issuer_ls180.v:130038.13-130038.29" - process $proc$issuer_ls180.v:130038$6121 - assign { } { } - assign $0\muxid$1[1:0]$6122 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$6122 - end - attribute \src "issuer_ls180.v:130053.14-130053.43" - process $proc$issuer_ls180.v:130053$6123 - assign { } { } - assign $0\o$20[63:0]$6124 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o$20 $0\o$20[63:0]$6124 - end - attribute \src "issuer_ls180.v:130062.7-130062.23" - process $proc$issuer_ls180.v:130062$6125 - assign { } { } - assign $0\o_ok$21[0:0]$6126 1'0 - sync always - sync init - update \o_ok$21 $0\o_ok$21[0:0]$6126 - end - attribute \src "issuer_ls180.v:130350.7-130350.20" - process $proc$issuer_ls180.v:130350$6127 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "issuer_ls180.v:130360.3-130361.33" - process $proc$issuer_ls180.v:130360$5971 - assign { } { } - assign $0\cr_a$22[3:0]$5972 \cr_a$22$next - sync posedge \coresync_clk - update \cr_a$22 $0\cr_a$22[3:0]$5972 - end - attribute \src "issuer_ls180.v:130362.3-130363.39" - process $proc$issuer_ls180.v:130362$5973 - assign { } { } - assign $0\cr_a_ok$23[0:0]$5974 \cr_a_ok$23$next - sync posedge \coresync_clk - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$5974 - end - attribute \src "issuer_ls180.v:130364.3-130365.27" - process $proc$issuer_ls180.v:130364$5975 - assign { } { } - assign $0\o$20[63:0]$5976 \o$20$next - sync posedge \coresync_clk - update \o$20 $0\o$20[63:0]$5976 - end - attribute \src "issuer_ls180.v:130366.3-130367.33" - process $proc$issuer_ls180.v:130366$5977 - assign { } { } - assign $0\o_ok$21[0:0]$5978 \o_ok$21$next - sync posedge \coresync_clk - update \o_ok$21 $0\o_ok$21[0:0]$5978 - end - attribute \src "issuer_ls180.v:130368.3-130369.65" - process $proc$issuer_ls180.v:130368$5979 - assign { } { } - assign $0\logical_op__insn_type$2[6:0]$5980 \logical_op__insn_type$2$next - sync posedge \coresync_clk - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$5980 - end - attribute \src "issuer_ls180.v:130370.3-130371.61" - process $proc$issuer_ls180.v:130370$5981 - assign { } { } - assign $0\logical_op__fn_unit$3[11:0]$5982 \logical_op__fn_unit$3$next - sync posedge \coresync_clk - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$5982 - end - attribute \src "issuer_ls180.v:130372.3-130373.75" - process $proc$issuer_ls180.v:130372$5983 - assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$5984 \logical_op__imm_data__data$4$next - sync posedge \coresync_clk - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$5984 - end - attribute \src "issuer_ls180.v:130374.3-130375.71" - process $proc$issuer_ls180.v:130374$5985 - assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$5986 \logical_op__imm_data__ok$5$next - sync posedge \coresync_clk - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$5986 - end - attribute \src "issuer_ls180.v:130376.3-130377.59" - process $proc$issuer_ls180.v:130376$5987 - assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$5988 \logical_op__rc__rc$6$next - sync posedge \coresync_clk - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$5988 - end - attribute \src "issuer_ls180.v:130378.3-130379.59" - process $proc$issuer_ls180.v:130378$5989 - assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$5990 \logical_op__rc__ok$7$next - sync posedge \coresync_clk - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$5990 - end - attribute \src "issuer_ls180.v:130380.3-130381.59" - process $proc$issuer_ls180.v:130380$5991 - assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$5992 \logical_op__oe__oe$8$next - sync posedge \coresync_clk - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$5992 - end - attribute \src "issuer_ls180.v:130382.3-130383.59" - process $proc$issuer_ls180.v:130382$5993 - assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$5994 \logical_op__oe__ok$9$next - sync posedge \coresync_clk - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$5994 - end - attribute \src "issuer_ls180.v:130384.3-130385.67" - process $proc$issuer_ls180.v:130384$5995 - assign { } { } - assign $0\logical_op__invert_in$10[0:0]$5996 \logical_op__invert_in$10$next - sync posedge \coresync_clk - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$5996 - end - attribute \src "issuer_ls180.v:130386.3-130387.61" - process $proc$issuer_ls180.v:130386$5997 - assign { } { } - assign $0\logical_op__zero_a$11[0:0]$5998 \logical_op__zero_a$11$next - sync posedge \coresync_clk - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$5998 - end - attribute \src "issuer_ls180.v:130388.3-130389.71" - process $proc$issuer_ls180.v:130388$5999 - assign { } { } - assign $0\logical_op__input_carry$12[1:0]$6000 \logical_op__input_carry$12$next - sync posedge \coresync_clk - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6000 - end - attribute \src "issuer_ls180.v:130390.3-130391.69" - process $proc$issuer_ls180.v:130390$6001 - assign { } { } - assign $0\logical_op__invert_out$13[0:0]$6002 \logical_op__invert_out$13$next - sync posedge \coresync_clk - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6002 - end - attribute \src "issuer_ls180.v:130392.3-130393.67" - process $proc$issuer_ls180.v:130392$6003 - assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$6004 \logical_op__write_cr0$14$next - sync posedge \coresync_clk - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6004 - end - attribute \src "issuer_ls180.v:130394.3-130395.73" - process $proc$issuer_ls180.v:130394$6005 - assign { } { } - assign $0\logical_op__output_carry$15[0:0]$6006 \logical_op__output_carry$15$next - sync posedge \coresync_clk - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6006 - end - attribute \src "issuer_ls180.v:130396.3-130397.65" - process $proc$issuer_ls180.v:130396$6007 - assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$6008 \logical_op__is_32bit$16$next - sync posedge \coresync_clk - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6008 - end - attribute \src "issuer_ls180.v:130398.3-130399.67" - process $proc$issuer_ls180.v:130398$6009 - assign { } { } - assign $0\logical_op__is_signed$17[0:0]$6010 \logical_op__is_signed$17$next - sync posedge \coresync_clk - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6010 - end - attribute \src "issuer_ls180.v:130400.3-130401.65" - process $proc$issuer_ls180.v:130400$6011 - assign { } { } - assign $0\logical_op__data_len$18[3:0]$6012 \logical_op__data_len$18$next - sync posedge \coresync_clk - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6012 - end - attribute \src "issuer_ls180.v:130402.3-130403.57" - process $proc$issuer_ls180.v:130402$6013 - assign { } { } - assign $0\logical_op__insn$19[31:0]$6014 \logical_op__insn$19$next - sync posedge \coresync_clk - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6014 - end - attribute \src "issuer_ls180.v:130404.3-130405.33" - process $proc$issuer_ls180.v:130404$6015 - assign { } { } - assign $0\muxid$1[1:0]$6016 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$6016 - end - attribute \src "issuer_ls180.v:130406.3-130407.29" - process $proc$issuer_ls180.v:130406$6017 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "issuer_ls180.v:130464.3-130481.6" - process $proc$issuer_ls180.v:130464$6018 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$6019 $2\r_busy$next[0:0]$6021 - attribute \src "issuer_ls180.v:130465.5-130465.29" - switch \initial - attribute \src "issuer_ls180.v:130465.9-130465.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$6020 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\r_busy$next[0:0]$6020 1'0 - case - assign $1\r_busy$next[0:0]$6020 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$6021 1'0 - case - assign $2\r_busy$next[0:0]$6021 $1\r_busy$next[0:0]$6020 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$6019 - end - attribute \src "issuer_ls180.v:130482.3-130494.6" - process $proc$issuer_ls180.v:130482$6022 - assign { } { } - assign { } { } - assign $0\muxid$1$next[1:0]$6023 $1\muxid$1$next[1:0]$6024 - attribute \src "issuer_ls180.v:130483.5-130483.29" - switch \initial - attribute \src "issuer_ls180.v:130483.9-130483.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$1$next[1:0]$6024 \muxid$51 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$1$next[1:0]$6024 \muxid$51 - case - assign $1\muxid$1$next[1:0]$6024 \muxid$1 - end - sync always - update \muxid$1$next $0\muxid$1$next[1:0]$6023 - end - attribute \src "issuer_ls180.v:130495.3-130536.6" - process $proc$issuer_ls180.v:130495$6025 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\logical_op__data_len$18$next[3:0]$6026 $1\logical_op__data_len$18$next[3:0]$6044 - assign $0\logical_op__fn_unit$3$next[11:0]$6027 $1\logical_op__fn_unit$3$next[11:0]$6045 - assign { } { } - assign { } { } - assign $0\logical_op__input_carry$12$next[1:0]$6030 $1\logical_op__input_carry$12$next[1:0]$6048 - assign $0\logical_op__insn$19$next[31:0]$6031 $1\logical_op__insn$19$next[31:0]$6049 - assign $0\logical_op__insn_type$2$next[6:0]$6032 $1\logical_op__insn_type$2$next[6:0]$6050 - assign $0\logical_op__invert_in$10$next[0:0]$6033 $1\logical_op__invert_in$10$next[0:0]$6051 - assign $0\logical_op__invert_out$13$next[0:0]$6034 $1\logical_op__invert_out$13$next[0:0]$6052 - assign $0\logical_op__is_32bit$16$next[0:0]$6035 $1\logical_op__is_32bit$16$next[0:0]$6053 - assign $0\logical_op__is_signed$17$next[0:0]$6036 $1\logical_op__is_signed$17$next[0:0]$6054 - assign { } { } - assign { } { } - assign $0\logical_op__output_carry$15$next[0:0]$6039 $1\logical_op__output_carry$15$next[0:0]$6057 - assign { } { } - assign { } { } - assign $0\logical_op__write_cr0$14$next[0:0]$6042 $1\logical_op__write_cr0$14$next[0:0]$6060 - assign $0\logical_op__zero_a$11$next[0:0]$6043 $1\logical_op__zero_a$11$next[0:0]$6061 - assign $0\logical_op__imm_data__data$4$next[63:0]$6028 $2\logical_op__imm_data__data$4$next[63:0]$6062 - assign $0\logical_op__imm_data__ok$5$next[0:0]$6029 $2\logical_op__imm_data__ok$5$next[0:0]$6063 - assign $0\logical_op__oe__oe$8$next[0:0]$6037 $2\logical_op__oe__oe$8$next[0:0]$6064 - assign $0\logical_op__oe__ok$9$next[0:0]$6038 $2\logical_op__oe__ok$9$next[0:0]$6065 - assign $0\logical_op__rc__ok$7$next[0:0]$6040 $2\logical_op__rc__ok$7$next[0:0]$6066 - assign $0\logical_op__rc__rc$6$next[0:0]$6041 $2\logical_op__rc__rc$6$next[0:0]$6067 - attribute \src "issuer_ls180.v:130496.5-130496.29" - switch \initial - attribute \src "issuer_ls180.v:130496.9-130496.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$6049 $1\logical_op__data_len$18$next[3:0]$6044 $1\logical_op__is_signed$17$next[0:0]$6054 $1\logical_op__is_32bit$16$next[0:0]$6053 $1\logical_op__output_carry$15$next[0:0]$6057 $1\logical_op__write_cr0$14$next[0:0]$6060 $1\logical_op__invert_out$13$next[0:0]$6052 $1\logical_op__input_carry$12$next[1:0]$6048 $1\logical_op__zero_a$11$next[0:0]$6061 $1\logical_op__invert_in$10$next[0:0]$6051 $1\logical_op__oe__ok$9$next[0:0]$6056 $1\logical_op__oe__oe$8$next[0:0]$6055 $1\logical_op__rc__ok$7$next[0:0]$6058 $1\logical_op__rc__rc$6$next[0:0]$6059 $1\logical_op__imm_data__ok$5$next[0:0]$6047 $1\logical_op__imm_data__data$4$next[63:0]$6046 $1\logical_op__fn_unit$3$next[11:0]$6045 $1\logical_op__insn_type$2$next[6:0]$6050 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$6049 $1\logical_op__data_len$18$next[3:0]$6044 $1\logical_op__is_signed$17$next[0:0]$6054 $1\logical_op__is_32bit$16$next[0:0]$6053 $1\logical_op__output_carry$15$next[0:0]$6057 $1\logical_op__write_cr0$14$next[0:0]$6060 $1\logical_op__invert_out$13$next[0:0]$6052 $1\logical_op__input_carry$12$next[1:0]$6048 $1\logical_op__zero_a$11$next[0:0]$6061 $1\logical_op__invert_in$10$next[0:0]$6051 $1\logical_op__oe__ok$9$next[0:0]$6056 $1\logical_op__oe__oe$8$next[0:0]$6055 $1\logical_op__rc__ok$7$next[0:0]$6058 $1\logical_op__rc__rc$6$next[0:0]$6059 $1\logical_op__imm_data__ok$5$next[0:0]$6047 $1\logical_op__imm_data__data$4$next[63:0]$6046 $1\logical_op__fn_unit$3$next[11:0]$6045 $1\logical_op__insn_type$2$next[6:0]$6050 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } - case - assign $1\logical_op__data_len$18$next[3:0]$6044 \logical_op__data_len$18 - assign $1\logical_op__fn_unit$3$next[11:0]$6045 \logical_op__fn_unit$3 - assign $1\logical_op__imm_data__data$4$next[63:0]$6046 \logical_op__imm_data__data$4 - assign $1\logical_op__imm_data__ok$5$next[0:0]$6047 \logical_op__imm_data__ok$5 - assign $1\logical_op__input_carry$12$next[1:0]$6048 \logical_op__input_carry$12 - assign $1\logical_op__insn$19$next[31:0]$6049 \logical_op__insn$19 - assign $1\logical_op__insn_type$2$next[6:0]$6050 \logical_op__insn_type$2 - assign $1\logical_op__invert_in$10$next[0:0]$6051 \logical_op__invert_in$10 - assign $1\logical_op__invert_out$13$next[0:0]$6052 \logical_op__invert_out$13 - assign $1\logical_op__is_32bit$16$next[0:0]$6053 \logical_op__is_32bit$16 - assign $1\logical_op__is_signed$17$next[0:0]$6054 \logical_op__is_signed$17 - assign $1\logical_op__oe__oe$8$next[0:0]$6055 \logical_op__oe__oe$8 - assign $1\logical_op__oe__ok$9$next[0:0]$6056 \logical_op__oe__ok$9 - assign $1\logical_op__output_carry$15$next[0:0]$6057 \logical_op__output_carry$15 - assign $1\logical_op__rc__ok$7$next[0:0]$6058 \logical_op__rc__ok$7 - assign $1\logical_op__rc__rc$6$next[0:0]$6059 \logical_op__rc__rc$6 - assign $1\logical_op__write_cr0$14$next[0:0]$6060 \logical_op__write_cr0$14 - assign $1\logical_op__zero_a$11$next[0:0]$6061 \logical_op__zero_a$11 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\logical_op__imm_data__data$4$next[63:0]$6062 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$5$next[0:0]$6063 1'0 - assign $2\logical_op__rc__rc$6$next[0:0]$6067 1'0 - assign $2\logical_op__rc__ok$7$next[0:0]$6066 1'0 - assign $2\logical_op__oe__oe$8$next[0:0]$6064 1'0 - assign $2\logical_op__oe__ok$9$next[0:0]$6065 1'0 - case - assign $2\logical_op__imm_data__data$4$next[63:0]$6062 $1\logical_op__imm_data__data$4$next[63:0]$6046 - assign $2\logical_op__imm_data__ok$5$next[0:0]$6063 $1\logical_op__imm_data__ok$5$next[0:0]$6047 - assign $2\logical_op__oe__oe$8$next[0:0]$6064 $1\logical_op__oe__oe$8$next[0:0]$6055 - assign $2\logical_op__oe__ok$9$next[0:0]$6065 $1\logical_op__oe__ok$9$next[0:0]$6056 - assign $2\logical_op__rc__ok$7$next[0:0]$6066 $1\logical_op__rc__ok$7$next[0:0]$6058 - assign $2\logical_op__rc__rc$6$next[0:0]$6067 $1\logical_op__rc__rc$6$next[0:0]$6059 - end - sync always - update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$6026 - update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[11:0]$6027 - update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$6028 - update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$6029 - update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$6030 - update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$6031 - update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$6032 - update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$6033 - update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$6034 - update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$6035 - update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$6036 - update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$6037 - update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$6038 - update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$6039 - update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$6040 - update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$6041 - update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$6042 - update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$6043 - end - attribute \src "issuer_ls180.v:130537.3-130555.6" - process $proc$issuer_ls180.v:130537$6068 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$20$next[63:0]$6069 $1\o$20$next[63:0]$6071 - assign { } { } - assign $0\o_ok$21$next[0:0]$6070 $2\o_ok$21$next[0:0]$6073 - attribute \src "issuer_ls180.v:130538.5-130538.29" - switch \initial - attribute \src "issuer_ls180.v:130538.9-130538.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$21$next[0:0]$6072 $1\o$20$next[63:0]$6071 } { \o_ok$71 \o$70 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\o_ok$21$next[0:0]$6072 $1\o$20$next[63:0]$6071 } { \o_ok$71 \o$70 } - case - assign $1\o$20$next[63:0]$6071 \o$20 - assign $1\o_ok$21$next[0:0]$6072 \o_ok$21 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o_ok$21$next[0:0]$6073 1'0 - case - assign $2\o_ok$21$next[0:0]$6073 $1\o_ok$21$next[0:0]$6072 - end - sync always - update \o$20$next $0\o$20$next[63:0]$6069 - update \o_ok$21$next $0\o_ok$21$next[0:0]$6070 - end - attribute \src "issuer_ls180.v:130556.3-130574.6" - process $proc$issuer_ls180.v:130556$6074 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$22$next[3:0]$6075 $1\cr_a$22$next[3:0]$6077 - assign { } { } - assign $0\cr_a_ok$23$next[0:0]$6076 $2\cr_a_ok$23$next[0:0]$6079 - attribute \src "issuer_ls180.v:130557.5-130557.29" - switch \initial - attribute \src "issuer_ls180.v:130557.9-130557.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$6078 $1\cr_a$22$next[3:0]$6077 } { \cr_a_ok$73 \cr_a$72 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$6078 $1\cr_a$22$next[3:0]$6077 } { \cr_a_ok$73 \cr_a$72 } - case - assign $1\cr_a$22$next[3:0]$6077 \cr_a$22 - assign $1\cr_a_ok$23$next[0:0]$6078 \cr_a_ok$23 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_a_ok$23$next[0:0]$6079 1'0 - case - assign $2\cr_a_ok$23$next[0:0]$6079 $1\cr_a_ok$23$next[0:0]$6078 - end - sync always - update \cr_a$22$next $0\cr_a$22$next[3:0]$6075 - update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$6076 - end - connect \$49 $and$issuer_ls180.v:130359$5970_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \cr_a_ok$73 \cr_a$72 } { \output_cr_a_ok \output_cr_a$45 } - connect { \o_ok$71 \o$70 } { \output_o_ok$44 \output_o$43 } - connect { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } { \output_logical_op__insn$42 \output_logical_op__data_len$41 \output_logical_op__is_signed$40 \output_logical_op__is_32bit$39 \output_logical_op__output_carry$38 \output_logical_op__write_cr0$37 \output_logical_op__invert_out$36 \output_logical_op__input_carry$35 \output_logical_op__zero_a$34 \output_logical_op__invert_in$33 \output_logical_op__oe__ok$32 \output_logical_op__oe__oe$31 \output_logical_op__rc__ok$30 \output_logical_op__rc__rc$29 \output_logical_op__imm_data__ok$28 \output_logical_op__imm_data__data$27 \output_logical_op__fn_unit$26 \output_logical_op__insn_type$25 } - connect \muxid$51 \output_muxid$24 - connect \p_valid_i_p_ready_o \$49 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$48 \p_valid_i - connect { \xer_so_ok$47 \output_xer_so } { \xer_so_ok \xer_so } - connect { \cr_a_ok$46 \output_cr_a } { \cr_a_ok \cr_a } - connect { \output_o_ok \output_o } { \o_ok \o } - connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - connect \output_muxid \muxid -end -attribute \src "ls180.v:4.1-9629.10" -attribute \cells_not_processed 1 -module \ls180 - attribute \src "ls180.v:9368.1-9378.4" - wire width 7 $0$memwr$\mem$ls180.v:9370$1_ADDR[6:0]$2460 - attribute \src "ls180.v:9368.1-9378.4" - wire width 32 $0$memwr$\mem$ls180.v:9370$1_DATA[31:0]$2461 - attribute \src "ls180.v:9368.1-9378.4" - wire width 32 $0$memwr$\mem$ls180.v:9370$1_EN[31:0]$2462 - attribute \src "ls180.v:9368.1-9378.4" - wire width 7 $0$memwr$\mem$ls180.v:9372$2_ADDR[6:0]$2463 - attribute \src "ls180.v:9368.1-9378.4" - wire width 32 $0$memwr$\mem$ls180.v:9372$2_DATA[31:0]$2464 - attribute \src "ls180.v:9368.1-9378.4" - wire width 32 $0$memwr$\mem$ls180.v:9372$2_EN[31:0]$2465 - attribute \src "ls180.v:9368.1-9378.4" - wire width 7 $0$memwr$\mem$ls180.v:9374$3_ADDR[6:0]$2466 - attribute \src "ls180.v:9368.1-9378.4" - wire width 32 $0$memwr$\mem$ls180.v:9374$3_DATA[31:0]$2467 - attribute \src "ls180.v:9368.1-9378.4" - wire width 32 $0$memwr$\mem$ls180.v:9374$3_EN[31:0]$2468 - attribute \src "ls180.v:9368.1-9378.4" - wire width 7 $0$memwr$\mem$ls180.v:9376$4_ADDR[6:0]$2469 - attribute \src "ls180.v:9368.1-9378.4" - wire width 32 $0$memwr$\mem$ls180.v:9376$4_DATA[31:0]$2470 - attribute \src "ls180.v:9368.1-9378.4" - wire width 32 $0$memwr$\mem$ls180.v:9376$4_EN[31:0]$2471 - attribute \src "ls180.v:9389.1-9393.4" - wire width 4 $0$memwr$\storage$ls180.v:9391$5_ADDR[3:0]$2474 - attribute \src "ls180.v:9389.1-9393.4" - wire width 10 $0$memwr$\storage$ls180.v:9391$5_DATA[9:0]$2475 - attribute \src "ls180.v:9389.1-9393.4" - wire width 10 $0$memwr$\storage$ls180.v:9391$5_EN[9:0]$2476 - attribute \src "ls180.v:9406.1-9410.4" - wire width 4 $0$memwr$\storage_1$ls180.v:9408$6_ADDR[3:0]$2481 - attribute \src "ls180.v:9406.1-9410.4" - wire width 10 $0$memwr$\storage_1$ls180.v:9408$6_DATA[9:0]$2482 - attribute \src "ls180.v:9406.1-9410.4" - wire width 10 $0$memwr$\storage_1$ls180.v:9408$6_EN[9:0]$2483 - attribute \src "ls180.v:9422.1-9426.4" - wire width 3 $0$memwr$\storage_2$ls180.v:9424$7_ADDR[2:0]$2488 - attribute \src "ls180.v:9422.1-9426.4" - wire width 25 $0$memwr$\storage_2$ls180.v:9424$7_DATA[24:0]$2489 - attribute \src "ls180.v:9422.1-9426.4" - wire width 25 $0$memwr$\storage_2$ls180.v:9424$7_EN[24:0]$2490 - attribute \src "ls180.v:9436.1-9440.4" - wire width 3 $0$memwr$\storage_3$ls180.v:9438$8_ADDR[2:0]$2495 - attribute \src "ls180.v:9436.1-9440.4" - wire width 25 $0$memwr$\storage_3$ls180.v:9438$8_DATA[24:0]$2496 - attribute \src "ls180.v:9436.1-9440.4" - wire width 25 $0$memwr$\storage_3$ls180.v:9438$8_EN[24:0]$2497 - attribute \src "ls180.v:9450.1-9454.4" - wire width 3 $0$memwr$\storage_4$ls180.v:9452$9_ADDR[2:0]$2502 - attribute \src "ls180.v:9450.1-9454.4" - wire width 25 $0$memwr$\storage_4$ls180.v:9452$9_DATA[24:0]$2503 - attribute \src "ls180.v:9450.1-9454.4" - wire width 25 $0$memwr$\storage_4$ls180.v:9452$9_EN[24:0]$2504 - attribute \src "ls180.v:9464.1-9468.4" - wire width 3 $0$memwr$\storage_5$ls180.v:9466$10_ADDR[2:0]$2509 - attribute \src "ls180.v:9464.1-9468.4" - wire width 25 $0$memwr$\storage_5$ls180.v:9466$10_DATA[24:0]$2510 - attribute \src "ls180.v:9464.1-9468.4" - wire width 25 $0$memwr$\storage_5$ls180.v:9466$10_EN[24:0]$2511 - attribute \src "ls180.v:9478.1-9482.4" - wire width 5 $0$memwr$\storage_6$ls180.v:9480$11_ADDR[4:0]$2516 - attribute \src "ls180.v:9478.1-9482.4" - wire width 10 $0$memwr$\storage_6$ls180.v:9480$11_DATA[9:0]$2517 - attribute \src "ls180.v:9478.1-9482.4" - wire width 10 $0$memwr$\storage_6$ls180.v:9480$11_EN[9:0]$2518 - attribute \src "ls180.v:9492.1-9496.4" - wire width 5 $0$memwr$\storage_7$ls180.v:9494$12_ADDR[4:0]$2523 - attribute \src "ls180.v:9492.1-9496.4" - wire width 10 $0$memwr$\storage_7$ls180.v:9494$12_DATA[9:0]$2524 - attribute \src "ls180.v:9492.1-9496.4" - wire width 10 $0$memwr$\storage_7$ls180.v:9494$12_EN[9:0]$2525 - attribute \src "ls180.v:3103.1-3196.4" - wire width 3 $0\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:3260.1-3353.4" - wire width 3 $0\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:3417.1-3510.4" - wire width 3 $0\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:3574.1-3667.4" - wire width 3 $0\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:6162.1-6178.4" - wire $0\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:6383.1-6399.4" - wire $0\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:6400.1-6416.4" - wire $0\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:6468.1-6475.4" - wire width 22 $0\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:6476.1-6483.4" - wire $0\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:6484.1-6491.4" - wire $0\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:6492.1-6499.4" - wire width 22 $0\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:6500.1-6507.4" - wire $0\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:6508.1-6515.4" - wire $0\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:6516.1-6523.4" - wire width 22 $0\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:6524.1-6531.4" - wire $0\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:6179.1-6195.4" - wire width 13 $0\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:6532.1-6539.4" - wire $0\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:6540.1-6547.4" - wire width 22 $0\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:6548.1-6555.4" - wire $0\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:6556.1-6563.4" - wire $0\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:6564.1-6580.4" - wire width 32 $0\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:6581.1-6597.4" - wire width 32 $0\builder_comb_rhs_array_muxed25[31:0] - attribute \src "ls180.v:6598.1-6614.4" - wire width 4 $0\builder_comb_rhs_array_muxed26[3:0] - attribute \src "ls180.v:6615.1-6631.4" - wire $0\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:6632.1-6648.4" - wire $0\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:6649.1-6665.4" - wire $0\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:6196.1-6212.4" - wire width 2 $0\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:6666.1-6682.4" - wire width 3 $0\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:6683.1-6699.4" - wire width 2 $0\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:6213.1-6229.4" - wire $0\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:6230.1-6246.4" - wire $0\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:6247.1-6263.4" - wire $0\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:6315.1-6331.4" - wire $0\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:6332.1-6348.4" - wire width 13 $0\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:6349.1-6365.4" - wire width 2 $0\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:6366.1-6382.4" - wire $0\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:6264.1-6280.4" - wire $0\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:6281.1-6297.4" - wire $0\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:6298.1-6314.4" - wire $0\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:6417.1-6433.4" - wire $0\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:6434.1-6450.4" - wire $0\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:6451.1-6467.4" - wire $0\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:2607.1-2653.4" - wire $0\builder_converter0_next_state[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\builder_converter0_state[0:0] - attribute \src "ls180.v:2667.1-2713.4" - wire $0\builder_converter1_next_state[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\builder_converter1_state[0:0] - attribute \src "ls180.v:3920.1-3966.4" - wire $0\builder_converter_next_state[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\builder_converter_state[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 20 $0\builder_count[19:0] - attribute \src "ls180.v:5510.1-5521.4" - wire $0\builder_error[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 2 $0\builder_grant[1:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate0__o[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate0_oe[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate10__o[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate10_oe[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate11__o[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate11_oe[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate12__o[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate12_oe[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate13__o[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate13_oe[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate14__o[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate14_oe[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate15__o[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate15_oe[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate16__o[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate16_oe[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate17__o[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate17_oe[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate18__o[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate18_oe[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate19__o[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate19_oe[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate1__o[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate1_oe[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate20__o[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate20_oe[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate2__o[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate2_oe[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate3__o[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate3_oe[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate4__o[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate4_oe[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate5__o[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate5_oe[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate6__o[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate6_oe[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate7__o[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate7_oe[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate8__o[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate8_oe[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate9__o[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\builder_inferedsdrtristate9_oe[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 14 $0\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:5402.1-5438.4" - wire width 14 $0\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:5402.1-5438.4" - wire $0\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:5402.1-5438.4" - wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:5402.1-5438.4" - wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\builder_libresocsim_we[0:0] - attribute \src "ls180.v:5402.1-5438.4" - wire $0\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:5402.1-5438.4" - wire $0\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:5402.1-5438.4" - wire $0\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:5402.1-5438.4" - wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1762.5-1762.44" - wire $0\builder_libresocsim_wishbone_err[0:0] - attribute \src "ls180.v:1651.5-1651.27" - wire $0\builder_locked0[0:0] - attribute \src "ls180.v:1652.5-1652.27" - wire $0\builder_locked1[0:0] - attribute \src "ls180.v:1653.5-1653.27" - wire $0\builder_locked2[0:0] - attribute \src "ls180.v:1654.5-1654.27" - wire $0\builder_locked3[0:0] - attribute \src "ls180.v:3792.1-3864.4" - wire width 3 $0\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\builder_multiplexer_state[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\builder_multiregimpl1_regs0[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\builder_multiregimpl1_regs1[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\builder_multiregimpl2_regs0[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\builder_multiregimpl2_regs1[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:5402.1-5438.4" - wire width 2 $0\builder_next_state[1:0] - attribute \src "ls180.v:3009.1-3039.4" - wire width 2 $0\builder_refresher_next_state[1:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 2 $0\builder_refresher_state[1:0] - attribute \src "ls180.v:5153.1-5192.4" - wire width 2 $0\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 2 $0\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:4720.1-4799.4" - wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire width 3 $0\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:5212.1-5249.4" - wire $0\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:5250.1-5286.4" - wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:4395.1-4467.4" - wire width 3 $0\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:4240.1-4333.4" - wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:4130.1-4206.4" - wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:4367.1-4394.4" - wire $0\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:4501.1-4602.4" - wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:4096.1-4129.4" - wire $0\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:5510.1-5521.4" - wire $0\builder_shared_ack[0:0] - attribute \src "ls180.v:5510.1-5521.4" - wire width 32 $0\builder_shared_dat_r[31:0] - attribute \src "ls180.v:5460.1-5467.4" - wire width 5 $0\builder_slave_sel[4:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 5 $0\builder_slave_sel_r[4:0] - attribute \src "ls180.v:3990.1-4038.4" - wire width 2 $0\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 2 $0\builder_spimaster0_state[1:0] - attribute \src "ls180.v:5353.1-5401.4" - wire width 2 $0\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 2 $0\builder_spimaster1_state[1:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 2 $0\builder_state[1:0] - attribute \src "ls180.v:6819.1-6847.4" - wire $0\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:6848.1-6876.4" - wire $0\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:6700.1-6716.4" - wire width 2 $0\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:6717.1-6733.4" - wire width 13 $0\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:6734.1-6750.4" - wire $0\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:6751.1-6767.4" - wire $0\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:6768.1-6784.4" - wire $0\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:6785.1-6801.4" - wire $0\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:6802.1-6818.4" - wire $0\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\libresocsim_clk_divider1[15:0] - attribute \src "ls180.v:5353.1-5401.4" - wire $0\libresocsim_clk_enable[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_clocker_clk0[0:0] - attribute \src "ls180.v:4066.1-4094.4" - wire $0\libresocsim_clocker_clk1[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_clocker_clk_d[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 9 $0\libresocsim_clocker_clks[8:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_clocker_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 9 $0\libresocsim_clocker_storage[8:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\libresocsim_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\libresocsim_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1030.5-1030.54" - wire $0\libresocsim_cmdr_cmdr_converter_sink_first[0:0] - attribute \src "ls180.v:1031.5-1031.53" - wire $0\libresocsim_cmdr_cmdr_converter_sink_last[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 4 $0\libresocsim_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1011.5-1011.47" - wire $0\libresocsim_cmdr_cmdr_pads_in_ready[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:4240.1-4333.4" - wire $0\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:4240.1-4333.4" - wire $0\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:4240.1-4333.4" - wire $0\libresocsim_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\libresocsim_cmdr_count[7:0] - attribute \src "ls180.v:4240.1-4333.4" - wire width 8 $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:4240.1-4333.4" - wire $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:984.5-984.50" - wire $0\libresocsim_cmdr_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:985.5-985.49" - wire $0\libresocsim_cmdr_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:986.5-986.56" - wire $0\libresocsim_cmdr_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:988.5-988.58" - wire $0\libresocsim_cmdr_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:989.5-989.59" - wire $0\libresocsim_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:991.11-991.65" - wire width 4 $0\libresocsim_cmdr_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:992.5-992.60" - wire $0\libresocsim_cmdr_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4240.1-4333.4" - wire $0\libresocsim_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4240.1-4333.4" - wire $0\libresocsim_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4240.1-4333.4" - wire $0\libresocsim_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:997.11-997.58" - wire width 4 $0\libresocsim_cmdr_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:998.5-998.53" - wire $0\libresocsim_cmdr_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_cmdr_sink_last[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire width 8 $0\libresocsim_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:4240.1-4333.4" - wire $0\libresocsim_cmdr_sink_ready[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_cmdr_sink_valid[0:0] - attribute \src "ls180.v:4240.1-4333.4" - wire $0\libresocsim_cmdr_source_last[0:0] - attribute \src "ls180.v:4240.1-4333.4" - wire width 8 $0\libresocsim_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:4240.1-4333.4" - wire width 3 $0\libresocsim_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_cmdr_source_ready[0:0] - attribute \src "ls180.v:4240.1-4333.4" - wire $0\libresocsim_cmdr_source_valid[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 32 $0\libresocsim_cmdr_timeout[31:0] - attribute \src "ls180.v:4240.1-4333.4" - wire width 32 $0\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:4240.1-4333.4" - wire $0\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\libresocsim_cmdw_count[7:0] - attribute \src "ls180.v:4130.1-4206.4" - wire width 8 $0\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:4130.1-4206.4" - wire $0\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:4130.1-4206.4" - wire $0\libresocsim_cmdw_done[0:0] - attribute \src "ls180.v:4130.1-4206.4" - wire $0\libresocsim_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4130.1-4206.4" - wire $0\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4130.1-4206.4" - wire $0\libresocsim_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:974.11-974.58" - wire width 4 $0\libresocsim_cmdw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:975.5-975.53" - wire $0\libresocsim_cmdw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_cmdw_sink_last[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire width 8 $0\libresocsim_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:4130.1-4206.4" - wire $0\libresocsim_cmdw_sink_ready[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_cmdw_sink_valid[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_control_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\libresocsim_control_storage[15:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\libresocsim_count[2:0] - attribute \src "ls180.v:5353.1-5401.4" - wire width 3 $0\libresocsim_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:5353.1-5401.4" - wire $0\libresocsim_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:5353.1-5401.4" - wire $0\libresocsim_cs_enable[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_cs_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_cs_storage[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 10 $0\libresocsim_datar_count[9:0] - attribute \src "ls180.v:4501.1-4602.4" - wire width 10 $0\libresocsim_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:4501.1-4602.4" - wire $0\libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\libresocsim_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1186.5-1186.56" - wire $0\libresocsim_datar_datar_converter_sink_first[0:0] - attribute \src "ls180.v:1187.5-1187.55" - wire $0\libresocsim_datar_datar_converter_sink_last[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\libresocsim_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 2 $0\libresocsim_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1167.5-1167.49" - wire $0\libresocsim_datar_datar_pads_in_ready[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_datar_datar_reset[0:0] - attribute \src "ls180.v:4501.1-4602.4" - wire $0\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:4501.1-4602.4" - wire $0\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_datar_datar_run[0:0] - attribute \src "ls180.v:4501.1-4602.4" - wire $0\libresocsim_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1138.5-1138.51" - wire $0\libresocsim_datar_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1139.5-1139.50" - wire $0\libresocsim_datar_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1140.5-1140.57" - wire $0\libresocsim_datar_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1142.5-1142.59" - wire $0\libresocsim_datar_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1143.5-1143.60" - wire $0\libresocsim_datar_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1145.11-1145.66" - wire width 4 $0\libresocsim_datar_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1146.5-1146.61" - wire $0\libresocsim_datar_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4501.1-4602.4" - wire $0\libresocsim_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1149.5-1149.52" - wire $0\libresocsim_datar_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1150.5-1150.53" - wire $0\libresocsim_datar_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1151.11-1151.59" - wire width 4 $0\libresocsim_datar_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1152.5-1152.54" - wire $0\libresocsim_datar_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_datar_sink_last[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire width 10 $0\libresocsim_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:4501.1-4602.4" - wire $0\libresocsim_datar_sink_ready[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_datar_sink_valid[0:0] - attribute \src "ls180.v:1159.5-1159.42" - wire $0\libresocsim_datar_source_first[0:0] - attribute \src "ls180.v:4501.1-4602.4" - wire $0\libresocsim_datar_source_last[0:0] - attribute \src "ls180.v:4501.1-4602.4" - wire width 8 $0\libresocsim_datar_source_payload_data[7:0] - attribute \src "ls180.v:4501.1-4602.4" - wire width 3 $0\libresocsim_datar_source_payload_status[2:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_datar_source_ready[0:0] - attribute \src "ls180.v:4501.1-4602.4" - wire $0\libresocsim_datar_source_valid[0:0] - attribute \src "ls180.v:4501.1-4602.4" - wire $0\libresocsim_datar_stop[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 32 $0\libresocsim_datar_timeout[31:0] - attribute \src "ls180.v:4501.1-4602.4" - wire width 32 $0\libresocsim_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:4501.1-4602.4" - wire $0\libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\libresocsim_dataw_count[7:0] - attribute \src "ls180.v:4395.1-4467.4" - wire width 8 $0\libresocsim_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:4395.1-4467.4" - wire $0\libresocsim_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\libresocsim_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\libresocsim_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1108.5-1108.55" - wire $0\libresocsim_dataw_crcr_converter_sink_first[0:0] - attribute \src "ls180.v:1109.5-1109.54" - wire $0\libresocsim_dataw_crcr_converter_sink_last[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\libresocsim_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 4 $0\libresocsim_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1089.5-1089.48" - wire $0\libresocsim_dataw_crcr_pads_in_ready[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_dataw_crcr_reset[0:0] - attribute \src "ls180.v:4367.1-4394.4" - wire $0\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:4367.1-4394.4" - wire $0\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_dataw_crcr_run[0:0] - attribute \src "ls180.v:4367.1-4394.4" - wire $0\libresocsim_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:4367.1-4394.4" - wire $0\libresocsim_dataw_error[0:0] - attribute \src "ls180.v:1076.5-1076.51" - wire $0\libresocsim_dataw_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1077.5-1077.50" - wire $0\libresocsim_dataw_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1078.5-1078.57" - wire $0\libresocsim_dataw_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1079.5-1079.59" - wire $0\libresocsim_dataw_pads_in_pads_in_payload_cmd_i[0:0] - attribute \src "ls180.v:1080.5-1080.59" - wire $0\libresocsim_dataw_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1081.5-1081.60" - wire $0\libresocsim_dataw_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1082.11-1082.66" - wire width 4 $0\libresocsim_dataw_pads_in_pads_in_payload_data_i[3:0] - attribute \src "ls180.v:1083.11-1083.66" - wire width 4 $0\libresocsim_dataw_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1084.5-1084.61" - wire $0\libresocsim_dataw_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:1074.5-1074.51" - wire $0\libresocsim_dataw_pads_in_pads_in_valid[0:0] - attribute \src "ls180.v:4395.1-4467.4" - wire $0\libresocsim_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1063.5-1063.52" - wire $0\libresocsim_dataw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1064.5-1064.53" - wire $0\libresocsim_dataw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4395.1-4467.4" - wire width 4 $0\libresocsim_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4395.1-4467.4" - wire $0\libresocsim_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_dataw_sink_first[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_dataw_sink_last[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire width 8 $0\libresocsim_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:4395.1-4467.4" - wire $0\libresocsim_dataw_sink_ready[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_dataw_sink_valid[0:0] - attribute \src "ls180.v:4395.1-4467.4" - wire $0\libresocsim_dataw_start[0:0] - attribute \src "ls180.v:4395.1-4467.4" - wire $0\libresocsim_dataw_stop[0:0] - attribute \src "ls180.v:4367.1-4394.4" - wire $0\libresocsim_dataw_valid[0:0] - attribute \src "ls180.v:5353.1-5401.4" - wire $0\libresocsim_done0[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\libresocsim_init_count[7:0] - attribute \src "ls180.v:4096.1-4129.4" - wire width 8 $0\libresocsim_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:4096.1-4129.4" - wire $0\libresocsim_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:956.5-956.41" - wire $0\libresocsim_init_initialize_w[0:0] - attribute \src "ls180.v:4096.1-4129.4" - wire $0\libresocsim_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4096.1-4129.4" - wire $0\libresocsim_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4096.1-4129.4" - wire $0\libresocsim_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4096.1-4129.4" - wire width 4 $0\libresocsim_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4096.1-4129.4" - wire $0\libresocsim_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1405.11-1405.48" - wire width 2 $0\libresocsim_interface0_bus_bte[1:0] - attribute \src "ls180.v:1404.11-1404.48" - wire width 3 $0\libresocsim_interface0_bus_cti[2:0] - attribute \src "ls180.v:5212.1-5249.4" - wire width 32 $0\libresocsim_interface1_bus_adr[31:0] - attribute \src "ls180.v:1496.11-1496.48" - wire width 2 $0\libresocsim_interface1_bus_bte[1:0] - attribute \src "ls180.v:1495.11-1495.48" - wire width 3 $0\libresocsim_interface1_bus_cti[2:0] - attribute \src "ls180.v:5212.1-5249.4" - wire $0\libresocsim_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1488.12-1488.52" - wire width 32 $0\libresocsim_interface1_bus_dat_w[31:0] - attribute \src "ls180.v:5212.1-5249.4" - wire width 4 $0\libresocsim_interface1_bus_sel[3:0] - attribute \src "ls180.v:5212.1-5249.4" - wire $0\libresocsim_interface1_bus_stb[0:0] - attribute \src "ls180.v:5212.1-5249.4" - wire $0\libresocsim_interface1_bus_we[0:0] - attribute \src "ls180.v:5353.1-5401.4" - wire $0\libresocsim_irq[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_loopback_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_loopback_storage[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\libresocsim_miso[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\libresocsim_miso_data[7:0] - attribute \src "ls180.v:5353.1-5401.4" - wire $0\libresocsim_miso_latch[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\libresocsim_mosi_data[7:0] - attribute \src "ls180.v:5353.1-5401.4" - wire $0\libresocsim_mosi_latch[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_mosi_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\libresocsim_mosi_sel[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\libresocsim_mosi_storage[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 2 $0\libresocsim_sdblock2mem_converter_demux[1:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 32 $0\libresocsim_sdblock2mem_converter_source_payload_data[31:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\libresocsim_sdblock2mem_converter_source_payload_valid_token_count[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 5 $0\libresocsim_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 6 $0\libresocsim_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 5 $0\libresocsim_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1429.5-1429.48" - wire $0\libresocsim_sdblock2mem_fifo_replace[0:0] - attribute \src "ls180.v:5120.1-5127.4" - wire width 5 $0\libresocsim_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:5153.1-5192.4" - wire width 32 $0\libresocsim_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:5153.1-5192.4" - wire width 32 $0\libresocsim_sdblock2mem_sink_sink_payload_data1[31:0] - attribute \src "ls180.v:5153.1-5192.4" - wire $0\libresocsim_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 64 $0\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 32 $0\libresocsim_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 32 $0\libresocsim_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:5153.1-5192.4" - wire width 32 $0\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:5153.1-5192.4" - wire $0\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:5153.1-5192.4" - wire $0\libresocsim_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:5153.1-5192.4" - wire $0\libresocsim_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdcore_block_count_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 32 $0\libresocsim_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdcore_block_length_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 10 $0\libresocsim_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 32 $0\libresocsim_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 32 $0\libresocsim_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\libresocsim_sdcore_cmd_count[2:0] - attribute \src "ls180.v:4902.1-5092.4" - wire width 3 $0\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdcore_cmd_done[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdcore_cmd_error[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 128 $0\libresocsim_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:4902.1-5092.4" - wire width 128 $0\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1238.5-1238.41" - wire $0\libresocsim_sdcore_cmd_send_w[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 4 $0\libresocsim_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:4808.1-4815.4" - wire $0\libresocsim_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:4864.1-4871.4" - wire width 16 $0\libresocsim_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\libresocsim_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:4818.1-4825.4" - wire $0\libresocsim_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:4874.1-4881.4" - wire width 16 $0\libresocsim_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\libresocsim_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:4828.1-4835.4" - wire $0\libresocsim_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:4884.1-4891.4" - wire width 16 $0\libresocsim_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\libresocsim_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:4838.1-4845.4" - wire $0\libresocsim_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:4894.1-4901.4" - wire width 16 $0\libresocsim_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\libresocsim_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\libresocsim_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\libresocsim_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\libresocsim_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\libresocsim_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\libresocsim_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\libresocsim_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\libresocsim_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\libresocsim_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire width 8 $0\libresocsim_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:4853.1-4860.4" - wire $0\libresocsim_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1344.5-1344.57" - wire $0\libresocsim_sdcore_crc16_checker_source_first[0:0] - attribute \src "ls180.v:4847.1-4852.4" - wire $0\libresocsim_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\libresocsim_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:4800.1-4805.4" - wire $0\libresocsim_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\libresocsim_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:4720.1-4799.4" - wire width 3 $0\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:4720.1-4799.4" - wire $0\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:4682.1-4689.4" - wire width 16 $0\libresocsim_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\libresocsim_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:4692.1-4699.4" - wire width 16 $0\libresocsim_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\libresocsim_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:4702.1-4709.4" - wire width 16 $0\libresocsim_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\libresocsim_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:4712.1-4719.4" - wire width 16 $0\libresocsim_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\libresocsim_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\libresocsim_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:4720.1-4799.4" - wire width 16 $0\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:4720.1-4799.4" - wire $0\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\libresocsim_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:4720.1-4799.4" - wire width 16 $0\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:4720.1-4799.4" - wire $0\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\libresocsim_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:4720.1-4799.4" - wire width 16 $0\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:4720.1-4799.4" - wire $0\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\libresocsim_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:4720.1-4799.4" - wire width 16 $0\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:4720.1-4799.4" - wire $0\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:4720.1-4799.4" - wire $0\libresocsim_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1301.5-1301.58" - wire $0\libresocsim_sdcore_crc16_inserter_source_first[0:0] - attribute \src "ls180.v:4720.1-4799.4" - wire $0\libresocsim_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:4720.1-4799.4" - wire width 8 $0\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:4720.1-4799.4" - wire $0\libresocsim_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:4660.1-4667.4" - wire width 7 $0\libresocsim_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 7 $0\libresocsim_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 32 $0\libresocsim_sdcore_data_count[31:0] - attribute \src "ls180.v:4902.1-5092.4" - wire width 32 $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdcore_data_done[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdcore_data_error[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdcore_data_timeout[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:4902.1-5092.4" - wire $0\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 2 $0\libresocsim_sdmem2block_converter_mux[1:0] - attribute \src "ls180.v:5298.1-5314.4" - wire width 8 $0\libresocsim_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 64 $0\libresocsim_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 32 $0\libresocsim_sdmem2block_dma_data[31:0] - attribute \src "ls180.v:5212.1-5249.4" - wire width 32 $0\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] - attribute \src "ls180.v:5212.1-5249.4" - wire $0\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:5250.1-5286.4" - wire $0\libresocsim_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 32 $0\libresocsim_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\libresocsim_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 32 $0\libresocsim_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:5250.1-5286.4" - wire width 32 $0\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:5250.1-5286.4" - wire $0\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:5250.1-5286.4" - wire $0\libresocsim_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:5250.1-5286.4" - wire width 32 $0\libresocsim_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:5212.1-5249.4" - wire $0\libresocsim_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:5250.1-5286.4" - wire $0\libresocsim_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1509.5-1509.52" - wire $0\libresocsim_sdmem2block_dma_source_first[0:0] - attribute \src "ls180.v:5212.1-5249.4" - wire $0\libresocsim_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:5212.1-5249.4" - wire width 32 $0\libresocsim_sdmem2block_dma_source_payload_data[31:0] - attribute \src "ls180.v:5212.1-5249.4" - wire $0\libresocsim_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 5 $0\libresocsim_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 6 $0\libresocsim_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 5 $0\libresocsim_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1565.5-1565.48" - wire $0\libresocsim_sdmem2block_fifo_replace[0:0] - attribute \src "ls180.v:5328.1-5335.4" - wire width 5 $0\libresocsim_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\libresocsim_sdpads_cmd_i[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire width 4 $0\libresocsim_sdpads_data_i[3:0] - attribute \src "ls180.v:5979.1-5984.4" - wire $0\libresocsim_start1[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\libresocsim_storage[15:0] - attribute \src "ls180.v:915.12-915.37" - wire width 16 $0\main_clk_divider0[15:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\main_clk_divider1[15:0] - attribute \src "ls180.v:3990.1-4038.4" - wire $0\main_clk_enable[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_cmd_consumed[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_control_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\main_control_storage[15:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_converter_counter[0:0] - attribute \src "ls180.v:3920.1-3966.4" - wire $0\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:3920.1-3966.4" - wire $0\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 32 $0\main_converter_dat_r[31:0] - attribute \src "ls180.v:3920.1-3966.4" - wire $0\main_converter_skip[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\main_count[2:0] - attribute \src "ls180.v:3990.1-4038.4" - wire width 3 $0\main_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:3990.1-4038.4" - wire $0\main_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:3990.1-4038.4" - wire $0\main_cs_enable[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_cs_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_cs_storage[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire width 16 $0\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:3990.1-4038.4" - wire $0\main_done0[0:0] - attribute \src "ls180.v:6965.1-6967.4" - wire $0\main_int_rst[0:0] - attribute \src "ls180.v:3990.1-4038.4" - wire $0\main_irq[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_converter0_counter[0:0] - attribute \src "ls180.v:2607.1-2653.4" - wire $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:2607.1-2653.4" - wire $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 64 $0\main_libresocsim_converter0_dat_r[63:0] - attribute \src "ls180.v:2607.1-2653.4" - wire $0\main_libresocsim_converter0_skip[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_converter1_counter[0:0] - attribute \src "ls180.v:2667.1-2713.4" - wire $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:2667.1-2713.4" - wire $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 64 $0\main_libresocsim_converter1_dat_r[63:0] - attribute \src "ls180.v:2667.1-2713.4" - wire $0\main_libresocsim_converter1_skip[0:0] - attribute \src "ls180.v:2607.1-2653.4" - wire width 30 $0\main_libresocsim_interface0_converted_interface_adr[29:0] - attribute \src "ls180.v:106.11-106.69" - wire width 2 $0\main_libresocsim_interface0_converted_interface_bte[1:0] - attribute \src "ls180.v:105.11-105.69" - wire width 3 $0\main_libresocsim_interface0_converted_interface_cti[2:0] - attribute \src "ls180.v:2607.1-2653.4" - wire $0\main_libresocsim_interface0_converted_interface_cyc[0:0] - attribute \src "ls180.v:2595.1-2605.4" - wire width 32 $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] - attribute \src "ls180.v:2607.1-2653.4" - wire width 4 $0\main_libresocsim_interface0_converted_interface_sel[3:0] - attribute \src "ls180.v:2607.1-2653.4" - wire $0\main_libresocsim_interface0_converted_interface_stb[0:0] - attribute \src "ls180.v:2607.1-2653.4" - wire $0\main_libresocsim_interface0_converted_interface_we[0:0] - attribute \src "ls180.v:2667.1-2713.4" - wire width 30 $0\main_libresocsim_interface1_converted_interface_adr[29:0] - attribute \src "ls180.v:121.11-121.69" - wire width 2 $0\main_libresocsim_interface1_converted_interface_bte[1:0] - attribute \src "ls180.v:120.11-120.69" - wire width 3 $0\main_libresocsim_interface1_converted_interface_cti[2:0] - attribute \src "ls180.v:2667.1-2713.4" - wire $0\main_libresocsim_interface1_converted_interface_cyc[0:0] - attribute \src "ls180.v:2655.1-2665.4" - wire width 32 $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] - attribute \src "ls180.v:2667.1-2713.4" - wire width 4 $0\main_libresocsim_interface1_converted_interface_sel[3:0] - attribute \src "ls180.v:2667.1-2713.4" - wire $0\main_libresocsim_interface1_converted_interface_stb[0:0] - attribute \src "ls180.v:2667.1-2713.4" - wire $0\main_libresocsim_interface1_converted_interface_we[0:0] - attribute \src "ls180.v:2667.1-2713.4" - wire $0\main_libresocsim_libresoc_dbus_ack[0:0] - attribute \src "ls180.v:54.5-54.46" - wire $0\main_libresocsim_libresoc_dbus_err[0:0] - attribute \src "ls180.v:88.11-88.52" - wire width 4 $0\main_libresocsim_libresoc_dmi_addr[3:0] - attribute \src "ls180.v:89.12-89.53" - wire width 64 $0\main_libresocsim_libresoc_dmi_din[63:0] - attribute \src "ls180.v:93.5-93.45" - wire $0\main_libresocsim_libresoc_dmi_req[0:0] - attribute \src "ls180.v:91.5-91.44" - wire $0\main_libresocsim_libresoc_dmi_wr[0:0] - attribute \src "ls180.v:2607.1-2653.4" - wire $0\main_libresocsim_libresoc_ibus_ack[0:0] - attribute \src "ls180.v:65.5-65.46" - wire $0\main_libresocsim_libresoc_ibus_err[0:0] - attribute \src "ls180.v:2588.1-2593.4" - wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 32 $0\main_libresocsim_phase_accumulator_rx[31:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 32 $0\main_libresocsim_phase_accumulator_tx[31:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:137.5-137.40" - wire $0\main_libresocsim_ram_bus_err[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 4 $0\main_libresocsim_rx_bitcount[3:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_rx_busy[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_rx_r[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\main_libresocsim_rx_reg[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_sink_ready[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 32 $0\main_libresocsim_soccontroller_bus_errors[31:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_soccontroller_reset_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_soccontroller_reset_storage[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_soccontroller_scratch_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 32 $0\main_libresocsim_soccontroller_scratch_storage[31:0] - attribute \src "ls180.v:156.5-156.41" - wire $0\main_libresocsim_source_first[0:0] - attribute \src "ls180.v:157.5-157.40" - wire $0\main_libresocsim_source_last[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\main_libresocsim_source_payload_data[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_source_valid[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 32 $0\main_libresocsim_storage[31:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_timer_en_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_timer_en_storage[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_timer_eventmanager_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_timer_eventmanager_storage[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_timer_load_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 32 $0\main_libresocsim_timer_load_storage[31:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_timer_reload_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 32 $0\main_libresocsim_timer_reload_storage[31:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_timer_update_value_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_timer_update_value_storage[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 32 $0\main_libresocsim_timer_value[31:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 32 $0\main_libresocsim_timer_value_status[31:0] - attribute \src "ls180.v:2843.1-2848.4" - wire $0\main_libresocsim_timer_zero_clear[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_timer_zero_old_trigger[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_timer_zero_pending[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 4 $0\main_libresocsim_tx_bitcount[3:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_tx_busy[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\main_libresocsim_tx_reg[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_uart_clk_rxen[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_uart_clk_txen[0:0] - attribute \src "ls180.v:2773.1-2777.4" - wire width 2 $0\main_libresocsim_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_uart_eventmanager_re[0:0] - attribute \src "ls180.v:2762.1-2766.4" - wire width 2 $0\main_libresocsim_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 2 $0\main_libresocsim_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:283.5-283.39" - wire $0\main_libresocsim_uart_reset[0:0] - attribute \src "ls180.v:2767.1-2772.4" - wire $0\main_libresocsim_uart_rx_clear[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 4 $0\main_libresocsim_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 5 $0\main_libresocsim_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 4 $0\main_libresocsim_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:265.5-265.49" - wire $0\main_libresocsim_uart_rx_fifo_replace[0:0] - attribute \src "ls180.v:2825.1-2832.4" - wire width 4 $0\main_libresocsim_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_uart_rx_pending[0:0] - attribute \src "ls180.v:2756.1-2761.4" - wire $0\main_libresocsim_uart_tx_clear[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 4 $0\main_libresocsim_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 5 $0\main_libresocsim_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 4 $0\main_libresocsim_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:228.5-228.49" - wire $0\main_libresocsim_uart_tx_fifo_replace[0:0] - attribute \src "ls180.v:211.5-211.52" - wire $0\main_libresocsim_uart_tx_fifo_sink_first[0:0] - attribute \src "ls180.v:212.5-212.51" - wire $0\main_libresocsim_uart_tx_fifo_sink_last[0:0] - attribute \src "ls180.v:2795.1-2802.4" - wire width 4 $0\main_libresocsim_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_libresocsim_uart_tx_pending[0:0] - attribute \src "ls180.v:2716.1-2722.4" - wire width 4 $0\main_libresocsim_we[3:0] - attribute \src "ls180.v:3920.1-3966.4" - wire width 30 $0\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:3920.1-3966.4" - wire $0\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:3908.1-3918.4" - wire width 16 $0\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:3920.1-3966.4" - wire width 2 $0\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:3920.1-3966.4" - wire $0\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:3920.1-3966.4" - wire $0\main_litedram_wb_we[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_loopback_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_loopback_storage[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\main_miso[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\main_miso_data[7:0] - attribute \src "ls180.v:3990.1-4038.4" - wire $0\main_miso_latch[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\main_mosi_data[7:0] - attribute \src "ls180.v:3990.1-4038.4" - wire $0\main_mosi_latch[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_mosi_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\main_mosi_sel[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 8 $0\main_mosi_storage[7:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\main_rddata_en[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_address_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 13 $0\main_sdram_address_storage[12:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 2 $0\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:3065.1-3072.4" - wire $0\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:511.5-511.64" - wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:494.5-494.67" - wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:495.5-495.66" - wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3087.1-3094.4" - wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3054.1-3061.4" - wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:3103.1-3196.4" - wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:3103.1-3196.4" - wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3103.1-3196.4" - wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3103.1-3196.4" - wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3103.1-3196.4" - wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:3103.1-3196.4" - wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:3752.1-3760.4" - wire $0\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:3103.1-3196.4" - wire $0\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:3103.1-3196.4" - wire $0\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:3103.1-3196.4" - wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:3103.1-3196.4" - wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 13 $0\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:3103.1-3196.4" - wire $0\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:3103.1-3196.4" - wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3103.1-3196.4" - wire $0\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:553.32-553.76" - wire $0\main_sdram_bankmachine0_trascon_ready[0:0] - attribute \src "ls180.v:551.32-551.75" - wire $0\main_sdram_bankmachine0_trccon_ready[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:3222.1-3229.4" - wire $0\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:593.5-593.64" - wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:576.5-576.67" - wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:577.5-577.66" - wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3244.1-3251.4" - wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3211.1-3218.4" - wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:3260.1-3353.4" - wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:3260.1-3353.4" - wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3260.1-3353.4" - wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3260.1-3353.4" - wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3260.1-3353.4" - wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:3260.1-3353.4" - wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:3761.1-3769.4" - wire $0\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:3260.1-3353.4" - wire $0\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:3260.1-3353.4" - wire $0\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:3260.1-3353.4" - wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:3260.1-3353.4" - wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 13 $0\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:3260.1-3353.4" - wire $0\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:3260.1-3353.4" - wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3260.1-3353.4" - wire $0\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:635.32-635.76" - wire $0\main_sdram_bankmachine1_trascon_ready[0:0] - attribute \src "ls180.v:633.32-633.75" - wire $0\main_sdram_bankmachine1_trccon_ready[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:3379.1-3386.4" - wire $0\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:675.5-675.64" - wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:658.5-658.67" - wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:659.5-659.66" - wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3401.1-3408.4" - wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3368.1-3375.4" - wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:3417.1-3510.4" - wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:3417.1-3510.4" - wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3417.1-3510.4" - wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3417.1-3510.4" - wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3417.1-3510.4" - wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:3417.1-3510.4" - wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:3770.1-3778.4" - wire $0\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:3417.1-3510.4" - wire $0\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:3417.1-3510.4" - wire $0\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:3417.1-3510.4" - wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:3417.1-3510.4" - wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 13 $0\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:3417.1-3510.4" - wire $0\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:3417.1-3510.4" - wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3417.1-3510.4" - wire $0\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:717.32-717.76" - wire $0\main_sdram_bankmachine2_trascon_ready[0:0] - attribute \src "ls180.v:715.32-715.75" - wire $0\main_sdram_bankmachine2_trccon_ready[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:3536.1-3543.4" - wire $0\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:757.5-757.64" - wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:740.5-740.67" - wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:741.5-741.66" - wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3558.1-3565.4" - wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3525.1-3532.4" - wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:3574.1-3667.4" - wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:3574.1-3667.4" - wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3574.1-3667.4" - wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3574.1-3667.4" - wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3574.1-3667.4" - wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:3574.1-3667.4" - wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:3779.1-3787.4" - wire $0\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:3574.1-3667.4" - wire $0\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:3574.1-3667.4" - wire $0\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:3574.1-3667.4" - wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:3574.1-3667.4" - wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 13 $0\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:3574.1-3667.4" - wire $0\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:3574.1-3667.4" - wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3574.1-3667.4" - wire $0\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:799.32-799.76" - wire $0\main_sdram_bankmachine3_trascon_ready[0:0] - attribute \src "ls180.v:797.32-797.75" - wire $0\main_sdram_bankmachine3_trccon_ready[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:3701.1-3706.4" - wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:3707.1-3712.4" - wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:3713.1-3718.4" - wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:807.5-807.43" - wire $0\main_sdram_choose_cmd_cmd_ready[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 2 $0\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:3687.1-3693.4" - wire width 4 $0\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:805.5-805.48" - wire $0\main_sdram_choose_cmd_want_activates[0:0] - attribute \src "ls180.v:804.5-804.43" - wire $0\main_sdram_choose_cmd_want_cmds[0:0] - attribute \src "ls180.v:802.5-802.44" - wire $0\main_sdram_choose_cmd_want_reads[0:0] - attribute \src "ls180.v:803.5-803.45" - wire $0\main_sdram_choose_cmd_want_writes[0:0] - attribute \src "ls180.v:3734.1-3739.4" - wire $0\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:3740.1-3745.4" - wire $0\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:3746.1-3751.4" - wire $0\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:3792.1-3864.4" - wire $0\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 2 $0\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:3720.1-3726.4" - wire width 4 $0\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:3792.1-3864.4" - wire $0\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:3792.1-3864.4" - wire $0\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:3792.1-3864.4" - wire $0\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:3009.1-3039.4" - wire $0\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 13 $0\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 2 $0\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:455.5-455.42" - wire $0\main_sdram_cmd_payload_is_read[0:0] - attribute \src "ls180.v:456.5-456.43" - wire $0\main_sdram_cmd_payload_is_write[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:3792.1-3864.4" - wire $0\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:3009.1-3039.4" - wire $0\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:391.5-391.38" - wire $0\main_sdram_command_issue_w[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_command_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 6 $0\main_sdram_command_storage[5:0] - attribute \src "ls180.v:440.5-440.35" - wire $0\main_sdram_dfi_p0_act_n[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 13 $0\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 2 $0\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:3792.1-3864.4" - wire $0\main_sdram_en0[0:0] - attribute \src "ls180.v:3792.1-3864.4" - wire $0\main_sdram_en1[0:0] - attribute \src "ls180.v:3888.1-3901.4" - wire width 16 $0\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:3888.1-3901.4" - wire width 2 $0\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:341.5-341.36" - wire $0\main_sdram_inti_p0_act_n[0:0] - attribute \src "ls180.v:2950.1-2966.4" - wire $0\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:2950.1-2966.4" - wire $0\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:2950.1-2966.4" - wire $0\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:2892.1-2946.4" - wire width 16 $0\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:2892.1-2946.4" - wire $0\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:2950.1-2966.4" - wire $0\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:2892.1-2946.4" - wire $0\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:2892.1-2946.4" - wire width 13 $0\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:2892.1-2946.4" - wire width 2 $0\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:2892.1-2946.4" - wire $0\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:2892.1-2946.4" - wire $0\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:2892.1-2946.4" - wire $0\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:2892.1-2946.4" - wire $0\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:2892.1-2946.4" - wire $0\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:2892.1-2946.4" - wire $0\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:2892.1-2946.4" - wire $0\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:2892.1-2946.4" - wire $0\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:2892.1-2946.4" - wire width 16 $0\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:2892.1-2946.4" - wire $0\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:2892.1-2946.4" - wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:838.12-838.36" - wire width 13 $0\main_sdram_nop_a[12:0] - attribute \src "ls180.v:839.11-839.35" - wire width 2 $0\main_sdram_nop_ba[1:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 4 $0\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:3009.1-3039.4" - wire $0\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:2892.1-2946.4" - wire width 16 $0\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:2892.1-2946.4" - wire $0\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\main_sdram_status[15:0] - attribute \src "ls180.v:841.5-841.31" - wire $0\main_sdram_steerer0[0:0] - attribute \src "ls180.v:842.5-842.31" - wire $0\main_sdram_steerer1[0:0] - attribute \src "ls180.v:3792.1-3864.4" - wire width 2 $0\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 4 $0\main_sdram_storage[3:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:846.32-846.63" - wire $0\main_sdram_tfawcon_ready[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 5 $0\main_sdram_time0[4:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 4 $0\main_sdram_time1[3:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 10 $0\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:844.32-844.63" - wire $0\main_sdram_trrdcon_ready[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 3 $0\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire width 16 $0\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:5933.1-5938.4" - wire $0\main_start1[0:0] - attribute \src "ls180.v:3920.1-3966.4" - wire $0\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:885.5-885.29" - wire $0\main_wb_sdram_err[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\main_wdata_consumed[0:0] - attribute \src "ls180.v:9368.1-9378.4" - wire width 7 $0\memadr[6:0] - attribute \src "ls180.v:9389.1-9393.4" - wire width 10 $0\memdat[9:0] - attribute \src "ls180.v:9395.1-9398.4" - wire width 10 $0\memdat_1[9:0] - attribute \src "ls180.v:9406.1-9410.4" - wire width 10 $0\memdat_2[9:0] - attribute \src "ls180.v:9412.1-9415.4" - wire width 10 $0\memdat_3[9:0] - attribute \src "ls180.v:9422.1-9426.4" - wire width 25 $0\memdat_4[24:0] - attribute \src "ls180.v:9436.1-9440.4" - wire width 25 $0\memdat_5[24:0] - attribute \src "ls180.v:9450.1-9454.4" - wire width 25 $0\memdat_6[24:0] - attribute \src "ls180.v:9464.1-9468.4" - wire width 25 $0\memdat_7[24:0] - attribute \src "ls180.v:9478.1-9482.4" - wire width 10 $0\memdat_8[9:0] - attribute \src "ls180.v:9492.1-9496.4" - wire width 10 $0\memdat_9[9:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\sdcard_clk[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire width 13 $0\sdram_a[12:0] - attribute \src "ls180.v:6969.1-7054.4" - wire width 2 $0\sdram_ba[1:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\sdram_cas_n[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\sdram_cke[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\sdram_cs_n[0:0] - attribute \src "ls180.v:2855.1-2859.4" - wire width 2 $0\sdram_dm[1:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\sdram_ras_n[0:0] - attribute \src "ls180.v:6969.1-7054.4" - wire $0\sdram_we_n[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\serial_tx[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\spi_master_clk[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\spi_master_cs_n[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\spi_master_mosi[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\spisdcard_clk[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\spisdcard_cs_n[0:0] - attribute \src "ls180.v:7056.1-9364.4" - wire $0\spisdcard_mosi[0:0] - attribute \src "ls180.v:1630.11-1630.49" - wire width 3 $1\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:1629.11-1629.44" - wire width 3 $1\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:1632.11-1632.49" - wire width 3 $1\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:1631.11-1631.44" - wire width 3 $1\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:1634.11-1634.49" - wire width 3 $1\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:1633.11-1633.44" - wire width 3 $1\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:1636.11-1636.49" - wire width 3 $1\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:1635.11-1635.44" - wire width 3 $1\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:2375.5-2375.41" - wire $1\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:2388.5-2388.42" - wire $1\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:2389.5-2389.42" - wire $1\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:2393.12-2393.50" - wire width 22 $1\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:2394.5-2394.42" - wire $1\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:2395.5-2395.42" - wire $1\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:2396.12-2396.50" - wire width 22 $1\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:2397.5-2397.42" - wire $1\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:2398.5-2398.42" - wire $1\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:2399.12-2399.50" - wire width 22 $1\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:2400.5-2400.42" - wire $1\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:2376.12-2376.49" - wire width 13 $1\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2401.5-2401.42" - wire $1\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:2402.12-2402.50" - wire width 22 $1\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:2403.5-2403.42" - wire $1\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:2404.5-2404.42" - wire $1\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:2405.12-2405.50" - wire width 32 $1\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:2406.12-2406.50" - wire width 32 $1\builder_comb_rhs_array_muxed25[31:0] - attribute \src "ls180.v:2407.11-2407.48" - wire width 4 $1\builder_comb_rhs_array_muxed26[3:0] - attribute \src "ls180.v:2408.5-2408.42" - wire $1\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:2409.5-2409.42" - wire $1\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:2410.5-2410.42" - wire $1\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:2377.11-2377.47" - wire width 2 $1\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:2411.11-2411.48" - wire width 3 $1\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:2412.11-2412.48" - wire width 2 $1\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:2378.5-2378.41" - wire $1\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2379.5-2379.41" - wire $1\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2380.5-2380.41" - wire $1\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2384.5-2384.41" - wire $1\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:2385.12-2385.49" - wire width 13 $1\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:2386.11-2386.47" - wire width 2 $1\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:2387.5-2387.41" - wire $1\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:2381.5-2381.39" - wire $1\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:2382.5-2382.39" - wire $1\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:2383.5-2383.39" - wire $1\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:2390.5-2390.39" - wire $1\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:2391.5-2391.39" - wire $1\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:2392.5-2392.39" - wire $1\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:1620.5-1620.41" - wire $1\builder_converter0_next_state[0:0] - attribute \src "ls180.v:1619.5-1619.36" - wire $1\builder_converter0_state[0:0] - attribute \src "ls180.v:1624.5-1624.41" - wire $1\builder_converter1_next_state[0:0] - attribute \src "ls180.v:1623.5-1623.36" - wire $1\builder_converter1_state[0:0] - attribute \src "ls180.v:1661.5-1661.40" - wire $1\builder_converter_next_state[0:0] - attribute \src "ls180.v:1660.5-1660.35" - wire $1\builder_converter_state[0:0] - attribute \src "ls180.v:1781.12-1781.39" - wire width 20 $1\builder_count[19:0] - attribute \src "ls180.v:1778.5-1778.25" - wire $1\builder_error[0:0] - attribute \src "ls180.v:1775.11-1775.31" - wire width 2 $1\builder_grant[1:0] - attribute \src "ls180.v:2444.5-2444.42" - wire $1\builder_inferedsdrtristate0__o[0:0] - attribute \src "ls180.v:2445.5-2445.42" - wire $1\builder_inferedsdrtristate0_oe[0:0] - attribute \src "ls180.v:2484.5-2484.43" - wire $1\builder_inferedsdrtristate10__o[0:0] - attribute \src "ls180.v:2485.5-2485.43" - wire $1\builder_inferedsdrtristate10_oe[0:0] - attribute \src "ls180.v:2488.5-2488.43" - wire $1\builder_inferedsdrtristate11__o[0:0] - attribute \src "ls180.v:2489.5-2489.43" - wire $1\builder_inferedsdrtristate11_oe[0:0] - attribute \src "ls180.v:2492.5-2492.43" - wire $1\builder_inferedsdrtristate12__o[0:0] - attribute \src "ls180.v:2493.5-2493.43" - wire $1\builder_inferedsdrtristate12_oe[0:0] - attribute \src "ls180.v:2496.5-2496.43" - wire $1\builder_inferedsdrtristate13__o[0:0] - attribute \src "ls180.v:2497.5-2497.43" - wire $1\builder_inferedsdrtristate13_oe[0:0] - attribute \src "ls180.v:2500.5-2500.43" - wire $1\builder_inferedsdrtristate14__o[0:0] - attribute \src "ls180.v:2501.5-2501.43" - wire $1\builder_inferedsdrtristate14_oe[0:0] - attribute \src "ls180.v:2504.5-2504.43" - wire $1\builder_inferedsdrtristate15__o[0:0] - attribute \src "ls180.v:2505.5-2505.43" - wire $1\builder_inferedsdrtristate15_oe[0:0] - attribute \src "ls180.v:2513.5-2513.43" - wire $1\builder_inferedsdrtristate16__o[0:0] - attribute \src "ls180.v:2514.5-2514.43" - wire $1\builder_inferedsdrtristate16_oe[0:0] - attribute \src "ls180.v:2517.5-2517.43" - wire $1\builder_inferedsdrtristate17__o[0:0] - attribute \src "ls180.v:2518.5-2518.43" - wire $1\builder_inferedsdrtristate17_oe[0:0] - attribute \src "ls180.v:2521.5-2521.43" - wire $1\builder_inferedsdrtristate18__o[0:0] - attribute \src "ls180.v:2522.5-2522.43" - wire $1\builder_inferedsdrtristate18_oe[0:0] - attribute \src "ls180.v:2525.5-2525.43" - wire $1\builder_inferedsdrtristate19__o[0:0] - attribute \src "ls180.v:2526.5-2526.43" - wire $1\builder_inferedsdrtristate19_oe[0:0] - attribute \src "ls180.v:2448.5-2448.42" - wire $1\builder_inferedsdrtristate1__o[0:0] - attribute \src "ls180.v:2449.5-2449.42" - wire $1\builder_inferedsdrtristate1_oe[0:0] - attribute \src "ls180.v:2529.5-2529.43" - wire $1\builder_inferedsdrtristate20__o[0:0] - attribute \src "ls180.v:2530.5-2530.43" - wire $1\builder_inferedsdrtristate20_oe[0:0] - attribute \src "ls180.v:2452.5-2452.42" - wire $1\builder_inferedsdrtristate2__o[0:0] - attribute \src "ls180.v:2453.5-2453.42" - wire $1\builder_inferedsdrtristate2_oe[0:0] - attribute \src "ls180.v:2456.5-2456.42" - wire $1\builder_inferedsdrtristate3__o[0:0] - attribute \src "ls180.v:2457.5-2457.42" - wire $1\builder_inferedsdrtristate3_oe[0:0] - attribute \src "ls180.v:2460.5-2460.42" - wire $1\builder_inferedsdrtristate4__o[0:0] - attribute \src "ls180.v:2461.5-2461.42" - wire $1\builder_inferedsdrtristate4_oe[0:0] - attribute \src "ls180.v:2464.5-2464.42" - wire $1\builder_inferedsdrtristate5__o[0:0] - attribute \src "ls180.v:2465.5-2465.42" - wire $1\builder_inferedsdrtristate5_oe[0:0] - attribute \src "ls180.v:2468.5-2468.42" - wire $1\builder_inferedsdrtristate6__o[0:0] - attribute \src "ls180.v:2469.5-2469.42" - wire $1\builder_inferedsdrtristate6_oe[0:0] - attribute \src "ls180.v:2472.5-2472.42" - wire $1\builder_inferedsdrtristate7__o[0:0] - attribute \src "ls180.v:2473.5-2473.42" - wire $1\builder_inferedsdrtristate7_oe[0:0] - attribute \src "ls180.v:2476.5-2476.42" - wire $1\builder_inferedsdrtristate8__o[0:0] - attribute \src "ls180.v:2477.5-2477.42" - wire $1\builder_inferedsdrtristate8_oe[0:0] - attribute \src "ls180.v:2480.5-2480.42" - wire $1\builder_inferedsdrtristate9__o[0:0] - attribute \src "ls180.v:2481.5-2481.42" - wire $1\builder_inferedsdrtristate9_oe[0:0] - attribute \src "ls180.v:1785.11-1785.51" - wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2255.11-2255.52" - wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2320.11-2320.52" - wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2345.11-2345.52" - wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1826.11-1826.51" - wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1835.11-1835.51" - wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1844.11-1844.51" - wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1909.11-1909.51" - wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2042.11-2042.51" - wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2123.11-2123.51" - wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2140.11-2140.51" - wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2181.11-2181.51" - wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2214.11-2214.51" - wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1748.12-1748.43" - wire width 14 $1\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:2371.12-2371.55" - wire width 14 $1\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:2372.5-2372.50" - wire $1\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:1750.11-1750.43" - wire width 8 $1\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:2369.11-2369.55" - wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:2370.5-2370.52" - wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:1749.5-1749.34" - wire $1\builder_libresocsim_we[0:0] - attribute \src "ls180.v:2373.5-2373.46" - wire $1\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:2374.5-2374.49" - wire $1\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:1758.5-1758.44" - wire $1\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:1754.12-1754.54" - wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1638.11-1638.48" - wire width 3 $1\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:1637.11-1637.43" - wire width 3 $1\builder_multiplexer_state[2:0] - attribute \src "ls180.v:2422.32-2422.66" - wire $1\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:2423.32-2423.66" - wire $1\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:2508.38-2508.72" - wire width 8 $1\builder_multiregimpl1_regs0[7:0] - attribute \src "ls180.v:2509.38-2509.72" - wire width 8 $1\builder_multiregimpl1_regs1[7:0] - attribute \src "ls180.v:2510.38-2510.72" - wire width 8 $1\builder_multiregimpl2_regs0[7:0] - attribute \src "ls180.v:2511.38-2511.72" - wire width 8 $1\builder_multiregimpl2_regs1[7:0] - attribute \src "ls180.v:1656.5-1656.43" - wire $1\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:1657.5-1657.43" - wire $1\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:1658.5-1658.43" - wire $1\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:1659.5-1659.43" - wire $1\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:1655.5-1655.42" - wire $1\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:2368.11-2368.36" - wire width 2 $1\builder_next_state[1:0] - attribute \src "ls180.v:1628.11-1628.46" - wire width 2 $1\builder_refresher_next_state[1:0] - attribute \src "ls180.v:1627.11-1627.41" - wire width 2 $1\builder_refresher_state[1:0] - attribute \src "ls180.v:1733.11-1733.51" - wire width 2 $1\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:1732.11-1732.46" - wire width 2 $1\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:1701.5-1701.57" - wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:1700.5-1700.52" - wire $1\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:1713.11-1713.47" - wire width 3 $1\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:1712.11-1712.42" - wire width 3 $1\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:1737.5-1737.49" - wire $1\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:1736.5-1736.44" - wire $1\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:1741.11-1741.65" - wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:1740.11-1740.60" - wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:1689.11-1689.46" - wire width 3 $1\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:1688.11-1688.41" - wire width 3 $1\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:1677.11-1677.52" - wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:1676.11-1676.47" - wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:1673.11-1673.52" - wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:1672.11-1672.47" - wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:1685.5-1685.46" - wire $1\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:1684.5-1684.41" - wire $1\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:1693.11-1693.53" - wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:1692.11-1692.48" - wire width 3 $1\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:1669.5-1669.46" - wire $1\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:1668.5-1668.41" - wire $1\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:1769.5-1769.30" - wire $1\builder_shared_ack[0:0] - attribute \src "ls180.v:1765.12-1765.40" - wire width 32 $1\builder_shared_dat_r[31:0] - attribute \src "ls180.v:1776.11-1776.35" - wire width 5 $1\builder_slave_sel[4:0] - attribute \src "ls180.v:1777.11-1777.37" - wire width 5 $1\builder_slave_sel_r[4:0] - attribute \src "ls180.v:1665.11-1665.47" - wire width 2 $1\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:1664.11-1664.42" - wire width 2 $1\builder_spimaster0_state[1:0] - attribute \src "ls180.v:1745.11-1745.47" - wire width 2 $1\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:1744.11-1744.42" - wire width 2 $1\builder_spimaster1_state[1:0] - attribute \src "ls180.v:2367.11-2367.31" - wire width 2 $1\builder_state[1:0] - attribute \src "ls180.v:2420.5-2420.39" - wire $1\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:2421.5-2421.39" - wire $1\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:2413.11-2413.47" - wire width 2 $1\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:2414.12-2414.49" - wire width 13 $1\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2415.5-2415.41" - wire $1\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:2416.5-2416.41" - wire $1\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2417.5-2417.41" - wire $1\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2418.5-2418.41" - wire $1\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2419.5-2419.41" - wire $1\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:1611.12-1611.44" - wire width 16 $1\libresocsim_clk_divider1[15:0] - attribute \src "ls180.v:1606.5-1606.34" - wire $1\libresocsim_clk_enable[0:0] - attribute \src "ls180.v:948.5-948.36" - wire $1\libresocsim_clocker_clk0[0:0] - attribute \src "ls180.v:951.5-951.36" - wire $1\libresocsim_clocker_clk1[0:0] - attribute \src "ls180.v:952.5-952.37" - wire $1\libresocsim_clocker_clk_d[0:0] - attribute \src "ls180.v:950.11-950.42" - wire width 9 $1\libresocsim_clocker_clks[8:0] - attribute \src "ls180.v:946.5-946.34" - wire $1\libresocsim_clocker_re[0:0] - attribute \src "ls180.v:945.11-945.47" - wire width 9 $1\libresocsim_clocker_storage[8:0] - attribute \src "ls180.v:1054.5-1054.50" - wire $1\libresocsim_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:1055.5-1055.49" - wire $1\libresocsim_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:1056.11-1056.63" - wire width 8 $1\libresocsim_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1052.5-1052.50" - wire $1\libresocsim_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:1039.11-1039.55" - wire width 3 $1\libresocsim_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1035.5-1035.56" - wire $1\libresocsim_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:1036.5-1036.55" - wire $1\libresocsim_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:1037.11-1037.69" - wire width 8 $1\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1038.11-1038.82" - wire width 4 $1\libresocsim_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1041.5-1041.54" - wire $1\libresocsim_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1057.5-1057.39" - wire $1\libresocsim_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:1682.5-1682.67" - wire $1\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:1683.5-1683.70" - wire $1\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:1027.5-1027.37" - wire $1\libresocsim_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:1022.5-1022.54" - wire $1\libresocsim_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:1009.11-1009.40" - wire width 8 $1\libresocsim_cmdr_count[7:0] - attribute \src "ls180.v:1678.11-1678.68" - wire width 8 $1\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:1679.5-1679.65" - wire $1\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:994.5-994.49" - wire $1\libresocsim_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:995.5-995.51" - wire $1\libresocsim_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:996.5-996.52" - wire $1\libresocsim_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1001.5-1001.38" - wire $1\libresocsim_cmdr_sink_last[0:0] - attribute \src "ls180.v:1002.11-1002.54" - wire width 8 $1\libresocsim_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:1000.5-1000.39" - wire $1\libresocsim_cmdr_sink_ready[0:0] - attribute \src "ls180.v:999.5-999.39" - wire $1\libresocsim_cmdr_sink_valid[0:0] - attribute \src "ls180.v:1005.5-1005.40" - wire $1\libresocsim_cmdr_source_last[0:0] - attribute \src "ls180.v:1006.11-1006.54" - wire width 8 $1\libresocsim_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:1007.11-1007.56" - wire width 3 $1\libresocsim_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:1004.5-1004.41" - wire $1\libresocsim_cmdr_source_ready[0:0] - attribute \src "ls180.v:1003.5-1003.41" - wire $1\libresocsim_cmdr_source_valid[0:0] - attribute \src "ls180.v:1008.12-1008.49" - wire width 32 $1\libresocsim_cmdr_timeout[31:0] - attribute \src "ls180.v:1680.12-1680.72" - wire width 32 $1\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:1681.5-1681.67" - wire $1\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:981.11-981.40" - wire width 8 $1\libresocsim_cmdw_count[7:0] - attribute \src "ls180.v:1674.11-1674.67" - wire width 8 $1\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:1675.5-1675.64" - wire $1\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:980.5-980.33" - wire $1\libresocsim_cmdw_done[0:0] - attribute \src "ls180.v:971.5-971.49" - wire $1\libresocsim_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:972.5-972.51" - wire $1\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:973.5-973.52" - wire $1\libresocsim_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:978.5-978.38" - wire $1\libresocsim_cmdw_sink_last[0:0] - attribute \src "ls180.v:979.11-979.52" - wire width 8 $1\libresocsim_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:977.5-977.39" - wire $1\libresocsim_cmdw_sink_ready[0:0] - attribute \src "ls180.v:976.5-976.39" - wire $1\libresocsim_cmdw_sink_valid[0:0] - attribute \src "ls180.v:1593.5-1593.34" - wire $1\libresocsim_control_re[0:0] - attribute \src "ls180.v:1592.12-1592.47" - wire width 16 $1\libresocsim_control_storage[15:0] - attribute \src "ls180.v:1608.11-1608.35" - wire width 3 $1\libresocsim_count[2:0] - attribute \src "ls180.v:1746.11-1746.57" - wire width 3 $1\libresocsim_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:1747.5-1747.54" - wire $1\libresocsim_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:1607.5-1607.33" - wire $1\libresocsim_cs_enable[0:0] - attribute \src "ls180.v:1603.5-1603.29" - wire $1\libresocsim_cs_re[0:0] - attribute \src "ls180.v:1602.5-1602.34" - wire $1\libresocsim_cs_storage[0:0] - attribute \src "ls180.v:1165.11-1165.42" - wire width 10 $1\libresocsim_datar_count[9:0] - attribute \src "ls180.v:1694.11-1694.71" - wire width 10 $1\libresocsim_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:1695.5-1695.67" - wire $1\libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:1210.5-1210.52" - wire $1\libresocsim_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:1211.5-1211.51" - wire $1\libresocsim_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:1212.11-1212.65" - wire width 8 $1\libresocsim_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:1208.5-1208.52" - wire $1\libresocsim_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:1195.5-1195.51" - wire $1\libresocsim_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1191.5-1191.58" - wire $1\libresocsim_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:1192.5-1192.57" - wire $1\libresocsim_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:1193.11-1193.71" - wire width 8 $1\libresocsim_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:1194.11-1194.84" - wire width 2 $1\libresocsim_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:1197.5-1197.56" - wire $1\libresocsim_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1213.5-1213.41" - wire $1\libresocsim_datar_datar_reset[0:0] - attribute \src "ls180.v:1698.5-1698.70" - wire $1\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:1699.5-1699.73" - wire $1\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:1183.5-1183.39" - wire $1\libresocsim_datar_datar_run[0:0] - attribute \src "ls180.v:1178.5-1178.56" - wire $1\libresocsim_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1148.5-1148.50" - wire $1\libresocsim_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1155.5-1155.39" - wire $1\libresocsim_datar_sink_last[0:0] - attribute \src "ls180.v:1156.11-1156.62" - wire width 10 $1\libresocsim_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:1154.5-1154.40" - wire $1\libresocsim_datar_sink_ready[0:0] - attribute \src "ls180.v:1153.5-1153.40" - wire $1\libresocsim_datar_sink_valid[0:0] - attribute \src "ls180.v:1160.5-1160.41" - wire $1\libresocsim_datar_source_last[0:0] - attribute \src "ls180.v:1161.11-1161.55" - wire width 8 $1\libresocsim_datar_source_payload_data[7:0] - attribute \src "ls180.v:1162.11-1162.57" - wire width 3 $1\libresocsim_datar_source_payload_status[2:0] - attribute \src "ls180.v:1158.5-1158.42" - wire $1\libresocsim_datar_source_ready[0:0] - attribute \src "ls180.v:1157.5-1157.42" - wire $1\libresocsim_datar_source_valid[0:0] - attribute \src "ls180.v:1163.5-1163.34" - wire $1\libresocsim_datar_stop[0:0] - attribute \src "ls180.v:1164.12-1164.50" - wire width 32 $1\libresocsim_datar_timeout[31:0] - attribute \src "ls180.v:1696.12-1696.74" - wire width 32 $1\libresocsim_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:1697.5-1697.69" - wire $1\libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:1073.11-1073.41" - wire width 8 $1\libresocsim_dataw_count[7:0] - attribute \src "ls180.v:1690.11-1690.62" - wire width 8 $1\libresocsim_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:1691.5-1691.59" - wire $1\libresocsim_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1132.5-1132.51" - wire $1\libresocsim_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:1133.5-1133.50" - wire $1\libresocsim_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:1134.11-1134.64" - wire width 8 $1\libresocsim_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1130.5-1130.51" - wire $1\libresocsim_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:1117.11-1117.56" - wire width 3 $1\libresocsim_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1113.5-1113.57" - wire $1\libresocsim_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:1114.5-1114.56" - wire $1\libresocsim_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:1115.11-1115.70" - wire width 8 $1\libresocsim_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1116.11-1116.83" - wire width 4 $1\libresocsim_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1119.5-1119.55" - wire $1\libresocsim_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1135.5-1135.40" - wire $1\libresocsim_dataw_crcr_reset[0:0] - attribute \src "ls180.v:1686.5-1686.67" - wire $1\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:1687.5-1687.70" - wire $1\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:1105.5-1105.38" - wire $1\libresocsim_dataw_crcr_run[0:0] - attribute \src "ls180.v:1100.5-1100.55" - wire $1\libresocsim_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:1087.5-1087.35" - wire $1\libresocsim_dataw_error[0:0] - attribute \src "ls180.v:1062.5-1062.50" - wire $1\libresocsim_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1065.11-1065.59" - wire width 4 $1\libresocsim_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1066.5-1066.54" - wire $1\libresocsim_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1069.5-1069.40" - wire $1\libresocsim_dataw_sink_first[0:0] - attribute \src "ls180.v:1070.5-1070.39" - wire $1\libresocsim_dataw_sink_last[0:0] - attribute \src "ls180.v:1071.11-1071.53" - wire width 8 $1\libresocsim_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:1068.5-1068.40" - wire $1\libresocsim_dataw_sink_ready[0:0] - attribute \src "ls180.v:1067.5-1067.40" - wire $1\libresocsim_dataw_sink_valid[0:0] - attribute \src "ls180.v:1085.5-1085.35" - wire $1\libresocsim_dataw_start[0:0] - attribute \src "ls180.v:1072.5-1072.34" - wire $1\libresocsim_dataw_stop[0:0] - attribute \src "ls180.v:1086.5-1086.35" - wire $1\libresocsim_dataw_valid[0:0] - attribute \src "ls180.v:1583.5-1583.29" - wire $1\libresocsim_done0[0:0] - attribute \src "ls180.v:966.11-966.40" - wire width 8 $1\libresocsim_init_count[7:0] - attribute \src "ls180.v:1670.11-1670.67" - wire width 8 $1\libresocsim_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:1671.5-1671.64" - wire $1\libresocsim_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:961.5-961.49" - wire $1\libresocsim_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:962.5-962.51" - wire $1\libresocsim_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:963.5-963.52" - wire $1\libresocsim_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:964.11-964.58" - wire width 4 $1\libresocsim_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:965.5-965.53" - wire $1\libresocsim_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1487.12-1487.50" - wire width 32 $1\libresocsim_interface1_bus_adr[31:0] - attribute \src "ls180.v:1491.5-1491.42" - wire $1\libresocsim_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1490.11-1490.48" - wire width 4 $1\libresocsim_interface1_bus_sel[3:0] - attribute \src "ls180.v:1492.5-1492.42" - wire $1\libresocsim_interface1_bus_stb[0:0] - attribute \src "ls180.v:1494.5-1494.41" - wire $1\libresocsim_interface1_bus_we[0:0] - attribute \src "ls180.v:1584.5-1584.27" - wire $1\libresocsim_irq[0:0] - attribute \src "ls180.v:1605.5-1605.35" - wire $1\libresocsim_loopback_re[0:0] - attribute \src "ls180.v:1604.5-1604.40" - wire $1\libresocsim_loopback_storage[0:0] - attribute \src "ls180.v:1586.11-1586.34" - wire width 8 $1\libresocsim_miso[7:0] - attribute \src "ls180.v:1616.11-1616.39" - wire width 8 $1\libresocsim_miso_data[7:0] - attribute \src "ls180.v:1610.5-1610.34" - wire $1\libresocsim_miso_latch[0:0] - attribute \src "ls180.v:1614.11-1614.39" - wire width 8 $1\libresocsim_mosi_data[7:0] - attribute \src "ls180.v:1609.5-1609.34" - wire $1\libresocsim_mosi_latch[0:0] - attribute \src "ls180.v:1598.5-1598.31" - wire $1\libresocsim_mosi_re[0:0] - attribute \src "ls180.v:1615.11-1615.38" - wire width 3 $1\libresocsim_mosi_sel[2:0] - attribute \src "ls180.v:1597.11-1597.42" - wire width 8 $1\libresocsim_mosi_storage[7:0] - attribute \src "ls180.v:1618.5-1618.26" - wire $1\libresocsim_re[0:0] - attribute \src "ls180.v:1456.11-1456.57" - wire width 2 $1\libresocsim_sdblock2mem_converter_demux[1:0] - attribute \src "ls180.v:1452.5-1452.58" - wire $1\libresocsim_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:1453.5-1453.57" - wire $1\libresocsim_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:1454.12-1454.73" - wire width 32 $1\libresocsim_sdblock2mem_converter_source_payload_data[31:0] - attribute \src "ls180.v:1455.11-1455.84" - wire width 3 $1\libresocsim_sdblock2mem_converter_source_payload_valid_token_count[2:0] - attribute \src "ls180.v:1458.5-1458.56" - wire $1\libresocsim_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:1431.11-1431.54" - wire width 5 $1\libresocsim_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:1428.11-1428.52" - wire width 6 $1\libresocsim_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:1430.11-1430.54" - wire width 5 $1\libresocsim_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1432.11-1432.57" - wire width 5 $1\libresocsim_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1466.12-1466.69" - wire width 32 $1\libresocsim_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:1467.12-1467.67" - wire width 32 $1\libresocsim_sdblock2mem_sink_sink_payload_data1[31:0] - attribute \src "ls180.v:1464.5-1464.52" - wire $1\libresocsim_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:1474.5-1474.61" - wire $1\libresocsim_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:1473.12-1473.74" - wire width 64 $1\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:1478.5-1478.63" - wire $1\libresocsim_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:1477.5-1477.68" - wire $1\libresocsim_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:1476.5-1476.63" - wire $1\libresocsim_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:1475.12-1475.76" - wire width 32 $1\libresocsim_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:1482.5-1482.61" - wire $1\libresocsim_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:1481.5-1481.66" - wire $1\libresocsim_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:1484.12-1484.68" - wire width 32 $1\libresocsim_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:1734.12-1734.94" - wire width 32 $1\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:1735.5-1735.89" - wire $1\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:1469.5-1469.64" - wire $1\libresocsim_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:1479.5-1479.60" - wire $1\libresocsim_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:1248.5-1248.45" - wire $1\libresocsim_sdcore_block_count_re[0:0] - attribute \src "ls180.v:1247.12-1247.58" - wire width 32 $1\libresocsim_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:1246.5-1246.46" - wire $1\libresocsim_sdcore_block_length_re[0:0] - attribute \src "ls180.v:1245.11-1245.58" - wire width 10 $1\libresocsim_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:1232.5-1232.46" - wire $1\libresocsim_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:1231.12-1231.59" - wire width 32 $1\libresocsim_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:1234.5-1234.45" - wire $1\libresocsim_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:1233.12-1233.58" - wire width 32 $1\libresocsim_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:1387.11-1387.46" - wire width 3 $1\libresocsim_sdcore_cmd_count[2:0] - attribute \src "ls180.v:1718.11-1718.69" - wire width 3 $1\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:1719.5-1719.66" - wire $1\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:1388.5-1388.39" - wire $1\libresocsim_sdcore_cmd_done[0:0] - attribute \src "ls180.v:1714.5-1714.62" - wire $1\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:1715.5-1715.65" - wire $1\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:1389.5-1389.40" - wire $1\libresocsim_sdcore_cmd_error[0:0] - attribute \src "ls180.v:1722.5-1722.63" - wire $1\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:1723.5-1723.66" - wire $1\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:1239.13-1239.60" - wire width 128 $1\libresocsim_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:1730.13-1730.83" - wire width 128 $1\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:1731.5-1731.76" - wire $1\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1390.5-1390.42" - wire $1\libresocsim_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:1724.5-1724.65" - wire $1\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:1725.5-1725.68" - wire $1\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:1348.11-1348.54" - wire width 4 $1\libresocsim_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:1354.5-1354.53" - wire $1\libresocsim_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:1353.12-1353.61" - wire width 16 $1\libresocsim_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:1349.12-1349.65" - wire width 16 $1\libresocsim_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:1361.5-1361.53" - wire $1\libresocsim_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:1360.12-1360.61" - wire width 16 $1\libresocsim_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:1356.12-1356.65" - wire width 16 $1\libresocsim_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:1368.5-1368.53" - wire $1\libresocsim_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:1367.12-1367.61" - wire width 16 $1\libresocsim_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:1363.12-1363.65" - wire width 16 $1\libresocsim_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:1375.5-1375.53" - wire $1\libresocsim_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:1374.12-1374.61" - wire width 16 $1\libresocsim_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:1370.12-1370.65" - wire width 16 $1\libresocsim_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:1377.12-1377.60" - wire width 16 $1\libresocsim_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:1378.12-1378.60" - wire width 16 $1\libresocsim_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:1379.12-1379.60" - wire width 16 $1\libresocsim_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:1380.12-1380.60" - wire width 16 $1\libresocsim_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:1382.12-1382.58" - wire width 16 $1\libresocsim_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:1383.12-1383.58" - wire width 16 $1\libresocsim_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:1384.12-1384.58" - wire width 16 $1\libresocsim_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:1385.12-1385.58" - wire width 16 $1\libresocsim_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:1339.5-1339.55" - wire $1\libresocsim_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:1340.5-1340.54" - wire $1\libresocsim_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:1341.11-1341.68" - wire width 8 $1\libresocsim_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:1338.5-1338.55" - wire $1\libresocsim_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:1337.5-1337.55" - wire $1\libresocsim_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1342.5-1342.57" - wire $1\libresocsim_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:1347.11-1347.54" - wire width 8 $1\libresocsim_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:1381.5-1381.50" - wire $1\libresocsim_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:1304.11-1304.55" - wire width 3 $1\libresocsim_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:1710.11-1710.94" - wire width 3 $1\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:1711.5-1711.91" - wire $1\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:1309.12-1309.62" - wire width 16 $1\libresocsim_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:1305.12-1305.66" - wire width 16 $1\libresocsim_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:1316.12-1316.62" - wire width 16 $1\libresocsim_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:1312.12-1312.66" - wire width 16 $1\libresocsim_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:1323.12-1323.62" - wire width 16 $1\libresocsim_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:1319.12-1319.66" - wire width 16 $1\libresocsim_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:1330.12-1330.62" - wire width 16 $1\libresocsim_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:1326.12-1326.66" - wire width 16 $1\libresocsim_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:1333.12-1333.61" - wire width 16 $1\libresocsim_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:1702.12-1702.100" - wire width 16 $1\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:1703.5-1703.95" - wire $1\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:1334.12-1334.61" - wire width 16 $1\libresocsim_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:1704.12-1704.100" - wire width 16 $1\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:1705.5-1705.95" - wire $1\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:1335.12-1335.61" - wire width 16 $1\libresocsim_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:1706.12-1706.100" - wire width 16 $1\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:1707.5-1707.95" - wire $1\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:1336.12-1336.61" - wire width 16 $1\libresocsim_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:1708.12-1708.100" - wire width 16 $1\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:1709.5-1709.95" - wire $1\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:1295.5-1295.56" - wire $1\libresocsim_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1302.5-1302.57" - wire $1\libresocsim_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:1303.11-1303.71" - wire width 8 $1\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:1300.5-1300.58" - wire $1\libresocsim_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:1299.5-1299.58" - wire $1\libresocsim_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:1291.11-1291.54" - wire width 7 $1\libresocsim_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:1249.11-1249.58" - wire width 7 $1\libresocsim_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:1392.12-1392.49" - wire width 32 $1\libresocsim_sdcore_data_count[31:0] - attribute \src "ls180.v:1720.12-1720.72" - wire width 32 $1\libresocsim_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:1721.5-1721.67" - wire $1\libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:1393.5-1393.40" - wire $1\libresocsim_sdcore_data_done[0:0] - attribute \src "ls180.v:1716.5-1716.63" - wire $1\libresocsim_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:1717.5-1717.66" - wire $1\libresocsim_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:1394.5-1394.41" - wire $1\libresocsim_sdcore_data_error[0:0] - attribute \src "ls180.v:1726.5-1726.64" - wire $1\libresocsim_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:1727.5-1727.67" - wire $1\libresocsim_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:1395.5-1395.43" - wire $1\libresocsim_sdcore_data_timeout[0:0] - attribute \src "ls180.v:1728.5-1728.66" - wire $1\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:1729.5-1729.69" - wire $1\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:1540.11-1540.55" - wire width 2 $1\libresocsim_sdmem2block_converter_mux[1:0] - attribute \src "ls180.v:1538.11-1538.71" - wire width 8 $1\libresocsim_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:1514.5-1514.47" - wire $1\libresocsim_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:1513.12-1513.60" - wire width 64 $1\libresocsim_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:1512.12-1512.52" - wire width 32 $1\libresocsim_sdmem2block_dma_data[31:0] - attribute \src "ls180.v:1738.12-1738.82" - wire width 32 $1\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] - attribute \src "ls180.v:1739.5-1739.77" - wire $1\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1519.5-1519.51" - wire $1\libresocsim_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:1518.5-1518.49" - wire $1\libresocsim_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:1517.5-1517.54" - wire $1\libresocsim_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:1516.5-1516.49" - wire $1\libresocsim_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:1515.12-1515.62" - wire width 32 $1\libresocsim_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:1522.5-1522.47" - wire $1\libresocsim_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:1521.5-1521.52" - wire $1\libresocsim_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:1526.12-1526.54" - wire width 32 $1\libresocsim_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:1742.12-1742.94" - wire width 32 $1\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:1743.5-1743.89" - wire $1\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:1505.5-1505.49" - wire $1\libresocsim_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:1506.12-1506.68" - wire width 32 $1\libresocsim_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:1504.5-1504.50" - wire $1\libresocsim_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:1503.5-1503.50" - wire $1\libresocsim_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1510.5-1510.51" - wire $1\libresocsim_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:1511.12-1511.67" - wire width 32 $1\libresocsim_sdmem2block_dma_source_payload_data[31:0] - attribute \src "ls180.v:1507.5-1507.52" - wire $1\libresocsim_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:1567.11-1567.54" - wire width 5 $1\libresocsim_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:1564.11-1564.52" - wire width 6 $1\libresocsim_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:1566.11-1566.54" - wire width 5 $1\libresocsim_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1568.11-1568.57" - wire width 5 $1\libresocsim_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1215.5-1215.36" - wire $1\libresocsim_sdpads_cmd_i[0:0] - attribute \src "ls180.v:1218.11-1218.43" - wire width 4 $1\libresocsim_sdpads_data_i[3:0] - attribute \src "ls180.v:1590.5-1590.30" - wire $1\libresocsim_start1[0:0] - attribute \src "ls180.v:1617.12-1617.41" - wire width 16 $1\libresocsim_storage[15:0] - attribute \src "ls180.v:937.12-937.37" - wire width 16 $1\main_clk_divider1[15:0] - attribute \src "ls180.v:932.5-932.27" - wire $1\main_clk_enable[0:0] - attribute \src "ls180.v:898.5-898.29" - wire $1\main_cmd_consumed[0:0] - attribute \src "ls180.v:919.5-919.27" - wire $1\main_control_re[0:0] - attribute \src "ls180.v:918.12-918.40" - wire width 16 $1\main_control_storage[15:0] - attribute \src "ls180.v:895.5-895.34" - wire $1\main_converter_counter[0:0] - attribute \src "ls180.v:1662.5-1662.55" - wire $1\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:1663.5-1663.58" - wire $1\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:897.12-897.40" - wire width 32 $1\main_converter_dat_r[31:0] - attribute \src "ls180.v:894.5-894.31" - wire $1\main_converter_skip[0:0] - attribute \src "ls180.v:934.11-934.28" - wire width 3 $1\main_count[2:0] - attribute \src "ls180.v:1666.11-1666.50" - wire width 3 $1\main_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:1667.5-1667.47" - wire $1\main_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:933.5-933.26" - wire $1\main_cs_enable[0:0] - attribute \src "ls180.v:929.5-929.22" - wire $1\main_cs_re[0:0] - attribute \src "ls180.v:928.5-928.27" - wire $1\main_cs_storage[0:0] - attribute \src "ls180.v:329.12-329.38" - wire width 16 $1\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:330.5-330.36" - wire $1\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:909.5-909.22" - wire $1\main_done0[0:0] - attribute \src "ls180.v:314.5-314.24" - wire $1\main_int_rst[0:0] - attribute \src "ls180.v:910.5-910.20" - wire $1\main_irq[0:0] - attribute \src "ls180.v:109.5-109.47" - wire $1\main_libresocsim_converter0_counter[0:0] - attribute \src "ls180.v:1621.5-1621.69" - wire $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:1622.5-1622.72" - wire $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:111.12-111.53" - wire width 64 $1\main_libresocsim_converter0_dat_r[63:0] - attribute \src "ls180.v:108.5-108.44" - wire $1\main_libresocsim_converter0_skip[0:0] - attribute \src "ls180.v:124.5-124.47" - wire $1\main_libresocsim_converter1_counter[0:0] - attribute \src "ls180.v:1625.5-1625.69" - wire $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:1626.5-1626.72" - wire $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:126.12-126.53" - wire width 64 $1\main_libresocsim_converter1_dat_r[63:0] - attribute \src "ls180.v:123.5-123.44" - wire $1\main_libresocsim_converter1_skip[0:0] - attribute \src "ls180.v:97.12-97.71" - wire width 30 $1\main_libresocsim_interface0_converted_interface_adr[29:0] - attribute \src "ls180.v:101.5-101.63" - wire $1\main_libresocsim_interface0_converted_interface_cyc[0:0] - attribute \src "ls180.v:98.12-98.73" - wire width 32 $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] - attribute \src "ls180.v:100.11-100.69" - wire width 4 $1\main_libresocsim_interface0_converted_interface_sel[3:0] - attribute \src "ls180.v:102.5-102.63" - wire $1\main_libresocsim_interface0_converted_interface_stb[0:0] - attribute \src "ls180.v:104.5-104.62" - wire $1\main_libresocsim_interface0_converted_interface_we[0:0] - attribute \src "ls180.v:112.12-112.71" - wire width 30 $1\main_libresocsim_interface1_converted_interface_adr[29:0] - attribute \src "ls180.v:116.5-116.63" - wire $1\main_libresocsim_interface1_converted_interface_cyc[0:0] - attribute \src "ls180.v:113.12-113.73" - wire width 32 $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] - attribute \src "ls180.v:115.11-115.69" - wire width 4 $1\main_libresocsim_interface1_converted_interface_sel[3:0] - attribute \src "ls180.v:117.5-117.63" - wire $1\main_libresocsim_interface1_converted_interface_stb[0:0] - attribute \src "ls180.v:119.5-119.62" - wire $1\main_libresocsim_interface1_converted_interface_we[0:0] - attribute \src "ls180.v:50.5-50.46" - wire $1\main_libresocsim_libresoc_dbus_ack[0:0] - attribute \src "ls180.v:61.5-61.46" - wire $1\main_libresocsim_libresoc_ibus_ack[0:0] - attribute \src "ls180.v:43.12-43.55" - wire width 16 $1\main_libresocsim_libresoc_interrupt[15:0] - attribute \src "ls180.v:160.12-160.57" - wire width 32 $1\main_libresocsim_phase_accumulator_rx[31:0] - attribute \src "ls180.v:150.12-150.57" - wire width 32 $1\main_libresocsim_phase_accumulator_tx[31:0] - attribute \src "ls180.v:133.5-133.40" - wire $1\main_libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:143.5-143.31" - wire $1\main_libresocsim_re[0:0] - attribute \src "ls180.v:164.11-164.46" - wire width 4 $1\main_libresocsim_rx_bitcount[3:0] - attribute \src "ls180.v:165.5-165.36" - wire $1\main_libresocsim_rx_busy[0:0] - attribute \src "ls180.v:162.5-162.33" - wire $1\main_libresocsim_rx_r[0:0] - attribute \src "ls180.v:163.11-163.41" - wire width 8 $1\main_libresocsim_rx_reg[7:0] - attribute \src "ls180.v:145.5-145.39" - wire $1\main_libresocsim_sink_ready[0:0] - attribute \src "ls180.v:41.12-41.61" - wire width 32 $1\main_libresocsim_soccontroller_bus_errors[31:0] - attribute \src "ls180.v:34.5-34.51" - wire $1\main_libresocsim_soccontroller_reset_re[0:0] - attribute \src "ls180.v:33.5-33.56" - wire $1\main_libresocsim_soccontroller_reset_storage[0:0] - attribute \src "ls180.v:36.5-36.53" - wire $1\main_libresocsim_soccontroller_scratch_re[0:0] - attribute \src "ls180.v:35.12-35.74" - wire width 32 $1\main_libresocsim_soccontroller_scratch_storage[31:0] - attribute \src "ls180.v:158.11-158.54" - wire width 8 $1\main_libresocsim_source_payload_data[7:0] - attribute \src "ls180.v:154.5-154.41" - wire $1\main_libresocsim_source_valid[0:0] - attribute \src "ls180.v:142.12-142.50" - wire width 32 $1\main_libresocsim_storage[31:0] - attribute \src "ls180.v:289.5-289.40" - wire $1\main_libresocsim_timer_en_re[0:0] - attribute \src "ls180.v:288.5-288.45" - wire $1\main_libresocsim_timer_en_storage[0:0] - attribute \src "ls180.v:309.5-309.50" - wire $1\main_libresocsim_timer_eventmanager_re[0:0] - attribute \src "ls180.v:308.5-308.55" - wire $1\main_libresocsim_timer_eventmanager_storage[0:0] - attribute \src "ls180.v:285.5-285.42" - wire $1\main_libresocsim_timer_load_re[0:0] - attribute \src "ls180.v:284.12-284.55" - wire width 32 $1\main_libresocsim_timer_load_storage[31:0] - attribute \src "ls180.v:287.5-287.44" - wire $1\main_libresocsim_timer_reload_re[0:0] - attribute \src "ls180.v:286.12-286.57" - wire width 32 $1\main_libresocsim_timer_reload_storage[31:0] - attribute \src "ls180.v:291.5-291.50" - wire $1\main_libresocsim_timer_update_value_re[0:0] - attribute \src "ls180.v:290.5-290.55" - wire $1\main_libresocsim_timer_update_value_storage[0:0] - attribute \src "ls180.v:310.12-310.48" - wire width 32 $1\main_libresocsim_timer_value[31:0] - attribute \src "ls180.v:292.12-292.55" - wire width 32 $1\main_libresocsim_timer_value_status[31:0] - attribute \src "ls180.v:298.5-298.45" - wire $1\main_libresocsim_timer_zero_clear[0:0] - attribute \src "ls180.v:299.5-299.51" - wire $1\main_libresocsim_timer_zero_old_trigger[0:0] - attribute \src "ls180.v:296.5-296.47" - wire $1\main_libresocsim_timer_zero_pending[0:0] - attribute \src "ls180.v:152.11-152.46" - wire width 4 $1\main_libresocsim_tx_bitcount[3:0] - attribute \src "ls180.v:153.5-153.36" - wire $1\main_libresocsim_tx_busy[0:0] - attribute \src "ls180.v:151.11-151.41" - wire width 8 $1\main_libresocsim_tx_reg[7:0] - attribute \src "ls180.v:159.5-159.42" - wire $1\main_libresocsim_uart_clk_rxen[0:0] - attribute \src "ls180.v:149.5-149.42" - wire $1\main_libresocsim_uart_clk_txen[0:0] - attribute \src "ls180.v:192.11-192.62" - wire width 2 $1\main_libresocsim_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:194.5-194.49" - wire $1\main_libresocsim_uart_eventmanager_re[0:0] - attribute \src "ls180.v:188.11-188.61" - wire width 2 $1\main_libresocsim_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:193.11-193.60" - wire width 2 $1\main_libresocsim_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:183.5-183.42" - wire $1\main_libresocsim_uart_rx_clear[0:0] - attribute \src "ls180.v:267.11-267.55" - wire width 4 $1\main_libresocsim_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:264.11-264.54" - wire width 5 $1\main_libresocsim_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:266.11-266.55" - wire width 4 $1\main_libresocsim_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:257.5-257.50" - wire $1\main_libresocsim_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:268.11-268.58" - wire width 4 $1\main_libresocsim_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:184.5-184.48" - wire $1\main_libresocsim_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:181.5-181.44" - wire $1\main_libresocsim_uart_rx_pending[0:0] - attribute \src "ls180.v:178.5-178.42" - wire $1\main_libresocsim_uart_tx_clear[0:0] - attribute \src "ls180.v:230.11-230.55" - wire width 4 $1\main_libresocsim_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:227.11-227.54" - wire width 5 $1\main_libresocsim_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:229.11-229.55" - wire width 4 $1\main_libresocsim_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:220.5-220.50" - wire $1\main_libresocsim_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:231.11-231.58" - wire width 4 $1\main_libresocsim_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:179.5-179.48" - wire $1\main_libresocsim_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:176.5-176.44" - wire $1\main_libresocsim_uart_tx_pending[0:0] - attribute \src "ls180.v:140.11-140.37" - wire width 4 $1\main_libresocsim_we[3:0] - attribute \src "ls180.v:886.12-886.40" - wire width 30 $1\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:890.5-890.32" - wire $1\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:887.12-887.42" - wire width 16 $1\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:889.11-889.38" - wire width 2 $1\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:891.5-891.32" - wire $1\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:893.5-893.31" - wire $1\main_litedram_wb_we[0:0] - attribute \src "ls180.v:931.5-931.28" - wire $1\main_loopback_re[0:0] - attribute \src "ls180.v:930.5-930.33" - wire $1\main_loopback_storage[0:0] - attribute \src "ls180.v:912.11-912.27" - wire width 8 $1\main_miso[7:0] - attribute \src "ls180.v:942.11-942.32" - wire width 8 $1\main_miso_data[7:0] - attribute \src "ls180.v:936.5-936.27" - wire $1\main_miso_latch[0:0] - attribute \src "ls180.v:940.11-940.32" - wire width 8 $1\main_mosi_data[7:0] - attribute \src "ls180.v:935.5-935.27" - wire $1\main_mosi_latch[0:0] - attribute \src "ls180.v:924.5-924.24" - wire $1\main_mosi_re[0:0] - attribute \src "ls180.v:941.11-941.31" - wire width 3 $1\main_mosi_sel[2:0] - attribute \src "ls180.v:923.11-923.35" - wire width 8 $1\main_mosi_storage[7:0] - attribute \src "ls180.v:331.11-331.32" - wire width 3 $1\main_rddata_en[2:0] - attribute \src "ls180.v:393.5-393.33" - wire $1\main_sdram_address_re[0:0] - attribute \src "ls180.v:392.12-392.46" - wire width 13 $1\main_sdram_address_storage[12:0] - attribute \src "ls180.v:395.5-395.34" - wire $1\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:394.11-394.45" - wire width 2 $1\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:491.5-491.50" - wire $1\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:513.11-513.70" - wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:510.11-510.68" - wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:512.11-512.70" - wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:514.11-514.73" - wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:537.5-537.59" - wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:538.5-538.58" - wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:540.12-540.74" - wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:539.5-539.64" - wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:535.5-535.59" - wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:483.12-483.57" - wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:485.5-485.51" - wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:488.5-488.54" - wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:489.5-489.55" - wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:490.5-490.56" - wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:486.5-486.51" - wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:487.5-487.50" - wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:482.5-482.45" - wire $1\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:481.5-481.45" - wire $1\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:480.5-480.47" - wire $1\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:478.5-478.51" - wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:477.5-477.51" - wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:541.12-541.47" - wire width 13 $1\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:545.5-545.45" - wire $1\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:546.5-546.54" - wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:544.5-544.44" - wire $1\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:542.5-542.46" - wire $1\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:549.11-549.55" - wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:548.32-548.76" - wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:573.5-573.50" - wire $1\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:595.11-595.70" - wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:592.11-592.68" - wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:594.11-594.70" - wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:596.11-596.73" - wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:619.5-619.59" - wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:620.5-620.58" - wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:622.12-622.74" - wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:621.5-621.64" - wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:617.5-617.59" - wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:565.12-565.57" - wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:567.5-567.51" - wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:570.5-570.54" - wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:571.5-571.55" - wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:572.5-572.56" - wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:568.5-568.51" - wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:569.5-569.50" - wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:564.5-564.45" - wire $1\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:563.5-563.45" - wire $1\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:562.5-562.47" - wire $1\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:560.5-560.51" - wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:559.5-559.51" - wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:623.12-623.47" - wire width 13 $1\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:627.5-627.45" - wire $1\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:628.5-628.54" - wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:626.5-626.44" - wire $1\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:624.5-624.46" - wire $1\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:631.11-631.55" - wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:630.32-630.76" - wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:655.5-655.50" - wire $1\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:677.11-677.70" - wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:674.11-674.68" - wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:676.11-676.70" - wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:678.11-678.73" - wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:701.5-701.59" - wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:702.5-702.58" - wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:704.12-704.74" - wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:703.5-703.64" - wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:699.5-699.59" - wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:647.12-647.57" - wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:649.5-649.51" - wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:652.5-652.54" - wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:653.5-653.55" - wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:654.5-654.56" - wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:650.5-650.51" - wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:651.5-651.50" - wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:646.5-646.45" - wire $1\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:645.5-645.45" - wire $1\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:644.5-644.47" - wire $1\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:642.5-642.51" - wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:641.5-641.51" - wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:705.12-705.47" - wire width 13 $1\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:709.5-709.45" - wire $1\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:710.5-710.54" - wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:708.5-708.44" - wire $1\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:706.5-706.46" - wire $1\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:713.11-713.55" - wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:712.32-712.76" - wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:737.5-737.50" - wire $1\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:759.11-759.70" - wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:756.11-756.68" - wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:758.11-758.70" - wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:760.11-760.73" - wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:783.5-783.59" - wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:784.5-784.58" - wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:786.12-786.74" - wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:785.5-785.64" - wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:781.5-781.59" - wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:729.12-729.57" - wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:731.5-731.51" - wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:734.5-734.54" - wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:735.5-735.55" - wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:736.5-736.56" - wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:732.5-732.51" - wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:733.5-733.50" - wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:728.5-728.45" - wire $1\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:727.5-727.45" - wire $1\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:726.5-726.47" - wire $1\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:724.5-724.51" - wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:723.5-723.51" - wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:787.12-787.47" - wire width 13 $1\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:791.5-791.45" - wire $1\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:792.5-792.54" - wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:790.5-790.44" - wire $1\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:788.5-788.46" - wire $1\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:795.11-795.55" - wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:794.32-794.76" - wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:810.5-810.49" - wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:811.5-811.49" - wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:812.5-812.48" - wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:818.11-818.45" - wire width 2 $1\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:816.11-816.46" - wire width 4 $1\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:828.5-828.49" - wire $1\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:829.5-829.49" - wire $1\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:830.5-830.48" - wire $1\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:825.5-825.43" - wire $1\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:836.11-836.45" - wire width 2 $1\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:834.11-834.46" - wire width 4 $1\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:823.5-823.48" - wire $1\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:820.5-820.44" - wire $1\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:821.5-821.45" - wire $1\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:449.5-449.31" - wire $1\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:450.12-450.44" - wire width 13 $1\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:451.11-451.43" - wire width 2 $1\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:452.5-452.38" - wire $1\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:453.5-453.38" - wire $1\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:454.5-454.37" - wire $1\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:448.5-448.32" - wire $1\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:447.5-447.32" - wire $1\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:387.5-387.33" - wire $1\main_sdram_command_re[0:0] - attribute \src "ls180.v:386.11-386.44" - wire width 6 $1\main_sdram_command_storage[5:0] - attribute \src "ls180.v:431.12-431.45" - wire width 13 $1\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:432.11-432.40" - wire width 2 $1\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:433.5-433.35" - wire $1\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:434.5-434.34" - wire $1\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:435.5-435.35" - wire $1\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:444.5-444.39" - wire $1\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:436.5-436.34" - wire $1\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:442.5-442.39" - wire $1\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:855.5-855.26" - wire $1\main_sdram_en0[0:0] - attribute \src "ls180.v:858.5-858.26" - wire $1\main_sdram_en1[0:0] - attribute \src "ls180.v:428.12-428.46" - wire width 16 $1\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:429.11-429.47" - wire width 2 $1\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:334.5-334.36" - wire $1\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:335.5-335.35" - wire $1\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:336.5-336.36" - wire $1\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:346.12-346.45" - wire width 16 $1\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:347.5-347.43" - wire $1\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:337.5-337.35" - wire $1\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:373.5-373.38" - wire $1\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:364.12-364.48" - wire width 13 $1\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:365.11-365.43" - wire width 2 $1\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:366.5-366.38" - wire $1\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:370.5-370.36" - wire $1\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:367.5-367.37" - wire $1\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:371.5-371.36" - wire $1\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:368.5-368.38" - wire $1\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:377.5-377.42" - wire $1\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:372.5-372.40" - wire $1\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:369.5-369.37" - wire $1\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:374.12-374.47" - wire width 16 $1\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:375.5-375.42" - wire $1\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:376.11-376.50" - wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:465.5-465.38" - wire $1\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:464.5-464.38" - wire $1\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:385.5-385.25" - wire $1\main_sdram_re[0:0] - attribute \src "ls180.v:471.5-471.38" - wire $1\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:470.11-470.46" - wire width 4 $1\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:469.5-469.38" - wire $1\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:466.5-466.39" - wire $1\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:362.12-362.46" - wire width 16 $1\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:363.5-363.44" - wire $1\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:398.12-398.37" - wire width 16 $1\main_sdram_status[15:0] - attribute \src "ls180.v:840.11-840.40" - wire width 2 $1\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:384.11-384.36" - wire width 4 $1\main_sdram_storage[3:0] - attribute \src "ls180.v:849.5-849.36" - wire $1\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:848.32-848.63" - wire $1\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:857.11-857.34" - wire width 5 $1\main_sdram_time0[4:0] - attribute \src "ls180.v:860.11-860.34" - wire width 4 $1\main_sdram_time1[3:0] - attribute \src "ls180.v:462.11-462.44" - wire width 10 $1\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:852.11-852.42" - wire width 3 $1\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:851.32-851.63" - wire $1\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:397.5-397.32" - wire $1\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:396.12-396.45" - wire width 16 $1\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:916.5-916.23" - wire $1\main_start1[0:0] - attribute \src "ls180.v:881.5-881.29" - wire $1\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:899.5-899.31" - wire $1\main_wdata_consumed[0:0] - attribute \src "ls180.v:2636.68-2636.110" - wire $add$ls180.v:2636$22_Y - attribute \src "ls180.v:2696.68-2696.110" - wire $add$ls180.v:2696$33_Y - attribute \src "ls180.v:2794.48-2794.125" - wire width 5 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"ls180.v:4650.192-4650.327" - wire $xor$ls180.v:4650$784_Y - attribute \src "ls180.v:4651.423-4651.509" - wire $xor$ls180.v:4651$785_Y - attribute \src "ls180.v:4651.240-4651.326" - wire $xor$ls180.v:4651$786_Y - attribute \src "ls180.v:4651.192-4651.327" - wire $xor$ls180.v:4651$787_Y - attribute \src "ls180.v:4652.423-4652.509" - wire $xor$ls180.v:4652$788_Y - attribute \src "ls180.v:4652.240-4652.326" - wire $xor$ls180.v:4652$789_Y - attribute \src "ls180.v:4652.192-4652.327" - wire $xor$ls180.v:4652$790_Y - attribute \src "ls180.v:4653.423-4653.509" - wire $xor$ls180.v:4653$791_Y - attribute \src "ls180.v:4653.240-4653.326" - wire $xor$ls180.v:4653$792_Y - attribute \src "ls180.v:4653.192-4653.327" - wire $xor$ls180.v:4653$793_Y - attribute \src "ls180.v:4654.423-4654.509" - wire $xor$ls180.v:4654$794_Y - attribute \src "ls180.v:4654.240-4654.326" - wire $xor$ls180.v:4654$795_Y - attribute \src "ls180.v:4654.192-4654.327" - wire $xor$ls180.v:4654$796_Y - attribute \src "ls180.v:4655.423-4655.509" - wire $xor$ls180.v:4655$797_Y - attribute \src "ls180.v:4655.240-4655.326" - wire $xor$ls180.v:4655$798_Y - attribute \src "ls180.v:4655.192-4655.327" - wire $xor$ls180.v:4655$799_Y - attribute \src "ls180.v:4656.423-4656.509" - wire $xor$ls180.v:4656$800_Y - attribute \src "ls180.v:4656.240-4656.326" - wire $xor$ls180.v:4656$801_Y - attribute \src "ls180.v:4656.192-4656.327" - wire $xor$ls180.v:4656$802_Y - attribute \src "ls180.v:4657.423-4657.509" - wire $xor$ls180.v:4657$803_Y - attribute \src "ls180.v:4657.240-4657.326" - wire $xor$ls180.v:4657$804_Y - attribute \src "ls180.v:4657.192-4657.327" - wire $xor$ls180.v:4657$805_Y - attribute \src "ls180.v:4658.423-4658.509" - wire $xor$ls180.v:4658$806_Y - attribute \src "ls180.v:4658.240-4658.326" - wire $xor$ls180.v:4658$807_Y - attribute \src "ls180.v:4658.192-4658.327" - wire $xor$ls180.v:4658$808_Y - attribute \src "ls180.v:4659.423-4659.509" - wire $xor$ls180.v:4659$809_Y - attribute \src "ls180.v:4659.240-4659.326" - wire $xor$ls180.v:4659$810_Y - attribute \src "ls180.v:4659.192-4659.327" - wire $xor$ls180.v:4659$811_Y - attribute \src "ls180.v:4680.1039-4680.1137" - wire $xor$ls180.v:4680$825_Y - attribute \src "ls180.v:4680.732-4680.830" - wire $xor$ls180.v:4680$826_Y - attribute \src "ls180.v:4680.679-4680.831" - wire $xor$ls180.v:4680$827_Y - attribute \src "ls180.v:4680.269-4680.367" - wire $xor$ls180.v:4680$828_Y - attribute \src "ls180.v:4680.215-4680.368" - wire $xor$ls180.v:4680$829_Y - attribute \src "ls180.v:4681.1039-4681.1137" - wire $xor$ls180.v:4681$830_Y - attribute \src "ls180.v:4681.732-4681.830" - wire $xor$ls180.v:4681$831_Y - attribute \src "ls180.v:4681.679-4681.831" - wire $xor$ls180.v:4681$832_Y - attribute \src "ls180.v:4681.269-4681.367" - wire $xor$ls180.v:4681$833_Y - attribute \src "ls180.v:4681.215-4681.368" - wire $xor$ls180.v:4681$834_Y - attribute \src "ls180.v:4690.1039-4690.1137" - wire $xor$ls180.v:4690$836_Y - attribute \src "ls180.v:4690.732-4690.830" - wire $xor$ls180.v:4690$837_Y - attribute \src "ls180.v:4690.679-4690.831" - wire $xor$ls180.v:4690$838_Y - attribute \src "ls180.v:4690.269-4690.367" - wire $xor$ls180.v:4690$839_Y - attribute \src "ls180.v:4690.215-4690.368" - wire $xor$ls180.v:4690$840_Y - attribute \src "ls180.v:4691.1039-4691.1137" - wire $xor$ls180.v:4691$841_Y - attribute \src "ls180.v:4691.732-4691.830" - wire $xor$ls180.v:4691$842_Y - attribute \src "ls180.v:4691.679-4691.831" - wire $xor$ls180.v:4691$843_Y - attribute \src "ls180.v:4691.269-4691.367" - wire $xor$ls180.v:4691$844_Y - attribute \src "ls180.v:4691.215-4691.368" - wire $xor$ls180.v:4691$845_Y - attribute \src "ls180.v:4700.1039-4700.1137" - wire $xor$ls180.v:4700$847_Y - attribute \src "ls180.v:4700.732-4700.830" - wire $xor$ls180.v:4700$848_Y - attribute \src "ls180.v:4700.679-4700.831" - wire $xor$ls180.v:4700$849_Y - attribute \src "ls180.v:4700.269-4700.367" - wire $xor$ls180.v:4700$850_Y - attribute \src "ls180.v:4700.215-4700.368" - wire $xor$ls180.v:4700$851_Y - attribute \src "ls180.v:4701.1039-4701.1137" - wire $xor$ls180.v:4701$852_Y - attribute \src "ls180.v:4701.732-4701.830" - wire $xor$ls180.v:4701$853_Y - attribute \src "ls180.v:4701.679-4701.831" - wire $xor$ls180.v:4701$854_Y - attribute \src "ls180.v:4701.269-4701.367" - wire $xor$ls180.v:4701$855_Y - attribute \src "ls180.v:4701.215-4701.368" - wire $xor$ls180.v:4701$856_Y - attribute \src "ls180.v:4710.1039-4710.1137" - wire $xor$ls180.v:4710$858_Y - attribute \src "ls180.v:4710.732-4710.830" - wire $xor$ls180.v:4710$859_Y - attribute \src "ls180.v:4710.679-4710.831" - wire $xor$ls180.v:4710$860_Y - attribute \src "ls180.v:4710.269-4710.367" - wire $xor$ls180.v:4710$861_Y - attribute \src "ls180.v:4710.215-4710.368" - wire $xor$ls180.v:4710$862_Y - attribute \src "ls180.v:4711.1039-4711.1137" - wire $xor$ls180.v:4711$863_Y - attribute \src "ls180.v:4711.732-4711.830" - wire $xor$ls180.v:4711$864_Y - attribute \src "ls180.v:4711.679-4711.831" - wire $xor$ls180.v:4711$865_Y - attribute \src "ls180.v:4711.269-4711.367" - wire $xor$ls180.v:4711$866_Y - attribute \src "ls180.v:4711.215-4711.368" - wire $xor$ls180.v:4711$867_Y - attribute \src "ls180.v:4862.1019-4862.1115" - wire $xor$ls180.v:4862$900_Y - attribute \src "ls180.v:4862.718-4862.814" - wire $xor$ls180.v:4862$901_Y - attribute \src "ls180.v:4862.666-4862.815" - wire $xor$ls180.v:4862$902_Y - attribute \src "ls180.v:4862.264-4862.360" - wire $xor$ls180.v:4862$903_Y - attribute \src "ls180.v:4862.211-4862.361" - wire $xor$ls180.v:4862$904_Y - attribute \src "ls180.v:4863.1019-4863.1115" - wire $xor$ls180.v:4863$905_Y - attribute \src "ls180.v:4863.718-4863.814" - wire $xor$ls180.v:4863$906_Y - attribute \src "ls180.v:4863.666-4863.815" - wire $xor$ls180.v:4863$907_Y - attribute \src "ls180.v:4863.264-4863.360" - wire $xor$ls180.v:4863$908_Y - attribute \src "ls180.v:4863.211-4863.361" - wire $xor$ls180.v:4863$909_Y - attribute \src "ls180.v:4872.1019-4872.1115" - wire $xor$ls180.v:4872$911_Y - attribute \src "ls180.v:4872.718-4872.814" - wire $xor$ls180.v:4872$912_Y - attribute \src "ls180.v:4872.666-4872.815" - wire $xor$ls180.v:4872$913_Y - attribute \src "ls180.v:4872.264-4872.360" - wire $xor$ls180.v:4872$914_Y - attribute \src "ls180.v:4872.211-4872.361" - wire $xor$ls180.v:4872$915_Y - attribute \src "ls180.v:4873.1019-4873.1115" - wire $xor$ls180.v:4873$916_Y - attribute \src "ls180.v:4873.718-4873.814" - wire $xor$ls180.v:4873$917_Y - attribute \src "ls180.v:4873.666-4873.815" - wire $xor$ls180.v:4873$918_Y - attribute \src "ls180.v:4873.264-4873.360" - wire $xor$ls180.v:4873$919_Y - attribute \src "ls180.v:4873.211-4873.361" - wire $xor$ls180.v:4873$920_Y - attribute \src "ls180.v:4882.1019-4882.1115" - wire $xor$ls180.v:4882$922_Y - attribute \src "ls180.v:4882.718-4882.814" - wire $xor$ls180.v:4882$923_Y - attribute \src "ls180.v:4882.666-4882.815" - wire $xor$ls180.v:4882$924_Y - attribute \src "ls180.v:4882.264-4882.360" - wire $xor$ls180.v:4882$925_Y - attribute \src "ls180.v:4882.211-4882.361" - wire $xor$ls180.v:4882$926_Y - attribute \src "ls180.v:4883.1019-4883.1115" - wire $xor$ls180.v:4883$927_Y - attribute \src "ls180.v:4883.718-4883.814" - wire $xor$ls180.v:4883$928_Y - attribute \src "ls180.v:4883.666-4883.815" - wire $xor$ls180.v:4883$929_Y - attribute \src "ls180.v:4883.264-4883.360" - wire $xor$ls180.v:4883$930_Y - attribute \src "ls180.v:4883.211-4883.361" - wire $xor$ls180.v:4883$931_Y - attribute \src "ls180.v:4892.1019-4892.1115" - wire $xor$ls180.v:4892$933_Y - attribute \src "ls180.v:4892.718-4892.814" - wire $xor$ls180.v:4892$934_Y - attribute \src "ls180.v:4892.666-4892.815" - wire $xor$ls180.v:4892$935_Y - attribute \src "ls180.v:4892.264-4892.360" - wire $xor$ls180.v:4892$936_Y - attribute \src "ls180.v:4892.211-4892.361" - wire $xor$ls180.v:4892$937_Y - attribute \src "ls180.v:4893.1019-4893.1115" - wire $xor$ls180.v:4893$938_Y - attribute \src "ls180.v:4893.718-4893.814" - wire $xor$ls180.v:4893$939_Y - attribute \src "ls180.v:4893.666-4893.815" - wire $xor$ls180.v:4893$940_Y - attribute \src "ls180.v:4893.264-4893.360" - wire $xor$ls180.v:4893$941_Y - attribute \src "ls180.v:4893.211-4893.361" - wire $xor$ls180.v:4893$942_Y - attribute \src "ls180.v:1630.11-1630.42" - wire width 3 \builder_bankmachine0_next_state - attribute \src "ls180.v:1629.11-1629.37" - wire width 3 \builder_bankmachine0_state - attribute \src "ls180.v:1632.11-1632.42" - wire width 3 \builder_bankmachine1_next_state - attribute \src "ls180.v:1631.11-1631.37" - wire width 3 \builder_bankmachine1_state - attribute \src "ls180.v:1634.11-1634.42" - wire width 3 \builder_bankmachine2_next_state - attribute \src "ls180.v:1633.11-1633.37" - wire width 3 \builder_bankmachine2_state - attribute \src "ls180.v:1636.11-1636.42" - wire width 3 \builder_bankmachine3_next_state - attribute \src "ls180.v:1635.11-1635.37" - wire width 3 \builder_bankmachine3_state - attribute \src "ls180.v:2375.5-2375.34" - wire \builder_comb_rhs_array_muxed0 - attribute \src "ls180.v:2376.12-2376.41" - wire width 13 \builder_comb_rhs_array_muxed1 - attribute \src "ls180.v:2388.5-2388.35" - wire \builder_comb_rhs_array_muxed10 - attribute \src "ls180.v:2389.5-2389.35" - wire \builder_comb_rhs_array_muxed11 - attribute \src "ls180.v:2393.12-2393.42" - wire width 22 \builder_comb_rhs_array_muxed12 - attribute \src "ls180.v:2394.5-2394.35" - wire \builder_comb_rhs_array_muxed13 - attribute \src "ls180.v:2395.5-2395.35" - wire \builder_comb_rhs_array_muxed14 - attribute \src "ls180.v:2396.12-2396.42" - wire width 22 \builder_comb_rhs_array_muxed15 - attribute \src "ls180.v:2397.5-2397.35" - wire \builder_comb_rhs_array_muxed16 - attribute \src "ls180.v:2398.5-2398.35" - wire \builder_comb_rhs_array_muxed17 - attribute \src "ls180.v:2399.12-2399.42" - wire width 22 \builder_comb_rhs_array_muxed18 - attribute \src "ls180.v:2400.5-2400.35" - wire \builder_comb_rhs_array_muxed19 - attribute \src "ls180.v:2377.11-2377.40" - wire width 2 \builder_comb_rhs_array_muxed2 - attribute \src "ls180.v:2401.5-2401.35" - wire \builder_comb_rhs_array_muxed20 - attribute \src "ls180.v:2402.12-2402.42" - wire width 22 \builder_comb_rhs_array_muxed21 - attribute \src "ls180.v:2403.5-2403.35" - wire \builder_comb_rhs_array_muxed22 - attribute \src "ls180.v:2404.5-2404.35" - wire \builder_comb_rhs_array_muxed23 - attribute \src "ls180.v:2405.12-2405.42" - wire width 32 \builder_comb_rhs_array_muxed24 - attribute \src "ls180.v:2406.12-2406.42" - wire width 32 \builder_comb_rhs_array_muxed25 - attribute \src "ls180.v:2407.11-2407.41" - wire width 4 \builder_comb_rhs_array_muxed26 - attribute \src "ls180.v:2408.5-2408.35" - wire \builder_comb_rhs_array_muxed27 - attribute \src "ls180.v:2409.5-2409.35" - wire \builder_comb_rhs_array_muxed28 - attribute \src "ls180.v:2410.5-2410.35" - wire \builder_comb_rhs_array_muxed29 - attribute \src "ls180.v:2378.5-2378.34" - wire \builder_comb_rhs_array_muxed3 - attribute \src "ls180.v:2411.11-2411.41" - wire width 3 \builder_comb_rhs_array_muxed30 - attribute \src "ls180.v:2412.11-2412.41" - wire width 2 \builder_comb_rhs_array_muxed31 - attribute \src "ls180.v:2379.5-2379.34" - wire \builder_comb_rhs_array_muxed4 - attribute \src "ls180.v:2380.5-2380.34" - wire \builder_comb_rhs_array_muxed5 - attribute \src "ls180.v:2384.5-2384.34" - wire \builder_comb_rhs_array_muxed6 - attribute \src "ls180.v:2385.12-2385.41" - wire width 13 \builder_comb_rhs_array_muxed7 - attribute \src "ls180.v:2386.11-2386.40" - wire width 2 \builder_comb_rhs_array_muxed8 - attribute \src "ls180.v:2387.5-2387.34" - wire \builder_comb_rhs_array_muxed9 - attribute \src "ls180.v:2381.5-2381.32" - wire \builder_comb_t_array_muxed0 - attribute \src "ls180.v:2382.5-2382.32" - wire \builder_comb_t_array_muxed1 - attribute \src "ls180.v:2383.5-2383.32" - wire \builder_comb_t_array_muxed2 - attribute \src "ls180.v:2390.5-2390.32" - wire \builder_comb_t_array_muxed3 - attribute \src "ls180.v:2391.5-2391.32" - wire \builder_comb_t_array_muxed4 - attribute \src "ls180.v:2392.5-2392.32" - wire \builder_comb_t_array_muxed5 - attribute \src "ls180.v:1620.5-1620.34" - wire \builder_converter0_next_state - attribute \src "ls180.v:1619.5-1619.29" - wire \builder_converter0_state - attribute \src "ls180.v:1624.5-1624.34" - wire \builder_converter1_next_state - attribute \src "ls180.v:1623.5-1623.29" - wire \builder_converter1_state - attribute \src "ls180.v:1661.5-1661.33" - wire \builder_converter_next_state - attribute \src "ls180.v:1660.5-1660.28" - wire \builder_converter_state - attribute \src "ls180.v:1781.12-1781.25" - wire width 20 \builder_count - attribute \src "ls180.v:2363.13-2363.41" - wire width 14 \builder_csr_interconnect_adr - attribute \src "ls180.v:2366.12-2366.42" - wire width 8 \builder_csr_interconnect_dat_r - attribute \src "ls180.v:2365.12-2365.42" - wire width 8 \builder_csr_interconnect_dat_w - attribute \src "ls180.v:2364.6-2364.33" - wire \builder_csr_interconnect_we - attribute \src "ls180.v:1819.12-1819.42" - wire width 8 \builder_csrbank0_bus_errors0_r - attribute \src "ls180.v:1818.6-1818.37" - wire \builder_csrbank0_bus_errors0_re - attribute \src "ls180.v:1821.12-1821.42" - wire width 8 \builder_csrbank0_bus_errors0_w - attribute \src "ls180.v:1820.6-1820.37" - wire \builder_csrbank0_bus_errors0_we - attribute \src "ls180.v:1815.12-1815.42" - wire width 8 \builder_csrbank0_bus_errors1_r - attribute \src "ls180.v:1814.6-1814.37" - wire \builder_csrbank0_bus_errors1_re - attribute \src "ls180.v:1817.12-1817.42" - wire width 8 \builder_csrbank0_bus_errors1_w - attribute \src "ls180.v:1816.6-1816.37" - wire \builder_csrbank0_bus_errors1_we - attribute \src "ls180.v:1811.12-1811.42" - wire width 8 \builder_csrbank0_bus_errors2_r - attribute \src "ls180.v:1810.6-1810.37" - wire \builder_csrbank0_bus_errors2_re - attribute \src "ls180.v:1813.12-1813.42" - wire width 8 \builder_csrbank0_bus_errors2_w - attribute \src "ls180.v:1812.6-1812.37" - wire \builder_csrbank0_bus_errors2_we - attribute \src "ls180.v:1807.12-1807.42" - wire width 8 \builder_csrbank0_bus_errors3_r - attribute \src "ls180.v:1806.6-1806.37" - wire \builder_csrbank0_bus_errors3_re - attribute \src "ls180.v:1809.12-1809.42" - wire width 8 \builder_csrbank0_bus_errors3_w - attribute \src "ls180.v:1808.6-1808.37" - wire \builder_csrbank0_bus_errors3_we - attribute \src "ls180.v:1787.6-1787.31" - wire \builder_csrbank0_reset0_r - attribute \src "ls180.v:1786.6-1786.32" - wire \builder_csrbank0_reset0_re - attribute \src "ls180.v:1789.6-1789.31" - wire \builder_csrbank0_reset0_w - attribute \src "ls180.v:1788.6-1788.32" - wire \builder_csrbank0_reset0_we - attribute \src "ls180.v:1803.12-1803.39" - wire width 8 \builder_csrbank0_scratch0_r - attribute \src "ls180.v:1802.6-1802.34" - wire \builder_csrbank0_scratch0_re - attribute \src "ls180.v:1805.12-1805.39" - wire width 8 \builder_csrbank0_scratch0_w - attribute \src "ls180.v:1804.6-1804.34" - wire \builder_csrbank0_scratch0_we - attribute \src "ls180.v:1799.12-1799.39" - wire width 8 \builder_csrbank0_scratch1_r - attribute \src "ls180.v:1798.6-1798.34" - wire \builder_csrbank0_scratch1_re - attribute \src "ls180.v:1801.12-1801.39" - wire width 8 \builder_csrbank0_scratch1_w - attribute \src "ls180.v:1800.6-1800.34" - wire \builder_csrbank0_scratch1_we - attribute \src "ls180.v:1795.12-1795.39" - wire width 8 \builder_csrbank0_scratch2_r - attribute \src "ls180.v:1794.6-1794.34" - wire \builder_csrbank0_scratch2_re - attribute \src "ls180.v:1797.12-1797.39" - wire width 8 \builder_csrbank0_scratch2_w - attribute \src "ls180.v:1796.6-1796.34" - wire \builder_csrbank0_scratch2_we - attribute \src "ls180.v:1791.12-1791.39" - wire width 8 \builder_csrbank0_scratch3_r - attribute \src "ls180.v:1790.6-1790.34" - wire \builder_csrbank0_scratch3_re - attribute \src "ls180.v:1793.12-1793.39" - wire width 8 \builder_csrbank0_scratch3_w - attribute \src "ls180.v:1792.6-1792.34" - wire \builder_csrbank0_scratch3_we - attribute \src "ls180.v:1822.6-1822.26" - wire \builder_csrbank0_sel - attribute \src "ls180.v:2289.6-2289.29" - wire \builder_csrbank10_en0_r - attribute \src "ls180.v:2288.6-2288.30" - wire \builder_csrbank10_en0_re - attribute \src "ls180.v:2291.6-2291.29" - wire \builder_csrbank10_en0_w - attribute \src "ls180.v:2290.6-2290.30" - wire \builder_csrbank10_en0_we - attribute \src "ls180.v:2313.6-2313.36" - wire \builder_csrbank10_ev_enable0_r - attribute \src "ls180.v:2312.6-2312.37" - wire \builder_csrbank10_ev_enable0_re - attribute \src "ls180.v:2315.6-2315.36" - wire \builder_csrbank10_ev_enable0_w - attribute \src "ls180.v:2314.6-2314.37" - wire \builder_csrbank10_ev_enable0_we - attribute \src "ls180.v:2269.12-2269.37" - wire width 8 \builder_csrbank10_load0_r - attribute \src "ls180.v:2268.6-2268.32" - wire \builder_csrbank10_load0_re - attribute \src "ls180.v:2271.12-2271.37" - wire width 8 \builder_csrbank10_load0_w - attribute \src "ls180.v:2270.6-2270.32" - wire \builder_csrbank10_load0_we - attribute \src "ls180.v:2265.12-2265.37" - wire width 8 \builder_csrbank10_load1_r - attribute \src "ls180.v:2264.6-2264.32" - wire \builder_csrbank10_load1_re - attribute \src "ls180.v:2267.12-2267.37" - wire width 8 \builder_csrbank10_load1_w - attribute \src "ls180.v:2266.6-2266.32" - wire \builder_csrbank10_load1_we - attribute \src "ls180.v:2261.12-2261.37" - wire width 8 \builder_csrbank10_load2_r - attribute \src "ls180.v:2260.6-2260.32" - wire \builder_csrbank10_load2_re - attribute \src "ls180.v:2263.12-2263.37" - wire width 8 \builder_csrbank10_load2_w - attribute \src "ls180.v:2262.6-2262.32" - wire \builder_csrbank10_load2_we - attribute \src "ls180.v:2257.12-2257.37" - wire width 8 \builder_csrbank10_load3_r - attribute \src "ls180.v:2256.6-2256.32" - wire \builder_csrbank10_load3_re - attribute \src "ls180.v:2259.12-2259.37" - wire width 8 \builder_csrbank10_load3_w - attribute \src "ls180.v:2258.6-2258.32" - wire \builder_csrbank10_load3_we - attribute \src "ls180.v:2285.12-2285.39" - wire width 8 \builder_csrbank10_reload0_r - attribute \src "ls180.v:2284.6-2284.34" - wire \builder_csrbank10_reload0_re - attribute \src "ls180.v:2287.12-2287.39" - wire width 8 \builder_csrbank10_reload0_w - attribute \src "ls180.v:2286.6-2286.34" - wire \builder_csrbank10_reload0_we - attribute \src "ls180.v:2281.12-2281.39" - wire width 8 \builder_csrbank10_reload1_r - attribute \src "ls180.v:2280.6-2280.34" - wire \builder_csrbank10_reload1_re - attribute \src "ls180.v:2283.12-2283.39" - wire width 8 \builder_csrbank10_reload1_w - attribute \src "ls180.v:2282.6-2282.34" - wire \builder_csrbank10_reload1_we - attribute \src "ls180.v:2277.12-2277.39" - wire width 8 \builder_csrbank10_reload2_r - attribute \src "ls180.v:2276.6-2276.34" - wire \builder_csrbank10_reload2_re - attribute \src "ls180.v:2279.12-2279.39" - wire width 8 \builder_csrbank10_reload2_w - attribute \src "ls180.v:2278.6-2278.34" - wire \builder_csrbank10_reload2_we - attribute \src "ls180.v:2273.12-2273.39" - wire width 8 \builder_csrbank10_reload3_r - attribute \src "ls180.v:2272.6-2272.34" - wire \builder_csrbank10_reload3_re - attribute \src "ls180.v:2275.12-2275.39" - wire width 8 \builder_csrbank10_reload3_w - attribute \src "ls180.v:2274.6-2274.34" - wire \builder_csrbank10_reload3_we - attribute \src "ls180.v:2316.6-2316.27" - wire \builder_csrbank10_sel - attribute \src "ls180.v:2293.6-2293.39" - wire \builder_csrbank10_update_value0_r - attribute \src "ls180.v:2292.6-2292.40" - wire \builder_csrbank10_update_value0_re - attribute \src "ls180.v:2295.6-2295.39" - wire \builder_csrbank10_update_value0_w - attribute \src "ls180.v:2294.6-2294.40" - wire \builder_csrbank10_update_value0_we - attribute \src "ls180.v:2309.12-2309.38" - wire width 8 \builder_csrbank10_value0_r - attribute \src "ls180.v:2308.6-2308.33" - wire \builder_csrbank10_value0_re - attribute \src "ls180.v:2311.12-2311.38" - wire width 8 \builder_csrbank10_value0_w - attribute \src "ls180.v:2310.6-2310.33" - wire \builder_csrbank10_value0_we - attribute \src "ls180.v:2305.12-2305.38" - wire width 8 \builder_csrbank10_value1_r - attribute \src "ls180.v:2304.6-2304.33" - wire \builder_csrbank10_value1_re - attribute \src "ls180.v:2307.12-2307.38" - wire width 8 \builder_csrbank10_value1_w - attribute \src "ls180.v:2306.6-2306.33" - wire \builder_csrbank10_value1_we - attribute \src "ls180.v:2301.12-2301.38" - wire width 8 \builder_csrbank10_value2_r - attribute \src "ls180.v:2300.6-2300.33" - wire \builder_csrbank10_value2_re - attribute \src "ls180.v:2303.12-2303.38" - wire width 8 \builder_csrbank10_value2_w - attribute \src "ls180.v:2302.6-2302.33" - wire \builder_csrbank10_value2_we - attribute \src "ls180.v:2297.12-2297.38" - wire width 8 \builder_csrbank10_value3_r - attribute \src "ls180.v:2296.6-2296.33" - wire \builder_csrbank10_value3_re - attribute \src "ls180.v:2299.12-2299.38" - wire width 8 \builder_csrbank10_value3_w - attribute \src "ls180.v:2298.6-2298.33" - wire \builder_csrbank10_value3_we - attribute \src "ls180.v:2330.12-2330.42" - wire width 2 \builder_csrbank11_ev_enable0_r - attribute \src "ls180.v:2329.6-2329.37" - wire \builder_csrbank11_ev_enable0_re - attribute \src "ls180.v:2332.12-2332.42" - wire width 2 \builder_csrbank11_ev_enable0_w - attribute \src "ls180.v:2331.6-2331.37" - wire \builder_csrbank11_ev_enable0_we - attribute \src "ls180.v:2326.6-2326.33" - wire \builder_csrbank11_rxempty_r - attribute \src "ls180.v:2325.6-2325.34" - wire \builder_csrbank11_rxempty_re - attribute \src "ls180.v:2328.6-2328.33" - wire \builder_csrbank11_rxempty_w - attribute \src "ls180.v:2327.6-2327.34" - wire \builder_csrbank11_rxempty_we - attribute \src "ls180.v:2338.6-2338.32" - wire \builder_csrbank11_rxfull_r - attribute \src "ls180.v:2337.6-2337.33" - wire \builder_csrbank11_rxfull_re - attribute \src "ls180.v:2340.6-2340.32" - wire \builder_csrbank11_rxfull_w - attribute \src "ls180.v:2339.6-2339.33" - wire \builder_csrbank11_rxfull_we - attribute \src "ls180.v:2341.6-2341.27" - wire \builder_csrbank11_sel - attribute \src "ls180.v:2334.6-2334.33" - wire \builder_csrbank11_txempty_r - attribute \src "ls180.v:2333.6-2333.34" - wire \builder_csrbank11_txempty_re - attribute \src "ls180.v:2336.6-2336.33" - wire \builder_csrbank11_txempty_w - attribute \src "ls180.v:2335.6-2335.34" - wire \builder_csrbank11_txempty_we - attribute \src "ls180.v:2322.6-2322.32" - wire \builder_csrbank11_txfull_r - attribute \src "ls180.v:2321.6-2321.33" - wire \builder_csrbank11_txfull_re - attribute \src "ls180.v:2324.6-2324.32" - wire \builder_csrbank11_txfull_w - attribute \src "ls180.v:2323.6-2323.33" - wire \builder_csrbank11_txfull_we - attribute \src "ls180.v:2362.6-2362.27" - wire \builder_csrbank12_sel - attribute \src "ls180.v:2359.12-2359.44" - wire width 8 \builder_csrbank12_tuning_word0_r - attribute \src "ls180.v:2358.6-2358.39" - wire \builder_csrbank12_tuning_word0_re - attribute \src "ls180.v:2361.12-2361.44" - wire width 8 \builder_csrbank12_tuning_word0_w - attribute \src "ls180.v:2360.6-2360.39" - wire \builder_csrbank12_tuning_word0_we - attribute \src "ls180.v:2355.12-2355.44" - wire width 8 \builder_csrbank12_tuning_word1_r - attribute \src "ls180.v:2354.6-2354.39" - wire \builder_csrbank12_tuning_word1_re - attribute \src "ls180.v:2357.12-2357.44" - wire width 8 \builder_csrbank12_tuning_word1_w - attribute \src "ls180.v:2356.6-2356.39" - wire \builder_csrbank12_tuning_word1_we - attribute \src "ls180.v:2351.12-2351.44" - wire width 8 \builder_csrbank12_tuning_word2_r - attribute \src "ls180.v:2350.6-2350.39" - wire \builder_csrbank12_tuning_word2_re - attribute \src "ls180.v:2353.12-2353.44" - wire width 8 \builder_csrbank12_tuning_word2_w - attribute \src "ls180.v:2352.6-2352.39" - wire \builder_csrbank12_tuning_word2_we - attribute \src "ls180.v:2347.12-2347.44" - wire width 8 \builder_csrbank12_tuning_word3_r - attribute \src "ls180.v:2346.6-2346.39" - wire \builder_csrbank12_tuning_word3_re - attribute \src "ls180.v:2349.12-2349.44" - wire width 8 \builder_csrbank12_tuning_word3_w - attribute \src "ls180.v:2348.6-2348.39" - wire \builder_csrbank12_tuning_word3_we - attribute \src "ls180.v:1828.12-1828.33" - wire width 8 \builder_csrbank1_in_r - attribute \src "ls180.v:1827.6-1827.28" - wire \builder_csrbank1_in_re - attribute \src "ls180.v:1830.12-1830.33" - wire width 8 \builder_csrbank1_in_w - attribute \src "ls180.v:1829.6-1829.28" - wire \builder_csrbank1_in_we - attribute \src "ls180.v:1831.6-1831.26" - wire \builder_csrbank1_sel - attribute \src "ls180.v:1837.12-1837.33" - wire width 8 \builder_csrbank2_in_r - attribute \src "ls180.v:1836.6-1836.28" - wire \builder_csrbank2_in_re - attribute \src "ls180.v:1839.12-1839.33" - wire width 8 \builder_csrbank2_in_w - attribute \src "ls180.v:1838.6-1838.28" - wire \builder_csrbank2_in_we - attribute \src "ls180.v:1840.6-1840.26" - wire \builder_csrbank2_sel - attribute \src "ls180.v:1874.12-1874.40" - wire width 8 \builder_csrbank3_dma_base0_r - attribute \src "ls180.v:1873.6-1873.35" - wire \builder_csrbank3_dma_base0_re - attribute \src "ls180.v:1876.12-1876.40" - wire width 8 \builder_csrbank3_dma_base0_w - attribute \src "ls180.v:1875.6-1875.35" - wire \builder_csrbank3_dma_base0_we - attribute \src "ls180.v:1870.12-1870.40" - wire width 8 \builder_csrbank3_dma_base1_r - attribute \src "ls180.v:1869.6-1869.35" - wire \builder_csrbank3_dma_base1_re - attribute \src "ls180.v:1872.12-1872.40" - wire width 8 \builder_csrbank3_dma_base1_w - attribute \src "ls180.v:1871.6-1871.35" - wire \builder_csrbank3_dma_base1_we - attribute \src "ls180.v:1866.12-1866.40" - wire width 8 \builder_csrbank3_dma_base2_r - attribute \src "ls180.v:1865.6-1865.35" - wire \builder_csrbank3_dma_base2_re - attribute \src "ls180.v:1868.12-1868.40" - wire width 8 \builder_csrbank3_dma_base2_w - attribute \src "ls180.v:1867.6-1867.35" - wire \builder_csrbank3_dma_base2_we - attribute \src "ls180.v:1862.12-1862.40" - wire width 8 \builder_csrbank3_dma_base3_r - attribute \src "ls180.v:1861.6-1861.35" - wire \builder_csrbank3_dma_base3_re - attribute \src "ls180.v:1864.12-1864.40" - wire width 8 \builder_csrbank3_dma_base3_w - attribute \src "ls180.v:1863.6-1863.35" - wire \builder_csrbank3_dma_base3_we - attribute \src "ls180.v:1858.12-1858.40" - wire width 8 \builder_csrbank3_dma_base4_r - attribute \src "ls180.v:1857.6-1857.35" - wire \builder_csrbank3_dma_base4_re - attribute \src "ls180.v:1860.12-1860.40" - wire width 8 \builder_csrbank3_dma_base4_w - attribute \src "ls180.v:1859.6-1859.35" - wire \builder_csrbank3_dma_base4_we - attribute \src "ls180.v:1854.12-1854.40" - wire width 8 \builder_csrbank3_dma_base5_r - attribute \src "ls180.v:1853.6-1853.35" - wire \builder_csrbank3_dma_base5_re - attribute \src "ls180.v:1856.12-1856.40" - wire width 8 \builder_csrbank3_dma_base5_w - attribute \src "ls180.v:1855.6-1855.35" - wire \builder_csrbank3_dma_base5_we - attribute \src "ls180.v:1850.12-1850.40" - wire width 8 \builder_csrbank3_dma_base6_r - attribute \src "ls180.v:1849.6-1849.35" - wire \builder_csrbank3_dma_base6_re - attribute \src "ls180.v:1852.12-1852.40" - wire width 8 \builder_csrbank3_dma_base6_w - attribute \src "ls180.v:1851.6-1851.35" - wire \builder_csrbank3_dma_base6_we - attribute \src "ls180.v:1846.12-1846.40" - wire width 8 \builder_csrbank3_dma_base7_r - attribute \src "ls180.v:1845.6-1845.35" - wire \builder_csrbank3_dma_base7_re - attribute \src "ls180.v:1848.12-1848.40" - wire width 8 \builder_csrbank3_dma_base7_w - attribute \src "ls180.v:1847.6-1847.35" - wire \builder_csrbank3_dma_base7_we - attribute \src "ls180.v:1898.6-1898.33" - wire \builder_csrbank3_dma_done_r - attribute \src "ls180.v:1897.6-1897.34" - wire \builder_csrbank3_dma_done_re - attribute \src "ls180.v:1900.6-1900.33" - wire \builder_csrbank3_dma_done_w - attribute \src "ls180.v:1899.6-1899.34" - wire \builder_csrbank3_dma_done_we - attribute \src "ls180.v:1894.6-1894.36" - wire \builder_csrbank3_dma_enable0_r - attribute \src "ls180.v:1893.6-1893.37" - wire \builder_csrbank3_dma_enable0_re - attribute \src "ls180.v:1896.6-1896.36" - wire \builder_csrbank3_dma_enable0_w - attribute \src "ls180.v:1895.6-1895.37" - wire \builder_csrbank3_dma_enable0_we - attribute \src "ls180.v:1890.12-1890.42" - wire width 8 \builder_csrbank3_dma_length0_r - attribute \src "ls180.v:1889.6-1889.37" - wire \builder_csrbank3_dma_length0_re - attribute \src "ls180.v:1892.12-1892.42" - wire width 8 \builder_csrbank3_dma_length0_w - attribute \src "ls180.v:1891.6-1891.37" - wire \builder_csrbank3_dma_length0_we - attribute \src "ls180.v:1886.12-1886.42" - wire width 8 \builder_csrbank3_dma_length1_r - attribute \src "ls180.v:1885.6-1885.37" - wire \builder_csrbank3_dma_length1_re - attribute \src "ls180.v:1888.12-1888.42" - wire width 8 \builder_csrbank3_dma_length1_w - attribute \src "ls180.v:1887.6-1887.37" - wire \builder_csrbank3_dma_length1_we - attribute \src "ls180.v:1882.12-1882.42" - wire width 8 \builder_csrbank3_dma_length2_r - attribute \src "ls180.v:1881.6-1881.37" - wire \builder_csrbank3_dma_length2_re - attribute \src "ls180.v:1884.12-1884.42" - wire width 8 \builder_csrbank3_dma_length2_w - attribute \src "ls180.v:1883.6-1883.37" - wire \builder_csrbank3_dma_length2_we - attribute \src "ls180.v:1878.12-1878.42" - wire width 8 \builder_csrbank3_dma_length3_r - attribute \src "ls180.v:1877.6-1877.37" - wire \builder_csrbank3_dma_length3_re - attribute \src "ls180.v:1880.12-1880.42" - wire width 8 \builder_csrbank3_dma_length3_w - attribute \src "ls180.v:1879.6-1879.37" - wire \builder_csrbank3_dma_length3_we - attribute \src "ls180.v:1902.6-1902.34" - wire \builder_csrbank3_dma_loop0_r - attribute \src "ls180.v:1901.6-1901.35" - wire \builder_csrbank3_dma_loop0_re - attribute \src "ls180.v:1904.6-1904.34" - wire \builder_csrbank3_dma_loop0_w - attribute \src "ls180.v:1903.6-1903.35" - wire \builder_csrbank3_dma_loop0_we - attribute \src "ls180.v:1905.6-1905.26" - wire \builder_csrbank3_sel - attribute \src "ls180.v:2035.12-2035.43" - wire width 8 \builder_csrbank4_block_count0_r - attribute \src "ls180.v:2034.6-2034.38" - wire \builder_csrbank4_block_count0_re - attribute \src "ls180.v:2037.12-2037.43" - wire width 8 \builder_csrbank4_block_count0_w - attribute \src "ls180.v:2036.6-2036.38" - wire \builder_csrbank4_block_count0_we - attribute \src "ls180.v:2031.12-2031.43" - wire width 8 \builder_csrbank4_block_count1_r - attribute \src "ls180.v:2030.6-2030.38" - wire \builder_csrbank4_block_count1_re - attribute \src "ls180.v:2033.12-2033.43" - wire width 8 \builder_csrbank4_block_count1_w - attribute \src "ls180.v:2032.6-2032.38" - wire \builder_csrbank4_block_count1_we - attribute \src "ls180.v:2027.12-2027.43" - wire width 8 \builder_csrbank4_block_count2_r - attribute \src "ls180.v:2026.6-2026.38" - wire \builder_csrbank4_block_count2_re - attribute \src "ls180.v:2029.12-2029.43" - wire width 8 \builder_csrbank4_block_count2_w - attribute \src "ls180.v:2028.6-2028.38" - wire \builder_csrbank4_block_count2_we - attribute \src "ls180.v:2023.12-2023.43" - wire width 8 \builder_csrbank4_block_count3_r - attribute \src "ls180.v:2022.6-2022.38" - wire \builder_csrbank4_block_count3_re - attribute \src "ls180.v:2025.12-2025.43" - wire width 8 \builder_csrbank4_block_count3_w - attribute \src "ls180.v:2024.6-2024.38" - wire \builder_csrbank4_block_count3_we - attribute \src "ls180.v:2019.12-2019.44" - wire width 8 \builder_csrbank4_block_length0_r - attribute \src "ls180.v:2018.6-2018.39" - wire \builder_csrbank4_block_length0_re - attribute \src "ls180.v:2021.12-2021.44" - wire width 8 \builder_csrbank4_block_length0_w - attribute \src "ls180.v:2020.6-2020.39" - wire \builder_csrbank4_block_length0_we - attribute \src "ls180.v:2015.12-2015.44" - wire width 2 \builder_csrbank4_block_length1_r - attribute \src "ls180.v:2014.6-2014.39" - wire \builder_csrbank4_block_length1_re - attribute \src "ls180.v:2017.12-2017.44" - wire width 2 \builder_csrbank4_block_length1_w - attribute \src "ls180.v:2016.6-2016.39" - wire \builder_csrbank4_block_length1_we - attribute \src "ls180.v:1923.12-1923.44" - wire width 8 \builder_csrbank4_cmd_argument0_r - attribute \src "ls180.v:1922.6-1922.39" - wire \builder_csrbank4_cmd_argument0_re - attribute \src "ls180.v:1925.12-1925.44" - wire width 8 \builder_csrbank4_cmd_argument0_w - attribute \src "ls180.v:1924.6-1924.39" - wire \builder_csrbank4_cmd_argument0_we - attribute \src "ls180.v:1919.12-1919.44" - wire width 8 \builder_csrbank4_cmd_argument1_r - attribute \src "ls180.v:1918.6-1918.39" - wire \builder_csrbank4_cmd_argument1_re - attribute \src "ls180.v:1921.12-1921.44" - wire width 8 \builder_csrbank4_cmd_argument1_w - attribute \src "ls180.v:1920.6-1920.39" - wire \builder_csrbank4_cmd_argument1_we - attribute \src "ls180.v:1915.12-1915.44" - wire width 8 \builder_csrbank4_cmd_argument2_r - attribute \src "ls180.v:1914.6-1914.39" - wire \builder_csrbank4_cmd_argument2_re - attribute \src "ls180.v:1917.12-1917.44" - wire width 8 \builder_csrbank4_cmd_argument2_w - attribute \src "ls180.v:1916.6-1916.39" - wire \builder_csrbank4_cmd_argument2_we - attribute \src "ls180.v:1911.12-1911.44" - wire width 8 \builder_csrbank4_cmd_argument3_r - attribute \src "ls180.v:1910.6-1910.39" - wire \builder_csrbank4_cmd_argument3_re - attribute \src "ls180.v:1913.12-1913.44" - wire width 8 \builder_csrbank4_cmd_argument3_w - attribute \src "ls180.v:1912.6-1912.39" - wire \builder_csrbank4_cmd_argument3_we - attribute \src "ls180.v:1939.12-1939.43" - wire width 8 \builder_csrbank4_cmd_command0_r - attribute \src "ls180.v:1938.6-1938.38" - wire \builder_csrbank4_cmd_command0_re - attribute \src "ls180.v:1941.12-1941.43" - wire width 8 \builder_csrbank4_cmd_command0_w - attribute \src "ls180.v:1940.6-1940.38" - wire \builder_csrbank4_cmd_command0_we - attribute \src "ls180.v:1935.12-1935.43" - wire width 8 \builder_csrbank4_cmd_command1_r - attribute \src "ls180.v:1934.6-1934.38" - wire \builder_csrbank4_cmd_command1_re - attribute \src "ls180.v:1937.12-1937.43" - wire width 8 \builder_csrbank4_cmd_command1_w - attribute \src "ls180.v:1936.6-1936.38" - wire \builder_csrbank4_cmd_command1_we - attribute \src "ls180.v:1931.12-1931.43" - wire width 8 \builder_csrbank4_cmd_command2_r - attribute \src "ls180.v:1930.6-1930.38" - wire \builder_csrbank4_cmd_command2_re - attribute \src "ls180.v:1933.12-1933.43" - wire width 8 \builder_csrbank4_cmd_command2_w - attribute \src "ls180.v:1932.6-1932.38" - wire \builder_csrbank4_cmd_command2_we - attribute \src "ls180.v:1927.12-1927.43" - wire width 8 \builder_csrbank4_cmd_command3_r - attribute \src "ls180.v:1926.6-1926.38" - wire \builder_csrbank4_cmd_command3_re - attribute \src "ls180.v:1929.12-1929.43" - wire width 8 \builder_csrbank4_cmd_command3_w - attribute \src "ls180.v:1928.6-1928.38" - wire \builder_csrbank4_cmd_command3_we - attribute \src "ls180.v:2007.12-2007.40" - wire width 4 \builder_csrbank4_cmd_event_r - attribute \src "ls180.v:2006.6-2006.35" - wire \builder_csrbank4_cmd_event_re - attribute \src "ls180.v:2009.12-2009.40" - wire width 4 \builder_csrbank4_cmd_event_w - attribute \src "ls180.v:2008.6-2008.35" - wire \builder_csrbank4_cmd_event_we - attribute \src "ls180.v:2003.12-2003.44" - wire width 8 \builder_csrbank4_cmd_response0_r - attribute \src "ls180.v:2002.6-2002.39" - wire \builder_csrbank4_cmd_response0_re - attribute \src "ls180.v:2005.12-2005.44" - wire width 8 \builder_csrbank4_cmd_response0_w - attribute \src "ls180.v:2004.6-2004.39" - wire \builder_csrbank4_cmd_response0_we - attribute \src "ls180.v:1963.12-1963.45" - wire width 8 \builder_csrbank4_cmd_response10_r - attribute \src "ls180.v:1962.6-1962.40" - wire \builder_csrbank4_cmd_response10_re - attribute \src "ls180.v:1965.12-1965.45" - wire width 8 \builder_csrbank4_cmd_response10_w - attribute \src "ls180.v:1964.6-1964.40" - wire \builder_csrbank4_cmd_response10_we - attribute \src "ls180.v:1959.12-1959.45" - wire width 8 \builder_csrbank4_cmd_response11_r - attribute \src "ls180.v:1958.6-1958.40" - wire \builder_csrbank4_cmd_response11_re - attribute \src "ls180.v:1961.12-1961.45" - wire width 8 \builder_csrbank4_cmd_response11_w - attribute \src "ls180.v:1960.6-1960.40" - wire \builder_csrbank4_cmd_response11_we - attribute \src "ls180.v:1955.12-1955.45" - wire width 8 \builder_csrbank4_cmd_response12_r - attribute \src "ls180.v:1954.6-1954.40" - wire \builder_csrbank4_cmd_response12_re - attribute \src "ls180.v:1957.12-1957.45" - wire width 8 \builder_csrbank4_cmd_response12_w - attribute \src "ls180.v:1956.6-1956.40" - wire \builder_csrbank4_cmd_response12_we - attribute \src "ls180.v:1951.12-1951.45" - wire width 8 \builder_csrbank4_cmd_response13_r - attribute \src "ls180.v:1950.6-1950.40" - wire \builder_csrbank4_cmd_response13_re - attribute \src "ls180.v:1953.12-1953.45" - wire width 8 \builder_csrbank4_cmd_response13_w - attribute \src "ls180.v:1952.6-1952.40" - wire \builder_csrbank4_cmd_response13_we - attribute \src "ls180.v:1947.12-1947.45" - wire width 8 \builder_csrbank4_cmd_response14_r - attribute \src "ls180.v:1946.6-1946.40" - wire \builder_csrbank4_cmd_response14_re - attribute \src "ls180.v:1949.12-1949.45" - wire width 8 \builder_csrbank4_cmd_response14_w - attribute \src "ls180.v:1948.6-1948.40" - wire \builder_csrbank4_cmd_response14_we - attribute \src "ls180.v:1943.12-1943.45" - wire width 8 \builder_csrbank4_cmd_response15_r - attribute \src "ls180.v:1942.6-1942.40" - wire \builder_csrbank4_cmd_response15_re - attribute \src "ls180.v:1945.12-1945.45" - wire width 8 \builder_csrbank4_cmd_response15_w - attribute \src "ls180.v:1944.6-1944.40" - wire \builder_csrbank4_cmd_response15_we - attribute \src "ls180.v:1999.12-1999.44" - wire width 8 \builder_csrbank4_cmd_response1_r - attribute \src "ls180.v:1998.6-1998.39" - wire \builder_csrbank4_cmd_response1_re - attribute \src "ls180.v:2001.12-2001.44" - wire width 8 \builder_csrbank4_cmd_response1_w - attribute \src "ls180.v:2000.6-2000.39" - wire \builder_csrbank4_cmd_response1_we - attribute \src "ls180.v:1995.12-1995.44" - wire width 8 \builder_csrbank4_cmd_response2_r - attribute \src "ls180.v:1994.6-1994.39" - wire \builder_csrbank4_cmd_response2_re - attribute \src "ls180.v:1997.12-1997.44" - wire width 8 \builder_csrbank4_cmd_response2_w - attribute \src "ls180.v:1996.6-1996.39" - wire \builder_csrbank4_cmd_response2_we - attribute \src "ls180.v:1991.12-1991.44" - wire width 8 \builder_csrbank4_cmd_response3_r - attribute \src "ls180.v:1990.6-1990.39" - wire \builder_csrbank4_cmd_response3_re - attribute \src "ls180.v:1993.12-1993.44" - wire width 8 \builder_csrbank4_cmd_response3_w - attribute \src "ls180.v:1992.6-1992.39" - wire \builder_csrbank4_cmd_response3_we - attribute \src "ls180.v:1987.12-1987.44" - wire width 8 \builder_csrbank4_cmd_response4_r - attribute \src "ls180.v:1986.6-1986.39" - wire \builder_csrbank4_cmd_response4_re - attribute \src "ls180.v:1989.12-1989.44" - wire width 8 \builder_csrbank4_cmd_response4_w - attribute \src "ls180.v:1988.6-1988.39" - wire \builder_csrbank4_cmd_response4_we - attribute \src "ls180.v:1983.12-1983.44" - wire width 8 \builder_csrbank4_cmd_response5_r - attribute \src "ls180.v:1982.6-1982.39" - wire \builder_csrbank4_cmd_response5_re - attribute \src "ls180.v:1985.12-1985.44" - wire width 8 \builder_csrbank4_cmd_response5_w - attribute \src "ls180.v:1984.6-1984.39" - wire \builder_csrbank4_cmd_response5_we - attribute \src "ls180.v:1979.12-1979.44" - wire width 8 \builder_csrbank4_cmd_response6_r - attribute \src "ls180.v:1978.6-1978.39" - wire \builder_csrbank4_cmd_response6_re - attribute \src "ls180.v:1981.12-1981.44" - wire width 8 \builder_csrbank4_cmd_response6_w - attribute \src "ls180.v:1980.6-1980.39" - wire \builder_csrbank4_cmd_response6_we - attribute \src "ls180.v:1975.12-1975.44" - wire width 8 \builder_csrbank4_cmd_response7_r - attribute \src "ls180.v:1974.6-1974.39" - wire \builder_csrbank4_cmd_response7_re - attribute \src "ls180.v:1977.12-1977.44" - wire width 8 \builder_csrbank4_cmd_response7_w - attribute \src "ls180.v:1976.6-1976.39" - wire \builder_csrbank4_cmd_response7_we - attribute \src "ls180.v:1971.12-1971.44" - wire width 8 \builder_csrbank4_cmd_response8_r - attribute \src "ls180.v:1970.6-1970.39" - wire \builder_csrbank4_cmd_response8_re - attribute \src "ls180.v:1973.12-1973.44" - wire width 8 \builder_csrbank4_cmd_response8_w - attribute \src "ls180.v:1972.6-1972.39" - wire \builder_csrbank4_cmd_response8_we - attribute \src "ls180.v:1967.12-1967.44" - wire width 8 \builder_csrbank4_cmd_response9_r - attribute \src "ls180.v:1966.6-1966.39" - wire \builder_csrbank4_cmd_response9_re - attribute \src "ls180.v:1969.12-1969.44" - wire width 8 \builder_csrbank4_cmd_response9_w - attribute \src "ls180.v:1968.6-1968.39" - wire \builder_csrbank4_cmd_response9_we - attribute \src "ls180.v:2011.12-2011.41" - wire width 4 \builder_csrbank4_data_event_r - attribute \src "ls180.v:2010.6-2010.36" - wire \builder_csrbank4_data_event_re - attribute \src "ls180.v:2013.12-2013.41" - wire width 4 \builder_csrbank4_data_event_w - attribute \src "ls180.v:2012.6-2012.36" - wire \builder_csrbank4_data_event_we - attribute \src "ls180.v:2038.6-2038.26" - wire \builder_csrbank4_sel - attribute \src "ls180.v:2072.12-2072.40" - wire width 8 \builder_csrbank5_dma_base0_r - attribute \src "ls180.v:2071.6-2071.35" - wire \builder_csrbank5_dma_base0_re - attribute \src "ls180.v:2074.12-2074.40" - wire width 8 \builder_csrbank5_dma_base0_w - attribute \src "ls180.v:2073.6-2073.35" - wire \builder_csrbank5_dma_base0_we - attribute \src "ls180.v:2068.12-2068.40" - wire width 8 \builder_csrbank5_dma_base1_r - attribute \src "ls180.v:2067.6-2067.35" - wire \builder_csrbank5_dma_base1_re - attribute \src "ls180.v:2070.12-2070.40" - wire width 8 \builder_csrbank5_dma_base1_w - attribute \src "ls180.v:2069.6-2069.35" - wire \builder_csrbank5_dma_base1_we - attribute \src "ls180.v:2064.12-2064.40" - wire width 8 \builder_csrbank5_dma_base2_r - attribute \src "ls180.v:2063.6-2063.35" - wire \builder_csrbank5_dma_base2_re - attribute \src "ls180.v:2066.12-2066.40" - wire width 8 \builder_csrbank5_dma_base2_w - attribute \src "ls180.v:2065.6-2065.35" - wire \builder_csrbank5_dma_base2_we - attribute \src "ls180.v:2060.12-2060.40" - wire width 8 \builder_csrbank5_dma_base3_r - attribute \src "ls180.v:2059.6-2059.35" - wire \builder_csrbank5_dma_base3_re - attribute \src "ls180.v:2062.12-2062.40" - wire width 8 \builder_csrbank5_dma_base3_w - attribute \src "ls180.v:2061.6-2061.35" - wire \builder_csrbank5_dma_base3_we - attribute \src "ls180.v:2056.12-2056.40" - wire width 8 \builder_csrbank5_dma_base4_r - attribute \src "ls180.v:2055.6-2055.35" - wire \builder_csrbank5_dma_base4_re - attribute \src "ls180.v:2058.12-2058.40" - wire width 8 \builder_csrbank5_dma_base4_w - attribute \src "ls180.v:2057.6-2057.35" - wire \builder_csrbank5_dma_base4_we - attribute \src "ls180.v:2052.12-2052.40" - wire width 8 \builder_csrbank5_dma_base5_r - attribute \src "ls180.v:2051.6-2051.35" - wire \builder_csrbank5_dma_base5_re - attribute \src "ls180.v:2054.12-2054.40" - wire width 8 \builder_csrbank5_dma_base5_w - attribute \src "ls180.v:2053.6-2053.35" - wire \builder_csrbank5_dma_base5_we - attribute \src "ls180.v:2048.12-2048.40" - wire width 8 \builder_csrbank5_dma_base6_r - attribute \src "ls180.v:2047.6-2047.35" - wire \builder_csrbank5_dma_base6_re - attribute \src "ls180.v:2050.12-2050.40" - wire width 8 \builder_csrbank5_dma_base6_w - attribute \src "ls180.v:2049.6-2049.35" - wire \builder_csrbank5_dma_base6_we - attribute \src "ls180.v:2044.12-2044.40" - wire width 8 \builder_csrbank5_dma_base7_r - attribute \src "ls180.v:2043.6-2043.35" - wire \builder_csrbank5_dma_base7_re - attribute \src "ls180.v:2046.12-2046.40" - wire width 8 \builder_csrbank5_dma_base7_w - attribute \src "ls180.v:2045.6-2045.35" - wire \builder_csrbank5_dma_base7_we - attribute \src "ls180.v:2096.6-2096.33" - wire \builder_csrbank5_dma_done_r - attribute \src "ls180.v:2095.6-2095.34" - wire \builder_csrbank5_dma_done_re - attribute \src "ls180.v:2098.6-2098.33" - wire \builder_csrbank5_dma_done_w - attribute \src "ls180.v:2097.6-2097.34" - wire \builder_csrbank5_dma_done_we - attribute \src "ls180.v:2092.6-2092.36" - wire \builder_csrbank5_dma_enable0_r - attribute \src "ls180.v:2091.6-2091.37" - wire \builder_csrbank5_dma_enable0_re - attribute \src "ls180.v:2094.6-2094.36" - wire \builder_csrbank5_dma_enable0_w - attribute \src "ls180.v:2093.6-2093.37" - wire \builder_csrbank5_dma_enable0_we - attribute \src "ls180.v:2088.12-2088.42" - wire width 8 \builder_csrbank5_dma_length0_r - attribute \src "ls180.v:2087.6-2087.37" - wire \builder_csrbank5_dma_length0_re - attribute \src "ls180.v:2090.12-2090.42" - wire width 8 \builder_csrbank5_dma_length0_w - attribute \src "ls180.v:2089.6-2089.37" - wire \builder_csrbank5_dma_length0_we - attribute \src "ls180.v:2084.12-2084.42" - wire width 8 \builder_csrbank5_dma_length1_r - attribute \src "ls180.v:2083.6-2083.37" - wire \builder_csrbank5_dma_length1_re - attribute \src "ls180.v:2086.12-2086.42" - wire width 8 \builder_csrbank5_dma_length1_w - attribute \src "ls180.v:2085.6-2085.37" - wire \builder_csrbank5_dma_length1_we - attribute \src "ls180.v:2080.12-2080.42" - wire width 8 \builder_csrbank5_dma_length2_r - attribute \src "ls180.v:2079.6-2079.37" - wire \builder_csrbank5_dma_length2_re - attribute \src "ls180.v:2082.12-2082.42" - wire width 8 \builder_csrbank5_dma_length2_w - attribute \src "ls180.v:2081.6-2081.37" - wire \builder_csrbank5_dma_length2_we - attribute \src "ls180.v:2076.12-2076.42" - wire width 8 \builder_csrbank5_dma_length3_r - attribute \src "ls180.v:2075.6-2075.37" - wire \builder_csrbank5_dma_length3_re - attribute \src "ls180.v:2078.12-2078.42" - wire width 8 \builder_csrbank5_dma_length3_w - attribute \src "ls180.v:2077.6-2077.37" - wire \builder_csrbank5_dma_length3_we - attribute \src "ls180.v:2100.6-2100.34" - wire \builder_csrbank5_dma_loop0_r - attribute \src "ls180.v:2099.6-2099.35" - wire \builder_csrbank5_dma_loop0_re - attribute \src "ls180.v:2102.6-2102.34" - wire \builder_csrbank5_dma_loop0_w - attribute \src "ls180.v:2101.6-2101.35" - wire \builder_csrbank5_dma_loop0_we - attribute \src "ls180.v:2116.12-2116.42" - wire width 8 \builder_csrbank5_dma_offset0_r - attribute \src "ls180.v:2115.6-2115.37" - wire \builder_csrbank5_dma_offset0_re - attribute \src "ls180.v:2118.12-2118.42" - wire width 8 \builder_csrbank5_dma_offset0_w - attribute \src "ls180.v:2117.6-2117.37" - wire \builder_csrbank5_dma_offset0_we - attribute \src "ls180.v:2112.12-2112.42" - wire width 8 \builder_csrbank5_dma_offset1_r - attribute \src "ls180.v:2111.6-2111.37" - wire \builder_csrbank5_dma_offset1_re - attribute \src "ls180.v:2114.12-2114.42" - wire width 8 \builder_csrbank5_dma_offset1_w - attribute \src "ls180.v:2113.6-2113.37" - wire \builder_csrbank5_dma_offset1_we - attribute \src "ls180.v:2108.12-2108.42" - wire width 8 \builder_csrbank5_dma_offset2_r - attribute \src "ls180.v:2107.6-2107.37" - wire \builder_csrbank5_dma_offset2_re - attribute \src "ls180.v:2110.12-2110.42" - wire width 8 \builder_csrbank5_dma_offset2_w - attribute \src "ls180.v:2109.6-2109.37" - wire \builder_csrbank5_dma_offset2_we - attribute \src "ls180.v:2104.12-2104.42" - wire width 8 \builder_csrbank5_dma_offset3_r - attribute \src "ls180.v:2103.6-2103.37" - wire \builder_csrbank5_dma_offset3_re - attribute \src "ls180.v:2106.12-2106.42" - wire width 8 \builder_csrbank5_dma_offset3_w - attribute \src "ls180.v:2105.6-2105.37" - wire \builder_csrbank5_dma_offset3_we - attribute \src "ls180.v:2119.6-2119.26" - wire \builder_csrbank5_sel - attribute \src "ls180.v:2125.6-2125.36" - wire \builder_csrbank6_card_detect_r - attribute \src "ls180.v:2124.6-2124.37" - wire \builder_csrbank6_card_detect_re - attribute \src "ls180.v:2127.6-2127.36" - wire \builder_csrbank6_card_detect_w - attribute \src "ls180.v:2126.6-2126.37" - wire \builder_csrbank6_card_detect_we - attribute \src "ls180.v:2133.12-2133.47" - wire width 8 \builder_csrbank6_clocker_divider0_r - attribute \src "ls180.v:2132.6-2132.42" - wire \builder_csrbank6_clocker_divider0_re - attribute \src "ls180.v:2135.12-2135.47" - wire width 8 \builder_csrbank6_clocker_divider0_w - attribute \src "ls180.v:2134.6-2134.42" - wire \builder_csrbank6_clocker_divider0_we - attribute \src "ls180.v:2129.6-2129.41" - wire \builder_csrbank6_clocker_divider1_r - attribute \src "ls180.v:2128.6-2128.42" - wire \builder_csrbank6_clocker_divider1_re - attribute \src "ls180.v:2131.6-2131.41" - wire \builder_csrbank6_clocker_divider1_w - attribute \src "ls180.v:2130.6-2130.42" - wire \builder_csrbank6_clocker_divider1_we - attribute \src "ls180.v:2136.6-2136.26" - wire \builder_csrbank6_sel - attribute \src "ls180.v:2142.12-2142.44" - wire width 4 \builder_csrbank7_dfii_control0_r - attribute \src "ls180.v:2141.6-2141.39" - wire \builder_csrbank7_dfii_control0_re - attribute \src "ls180.v:2144.12-2144.44" - wire width 4 \builder_csrbank7_dfii_control0_w - attribute \src "ls180.v:2143.6-2143.39" - wire \builder_csrbank7_dfii_control0_we - attribute \src "ls180.v:2154.12-2154.48" - wire width 8 \builder_csrbank7_dfii_pi0_address0_r - attribute \src "ls180.v:2153.6-2153.43" - wire \builder_csrbank7_dfii_pi0_address0_re - attribute \src "ls180.v:2156.12-2156.48" - wire width 8 \builder_csrbank7_dfii_pi0_address0_w - attribute \src "ls180.v:2155.6-2155.43" - wire \builder_csrbank7_dfii_pi0_address0_we - attribute \src "ls180.v:2150.12-2150.48" - wire width 5 \builder_csrbank7_dfii_pi0_address1_r - attribute \src "ls180.v:2149.6-2149.43" - wire \builder_csrbank7_dfii_pi0_address1_re - attribute \src "ls180.v:2152.12-2152.48" - wire width 5 \builder_csrbank7_dfii_pi0_address1_w - attribute \src "ls180.v:2151.6-2151.43" - wire \builder_csrbank7_dfii_pi0_address1_we - attribute \src "ls180.v:2158.12-2158.49" - wire width 2 \builder_csrbank7_dfii_pi0_baddress0_r - attribute \src "ls180.v:2157.6-2157.44" - wire \builder_csrbank7_dfii_pi0_baddress0_re - attribute \src "ls180.v:2160.12-2160.49" - wire width 2 \builder_csrbank7_dfii_pi0_baddress0_w - attribute \src "ls180.v:2159.6-2159.44" - wire \builder_csrbank7_dfii_pi0_baddress0_we - attribute \src "ls180.v:2146.12-2146.48" - wire width 6 \builder_csrbank7_dfii_pi0_command0_r - attribute \src "ls180.v:2145.6-2145.43" - wire \builder_csrbank7_dfii_pi0_command0_re - attribute \src "ls180.v:2148.12-2148.48" - wire width 6 \builder_csrbank7_dfii_pi0_command0_w - attribute \src "ls180.v:2147.6-2147.43" - wire \builder_csrbank7_dfii_pi0_command0_we - attribute \src "ls180.v:2174.12-2174.47" - wire width 8 \builder_csrbank7_dfii_pi0_rddata0_r - attribute \src "ls180.v:2173.6-2173.42" - wire \builder_csrbank7_dfii_pi0_rddata0_re - attribute \src "ls180.v:2176.12-2176.47" - wire width 8 \builder_csrbank7_dfii_pi0_rddata0_w - attribute \src "ls180.v:2175.6-2175.42" - wire \builder_csrbank7_dfii_pi0_rddata0_we - attribute \src "ls180.v:2170.12-2170.47" - wire width 8 \builder_csrbank7_dfii_pi0_rddata1_r - attribute \src "ls180.v:2169.6-2169.42" - wire \builder_csrbank7_dfii_pi0_rddata1_re - attribute \src "ls180.v:2172.12-2172.47" - wire width 8 \builder_csrbank7_dfii_pi0_rddata1_w - attribute \src "ls180.v:2171.6-2171.42" - wire \builder_csrbank7_dfii_pi0_rddata1_we - attribute \src "ls180.v:2166.12-2166.47" - wire width 8 \builder_csrbank7_dfii_pi0_wrdata0_r - attribute \src "ls180.v:2165.6-2165.42" - wire \builder_csrbank7_dfii_pi0_wrdata0_re - attribute \src "ls180.v:2168.12-2168.47" - wire width 8 \builder_csrbank7_dfii_pi0_wrdata0_w - attribute \src "ls180.v:2167.6-2167.42" - wire \builder_csrbank7_dfii_pi0_wrdata0_we - attribute \src "ls180.v:2162.12-2162.47" - wire width 8 \builder_csrbank7_dfii_pi0_wrdata1_r - attribute \src "ls180.v:2161.6-2161.42" - wire \builder_csrbank7_dfii_pi0_wrdata1_re - attribute \src "ls180.v:2164.12-2164.47" - wire width 8 \builder_csrbank7_dfii_pi0_wrdata1_w - attribute \src "ls180.v:2163.6-2163.42" - wire \builder_csrbank7_dfii_pi0_wrdata1_we - attribute \src "ls180.v:2177.6-2177.26" - wire \builder_csrbank7_sel - attribute \src "ls180.v:2187.12-2187.39" - wire width 8 \builder_csrbank8_control0_r - attribute \src "ls180.v:2186.6-2186.34" - wire \builder_csrbank8_control0_re - attribute \src "ls180.v:2189.12-2189.39" - wire width 8 \builder_csrbank8_control0_w - attribute \src "ls180.v:2188.6-2188.34" - wire \builder_csrbank8_control0_we - attribute \src "ls180.v:2183.12-2183.39" - wire width 8 \builder_csrbank8_control1_r - attribute \src "ls180.v:2182.6-2182.34" - wire \builder_csrbank8_control1_re - attribute \src "ls180.v:2185.12-2185.39" - wire width 8 \builder_csrbank8_control1_w - attribute \src "ls180.v:2184.6-2184.34" - wire \builder_csrbank8_control1_we - attribute \src "ls180.v:2203.6-2203.28" - wire \builder_csrbank8_cs0_r - attribute \src "ls180.v:2202.6-2202.29" - wire \builder_csrbank8_cs0_re - attribute \src "ls180.v:2205.6-2205.28" - wire \builder_csrbank8_cs0_w - attribute \src "ls180.v:2204.6-2204.29" - wire \builder_csrbank8_cs0_we - attribute \src "ls180.v:2207.6-2207.34" - wire \builder_csrbank8_loopback0_r - attribute \src "ls180.v:2206.6-2206.35" - wire \builder_csrbank8_loopback0_re - attribute \src "ls180.v:2209.6-2209.34" - wire \builder_csrbank8_loopback0_w - attribute \src "ls180.v:2208.6-2208.35" - wire \builder_csrbank8_loopback0_we - attribute \src "ls180.v:2199.12-2199.35" - wire width 8 \builder_csrbank8_miso_r - attribute \src "ls180.v:2198.6-2198.30" - wire \builder_csrbank8_miso_re - attribute \src "ls180.v:2201.12-2201.35" - wire width 8 \builder_csrbank8_miso_w - attribute \src "ls180.v:2200.6-2200.30" - wire \builder_csrbank8_miso_we - attribute \src "ls180.v:2195.12-2195.36" - wire width 8 \builder_csrbank8_mosi0_r - attribute \src "ls180.v:2194.6-2194.31" - wire \builder_csrbank8_mosi0_re - attribute \src "ls180.v:2197.12-2197.36" - wire width 8 \builder_csrbank8_mosi0_w - attribute \src "ls180.v:2196.6-2196.31" - wire \builder_csrbank8_mosi0_we - attribute \src "ls180.v:2210.6-2210.26" - wire \builder_csrbank8_sel - attribute \src "ls180.v:2191.6-2191.31" - wire \builder_csrbank8_status_r - attribute \src "ls180.v:2190.6-2190.32" - wire \builder_csrbank8_status_re - attribute \src "ls180.v:2193.6-2193.31" - wire \builder_csrbank8_status_w - attribute \src "ls180.v:2192.6-2192.32" - wire \builder_csrbank8_status_we - attribute \src "ls180.v:2248.12-2248.43" - wire width 8 \builder_csrbank9_clk_divider0_r - attribute \src "ls180.v:2247.6-2247.38" - wire \builder_csrbank9_clk_divider0_re - attribute \src "ls180.v:2250.12-2250.43" - wire width 8 \builder_csrbank9_clk_divider0_w - attribute \src "ls180.v:2249.6-2249.38" - wire \builder_csrbank9_clk_divider0_we - attribute \src "ls180.v:2244.12-2244.43" - wire width 8 \builder_csrbank9_clk_divider1_r - attribute \src "ls180.v:2243.6-2243.38" - wire \builder_csrbank9_clk_divider1_re - attribute \src "ls180.v:2246.12-2246.43" - wire width 8 \builder_csrbank9_clk_divider1_w - attribute \src "ls180.v:2245.6-2245.38" - wire \builder_csrbank9_clk_divider1_we - attribute \src "ls180.v:2220.12-2220.39" - wire width 8 \builder_csrbank9_control0_r - attribute \src "ls180.v:2219.6-2219.34" - wire \builder_csrbank9_control0_re - attribute \src "ls180.v:2222.12-2222.39" - wire width 8 \builder_csrbank9_control0_w - attribute \src "ls180.v:2221.6-2221.34" - wire \builder_csrbank9_control0_we - attribute \src "ls180.v:2216.12-2216.39" - wire width 8 \builder_csrbank9_control1_r - attribute \src "ls180.v:2215.6-2215.34" - wire \builder_csrbank9_control1_re - attribute \src "ls180.v:2218.12-2218.39" - wire width 8 \builder_csrbank9_control1_w - attribute \src "ls180.v:2217.6-2217.34" - wire \builder_csrbank9_control1_we - attribute \src "ls180.v:2236.6-2236.28" - wire \builder_csrbank9_cs0_r - attribute \src "ls180.v:2235.6-2235.29" - wire \builder_csrbank9_cs0_re - attribute \src "ls180.v:2238.6-2238.28" - wire \builder_csrbank9_cs0_w - attribute \src "ls180.v:2237.6-2237.29" - wire \builder_csrbank9_cs0_we - attribute \src "ls180.v:2240.6-2240.34" - wire \builder_csrbank9_loopback0_r - attribute \src "ls180.v:2239.6-2239.35" - wire \builder_csrbank9_loopback0_re - attribute \src "ls180.v:2242.6-2242.34" - wire \builder_csrbank9_loopback0_w - attribute \src "ls180.v:2241.6-2241.35" - wire \builder_csrbank9_loopback0_we - attribute \src "ls180.v:2232.12-2232.35" - wire width 8 \builder_csrbank9_miso_r - attribute \src "ls180.v:2231.6-2231.30" - wire \builder_csrbank9_miso_re - attribute \src "ls180.v:2234.12-2234.35" - wire width 8 \builder_csrbank9_miso_w - attribute \src "ls180.v:2233.6-2233.30" - wire \builder_csrbank9_miso_we - attribute \src "ls180.v:2228.12-2228.36" - wire width 8 \builder_csrbank9_mosi0_r - attribute \src "ls180.v:2227.6-2227.31" - wire \builder_csrbank9_mosi0_re - attribute \src "ls180.v:2230.12-2230.36" - wire width 8 \builder_csrbank9_mosi0_w - attribute \src "ls180.v:2229.6-2229.31" - wire \builder_csrbank9_mosi0_we - attribute \src "ls180.v:2251.6-2251.26" - wire \builder_csrbank9_sel - attribute \src "ls180.v:2224.6-2224.31" - wire \builder_csrbank9_status_r - attribute \src "ls180.v:2223.6-2223.32" - wire \builder_csrbank9_status_re - attribute \src "ls180.v:2226.6-2226.31" - wire \builder_csrbank9_status_w - attribute \src "ls180.v:2225.6-2225.32" - wire \builder_csrbank9_status_we - attribute \src "ls180.v:1780.6-1780.18" - wire \builder_done - attribute \src "ls180.v:1778.5-1778.18" - wire \builder_error - attribute \src "ls180.v:1775.11-1775.24" - wire width 2 \builder_grant - attribute \src "ls180.v:2446.6-2446.36" - wire \builder_inferedsdrtristate0__i - attribute \src "ls180.v:2444.5-2444.35" - wire \builder_inferedsdrtristate0__o - attribute \src "ls180.v:2445.5-2445.35" - wire \builder_inferedsdrtristate0_oe - attribute \src "ls180.v:2486.6-2486.37" - wire \builder_inferedsdrtristate10__i - attribute \src "ls180.v:2484.5-2484.36" - wire \builder_inferedsdrtristate10__o - attribute \src "ls180.v:2485.5-2485.36" - wire \builder_inferedsdrtristate10_oe - attribute \src "ls180.v:2490.6-2490.37" - wire \builder_inferedsdrtristate11__i - attribute \src "ls180.v:2488.5-2488.36" - wire \builder_inferedsdrtristate11__o - attribute \src "ls180.v:2489.5-2489.36" - wire \builder_inferedsdrtristate11_oe - attribute \src "ls180.v:2494.6-2494.37" - wire \builder_inferedsdrtristate12__i - attribute \src "ls180.v:2492.5-2492.36" - wire \builder_inferedsdrtristate12__o - attribute \src "ls180.v:2493.5-2493.36" - wire \builder_inferedsdrtristate12_oe - attribute \src "ls180.v:2498.6-2498.37" - wire \builder_inferedsdrtristate13__i - attribute \src "ls180.v:2496.5-2496.36" - wire \builder_inferedsdrtristate13__o - attribute \src "ls180.v:2497.5-2497.36" - wire \builder_inferedsdrtristate13_oe - attribute \src "ls180.v:2502.6-2502.37" - wire \builder_inferedsdrtristate14__i - attribute \src "ls180.v:2500.5-2500.36" - wire \builder_inferedsdrtristate14__o - attribute \src "ls180.v:2501.5-2501.36" - wire \builder_inferedsdrtristate14_oe - attribute \src "ls180.v:2506.6-2506.37" - wire \builder_inferedsdrtristate15__i - attribute \src "ls180.v:2504.5-2504.36" - wire \builder_inferedsdrtristate15__o - attribute \src "ls180.v:2505.5-2505.36" - wire \builder_inferedsdrtristate15_oe - attribute \src "ls180.v:2515.6-2515.37" - wire \builder_inferedsdrtristate16__i - attribute \src "ls180.v:2513.5-2513.36" - wire \builder_inferedsdrtristate16__o - attribute \src "ls180.v:2514.5-2514.36" - wire \builder_inferedsdrtristate16_oe - attribute \src "ls180.v:2519.6-2519.37" - wire \builder_inferedsdrtristate17__i - attribute \src "ls180.v:2517.5-2517.36" - wire \builder_inferedsdrtristate17__o - attribute \src "ls180.v:2518.5-2518.36" - wire \builder_inferedsdrtristate17_oe - attribute \src "ls180.v:2523.6-2523.37" - wire \builder_inferedsdrtristate18__i - attribute \src "ls180.v:2521.5-2521.36" - wire \builder_inferedsdrtristate18__o - attribute \src "ls180.v:2522.5-2522.36" - wire \builder_inferedsdrtristate18_oe - attribute \src "ls180.v:2527.6-2527.37" - wire \builder_inferedsdrtristate19__i - attribute \src "ls180.v:2525.5-2525.36" - wire \builder_inferedsdrtristate19__o - attribute \src "ls180.v:2526.5-2526.36" - wire \builder_inferedsdrtristate19_oe - attribute \src "ls180.v:2450.6-2450.36" - wire \builder_inferedsdrtristate1__i - attribute \src "ls180.v:2448.5-2448.35" - wire \builder_inferedsdrtristate1__o - attribute \src "ls180.v:2449.5-2449.35" - wire \builder_inferedsdrtristate1_oe - attribute \src "ls180.v:2531.6-2531.37" - wire \builder_inferedsdrtristate20__i - attribute \src "ls180.v:2529.5-2529.36" - wire \builder_inferedsdrtristate20__o - attribute \src "ls180.v:2530.5-2530.36" - wire \builder_inferedsdrtristate20_oe - attribute \src "ls180.v:2454.6-2454.36" - wire \builder_inferedsdrtristate2__i - attribute \src "ls180.v:2452.5-2452.35" - wire \builder_inferedsdrtristate2__o - attribute \src "ls180.v:2453.5-2453.35" - wire \builder_inferedsdrtristate2_oe - attribute \src "ls180.v:2458.6-2458.36" - wire \builder_inferedsdrtristate3__i - attribute \src "ls180.v:2456.5-2456.35" - wire \builder_inferedsdrtristate3__o - attribute \src "ls180.v:2457.5-2457.35" - wire \builder_inferedsdrtristate3_oe - attribute \src "ls180.v:2462.6-2462.36" - wire \builder_inferedsdrtristate4__i - attribute \src "ls180.v:2460.5-2460.35" - wire \builder_inferedsdrtristate4__o - attribute \src "ls180.v:2461.5-2461.35" - wire \builder_inferedsdrtristate4_oe - attribute \src "ls180.v:2466.6-2466.36" - wire \builder_inferedsdrtristate5__i - attribute \src "ls180.v:2464.5-2464.35" - wire \builder_inferedsdrtristate5__o - attribute \src "ls180.v:2465.5-2465.35" - wire \builder_inferedsdrtristate5_oe - attribute \src "ls180.v:2470.6-2470.36" - wire \builder_inferedsdrtristate6__i - attribute \src "ls180.v:2468.5-2468.35" - wire \builder_inferedsdrtristate6__o - attribute \src "ls180.v:2469.5-2469.35" - wire \builder_inferedsdrtristate6_oe - attribute \src "ls180.v:2474.6-2474.36" - wire \builder_inferedsdrtristate7__i - attribute \src "ls180.v:2472.5-2472.35" - wire \builder_inferedsdrtristate7__o - attribute \src "ls180.v:2473.5-2473.35" - wire \builder_inferedsdrtristate7_oe - attribute \src "ls180.v:2478.6-2478.36" - wire \builder_inferedsdrtristate8__i - attribute \src "ls180.v:2476.5-2476.35" - wire \builder_inferedsdrtristate8__o - attribute \src "ls180.v:2477.5-2477.35" - wire \builder_inferedsdrtristate8_oe - attribute \src "ls180.v:2482.6-2482.36" - wire \builder_inferedsdrtristate9__i - attribute \src "ls180.v:2480.5-2480.35" - wire \builder_inferedsdrtristate9__o - attribute \src "ls180.v:2481.5-2481.35" - wire \builder_inferedsdrtristate9_oe - attribute \src "ls180.v:1782.13-1782.44" - wire width 14 \builder_interface0_bank_bus_adr - attribute \src "ls180.v:1785.11-1785.44" - wire width 8 \builder_interface0_bank_bus_dat_r - attribute \src "ls180.v:1784.12-1784.45" - wire width 8 \builder_interface0_bank_bus_dat_w - attribute \src "ls180.v:1783.6-1783.36" - wire \builder_interface0_bank_bus_we - attribute \src "ls180.v:2252.13-2252.45" - wire width 14 \builder_interface10_bank_bus_adr - attribute \src "ls180.v:2255.11-2255.45" - wire width 8 \builder_interface10_bank_bus_dat_r - attribute \src "ls180.v:2254.12-2254.46" - wire width 8 \builder_interface10_bank_bus_dat_w - attribute \src "ls180.v:2253.6-2253.37" - wire \builder_interface10_bank_bus_we - attribute \src "ls180.v:2317.13-2317.45" - wire width 14 \builder_interface11_bank_bus_adr - attribute \src "ls180.v:2320.11-2320.45" - wire width 8 \builder_interface11_bank_bus_dat_r - attribute \src "ls180.v:2319.12-2319.46" - wire width 8 \builder_interface11_bank_bus_dat_w - attribute \src "ls180.v:2318.6-2318.37" - wire \builder_interface11_bank_bus_we - attribute \src "ls180.v:2342.13-2342.45" - wire width 14 \builder_interface12_bank_bus_adr - attribute \src "ls180.v:2345.11-2345.45" - wire width 8 \builder_interface12_bank_bus_dat_r - attribute \src "ls180.v:2344.12-2344.46" - wire width 8 \builder_interface12_bank_bus_dat_w - attribute \src "ls180.v:2343.6-2343.37" - wire \builder_interface12_bank_bus_we - attribute \src "ls180.v:1823.13-1823.44" - wire width 14 \builder_interface1_bank_bus_adr - attribute \src "ls180.v:1826.11-1826.44" - wire width 8 \builder_interface1_bank_bus_dat_r - attribute \src "ls180.v:1825.12-1825.45" - wire width 8 \builder_interface1_bank_bus_dat_w - attribute \src "ls180.v:1824.6-1824.36" - wire \builder_interface1_bank_bus_we - attribute \src "ls180.v:1832.13-1832.44" - wire width 14 \builder_interface2_bank_bus_adr - attribute \src "ls180.v:1835.11-1835.44" - wire width 8 \builder_interface2_bank_bus_dat_r - attribute \src "ls180.v:1834.12-1834.45" - wire width 8 \builder_interface2_bank_bus_dat_w - attribute \src "ls180.v:1833.6-1833.36" - wire \builder_interface2_bank_bus_we - attribute \src "ls180.v:1841.13-1841.44" - wire width 14 \builder_interface3_bank_bus_adr - attribute \src "ls180.v:1844.11-1844.44" - wire width 8 \builder_interface3_bank_bus_dat_r - attribute \src "ls180.v:1843.12-1843.45" - wire width 8 \builder_interface3_bank_bus_dat_w - attribute \src "ls180.v:1842.6-1842.36" - wire \builder_interface3_bank_bus_we - attribute \src "ls180.v:1906.13-1906.44" - wire width 14 \builder_interface4_bank_bus_adr - attribute \src "ls180.v:1909.11-1909.44" - wire width 8 \builder_interface4_bank_bus_dat_r - attribute \src "ls180.v:1908.12-1908.45" - wire width 8 \builder_interface4_bank_bus_dat_w - attribute \src "ls180.v:1907.6-1907.36" - wire \builder_interface4_bank_bus_we - attribute \src "ls180.v:2039.13-2039.44" - wire width 14 \builder_interface5_bank_bus_adr - attribute \src "ls180.v:2042.11-2042.44" - wire width 8 \builder_interface5_bank_bus_dat_r - attribute \src "ls180.v:2041.12-2041.45" - wire width 8 \builder_interface5_bank_bus_dat_w - attribute \src "ls180.v:2040.6-2040.36" - wire \builder_interface5_bank_bus_we - attribute \src "ls180.v:2120.13-2120.44" - wire width 14 \builder_interface6_bank_bus_adr - attribute \src "ls180.v:2123.11-2123.44" - wire width 8 \builder_interface6_bank_bus_dat_r - attribute \src "ls180.v:2122.12-2122.45" - wire width 8 \builder_interface6_bank_bus_dat_w - attribute \src "ls180.v:2121.6-2121.36" - wire \builder_interface6_bank_bus_we - attribute \src "ls180.v:2137.13-2137.44" - wire width 14 \builder_interface7_bank_bus_adr - attribute \src "ls180.v:2140.11-2140.44" - wire width 8 \builder_interface7_bank_bus_dat_r - attribute \src "ls180.v:2139.12-2139.45" - wire width 8 \builder_interface7_bank_bus_dat_w - attribute \src "ls180.v:2138.6-2138.36" - wire \builder_interface7_bank_bus_we - attribute \src "ls180.v:2178.13-2178.44" - wire width 14 \builder_interface8_bank_bus_adr - attribute \src "ls180.v:2181.11-2181.44" - wire width 8 \builder_interface8_bank_bus_dat_r - attribute \src "ls180.v:2180.12-2180.45" - wire width 8 \builder_interface8_bank_bus_dat_w - attribute \src "ls180.v:2179.6-2179.36" - wire \builder_interface8_bank_bus_we - attribute \src "ls180.v:2211.13-2211.44" - wire width 14 \builder_interface9_bank_bus_adr - attribute \src "ls180.v:2214.11-2214.44" - wire width 8 \builder_interface9_bank_bus_dat_r - attribute \src "ls180.v:2213.12-2213.45" - wire width 8 \builder_interface9_bank_bus_dat_w - attribute \src "ls180.v:2212.6-2212.36" - wire \builder_interface9_bank_bus_we - attribute \src "ls180.v:1748.12-1748.35" - wire width 14 \builder_libresocsim_adr - attribute \src "ls180.v:2371.12-2371.47" - wire width 14 \builder_libresocsim_adr_next_value1 - attribute \src "ls180.v:2372.5-2372.43" - wire \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:1751.12-1751.37" - wire width 8 \builder_libresocsim_dat_r - attribute \src "ls180.v:1750.11-1750.36" - wire width 8 \builder_libresocsim_dat_w - attribute \src "ls180.v:2369.11-2369.48" - wire width 8 \builder_libresocsim_dat_w_next_value0 - attribute \src "ls180.v:2370.5-2370.45" - wire \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:1749.5-1749.27" - wire \builder_libresocsim_we - attribute \src "ls180.v:2373.5-2373.39" - wire \builder_libresocsim_we_next_value2 - attribute \src "ls180.v:2374.5-2374.42" - wire \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:1758.5-1758.37" - wire \builder_libresocsim_wishbone_ack - attribute \src "ls180.v:1752.13-1752.45" - wire width 30 \builder_libresocsim_wishbone_adr - attribute \src "ls180.v:1761.12-1761.44" - wire width 2 \builder_libresocsim_wishbone_bte - attribute \src "ls180.v:1760.12-1760.44" - wire width 3 \builder_libresocsim_wishbone_cti - attribute \src "ls180.v:1756.6-1756.38" - wire \builder_libresocsim_wishbone_cyc - attribute \src "ls180.v:1754.12-1754.46" - wire width 32 \builder_libresocsim_wishbone_dat_r - attribute \src "ls180.v:1753.13-1753.47" - wire width 32 \builder_libresocsim_wishbone_dat_w - attribute \src "ls180.v:1762.5-1762.37" - wire \builder_libresocsim_wishbone_err - attribute \src "ls180.v:1755.12-1755.44" - wire width 4 \builder_libresocsim_wishbone_sel - attribute \src "ls180.v:1757.6-1757.38" - wire \builder_libresocsim_wishbone_stb - attribute \src "ls180.v:1759.6-1759.37" - wire \builder_libresocsim_wishbone_we - attribute \src "ls180.v:1651.5-1651.20" - wire \builder_locked0 - attribute \src "ls180.v:1652.5-1652.20" - wire \builder_locked1 - attribute \src "ls180.v:1653.5-1653.20" - wire \builder_locked2 - attribute \src "ls180.v:1654.5-1654.20" - wire \builder_locked3 - attribute \src "ls180.v:1638.11-1638.41" - wire width 3 \builder_multiplexer_next_state - attribute \src "ls180.v:1637.11-1637.36" - wire width 3 \builder_multiplexer_state - attribute \no_retiming "true" - attribute \src "ls180.v:2422.32-2422.59" - wire \builder_multiregimpl0_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2423.32-2423.59" - wire \builder_multiregimpl0_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2508.38-2508.65" - wire width 8 \builder_multiregimpl1_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2509.38-2509.65" - wire width 8 \builder_multiregimpl1_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2510.38-2510.65" - wire width 8 \builder_multiregimpl2_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2511.38-2511.65" - wire width 8 \builder_multiregimpl2_regs1 - attribute \src "ls180.v:1656.5-1656.36" - wire \builder_new_master_rdata_valid0 - attribute \src "ls180.v:1657.5-1657.36" - wire \builder_new_master_rdata_valid1 - attribute \src "ls180.v:1658.5-1658.36" - wire \builder_new_master_rdata_valid2 - attribute \src "ls180.v:1659.5-1659.36" - wire \builder_new_master_rdata_valid3 - attribute \src "ls180.v:1655.5-1655.35" - wire \builder_new_master_wdata_ready - attribute \src "ls180.v:2368.11-2368.29" - wire width 2 \builder_next_state - attribute \src "ls180.v:1628.11-1628.39" - wire width 2 \builder_refresher_next_state - attribute \src "ls180.v:1627.11-1627.34" - wire width 2 \builder_refresher_state - attribute \src "ls180.v:1774.12-1774.27" - wire width 4 \builder_request - attribute \src "ls180.v:1641.6-1641.28" - wire \builder_roundrobin0_ce - attribute \src "ls180.v:1640.6-1640.31" - wire \builder_roundrobin0_grant - attribute \src "ls180.v:1639.6-1639.33" - wire \builder_roundrobin0_request - attribute \src "ls180.v:1644.6-1644.28" - wire \builder_roundrobin1_ce - attribute \src "ls180.v:1643.6-1643.31" - wire \builder_roundrobin1_grant - attribute \src "ls180.v:1642.6-1642.33" - wire \builder_roundrobin1_request - attribute \src "ls180.v:1647.6-1647.28" - wire \builder_roundrobin2_ce - attribute \src "ls180.v:1646.6-1646.31" - wire \builder_roundrobin2_grant - attribute \src "ls180.v:1645.6-1645.33" - wire \builder_roundrobin2_request - attribute \src "ls180.v:1650.6-1650.28" - wire \builder_roundrobin3_ce - attribute \src "ls180.v:1649.6-1649.31" - wire \builder_roundrobin3_grant - attribute \src "ls180.v:1648.6-1648.33" - wire \builder_roundrobin3_request - attribute \src "ls180.v:1733.11-1733.44" - wire width 2 \builder_sdblock2memdma_next_state - attribute \src "ls180.v:1732.11-1732.39" - wire width 2 \builder_sdblock2memdma_state - attribute \src "ls180.v:1701.5-1701.50" - wire \builder_sdcore_crcupstreaminserter_next_state - attribute \src "ls180.v:1700.5-1700.45" - wire \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:1713.11-1713.40" - wire width 3 \builder_sdcore_fsm_next_state - attribute \src "ls180.v:1712.11-1712.35" - wire width 3 \builder_sdcore_fsm_state - attribute \src "ls180.v:1737.5-1737.42" - wire \builder_sdmem2blockdma_fsm_next_state - attribute \src "ls180.v:1736.5-1736.37" - wire \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:1741.11-1741.58" - wire width 2 \builder_sdmem2blockdma_resetinserter_next_state - attribute \src "ls180.v:1740.11-1740.53" - wire width 2 \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:1689.11-1689.39" - wire width 3 \builder_sdphy_fsm_next_state - attribute \src "ls180.v:1688.11-1688.34" - wire width 3 \builder_sdphy_fsm_state - attribute \src "ls180.v:1677.11-1677.45" - wire width 3 \builder_sdphy_sdphycmdr_next_state - attribute \src "ls180.v:1676.11-1676.40" - wire width 3 \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:1673.11-1673.45" - wire width 2 \builder_sdphy_sdphycmdw_next_state - attribute \src "ls180.v:1672.11-1672.40" - wire width 2 \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:1685.5-1685.39" - wire \builder_sdphy_sdphycrcr_next_state - attribute \src "ls180.v:1684.5-1684.34" - wire \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:1693.11-1693.46" - wire width 3 \builder_sdphy_sdphydatar_next_state - attribute \src "ls180.v:1692.11-1692.41" - wire width 3 \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:1669.5-1669.39" - wire \builder_sdphy_sdphyinit_next_state - attribute \src "ls180.v:1668.5-1668.34" - wire \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:1769.5-1769.23" - wire \builder_shared_ack - attribute \src "ls180.v:1763.13-1763.31" - wire width 30 \builder_shared_adr - attribute \src "ls180.v:1772.12-1772.30" - wire width 2 \builder_shared_bte - attribute \src "ls180.v:1771.12-1771.30" - wire width 3 \builder_shared_cti - attribute \src "ls180.v:1767.6-1767.24" - wire \builder_shared_cyc - attribute \src "ls180.v:1765.12-1765.32" - wire width 32 \builder_shared_dat_r - attribute \src "ls180.v:1764.13-1764.33" - wire width 32 \builder_shared_dat_w - attribute \src "ls180.v:1773.6-1773.24" - wire \builder_shared_err - attribute \src "ls180.v:1766.12-1766.30" - wire width 4 \builder_shared_sel - attribute \src "ls180.v:1768.6-1768.24" - wire \builder_shared_stb - attribute \src "ls180.v:1770.6-1770.23" - wire \builder_shared_we - attribute \src "ls180.v:1776.11-1776.28" - wire width 5 \builder_slave_sel - attribute \src "ls180.v:1777.11-1777.30" - wire width 5 \builder_slave_sel_r - attribute \src "ls180.v:1665.11-1665.40" - wire width 2 \builder_spimaster0_next_state - attribute \src "ls180.v:1664.11-1664.35" - wire width 2 \builder_spimaster0_state - attribute \src "ls180.v:1745.11-1745.40" - wire width 2 \builder_spimaster1_next_state - attribute \src "ls180.v:1744.11-1744.35" - wire width 2 \builder_spimaster1_state - attribute \src "ls180.v:2367.11-2367.24" - wire width 2 \builder_state - attribute \src "ls180.v:2420.5-2420.32" - wire \builder_sync_f_array_muxed0 - attribute \src "ls180.v:2421.5-2421.32" - wire \builder_sync_f_array_muxed1 - attribute \src "ls180.v:2413.11-2413.40" - wire width 2 \builder_sync_rhs_array_muxed0 - attribute \src "ls180.v:2414.12-2414.41" - wire width 13 \builder_sync_rhs_array_muxed1 - attribute \src "ls180.v:2415.5-2415.34" - wire \builder_sync_rhs_array_muxed2 - attribute \src "ls180.v:2416.5-2416.34" - wire \builder_sync_rhs_array_muxed3 - attribute \src "ls180.v:2417.5-2417.34" - wire \builder_sync_rhs_array_muxed4 - attribute \src "ls180.v:2418.5-2418.34" - wire \builder_sync_rhs_array_muxed5 - attribute \src "ls180.v:2419.5-2419.34" - wire \builder_sync_rhs_array_muxed6 - attribute \src "ls180.v:1779.6-1779.18" - wire \builder_wait - attribute \src "ls180.v:23.19-23.23" - wire width 3 input 19 \eint - attribute \src "ls180.v:17.19-17.26" - wire width 8 input 13 \gpio_in - attribute \src "ls180.v:18.19-18.27" - wire width 8 input 14 \gpio_out - attribute \src "ls180.v:1589.13-1589.37" - wire width 16 \libresocsim_clk_divider0 - attribute \src "ls180.v:1611.12-1611.36" - wire width 16 \libresocsim_clk_divider1 - attribute \src "ls180.v:1606.5-1606.27" - wire \libresocsim_clk_enable - attribute \src "ls180.v:1613.6-1613.26" - wire \libresocsim_clk_fall - attribute \src "ls180.v:1612.6-1612.26" - wire \libresocsim_clk_rise - attribute \src "ls180.v:949.6-949.28" - wire \libresocsim_clocker_ce - attribute \src "ls180.v:948.5-948.29" - wire \libresocsim_clocker_clk0 - attribute \src "ls180.v:951.5-951.29" - wire \libresocsim_clocker_clk1 - attribute \src "ls180.v:952.5-952.30" - wire \libresocsim_clocker_clk_d - attribute \src "ls180.v:950.11-950.35" - wire width 9 \libresocsim_clocker_clks - attribute \src "ls180.v:946.5-946.27" - wire \libresocsim_clocker_re - attribute \src "ls180.v:947.6-947.30" - wire \libresocsim_clocker_stop - attribute \src "ls180.v:945.11-945.38" - wire width 9 \libresocsim_clocker_storage - attribute \src "ls180.v:1049.6-1049.42" - wire \libresocsim_cmdr_cmdr_buf_sink_first - attribute \src "ls180.v:1050.6-1050.41" - wire \libresocsim_cmdr_cmdr_buf_sink_last - attribute \src "ls180.v:1051.12-1051.55" - wire width 8 \libresocsim_cmdr_cmdr_buf_sink_payload_data - attribute \src "ls180.v:1048.6-1048.42" - wire \libresocsim_cmdr_cmdr_buf_sink_ready - attribute \src "ls180.v:1047.6-1047.42" - wire \libresocsim_cmdr_cmdr_buf_sink_valid - attribute \src "ls180.v:1054.5-1054.43" - wire \libresocsim_cmdr_cmdr_buf_source_first - attribute \src "ls180.v:1055.5-1055.42" - wire \libresocsim_cmdr_cmdr_buf_source_last - attribute \src "ls180.v:1056.11-1056.56" - wire width 8 \libresocsim_cmdr_cmdr_buf_source_payload_data - attribute \src "ls180.v:1053.6-1053.44" - wire \libresocsim_cmdr_cmdr_buf_source_ready - attribute \src "ls180.v:1052.5-1052.43" - wire \libresocsim_cmdr_cmdr_buf_source_valid - attribute \src "ls180.v:1039.11-1039.48" - wire width 3 \libresocsim_cmdr_cmdr_converter_demux - attribute \src "ls180.v:1040.6-1040.47" - wire \libresocsim_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:1030.5-1030.47" - wire \libresocsim_cmdr_cmdr_converter_sink_first - attribute \src "ls180.v:1031.5-1031.46" - wire \libresocsim_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:1032.6-1032.55" - wire \libresocsim_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:1029.6-1029.48" - wire \libresocsim_cmdr_cmdr_converter_sink_ready - attribute \src "ls180.v:1028.6-1028.48" - wire \libresocsim_cmdr_cmdr_converter_sink_valid - attribute \src "ls180.v:1035.5-1035.49" - wire \libresocsim_cmdr_cmdr_converter_source_first - attribute \src "ls180.v:1036.5-1036.48" - wire \libresocsim_cmdr_cmdr_converter_source_last - attribute \src "ls180.v:1037.11-1037.62" - wire width 8 \libresocsim_cmdr_cmdr_converter_source_payload_data - attribute \src "ls180.v:1038.11-1038.75" - wire width 4 \libresocsim_cmdr_cmdr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1034.6-1034.50" - wire \libresocsim_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:1033.6-1033.50" - wire \libresocsim_cmdr_cmdr_converter_source_valid - attribute \src "ls180.v:1041.5-1041.47" - wire \libresocsim_cmdr_cmdr_converter_strobe_all - attribute \src "ls180.v:1012.6-1012.41" - wire \libresocsim_cmdr_cmdr_pads_in_first - attribute \src "ls180.v:1013.6-1013.40" - wire \libresocsim_cmdr_cmdr_pads_in_last - attribute \src "ls180.v:1014.6-1014.47" - wire \libresocsim_cmdr_cmdr_pads_in_payload_clk - attribute \src "ls180.v:1015.6-1015.49" - wire \libresocsim_cmdr_cmdr_pads_in_payload_cmd_i - attribute \src "ls180.v:1016.6-1016.49" - wire \libresocsim_cmdr_cmdr_pads_in_payload_cmd_o - attribute \src "ls180.v:1017.6-1017.50" - wire \libresocsim_cmdr_cmdr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1018.12-1018.56" - wire width 4 \libresocsim_cmdr_cmdr_pads_in_payload_data_i - attribute \src "ls180.v:1019.12-1019.56" - wire width 4 \libresocsim_cmdr_cmdr_pads_in_payload_data_o - attribute \src "ls180.v:1020.6-1020.51" - wire \libresocsim_cmdr_cmdr_pads_in_payload_data_oe - attribute \src "ls180.v:1011.5-1011.40" - wire \libresocsim_cmdr_cmdr_pads_in_ready - attribute \src "ls180.v:1010.6-1010.41" - wire \libresocsim_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:1057.5-1057.32" - wire \libresocsim_cmdr_cmdr_reset - attribute \src "ls180.v:1682.5-1682.60" - wire \libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 - attribute \src "ls180.v:1683.5-1683.63" - wire \libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:1027.5-1027.30" - wire \libresocsim_cmdr_cmdr_run - attribute \src "ls180.v:1023.6-1023.48" - wire \libresocsim_cmdr_cmdr_source_source_first0 - attribute \src "ls180.v:1044.6-1044.48" - wire \libresocsim_cmdr_cmdr_source_source_first1 - attribute \src "ls180.v:1024.6-1024.47" - wire \libresocsim_cmdr_cmdr_source_source_last0 - attribute \src "ls180.v:1045.6-1045.47" - wire \libresocsim_cmdr_cmdr_source_source_last1 - attribute \src "ls180.v:1025.12-1025.61" - wire width 8 \libresocsim_cmdr_cmdr_source_source_payload_data0 - attribute \src "ls180.v:1046.12-1046.61" - wire width 8 \libresocsim_cmdr_cmdr_source_source_payload_data1 - attribute \src "ls180.v:1022.5-1022.47" - wire \libresocsim_cmdr_cmdr_source_source_ready0 - attribute \src "ls180.v:1043.6-1043.48" - wire \libresocsim_cmdr_cmdr_source_source_ready1 - attribute \src "ls180.v:1021.6-1021.48" - wire \libresocsim_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:1042.6-1042.48" - wire \libresocsim_cmdr_cmdr_source_source_valid1 - attribute \src "ls180.v:1026.6-1026.33" - wire \libresocsim_cmdr_cmdr_start - attribute \src "ls180.v:1009.11-1009.33" - wire width 8 \libresocsim_cmdr_count - attribute \src "ls180.v:1678.11-1678.61" - wire width 8 \libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0 - attribute \src "ls180.v:1679.5-1679.58" - wire \libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:984.5-984.43" - wire \libresocsim_cmdr_pads_in_pads_in_first - attribute \src "ls180.v:985.5-985.42" - wire \libresocsim_cmdr_pads_in_pads_in_last - attribute \src "ls180.v:986.5-986.49" - wire \libresocsim_cmdr_pads_in_pads_in_payload_clk - attribute \src "ls180.v:987.6-987.52" - wire \libresocsim_cmdr_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:988.5-988.51" - wire \libresocsim_cmdr_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:989.5-989.52" - wire \libresocsim_cmdr_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:990.12-990.59" - wire width 4 \libresocsim_cmdr_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:991.11-991.58" - wire width 4 \libresocsim_cmdr_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:992.5-992.53" - wire \libresocsim_cmdr_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:983.6-983.44" - wire \libresocsim_cmdr_pads_in_pads_in_ready - attribute \src "ls180.v:982.6-982.44" - wire \libresocsim_cmdr_pads_in_pads_in_valid - attribute \src "ls180.v:994.5-994.42" - wire \libresocsim_cmdr_pads_out_payload_clk - attribute \src "ls180.v:995.5-995.44" - wire \libresocsim_cmdr_pads_out_payload_cmd_o - attribute \src "ls180.v:996.5-996.45" - wire \libresocsim_cmdr_pads_out_payload_cmd_oe - attribute \src "ls180.v:997.11-997.51" - wire width 4 \libresocsim_cmdr_pads_out_payload_data_o - attribute \src "ls180.v:998.5-998.46" - wire \libresocsim_cmdr_pads_out_payload_data_oe - attribute \src "ls180.v:993.6-993.37" - wire \libresocsim_cmdr_pads_out_ready - attribute \src "ls180.v:1001.5-1001.31" - wire \libresocsim_cmdr_sink_last - attribute \src "ls180.v:1002.11-1002.47" - wire width 8 \libresocsim_cmdr_sink_payload_length - attribute \src "ls180.v:1000.5-1000.32" - wire \libresocsim_cmdr_sink_ready - attribute \src "ls180.v:999.5-999.32" - wire \libresocsim_cmdr_sink_valid - attribute \src "ls180.v:1005.5-1005.33" - wire \libresocsim_cmdr_source_last - attribute \src "ls180.v:1006.11-1006.47" - wire width 8 \libresocsim_cmdr_source_payload_data - attribute \src "ls180.v:1007.11-1007.49" - wire width 3 \libresocsim_cmdr_source_payload_status - attribute \src "ls180.v:1004.5-1004.34" - wire \libresocsim_cmdr_source_ready - attribute \src "ls180.v:1003.5-1003.34" - wire \libresocsim_cmdr_source_valid - attribute \src "ls180.v:1008.12-1008.36" - wire width 32 \libresocsim_cmdr_timeout - attribute \src "ls180.v:1680.12-1680.64" - wire width 32 \libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1 - attribute \src "ls180.v:1681.5-1681.60" - wire \libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:981.11-981.33" - wire width 8 \libresocsim_cmdw_count - attribute \src "ls180.v:1674.11-1674.60" - wire width 8 \libresocsim_cmdw_count_sdphy_sdphycmdw_next_value - attribute \src "ls180.v:1675.5-1675.57" - wire \libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:980.5-980.26" - wire \libresocsim_cmdw_done - attribute \src "ls180.v:968.6-968.44" - wire \libresocsim_cmdw_pads_in_payload_cmd_i - attribute \src "ls180.v:969.12-969.51" - wire width 4 \libresocsim_cmdw_pads_in_payload_data_i - attribute \src "ls180.v:967.6-967.36" - wire \libresocsim_cmdw_pads_in_valid - attribute \src "ls180.v:971.5-971.42" - wire \libresocsim_cmdw_pads_out_payload_clk - attribute \src "ls180.v:972.5-972.44" - wire \libresocsim_cmdw_pads_out_payload_cmd_o - attribute \src "ls180.v:973.5-973.45" - wire \libresocsim_cmdw_pads_out_payload_cmd_oe - attribute \src "ls180.v:974.11-974.51" - wire width 4 \libresocsim_cmdw_pads_out_payload_data_o - attribute \src "ls180.v:975.5-975.46" - wire \libresocsim_cmdw_pads_out_payload_data_oe - attribute \src "ls180.v:970.6-970.37" - wire \libresocsim_cmdw_pads_out_ready - attribute \src "ls180.v:978.5-978.31" - wire \libresocsim_cmdw_sink_last - attribute \src "ls180.v:979.11-979.45" - wire width 8 \libresocsim_cmdw_sink_payload_data - attribute \src "ls180.v:977.5-977.32" - wire \libresocsim_cmdw_sink_ready - attribute \src "ls180.v:976.5-976.32" - wire \libresocsim_cmdw_sink_valid - attribute \src "ls180.v:1593.5-1593.27" - wire \libresocsim_control_re - attribute \src "ls180.v:1592.12-1592.39" - wire width 16 \libresocsim_control_storage - attribute \src "ls180.v:1608.11-1608.28" - wire width 3 \libresocsim_count - attribute \src "ls180.v:1746.11-1746.50" - wire width 3 \libresocsim_count_spimaster1_next_value - attribute \src "ls180.v:1747.5-1747.47" - wire \libresocsim_count_spimaster1_next_value_ce - attribute \src "ls180.v:1587.6-1587.20" - wire \libresocsim_cs - attribute \src "ls180.v:1607.5-1607.26" - wire \libresocsim_cs_enable - attribute \src "ls180.v:1603.5-1603.22" - wire \libresocsim_cs_re - attribute \src "ls180.v:1602.5-1602.27" - wire \libresocsim_cs_storage - attribute \src "ls180.v:1165.11-1165.34" - wire width 10 \libresocsim_datar_count - attribute \src "ls180.v:1694.11-1694.63" - wire width 10 \libresocsim_datar_count_sdphy_sdphydatar_next_value0 - attribute \src "ls180.v:1695.5-1695.60" - wire \libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:1205.6-1205.44" - wire \libresocsim_datar_datar_buf_sink_first - attribute \src "ls180.v:1206.6-1206.43" - wire \libresocsim_datar_datar_buf_sink_last - attribute \src "ls180.v:1207.12-1207.57" - wire width 8 \libresocsim_datar_datar_buf_sink_payload_data - attribute \src "ls180.v:1204.6-1204.44" - wire \libresocsim_datar_datar_buf_sink_ready - attribute \src "ls180.v:1203.6-1203.44" - wire \libresocsim_datar_datar_buf_sink_valid - attribute \src "ls180.v:1210.5-1210.45" - wire \libresocsim_datar_datar_buf_source_first - attribute \src "ls180.v:1211.5-1211.44" - wire \libresocsim_datar_datar_buf_source_last - attribute \src "ls180.v:1212.11-1212.58" - wire width 8 \libresocsim_datar_datar_buf_source_payload_data - attribute \src "ls180.v:1209.6-1209.46" - wire \libresocsim_datar_datar_buf_source_ready - attribute \src "ls180.v:1208.5-1208.45" - wire \libresocsim_datar_datar_buf_source_valid - attribute \src "ls180.v:1195.5-1195.44" - wire \libresocsim_datar_datar_converter_demux - attribute \src "ls180.v:1196.6-1196.49" - wire \libresocsim_datar_datar_converter_load_part - attribute \src "ls180.v:1186.5-1186.49" - wire \libresocsim_datar_datar_converter_sink_first - attribute \src "ls180.v:1187.5-1187.48" - wire \libresocsim_datar_datar_converter_sink_last - attribute \src "ls180.v:1188.12-1188.63" - wire width 4 \libresocsim_datar_datar_converter_sink_payload_data - attribute \src "ls180.v:1185.6-1185.50" - wire \libresocsim_datar_datar_converter_sink_ready - attribute \src "ls180.v:1184.6-1184.50" - wire \libresocsim_datar_datar_converter_sink_valid - attribute \src "ls180.v:1191.5-1191.51" - wire \libresocsim_datar_datar_converter_source_first - attribute \src "ls180.v:1192.5-1192.50" - wire \libresocsim_datar_datar_converter_source_last - attribute \src "ls180.v:1193.11-1193.64" - wire width 8 \libresocsim_datar_datar_converter_source_payload_data - attribute \src "ls180.v:1194.11-1194.77" - wire width 2 \libresocsim_datar_datar_converter_source_payload_valid_token_count - attribute \src "ls180.v:1190.6-1190.52" - wire \libresocsim_datar_datar_converter_source_ready - attribute \src "ls180.v:1189.6-1189.52" - wire \libresocsim_datar_datar_converter_source_valid - attribute \src "ls180.v:1197.5-1197.49" - wire \libresocsim_datar_datar_converter_strobe_all - attribute \src "ls180.v:1168.6-1168.43" - wire \libresocsim_datar_datar_pads_in_first - attribute \src "ls180.v:1169.6-1169.42" - wire \libresocsim_datar_datar_pads_in_last - attribute \src "ls180.v:1170.6-1170.49" - wire \libresocsim_datar_datar_pads_in_payload_clk - attribute \src "ls180.v:1171.6-1171.51" - wire \libresocsim_datar_datar_pads_in_payload_cmd_i - attribute \src "ls180.v:1172.6-1172.51" - wire \libresocsim_datar_datar_pads_in_payload_cmd_o - attribute \src "ls180.v:1173.6-1173.52" - wire \libresocsim_datar_datar_pads_in_payload_cmd_oe - attribute \src "ls180.v:1174.12-1174.58" - wire width 4 \libresocsim_datar_datar_pads_in_payload_data_i - attribute \src "ls180.v:1175.12-1175.58" - wire width 4 \libresocsim_datar_datar_pads_in_payload_data_o - attribute \src "ls180.v:1176.6-1176.53" - wire \libresocsim_datar_datar_pads_in_payload_data_oe - attribute \src "ls180.v:1167.5-1167.42" - wire \libresocsim_datar_datar_pads_in_ready - attribute \src "ls180.v:1166.6-1166.43" - wire \libresocsim_datar_datar_pads_in_valid - attribute \src "ls180.v:1213.5-1213.34" - wire \libresocsim_datar_datar_reset - attribute \src "ls180.v:1698.5-1698.63" - wire \libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value2 - attribute \src "ls180.v:1699.5-1699.66" - wire \libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:1183.5-1183.32" - wire \libresocsim_datar_datar_run - attribute \src "ls180.v:1179.6-1179.50" - wire \libresocsim_datar_datar_source_source_first0 - attribute \src "ls180.v:1200.6-1200.50" - wire \libresocsim_datar_datar_source_source_first1 - attribute \src "ls180.v:1180.6-1180.49" - wire \libresocsim_datar_datar_source_source_last0 - attribute \src "ls180.v:1201.6-1201.49" - wire \libresocsim_datar_datar_source_source_last1 - attribute \src "ls180.v:1181.12-1181.63" - wire width 8 \libresocsim_datar_datar_source_source_payload_data0 - attribute \src "ls180.v:1202.12-1202.63" - wire width 8 \libresocsim_datar_datar_source_source_payload_data1 - attribute \src "ls180.v:1178.5-1178.49" - wire \libresocsim_datar_datar_source_source_ready0 - attribute \src "ls180.v:1199.6-1199.50" - wire \libresocsim_datar_datar_source_source_ready1 - attribute \src "ls180.v:1177.6-1177.50" - wire \libresocsim_datar_datar_source_source_valid0 - attribute \src "ls180.v:1198.6-1198.50" - wire \libresocsim_datar_datar_source_source_valid1 - attribute \src "ls180.v:1182.6-1182.35" - wire \libresocsim_datar_datar_start - attribute \src "ls180.v:1138.5-1138.44" - wire \libresocsim_datar_pads_in_pads_in_first - attribute \src "ls180.v:1139.5-1139.43" - wire \libresocsim_datar_pads_in_pads_in_last - attribute \src "ls180.v:1140.5-1140.50" - wire \libresocsim_datar_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1141.6-1141.53" - wire \libresocsim_datar_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1142.5-1142.52" - wire \libresocsim_datar_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1143.5-1143.53" - wire \libresocsim_datar_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1144.12-1144.60" - wire width 4 \libresocsim_datar_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1145.11-1145.59" - wire width 4 \libresocsim_datar_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1146.5-1146.54" - wire \libresocsim_datar_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1137.6-1137.45" - wire \libresocsim_datar_pads_in_pads_in_ready - attribute \src "ls180.v:1136.6-1136.45" - wire \libresocsim_datar_pads_in_pads_in_valid - attribute \src "ls180.v:1148.5-1148.43" - wire \libresocsim_datar_pads_out_payload_clk - attribute \src "ls180.v:1149.5-1149.45" - wire \libresocsim_datar_pads_out_payload_cmd_o - attribute \src "ls180.v:1150.5-1150.46" - wire \libresocsim_datar_pads_out_payload_cmd_oe - attribute \src "ls180.v:1151.11-1151.52" - wire width 4 \libresocsim_datar_pads_out_payload_data_o - attribute \src "ls180.v:1152.5-1152.47" - wire \libresocsim_datar_pads_out_payload_data_oe - attribute \src "ls180.v:1147.6-1147.38" - wire \libresocsim_datar_pads_out_ready - attribute \src "ls180.v:1155.5-1155.32" - wire \libresocsim_datar_sink_last - attribute \src "ls180.v:1156.11-1156.54" - wire width 10 \libresocsim_datar_sink_payload_block_length - attribute \src "ls180.v:1154.5-1154.33" - wire \libresocsim_datar_sink_ready - attribute \src "ls180.v:1153.5-1153.33" - wire \libresocsim_datar_sink_valid - attribute \src "ls180.v:1159.5-1159.35" - wire \libresocsim_datar_source_first - attribute \src "ls180.v:1160.5-1160.34" - wire \libresocsim_datar_source_last - attribute \src "ls180.v:1161.11-1161.48" - wire width 8 \libresocsim_datar_source_payload_data - attribute \src "ls180.v:1162.11-1162.50" - wire width 3 \libresocsim_datar_source_payload_status - attribute \src "ls180.v:1158.5-1158.35" - wire \libresocsim_datar_source_ready - attribute \src "ls180.v:1157.5-1157.35" - wire \libresocsim_datar_source_valid - attribute \src "ls180.v:1163.5-1163.27" - wire \libresocsim_datar_stop - attribute \src "ls180.v:1164.12-1164.37" - wire width 32 \libresocsim_datar_timeout - attribute \src "ls180.v:1696.12-1696.66" - wire width 32 \libresocsim_datar_timeout_sdphy_sdphydatar_next_value1 - attribute \src "ls180.v:1697.5-1697.62" - wire \libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:1073.11-1073.34" - wire width 8 \libresocsim_dataw_count - attribute \src "ls180.v:1690.11-1690.55" - wire width 8 \libresocsim_dataw_count_sdphy_fsm_next_value - attribute \src "ls180.v:1691.5-1691.52" - wire \libresocsim_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:1127.6-1127.43" - wire \libresocsim_dataw_crcr_buf_sink_first - attribute \src "ls180.v:1128.6-1128.42" - wire \libresocsim_dataw_crcr_buf_sink_last - attribute \src "ls180.v:1129.12-1129.56" - wire width 8 \libresocsim_dataw_crcr_buf_sink_payload_data - attribute \src "ls180.v:1126.6-1126.43" - wire \libresocsim_dataw_crcr_buf_sink_ready - attribute \src "ls180.v:1125.6-1125.43" - wire \libresocsim_dataw_crcr_buf_sink_valid - attribute \src "ls180.v:1132.5-1132.44" - wire \libresocsim_dataw_crcr_buf_source_first - attribute \src "ls180.v:1133.5-1133.43" - wire \libresocsim_dataw_crcr_buf_source_last - attribute \src "ls180.v:1134.11-1134.57" - wire width 8 \libresocsim_dataw_crcr_buf_source_payload_data - attribute \src "ls180.v:1131.6-1131.45" - wire \libresocsim_dataw_crcr_buf_source_ready - attribute \src "ls180.v:1130.5-1130.44" - wire \libresocsim_dataw_crcr_buf_source_valid - attribute \src "ls180.v:1117.11-1117.49" - wire width 3 \libresocsim_dataw_crcr_converter_demux - attribute \src "ls180.v:1118.6-1118.48" - wire \libresocsim_dataw_crcr_converter_load_part - attribute \src "ls180.v:1108.5-1108.48" - wire \libresocsim_dataw_crcr_converter_sink_first - attribute \src "ls180.v:1109.5-1109.47" - wire \libresocsim_dataw_crcr_converter_sink_last - attribute \src "ls180.v:1110.6-1110.56" - wire \libresocsim_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:1107.6-1107.49" - wire \libresocsim_dataw_crcr_converter_sink_ready - attribute \src "ls180.v:1106.6-1106.49" - wire \libresocsim_dataw_crcr_converter_sink_valid - attribute \src "ls180.v:1113.5-1113.50" - wire \libresocsim_dataw_crcr_converter_source_first - attribute \src "ls180.v:1114.5-1114.49" - wire \libresocsim_dataw_crcr_converter_source_last - attribute \src "ls180.v:1115.11-1115.63" - wire width 8 \libresocsim_dataw_crcr_converter_source_payload_data - attribute \src "ls180.v:1116.11-1116.76" - wire width 4 \libresocsim_dataw_crcr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1112.6-1112.51" - wire \libresocsim_dataw_crcr_converter_source_ready - attribute \src "ls180.v:1111.6-1111.51" - wire \libresocsim_dataw_crcr_converter_source_valid - attribute \src "ls180.v:1119.5-1119.48" - wire \libresocsim_dataw_crcr_converter_strobe_all - attribute \src "ls180.v:1090.6-1090.42" - wire \libresocsim_dataw_crcr_pads_in_first - attribute \src "ls180.v:1091.6-1091.41" - wire \libresocsim_dataw_crcr_pads_in_last - attribute \src "ls180.v:1092.6-1092.48" - wire \libresocsim_dataw_crcr_pads_in_payload_clk - attribute \src "ls180.v:1093.6-1093.50" - wire \libresocsim_dataw_crcr_pads_in_payload_cmd_i - attribute \src "ls180.v:1094.6-1094.50" - wire \libresocsim_dataw_crcr_pads_in_payload_cmd_o - attribute \src "ls180.v:1095.6-1095.51" - wire \libresocsim_dataw_crcr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1096.12-1096.57" - wire width 4 \libresocsim_dataw_crcr_pads_in_payload_data_i - attribute \src "ls180.v:1097.12-1097.57" - wire width 4 \libresocsim_dataw_crcr_pads_in_payload_data_o - attribute \src "ls180.v:1098.6-1098.52" - wire \libresocsim_dataw_crcr_pads_in_payload_data_oe - attribute \src "ls180.v:1089.5-1089.41" - wire \libresocsim_dataw_crcr_pads_in_ready - attribute \src "ls180.v:1088.6-1088.42" - wire \libresocsim_dataw_crcr_pads_in_valid - attribute \src "ls180.v:1135.5-1135.33" - wire \libresocsim_dataw_crcr_reset - attribute \src "ls180.v:1686.5-1686.60" - wire \libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value - attribute \src "ls180.v:1687.5-1687.63" - wire \libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:1105.5-1105.31" - wire \libresocsim_dataw_crcr_run - attribute \src "ls180.v:1101.6-1101.49" - wire \libresocsim_dataw_crcr_source_source_first0 - attribute \src "ls180.v:1122.6-1122.49" - wire \libresocsim_dataw_crcr_source_source_first1 - attribute \src "ls180.v:1102.6-1102.48" - wire \libresocsim_dataw_crcr_source_source_last0 - attribute \src "ls180.v:1123.6-1123.48" - wire \libresocsim_dataw_crcr_source_source_last1 - attribute \src "ls180.v:1103.12-1103.62" - wire width 8 \libresocsim_dataw_crcr_source_source_payload_data0 - attribute \src "ls180.v:1124.12-1124.62" - wire width 8 \libresocsim_dataw_crcr_source_source_payload_data1 - attribute \src "ls180.v:1100.5-1100.48" - wire \libresocsim_dataw_crcr_source_source_ready0 - attribute \src "ls180.v:1121.6-1121.49" - wire \libresocsim_dataw_crcr_source_source_ready1 - attribute \src "ls180.v:1099.6-1099.49" - wire \libresocsim_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:1120.6-1120.49" - wire \libresocsim_dataw_crcr_source_source_valid1 - attribute \src "ls180.v:1104.6-1104.34" - wire \libresocsim_dataw_crcr_start - attribute \src "ls180.v:1087.5-1087.28" - wire \libresocsim_dataw_error - attribute \src "ls180.v:1076.5-1076.44" - wire \libresocsim_dataw_pads_in_pads_in_first - attribute \src "ls180.v:1077.5-1077.43" - wire \libresocsim_dataw_pads_in_pads_in_last - attribute \src "ls180.v:1078.5-1078.50" - wire \libresocsim_dataw_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1079.5-1079.52" - wire \libresocsim_dataw_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1080.5-1080.52" - wire \libresocsim_dataw_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1081.5-1081.53" - wire \libresocsim_dataw_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1082.11-1082.59" - wire width 4 \libresocsim_dataw_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1083.11-1083.59" - wire width 4 \libresocsim_dataw_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1084.5-1084.54" - wire \libresocsim_dataw_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1075.6-1075.45" - wire \libresocsim_dataw_pads_in_pads_in_ready - attribute \src "ls180.v:1074.5-1074.44" - wire \libresocsim_dataw_pads_in_pads_in_valid - attribute \src "ls180.v:1059.6-1059.45" - wire \libresocsim_dataw_pads_in_payload_cmd_i - attribute \src "ls180.v:1060.12-1060.52" - wire width 4 \libresocsim_dataw_pads_in_payload_data_i - attribute \src "ls180.v:1058.6-1058.37" - wire \libresocsim_dataw_pads_in_valid - attribute \src "ls180.v:1062.5-1062.43" - wire \libresocsim_dataw_pads_out_payload_clk - attribute \src "ls180.v:1063.5-1063.45" - wire \libresocsim_dataw_pads_out_payload_cmd_o - attribute \src "ls180.v:1064.5-1064.46" - wire \libresocsim_dataw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1065.11-1065.52" - wire width 4 \libresocsim_dataw_pads_out_payload_data_o - attribute \src "ls180.v:1066.5-1066.47" - wire \libresocsim_dataw_pads_out_payload_data_oe - attribute \src "ls180.v:1061.6-1061.38" - wire \libresocsim_dataw_pads_out_ready - attribute \src "ls180.v:1069.5-1069.33" - wire \libresocsim_dataw_sink_first - attribute \src "ls180.v:1070.5-1070.32" - wire \libresocsim_dataw_sink_last - attribute \src "ls180.v:1071.11-1071.46" - wire width 8 \libresocsim_dataw_sink_payload_data - attribute \src "ls180.v:1068.5-1068.33" - wire \libresocsim_dataw_sink_ready - attribute \src "ls180.v:1067.5-1067.33" - wire \libresocsim_dataw_sink_valid - attribute \src "ls180.v:1085.5-1085.28" - wire \libresocsim_dataw_start - attribute \src "ls180.v:1072.5-1072.27" - wire \libresocsim_dataw_stop - attribute \src "ls180.v:1086.5-1086.28" - wire \libresocsim_dataw_valid - attribute \src "ls180.v:1583.5-1583.22" - wire \libresocsim_done0 - attribute \src "ls180.v:1594.6-1594.23" - wire \libresocsim_done1 - attribute \src "ls180.v:966.11-966.33" - wire width 8 \libresocsim_init_count - attribute \src "ls180.v:1670.11-1670.60" - wire width 8 \libresocsim_init_count_sdphy_sdphyinit_next_value - attribute \src "ls180.v:1671.5-1671.57" - wire \libresocsim_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:954.6-954.35" - wire \libresocsim_init_initialize_r - attribute \src "ls180.v:953.6-953.36" - wire \libresocsim_init_initialize_re - attribute \src "ls180.v:956.5-956.34" - wire \libresocsim_init_initialize_w - attribute \src "ls180.v:955.6-955.36" - wire \libresocsim_init_initialize_we - attribute \src "ls180.v:958.6-958.44" - wire \libresocsim_init_pads_in_payload_cmd_i - attribute \src "ls180.v:959.12-959.51" - wire width 4 \libresocsim_init_pads_in_payload_data_i - attribute \src "ls180.v:957.6-957.36" - wire \libresocsim_init_pads_in_valid - attribute \src "ls180.v:961.5-961.42" - wire \libresocsim_init_pads_out_payload_clk - attribute \src "ls180.v:962.5-962.44" - wire \libresocsim_init_pads_out_payload_cmd_o - attribute \src "ls180.v:963.5-963.45" - wire \libresocsim_init_pads_out_payload_cmd_oe - attribute \src "ls180.v:964.11-964.51" - wire width 4 \libresocsim_init_pads_out_payload_data_o - attribute \src "ls180.v:965.5-965.46" - wire \libresocsim_init_pads_out_payload_data_oe - attribute \src "ls180.v:960.6-960.37" - wire \libresocsim_init_pads_out_ready - attribute \src "ls180.v:1402.6-1402.36" - wire \libresocsim_interface0_bus_ack - attribute \src "ls180.v:1396.13-1396.43" - wire width 32 \libresocsim_interface0_bus_adr - attribute \src "ls180.v:1405.11-1405.41" - wire width 2 \libresocsim_interface0_bus_bte - attribute \src "ls180.v:1404.11-1404.41" - wire width 3 \libresocsim_interface0_bus_cti - attribute \src "ls180.v:1400.6-1400.36" - wire \libresocsim_interface0_bus_cyc - attribute \src "ls180.v:1398.13-1398.45" - wire width 32 \libresocsim_interface0_bus_dat_r - attribute \src "ls180.v:1397.13-1397.45" - wire width 32 \libresocsim_interface0_bus_dat_w - attribute \src "ls180.v:1406.6-1406.36" - wire \libresocsim_interface0_bus_err - attribute \src "ls180.v:1399.12-1399.42" - wire width 4 \libresocsim_interface0_bus_sel - attribute \src "ls180.v:1401.6-1401.36" - wire \libresocsim_interface0_bus_stb - attribute \src "ls180.v:1403.6-1403.35" - wire \libresocsim_interface0_bus_we - attribute \src "ls180.v:1493.6-1493.36" - wire \libresocsim_interface1_bus_ack - attribute \src "ls180.v:1487.12-1487.42" - wire width 32 \libresocsim_interface1_bus_adr - attribute \src "ls180.v:1496.11-1496.41" - wire width 2 \libresocsim_interface1_bus_bte - attribute \src "ls180.v:1495.11-1495.41" - wire width 3 \libresocsim_interface1_bus_cti - attribute \src "ls180.v:1491.5-1491.35" - wire \libresocsim_interface1_bus_cyc - attribute \src "ls180.v:1489.13-1489.45" - wire width 32 \libresocsim_interface1_bus_dat_r - attribute \src "ls180.v:1488.12-1488.44" - wire width 32 \libresocsim_interface1_bus_dat_w - attribute \src "ls180.v:1497.6-1497.36" - wire \libresocsim_interface1_bus_err - attribute \src "ls180.v:1490.11-1490.41" - wire width 4 \libresocsim_interface1_bus_sel - attribute \src "ls180.v:1492.5-1492.35" - wire \libresocsim_interface1_bus_stb - attribute \src "ls180.v:1494.5-1494.34" - wire \libresocsim_interface1_bus_we - attribute \src "ls180.v:1584.5-1584.20" - wire \libresocsim_irq - attribute \src "ls180.v:1582.12-1582.31" - wire width 8 \libresocsim_length0 - attribute \src "ls180.v:1591.12-1591.31" - wire width 8 \libresocsim_length1 - attribute \src "ls180.v:1588.6-1588.26" - wire \libresocsim_loopback - attribute \src "ls180.v:1605.5-1605.28" - wire \libresocsim_loopback_re - attribute \src "ls180.v:1604.5-1604.33" - wire \libresocsim_loopback_storage - attribute \src "ls180.v:1586.11-1586.27" - wire width 8 \libresocsim_miso - attribute \src "ls180.v:1616.11-1616.32" - wire width 8 \libresocsim_miso_data - attribute \src "ls180.v:1610.5-1610.27" - wire \libresocsim_miso_latch - attribute \src "ls180.v:1599.12-1599.35" - wire width 8 \libresocsim_miso_status - attribute \src "ls180.v:1600.6-1600.25" - wire \libresocsim_miso_we - attribute \src "ls180.v:1585.12-1585.28" - wire width 8 \libresocsim_mosi - attribute \src "ls180.v:1614.11-1614.32" - wire width 8 \libresocsim_mosi_data - attribute \src "ls180.v:1609.5-1609.27" - wire \libresocsim_mosi_latch - attribute \src "ls180.v:1598.5-1598.24" - wire \libresocsim_mosi_re - attribute \src "ls180.v:1615.11-1615.31" - wire width 3 \libresocsim_mosi_sel - attribute \src "ls180.v:1597.11-1597.35" - wire width 8 \libresocsim_mosi_storage - attribute \src "ls180.v:1618.5-1618.19" - wire \libresocsim_re - attribute \src "ls180.v:1456.11-1456.50" - wire width 2 \libresocsim_sdblock2mem_converter_demux - attribute \src "ls180.v:1457.6-1457.49" - wire \libresocsim_sdblock2mem_converter_load_part - attribute \src "ls180.v:1447.6-1447.50" - wire \libresocsim_sdblock2mem_converter_sink_first - attribute \src "ls180.v:1448.6-1448.49" - wire \libresocsim_sdblock2mem_converter_sink_last - attribute \src "ls180.v:1449.12-1449.63" - wire width 8 \libresocsim_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:1446.6-1446.50" - wire \libresocsim_sdblock2mem_converter_sink_ready - attribute \src "ls180.v:1445.6-1445.50" - wire \libresocsim_sdblock2mem_converter_sink_valid - attribute \src "ls180.v:1452.5-1452.51" - wire \libresocsim_sdblock2mem_converter_source_first - attribute \src "ls180.v:1453.5-1453.50" - wire \libresocsim_sdblock2mem_converter_source_last - attribute \src "ls180.v:1454.12-1454.65" - wire width 32 \libresocsim_sdblock2mem_converter_source_payload_data - attribute \src "ls180.v:1455.11-1455.77" - wire width 3 \libresocsim_sdblock2mem_converter_source_payload_valid_token_count - attribute \src "ls180.v:1451.6-1451.52" - wire \libresocsim_sdblock2mem_converter_source_ready - attribute \src "ls180.v:1450.6-1450.52" - wire \libresocsim_sdblock2mem_converter_source_valid - attribute \src "ls180.v:1458.5-1458.49" - wire \libresocsim_sdblock2mem_converter_strobe_all - attribute \src "ls180.v:1431.11-1431.47" - wire width 5 \libresocsim_sdblock2mem_fifo_consume - attribute \src "ls180.v:1436.6-1436.42" - wire \libresocsim_sdblock2mem_fifo_do_read - attribute \src "ls180.v:1440.6-1440.48" - wire \libresocsim_sdblock2mem_fifo_fifo_in_first - attribute \src "ls180.v:1441.6-1441.47" - wire \libresocsim_sdblock2mem_fifo_fifo_in_last - attribute \src "ls180.v:1439.12-1439.61" - wire width 8 \libresocsim_sdblock2mem_fifo_fifo_in_payload_data - attribute \src "ls180.v:1443.6-1443.49" - wire \libresocsim_sdblock2mem_fifo_fifo_out_first - attribute \src "ls180.v:1444.6-1444.48" - wire \libresocsim_sdblock2mem_fifo_fifo_out_last - attribute \src "ls180.v:1442.12-1442.62" - wire width 8 \libresocsim_sdblock2mem_fifo_fifo_out_payload_data - attribute \src "ls180.v:1428.11-1428.45" - wire width 6 \libresocsim_sdblock2mem_fifo_level - attribute \src "ls180.v:1430.11-1430.47" - wire width 5 \libresocsim_sdblock2mem_fifo_produce - attribute \src "ls180.v:1437.12-1437.51" - wire width 5 \libresocsim_sdblock2mem_fifo_rdport_adr - attribute \src "ls180.v:1438.12-1438.53" - wire width 10 \libresocsim_sdblock2mem_fifo_rdport_dat_r - attribute \src "ls180.v:1429.5-1429.41" - wire \libresocsim_sdblock2mem_fifo_replace - attribute \src "ls180.v:1414.6-1414.45" - wire \libresocsim_sdblock2mem_fifo_sink_first - attribute \src "ls180.v:1415.6-1415.44" - wire \libresocsim_sdblock2mem_fifo_sink_last - attribute \src "ls180.v:1416.12-1416.58" - wire width 8 \libresocsim_sdblock2mem_fifo_sink_payload_data - attribute \src "ls180.v:1413.6-1413.45" - wire \libresocsim_sdblock2mem_fifo_sink_ready - attribute \src "ls180.v:1412.6-1412.45" - wire \libresocsim_sdblock2mem_fifo_sink_valid - attribute \src "ls180.v:1419.6-1419.47" - wire \libresocsim_sdblock2mem_fifo_source_first - attribute \src "ls180.v:1420.6-1420.46" - wire \libresocsim_sdblock2mem_fifo_source_last - attribute \src "ls180.v:1421.12-1421.60" - wire width 8 \libresocsim_sdblock2mem_fifo_source_payload_data - attribute \src "ls180.v:1418.6-1418.47" - wire \libresocsim_sdblock2mem_fifo_source_ready - attribute \src "ls180.v:1417.6-1417.47" - wire \libresocsim_sdblock2mem_fifo_source_valid - attribute \src "ls180.v:1426.12-1426.53" - wire width 10 \libresocsim_sdblock2mem_fifo_syncfifo_din - attribute \src "ls180.v:1427.12-1427.54" - wire width 10 \libresocsim_sdblock2mem_fifo_syncfifo_dout - attribute \src "ls180.v:1424.6-1424.46" - wire \libresocsim_sdblock2mem_fifo_syncfifo_re - attribute \src "ls180.v:1425.6-1425.52" - wire \libresocsim_sdblock2mem_fifo_syncfifo_readable - attribute \src "ls180.v:1422.6-1422.46" - wire \libresocsim_sdblock2mem_fifo_syncfifo_we - attribute \src "ls180.v:1423.6-1423.52" - wire \libresocsim_sdblock2mem_fifo_syncfifo_writable - attribute \src "ls180.v:1432.11-1432.50" - wire width 5 \libresocsim_sdblock2mem_fifo_wrport_adr - attribute \src "ls180.v:1433.12-1433.53" - wire width 10 \libresocsim_sdblock2mem_fifo_wrport_dat_r - attribute \src "ls180.v:1435.12-1435.53" - wire width 10 \libresocsim_sdblock2mem_fifo_wrport_dat_w - attribute \src "ls180.v:1434.6-1434.44" - wire \libresocsim_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:1409.6-1409.45" - wire \libresocsim_sdblock2mem_sink_sink_first - attribute \src "ls180.v:1410.6-1410.44" - wire \libresocsim_sdblock2mem_sink_sink_last - attribute \src "ls180.v:1466.12-1466.61" - wire width 32 \libresocsim_sdblock2mem_sink_sink_payload_address - attribute \src "ls180.v:1411.12-1411.59" - wire width 8 \libresocsim_sdblock2mem_sink_sink_payload_data0 - attribute \src "ls180.v:1467.12-1467.59" - wire width 32 \libresocsim_sdblock2mem_sink_sink_payload_data1 - attribute \src "ls180.v:1408.6-1408.46" - wire \libresocsim_sdblock2mem_sink_sink_ready0 - attribute \src "ls180.v:1465.6-1465.46" - wire \libresocsim_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:1407.6-1407.46" - wire \libresocsim_sdblock2mem_sink_sink_valid0 - attribute \src "ls180.v:1464.5-1464.45" - wire \libresocsim_sdblock2mem_sink_sink_valid1 - attribute \src "ls180.v:1461.6-1461.49" - wire \libresocsim_sdblock2mem_source_source_first - attribute \src "ls180.v:1462.6-1462.48" - wire \libresocsim_sdblock2mem_source_source_last - attribute \src "ls180.v:1463.13-1463.63" - wire width 32 \libresocsim_sdblock2mem_source_source_payload_data - attribute \src "ls180.v:1460.6-1460.49" - wire \libresocsim_sdblock2mem_source_source_ready - attribute \src "ls180.v:1459.6-1459.49" - wire \libresocsim_sdblock2mem_source_source_valid - attribute \src "ls180.v:1483.13-1483.59" - wire width 32 \libresocsim_sdblock2mem_wishbonedmawriter_base - attribute \src "ls180.v:1474.5-1474.54" - wire \libresocsim_sdblock2mem_wishbonedmawriter_base_re - attribute \src "ls180.v:1473.12-1473.66" - wire width 64 \libresocsim_sdblock2mem_wishbonedmawriter_base_storage - attribute \src "ls180.v:1478.5-1478.56" - wire \libresocsim_sdblock2mem_wishbonedmawriter_enable_re - attribute \src "ls180.v:1477.5-1477.61" - wire \libresocsim_sdblock2mem_wishbonedmawriter_enable_storage - attribute \src "ls180.v:1485.13-1485.61" - wire width 32 \libresocsim_sdblock2mem_wishbonedmawriter_length - attribute \src "ls180.v:1476.5-1476.56" - wire \libresocsim_sdblock2mem_wishbonedmawriter_length_re - attribute \src "ls180.v:1475.12-1475.68" - wire width 32 \libresocsim_sdblock2mem_wishbonedmawriter_length_storage - attribute \src "ls180.v:1482.5-1482.54" - wire \libresocsim_sdblock2mem_wishbonedmawriter_loop_re - attribute \src "ls180.v:1481.5-1481.59" - wire \libresocsim_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:1484.12-1484.60" - wire width 32 \libresocsim_sdblock2mem_wishbonedmawriter_offset - attribute \src "ls180.v:1734.12-1734.86" - wire width 32 \libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value - attribute \src "ls180.v:1735.5-1735.82" - wire \libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:1486.6-1486.53" - wire \libresocsim_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:1470.6-1470.58" - wire \libresocsim_sdblock2mem_wishbonedmawriter_sink_first - attribute \src "ls180.v:1471.6-1471.57" - wire \libresocsim_sdblock2mem_wishbonedmawriter_sink_last - attribute \src "ls180.v:1472.13-1472.72" - wire width 32 \libresocsim_sdblock2mem_wishbonedmawriter_sink_payload_data - attribute \src "ls180.v:1469.5-1469.57" - wire \libresocsim_sdblock2mem_wishbonedmawriter_sink_ready - attribute \src "ls180.v:1468.6-1468.58" - wire \libresocsim_sdblock2mem_wishbonedmawriter_sink_valid - attribute \src "ls180.v:1479.5-1479.53" - wire \libresocsim_sdblock2mem_wishbonedmawriter_status - attribute \src "ls180.v:1480.6-1480.50" - wire \libresocsim_sdblock2mem_wishbonedmawriter_we - attribute \src "ls180.v:1248.5-1248.38" - wire \libresocsim_sdcore_block_count_re - attribute \src "ls180.v:1247.12-1247.50" - wire width 32 \libresocsim_sdcore_block_count_storage - attribute \src "ls180.v:1246.5-1246.39" - wire \libresocsim_sdcore_block_length_re - attribute \src "ls180.v:1245.11-1245.50" - wire width 10 \libresocsim_sdcore_block_length_storage - attribute \src "ls180.v:1232.5-1232.39" - wire \libresocsim_sdcore_cmd_argument_re - attribute \src "ls180.v:1231.12-1231.51" - wire width 32 \libresocsim_sdcore_cmd_argument_storage - attribute \src "ls180.v:1234.5-1234.38" - wire \libresocsim_sdcore_cmd_command_re - attribute \src "ls180.v:1233.12-1233.50" - wire width 32 \libresocsim_sdcore_cmd_command_storage - attribute \src "ls180.v:1387.11-1387.39" - wire width 3 \libresocsim_sdcore_cmd_count - attribute \src "ls180.v:1718.11-1718.62" - wire width 3 \libresocsim_sdcore_cmd_count_sdcore_fsm_next_value2 - attribute \src "ls180.v:1719.5-1719.59" - wire \libresocsim_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:1388.5-1388.32" - wire \libresocsim_sdcore_cmd_done - attribute \src "ls180.v:1714.5-1714.55" - wire \libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0 - attribute \src "ls180.v:1715.5-1715.58" - wire \libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:1389.5-1389.33" - wire \libresocsim_sdcore_cmd_error - attribute \src "ls180.v:1722.5-1722.56" - wire \libresocsim_sdcore_cmd_error_sdcore_fsm_next_value4 - attribute \src "ls180.v:1723.5-1723.59" - wire \libresocsim_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:1241.12-1241.47" - wire width 4 \libresocsim_sdcore_cmd_event_status - attribute \src "ls180.v:1242.6-1242.37" - wire \libresocsim_sdcore_cmd_event_we - attribute \src "ls180.v:1239.13-1239.51" - wire width 128 \libresocsim_sdcore_cmd_response_status - attribute \src "ls180.v:1730.13-1730.74" - wire width 128 \libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value8 - attribute \src "ls180.v:1731.5-1731.69" - wire \libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:1240.6-1240.40" - wire \libresocsim_sdcore_cmd_response_we - attribute \src "ls180.v:1236.6-1236.35" - wire \libresocsim_sdcore_cmd_send_r - attribute \src "ls180.v:1235.6-1235.36" - wire \libresocsim_sdcore_cmd_send_re - attribute \src "ls180.v:1238.5-1238.34" - wire \libresocsim_sdcore_cmd_send_w - attribute \src "ls180.v:1237.6-1237.36" - wire \libresocsim_sdcore_cmd_send_we - attribute \src "ls180.v:1390.5-1390.35" - wire \libresocsim_sdcore_cmd_timeout - attribute \src "ls180.v:1724.5-1724.58" - wire \libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value5 - attribute \src "ls180.v:1725.5-1725.61" - wire \libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:1386.12-1386.39" - wire width 2 \libresocsim_sdcore_cmd_type - attribute \src "ls180.v:1348.11-1348.47" - wire width 4 \libresocsim_sdcore_crc16_checker_cnt - attribute \src "ls180.v:1354.5-1354.46" - wire \libresocsim_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:1353.12-1353.53" - wire width 16 \libresocsim_sdcore_crc16_checker_crc0_crc - attribute \src "ls180.v:1349.12-1349.57" - wire width 16 \libresocsim_sdcore_crc16_checker_crc0_crcreg0 - attribute \src "ls180.v:1350.13-1350.58" - wire width 16 \libresocsim_sdcore_crc16_checker_crc0_crcreg1 - attribute \src "ls180.v:1351.13-1351.58" - wire width 16 \libresocsim_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:1355.6-1355.50" - wire \libresocsim_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:1352.12-1352.53" - wire width 2 \libresocsim_sdcore_crc16_checker_crc0_val - attribute \src "ls180.v:1361.5-1361.46" - wire \libresocsim_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:1360.12-1360.53" - wire width 16 \libresocsim_sdcore_crc16_checker_crc1_crc - attribute \src "ls180.v:1356.12-1356.57" - wire width 16 \libresocsim_sdcore_crc16_checker_crc1_crcreg0 - attribute \src "ls180.v:1357.13-1357.58" - wire width 16 \libresocsim_sdcore_crc16_checker_crc1_crcreg1 - attribute \src "ls180.v:1358.13-1358.58" - wire width 16 \libresocsim_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:1362.6-1362.50" - wire \libresocsim_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:1359.12-1359.53" - wire width 2 \libresocsim_sdcore_crc16_checker_crc1_val - attribute \src "ls180.v:1368.5-1368.46" - wire \libresocsim_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:1367.12-1367.53" - wire width 16 \libresocsim_sdcore_crc16_checker_crc2_crc - attribute \src "ls180.v:1363.12-1363.57" - wire width 16 \libresocsim_sdcore_crc16_checker_crc2_crcreg0 - attribute \src "ls180.v:1364.13-1364.58" - wire width 16 \libresocsim_sdcore_crc16_checker_crc2_crcreg1 - attribute \src "ls180.v:1365.13-1365.58" - wire width 16 \libresocsim_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:1369.6-1369.50" - wire \libresocsim_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:1366.12-1366.53" - wire width 2 \libresocsim_sdcore_crc16_checker_crc2_val - attribute \src "ls180.v:1375.5-1375.46" - wire \libresocsim_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:1374.12-1374.53" - wire width 16 \libresocsim_sdcore_crc16_checker_crc3_crc - attribute \src "ls180.v:1370.12-1370.57" - wire width 16 \libresocsim_sdcore_crc16_checker_crc3_crcreg0 - attribute \src "ls180.v:1371.13-1371.58" - wire width 16 \libresocsim_sdcore_crc16_checker_crc3_crcreg1 - attribute \src "ls180.v:1372.13-1372.58" - wire width 16 \libresocsim_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:1376.6-1376.50" - wire \libresocsim_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:1373.12-1373.53" - wire width 2 \libresocsim_sdcore_crc16_checker_crc3_val - attribute \src "ls180.v:1377.12-1377.52" - wire width 16 \libresocsim_sdcore_crc16_checker_crctmp0 - attribute \src "ls180.v:1378.12-1378.52" - wire width 16 \libresocsim_sdcore_crc16_checker_crctmp1 - attribute \src "ls180.v:1379.12-1379.52" - wire width 16 \libresocsim_sdcore_crc16_checker_crctmp2 - attribute \src "ls180.v:1380.12-1380.52" - wire width 16 \libresocsim_sdcore_crc16_checker_crctmp3 - attribute \src "ls180.v:1382.12-1382.50" - wire width 16 \libresocsim_sdcore_crc16_checker_fifo0 - attribute \src "ls180.v:1383.12-1383.50" - wire width 16 \libresocsim_sdcore_crc16_checker_fifo1 - attribute \src "ls180.v:1384.12-1384.50" - wire width 16 \libresocsim_sdcore_crc16_checker_fifo2 - attribute \src "ls180.v:1385.12-1385.50" - wire width 16 \libresocsim_sdcore_crc16_checker_fifo3 - attribute \src "ls180.v:1339.5-1339.48" - wire \libresocsim_sdcore_crc16_checker_sink_first - attribute \src "ls180.v:1340.5-1340.47" - wire \libresocsim_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:1341.11-1341.61" - wire width 8 \libresocsim_sdcore_crc16_checker_sink_payload_data - attribute \src "ls180.v:1338.5-1338.48" - wire \libresocsim_sdcore_crc16_checker_sink_ready - attribute \src "ls180.v:1337.5-1337.48" - wire \libresocsim_sdcore_crc16_checker_sink_valid - attribute \src "ls180.v:1344.5-1344.50" - wire \libresocsim_sdcore_crc16_checker_source_first - attribute \src "ls180.v:1345.6-1345.50" - wire \libresocsim_sdcore_crc16_checker_source_last - attribute \src "ls180.v:1346.12-1346.64" - wire width 8 \libresocsim_sdcore_crc16_checker_source_payload_data - attribute \src "ls180.v:1343.6-1343.51" - wire \libresocsim_sdcore_crc16_checker_source_ready - attribute \src "ls180.v:1342.5-1342.50" - wire \libresocsim_sdcore_crc16_checker_source_valid - attribute \src "ls180.v:1347.11-1347.47" - wire width 8 \libresocsim_sdcore_crc16_checker_val - attribute \src "ls180.v:1381.5-1381.43" - wire \libresocsim_sdcore_crc16_checker_valid - attribute \src "ls180.v:1304.11-1304.48" - wire width 3 \libresocsim_sdcore_crc16_inserter_cnt - attribute \src "ls180.v:1710.11-1710.87" - wire width 3 \libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 - attribute \src "ls180.v:1711.5-1711.84" - wire \libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:1310.6-1310.48" - wire \libresocsim_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:1309.12-1309.54" - wire width 16 \libresocsim_sdcore_crc16_inserter_crc0_crc - attribute \src "ls180.v:1305.12-1305.58" - wire width 16 \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 - attribute \src "ls180.v:1306.13-1306.59" - wire width 16 \libresocsim_sdcore_crc16_inserter_crc0_crcreg1 - attribute \src "ls180.v:1307.13-1307.59" - wire width 16 \libresocsim_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:1311.6-1311.51" - wire \libresocsim_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:1308.12-1308.54" - wire width 2 \libresocsim_sdcore_crc16_inserter_crc0_val - attribute \src "ls180.v:1317.6-1317.48" - wire \libresocsim_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:1316.12-1316.54" - wire width 16 \libresocsim_sdcore_crc16_inserter_crc1_crc - attribute \src "ls180.v:1312.12-1312.58" - wire width 16 \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 - attribute \src "ls180.v:1313.13-1313.59" - wire width 16 \libresocsim_sdcore_crc16_inserter_crc1_crcreg1 - attribute \src "ls180.v:1314.13-1314.59" - wire width 16 \libresocsim_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:1318.6-1318.51" - wire \libresocsim_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:1315.12-1315.54" - wire width 2 \libresocsim_sdcore_crc16_inserter_crc1_val - attribute \src "ls180.v:1324.6-1324.48" - wire \libresocsim_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:1323.12-1323.54" - wire width 16 \libresocsim_sdcore_crc16_inserter_crc2_crc - attribute \src "ls180.v:1319.12-1319.58" - wire width 16 \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 - attribute \src "ls180.v:1320.13-1320.59" - wire width 16 \libresocsim_sdcore_crc16_inserter_crc2_crcreg1 - attribute \src "ls180.v:1321.13-1321.59" - wire width 16 \libresocsim_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:1325.6-1325.51" - wire \libresocsim_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:1322.12-1322.54" - wire width 2 \libresocsim_sdcore_crc16_inserter_crc2_val - attribute \src "ls180.v:1331.6-1331.48" - wire \libresocsim_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:1330.12-1330.54" - wire width 16 \libresocsim_sdcore_crc16_inserter_crc3_crc - attribute \src "ls180.v:1326.12-1326.58" - wire width 16 \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 - attribute \src "ls180.v:1327.13-1327.59" - wire width 16 \libresocsim_sdcore_crc16_inserter_crc3_crcreg1 - attribute \src "ls180.v:1328.13-1328.59" - wire width 16 \libresocsim_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:1332.6-1332.51" - wire \libresocsim_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:1329.12-1329.54" - wire width 2 \libresocsim_sdcore_crc16_inserter_crc3_val - attribute \src "ls180.v:1333.12-1333.53" - wire width 16 \libresocsim_sdcore_crc16_inserter_crctmp0 - attribute \src "ls180.v:1702.12-1702.92" - wire width 16 \libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 - attribute \src "ls180.v:1703.5-1703.88" - wire \libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:1334.12-1334.53" - wire width 16 \libresocsim_sdcore_crc16_inserter_crctmp1 - attribute \src "ls180.v:1704.12-1704.92" - wire width 16 \libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 - attribute \src "ls180.v:1705.5-1705.88" - wire \libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:1335.12-1335.53" - wire width 16 \libresocsim_sdcore_crc16_inserter_crctmp2 - attribute \src "ls180.v:1706.12-1706.92" - wire width 16 \libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 - attribute \src "ls180.v:1707.5-1707.88" - wire \libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:1336.12-1336.53" - wire width 16 \libresocsim_sdcore_crc16_inserter_crctmp3 - attribute \src "ls180.v:1708.12-1708.92" - wire width 16 \libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 - attribute \src "ls180.v:1709.5-1709.88" - wire \libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:1296.6-1296.50" - wire \libresocsim_sdcore_crc16_inserter_sink_first - attribute \src "ls180.v:1297.6-1297.49" - wire \libresocsim_sdcore_crc16_inserter_sink_last - attribute \src "ls180.v:1298.12-1298.63" - wire width 8 \libresocsim_sdcore_crc16_inserter_sink_payload_data - attribute \src "ls180.v:1295.5-1295.49" - wire \libresocsim_sdcore_crc16_inserter_sink_ready - attribute \src "ls180.v:1294.6-1294.50" - wire \libresocsim_sdcore_crc16_inserter_sink_valid - attribute \src "ls180.v:1301.5-1301.51" - wire \libresocsim_sdcore_crc16_inserter_source_first - attribute \src "ls180.v:1302.5-1302.50" - wire \libresocsim_sdcore_crc16_inserter_source_last - attribute \src "ls180.v:1303.11-1303.64" - wire width 8 \libresocsim_sdcore_crc16_inserter_source_payload_data - attribute \src "ls180.v:1300.5-1300.51" - wire \libresocsim_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:1299.5-1299.51" - wire \libresocsim_sdcore_crc16_inserter_source_valid - attribute \src "ls180.v:1292.6-1292.42" - wire \libresocsim_sdcore_crc7_inserter_clr - attribute \src "ls180.v:1291.11-1291.47" - wire width 7 \libresocsim_sdcore_crc7_inserter_crc - attribute \src "ls180.v:1249.11-1249.51" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg0 - attribute \src "ls180.v:1250.12-1250.52" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg1 - attribute \src "ls180.v:1259.12-1259.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg10 - attribute \src "ls180.v:1260.12-1260.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg11 - attribute \src "ls180.v:1261.12-1261.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg12 - attribute \src "ls180.v:1262.12-1262.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg13 - attribute \src "ls180.v:1263.12-1263.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg14 - attribute \src "ls180.v:1264.12-1264.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg15 - attribute \src "ls180.v:1265.12-1265.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg16 - attribute \src "ls180.v:1266.12-1266.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg17 - attribute \src "ls180.v:1267.12-1267.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg18 - attribute \src "ls180.v:1268.12-1268.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg19 - attribute \src "ls180.v:1251.12-1251.52" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg2 - attribute \src "ls180.v:1269.12-1269.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg20 - attribute \src "ls180.v:1270.12-1270.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg21 - attribute \src "ls180.v:1271.12-1271.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg22 - attribute \src "ls180.v:1272.12-1272.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg23 - attribute \src "ls180.v:1273.12-1273.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg24 - attribute \src "ls180.v:1274.12-1274.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg25 - attribute \src "ls180.v:1275.12-1275.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg26 - attribute \src "ls180.v:1276.12-1276.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg27 - attribute \src "ls180.v:1277.12-1277.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg28 - attribute \src "ls180.v:1278.12-1278.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg29 - attribute \src "ls180.v:1252.12-1252.52" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg3 - attribute \src "ls180.v:1279.12-1279.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg30 - attribute \src "ls180.v:1280.12-1280.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg31 - attribute \src "ls180.v:1281.12-1281.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg32 - attribute \src "ls180.v:1282.12-1282.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg33 - attribute \src "ls180.v:1283.12-1283.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg34 - attribute \src "ls180.v:1284.12-1284.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg35 - attribute \src "ls180.v:1285.12-1285.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg36 - attribute \src "ls180.v:1286.12-1286.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg37 - attribute \src "ls180.v:1287.12-1287.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg38 - attribute \src "ls180.v:1288.12-1288.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg39 - attribute \src "ls180.v:1253.12-1253.52" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg4 - attribute \src "ls180.v:1289.12-1289.53" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:1254.12-1254.52" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg5 - attribute \src "ls180.v:1255.12-1255.52" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg6 - attribute \src "ls180.v:1256.12-1256.52" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg7 - attribute \src "ls180.v:1257.12-1257.52" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg8 - attribute \src "ls180.v:1258.12-1258.52" - wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg9 - attribute \src "ls180.v:1293.6-1293.45" - wire \libresocsim_sdcore_crc7_inserter_enable - attribute \src "ls180.v:1290.13-1290.49" - wire width 40 \libresocsim_sdcore_crc7_inserter_val - attribute \src "ls180.v:1392.12-1392.41" - wire width 32 \libresocsim_sdcore_data_count - attribute \src "ls180.v:1720.12-1720.64" - wire width 32 \libresocsim_sdcore_data_count_sdcore_fsm_next_value3 - attribute \src "ls180.v:1721.5-1721.60" - wire \libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:1393.5-1393.33" - wire \libresocsim_sdcore_data_done - attribute \src "ls180.v:1716.5-1716.56" - wire \libresocsim_sdcore_data_done_sdcore_fsm_next_value1 - attribute \src "ls180.v:1717.5-1717.59" - wire \libresocsim_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:1394.5-1394.34" - wire \libresocsim_sdcore_data_error - attribute \src "ls180.v:1726.5-1726.57" - wire \libresocsim_sdcore_data_error_sdcore_fsm_next_value6 - attribute \src "ls180.v:1727.5-1727.60" - wire \libresocsim_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:1243.12-1243.48" - wire width 4 \libresocsim_sdcore_data_event_status - attribute \src "ls180.v:1244.6-1244.38" - wire \libresocsim_sdcore_data_event_we - attribute \src "ls180.v:1395.5-1395.36" - wire \libresocsim_sdcore_data_timeout - attribute \src "ls180.v:1728.5-1728.59" - wire \libresocsim_sdcore_data_timeout_sdcore_fsm_next_value7 - attribute \src "ls180.v:1729.5-1729.62" - wire \libresocsim_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:1391.12-1391.40" - wire width 2 \libresocsim_sdcore_data_type - attribute \src "ls180.v:1223.6-1223.40" - wire \libresocsim_sdcore_sink_sink_first - attribute \src "ls180.v:1224.6-1224.39" - wire \libresocsim_sdcore_sink_sink_last - attribute \src "ls180.v:1225.12-1225.53" - wire width 8 \libresocsim_sdcore_sink_sink_payload_data - attribute \src "ls180.v:1222.6-1222.40" - wire \libresocsim_sdcore_sink_sink_ready - attribute \src "ls180.v:1221.6-1221.40" - wire \libresocsim_sdcore_sink_sink_valid - attribute \src "ls180.v:1228.6-1228.44" - wire \libresocsim_sdcore_source_source_first - attribute \src "ls180.v:1229.6-1229.43" - wire \libresocsim_sdcore_source_source_last - attribute \src "ls180.v:1230.12-1230.57" - wire width 8 \libresocsim_sdcore_source_source_payload_data - attribute \src "ls180.v:1227.6-1227.44" - wire \libresocsim_sdcore_source_source_ready - attribute \src "ls180.v:1226.6-1226.44" - wire \libresocsim_sdcore_source_source_valid - attribute \src "ls180.v:1541.6-1541.45" - wire \libresocsim_sdmem2block_converter_first - attribute \src "ls180.v:1542.6-1542.44" - wire \libresocsim_sdmem2block_converter_last - attribute \src "ls180.v:1540.11-1540.48" - wire width 2 \libresocsim_sdmem2block_converter_mux - attribute \src "ls180.v:1531.6-1531.50" - wire \libresocsim_sdmem2block_converter_sink_first - attribute \src "ls180.v:1532.6-1532.49" - wire \libresocsim_sdmem2block_converter_sink_last - attribute \src "ls180.v:1533.13-1533.64" - wire width 32 \libresocsim_sdmem2block_converter_sink_payload_data - attribute \src "ls180.v:1530.6-1530.50" - wire \libresocsim_sdmem2block_converter_sink_ready - attribute \src "ls180.v:1529.6-1529.50" - wire \libresocsim_sdmem2block_converter_sink_valid - attribute \src "ls180.v:1536.6-1536.52" - wire \libresocsim_sdmem2block_converter_source_first - attribute \src "ls180.v:1537.6-1537.51" - wire \libresocsim_sdmem2block_converter_source_last - attribute \src "ls180.v:1538.11-1538.64" - wire width 8 \libresocsim_sdmem2block_converter_source_payload_data - attribute \src "ls180.v:1539.6-1539.72" - wire \libresocsim_sdmem2block_converter_source_payload_valid_token_count - attribute \src "ls180.v:1535.6-1535.52" - wire \libresocsim_sdmem2block_converter_source_ready - attribute \src "ls180.v:1534.6-1534.52" - wire \libresocsim_sdmem2block_converter_source_valid - attribute \src "ls180.v:1525.13-1525.45" - wire width 32 \libresocsim_sdmem2block_dma_base - attribute \src "ls180.v:1514.5-1514.40" - wire \libresocsim_sdmem2block_dma_base_re - attribute \src "ls180.v:1513.12-1513.52" - wire width 64 \libresocsim_sdmem2block_dma_base_storage - attribute \src "ls180.v:1512.12-1512.44" - wire width 32 \libresocsim_sdmem2block_dma_data - attribute \src "ls180.v:1738.12-1738.74" - wire width 32 \libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value - attribute \src "ls180.v:1739.5-1739.70" - wire \libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:1519.5-1519.44" - wire \libresocsim_sdmem2block_dma_done_status - attribute \src "ls180.v:1520.6-1520.41" - wire \libresocsim_sdmem2block_dma_done_we - attribute \src "ls180.v:1518.5-1518.42" - wire \libresocsim_sdmem2block_dma_enable_re - attribute \src "ls180.v:1517.5-1517.47" - wire \libresocsim_sdmem2block_dma_enable_storage - attribute \src "ls180.v:1527.13-1527.47" - wire width 32 \libresocsim_sdmem2block_dma_length - attribute \src "ls180.v:1516.5-1516.42" - wire \libresocsim_sdmem2block_dma_length_re - attribute \src "ls180.v:1515.12-1515.54" - wire width 32 \libresocsim_sdmem2block_dma_length_storage - attribute \src "ls180.v:1522.5-1522.40" - wire \libresocsim_sdmem2block_dma_loop_re - attribute \src "ls180.v:1521.5-1521.45" - wire \libresocsim_sdmem2block_dma_loop_storage - attribute \src "ls180.v:1526.12-1526.46" - wire width 32 \libresocsim_sdmem2block_dma_offset - attribute \src "ls180.v:1742.12-1742.86" - wire width 32 \libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value - attribute \src "ls180.v:1743.5-1743.82" - wire \libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:1523.13-1523.54" - wire width 32 \libresocsim_sdmem2block_dma_offset_status - attribute \src "ls180.v:1524.6-1524.43" - wire \libresocsim_sdmem2block_dma_offset_we - attribute \src "ls180.v:1528.6-1528.39" - wire \libresocsim_sdmem2block_dma_reset - attribute \src "ls180.v:1505.5-1505.42" - wire \libresocsim_sdmem2block_dma_sink_last - attribute \src "ls180.v:1506.12-1506.60" - wire width 32 \libresocsim_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:1504.5-1504.43" - wire \libresocsim_sdmem2block_dma_sink_ready - attribute \src "ls180.v:1503.5-1503.43" - wire \libresocsim_sdmem2block_dma_sink_valid - attribute \src "ls180.v:1509.5-1509.45" - wire \libresocsim_sdmem2block_dma_source_first - attribute \src "ls180.v:1510.5-1510.44" - wire \libresocsim_sdmem2block_dma_source_last - attribute \src "ls180.v:1511.12-1511.59" - wire width 32 \libresocsim_sdmem2block_dma_source_payload_data - attribute \src "ls180.v:1508.6-1508.46" - wire \libresocsim_sdmem2block_dma_source_ready - attribute \src "ls180.v:1507.5-1507.45" - wire \libresocsim_sdmem2block_dma_source_valid - attribute \src "ls180.v:1567.11-1567.47" - wire width 5 \libresocsim_sdmem2block_fifo_consume - attribute \src "ls180.v:1572.6-1572.42" - wire \libresocsim_sdmem2block_fifo_do_read - attribute \src "ls180.v:1576.6-1576.48" - wire \libresocsim_sdmem2block_fifo_fifo_in_first - attribute \src "ls180.v:1577.6-1577.47" - wire \libresocsim_sdmem2block_fifo_fifo_in_last - attribute \src "ls180.v:1575.12-1575.61" - wire width 8 \libresocsim_sdmem2block_fifo_fifo_in_payload_data - attribute \src "ls180.v:1579.6-1579.49" - wire \libresocsim_sdmem2block_fifo_fifo_out_first - attribute \src "ls180.v:1580.6-1580.48" - wire \libresocsim_sdmem2block_fifo_fifo_out_last - attribute \src "ls180.v:1578.12-1578.62" - wire width 8 \libresocsim_sdmem2block_fifo_fifo_out_payload_data - attribute \src "ls180.v:1564.11-1564.45" - wire width 6 \libresocsim_sdmem2block_fifo_level - attribute \src "ls180.v:1566.11-1566.47" - wire width 5 \libresocsim_sdmem2block_fifo_produce - attribute \src "ls180.v:1573.12-1573.51" - wire width 5 \libresocsim_sdmem2block_fifo_rdport_adr - attribute \src "ls180.v:1574.12-1574.53" - wire width 10 \libresocsim_sdmem2block_fifo_rdport_dat_r - attribute \src "ls180.v:1565.5-1565.41" - wire \libresocsim_sdmem2block_fifo_replace - attribute \src "ls180.v:1550.6-1550.45" - wire \libresocsim_sdmem2block_fifo_sink_first - attribute \src "ls180.v:1551.6-1551.44" - wire \libresocsim_sdmem2block_fifo_sink_last - attribute \src "ls180.v:1552.12-1552.58" - wire width 8 \libresocsim_sdmem2block_fifo_sink_payload_data - attribute \src "ls180.v:1549.6-1549.45" - wire \libresocsim_sdmem2block_fifo_sink_ready - attribute \src "ls180.v:1548.6-1548.45" - wire \libresocsim_sdmem2block_fifo_sink_valid - attribute \src "ls180.v:1555.6-1555.47" - wire \libresocsim_sdmem2block_fifo_source_first - attribute \src "ls180.v:1556.6-1556.46" - wire \libresocsim_sdmem2block_fifo_source_last - attribute \src "ls180.v:1557.12-1557.60" - wire width 8 \libresocsim_sdmem2block_fifo_source_payload_data - attribute \src "ls180.v:1554.6-1554.47" - wire \libresocsim_sdmem2block_fifo_source_ready - attribute \src "ls180.v:1553.6-1553.47" - wire \libresocsim_sdmem2block_fifo_source_valid - attribute \src "ls180.v:1562.12-1562.53" - wire width 10 \libresocsim_sdmem2block_fifo_syncfifo_din - attribute \src "ls180.v:1563.12-1563.54" - wire width 10 \libresocsim_sdmem2block_fifo_syncfifo_dout - attribute \src "ls180.v:1560.6-1560.46" - wire \libresocsim_sdmem2block_fifo_syncfifo_re - attribute \src "ls180.v:1561.6-1561.52" - wire \libresocsim_sdmem2block_fifo_syncfifo_readable - attribute \src "ls180.v:1558.6-1558.46" - wire \libresocsim_sdmem2block_fifo_syncfifo_we - attribute \src "ls180.v:1559.6-1559.52" - wire \libresocsim_sdmem2block_fifo_syncfifo_writable - attribute \src "ls180.v:1568.11-1568.50" - wire width 5 \libresocsim_sdmem2block_fifo_wrport_adr - attribute \src "ls180.v:1569.12-1569.53" - wire width 10 \libresocsim_sdmem2block_fifo_wrport_dat_r - attribute \src "ls180.v:1571.12-1571.53" - wire width 10 \libresocsim_sdmem2block_fifo_wrport_dat_w - attribute \src "ls180.v:1570.6-1570.44" - wire \libresocsim_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:1500.6-1500.50" - wire \libresocsim_sdmem2block_source_source_first0 - attribute \src "ls180.v:1545.6-1545.50" - wire \libresocsim_sdmem2block_source_source_first1 - attribute \src "ls180.v:1501.6-1501.49" - wire \libresocsim_sdmem2block_source_source_last0 - attribute \src "ls180.v:1546.6-1546.49" - wire \libresocsim_sdmem2block_source_source_last1 - attribute \src "ls180.v:1502.12-1502.63" - wire width 8 \libresocsim_sdmem2block_source_source_payload_data0 - attribute \src "ls180.v:1547.12-1547.63" - wire width 8 \libresocsim_sdmem2block_source_source_payload_data1 - attribute \src "ls180.v:1499.6-1499.50" - wire \libresocsim_sdmem2block_source_source_ready0 - attribute \src "ls180.v:1544.6-1544.50" - wire \libresocsim_sdmem2block_source_source_ready1 - attribute \src "ls180.v:1498.6-1498.50" - wire \libresocsim_sdmem2block_source_source_valid0 - attribute \src "ls180.v:1543.6-1543.50" - wire \libresocsim_sdmem2block_source_source_valid1 - attribute \src "ls180.v:1214.6-1214.28" - wire \libresocsim_sdpads_clk - attribute \src "ls180.v:1215.5-1215.29" - wire \libresocsim_sdpads_cmd_i - attribute \src "ls180.v:1216.6-1216.30" - wire \libresocsim_sdpads_cmd_o - attribute \src "ls180.v:1217.6-1217.31" - wire \libresocsim_sdpads_cmd_oe - attribute \src "ls180.v:1218.11-1218.36" - wire width 4 \libresocsim_sdpads_data_i - attribute \src "ls180.v:1219.12-1219.37" - wire width 4 \libresocsim_sdpads_data_o - attribute \src "ls180.v:1220.6-1220.32" - wire \libresocsim_sdpads_data_oe - attribute \src "ls180.v:1601.6-1601.21" - wire \libresocsim_sel - attribute \src "ls180.v:1581.6-1581.24" - wire \libresocsim_start0 - attribute \src "ls180.v:1590.5-1590.23" - wire \libresocsim_start1 - attribute \src "ls180.v:943.6-943.24" - wire \libresocsim_status - attribute \src "ls180.v:1595.6-1595.31" - wire \libresocsim_status_status - attribute \src "ls180.v:1596.6-1596.27" - wire \libresocsim_status_we - attribute \src "ls180.v:1617.12-1617.31" - wire width 16 \libresocsim_storage - attribute \src "ls180.v:944.6-944.20" - wire \libresocsim_we - attribute \src "ls180.v:900.6-900.18" - wire \main_ack_cmd - attribute \src "ls180.v:902.6-902.20" - wire \main_ack_rdata - attribute \src "ls180.v:901.6-901.20" - wire \main_ack_wdata - attribute \src "ls180.v:915.12-915.29" - wire width 16 \main_clk_divider0 - attribute \src "ls180.v:937.12-937.29" - wire width 16 \main_clk_divider1 - attribute \src "ls180.v:932.5-932.20" - wire \main_clk_enable - attribute \src "ls180.v:939.6-939.19" - wire \main_clk_fall - attribute \src "ls180.v:938.6-938.19" - wire \main_clk_rise - attribute \src "ls180.v:898.5-898.22" - wire \main_cmd_consumed - attribute \src "ls180.v:919.5-919.20" - wire \main_control_re - attribute \src "ls180.v:918.12-918.32" - wire width 16 \main_control_storage - attribute \src "ls180.v:895.5-895.27" - wire \main_converter_counter - attribute \src "ls180.v:1662.5-1662.48" - wire \main_converter_counter_converter_next_value - attribute \src "ls180.v:1663.5-1663.51" - wire \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:897.12-897.32" - wire width 32 \main_converter_dat_r - attribute \src "ls180.v:896.6-896.26" - wire \main_converter_reset - attribute \src "ls180.v:894.5-894.24" - wire \main_converter_skip - attribute \src "ls180.v:934.11-934.21" - wire width 3 \main_count - attribute \src "ls180.v:1666.11-1666.43" - wire width 3 \main_count_spimaster0_next_value - attribute \src "ls180.v:1667.5-1667.40" - wire \main_count_spimaster0_next_value_ce - attribute \src "ls180.v:913.6-913.13" - wire \main_cs - attribute \src "ls180.v:933.5-933.19" - wire \main_cs_enable - attribute \src "ls180.v:929.5-929.15" - wire \main_cs_re - attribute \src "ls180.v:928.5-928.20" - wire \main_cs_storage - attribute \src "ls180.v:324.6-324.23" - wire \main_dfi_p0_act_n - attribute \src "ls180.v:315.13-315.32" - wire width 13 \main_dfi_p0_address - attribute \src "ls180.v:316.12-316.28" - wire width 2 \main_dfi_p0_bank - attribute \src "ls180.v:317.6-317.23" - wire \main_dfi_p0_cas_n - attribute \src "ls180.v:321.6-321.21" - wire \main_dfi_p0_cke - attribute \src "ls180.v:318.6-318.22" - wire \main_dfi_p0_cs_n - attribute \src "ls180.v:322.6-322.21" - wire \main_dfi_p0_odt - attribute \src "ls180.v:319.6-319.23" - wire \main_dfi_p0_ras_n - attribute \src "ls180.v:329.12-329.30" - wire width 16 \main_dfi_p0_rddata - attribute \src "ls180.v:328.6-328.27" - wire \main_dfi_p0_rddata_en - attribute \src "ls180.v:330.5-330.29" - wire \main_dfi_p0_rddata_valid - attribute \src "ls180.v:323.6-323.25" - wire \main_dfi_p0_reset_n - attribute \src "ls180.v:320.6-320.22" - wire \main_dfi_p0_we_n - attribute \src "ls180.v:325.13-325.31" - wire width 16 \main_dfi_p0_wrdata - attribute \src "ls180.v:326.6-326.27" - wire \main_dfi_p0_wrdata_en - attribute \src "ls180.v:327.12-327.35" - wire width 2 \main_dfi_p0_wrdata_mask - attribute \src "ls180.v:909.5-909.15" - wire \main_done0 - attribute \src "ls180.v:920.6-920.16" - wire \main_done1 - attribute \src "ls180.v:903.12-903.31" - wire width 8 \main_gpio_in_status - attribute \src "ls180.v:904.6-904.21" - wire \main_gpio_in_we - attribute \src "ls180.v:905.12-905.32" - wire width 8 \main_gpio_out_status - attribute \src "ls180.v:906.6-906.22" - wire \main_gpio_out_we - attribute \src "ls180.v:314.5-314.17" - wire \main_int_rst - attribute \src "ls180.v:910.5-910.13" - wire \main_irq - attribute \src "ls180.v:908.12-908.24" - wire width 8 \main_length0 - attribute \src "ls180.v:917.12-917.24" - wire width 8 \main_length1 - attribute \src "ls180.v:138.12-138.32" - wire width 7 \main_libresocsim_adr - attribute \src "ls180.v:109.5-109.40" - wire \main_libresocsim_converter0_counter - attribute \src "ls180.v:1621.5-1621.62" - wire \main_libresocsim_converter0_counter_converter0_next_value - attribute \src "ls180.v:1622.5-1622.65" - wire \main_libresocsim_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:111.12-111.45" - wire width 64 \main_libresocsim_converter0_dat_r - attribute \src "ls180.v:110.6-110.39" - wire \main_libresocsim_converter0_reset - attribute \src "ls180.v:108.5-108.37" - wire \main_libresocsim_converter0_skip - attribute \src "ls180.v:124.5-124.40" - wire \main_libresocsim_converter1_counter - attribute \src "ls180.v:1625.5-1625.62" - wire \main_libresocsim_converter1_counter_converter1_next_value - attribute \src "ls180.v:1626.5-1626.65" - wire \main_libresocsim_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:126.12-126.45" - wire width 64 \main_libresocsim_converter1_dat_r - attribute \src "ls180.v:125.6-125.39" - wire \main_libresocsim_converter1_reset - attribute \src "ls180.v:123.5-123.37" - wire \main_libresocsim_converter1_skip - attribute \src "ls180.v:139.13-139.35" - wire width 32 \main_libresocsim_dat_r - attribute \src "ls180.v:141.13-141.35" - wire width 32 \main_libresocsim_dat_w - attribute \src "ls180.v:103.6-103.57" - wire \main_libresocsim_interface0_converted_interface_ack - attribute \src "ls180.v:97.12-97.63" - wire width 30 \main_libresocsim_interface0_converted_interface_adr - attribute \src "ls180.v:106.11-106.62" - wire width 2 \main_libresocsim_interface0_converted_interface_bte - attribute \src "ls180.v:105.11-105.62" - wire width 3 \main_libresocsim_interface0_converted_interface_cti - attribute \src "ls180.v:101.5-101.56" - wire \main_libresocsim_interface0_converted_interface_cyc - attribute \src "ls180.v:99.13-99.66" - wire width 32 \main_libresocsim_interface0_converted_interface_dat_r - attribute \src "ls180.v:98.12-98.65" - wire width 32 \main_libresocsim_interface0_converted_interface_dat_w - attribute \src "ls180.v:107.6-107.57" - wire \main_libresocsim_interface0_converted_interface_err - attribute \src "ls180.v:100.11-100.62" - wire width 4 \main_libresocsim_interface0_converted_interface_sel - attribute \src "ls180.v:102.5-102.56" - wire \main_libresocsim_interface0_converted_interface_stb - attribute \src "ls180.v:104.5-104.55" - wire \main_libresocsim_interface0_converted_interface_we - attribute \src "ls180.v:118.6-118.57" - wire \main_libresocsim_interface1_converted_interface_ack - attribute \src "ls180.v:112.12-112.63" - wire width 30 \main_libresocsim_interface1_converted_interface_adr - attribute \src "ls180.v:121.11-121.62" - wire width 2 \main_libresocsim_interface1_converted_interface_bte - attribute \src "ls180.v:120.11-120.62" - wire width 3 \main_libresocsim_interface1_converted_interface_cti - attribute \src "ls180.v:116.5-116.56" - wire \main_libresocsim_interface1_converted_interface_cyc - attribute \src "ls180.v:114.13-114.66" - wire width 32 \main_libresocsim_interface1_converted_interface_dat_r - attribute \src "ls180.v:113.12-113.65" - wire width 32 \main_libresocsim_interface1_converted_interface_dat_w - attribute \src "ls180.v:122.6-122.57" - wire \main_libresocsim_interface1_converted_interface_err - attribute \src "ls180.v:115.11-115.62" - wire width 4 \main_libresocsim_interface1_converted_interface_sel - attribute \src "ls180.v:117.5-117.56" - wire \main_libresocsim_interface1_converted_interface_stb - attribute \src "ls180.v:119.5-119.55" - wire \main_libresocsim_interface1_converted_interface_we - attribute \src "ls180.v:94.6-94.32" - wire \main_libresocsim_libresoc0 - attribute \src "ls180.v:95.6-95.32" - wire \main_libresocsim_libresoc1 - attribute \src "ls180.v:96.13-96.39" - wire width 64 \main_libresocsim_libresoc2 - attribute \src "ls180.v:50.5-50.39" - wire \main_libresocsim_libresoc_dbus_ack - attribute \src "ls180.v:44.13-44.47" - wire width 29 \main_libresocsim_libresoc_dbus_adr - attribute \src "ls180.v:53.12-53.46" - wire width 2 \main_libresocsim_libresoc_dbus_bte - attribute \src "ls180.v:52.12-52.46" - wire width 3 \main_libresocsim_libresoc_dbus_cti - attribute \src "ls180.v:48.6-48.40" - wire \main_libresocsim_libresoc_dbus_cyc - attribute \src "ls180.v:46.13-46.49" - wire width 64 \main_libresocsim_libresoc_dbus_dat_r - attribute \src "ls180.v:45.13-45.49" - wire width 64 \main_libresocsim_libresoc_dbus_dat_w - attribute \src "ls180.v:54.5-54.39" - wire \main_libresocsim_libresoc_dbus_err - attribute \src "ls180.v:47.12-47.46" - wire width 8 \main_libresocsim_libresoc_dbus_sel - attribute \src "ls180.v:49.6-49.40" - wire \main_libresocsim_libresoc_dbus_stb - attribute \src "ls180.v:51.6-51.39" - wire \main_libresocsim_libresoc_dbus_we - attribute \src "ls180.v:92.6-92.39" - wire \main_libresocsim_libresoc_dmi_ack - attribute \src "ls180.v:88.11-88.45" - wire width 4 \main_libresocsim_libresoc_dmi_addr - attribute \src "ls180.v:89.12-89.45" - wire width 64 \main_libresocsim_libresoc_dmi_din - attribute \src "ls180.v:90.13-90.47" - wire width 64 \main_libresocsim_libresoc_dmi_dout - attribute \src "ls180.v:93.5-93.38" - wire \main_libresocsim_libresoc_dmi_req - attribute \src "ls180.v:91.5-91.37" - wire \main_libresocsim_libresoc_dmi_wr - attribute \src "ls180.v:61.5-61.39" - wire \main_libresocsim_libresoc_ibus_ack - attribute \src "ls180.v:55.13-55.47" - wire width 29 \main_libresocsim_libresoc_ibus_adr - attribute \src "ls180.v:64.12-64.46" - wire width 2 \main_libresocsim_libresoc_ibus_bte - attribute \src "ls180.v:63.12-63.46" - wire width 3 \main_libresocsim_libresoc_ibus_cti - attribute \src "ls180.v:59.6-59.40" - wire \main_libresocsim_libresoc_ibus_cyc - attribute \src "ls180.v:57.13-57.49" - wire width 64 \main_libresocsim_libresoc_ibus_dat_r - attribute \src "ls180.v:56.13-56.49" - wire width 64 \main_libresocsim_libresoc_ibus_dat_w - attribute \src "ls180.v:65.5-65.39" - wire \main_libresocsim_libresoc_ibus_err - attribute \src "ls180.v:58.12-58.46" - wire width 8 \main_libresocsim_libresoc_ibus_sel - attribute \src "ls180.v:60.6-60.40" - wire \main_libresocsim_libresoc_ibus_stb - attribute \src "ls180.v:62.6-62.39" - wire \main_libresocsim_libresoc_ibus_we - attribute \src "ls180.v:43.12-43.47" - wire width 16 \main_libresocsim_libresoc_interrupt - attribute \src "ls180.v:42.6-42.37" - wire \main_libresocsim_libresoc_reset - attribute \src "ls180.v:72.6-72.44" - wire \main_libresocsim_libresoc_xics_icp_ack - attribute \src "ls180.v:66.13-66.51" - wire width 30 \main_libresocsim_libresoc_xics_icp_adr - attribute \src "ls180.v:75.12-75.50" - wire width 2 \main_libresocsim_libresoc_xics_icp_bte - attribute \src "ls180.v:74.12-74.50" - wire width 3 \main_libresocsim_libresoc_xics_icp_cti - attribute \src "ls180.v:70.6-70.44" - wire \main_libresocsim_libresoc_xics_icp_cyc - attribute \src "ls180.v:68.13-68.53" - wire width 32 \main_libresocsim_libresoc_xics_icp_dat_r - attribute \src "ls180.v:67.13-67.53" - wire width 32 \main_libresocsim_libresoc_xics_icp_dat_w - attribute \src "ls180.v:76.6-76.44" - wire \main_libresocsim_libresoc_xics_icp_err - attribute \src "ls180.v:69.12-69.50" - wire width 4 \main_libresocsim_libresoc_xics_icp_sel - attribute \src "ls180.v:71.6-71.44" - wire \main_libresocsim_libresoc_xics_icp_stb - attribute \src "ls180.v:73.6-73.43" - wire \main_libresocsim_libresoc_xics_icp_we - attribute \src "ls180.v:83.6-83.44" - wire \main_libresocsim_libresoc_xics_ics_ack - attribute \src "ls180.v:77.13-77.51" - wire width 30 \main_libresocsim_libresoc_xics_ics_adr - attribute \src "ls180.v:86.12-86.50" - wire width 2 \main_libresocsim_libresoc_xics_ics_bte - attribute \src "ls180.v:85.12-85.50" - wire width 3 \main_libresocsim_libresoc_xics_ics_cti - attribute \src "ls180.v:81.6-81.44" - wire \main_libresocsim_libresoc_xics_ics_cyc - attribute \src "ls180.v:79.13-79.53" - wire width 32 \main_libresocsim_libresoc_xics_ics_dat_r - attribute \src "ls180.v:78.13-78.53" - wire width 32 \main_libresocsim_libresoc_xics_ics_dat_w - attribute \src "ls180.v:87.6-87.44" - wire \main_libresocsim_libresoc_xics_ics_err - attribute \src "ls180.v:80.12-80.50" - wire width 4 \main_libresocsim_libresoc_xics_ics_sel - attribute \src "ls180.v:82.6-82.44" - wire \main_libresocsim_libresoc_xics_ics_stb - attribute \src "ls180.v:84.6-84.43" - wire \main_libresocsim_libresoc_xics_ics_we - attribute \src "ls180.v:160.12-160.49" - wire width 32 \main_libresocsim_phase_accumulator_rx - attribute \src "ls180.v:150.12-150.49" - wire width 32 \main_libresocsim_phase_accumulator_tx - attribute \src "ls180.v:133.5-133.33" - wire \main_libresocsim_ram_bus_ack - attribute \src "ls180.v:127.13-127.41" - wire width 30 \main_libresocsim_ram_bus_adr - attribute \src "ls180.v:136.12-136.40" - wire width 2 \main_libresocsim_ram_bus_bte - attribute \src "ls180.v:135.12-135.40" - wire width 3 \main_libresocsim_ram_bus_cti - attribute \src "ls180.v:131.6-131.34" - wire \main_libresocsim_ram_bus_cyc - attribute \src "ls180.v:129.13-129.43" - wire width 32 \main_libresocsim_ram_bus_dat_r - attribute \src "ls180.v:128.13-128.43" - wire width 32 \main_libresocsim_ram_bus_dat_w - attribute \src "ls180.v:137.5-137.33" - wire \main_libresocsim_ram_bus_err - attribute \src "ls180.v:130.12-130.40" - wire width 4 \main_libresocsim_ram_bus_sel - attribute \src "ls180.v:132.6-132.34" - wire \main_libresocsim_ram_bus_stb - attribute \src "ls180.v:134.6-134.33" - wire \main_libresocsim_ram_bus_we - attribute \src "ls180.v:143.5-143.24" - wire \main_libresocsim_re - attribute \src "ls180.v:161.6-161.25" - wire \main_libresocsim_rx - attribute \src "ls180.v:164.11-164.39" - wire width 4 \main_libresocsim_rx_bitcount - attribute \src "ls180.v:165.5-165.29" - wire \main_libresocsim_rx_busy - attribute \src "ls180.v:162.5-162.26" - wire \main_libresocsim_rx_r - attribute \src "ls180.v:163.11-163.34" - wire width 8 \main_libresocsim_rx_reg - attribute \src "ls180.v:146.6-146.33" - wire \main_libresocsim_sink_first - attribute \src "ls180.v:147.6-147.32" - wire \main_libresocsim_sink_last - attribute \src "ls180.v:148.12-148.46" - wire width 8 \main_libresocsim_sink_payload_data - attribute \src "ls180.v:145.5-145.32" - wire \main_libresocsim_sink_ready - attribute \src "ls180.v:144.6-144.33" - wire \main_libresocsim_sink_valid - attribute \src "ls180.v:40.6-40.46" - wire \main_libresocsim_soccontroller_bus_error - attribute \src "ls180.v:41.12-41.53" - wire width 32 \main_libresocsim_soccontroller_bus_errors - attribute \src "ls180.v:37.13-37.61" - wire width 32 \main_libresocsim_soccontroller_bus_errors_status - attribute \src "ls180.v:38.6-38.50" - wire \main_libresocsim_soccontroller_bus_errors_we - attribute \src "ls180.v:39.6-39.42" - wire \main_libresocsim_soccontroller_reset - attribute \src "ls180.v:34.5-34.44" - wire \main_libresocsim_soccontroller_reset_re - attribute \src "ls180.v:33.5-33.49" - wire \main_libresocsim_soccontroller_reset_storage - attribute \src "ls180.v:36.5-36.46" - wire \main_libresocsim_soccontroller_scratch_re - attribute \src "ls180.v:35.12-35.58" - wire width 32 \main_libresocsim_soccontroller_scratch_storage - attribute \src "ls180.v:156.5-156.34" - wire \main_libresocsim_source_first - attribute \src "ls180.v:157.5-157.33" - wire \main_libresocsim_source_last - attribute \src "ls180.v:158.11-158.47" - wire width 8 \main_libresocsim_source_payload_data - attribute \src "ls180.v:155.6-155.35" - wire \main_libresocsim_source_ready - attribute \src "ls180.v:154.5-154.34" - wire \main_libresocsim_source_valid - attribute \src "ls180.v:142.12-142.36" - wire width 32 \main_libresocsim_storage - attribute \src "ls180.v:289.5-289.33" - wire \main_libresocsim_timer_en_re - attribute \src "ls180.v:288.5-288.38" - wire \main_libresocsim_timer_en_storage - attribute \src "ls180.v:305.6-305.51" - wire \main_libresocsim_timer_eventmanager_pending_r - attribute \src "ls180.v:304.6-304.52" - wire \main_libresocsim_timer_eventmanager_pending_re - attribute \src "ls180.v:307.6-307.51" - wire \main_libresocsim_timer_eventmanager_pending_w - attribute \src "ls180.v:306.6-306.52" - wire \main_libresocsim_timer_eventmanager_pending_we - attribute \src "ls180.v:309.5-309.43" - wire \main_libresocsim_timer_eventmanager_re - attribute \src "ls180.v:301.6-301.50" - wire \main_libresocsim_timer_eventmanager_status_r - attribute \src "ls180.v:300.6-300.51" - wire \main_libresocsim_timer_eventmanager_status_re - attribute \src "ls180.v:303.6-303.50" - wire \main_libresocsim_timer_eventmanager_status_w - attribute \src "ls180.v:302.6-302.51" - wire \main_libresocsim_timer_eventmanager_status_we - attribute \src "ls180.v:308.5-308.48" - wire \main_libresocsim_timer_eventmanager_storage - attribute \src "ls180.v:294.6-294.32" - wire \main_libresocsim_timer_irq - attribute \src "ls180.v:285.5-285.35" - wire \main_libresocsim_timer_load_re - attribute \src "ls180.v:284.12-284.47" - wire width 32 \main_libresocsim_timer_load_storage - attribute \src "ls180.v:287.5-287.37" - wire \main_libresocsim_timer_reload_re - attribute \src "ls180.v:286.12-286.49" - wire width 32 \main_libresocsim_timer_reload_storage - attribute \src "ls180.v:291.5-291.43" - wire \main_libresocsim_timer_update_value_re - attribute \src "ls180.v:290.5-290.48" - wire \main_libresocsim_timer_update_value_storage - attribute \src "ls180.v:310.12-310.40" - wire width 32 \main_libresocsim_timer_value - attribute \src "ls180.v:292.12-292.47" - wire width 32 \main_libresocsim_timer_value_status - attribute \src "ls180.v:293.6-293.37" - wire \main_libresocsim_timer_value_we - attribute \src "ls180.v:298.5-298.38" - wire \main_libresocsim_timer_zero_clear - attribute \src "ls180.v:299.5-299.44" - wire \main_libresocsim_timer_zero_old_trigger - attribute \src "ls180.v:296.5-296.40" - wire \main_libresocsim_timer_zero_pending - attribute \src "ls180.v:295.6-295.40" - wire \main_libresocsim_timer_zero_status - attribute \src "ls180.v:297.6-297.41" - wire \main_libresocsim_timer_zero_trigger - attribute \src "ls180.v:152.11-152.39" - wire width 4 \main_libresocsim_tx_bitcount - attribute \src "ls180.v:153.5-153.29" - wire \main_libresocsim_tx_busy - attribute \src "ls180.v:151.11-151.34" - wire width 8 \main_libresocsim_tx_reg - attribute \src "ls180.v:159.5-159.35" - wire \main_libresocsim_uart_clk_rxen - attribute \src "ls180.v:149.5-149.35" - wire \main_libresocsim_uart_clk_txen - attribute \src "ls180.v:190.12-190.56" - wire width 2 \main_libresocsim_uart_eventmanager_pending_r - attribute \src "ls180.v:189.6-189.51" - wire \main_libresocsim_uart_eventmanager_pending_re - attribute \src "ls180.v:192.11-192.55" - wire width 2 \main_libresocsim_uart_eventmanager_pending_w - attribute \src "ls180.v:191.6-191.51" - wire \main_libresocsim_uart_eventmanager_pending_we - attribute \src "ls180.v:194.5-194.42" - wire \main_libresocsim_uart_eventmanager_re - attribute \src "ls180.v:186.12-186.55" - wire width 2 \main_libresocsim_uart_eventmanager_status_r - attribute \src "ls180.v:185.6-185.50" - wire \main_libresocsim_uart_eventmanager_status_re - attribute \src "ls180.v:188.11-188.54" - wire width 2 \main_libresocsim_uart_eventmanager_status_w - attribute \src "ls180.v:187.6-187.50" - wire \main_libresocsim_uart_eventmanager_status_we - attribute \src "ls180.v:193.11-193.53" - wire width 2 \main_libresocsim_uart_eventmanager_storage - attribute \src "ls180.v:174.6-174.31" - wire \main_libresocsim_uart_irq - attribute \src "ls180.v:283.5-283.32" - wire \main_libresocsim_uart_reset - attribute \src "ls180.v:183.5-183.35" - wire \main_libresocsim_uart_rx_clear - attribute \src "ls180.v:267.11-267.48" - wire width 4 \main_libresocsim_uart_rx_fifo_consume - attribute \src "ls180.v:272.6-272.43" - wire \main_libresocsim_uart_rx_fifo_do_read - attribute \src "ls180.v:278.6-278.49" - wire \main_libresocsim_uart_rx_fifo_fifo_in_first - attribute \src "ls180.v:279.6-279.48" - wire \main_libresocsim_uart_rx_fifo_fifo_in_last - attribute \src "ls180.v:277.12-277.62" - wire width 8 \main_libresocsim_uart_rx_fifo_fifo_in_payload_data - attribute \src "ls180.v:281.6-281.50" - wire \main_libresocsim_uart_rx_fifo_fifo_out_first - attribute \src "ls180.v:282.6-282.49" - wire \main_libresocsim_uart_rx_fifo_fifo_out_last - attribute \src "ls180.v:280.12-280.63" - wire width 8 \main_libresocsim_uart_rx_fifo_fifo_out_payload_data - attribute \src "ls180.v:264.11-264.47" - wire width 5 \main_libresocsim_uart_rx_fifo_level0 - attribute \src "ls180.v:276.12-276.48" - wire width 5 \main_libresocsim_uart_rx_fifo_level1 - attribute \src "ls180.v:266.11-266.48" - wire width 4 \main_libresocsim_uart_rx_fifo_produce - attribute \src "ls180.v:273.12-273.52" - wire width 4 \main_libresocsim_uart_rx_fifo_rdport_adr - attribute \src "ls180.v:274.12-274.54" - wire width 10 \main_libresocsim_uart_rx_fifo_rdport_dat_r - attribute \src "ls180.v:275.6-275.45" - wire \main_libresocsim_uart_rx_fifo_rdport_re - attribute \src "ls180.v:256.6-256.38" - wire \main_libresocsim_uart_rx_fifo_re - attribute \src "ls180.v:257.5-257.43" - wire \main_libresocsim_uart_rx_fifo_readable - attribute \src "ls180.v:265.5-265.42" - wire \main_libresocsim_uart_rx_fifo_replace - attribute \src "ls180.v:248.6-248.46" - wire \main_libresocsim_uart_rx_fifo_sink_first - attribute \src "ls180.v:249.6-249.45" - wire \main_libresocsim_uart_rx_fifo_sink_last - attribute \src "ls180.v:250.12-250.59" - wire width 8 \main_libresocsim_uart_rx_fifo_sink_payload_data - attribute \src "ls180.v:247.6-247.46" - wire \main_libresocsim_uart_rx_fifo_sink_ready - attribute \src "ls180.v:246.6-246.46" - wire \main_libresocsim_uart_rx_fifo_sink_valid - attribute \src "ls180.v:253.6-253.48" - wire \main_libresocsim_uart_rx_fifo_source_first - attribute \src "ls180.v:254.6-254.47" - wire \main_libresocsim_uart_rx_fifo_source_last - attribute \src "ls180.v:255.12-255.61" - wire width 8 \main_libresocsim_uart_rx_fifo_source_payload_data - attribute \src "ls180.v:252.6-252.48" - wire \main_libresocsim_uart_rx_fifo_source_ready - attribute \src "ls180.v:251.6-251.48" - wire \main_libresocsim_uart_rx_fifo_source_valid - attribute \src "ls180.v:262.12-262.54" - wire width 10 \main_libresocsim_uart_rx_fifo_syncfifo_din - attribute \src "ls180.v:263.12-263.55" - wire width 10 \main_libresocsim_uart_rx_fifo_syncfifo_dout - attribute \src "ls180.v:260.6-260.47" - wire \main_libresocsim_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:261.6-261.53" - wire \main_libresocsim_uart_rx_fifo_syncfifo_readable - attribute \src "ls180.v:258.6-258.47" - wire \main_libresocsim_uart_rx_fifo_syncfifo_we - attribute \src "ls180.v:259.6-259.53" - wire \main_libresocsim_uart_rx_fifo_syncfifo_writable - attribute \src "ls180.v:268.11-268.51" - wire width 4 \main_libresocsim_uart_rx_fifo_wrport_adr - attribute \src "ls180.v:269.12-269.54" - wire width 10 \main_libresocsim_uart_rx_fifo_wrport_dat_r - attribute \src "ls180.v:271.12-271.54" - wire width 10 \main_libresocsim_uart_rx_fifo_wrport_dat_w - attribute \src "ls180.v:270.6-270.45" - wire \main_libresocsim_uart_rx_fifo_wrport_we - attribute \src "ls180.v:184.5-184.41" - wire \main_libresocsim_uart_rx_old_trigger - attribute \src "ls180.v:181.5-181.37" - wire \main_libresocsim_uart_rx_pending - attribute \src "ls180.v:180.6-180.37" - wire \main_libresocsim_uart_rx_status - attribute \src "ls180.v:182.6-182.38" - wire \main_libresocsim_uart_rx_trigger - attribute \src "ls180.v:172.6-172.42" - wire \main_libresocsim_uart_rxempty_status - attribute \src "ls180.v:173.6-173.38" - wire \main_libresocsim_uart_rxempty_we - attribute \src "ls180.v:197.6-197.41" - wire \main_libresocsim_uart_rxfull_status - attribute \src "ls180.v:198.6-198.37" - wire \main_libresocsim_uart_rxfull_we - attribute \src "ls180.v:167.12-167.40" - wire width 8 \main_libresocsim_uart_rxtx_r - attribute \src "ls180.v:166.6-166.35" - wire \main_libresocsim_uart_rxtx_re - attribute \src "ls180.v:169.12-169.40" - wire width 8 \main_libresocsim_uart_rxtx_w - attribute \src "ls180.v:168.6-168.35" - wire \main_libresocsim_uart_rxtx_we - attribute \src "ls180.v:178.5-178.35" - wire \main_libresocsim_uart_tx_clear - attribute \src "ls180.v:230.11-230.48" - wire width 4 \main_libresocsim_uart_tx_fifo_consume - attribute \src "ls180.v:235.6-235.43" - wire \main_libresocsim_uart_tx_fifo_do_read - attribute \src "ls180.v:241.6-241.49" - wire \main_libresocsim_uart_tx_fifo_fifo_in_first - attribute \src "ls180.v:242.6-242.48" - wire \main_libresocsim_uart_tx_fifo_fifo_in_last - attribute \src "ls180.v:240.12-240.62" - wire width 8 \main_libresocsim_uart_tx_fifo_fifo_in_payload_data - attribute \src "ls180.v:244.6-244.50" - wire \main_libresocsim_uart_tx_fifo_fifo_out_first - attribute \src "ls180.v:245.6-245.49" - wire \main_libresocsim_uart_tx_fifo_fifo_out_last - attribute \src "ls180.v:243.12-243.63" - wire width 8 \main_libresocsim_uart_tx_fifo_fifo_out_payload_data - attribute \src "ls180.v:227.11-227.47" - wire width 5 \main_libresocsim_uart_tx_fifo_level0 - attribute \src "ls180.v:239.12-239.48" - wire width 5 \main_libresocsim_uart_tx_fifo_level1 - attribute \src "ls180.v:229.11-229.48" - wire width 4 \main_libresocsim_uart_tx_fifo_produce - attribute \src "ls180.v:236.12-236.52" - wire width 4 \main_libresocsim_uart_tx_fifo_rdport_adr - attribute \src "ls180.v:237.12-237.54" - wire width 10 \main_libresocsim_uart_tx_fifo_rdport_dat_r - attribute \src "ls180.v:238.6-238.45" - wire \main_libresocsim_uart_tx_fifo_rdport_re - attribute \src "ls180.v:219.6-219.38" - wire \main_libresocsim_uart_tx_fifo_re - attribute \src "ls180.v:220.5-220.43" - wire \main_libresocsim_uart_tx_fifo_readable - attribute \src "ls180.v:228.5-228.42" - wire \main_libresocsim_uart_tx_fifo_replace - attribute \src "ls180.v:211.5-211.45" - wire \main_libresocsim_uart_tx_fifo_sink_first - attribute \src "ls180.v:212.5-212.44" - wire \main_libresocsim_uart_tx_fifo_sink_last - attribute \src "ls180.v:213.12-213.59" - wire width 8 \main_libresocsim_uart_tx_fifo_sink_payload_data - attribute \src "ls180.v:210.6-210.46" - wire \main_libresocsim_uart_tx_fifo_sink_ready - attribute \src "ls180.v:209.6-209.46" - wire \main_libresocsim_uart_tx_fifo_sink_valid - attribute \src "ls180.v:216.6-216.48" - wire \main_libresocsim_uart_tx_fifo_source_first - attribute \src "ls180.v:217.6-217.47" - wire \main_libresocsim_uart_tx_fifo_source_last - attribute \src "ls180.v:218.12-218.61" - wire width 8 \main_libresocsim_uart_tx_fifo_source_payload_data - attribute \src "ls180.v:215.6-215.48" - wire \main_libresocsim_uart_tx_fifo_source_ready - attribute \src "ls180.v:214.6-214.48" - wire \main_libresocsim_uart_tx_fifo_source_valid - attribute \src "ls180.v:225.12-225.54" - wire width 10 \main_libresocsim_uart_tx_fifo_syncfifo_din - attribute \src "ls180.v:226.12-226.55" - wire width 10 \main_libresocsim_uart_tx_fifo_syncfifo_dout - attribute \src "ls180.v:223.6-223.47" - wire \main_libresocsim_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:224.6-224.53" - wire \main_libresocsim_uart_tx_fifo_syncfifo_readable - attribute \src "ls180.v:221.6-221.47" - wire \main_libresocsim_uart_tx_fifo_syncfifo_we - attribute \src "ls180.v:222.6-222.53" - wire \main_libresocsim_uart_tx_fifo_syncfifo_writable - attribute \src "ls180.v:231.11-231.51" - wire width 4 \main_libresocsim_uart_tx_fifo_wrport_adr - attribute \src "ls180.v:232.12-232.54" - wire width 10 \main_libresocsim_uart_tx_fifo_wrport_dat_r - attribute \src "ls180.v:234.12-234.54" - wire width 10 \main_libresocsim_uart_tx_fifo_wrport_dat_w - attribute \src "ls180.v:233.6-233.45" - wire \main_libresocsim_uart_tx_fifo_wrport_we - attribute \src "ls180.v:179.5-179.41" - wire \main_libresocsim_uart_tx_old_trigger - attribute \src "ls180.v:176.5-176.37" - wire \main_libresocsim_uart_tx_pending - attribute \src "ls180.v:175.6-175.37" - wire \main_libresocsim_uart_tx_status - attribute \src "ls180.v:177.6-177.38" - wire \main_libresocsim_uart_tx_trigger - attribute \src "ls180.v:195.6-195.42" - wire \main_libresocsim_uart_txempty_status - attribute \src "ls180.v:196.6-196.38" - wire \main_libresocsim_uart_txempty_we - attribute \src "ls180.v:170.6-170.41" - wire \main_libresocsim_uart_txfull_status - attribute \src "ls180.v:171.6-171.37" - wire \main_libresocsim_uart_txfull_we - attribute \src "ls180.v:201.6-201.43" - wire \main_libresocsim_uart_uart_sink_first - attribute \src "ls180.v:202.6-202.42" - wire \main_libresocsim_uart_uart_sink_last - attribute \src "ls180.v:203.12-203.56" - wire width 8 \main_libresocsim_uart_uart_sink_payload_data - attribute \src "ls180.v:200.6-200.43" - wire \main_libresocsim_uart_uart_sink_ready - attribute \src "ls180.v:199.6-199.43" - wire \main_libresocsim_uart_uart_sink_valid - attribute \src "ls180.v:206.6-206.45" - wire \main_libresocsim_uart_uart_source_first - attribute \src "ls180.v:207.6-207.44" - wire \main_libresocsim_uart_uart_source_last - attribute \src "ls180.v:208.12-208.58" - wire width 8 \main_libresocsim_uart_uart_source_payload_data - attribute \src "ls180.v:205.6-205.45" - wire \main_libresocsim_uart_uart_source_ready - attribute \src "ls180.v:204.6-204.45" - wire \main_libresocsim_uart_uart_source_valid - attribute \src "ls180.v:140.11-140.30" - wire width 4 \main_libresocsim_we - attribute \src "ls180.v:892.6-892.26" - wire \main_litedram_wb_ack - attribute \src "ls180.v:886.12-886.32" - wire width 30 \main_litedram_wb_adr - attribute \src "ls180.v:890.5-890.25" - wire \main_litedram_wb_cyc - attribute \src "ls180.v:888.13-888.35" - wire width 16 \main_litedram_wb_dat_r - attribute \src "ls180.v:887.12-887.34" - wire width 16 \main_litedram_wb_dat_w - attribute \src "ls180.v:889.11-889.31" - wire width 2 \main_litedram_wb_sel - attribute \src "ls180.v:891.5-891.25" - wire \main_litedram_wb_stb - attribute \src "ls180.v:893.5-893.24" - wire \main_litedram_wb_we - attribute \src "ls180.v:914.6-914.19" - wire \main_loopback - attribute \src "ls180.v:931.5-931.21" - wire \main_loopback_re - attribute \src "ls180.v:930.5-930.26" - wire \main_loopback_storage - attribute \src "ls180.v:912.11-912.20" - wire width 8 \main_miso - attribute \src "ls180.v:942.11-942.25" - wire width 8 \main_miso_data - attribute \src "ls180.v:936.5-936.20" - wire \main_miso_latch - attribute \src "ls180.v:925.12-925.28" - wire width 8 \main_miso_status - attribute \src "ls180.v:926.6-926.18" - wire \main_miso_we - attribute \src "ls180.v:911.12-911.21" - wire width 8 \main_mosi - attribute \src "ls180.v:940.11-940.25" - wire width 8 \main_mosi_data - attribute \src "ls180.v:935.5-935.20" - wire \main_mosi_latch - attribute \src "ls180.v:924.5-924.17" - wire \main_mosi_re - attribute \src "ls180.v:941.11-941.24" - wire width 3 \main_mosi_sel - attribute \src "ls180.v:923.11-923.28" - wire width 8 \main_mosi_storage - attribute \src "ls180.v:865.6-865.24" - wire \main_port_cmd_last - attribute \src "ls180.v:867.13-867.39" - wire width 24 \main_port_cmd_payload_addr - attribute \src "ls180.v:866.6-866.30" - wire \main_port_cmd_payload_we - attribute \src "ls180.v:864.6-864.25" - wire \main_port_cmd_ready - attribute \src "ls180.v:863.6-863.25" - wire \main_port_cmd_valid - attribute \src "ls180.v:862.6-862.21" - wire \main_port_flush - attribute \src "ls180.v:874.13-874.41" - wire width 16 \main_port_rdata_payload_data - attribute \src "ls180.v:873.6-873.27" - wire \main_port_rdata_ready - attribute \src "ls180.v:872.6-872.27" - wire \main_port_rdata_valid - attribute \src "ls180.v:870.13-870.41" - wire width 16 \main_port_wdata_payload_data - attribute \src "ls180.v:871.12-871.38" - wire width 2 \main_port_wdata_payload_we - attribute \src "ls180.v:869.6-869.27" - wire \main_port_wdata_ready - attribute \src "ls180.v:868.6-868.27" - wire \main_port_wdata_valid - attribute \src "ls180.v:331.11-331.25" - wire width 3 \main_rddata_en - attribute \src "ls180.v:393.5-393.26" - wire \main_sdram_address_re - attribute \src "ls180.v:392.12-392.38" - wire width 13 \main_sdram_address_storage - attribute \src "ls180.v:395.5-395.27" - wire \main_sdram_baddress_re - attribute \src "ls180.v:394.11-394.38" - wire width 2 \main_sdram_baddress_storage - attribute \src "ls180.v:491.5-491.43" - wire \main_sdram_bankmachine0_auto_precharge - attribute \src "ls180.v:513.11-513.63" - wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - attribute \src "ls180.v:518.6-518.58" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:523.6-523.64" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:524.6-524.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:522.13-522.78" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:521.6-521.69" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:527.6-527.65" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:528.6-528.64" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:526.13-526.79" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:525.6-525.70" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:510.11-510.61" - wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level - attribute \src "ls180.v:512.11-512.63" - wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - attribute \src "ls180.v:519.12-519.67" - wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:520.13-520.70" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:511.5-511.57" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:494.5-494.60" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:495.5-495.59" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:497.13-497.75" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:496.6-496.66" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:493.6-493.61" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:492.6-492.61" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:500.6-500.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:501.6-501.62" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:503.13-503.77" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:502.6-502.68" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:499.6-499.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:498.6-498.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:508.13-508.71" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - attribute \src "ls180.v:509.13-509.72" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout - attribute \src "ls180.v:506.6-506.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - attribute \src "ls180.v:507.6-507.69" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - attribute \src "ls180.v:504.6-504.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - attribute \src "ls180.v:505.6-505.69" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - attribute \src "ls180.v:514.11-514.66" - wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:515.13-515.70" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:517.13-517.70" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:516.6-516.60" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:531.6-531.51" - wire \main_sdram_bankmachine0_cmd_buffer_sink_first - attribute \src "ls180.v:532.6-532.50" - wire \main_sdram_bankmachine0_cmd_buffer_sink_last - attribute \src "ls180.v:534.13-534.65" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:533.6-533.56" - wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we - attribute \src "ls180.v:530.6-530.51" - wire \main_sdram_bankmachine0_cmd_buffer_sink_ready - attribute \src "ls180.v:529.6-529.51" - wire \main_sdram_bankmachine0_cmd_buffer_sink_valid - attribute \src "ls180.v:537.5-537.52" - wire \main_sdram_bankmachine0_cmd_buffer_source_first - attribute \src "ls180.v:538.5-538.51" - wire \main_sdram_bankmachine0_cmd_buffer_source_last - attribute \src "ls180.v:540.12-540.66" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr - attribute \src "ls180.v:539.5-539.57" - wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:536.6-536.53" - wire \main_sdram_bankmachine0_cmd_buffer_source_ready - attribute \src "ls180.v:535.5-535.52" - wire \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:483.12-483.49" - wire width 13 \main_sdram_bankmachine0_cmd_payload_a - attribute \src "ls180.v:484.12-484.50" - wire width 2 \main_sdram_bankmachine0_cmd_payload_ba - attribute \src "ls180.v:485.5-485.44" - wire \main_sdram_bankmachine0_cmd_payload_cas - attribute \src "ls180.v:488.5-488.47" - wire \main_sdram_bankmachine0_cmd_payload_is_cmd - attribute \src "ls180.v:489.5-489.48" - wire \main_sdram_bankmachine0_cmd_payload_is_read - attribute \src "ls180.v:490.5-490.49" - wire \main_sdram_bankmachine0_cmd_payload_is_write - attribute \src "ls180.v:486.5-486.44" - wire \main_sdram_bankmachine0_cmd_payload_ras - attribute \src "ls180.v:487.5-487.43" - wire \main_sdram_bankmachine0_cmd_payload_we - attribute \src "ls180.v:482.5-482.38" - wire \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:481.5-481.38" - wire \main_sdram_bankmachine0_cmd_valid - attribute \src "ls180.v:480.5-480.40" - wire \main_sdram_bankmachine0_refresh_gnt - attribute \src "ls180.v:479.6-479.41" - wire \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:475.13-475.45" - wire width 22 \main_sdram_bankmachine0_req_addr - attribute \src "ls180.v:476.6-476.38" - wire \main_sdram_bankmachine0_req_lock - attribute \src "ls180.v:478.5-478.44" - wire \main_sdram_bankmachine0_req_rdata_valid - attribute \src "ls180.v:473.6-473.39" - wire \main_sdram_bankmachine0_req_ready - attribute \src "ls180.v:472.6-472.39" - wire \main_sdram_bankmachine0_req_valid - attribute \src "ls180.v:477.5-477.44" - wire \main_sdram_bankmachine0_req_wdata_ready - attribute \src "ls180.v:474.6-474.36" - wire \main_sdram_bankmachine0_req_we - attribute \src "ls180.v:541.12-541.39" - wire width 13 \main_sdram_bankmachine0_row - attribute \src "ls180.v:545.5-545.38" - wire \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:546.5-546.47" - wire \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:543.6-543.37" - wire \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:544.5-544.37" - wire \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:542.5-542.39" - wire \main_sdram_bankmachine0_row_opened - attribute \no_retiming "true" - attribute \src "ls180.v:553.32-553.69" - wire \main_sdram_bankmachine0_trascon_ready - attribute \src "ls180.v:552.6-552.43" - wire \main_sdram_bankmachine0_trascon_valid - attribute \no_retiming "true" - attribute \src "ls180.v:551.32-551.68" - wire \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:550.6-550.42" - wire \main_sdram_bankmachine0_trccon_valid - attribute \src "ls180.v:549.11-549.48" - wire width 3 \main_sdram_bankmachine0_twtpcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:548.32-548.69" - wire \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:547.6-547.43" - wire \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:573.5-573.43" - wire \main_sdram_bankmachine1_auto_precharge - attribute \src "ls180.v:595.11-595.63" - wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - attribute \src "ls180.v:600.6-600.58" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:605.6-605.64" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:606.6-606.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:604.13-604.78" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:603.6-603.69" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:609.6-609.65" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:610.6-610.64" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:608.13-608.79" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:607.6-607.70" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:592.11-592.61" - wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level - attribute \src "ls180.v:594.11-594.63" - wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - attribute \src "ls180.v:601.12-601.67" - wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:602.13-602.70" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:593.5-593.57" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:576.5-576.60" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:577.5-577.59" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:579.13-579.75" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:578.6-578.66" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:575.6-575.61" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:574.6-574.61" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:582.6-582.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:583.6-583.62" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:585.13-585.77" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:584.6-584.68" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:581.6-581.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:580.6-580.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:590.13-590.71" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - attribute \src "ls180.v:591.13-591.72" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout - attribute \src "ls180.v:588.6-588.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - attribute \src "ls180.v:589.6-589.69" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - attribute \src "ls180.v:586.6-586.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - attribute \src "ls180.v:587.6-587.69" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - attribute \src "ls180.v:596.11-596.66" - wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:597.13-597.70" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:599.13-599.70" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:598.6-598.60" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:613.6-613.51" - wire \main_sdram_bankmachine1_cmd_buffer_sink_first - attribute \src "ls180.v:614.6-614.50" - wire \main_sdram_bankmachine1_cmd_buffer_sink_last - attribute \src "ls180.v:616.13-616.65" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:615.6-615.56" - wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we - attribute \src "ls180.v:612.6-612.51" - wire \main_sdram_bankmachine1_cmd_buffer_sink_ready - attribute \src "ls180.v:611.6-611.51" - wire \main_sdram_bankmachine1_cmd_buffer_sink_valid - attribute \src "ls180.v:619.5-619.52" - wire \main_sdram_bankmachine1_cmd_buffer_source_first - attribute \src "ls180.v:620.5-620.51" - wire \main_sdram_bankmachine1_cmd_buffer_source_last - attribute \src "ls180.v:622.12-622.66" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr - attribute \src "ls180.v:621.5-621.57" - wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:618.6-618.53" - wire \main_sdram_bankmachine1_cmd_buffer_source_ready - attribute \src "ls180.v:617.5-617.52" - wire \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:565.12-565.49" - wire width 13 \main_sdram_bankmachine1_cmd_payload_a - attribute \src "ls180.v:566.12-566.50" - wire width 2 \main_sdram_bankmachine1_cmd_payload_ba - attribute \src "ls180.v:567.5-567.44" - wire \main_sdram_bankmachine1_cmd_payload_cas - attribute \src "ls180.v:570.5-570.47" - wire \main_sdram_bankmachine1_cmd_payload_is_cmd - attribute \src "ls180.v:571.5-571.48" - wire \main_sdram_bankmachine1_cmd_payload_is_read - attribute \src "ls180.v:572.5-572.49" - wire \main_sdram_bankmachine1_cmd_payload_is_write - attribute \src "ls180.v:568.5-568.44" - wire \main_sdram_bankmachine1_cmd_payload_ras - attribute \src "ls180.v:569.5-569.43" - wire \main_sdram_bankmachine1_cmd_payload_we - attribute \src "ls180.v:564.5-564.38" - wire \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:563.5-563.38" - wire \main_sdram_bankmachine1_cmd_valid - attribute \src "ls180.v:562.5-562.40" - wire \main_sdram_bankmachine1_refresh_gnt - attribute \src "ls180.v:561.6-561.41" - wire \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:557.13-557.45" - wire width 22 \main_sdram_bankmachine1_req_addr - attribute \src "ls180.v:558.6-558.38" - wire \main_sdram_bankmachine1_req_lock - attribute \src "ls180.v:560.5-560.44" - wire \main_sdram_bankmachine1_req_rdata_valid - attribute \src "ls180.v:555.6-555.39" - wire \main_sdram_bankmachine1_req_ready - attribute \src "ls180.v:554.6-554.39" - wire \main_sdram_bankmachine1_req_valid - attribute \src "ls180.v:559.5-559.44" - wire \main_sdram_bankmachine1_req_wdata_ready - attribute \src "ls180.v:556.6-556.36" - wire \main_sdram_bankmachine1_req_we - attribute \src "ls180.v:623.12-623.39" - wire width 13 \main_sdram_bankmachine1_row - attribute \src "ls180.v:627.5-627.38" - wire \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:628.5-628.47" - wire \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:625.6-625.37" - wire \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:626.5-626.37" - wire \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:624.5-624.39" - wire \main_sdram_bankmachine1_row_opened - attribute \no_retiming "true" - attribute \src "ls180.v:635.32-635.69" - wire \main_sdram_bankmachine1_trascon_ready - attribute \src "ls180.v:634.6-634.43" - wire \main_sdram_bankmachine1_trascon_valid - attribute \no_retiming "true" - attribute \src "ls180.v:633.32-633.68" - wire \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:632.6-632.42" - wire \main_sdram_bankmachine1_trccon_valid - attribute \src "ls180.v:631.11-631.48" - wire width 3 \main_sdram_bankmachine1_twtpcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:630.32-630.69" - wire \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:629.6-629.43" - wire \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:655.5-655.43" - wire \main_sdram_bankmachine2_auto_precharge - attribute \src "ls180.v:677.11-677.63" - wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - attribute \src "ls180.v:682.6-682.58" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:687.6-687.64" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:688.6-688.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:686.13-686.78" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:685.6-685.69" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:691.6-691.65" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:692.6-692.64" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:690.13-690.79" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:689.6-689.70" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:674.11-674.61" - wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level - attribute \src "ls180.v:676.11-676.63" - wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - attribute \src "ls180.v:683.12-683.67" - wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:684.13-684.70" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:675.5-675.57" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:658.5-658.60" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:659.5-659.59" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:661.13-661.75" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:660.6-660.66" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:657.6-657.61" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:656.6-656.61" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:664.6-664.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:665.6-665.62" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:667.13-667.77" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:666.6-666.68" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:663.6-663.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:662.6-662.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:672.13-672.71" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - attribute \src "ls180.v:673.13-673.72" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout - attribute \src "ls180.v:670.6-670.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - attribute \src "ls180.v:671.6-671.69" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - attribute \src "ls180.v:668.6-668.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - attribute \src "ls180.v:669.6-669.69" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - attribute \src "ls180.v:678.11-678.66" - wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:679.13-679.70" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:681.13-681.70" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:680.6-680.60" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:695.6-695.51" - wire \main_sdram_bankmachine2_cmd_buffer_sink_first - attribute \src "ls180.v:696.6-696.50" - wire \main_sdram_bankmachine2_cmd_buffer_sink_last - attribute \src "ls180.v:698.13-698.65" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:697.6-697.56" - wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we - attribute \src "ls180.v:694.6-694.51" - wire \main_sdram_bankmachine2_cmd_buffer_sink_ready - attribute \src "ls180.v:693.6-693.51" - wire \main_sdram_bankmachine2_cmd_buffer_sink_valid - attribute \src "ls180.v:701.5-701.52" - wire \main_sdram_bankmachine2_cmd_buffer_source_first - attribute \src "ls180.v:702.5-702.51" - wire \main_sdram_bankmachine2_cmd_buffer_source_last - attribute \src "ls180.v:704.12-704.66" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr - attribute \src "ls180.v:703.5-703.57" - wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:700.6-700.53" - wire \main_sdram_bankmachine2_cmd_buffer_source_ready - attribute \src "ls180.v:699.5-699.52" - wire \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:647.12-647.49" - wire width 13 \main_sdram_bankmachine2_cmd_payload_a - attribute \src "ls180.v:648.12-648.50" - wire width 2 \main_sdram_bankmachine2_cmd_payload_ba - attribute \src "ls180.v:649.5-649.44" - wire \main_sdram_bankmachine2_cmd_payload_cas - attribute \src "ls180.v:652.5-652.47" - wire \main_sdram_bankmachine2_cmd_payload_is_cmd - attribute \src "ls180.v:653.5-653.48" - wire \main_sdram_bankmachine2_cmd_payload_is_read - attribute \src "ls180.v:654.5-654.49" - wire \main_sdram_bankmachine2_cmd_payload_is_write - attribute \src "ls180.v:650.5-650.44" - wire \main_sdram_bankmachine2_cmd_payload_ras - attribute \src "ls180.v:651.5-651.43" - wire \main_sdram_bankmachine2_cmd_payload_we - attribute \src "ls180.v:646.5-646.38" - wire \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:645.5-645.38" - wire \main_sdram_bankmachine2_cmd_valid - attribute \src "ls180.v:644.5-644.40" - wire \main_sdram_bankmachine2_refresh_gnt - attribute \src "ls180.v:643.6-643.41" - wire \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:639.13-639.45" - wire width 22 \main_sdram_bankmachine2_req_addr - attribute \src "ls180.v:640.6-640.38" - wire \main_sdram_bankmachine2_req_lock - attribute \src "ls180.v:642.5-642.44" - wire \main_sdram_bankmachine2_req_rdata_valid - attribute \src "ls180.v:637.6-637.39" - wire \main_sdram_bankmachine2_req_ready - attribute \src "ls180.v:636.6-636.39" - wire \main_sdram_bankmachine2_req_valid - attribute \src "ls180.v:641.5-641.44" - wire \main_sdram_bankmachine2_req_wdata_ready - attribute \src "ls180.v:638.6-638.36" - wire \main_sdram_bankmachine2_req_we - attribute \src "ls180.v:705.12-705.39" - wire width 13 \main_sdram_bankmachine2_row - attribute \src "ls180.v:709.5-709.38" - wire \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:710.5-710.47" - wire \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:707.6-707.37" - wire \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:708.5-708.37" - wire \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:706.5-706.39" - wire \main_sdram_bankmachine2_row_opened - attribute \no_retiming "true" - attribute \src "ls180.v:717.32-717.69" - wire \main_sdram_bankmachine2_trascon_ready - attribute \src "ls180.v:716.6-716.43" - wire \main_sdram_bankmachine2_trascon_valid - attribute \no_retiming "true" - attribute \src "ls180.v:715.32-715.68" - wire \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:714.6-714.42" - wire \main_sdram_bankmachine2_trccon_valid - attribute \src "ls180.v:713.11-713.48" - wire width 3 \main_sdram_bankmachine2_twtpcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:712.32-712.69" - wire \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:711.6-711.43" - wire \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:737.5-737.43" - wire \main_sdram_bankmachine3_auto_precharge - attribute \src "ls180.v:759.11-759.63" - wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - attribute \src "ls180.v:764.6-764.58" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:769.6-769.64" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:770.6-770.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:768.13-768.78" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:767.6-767.69" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:773.6-773.65" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:774.6-774.64" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:772.13-772.79" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:771.6-771.70" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:756.11-756.61" - wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level - attribute \src "ls180.v:758.11-758.63" - wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - attribute \src "ls180.v:765.12-765.67" - wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:766.13-766.70" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:757.5-757.57" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:740.5-740.60" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:741.5-741.59" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:743.13-743.75" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:742.6-742.66" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:739.6-739.61" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:738.6-738.61" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:746.6-746.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:747.6-747.62" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:749.13-749.77" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:748.6-748.68" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:745.6-745.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:744.6-744.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:754.13-754.71" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - attribute \src "ls180.v:755.13-755.72" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout - attribute \src "ls180.v:752.6-752.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - attribute \src "ls180.v:753.6-753.69" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - attribute \src "ls180.v:750.6-750.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - attribute \src "ls180.v:751.6-751.69" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - attribute \src "ls180.v:760.11-760.66" - wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:761.13-761.70" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:763.13-763.70" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:762.6-762.60" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:777.6-777.51" - wire \main_sdram_bankmachine3_cmd_buffer_sink_first - attribute \src "ls180.v:778.6-778.50" - wire \main_sdram_bankmachine3_cmd_buffer_sink_last - attribute \src "ls180.v:780.13-780.65" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:779.6-779.56" - wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we - attribute \src "ls180.v:776.6-776.51" - wire \main_sdram_bankmachine3_cmd_buffer_sink_ready - attribute \src "ls180.v:775.6-775.51" - wire \main_sdram_bankmachine3_cmd_buffer_sink_valid - attribute \src "ls180.v:783.5-783.52" - wire \main_sdram_bankmachine3_cmd_buffer_source_first - attribute \src "ls180.v:784.5-784.51" - wire \main_sdram_bankmachine3_cmd_buffer_source_last - attribute \src "ls180.v:786.12-786.66" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr - attribute \src "ls180.v:785.5-785.57" - wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:782.6-782.53" - wire \main_sdram_bankmachine3_cmd_buffer_source_ready - attribute \src "ls180.v:781.5-781.52" - wire \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:729.12-729.49" - wire width 13 \main_sdram_bankmachine3_cmd_payload_a - attribute \src "ls180.v:730.12-730.50" - wire width 2 \main_sdram_bankmachine3_cmd_payload_ba - attribute \src "ls180.v:731.5-731.44" - wire \main_sdram_bankmachine3_cmd_payload_cas - attribute \src "ls180.v:734.5-734.47" - wire \main_sdram_bankmachine3_cmd_payload_is_cmd - attribute \src "ls180.v:735.5-735.48" - wire \main_sdram_bankmachine3_cmd_payload_is_read - attribute \src "ls180.v:736.5-736.49" - wire \main_sdram_bankmachine3_cmd_payload_is_write - attribute \src "ls180.v:732.5-732.44" - wire \main_sdram_bankmachine3_cmd_payload_ras - attribute \src "ls180.v:733.5-733.43" - wire \main_sdram_bankmachine3_cmd_payload_we - attribute \src "ls180.v:728.5-728.38" - wire \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:727.5-727.38" - wire \main_sdram_bankmachine3_cmd_valid - attribute \src "ls180.v:726.5-726.40" - wire \main_sdram_bankmachine3_refresh_gnt - attribute \src "ls180.v:725.6-725.41" - wire \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:721.13-721.45" - wire width 22 \main_sdram_bankmachine3_req_addr - attribute \src "ls180.v:722.6-722.38" - wire \main_sdram_bankmachine3_req_lock - attribute \src "ls180.v:724.5-724.44" - wire \main_sdram_bankmachine3_req_rdata_valid - attribute \src "ls180.v:719.6-719.39" - wire \main_sdram_bankmachine3_req_ready - attribute \src "ls180.v:718.6-718.39" - wire \main_sdram_bankmachine3_req_valid - attribute \src "ls180.v:723.5-723.44" - wire \main_sdram_bankmachine3_req_wdata_ready - attribute \src "ls180.v:720.6-720.36" - wire \main_sdram_bankmachine3_req_we - attribute \src "ls180.v:787.12-787.39" - wire width 13 \main_sdram_bankmachine3_row - attribute \src "ls180.v:791.5-791.38" - wire \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:792.5-792.47" - wire \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:789.6-789.37" - wire \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:790.5-790.37" - wire \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:788.5-788.39" - wire \main_sdram_bankmachine3_row_opened - attribute \no_retiming "true" - attribute \src "ls180.v:799.32-799.69" - wire \main_sdram_bankmachine3_trascon_ready - attribute \src "ls180.v:798.6-798.43" - wire \main_sdram_bankmachine3_trascon_valid - attribute \no_retiming "true" - attribute \src "ls180.v:797.32-797.68" - wire \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:796.6-796.42" - wire \main_sdram_bankmachine3_trccon_valid - attribute \src "ls180.v:795.11-795.48" - wire width 3 \main_sdram_bankmachine3_twtpcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:794.32-794.69" - wire \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:793.6-793.43" - wire \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:801.6-801.28" - wire \main_sdram_cas_allowed - attribute \src "ls180.v:819.6-819.30" - wire \main_sdram_choose_cmd_ce - attribute \src "ls180.v:808.13-808.48" - wire width 13 \main_sdram_choose_cmd_cmd_payload_a - attribute \src "ls180.v:809.12-809.48" - wire width 2 \main_sdram_choose_cmd_cmd_payload_ba - attribute \src "ls180.v:810.5-810.42" - wire \main_sdram_choose_cmd_cmd_payload_cas - attribute \src "ls180.v:813.6-813.46" - wire \main_sdram_choose_cmd_cmd_payload_is_cmd - attribute \src "ls180.v:814.6-814.47" - wire \main_sdram_choose_cmd_cmd_payload_is_read - attribute \src "ls180.v:815.6-815.48" - wire \main_sdram_choose_cmd_cmd_payload_is_write - attribute \src "ls180.v:811.5-811.42" - wire \main_sdram_choose_cmd_cmd_payload_ras - attribute \src "ls180.v:812.5-812.41" - wire \main_sdram_choose_cmd_cmd_payload_we - attribute \src "ls180.v:807.5-807.36" - wire \main_sdram_choose_cmd_cmd_ready - attribute \src "ls180.v:806.6-806.37" - wire \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:818.11-818.38" - wire width 2 \main_sdram_choose_cmd_grant - attribute \src "ls180.v:817.12-817.41" - wire width 4 \main_sdram_choose_cmd_request - attribute \src "ls180.v:816.11-816.39" - wire width 4 \main_sdram_choose_cmd_valids - attribute \src "ls180.v:805.5-805.41" - wire \main_sdram_choose_cmd_want_activates - attribute \src "ls180.v:804.5-804.36" - wire \main_sdram_choose_cmd_want_cmds - attribute \src "ls180.v:802.5-802.37" - wire \main_sdram_choose_cmd_want_reads - attribute \src "ls180.v:803.5-803.38" - wire \main_sdram_choose_cmd_want_writes - attribute \src "ls180.v:837.6-837.30" - wire \main_sdram_choose_req_ce - attribute \src "ls180.v:826.13-826.48" - wire width 13 \main_sdram_choose_req_cmd_payload_a - attribute \src "ls180.v:827.12-827.48" - wire width 2 \main_sdram_choose_req_cmd_payload_ba - attribute \src "ls180.v:828.5-828.42" - wire \main_sdram_choose_req_cmd_payload_cas - attribute \src "ls180.v:831.6-831.46" - wire \main_sdram_choose_req_cmd_payload_is_cmd - attribute \src "ls180.v:832.6-832.47" - wire \main_sdram_choose_req_cmd_payload_is_read - attribute \src "ls180.v:833.6-833.48" - wire \main_sdram_choose_req_cmd_payload_is_write - attribute \src "ls180.v:829.5-829.42" - wire \main_sdram_choose_req_cmd_payload_ras - attribute \src "ls180.v:830.5-830.41" - wire \main_sdram_choose_req_cmd_payload_we - attribute \src "ls180.v:825.5-825.36" - wire \main_sdram_choose_req_cmd_ready - attribute \src "ls180.v:824.6-824.37" - wire \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:836.11-836.38" - wire width 2 \main_sdram_choose_req_grant - attribute \src "ls180.v:835.12-835.41" - wire width 4 \main_sdram_choose_req_request - attribute \src "ls180.v:834.11-834.39" - wire width 4 \main_sdram_choose_req_valids - attribute \src "ls180.v:823.5-823.41" - wire \main_sdram_choose_req_want_activates - attribute \src "ls180.v:822.6-822.37" - wire \main_sdram_choose_req_want_cmds - attribute \src "ls180.v:820.5-820.37" - wire \main_sdram_choose_req_want_reads - attribute \src "ls180.v:821.5-821.38" - wire \main_sdram_choose_req_want_writes - attribute \src "ls180.v:381.6-381.20" - wire \main_sdram_cke - attribute \src "ls180.v:449.5-449.24" - wire \main_sdram_cmd_last - attribute \src "ls180.v:450.12-450.36" - wire width 13 \main_sdram_cmd_payload_a - attribute \src "ls180.v:451.11-451.36" - wire width 2 \main_sdram_cmd_payload_ba - attribute \src "ls180.v:452.5-452.31" - wire \main_sdram_cmd_payload_cas - attribute \src "ls180.v:455.5-455.35" - wire \main_sdram_cmd_payload_is_read - attribute \src "ls180.v:456.5-456.36" - wire \main_sdram_cmd_payload_is_write - attribute \src "ls180.v:453.5-453.31" - wire \main_sdram_cmd_payload_ras - attribute \src "ls180.v:454.5-454.30" - wire \main_sdram_cmd_payload_we - attribute \src "ls180.v:448.5-448.25" - wire \main_sdram_cmd_ready - attribute \src "ls180.v:447.5-447.25" - wire \main_sdram_cmd_valid - attribute \src "ls180.v:389.6-389.32" - wire \main_sdram_command_issue_r - attribute \src "ls180.v:388.6-388.33" - wire \main_sdram_command_issue_re - attribute \src "ls180.v:391.5-391.31" - wire \main_sdram_command_issue_w - attribute \src "ls180.v:390.6-390.33" - wire \main_sdram_command_issue_we - attribute \src "ls180.v:387.5-387.26" - wire \main_sdram_command_re - attribute \src "ls180.v:386.11-386.37" - wire width 6 \main_sdram_command_storage - attribute \src "ls180.v:440.5-440.28" - wire \main_sdram_dfi_p0_act_n - attribute \src "ls180.v:431.12-431.37" - wire width 13 \main_sdram_dfi_p0_address - attribute \src "ls180.v:432.11-432.33" - wire width 2 \main_sdram_dfi_p0_bank - attribute \src "ls180.v:433.5-433.28" - wire \main_sdram_dfi_p0_cas_n - attribute \src "ls180.v:437.6-437.27" - wire \main_sdram_dfi_p0_cke - attribute \src "ls180.v:434.5-434.27" - wire \main_sdram_dfi_p0_cs_n - attribute \src "ls180.v:438.6-438.27" - wire \main_sdram_dfi_p0_odt - attribute \src "ls180.v:435.5-435.28" - wire \main_sdram_dfi_p0_ras_n - attribute \src "ls180.v:445.13-445.37" - wire width 16 \main_sdram_dfi_p0_rddata - attribute \src "ls180.v:444.5-444.32" - wire \main_sdram_dfi_p0_rddata_en - attribute \src "ls180.v:446.6-446.36" - wire \main_sdram_dfi_p0_rddata_valid - attribute \src "ls180.v:439.6-439.31" - wire \main_sdram_dfi_p0_reset_n - attribute \src "ls180.v:436.5-436.27" - wire \main_sdram_dfi_p0_we_n - attribute \src "ls180.v:441.13-441.37" - wire width 16 \main_sdram_dfi_p0_wrdata - attribute \src "ls180.v:442.5-442.32" - wire \main_sdram_dfi_p0_wrdata_en - attribute \src "ls180.v:443.12-443.41" - wire width 2 \main_sdram_dfi_p0_wrdata_mask - attribute \src "ls180.v:855.5-855.19" - wire \main_sdram_en0 - attribute \src "ls180.v:858.5-858.19" - wire \main_sdram_en1 - attribute \src "ls180.v:861.6-861.30" - wire \main_sdram_go_to_refresh - attribute \src "ls180.v:403.13-403.44" - wire width 22 \main_sdram_interface_bank0_addr - attribute \src "ls180.v:404.6-404.37" - wire \main_sdram_interface_bank0_lock - attribute \src "ls180.v:406.6-406.44" - wire \main_sdram_interface_bank0_rdata_valid - attribute \src "ls180.v:401.6-401.38" - wire \main_sdram_interface_bank0_ready - attribute \src "ls180.v:400.6-400.38" - wire \main_sdram_interface_bank0_valid - attribute \src "ls180.v:405.6-405.44" - wire \main_sdram_interface_bank0_wdata_ready - attribute \src "ls180.v:402.6-402.35" - wire \main_sdram_interface_bank0_we - attribute \src "ls180.v:410.13-410.44" - wire width 22 \main_sdram_interface_bank1_addr - attribute \src "ls180.v:411.6-411.37" - wire \main_sdram_interface_bank1_lock - attribute \src "ls180.v:413.6-413.44" - wire \main_sdram_interface_bank1_rdata_valid - attribute \src "ls180.v:408.6-408.38" - wire \main_sdram_interface_bank1_ready - attribute \src "ls180.v:407.6-407.38" - wire \main_sdram_interface_bank1_valid - attribute \src "ls180.v:412.6-412.44" - wire \main_sdram_interface_bank1_wdata_ready - attribute \src "ls180.v:409.6-409.35" - wire \main_sdram_interface_bank1_we - attribute \src "ls180.v:417.13-417.44" - wire width 22 \main_sdram_interface_bank2_addr - attribute \src "ls180.v:418.6-418.37" - wire \main_sdram_interface_bank2_lock - attribute \src "ls180.v:420.6-420.44" - wire \main_sdram_interface_bank2_rdata_valid - attribute \src "ls180.v:415.6-415.38" - wire \main_sdram_interface_bank2_ready - attribute \src "ls180.v:414.6-414.38" - wire \main_sdram_interface_bank2_valid - attribute \src "ls180.v:419.6-419.44" - wire \main_sdram_interface_bank2_wdata_ready - attribute \src "ls180.v:416.6-416.35" - wire \main_sdram_interface_bank2_we - attribute \src "ls180.v:424.13-424.44" - wire width 22 \main_sdram_interface_bank3_addr - attribute \src "ls180.v:425.6-425.37" - wire \main_sdram_interface_bank3_lock - attribute \src "ls180.v:427.6-427.44" - wire \main_sdram_interface_bank3_rdata_valid - attribute \src "ls180.v:422.6-422.38" - wire \main_sdram_interface_bank3_ready - attribute \src "ls180.v:421.6-421.38" - wire \main_sdram_interface_bank3_valid - attribute \src "ls180.v:426.6-426.44" - wire \main_sdram_interface_bank3_wdata_ready - attribute \src "ls180.v:423.6-423.35" - wire \main_sdram_interface_bank3_we - attribute \src "ls180.v:430.13-430.39" - wire width 16 \main_sdram_interface_rdata - attribute \src "ls180.v:428.12-428.38" - wire width 16 \main_sdram_interface_wdata - attribute \src "ls180.v:429.11-429.40" - wire width 2 \main_sdram_interface_wdata_we - attribute \src "ls180.v:341.5-341.29" - wire \main_sdram_inti_p0_act_n - attribute \src "ls180.v:332.13-332.39" - wire width 13 \main_sdram_inti_p0_address - attribute \src "ls180.v:333.12-333.35" - wire width 2 \main_sdram_inti_p0_bank - attribute \src "ls180.v:334.5-334.29" - wire \main_sdram_inti_p0_cas_n - attribute \src "ls180.v:338.6-338.28" - wire \main_sdram_inti_p0_cke - attribute \src "ls180.v:335.5-335.28" - wire \main_sdram_inti_p0_cs_n - attribute \src "ls180.v:339.6-339.28" - wire \main_sdram_inti_p0_odt - attribute \src "ls180.v:336.5-336.29" - wire \main_sdram_inti_p0_ras_n - attribute \src "ls180.v:346.12-346.37" - wire width 16 \main_sdram_inti_p0_rddata - attribute \src "ls180.v:345.6-345.34" - wire \main_sdram_inti_p0_rddata_en - attribute \src "ls180.v:347.5-347.36" - wire \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:340.6-340.32" - wire \main_sdram_inti_p0_reset_n - attribute \src "ls180.v:337.5-337.28" - wire \main_sdram_inti_p0_we_n - attribute \src "ls180.v:342.13-342.38" - wire width 16 \main_sdram_inti_p0_wrdata - attribute \src "ls180.v:343.6-343.34" - wire \main_sdram_inti_p0_wrdata_en - attribute \src "ls180.v:344.12-344.42" - wire width 2 \main_sdram_inti_p0_wrdata_mask - attribute \src "ls180.v:373.5-373.31" - wire \main_sdram_master_p0_act_n - attribute \src "ls180.v:364.12-364.40" - wire width 13 \main_sdram_master_p0_address - attribute \src "ls180.v:365.11-365.36" - wire width 2 \main_sdram_master_p0_bank - attribute \src "ls180.v:366.5-366.31" - wire \main_sdram_master_p0_cas_n - attribute \src "ls180.v:370.5-370.29" - wire \main_sdram_master_p0_cke - attribute \src "ls180.v:367.5-367.30" - wire \main_sdram_master_p0_cs_n - attribute \src "ls180.v:371.5-371.29" - wire \main_sdram_master_p0_odt - attribute \src "ls180.v:368.5-368.31" - wire \main_sdram_master_p0_ras_n - attribute \src "ls180.v:378.13-378.40" - wire width 16 \main_sdram_master_p0_rddata - attribute \src "ls180.v:377.5-377.35" - wire \main_sdram_master_p0_rddata_en - attribute \src "ls180.v:379.6-379.39" - wire \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:372.5-372.33" - wire \main_sdram_master_p0_reset_n - attribute \src "ls180.v:369.5-369.30" - wire \main_sdram_master_p0_we_n - attribute \src "ls180.v:374.12-374.39" - wire width 16 \main_sdram_master_p0_wrdata - attribute \src "ls180.v:375.5-375.35" - wire \main_sdram_master_p0_wrdata_en - attribute \src "ls180.v:376.11-376.43" - wire width 2 \main_sdram_master_p0_wrdata_mask - attribute \src "ls180.v:856.6-856.26" - wire \main_sdram_max_time0 - attribute \src "ls180.v:859.6-859.26" - wire \main_sdram_max_time1 - attribute \src "ls180.v:838.12-838.28" - wire width 13 \main_sdram_nop_a - attribute \src "ls180.v:839.11-839.28" - wire width 2 \main_sdram_nop_ba - attribute \src "ls180.v:382.6-382.20" - wire \main_sdram_odt - attribute \src "ls180.v:465.5-465.31" - wire \main_sdram_postponer_count - attribute \src "ls180.v:463.6-463.32" - wire \main_sdram_postponer_req_i - attribute \src "ls180.v:464.5-464.31" - wire \main_sdram_postponer_req_o - attribute \src "ls180.v:800.6-800.28" - wire \main_sdram_ras_allowed - attribute \src "ls180.v:385.5-385.18" - wire \main_sdram_re - attribute \src "ls180.v:853.6-853.31" - wire \main_sdram_read_available - attribute \src "ls180.v:383.6-383.24" - wire \main_sdram_reset_n - attribute \src "ls180.v:380.6-380.20" - wire \main_sdram_sel - attribute \src "ls180.v:471.5-471.31" - wire \main_sdram_sequencer_count - attribute \src "ls180.v:470.11-470.39" - wire width 4 \main_sdram_sequencer_counter - attribute \src "ls180.v:467.6-467.32" - wire \main_sdram_sequencer_done0 - attribute \src "ls180.v:469.5-469.31" - wire \main_sdram_sequencer_done1 - attribute \src "ls180.v:466.5-466.32" - wire \main_sdram_sequencer_start0 - attribute \src "ls180.v:468.6-468.33" - wire \main_sdram_sequencer_start1 - attribute \src "ls180.v:357.6-357.31" - wire \main_sdram_slave_p0_act_n - attribute \src "ls180.v:348.13-348.40" - wire width 13 \main_sdram_slave_p0_address - attribute \src "ls180.v:349.12-349.36" - wire width 2 \main_sdram_slave_p0_bank - attribute \src "ls180.v:350.6-350.31" - wire \main_sdram_slave_p0_cas_n - attribute \src "ls180.v:354.6-354.29" - wire \main_sdram_slave_p0_cke - attribute \src "ls180.v:351.6-351.30" - wire \main_sdram_slave_p0_cs_n - attribute \src "ls180.v:355.6-355.29" - wire \main_sdram_slave_p0_odt - attribute \src "ls180.v:352.6-352.31" - wire \main_sdram_slave_p0_ras_n - attribute \src "ls180.v:362.12-362.38" - wire width 16 \main_sdram_slave_p0_rddata - attribute \src "ls180.v:361.6-361.35" - wire \main_sdram_slave_p0_rddata_en - attribute \src "ls180.v:363.5-363.37" - wire \main_sdram_slave_p0_rddata_valid - attribute \src "ls180.v:356.6-356.33" - wire \main_sdram_slave_p0_reset_n - attribute \src "ls180.v:353.6-353.30" - wire \main_sdram_slave_p0_we_n - attribute \src "ls180.v:358.13-358.39" - wire width 16 \main_sdram_slave_p0_wrdata - attribute \src "ls180.v:359.6-359.35" - wire \main_sdram_slave_p0_wrdata_en - attribute \src "ls180.v:360.12-360.43" - wire width 2 \main_sdram_slave_p0_wrdata_mask - attribute \src "ls180.v:398.12-398.29" - wire width 16 \main_sdram_status - attribute \src "ls180.v:841.5-841.24" - wire \main_sdram_steerer0 - attribute \src "ls180.v:842.5-842.24" - wire \main_sdram_steerer1 - attribute \src "ls180.v:840.11-840.33" - wire width 2 \main_sdram_steerer_sel - attribute \src "ls180.v:384.11-384.29" - wire width 4 \main_sdram_storage - attribute \src "ls180.v:849.5-849.29" - wire \main_sdram_tccdcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:848.32-848.56" - wire \main_sdram_tccdcon_ready - attribute \src "ls180.v:847.6-847.30" - wire \main_sdram_tccdcon_valid - attribute \no_retiming "true" - attribute \src "ls180.v:846.32-846.56" - wire \main_sdram_tfawcon_ready - attribute \src "ls180.v:845.6-845.30" - wire \main_sdram_tfawcon_valid - attribute \src "ls180.v:857.11-857.27" - wire width 5 \main_sdram_time0 - attribute \src "ls180.v:860.11-860.27" - wire width 4 \main_sdram_time1 - attribute \src "ls180.v:460.12-460.35" - wire width 10 \main_sdram_timer_count0 - attribute \src "ls180.v:462.11-462.34" - wire width 10 \main_sdram_timer_count1 - attribute \src "ls180.v:459.6-459.28" - wire \main_sdram_timer_done0 - attribute \src "ls180.v:461.6-461.28" - wire \main_sdram_timer_done1 - attribute \src "ls180.v:458.6-458.27" - wire \main_sdram_timer_wait - attribute \no_retiming "true" - attribute \src "ls180.v:844.32-844.56" - wire \main_sdram_trrdcon_ready - attribute \src "ls180.v:843.6-843.30" - wire \main_sdram_trrdcon_valid - attribute \src "ls180.v:852.11-852.35" - wire width 3 \main_sdram_twtrcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:851.32-851.56" - wire \main_sdram_twtrcon_ready - attribute \src "ls180.v:850.6-850.30" - wire \main_sdram_twtrcon_valid - attribute \src "ls180.v:457.6-457.30" - wire \main_sdram_wants_refresh - attribute \src "ls180.v:399.6-399.19" - wire \main_sdram_we - attribute \src "ls180.v:397.5-397.25" - wire \main_sdram_wrdata_re - attribute \src "ls180.v:396.12-396.37" - wire width 16 \main_sdram_wrdata_storage - attribute \src "ls180.v:854.6-854.32" - wire \main_sdram_write_available - attribute \src "ls180.v:927.6-927.14" - wire \main_sel - attribute \src "ls180.v:907.6-907.17" - wire \main_start0 - attribute \src "ls180.v:916.5-916.16" - wire \main_start1 - attribute \src "ls180.v:921.6-921.24" - wire \main_status_status - attribute \src "ls180.v:922.6-922.20" - wire \main_status_we - attribute \src "ls180.v:881.5-881.22" - wire \main_wb_sdram_ack - attribute \src "ls180.v:875.13-875.30" - wire width 30 \main_wb_sdram_adr - attribute \src "ls180.v:884.12-884.29" - wire width 2 \main_wb_sdram_bte - attribute \src "ls180.v:883.12-883.29" - wire width 3 \main_wb_sdram_cti - attribute \src "ls180.v:879.6-879.23" - wire \main_wb_sdram_cyc - attribute \src "ls180.v:877.13-877.32" - wire width 32 \main_wb_sdram_dat_r - attribute \src "ls180.v:876.13-876.32" - wire width 32 \main_wb_sdram_dat_w - attribute \src "ls180.v:885.5-885.22" - wire \main_wb_sdram_err - attribute \src "ls180.v:878.12-878.29" - wire width 4 \main_wb_sdram_sel - attribute \src "ls180.v:880.6-880.23" - wire \main_wb_sdram_stb - attribute \src "ls180.v:882.6-882.22" - wire \main_wb_sdram_we - attribute \src "ls180.v:899.5-899.24" - wire \main_wdata_consumed - attribute \src "ls180.v:9367.11-9367.17" - wire width 7 \memadr - attribute \src "ls180.v:9387.11-9387.17" - wire width 10 \memdat - attribute \src "ls180.v:9388.11-9388.19" - wire width 10 \memdat_1 - attribute \src "ls180.v:9404.11-9404.19" - wire width 10 \memdat_2 - attribute \src "ls180.v:9405.11-9405.19" - wire width 10 \memdat_3 - attribute \src "ls180.v:9421.12-9421.20" - wire width 25 \memdat_4 - attribute \src "ls180.v:9435.12-9435.20" - wire width 25 \memdat_5 - attribute \src "ls180.v:9449.12-9449.20" - wire width 25 \memdat_6 - attribute \src "ls180.v:9463.12-9463.20" - wire width 25 \memdat_7 - attribute \src "ls180.v:9477.11-9477.19" - wire width 10 \memdat_8 - attribute \src "ls180.v:9491.11-9491.19" - wire width 10 \memdat_9 - attribute \src "ls180.v:313.6-313.13" - wire \por_clk - attribute \src "ls180.v:24.13-24.23" - wire output 20 \sdcard_clk - attribute \src "ls180.v:25.13-25.23" - wire inout 21 \sdcard_cmd - attribute \src "ls180.v:26.19-26.30" - wire width 4 inout 22 \sdcard_data - attribute \src "ls180.v:8.20-8.27" - wire width 13 output 4 \sdram_a - attribute \src "ls180.v:15.19-15.27" - wire width 2 output 11 \sdram_ba - attribute \src "ls180.v:12.13-12.24" - wire output 8 \sdram_cas_n - attribute \src "ls180.v:14.13-14.22" - wire output 10 \sdram_cke - attribute \src "ls180.v:13.13-13.23" - wire output 9 \sdram_cs_n - attribute \src "ls180.v:16.19-16.27" - wire width 2 output 12 \sdram_dm - attribute \src "ls180.v:9.20-9.28" - wire width 16 inout 5 \sdram_dq - attribute \src "ls180.v:11.13-11.24" - wire output 7 \sdram_ras_n - attribute \src "ls180.v:10.13-10.23" - wire output 6 \sdram_we_n - attribute \src "ls180.v:2424.6-2424.15" - wire \sdrio_clk - attribute \src "ls180.v:2425.6-2425.17" - wire \sdrio_clk_1 - attribute \src "ls180.v:2434.6-2434.18" - wire \sdrio_clk_10 - attribute \src "ls180.v:2435.6-2435.18" - wire \sdrio_clk_11 - attribute \src "ls180.v:2436.6-2436.18" - wire \sdrio_clk_12 - attribute \src "ls180.v:2437.6-2437.18" - wire \sdrio_clk_13 - attribute \src "ls180.v:2438.6-2438.18" - wire \sdrio_clk_14 - attribute \src "ls180.v:2439.6-2439.18" - wire \sdrio_clk_15 - attribute \src "ls180.v:2440.6-2440.18" - wire \sdrio_clk_16 - attribute \src "ls180.v:2441.6-2441.18" - wire \sdrio_clk_17 - attribute \src "ls180.v:2442.6-2442.18" - wire \sdrio_clk_18 - attribute \src "ls180.v:2443.6-2443.18" - wire \sdrio_clk_19 - attribute \src "ls180.v:2426.6-2426.17" - wire \sdrio_clk_2 - attribute \src "ls180.v:2447.6-2447.18" - wire \sdrio_clk_20 - attribute \src "ls180.v:2451.6-2451.18" - wire \sdrio_clk_21 - attribute \src "ls180.v:2455.6-2455.18" - wire \sdrio_clk_22 - attribute \src "ls180.v:2459.6-2459.18" - wire \sdrio_clk_23 - attribute \src "ls180.v:2463.6-2463.18" - wire \sdrio_clk_24 - attribute \src "ls180.v:2467.6-2467.18" - wire \sdrio_clk_25 - attribute \src "ls180.v:2471.6-2471.18" - wire \sdrio_clk_26 - attribute \src "ls180.v:2475.6-2475.18" - wire \sdrio_clk_27 - attribute \src "ls180.v:2479.6-2479.18" - wire \sdrio_clk_28 - attribute \src "ls180.v:2483.6-2483.18" - wire \sdrio_clk_29 - attribute \src "ls180.v:2427.6-2427.17" - wire \sdrio_clk_3 - attribute \src "ls180.v:2487.6-2487.18" - wire \sdrio_clk_30 - attribute \src "ls180.v:2491.6-2491.18" - wire \sdrio_clk_31 - attribute \src "ls180.v:2495.6-2495.18" - wire \sdrio_clk_32 - attribute \src "ls180.v:2499.6-2499.18" - wire \sdrio_clk_33 - attribute \src "ls180.v:2503.6-2503.18" - wire \sdrio_clk_34 - attribute \src "ls180.v:2507.6-2507.18" - wire \sdrio_clk_35 - attribute \src "ls180.v:2512.6-2512.18" - wire \sdrio_clk_36 - attribute \src "ls180.v:2516.6-2516.18" - wire \sdrio_clk_37 - attribute \src "ls180.v:2520.6-2520.18" - wire \sdrio_clk_38 - attribute \src "ls180.v:2524.6-2524.18" - wire \sdrio_clk_39 - attribute \src "ls180.v:2428.6-2428.17" - wire \sdrio_clk_4 - attribute \src "ls180.v:2528.6-2528.18" - wire \sdrio_clk_40 - attribute \src "ls180.v:2532.6-2532.18" - wire \sdrio_clk_41 - attribute \src "ls180.v:2533.6-2533.18" - wire \sdrio_clk_42 - attribute \src "ls180.v:2534.6-2534.18" - wire \sdrio_clk_43 - attribute \src "ls180.v:2535.6-2535.18" - wire \sdrio_clk_44 - attribute \src "ls180.v:2536.6-2536.18" - wire \sdrio_clk_45 - attribute \src "ls180.v:2537.6-2537.18" - wire \sdrio_clk_46 - attribute \src "ls180.v:2538.6-2538.18" - wire \sdrio_clk_47 - attribute \src "ls180.v:2539.6-2539.18" - wire \sdrio_clk_48 - attribute \src "ls180.v:2540.6-2540.18" - wire \sdrio_clk_49 - attribute \src "ls180.v:2429.6-2429.17" - wire \sdrio_clk_5 - attribute \src "ls180.v:2541.6-2541.18" - wire \sdrio_clk_50 - attribute \src "ls180.v:2542.6-2542.18" - wire \sdrio_clk_51 - attribute \src "ls180.v:2543.6-2543.18" - wire \sdrio_clk_52 - attribute \src "ls180.v:2544.6-2544.18" - wire \sdrio_clk_53 - attribute \src "ls180.v:2545.6-2545.18" - wire \sdrio_clk_54 - attribute \src "ls180.v:2546.6-2546.18" - wire \sdrio_clk_55 - attribute \src "ls180.v:2547.6-2547.18" - wire \sdrio_clk_56 - attribute \src "ls180.v:2548.6-2548.18" - wire \sdrio_clk_57 - attribute \src "ls180.v:2549.6-2549.18" - wire \sdrio_clk_58 - attribute \src "ls180.v:2550.6-2550.18" - wire \sdrio_clk_59 - attribute \src "ls180.v:2430.6-2430.17" - wire \sdrio_clk_6 - attribute \src "ls180.v:2551.6-2551.18" - wire \sdrio_clk_60 - attribute \src "ls180.v:2552.6-2552.18" - wire \sdrio_clk_61 - attribute \src "ls180.v:2553.6-2553.18" - wire \sdrio_clk_62 - attribute \src "ls180.v:2554.6-2554.18" - wire \sdrio_clk_63 - attribute \src "ls180.v:2555.6-2555.18" - wire \sdrio_clk_64 - attribute \src "ls180.v:2556.6-2556.18" - wire \sdrio_clk_65 - attribute \src "ls180.v:2557.6-2557.18" - wire \sdrio_clk_66 - attribute \src "ls180.v:2558.6-2558.18" - wire \sdrio_clk_67 - attribute \src "ls180.v:2559.6-2559.18" - wire \sdrio_clk_68 - attribute \src "ls180.v:2560.6-2560.18" - wire \sdrio_clk_69 - attribute \src "ls180.v:2431.6-2431.17" - wire \sdrio_clk_7 - attribute \src "ls180.v:2561.6-2561.18" - wire \sdrio_clk_70 - attribute \src "ls180.v:2562.6-2562.18" - wire \sdrio_clk_71 - attribute \src "ls180.v:2563.6-2563.18" - wire \sdrio_clk_72 - attribute \src "ls180.v:2564.6-2564.18" - wire \sdrio_clk_73 - attribute \src "ls180.v:2565.6-2565.18" - wire \sdrio_clk_74 - attribute \src "ls180.v:2566.6-2566.18" - wire \sdrio_clk_75 - attribute \src "ls180.v:2567.6-2567.18" - wire \sdrio_clk_76 - attribute \src "ls180.v:2568.6-2568.18" - wire \sdrio_clk_77 - attribute \src "ls180.v:2569.6-2569.18" - wire \sdrio_clk_78 - attribute \src "ls180.v:2570.6-2570.18" - wire \sdrio_clk_79 - attribute \src "ls180.v:2432.6-2432.17" - wire \sdrio_clk_8 - attribute \src "ls180.v:2571.6-2571.18" - wire \sdrio_clk_80 - attribute \src "ls180.v:2572.6-2572.18" - wire \sdrio_clk_81 - attribute \src "ls180.v:2573.6-2573.18" - wire \sdrio_clk_82 - attribute \src "ls180.v:2574.6-2574.18" - wire \sdrio_clk_83 - attribute \src "ls180.v:2433.6-2433.17" - wire \sdrio_clk_9 - attribute \src "ls180.v:6.13-6.22" - wire input 2 \serial_rx - attribute \src "ls180.v:5.13-5.22" - wire output 1 \serial_tx - attribute \src "ls180.v:19.13-19.27" - wire output 15 \spi_master_clk - attribute \src "ls180.v:21.13-21.28" - wire output 17 \spi_master_cs_n - attribute \src "ls180.v:22.13-22.28" - wire input 18 \spi_master_miso - attribute \src "ls180.v:20.13-20.28" - wire output 16 \spi_master_mosi - attribute \src "ls180.v:27.13-27.26" - wire output 23 \spisdcard_clk - attribute \src "ls180.v:29.13-29.27" - wire output 25 \spisdcard_cs_n - attribute \src "ls180.v:30.13-30.27" - wire input 26 \spisdcard_miso - attribute \src "ls180.v:28.13-28.27" - wire output 24 \spisdcard_mosi - attribute \src "ls180.v:7.13-7.20" - wire input 3 \sys_clk - attribute \src "ls180.v:311.6-311.15" - wire \sys_clk_1 - attribute \src "ls180.v:312.6-312.13" - wire \sys_rst - attribute \src "ls180.v:9366.12-9366.15" - memory width 32 size 128 \mem - attribute \src "ls180.v:9386.11-9386.18" - memory width 10 size 16 \storage - attribute \src "ls180.v:9403.11-9403.20" - memory width 10 size 16 \storage_1 - attribute \src "ls180.v:9420.12-9420.21" - memory width 25 size 8 \storage_2 - attribute \src "ls180.v:9434.12-9434.21" - memory width 25 size 8 \storage_3 - attribute \src "ls180.v:9448.12-9448.21" - memory width 25 size 8 \storage_4 - attribute \src "ls180.v:9462.12-9462.21" - memory width 25 size 8 \storage_5 - attribute \src "ls180.v:9476.11-9476.20" - memory width 10 size 32 \storage_6 - attribute \src "ls180.v:9490.11-9490.20" - memory width 10 size 32 \storage_7 - attribute \src "ls180.v:2636.68-2636.110" - cell $add $add$ls180.v:2636$22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter0_counter - connect \B 1'1 - connect \Y $add$ls180.v:2636$22_Y - end - attribute \src "ls180.v:2696.68-2696.110" - cell $add $add$ls180.v:2696$33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter1_counter - connect \B 1'1 - connect \Y $add$ls180.v:2696$33_Y - end - attribute \src "ls180.v:2794.48-2794.125" - cell $add $add$ls180.v:2794$69 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_libresocsim_uart_tx_fifo_level0 - connect \B \main_libresocsim_uart_tx_fifo_readable - connect \Y $add$ls180.v:2794$69_Y - end - attribute \src "ls180.v:2824.48-2824.125" - cell $add $add$ls180.v:2824$80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_libresocsim_uart_rx_fifo_level0 - connect \B \main_libresocsim_uart_rx_fifo_readable - connect \Y $add$ls180.v:2824$80_Y - end - attribute \src "ls180.v:3949.54-3949.83" - cell $add $add$ls180.v:3949$566 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter_counter - connect \B 1'1 - connect \Y $add$ls180.v:3949$566_Y - end - attribute \src "ls180.v:4014.42-4014.59" - cell $add $add$ls180.v:4014$597 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_count - connect \B 1'1 - connect \Y $add$ls180.v:4014$597_Y - end - attribute \src "ls180.v:4114.59-4114.88" - cell $add $add$ls180.v:4114$625 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \libresocsim_init_count - connect \B 1'1 - connect \Y $add$ls180.v:4114$625_Y - end - attribute \src "ls180.v:4171.59-4171.88" - cell $add $add$ls180.v:4171$628 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \libresocsim_cmdw_count - connect \B 1'1 - connect \Y $add$ls180.v:4171$628_Y - end - attribute \src "ls180.v:4188.59-4188.88" - cell $add $add$ls180.v:4188$630 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \libresocsim_cmdw_count - connect \B 1'1 - connect \Y $add$ls180.v:4188$630_Y - end - attribute \src "ls180.v:4281.60-4281.89" - cell $add $add$ls180.v:4281$647 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \libresocsim_cmdr_count - connect \B 1'1 - connect \Y $add$ls180.v:4281$647_Y - end - attribute \src "ls180.v:4306.60-4306.89" - cell $add $add$ls180.v:4306$650 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \libresocsim_cmdr_count - connect \B 1'1 - connect \Y $add$ls180.v:4306$650_Y - end - attribute \src "ls180.v:4428.54-4428.84" - cell $add $add$ls180.v:4428$667 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \libresocsim_dataw_count - connect \B 1'1 - connect \Y $add$ls180.v:4428$667_Y - end - attribute \src "ls180.v:4539.67-4539.117" - cell $add $add$ls180.v:4539$681 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 10 - connect \A \libresocsim_datar_sink_payload_block_length - connect \B 4'1000 - connect \Y $add$ls180.v:4539$681_Y - end - attribute \src "ls180.v:4544.63-4544.93" - cell $add $add$ls180.v:4544$684 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 10 - connect \A \libresocsim_datar_count - connect \B 1'1 - connect \Y $add$ls180.v:4544$684_Y - end - attribute \src "ls180.v:4570.62-4570.92" - cell $add $add$ls180.v:4570$687 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 10 - connect \A \libresocsim_datar_count - connect \B 1'1 - connect \Y $add$ls180.v:4570$687_Y - end - attribute \src "ls180.v:4774.87-4774.131" - cell $add $add$ls180.v:4774$872 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \libresocsim_sdcore_crc16_inserter_cnt - connect \B 1'1 - connect \Y $add$ls180.v:4774$872_Y - end - attribute \src "ls180.v:4968.61-4968.96" - cell $add $add$ls180.v:4968$947 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \libresocsim_sdcore_cmd_count - connect \B 1'1 - connect \Y $add$ls180.v:4968$947_Y - end - attribute \src "ls180.v:5020.62-5020.98" - cell $add $add$ls180.v:5020$957 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \libresocsim_sdcore_data_count - connect \B 1'1 - connect \Y $add$ls180.v:5020$957_Y - end - attribute \src "ls180.v:5046.64-5046.100" - cell $add $add$ls180.v:5046$965 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \libresocsim_sdcore_data_count - connect \B 1'1 - connect \Y $add$ls180.v:5046$965_Y - end - attribute \src "ls180.v:5167.58-5167.155" - cell $add $add$ls180.v:5167$981 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \libresocsim_sdblock2mem_wishbonedmawriter_base - connect \B \libresocsim_sdblock2mem_wishbonedmawriter_offset - connect \Y $add$ls180.v:5167$981_Y - end - attribute \src "ls180.v:5170.84-5170.139" - cell $add $add$ls180.v:5170$983 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \libresocsim_sdblock2mem_wishbonedmawriter_offset - connect \B 1'1 - connect \Y $add$ls180.v:5170$983_Y - end - attribute \src "ls180.v:5263.57-5263.126" - cell $add $add$ls180.v:5263$992 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \libresocsim_sdmem2block_dma_base - connect \B \libresocsim_sdmem2block_dma_offset - connect \Y $add$ls180.v:5263$992_Y - end - attribute \src "ls180.v:5265.84-5265.125" - cell $add $add$ls180.v:5265$993 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \libresocsim_sdmem2block_dma_offset - connect \B 1'1 - connect \Y $add$ls180.v:5265$993_Y - end - attribute \src "ls180.v:5377.49-5377.73" - cell $add $add$ls180.v:5377$1012 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \libresocsim_count - connect \B 1'1 - connect \Y $add$ls180.v:5377$1012_Y - end - attribute \src "ls180.v:7081.50-7081.98" - cell $add $add$ls180.v:7081$2191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_libresocsim_soccontroller_bus_errors - connect \B 1'1 - connect \Y $add$ls180.v:7081$2191_Y - end - attribute \src "ls180.v:7096.37-7096.72" - cell $add $add$ls180.v:7096$2200 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_libresocsim_tx_bitcount - connect \B 1'1 - connect \Y $add$ls180.v:7096$2200_Y - end - attribute \src "ls180.v:7112.79-7112.143" - cell $add $add$ls180.v:7112$2203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 33 - connect \A \main_libresocsim_phase_accumulator_tx - connect \B \main_libresocsim_storage - connect \Y $add$ls180.v:7112$2203_Y - end - attribute \src "ls180.v:7125.37-7125.72" - cell $add $add$ls180.v:7125$2207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_libresocsim_rx_bitcount - connect \B 1'1 - connect \Y $add$ls180.v:7125$2207_Y - end - attribute \src "ls180.v:7144.79-7144.143" - cell $add $add$ls180.v:7144$2210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 33 - connect \A \main_libresocsim_phase_accumulator_rx - connect \B \main_libresocsim_storage - connect \Y $add$ls180.v:7144$2210_Y - end - attribute \src "ls180.v:7170.45-7170.89" - cell $add $add$ls180.v:7170$2218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_libresocsim_uart_tx_fifo_produce - connect \B 1'1 - connect \Y $add$ls180.v:7170$2218_Y - end - attribute \src "ls180.v:7173.45-7173.89" - cell $add $add$ls180.v:7173$2219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_libresocsim_uart_tx_fifo_consume - connect \B 1'1 - connect \Y $add$ls180.v:7173$2219_Y - end - attribute \src "ls180.v:7177.45-7177.88" - cell $add $add$ls180.v:7177$2224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_libresocsim_uart_tx_fifo_level0 - connect \B 1'1 - connect \Y $add$ls180.v:7177$2224_Y - end - attribute \src "ls180.v:7192.45-7192.89" - cell $add $add$ls180.v:7192$2229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_libresocsim_uart_rx_fifo_produce - connect \B 1'1 - connect \Y $add$ls180.v:7192$2229_Y - end - attribute \src "ls180.v:7195.45-7195.89" - cell $add $add$ls180.v:7195$2230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_libresocsim_uart_rx_fifo_consume - connect \B 1'1 - connect \Y $add$ls180.v:7195$2230_Y - end - attribute \src "ls180.v:7199.45-7199.88" - cell $add $add$ls180.v:7199$2235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_libresocsim_uart_rx_fifo_level0 - connect \B 1'1 - connect \Y $add$ls180.v:7199$2235_Y - end - attribute \src "ls180.v:7298.37-7298.72" - cell $add $add$ls180.v:7298$2254 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_sequencer_counter - connect \B 1'1 - connect \Y $add$ls180.v:7298$2254_Y - end - attribute \src "ls180.v:7315.60-7315.119" - cell $add $add$ls180.v:7315$2258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $add$ls180.v:7315$2258_Y - end - attribute \src "ls180.v:7318.60-7318.119" - cell $add $add$ls180.v:7318$2259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - connect \B 1'1 - connect \Y $add$ls180.v:7318$2259_Y - end - attribute \src "ls180.v:7322.59-7322.116" - cell $add $add$ls180.v:7322$2264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $add$ls180.v:7322$2264_Y - end - attribute \src "ls180.v:7361.60-7361.119" - cell $add $add$ls180.v:7361$2274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $add$ls180.v:7361$2274_Y - end - attribute \src "ls180.v:7364.60-7364.119" - cell $add $add$ls180.v:7364$2275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - connect \B 1'1 - connect \Y $add$ls180.v:7364$2275_Y - end - attribute \src "ls180.v:7368.59-7368.116" - cell $add $add$ls180.v:7368$2280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $add$ls180.v:7368$2280_Y - end - attribute \src "ls180.v:7407.60-7407.119" - cell $add $add$ls180.v:7407$2290 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $add$ls180.v:7407$2290_Y - end - attribute \src "ls180.v:7410.60-7410.119" - cell $add $add$ls180.v:7410$2291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - connect \B 1'1 - connect \Y $add$ls180.v:7410$2291_Y - end - attribute \src "ls180.v:7414.59-7414.116" - cell $add $add$ls180.v:7414$2296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $add$ls180.v:7414$2296_Y - end - attribute \src "ls180.v:7453.60-7453.119" - cell $add $add$ls180.v:7453$2306 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $add$ls180.v:7453$2306_Y - end - attribute \src "ls180.v:7456.60-7456.119" - cell $add $add$ls180.v:7456$2307 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - connect \B 1'1 - connect \Y $add$ls180.v:7456$2307_Y - end - attribute \src "ls180.v:7460.59-7460.116" - cell $add $add$ls180.v:7460$2312 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $add$ls180.v:7460$2312_Y - end - attribute \src "ls180.v:7682.24-7682.48" - cell $add $add$ls180.v:7682$2361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_clk_divider1 - connect \B 1'1 - connect \Y $add$ls180.v:7682$2361_Y - end - attribute \src "ls180.v:7718.32-7718.63" - cell $add $add$ls180.v:7718$2367 - parameter \A_SIGNED 0 - parameter \A_WIDTH 9 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 9 - connect \A \libresocsim_clocker_clks - connect \B 1'1 - connect \Y $add$ls180.v:7718$2367_Y - end - attribute \src "ls180.v:7741.46-7741.90" - cell $add $add$ls180.v:7741$2371 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \libresocsim_cmdr_cmdr_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:7741$2371_Y - end - attribute \src "ls180.v:7787.72-7787.116" - cell $add $add$ls180.v:7787$2377 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \libresocsim_cmdr_cmdr_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:7787$2377_Y - end - attribute \src "ls180.v:7822.47-7822.92" - cell $add $add$ls180.v:7822$2383 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \libresocsim_dataw_crcr_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:7822$2383_Y - end - attribute \src "ls180.v:7868.73-7868.118" - cell $add $add$ls180.v:7868$2389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \libresocsim_dataw_crcr_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:7868$2389_Y - end - attribute \src "ls180.v:7901.48-7901.94" - cell $add $add$ls180.v:7901$2395 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_datar_datar_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:7901$2395_Y - end - attribute \src "ls180.v:7929.74-7929.120" - cell $add $add$ls180.v:7929$2401 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \libresocsim_datar_datar_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:7929$2401_Y - end - attribute \src "ls180.v:8041.46-8041.89" - cell $add $add$ls180.v:8041$2414 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \libresocsim_sdcore_crc16_checker_cnt - connect \B 1'1 - connect \Y $add$ls180.v:8041$2414_Y - end - attribute \src "ls180.v:8102.44-8102.87" - cell $add $add$ls180.v:8102$2418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \libresocsim_sdblock2mem_fifo_produce - connect \B 1'1 - connect \Y $add$ls180.v:8102$2418_Y - end - attribute \src "ls180.v:8105.44-8105.87" - cell $add $add$ls180.v:8105$2419 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \libresocsim_sdblock2mem_fifo_consume - connect \B 1'1 - connect \Y $add$ls180.v:8105$2419_Y - end - attribute \src "ls180.v:8109.43-8109.84" - cell $add $add$ls180.v:8109$2424 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \libresocsim_sdblock2mem_fifo_level - connect \B 1'1 - connect \Y $add$ls180.v:8109$2424_Y - end - attribute \src "ls180.v:8124.48-8124.94" - cell $add $add$ls180.v:8124$2428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \libresocsim_sdblock2mem_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8124$2428_Y - end - attribute \src "ls180.v:8158.74-8158.120" - cell $add $add$ls180.v:8158$2434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \libresocsim_sdblock2mem_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8158$2434_Y - end - attribute \src "ls180.v:8184.46-8184.90" - cell $add $add$ls180.v:8184$2436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \libresocsim_sdmem2block_converter_mux - connect \B 1'1 - connect \Y $add$ls180.v:8184$2436_Y - end - attribute \src "ls180.v:8188.44-8188.87" - cell $add $add$ls180.v:8188$2440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \libresocsim_sdmem2block_fifo_produce - connect \B 1'1 - connect \Y $add$ls180.v:8188$2440_Y - end - attribute \src "ls180.v:8191.44-8191.87" - cell $add $add$ls180.v:8191$2441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \libresocsim_sdmem2block_fifo_consume - connect \B 1'1 - connect \Y $add$ls180.v:8191$2441_Y - end - attribute \src "ls180.v:8195.43-8195.84" - cell $add $add$ls180.v:8195$2446 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \libresocsim_sdmem2block_fifo_level - connect \B 1'1 - connect \Y $add$ls180.v:8195$2446_Y - end - attribute \src "ls180.v:8202.31-8202.62" - cell $add $add$ls180.v:8202$2448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \libresocsim_clk_divider1 - connect \B 1'1 - connect \Y $add$ls180.v:8202$2448_Y - end - attribute \src "ls180.v:2630.9-2630.80" - cell $and $and$ls180.v:2630$17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_ibus_stb - connect \B \main_libresocsim_libresoc_ibus_cyc - connect \Y $and$ls180.v:2630$17_Y - end - attribute \src "ls180.v:2648.9-2648.80" - cell $and $and$ls180.v:2648$24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_ibus_stb - connect \B \main_libresocsim_libresoc_ibus_cyc - connect \Y $and$ls180.v:2648$24_Y - end - attribute \src "ls180.v:2690.9-2690.80" - cell $and $and$ls180.v:2690$28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_dbus_stb - connect \B \main_libresocsim_libresoc_dbus_cyc - connect \Y $and$ls180.v:2690$28_Y - end - attribute \src "ls180.v:2708.9-2708.80" - cell $and $and$ls180.v:2708$35 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_dbus_stb - connect \B \main_libresocsim_libresoc_dbus_cyc - connect \Y $and$ls180.v:2708$35_Y - end - attribute \src "ls180.v:2718.31-2718.90" - cell $and $and$ls180.v:2718$37 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2718$37_Y - end - attribute \src "ls180.v:2718.30-2718.121" - cell $and $and$ls180.v:2718$38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2718$37_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2718$38_Y - end - attribute \src "ls180.v:2718.29-2718.156" - cell $and $and$ls180.v:2718$39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2718$38_Y - connect \B \main_libresocsim_ram_bus_sel [0] - connect \Y $and$ls180.v:2718$39_Y - end - attribute \src "ls180.v:2719.31-2719.90" - cell $and $and$ls180.v:2719$40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2719$40_Y - end - attribute \src "ls180.v:2719.30-2719.121" - cell $and $and$ls180.v:2719$41 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2719$40_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2719$41_Y - end - attribute \src "ls180.v:2719.29-2719.156" - cell $and $and$ls180.v:2719$42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2719$41_Y - connect \B \main_libresocsim_ram_bus_sel [1] - connect \Y $and$ls180.v:2719$42_Y - end - attribute \src "ls180.v:2720.31-2720.90" - cell $and $and$ls180.v:2720$43 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2720$43_Y - end - attribute \src "ls180.v:2720.30-2720.121" - cell $and $and$ls180.v:2720$44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2720$43_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2720$44_Y - end - attribute \src "ls180.v:2720.29-2720.156" - cell $and $and$ls180.v:2720$45 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2720$44_Y - connect \B \main_libresocsim_ram_bus_sel [2] - connect \Y $and$ls180.v:2720$45_Y - end - attribute \src "ls180.v:2721.31-2721.90" - cell $and $and$ls180.v:2721$46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2721$46_Y - end - attribute \src "ls180.v:2721.30-2721.121" - cell $and $and$ls180.v:2721$47 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2721$46_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2721$47_Y - end - attribute \src "ls180.v:2721.29-2721.156" - cell $and $and$ls180.v:2721$48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2721$47_Y - connect \B \main_libresocsim_ram_bus_sel [3] - connect \Y $and$ls180.v:2721$48_Y - end - attribute \src "ls180.v:2754.88-2754.124" - cell $and $and$ls180.v:2754$54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B \main_libresocsim_uart_rxtx_we - connect \Y $and$ls180.v:2754$54_Y - end - attribute \src "ls180.v:2758.7-2758.102" - cell $and $and$ls180.v:2758$58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_eventmanager_pending_re - connect \B \main_libresocsim_uart_eventmanager_pending_r [0] - connect \Y $and$ls180.v:2758$58_Y - end - attribute \src "ls180.v:2769.7-2769.102" - cell $and $and$ls180.v:2769$61 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_eventmanager_pending_re - connect \B \main_libresocsim_uart_eventmanager_pending_r [1] - connect \Y $and$ls180.v:2769$61_Y - end - attribute \src "ls180.v:2778.38-2778.133" - cell $and $and$ls180.v:2778$63 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_eventmanager_pending_w [0] - connect \B \main_libresocsim_uart_eventmanager_storage [0] - connect \Y $and$ls180.v:2778$63_Y - end - attribute \src "ls180.v:2778.138-2778.233" - cell $and $and$ls180.v:2778$64 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_eventmanager_pending_w [1] - connect \B \main_libresocsim_uart_eventmanager_storage [1] - connect \Y $and$ls180.v:2778$64_Y - end - attribute \src "ls180.v:2793.53-2793.181" - cell $and $and$ls180.v:2793$68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_tx_fifo_syncfifo_readable - connect \B $or$ls180.v:2793$67_Y - connect \Y $and$ls180.v:2793$68_Y - end - attribute \src "ls180.v:2804.51-2804.184" - cell $and $and$ls180.v:2804$73 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_tx_fifo_syncfifo_we - connect \B $or$ls180.v:2804$72_Y - connect \Y $and$ls180.v:2804$73_Y - end - attribute \src "ls180.v:2805.49-2805.140" - cell $and $and$ls180.v:2805$74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_tx_fifo_syncfifo_readable - connect \B \main_libresocsim_uart_tx_fifo_syncfifo_re - connect \Y $and$ls180.v:2805$74_Y - end - attribute \src "ls180.v:2823.53-2823.181" - cell $and $and$ls180.v:2823$79 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_rx_fifo_syncfifo_readable - connect \B $or$ls180.v:2823$78_Y - connect \Y $and$ls180.v:2823$79_Y - end - attribute \src "ls180.v:2834.51-2834.184" - cell $and $and$ls180.v:2834$84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_rx_fifo_syncfifo_we - connect \B $or$ls180.v:2834$83_Y - connect \Y $and$ls180.v:2834$84_Y - end - attribute \src "ls180.v:2835.49-2835.140" - cell $and $and$ls180.v:2835$85 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_rx_fifo_syncfifo_readable - connect \B \main_libresocsim_uart_rx_fifo_syncfifo_re - connect \Y $and$ls180.v:2835$85_Y - end - attribute \src "ls180.v:2845.7-2845.101" - cell $and $and$ls180.v:2845$90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_timer_eventmanager_pending_re - connect \B \main_libresocsim_timer_eventmanager_pending_r - connect \Y $and$ls180.v:2845$90_Y - end - attribute \src "ls180.v:2850.38-2850.129" - cell $and $and$ls180.v:2850$91 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_timer_eventmanager_pending_w - connect \B \main_libresocsim_timer_eventmanager_storage - connect \Y $and$ls180.v:2850$91_Y - end - attribute \src "ls180.v:2969.40-2969.99" - cell $and $and$ls180.v:2969$99 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_issue_re - connect \B \main_sdram_command_storage [4] - connect \Y $and$ls180.v:2969$99_Y - end - attribute \src "ls180.v:2970.40-2970.99" - cell $and $and$ls180.v:2970$100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_issue_re - connect \B \main_sdram_command_storage [5] - connect \Y $and$ls180.v:2970$100_Y - end - attribute \src "ls180.v:3008.38-3008.103" - cell $and $and$ls180.v:3008$106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_done1 - connect \B $eq$ls180.v:3008$105_Y - connect \Y $and$ls180.v:3008$106_Y - end - attribute \src "ls180.v:3062.50-3062.119" - cell $and $and$ls180.v:3062$114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3062$114_Y - end - attribute \src "ls180.v:3062.49-3062.167" - cell $and $and$ls180.v:3062$115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3062$114_Y - connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3062$115_Y - end - attribute \src "ls180.v:3063.49-3063.118" - cell $and $and$ls180.v:3063$116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3063$116_Y - end - attribute \src "ls180.v:3063.48-3063.154" - cell $and $and$ls180.v:3063$117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3063$116_Y - connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3063$117_Y - end - attribute \src "ls180.v:3064.50-3064.119" - cell $and $and$ls180.v:3064$118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3064$118_Y - end - attribute \src "ls180.v:3064.49-3064.155" - cell $and $and$ls180.v:3064$119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3064$118_Y - connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3064$119_Y - end - attribute \src "ls180.v:3067.7-3067.114" - cell $and $and$ls180.v:3067$121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $and$ls180.v:3067$121_Y - end - attribute \src "ls180.v:3096.66-3096.246" - cell $and $and$ls180.v:3096$127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B $or$ls180.v:3096$126_Y - connect \Y $and$ls180.v:3096$127_Y - end - attribute \src "ls180.v:3097.64-3097.187" - cell $and $and$ls180.v:3097$128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - connect \Y $and$ls180.v:3097$128_Y - end - attribute \src "ls180.v:3121.9-3121.86" - cell $and $and$ls180.v:3121$134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3121$134_Y - end - attribute \src "ls180.v:3133.9-3133.86" - cell $and $and$ls180.v:3133$135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3133$135_Y - end - attribute \src "ls180.v:3183.13-3183.87" - cell $and $and$ls180.v:3183$137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_ready - connect \B \main_sdram_bankmachine0_auto_precharge - connect \Y $and$ls180.v:3183$137_Y - end - attribute \src "ls180.v:3219.50-3219.119" - cell $and $and$ls180.v:3219$144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3219$144_Y - end - attribute \src "ls180.v:3219.49-3219.167" - cell $and $and$ls180.v:3219$145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3219$144_Y - connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3219$145_Y - end - attribute \src "ls180.v:3220.49-3220.118" - cell $and $and$ls180.v:3220$146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3220$146_Y - end - attribute \src "ls180.v:3220.48-3220.154" - cell $and $and$ls180.v:3220$147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3220$146_Y - connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3220$147_Y - end - attribute \src "ls180.v:3221.50-3221.119" - cell $and $and$ls180.v:3221$148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3221$148_Y - end - attribute \src "ls180.v:3221.49-3221.155" - cell $and $and$ls180.v:3221$149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3221$148_Y - connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3221$149_Y - end - attribute \src "ls180.v:3224.7-3224.114" - cell $and $and$ls180.v:3224$151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $and$ls180.v:3224$151_Y - end - attribute \src "ls180.v:3253.66-3253.246" - cell $and $and$ls180.v:3253$157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B $or$ls180.v:3253$156_Y - connect \Y $and$ls180.v:3253$157_Y - end - attribute \src "ls180.v:3254.64-3254.187" - cell $and $and$ls180.v:3254$158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - connect \Y $and$ls180.v:3254$158_Y - end - attribute \src "ls180.v:3278.9-3278.86" - cell $and $and$ls180.v:3278$164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3278$164_Y - end - attribute \src "ls180.v:3290.9-3290.86" - cell $and $and$ls180.v:3290$165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3290$165_Y - end - attribute \src "ls180.v:3340.13-3340.87" - cell $and $and$ls180.v:3340$167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_ready - connect \B \main_sdram_bankmachine1_auto_precharge - connect \Y $and$ls180.v:3340$167_Y - end - attribute \src "ls180.v:3376.50-3376.119" - cell $and $and$ls180.v:3376$174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3376$174_Y - end - attribute \src "ls180.v:3376.49-3376.167" - cell $and $and$ls180.v:3376$175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3376$174_Y - connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3376$175_Y - end - attribute \src "ls180.v:3377.49-3377.118" - cell $and $and$ls180.v:3377$176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3377$176_Y - end - attribute \src "ls180.v:3377.48-3377.154" - cell $and $and$ls180.v:3377$177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3377$176_Y - connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3377$177_Y - end - attribute \src "ls180.v:3378.50-3378.119" - cell $and $and$ls180.v:3378$178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3378$178_Y - end - attribute \src "ls180.v:3378.49-3378.155" - cell $and $and$ls180.v:3378$179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3378$178_Y - connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3378$179_Y - end - attribute \src "ls180.v:3381.7-3381.114" - cell $and $and$ls180.v:3381$181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $and$ls180.v:3381$181_Y - end - attribute \src "ls180.v:3410.66-3410.246" - cell $and $and$ls180.v:3410$187 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B $or$ls180.v:3410$186_Y - connect \Y $and$ls180.v:3410$187_Y - end - attribute \src "ls180.v:3411.64-3411.187" - cell $and $and$ls180.v:3411$188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - connect \Y $and$ls180.v:3411$188_Y - end - attribute \src "ls180.v:3435.9-3435.86" - cell $and $and$ls180.v:3435$194 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3435$194_Y - end - attribute \src "ls180.v:3447.9-3447.86" - cell $and $and$ls180.v:3447$195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3447$195_Y - end - attribute \src "ls180.v:3497.13-3497.87" - cell $and $and$ls180.v:3497$197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_ready - connect \B \main_sdram_bankmachine2_auto_precharge - connect \Y $and$ls180.v:3497$197_Y - end - attribute \src "ls180.v:3533.50-3533.119" - cell $and $and$ls180.v:3533$204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3533$204_Y - end - attribute \src "ls180.v:3533.49-3533.167" - cell $and $and$ls180.v:3533$205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3533$204_Y - connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3533$205_Y - end - attribute \src "ls180.v:3534.49-3534.118" - cell $and $and$ls180.v:3534$206 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3534$206_Y - end - attribute \src "ls180.v:3534.48-3534.154" - cell $and $and$ls180.v:3534$207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3534$206_Y - connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3534$207_Y - end - attribute \src "ls180.v:3535.50-3535.119" - cell $and $and$ls180.v:3535$208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3535$208_Y - end - attribute \src "ls180.v:3535.49-3535.155" - cell $and $and$ls180.v:3535$209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3535$208_Y - connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3535$209_Y - end - attribute \src "ls180.v:3538.7-3538.114" - cell $and $and$ls180.v:3538$211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $and$ls180.v:3538$211_Y - end - attribute \src "ls180.v:3567.66-3567.246" - cell $and $and$ls180.v:3567$217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B $or$ls180.v:3567$216_Y - connect \Y $and$ls180.v:3567$217_Y - end - attribute \src "ls180.v:3568.64-3568.187" - cell $and $and$ls180.v:3568$218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - connect \Y $and$ls180.v:3568$218_Y - end - attribute \src "ls180.v:3592.9-3592.86" - cell $and $and$ls180.v:3592$224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3592$224_Y - end - attribute \src "ls180.v:3604.9-3604.86" - cell $and $and$ls180.v:3604$225 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3604$225_Y - end - attribute \src "ls180.v:3654.13-3654.87" - cell $and $and$ls180.v:3654$227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_ready - connect \B \main_sdram_bankmachine3_auto_precharge - connect \Y $and$ls180.v:3654$227_Y - end - attribute \src "ls180.v:3669.37-3669.102" - cell $and $and$ls180.v:3669$228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3669$228_Y - end - attribute \src "ls180.v:3669.108-3669.188" - cell $and $and$ls180.v:3669$230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3669$229_Y - connect \Y $and$ls180.v:3669$230_Y - end - attribute \src "ls180.v:3669.107-3669.231" - cell $and $and$ls180.v:3669$232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3669$230_Y - connect \B $not$ls180.v:3669$231_Y - connect \Y $and$ls180.v:3669$232_Y - end - attribute \src "ls180.v:3669.36-3669.232" - cell $and $and$ls180.v:3669$233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3669$228_Y - connect \B $and$ls180.v:3669$232_Y - connect \Y $and$ls180.v:3669$233_Y - end - attribute \src "ls180.v:3670.37-3670.102" - cell $and $and$ls180.v:3670$234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3670$234_Y - end - attribute \src "ls180.v:3670.108-3670.188" - cell $and $and$ls180.v:3670$236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3670$235_Y - connect \Y $and$ls180.v:3670$236_Y - end - attribute \src "ls180.v:3670.107-3670.231" - cell $and $and$ls180.v:3670$238 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3670$236_Y - connect \B $not$ls180.v:3670$237_Y - connect \Y $and$ls180.v:3670$238_Y - end - attribute \src "ls180.v:3670.36-3670.232" - cell $and $and$ls180.v:3670$239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3670$234_Y - connect \B $and$ls180.v:3670$238_Y - connect \Y $and$ls180.v:3670$239_Y - end - attribute \src "ls180.v:3671.34-3671.85" - cell $and $and$ls180.v:3671$240 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_trrdcon_ready - connect \B \main_sdram_tfawcon_ready - connect \Y $and$ls180.v:3671$240_Y - end - attribute \src "ls180.v:3672.37-3672.102" - cell $and $and$ls180.v:3672$241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3672$241_Y - end - attribute \src "ls180.v:3672.36-3672.194" - cell $and $and$ls180.v:3672$243 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3672$241_Y - connect \B $or$ls180.v:3672$242_Y - connect \Y $and$ls180.v:3672$243_Y - end - attribute \src "ls180.v:3674.37-3674.102" - cell $and $and$ls180.v:3674$244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3674$244_Y - end - attribute \src "ls180.v:3674.36-3674.148" - cell $and $and$ls180.v:3674$245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3674$244_Y - connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:3674$245_Y - end - attribute \src "ls180.v:3675.40-3675.119" - cell $and $and$ls180.v:3675$246 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_payload_is_read - connect \Y $and$ls180.v:3675$246_Y - end - attribute \src "ls180.v:3675.124-3675.203" - cell $and $and$ls180.v:3675$247 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_payload_is_read - connect \Y $and$ls180.v:3675$247_Y - end - attribute \src "ls180.v:3675.209-3675.288" - cell $and $and$ls180.v:3675$249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_payload_is_read - connect \Y $and$ls180.v:3675$249_Y - end - attribute \src "ls180.v:3675.294-3675.373" - cell $and $and$ls180.v:3675$251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_payload_is_read - connect \Y $and$ls180.v:3675$251_Y - end - attribute \src "ls180.v:3676.41-3676.121" - cell $and $and$ls180.v:3676$253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3676$253_Y - end - attribute \src "ls180.v:3676.126-3676.206" - cell $and $and$ls180.v:3676$254 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3676$254_Y - end - attribute \src "ls180.v:3676.212-3676.292" - cell $and $and$ls180.v:3676$256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3676$256_Y - end - attribute \src "ls180.v:3676.298-3676.378" - cell $and $and$ls180.v:3676$258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3676$258_Y - end - attribute \src "ls180.v:3683.38-3683.111" - cell $and $and$ls180.v:3683$262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_refresh_gnt - connect \B \main_sdram_bankmachine1_refresh_gnt - connect \Y $and$ls180.v:3683$262_Y - end - attribute \src "ls180.v:3683.37-3683.150" - cell $and $and$ls180.v:3683$263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3683$262_Y - connect \B \main_sdram_bankmachine2_refresh_gnt - connect \Y $and$ls180.v:3683$263_Y - end - attribute \src "ls180.v:3683.36-3683.189" - cell $and $and$ls180.v:3683$264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3683$263_Y - connect \B \main_sdram_bankmachine3_refresh_gnt - connect \Y $and$ls180.v:3683$264_Y - end - attribute \src "ls180.v:3689.77-3689.153" - cell $and $and$ls180.v:3689$267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3689$267_Y - end - attribute \src "ls180.v:3689.162-3689.246" - cell $and $and$ls180.v:3689$269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:3689$268_Y - connect \Y $and$ls180.v:3689$269_Y - end - attribute \src "ls180.v:3689.161-3689.291" - cell $and $and$ls180.v:3689$271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3689$269_Y - connect \B $not$ls180.v:3689$270_Y - connect \Y $and$ls180.v:3689$271_Y - end - attribute \src "ls180.v:3689.76-3689.333" - cell $and $and$ls180.v:3689$274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3689$267_Y - connect \B $or$ls180.v:3689$273_Y - connect \Y $and$ls180.v:3689$274_Y - end - attribute \src "ls180.v:3689.338-3689.505" - cell $and $and$ls180.v:3689$277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3689$275_Y - connect \B $eq$ls180.v:3689$276_Y - connect \Y $and$ls180.v:3689$277_Y - end - attribute \src "ls180.v:3689.38-3689.507" - cell $and $and$ls180.v:3689$279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:3689$278_Y - connect \Y $and$ls180.v:3689$279_Y - end - attribute \src "ls180.v:3690.77-3690.153" - cell $and $and$ls180.v:3690$280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3690$280_Y - end - attribute \src "ls180.v:3690.162-3690.246" - cell $and $and$ls180.v:3690$282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:3690$281_Y - connect \Y $and$ls180.v:3690$282_Y - end - attribute \src "ls180.v:3690.161-3690.291" - cell $and $and$ls180.v:3690$284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3690$282_Y - connect \B $not$ls180.v:3690$283_Y - connect \Y $and$ls180.v:3690$284_Y - end - attribute \src "ls180.v:3690.76-3690.333" - cell $and $and$ls180.v:3690$287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3690$280_Y - connect \B $or$ls180.v:3690$286_Y - connect \Y $and$ls180.v:3690$287_Y - end - attribute \src "ls180.v:3690.338-3690.505" - cell $and $and$ls180.v:3690$290 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3690$288_Y - connect \B $eq$ls180.v:3690$289_Y - connect \Y $and$ls180.v:3690$290_Y - end - attribute \src "ls180.v:3690.38-3690.507" - cell $and $and$ls180.v:3690$292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:3690$291_Y - connect \Y $and$ls180.v:3690$292_Y - end - attribute \src "ls180.v:3691.77-3691.153" - cell $and $and$ls180.v:3691$293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3691$293_Y - end - attribute \src "ls180.v:3691.162-3691.246" - cell $and $and$ls180.v:3691$295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:3691$294_Y - connect \Y $and$ls180.v:3691$295_Y - end - attribute \src "ls180.v:3691.161-3691.291" - cell $and $and$ls180.v:3691$297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3691$295_Y - connect \B $not$ls180.v:3691$296_Y - connect \Y $and$ls180.v:3691$297_Y - end - attribute \src "ls180.v:3691.76-3691.333" - cell $and $and$ls180.v:3691$300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3691$293_Y - connect \B $or$ls180.v:3691$299_Y - connect \Y $and$ls180.v:3691$300_Y - end - attribute \src "ls180.v:3691.338-3691.505" - cell $and $and$ls180.v:3691$303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3691$301_Y - connect \B $eq$ls180.v:3691$302_Y - connect \Y $and$ls180.v:3691$303_Y - end - attribute \src "ls180.v:3691.38-3691.507" - cell $and $and$ls180.v:3691$305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:3691$304_Y - connect \Y $and$ls180.v:3691$305_Y - end - attribute \src "ls180.v:3692.77-3692.153" - cell $and $and$ls180.v:3692$306 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3692$306_Y - end - attribute \src "ls180.v:3692.162-3692.246" - cell $and $and$ls180.v:3692$308 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:3692$307_Y - connect \Y $and$ls180.v:3692$308_Y - end - attribute \src "ls180.v:3692.161-3692.291" - cell $and $and$ls180.v:3692$310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3692$308_Y - connect \B $not$ls180.v:3692$309_Y - connect \Y $and$ls180.v:3692$310_Y - end - attribute \src "ls180.v:3692.76-3692.333" - cell $and $and$ls180.v:3692$313 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3692$306_Y - connect \B $or$ls180.v:3692$312_Y - connect \Y $and$ls180.v:3692$313_Y - end - attribute \src "ls180.v:3692.338-3692.505" - cell $and $and$ls180.v:3692$316 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3692$314_Y - connect \B $eq$ls180.v:3692$315_Y - connect \Y $and$ls180.v:3692$316_Y - end - attribute \src "ls180.v:3692.38-3692.507" - cell $and $and$ls180.v:3692$318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:3692$317_Y - connect \Y $and$ls180.v:3692$318_Y - end - attribute \src "ls180.v:3722.77-3722.153" - cell $and $and$ls180.v:3722$325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd - connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3722$325_Y - end - attribute \src "ls180.v:3722.162-3722.246" - cell $and $and$ls180.v:3722$327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:3722$326_Y - connect \Y $and$ls180.v:3722$327_Y - end - attribute \src "ls180.v:3722.161-3722.291" - cell $and $and$ls180.v:3722$329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3722$327_Y - connect \B $not$ls180.v:3722$328_Y - connect \Y $and$ls180.v:3722$329_Y - end - attribute \src "ls180.v:3722.76-3722.333" - cell $and $and$ls180.v:3722$332 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3722$325_Y - connect \B $or$ls180.v:3722$331_Y - connect \Y $and$ls180.v:3722$332_Y - end - attribute \src "ls180.v:3722.338-3722.505" - cell $and $and$ls180.v:3722$335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3722$333_Y - connect \B $eq$ls180.v:3722$334_Y - connect \Y $and$ls180.v:3722$335_Y - end - attribute \src "ls180.v:3722.38-3722.507" - cell $and $and$ls180.v:3722$337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:3722$336_Y - connect \Y $and$ls180.v:3722$337_Y - end - attribute \src "ls180.v:3723.77-3723.153" - cell $and $and$ls180.v:3723$338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd - connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3723$338_Y - end - attribute \src "ls180.v:3723.162-3723.246" - cell $and $and$ls180.v:3723$340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:3723$339_Y - connect \Y $and$ls180.v:3723$340_Y - end - attribute \src "ls180.v:3723.161-3723.291" - cell $and $and$ls180.v:3723$342 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3723$340_Y - connect \B $not$ls180.v:3723$341_Y - connect \Y $and$ls180.v:3723$342_Y - end - attribute \src "ls180.v:3723.76-3723.333" - cell $and $and$ls180.v:3723$345 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3723$338_Y - connect \B $or$ls180.v:3723$344_Y - connect \Y $and$ls180.v:3723$345_Y - end - attribute \src "ls180.v:3723.338-3723.505" - cell $and $and$ls180.v:3723$348 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3723$346_Y - connect \B $eq$ls180.v:3723$347_Y - connect \Y $and$ls180.v:3723$348_Y - end - attribute \src "ls180.v:3723.38-3723.507" - cell $and $and$ls180.v:3723$350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:3723$349_Y - connect \Y $and$ls180.v:3723$350_Y - end - attribute \src "ls180.v:3724.77-3724.153" - cell $and $and$ls180.v:3724$351 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd - connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3724$351_Y - end - attribute \src "ls180.v:3724.162-3724.246" - cell $and $and$ls180.v:3724$353 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:3724$352_Y - connect \Y $and$ls180.v:3724$353_Y - end - attribute \src "ls180.v:3724.161-3724.291" - cell $and $and$ls180.v:3724$355 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3724$353_Y - connect \B $not$ls180.v:3724$354_Y - connect \Y $and$ls180.v:3724$355_Y - end - attribute \src "ls180.v:3724.76-3724.333" - cell $and $and$ls180.v:3724$358 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3724$351_Y - connect \B $or$ls180.v:3724$357_Y - connect \Y $and$ls180.v:3724$358_Y - end - attribute \src "ls180.v:3724.338-3724.505" - cell $and $and$ls180.v:3724$361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3724$359_Y - connect \B $eq$ls180.v:3724$360_Y - connect \Y $and$ls180.v:3724$361_Y - end - attribute \src "ls180.v:3724.38-3724.507" - cell $and $and$ls180.v:3724$363 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:3724$362_Y - connect \Y $and$ls180.v:3724$363_Y - end - attribute \src "ls180.v:3725.77-3725.153" - cell $and $and$ls180.v:3725$364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd - connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3725$364_Y - end - attribute \src "ls180.v:3725.162-3725.246" - cell $and $and$ls180.v:3725$366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:3725$365_Y - connect \Y $and$ls180.v:3725$366_Y - end - attribute \src "ls180.v:3725.161-3725.291" - cell $and $and$ls180.v:3725$368 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3725$366_Y - connect \B $not$ls180.v:3725$367_Y - connect \Y $and$ls180.v:3725$368_Y - end - attribute \src "ls180.v:3725.76-3725.333" - cell $and $and$ls180.v:3725$371 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3725$364_Y - connect \B $or$ls180.v:3725$370_Y - connect \Y $and$ls180.v:3725$371_Y - end - attribute \src "ls180.v:3725.338-3725.505" - cell $and $and$ls180.v:3725$374 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3725$372_Y - connect \B $eq$ls180.v:3725$373_Y - connect \Y $and$ls180.v:3725$374_Y - end - attribute \src "ls180.v:3725.38-3725.507" - cell $and $and$ls180.v:3725$376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:3725$375_Y - connect \Y $and$ls180.v:3725$376_Y - end - attribute \src "ls180.v:3754.8-3754.73" - cell $and $and$ls180.v:3754$381 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3754$381_Y - end - attribute \src "ls180.v:3754.7-3754.114" - cell $and $and$ls180.v:3754$383 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3754$381_Y - connect \B $eq$ls180.v:3754$382_Y - connect \Y $and$ls180.v:3754$383_Y - end - attribute \src "ls180.v:3757.8-3757.73" - cell $and $and$ls180.v:3757$384 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3757$384_Y - end - attribute \src "ls180.v:3757.7-3757.114" - cell $and $and$ls180.v:3757$386 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3757$384_Y - connect \B $eq$ls180.v:3757$385_Y - connect \Y $and$ls180.v:3757$386_Y - end - attribute \src "ls180.v:3763.8-3763.73" - cell $and $and$ls180.v:3763$388 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3763$388_Y - end - attribute \src "ls180.v:3763.7-3763.114" - cell $and $and$ls180.v:3763$390 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3763$388_Y - connect \B $eq$ls180.v:3763$389_Y - connect \Y $and$ls180.v:3763$390_Y - end - attribute \src "ls180.v:3766.8-3766.73" - cell $and $and$ls180.v:3766$391 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3766$391_Y - end - attribute \src "ls180.v:3766.7-3766.114" - cell $and $and$ls180.v:3766$393 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3766$391_Y - connect \B $eq$ls180.v:3766$392_Y - connect \Y $and$ls180.v:3766$393_Y - end - attribute \src "ls180.v:3772.8-3772.73" - cell $and $and$ls180.v:3772$395 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3772$395_Y - end - attribute \src "ls180.v:3772.7-3772.114" - cell $and $and$ls180.v:3772$397 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3772$395_Y - connect \B $eq$ls180.v:3772$396_Y - connect \Y $and$ls180.v:3772$397_Y - end - attribute \src "ls180.v:3775.8-3775.73" - cell $and $and$ls180.v:3775$398 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3775$398_Y - end - attribute \src "ls180.v:3775.7-3775.114" - cell $and $and$ls180.v:3775$400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3775$398_Y - connect \B $eq$ls180.v:3775$399_Y - connect \Y $and$ls180.v:3775$400_Y - end - attribute \src "ls180.v:3781.8-3781.73" - cell $and $and$ls180.v:3781$402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3781$402_Y - end - attribute \src "ls180.v:3781.7-3781.114" - cell $and $and$ls180.v:3781$404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3781$402_Y - connect \B $eq$ls180.v:3781$403_Y - connect \Y $and$ls180.v:3781$404_Y - end - attribute \src "ls180.v:3784.8-3784.73" - cell $and $and$ls180.v:3784$405 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3784$405_Y - end - attribute \src "ls180.v:3784.7-3784.114" - cell $and $and$ls180.v:3784$407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3784$405_Y - connect \B $eq$ls180.v:3784$406_Y - connect \Y $and$ls180.v:3784$407_Y - end - attribute \src "ls180.v:3809.71-3809.151" - cell $and $and$ls180.v:3809$412 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3809$411_Y - connect \Y $and$ls180.v:3809$412_Y - end - attribute \src "ls180.v:3809.70-3809.194" - cell $and $and$ls180.v:3809$414 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3809$412_Y - connect \B $not$ls180.v:3809$413_Y - connect \Y $and$ls180.v:3809$414_Y - end - attribute \src "ls180.v:3809.41-3809.222" - cell $and $and$ls180.v:3809$417 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:3809$416_Y - connect \Y $and$ls180.v:3809$417_Y - end - attribute \src "ls180.v:3847.71-3847.151" - cell $and $and$ls180.v:3847$421 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3847$420_Y - connect \Y $and$ls180.v:3847$421_Y - end - attribute \src "ls180.v:3847.70-3847.194" - cell $and $and$ls180.v:3847$423 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3847$421_Y - connect \B $not$ls180.v:3847$422_Y - connect \Y $and$ls180.v:3847$423_Y - end - attribute \src "ls180.v:3847.41-3847.222" - cell $and $and$ls180.v:3847$426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:3847$425_Y - connect \Y $and$ls180.v:3847$426_Y - end - attribute \src "ls180.v:3865.110-3865.179" - cell $and $and$ls180.v:3865$431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3865$430_Y - connect \Y $and$ls180.v:3865$431_Y - end - attribute \src "ls180.v:3865.185-3865.254" - cell $and $and$ls180.v:3865$434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3865$433_Y - connect \Y $and$ls180.v:3865$434_Y - end - attribute \src "ls180.v:3865.260-3865.329" - cell $and $and$ls180.v:3865$437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3865$436_Y - connect \Y $and$ls180.v:3865$437_Y - end - attribute \src "ls180.v:3865.41-3865.332" - cell $and $and$ls180.v:3865$440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3865$429_Y - connect \B $not$ls180.v:3865$439_Y - connect \Y $and$ls180.v:3865$440_Y - end - attribute \src "ls180.v:3865.40-3865.355" - cell $and $and$ls180.v:3865$441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3865$440_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:3865$441_Y - end - attribute \src "ls180.v:3866.34-3866.106" - cell $and $and$ls180.v:3866$444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3866$442_Y - connect \B $not$ls180.v:3866$443_Y - connect \Y $and$ls180.v:3866$444_Y - end - attribute \src "ls180.v:3870.110-3870.179" - cell $and $and$ls180.v:3870$447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3870$446_Y - connect \Y $and$ls180.v:3870$447_Y - end - attribute \src "ls180.v:3870.185-3870.254" - cell $and $and$ls180.v:3870$450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3870$449_Y - connect \Y $and$ls180.v:3870$450_Y - end - attribute \src "ls180.v:3870.260-3870.329" - cell $and $and$ls180.v:3870$453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3870$452_Y - connect \Y $and$ls180.v:3870$453_Y - end - attribute \src "ls180.v:3870.41-3870.332" - cell $and $and$ls180.v:3870$456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3870$445_Y - connect \B $not$ls180.v:3870$455_Y - connect \Y $and$ls180.v:3870$456_Y - end - attribute \src "ls180.v:3870.40-3870.355" - cell $and $and$ls180.v:3870$457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3870$456_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:3870$457_Y - end - attribute \src "ls180.v:3871.34-3871.106" - cell $and $and$ls180.v:3871$460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3871$458_Y - connect \B $not$ls180.v:3871$459_Y - connect \Y $and$ls180.v:3871$460_Y - end - attribute \src "ls180.v:3875.110-3875.179" - cell $and $and$ls180.v:3875$463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3875$462_Y - connect \Y $and$ls180.v:3875$463_Y - end - attribute \src "ls180.v:3875.185-3875.254" - cell $and $and$ls180.v:3875$466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3875$465_Y - connect \Y $and$ls180.v:3875$466_Y - end - attribute \src "ls180.v:3875.260-3875.329" - cell $and $and$ls180.v:3875$469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3875$468_Y - connect \Y $and$ls180.v:3875$469_Y - end - attribute \src "ls180.v:3875.41-3875.332" - cell $and $and$ls180.v:3875$472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3875$461_Y - connect \B $not$ls180.v:3875$471_Y - connect \Y $and$ls180.v:3875$472_Y - end - attribute \src "ls180.v:3875.40-3875.355" - cell $and $and$ls180.v:3875$473 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3875$472_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:3875$473_Y - end - attribute \src "ls180.v:3876.34-3876.106" - cell $and $and$ls180.v:3876$476 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3876$474_Y - connect \B $not$ls180.v:3876$475_Y - connect \Y $and$ls180.v:3876$476_Y - end - attribute \src "ls180.v:3880.110-3880.179" - cell $and $and$ls180.v:3880$479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3880$478_Y - connect \Y $and$ls180.v:3880$479_Y - end - attribute \src "ls180.v:3880.185-3880.254" - cell $and $and$ls180.v:3880$482 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3880$481_Y - connect \Y $and$ls180.v:3880$482_Y - end - attribute \src "ls180.v:3880.260-3880.329" - cell $and $and$ls180.v:3880$485 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3880$484_Y - connect \Y $and$ls180.v:3880$485_Y - end - attribute \src "ls180.v:3880.41-3880.332" - cell $and $and$ls180.v:3880$488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3880$477_Y - connect \B $not$ls180.v:3880$487_Y - connect \Y $and$ls180.v:3880$488_Y - end - attribute \src "ls180.v:3880.40-3880.355" - cell $and $and$ls180.v:3880$489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3880$488_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:3880$489_Y - end - attribute \src "ls180.v:3881.34-3881.106" - cell $and $and$ls180.v:3881$492 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3881$490_Y - connect \B $not$ls180.v:3881$491_Y - connect \Y $and$ls180.v:3881$492_Y - end - attribute \src "ls180.v:3885.151-3885.220" - cell $and $and$ls180.v:3885$496 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3885$495_Y - connect \Y $and$ls180.v:3885$496_Y - end - attribute \src "ls180.v:3885.226-3885.295" - cell $and $and$ls180.v:3885$499 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3885$498_Y - connect \Y $and$ls180.v:3885$499_Y - end - attribute \src "ls180.v:3885.301-3885.370" - cell $and $and$ls180.v:3885$502 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3885$501_Y - connect \Y $and$ls180.v:3885$502_Y - end - attribute \src "ls180.v:3885.82-3885.373" - cell $and $and$ls180.v:3885$505 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3885$494_Y - connect \B $not$ls180.v:3885$504_Y - connect \Y $and$ls180.v:3885$505_Y - end - attribute \src "ls180.v:3885.43-3885.374" - cell $and $and$ls180.v:3885$506 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3885$493_Y - connect \B $and$ls180.v:3885$505_Y - connect \Y $and$ls180.v:3885$506_Y - end - attribute \src "ls180.v:3885.42-3885.410" - cell $and $and$ls180.v:3885$507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3885$506_Y - connect \B \main_sdram_interface_bank0_ready - connect \Y $and$ls180.v:3885$507_Y - end - attribute \src "ls180.v:3885.525-3885.594" - cell $and $and$ls180.v:3885$512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3885$511_Y - connect \Y $and$ls180.v:3885$512_Y - end - attribute \src "ls180.v:3885.600-3885.669" - cell $and $and$ls180.v:3885$515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3885$514_Y - connect \Y $and$ls180.v:3885$515_Y - end - attribute \src "ls180.v:3885.675-3885.744" - cell $and $and$ls180.v:3885$518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3885$517_Y - connect \Y $and$ls180.v:3885$518_Y - end - attribute \src "ls180.v:3885.456-3885.747" - cell $and $and$ls180.v:3885$521 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3885$510_Y - connect \B $not$ls180.v:3885$520_Y - connect \Y $and$ls180.v:3885$521_Y - end - attribute \src "ls180.v:3885.417-3885.748" - cell $and $and$ls180.v:3885$522 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3885$509_Y - connect \B $and$ls180.v:3885$521_Y - connect \Y $and$ls180.v:3885$522_Y - end - attribute \src "ls180.v:3885.416-3885.784" - cell $and $and$ls180.v:3885$523 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3885$522_Y - connect \B \main_sdram_interface_bank1_ready - connect \Y $and$ls180.v:3885$523_Y - end - attribute \src "ls180.v:3885.899-3885.968" - cell $and $and$ls180.v:3885$528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3885$527_Y - connect \Y $and$ls180.v:3885$528_Y - end - attribute \src "ls180.v:3885.974-3885.1043" - cell $and $and$ls180.v:3885$531 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3885$530_Y - connect \Y $and$ls180.v:3885$531_Y - end - attribute \src "ls180.v:3885.1049-3885.1118" - cell $and $and$ls180.v:3885$534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3885$533_Y - connect \Y $and$ls180.v:3885$534_Y - end - attribute \src "ls180.v:3885.830-3885.1121" - cell $and $and$ls180.v:3885$537 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3885$526_Y - connect \B $not$ls180.v:3885$536_Y - connect \Y $and$ls180.v:3885$537_Y - end - attribute \src "ls180.v:3885.791-3885.1122" - cell $and $and$ls180.v:3885$538 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3885$525_Y - connect \B $and$ls180.v:3885$537_Y - connect \Y $and$ls180.v:3885$538_Y - end - attribute \src "ls180.v:3885.790-3885.1158" - cell $and $and$ls180.v:3885$539 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3885$538_Y - connect \B \main_sdram_interface_bank2_ready - connect \Y $and$ls180.v:3885$539_Y - end - attribute \src "ls180.v:3885.1273-3885.1342" - cell $and $and$ls180.v:3885$544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3885$543_Y - connect \Y $and$ls180.v:3885$544_Y - end - attribute \src "ls180.v:3885.1348-3885.1417" - cell $and $and$ls180.v:3885$547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3885$546_Y - connect \Y $and$ls180.v:3885$547_Y - end - attribute \src "ls180.v:3885.1423-3885.1492" - cell $and $and$ls180.v:3885$550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3885$549_Y - connect \Y $and$ls180.v:3885$550_Y - end - attribute \src "ls180.v:3885.1204-3885.1495" - cell $and $and$ls180.v:3885$553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3885$542_Y - connect \B $not$ls180.v:3885$552_Y - connect \Y $and$ls180.v:3885$553_Y - end - attribute \src "ls180.v:3885.1165-3885.1496" - cell $and $and$ls180.v:3885$554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3885$541_Y - connect \B $and$ls180.v:3885$553_Y - connect \Y $and$ls180.v:3885$554_Y - end - attribute \src "ls180.v:3885.1164-3885.1532" - cell $and $and$ls180.v:3885$555 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3885$554_Y - connect \B \main_sdram_interface_bank3_ready - connect \Y $and$ls180.v:3885$555_Y - end - attribute \src "ls180.v:3943.9-3943.46" - cell $and $and$ls180.v:3943$561 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_stb - connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:3943$561_Y - end - attribute \src "ls180.v:3961.9-3961.46" - cell $and $and$ls180.v:3961$568 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_stb - connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:3961$568_Y - end - attribute \src "ls180.v:3974.32-3974.75" - cell $and $and$ls180.v:3974$572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_cyc - connect \B \main_litedram_wb_stb - connect \Y $and$ls180.v:3974$572_Y - end - attribute \src "ls180.v:3974.31-3974.99" - cell $and $and$ls180.v:3974$574 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3974$572_Y - connect \B $not$ls180.v:3974$573_Y - connect \Y $and$ls180.v:3974$574_Y - end - attribute \src "ls180.v:3975.34-3975.102" - cell $and $and$ls180.v:3975$576 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3975$575_Y - connect \B \main_port_cmd_payload_we - connect \Y $and$ls180.v:3975$576_Y - end - attribute \src "ls180.v:3975.33-3975.128" - cell $and $and$ls180.v:3975$578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3975$576_Y - connect \B $not$ls180.v:3975$577_Y - connect \Y $and$ls180.v:3975$578_Y - end - attribute \src "ls180.v:3976.33-3976.104" - cell $and $and$ls180.v:3976$581 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3976$579_Y - connect \B $not$ls180.v:3976$580_Y - connect \Y $and$ls180.v:3976$581_Y - end - attribute \src "ls180.v:3977.49-3977.85" - cell $and $and$ls180.v:3977$582 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_we - connect \B \main_ack_wdata - connect \Y $and$ls180.v:3977$582_Y - end - attribute \src "ls180.v:3977.90-3977.129" - cell $and $and$ls180.v:3977$584 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3977$583_Y - connect \B \main_ack_rdata - connect \Y $and$ls180.v:3977$584_Y - end - attribute \src "ls180.v:3977.32-3977.131" - cell $and $and$ls180.v:3977$586 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_ack_cmd - connect \B $or$ls180.v:3977$585_Y - connect \Y $and$ls180.v:3977$586_Y - end - attribute \src "ls180.v:3978.25-3978.66" - cell $and $and$ls180.v:3978$587 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_valid - connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:3978$587_Y - end - attribute \src "ls180.v:3979.27-3979.72" - cell $and $and$ls180.v:3979$589 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_wdata_valid - connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:3979$589_Y - end - attribute \src "ls180.v:3980.26-3980.71" - cell $and $and$ls180.v:3980$591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_rdata_valid - connect \B \main_port_rdata_ready - connect \Y $and$ls180.v:3980$591_Y - end - attribute \src "ls180.v:4095.34-4095.89" - cell $and $and$ls180.v:4095$623 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_clocker_clk1 - connect \B $not$ls180.v:4095$622_Y - connect \Y $and$ls180.v:4095$623_Y - end - attribute \src "ls180.v:4199.9-4199.70" - cell $and $and$ls180.v:4199$632 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdw_sink_valid - connect \B \libresocsim_cmdw_pads_out_ready - connect \Y $and$ls180.v:4199$632_Y - end - attribute \src "ls180.v:4219.54-4219.149" - cell $and $and$ls180.v:4219$635 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdr_cmdr_pads_in_valid - connect \B $or$ls180.v:4219$634_Y - connect \Y $and$ls180.v:4219$635_Y - end - attribute \src "ls180.v:4238.53-4238.140" - cell $and $and$ls180.v:4238$638 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdr_cmdr_converter_sink_valid - connect \B \libresocsim_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:4238$638_Y - end - attribute \src "ls180.v:4279.9-4279.70" - cell $and $and$ls180.v:4279$646 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdr_source_valid - connect \B \libresocsim_cmdr_source_ready - connect \Y $and$ls180.v:4279$646_Y - end - attribute \src "ls180.v:4317.9-4317.70" - cell $and $and$ls180.v:4317$652 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdr_source_valid - connect \B \libresocsim_cmdr_source_ready - connect \Y $and$ls180.v:4317$652_Y - end - attribute \src "ls180.v:4326.10-4326.71" - cell $and $and$ls180.v:4326$653 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdr_sink_valid - connect \B \libresocsim_cmdr_pads_out_ready - connect \Y $and$ls180.v:4326$653_Y - end - attribute \src "ls180.v:4326.9-4326.96" - cell $and $and$ls180.v:4326$654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4326$653_Y - connect \B \libresocsim_cmdw_done - connect \Y $and$ls180.v:4326$654_Y - end - attribute \src "ls180.v:4346.55-4346.120" - cell $and $and$ls180.v:4346$656 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_dataw_crcr_pads_in_valid - connect \B \libresocsim_dataw_crcr_run - connect \Y $and$ls180.v:4346$656_Y - end - attribute \src "ls180.v:4365.54-4365.143" - cell $and $and$ls180.v:4365$659 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_dataw_crcr_converter_sink_valid - connect \B \libresocsim_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:4365$659_Y - end - attribute \src "ls180.v:4462.9-4462.72" - cell $and $and$ls180.v:4462$669 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_dataw_sink_valid - connect \B \libresocsim_dataw_pads_out_ready - connect \Y $and$ls180.v:4462$669_Y - end - attribute \src "ls180.v:4480.56-4480.123" - cell $and $and$ls180.v:4480$671 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_datar_datar_pads_in_valid - connect \B \libresocsim_datar_datar_run - connect \Y $and$ls180.v:4480$671_Y - end - attribute \src "ls180.v:4499.55-4499.146" - cell $and $and$ls180.v:4499$674 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_datar_datar_converter_sink_valid - connect \B \libresocsim_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:4499$674_Y - end - attribute \src "ls180.v:4581.9-4581.72" - cell $and $and$ls180.v:4581$689 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_datar_source_valid - connect \B \libresocsim_datar_source_ready - connect \Y $and$ls180.v:4581$689_Y - end - attribute \src "ls180.v:4588.9-4588.72" - cell $and $and$ls180.v:4588$690 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_datar_sink_valid - connect \B \libresocsim_datar_pads_out_ready - connect \Y $and$ls180.v:4588$690_Y - end - attribute \src "ls180.v:4669.55-4669.145" - cell $and $and$ls180.v:4669$813 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_sink_last - connect \B \libresocsim_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:4669$813_Y - end - attribute \src "ls180.v:4669.54-4669.193" - cell $and $and$ls180.v:4669$814 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4669$813_Y - connect \B \libresocsim_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4669$814_Y - end - attribute \src "ls180.v:4670.57-4670.148" - cell $and $and$ls180.v:4670$815 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_sink_valid - connect \B \libresocsim_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4670$815_Y - end - attribute \src "ls180.v:4672.55-4672.145" - cell $and $and$ls180.v:4672$816 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_sink_last - connect \B \libresocsim_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:4672$816_Y - end - attribute \src "ls180.v:4672.54-4672.193" - cell $and $and$ls180.v:4672$817 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4672$816_Y - connect \B \libresocsim_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4672$817_Y - end - attribute \src "ls180.v:4673.57-4673.148" - cell $and $and$ls180.v:4673$818 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_sink_valid - connect \B \libresocsim_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4673$818_Y - end - attribute \src "ls180.v:4675.55-4675.145" - cell $and $and$ls180.v:4675$819 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_sink_last - connect \B \libresocsim_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:4675$819_Y - end - attribute \src "ls180.v:4675.54-4675.193" - cell $and $and$ls180.v:4675$820 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4675$819_Y - connect \B \libresocsim_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4675$820_Y - end - attribute \src "ls180.v:4676.57-4676.148" - cell $and $and$ls180.v:4676$821 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_sink_valid - connect \B \libresocsim_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4676$821_Y - end - attribute \src "ls180.v:4678.55-4678.145" - cell $and $and$ls180.v:4678$822 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_sink_last - connect \B \libresocsim_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:4678$822_Y - end - attribute \src "ls180.v:4678.54-4678.193" - cell $and $and$ls180.v:4678$823 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4678$822_Y - connect \B \libresocsim_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4678$823_Y - end - attribute \src "ls180.v:4679.57-4679.148" - cell $and $and$ls180.v:4679$824 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_sink_valid - connect \B \libresocsim_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4679$824_Y - end - attribute \src "ls180.v:4792.10-4792.100" - cell $and $and$ls180.v:4792$873 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_sink_valid - connect \B \libresocsim_sdcore_crc16_inserter_sink_last - connect \Y $and$ls180.v:4792$873_Y - end - attribute \src "ls180.v:4792.9-4792.148" - cell $and $and$ls180.v:4792$874 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4792$873_Y - connect \B \libresocsim_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4792$874_Y - end - attribute \src "ls180.v:4802.9-4802.180" - cell $and $and$ls180.v:4802$878 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4802$876_Y - connect \B $eq$ls180.v:4802$877_Y - connect \Y $and$ls180.v:4802$878_Y - end - attribute \src "ls180.v:4802.8-4802.268" - cell $and $and$ls180.v:4802$880 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4802$878_Y - connect \B $eq$ls180.v:4802$879_Y - connect \Y $and$ls180.v:4802$880_Y - end - attribute \src "ls180.v:4802.7-4802.356" - cell $and $and$ls180.v:4802$882 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4802$880_Y - connect \B $eq$ls180.v:4802$881_Y - connect \Y $and$ls180.v:4802$882_Y - end - attribute \src "ls180.v:4807.56-4807.145" - cell $and $and$ls180.v:4807$883 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_sink_valid - connect \B \libresocsim_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:4807$883_Y - end - attribute \src "ls180.v:4817.56-4817.145" - cell $and $and$ls180.v:4817$886 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_sink_valid - connect \B \libresocsim_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:4817$886_Y - end - attribute \src "ls180.v:4827.56-4827.145" - cell $and $and$ls180.v:4827$889 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_sink_valid - connect \B \libresocsim_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:4827$889_Y - end - attribute \src "ls180.v:4837.56-4837.145" - cell $and $and$ls180.v:4837$892 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_sink_valid - connect \B \libresocsim_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:4837$892_Y - end - attribute \src "ls180.v:4849.7-4849.98" - cell $and $and$ls180.v:4849$897 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_sink_valid - connect \B $gt$ls180.v:4849$896_Y - connect \Y $and$ls180.v:4849$897_Y - end - attribute \src "ls180.v:4967.9-4967.66" - cell $and $and$ls180.v:4967$946 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdw_sink_valid - connect \B \libresocsim_cmdw_sink_ready - connect \Y $and$ls180.v:4967$946_Y - end - attribute \src "ls180.v:5019.10-5019.68" - cell $and $and$ls180.v:5019$955 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_dataw_sink_valid - connect \B \libresocsim_dataw_sink_last - connect \Y $and$ls180.v:5019$955_Y - end - attribute \src "ls180.v:5019.9-5019.100" - cell $and $and$ls180.v:5019$956 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5019$955_Y - connect \B \libresocsim_dataw_sink_ready - connect \Y $and$ls180.v:5019$956_Y - end - attribute \src "ls180.v:5045.11-5045.73" - cell $and $and$ls180.v:5045$964 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_datar_source_last - connect \B \libresocsim_datar_source_ready - connect \Y $and$ls180.v:5045$964_Y - end - attribute \src "ls180.v:5129.50-5129.180" - cell $and $and$ls180.v:5129$972 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdblock2mem_fifo_syncfifo_we - connect \B $or$ls180.v:5129$971_Y - connect \Y $and$ls180.v:5129$972_Y - end - attribute \src "ls180.v:5130.48-5130.137" - cell $and $and$ls180.v:5130$973 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdblock2mem_fifo_syncfifo_readable - connect \B \libresocsim_sdblock2mem_fifo_syncfifo_re - connect \Y $and$ls180.v:5130$973_Y - end - attribute \src "ls180.v:5142.55-5142.146" - cell $and $and$ls180.v:5142$978 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdblock2mem_converter_sink_valid - connect \B \libresocsim_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:5142$978_Y - end - attribute \src "ls180.v:5169.9-5169.116" - cell $and $and$ls180.v:5169$982 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdblock2mem_wishbonedmawriter_sink_valid - connect \B \libresocsim_sdblock2mem_wishbonedmawriter_sink_ready - connect \Y $and$ls180.v:5169$982_Y - end - attribute \src "ls180.v:5242.9-5242.72" - cell $and $and$ls180.v:5242$988 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_interface1_bus_stb - connect \B \libresocsim_interface1_bus_ack - connect \Y $and$ls180.v:5242$988_Y - end - attribute \src "ls180.v:5295.58-5295.144" - cell $and $and$ls180.v:5295$996 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdmem2block_converter_sink_first - connect \B \libresocsim_sdmem2block_converter_first - connect \Y $and$ls180.v:5295$996_Y - end - attribute \src "ls180.v:5296.57-5296.141" - cell $and $and$ls180.v:5296$997 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdmem2block_converter_sink_last - connect \B \libresocsim_sdmem2block_converter_last - connect \Y $and$ls180.v:5296$997_Y - end - attribute \src "ls180.v:5297.56-5297.143" - cell $and $and$ls180.v:5297$998 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdmem2block_converter_last - connect \B \libresocsim_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:5297$998_Y - end - attribute \src "ls180.v:5337.50-5337.180" - cell $and $and$ls180.v:5337$1003 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdmem2block_fifo_syncfifo_we - connect \B $or$ls180.v:5337$1002_Y - connect \Y $and$ls180.v:5337$1003_Y - end - attribute \src "ls180.v:5338.48-5338.137" - cell $and $and$ls180.v:5338$1004 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdmem2block_fifo_syncfifo_readable - connect \B \libresocsim_sdmem2block_fifo_syncfifo_re - connect \Y $and$ls180.v:5338$1004_Y - end - attribute \src "ls180.v:5429.9-5429.76" - cell $and $and$ls180.v:5429$1016 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_libresocsim_wishbone_cyc - connect \B \builder_libresocsim_wishbone_stb - connect \Y $and$ls180.v:5429$1016_Y - end - attribute \src "ls180.v:5432.44-5432.120" - cell $and $and$ls180.v:5432$1018 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_libresocsim_wishbone_we - connect \B $ne$ls180.v:5432$1017_Y - connect \Y $and$ls180.v:5432$1018_Y - end - attribute \src "ls180.v:5451.63-5451.107" - cell $and $and$ls180.v:5451$1020 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5451$1019_Y - connect \Y $and$ls180.v:5451$1020_Y - end - attribute \src "ls180.v:5452.63-5452.107" - cell $and $and$ls180.v:5452$1022 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5452$1021_Y - connect \Y $and$ls180.v:5452$1022_Y - end - attribute \src "ls180.v:5453.42-5453.86" - cell $and $and$ls180.v:5453$1024 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5453$1023_Y - connect \Y $and$ls180.v:5453$1024_Y - end - attribute \src "ls180.v:5454.42-5454.86" - cell $and $and$ls180.v:5454$1026 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5454$1025_Y - connect \Y $and$ls180.v:5454$1026_Y - end - attribute \src "ls180.v:5455.63-5455.107" - cell $and $and$ls180.v:5455$1028 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5455$1027_Y - connect \Y $and$ls180.v:5455$1028_Y - end - attribute \src "ls180.v:5456.63-5456.107" - cell $and $and$ls180.v:5456$1030 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5456$1029_Y - connect \Y $and$ls180.v:5456$1030_Y - end - attribute \src "ls180.v:5457.42-5457.86" - cell $and $and$ls180.v:5457$1032 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5457$1031_Y - connect \Y $and$ls180.v:5457$1032_Y - end - attribute \src "ls180.v:5458.42-5458.86" - cell $and $and$ls180.v:5458$1034 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5458$1033_Y - connect \Y $and$ls180.v:5458$1034_Y - end - attribute \src "ls180.v:5503.40-5503.81" - cell $and $and$ls180.v:5503$1041 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [0] - connect \Y $and$ls180.v:5503$1041_Y - end - attribute \src "ls180.v:5504.50-5504.91" - cell $and $and$ls180.v:5504$1042 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [1] - connect \Y $and$ls180.v:5504$1042_Y - end - attribute \src "ls180.v:5505.50-5505.91" - cell $and $and$ls180.v:5505$1043 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [2] - connect \Y $and$ls180.v:5505$1043_Y - end - attribute \src "ls180.v:5506.29-5506.70" - cell $and $and$ls180.v:5506$1044 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [3] - connect \Y $and$ls180.v:5506$1044_Y - end - attribute \src "ls180.v:5507.44-5507.85" - cell $and $and$ls180.v:5507$1045 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [4] - connect \Y $and$ls180.v:5507$1045_Y - end - attribute \src "ls180.v:5509.25-5509.64" - cell $and $and$ls180.v:5509$1050 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_stb - connect \B \builder_shared_cyc - connect \Y $and$ls180.v:5509$1050_Y - end - attribute \src "ls180.v:5509.24-5509.89" - cell $and $and$ls180.v:5509$1052 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5509$1050_Y - connect \B $not$ls180.v:5509$1051_Y - connect \Y $and$ls180.v:5509$1052_Y - end - attribute \src "ls180.v:5515.31-5515.92" - cell $and $and$ls180.v:5515$1058 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } - connect \B \main_libresocsim_ram_bus_dat_r - connect \Y $and$ls180.v:5515$1058_Y - end - attribute \src "ls180.v:5515.97-5515.168" - cell $and $and$ls180.v:5515$1059 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } - connect \B \main_libresocsim_libresoc_xics_icp_dat_r - connect \Y $and$ls180.v:5515$1059_Y - end - attribute \src "ls180.v:5515.174-5515.245" - cell $and $and$ls180.v:5515$1061 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } - connect \B \main_libresocsim_libresoc_xics_ics_dat_r - connect \Y $and$ls180.v:5515$1061_Y - end - attribute \src "ls180.v:5515.251-5515.301" - cell $and $and$ls180.v:5515$1063 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } - connect \B \main_wb_sdram_dat_r - connect \Y $and$ls180.v:5515$1063_Y - end - attribute \src "ls180.v:5515.307-5515.372" - cell $and $and$ls180.v:5515$1065 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } - connect \B \builder_libresocsim_wishbone_dat_r - connect \Y $and$ls180.v:5515$1065_Y - end - attribute \src "ls180.v:5525.39-5525.92" - cell $and $and$ls180.v:5525$1069 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5525$1069_Y - end - attribute \src "ls180.v:5525.38-5525.142" - cell $and $and$ls180.v:5525$1071 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5525$1069_Y - connect \B $eq$ls180.v:5525$1070_Y - connect \Y $and$ls180.v:5525$1071_Y - end - attribute \src "ls180.v:5526.39-5526.95" - cell $and $and$ls180.v:5526$1073 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5526$1072_Y - connect \Y $and$ls180.v:5526$1073_Y - end - attribute \src "ls180.v:5526.38-5526.145" - cell $and $and$ls180.v:5526$1075 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5526$1073_Y - connect \B $eq$ls180.v:5526$1074_Y - connect \Y $and$ls180.v:5526$1075_Y - end - attribute \src "ls180.v:5528.41-5528.94" - cell $and $and$ls180.v:5528$1076 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5528$1076_Y - end - attribute \src "ls180.v:5528.40-5528.144" - cell $and $and$ls180.v:5528$1078 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5528$1076_Y - connect \B $eq$ls180.v:5528$1077_Y - connect \Y $and$ls180.v:5528$1078_Y - end - attribute \src "ls180.v:5529.41-5529.97" - cell $and $and$ls180.v:5529$1080 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5529$1079_Y - connect \Y $and$ls180.v:5529$1080_Y - end - attribute \src "ls180.v:5529.40-5529.147" - cell $and $and$ls180.v:5529$1082 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5529$1080_Y - connect \B $eq$ls180.v:5529$1081_Y - connect \Y $and$ls180.v:5529$1082_Y - end - attribute \src "ls180.v:5531.41-5531.94" - cell $and $and$ls180.v:5531$1083 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5531$1083_Y - end - attribute \src "ls180.v:5531.40-5531.144" - cell $and $and$ls180.v:5531$1085 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5531$1083_Y - connect \B $eq$ls180.v:5531$1084_Y - connect \Y $and$ls180.v:5531$1085_Y - end - attribute \src "ls180.v:5532.41-5532.97" - cell $and $and$ls180.v:5532$1087 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5532$1086_Y - connect \Y $and$ls180.v:5532$1087_Y - end - attribute \src "ls180.v:5532.40-5532.147" - cell $and $and$ls180.v:5532$1089 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5532$1087_Y - connect \B $eq$ls180.v:5532$1088_Y - connect \Y $and$ls180.v:5532$1089_Y - end - attribute \src "ls180.v:5534.41-5534.94" - cell $and $and$ls180.v:5534$1090 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5534$1090_Y - end - attribute \src "ls180.v:5534.40-5534.144" - cell $and $and$ls180.v:5534$1092 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5534$1090_Y - connect \B $eq$ls180.v:5534$1091_Y - connect \Y $and$ls180.v:5534$1092_Y - end - attribute \src "ls180.v:5535.41-5535.97" - cell $and $and$ls180.v:5535$1094 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5535$1093_Y - connect \Y $and$ls180.v:5535$1094_Y - end - attribute \src "ls180.v:5535.40-5535.147" - cell $and $and$ls180.v:5535$1096 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5535$1094_Y - connect \B $eq$ls180.v:5535$1095_Y - connect \Y $and$ls180.v:5535$1096_Y - end - attribute \src "ls180.v:5537.41-5537.94" - cell $and $and$ls180.v:5537$1097 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5537$1097_Y - end - attribute \src "ls180.v:5537.40-5537.144" - cell $and $and$ls180.v:5537$1099 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5537$1097_Y - connect \B $eq$ls180.v:5537$1098_Y - connect \Y $and$ls180.v:5537$1099_Y - end - attribute \src "ls180.v:5538.41-5538.97" - cell $and $and$ls180.v:5538$1101 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5538$1100_Y - connect \Y $and$ls180.v:5538$1101_Y - end - attribute \src "ls180.v:5538.40-5538.147" - cell $and $and$ls180.v:5538$1103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5538$1101_Y - connect \B $eq$ls180.v:5538$1102_Y - connect \Y $and$ls180.v:5538$1103_Y - end - attribute \src "ls180.v:5540.44-5540.97" - cell $and $and$ls180.v:5540$1104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5540$1104_Y - end - attribute \src "ls180.v:5540.43-5540.147" - cell $and $and$ls180.v:5540$1106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5540$1104_Y - connect \B $eq$ls180.v:5540$1105_Y - connect \Y $and$ls180.v:5540$1106_Y - end - attribute \src "ls180.v:5541.44-5541.100" - cell $and $and$ls180.v:5541$1108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5541$1107_Y - connect \Y $and$ls180.v:5541$1108_Y - end - attribute \src "ls180.v:5541.43-5541.150" - cell $and $and$ls180.v:5541$1110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5541$1108_Y - connect \B $eq$ls180.v:5541$1109_Y - connect \Y $and$ls180.v:5541$1110_Y - end - attribute \src "ls180.v:5543.44-5543.97" - cell $and $and$ls180.v:5543$1111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5543$1111_Y - end - attribute \src "ls180.v:5543.43-5543.147" - cell $and $and$ls180.v:5543$1113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5543$1111_Y - connect \B $eq$ls180.v:5543$1112_Y - connect \Y $and$ls180.v:5543$1113_Y - end - attribute \src "ls180.v:5544.44-5544.100" - cell $and $and$ls180.v:5544$1115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5544$1114_Y - connect \Y $and$ls180.v:5544$1115_Y - end - attribute \src "ls180.v:5544.43-5544.150" - cell $and $and$ls180.v:5544$1117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5544$1115_Y - connect \B $eq$ls180.v:5544$1116_Y - connect \Y $and$ls180.v:5544$1117_Y - end - attribute \src "ls180.v:5546.44-5546.97" - cell $and $and$ls180.v:5546$1118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5546$1118_Y - end - attribute \src "ls180.v:5546.43-5546.147" - cell $and $and$ls180.v:5546$1120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5546$1118_Y - connect \B $eq$ls180.v:5546$1119_Y - connect \Y $and$ls180.v:5546$1120_Y - end - attribute \src "ls180.v:5547.44-5547.100" - cell $and $and$ls180.v:5547$1122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5547$1121_Y - connect \Y $and$ls180.v:5547$1122_Y - end - attribute \src "ls180.v:5547.43-5547.150" - cell $and $and$ls180.v:5547$1124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5547$1122_Y - connect \B $eq$ls180.v:5547$1123_Y - connect \Y $and$ls180.v:5547$1124_Y - end - attribute \src "ls180.v:5549.44-5549.97" - cell $and $and$ls180.v:5549$1125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5549$1125_Y - end - attribute \src "ls180.v:5549.43-5549.147" - cell $and $and$ls180.v:5549$1127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5549$1125_Y - connect \B $eq$ls180.v:5549$1126_Y - connect \Y $and$ls180.v:5549$1127_Y - end - attribute \src "ls180.v:5550.44-5550.100" - cell $and $and$ls180.v:5550$1129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5550$1128_Y - connect \Y $and$ls180.v:5550$1129_Y - end - attribute \src "ls180.v:5550.43-5550.150" - cell $and $and$ls180.v:5550$1131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5550$1129_Y - connect \B $eq$ls180.v:5550$1130_Y - connect \Y $and$ls180.v:5550$1131_Y - end - attribute \src "ls180.v:5563.35-5563.88" - cell $and $and$ls180.v:5563$1133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5563$1133_Y - end - attribute \src "ls180.v:5563.34-5563.136" - cell $and $and$ls180.v:5563$1135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5563$1133_Y - connect \B $eq$ls180.v:5563$1134_Y - connect \Y $and$ls180.v:5563$1135_Y - end - attribute \src "ls180.v:5564.35-5564.91" - cell $and $and$ls180.v:5564$1137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5564$1136_Y - connect \Y $and$ls180.v:5564$1137_Y - end - attribute \src "ls180.v:5564.34-5564.139" - cell $and $and$ls180.v:5564$1139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5564$1137_Y - connect \B $eq$ls180.v:5564$1138_Y - connect \Y $and$ls180.v:5564$1139_Y - end - attribute \src "ls180.v:5569.35-5569.88" - cell $and $and$ls180.v:5569$1141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5569$1141_Y - end - attribute \src "ls180.v:5569.34-5569.136" - cell $and $and$ls180.v:5569$1143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5569$1141_Y - connect \B $eq$ls180.v:5569$1142_Y - connect \Y $and$ls180.v:5569$1143_Y - end - attribute \src "ls180.v:5570.35-5570.91" - cell $and $and$ls180.v:5570$1145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5570$1144_Y - connect \Y $and$ls180.v:5570$1145_Y - end - attribute \src "ls180.v:5570.34-5570.139" - cell $and $and$ls180.v:5570$1147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5570$1145_Y - connect \B $eq$ls180.v:5570$1146_Y - connect \Y $and$ls180.v:5570$1147_Y - end - attribute \src "ls180.v:5575.42-5575.95" - cell $and $and$ls180.v:5575$1149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5575$1149_Y - end - attribute \src "ls180.v:5575.41-5575.145" - cell $and $and$ls180.v:5575$1151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5575$1149_Y - connect \B $eq$ls180.v:5575$1150_Y - connect \Y $and$ls180.v:5575$1151_Y - end - attribute \src "ls180.v:5576.42-5576.98" - cell $and $and$ls180.v:5576$1153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5576$1152_Y - connect \Y $and$ls180.v:5576$1153_Y - end - attribute \src "ls180.v:5576.41-5576.148" - cell $and $and$ls180.v:5576$1155 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5576$1153_Y - connect \B $eq$ls180.v:5576$1154_Y - connect \Y $and$ls180.v:5576$1155_Y - end - attribute \src "ls180.v:5578.42-5578.95" - cell $and $and$ls180.v:5578$1156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5578$1156_Y - end - attribute \src "ls180.v:5578.41-5578.145" - cell $and $and$ls180.v:5578$1158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5578$1156_Y - connect \B $eq$ls180.v:5578$1157_Y - connect \Y $and$ls180.v:5578$1158_Y - end - attribute \src "ls180.v:5579.42-5579.98" - cell $and $and$ls180.v:5579$1160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5579$1159_Y - connect \Y $and$ls180.v:5579$1160_Y - end - attribute \src "ls180.v:5579.41-5579.148" - cell $and $and$ls180.v:5579$1162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5579$1160_Y - connect \B $eq$ls180.v:5579$1161_Y - connect \Y $and$ls180.v:5579$1162_Y - end - attribute \src "ls180.v:5581.42-5581.95" - cell $and $and$ls180.v:5581$1163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5581$1163_Y - end - attribute \src "ls180.v:5581.41-5581.145" - cell $and $and$ls180.v:5581$1165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5581$1163_Y - connect \B $eq$ls180.v:5581$1164_Y - connect \Y $and$ls180.v:5581$1165_Y - end - attribute \src "ls180.v:5582.42-5582.98" - cell $and $and$ls180.v:5582$1167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5582$1166_Y - connect \Y $and$ls180.v:5582$1167_Y - end - attribute \src "ls180.v:5582.41-5582.148" - cell $and $and$ls180.v:5582$1169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5582$1167_Y - connect \B $eq$ls180.v:5582$1168_Y - connect \Y $and$ls180.v:5582$1169_Y - end - attribute \src "ls180.v:5584.42-5584.95" - cell $and $and$ls180.v:5584$1170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5584$1170_Y - end - attribute \src "ls180.v:5584.41-5584.145" - cell $and $and$ls180.v:5584$1172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5584$1170_Y - connect \B $eq$ls180.v:5584$1171_Y - connect \Y $and$ls180.v:5584$1172_Y - end - attribute \src "ls180.v:5585.42-5585.98" - cell $and $and$ls180.v:5585$1174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5585$1173_Y - connect \Y $and$ls180.v:5585$1174_Y - end - attribute \src "ls180.v:5585.41-5585.148" - cell $and $and$ls180.v:5585$1176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5585$1174_Y - connect \B $eq$ls180.v:5585$1175_Y - connect \Y $and$ls180.v:5585$1176_Y - end - attribute \src "ls180.v:5587.42-5587.95" - cell $and $and$ls180.v:5587$1177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5587$1177_Y - end - attribute \src "ls180.v:5587.41-5587.145" - cell $and $and$ls180.v:5587$1179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5587$1177_Y - connect \B $eq$ls180.v:5587$1178_Y - connect \Y $and$ls180.v:5587$1179_Y - end - attribute \src "ls180.v:5588.42-5588.98" - cell $and $and$ls180.v:5588$1181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5588$1180_Y - connect \Y $and$ls180.v:5588$1181_Y - end - attribute \src "ls180.v:5588.41-5588.148" - cell $and $and$ls180.v:5588$1183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5588$1181_Y - connect \B $eq$ls180.v:5588$1182_Y - connect \Y $and$ls180.v:5588$1183_Y - end - attribute \src "ls180.v:5590.42-5590.95" - cell $and $and$ls180.v:5590$1184 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5590$1184_Y - end - attribute \src "ls180.v:5590.41-5590.145" - cell $and $and$ls180.v:5590$1186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5590$1184_Y - connect \B $eq$ls180.v:5590$1185_Y - connect \Y $and$ls180.v:5590$1186_Y - end - attribute \src "ls180.v:5591.42-5591.98" - cell $and $and$ls180.v:5591$1188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5591$1187_Y - connect \Y $and$ls180.v:5591$1188_Y - end - attribute \src "ls180.v:5591.41-5591.148" - cell $and $and$ls180.v:5591$1190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5591$1188_Y - connect \B $eq$ls180.v:5591$1189_Y - connect \Y $and$ls180.v:5591$1190_Y - end - attribute \src "ls180.v:5593.42-5593.95" - cell $and $and$ls180.v:5593$1191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5593$1191_Y - end - attribute \src "ls180.v:5593.41-5593.145" - cell $and $and$ls180.v:5593$1193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5593$1191_Y - connect \B $eq$ls180.v:5593$1192_Y - connect \Y $and$ls180.v:5593$1193_Y - end - attribute \src "ls180.v:5594.42-5594.98" - cell $and $and$ls180.v:5594$1195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5594$1194_Y - connect \Y $and$ls180.v:5594$1195_Y - end - attribute \src "ls180.v:5594.41-5594.148" - cell $and $and$ls180.v:5594$1197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5594$1195_Y - connect \B $eq$ls180.v:5594$1196_Y - connect \Y $and$ls180.v:5594$1197_Y - end - attribute \src "ls180.v:5596.42-5596.95" - cell $and $and$ls180.v:5596$1198 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5596$1198_Y - end - attribute \src "ls180.v:5596.41-5596.145" - cell $and $and$ls180.v:5596$1200 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5596$1198_Y - connect \B $eq$ls180.v:5596$1199_Y - connect \Y $and$ls180.v:5596$1200_Y - end - attribute \src "ls180.v:5597.42-5597.98" - cell $and $and$ls180.v:5597$1202 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5597$1201_Y - connect \Y $and$ls180.v:5597$1202_Y - end - attribute \src "ls180.v:5597.41-5597.148" - cell $and $and$ls180.v:5597$1204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5597$1202_Y - connect \B $eq$ls180.v:5597$1203_Y - connect \Y $and$ls180.v:5597$1204_Y - end - attribute \src "ls180.v:5599.44-5599.97" - cell $and $and$ls180.v:5599$1205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5599$1205_Y - end - attribute \src "ls180.v:5599.43-5599.147" - cell $and $and$ls180.v:5599$1207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5599$1205_Y - connect \B $eq$ls180.v:5599$1206_Y - connect \Y $and$ls180.v:5599$1207_Y - end - attribute \src "ls180.v:5600.44-5600.100" - cell $and $and$ls180.v:5600$1209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5600$1208_Y - connect \Y $and$ls180.v:5600$1209_Y - end - attribute \src "ls180.v:5600.43-5600.150" - cell $and $and$ls180.v:5600$1211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5600$1209_Y - connect \B $eq$ls180.v:5600$1210_Y - connect \Y $and$ls180.v:5600$1211_Y - end - attribute \src "ls180.v:5602.44-5602.97" - cell $and $and$ls180.v:5602$1212 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5602$1212_Y - end - attribute \src "ls180.v:5602.43-5602.147" - cell $and $and$ls180.v:5602$1214 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5602$1212_Y - connect \B $eq$ls180.v:5602$1213_Y - connect \Y $and$ls180.v:5602$1214_Y - end - attribute \src "ls180.v:5603.44-5603.100" - cell $and $and$ls180.v:5603$1216 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5603$1215_Y - connect \Y $and$ls180.v:5603$1216_Y - end - attribute \src "ls180.v:5603.43-5603.150" - cell $and $and$ls180.v:5603$1218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5603$1216_Y - connect \B $eq$ls180.v:5603$1217_Y - connect \Y $and$ls180.v:5603$1218_Y - end - attribute \src "ls180.v:5605.44-5605.97" - cell $and $and$ls180.v:5605$1219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5605$1219_Y - end - attribute \src "ls180.v:5605.43-5605.148" - cell $and $and$ls180.v:5605$1221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5605$1219_Y - connect \B $eq$ls180.v:5605$1220_Y - connect \Y $and$ls180.v:5605$1221_Y - end - attribute \src "ls180.v:5606.44-5606.100" - cell $and $and$ls180.v:5606$1223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5606$1222_Y - connect \Y $and$ls180.v:5606$1223_Y - end - attribute \src "ls180.v:5606.43-5606.151" - cell $and $and$ls180.v:5606$1225 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5606$1223_Y - connect \B $eq$ls180.v:5606$1224_Y - connect \Y $and$ls180.v:5606$1225_Y - end - attribute \src "ls180.v:5608.44-5608.97" - cell $and $and$ls180.v:5608$1226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5608$1226_Y - end - attribute \src "ls180.v:5608.43-5608.148" - cell $and $and$ls180.v:5608$1228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5608$1226_Y - connect \B $eq$ls180.v:5608$1227_Y - connect \Y $and$ls180.v:5608$1228_Y - end - attribute \src "ls180.v:5609.44-5609.100" - cell $and $and$ls180.v:5609$1230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5609$1229_Y - connect \Y $and$ls180.v:5609$1230_Y - end - attribute \src "ls180.v:5609.43-5609.151" - cell $and $and$ls180.v:5609$1232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5609$1230_Y - connect \B $eq$ls180.v:5609$1231_Y - connect \Y $and$ls180.v:5609$1232_Y - end - attribute \src "ls180.v:5611.44-5611.97" - cell $and $and$ls180.v:5611$1233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5611$1233_Y - end - attribute \src "ls180.v:5611.43-5611.148" - cell $and $and$ls180.v:5611$1235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5611$1233_Y - connect \B $eq$ls180.v:5611$1234_Y - connect \Y $and$ls180.v:5611$1235_Y - end - attribute \src "ls180.v:5612.44-5612.100" - cell $and $and$ls180.v:5612$1237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5612$1236_Y - connect \Y $and$ls180.v:5612$1237_Y - end - attribute \src "ls180.v:5612.43-5612.151" - cell $and $and$ls180.v:5612$1239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5612$1237_Y - connect \B $eq$ls180.v:5612$1238_Y - connect \Y $and$ls180.v:5612$1239_Y - end - attribute \src "ls180.v:5614.41-5614.94" - cell $and $and$ls180.v:5614$1240 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5614$1240_Y - end - attribute \src "ls180.v:5614.40-5614.145" - cell $and $and$ls180.v:5614$1242 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5614$1240_Y - connect \B $eq$ls180.v:5614$1241_Y - connect \Y $and$ls180.v:5614$1242_Y - end - attribute \src "ls180.v:5615.41-5615.97" - cell $and $and$ls180.v:5615$1244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5615$1243_Y - connect \Y $and$ls180.v:5615$1244_Y - end - attribute \src "ls180.v:5615.40-5615.148" - cell $and $and$ls180.v:5615$1246 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5615$1244_Y - connect \B $eq$ls180.v:5615$1245_Y - connect \Y $and$ls180.v:5615$1246_Y - end - attribute \src "ls180.v:5617.42-5617.95" - cell $and $and$ls180.v:5617$1247 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5617$1247_Y - end - attribute \src "ls180.v:5617.41-5617.146" - cell $and $and$ls180.v:5617$1249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5617$1247_Y - connect \B $eq$ls180.v:5617$1248_Y - connect \Y $and$ls180.v:5617$1249_Y - end - attribute \src "ls180.v:5618.42-5618.98" - cell $and $and$ls180.v:5618$1251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5618$1250_Y - connect \Y $and$ls180.v:5618$1251_Y - end - attribute \src "ls180.v:5618.41-5618.149" - cell $and $and$ls180.v:5618$1253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5618$1251_Y - connect \B $eq$ls180.v:5618$1252_Y - connect \Y $and$ls180.v:5618$1253_Y - end - attribute \src "ls180.v:5637.46-5637.99" - cell $and $and$ls180.v:5637$1255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5637$1255_Y - end - attribute \src "ls180.v:5637.45-5637.149" - cell $and $and$ls180.v:5637$1257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5637$1255_Y - connect \B $eq$ls180.v:5637$1256_Y - connect \Y $and$ls180.v:5637$1257_Y - end - attribute \src "ls180.v:5638.46-5638.102" - cell $and $and$ls180.v:5638$1259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5638$1258_Y - connect \Y $and$ls180.v:5638$1259_Y - end - attribute \src "ls180.v:5638.45-5638.152" - cell $and $and$ls180.v:5638$1261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5638$1259_Y - connect \B $eq$ls180.v:5638$1260_Y - connect \Y $and$ls180.v:5638$1261_Y - end - attribute \src "ls180.v:5640.46-5640.99" - cell $and $and$ls180.v:5640$1262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5640$1262_Y - end - attribute \src "ls180.v:5640.45-5640.149" - cell $and $and$ls180.v:5640$1264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5640$1262_Y - connect \B $eq$ls180.v:5640$1263_Y - connect \Y $and$ls180.v:5640$1264_Y - end - attribute \src "ls180.v:5641.46-5641.102" - cell $and $and$ls180.v:5641$1266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5641$1265_Y - connect \Y $and$ls180.v:5641$1266_Y - end - attribute \src "ls180.v:5641.45-5641.152" - cell $and $and$ls180.v:5641$1268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5641$1266_Y - connect \B $eq$ls180.v:5641$1267_Y - connect \Y $and$ls180.v:5641$1268_Y - end - attribute \src "ls180.v:5643.46-5643.99" - cell $and $and$ls180.v:5643$1269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5643$1269_Y - end - attribute \src "ls180.v:5643.45-5643.149" - cell $and $and$ls180.v:5643$1271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5643$1269_Y - connect \B $eq$ls180.v:5643$1270_Y - connect \Y $and$ls180.v:5643$1271_Y - end - attribute \src "ls180.v:5644.46-5644.102" - cell $and $and$ls180.v:5644$1273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5644$1272_Y - connect \Y $and$ls180.v:5644$1273_Y - end - attribute \src "ls180.v:5644.45-5644.152" - cell $and $and$ls180.v:5644$1275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5644$1273_Y - connect \B $eq$ls180.v:5644$1274_Y - connect \Y $and$ls180.v:5644$1275_Y - end - attribute \src "ls180.v:5646.46-5646.99" - cell $and $and$ls180.v:5646$1276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5646$1276_Y - end - attribute \src "ls180.v:5646.45-5646.149" - cell $and $and$ls180.v:5646$1278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5646$1276_Y - connect \B $eq$ls180.v:5646$1277_Y - connect \Y $and$ls180.v:5646$1278_Y - end - attribute \src "ls180.v:5647.46-5647.102" - cell $and $and$ls180.v:5647$1280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5647$1279_Y - connect \Y $and$ls180.v:5647$1280_Y - end - attribute \src "ls180.v:5647.45-5647.152" - cell $and $and$ls180.v:5647$1282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5647$1280_Y - connect \B $eq$ls180.v:5647$1281_Y - connect \Y $and$ls180.v:5647$1282_Y - end - attribute \src "ls180.v:5649.45-5649.98" - cell $and $and$ls180.v:5649$1283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5649$1283_Y - end - attribute \src "ls180.v:5649.44-5649.148" - cell $and $and$ls180.v:5649$1285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5649$1283_Y - connect \B $eq$ls180.v:5649$1284_Y - connect \Y $and$ls180.v:5649$1285_Y - end - attribute \src "ls180.v:5650.45-5650.101" - cell $and $and$ls180.v:5650$1287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5650$1286_Y - connect \Y $and$ls180.v:5650$1287_Y - end - attribute \src "ls180.v:5650.44-5650.151" - cell $and $and$ls180.v:5650$1289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5650$1287_Y - connect \B $eq$ls180.v:5650$1288_Y - connect \Y $and$ls180.v:5650$1289_Y - end - attribute \src "ls180.v:5652.45-5652.98" - cell $and $and$ls180.v:5652$1290 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5652$1290_Y - end - attribute \src "ls180.v:5652.44-5652.148" - cell $and $and$ls180.v:5652$1292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5652$1290_Y - connect \B $eq$ls180.v:5652$1291_Y - connect \Y $and$ls180.v:5652$1292_Y - end - attribute \src "ls180.v:5653.45-5653.101" - cell $and $and$ls180.v:5653$1294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5653$1293_Y - connect \Y $and$ls180.v:5653$1294_Y - end - attribute \src "ls180.v:5653.44-5653.151" - cell $and $and$ls180.v:5653$1296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5653$1294_Y - connect \B $eq$ls180.v:5653$1295_Y - connect \Y $and$ls180.v:5653$1296_Y - end - attribute \src "ls180.v:5655.45-5655.98" - cell $and $and$ls180.v:5655$1297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5655$1297_Y - end - attribute \src "ls180.v:5655.44-5655.148" - cell $and $and$ls180.v:5655$1299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5655$1297_Y - connect \B $eq$ls180.v:5655$1298_Y - connect \Y $and$ls180.v:5655$1299_Y - end - attribute \src "ls180.v:5656.45-5656.101" - cell $and $and$ls180.v:5656$1301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5656$1300_Y - connect \Y $and$ls180.v:5656$1301_Y - end - attribute \src "ls180.v:5656.44-5656.151" - cell $and $and$ls180.v:5656$1303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5656$1301_Y - connect \B $eq$ls180.v:5656$1302_Y - connect \Y $and$ls180.v:5656$1303_Y - end - attribute \src "ls180.v:5658.45-5658.98" - cell $and $and$ls180.v:5658$1304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5658$1304_Y - end - attribute \src "ls180.v:5658.44-5658.148" - cell $and $and$ls180.v:5658$1306 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5658$1304_Y - connect \B $eq$ls180.v:5658$1305_Y - connect \Y $and$ls180.v:5658$1306_Y - end - attribute \src "ls180.v:5659.45-5659.101" - cell $and $and$ls180.v:5659$1308 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5659$1307_Y - connect \Y $and$ls180.v:5659$1308_Y - end - attribute \src "ls180.v:5659.44-5659.151" - cell $and $and$ls180.v:5659$1310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5659$1308_Y - connect \B $eq$ls180.v:5659$1309_Y - connect \Y $and$ls180.v:5659$1310_Y - end - attribute \src "ls180.v:5661.43-5661.96" - cell $and $and$ls180.v:5661$1311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5661$1311_Y - end - attribute \src "ls180.v:5661.42-5661.146" - cell $and $and$ls180.v:5661$1313 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5661$1311_Y - connect \B $eq$ls180.v:5661$1312_Y - connect \Y $and$ls180.v:5661$1313_Y - end - attribute \src "ls180.v:5662.43-5662.99" - cell $and $and$ls180.v:5662$1315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5662$1314_Y - connect \Y $and$ls180.v:5662$1315_Y - end - attribute \src "ls180.v:5662.42-5662.149" - cell $and $and$ls180.v:5662$1317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5662$1315_Y - connect \B $eq$ls180.v:5662$1316_Y - connect \Y $and$ls180.v:5662$1317_Y - end - attribute \src "ls180.v:5664.47-5664.100" - cell $and $and$ls180.v:5664$1318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5664$1318_Y - end - attribute \src "ls180.v:5664.46-5664.150" - cell $and $and$ls180.v:5664$1320 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5664$1318_Y - connect \B $eq$ls180.v:5664$1319_Y - connect \Y $and$ls180.v:5664$1320_Y - end - attribute \src "ls180.v:5665.47-5665.103" - cell $and $and$ls180.v:5665$1322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5665$1321_Y - connect \Y $and$ls180.v:5665$1322_Y - end - attribute \src "ls180.v:5665.46-5665.153" - cell $and $and$ls180.v:5665$1324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5665$1322_Y - connect \B $eq$ls180.v:5665$1323_Y - connect \Y $and$ls180.v:5665$1324_Y - end - attribute \src "ls180.v:5667.47-5667.100" - cell $and $and$ls180.v:5667$1325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5667$1325_Y - end - attribute \src "ls180.v:5667.46-5667.151" - cell $and $and$ls180.v:5667$1327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5667$1325_Y - connect \B $eq$ls180.v:5667$1326_Y - connect \Y $and$ls180.v:5667$1327_Y - end - attribute \src "ls180.v:5668.47-5668.103" - cell $and $and$ls180.v:5668$1329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5668$1328_Y - connect \Y $and$ls180.v:5668$1329_Y - end - attribute \src "ls180.v:5668.46-5668.154" - cell $and $and$ls180.v:5668$1331 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5668$1329_Y - connect \B $eq$ls180.v:5668$1330_Y - connect \Y $and$ls180.v:5668$1331_Y - end - attribute \src "ls180.v:5670.47-5670.100" - cell $and $and$ls180.v:5670$1332 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5670$1332_Y - end - attribute \src "ls180.v:5670.46-5670.151" - cell $and $and$ls180.v:5670$1334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5670$1332_Y - connect \B $eq$ls180.v:5670$1333_Y - connect \Y $and$ls180.v:5670$1334_Y - end - attribute \src "ls180.v:5671.47-5671.103" - cell $and $and$ls180.v:5671$1336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5671$1335_Y - connect \Y $and$ls180.v:5671$1336_Y - end - attribute \src "ls180.v:5671.46-5671.154" - cell $and $and$ls180.v:5671$1338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5671$1336_Y - connect \B $eq$ls180.v:5671$1337_Y - connect \Y $and$ls180.v:5671$1338_Y - end - attribute \src "ls180.v:5673.47-5673.100" - cell $and $and$ls180.v:5673$1339 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5673$1339_Y - end - attribute \src "ls180.v:5673.46-5673.151" - cell $and $and$ls180.v:5673$1341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5673$1339_Y - connect \B $eq$ls180.v:5673$1340_Y - connect \Y $and$ls180.v:5673$1341_Y - end - attribute \src "ls180.v:5674.47-5674.103" - cell $and $and$ls180.v:5674$1343 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5674$1342_Y - connect \Y $and$ls180.v:5674$1343_Y - end - attribute \src "ls180.v:5674.46-5674.154" - cell $and $and$ls180.v:5674$1345 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5674$1343_Y - connect \B $eq$ls180.v:5674$1344_Y - connect \Y $and$ls180.v:5674$1345_Y - end - attribute \src "ls180.v:5676.47-5676.100" - cell $and $and$ls180.v:5676$1346 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5676$1346_Y - end - attribute \src "ls180.v:5676.46-5676.151" - cell $and $and$ls180.v:5676$1348 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5676$1346_Y - connect \B $eq$ls180.v:5676$1347_Y - connect \Y $and$ls180.v:5676$1348_Y - end - attribute \src "ls180.v:5677.47-5677.103" - cell $and $and$ls180.v:5677$1350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5677$1349_Y - connect \Y $and$ls180.v:5677$1350_Y - end - attribute \src "ls180.v:5677.46-5677.154" - cell $and $and$ls180.v:5677$1352 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5677$1350_Y - connect \B $eq$ls180.v:5677$1351_Y - connect \Y $and$ls180.v:5677$1352_Y - end - attribute \src "ls180.v:5679.47-5679.100" - cell $and $and$ls180.v:5679$1353 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5679$1353_Y - end - attribute \src "ls180.v:5679.46-5679.151" - cell $and $and$ls180.v:5679$1355 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5679$1353_Y - connect \B $eq$ls180.v:5679$1354_Y - connect \Y $and$ls180.v:5679$1355_Y - end - attribute \src "ls180.v:5680.47-5680.103" - cell $and $and$ls180.v:5680$1357 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5680$1356_Y - connect \Y $and$ls180.v:5680$1357_Y - end - attribute \src "ls180.v:5680.46-5680.154" - cell $and $and$ls180.v:5680$1359 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5680$1357_Y - connect \B $eq$ls180.v:5680$1358_Y - connect \Y $and$ls180.v:5680$1359_Y - end - attribute \src "ls180.v:5682.46-5682.99" - cell $and $and$ls180.v:5682$1360 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5682$1360_Y - end - attribute \src "ls180.v:5682.45-5682.150" - cell $and $and$ls180.v:5682$1362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5682$1360_Y - connect \B $eq$ls180.v:5682$1361_Y - connect \Y $and$ls180.v:5682$1362_Y - end - attribute \src "ls180.v:5683.46-5683.102" - cell $and $and$ls180.v:5683$1364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5683$1363_Y - connect \Y $and$ls180.v:5683$1364_Y - end - attribute \src "ls180.v:5683.45-5683.153" - cell $and $and$ls180.v:5683$1366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5683$1364_Y - connect \B $eq$ls180.v:5683$1365_Y - connect \Y $and$ls180.v:5683$1366_Y - end - attribute \src "ls180.v:5685.46-5685.99" - cell $and $and$ls180.v:5685$1367 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5685$1367_Y - end - attribute \src "ls180.v:5685.45-5685.150" - cell $and $and$ls180.v:5685$1369 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5685$1367_Y - connect \B $eq$ls180.v:5685$1368_Y - connect \Y $and$ls180.v:5685$1369_Y - end - attribute \src "ls180.v:5686.46-5686.102" - cell $and $and$ls180.v:5686$1371 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5686$1370_Y - connect \Y $and$ls180.v:5686$1371_Y - end - attribute \src "ls180.v:5686.45-5686.153" - cell $and $and$ls180.v:5686$1373 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5686$1371_Y - connect \B $eq$ls180.v:5686$1372_Y - connect \Y $and$ls180.v:5686$1373_Y - end - attribute \src "ls180.v:5688.46-5688.99" - cell $and $and$ls180.v:5688$1374 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5688$1374_Y - end - attribute \src "ls180.v:5688.45-5688.150" - cell $and $and$ls180.v:5688$1376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5688$1374_Y - connect \B $eq$ls180.v:5688$1375_Y - connect \Y $and$ls180.v:5688$1376_Y - end - attribute \src "ls180.v:5689.46-5689.102" - cell $and $and$ls180.v:5689$1378 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5689$1377_Y - connect \Y $and$ls180.v:5689$1378_Y - end - attribute \src "ls180.v:5689.45-5689.153" - cell $and $and$ls180.v:5689$1380 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5689$1378_Y - connect \B $eq$ls180.v:5689$1379_Y - connect \Y $and$ls180.v:5689$1380_Y - end - attribute \src "ls180.v:5691.46-5691.99" - cell $and $and$ls180.v:5691$1381 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5691$1381_Y - end - attribute \src "ls180.v:5691.45-5691.150" - cell $and $and$ls180.v:5691$1383 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5691$1381_Y - connect \B $eq$ls180.v:5691$1382_Y - connect \Y $and$ls180.v:5691$1383_Y - end - attribute \src "ls180.v:5692.46-5692.102" - cell $and $and$ls180.v:5692$1385 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5692$1384_Y - connect \Y $and$ls180.v:5692$1385_Y - end - attribute \src "ls180.v:5692.45-5692.153" - cell $and $and$ls180.v:5692$1387 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5692$1385_Y - connect \B $eq$ls180.v:5692$1386_Y - connect \Y $and$ls180.v:5692$1387_Y - end - attribute \src "ls180.v:5694.46-5694.99" - cell $and $and$ls180.v:5694$1388 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5694$1388_Y - end - attribute \src "ls180.v:5694.45-5694.150" - cell $and $and$ls180.v:5694$1390 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5694$1388_Y - connect \B $eq$ls180.v:5694$1389_Y - connect \Y $and$ls180.v:5694$1390_Y - end - attribute \src "ls180.v:5695.46-5695.102" - cell $and $and$ls180.v:5695$1392 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5695$1391_Y - connect \Y $and$ls180.v:5695$1392_Y - end - attribute \src "ls180.v:5695.45-5695.153" - cell $and $and$ls180.v:5695$1394 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5695$1392_Y - connect \B $eq$ls180.v:5695$1393_Y - connect \Y $and$ls180.v:5695$1394_Y - end - attribute \src "ls180.v:5697.46-5697.99" - cell $and $and$ls180.v:5697$1395 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5697$1395_Y - end - attribute \src "ls180.v:5697.45-5697.150" - cell $and $and$ls180.v:5697$1397 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5697$1395_Y - connect \B $eq$ls180.v:5697$1396_Y - connect \Y $and$ls180.v:5697$1397_Y - end - attribute \src "ls180.v:5698.46-5698.102" - cell $and $and$ls180.v:5698$1399 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5698$1398_Y - connect \Y $and$ls180.v:5698$1399_Y - end - attribute \src "ls180.v:5698.45-5698.153" - cell $and $and$ls180.v:5698$1401 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5698$1399_Y - connect \B $eq$ls180.v:5698$1400_Y - connect \Y $and$ls180.v:5698$1401_Y - end - attribute \src "ls180.v:5700.46-5700.99" - cell $and $and$ls180.v:5700$1402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5700$1402_Y - end - attribute \src "ls180.v:5700.45-5700.150" - cell $and $and$ls180.v:5700$1404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5700$1402_Y - connect \B $eq$ls180.v:5700$1403_Y - connect \Y $and$ls180.v:5700$1404_Y - end - attribute \src "ls180.v:5701.46-5701.102" - cell $and $and$ls180.v:5701$1406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5701$1405_Y - connect \Y $and$ls180.v:5701$1406_Y - end - attribute \src "ls180.v:5701.45-5701.153" - cell $and $and$ls180.v:5701$1408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5701$1406_Y - connect \B $eq$ls180.v:5701$1407_Y - connect \Y $and$ls180.v:5701$1408_Y - end - attribute \src "ls180.v:5703.46-5703.99" - cell $and $and$ls180.v:5703$1409 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5703$1409_Y - end - attribute \src "ls180.v:5703.45-5703.150" - cell $and $and$ls180.v:5703$1411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5703$1409_Y - connect \B $eq$ls180.v:5703$1410_Y - connect \Y $and$ls180.v:5703$1411_Y - end - attribute \src "ls180.v:5704.46-5704.102" - cell $and $and$ls180.v:5704$1413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5704$1412_Y - connect \Y $and$ls180.v:5704$1413_Y - end - attribute \src "ls180.v:5704.45-5704.153" - cell $and $and$ls180.v:5704$1415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5704$1413_Y - connect \B $eq$ls180.v:5704$1414_Y - connect \Y $and$ls180.v:5704$1415_Y - end - attribute \src "ls180.v:5706.46-5706.99" - cell $and $and$ls180.v:5706$1416 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5706$1416_Y - end - attribute \src "ls180.v:5706.45-5706.150" - cell $and $and$ls180.v:5706$1418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5706$1416_Y - connect \B $eq$ls180.v:5706$1417_Y - connect \Y $and$ls180.v:5706$1418_Y - end - attribute \src "ls180.v:5707.46-5707.102" - cell $and $and$ls180.v:5707$1420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5707$1419_Y - connect \Y $and$ls180.v:5707$1420_Y - end - attribute \src "ls180.v:5707.45-5707.153" - cell $and $and$ls180.v:5707$1422 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5707$1420_Y - connect \B $eq$ls180.v:5707$1421_Y - connect \Y $and$ls180.v:5707$1422_Y - end - attribute \src "ls180.v:5709.46-5709.99" - cell $and $and$ls180.v:5709$1423 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5709$1423_Y - end - attribute \src "ls180.v:5709.45-5709.150" - cell $and $and$ls180.v:5709$1425 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5709$1423_Y - connect \B $eq$ls180.v:5709$1424_Y - connect \Y $and$ls180.v:5709$1425_Y - end - attribute \src "ls180.v:5710.46-5710.102" - cell $and $and$ls180.v:5710$1427 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5710$1426_Y - connect \Y $and$ls180.v:5710$1427_Y - end - attribute \src "ls180.v:5710.45-5710.153" - cell $and $and$ls180.v:5710$1429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5710$1427_Y - connect \B $eq$ls180.v:5710$1428_Y - connect \Y $and$ls180.v:5710$1429_Y - end - attribute \src "ls180.v:5712.42-5712.95" - cell $and $and$ls180.v:5712$1430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5712$1430_Y - end - attribute \src "ls180.v:5712.41-5712.146" - cell $and $and$ls180.v:5712$1432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5712$1430_Y - connect \B $eq$ls180.v:5712$1431_Y - connect \Y $and$ls180.v:5712$1432_Y - end - attribute \src "ls180.v:5713.42-5713.98" - cell $and $and$ls180.v:5713$1434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5713$1433_Y - connect \Y $and$ls180.v:5713$1434_Y - end - attribute \src "ls180.v:5713.41-5713.149" - cell $and $and$ls180.v:5713$1436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5713$1434_Y - connect \B $eq$ls180.v:5713$1435_Y - connect \Y $and$ls180.v:5713$1436_Y - end - attribute \src "ls180.v:5715.43-5715.96" - cell $and $and$ls180.v:5715$1437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5715$1437_Y - end - attribute \src "ls180.v:5715.42-5715.147" - cell $and $and$ls180.v:5715$1439 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5715$1437_Y - connect \B $eq$ls180.v:5715$1438_Y - connect \Y $and$ls180.v:5715$1439_Y - end - attribute \src "ls180.v:5716.43-5716.99" - cell $and $and$ls180.v:5716$1441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5716$1440_Y - connect \Y $and$ls180.v:5716$1441_Y - end - attribute \src "ls180.v:5716.42-5716.150" - cell $and $and$ls180.v:5716$1443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5716$1441_Y - connect \B $eq$ls180.v:5716$1442_Y - connect \Y $and$ls180.v:5716$1443_Y - end - attribute \src "ls180.v:5718.46-5718.99" - cell $and $and$ls180.v:5718$1444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5718$1444_Y - end - attribute \src "ls180.v:5718.45-5718.150" - cell $and $and$ls180.v:5718$1446 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5718$1444_Y - connect \B $eq$ls180.v:5718$1445_Y - connect \Y $and$ls180.v:5718$1446_Y - end - attribute \src "ls180.v:5719.46-5719.102" - cell $and $and$ls180.v:5719$1448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5719$1447_Y - connect \Y $and$ls180.v:5719$1448_Y - end - attribute \src "ls180.v:5719.45-5719.153" - cell $and $and$ls180.v:5719$1450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5719$1448_Y - connect \B $eq$ls180.v:5719$1449_Y - connect \Y $and$ls180.v:5719$1450_Y - end - attribute \src "ls180.v:5721.46-5721.99" - cell $and $and$ls180.v:5721$1451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5721$1451_Y - end - attribute \src "ls180.v:5721.45-5721.150" - cell $and $and$ls180.v:5721$1453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5721$1451_Y - connect \B $eq$ls180.v:5721$1452_Y - connect \Y $and$ls180.v:5721$1453_Y - end - attribute \src "ls180.v:5722.46-5722.102" - cell $and $and$ls180.v:5722$1455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5722$1454_Y - connect \Y $and$ls180.v:5722$1455_Y - end - attribute \src "ls180.v:5722.45-5722.153" - cell $and $and$ls180.v:5722$1457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5722$1455_Y - connect \B $eq$ls180.v:5722$1456_Y - connect \Y $and$ls180.v:5722$1457_Y - end - attribute \src "ls180.v:5724.45-5724.98" - cell $and $and$ls180.v:5724$1458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5724$1458_Y - end - attribute \src "ls180.v:5724.44-5724.149" - cell $and $and$ls180.v:5724$1460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5724$1458_Y - connect \B $eq$ls180.v:5724$1459_Y - connect \Y $and$ls180.v:5724$1460_Y - end - attribute \src "ls180.v:5725.45-5725.101" - cell $and $and$ls180.v:5725$1462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5725$1461_Y - connect \Y $and$ls180.v:5725$1462_Y - end - attribute \src "ls180.v:5725.44-5725.152" - cell $and $and$ls180.v:5725$1464 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5725$1462_Y - connect \B $eq$ls180.v:5725$1463_Y - connect \Y $and$ls180.v:5725$1464_Y - end - attribute \src "ls180.v:5727.45-5727.98" - cell $and $and$ls180.v:5727$1465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5727$1465_Y - end - attribute \src "ls180.v:5727.44-5727.149" - cell $and $and$ls180.v:5727$1467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5727$1465_Y - connect \B $eq$ls180.v:5727$1466_Y - connect \Y $and$ls180.v:5727$1467_Y - end - attribute \src "ls180.v:5728.45-5728.101" - cell $and $and$ls180.v:5728$1469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5728$1468_Y - connect \Y $and$ls180.v:5728$1469_Y - end - attribute \src "ls180.v:5728.44-5728.152" - cell $and $and$ls180.v:5728$1471 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5728$1469_Y - connect \B $eq$ls180.v:5728$1470_Y - connect \Y $and$ls180.v:5728$1471_Y - end - attribute \src "ls180.v:5730.45-5730.98" - cell $and $and$ls180.v:5730$1472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5730$1472_Y - end - attribute \src "ls180.v:5730.44-5730.149" - cell $and $and$ls180.v:5730$1474 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5730$1472_Y - connect \B $eq$ls180.v:5730$1473_Y - connect \Y $and$ls180.v:5730$1474_Y - end - attribute \src "ls180.v:5731.45-5731.101" - cell $and $and$ls180.v:5731$1476 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5731$1475_Y - connect \Y $and$ls180.v:5731$1476_Y - end - attribute \src "ls180.v:5731.44-5731.152" - cell $and $and$ls180.v:5731$1478 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5731$1476_Y - connect \B $eq$ls180.v:5731$1477_Y - connect \Y $and$ls180.v:5731$1478_Y - end - attribute \src "ls180.v:5733.45-5733.98" - cell $and $and$ls180.v:5733$1479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5733$1479_Y - end - attribute \src "ls180.v:5733.44-5733.149" - cell $and $and$ls180.v:5733$1481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5733$1479_Y - connect \B $eq$ls180.v:5733$1480_Y - connect \Y $and$ls180.v:5733$1481_Y - end - attribute \src "ls180.v:5734.45-5734.101" - cell $and $and$ls180.v:5734$1483 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5734$1482_Y - connect \Y $and$ls180.v:5734$1483_Y - end - attribute \src "ls180.v:5734.44-5734.152" - cell $and $and$ls180.v:5734$1485 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5734$1483_Y - connect \B $eq$ls180.v:5734$1484_Y - connect \Y $and$ls180.v:5734$1485_Y - end - attribute \src "ls180.v:5772.42-5772.95" - cell $and $and$ls180.v:5772$1487 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5772$1487_Y - end - attribute \src "ls180.v:5772.41-5772.145" - cell $and $and$ls180.v:5772$1489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5772$1487_Y - connect \B $eq$ls180.v:5772$1488_Y - connect \Y $and$ls180.v:5772$1489_Y - end - attribute \src "ls180.v:5773.42-5773.98" - cell $and $and$ls180.v:5773$1491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5773$1490_Y - connect \Y $and$ls180.v:5773$1491_Y - end - attribute \src "ls180.v:5773.41-5773.148" - cell $and $and$ls180.v:5773$1493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5773$1491_Y - connect \B $eq$ls180.v:5773$1492_Y - connect \Y $and$ls180.v:5773$1493_Y - end - attribute \src "ls180.v:5775.42-5775.95" - cell $and $and$ls180.v:5775$1494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5775$1494_Y - end - attribute \src "ls180.v:5775.41-5775.145" - cell $and $and$ls180.v:5775$1496 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5775$1494_Y - connect \B $eq$ls180.v:5775$1495_Y - connect \Y $and$ls180.v:5775$1496_Y - end - attribute \src "ls180.v:5776.42-5776.98" - cell $and $and$ls180.v:5776$1498 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5776$1497_Y - connect \Y $and$ls180.v:5776$1498_Y - end - attribute \src "ls180.v:5776.41-5776.148" - cell $and $and$ls180.v:5776$1500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5776$1498_Y - connect \B $eq$ls180.v:5776$1499_Y - connect \Y $and$ls180.v:5776$1500_Y - end - attribute \src "ls180.v:5778.42-5778.95" - cell $and $and$ls180.v:5778$1501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5778$1501_Y - end - attribute \src "ls180.v:5778.41-5778.145" - cell $and $and$ls180.v:5778$1503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5778$1501_Y - connect \B $eq$ls180.v:5778$1502_Y - connect \Y $and$ls180.v:5778$1503_Y - end - attribute \src "ls180.v:5779.42-5779.98" - cell $and $and$ls180.v:5779$1505 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5779$1504_Y - connect \Y $and$ls180.v:5779$1505_Y - end - attribute \src "ls180.v:5779.41-5779.148" - cell $and $and$ls180.v:5779$1507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5779$1505_Y - connect \B $eq$ls180.v:5779$1506_Y - connect \Y $and$ls180.v:5779$1507_Y - end - attribute \src "ls180.v:5781.42-5781.95" - cell $and $and$ls180.v:5781$1508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5781$1508_Y - end - attribute \src "ls180.v:5781.41-5781.145" - cell $and $and$ls180.v:5781$1510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5781$1508_Y - connect \B $eq$ls180.v:5781$1509_Y - connect \Y $and$ls180.v:5781$1510_Y - end - attribute \src "ls180.v:5782.42-5782.98" - cell $and $and$ls180.v:5782$1512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5782$1511_Y - connect \Y $and$ls180.v:5782$1512_Y - end - attribute \src "ls180.v:5782.41-5782.148" - cell $and $and$ls180.v:5782$1514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5782$1512_Y - connect \B $eq$ls180.v:5782$1513_Y - connect \Y $and$ls180.v:5782$1514_Y - end - attribute \src "ls180.v:5784.42-5784.95" - cell $and $and$ls180.v:5784$1515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5784$1515_Y - end - attribute \src "ls180.v:5784.41-5784.145" - cell $and $and$ls180.v:5784$1517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5784$1515_Y - connect \B $eq$ls180.v:5784$1516_Y - connect \Y $and$ls180.v:5784$1517_Y - end - attribute \src "ls180.v:5785.42-5785.98" - cell $and $and$ls180.v:5785$1519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5785$1518_Y - connect \Y $and$ls180.v:5785$1519_Y - end - attribute \src "ls180.v:5785.41-5785.148" - cell $and $and$ls180.v:5785$1521 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5785$1519_Y - connect \B $eq$ls180.v:5785$1520_Y - connect \Y $and$ls180.v:5785$1521_Y - end - attribute \src "ls180.v:5787.42-5787.95" - cell $and $and$ls180.v:5787$1522 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5787$1522_Y - end - attribute \src "ls180.v:5787.41-5787.145" - cell $and $and$ls180.v:5787$1524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5787$1522_Y - connect \B $eq$ls180.v:5787$1523_Y - connect \Y $and$ls180.v:5787$1524_Y - end - attribute \src "ls180.v:5788.42-5788.98" - cell $and $and$ls180.v:5788$1526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5788$1525_Y - connect \Y $and$ls180.v:5788$1526_Y - end - attribute \src "ls180.v:5788.41-5788.148" - cell $and $and$ls180.v:5788$1528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5788$1526_Y - connect \B $eq$ls180.v:5788$1527_Y - connect \Y $and$ls180.v:5788$1528_Y - end - attribute \src "ls180.v:5790.42-5790.95" - cell $and $and$ls180.v:5790$1529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5790$1529_Y - end - attribute \src "ls180.v:5790.41-5790.145" - cell $and $and$ls180.v:5790$1531 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5790$1529_Y - connect \B $eq$ls180.v:5790$1530_Y - connect \Y $and$ls180.v:5790$1531_Y - end - attribute \src "ls180.v:5791.42-5791.98" - cell $and $and$ls180.v:5791$1533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5791$1532_Y - connect \Y $and$ls180.v:5791$1533_Y - end - attribute \src "ls180.v:5791.41-5791.148" - cell $and $and$ls180.v:5791$1535 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5791$1533_Y - connect \B $eq$ls180.v:5791$1534_Y - connect \Y $and$ls180.v:5791$1535_Y - end - attribute \src "ls180.v:5793.42-5793.95" - cell $and $and$ls180.v:5793$1536 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5793$1536_Y - end - attribute \src "ls180.v:5793.41-5793.145" - cell $and $and$ls180.v:5793$1538 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5793$1536_Y - connect \B $eq$ls180.v:5793$1537_Y - connect \Y $and$ls180.v:5793$1538_Y - end - attribute \src "ls180.v:5794.42-5794.98" - cell $and $and$ls180.v:5794$1540 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5794$1539_Y - connect \Y $and$ls180.v:5794$1540_Y - end - attribute \src "ls180.v:5794.41-5794.148" - cell $and $and$ls180.v:5794$1542 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5794$1540_Y - connect \B $eq$ls180.v:5794$1541_Y - connect \Y $and$ls180.v:5794$1542_Y - end - attribute \src "ls180.v:5796.44-5796.97" - cell $and $and$ls180.v:5796$1543 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5796$1543_Y - end - attribute \src "ls180.v:5796.43-5796.147" - cell $and $and$ls180.v:5796$1545 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5796$1543_Y - connect \B $eq$ls180.v:5796$1544_Y - connect \Y $and$ls180.v:5796$1545_Y - end - attribute \src "ls180.v:5797.44-5797.100" - cell $and $and$ls180.v:5797$1547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5797$1546_Y - connect \Y $and$ls180.v:5797$1547_Y - end - attribute \src "ls180.v:5797.43-5797.150" - cell $and $and$ls180.v:5797$1549 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5797$1547_Y - connect \B $eq$ls180.v:5797$1548_Y - connect \Y $and$ls180.v:5797$1549_Y - end - attribute \src "ls180.v:5799.44-5799.97" - cell $and $and$ls180.v:5799$1550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5799$1550_Y - end - attribute \src "ls180.v:5799.43-5799.147" - cell $and $and$ls180.v:5799$1552 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5799$1550_Y - connect \B $eq$ls180.v:5799$1551_Y - connect \Y $and$ls180.v:5799$1552_Y - end - attribute \src "ls180.v:5800.44-5800.100" - cell $and $and$ls180.v:5800$1554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5800$1553_Y - connect \Y $and$ls180.v:5800$1554_Y - end - attribute \src "ls180.v:5800.43-5800.150" - cell $and $and$ls180.v:5800$1556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5800$1554_Y - connect \B $eq$ls180.v:5800$1555_Y - connect \Y $and$ls180.v:5800$1556_Y - end - attribute \src "ls180.v:5802.44-5802.97" - cell $and $and$ls180.v:5802$1557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5802$1557_Y - end - attribute \src "ls180.v:5802.43-5802.148" - cell $and $and$ls180.v:5802$1559 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5802$1557_Y - connect \B $eq$ls180.v:5802$1558_Y - connect \Y $and$ls180.v:5802$1559_Y - end - attribute \src "ls180.v:5803.44-5803.100" - cell $and $and$ls180.v:5803$1561 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5803$1560_Y - connect \Y $and$ls180.v:5803$1561_Y - end - attribute \src "ls180.v:5803.43-5803.151" - cell $and $and$ls180.v:5803$1563 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5803$1561_Y - connect \B $eq$ls180.v:5803$1562_Y - connect \Y $and$ls180.v:5803$1563_Y - end - attribute \src "ls180.v:5805.44-5805.97" - cell $and $and$ls180.v:5805$1564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5805$1564_Y - end - attribute \src "ls180.v:5805.43-5805.148" - cell $and $and$ls180.v:5805$1566 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5805$1564_Y - connect \B $eq$ls180.v:5805$1565_Y - connect \Y $and$ls180.v:5805$1566_Y - end - attribute \src "ls180.v:5806.44-5806.100" - cell $and $and$ls180.v:5806$1568 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5806$1567_Y - connect \Y $and$ls180.v:5806$1568_Y - end - attribute \src "ls180.v:5806.43-5806.151" - cell $and $and$ls180.v:5806$1570 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5806$1568_Y - connect \B $eq$ls180.v:5806$1569_Y - connect \Y $and$ls180.v:5806$1570_Y - end - attribute \src "ls180.v:5808.44-5808.97" - cell $and $and$ls180.v:5808$1571 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5808$1571_Y - end - attribute \src "ls180.v:5808.43-5808.148" - cell $and $and$ls180.v:5808$1573 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5808$1571_Y - connect \B $eq$ls180.v:5808$1572_Y - connect \Y $and$ls180.v:5808$1573_Y - end - attribute \src "ls180.v:5809.44-5809.100" - cell $and $and$ls180.v:5809$1575 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5809$1574_Y - connect \Y $and$ls180.v:5809$1575_Y - end - attribute \src "ls180.v:5809.43-5809.151" - cell $and $and$ls180.v:5809$1577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5809$1575_Y - connect \B $eq$ls180.v:5809$1576_Y - connect \Y $and$ls180.v:5809$1577_Y - end - attribute \src "ls180.v:5811.41-5811.94" - cell $and $and$ls180.v:5811$1578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5811$1578_Y - end - attribute \src "ls180.v:5811.40-5811.145" - cell $and $and$ls180.v:5811$1580 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5811$1578_Y - connect \B $eq$ls180.v:5811$1579_Y - connect \Y $and$ls180.v:5811$1580_Y - end - attribute \src "ls180.v:5812.41-5812.97" - cell $and $and$ls180.v:5812$1582 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5812$1581_Y - connect \Y $and$ls180.v:5812$1582_Y - end - attribute \src "ls180.v:5812.40-5812.148" - cell $and $and$ls180.v:5812$1584 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5812$1582_Y - connect \B $eq$ls180.v:5812$1583_Y - connect \Y $and$ls180.v:5812$1584_Y - end - attribute \src "ls180.v:5814.42-5814.95" - cell $and $and$ls180.v:5814$1585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5814$1585_Y - end - attribute \src "ls180.v:5814.41-5814.146" - cell $and $and$ls180.v:5814$1587 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5814$1585_Y - connect \B $eq$ls180.v:5814$1586_Y - connect \Y $and$ls180.v:5814$1587_Y - end - attribute \src "ls180.v:5815.42-5815.98" - cell $and $and$ls180.v:5815$1589 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5815$1588_Y - connect \Y $and$ls180.v:5815$1589_Y - end - attribute \src "ls180.v:5815.41-5815.149" - cell $and $and$ls180.v:5815$1591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5815$1589_Y - connect \B $eq$ls180.v:5815$1590_Y - connect \Y $and$ls180.v:5815$1591_Y - end - attribute \src "ls180.v:5817.44-5817.97" - cell $and $and$ls180.v:5817$1592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5817$1592_Y - end - attribute \src "ls180.v:5817.43-5817.148" - cell $and $and$ls180.v:5817$1594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5817$1592_Y - connect \B $eq$ls180.v:5817$1593_Y - connect \Y $and$ls180.v:5817$1594_Y - end - attribute \src "ls180.v:5818.44-5818.100" - cell $and $and$ls180.v:5818$1596 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5818$1595_Y - connect \Y $and$ls180.v:5818$1596_Y - end - attribute \src "ls180.v:5818.43-5818.151" - cell $and $and$ls180.v:5818$1598 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5818$1596_Y - connect \B $eq$ls180.v:5818$1597_Y - connect \Y $and$ls180.v:5818$1598_Y - end - attribute \src "ls180.v:5820.44-5820.97" - cell $and $and$ls180.v:5820$1599 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5820$1599_Y - end - attribute \src "ls180.v:5820.43-5820.148" - cell $and $and$ls180.v:5820$1601 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5820$1599_Y - connect \B $eq$ls180.v:5820$1600_Y - connect \Y $and$ls180.v:5820$1601_Y - end - attribute \src "ls180.v:5821.44-5821.100" - cell $and $and$ls180.v:5821$1603 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5821$1602_Y - connect \Y $and$ls180.v:5821$1603_Y - end - attribute \src "ls180.v:5821.43-5821.151" - cell $and $and$ls180.v:5821$1605 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5821$1603_Y - connect \B $eq$ls180.v:5821$1604_Y - connect \Y $and$ls180.v:5821$1605_Y - end - attribute \src "ls180.v:5823.44-5823.97" - cell $and $and$ls180.v:5823$1606 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5823$1606_Y - end - attribute \src "ls180.v:5823.43-5823.148" - cell $and $and$ls180.v:5823$1608 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5823$1606_Y - connect \B $eq$ls180.v:5823$1607_Y - connect \Y $and$ls180.v:5823$1608_Y - end - attribute \src "ls180.v:5824.44-5824.100" - cell $and $and$ls180.v:5824$1610 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5824$1609_Y - connect \Y $and$ls180.v:5824$1610_Y - end - attribute \src "ls180.v:5824.43-5824.151" - cell $and $and$ls180.v:5824$1612 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5824$1610_Y - connect \B $eq$ls180.v:5824$1611_Y - connect \Y $and$ls180.v:5824$1612_Y - end - attribute \src "ls180.v:5826.44-5826.97" - cell $and $and$ls180.v:5826$1613 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5826$1613_Y - end - attribute \src "ls180.v:5826.43-5826.148" - cell $and $and$ls180.v:5826$1615 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5826$1613_Y - connect \B $eq$ls180.v:5826$1614_Y - connect \Y $and$ls180.v:5826$1615_Y - end - attribute \src "ls180.v:5827.44-5827.100" - cell $and $and$ls180.v:5827$1617 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5827$1616_Y - connect \Y $and$ls180.v:5827$1617_Y - end - attribute \src "ls180.v:5827.43-5827.151" - cell $and $and$ls180.v:5827$1619 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5827$1617_Y - connect \B $eq$ls180.v:5827$1618_Y - connect \Y $and$ls180.v:5827$1619_Y - end - attribute \src "ls180.v:5851.44-5851.97" - cell $and $and$ls180.v:5851$1621 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5851$1621_Y - end - attribute \src "ls180.v:5851.43-5851.147" - cell $and $and$ls180.v:5851$1623 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5851$1621_Y - connect \B $eq$ls180.v:5851$1622_Y - connect \Y $and$ls180.v:5851$1623_Y - end - attribute \src "ls180.v:5852.44-5852.100" - cell $and $and$ls180.v:5852$1625 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:5852$1624_Y - connect \Y $and$ls180.v:5852$1625_Y - end - attribute \src "ls180.v:5852.43-5852.150" - cell $and $and$ls180.v:5852$1627 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5852$1625_Y - connect \B $eq$ls180.v:5852$1626_Y - connect \Y $and$ls180.v:5852$1627_Y - end - attribute \src "ls180.v:5854.49-5854.102" - cell $and $and$ls180.v:5854$1628 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5854$1628_Y - end - attribute \src "ls180.v:5854.48-5854.152" - cell $and $and$ls180.v:5854$1630 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5854$1628_Y - connect \B $eq$ls180.v:5854$1629_Y - connect \Y $and$ls180.v:5854$1630_Y - end - attribute \src "ls180.v:5855.49-5855.105" - cell $and $and$ls180.v:5855$1632 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:5855$1631_Y - connect \Y $and$ls180.v:5855$1632_Y - end - attribute \src "ls180.v:5855.48-5855.155" - cell $and $and$ls180.v:5855$1634 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5855$1632_Y - connect \B $eq$ls180.v:5855$1633_Y - connect \Y $and$ls180.v:5855$1634_Y - end - attribute \src "ls180.v:5857.49-5857.102" - cell $and $and$ls180.v:5857$1635 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5857$1635_Y - end - attribute \src "ls180.v:5857.48-5857.152" - cell $and $and$ls180.v:5857$1637 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5857$1635_Y - connect \B $eq$ls180.v:5857$1636_Y - connect \Y $and$ls180.v:5857$1637_Y - end - attribute \src "ls180.v:5858.49-5858.105" - cell $and $and$ls180.v:5858$1639 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:5858$1638_Y - connect \Y $and$ls180.v:5858$1639_Y - end - attribute \src "ls180.v:5858.48-5858.155" - cell $and $and$ls180.v:5858$1641 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5858$1639_Y - connect \B $eq$ls180.v:5858$1640_Y - connect \Y $and$ls180.v:5858$1641_Y - end - attribute \src "ls180.v:5860.43-5860.96" - cell $and $and$ls180.v:5860$1642 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5860$1642_Y - end - attribute \src "ls180.v:5860.42-5860.146" - cell $and $and$ls180.v:5860$1644 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5860$1642_Y - connect \B $eq$ls180.v:5860$1643_Y - connect \Y $and$ls180.v:5860$1644_Y - end - attribute \src "ls180.v:5861.43-5861.99" - cell $and $and$ls180.v:5861$1646 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:5861$1645_Y - connect \Y $and$ls180.v:5861$1646_Y - end - attribute \src "ls180.v:5861.42-5861.149" - cell $and $and$ls180.v:5861$1648 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5861$1646_Y - connect \B $eq$ls180.v:5861$1647_Y - connect \Y $and$ls180.v:5861$1648_Y - end - attribute \src "ls180.v:5868.46-5868.99" - cell $and $and$ls180.v:5868$1650 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:5868$1650_Y - end - attribute \src "ls180.v:5868.45-5868.149" - cell $and $and$ls180.v:5868$1652 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5868$1650_Y - connect \B $eq$ls180.v:5868$1651_Y - connect \Y $and$ls180.v:5868$1652_Y - end - attribute \src "ls180.v:5869.46-5869.102" - cell $and $and$ls180.v:5869$1654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:5869$1653_Y - connect \Y $and$ls180.v:5869$1654_Y - end - attribute \src "ls180.v:5869.45-5869.152" - cell $and $and$ls180.v:5869$1656 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5869$1654_Y - connect \B $eq$ls180.v:5869$1655_Y - connect \Y $and$ls180.v:5869$1656_Y - end - attribute \src "ls180.v:5871.50-5871.103" - cell $and $and$ls180.v:5871$1657 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:5871$1657_Y - end - attribute \src "ls180.v:5871.49-5871.153" - cell $and $and$ls180.v:5871$1659 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5871$1657_Y - connect \B $eq$ls180.v:5871$1658_Y - connect \Y $and$ls180.v:5871$1659_Y - end - attribute \src "ls180.v:5872.50-5872.106" - cell $and $and$ls180.v:5872$1661 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:5872$1660_Y - connect \Y $and$ls180.v:5872$1661_Y - end - attribute \src "ls180.v:5872.49-5872.156" - cell $and $and$ls180.v:5872$1663 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5872$1661_Y - connect \B $eq$ls180.v:5872$1662_Y - connect \Y $and$ls180.v:5872$1663_Y - end - attribute \src "ls180.v:5874.40-5874.93" - cell $and $and$ls180.v:5874$1664 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:5874$1664_Y - end - attribute \src "ls180.v:5874.39-5874.143" - cell $and $and$ls180.v:5874$1666 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5874$1664_Y - connect \B $eq$ls180.v:5874$1665_Y - connect \Y $and$ls180.v:5874$1666_Y - end - attribute \src "ls180.v:5875.40-5875.96" - cell $and $and$ls180.v:5875$1668 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:5875$1667_Y - connect \Y $and$ls180.v:5875$1668_Y - end - attribute \src "ls180.v:5875.39-5875.146" - cell $and $and$ls180.v:5875$1670 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5875$1668_Y - connect \B $eq$ls180.v:5875$1669_Y - connect \Y $and$ls180.v:5875$1670_Y - end - attribute \src "ls180.v:5877.50-5877.103" - cell $and $and$ls180.v:5877$1671 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:5877$1671_Y - end - attribute \src "ls180.v:5877.49-5877.153" - cell $and $and$ls180.v:5877$1673 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5877$1671_Y - connect \B $eq$ls180.v:5877$1672_Y - connect \Y $and$ls180.v:5877$1673_Y - end - attribute \src "ls180.v:5878.50-5878.106" - cell $and $and$ls180.v:5878$1675 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:5878$1674_Y - connect \Y $and$ls180.v:5878$1675_Y - end - attribute \src "ls180.v:5878.49-5878.156" - cell $and $and$ls180.v:5878$1677 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5878$1675_Y - connect \B $eq$ls180.v:5878$1676_Y - connect \Y $and$ls180.v:5878$1677_Y - end - attribute \src "ls180.v:5880.50-5880.103" - cell $and $and$ls180.v:5880$1678 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:5880$1678_Y - end - attribute \src "ls180.v:5880.49-5880.153" - cell $and $and$ls180.v:5880$1680 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5880$1678_Y - connect \B $eq$ls180.v:5880$1679_Y - connect \Y $and$ls180.v:5880$1680_Y - end - attribute \src "ls180.v:5881.50-5881.106" - cell $and $and$ls180.v:5881$1682 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:5881$1681_Y - connect \Y $and$ls180.v:5881$1682_Y - end - attribute \src "ls180.v:5881.49-5881.156" - cell $and $and$ls180.v:5881$1684 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5881$1682_Y - connect \B $eq$ls180.v:5881$1683_Y - connect \Y $and$ls180.v:5881$1684_Y - end - attribute \src "ls180.v:5883.51-5883.104" - cell $and $and$ls180.v:5883$1685 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:5883$1685_Y - end - attribute \src "ls180.v:5883.50-5883.154" - cell $and $and$ls180.v:5883$1687 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5883$1685_Y - connect \B $eq$ls180.v:5883$1686_Y - connect \Y $and$ls180.v:5883$1687_Y - end - attribute \src "ls180.v:5884.51-5884.107" - cell $and $and$ls180.v:5884$1689 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:5884$1688_Y - connect \Y $and$ls180.v:5884$1689_Y - end - attribute \src "ls180.v:5884.50-5884.157" - cell $and $and$ls180.v:5884$1691 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5884$1689_Y - connect \B $eq$ls180.v:5884$1690_Y - connect \Y $and$ls180.v:5884$1691_Y - end - attribute \src "ls180.v:5886.49-5886.102" - cell $and $and$ls180.v:5886$1692 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:5886$1692_Y - end - attribute \src "ls180.v:5886.48-5886.152" - cell $and $and$ls180.v:5886$1694 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5886$1692_Y - connect \B $eq$ls180.v:5886$1693_Y - connect \Y $and$ls180.v:5886$1694_Y - end - attribute \src "ls180.v:5887.49-5887.105" - cell $and $and$ls180.v:5887$1696 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:5887$1695_Y - connect \Y $and$ls180.v:5887$1696_Y - end - attribute \src "ls180.v:5887.48-5887.155" - cell $and $and$ls180.v:5887$1698 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5887$1696_Y - connect \B $eq$ls180.v:5887$1697_Y - connect \Y $and$ls180.v:5887$1698_Y - end - attribute \src "ls180.v:5889.49-5889.102" - cell $and $and$ls180.v:5889$1699 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:5889$1699_Y - end - attribute \src "ls180.v:5889.48-5889.152" - cell $and $and$ls180.v:5889$1701 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5889$1699_Y - connect \B $eq$ls180.v:5889$1700_Y - connect \Y $and$ls180.v:5889$1701_Y - end - attribute \src "ls180.v:5890.49-5890.105" - cell $and $and$ls180.v:5890$1703 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:5890$1702_Y - connect \Y $and$ls180.v:5890$1703_Y - end - attribute \src "ls180.v:5890.48-5890.155" - cell $and $and$ls180.v:5890$1705 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5890$1703_Y - connect \B $eq$ls180.v:5890$1704_Y - connect \Y $and$ls180.v:5890$1705_Y - end - attribute \src "ls180.v:5892.49-5892.102" - cell $and $and$ls180.v:5892$1706 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:5892$1706_Y - end - attribute \src "ls180.v:5892.48-5892.152" - cell $and $and$ls180.v:5892$1708 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5892$1706_Y - connect \B $eq$ls180.v:5892$1707_Y - connect \Y $and$ls180.v:5892$1708_Y - end - attribute \src "ls180.v:5893.49-5893.105" - cell $and $and$ls180.v:5893$1710 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:5893$1709_Y - connect \Y $and$ls180.v:5893$1710_Y - end - attribute \src "ls180.v:5893.48-5893.155" - cell $and $and$ls180.v:5893$1712 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5893$1710_Y - connect \B $eq$ls180.v:5893$1711_Y - connect \Y $and$ls180.v:5893$1712_Y - end - attribute \src "ls180.v:5895.49-5895.102" - cell $and $and$ls180.v:5895$1713 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:5895$1713_Y - end - attribute \src "ls180.v:5895.48-5895.152" - cell $and $and$ls180.v:5895$1715 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5895$1713_Y - connect \B $eq$ls180.v:5895$1714_Y - connect \Y $and$ls180.v:5895$1715_Y - end - attribute \src "ls180.v:5896.49-5896.105" - cell $and $and$ls180.v:5896$1717 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:5896$1716_Y - connect \Y $and$ls180.v:5896$1717_Y - end - attribute \src "ls180.v:5896.48-5896.155" - cell $and $and$ls180.v:5896$1719 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5896$1717_Y - connect \B $eq$ls180.v:5896$1718_Y - connect \Y $and$ls180.v:5896$1719_Y - end - attribute \src "ls180.v:5913.41-5913.94" - cell $and $and$ls180.v:5913$1721 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:5913$1721_Y - end - attribute \src "ls180.v:5913.40-5913.144" - cell $and $and$ls180.v:5913$1723 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5913$1721_Y - connect \B $eq$ls180.v:5913$1722_Y - connect \Y $and$ls180.v:5913$1723_Y - end - attribute \src "ls180.v:5914.41-5914.97" - cell $and $and$ls180.v:5914$1725 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:5914$1724_Y - connect \Y $and$ls180.v:5914$1725_Y - end - attribute \src "ls180.v:5914.40-5914.147" - cell $and $and$ls180.v:5914$1727 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5914$1725_Y - connect \B $eq$ls180.v:5914$1726_Y - connect \Y $and$ls180.v:5914$1727_Y - end - attribute \src "ls180.v:5916.41-5916.94" - cell $and $and$ls180.v:5916$1728 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:5916$1728_Y - end - attribute \src "ls180.v:5916.40-5916.144" - cell $and $and$ls180.v:5916$1730 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5916$1728_Y - connect \B $eq$ls180.v:5916$1729_Y - connect \Y $and$ls180.v:5916$1730_Y - end - attribute \src "ls180.v:5917.41-5917.97" - cell $and $and$ls180.v:5917$1732 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:5917$1731_Y - connect \Y $and$ls180.v:5917$1732_Y - end - attribute \src "ls180.v:5917.40-5917.147" - cell $and $and$ls180.v:5917$1734 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5917$1732_Y - connect \B $eq$ls180.v:5917$1733_Y - connect \Y $and$ls180.v:5917$1734_Y - end - attribute \src "ls180.v:5919.39-5919.92" - cell $and $and$ls180.v:5919$1735 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:5919$1735_Y - end - attribute \src "ls180.v:5919.38-5919.142" - cell $and $and$ls180.v:5919$1737 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5919$1735_Y - connect \B $eq$ls180.v:5919$1736_Y - connect \Y $and$ls180.v:5919$1737_Y - end - attribute \src "ls180.v:5920.39-5920.95" - cell $and $and$ls180.v:5920$1739 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:5920$1738_Y - connect \Y $and$ls180.v:5920$1739_Y - end - attribute \src "ls180.v:5920.38-5920.145" - cell $and $and$ls180.v:5920$1741 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5920$1739_Y - connect \B $eq$ls180.v:5920$1740_Y - connect \Y $and$ls180.v:5920$1741_Y - end - attribute \src "ls180.v:5922.38-5922.91" - cell $and $and$ls180.v:5922$1742 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:5922$1742_Y - end - attribute \src "ls180.v:5922.37-5922.141" - cell $and $and$ls180.v:5922$1744 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5922$1742_Y - connect \B $eq$ls180.v:5922$1743_Y - connect \Y $and$ls180.v:5922$1744_Y - end - attribute \src "ls180.v:5923.38-5923.94" - cell $and $and$ls180.v:5923$1746 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:5923$1745_Y - connect \Y $and$ls180.v:5923$1746_Y - end - attribute \src "ls180.v:5923.37-5923.144" - cell $and $and$ls180.v:5923$1748 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5923$1746_Y - connect \B $eq$ls180.v:5923$1747_Y - connect \Y $and$ls180.v:5923$1748_Y - end - attribute \src "ls180.v:5925.37-5925.90" - cell $and $and$ls180.v:5925$1749 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:5925$1749_Y - end - attribute \src "ls180.v:5925.36-5925.140" - cell $and $and$ls180.v:5925$1751 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5925$1749_Y - connect \B $eq$ls180.v:5925$1750_Y - connect \Y $and$ls180.v:5925$1751_Y - end - attribute \src "ls180.v:5926.37-5926.93" - cell $and $and$ls180.v:5926$1753 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:5926$1752_Y - connect \Y $and$ls180.v:5926$1753_Y - end - attribute \src "ls180.v:5926.36-5926.143" - cell $and $and$ls180.v:5926$1755 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5926$1753_Y - connect \B $eq$ls180.v:5926$1754_Y - connect \Y $and$ls180.v:5926$1755_Y - end - attribute \src "ls180.v:5928.36-5928.89" - cell $and $and$ls180.v:5928$1756 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:5928$1756_Y - end - attribute \src "ls180.v:5928.35-5928.139" - cell $and $and$ls180.v:5928$1758 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5928$1756_Y - connect \B $eq$ls180.v:5928$1757_Y - connect \Y $and$ls180.v:5928$1758_Y - end - attribute \src "ls180.v:5929.36-5929.92" - cell $and $and$ls180.v:5929$1760 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:5929$1759_Y - connect \Y $and$ls180.v:5929$1760_Y - end - attribute \src "ls180.v:5929.35-5929.142" - cell $and $and$ls180.v:5929$1762 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5929$1760_Y - connect \B $eq$ls180.v:5929$1761_Y - connect \Y $and$ls180.v:5929$1762_Y - end - attribute \src "ls180.v:5931.42-5931.95" - cell $and $and$ls180.v:5931$1763 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:5931$1763_Y - end - attribute \src "ls180.v:5931.41-5931.145" - cell $and $and$ls180.v:5931$1765 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5931$1763_Y - connect \B $eq$ls180.v:5931$1764_Y - connect \Y $and$ls180.v:5931$1765_Y - end - attribute \src "ls180.v:5932.42-5932.98" - cell $and $and$ls180.v:5932$1767 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:5932$1766_Y - connect \Y $and$ls180.v:5932$1767_Y - end - attribute \src "ls180.v:5932.41-5932.148" - cell $and $and$ls180.v:5932$1769 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5932$1767_Y - connect \B $eq$ls180.v:5932$1768_Y - connect \Y $and$ls180.v:5932$1769_Y - end - attribute \src "ls180.v:5953.41-5953.94" - cell $and $and$ls180.v:5953$1772 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:5953$1772_Y - end - attribute \src "ls180.v:5953.40-5953.144" - cell $and $and$ls180.v:5953$1774 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5953$1772_Y - connect \B $eq$ls180.v:5953$1773_Y - connect \Y $and$ls180.v:5953$1774_Y - end - attribute \src "ls180.v:5954.41-5954.97" - cell $and $and$ls180.v:5954$1776 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:5954$1775_Y - connect \Y $and$ls180.v:5954$1776_Y - end - attribute \src "ls180.v:5954.40-5954.147" - cell $and $and$ls180.v:5954$1778 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5954$1776_Y - connect \B $eq$ls180.v:5954$1777_Y - connect \Y $and$ls180.v:5954$1778_Y - end - attribute \src "ls180.v:5956.41-5956.94" - cell $and $and$ls180.v:5956$1779 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:5956$1779_Y - end - attribute \src "ls180.v:5956.40-5956.144" - cell $and $and$ls180.v:5956$1781 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5956$1779_Y - connect \B $eq$ls180.v:5956$1780_Y - connect \Y $and$ls180.v:5956$1781_Y - end - attribute \src "ls180.v:5957.41-5957.97" - cell $and $and$ls180.v:5957$1783 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:5957$1782_Y - connect \Y $and$ls180.v:5957$1783_Y - end - attribute \src "ls180.v:5957.40-5957.147" - cell $and $and$ls180.v:5957$1785 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5957$1783_Y - connect \B $eq$ls180.v:5957$1784_Y - connect \Y $and$ls180.v:5957$1785_Y - end - attribute \src "ls180.v:5959.39-5959.92" - cell $and $and$ls180.v:5959$1786 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:5959$1786_Y - end - attribute \src "ls180.v:5959.38-5959.142" - cell $and $and$ls180.v:5959$1788 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5959$1786_Y - connect \B $eq$ls180.v:5959$1787_Y - connect \Y $and$ls180.v:5959$1788_Y - end - attribute \src "ls180.v:5960.39-5960.95" - cell $and $and$ls180.v:5960$1790 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:5960$1789_Y - connect \Y $and$ls180.v:5960$1790_Y - end - attribute \src "ls180.v:5960.38-5960.145" - cell $and $and$ls180.v:5960$1792 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5960$1790_Y - connect \B $eq$ls180.v:5960$1791_Y - connect \Y $and$ls180.v:5960$1792_Y - end - attribute \src "ls180.v:5962.38-5962.91" - cell $and $and$ls180.v:5962$1793 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:5962$1793_Y - end - attribute \src "ls180.v:5962.37-5962.141" - cell $and $and$ls180.v:5962$1795 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5962$1793_Y - connect \B $eq$ls180.v:5962$1794_Y - connect \Y $and$ls180.v:5962$1795_Y - end - attribute \src "ls180.v:5963.38-5963.94" - cell $and $and$ls180.v:5963$1797 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:5963$1796_Y - connect \Y $and$ls180.v:5963$1797_Y - end - attribute \src "ls180.v:5963.37-5963.144" - cell $and $and$ls180.v:5963$1799 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5963$1797_Y - connect \B $eq$ls180.v:5963$1798_Y - connect \Y $and$ls180.v:5963$1799_Y - end - attribute \src "ls180.v:5965.37-5965.90" - cell $and $and$ls180.v:5965$1800 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:5965$1800_Y - end - attribute \src "ls180.v:5965.36-5965.140" - cell $and $and$ls180.v:5965$1802 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5965$1800_Y - connect \B $eq$ls180.v:5965$1801_Y - connect \Y $and$ls180.v:5965$1802_Y - end - attribute \src "ls180.v:5966.37-5966.93" - cell $and $and$ls180.v:5966$1804 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:5966$1803_Y - connect \Y $and$ls180.v:5966$1804_Y - end - attribute \src "ls180.v:5966.36-5966.143" - cell $and $and$ls180.v:5966$1806 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5966$1804_Y - connect \B $eq$ls180.v:5966$1805_Y - connect \Y $and$ls180.v:5966$1806_Y - end - attribute \src "ls180.v:5968.36-5968.89" - cell $and $and$ls180.v:5968$1807 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:5968$1807_Y - end - attribute \src "ls180.v:5968.35-5968.139" - cell $and $and$ls180.v:5968$1809 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5968$1807_Y - connect \B $eq$ls180.v:5968$1808_Y - connect \Y $and$ls180.v:5968$1809_Y - end - attribute \src "ls180.v:5969.36-5969.92" - cell $and $and$ls180.v:5969$1811 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:5969$1810_Y - connect \Y $and$ls180.v:5969$1811_Y - end - attribute \src "ls180.v:5969.35-5969.142" - cell $and $and$ls180.v:5969$1813 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5969$1811_Y - connect \B $eq$ls180.v:5969$1812_Y - connect \Y $and$ls180.v:5969$1813_Y - end - attribute \src "ls180.v:5971.42-5971.95" - cell $and $and$ls180.v:5971$1814 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:5971$1814_Y - end - attribute \src "ls180.v:5971.41-5971.145" - cell $and $and$ls180.v:5971$1816 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5971$1814_Y - connect \B $eq$ls180.v:5971$1815_Y - connect \Y $and$ls180.v:5971$1816_Y - end - attribute \src "ls180.v:5972.42-5972.98" - cell $and $and$ls180.v:5972$1818 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:5972$1817_Y - connect \Y $and$ls180.v:5972$1818_Y - end - attribute \src "ls180.v:5972.41-5972.148" - cell $and $and$ls180.v:5972$1820 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5972$1818_Y - connect \B $eq$ls180.v:5972$1819_Y - connect \Y $and$ls180.v:5972$1820_Y - end - attribute \src "ls180.v:5974.45-5974.98" - cell $and $and$ls180.v:5974$1821 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:5974$1821_Y - end - attribute \src "ls180.v:5974.44-5974.148" - cell $and $and$ls180.v:5974$1823 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5974$1821_Y - connect \B $eq$ls180.v:5974$1822_Y - connect \Y $and$ls180.v:5974$1823_Y - end - attribute \src "ls180.v:5975.45-5975.101" - cell $and $and$ls180.v:5975$1825 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:5975$1824_Y - connect \Y $and$ls180.v:5975$1825_Y - end - attribute \src "ls180.v:5975.44-5975.151" - cell $and $and$ls180.v:5975$1827 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5975$1825_Y - connect \B $eq$ls180.v:5975$1826_Y - connect \Y $and$ls180.v:5975$1827_Y - end - attribute \src "ls180.v:5977.45-5977.98" - cell $and $and$ls180.v:5977$1828 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:5977$1828_Y - end - attribute \src "ls180.v:5977.44-5977.148" - cell $and $and$ls180.v:5977$1830 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5977$1828_Y - connect \B $eq$ls180.v:5977$1829_Y - connect \Y $and$ls180.v:5977$1830_Y - end - attribute \src "ls180.v:5978.45-5978.101" - cell $and $and$ls180.v:5978$1832 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:5978$1831_Y - connect \Y $and$ls180.v:5978$1832_Y - end - attribute \src "ls180.v:5978.44-5978.151" - cell $and $and$ls180.v:5978$1834 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5978$1832_Y - connect \B $eq$ls180.v:5978$1833_Y - connect \Y $and$ls180.v:5978$1834_Y - end - attribute \src "ls180.v:6001.39-6001.94" - cell $and $and$ls180.v:6001$1837 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6001$1837_Y - end - attribute \src "ls180.v:6001.38-6001.145" - cell $and $and$ls180.v:6001$1839 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6001$1837_Y - connect \B $eq$ls180.v:6001$1838_Y - connect \Y $and$ls180.v:6001$1839_Y - end - attribute \src "ls180.v:6002.39-6002.97" - cell $and $and$ls180.v:6002$1841 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6002$1840_Y - connect \Y $and$ls180.v:6002$1841_Y - end - attribute \src "ls180.v:6002.38-6002.148" - cell $and $and$ls180.v:6002$1843 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6002$1841_Y - connect \B $eq$ls180.v:6002$1842_Y - connect \Y $and$ls180.v:6002$1843_Y - end - attribute \src "ls180.v:6004.39-6004.94" - cell $and $and$ls180.v:6004$1844 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6004$1844_Y - end - attribute \src "ls180.v:6004.38-6004.145" - cell $and $and$ls180.v:6004$1846 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6004$1844_Y - connect \B $eq$ls180.v:6004$1845_Y - connect \Y $and$ls180.v:6004$1846_Y - end - attribute \src "ls180.v:6005.39-6005.97" - cell $and $and$ls180.v:6005$1848 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6005$1847_Y - connect \Y $and$ls180.v:6005$1848_Y - end - attribute \src "ls180.v:6005.38-6005.148" - cell $and $and$ls180.v:6005$1850 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6005$1848_Y - connect \B $eq$ls180.v:6005$1849_Y - connect \Y $and$ls180.v:6005$1850_Y - end - attribute \src "ls180.v:6007.39-6007.94" - cell $and $and$ls180.v:6007$1851 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6007$1851_Y - end - attribute \src "ls180.v:6007.38-6007.145" - cell $and $and$ls180.v:6007$1853 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6007$1851_Y - connect \B $eq$ls180.v:6007$1852_Y - connect \Y $and$ls180.v:6007$1853_Y - end - attribute \src "ls180.v:6008.39-6008.97" - cell $and $and$ls180.v:6008$1855 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6008$1854_Y - connect \Y $and$ls180.v:6008$1855_Y - end - attribute \src "ls180.v:6008.38-6008.148" - cell $and $and$ls180.v:6008$1857 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6008$1855_Y - connect \B $eq$ls180.v:6008$1856_Y - connect \Y $and$ls180.v:6008$1857_Y - end - attribute \src "ls180.v:6010.39-6010.94" - cell $and $and$ls180.v:6010$1858 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6010$1858_Y - end - attribute \src "ls180.v:6010.38-6010.145" - cell $and $and$ls180.v:6010$1860 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6010$1858_Y - connect \B $eq$ls180.v:6010$1859_Y - connect \Y $and$ls180.v:6010$1860_Y - end - attribute \src "ls180.v:6011.39-6011.97" - cell $and $and$ls180.v:6011$1862 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6011$1861_Y - connect \Y $and$ls180.v:6011$1862_Y - end - attribute \src "ls180.v:6011.38-6011.148" - cell $and $and$ls180.v:6011$1864 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6011$1862_Y - connect \B $eq$ls180.v:6011$1863_Y - connect \Y $and$ls180.v:6011$1864_Y - end - attribute \src "ls180.v:6013.41-6013.96" - cell $and $and$ls180.v:6013$1865 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6013$1865_Y - end - attribute \src "ls180.v:6013.40-6013.147" - cell $and $and$ls180.v:6013$1867 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6013$1865_Y - connect \B $eq$ls180.v:6013$1866_Y - connect \Y $and$ls180.v:6013$1867_Y - end - attribute \src "ls180.v:6014.41-6014.99" - cell $and $and$ls180.v:6014$1869 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6014$1868_Y - connect \Y $and$ls180.v:6014$1869_Y - end - attribute \src "ls180.v:6014.40-6014.150" - cell $and $and$ls180.v:6014$1871 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6014$1869_Y - connect \B $eq$ls180.v:6014$1870_Y - connect \Y $and$ls180.v:6014$1871_Y - end - attribute \src "ls180.v:6016.41-6016.96" - cell $and $and$ls180.v:6016$1872 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6016$1872_Y - end - attribute \src "ls180.v:6016.40-6016.147" - cell $and $and$ls180.v:6016$1874 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6016$1872_Y - connect \B $eq$ls180.v:6016$1873_Y - connect \Y $and$ls180.v:6016$1874_Y - end - attribute \src "ls180.v:6017.41-6017.99" - cell $and $and$ls180.v:6017$1876 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6017$1875_Y - connect \Y $and$ls180.v:6017$1876_Y - end - attribute \src "ls180.v:6017.40-6017.150" - cell $and $and$ls180.v:6017$1878 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6017$1876_Y - connect \B $eq$ls180.v:6017$1877_Y - connect \Y $and$ls180.v:6017$1878_Y - end - attribute \src "ls180.v:6019.41-6019.96" - cell $and $and$ls180.v:6019$1879 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6019$1879_Y - end - attribute \src "ls180.v:6019.40-6019.147" - cell $and $and$ls180.v:6019$1881 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6019$1879_Y - connect \B $eq$ls180.v:6019$1880_Y - connect \Y $and$ls180.v:6019$1881_Y - end - attribute \src "ls180.v:6020.41-6020.99" - cell $and $and$ls180.v:6020$1883 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6020$1882_Y - connect \Y $and$ls180.v:6020$1883_Y - end - attribute \src "ls180.v:6020.40-6020.150" - cell $and $and$ls180.v:6020$1885 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6020$1883_Y - connect \B $eq$ls180.v:6020$1884_Y - connect \Y $and$ls180.v:6020$1885_Y - end - attribute \src "ls180.v:6022.41-6022.96" - cell $and $and$ls180.v:6022$1886 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6022$1886_Y - end - attribute \src "ls180.v:6022.40-6022.147" - cell $and $and$ls180.v:6022$1888 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6022$1886_Y - connect \B $eq$ls180.v:6022$1887_Y - connect \Y $and$ls180.v:6022$1888_Y - end - attribute \src "ls180.v:6023.41-6023.99" - cell $and $and$ls180.v:6023$1890 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6023$1889_Y - connect \Y $and$ls180.v:6023$1890_Y - end - attribute \src "ls180.v:6023.40-6023.150" - cell $and $and$ls180.v:6023$1892 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6023$1890_Y - connect \B $eq$ls180.v:6023$1891_Y - connect \Y $and$ls180.v:6023$1892_Y - end - attribute \src "ls180.v:6025.37-6025.92" - cell $and $and$ls180.v:6025$1893 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6025$1893_Y - end - attribute \src "ls180.v:6025.36-6025.143" - cell $and $and$ls180.v:6025$1895 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6025$1893_Y - connect \B $eq$ls180.v:6025$1894_Y - connect \Y $and$ls180.v:6025$1895_Y - end - attribute \src "ls180.v:6026.37-6026.95" - cell $and $and$ls180.v:6026$1897 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6026$1896_Y - connect \Y $and$ls180.v:6026$1897_Y - end - attribute \src "ls180.v:6026.36-6026.146" - cell $and $and$ls180.v:6026$1899 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6026$1897_Y - connect \B $eq$ls180.v:6026$1898_Y - connect \Y $and$ls180.v:6026$1899_Y - end - attribute \src "ls180.v:6028.47-6028.102" - cell $and $and$ls180.v:6028$1900 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6028$1900_Y - end - attribute \src "ls180.v:6028.46-6028.153" - cell $and $and$ls180.v:6028$1902 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6028$1900_Y - connect \B $eq$ls180.v:6028$1901_Y - connect \Y $and$ls180.v:6028$1902_Y - end - attribute \src "ls180.v:6029.47-6029.105" - cell $and $and$ls180.v:6029$1904 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6029$1903_Y - connect \Y $and$ls180.v:6029$1904_Y - end - attribute \src "ls180.v:6029.46-6029.156" - cell $and $and$ls180.v:6029$1906 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6029$1904_Y - connect \B $eq$ls180.v:6029$1905_Y - connect \Y $and$ls180.v:6029$1906_Y - end - attribute \src "ls180.v:6031.40-6031.95" - cell $and $and$ls180.v:6031$1907 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6031$1907_Y - end - attribute \src "ls180.v:6031.39-6031.147" - cell $and $and$ls180.v:6031$1909 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6031$1907_Y - connect \B $eq$ls180.v:6031$1908_Y - connect \Y $and$ls180.v:6031$1909_Y - end - attribute \src "ls180.v:6032.40-6032.98" - cell $and $and$ls180.v:6032$1911 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6032$1910_Y - connect \Y $and$ls180.v:6032$1911_Y - end - attribute \src "ls180.v:6032.39-6032.150" - cell $and $and$ls180.v:6032$1913 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6032$1911_Y - connect \B $eq$ls180.v:6032$1912_Y - connect \Y $and$ls180.v:6032$1913_Y - end - attribute \src "ls180.v:6034.40-6034.95" - cell $and $and$ls180.v:6034$1914 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6034$1914_Y - end - attribute \src "ls180.v:6034.39-6034.147" - cell $and $and$ls180.v:6034$1916 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6034$1914_Y - connect \B $eq$ls180.v:6034$1915_Y - connect \Y $and$ls180.v:6034$1916_Y - end - attribute \src "ls180.v:6035.40-6035.98" - cell $and $and$ls180.v:6035$1918 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6035$1917_Y - connect \Y $and$ls180.v:6035$1918_Y - end - attribute \src "ls180.v:6035.39-6035.150" - cell $and $and$ls180.v:6035$1920 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6035$1918_Y - connect \B $eq$ls180.v:6035$1919_Y - connect \Y $and$ls180.v:6035$1920_Y - end - attribute \src "ls180.v:6037.40-6037.95" - cell $and $and$ls180.v:6037$1921 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6037$1921_Y - end - attribute \src "ls180.v:6037.39-6037.147" - cell $and $and$ls180.v:6037$1923 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6037$1921_Y - connect \B $eq$ls180.v:6037$1922_Y - connect \Y $and$ls180.v:6037$1923_Y - end - attribute \src "ls180.v:6038.40-6038.98" - cell $and $and$ls180.v:6038$1925 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6038$1924_Y - connect \Y $and$ls180.v:6038$1925_Y - end - attribute \src "ls180.v:6038.39-6038.150" - cell $and $and$ls180.v:6038$1927 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6038$1925_Y - connect \B $eq$ls180.v:6038$1926_Y - connect \Y $and$ls180.v:6038$1927_Y - end - attribute \src "ls180.v:6040.40-6040.95" - cell $and $and$ls180.v:6040$1928 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6040$1928_Y - end - attribute \src "ls180.v:6040.39-6040.147" - cell $and $and$ls180.v:6040$1930 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6040$1928_Y - connect \B $eq$ls180.v:6040$1929_Y - connect \Y $and$ls180.v:6040$1930_Y - end - attribute \src "ls180.v:6041.40-6041.98" - cell $and $and$ls180.v:6041$1932 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6041$1931_Y - connect \Y $and$ls180.v:6041$1932_Y - end - attribute \src "ls180.v:6041.39-6041.150" - cell $and $and$ls180.v:6041$1934 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6041$1932_Y - connect \B $eq$ls180.v:6041$1933_Y - connect \Y $and$ls180.v:6041$1934_Y - end - attribute \src "ls180.v:6043.58-6043.113" - cell $and $and$ls180.v:6043$1935 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6043$1935_Y - end - attribute \src "ls180.v:6043.57-6043.165" - cell $and $and$ls180.v:6043$1937 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6043$1935_Y - connect \B $eq$ls180.v:6043$1936_Y - connect \Y $and$ls180.v:6043$1937_Y - end - attribute \src "ls180.v:6044.58-6044.116" - cell $and $and$ls180.v:6044$1939 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6044$1938_Y - connect \Y $and$ls180.v:6044$1939_Y - end - attribute \src "ls180.v:6044.57-6044.168" - cell $and $and$ls180.v:6044$1941 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6044$1939_Y - connect \B $eq$ls180.v:6044$1940_Y - connect \Y $and$ls180.v:6044$1941_Y - end - attribute \src "ls180.v:6046.59-6046.114" - cell $and $and$ls180.v:6046$1942 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6046$1942_Y - end - attribute \src "ls180.v:6046.58-6046.166" - cell $and $and$ls180.v:6046$1944 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6046$1942_Y - connect \B $eq$ls180.v:6046$1943_Y - connect \Y $and$ls180.v:6046$1944_Y - end - attribute \src "ls180.v:6047.59-6047.117" - cell $and $and$ls180.v:6047$1946 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6047$1945_Y - connect \Y $and$ls180.v:6047$1946_Y - end - attribute \src "ls180.v:6047.58-6047.169" - cell $and $and$ls180.v:6047$1948 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6047$1946_Y - connect \B $eq$ls180.v:6047$1947_Y - connect \Y $and$ls180.v:6047$1948_Y - end - attribute \src "ls180.v:6049.44-6049.99" - cell $and $and$ls180.v:6049$1949 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6049$1949_Y - end - attribute \src "ls180.v:6049.43-6049.151" - cell $and $and$ls180.v:6049$1951 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6049$1949_Y - connect \B $eq$ls180.v:6049$1950_Y - connect \Y $and$ls180.v:6049$1951_Y - end - attribute \src "ls180.v:6050.44-6050.102" - cell $and $and$ls180.v:6050$1953 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6050$1952_Y - connect \Y $and$ls180.v:6050$1953_Y - end - attribute \src "ls180.v:6050.43-6050.154" - cell $and $and$ls180.v:6050$1955 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6050$1953_Y - connect \B $eq$ls180.v:6050$1954_Y - connect \Y $and$ls180.v:6050$1955_Y - end - attribute \src "ls180.v:6069.42-6069.97" - cell $and $and$ls180.v:6069$1957 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6069$1957_Y - end - attribute \src "ls180.v:6069.41-6069.148" - cell $and $and$ls180.v:6069$1959 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6069$1957_Y - connect \B $eq$ls180.v:6069$1958_Y - connect \Y $and$ls180.v:6069$1959_Y - end - attribute \src "ls180.v:6070.42-6070.100" - cell $and $and$ls180.v:6070$1961 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6070$1960_Y - connect \Y $and$ls180.v:6070$1961_Y - end - attribute \src "ls180.v:6070.41-6070.151" - cell $and $and$ls180.v:6070$1963 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6070$1961_Y - connect \B $eq$ls180.v:6070$1962_Y - connect \Y $and$ls180.v:6070$1963_Y - end - attribute \src "ls180.v:6072.40-6072.95" - cell $and $and$ls180.v:6072$1964 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6072$1964_Y - end - attribute \src "ls180.v:6072.39-6072.146" - cell $and $and$ls180.v:6072$1966 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6072$1964_Y - connect \B $eq$ls180.v:6072$1965_Y - connect \Y $and$ls180.v:6072$1966_Y - end - attribute \src "ls180.v:6073.40-6073.98" - cell $and $and$ls180.v:6073$1968 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6073$1967_Y - connect \Y $and$ls180.v:6073$1968_Y - end - attribute \src "ls180.v:6073.39-6073.149" - cell $and $and$ls180.v:6073$1970 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6073$1968_Y - connect \B $eq$ls180.v:6073$1969_Y - connect \Y $and$ls180.v:6073$1970_Y - end - attribute \src "ls180.v:6075.41-6075.96" - cell $and $and$ls180.v:6075$1971 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6075$1971_Y - end - attribute \src "ls180.v:6075.40-6075.147" - cell $and $and$ls180.v:6075$1973 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6075$1971_Y - connect \B $eq$ls180.v:6075$1972_Y - connect \Y $and$ls180.v:6075$1973_Y - end - attribute \src "ls180.v:6076.41-6076.99" - cell $and $and$ls180.v:6076$1975 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6076$1974_Y - connect \Y $and$ls180.v:6076$1975_Y - end - attribute \src "ls180.v:6076.40-6076.150" - cell $and $and$ls180.v:6076$1977 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6076$1975_Y - connect \B $eq$ls180.v:6076$1976_Y - connect \Y $and$ls180.v:6076$1977_Y - end - attribute \src "ls180.v:6078.57-6078.112" - cell $and $and$ls180.v:6078$1978 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6078$1978_Y - end - attribute \src "ls180.v:6078.56-6078.163" - cell $and $and$ls180.v:6078$1980 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6078$1978_Y - connect \B $eq$ls180.v:6078$1979_Y - connect \Y $and$ls180.v:6078$1980_Y - end - attribute \src "ls180.v:6079.57-6079.115" - cell $and $and$ls180.v:6079$1982 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6079$1981_Y - connect \Y $and$ls180.v:6079$1982_Y - end - attribute \src "ls180.v:6079.56-6079.166" - cell $and $and$ls180.v:6079$1984 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6079$1982_Y - connect \B $eq$ls180.v:6079$1983_Y - connect \Y $and$ls180.v:6079$1984_Y - end - attribute \src "ls180.v:6081.58-6081.113" - cell $and $and$ls180.v:6081$1985 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6081$1985_Y - end - attribute \src "ls180.v:6081.57-6081.164" - cell $and $and$ls180.v:6081$1987 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6081$1985_Y - connect \B $eq$ls180.v:6081$1986_Y - connect \Y $and$ls180.v:6081$1987_Y - end - attribute \src "ls180.v:6082.58-6082.116" - cell $and $and$ls180.v:6082$1989 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6082$1988_Y - connect \Y $and$ls180.v:6082$1989_Y - end - attribute \src "ls180.v:6082.57-6082.167" - cell $and $and$ls180.v:6082$1991 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6082$1989_Y - connect \B $eq$ls180.v:6082$1990_Y - connect \Y $and$ls180.v:6082$1991_Y - end - attribute \src "ls180.v:6084.44-6084.99" - cell $and $and$ls180.v:6084$1992 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6084$1992_Y - end - attribute \src "ls180.v:6084.43-6084.150" - cell $and $and$ls180.v:6084$1994 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6084$1992_Y - connect \B $eq$ls180.v:6084$1993_Y - connect \Y $and$ls180.v:6084$1994_Y - end - attribute \src "ls180.v:6085.44-6085.102" - cell $and $and$ls180.v:6085$1996 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6085$1995_Y - connect \Y $and$ls180.v:6085$1996_Y - end - attribute \src "ls180.v:6085.43-6085.153" - cell $and $and$ls180.v:6085$1998 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6085$1996_Y - connect \B $eq$ls180.v:6085$1997_Y - connect \Y $and$ls180.v:6085$1998_Y - end - attribute \src "ls180.v:6087.41-6087.96" - cell $and $and$ls180.v:6087$1999 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6087$1999_Y - end - attribute \src "ls180.v:6087.40-6087.147" - cell $and $and$ls180.v:6087$2001 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6087$1999_Y - connect \B $eq$ls180.v:6087$2000_Y - connect \Y $and$ls180.v:6087$2001_Y - end - attribute \src "ls180.v:6088.41-6088.99" - cell $and $and$ls180.v:6088$2003 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6088$2002_Y - connect \Y $and$ls180.v:6088$2003_Y - end - attribute \src "ls180.v:6088.40-6088.150" - cell $and $and$ls180.v:6088$2005 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6088$2003_Y - connect \B $eq$ls180.v:6088$2004_Y - connect \Y $and$ls180.v:6088$2005_Y - end - attribute \src "ls180.v:6090.40-6090.95" - cell $and $and$ls180.v:6090$2006 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6090$2006_Y - end - attribute \src "ls180.v:6090.39-6090.146" - cell $and $and$ls180.v:6090$2008 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6090$2006_Y - connect \B $eq$ls180.v:6090$2007_Y - connect \Y $and$ls180.v:6090$2008_Y - end - attribute \src "ls180.v:6091.40-6091.98" - cell $and $and$ls180.v:6091$2010 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6091$2009_Y - connect \Y $and$ls180.v:6091$2010_Y - end - attribute \src "ls180.v:6091.39-6091.149" - cell $and $and$ls180.v:6091$2012 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6091$2010_Y - connect \B $eq$ls180.v:6091$2011_Y - connect \Y $and$ls180.v:6091$2012_Y - end - attribute \src "ls180.v:6103.46-6103.101" - cell $and $and$ls180.v:6103$2014 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6103$2014_Y - end - attribute \src "ls180.v:6103.45-6103.152" - cell $and $and$ls180.v:6103$2016 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6103$2014_Y - connect \B $eq$ls180.v:6103$2015_Y - connect \Y $and$ls180.v:6103$2016_Y - end - attribute \src "ls180.v:6104.46-6104.104" - cell $and $and$ls180.v:6104$2018 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6104$2017_Y - connect \Y $and$ls180.v:6104$2018_Y - end - attribute \src "ls180.v:6104.45-6104.155" - cell $and $and$ls180.v:6104$2020 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6104$2018_Y - connect \B $eq$ls180.v:6104$2019_Y - connect \Y $and$ls180.v:6104$2020_Y - end - attribute \src "ls180.v:6106.46-6106.101" - cell $and $and$ls180.v:6106$2021 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6106$2021_Y - end - attribute \src "ls180.v:6106.45-6106.152" - cell $and $and$ls180.v:6106$2023 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6106$2021_Y - connect \B $eq$ls180.v:6106$2022_Y - connect \Y $and$ls180.v:6106$2023_Y - end - attribute \src "ls180.v:6107.46-6107.104" - cell $and $and$ls180.v:6107$2025 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6107$2024_Y - connect \Y $and$ls180.v:6107$2025_Y - end - attribute \src "ls180.v:6107.45-6107.155" - cell $and $and$ls180.v:6107$2027 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6107$2025_Y - connect \B $eq$ls180.v:6107$2026_Y - connect \Y $and$ls180.v:6107$2027_Y - end - attribute \src "ls180.v:6109.46-6109.101" - cell $and $and$ls180.v:6109$2028 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6109$2028_Y - end - attribute \src "ls180.v:6109.45-6109.152" - cell $and $and$ls180.v:6109$2030 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6109$2028_Y - connect \B $eq$ls180.v:6109$2029_Y - connect \Y $and$ls180.v:6109$2030_Y - end - attribute \src "ls180.v:6110.46-6110.104" - cell $and $and$ls180.v:6110$2032 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6110$2031_Y - connect \Y $and$ls180.v:6110$2032_Y - end - attribute \src "ls180.v:6110.45-6110.155" - cell $and $and$ls180.v:6110$2034 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6110$2032_Y - connect \B $eq$ls180.v:6110$2033_Y - connect \Y $and$ls180.v:6110$2034_Y - end - attribute \src "ls180.v:6112.46-6112.101" - cell $and $and$ls180.v:6112$2035 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6112$2035_Y - end - attribute \src "ls180.v:6112.45-6112.152" - cell $and $and$ls180.v:6112$2037 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6112$2035_Y - connect \B $eq$ls180.v:6112$2036_Y - connect \Y $and$ls180.v:6112$2037_Y - end - attribute \src "ls180.v:6113.46-6113.104" - cell $and $and$ls180.v:6113$2039 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6113$2038_Y - connect \Y $and$ls180.v:6113$2039_Y - end - attribute \src "ls180.v:6113.45-6113.155" - cell $and $and$ls180.v:6113$2041 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6113$2039_Y - connect \B $eq$ls180.v:6113$2040_Y - connect \Y $and$ls180.v:6113$2041_Y - end - attribute \src "ls180.v:6488.109-6488.178" - cell $and $and$ls180.v:6488$2077 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6488$2076_Y - connect \Y $and$ls180.v:6488$2077_Y - end - attribute \src "ls180.v:6488.184-6488.253" - cell $and $and$ls180.v:6488$2080 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6488$2079_Y - connect \Y $and$ls180.v:6488$2080_Y - end - attribute \src "ls180.v:6488.259-6488.328" - cell $and $and$ls180.v:6488$2083 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6488$2082_Y - connect \Y $and$ls180.v:6488$2083_Y - end - attribute \src "ls180.v:6488.40-6488.331" - cell $and $and$ls180.v:6488$2086 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6488$2075_Y - connect \B $not$ls180.v:6488$2085_Y - connect \Y $and$ls180.v:6488$2086_Y - end - attribute \src "ls180.v:6488.39-6488.354" - cell $and $and$ls180.v:6488$2087 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6488$2086_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6488$2087_Y - end - attribute \src "ls180.v:6512.109-6512.178" - cell $and $and$ls180.v:6512$2093 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6512$2092_Y - connect \Y $and$ls180.v:6512$2093_Y - end - attribute \src "ls180.v:6512.184-6512.253" - cell $and $and$ls180.v:6512$2096 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6512$2095_Y - connect \Y $and$ls180.v:6512$2096_Y - end - attribute \src "ls180.v:6512.259-6512.328" - cell $and $and$ls180.v:6512$2099 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6512$2098_Y - connect \Y $and$ls180.v:6512$2099_Y - end - attribute \src "ls180.v:6512.40-6512.331" - cell $and $and$ls180.v:6512$2102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6512$2091_Y - connect \B $not$ls180.v:6512$2101_Y - connect \Y $and$ls180.v:6512$2102_Y - end - attribute \src "ls180.v:6512.39-6512.354" - cell $and $and$ls180.v:6512$2103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6512$2102_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6512$2103_Y - end - attribute \src "ls180.v:6536.109-6536.178" - cell $and $and$ls180.v:6536$2109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6536$2108_Y - connect \Y $and$ls180.v:6536$2109_Y - end - attribute \src "ls180.v:6536.184-6536.253" - cell $and $and$ls180.v:6536$2112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6536$2111_Y - connect \Y $and$ls180.v:6536$2112_Y - end - attribute \src "ls180.v:6536.259-6536.328" - cell $and $and$ls180.v:6536$2115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6536$2114_Y - connect \Y $and$ls180.v:6536$2115_Y - end - attribute \src "ls180.v:6536.40-6536.331" - cell $and $and$ls180.v:6536$2118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6536$2107_Y - connect \B $not$ls180.v:6536$2117_Y - connect \Y $and$ls180.v:6536$2118_Y - end - attribute \src "ls180.v:6536.39-6536.354" - cell $and $and$ls180.v:6536$2119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6536$2118_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6536$2119_Y - end - attribute \src "ls180.v:6560.109-6560.178" - cell $and $and$ls180.v:6560$2125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6560$2124_Y - connect \Y $and$ls180.v:6560$2125_Y - end - attribute \src "ls180.v:6560.184-6560.253" - cell $and $and$ls180.v:6560$2128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6560$2127_Y - connect \Y $and$ls180.v:6560$2128_Y - end - attribute \src "ls180.v:6560.259-6560.328" - cell $and $and$ls180.v:6560$2131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6560$2130_Y - connect \Y $and$ls180.v:6560$2131_Y - end - attribute \src "ls180.v:6560.40-6560.331" - cell $and $and$ls180.v:6560$2134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6560$2123_Y - connect \B $not$ls180.v:6560$2133_Y - connect \Y $and$ls180.v:6560$2134_Y - end - attribute \src "ls180.v:6560.39-6560.354" - cell $and $and$ls180.v:6560$2135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6560$2134_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6560$2135_Y - end - attribute \src "ls180.v:6741.39-6741.104" - cell $and $and$ls180.v:6741$2147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:6741$2147_Y - end - attribute \src "ls180.v:6741.38-6741.145" - cell $and $and$ls180.v:6741$2148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6741$2147_Y - connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:6741$2148_Y - end - attribute \src "ls180.v:6744.39-6744.104" - cell $and $and$ls180.v:6744$2149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:6744$2149_Y - end - attribute \src "ls180.v:6744.38-6744.145" - cell $and $and$ls180.v:6744$2150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6744$2149_Y - connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:6744$2150_Y - end - attribute \src "ls180.v:6747.39-6747.82" - cell $and $and$ls180.v:6747$2151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:6747$2151_Y - end - attribute \src "ls180.v:6747.38-6747.112" - cell $and $and$ls180.v:6747$2152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6747$2151_Y - connect \B \main_sdram_cmd_payload_cas - connect \Y $and$ls180.v:6747$2152_Y - end - attribute \src "ls180.v:6758.39-6758.104" - cell $and $and$ls180.v:6758$2154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:6758$2154_Y - end - attribute \src "ls180.v:6758.38-6758.145" - cell $and $and$ls180.v:6758$2155 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6758$2154_Y - connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:6758$2155_Y - end - attribute \src "ls180.v:6761.39-6761.104" - cell $and $and$ls180.v:6761$2156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:6761$2156_Y - end - attribute \src "ls180.v:6761.38-6761.145" - cell $and $and$ls180.v:6761$2157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6761$2156_Y - connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:6761$2157_Y - end - attribute \src "ls180.v:6764.39-6764.82" - cell $and $and$ls180.v:6764$2158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:6764$2158_Y - end - attribute \src "ls180.v:6764.38-6764.112" - cell $and $and$ls180.v:6764$2159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6764$2158_Y - connect \B \main_sdram_cmd_payload_ras - connect \Y $and$ls180.v:6764$2159_Y - end - attribute \src "ls180.v:6775.39-6775.104" - cell $and $and$ls180.v:6775$2161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:6775$2161_Y - end - attribute \src "ls180.v:6775.38-6775.144" - cell $and $and$ls180.v:6775$2162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6775$2161_Y - connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:6775$2162_Y - end - attribute \src "ls180.v:6778.39-6778.104" - cell $and $and$ls180.v:6778$2163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:6778$2163_Y - end - attribute \src "ls180.v:6778.38-6778.144" - cell $and $and$ls180.v:6778$2164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6778$2163_Y - connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:6778$2164_Y - end - attribute \src "ls180.v:6781.39-6781.82" - cell $and $and$ls180.v:6781$2165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:6781$2165_Y - end - attribute \src "ls180.v:6781.38-6781.111" - cell $and $and$ls180.v:6781$2166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6781$2165_Y - connect \B \main_sdram_cmd_payload_we - connect \Y $and$ls180.v:6781$2166_Y - end - attribute \src "ls180.v:6792.39-6792.104" - cell $and $and$ls180.v:6792$2168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:6792$2168_Y - end - attribute \src "ls180.v:6792.38-6792.149" - cell $and $and$ls180.v:6792$2169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6792$2168_Y - connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:6792$2169_Y - end - attribute \src "ls180.v:6795.39-6795.104" - cell $and $and$ls180.v:6795$2170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:6795$2170_Y - end - attribute \src "ls180.v:6795.38-6795.149" - cell $and $and$ls180.v:6795$2171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6795$2170_Y - connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:6795$2171_Y - end - attribute \src "ls180.v:6798.39-6798.82" - cell $and $and$ls180.v:6798$2172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:6798$2172_Y - end - attribute \src "ls180.v:6798.38-6798.116" - cell $and $and$ls180.v:6798$2173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6798$2172_Y - connect \B \main_sdram_cmd_payload_is_read - connect \Y $and$ls180.v:6798$2173_Y - end - attribute \src "ls180.v:6809.39-6809.104" - cell $and $and$ls180.v:6809$2175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:6809$2175_Y - end - attribute \src "ls180.v:6809.38-6809.150" - cell $and $and$ls180.v:6809$2176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6809$2175_Y - connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:6809$2176_Y - end - attribute \src "ls180.v:6812.39-6812.104" - cell $and $and$ls180.v:6812$2177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:6812$2177_Y - end - attribute \src "ls180.v:6812.38-6812.150" - cell $and $and$ls180.v:6812$2178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6812$2177_Y - connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:6812$2178_Y - end - attribute \src "ls180.v:6815.39-6815.82" - cell $and $and$ls180.v:6815$2179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:6815$2179_Y - end - attribute \src "ls180.v:6815.38-6815.117" - cell $and $and$ls180.v:6815$2180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6815$2179_Y - connect \B \main_sdram_cmd_payload_is_write - connect \Y $and$ls180.v:6815$2180_Y - end - attribute \src "ls180.v:7006.17-7006.69" - cell $and $and$ls180.v:7006$2186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7006$2185_Y - connect \B \libresocsim_sdpads_clk - connect \Y $and$ls180.v:7006$2186_Y - end - attribute \src "ls180.v:7085.8-7085.67" - cell $and $and$ls180.v:7085$2192 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:7085$2192_Y - end - attribute \src "ls180.v:7085.7-7085.102" - cell $and $and$ls180.v:7085$2194 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7085$2192_Y - connect \B $not$ls180.v:7085$2193_Y - connect \Y $and$ls180.v:7085$2194_Y - end - attribute \src "ls180.v:7089.8-7089.65" - cell $and $and$ls180.v:7089$2196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_sink_valid - connect \B $not$ls180.v:7089$2195_Y - connect \Y $and$ls180.v:7089$2196_Y - end - attribute \src "ls180.v:7089.7-7089.99" - cell $and $and$ls180.v:7089$2198 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7089$2196_Y - connect \B $not$ls180.v:7089$2197_Y - connect \Y $and$ls180.v:7089$2198_Y - end - attribute \src "ls180.v:7095.8-7095.65" - cell $and $and$ls180.v:7095$2199 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_clk_txen - connect \B \main_libresocsim_tx_busy - connect \Y $and$ls180.v:7095$2199_Y - end - attribute \src "ls180.v:7119.8-7119.54" - cell $and $and$ls180.v:7119$2206 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7119$2205_Y - connect \B \main_libresocsim_rx_r - connect \Y $and$ls180.v:7119$2206_Y - end - attribute \src "ls180.v:7152.7-7152.81" - cell $and $and$ls180.v:7152$2212 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7152$2211_Y - connect \B \main_libresocsim_uart_tx_old_trigger - connect \Y $and$ls180.v:7152$2212_Y - end - attribute \src "ls180.v:7159.7-7159.81" - cell $and $and$ls180.v:7159$2214 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7159$2213_Y - connect \B \main_libresocsim_uart_rx_old_trigger - connect \Y $and$ls180.v:7159$2214_Y - end - attribute \src "ls180.v:7169.8-7169.99" - cell $and $and$ls180.v:7169$2215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_tx_fifo_syncfifo_we - connect \B \main_libresocsim_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:7169$2215_Y - end - attribute \src "ls180.v:7169.7-7169.143" - cell $and $and$ls180.v:7169$2217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7169$2215_Y - connect \B $not$ls180.v:7169$2216_Y - connect \Y $and$ls180.v:7169$2217_Y - end - attribute \src "ls180.v:7175.8-7175.99" - cell $and $and$ls180.v:7175$2220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_tx_fifo_syncfifo_we - connect \B \main_libresocsim_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:7175$2220_Y - end - attribute \src "ls180.v:7175.7-7175.143" - cell $and $and$ls180.v:7175$2222 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7175$2220_Y - connect \B $not$ls180.v:7175$2221_Y - connect \Y $and$ls180.v:7175$2222_Y - end - attribute \src "ls180.v:7191.8-7191.99" - cell $and $and$ls180.v:7191$2226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_rx_fifo_syncfifo_we - connect \B \main_libresocsim_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:7191$2226_Y - end - attribute \src "ls180.v:7191.7-7191.143" - cell $and $and$ls180.v:7191$2228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7191$2226_Y - connect \B $not$ls180.v:7191$2227_Y - connect \Y $and$ls180.v:7191$2228_Y - end - attribute \src "ls180.v:7197.8-7197.99" - cell $and $and$ls180.v:7197$2231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_rx_fifo_syncfifo_we - connect \B \main_libresocsim_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:7197$2231_Y - end - attribute \src "ls180.v:7197.7-7197.143" - cell $and $and$ls180.v:7197$2233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7197$2231_Y - connect \B $not$ls180.v:7197$2232_Y - connect \Y $and$ls180.v:7197$2233_Y - end - attribute \src "ls180.v:7236.7-7236.87" - cell $and $and$ls180.v:7236$2240 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7236$2239_Y - connect \B \main_libresocsim_timer_zero_old_trigger - connect \Y $and$ls180.v:7236$2240_Y - end - attribute \src "ls180.v:7244.7-7244.56" - cell $and $and$ls180.v:7244$2242 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_timer_wait - connect \B $not$ls180.v:7244$2241_Y - connect \Y $and$ls180.v:7244$2242_Y - end - attribute \src "ls180.v:7272.7-7272.75" - cell $and $and$ls180.v:7272$2249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_start1 - connect \B $eq$ls180.v:7272$2248_Y - connect \Y $and$ls180.v:7272$2249_Y - end - attribute \src "ls180.v:7314.8-7314.131" - cell $and $and$ls180.v:7314$2255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7314$2255_Y - end - attribute \src "ls180.v:7314.7-7314.190" - cell $and $and$ls180.v:7314$2257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7314$2255_Y - connect \B $not$ls180.v:7314$2256_Y - connect \Y $and$ls180.v:7314$2257_Y - end - attribute \src "ls180.v:7320.8-7320.131" - cell $and $and$ls180.v:7320$2260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7320$2260_Y - end - attribute \src "ls180.v:7320.7-7320.190" - cell $and $and$ls180.v:7320$2262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7320$2260_Y - connect \B $not$ls180.v:7320$2261_Y - connect \Y $and$ls180.v:7320$2262_Y - end - attribute \src "ls180.v:7360.8-7360.131" - cell $and $and$ls180.v:7360$2271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7360$2271_Y - end - attribute \src "ls180.v:7360.7-7360.190" - cell $and $and$ls180.v:7360$2273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7360$2271_Y - connect \B $not$ls180.v:7360$2272_Y - connect \Y $and$ls180.v:7360$2273_Y - end - attribute \src "ls180.v:7366.8-7366.131" - cell $and $and$ls180.v:7366$2276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7366$2276_Y - end - attribute \src "ls180.v:7366.7-7366.190" - cell $and $and$ls180.v:7366$2278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7366$2276_Y - connect \B $not$ls180.v:7366$2277_Y - connect \Y $and$ls180.v:7366$2278_Y - end - attribute \src "ls180.v:7406.8-7406.131" - cell $and $and$ls180.v:7406$2287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7406$2287_Y - end - attribute \src "ls180.v:7406.7-7406.190" - cell $and $and$ls180.v:7406$2289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7406$2287_Y - connect \B $not$ls180.v:7406$2288_Y - connect \Y $and$ls180.v:7406$2289_Y - end - attribute \src "ls180.v:7412.8-7412.131" - cell $and $and$ls180.v:7412$2292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7412$2292_Y - end - attribute \src "ls180.v:7412.7-7412.190" - cell $and $and$ls180.v:7412$2294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7412$2292_Y - connect \B $not$ls180.v:7412$2293_Y - connect \Y $and$ls180.v:7412$2294_Y - end - attribute \src "ls180.v:7452.8-7452.131" - cell $and $and$ls180.v:7452$2303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:7452$2303_Y - end - attribute \src "ls180.v:7452.7-7452.190" - cell $and $and$ls180.v:7452$2305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7452$2303_Y - connect \B $not$ls180.v:7452$2304_Y - connect \Y $and$ls180.v:7452$2305_Y - end - attribute \src "ls180.v:7458.8-7458.131" - cell $and $and$ls180.v:7458$2308 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:7458$2308_Y - end - attribute \src "ls180.v:7458.7-7458.190" - cell $and $and$ls180.v:7458$2310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7458$2308_Y - connect \B $not$ls180.v:7458$2309_Y - connect \Y $and$ls180.v:7458$2310_Y - end - attribute \src "ls180.v:7655.48-7655.124" - cell $and $and$ls180.v:7655$2335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7655$2334_Y - connect \B \main_sdram_interface_bank0_wdata_ready - connect \Y $and$ls180.v:7655$2335_Y - end - attribute \src "ls180.v:7655.130-7655.206" - cell $and $and$ls180.v:7655$2338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7655$2337_Y - connect \B \main_sdram_interface_bank1_wdata_ready - connect \Y $and$ls180.v:7655$2338_Y - end - attribute \src "ls180.v:7655.212-7655.288" - cell $and $and$ls180.v:7655$2341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7655$2340_Y - connect \B \main_sdram_interface_bank2_wdata_ready - connect \Y $and$ls180.v:7655$2341_Y - end - attribute \src "ls180.v:7655.294-7655.370" - cell $and $and$ls180.v:7655$2344 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7655$2343_Y - connect \B \main_sdram_interface_bank3_wdata_ready - connect \Y $and$ls180.v:7655$2344_Y - end - attribute \src "ls180.v:7656.49-7656.125" - cell $and $and$ls180.v:7656$2347 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7656$2346_Y - connect \B \main_sdram_interface_bank0_rdata_valid - connect \Y $and$ls180.v:7656$2347_Y - end - attribute \src "ls180.v:7656.131-7656.207" - cell $and $and$ls180.v:7656$2350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7656$2349_Y - connect \B \main_sdram_interface_bank1_rdata_valid - connect \Y $and$ls180.v:7656$2350_Y - end - attribute \src "ls180.v:7656.213-7656.289" - cell $and $and$ls180.v:7656$2353 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7656$2352_Y - connect \B \main_sdram_interface_bank2_rdata_valid - connect \Y $and$ls180.v:7656$2353_Y - end - attribute \src "ls180.v:7656.295-7656.371" - cell $and $and$ls180.v:7656$2356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7656$2355_Y - connect \B \main_sdram_interface_bank3_rdata_valid - connect \Y $and$ls180.v:7656$2356_Y - end - attribute \src "ls180.v:7675.8-7675.49" - cell $and $and$ls180.v:7675$2359 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_valid - connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:7675$2359_Y - end - attribute \src "ls180.v:7678.8-7678.53" - cell $and $and$ls180.v:7678$2360 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_wdata_valid - connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:7678$2360_Y - end - attribute \src "ls180.v:7744.7-7744.98" - cell $and $and$ls180.v:7744$2372 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdr_cmdr_converter_source_valid - connect \B \libresocsim_cmdr_cmdr_converter_source_ready - connect \Y $and$ls180.v:7744$2372_Y - end - attribute \src "ls180.v:7745.8-7745.95" - cell $and $and$ls180.v:7745$2373 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdr_cmdr_converter_sink_valid - connect \B \libresocsim_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:7745$2373_Y - end - attribute \src "ls180.v:7753.8-7753.95" - cell $and $and$ls180.v:7753$2374 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdr_cmdr_converter_sink_valid - connect \B \libresocsim_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:7753$2374_Y - end - attribute \src "ls180.v:7825.7-7825.100" - cell $and $and$ls180.v:7825$2384 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_dataw_crcr_converter_source_valid - connect \B \libresocsim_dataw_crcr_converter_source_ready - connect \Y $and$ls180.v:7825$2384_Y - end - attribute \src "ls180.v:7826.8-7826.97" - cell $and $and$ls180.v:7826$2385 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_dataw_crcr_converter_sink_valid - connect \B \libresocsim_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:7826$2385_Y - end - attribute \src "ls180.v:7834.8-7834.97" - cell $and $and$ls180.v:7834$2386 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_dataw_crcr_converter_sink_valid - connect \B \libresocsim_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:7834$2386_Y - end - attribute \src "ls180.v:7904.7-7904.102" - cell $and $and$ls180.v:7904$2396 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_datar_datar_converter_source_valid - connect \B \libresocsim_datar_datar_converter_source_ready - connect \Y $and$ls180.v:7904$2396_Y - end - attribute \src "ls180.v:7905.8-7905.99" - cell $and $and$ls180.v:7905$2397 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_datar_datar_converter_sink_valid - connect \B \libresocsim_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:7905$2397_Y - end - attribute \src "ls180.v:7913.8-7913.99" - cell $and $and$ls180.v:7913$2398 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_datar_datar_converter_sink_valid - connect \B \libresocsim_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:7913$2398_Y - end - attribute \src "ls180.v:8004.7-8004.96" - cell $and $and$ls180.v:8004$2404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_sink_ready - connect \B \libresocsim_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8004$2404_Y - end - attribute \src "ls180.v:8007.7-8007.96" - cell $and $and$ls180.v:8007$2405 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_sink_ready - connect \B \libresocsim_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8007$2405_Y - end - attribute \src "ls180.v:8010.7-8010.96" - cell $and $and$ls180.v:8010$2406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_sink_ready - connect \B \libresocsim_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8010$2406_Y - end - attribute \src "ls180.v:8013.7-8013.96" - cell $and $and$ls180.v:8013$2407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_sink_ready - connect \B \libresocsim_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8013$2407_Y - end - attribute \src "ls180.v:8016.7-8016.96" - cell $and $and$ls180.v:8016$2408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_sink_valid - connect \B \libresocsim_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8016$2408_Y - end - attribute \src "ls180.v:8021.7-8021.96" - cell $and $and$ls180.v:8021$2409 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_sink_valid - connect \B \libresocsim_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8021$2409_Y - end - attribute \src "ls180.v:8026.7-8026.96" - cell $and $and$ls180.v:8026$2410 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_sink_valid - connect \B \libresocsim_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8026$2410_Y - end - attribute \src "ls180.v:8031.7-8031.96" - cell $and $and$ls180.v:8031$2411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_sink_valid - connect \B \libresocsim_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8031$2411_Y - end - attribute \src "ls180.v:8036.7-8036.96" - cell $and $and$ls180.v:8036$2412 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_sink_valid - connect \B \libresocsim_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8036$2412_Y - end - attribute \src "ls180.v:8101.8-8101.97" - cell $and $and$ls180.v:8101$2415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdblock2mem_fifo_syncfifo_we - connect \B \libresocsim_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8101$2415_Y - end - attribute \src "ls180.v:8101.7-8101.140" - cell $and $and$ls180.v:8101$2417 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8101$2415_Y - connect \B $not$ls180.v:8101$2416_Y - connect \Y $and$ls180.v:8101$2417_Y - end - attribute \src "ls180.v:8107.8-8107.97" - cell $and $and$ls180.v:8107$2420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdblock2mem_fifo_syncfifo_we - connect \B \libresocsim_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8107$2420_Y - end - attribute \src "ls180.v:8107.7-8107.140" - cell $and $and$ls180.v:8107$2422 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8107$2420_Y - connect \B $not$ls180.v:8107$2421_Y - connect \Y $and$ls180.v:8107$2422_Y - end - attribute \src "ls180.v:8127.7-8127.102" - cell $and $and$ls180.v:8127$2429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdblock2mem_converter_source_valid - connect \B \libresocsim_sdblock2mem_converter_source_ready - connect \Y $and$ls180.v:8127$2429_Y - end - attribute \src "ls180.v:8128.8-8128.99" - cell $and $and$ls180.v:8128$2430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdblock2mem_converter_sink_valid - connect \B \libresocsim_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8128$2430_Y - end - attribute \src "ls180.v:8136.8-8136.99" - cell $and $and$ls180.v:8136$2431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdblock2mem_converter_sink_valid - connect \B \libresocsim_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8136$2431_Y - end - attribute \src "ls180.v:8180.7-8180.102" - cell $and $and$ls180.v:8180$2435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdmem2block_converter_source_valid - connect \B \libresocsim_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:8180$2435_Y - end - attribute \src "ls180.v:8187.8-8187.97" - cell $and $and$ls180.v:8187$2437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdmem2block_fifo_syncfifo_we - connect \B \libresocsim_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8187$2437_Y - end - attribute \src "ls180.v:8187.7-8187.140" - cell $and $and$ls180.v:8187$2439 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8187$2437_Y - connect \B $not$ls180.v:8187$2438_Y - connect \Y $and$ls180.v:8187$2439_Y - end - attribute \src "ls180.v:8193.8-8193.97" - cell $and $and$ls180.v:8193$2442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdmem2block_fifo_syncfifo_we - connect \B \libresocsim_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8193$2442_Y - end - attribute \src "ls180.v:8193.7-8193.140" - cell $and $and$ls180.v:8193$2444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8193$2442_Y - connect \B $not$ls180.v:8193$2443_Y - connect \Y $and$ls180.v:8193$2444_Y - end - attribute \src "ls180.v:2631.42-2631.101" - cell $eq $eq$ls180.v:2631$18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface0_converted_interface_sel - connect \B 1'0 - connect \Y $eq$ls180.v:2631$18_Y - end - attribute \src "ls180.v:2638.11-2638.54" - cell $eq $eq$ls180.v:2638$23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter0_counter - connect \B 1'1 - connect \Y $eq$ls180.v:2638$23_Y - end - attribute \src "ls180.v:2691.42-2691.101" - cell $eq $eq$ls180.v:2691$29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface1_converted_interface_sel - connect \B 1'0 - connect \Y $eq$ls180.v:2691$29_Y - end - attribute \src "ls180.v:2698.11-2698.54" - cell $eq $eq$ls180.v:2698$34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter1_counter - connect \B 1'1 - connect \Y $eq$ls180.v:2698$34_Y - end - attribute \src "ls180.v:3004.34-3004.65" - cell $eq $eq$ls180.v:3004$102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_timer_count1 - connect \B 1'0 - connect \Y $eq$ls180.v:3004$102_Y - end - attribute \src "ls180.v:3008.68-3008.102" - cell $eq $eq$ls180.v:3008$105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_count - connect \B 1'0 - connect \Y $eq$ls180.v:3008$105_Y - end - attribute \src "ls180.v:3052.43-3052.134" - cell $eq $eq$ls180.v:3052$110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_row - connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3052$110_Y - end - attribute \src "ls180.v:3069.47-3069.88" - cell $eq $eq$ls180.v:3069$123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_row_close - connect \B 1'0 - connect \Y $eq$ls180.v:3069$123_Y - end - attribute \src "ls180.v:3209.43-3209.134" - cell $eq $eq$ls180.v:3209$140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_row - connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3209$140_Y - end - attribute \src "ls180.v:3226.47-3226.88" - cell $eq $eq$ls180.v:3226$153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_row_close - connect \B 1'0 - connect \Y $eq$ls180.v:3226$153_Y - end - attribute \src "ls180.v:3366.43-3366.134" - cell $eq $eq$ls180.v:3366$170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_row - connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3366$170_Y - end - attribute \src "ls180.v:3383.47-3383.88" - cell $eq $eq$ls180.v:3383$183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_row_close - connect \B 1'0 - connect \Y $eq$ls180.v:3383$183_Y - end - attribute \src "ls180.v:3523.43-3523.134" - cell $eq $eq$ls180.v:3523$200 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_row - connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3523$200_Y - end - attribute \src "ls180.v:3540.47-3540.88" - cell $eq $eq$ls180.v:3540$213 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_row_close - connect \B 1'0 - connect \Y $eq$ls180.v:3540$213_Y - end - attribute \src "ls180.v:3677.32-3677.56" - cell $eq $eq$ls180.v:3677$260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_time0 - connect \B 1'0 - connect \Y $eq$ls180.v:3677$260_Y - end - attribute \src "ls180.v:3678.32-3678.56" - cell $eq $eq$ls180.v:3678$261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_time1 - connect \B 1'0 - connect \Y $eq$ls180.v:3678$261_Y - end - attribute \src "ls180.v:3689.339-3689.418" - cell $eq $eq$ls180.v:3689$275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_read - connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3689$275_Y - end - attribute \src "ls180.v:3689.423-3689.504" - cell $eq $eq$ls180.v:3689$276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_write - connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3689$276_Y - end - attribute \src "ls180.v:3690.339-3690.418" - cell $eq $eq$ls180.v:3690$288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_read - connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3690$288_Y - end - attribute \src "ls180.v:3690.423-3690.504" - cell $eq $eq$ls180.v:3690$289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_write - connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3690$289_Y - end - attribute \src "ls180.v:3691.339-3691.418" - cell $eq $eq$ls180.v:3691$301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_read - connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3691$301_Y - end - attribute \src "ls180.v:3691.423-3691.504" - cell $eq $eq$ls180.v:3691$302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_write - connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3691$302_Y - end - attribute \src "ls180.v:3692.339-3692.418" - cell $eq $eq$ls180.v:3692$314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_read - connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3692$314_Y - end - attribute \src "ls180.v:3692.423-3692.504" - cell $eq $eq$ls180.v:3692$315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_write - connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3692$315_Y - end - attribute \src "ls180.v:3722.339-3722.418" - cell $eq $eq$ls180.v:3722$333 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_read - connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3722$333_Y - end - attribute \src "ls180.v:3722.423-3722.504" - cell $eq $eq$ls180.v:3722$334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_write - connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3722$334_Y - end - attribute \src "ls180.v:3723.339-3723.418" - cell $eq $eq$ls180.v:3723$346 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_read - connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3723$346_Y - end - attribute \src "ls180.v:3723.423-3723.504" - cell $eq $eq$ls180.v:3723$347 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_write - connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3723$347_Y - end - attribute \src "ls180.v:3724.339-3724.418" - cell $eq $eq$ls180.v:3724$359 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_read - connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3724$359_Y - end - attribute \src "ls180.v:3724.423-3724.504" - cell $eq $eq$ls180.v:3724$360 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_write - connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3724$360_Y - end - attribute \src "ls180.v:3725.339-3725.418" - cell $eq $eq$ls180.v:3725$372 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_read - connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3725$372_Y - end - attribute \src "ls180.v:3725.423-3725.504" - cell $eq $eq$ls180.v:3725$373 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_write - connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3725$373_Y - end - attribute \src "ls180.v:3754.78-3754.113" - cell $eq $eq$ls180.v:3754$382 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3754$382_Y - end - attribute \src "ls180.v:3757.78-3757.113" - cell $eq $eq$ls180.v:3757$385 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3757$385_Y - end - attribute \src "ls180.v:3763.78-3763.113" - cell $eq $eq$ls180.v:3763$389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_grant - connect \B 1'1 - connect \Y $eq$ls180.v:3763$389_Y - end - attribute \src "ls180.v:3766.78-3766.113" - cell $eq $eq$ls180.v:3766$392 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_grant - connect \B 1'1 - connect \Y $eq$ls180.v:3766$392_Y - end - attribute \src "ls180.v:3772.78-3772.113" - cell $eq $eq$ls180.v:3772$396 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_grant - connect \B 2'10 - connect \Y $eq$ls180.v:3772$396_Y - end - attribute \src "ls180.v:3775.78-3775.113" - cell $eq $eq$ls180.v:3775$399 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_grant - connect \B 2'10 - connect \Y $eq$ls180.v:3775$399_Y - end - attribute \src "ls180.v:3781.78-3781.113" - cell $eq $eq$ls180.v:3781$403 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_grant - connect \B 2'11 - connect \Y $eq$ls180.v:3781$403_Y - end - attribute \src "ls180.v:3784.78-3784.113" - cell $eq $eq$ls180.v:3784$406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_grant - connect \B 2'11 - connect \Y $eq$ls180.v:3784$406_Y - end - attribute \src "ls180.v:3865.42-3865.82" - cell $eq $eq$ls180.v:3865$429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'0 - connect \Y $eq$ls180.v:3865$429_Y - end - attribute \src "ls180.v:3865.145-3865.178" - cell $eq $eq$ls180.v:3865$430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3865$430_Y - end - attribute \src "ls180.v:3865.220-3865.253" - cell $eq $eq$ls180.v:3865$433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3865$433_Y - end - attribute \src "ls180.v:3865.295-3865.328" - cell $eq $eq$ls180.v:3865$436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3865$436_Y - end - attribute \src "ls180.v:3870.42-3870.82" - cell $eq $eq$ls180.v:3870$445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'1 - connect \Y $eq$ls180.v:3870$445_Y - end - attribute \src "ls180.v:3870.145-3870.178" - cell $eq $eq$ls180.v:3870$446 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3870$446_Y - end - attribute \src "ls180.v:3870.220-3870.253" - cell $eq $eq$ls180.v:3870$449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3870$449_Y - end - attribute \src "ls180.v:3870.295-3870.328" - cell $eq $eq$ls180.v:3870$452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3870$452_Y - end - attribute \src "ls180.v:3875.42-3875.82" - cell $eq $eq$ls180.v:3875$461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'10 - connect \Y $eq$ls180.v:3875$461_Y - end - attribute \src "ls180.v:3875.145-3875.178" - cell $eq $eq$ls180.v:3875$462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3875$462_Y - end - attribute \src "ls180.v:3875.220-3875.253" - cell $eq $eq$ls180.v:3875$465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3875$465_Y - end - attribute \src "ls180.v:3875.295-3875.328" - cell $eq $eq$ls180.v:3875$468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3875$468_Y - end - attribute \src "ls180.v:3880.42-3880.82" - cell $eq $eq$ls180.v:3880$477 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'11 - connect \Y $eq$ls180.v:3880$477_Y - end - attribute \src "ls180.v:3880.145-3880.178" - cell $eq $eq$ls180.v:3880$478 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3880$478_Y - end - attribute \src "ls180.v:3880.220-3880.253" - cell $eq $eq$ls180.v:3880$481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3880$481_Y - end - attribute \src "ls180.v:3880.295-3880.328" - cell $eq $eq$ls180.v:3880$484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3880$484_Y - end - attribute \src "ls180.v:3885.44-3885.77" - cell $eq $eq$ls180.v:3885$493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3885$493_Y - end - attribute \src "ls180.v:3885.83-3885.123" - cell $eq $eq$ls180.v:3885$494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'0 - connect \Y $eq$ls180.v:3885$494_Y - end - attribute \src "ls180.v:3885.186-3885.219" - cell $eq $eq$ls180.v:3885$495 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3885$495_Y - end - attribute \src "ls180.v:3885.261-3885.294" - cell $eq $eq$ls180.v:3885$498 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3885$498_Y - end - attribute \src "ls180.v:3885.336-3885.369" - cell $eq $eq$ls180.v:3885$501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3885$501_Y - end - attribute \src "ls180.v:3885.418-3885.451" - cell $eq $eq$ls180.v:3885$509 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3885$509_Y - end - attribute \src "ls180.v:3885.457-3885.497" - cell $eq $eq$ls180.v:3885$510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'1 - connect \Y $eq$ls180.v:3885$510_Y - end - attribute \src "ls180.v:3885.560-3885.593" - cell $eq $eq$ls180.v:3885$511 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3885$511_Y - end - attribute \src "ls180.v:3885.635-3885.668" - cell $eq $eq$ls180.v:3885$514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3885$514_Y - end - attribute \src "ls180.v:3885.710-3885.743" - cell $eq $eq$ls180.v:3885$517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3885$517_Y - end - attribute \src "ls180.v:3885.792-3885.825" - cell $eq $eq$ls180.v:3885$525 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3885$525_Y - end - attribute \src "ls180.v:3885.831-3885.871" - cell $eq $eq$ls180.v:3885$526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'10 - connect \Y $eq$ls180.v:3885$526_Y - end - attribute \src "ls180.v:3885.934-3885.967" - cell $eq $eq$ls180.v:3885$527 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3885$527_Y - end - attribute \src "ls180.v:3885.1009-3885.1042" - cell $eq $eq$ls180.v:3885$530 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3885$530_Y - end - attribute \src "ls180.v:3885.1084-3885.1117" - cell $eq $eq$ls180.v:3885$533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3885$533_Y - end - attribute \src "ls180.v:3885.1166-3885.1199" - cell $eq $eq$ls180.v:3885$541 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3885$541_Y - end - attribute \src "ls180.v:3885.1205-3885.1245" - cell $eq $eq$ls180.v:3885$542 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'11 - connect \Y $eq$ls180.v:3885$542_Y - end - attribute \src "ls180.v:3885.1308-3885.1341" - cell $eq $eq$ls180.v:3885$543 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3885$543_Y - end - attribute \src "ls180.v:3885.1383-3885.1416" - cell $eq $eq$ls180.v:3885$546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3885$546_Y - end - attribute \src "ls180.v:3885.1458-3885.1491" - cell $eq $eq$ls180.v:3885$549 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3885$549_Y - end - attribute \src "ls180.v:3944.29-3944.57" - cell $eq $eq$ls180.v:3944$562 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_sel - connect \B 1'0 - connect \Y $eq$ls180.v:3944$562_Y - end - attribute \src "ls180.v:3951.11-3951.41" - cell $eq $eq$ls180.v:3951$567 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter_counter - connect \B 1'1 - connect \Y $eq$ls180.v:3951$567_Y - end - attribute \src "ls180.v:3988.25-3988.78" - cell $eq $eq$ls180.v:3988$593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_clk_divider1 - connect \B $sub$ls180.v:3988$592_Y - connect \Y $eq$ls180.v:3988$593_Y - end - attribute \src "ls180.v:3989.25-3989.72" - cell $eq $eq$ls180.v:3989$595 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_clk_divider1 - connect \B $sub$ls180.v:3989$594_Y - connect \Y $eq$ls180.v:3989$595_Y - end - attribute \src "ls180.v:4016.10-4016.45" - cell $eq $eq$ls180.v:4016$599 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \main_count - connect \B $sub$ls180.v:4016$598_Y - connect \Y $eq$ls180.v:4016$599_Y - end - attribute \src "ls180.v:4116.10-4116.41" - cell $eq $eq$ls180.v:4116$626 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \libresocsim_init_count - connect \B 7'1001111 - connect \Y $eq$ls180.v:4116$626_Y - end - attribute \src "ls180.v:4173.10-4173.40" - cell $eq $eq$ls180.v:4173$629 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdw_count - connect \B 3'111 - connect \Y $eq$ls180.v:4173$629_Y - end - attribute \src "ls180.v:4190.10-4190.40" - cell $eq $eq$ls180.v:4190$631 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdw_count - connect \B 3'111 - connect \Y $eq$ls180.v:4190$631_Y - end - attribute \src "ls180.v:4218.39-4218.90" - cell $eq $eq$ls180.v:4218$633 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdr_cmdr_pads_in_payload_cmd_i - connect \B 1'0 - connect \Y $eq$ls180.v:4218$633_Y - end - attribute \src "ls180.v:4268.9-4268.41" - cell $eq $eq$ls180.v:4268$643 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdr_timeout - connect \B 1'0 - connect \Y $eq$ls180.v:4268$643_Y - end - attribute \src "ls180.v:4277.37-4277.108" - cell $eq $eq$ls180.v:4277$645 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdr_count - connect \B $sub$ls180.v:4277$644_Y - connect \Y $eq$ls180.v:4277$645_Y - end - attribute \src "ls180.v:4296.9-4296.41" - cell $eq $eq$ls180.v:4296$649 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdr_timeout - connect \B 1'0 - connect \Y $eq$ls180.v:4296$649_Y - end - attribute \src "ls180.v:4308.10-4308.40" - cell $eq $eq$ls180.v:4308$651 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdr_count - connect \B 3'111 - connect \Y $eq$ls180.v:4308$651_Y - end - attribute \src "ls180.v:4345.40-4345.96" - cell $eq $eq$ls180.v:4345$655 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_dataw_crcr_pads_in_payload_data_i [0] - connect \B 1'0 - connect \Y $eq$ls180.v:4345$655_Y - end - attribute \src "ls180.v:4382.33-4382.91" - cell $eq $eq$ls180.v:4382$664 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \libresocsim_dataw_crcr_source_source_payload_data0 - connect \B 3'101 - connect \Y $eq$ls180.v:4382$664_Y - end - attribute \src "ls180.v:4430.10-4430.41" - cell $eq $eq$ls180.v:4430$668 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_dataw_count - connect \B 1'1 - connect \Y $eq$ls180.v:4430$668_Y - end - attribute \src "ls180.v:4479.41-4479.100" - cell $eq $eq$ls180.v:4479$670 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_datar_datar_pads_in_payload_data_i - connect \B 1'0 - connect \Y $eq$ls180.v:4479$670_Y - end - attribute \src "ls180.v:4530.9-4530.42" - cell $eq $eq$ls180.v:4530$680 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_datar_timeout - connect \B 1'0 - connect \Y $eq$ls180.v:4530$680_Y - end - attribute \src "ls180.v:4539.38-4539.126" - cell $eq $eq$ls180.v:4539$683 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \libresocsim_datar_count - connect \B $sub$ls180.v:4539$682_Y - connect \Y $eq$ls180.v:4539$683_Y - end - attribute \src "ls180.v:4562.9-4562.42" - cell $eq $eq$ls180.v:4562$686 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_datar_timeout - connect \B 1'0 - connect \Y $eq$ls180.v:4562$686_Y - end - attribute \src "ls180.v:4572.10-4572.42" - cell $eq $eq$ls180.v:4572$688 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \libresocsim_datar_count - connect \B 6'100111 - connect \Y $eq$ls180.v:4572$688_Y - end - attribute \src "ls180.v:4741.9-4741.54" - cell $eq $eq$ls180.v:4741$870 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:4741$870_Y - end - attribute \src "ls180.v:4771.10-4771.55" - cell $eq $eq$ls180.v:4771$871 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:4771$871_Y - end - attribute \src "ls180.v:4802.10-4802.92" - cell $eq $eq$ls180.v:4802$876 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_fifo0 - connect \B \libresocsim_sdcore_crc16_checker_crctmp0 - connect \Y $eq$ls180.v:4802$876_Y - end - attribute \src "ls180.v:4802.97-4802.179" - cell $eq $eq$ls180.v:4802$877 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_fifo1 - connect \B \libresocsim_sdcore_crc16_checker_crctmp1 - connect \Y $eq$ls180.v:4802$877_Y - end - attribute \src "ls180.v:4802.185-4802.267" - cell $eq $eq$ls180.v:4802$879 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_fifo2 - connect \B \libresocsim_sdcore_crc16_checker_crctmp2 - connect \Y $eq$ls180.v:4802$879_Y - end - attribute \src "ls180.v:4802.273-4802.355" - cell $eq $eq$ls180.v:4802$881 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_fifo3 - connect \B \libresocsim_sdcore_crc16_checker_crctmp3 - connect \Y $eq$ls180.v:4802$881_Y - end - attribute \src "ls180.v:4810.7-4810.51" - cell $eq $eq$ls180.v:4810$885 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:4810$885_Y - end - attribute \src "ls180.v:4820.7-4820.51" - cell $eq $eq$ls180.v:4820$888 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:4820$888_Y - end - attribute \src "ls180.v:4830.7-4830.51" - cell $eq $eq$ls180.v:4830$891 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:4830$891_Y - end - attribute \src "ls180.v:4840.7-4840.51" - cell $eq $eq$ls180.v:4840$894 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:4840$894_Y - end - attribute \src "ls180.v:4964.37-4964.72" - cell $eq $eq$ls180.v:4964$945 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_cmd_type - connect \B 1'0 - connect \Y $eq$ls180.v:4964$945_Y - end - attribute \src "ls180.v:4970.10-4970.46" - cell $eq $eq$ls180.v:4970$948 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_cmd_count - connect \B 3'101 - connect \Y $eq$ls180.v:4970$948_Y - end - attribute \src "ls180.v:4971.11-4971.46" - cell $eq $eq$ls180.v:4971$949 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_cmd_type - connect \B 1'0 - connect \Y $eq$ls180.v:4971$949_Y - end - attribute \src "ls180.v:4983.35-4983.71" - cell $eq $eq$ls180.v:4983$950 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_data_type - connect \B 1'0 - connect \Y $eq$ls180.v:4983$950_Y - end - attribute \src "ls180.v:4984.9-4984.44" - cell $eq $eq$ls180.v:4984$951 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_cmd_type - connect \B 2'10 - connect \Y $eq$ls180.v:4984$951_Y - end - attribute \src "ls180.v:4991.10-4991.56" - cell $eq $eq$ls180.v:4991$952 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdr_source_payload_status - connect \B 1'1 - connect \Y $eq$ls180.v:4991$952_Y - end - attribute \src "ls180.v:4997.12-4997.48" - cell $eq $eq$ls180.v:4997$953 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_data_type - connect \B 2'10 - connect \Y $eq$ls180.v:4997$953_Y - end - attribute \src "ls180.v:5000.13-5000.49" - cell $eq $eq$ls180.v:5000$954 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_data_type - connect \B 1'1 - connect \Y $eq$ls180.v:5000$954_Y - end - attribute \src "ls180.v:5022.10-5022.90" - cell $eq $eq$ls180.v:5022$959 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_data_count - connect \B $sub$ls180.v:5022$958_Y - connect \Y $eq$ls180.v:5022$959_Y - end - attribute \src "ls180.v:5037.36-5037.116" - cell $eq $eq$ls180.v:5037$962 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_data_count - connect \B $sub$ls180.v:5037$961_Y - connect \Y $eq$ls180.v:5037$962_Y - end - attribute \src "ls180.v:5039.10-5039.57" - cell $eq $eq$ls180.v:5039$963 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_datar_source_payload_status - connect \B 1'0 - connect \Y $eq$ls180.v:5039$963_Y - end - attribute \src "ls180.v:5048.12-5048.92" - cell $eq $eq$ls180.v:5048$967 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_data_count - connect \B $sub$ls180.v:5048$966_Y - connect \Y $eq$ls180.v:5048$967_Y - end - attribute \src "ls180.v:5055.11-5055.58" - cell $eq $eq$ls180.v:5055$968 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_datar_source_payload_status - connect \B 1'1 - connect \Y $eq$ls180.v:5055$968_Y - end - attribute \src "ls180.v:5172.10-5172.119" - cell $eq $eq$ls180.v:5172$985 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdblock2mem_wishbonedmawriter_offset - connect \B $sub$ls180.v:5172$984_Y - connect \Y $eq$ls180.v:5172$985_Y - end - attribute \src "ls180.v:5262.46-5262.127" - cell $eq $eq$ls180.v:5262$991 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdmem2block_dma_offset - connect \B $sub$ls180.v:5262$990_Y - connect \Y $eq$ls180.v:5262$991_Y - end - attribute \src "ls180.v:5292.51-5292.96" - cell $eq $eq$ls180.v:5292$994 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdmem2block_converter_mux - connect \B 1'0 - connect \Y $eq$ls180.v:5292$994_Y - end - attribute \src "ls180.v:5293.50-5293.95" - cell $eq $eq$ls180.v:5293$995 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdmem2block_converter_mux - connect \B 2'11 - connect \Y $eq$ls180.v:5293$995_Y - end - attribute \src "ls180.v:5350.32-5350.99" - cell $eq $eq$ls180.v:5350$1008 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \libresocsim_clk_divider1 - connect \B $sub$ls180.v:5350$1007_Y - connect \Y $eq$ls180.v:5350$1008_Y - end - attribute \src "ls180.v:5351.32-5351.93" - cell $eq $eq$ls180.v:5351$1010 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \libresocsim_clk_divider1 - connect \B $sub$ls180.v:5351$1009_Y - connect \Y $eq$ls180.v:5351$1010_Y - end - attribute \src "ls180.v:5379.10-5379.59" - cell $eq $eq$ls180.v:5379$1014 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \libresocsim_count - connect \B $sub$ls180.v:5379$1013_Y - connect \Y $eq$ls180.v:5379$1014_Y - end - attribute \src "ls180.v:5451.85-5451.106" - cell $eq $eq$ls180.v:5451$1019 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 1'0 - connect \Y $eq$ls180.v:5451$1019_Y - end - attribute \src "ls180.v:5452.85-5452.106" - cell $eq $eq$ls180.v:5452$1021 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 1'1 - connect \Y $eq$ls180.v:5452$1021_Y - end - attribute \src "ls180.v:5453.64-5453.85" - cell $eq $eq$ls180.v:5453$1023 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 2'10 - connect \Y $eq$ls180.v:5453$1023_Y - end - attribute \src "ls180.v:5454.64-5454.85" - cell $eq $eq$ls180.v:5454$1025 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 2'11 - connect \Y $eq$ls180.v:5454$1025_Y - end - attribute \src "ls180.v:5455.85-5455.106" - cell $eq $eq$ls180.v:5455$1027 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 1'0 - connect \Y $eq$ls180.v:5455$1027_Y - end - attribute \src "ls180.v:5456.85-5456.106" - cell $eq $eq$ls180.v:5456$1029 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 1'1 - connect \Y $eq$ls180.v:5456$1029_Y - end - attribute \src "ls180.v:5457.64-5457.85" - cell $eq $eq$ls180.v:5457$1031 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 2'10 - connect \Y $eq$ls180.v:5457$1031_Y - end - attribute \src "ls180.v:5458.64-5458.85" - cell $eq $eq$ls180.v:5458$1033 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 2'11 - connect \Y $eq$ls180.v:5458$1033_Y - end - attribute \src "ls180.v:5462.27-5462.59" - cell $eq $eq$ls180.v:5462$1036 - parameter \A_SIGNED 0 - parameter \A_WIDTH 23 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:7] - connect \B 1'0 - connect \Y $eq$ls180.v:5462$1036_Y - end - attribute \src "ls180.v:5463.27-5463.68" - cell $eq $eq$ls180.v:5463$1037 - parameter \A_SIGNED 0 - parameter \A_WIDTH 27 - parameter \B_SIGNED 0 - parameter \B_WIDTH 27 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:3] - connect \B 27'110000000000000100000000000 - connect \Y $eq$ls180.v:5463$1037_Y - end - attribute \src "ls180.v:5464.27-5464.66" - cell $eq $eq$ls180.v:5464$1038 - parameter \A_SIGNED 0 - parameter \A_WIDTH 20 - parameter \B_SIGNED 0 - parameter \B_WIDTH 20 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:10] - connect \B 20'11000000000000010001 - connect \Y $eq$ls180.v:5464$1038_Y - end - attribute \src "ls180.v:5465.27-5465.61" - cell $eq $eq$ls180.v:5465$1039 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:23] - connect \B 7'1001000 - connect \Y $eq$ls180.v:5465$1039_Y - end - attribute \src "ls180.v:5466.27-5466.65" - cell $eq $eq$ls180.v:5466$1040 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:14] - connect \B 16'1100000000000000 - connect \Y $eq$ls180.v:5466$1040_Y - end - attribute \src "ls180.v:5522.24-5522.45" - cell $eq $eq$ls180.v:5522$1067 - parameter \A_SIGNED 0 - parameter \A_WIDTH 20 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_count - connect \B 1'0 - connect \Y $eq$ls180.v:5522$1067_Y - end - attribute \src "ls180.v:5523.32-5523.77" - cell $eq $eq$ls180.v:5523$1068 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [13:9] - connect \B 1'0 - connect \Y $eq$ls180.v:5523$1068_Y - end - attribute \src "ls180.v:5525.97-5525.141" - cell $eq $eq$ls180.v:5525$1070 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5525$1070_Y - end - attribute \src "ls180.v:5526.100-5526.144" - cell $eq $eq$ls180.v:5526$1074 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5526$1074_Y - end - attribute \src "ls180.v:5528.99-5528.143" - cell $eq $eq$ls180.v:5528$1077 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5528$1077_Y - end - attribute \src "ls180.v:5529.102-5529.146" - cell $eq $eq$ls180.v:5529$1081 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5529$1081_Y - end - attribute \src "ls180.v:5531.99-5531.143" - cell $eq $eq$ls180.v:5531$1084 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5531$1084_Y - end - attribute \src "ls180.v:5532.102-5532.146" - cell $eq $eq$ls180.v:5532$1088 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5532$1088_Y - end - attribute \src "ls180.v:5534.99-5534.143" - cell $eq $eq$ls180.v:5534$1091 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5534$1091_Y - end - attribute \src "ls180.v:5535.102-5535.146" - cell $eq $eq$ls180.v:5535$1095 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5535$1095_Y - end - attribute \src "ls180.v:5537.99-5537.143" - cell $eq $eq$ls180.v:5537$1098 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5537$1098_Y - end - attribute \src "ls180.v:5538.102-5538.146" - cell $eq $eq$ls180.v:5538$1102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5538$1102_Y - end - attribute \src "ls180.v:5540.102-5540.146" - cell $eq $eq$ls180.v:5540$1105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5540$1105_Y - end - attribute \src "ls180.v:5541.105-5541.149" - cell $eq $eq$ls180.v:5541$1109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5541$1109_Y - end - attribute \src "ls180.v:5543.102-5543.146" - cell $eq $eq$ls180.v:5543$1112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5543$1112_Y - end - attribute \src "ls180.v:5544.105-5544.149" - cell $eq $eq$ls180.v:5544$1116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5544$1116_Y - end - attribute \src "ls180.v:5546.102-5546.146" - cell $eq $eq$ls180.v:5546$1119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5546$1119_Y - end - attribute \src "ls180.v:5547.105-5547.149" - cell $eq $eq$ls180.v:5547$1123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5547$1123_Y - end - attribute \src "ls180.v:5549.102-5549.146" - cell $eq $eq$ls180.v:5549$1126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5549$1126_Y - end - attribute \src "ls180.v:5550.105-5550.149" - cell $eq $eq$ls180.v:5550$1130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5550$1130_Y - end - attribute \src "ls180.v:5561.32-5561.77" - cell $eq $eq$ls180.v:5561$1132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [13:9] - connect \B 3'110 - connect \Y $eq$ls180.v:5561$1132_Y - end - attribute \src "ls180.v:5563.93-5563.135" - cell $eq $eq$ls180.v:5563$1134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [0] - connect \B 1'0 - connect \Y $eq$ls180.v:5563$1134_Y - end - attribute \src "ls180.v:5564.96-5564.138" - cell $eq $eq$ls180.v:5564$1138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [0] - connect \B 1'0 - connect \Y $eq$ls180.v:5564$1138_Y - end - attribute \src "ls180.v:5567.32-5567.77" - cell $eq $eq$ls180.v:5567$1140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [13:9] - connect \B 3'111 - connect \Y $eq$ls180.v:5567$1140_Y - end - attribute \src "ls180.v:5569.93-5569.135" - cell $eq $eq$ls180.v:5569$1142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [0] - connect \B 1'0 - connect \Y $eq$ls180.v:5569$1142_Y - end - attribute \src "ls180.v:5570.96-5570.138" - cell $eq $eq$ls180.v:5570$1146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [0] - connect \B 1'0 - connect \Y $eq$ls180.v:5570$1146_Y - end - attribute \src "ls180.v:5573.32-5573.78" - cell $eq $eq$ls180.v:5573$1148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [13:9] - connect \B 4'1011 - connect \Y $eq$ls180.v:5573$1148_Y - end - attribute \src "ls180.v:5575.100-5575.144" - cell $eq $eq$ls180.v:5575$1150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5575$1150_Y - end - attribute \src "ls180.v:5576.103-5576.147" - cell $eq $eq$ls180.v:5576$1154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5576$1154_Y - end - attribute \src "ls180.v:5578.100-5578.144" - cell $eq $eq$ls180.v:5578$1157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5578$1157_Y - end - attribute \src "ls180.v:5579.103-5579.147" - cell $eq $eq$ls180.v:5579$1161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5579$1161_Y - end - attribute \src "ls180.v:5581.100-5581.144" - cell $eq $eq$ls180.v:5581$1164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5581$1164_Y - end - attribute \src "ls180.v:5582.103-5582.147" - cell $eq $eq$ls180.v:5582$1168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5582$1168_Y - end - attribute \src "ls180.v:5584.100-5584.144" - cell $eq $eq$ls180.v:5584$1171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5584$1171_Y - end - attribute \src "ls180.v:5585.103-5585.147" - cell $eq $eq$ls180.v:5585$1175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5585$1175_Y - end - attribute \src "ls180.v:5587.100-5587.144" - cell $eq $eq$ls180.v:5587$1178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5587$1178_Y - end - attribute \src "ls180.v:5588.103-5588.147" - cell $eq $eq$ls180.v:5588$1182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5588$1182_Y - end - attribute \src "ls180.v:5590.100-5590.144" - cell $eq $eq$ls180.v:5590$1185 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5590$1185_Y - end - attribute \src "ls180.v:5591.103-5591.147" - cell $eq $eq$ls180.v:5591$1189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5591$1189_Y - end - attribute \src "ls180.v:5593.100-5593.144" - cell $eq $eq$ls180.v:5593$1192 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5593$1192_Y - end - attribute \src "ls180.v:5594.103-5594.147" - cell $eq $eq$ls180.v:5594$1196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5594$1196_Y - end - attribute \src "ls180.v:5596.100-5596.144" - cell $eq $eq$ls180.v:5596$1199 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5596$1199_Y - end - attribute \src "ls180.v:5597.103-5597.147" - cell $eq $eq$ls180.v:5597$1203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5597$1203_Y - end - attribute \src "ls180.v:5599.102-5599.146" - cell $eq $eq$ls180.v:5599$1206 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5599$1206_Y - end - attribute \src "ls180.v:5600.105-5600.149" - cell $eq $eq$ls180.v:5600$1210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5600$1210_Y - end - attribute \src "ls180.v:5602.102-5602.146" - cell $eq $eq$ls180.v:5602$1213 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:5602$1213_Y - end - attribute \src "ls180.v:5603.105-5603.149" - cell $eq $eq$ls180.v:5603$1217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:5603$1217_Y - end - attribute \src "ls180.v:5605.102-5605.147" - cell $eq $eq$ls180.v:5605$1220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:5605$1220_Y - end - attribute \src "ls180.v:5606.105-5606.150" - cell $eq $eq$ls180.v:5606$1224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:5606$1224_Y - end - attribute \src "ls180.v:5608.102-5608.147" - cell $eq $eq$ls180.v:5608$1227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:5608$1227_Y - end - attribute \src "ls180.v:5609.105-5609.150" - cell $eq $eq$ls180.v:5609$1231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:5609$1231_Y - end - attribute \src "ls180.v:5611.102-5611.147" - cell $eq $eq$ls180.v:5611$1234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:5611$1234_Y - end - attribute \src "ls180.v:5612.105-5612.150" - cell $eq $eq$ls180.v:5612$1238 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:5612$1238_Y - end - attribute \src "ls180.v:5614.99-5614.144" - cell $eq $eq$ls180.v:5614$1241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:5614$1241_Y - end - attribute \src "ls180.v:5615.102-5615.147" - cell $eq $eq$ls180.v:5615$1245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:5615$1245_Y - end - attribute \src "ls180.v:5617.100-5617.145" - cell $eq $eq$ls180.v:5617$1248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:5617$1248_Y - end - attribute \src "ls180.v:5618.103-5618.148" - cell $eq $eq$ls180.v:5618$1252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:5618$1252_Y - end - attribute \src "ls180.v:5635.32-5635.78" - cell $eq $eq$ls180.v:5635$1254 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [13:9] - connect \B 4'1010 - connect \Y $eq$ls180.v:5635$1254_Y - end - attribute \src "ls180.v:5637.104-5637.148" - cell $eq $eq$ls180.v:5637$1256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5637$1256_Y - end - attribute \src "ls180.v:5638.107-5638.151" - cell $eq $eq$ls180.v:5638$1260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5638$1260_Y - end - attribute \src "ls180.v:5640.104-5640.148" - cell $eq $eq$ls180.v:5640$1263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5640$1263_Y - end - attribute \src "ls180.v:5641.107-5641.151" - cell $eq $eq$ls180.v:5641$1267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5641$1267_Y - end - attribute \src "ls180.v:5643.104-5643.148" - cell $eq $eq$ls180.v:5643$1270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5643$1270_Y - end - attribute \src "ls180.v:5644.107-5644.151" - cell $eq $eq$ls180.v:5644$1274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5644$1274_Y - end - attribute \src "ls180.v:5646.104-5646.148" - cell $eq $eq$ls180.v:5646$1277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5646$1277_Y - end - attribute \src "ls180.v:5647.107-5647.151" - cell $eq $eq$ls180.v:5647$1281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5647$1281_Y - end - attribute \src "ls180.v:5649.103-5649.147" - cell $eq $eq$ls180.v:5649$1284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5649$1284_Y - end - attribute \src "ls180.v:5650.106-5650.150" - cell $eq $eq$ls180.v:5650$1288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5650$1288_Y - end - attribute \src "ls180.v:5652.103-5652.147" - cell $eq $eq$ls180.v:5652$1291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5652$1291_Y - end - attribute \src "ls180.v:5653.106-5653.150" - cell $eq $eq$ls180.v:5653$1295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5653$1295_Y - end - attribute \src "ls180.v:5655.103-5655.147" - cell $eq $eq$ls180.v:5655$1298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5655$1298_Y - end - attribute \src "ls180.v:5656.106-5656.150" - cell $eq $eq$ls180.v:5656$1302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5656$1302_Y - end - attribute \src "ls180.v:5658.103-5658.147" - cell $eq $eq$ls180.v:5658$1305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5658$1305_Y - end - attribute \src "ls180.v:5659.106-5659.150" - cell $eq $eq$ls180.v:5659$1309 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5659$1309_Y - end - attribute \src "ls180.v:5661.101-5661.145" - cell $eq $eq$ls180.v:5661$1312 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5661$1312_Y - end - attribute \src "ls180.v:5662.104-5662.148" - cell $eq $eq$ls180.v:5662$1316 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5662$1316_Y - end - attribute \src "ls180.v:5664.105-5664.149" - cell $eq $eq$ls180.v:5664$1319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:5664$1319_Y - end - attribute \src "ls180.v:5665.108-5665.152" - cell $eq $eq$ls180.v:5665$1323 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:5665$1323_Y - end - attribute \src "ls180.v:5667.105-5667.150" - cell $eq $eq$ls180.v:5667$1326 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:5667$1326_Y - end - attribute \src "ls180.v:5668.108-5668.153" - cell $eq $eq$ls180.v:5668$1330 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:5668$1330_Y - end - attribute \src "ls180.v:5670.105-5670.150" - cell $eq $eq$ls180.v:5670$1333 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:5670$1333_Y - end - attribute \src "ls180.v:5671.108-5671.153" - cell $eq $eq$ls180.v:5671$1337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:5671$1337_Y - end - attribute \src "ls180.v:5673.105-5673.150" - cell $eq $eq$ls180.v:5673$1340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:5673$1340_Y - end - attribute \src "ls180.v:5674.108-5674.153" - cell $eq $eq$ls180.v:5674$1344 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:5674$1344_Y - end - attribute \src "ls180.v:5676.105-5676.150" - cell $eq $eq$ls180.v:5676$1347 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:5676$1347_Y - end - attribute \src "ls180.v:5677.108-5677.153" - cell $eq $eq$ls180.v:5677$1351 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:5677$1351_Y - end - attribute \src "ls180.v:5679.105-5679.150" - cell $eq $eq$ls180.v:5679$1354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:5679$1354_Y - end - attribute \src "ls180.v:5680.108-5680.153" - cell $eq $eq$ls180.v:5680$1358 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:5680$1358_Y - end - attribute \src "ls180.v:5682.104-5682.149" - cell $eq $eq$ls180.v:5682$1361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:5682$1361_Y - end - attribute \src "ls180.v:5683.107-5683.152" - cell $eq $eq$ls180.v:5683$1365 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:5683$1365_Y - end - attribute \src "ls180.v:5685.104-5685.149" - cell $eq $eq$ls180.v:5685$1368 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:5685$1368_Y - end - attribute \src "ls180.v:5686.107-5686.152" - cell $eq $eq$ls180.v:5686$1372 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:5686$1372_Y - end - attribute \src "ls180.v:5688.104-5688.149" - cell $eq $eq$ls180.v:5688$1375 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'10001 - connect \Y $eq$ls180.v:5688$1375_Y - end - attribute \src "ls180.v:5689.107-5689.152" - cell $eq $eq$ls180.v:5689$1379 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'10001 - connect \Y $eq$ls180.v:5689$1379_Y - end - attribute \src "ls180.v:5691.104-5691.149" - cell $eq $eq$ls180.v:5691$1382 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'10010 - connect \Y $eq$ls180.v:5691$1382_Y - end - attribute \src "ls180.v:5692.107-5692.152" - cell $eq $eq$ls180.v:5692$1386 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'10010 - connect \Y $eq$ls180.v:5692$1386_Y - end - attribute \src "ls180.v:5694.104-5694.149" - cell $eq $eq$ls180.v:5694$1389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'10011 - connect \Y $eq$ls180.v:5694$1389_Y - end - attribute \src "ls180.v:5695.107-5695.152" - cell $eq $eq$ls180.v:5695$1393 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'10011 - connect \Y $eq$ls180.v:5695$1393_Y - end - attribute \src "ls180.v:5697.104-5697.149" - cell $eq $eq$ls180.v:5697$1396 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'10100 - connect \Y $eq$ls180.v:5697$1396_Y - end - attribute \src "ls180.v:5698.107-5698.152" - cell $eq $eq$ls180.v:5698$1400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'10100 - connect \Y $eq$ls180.v:5698$1400_Y - end - attribute \src "ls180.v:5700.104-5700.149" - cell $eq $eq$ls180.v:5700$1403 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'10101 - connect \Y $eq$ls180.v:5700$1403_Y - end - attribute \src "ls180.v:5701.107-5701.152" - cell $eq $eq$ls180.v:5701$1407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'10101 - connect \Y $eq$ls180.v:5701$1407_Y - end - attribute \src "ls180.v:5703.104-5703.149" - cell $eq $eq$ls180.v:5703$1410 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'10110 - connect \Y $eq$ls180.v:5703$1410_Y - end - attribute \src "ls180.v:5704.107-5704.152" - cell $eq $eq$ls180.v:5704$1414 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'10110 - connect \Y $eq$ls180.v:5704$1414_Y - end - attribute \src "ls180.v:5706.104-5706.149" - cell $eq $eq$ls180.v:5706$1417 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'10111 - connect \Y $eq$ls180.v:5706$1417_Y - end - attribute \src "ls180.v:5707.107-5707.152" - cell $eq $eq$ls180.v:5707$1421 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'10111 - connect \Y $eq$ls180.v:5707$1421_Y - end - attribute \src "ls180.v:5709.104-5709.149" - cell $eq $eq$ls180.v:5709$1424 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'11000 - connect \Y $eq$ls180.v:5709$1424_Y - end - attribute \src "ls180.v:5710.107-5710.152" - cell $eq $eq$ls180.v:5710$1428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'11000 - connect \Y $eq$ls180.v:5710$1428_Y - end - attribute \src "ls180.v:5712.100-5712.145" - cell $eq $eq$ls180.v:5712$1431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'11001 - connect \Y $eq$ls180.v:5712$1431_Y - end - attribute \src "ls180.v:5713.103-5713.148" - cell $eq $eq$ls180.v:5713$1435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'11001 - connect \Y $eq$ls180.v:5713$1435_Y - end - attribute \src "ls180.v:5715.101-5715.146" - cell $eq $eq$ls180.v:5715$1438 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'11010 - connect \Y $eq$ls180.v:5715$1438_Y - end - attribute \src "ls180.v:5716.104-5716.149" - cell $eq $eq$ls180.v:5716$1442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'11010 - connect \Y $eq$ls180.v:5716$1442_Y - end - attribute \src "ls180.v:5718.104-5718.149" - cell $eq $eq$ls180.v:5718$1445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'11011 - connect \Y $eq$ls180.v:5718$1445_Y - end - attribute \src "ls180.v:5719.107-5719.152" - cell $eq $eq$ls180.v:5719$1449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'11011 - connect \Y $eq$ls180.v:5719$1449_Y - end - attribute \src "ls180.v:5721.104-5721.149" - cell $eq $eq$ls180.v:5721$1452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'11100 - connect \Y $eq$ls180.v:5721$1452_Y - end - attribute \src "ls180.v:5722.107-5722.152" - cell $eq $eq$ls180.v:5722$1456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'11100 - connect \Y $eq$ls180.v:5722$1456_Y - end - attribute \src "ls180.v:5724.103-5724.148" - cell $eq $eq$ls180.v:5724$1459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'11101 - connect \Y $eq$ls180.v:5724$1459_Y - end - attribute \src "ls180.v:5725.106-5725.151" - cell $eq $eq$ls180.v:5725$1463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'11101 - connect \Y $eq$ls180.v:5725$1463_Y - end - attribute \src "ls180.v:5727.103-5727.148" - cell $eq $eq$ls180.v:5727$1466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'11110 - connect \Y $eq$ls180.v:5727$1466_Y - end - attribute \src "ls180.v:5728.106-5728.151" - cell $eq $eq$ls180.v:5728$1470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'11110 - connect \Y $eq$ls180.v:5728$1470_Y - end - attribute \src "ls180.v:5730.103-5730.148" - cell $eq $eq$ls180.v:5730$1473 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'11111 - connect \Y $eq$ls180.v:5730$1473_Y - end - attribute \src "ls180.v:5731.106-5731.151" - cell $eq $eq$ls180.v:5731$1477 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 5'11111 - connect \Y $eq$ls180.v:5731$1477_Y - end - attribute \src "ls180.v:5733.103-5733.148" - cell $eq $eq$ls180.v:5733$1480 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 6'100000 - connect \Y $eq$ls180.v:5733$1480_Y - end - attribute \src "ls180.v:5734.106-5734.151" - cell $eq $eq$ls180.v:5734$1484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [5:0] - connect \B 6'100000 - connect \Y $eq$ls180.v:5734$1484_Y - end - attribute \src "ls180.v:5770.32-5770.78" - cell $eq $eq$ls180.v:5770$1486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [13:9] - connect \B 4'1100 - connect \Y $eq$ls180.v:5770$1486_Y - end - attribute \src "ls180.v:5772.100-5772.144" - cell $eq $eq$ls180.v:5772$1488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5772$1488_Y - end - attribute \src "ls180.v:5773.103-5773.147" - cell $eq $eq$ls180.v:5773$1492 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5773$1492_Y - end - attribute \src "ls180.v:5775.100-5775.144" - cell $eq $eq$ls180.v:5775$1495 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5775$1495_Y - end - attribute \src "ls180.v:5776.103-5776.147" - cell $eq $eq$ls180.v:5776$1499 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5776$1499_Y - end - attribute \src "ls180.v:5778.100-5778.144" - cell $eq $eq$ls180.v:5778$1502 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5778$1502_Y - end - attribute \src "ls180.v:5779.103-5779.147" - cell $eq $eq$ls180.v:5779$1506 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5779$1506_Y - end - attribute \src "ls180.v:5781.100-5781.144" - cell $eq $eq$ls180.v:5781$1509 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5781$1509_Y - end - attribute \src "ls180.v:5782.103-5782.147" - cell $eq $eq$ls180.v:5782$1513 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5782$1513_Y - end - attribute \src "ls180.v:5784.100-5784.144" - cell $eq $eq$ls180.v:5784$1516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5784$1516_Y - end - attribute \src "ls180.v:5785.103-5785.147" - cell $eq $eq$ls180.v:5785$1520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5785$1520_Y - end - attribute \src "ls180.v:5787.100-5787.144" - cell $eq $eq$ls180.v:5787$1523 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5787$1523_Y - end - attribute \src "ls180.v:5788.103-5788.147" - cell $eq $eq$ls180.v:5788$1527 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5788$1527_Y - end - attribute \src "ls180.v:5790.100-5790.144" - cell $eq $eq$ls180.v:5790$1530 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5790$1530_Y - end - attribute \src "ls180.v:5791.103-5791.147" - cell $eq $eq$ls180.v:5791$1534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5791$1534_Y - end - attribute \src "ls180.v:5793.100-5793.144" - cell $eq $eq$ls180.v:5793$1537 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5793$1537_Y - end - attribute \src "ls180.v:5794.103-5794.147" - cell $eq $eq$ls180.v:5794$1541 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5794$1541_Y - end - attribute \src "ls180.v:5796.102-5796.146" - cell $eq $eq$ls180.v:5796$1544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5796$1544_Y - end - attribute \src "ls180.v:5797.105-5797.149" - cell $eq $eq$ls180.v:5797$1548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5797$1548_Y - end - attribute \src "ls180.v:5799.102-5799.146" - cell $eq $eq$ls180.v:5799$1551 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:5799$1551_Y - end - attribute \src "ls180.v:5800.105-5800.149" - cell $eq $eq$ls180.v:5800$1555 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:5800$1555_Y - end - attribute \src "ls180.v:5802.102-5802.147" - cell $eq $eq$ls180.v:5802$1558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:5802$1558_Y - end - attribute \src "ls180.v:5803.105-5803.150" - cell $eq $eq$ls180.v:5803$1562 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:5803$1562_Y - end - attribute \src "ls180.v:5805.102-5805.147" - cell $eq $eq$ls180.v:5805$1565 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:5805$1565_Y - end - attribute \src "ls180.v:5806.105-5806.150" - cell $eq $eq$ls180.v:5806$1569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:5806$1569_Y - end - attribute \src "ls180.v:5808.102-5808.147" - cell $eq $eq$ls180.v:5808$1572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:5808$1572_Y - end - attribute \src "ls180.v:5809.105-5809.150" - cell $eq $eq$ls180.v:5809$1576 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:5809$1576_Y - end - attribute \src "ls180.v:5811.99-5811.144" - cell $eq $eq$ls180.v:5811$1579 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:5811$1579_Y - end - attribute \src "ls180.v:5812.102-5812.147" - cell $eq $eq$ls180.v:5812$1583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:5812$1583_Y - end - attribute \src "ls180.v:5814.100-5814.145" - cell $eq $eq$ls180.v:5814$1586 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:5814$1586_Y - end - attribute \src "ls180.v:5815.103-5815.148" - cell $eq $eq$ls180.v:5815$1590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:5815$1590_Y - end - attribute \src "ls180.v:5817.102-5817.147" - cell $eq $eq$ls180.v:5817$1593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:5817$1593_Y - end - attribute \src "ls180.v:5818.105-5818.150" - cell $eq $eq$ls180.v:5818$1597 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:5818$1597_Y - end - attribute \src "ls180.v:5820.102-5820.147" - cell $eq $eq$ls180.v:5820$1600 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:5820$1600_Y - end - attribute \src "ls180.v:5821.105-5821.150" - cell $eq $eq$ls180.v:5821$1604 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:5821$1604_Y - end - attribute \src "ls180.v:5823.102-5823.147" - cell $eq $eq$ls180.v:5823$1607 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 5'10001 - connect \Y $eq$ls180.v:5823$1607_Y - end - attribute \src "ls180.v:5824.105-5824.150" - cell $eq $eq$ls180.v:5824$1611 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 5'10001 - connect \Y $eq$ls180.v:5824$1611_Y - end - attribute \src "ls180.v:5826.102-5826.147" - cell $eq $eq$ls180.v:5826$1614 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 5'10010 - connect \Y $eq$ls180.v:5826$1614_Y - end - attribute \src "ls180.v:5827.105-5827.150" - cell $eq $eq$ls180.v:5827$1618 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [4:0] - connect \B 5'10010 - connect \Y $eq$ls180.v:5827$1618_Y - end - attribute \src "ls180.v:5849.32-5849.77" - cell $eq $eq$ls180.v:5849$1620 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [13:9] - connect \B 4'1001 - connect \Y $eq$ls180.v:5849$1620_Y - end - attribute \src "ls180.v:5851.102-5851.146" - cell $eq $eq$ls180.v:5851$1622 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [1:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5851$1622_Y - end - attribute \src "ls180.v:5852.105-5852.149" - cell $eq $eq$ls180.v:5852$1626 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [1:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5852$1626_Y - end - attribute \src "ls180.v:5854.107-5854.151" - cell $eq $eq$ls180.v:5854$1629 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [1:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5854$1629_Y - end - attribute \src "ls180.v:5855.110-5855.154" - cell $eq $eq$ls180.v:5855$1633 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [1:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5855$1633_Y - end - attribute \src "ls180.v:5857.107-5857.151" - cell $eq $eq$ls180.v:5857$1636 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [1:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5857$1636_Y - end - attribute \src "ls180.v:5858.110-5858.154" - cell $eq $eq$ls180.v:5858$1640 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [1:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5858$1640_Y - end - attribute \src "ls180.v:5860.101-5860.145" - cell $eq $eq$ls180.v:5860$1643 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [1:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5860$1643_Y - end - attribute \src "ls180.v:5861.104-5861.148" - cell $eq $eq$ls180.v:5861$1647 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [1:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5861$1647_Y - end - attribute \src "ls180.v:5866.32-5866.77" - cell $eq $eq$ls180.v:5866$1649 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [13:9] - connect \B 3'101 - connect \Y $eq$ls180.v:5866$1649_Y - end - attribute \src "ls180.v:5868.104-5868.148" - cell $eq $eq$ls180.v:5868$1651 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5868$1651_Y - end - attribute \src "ls180.v:5869.107-5869.151" - cell $eq $eq$ls180.v:5869$1655 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5869$1655_Y - end - attribute \src "ls180.v:5871.108-5871.152" - cell $eq $eq$ls180.v:5871$1658 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5871$1658_Y - end - attribute \src "ls180.v:5872.111-5872.155" - cell $eq $eq$ls180.v:5872$1662 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5872$1662_Y - end - attribute \src "ls180.v:5874.98-5874.142" - cell $eq $eq$ls180.v:5874$1665 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5874$1665_Y - end - attribute \src "ls180.v:5875.101-5875.145" - cell $eq $eq$ls180.v:5875$1669 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5875$1669_Y - end - attribute \src "ls180.v:5877.108-5877.152" - cell $eq $eq$ls180.v:5877$1672 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5877$1672_Y - end - attribute \src "ls180.v:5878.111-5878.155" - cell $eq $eq$ls180.v:5878$1676 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5878$1676_Y - end - attribute \src "ls180.v:5880.108-5880.152" - cell $eq $eq$ls180.v:5880$1679 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5880$1679_Y - end - attribute \src "ls180.v:5881.111-5881.155" - cell $eq $eq$ls180.v:5881$1683 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5881$1683_Y - end - attribute \src "ls180.v:5883.109-5883.153" - cell $eq $eq$ls180.v:5883$1686 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5883$1686_Y - end - attribute \src "ls180.v:5884.112-5884.156" - cell $eq $eq$ls180.v:5884$1690 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5884$1690_Y - end - attribute \src "ls180.v:5886.107-5886.151" - cell $eq $eq$ls180.v:5886$1693 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5886$1693_Y - end - attribute \src "ls180.v:5887.110-5887.154" - cell $eq $eq$ls180.v:5887$1697 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5887$1697_Y - end - attribute \src "ls180.v:5889.107-5889.151" - cell $eq $eq$ls180.v:5889$1700 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5889$1700_Y - end - attribute \src "ls180.v:5890.110-5890.154" - cell $eq $eq$ls180.v:5890$1704 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5890$1704_Y - end - attribute \src "ls180.v:5892.107-5892.151" - cell $eq $eq$ls180.v:5892$1707 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5892$1707_Y - end - attribute \src "ls180.v:5893.110-5893.154" - cell $eq $eq$ls180.v:5893$1711 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5893$1711_Y - end - attribute \src "ls180.v:5895.107-5895.151" - cell $eq $eq$ls180.v:5895$1714 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [3:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:5895$1714_Y - end - attribute \src "ls180.v:5896.110-5896.154" - cell $eq $eq$ls180.v:5896$1718 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [3:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:5896$1718_Y - end - attribute \src "ls180.v:5911.32-5911.77" - cell $eq $eq$ls180.v:5911$1720 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [13:9] - connect \B 4'1000 - connect \Y $eq$ls180.v:5911$1720_Y - end - attribute \src "ls180.v:5913.99-5913.143" - cell $eq $eq$ls180.v:5913$1722 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5913$1722_Y - end - attribute \src "ls180.v:5914.102-5914.146" - cell $eq $eq$ls180.v:5914$1726 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5914$1726_Y - end - attribute \src "ls180.v:5916.99-5916.143" - cell $eq $eq$ls180.v:5916$1729 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5916$1729_Y - end - attribute \src "ls180.v:5917.102-5917.146" - cell $eq $eq$ls180.v:5917$1733 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5917$1733_Y - end - attribute \src "ls180.v:5919.97-5919.141" - cell $eq $eq$ls180.v:5919$1736 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5919$1736_Y - end - attribute \src "ls180.v:5920.100-5920.144" - cell $eq $eq$ls180.v:5920$1740 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5920$1740_Y - end - attribute \src "ls180.v:5922.96-5922.140" - cell $eq $eq$ls180.v:5922$1743 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5922$1743_Y - end - attribute \src "ls180.v:5923.99-5923.143" - cell $eq $eq$ls180.v:5923$1747 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5923$1747_Y - end - attribute \src "ls180.v:5925.95-5925.139" - cell $eq $eq$ls180.v:5925$1750 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5925$1750_Y - end - attribute \src "ls180.v:5926.98-5926.142" - cell $eq $eq$ls180.v:5926$1754 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5926$1754_Y - end - attribute \src "ls180.v:5928.94-5928.138" - cell $eq $eq$ls180.v:5928$1757 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5928$1757_Y - end - attribute \src "ls180.v:5929.97-5929.141" - cell $eq $eq$ls180.v:5929$1761 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5929$1761_Y - end - attribute \src "ls180.v:5931.100-5931.144" - cell $eq $eq$ls180.v:5931$1764 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [2:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5931$1764_Y - end - attribute \src "ls180.v:5932.103-5932.147" - cell $eq $eq$ls180.v:5932$1768 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [2:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5932$1768_Y - end - attribute \src "ls180.v:5951.32-5951.78" - cell $eq $eq$ls180.v:5951$1771 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [13:9] - connect \B 4'1101 - connect \Y $eq$ls180.v:5951$1771_Y - end - attribute \src "ls180.v:5953.99-5953.143" - cell $eq $eq$ls180.v:5953$1773 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5953$1773_Y - end - attribute \src "ls180.v:5954.102-5954.146" - cell $eq $eq$ls180.v:5954$1777 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5954$1777_Y - end - attribute \src "ls180.v:5956.99-5956.143" - cell $eq $eq$ls180.v:5956$1780 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5956$1780_Y - end - attribute \src "ls180.v:5957.102-5957.146" - cell $eq $eq$ls180.v:5957$1784 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5957$1784_Y - end - attribute \src "ls180.v:5959.97-5959.141" - cell $eq $eq$ls180.v:5959$1787 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5959$1787_Y - end - attribute \src "ls180.v:5960.100-5960.144" - cell $eq $eq$ls180.v:5960$1791 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5960$1791_Y - end - attribute \src "ls180.v:5962.96-5962.140" - cell $eq $eq$ls180.v:5962$1794 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5962$1794_Y - end - attribute \src "ls180.v:5963.99-5963.143" - cell $eq $eq$ls180.v:5963$1798 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5963$1798_Y - end - attribute \src "ls180.v:5965.95-5965.139" - cell $eq $eq$ls180.v:5965$1801 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5965$1801_Y - end - attribute \src "ls180.v:5966.98-5966.142" - cell $eq $eq$ls180.v:5966$1805 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5966$1805_Y - end - attribute \src "ls180.v:5968.94-5968.138" - cell $eq $eq$ls180.v:5968$1808 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5968$1808_Y - end - attribute \src "ls180.v:5969.97-5969.141" - cell $eq $eq$ls180.v:5969$1812 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5969$1812_Y - end - attribute \src "ls180.v:5971.100-5971.144" - cell $eq $eq$ls180.v:5971$1815 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5971$1815_Y - end - attribute \src "ls180.v:5972.103-5972.147" - cell $eq $eq$ls180.v:5972$1819 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5972$1819_Y - end - attribute \src "ls180.v:5974.103-5974.147" - cell $eq $eq$ls180.v:5974$1822 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5974$1822_Y - end - attribute \src "ls180.v:5975.106-5975.150" - cell $eq $eq$ls180.v:5975$1826 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5975$1826_Y - end - attribute \src "ls180.v:5977.103-5977.147" - cell $eq $eq$ls180.v:5977$1829 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5977$1829_Y - end - attribute \src "ls180.v:5978.106-5978.150" - cell $eq $eq$ls180.v:5978$1833 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5978$1833_Y - end - attribute \src "ls180.v:5999.33-5999.79" - cell $eq $eq$ls180.v:5999$1836 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [13:9] - connect \B 3'100 - connect \Y $eq$ls180.v:5999$1836_Y - end - attribute \src "ls180.v:6001.99-6001.144" - cell $eq $eq$ls180.v:6001$1838 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6001$1838_Y - end - attribute \src "ls180.v:6002.102-6002.147" - cell $eq $eq$ls180.v:6002$1842 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6002$1842_Y - end - attribute \src "ls180.v:6004.99-6004.144" - cell $eq $eq$ls180.v:6004$1845 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6004$1845_Y - end - attribute \src "ls180.v:6005.102-6005.147" - cell $eq $eq$ls180.v:6005$1849 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6005$1849_Y - end - attribute \src "ls180.v:6007.99-6007.144" - cell $eq $eq$ls180.v:6007$1852 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6007$1852_Y - end - attribute \src "ls180.v:6008.102-6008.147" - cell $eq $eq$ls180.v:6008$1856 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6008$1856_Y - end - attribute \src "ls180.v:6010.99-6010.144" - cell $eq $eq$ls180.v:6010$1859 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6010$1859_Y - end - attribute \src "ls180.v:6011.102-6011.147" - cell $eq $eq$ls180.v:6011$1863 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6011$1863_Y - end - attribute \src "ls180.v:6013.101-6013.146" - cell $eq $eq$ls180.v:6013$1866 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6013$1866_Y - end - attribute \src "ls180.v:6014.104-6014.149" - cell $eq $eq$ls180.v:6014$1870 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6014$1870_Y - end - attribute \src "ls180.v:6016.101-6016.146" - cell $eq $eq$ls180.v:6016$1873 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6016$1873_Y - end - attribute \src "ls180.v:6017.104-6017.149" - cell $eq $eq$ls180.v:6017$1877 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6017$1877_Y - end - attribute \src "ls180.v:6019.101-6019.146" - cell $eq $eq$ls180.v:6019$1880 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6019$1880_Y - end - attribute \src "ls180.v:6020.104-6020.149" - cell $eq $eq$ls180.v:6020$1884 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6020$1884_Y - end - attribute \src "ls180.v:6022.101-6022.146" - cell $eq $eq$ls180.v:6022$1887 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6022$1887_Y - end - attribute \src "ls180.v:6023.104-6023.149" - cell $eq $eq$ls180.v:6023$1891 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6023$1891_Y - end - attribute \src "ls180.v:6025.97-6025.142" - cell $eq $eq$ls180.v:6025$1894 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6025$1894_Y - end - attribute \src "ls180.v:6026.100-6026.145" - cell $eq $eq$ls180.v:6026$1898 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6026$1898_Y - end - attribute \src "ls180.v:6028.107-6028.152" - cell $eq $eq$ls180.v:6028$1901 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6028$1901_Y - end - attribute \src "ls180.v:6029.110-6029.155" - cell $eq $eq$ls180.v:6029$1905 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6029$1905_Y - end - attribute \src "ls180.v:6031.100-6031.146" - cell $eq $eq$ls180.v:6031$1908 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6031$1908_Y - end - attribute \src "ls180.v:6032.103-6032.149" - cell $eq $eq$ls180.v:6032$1912 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6032$1912_Y - end - attribute \src "ls180.v:6034.100-6034.146" - cell $eq $eq$ls180.v:6034$1915 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6034$1915_Y - end - attribute \src "ls180.v:6035.103-6035.149" - cell $eq $eq$ls180.v:6035$1919 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6035$1919_Y - end - attribute \src "ls180.v:6037.100-6037.146" - cell $eq $eq$ls180.v:6037$1922 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6037$1922_Y - end - attribute \src "ls180.v:6038.103-6038.149" - cell $eq $eq$ls180.v:6038$1926 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6038$1926_Y - end - attribute \src "ls180.v:6040.100-6040.146" - cell $eq $eq$ls180.v:6040$1929 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6040$1929_Y - end - attribute \src "ls180.v:6041.103-6041.149" - cell $eq $eq$ls180.v:6041$1933 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6041$1933_Y - end - attribute \src "ls180.v:6043.118-6043.164" - cell $eq $eq$ls180.v:6043$1936 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6043$1936_Y - end - attribute \src "ls180.v:6044.121-6044.167" - cell $eq $eq$ls180.v:6044$1940 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6044$1940_Y - end - attribute \src "ls180.v:6046.119-6046.165" - cell $eq $eq$ls180.v:6046$1943 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6046$1943_Y - end - attribute \src "ls180.v:6047.122-6047.168" - cell $eq $eq$ls180.v:6047$1947 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6047$1947_Y - end - attribute \src "ls180.v:6049.104-6049.150" - cell $eq $eq$ls180.v:6049$1950 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6049$1950_Y - end - attribute \src "ls180.v:6050.107-6050.153" - cell $eq $eq$ls180.v:6050$1954 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [4:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6050$1954_Y - end - attribute \src "ls180.v:6067.33-6067.79" - cell $eq $eq$ls180.v:6067$1956 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [13:9] - connect \B 2'11 - connect \Y $eq$ls180.v:6067$1956_Y - end - attribute \src "ls180.v:6069.102-6069.147" - cell $eq $eq$ls180.v:6069$1958 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6069$1958_Y - end - attribute \src "ls180.v:6070.105-6070.150" - cell $eq $eq$ls180.v:6070$1962 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6070$1962_Y - end - attribute \src "ls180.v:6072.100-6072.145" - cell $eq $eq$ls180.v:6072$1965 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6072$1965_Y - end - attribute \src "ls180.v:6073.103-6073.148" - cell $eq $eq$ls180.v:6073$1969 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6073$1969_Y - end - attribute \src "ls180.v:6075.101-6075.146" - cell $eq $eq$ls180.v:6075$1972 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6075$1972_Y - end - attribute \src "ls180.v:6076.104-6076.149" - cell $eq $eq$ls180.v:6076$1976 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6076$1976_Y - end - attribute \src "ls180.v:6078.117-6078.162" - cell $eq $eq$ls180.v:6078$1979 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6078$1979_Y - end - attribute \src "ls180.v:6079.120-6079.165" - cell $eq $eq$ls180.v:6079$1983 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6079$1983_Y - end - attribute \src "ls180.v:6081.118-6081.163" - cell $eq $eq$ls180.v:6081$1986 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6081$1986_Y - end - attribute \src "ls180.v:6082.121-6082.166" - cell $eq $eq$ls180.v:6082$1990 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6082$1990_Y - end - attribute \src "ls180.v:6084.104-6084.149" - cell $eq $eq$ls180.v:6084$1993 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6084$1993_Y - end - attribute \src "ls180.v:6085.107-6085.152" - cell $eq $eq$ls180.v:6085$1997 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6085$1997_Y - end - attribute \src "ls180.v:6087.101-6087.146" - cell $eq $eq$ls180.v:6087$2000 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [2:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6087$2000_Y - end - attribute \src "ls180.v:6088.104-6088.149" - cell $eq $eq$ls180.v:6088$2004 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [2:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6088$2004_Y - end - attribute \src "ls180.v:6090.100-6090.145" - cell $eq $eq$ls180.v:6090$2007 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [2:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6090$2007_Y - end - attribute \src "ls180.v:6091.103-6091.148" - cell $eq $eq$ls180.v:6091$2011 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [2:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6091$2011_Y - end - attribute \src "ls180.v:6101.33-6101.79" - cell $eq $eq$ls180.v:6101$2013 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [13:9] - connect \B 2'10 - connect \Y $eq$ls180.v:6101$2013_Y - end - attribute \src "ls180.v:6103.106-6103.151" - cell $eq $eq$ls180.v:6103$2015 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [1:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6103$2015_Y - end - attribute \src "ls180.v:6104.109-6104.154" - cell $eq $eq$ls180.v:6104$2019 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [1:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6104$2019_Y - end - attribute \src "ls180.v:6106.106-6106.151" - cell $eq $eq$ls180.v:6106$2022 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [1:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6106$2022_Y - end - attribute \src "ls180.v:6107.109-6107.154" - cell $eq $eq$ls180.v:6107$2026 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [1:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6107$2026_Y - end - attribute \src "ls180.v:6109.106-6109.151" - cell $eq $eq$ls180.v:6109$2029 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [1:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6109$2029_Y - end - attribute \src "ls180.v:6110.109-6110.154" - cell $eq $eq$ls180.v:6110$2033 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [1:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6110$2033_Y - end - attribute \src "ls180.v:6112.106-6112.151" - cell $eq $eq$ls180.v:6112$2036 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [1:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6112$2036_Y - end - attribute \src "ls180.v:6113.109-6113.154" - cell $eq $eq$ls180.v:6113$2040 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [1:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6113$2040_Y - end - attribute \src "ls180.v:6488.41-6488.81" - cell $eq $eq$ls180.v:6488$2075 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'0 - connect \Y $eq$ls180.v:6488$2075_Y - end - attribute \src "ls180.v:6488.144-6488.177" - cell $eq $eq$ls180.v:6488$2076 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6488$2076_Y - end - attribute \src "ls180.v:6488.219-6488.252" - cell $eq $eq$ls180.v:6488$2079 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6488$2079_Y - end - attribute \src "ls180.v:6488.294-6488.327" - cell $eq $eq$ls180.v:6488$2082 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6488$2082_Y - end - attribute \src "ls180.v:6512.41-6512.81" - cell $eq $eq$ls180.v:6512$2091 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'1 - connect \Y $eq$ls180.v:6512$2091_Y - end - attribute \src "ls180.v:6512.144-6512.177" - cell $eq $eq$ls180.v:6512$2092 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6512$2092_Y - end - attribute \src "ls180.v:6512.219-6512.252" - cell $eq $eq$ls180.v:6512$2095 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6512$2095_Y - end - attribute \src "ls180.v:6512.294-6512.327" - cell $eq $eq$ls180.v:6512$2098 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6512$2098_Y - end - attribute \src "ls180.v:6536.41-6536.81" - cell $eq $eq$ls180.v:6536$2107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'10 - connect \Y $eq$ls180.v:6536$2107_Y - end - attribute \src "ls180.v:6536.144-6536.177" - cell $eq $eq$ls180.v:6536$2108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6536$2108_Y - end - attribute \src "ls180.v:6536.219-6536.252" - cell $eq $eq$ls180.v:6536$2111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6536$2111_Y - end - attribute \src "ls180.v:6536.294-6536.327" - cell $eq $eq$ls180.v:6536$2114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6536$2114_Y - end - attribute \src "ls180.v:6560.41-6560.81" - cell $eq $eq$ls180.v:6560$2123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'11 - connect \Y $eq$ls180.v:6560$2123_Y - end - attribute \src "ls180.v:6560.144-6560.177" - cell $eq $eq$ls180.v:6560$2124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6560$2124_Y - end - attribute \src "ls180.v:6560.219-6560.252" - cell $eq $eq$ls180.v:6560$2127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6560$2127_Y - end - attribute \src "ls180.v:6560.294-6560.327" - cell $eq $eq$ls180.v:6560$2130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6560$2130_Y - end - attribute \src "ls180.v:7097.9-7097.45" - cell $eq $eq$ls180.v:7097$2201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_tx_bitcount - connect \B 4'1000 - connect \Y $eq$ls180.v:7097$2201_Y - end - attribute \src "ls180.v:7100.10-7100.46" - cell $eq $eq$ls180.v:7100$2202 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_tx_bitcount - connect \B 4'1001 - connect \Y $eq$ls180.v:7100$2202_Y - end - attribute \src "ls180.v:7126.9-7126.45" - cell $eq $eq$ls180.v:7126$2208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_rx_bitcount - connect \B 1'0 - connect \Y $eq$ls180.v:7126$2208_Y - end - attribute \src "ls180.v:7131.10-7131.46" - cell $eq $eq$ls180.v:7131$2209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_rx_bitcount - connect \B 4'1001 - connect \Y $eq$ls180.v:7131$2209_Y - end - attribute \src "ls180.v:7221.8-7221.44" - cell $eq $eq$ls180.v:7221$2237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_timer_value - connect \B 1'0 - connect \Y $eq$ls180.v:7221$2237_Y - end - attribute \src "ls180.v:7252.8-7252.42" - cell $eq $eq$ls180.v:7252$2245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_postponer_count - connect \B 1'0 - connect \Y $eq$ls180.v:7252$2245_Y - end - attribute \src "ls180.v:7272.38-7272.74" - cell $eq $eq$ls180.v:7272$2248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 1'0 - connect \Y $eq$ls180.v:7272$2248_Y - end - attribute \src "ls180.v:7279.7-7279.43" - cell $eq $eq$ls180.v:7279$2250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 2'10 - connect \Y $eq$ls180.v:7279$2250_Y - end - attribute \src "ls180.v:7286.7-7286.43" - cell $eq $eq$ls180.v:7286$2251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 4'1000 - connect \Y $eq$ls180.v:7286$2251_Y - end - attribute \src "ls180.v:7294.7-7294.43" - cell $eq $eq$ls180.v:7294$2252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 4'1000 - connect \Y $eq$ls180.v:7294$2252_Y - end - attribute \src "ls180.v:7346.9-7346.54" - cell $eq $eq$ls180.v:7346$2270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7346$2270_Y - end - attribute \src "ls180.v:7392.9-7392.54" - cell $eq $eq$ls180.v:7392$2286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7392$2286_Y - end - attribute \src "ls180.v:7438.9-7438.54" - cell $eq $eq$ls180.v:7438$2302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7438$2302_Y - end - attribute \src "ls180.v:7484.9-7484.54" - cell $eq $eq$ls180.v:7484$2318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7484$2318_Y - end - attribute \src "ls180.v:7634.9-7634.41" - cell $eq $eq$ls180.v:7634$2330 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_tccdcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7634$2330_Y - end - attribute \src "ls180.v:7649.9-7649.41" - cell $eq $eq$ls180.v:7649$2333 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_twtrcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7649$2333_Y - end - attribute \src "ls180.v:7655.49-7655.82" - cell $eq $eq$ls180.v:7655$2334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7655$2334_Y - end - attribute \src "ls180.v:7655.131-7655.164" - cell $eq $eq$ls180.v:7655$2337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7655$2337_Y - end - attribute \src "ls180.v:7655.213-7655.246" - cell $eq $eq$ls180.v:7655$2340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7655$2340_Y - end - attribute \src "ls180.v:7655.295-7655.328" - cell $eq $eq$ls180.v:7655$2343 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7655$2343_Y - end - attribute \src "ls180.v:7656.50-7656.83" - cell $eq $eq$ls180.v:7656$2346 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7656$2346_Y - end - attribute \src "ls180.v:7656.132-7656.165" - cell $eq $eq$ls180.v:7656$2349 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7656$2349_Y - end - attribute \src "ls180.v:7656.214-7656.247" - cell $eq $eq$ls180.v:7656$2352 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7656$2352_Y - end - attribute \src "ls180.v:7656.296-7656.329" - cell $eq $eq$ls180.v:7656$2355 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7656$2355_Y - end - attribute \src "ls180.v:7737.9-7737.54" - cell $eq $eq$ls180.v:7737$2369 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdr_cmdr_converter_demux - connect \B 3'111 - connect \Y $eq$ls180.v:7737$2369_Y - end - attribute \src "ls180.v:7818.9-7818.55" - cell $eq $eq$ls180.v:7818$2381 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \libresocsim_dataw_crcr_converter_demux - connect \B 3'111 - connect \Y $eq$ls180.v:7818$2381_Y - end - attribute \src "ls180.v:7897.9-7897.56" - cell $eq $eq$ls180.v:7897$2393 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_datar_datar_converter_demux - connect \B 1'1 - connect \Y $eq$ls180.v:7897$2393_Y - end - attribute \src "ls180.v:8120.9-8120.56" - cell $eq $eq$ls180.v:8120$2426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdblock2mem_converter_demux - connect \B 2'11 - connect \Y $eq$ls180.v:8120$2426_Y - end - attribute \src "ls180.v:4849.54-4849.97" - cell $gt $gt$ls180.v:4849$896 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $gt$ls180.v:4849$896_Y - end - attribute \src "ls180.v:4855.7-4855.50" - cell $lt $lt$ls180.v:4855$899 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_cnt - connect \B 4'1000 - connect \Y $lt$ls180.v:4855$899_Y - end - attribute \src "ls180.v:9380.33-9380.36" - cell $memrd $memrd$\mem$ls180.v:9380$2472 - parameter \ABITS 7 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \TRANSPARENT 0 - parameter \WIDTH 32 - connect \ADDR \memadr - connect \CLK 1'x - connect \DATA $memrd$\mem$ls180.v:9380$2472_DATA - connect \EN 1'x - end - attribute \src "ls180.v:9392.12-9392.19" - cell $memrd $memrd$\storage$ls180.v:9392$2477 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_libresocsim_uart_tx_fifo_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:9392$2477_DATA - connect \EN 1'x - end - attribute \src "ls180.v:9397.15-9397.22" - cell $memrd $memrd$\storage$ls180.v:9397$2479 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_libresocsim_uart_tx_fifo_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:9397$2479_DATA - connect \EN 1'x - end - attribute \src "ls180.v:9409.14-9409.23" - cell $memrd $memrd$\storage_1$ls180.v:9409$2484 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_1" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_libresocsim_uart_rx_fifo_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:9409$2484_DATA - connect \EN 1'x - end - attribute \src "ls180.v:9414.15-9414.24" - cell $memrd $memrd$\storage_1$ls180.v:9414$2486 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_1" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_libresocsim_uart_rx_fifo_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:9414$2486_DATA - connect \EN 1'x - end - attribute \src "ls180.v:9425.14-9425.23" - cell $memrd $memrd$\storage_2$ls180.v:9425$2491 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_2" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:9425$2491_DATA - connect \EN 1'x - end - attribute \src "ls180.v:9432.68-9432.77" - cell $memrd $memrd$\storage_2$ls180.v:9432$2493 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_2" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:9432$2493_DATA - connect \EN 1'x - end - attribute \src "ls180.v:9439.14-9439.23" - cell $memrd $memrd$\storage_3$ls180.v:9439$2498 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_3" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:9439$2498_DATA - connect \EN 1'x - end - attribute \src "ls180.v:9446.68-9446.77" - cell $memrd $memrd$\storage_3$ls180.v:9446$2500 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_3" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:9446$2500_DATA - connect \EN 1'x - end - attribute \src "ls180.v:9453.14-9453.23" - cell $memrd $memrd$\storage_4$ls180.v:9453$2505 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_4" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:9453$2505_DATA - connect \EN 1'x - end - attribute \src "ls180.v:9460.68-9460.77" - cell $memrd $memrd$\storage_4$ls180.v:9460$2507 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_4" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:9460$2507_DATA - connect \EN 1'x - end - attribute \src "ls180.v:9467.14-9467.23" - cell $memrd $memrd$\storage_5$ls180.v:9467$2512 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_5" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:9467$2512_DATA - connect \EN 1'x - end - attribute \src "ls180.v:9474.68-9474.77" - cell $memrd $memrd$\storage_5$ls180.v:9474$2514 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_5" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:9474$2514_DATA - connect \EN 1'x - end - attribute \src "ls180.v:9481.14-9481.23" - cell $memrd $memrd$\storage_6$ls180.v:9481$2519 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_6" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \libresocsim_sdblock2mem_fifo_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:9481$2519_DATA - connect \EN 1'x - end - attribute \src "ls180.v:9488.52-9488.61" - cell $memrd $memrd$\storage_6$ls180.v:9488$2521 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_6" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \libresocsim_sdblock2mem_fifo_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:9488$2521_DATA - connect \EN 1'x - end - attribute \src "ls180.v:9495.14-9495.23" - cell $memrd $memrd$\storage_7$ls180.v:9495$2526 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_7" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \libresocsim_sdmem2block_fifo_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:9495$2526_DATA - connect \EN 1'x - end - attribute \src "ls180.v:9502.52-9502.61" - cell $memrd $memrd$\storage_7$ls180.v:9502$2528 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_7" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \libresocsim_sdmem2block_fifo_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:9502$2528_DATA - connect \EN 1'x - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2551 - parameter \ABITS 7 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 2551 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:9370$1_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:9370$1_DATA - connect \EN $memwr$\mem$ls180.v:9370$1_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2552 - parameter \ABITS 7 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 2552 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:9372$2_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:9372$2_DATA - connect \EN $memwr$\mem$ls180.v:9372$2_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2553 - parameter \ABITS 7 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 2553 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:9374$3_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:9374$3_DATA - connect \EN $memwr$\mem$ls180.v:9374$3_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2554 - parameter \ABITS 7 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 2554 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:9376$4_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:9376$4_DATA - connect \EN $memwr$\mem$ls180.v:9376$4_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage$ls180.v:0$2555 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage" - parameter \PRIORITY 2555 - parameter \WIDTH 10 - connect \ADDR $memwr$\storage$ls180.v:9391$5_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage$ls180.v:9391$5_DATA - connect \EN $memwr$\storage$ls180.v:9391$5_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_1$ls180.v:0$2556 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_1" - parameter \PRIORITY 2556 - parameter \WIDTH 10 - connect \ADDR $memwr$\storage_1$ls180.v:9408$6_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_1$ls180.v:9408$6_DATA - connect \EN $memwr$\storage_1$ls180.v:9408$6_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_2$ls180.v:0$2557 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_2" - parameter \PRIORITY 2557 - parameter \WIDTH 25 - connect \ADDR $memwr$\storage_2$ls180.v:9424$7_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_2$ls180.v:9424$7_DATA - connect \EN $memwr$\storage_2$ls180.v:9424$7_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_3$ls180.v:0$2558 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_3" - parameter \PRIORITY 2558 - parameter \WIDTH 25 - connect \ADDR $memwr$\storage_3$ls180.v:9438$8_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_3$ls180.v:9438$8_DATA - connect \EN $memwr$\storage_3$ls180.v:9438$8_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_4$ls180.v:0$2559 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_4" - parameter \PRIORITY 2559 - parameter \WIDTH 25 - connect \ADDR $memwr$\storage_4$ls180.v:9452$9_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_4$ls180.v:9452$9_DATA - connect \EN $memwr$\storage_4$ls180.v:9452$9_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_5$ls180.v:0$2560 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_5" - parameter \PRIORITY 2560 - parameter \WIDTH 25 - connect \ADDR $memwr$\storage_5$ls180.v:9466$10_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_5$ls180.v:9466$10_DATA - connect \EN $memwr$\storage_5$ls180.v:9466$10_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_6$ls180.v:0$2561 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_6" - parameter \PRIORITY 2561 - parameter \WIDTH 10 - connect \ADDR $memwr$\storage_6$ls180.v:9480$11_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_6$ls180.v:9480$11_DATA - connect \EN $memwr$\storage_6$ls180.v:9480$11_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_7$ls180.v:0$2562 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_7" - parameter \PRIORITY 2562 - parameter \WIDTH 10 - connect \ADDR $memwr$\storage_7$ls180.v:9494$12_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_7$ls180.v:9494$12_DATA - connect \EN $memwr$\storage_7$ls180.v:9494$12_EN - end - attribute \src "ls180.v:2809.59-2809.104" - cell $ne $ne$ls180.v:2809$75 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_tx_fifo_level0 - connect \B 5'10000 - connect \Y $ne$ls180.v:2809$75_Y - end - attribute \src "ls180.v:2810.59-2810.103" - cell $ne $ne$ls180.v:2810$76 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_tx_fifo_level0 - connect \B 1'0 - connect \Y $ne$ls180.v:2810$76_Y - end - attribute \src "ls180.v:2839.59-2839.104" - cell $ne $ne$ls180.v:2839$86 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_rx_fifo_level0 - connect \B 5'10000 - connect \Y $ne$ls180.v:2839$86_Y - end - attribute \src "ls180.v:2840.59-2840.103" - cell $ne $ne$ls180.v:2840$87 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_rx_fifo_level0 - connect \B 1'0 - connect \Y $ne$ls180.v:2840$87_Y - end - attribute \src "ls180.v:2841.47-2841.83" - cell $ne $ne$ls180.v:2841$88 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_timer_value - connect \B 1'0 - connect \Y $ne$ls180.v:2841$88_Y - end - attribute \src "ls180.v:3007.70-3007.104" - cell $ne $ne$ls180.v:3007$103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_count - connect \B 1'0 - connect \Y $ne$ls180.v:3007$103_Y - end - attribute \src "ls180.v:3068.8-3068.142" - cell $ne $ne$ls180.v:3068$122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] - connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3068$122_Y - end - attribute \src "ls180.v:3100.75-3100.133" - cell $ne $ne$ls180.v:3100$129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level - connect \B 4'1000 - connect \Y $ne$ls180.v:3100$129_Y - end - attribute \src "ls180.v:3101.75-3101.133" - cell $ne $ne$ls180.v:3101$130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level - connect \B 1'0 - connect \Y $ne$ls180.v:3101$130_Y - end - attribute \src "ls180.v:3225.8-3225.142" - cell $ne $ne$ls180.v:3225$152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] - connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3225$152_Y - end - attribute \src "ls180.v:3257.75-3257.133" - cell $ne $ne$ls180.v:3257$159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level - connect \B 4'1000 - connect \Y $ne$ls180.v:3257$159_Y - end - attribute \src "ls180.v:3258.75-3258.133" - cell $ne $ne$ls180.v:3258$160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level - connect \B 1'0 - connect \Y $ne$ls180.v:3258$160_Y - end - attribute \src "ls180.v:3382.8-3382.142" - cell $ne $ne$ls180.v:3382$182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] - connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3382$182_Y - end - attribute \src "ls180.v:3414.75-3414.133" - cell $ne $ne$ls180.v:3414$189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level - connect \B 4'1000 - connect \Y $ne$ls180.v:3414$189_Y - end - attribute \src "ls180.v:3415.75-3415.133" - cell $ne $ne$ls180.v:3415$190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level - connect \B 1'0 - connect \Y $ne$ls180.v:3415$190_Y - end - attribute \src "ls180.v:3539.8-3539.142" - cell $ne $ne$ls180.v:3539$212 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] - connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3539$212_Y - end - attribute \src "ls180.v:3571.75-3571.133" - cell $ne $ne$ls180.v:3571$219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level - connect \B 4'1000 - connect \Y $ne$ls180.v:3571$219_Y - end - attribute \src "ls180.v:3572.75-3572.133" - cell $ne $ne$ls180.v:3572$220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level - connect \B 1'0 - connect \Y $ne$ls180.v:3572$220_Y - end - attribute \src "ls180.v:4381.33-4381.91" - cell $ne $ne$ls180.v:4381$663 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \libresocsim_dataw_crcr_source_source_payload_data0 - connect \B 3'101 - connect \Y $ne$ls180.v:4381$663_Y - end - attribute \src "ls180.v:5028.10-5028.57" - cell $ne $ne$ls180.v:5028$960 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \libresocsim_datar_source_payload_status - connect \B 2'10 - connect \Y $ne$ls180.v:5028$960_Y - end - attribute \src "ls180.v:5133.58-5133.101" - cell $ne $ne$ls180.v:5133$974 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdblock2mem_fifo_level - connect \B 6'100000 - connect \Y $ne$ls180.v:5133$974_Y - end - attribute \src "ls180.v:5134.58-5134.100" - cell $ne $ne$ls180.v:5134$975 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdblock2mem_fifo_level - connect \B 1'0 - connect \Y $ne$ls180.v:5134$975_Y - end - attribute \src "ls180.v:5341.58-5341.101" - cell $ne $ne$ls180.v:5341$1005 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdmem2block_fifo_level - connect \B 6'100000 - connect \Y $ne$ls180.v:5341$1005_Y - end - attribute \src "ls180.v:5342.58-5342.100" - cell $ne $ne$ls180.v:5342$1006 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdmem2block_fifo_level - connect \B 1'0 - connect \Y $ne$ls180.v:5342$1006_Y - end - attribute \src "ls180.v:5432.79-5432.119" - cell $ne $ne$ls180.v:5432$1017 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_libresocsim_wishbone_sel - connect \B 1'0 - connect \Y $ne$ls180.v:5432$1017_Y - end - attribute \src "ls180.v:7079.7-7079.66" - cell $ne $ne$ls180.v:7079$2190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_soccontroller_bus_errors - connect \B 32'11111111111111111111111111111111 - connect \Y $ne$ls180.v:7079$2190_Y - end - attribute \src "ls180.v:7261.9-7261.43" - cell $ne $ne$ls180.v:7261$2246 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_count - connect \B 1'0 - connect \Y $ne$ls180.v:7261$2246_Y - end - attribute \src "ls180.v:7297.8-7297.44" - cell $ne $ne$ls180.v:7297$2253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 1'0 - connect \Y $ne$ls180.v:7297$2253_Y - end - attribute \src "ls180.v:8040.9-8040.54" - cell $ne $ne$ls180.v:8040$2413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_cnt - connect \B 4'1010 - connect \Y $ne$ls180.v:8040$2413_Y - end - attribute \src "ls180.v:2594.45-2594.80" - cell $not $not$ls180.v:2594$14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_ibus_cyc - connect \Y $not$ls180.v:2594$14_Y - end - attribute \src "ls180.v:2633.61-2633.94" - cell $not $not$ls180.v:2633$19 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter0_skip - connect \Y $not$ls180.v:2633$19_Y - end - attribute \src "ls180.v:2634.61-2634.94" - cell $not $not$ls180.v:2634$20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter0_skip - connect \Y $not$ls180.v:2634$20_Y - end - attribute \src "ls180.v:2654.45-2654.80" - cell $not $not$ls180.v:2654$25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_dbus_cyc - connect \Y $not$ls180.v:2654$25_Y - end - attribute \src "ls180.v:2693.61-2693.94" - cell $not $not$ls180.v:2693$30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter1_skip - connect \Y $not$ls180.v:2693$30_Y - end - attribute \src "ls180.v:2694.61-2694.94" - cell $not $not$ls180.v:2694$31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter1_skip - connect \Y $not$ls180.v:2694$31_Y - end - attribute \src "ls180.v:2738.47-2738.88" - cell $not $not$ls180.v:2738$49 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:2738$49_Y - end - attribute \src "ls180.v:2739.48-2739.91" - cell $not $not$ls180.v:2739$50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_tx_fifo_source_valid - connect \Y $not$ls180.v:2739$50_Y - end - attribute \src "ls180.v:2745.44-2745.85" - cell $not $not$ls180.v:2745$51 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:2745$51_Y - end - attribute \src "ls180.v:2751.48-2751.91" - cell $not $not$ls180.v:2751$52 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:2751$52_Y - end - attribute \src "ls180.v:2752.47-2752.88" - cell $not $not$ls180.v:2752$53 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_rx_fifo_sink_ready - connect \Y $not$ls180.v:2752$53_Y - end - attribute \src "ls180.v:2755.44-2755.87" - cell $not $not$ls180.v:2755$56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:2755$56_Y - end - attribute \src "ls180.v:2793.105-2793.144" - cell $not $not$ls180.v:2793$66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_tx_fifo_readable - connect \Y $not$ls180.v:2793$66_Y - end - attribute \src "ls180.v:2823.105-2823.144" - cell $not $not$ls180.v:2823$77 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_rx_fifo_readable - connect \Y $not$ls180.v:2823$77_Y - end - attribute \src "ls180.v:2956.34-2956.64" - cell $not $not$ls180.v:2956$95 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_storage [0] - connect \Y $not$ls180.v:2956$95_Y - end - attribute \src "ls180.v:2957.31-2957.61" - cell $not $not$ls180.v:2957$96 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_storage [1] - connect \Y $not$ls180.v:2957$96_Y - end - attribute \src "ls180.v:2958.32-2958.62" - cell $not $not$ls180.v:2958$97 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_storage [2] - connect \Y $not$ls180.v:2958$97_Y - end - attribute \src "ls180.v:2959.32-2959.62" - cell $not $not$ls180.v:2959$98 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_storage [3] - connect \Y $not$ls180.v:2959$98_Y - end - attribute \src "ls180.v:3001.33-3001.56" - cell $not $not$ls180.v:3001$101 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:3001$101_Y - end - attribute \src "ls180.v:3102.58-3102.106" - cell $not $not$ls180.v:3102$131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:3102$131_Y - end - attribute \src "ls180.v:3156.9-3156.45" - cell $not $not$ls180.v:3156$136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_refresh_req - connect \Y $not$ls180.v:3156$136_Y - end - attribute \src "ls180.v:3259.58-3259.106" - cell $not $not$ls180.v:3259$161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:3259$161_Y - end - attribute \src "ls180.v:3313.9-3313.45" - cell $not $not$ls180.v:3313$166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_refresh_req - connect \Y $not$ls180.v:3313$166_Y - end - attribute \src "ls180.v:3416.58-3416.106" - cell $not $not$ls180.v:3416$191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:3416$191_Y - end - attribute \src "ls180.v:3470.9-3470.45" - cell $not $not$ls180.v:3470$196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_refresh_req - connect \Y $not$ls180.v:3470$196_Y - end - attribute \src "ls180.v:3573.58-3573.106" - cell $not $not$ls180.v:3573$221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:3573$221_Y - end - attribute \src "ls180.v:3627.9-3627.45" - cell $not $not$ls180.v:3627$226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_refresh_req - connect \Y $not$ls180.v:3627$226_Y - end - attribute \src "ls180.v:3669.149-3669.187" - cell $not $not$ls180.v:3669$229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3669$229_Y - end - attribute \src "ls180.v:3669.193-3669.230" - cell $not $not$ls180.v:3669$231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3669$231_Y - end - attribute \src "ls180.v:3670.149-3670.187" - cell $not $not$ls180.v:3670$235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3670$235_Y - end - attribute \src "ls180.v:3670.193-3670.230" - cell $not $not$ls180.v:3670$237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3670$237_Y - end - attribute \src "ls180.v:3686.43-3686.73" - cell $not $not$ls180.v:3686$265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \main_sdram_interface_wdata_we - connect \Y $not$ls180.v:3686$265_Y - end - attribute \src "ls180.v:3689.205-3689.245" - cell $not $not$ls180.v:3689$268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:3689$268_Y - end - attribute \src "ls180.v:3689.251-3689.290" - cell $not $not$ls180.v:3689$270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:3689$270_Y - end - attribute \src "ls180.v:3689.159-3689.292" - cell $not $not$ls180.v:3689$272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3689$271_Y - connect \Y $not$ls180.v:3689$272_Y - end - attribute \src "ls180.v:3690.205-3690.245" - cell $not $not$ls180.v:3690$281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:3690$281_Y - end - attribute \src "ls180.v:3690.251-3690.290" - cell $not $not$ls180.v:3690$283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:3690$283_Y - end - attribute \src "ls180.v:3690.159-3690.292" - cell $not $not$ls180.v:3690$285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3690$284_Y - connect \Y $not$ls180.v:3690$285_Y - end - attribute \src "ls180.v:3691.205-3691.245" - cell $not $not$ls180.v:3691$294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:3691$294_Y - end - attribute \src "ls180.v:3691.251-3691.290" - cell $not $not$ls180.v:3691$296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:3691$296_Y - end - attribute \src "ls180.v:3691.159-3691.292" - cell $not $not$ls180.v:3691$298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3691$297_Y - connect \Y $not$ls180.v:3691$298_Y - end - attribute \src "ls180.v:3692.205-3692.245" - cell $not $not$ls180.v:3692$307 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:3692$307_Y - end - attribute \src "ls180.v:3692.251-3692.290" - cell $not $not$ls180.v:3692$309 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:3692$309_Y - end - attribute \src "ls180.v:3692.159-3692.292" - cell $not $not$ls180.v:3692$311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3692$310_Y - connect \Y $not$ls180.v:3692$311_Y - end - attribute \src "ls180.v:3719.71-3719.103" - cell $not $not$ls180.v:3719$322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \Y $not$ls180.v:3719$322_Y - end - attribute \src "ls180.v:3722.205-3722.245" - cell $not $not$ls180.v:3722$326 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:3722$326_Y - end - attribute \src "ls180.v:3722.251-3722.290" - cell $not $not$ls180.v:3722$328 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:3722$328_Y - end - attribute \src "ls180.v:3722.159-3722.292" - cell $not $not$ls180.v:3722$330 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3722$329_Y - connect \Y $not$ls180.v:3722$330_Y - end - attribute \src "ls180.v:3723.205-3723.245" - cell $not $not$ls180.v:3723$339 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:3723$339_Y - end - attribute \src "ls180.v:3723.251-3723.290" - cell $not $not$ls180.v:3723$341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:3723$341_Y - end - attribute \src "ls180.v:3723.159-3723.292" - cell $not $not$ls180.v:3723$343 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3723$342_Y - connect \Y $not$ls180.v:3723$343_Y - end - attribute \src "ls180.v:3724.205-3724.245" - cell $not $not$ls180.v:3724$352 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:3724$352_Y - end - attribute \src "ls180.v:3724.251-3724.290" - cell $not $not$ls180.v:3724$354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:3724$354_Y - end - attribute \src "ls180.v:3724.159-3724.292" - cell $not $not$ls180.v:3724$356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3724$355_Y - connect \Y $not$ls180.v:3724$356_Y - end - attribute \src "ls180.v:3725.205-3725.245" - cell $not $not$ls180.v:3725$365 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:3725$365_Y - end - attribute \src "ls180.v:3725.251-3725.290" - cell $not $not$ls180.v:3725$367 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:3725$367_Y - end - attribute \src "ls180.v:3725.159-3725.292" - cell $not $not$ls180.v:3725$369 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3725$368_Y - connect \Y $not$ls180.v:3725$369_Y - end - attribute \src "ls180.v:3788.71-3788.103" - cell $not $not$ls180.v:3788$408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \Y $not$ls180.v:3788$408_Y - end - attribute \src "ls180.v:3809.112-3809.150" - cell $not $not$ls180.v:3809$411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3809$411_Y - end - attribute \src "ls180.v:3809.156-3809.193" - cell $not $not$ls180.v:3809$413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3809$413_Y - end - attribute \src "ls180.v:3809.68-3809.195" - cell $not $not$ls180.v:3809$415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3809$414_Y - connect \Y $not$ls180.v:3809$415_Y - end - attribute \src "ls180.v:3817.11-3817.38" - cell $not $not$ls180.v:3817$418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_write_available - connect \Y $not$ls180.v:3817$418_Y - end - attribute \src "ls180.v:3847.112-3847.150" - cell $not $not$ls180.v:3847$420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3847$420_Y - end - attribute \src "ls180.v:3847.156-3847.193" - cell $not $not$ls180.v:3847$422 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3847$422_Y - end - attribute \src "ls180.v:3847.68-3847.195" - cell $not $not$ls180.v:3847$424 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3847$423_Y - connect \Y $not$ls180.v:3847$424_Y - end - attribute \src "ls180.v:3855.11-3855.37" - cell $not $not$ls180.v:3855$427 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_read_available - connect \Y $not$ls180.v:3855$427_Y - end - attribute \src "ls180.v:3865.87-3865.331" - cell $not $not$ls180.v:3865$439 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3865$438_Y - connect \Y $not$ls180.v:3865$439_Y - end - attribute \src "ls180.v:3866.35-3866.68" - cell $not $not$ls180.v:3866$442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_valid - connect \Y $not$ls180.v:3866$442_Y - end - attribute \src "ls180.v:3866.73-3866.105" - cell $not $not$ls180.v:3866$443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \Y $not$ls180.v:3866$443_Y - end - attribute \src "ls180.v:3870.87-3870.331" - cell $not $not$ls180.v:3870$455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3870$454_Y - connect \Y $not$ls180.v:3870$455_Y - end - attribute \src "ls180.v:3871.35-3871.68" - cell $not $not$ls180.v:3871$458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_valid - connect \Y $not$ls180.v:3871$458_Y - end - attribute \src "ls180.v:3871.73-3871.105" - cell $not $not$ls180.v:3871$459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \Y $not$ls180.v:3871$459_Y - end - attribute \src "ls180.v:3875.87-3875.331" - cell $not $not$ls180.v:3875$471 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3875$470_Y - connect \Y $not$ls180.v:3875$471_Y - end - attribute \src "ls180.v:3876.35-3876.68" - cell $not $not$ls180.v:3876$474 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_valid - connect \Y $not$ls180.v:3876$474_Y - end - attribute \src "ls180.v:3876.73-3876.105" - cell $not $not$ls180.v:3876$475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \Y $not$ls180.v:3876$475_Y - end - attribute \src "ls180.v:3880.87-3880.331" - cell $not $not$ls180.v:3880$487 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3880$486_Y - connect \Y $not$ls180.v:3880$487_Y - end - attribute \src "ls180.v:3881.35-3881.68" - cell $not $not$ls180.v:3881$490 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_valid - connect \Y $not$ls180.v:3881$490_Y - end - attribute \src "ls180.v:3881.73-3881.105" - cell $not $not$ls180.v:3881$491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \Y $not$ls180.v:3881$491_Y - end - attribute \src "ls180.v:3885.128-3885.372" - cell $not $not$ls180.v:3885$504 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3885$503_Y - connect \Y $not$ls180.v:3885$504_Y - end - attribute \src "ls180.v:3885.502-3885.746" - cell $not $not$ls180.v:3885$520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3885$519_Y - connect \Y $not$ls180.v:3885$520_Y - end - attribute \src "ls180.v:3885.876-3885.1120" - cell $not $not$ls180.v:3885$536 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3885$535_Y - connect \Y $not$ls180.v:3885$536_Y - end - attribute \src "ls180.v:3885.1250-3885.1494" - cell $not $not$ls180.v:3885$552 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3885$551_Y - connect \Y $not$ls180.v:3885$552_Y - end - attribute \src "ls180.v:3907.32-3907.50" - cell $not $not$ls180.v:3907$558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_cyc - connect \Y $not$ls180.v:3907$558_Y - end - attribute \src "ls180.v:3946.30-3946.50" - cell $not $not$ls180.v:3946$563 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter_skip - connect \Y $not$ls180.v:3946$563_Y - end - attribute \src "ls180.v:3947.30-3947.50" - cell $not $not$ls180.v:3947$564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter_skip - connect \Y $not$ls180.v:3947$564_Y - end - attribute \src "ls180.v:3972.27-3972.48" - cell $not $not$ls180.v:3972$570 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_cyc - connect \Y $not$ls180.v:3972$570_Y - end - attribute \src "ls180.v:3973.30-3973.50" - cell $not $not$ls180.v:3973$571 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:3973$571_Y - end - attribute \src "ls180.v:3974.80-3974.98" - cell $not $not$ls180.v:3974$573 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_cmd_consumed - connect \Y $not$ls180.v:3974$573_Y - end - attribute \src "ls180.v:3975.107-3975.127" - cell $not $not$ls180.v:3975$577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wdata_consumed - connect \Y $not$ls180.v:3975$577_Y - end - attribute \src "ls180.v:3976.78-3976.103" - cell $not $not$ls180.v:3976$580 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_we - connect \Y $not$ls180.v:3976$580_Y - end - attribute \src "ls180.v:3977.91-3977.111" - cell $not $not$ls180.v:3977$583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:3977$583_Y - end - attribute \src "ls180.v:4095.62-4095.88" - cell $not $not$ls180.v:4095$622 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_clocker_clk_d - connect \Y $not$ls180.v:4095$622_Y - end - attribute \src "ls180.v:4236.55-4236.98" - cell $not $not$ls180.v:4236$636 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdr_cmdr_converter_strobe_all - connect \Y $not$ls180.v:4236$636_Y - end - attribute \src "ls180.v:4239.49-4239.88" - cell $not $not$ls180.v:4239$639 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:4239$639_Y - end - attribute \src "ls180.v:4363.56-4363.100" - cell $not $not$ls180.v:4363$657 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_dataw_crcr_converter_strobe_all - connect \Y $not$ls180.v:4363$657_Y - end - attribute \src "ls180.v:4366.50-4366.90" - cell $not $not$ls180.v:4366$660 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:4366$660_Y - end - attribute \src "ls180.v:4416.31-4416.60" - cell $not $not$ls180.v:4416$666 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_dataw_sink_valid - connect \Y $not$ls180.v:4416$666_Y - end - attribute \src "ls180.v:4497.57-4497.102" - cell $not $not$ls180.v:4497$672 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_datar_datar_converter_strobe_all - connect \Y $not$ls180.v:4497$672_Y - end - attribute \src "ls180.v:4500.51-4500.92" - cell $not $not$ls180.v:4500$675 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_datar_datar_buf_source_valid - connect \Y $not$ls180.v:4500$675_Y - end - attribute \src "ls180.v:4616.49-4616.88" - cell $not $not$ls180.v:4616$691 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_valid - connect \Y $not$ls180.v:4616$691_Y - end - attribute \src "ls180.v:5140.57-5140.102" - cell $not $not$ls180.v:5140$976 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdblock2mem_converter_strobe_all - connect \Y $not$ls180.v:5140$976_Y - end - attribute \src "ls180.v:5152.59-5152.116" - cell $not $not$ls180.v:5152$979 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdblock2mem_wishbonedmawriter_enable_storage - connect \Y $not$ls180.v:5152$979_Y - end - attribute \src "ls180.v:5211.45-5211.88" - cell $not $not$ls180.v:5211$986 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdmem2block_dma_enable_storage - connect \Y $not$ls180.v:5211$986_Y - end - attribute \src "ls180.v:5509.69-5509.88" - cell $not $not$ls180.v:5509$1051 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \Y $not$ls180.v:5509$1051_Y - end - attribute \src "ls180.v:5526.63-5526.94" - cell $not $not$ls180.v:5526$1072 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5526$1072_Y - end - attribute \src "ls180.v:5529.65-5529.96" - cell $not $not$ls180.v:5529$1079 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5529$1079_Y - end - attribute \src "ls180.v:5532.65-5532.96" - cell $not $not$ls180.v:5532$1086 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5532$1086_Y - end - attribute \src "ls180.v:5535.65-5535.96" - cell $not $not$ls180.v:5535$1093 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5535$1093_Y - end - attribute \src "ls180.v:5538.65-5538.96" - cell $not $not$ls180.v:5538$1100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5538$1100_Y - end - attribute \src "ls180.v:5541.68-5541.99" - cell $not $not$ls180.v:5541$1107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5541$1107_Y - end - attribute \src "ls180.v:5544.68-5544.99" - cell $not $not$ls180.v:5544$1114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5544$1114_Y - end - attribute \src "ls180.v:5547.68-5547.99" - cell $not $not$ls180.v:5547$1121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5547$1121_Y - end - attribute \src "ls180.v:5550.68-5550.99" - cell $not $not$ls180.v:5550$1128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5550$1128_Y - end - attribute \src "ls180.v:5564.59-5564.90" - cell $not $not$ls180.v:5564$1136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5564$1136_Y - end - attribute \src "ls180.v:5570.59-5570.90" - cell $not $not$ls180.v:5570$1144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5570$1144_Y - end - attribute \src "ls180.v:5576.66-5576.97" - cell $not $not$ls180.v:5576$1152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5576$1152_Y - end - attribute \src "ls180.v:5579.66-5579.97" - cell $not $not$ls180.v:5579$1159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5579$1159_Y - end - attribute \src "ls180.v:5582.66-5582.97" - cell $not $not$ls180.v:5582$1166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5582$1166_Y - end - attribute \src "ls180.v:5585.66-5585.97" - cell $not $not$ls180.v:5585$1173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5585$1173_Y - end - attribute \src "ls180.v:5588.66-5588.97" - cell $not $not$ls180.v:5588$1180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5588$1180_Y - end - attribute \src "ls180.v:5591.66-5591.97" - cell $not $not$ls180.v:5591$1187 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5591$1187_Y - end - attribute \src "ls180.v:5594.66-5594.97" - cell $not $not$ls180.v:5594$1194 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5594$1194_Y - end - attribute \src "ls180.v:5597.66-5597.97" - cell $not $not$ls180.v:5597$1201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5597$1201_Y - end - attribute \src "ls180.v:5600.68-5600.99" - cell $not $not$ls180.v:5600$1208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5600$1208_Y - end - attribute \src "ls180.v:5603.68-5603.99" - cell $not $not$ls180.v:5603$1215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5603$1215_Y - end - attribute \src "ls180.v:5606.68-5606.99" - cell $not $not$ls180.v:5606$1222 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5606$1222_Y - end - attribute \src "ls180.v:5609.68-5609.99" - cell $not $not$ls180.v:5609$1229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5609$1229_Y - end - attribute \src "ls180.v:5612.68-5612.99" - cell $not $not$ls180.v:5612$1236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5612$1236_Y - end - attribute \src "ls180.v:5615.65-5615.96" - cell $not $not$ls180.v:5615$1243 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5615$1243_Y - end - attribute \src "ls180.v:5618.66-5618.97" - cell $not $not$ls180.v:5618$1250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5618$1250_Y - end - attribute \src "ls180.v:5638.70-5638.101" - cell $not $not$ls180.v:5638$1258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5638$1258_Y - end - attribute \src "ls180.v:5641.70-5641.101" - cell $not $not$ls180.v:5641$1265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5641$1265_Y - end - attribute \src "ls180.v:5644.70-5644.101" - cell $not $not$ls180.v:5644$1272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5644$1272_Y - end - attribute \src "ls180.v:5647.70-5647.101" - cell $not $not$ls180.v:5647$1279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5647$1279_Y - end - attribute \src "ls180.v:5650.69-5650.100" - cell $not $not$ls180.v:5650$1286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5650$1286_Y - end - attribute \src "ls180.v:5653.69-5653.100" - cell $not $not$ls180.v:5653$1293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5653$1293_Y - end - attribute \src "ls180.v:5656.69-5656.100" - cell $not $not$ls180.v:5656$1300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5656$1300_Y - end - attribute \src "ls180.v:5659.69-5659.100" - cell $not $not$ls180.v:5659$1307 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5659$1307_Y - end - attribute \src "ls180.v:5662.67-5662.98" - cell $not $not$ls180.v:5662$1314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5662$1314_Y - end - attribute \src "ls180.v:5665.71-5665.102" - cell $not $not$ls180.v:5665$1321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5665$1321_Y - end - attribute \src "ls180.v:5668.71-5668.102" - cell $not $not$ls180.v:5668$1328 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5668$1328_Y - end - attribute \src "ls180.v:5671.71-5671.102" - cell $not $not$ls180.v:5671$1335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5671$1335_Y - end - attribute \src "ls180.v:5674.71-5674.102" - cell $not $not$ls180.v:5674$1342 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5674$1342_Y - end - attribute \src "ls180.v:5677.71-5677.102" - cell $not $not$ls180.v:5677$1349 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5677$1349_Y - end - attribute \src "ls180.v:5680.71-5680.102" - cell $not $not$ls180.v:5680$1356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5680$1356_Y - end - attribute \src "ls180.v:5683.70-5683.101" - cell $not $not$ls180.v:5683$1363 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5683$1363_Y - end - attribute \src "ls180.v:5686.70-5686.101" - cell $not $not$ls180.v:5686$1370 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5686$1370_Y - end - attribute \src "ls180.v:5689.70-5689.101" - cell $not $not$ls180.v:5689$1377 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5689$1377_Y - end - attribute \src "ls180.v:5692.70-5692.101" - cell $not $not$ls180.v:5692$1384 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5692$1384_Y - end - attribute \src "ls180.v:5695.70-5695.101" - cell $not $not$ls180.v:5695$1391 - parameter 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$not$ls180.v:5794$1539 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5794$1539_Y - end - attribute \src "ls180.v:5797.68-5797.99" - cell $not $not$ls180.v:5797$1546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5797$1546_Y - end - attribute \src "ls180.v:5800.68-5800.99" - cell $not $not$ls180.v:5800$1553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5800$1553_Y - end - attribute \src "ls180.v:5803.68-5803.99" - cell $not $not$ls180.v:5803$1560 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5803$1560_Y - end - attribute \src "ls180.v:5806.68-5806.99" - cell $not $not$ls180.v:5806$1567 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5806$1567_Y - end - attribute \src "ls180.v:5809.68-5809.99" - cell $not $not$ls180.v:5809$1574 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5809$1574_Y - end - attribute \src "ls180.v:5812.65-5812.96" - cell $not $not$ls180.v:5812$1581 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5812$1581_Y - end - attribute \src "ls180.v:5815.66-5815.97" - cell $not $not$ls180.v:5815$1588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5815$1588_Y - end - attribute \src "ls180.v:5818.68-5818.99" - cell $not $not$ls180.v:5818$1595 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - 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\Y $not$ls180.v:5852$1624_Y - end - attribute \src "ls180.v:5855.73-5855.104" - cell $not $not$ls180.v:5855$1631 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:5855$1631_Y - end - attribute \src "ls180.v:5858.73-5858.104" - cell $not $not$ls180.v:5858$1638 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:5858$1638_Y - end - attribute \src "ls180.v:5861.67-5861.98" - cell $not $not$ls180.v:5861$1645 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:5861$1645_Y - end - attribute \src "ls180.v:5869.70-5869.101" - cell $not $not$ls180.v:5869$1653 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:5869$1653_Y - end - attribute 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"ls180.v:5969.60-5969.91" - cell $not $not$ls180.v:5969$1810 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:5969$1810_Y - end - attribute \src "ls180.v:5972.66-5972.97" - cell $not $not$ls180.v:5972$1817 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:5972$1817_Y - end - attribute \src "ls180.v:5975.69-5975.100" - cell $not $not$ls180.v:5975$1824 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:5975$1824_Y - end - attribute \src "ls180.v:5978.69-5978.100" - cell $not $not$ls180.v:5978$1831 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:5978$1831_Y - end - attribute \src "ls180.v:6002.64-6002.96" - cell $not $not$ls180.v:6002$1840 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6002$1840_Y - end - attribute \src "ls180.v:6005.64-6005.96" - cell $not $not$ls180.v:6005$1847 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6005$1847_Y - end - attribute \src "ls180.v:6008.64-6008.96" - cell $not $not$ls180.v:6008$1854 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6008$1854_Y - end - attribute \src "ls180.v:6011.64-6011.96" - cell $not $not$ls180.v:6011$1861 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6011$1861_Y - end - attribute \src "ls180.v:6014.66-6014.98" - cell $not $not$ls180.v:6014$1868 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6014$1868_Y - end - attribute \src "ls180.v:6017.66-6017.98" - cell $not $not$ls180.v:6017$1875 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6017$1875_Y - end - attribute \src "ls180.v:6020.66-6020.98" - cell $not $not$ls180.v:6020$1882 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6020$1882_Y - end - attribute \src "ls180.v:6023.66-6023.98" - cell $not $not$ls180.v:6023$1889 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6023$1889_Y - end - attribute \src "ls180.v:6026.62-6026.94" - cell $not $not$ls180.v:6026$1896 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6026$1896_Y - end - attribute \src "ls180.v:6029.72-6029.104" - cell $not $not$ls180.v:6029$1903 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6029$1903_Y - end - attribute \src "ls180.v:6032.65-6032.97" - cell $not $not$ls180.v:6032$1910 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6032$1910_Y - end - attribute \src "ls180.v:6035.65-6035.97" - cell $not $not$ls180.v:6035$1917 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6035$1917_Y - end - attribute \src "ls180.v:6038.65-6038.97" - cell $not $not$ls180.v:6038$1924 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6038$1924_Y - end - attribute \src "ls180.v:6041.65-6041.97" - cell $not $not$ls180.v:6041$1931 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6041$1931_Y - end - attribute \src "ls180.v:6044.83-6044.115" - cell $not $not$ls180.v:6044$1938 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6044$1938_Y - end - attribute \src "ls180.v:6047.84-6047.116" - cell $not $not$ls180.v:6047$1945 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6047$1945_Y - end - attribute \src "ls180.v:6050.69-6050.101" - cell $not $not$ls180.v:6050$1952 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6050$1952_Y - end - attribute \src "ls180.v:6070.67-6070.99" - cell $not $not$ls180.v:6070$1960 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6070$1960_Y - end - attribute \src "ls180.v:6073.65-6073.97" - cell $not $not$ls180.v:6073$1967 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6073$1967_Y - end - attribute \src "ls180.v:6076.66-6076.98" - cell $not $not$ls180.v:6076$1974 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6076$1974_Y - end - attribute \src "ls180.v:6079.82-6079.114" - cell $not $not$ls180.v:6079$1981 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6079$1981_Y - end - attribute \src "ls180.v:6082.83-6082.115" - cell $not $not$ls180.v:6082$1988 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6082$1988_Y - end - attribute \src "ls180.v:6085.69-6085.101" - cell $not $not$ls180.v:6085$1995 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6085$1995_Y - end - attribute \src "ls180.v:6088.66-6088.98" - cell $not $not$ls180.v:6088$2002 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6088$2002_Y - end - attribute \src "ls180.v:6091.65-6091.97" - cell $not $not$ls180.v:6091$2009 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6091$2009_Y - end - attribute \src "ls180.v:6104.71-6104.103" - cell $not $not$ls180.v:6104$2017 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6104$2017_Y - end - attribute \src "ls180.v:6107.71-6107.103" - cell $not $not$ls180.v:6107$2024 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6107$2024_Y - end - attribute \src "ls180.v:6110.71-6110.103" - cell $not $not$ls180.v:6110$2031 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6110$2031_Y - end - attribute \src "ls180.v:6113.71-6113.103" - cell $not $not$ls180.v:6113$2038 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6113$2038_Y - end - attribute \src "ls180.v:6488.86-6488.330" - cell $not $not$ls180.v:6488$2085 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6488$2084_Y - connect \Y $not$ls180.v:6488$2085_Y - end - attribute \src "ls180.v:6512.86-6512.330" - cell $not $not$ls180.v:6512$2101 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6512$2100_Y - connect \Y $not$ls180.v:6512$2101_Y - end - attribute \src "ls180.v:6536.86-6536.330" - cell $not $not$ls180.v:6536$2117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6536$2116_Y - connect \Y $not$ls180.v:6536$2117_Y - end - attribute \src "ls180.v:6560.86-6560.330" - cell $not $not$ls180.v:6560$2133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6560$2132_Y - connect \Y $not$ls180.v:6560$2133_Y - end - attribute \src "ls180.v:7006.18-7006.43" - cell $not $not$ls180.v:7006$2185 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_clocker_clk0 - connect \Y $not$ls180.v:7006$2185_Y - end - attribute \src "ls180.v:7085.72-7085.101" - cell $not $not$ls180.v:7085$2193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_ack - connect \Y $not$ls180.v:7085$2193_Y - end - attribute \src "ls180.v:7089.39-7089.64" - cell $not $not$ls180.v:7089$2195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_tx_busy - connect \Y $not$ls180.v:7089$2195_Y - end - attribute \src "ls180.v:7089.70-7089.98" - cell $not $not$ls180.v:7089$2197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_sink_ready - connect \Y $not$ls180.v:7089$2197_Y - end - attribute \src "ls180.v:7118.7-7118.32" - cell $not $not$ls180.v:7118$2204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_rx_busy - connect \Y $not$ls180.v:7118$2204_Y - end - attribute \src "ls180.v:7119.9-7119.29" - cell $not $not$ls180.v:7119$2205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_rx - connect \Y $not$ls180.v:7119$2205_Y - end - attribute \src "ls180.v:7152.8-7152.41" - cell $not $not$ls180.v:7152$2211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_tx_trigger - connect \Y $not$ls180.v:7152$2211_Y - end - attribute \src "ls180.v:7159.8-7159.41" - cell $not $not$ls180.v:7159$2213 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_rx_trigger - connect \Y $not$ls180.v:7159$2213_Y - end - attribute \src "ls180.v:7169.104-7169.142" - cell $not $not$ls180.v:7169$2216 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_tx_fifo_replace - connect \Y $not$ls180.v:7169$2216_Y - end - attribute \src "ls180.v:7175.104-7175.142" - cell $not $not$ls180.v:7175$2221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_tx_fifo_replace - connect \Y $not$ls180.v:7175$2221_Y - end - attribute \src "ls180.v:7176.8-7176.46" - cell $not $not$ls180.v:7176$2223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_tx_fifo_do_read - connect \Y $not$ls180.v:7176$2223_Y - end - attribute \src "ls180.v:7191.104-7191.142" - cell $not $not$ls180.v:7191$2227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_rx_fifo_replace - connect \Y $not$ls180.v:7191$2227_Y - end - attribute \src "ls180.v:7197.104-7197.142" - cell $not $not$ls180.v:7197$2232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_rx_fifo_replace - connect \Y $not$ls180.v:7197$2232_Y - end - attribute \src "ls180.v:7198.8-7198.46" - cell $not $not$ls180.v:7198$2234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_rx_fifo_do_read - connect \Y $not$ls180.v:7198$2234_Y - end - attribute \src "ls180.v:7236.8-7236.44" - cell $not $not$ls180.v:7236$2239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_timer_zero_trigger - connect \Y $not$ls180.v:7236$2239_Y - end - attribute \src "ls180.v:7244.32-7244.55" - cell $not $not$ls180.v:7244$2241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:7244$2241_Y - end - attribute \src "ls180.v:7314.136-7314.189" - cell $not $not$ls180.v:7314$2256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7314$2256_Y - end - attribute \src "ls180.v:7320.136-7320.189" - cell $not $not$ls180.v:7320$2261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7320$2261_Y - end - attribute \src "ls180.v:7321.8-7321.61" - cell $not $not$ls180.v:7321$2263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7321$2263_Y - end - attribute \src "ls180.v:7329.8-7329.56" - cell $not $not$ls180.v:7329$2266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:7329$2266_Y - end - attribute \src "ls180.v:7344.8-7344.46" - cell $not $not$ls180.v:7344$2268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \Y $not$ls180.v:7344$2268_Y - end - attribute \src "ls180.v:7360.136-7360.189" - cell $not $not$ls180.v:7360$2272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7360$2272_Y - end - attribute \src "ls180.v:7366.136-7366.189" - cell $not $not$ls180.v:7366$2277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7366$2277_Y - end - attribute \src "ls180.v:7367.8-7367.61" - cell $not $not$ls180.v:7367$2279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7367$2279_Y - end - attribute \src "ls180.v:7375.8-7375.56" - cell $not $not$ls180.v:7375$2282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:7375$2282_Y - end - attribute \src "ls180.v:7390.8-7390.46" - cell $not $not$ls180.v:7390$2284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \Y $not$ls180.v:7390$2284_Y - end - attribute \src "ls180.v:7406.136-7406.189" - cell $not $not$ls180.v:7406$2288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7406$2288_Y - end - attribute \src "ls180.v:7412.136-7412.189" - cell $not $not$ls180.v:7412$2293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7412$2293_Y - end - attribute \src "ls180.v:7413.8-7413.61" - cell $not $not$ls180.v:7413$2295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7413$2295_Y - end - attribute \src "ls180.v:7421.8-7421.56" - cell $not $not$ls180.v:7421$2298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:7421$2298_Y - end - attribute \src "ls180.v:7436.8-7436.46" - cell $not $not$ls180.v:7436$2300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \Y $not$ls180.v:7436$2300_Y - end - attribute \src "ls180.v:7452.136-7452.189" - cell $not $not$ls180.v:7452$2304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7452$2304_Y - end - attribute \src "ls180.v:7458.136-7458.189" - cell $not $not$ls180.v:7458$2309 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7458$2309_Y - end - attribute \src "ls180.v:7459.8-7459.61" - cell $not $not$ls180.v:7459$2311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7459$2311_Y - end - attribute \src "ls180.v:7467.8-7467.56" - cell $not $not$ls180.v:7467$2314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:7467$2314_Y - end - attribute \src "ls180.v:7482.8-7482.46" - cell $not $not$ls180.v:7482$2316 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \Y $not$ls180.v:7482$2316_Y - end - attribute \src "ls180.v:7490.7-7490.22" - cell $not $not$ls180.v:7490$2319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_en0 - connect \Y $not$ls180.v:7490$2319_Y - end - attribute \src "ls180.v:7493.8-7493.29" - cell $not $not$ls180.v:7493$2320 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_max_time0 - connect \Y $not$ls180.v:7493$2320_Y - end - attribute \src "ls180.v:7497.7-7497.22" - cell $not $not$ls180.v:7497$2322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_en1 - connect \Y $not$ls180.v:7497$2322_Y - end - attribute \src "ls180.v:7500.8-7500.29" - cell $not $not$ls180.v:7500$2323 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_max_time1 - connect \Y $not$ls180.v:7500$2323_Y - end - attribute \src "ls180.v:7619.30-7619.60" - cell $not $not$ls180.v:7619$2325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_sync_rhs_array_muxed2 - connect \Y $not$ls180.v:7619$2325_Y - end - attribute \src "ls180.v:7620.30-7620.60" - cell $not $not$ls180.v:7620$2326 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_sync_rhs_array_muxed3 - connect \Y $not$ls180.v:7620$2326_Y - end - attribute \src "ls180.v:7621.29-7621.59" - cell $not $not$ls180.v:7621$2327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_sync_rhs_array_muxed4 - connect \Y $not$ls180.v:7621$2327_Y - end - attribute \src "ls180.v:7632.8-7632.33" - cell $not $not$ls180.v:7632$2328 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_tccdcon_ready - connect \Y $not$ls180.v:7632$2328_Y - end - attribute \src "ls180.v:7647.8-7647.33" - cell $not $not$ls180.v:7647$2331 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_twtrcon_ready - connect \Y $not$ls180.v:7647$2331_Y - end - attribute \src "ls180.v:7691.23-7691.31" - cell $not $not$ls180.v:7691$2362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_cs - connect \Y $not$ls180.v:7691$2362_Y - end - attribute \src "ls180.v:7691.36-7691.51" - cell $not $not$ls180.v:7691$2363 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_cs_enable - connect \Y $not$ls180.v:7691$2363_Y - end - attribute \src "ls180.v:7717.7-7717.32" - cell $not $not$ls180.v:7717$2366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_clocker_stop - connect \Y $not$ls180.v:7717$2366_Y - end - attribute \src "ls180.v:7789.8-7789.47" - cell $not $not$ls180.v:7789$2378 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:7789$2378_Y - end - attribute \src "ls180.v:7870.8-7870.48" - cell $not $not$ls180.v:7870$2390 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:7870$2390_Y - end - attribute \src "ls180.v:7931.8-7931.49" - cell $not $not$ls180.v:7931$2402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_datar_datar_buf_source_valid - connect \Y $not$ls180.v:7931$2402_Y - end - attribute \src "ls180.v:8101.102-8101.139" - cell $not $not$ls180.v:8101$2416 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8101$2416_Y - end - attribute \src "ls180.v:8107.102-8107.139" - cell $not $not$ls180.v:8107$2421 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8107$2421_Y - end - attribute \src "ls180.v:8108.8-8108.45" - cell $not $not$ls180.v:8108$2423 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdblock2mem_fifo_do_read - connect \Y $not$ls180.v:8108$2423_Y - end - attribute \src "ls180.v:8187.102-8187.139" - cell $not $not$ls180.v:8187$2438 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8187$2438_Y - end - attribute \src "ls180.v:8193.102-8193.139" - cell $not $not$ls180.v:8193$2443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8193$2443_Y - end - attribute \src "ls180.v:8194.8-8194.45" - cell $not $not$ls180.v:8194$2445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdmem2block_fifo_do_read - connect \Y $not$ls180.v:8194$2445_Y - end - attribute \src "ls180.v:8211.22-8211.37" - cell $not $not$ls180.v:8211$2449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cs - connect \Y $not$ls180.v:8211$2449_Y - end - attribute \src "ls180.v:8211.42-8211.64" - cell $not $not$ls180.v:8211$2450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cs_enable - connect \Y $not$ls180.v:8211$2450_Y - end - attribute \src "ls180.v:8249.9-8249.28" - cell $not $not$ls180.v:8249$2453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [0] - connect \Y $not$ls180.v:8249$2453_Y - end - attribute \src "ls180.v:8264.9-8264.28" - cell $not $not$ls180.v:8264$2454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [1] - connect \Y $not$ls180.v:8264$2454_Y - end - attribute \src "ls180.v:8279.9-8279.28" - cell $not $not$ls180.v:8279$2455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [2] - connect \Y $not$ls180.v:8279$2455_Y - end - attribute \src "ls180.v:8294.9-8294.28" - cell $not $not$ls180.v:8294$2456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [3] - connect \Y $not$ls180.v:8294$2456_Y - end - attribute \src "ls180.v:8311.8-8311.21" - cell $not $not$ls180.v:8311$2457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_done - connect \Y $not$ls180.v:8311$2457_Y - end - attribute \src "ls180.v:2635.10-2635.96" - cell $or $or$ls180.v:2635$21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface0_converted_interface_ack - connect \B \main_libresocsim_converter0_skip - connect \Y $or$ls180.v:2635$21_Y - end - attribute \src "ls180.v:2695.10-2695.96" - cell $or $or$ls180.v:2695$32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface1_converted_interface_ack - connect \B \main_libresocsim_converter1_skip - connect \Y $or$ls180.v:2695$32_Y - end - attribute \src "ls180.v:2754.54-2754.125" - cell $or $or$ls180.v:2754$55 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_rx_clear - connect \B $and$ls180.v:2754$54_Y - connect \Y $or$ls180.v:2754$55_Y - end - attribute \src "ls180.v:2778.37-2778.234" - cell $or $or$ls180.v:2778$65 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2778$63_Y - connect \B $and$ls180.v:2778$64_Y - connect \Y $or$ls180.v:2778$65_Y - end - attribute \src "ls180.v:2793.104-2793.180" - cell $or $or$ls180.v:2793$67 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:2793$66_Y - connect \B \main_libresocsim_uart_tx_fifo_re - connect \Y $or$ls180.v:2793$67_Y - end - attribute \src "ls180.v:2804.96-2804.183" - cell $or $or$ls180.v:2804$72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_tx_fifo_syncfifo_writable - connect \B \main_libresocsim_uart_tx_fifo_replace - connect \Y $or$ls180.v:2804$72_Y - end - attribute \src "ls180.v:2823.104-2823.180" - cell $or $or$ls180.v:2823$78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:2823$77_Y - connect \B \main_libresocsim_uart_rx_fifo_re - connect \Y $or$ls180.v:2823$78_Y - end - attribute \src "ls180.v:2834.96-2834.183" - cell $or $or$ls180.v:2834$83 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_uart_rx_fifo_syncfifo_writable - connect \B \main_libresocsim_uart_rx_fifo_replace - connect \Y $or$ls180.v:2834$83_Y - end - attribute \src "ls180.v:3007.39-3007.105" - cell $or $or$ls180.v:3007$104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_start0 - connect \B $ne$ls180.v:3007$103_Y - connect \Y $or$ls180.v:3007$104_Y - end - attribute \src "ls180.v:3050.59-3050.140" - cell $or $or$ls180.v:3050$108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_req_wdata_ready - connect \B \main_sdram_bankmachine0_req_rdata_valid - connect \Y $or$ls180.v:3050$108_Y - end - attribute \src "ls180.v:3051.44-3051.151" - cell $or $or$ls180.v:3051$109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $or$ls180.v:3051$109_Y - end - attribute \src "ls180.v:3059.45-3059.170" - cell $or $or$ls180.v:3059$113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3059$112_Y - connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3059$113_Y - end - attribute \src "ls180.v:3096.127-3096.245" - cell $or $or$ls180.v:3096$126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3096$126_Y - end - attribute \src "ls180.v:3102.57-3102.157" - cell $or $or$ls180.v:3102$132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3102$131_Y - connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:3102$132_Y - end - attribute \src "ls180.v:3207.59-3207.140" - cell $or $or$ls180.v:3207$138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_req_wdata_ready - connect \B \main_sdram_bankmachine1_req_rdata_valid - connect \Y $or$ls180.v:3207$138_Y - end - attribute \src "ls180.v:3208.44-3208.151" - cell $or $or$ls180.v:3208$139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $or$ls180.v:3208$139_Y - end - attribute \src "ls180.v:3216.45-3216.170" - cell $or $or$ls180.v:3216$143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3216$142_Y - connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3216$143_Y - end - attribute \src "ls180.v:3253.127-3253.245" - cell $or $or$ls180.v:3253$156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3253$156_Y - end - attribute \src "ls180.v:3259.57-3259.157" - cell $or $or$ls180.v:3259$162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3259$161_Y - connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:3259$162_Y - end - attribute \src "ls180.v:3364.59-3364.140" - cell $or $or$ls180.v:3364$168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_req_wdata_ready - connect \B \main_sdram_bankmachine2_req_rdata_valid - connect \Y $or$ls180.v:3364$168_Y - end - attribute \src "ls180.v:3365.44-3365.151" - cell $or $or$ls180.v:3365$169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $or$ls180.v:3365$169_Y - end - attribute \src "ls180.v:3373.45-3373.170" - cell $or $or$ls180.v:3373$173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3373$172_Y - connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3373$173_Y - end - attribute \src "ls180.v:3410.127-3410.245" - cell $or $or$ls180.v:3410$186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3410$186_Y - end - attribute \src "ls180.v:3416.57-3416.157" - cell $or $or$ls180.v:3416$192 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3416$191_Y - connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:3416$192_Y - end - attribute \src "ls180.v:3521.59-3521.140" - cell $or $or$ls180.v:3521$198 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_req_wdata_ready - connect \B \main_sdram_bankmachine3_req_rdata_valid - connect \Y $or$ls180.v:3521$198_Y - end - attribute \src "ls180.v:3522.44-3522.151" - cell $or $or$ls180.v:3522$199 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $or$ls180.v:3522$199_Y - end - attribute \src "ls180.v:3530.45-3530.170" - cell $or $or$ls180.v:3530$203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3530$202_Y - connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3530$203_Y - end - attribute \src "ls180.v:3567.127-3567.245" - cell $or $or$ls180.v:3567$216 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3567$216_Y - end - attribute \src "ls180.v:3573.57-3573.157" - cell $or $or$ls180.v:3573$222 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3573$221_Y - connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:3573$222_Y - end - attribute \src "ls180.v:3672.107-3672.193" - cell $or $or$ls180.v:3672$242 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_is_write - connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $or$ls180.v:3672$242_Y - end - attribute \src "ls180.v:3675.39-3675.204" - cell $or $or$ls180.v:3675$248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3675$246_Y - connect \B $and$ls180.v:3675$247_Y - connect \Y $or$ls180.v:3675$248_Y - end - attribute \src "ls180.v:3675.38-3675.289" - cell $or $or$ls180.v:3675$250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3675$248_Y - connect \B $and$ls180.v:3675$249_Y - connect \Y $or$ls180.v:3675$250_Y - end - attribute \src "ls180.v:3675.37-3675.374" - cell $or $or$ls180.v:3675$252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3675$250_Y - connect \B $and$ls180.v:3675$251_Y - connect \Y $or$ls180.v:3675$252_Y - end - attribute \src "ls180.v:3676.40-3676.207" - cell $or $or$ls180.v:3676$255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3676$253_Y - connect \B $and$ls180.v:3676$254_Y - connect \Y $or$ls180.v:3676$255_Y - end - attribute \src "ls180.v:3676.39-3676.293" - cell $or $or$ls180.v:3676$257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3676$255_Y - connect \B $and$ls180.v:3676$256_Y - connect \Y $or$ls180.v:3676$257_Y - end - attribute \src "ls180.v:3676.38-3676.379" - cell $or $or$ls180.v:3676$259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3676$257_Y - connect \B $and$ls180.v:3676$258_Y - connect \Y $or$ls180.v:3676$259_Y - end - attribute \src "ls180.v:3689.158-3689.332" - cell $or $or$ls180.v:3689$273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3689$272_Y - connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3689$273_Y - end - attribute \src "ls180.v:3689.75-3689.506" - cell $or $or$ls180.v:3689$278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3689$274_Y - connect \B $and$ls180.v:3689$277_Y - connect \Y $or$ls180.v:3689$278_Y - end - attribute \src "ls180.v:3690.158-3690.332" - cell $or $or$ls180.v:3690$286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3690$285_Y - connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3690$286_Y - end - attribute \src "ls180.v:3690.75-3690.506" - cell $or $or$ls180.v:3690$291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3690$287_Y - connect \B $and$ls180.v:3690$290_Y - connect \Y $or$ls180.v:3690$291_Y - end - attribute \src "ls180.v:3691.158-3691.332" - cell $or $or$ls180.v:3691$299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3691$298_Y - connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3691$299_Y - end - attribute \src "ls180.v:3691.75-3691.506" - cell $or $or$ls180.v:3691$304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3691$300_Y - connect \B $and$ls180.v:3691$303_Y - connect \Y $or$ls180.v:3691$304_Y - end - attribute \src "ls180.v:3692.158-3692.332" - cell $or $or$ls180.v:3692$312 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3692$311_Y - connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3692$312_Y - end - attribute \src "ls180.v:3692.75-3692.506" - cell $or $or$ls180.v:3692$317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3692$313_Y - connect \B $and$ls180.v:3692$316_Y - connect \Y $or$ls180.v:3692$317_Y - end - attribute \src "ls180.v:3719.36-3719.104" - cell $or $or$ls180.v:3719$323 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_ready - connect \B $not$ls180.v:3719$322_Y - connect \Y $or$ls180.v:3719$323_Y - end - attribute \src "ls180.v:3722.158-3722.332" - cell $or $or$ls180.v:3722$331 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3722$330_Y - connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3722$331_Y - end - attribute \src "ls180.v:3722.75-3722.506" - cell $or $or$ls180.v:3722$336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3722$332_Y - connect \B $and$ls180.v:3722$335_Y - connect \Y $or$ls180.v:3722$336_Y - end - attribute \src "ls180.v:3723.158-3723.332" - cell $or $or$ls180.v:3723$344 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3723$343_Y - connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3723$344_Y - end - attribute \src "ls180.v:3723.75-3723.506" - cell $or $or$ls180.v:3723$349 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3723$345_Y - connect \B $and$ls180.v:3723$348_Y - connect \Y $or$ls180.v:3723$349_Y - end - attribute \src "ls180.v:3724.158-3724.332" - cell $or $or$ls180.v:3724$357 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3724$356_Y - connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3724$357_Y - end - attribute \src "ls180.v:3724.75-3724.506" - cell $or $or$ls180.v:3724$362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3724$358_Y - connect \B $and$ls180.v:3724$361_Y - connect \Y $or$ls180.v:3724$362_Y - end - attribute \src "ls180.v:3725.158-3725.332" - cell $or $or$ls180.v:3725$370 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3725$369_Y - connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3725$370_Y - end - attribute \src "ls180.v:3725.75-3725.506" - cell $or $or$ls180.v:3725$375 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3725$371_Y - connect \B $and$ls180.v:3725$374_Y - connect \Y $or$ls180.v:3725$375_Y - end - attribute \src "ls180.v:3788.36-3788.104" - cell $or $or$ls180.v:3788$409 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_ready - connect \B $not$ls180.v:3788$408_Y - connect \Y $or$ls180.v:3788$409_Y - end - attribute \src "ls180.v:3809.67-3809.221" - cell $or $or$ls180.v:3809$416 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3809$415_Y - connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:3809$416_Y - end - attribute \src "ls180.v:3817.10-3817.62" - cell $or $or$ls180.v:3817$419 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3817$418_Y - connect \B \main_sdram_max_time1 - connect \Y $or$ls180.v:3817$419_Y - end - attribute \src "ls180.v:3847.67-3847.221" - cell $or $or$ls180.v:3847$425 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3847$424_Y - connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:3847$425_Y - end - attribute \src "ls180.v:3855.10-3855.61" - cell $or $or$ls180.v:3855$428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3855$427_Y - connect \B \main_sdram_max_time0 - connect \Y $or$ls180.v:3855$428_Y - end - attribute \src "ls180.v:3865.91-3865.180" - cell $or $or$ls180.v:3865$432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked0 - connect \B $and$ls180.v:3865$431_Y - connect \Y $or$ls180.v:3865$432_Y - end - attribute \src "ls180.v:3865.90-3865.255" - cell $or $or$ls180.v:3865$435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3865$432_Y - connect \B $and$ls180.v:3865$434_Y - connect \Y $or$ls180.v:3865$435_Y - end - attribute \src "ls180.v:3865.89-3865.330" - cell $or $or$ls180.v:3865$438 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3865$435_Y - connect \B $and$ls180.v:3865$437_Y - connect \Y $or$ls180.v:3865$438_Y - end - attribute \src "ls180.v:3870.91-3870.180" - cell $or $or$ls180.v:3870$448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked1 - connect \B $and$ls180.v:3870$447_Y - connect \Y $or$ls180.v:3870$448_Y - end - attribute \src "ls180.v:3870.90-3870.255" - cell $or $or$ls180.v:3870$451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3870$448_Y - connect \B $and$ls180.v:3870$450_Y - connect \Y $or$ls180.v:3870$451_Y - end - attribute \src "ls180.v:3870.89-3870.330" - cell $or $or$ls180.v:3870$454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3870$451_Y - connect \B $and$ls180.v:3870$453_Y - connect \Y $or$ls180.v:3870$454_Y - end - attribute \src "ls180.v:3875.91-3875.180" - cell $or $or$ls180.v:3875$464 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked2 - connect \B $and$ls180.v:3875$463_Y - connect \Y $or$ls180.v:3875$464_Y - end - attribute \src "ls180.v:3875.90-3875.255" - cell $or $or$ls180.v:3875$467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3875$464_Y - connect \B $and$ls180.v:3875$466_Y - connect \Y $or$ls180.v:3875$467_Y - end - attribute \src "ls180.v:3875.89-3875.330" - cell $or $or$ls180.v:3875$470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3875$467_Y - connect \B $and$ls180.v:3875$469_Y - connect \Y $or$ls180.v:3875$470_Y - end - attribute \src "ls180.v:3880.91-3880.180" - cell $or $or$ls180.v:3880$480 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked3 - connect \B $and$ls180.v:3880$479_Y - connect \Y $or$ls180.v:3880$480_Y - end - attribute \src "ls180.v:3880.90-3880.255" - cell $or $or$ls180.v:3880$483 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3880$480_Y - connect \B $and$ls180.v:3880$482_Y - connect \Y $or$ls180.v:3880$483_Y - end - attribute \src "ls180.v:3880.89-3880.330" - cell $or $or$ls180.v:3880$486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3880$483_Y - connect \B $and$ls180.v:3880$485_Y - connect \Y $or$ls180.v:3880$486_Y - end - attribute \src "ls180.v:3885.132-3885.221" - cell $or $or$ls180.v:3885$497 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked0 - connect \B $and$ls180.v:3885$496_Y - connect \Y $or$ls180.v:3885$497_Y - end - attribute \src "ls180.v:3885.131-3885.296" - cell $or $or$ls180.v:3885$500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3885$497_Y - connect \B $and$ls180.v:3885$499_Y - connect \Y $or$ls180.v:3885$500_Y - end - attribute \src "ls180.v:3885.130-3885.371" - cell $or $or$ls180.v:3885$503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3885$500_Y - connect \B $and$ls180.v:3885$502_Y - connect \Y $or$ls180.v:3885$503_Y - end - attribute \src "ls180.v:3885.34-3885.411" - cell $or $or$ls180.v:3885$508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B $and$ls180.v:3885$507_Y - connect \Y $or$ls180.v:3885$508_Y - end - attribute \src "ls180.v:3885.506-3885.595" - cell $or $or$ls180.v:3885$513 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked1 - connect \B $and$ls180.v:3885$512_Y - connect \Y $or$ls180.v:3885$513_Y - end - attribute \src "ls180.v:3885.505-3885.670" - cell $or $or$ls180.v:3885$516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3885$513_Y - connect \B $and$ls180.v:3885$515_Y - connect \Y $or$ls180.v:3885$516_Y - end - attribute \src "ls180.v:3885.504-3885.745" - cell $or $or$ls180.v:3885$519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3885$516_Y - connect \B $and$ls180.v:3885$518_Y - connect \Y $or$ls180.v:3885$519_Y - end - attribute \src "ls180.v:3885.33-3885.785" - cell $or $or$ls180.v:3885$524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3885$508_Y - connect \B $and$ls180.v:3885$523_Y - connect \Y $or$ls180.v:3885$524_Y - end - attribute \src "ls180.v:3885.880-3885.969" - cell $or $or$ls180.v:3885$529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked2 - connect \B $and$ls180.v:3885$528_Y - connect \Y $or$ls180.v:3885$529_Y - end - attribute \src "ls180.v:3885.879-3885.1044" - cell $or $or$ls180.v:3885$532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3885$529_Y - connect \B $and$ls180.v:3885$531_Y - connect \Y $or$ls180.v:3885$532_Y - end - attribute \src "ls180.v:3885.878-3885.1119" - cell $or $or$ls180.v:3885$535 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3885$532_Y - connect \B $and$ls180.v:3885$534_Y - connect \Y $or$ls180.v:3885$535_Y - end - attribute \src "ls180.v:3885.32-3885.1159" - cell $or $or$ls180.v:3885$540 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3885$524_Y - connect \B $and$ls180.v:3885$539_Y - connect \Y $or$ls180.v:3885$540_Y - end - attribute \src "ls180.v:3885.1254-3885.1343" - cell $or $or$ls180.v:3885$545 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked3 - connect \B $and$ls180.v:3885$544_Y - connect \Y $or$ls180.v:3885$545_Y - end - attribute \src "ls180.v:3885.1253-3885.1418" - cell $or $or$ls180.v:3885$548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3885$545_Y - connect \B $and$ls180.v:3885$547_Y - connect \Y $or$ls180.v:3885$548_Y - end - attribute \src "ls180.v:3885.1252-3885.1493" - cell $or $or$ls180.v:3885$551 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3885$548_Y - connect \B $and$ls180.v:3885$550_Y - connect \Y $or$ls180.v:3885$551_Y - end - attribute \src "ls180.v:3885.31-3885.1533" - cell $or $or$ls180.v:3885$556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3885$540_Y - connect \B $and$ls180.v:3885$555_Y - connect \Y $or$ls180.v:3885$556_Y - end - attribute \src "ls180.v:3948.10-3948.52" - cell $or $or$ls180.v:3948$565 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_ack - connect \B \main_converter_skip - connect \Y $or$ls180.v:3948$565_Y - end - attribute \src "ls180.v:3975.35-3975.74" - cell $or $or$ls180.v:3975$575 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_valid - connect \B \main_cmd_consumed - connect \Y $or$ls180.v:3975$575_Y - end - attribute \src "ls180.v:3976.34-3976.73" - cell $or $or$ls180.v:3976$579 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_valid - connect \B \main_cmd_consumed - connect \Y $or$ls180.v:3976$579_Y - end - attribute \src "ls180.v:3977.48-3977.130" - cell $or $or$ls180.v:3977$585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3977$582_Y - connect \B $and$ls180.v:3977$584_Y - connect \Y $or$ls180.v:3977$585_Y - end - attribute \src "ls180.v:3978.24-3978.87" - cell $or $or$ls180.v:3978$588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3978$587_Y - connect \B \main_cmd_consumed - connect \Y $or$ls180.v:3978$588_Y - end - attribute \src "ls180.v:3979.26-3979.95" - cell $or $or$ls180.v:3979$590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3979$589_Y - connect \B \main_wdata_consumed - connect \Y $or$ls180.v:3979$590_Y - end - attribute \src "ls180.v:4040.37-4040.114" - cell $or $or$ls180.v:4040$600 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_init_pads_out_payload_clk - connect \B \libresocsim_cmdw_pads_out_payload_clk - connect \Y $or$ls180.v:4040$600_Y - end - attribute \src "ls180.v:4040.36-4040.155" - cell $or $or$ls180.v:4040$601 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4040$600_Y - connect \B \libresocsim_cmdr_pads_out_payload_clk - connect \Y $or$ls180.v:4040$601_Y - end - attribute \src "ls180.v:4040.35-4040.197" - cell $or $or$ls180.v:4040$602 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4040$601_Y - connect \B \libresocsim_dataw_pads_out_payload_clk - connect \Y $or$ls180.v:4040$602_Y - end - attribute \src "ls180.v:4040.34-4040.239" - cell $or $or$ls180.v:4040$603 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4040$602_Y - connect \B \libresocsim_datar_pads_out_payload_clk - connect \Y $or$ls180.v:4040$603_Y - end - attribute \src "ls180.v:4041.40-4041.123" - cell $or $or$ls180.v:4041$604 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_init_pads_out_payload_cmd_oe - connect \B \libresocsim_cmdw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4041$604_Y - end - attribute \src "ls180.v:4041.39-4041.167" - cell $or $or$ls180.v:4041$605 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4041$604_Y - connect \B \libresocsim_cmdr_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4041$605_Y - end - attribute \src "ls180.v:4041.38-4041.212" - cell $or $or$ls180.v:4041$606 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4041$605_Y - connect \B \libresocsim_dataw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4041$606_Y - end - attribute \src "ls180.v:4041.37-4041.257" - cell $or $or$ls180.v:4041$607 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4041$606_Y - connect \B \libresocsim_datar_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4041$607_Y - end - attribute \src "ls180.v:4042.39-4042.120" - cell $or $or$ls180.v:4042$608 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_init_pads_out_payload_cmd_o - connect \B \libresocsim_cmdw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4042$608_Y - end - attribute \src "ls180.v:4042.38-4042.163" - cell $or $or$ls180.v:4042$609 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4042$608_Y - connect \B \libresocsim_cmdr_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4042$609_Y - end - attribute \src "ls180.v:4042.37-4042.207" - cell $or $or$ls180.v:4042$610 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4042$609_Y - connect \B \libresocsim_dataw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4042$610_Y - end - attribute \src "ls180.v:4042.36-4042.251" - cell $or $or$ls180.v:4042$611 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4042$610_Y - connect \B \libresocsim_datar_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4042$611_Y - end - attribute \src "ls180.v:4043.41-4043.126" - cell $or $or$ls180.v:4043$612 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_init_pads_out_payload_data_oe - connect \B \libresocsim_cmdw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4043$612_Y - end - attribute \src "ls180.v:4043.40-4043.171" - cell $or $or$ls180.v:4043$613 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4043$612_Y - connect \B \libresocsim_cmdr_pads_out_payload_data_oe - connect \Y $or$ls180.v:4043$613_Y - end - attribute \src "ls180.v:4043.39-4043.217" - cell $or $or$ls180.v:4043$614 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4043$613_Y - connect \B \libresocsim_dataw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4043$614_Y - end - attribute \src "ls180.v:4043.38-4043.263" - cell $or $or$ls180.v:4043$615 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4043$614_Y - connect \B \libresocsim_datar_pads_out_payload_data_oe - connect \Y $or$ls180.v:4043$615_Y - end - attribute \src "ls180.v:4044.40-4044.123" - cell $or $or$ls180.v:4044$616 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \libresocsim_init_pads_out_payload_data_o - connect \B \libresocsim_cmdw_pads_out_payload_data_o - connect \Y $or$ls180.v:4044$616_Y - end - attribute \src "ls180.v:4044.39-4044.167" - cell $or $or$ls180.v:4044$617 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4044$616_Y - connect \B \libresocsim_cmdr_pads_out_payload_data_o - connect \Y $or$ls180.v:4044$617_Y - end - attribute \src "ls180.v:4044.38-4044.212" - cell $or $or$ls180.v:4044$618 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4044$617_Y - connect \B \libresocsim_dataw_pads_out_payload_data_o - connect \Y $or$ls180.v:4044$618_Y - end - attribute \src "ls180.v:4044.37-4044.257" - cell $or $or$ls180.v:4044$619 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4044$618_Y - connect \B \libresocsim_datar_pads_out_payload_data_o - connect \Y $or$ls180.v:4044$619_Y - end - attribute \src "ls180.v:4065.36-4065.83" - cell $or $or$ls180.v:4065$620 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_dataw_stop - connect \B \libresocsim_datar_stop - connect \Y $or$ls180.v:4065$620_Y - end - attribute \src "ls180.v:4219.93-4219.148" - cell $or $or$ls180.v:4219$634 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdr_cmdr_start - connect \B \libresocsim_cmdr_cmdr_run - connect \Y $or$ls180.v:4219$634_Y - end - attribute \src "ls180.v:4236.54-4236.146" - cell $or $or$ls180.v:4236$637 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4236$636_Y - connect \B \libresocsim_cmdr_cmdr_converter_source_ready - connect \Y $or$ls180.v:4236$637_Y - end - attribute \src "ls180.v:4239.48-4239.130" - cell $or $or$ls180.v:4239$640 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4239$639_Y - connect \B \libresocsim_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:4239$640_Y - end - attribute \src "ls180.v:4363.55-4363.149" - cell $or $or$ls180.v:4363$658 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4363$657_Y - connect \B \libresocsim_dataw_crcr_converter_source_ready - connect \Y $or$ls180.v:4363$658_Y - end - attribute \src "ls180.v:4366.49-4366.133" - cell $or $or$ls180.v:4366$661 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4366$660_Y - connect \B \libresocsim_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:4366$661_Y - end - attribute \src "ls180.v:4497.56-4497.152" - cell $or $or$ls180.v:4497$673 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4497$672_Y - connect \B \libresocsim_datar_datar_converter_source_ready - connect \Y $or$ls180.v:4497$673_Y - end - attribute \src "ls180.v:4500.50-4500.136" - cell $or $or$ls180.v:4500$676 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4500$675_Y - connect \B \libresocsim_datar_datar_buf_source_ready - connect \Y $or$ls180.v:4500$676_Y - end - attribute \src "ls180.v:5129.94-5129.179" - cell $or $or$ls180.v:5129$971 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdblock2mem_fifo_syncfifo_writable - connect \B \libresocsim_sdblock2mem_fifo_replace - connect \Y $or$ls180.v:5129$971_Y - end - attribute \src "ls180.v:5140.56-5140.152" - cell $or $or$ls180.v:5140$977 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:5140$976_Y - connect \B \libresocsim_sdblock2mem_converter_source_ready - connect \Y $or$ls180.v:5140$977_Y - end - attribute \src "ls180.v:5337.94-5337.179" - cell $or $or$ls180.v:5337$1002 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdmem2block_fifo_syncfifo_writable - connect \B \libresocsim_sdmem2block_fifo_replace - connect \Y $or$ls180.v:5337$1002_Y - end - attribute \src "ls180.v:5508.33-5508.102" - cell $or $or$ls180.v:5508$1046 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_err - connect \B \main_libresocsim_libresoc_xics_icp_err - connect \Y $or$ls180.v:5508$1046_Y - end - attribute \src "ls180.v:5508.32-5508.144" - cell $or $or$ls180.v:5508$1047 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5508$1046_Y - connect \B \main_libresocsim_libresoc_xics_ics_err - connect \Y $or$ls180.v:5508$1047_Y - end - attribute \src "ls180.v:5508.31-5508.165" - cell $or $or$ls180.v:5508$1048 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5508$1047_Y - connect \B \main_wb_sdram_err - connect \Y $or$ls180.v:5508$1048_Y - end - attribute \src "ls180.v:5508.30-5508.201" - cell $or $or$ls180.v:5508$1049 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5508$1048_Y - connect \B \builder_libresocsim_wishbone_err - connect \Y $or$ls180.v:5508$1049_Y - end - attribute \src "ls180.v:5514.28-5514.97" - cell $or $or$ls180.v:5514$1054 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_ack - connect \B \main_libresocsim_libresoc_xics_icp_ack - connect \Y $or$ls180.v:5514$1054_Y - end - attribute \src "ls180.v:5514.27-5514.139" - cell $or $or$ls180.v:5514$1055 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5514$1054_Y - connect \B \main_libresocsim_libresoc_xics_ics_ack - connect \Y $or$ls180.v:5514$1055_Y - end - attribute \src "ls180.v:5514.26-5514.160" - cell $or $or$ls180.v:5514$1056 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5514$1055_Y - connect \B \main_wb_sdram_ack - connect \Y $or$ls180.v:5514$1056_Y - end - attribute \src "ls180.v:5514.25-5514.196" - cell $or $or$ls180.v:5514$1057 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5514$1056_Y - connect \B \builder_libresocsim_wishbone_ack - connect \Y $or$ls180.v:5514$1057_Y - end - attribute \src "ls180.v:5515.30-5515.169" - cell $or $or$ls180.v:5515$1060 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $and$ls180.v:5515$1058_Y - connect \B $and$ls180.v:5515$1059_Y - connect \Y $or$ls180.v:5515$1060_Y - end - attribute \src "ls180.v:5515.29-5515.246" - cell $or $or$ls180.v:5515$1062 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5515$1060_Y - connect \B $and$ls180.v:5515$1061_Y - connect \Y $or$ls180.v:5515$1062_Y - end - attribute \src "ls180.v:5515.28-5515.302" - cell $or $or$ls180.v:5515$1064 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5515$1062_Y - connect \B $and$ls180.v:5515$1063_Y - connect \Y $or$ls180.v:5515$1064_Y - end - attribute \src "ls180.v:5515.27-5515.373" - cell $or $or$ls180.v:5515$1066 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5515$1064_Y - connect \B $and$ls180.v:5515$1065_Y - connect \Y $or$ls180.v:5515$1066_Y - end - attribute \src "ls180.v:6161.53-6161.122" - cell $or $or$ls180.v:6161$2042 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A \builder_interface0_bank_bus_dat_r - connect \B \builder_interface1_bank_bus_dat_r - connect \Y $or$ls180.v:6161$2042_Y - end - attribute \src "ls180.v:6161.52-6161.159" - cell $or $or$ls180.v:6161$2043 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6161$2042_Y - connect \B \builder_interface2_bank_bus_dat_r - connect \Y $or$ls180.v:6161$2043_Y - end - attribute \src "ls180.v:6161.51-6161.196" - cell $or $or$ls180.v:6161$2044 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6161$2043_Y - connect \B \builder_interface3_bank_bus_dat_r - connect \Y $or$ls180.v:6161$2044_Y - end - attribute \src "ls180.v:6161.50-6161.233" - cell $or $or$ls180.v:6161$2045 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6161$2044_Y - connect \B \builder_interface4_bank_bus_dat_r - connect \Y $or$ls180.v:6161$2045_Y - end - attribute \src "ls180.v:6161.49-6161.270" - cell $or $or$ls180.v:6161$2046 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6161$2045_Y - connect \B \builder_interface5_bank_bus_dat_r - connect \Y $or$ls180.v:6161$2046_Y - end - attribute \src "ls180.v:6161.48-6161.307" - cell $or $or$ls180.v:6161$2047 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6161$2046_Y - connect \B \builder_interface6_bank_bus_dat_r - connect \Y $or$ls180.v:6161$2047_Y - end - attribute \src "ls180.v:6161.47-6161.344" - cell $or $or$ls180.v:6161$2048 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6161$2047_Y - connect \B \builder_interface7_bank_bus_dat_r - connect \Y $or$ls180.v:6161$2048_Y - end - attribute \src "ls180.v:6161.46-6161.381" - cell $or $or$ls180.v:6161$2049 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6161$2048_Y - connect \B \builder_interface8_bank_bus_dat_r - connect \Y $or$ls180.v:6161$2049_Y - end - attribute \src "ls180.v:6161.45-6161.418" - cell $or $or$ls180.v:6161$2050 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6161$2049_Y - connect \B \builder_interface9_bank_bus_dat_r - connect \Y $or$ls180.v:6161$2050_Y - end - attribute \src "ls180.v:6161.44-6161.456" - cell $or $or$ls180.v:6161$2051 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6161$2050_Y - connect \B \builder_interface10_bank_bus_dat_r - connect \Y $or$ls180.v:6161$2051_Y - end - attribute \src "ls180.v:6161.43-6161.494" - cell $or $or$ls180.v:6161$2052 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6161$2051_Y - connect \B \builder_interface11_bank_bus_dat_r - connect \Y $or$ls180.v:6161$2052_Y - end - attribute \src "ls180.v:6161.42-6161.532" - cell $or $or$ls180.v:6161$2053 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6161$2052_Y - connect \B \builder_interface12_bank_bus_dat_r - connect \Y $or$ls180.v:6161$2053_Y - end - attribute \src "ls180.v:6488.90-6488.179" - cell $or $or$ls180.v:6488$2078 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked0 - connect \B $and$ls180.v:6488$2077_Y - connect \Y $or$ls180.v:6488$2078_Y - end - attribute \src "ls180.v:6488.89-6488.254" - cell $or $or$ls180.v:6488$2081 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6488$2078_Y - connect \B $and$ls180.v:6488$2080_Y - connect \Y $or$ls180.v:6488$2081_Y - end - attribute \src "ls180.v:6488.88-6488.329" - cell $or $or$ls180.v:6488$2084 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6488$2081_Y - connect \B $and$ls180.v:6488$2083_Y - connect \Y $or$ls180.v:6488$2084_Y - end - attribute \src "ls180.v:6512.90-6512.179" - cell $or $or$ls180.v:6512$2094 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked1 - connect \B $and$ls180.v:6512$2093_Y - connect \Y $or$ls180.v:6512$2094_Y - end - attribute \src "ls180.v:6512.89-6512.254" - cell $or $or$ls180.v:6512$2097 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6512$2094_Y - connect \B $and$ls180.v:6512$2096_Y - connect \Y $or$ls180.v:6512$2097_Y - end - attribute \src "ls180.v:6512.88-6512.329" - cell $or $or$ls180.v:6512$2100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6512$2097_Y - connect \B $and$ls180.v:6512$2099_Y - connect \Y $or$ls180.v:6512$2100_Y - end - attribute \src "ls180.v:6536.90-6536.179" - cell $or $or$ls180.v:6536$2110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked2 - connect \B $and$ls180.v:6536$2109_Y - connect \Y $or$ls180.v:6536$2110_Y - end - attribute \src "ls180.v:6536.89-6536.254" - cell $or $or$ls180.v:6536$2113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6536$2110_Y - connect \B $and$ls180.v:6536$2112_Y - connect \Y $or$ls180.v:6536$2113_Y - end - attribute \src "ls180.v:6536.88-6536.329" - cell $or $or$ls180.v:6536$2116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6536$2113_Y - connect \B $and$ls180.v:6536$2115_Y - connect \Y $or$ls180.v:6536$2116_Y - end - attribute \src "ls180.v:6560.90-6560.179" - cell $or $or$ls180.v:6560$2126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked3 - connect \B $and$ls180.v:6560$2125_Y - connect \Y $or$ls180.v:6560$2126_Y - end - attribute \src "ls180.v:6560.89-6560.254" - cell $or $or$ls180.v:6560$2129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6560$2126_Y - connect \B $and$ls180.v:6560$2128_Y - connect \Y $or$ls180.v:6560$2129_Y - end - attribute \src "ls180.v:6560.88-6560.329" - cell $or $or$ls180.v:6560$2132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6560$2129_Y - connect \B $and$ls180.v:6560$2131_Y - connect \Y $or$ls180.v:6560$2132_Y - end - attribute \src "ls180.v:7057.7-7057.93" - cell $or $or$ls180.v:7057$2188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface0_converted_interface_ack - connect \B \main_libresocsim_converter0_skip - connect \Y $or$ls180.v:7057$2188_Y - end - attribute \src "ls180.v:7068.7-7068.93" - cell $or $or$ls180.v:7068$2189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface1_converted_interface_ack - connect \B \main_libresocsim_converter1_skip - connect \Y $or$ls180.v:7068$2189_Y - end - attribute \src "ls180.v:7329.7-7329.107" - cell $or $or$ls180.v:7329$2267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7329$2266_Y - connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:7329$2267_Y - end - attribute \src "ls180.v:7375.7-7375.107" - cell $or $or$ls180.v:7375$2283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7375$2282_Y - connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:7375$2283_Y - end - attribute \src "ls180.v:7421.7-7421.107" - cell $or $or$ls180.v:7421$2299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7421$2298_Y - connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:7421$2299_Y - end - attribute \src "ls180.v:7467.7-7467.107" - cell $or $or$ls180.v:7467$2315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7467$2314_Y - connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:7467$2315_Y - end - attribute \src "ls180.v:7655.40-7655.125" - cell $or $or$ls180.v:7655$2336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B $and$ls180.v:7655$2335_Y - connect \Y $or$ls180.v:7655$2336_Y - end - attribute \src "ls180.v:7655.39-7655.207" - cell $or $or$ls180.v:7655$2339 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7655$2336_Y - connect \B $and$ls180.v:7655$2338_Y - connect \Y $or$ls180.v:7655$2339_Y - end - attribute \src "ls180.v:7655.38-7655.289" - cell $or $or$ls180.v:7655$2342 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7655$2339_Y - connect \B $and$ls180.v:7655$2341_Y - connect \Y $or$ls180.v:7655$2342_Y - end - attribute \src "ls180.v:7655.37-7655.371" - cell $or $or$ls180.v:7655$2345 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7655$2342_Y - connect \B $and$ls180.v:7655$2344_Y - connect \Y $or$ls180.v:7655$2345_Y - end - attribute \src "ls180.v:7656.41-7656.126" - cell $or $or$ls180.v:7656$2348 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B $and$ls180.v:7656$2347_Y - connect \Y $or$ls180.v:7656$2348_Y - end - attribute \src "ls180.v:7656.40-7656.208" - cell $or $or$ls180.v:7656$2351 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7656$2348_Y - connect \B $and$ls180.v:7656$2350_Y - connect \Y $or$ls180.v:7656$2351_Y - end - attribute \src "ls180.v:7656.39-7656.290" - cell $or $or$ls180.v:7656$2354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7656$2351_Y - connect \B $and$ls180.v:7656$2353_Y - connect \Y $or$ls180.v:7656$2354_Y - end - attribute \src "ls180.v:7656.38-7656.372" - cell $or $or$ls180.v:7656$2357 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7656$2354_Y - connect \B $and$ls180.v:7656$2356_Y - connect \Y $or$ls180.v:7656$2357_Y - end - attribute \src "ls180.v:7660.7-7660.49" - cell $or $or$ls180.v:7660$2358 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_ack - connect \B \main_converter_skip - connect \Y $or$ls180.v:7660$2358_Y - end - attribute \src "ls180.v:7691.22-7691.52" - cell $or $or$ls180.v:7691$2364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7691$2362_Y - connect \B $not$ls180.v:7691$2363_Y - connect \Y $or$ls180.v:7691$2364_Y - end - attribute \src "ls180.v:7731.33-7731.88" - cell $or $or$ls180.v:7731$2368 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdr_cmdr_start - connect \B \libresocsim_cmdr_cmdr_run - connect \Y $or$ls180.v:7731$2368_Y - end - attribute \src "ls180.v:7737.8-7737.99" - cell $or $or$ls180.v:7737$2370 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7737$2369_Y - connect \B \libresocsim_cmdr_cmdr_converter_sink_last - connect \Y $or$ls180.v:7737$2370_Y - end - attribute \src "ls180.v:7754.53-7754.142" - cell $or $or$ls180.v:7754$2375 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdr_cmdr_converter_sink_first - connect \B \libresocsim_cmdr_cmdr_converter_source_first - connect \Y $or$ls180.v:7754$2375_Y - end - attribute \src "ls180.v:7755.52-7755.139" - cell $or $or$ls180.v:7755$2376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cmdr_cmdr_converter_sink_last - connect \B \libresocsim_cmdr_cmdr_converter_source_last - connect \Y $or$ls180.v:7755$2376_Y - end - attribute \src "ls180.v:7789.7-7789.89" - cell $or $or$ls180.v:7789$2379 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7789$2378_Y - connect \B \libresocsim_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:7789$2379_Y - end - attribute \src "ls180.v:7812.34-7812.91" - cell $or $or$ls180.v:7812$2380 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_dataw_crcr_start - connect \B \libresocsim_dataw_crcr_run - connect \Y $or$ls180.v:7812$2380_Y - end - attribute \src "ls180.v:7818.8-7818.101" - cell $or $or$ls180.v:7818$2382 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7818$2381_Y - connect \B \libresocsim_dataw_crcr_converter_sink_last - connect \Y $or$ls180.v:7818$2382_Y - end - attribute \src "ls180.v:7835.54-7835.145" - cell $or $or$ls180.v:7835$2387 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_dataw_crcr_converter_sink_first - connect \B \libresocsim_dataw_crcr_converter_source_first - connect \Y $or$ls180.v:7835$2387_Y - end - attribute \src "ls180.v:7836.53-7836.142" - cell $or $or$ls180.v:7836$2388 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_dataw_crcr_converter_sink_last - connect \B \libresocsim_dataw_crcr_converter_source_last - connect \Y $or$ls180.v:7836$2388_Y - end - attribute \src "ls180.v:7870.7-7870.91" - cell $or $or$ls180.v:7870$2391 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7870$2390_Y - connect \B \libresocsim_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:7870$2391_Y - end - attribute \src "ls180.v:7891.35-7891.94" - cell $or $or$ls180.v:7891$2392 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_datar_datar_start - connect \B \libresocsim_datar_datar_run - connect \Y $or$ls180.v:7891$2392_Y - end - attribute \src "ls180.v:7897.8-7897.103" - cell $or $or$ls180.v:7897$2394 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7897$2393_Y - connect \B \libresocsim_datar_datar_converter_sink_last - connect \Y $or$ls180.v:7897$2394_Y - end - attribute \src "ls180.v:7914.55-7914.148" - cell $or $or$ls180.v:7914$2399 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_datar_datar_converter_sink_first - connect \B \libresocsim_datar_datar_converter_source_first - connect \Y $or$ls180.v:7914$2399_Y - end - attribute \src "ls180.v:7915.54-7915.145" - cell $or $or$ls180.v:7915$2400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_datar_datar_converter_sink_last - connect \B \libresocsim_datar_datar_converter_source_last - connect \Y $or$ls180.v:7915$2400_Y - end - attribute \src "ls180.v:7931.7-7931.93" - cell $or $or$ls180.v:7931$2403 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7931$2402_Y - connect \B \libresocsim_datar_datar_buf_source_ready - connect \Y $or$ls180.v:7931$2403_Y - end - attribute \src "ls180.v:8120.8-8120.103" - cell $or $or$ls180.v:8120$2427 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8120$2426_Y - connect \B \libresocsim_sdblock2mem_converter_sink_last - connect \Y $or$ls180.v:8120$2427_Y - end - attribute \src "ls180.v:8137.55-8137.148" - cell $or $or$ls180.v:8137$2432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdblock2mem_converter_sink_first - connect \B \libresocsim_sdblock2mem_converter_source_first - connect \Y $or$ls180.v:8137$2432_Y - end - attribute \src "ls180.v:8138.54-8138.145" - cell $or $or$ls180.v:8138$2433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdblock2mem_converter_sink_last - connect \B \libresocsim_sdblock2mem_converter_source_last - connect \Y $or$ls180.v:8138$2433_Y - end - attribute \src "ls180.v:8211.21-8211.65" - cell $or $or$ls180.v:8211$2451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8211$2449_Y - connect \B $not$ls180.v:8211$2450_Y - connect \Y $or$ls180.v:8211$2451_Y - end - attribute \src "ls180.v:9536.8-9536.49" - cell $or $or$ls180.v:9536$2529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sys_rst - connect \B \main_libresocsim_libresoc_reset - connect \Y $or$ls180.v:9536$2529_Y - end - attribute \src "ls180.v:3059.46-3059.94" - cell $sshl $sshl$ls180.v:3059$112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 - connect \A \main_sdram_bankmachine0_auto_precharge - connect \B 4'1010 - connect \Y $sshl$ls180.v:3059$112_Y - end - attribute \src "ls180.v:3216.46-3216.94" - cell $sshl $sshl$ls180.v:3216$142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 - connect \A \main_sdram_bankmachine1_auto_precharge - connect \B 4'1010 - connect \Y $sshl$ls180.v:3216$142_Y - end - attribute \src "ls180.v:3373.46-3373.94" - cell $sshl $sshl$ls180.v:3373$172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 - connect \A \main_sdram_bankmachine2_auto_precharge - connect \B 4'1010 - connect \Y $sshl$ls180.v:3373$172_Y - end - attribute \src "ls180.v:3530.46-3530.94" - cell $sshl $sshl$ls180.v:3530$202 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 - connect \A \main_sdram_bankmachine3_auto_precharge - connect \B 4'1010 - connect \Y $sshl$ls180.v:3530$202_Y - end - attribute \src "ls180.v:2798.48-2798.92" - cell $sub $sub$ls180.v:2798$71 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_libresocsim_uart_tx_fifo_produce - connect \B 1'1 - connect \Y $sub$ls180.v:2798$71_Y - end - attribute \src "ls180.v:2828.48-2828.92" - cell $sub $sub$ls180.v:2828$82 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_libresocsim_uart_rx_fifo_produce - connect \B 1'1 - connect \Y $sub$ls180.v:2828$82_Y - end - attribute \src "ls180.v:3090.63-3090.122" - cell $sub $sub$ls180.v:3090$125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $sub$ls180.v:3090$125_Y - end - attribute \src "ls180.v:3247.63-3247.122" - cell $sub $sub$ls180.v:3247$155 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $sub$ls180.v:3247$155_Y - end - attribute \src "ls180.v:3404.63-3404.122" - cell $sub $sub$ls180.v:3404$185 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $sub$ls180.v:3404$185_Y - end - attribute \src "ls180.v:3561.63-3561.122" - cell $sub $sub$ls180.v:3561$215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $sub$ls180.v:3561$215_Y - end - attribute \src "ls180.v:3967.38-3967.75" - cell $sub $sub$ls180.v:3967$569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 30 - parameter \B_SIGNED 0 - parameter \B_WIDTH 31 - parameter \Y_WIDTH 31 - connect \A \main_litedram_wb_adr - connect \B 31'1001000000000000000000000000000 - connect \Y $sub$ls180.v:3967$569_Y - end - attribute \src "ls180.v:3988.47-3988.77" - cell $sub $sub$ls180.v:3988$592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 15 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_clk_divider0 [15:1] - connect \B 1'1 - connect \Y $sub$ls180.v:3988$592_Y - end - attribute \src "ls180.v:3989.47-3989.71" - cell $sub $sub$ls180.v:3989$594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_clk_divider0 - connect \B 1'1 - connect \Y $sub$ls180.v:3989$594_Y - end - attribute \src "ls180.v:4016.25-4016.44" - cell $sub $sub$ls180.v:4016$598 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_length0 - connect \B 1'1 - connect \Y $sub$ls180.v:4016$598_Y - end - attribute \src "ls180.v:4266.61-4266.92" - cell $sub $sub$ls180.v:4266$642 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \libresocsim_cmdr_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:4266$642_Y - end - attribute \src "ls180.v:4277.64-4277.107" - cell $sub $sub$ls180.v:4277$644 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \libresocsim_cmdr_sink_payload_length - connect \B 1'1 - connect \Y $sub$ls180.v:4277$644_Y - end - attribute \src "ls180.v:4294.61-4294.92" - cell $sub $sub$ls180.v:4294$648 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \libresocsim_cmdr_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:4294$648_Y - end - attribute \src "ls180.v:4523.63-4523.95" - cell $sub $sub$ls180.v:4523$678 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \libresocsim_datar_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:4523$678_Y - end - attribute \src "ls180.v:4528.63-4528.95" - cell $sub $sub$ls180.v:4528$679 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \libresocsim_datar_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:4528$679_Y - end - attribute \src "ls180.v:4539.66-4539.125" - cell $sub $sub$ls180.v:4539$682 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 10 - connect \A $add$ls180.v:4539$681_Y - connect \B 1'1 - connect \Y $sub$ls180.v:4539$682_Y - end - attribute \src "ls180.v:4560.63-4560.95" - cell $sub $sub$ls180.v:4560$685 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \libresocsim_datar_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:4560$685_Y - end - attribute \src "ls180.v:5022.44-5022.89" - cell $sub $sub$ls180.v:5022$958 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \libresocsim_sdcore_block_count_storage - connect \B 1'1 - connect \Y $sub$ls180.v:5022$958_Y - end - attribute \src "ls180.v:5037.70-5037.115" - cell $sub $sub$ls180.v:5037$961 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \libresocsim_sdcore_block_count_storage - connect \B 1'1 - connect \Y $sub$ls180.v:5037$961_Y - end - attribute \src "ls180.v:5048.46-5048.91" - cell $sub $sub$ls180.v:5048$966 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \libresocsim_sdcore_block_count_storage - connect \B 1'1 - connect \Y $sub$ls180.v:5048$966_Y - end - attribute \src "ls180.v:5123.47-5123.90" - cell $sub $sub$ls180.v:5123$970 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \libresocsim_sdblock2mem_fifo_produce - connect \B 1'1 - connect \Y $sub$ls180.v:5123$970_Y - end - attribute \src "ls180.v:5172.63-5172.118" - cell $sub $sub$ls180.v:5172$984 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \libresocsim_sdblock2mem_wishbonedmawriter_length - connect \B 1'1 - connect \Y $sub$ls180.v:5172$984_Y - end - attribute \src "ls180.v:5262.85-5262.126" - cell $sub $sub$ls180.v:5262$990 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \libresocsim_sdmem2block_dma_length - connect \B 1'1 - connect \Y $sub$ls180.v:5262$990_Y - end - attribute \src "ls180.v:5331.47-5331.90" - cell $sub $sub$ls180.v:5331$1001 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \libresocsim_sdmem2block_fifo_produce - connect \B 1'1 - connect \Y $sub$ls180.v:5331$1001_Y - end - attribute \src "ls180.v:5350.61-5350.98" - cell $sub $sub$ls180.v:5350$1007 - parameter \A_SIGNED 0 - parameter \A_WIDTH 15 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \libresocsim_clk_divider0 [15:1] - connect \B 1'1 - connect \Y $sub$ls180.v:5350$1007_Y - end - attribute \src "ls180.v:5351.61-5351.92" - cell $sub $sub$ls180.v:5351$1009 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \libresocsim_clk_divider0 - connect \B 1'1 - connect \Y $sub$ls180.v:5351$1009_Y - end - attribute \src "ls180.v:5379.32-5379.58" - cell $sub $sub$ls180.v:5379$1013 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \libresocsim_length0 - connect \B 1'1 - connect \Y $sub$ls180.v:5379$1013_Y - end - attribute \src "ls180.v:7181.45-7181.88" - cell $sub $sub$ls180.v:7181$2225 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_libresocsim_uart_tx_fifo_level0 - connect \B 1'1 - connect \Y $sub$ls180.v:7181$2225_Y - end - attribute \src "ls180.v:7203.45-7203.88" - cell $sub $sub$ls180.v:7203$2236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_libresocsim_uart_rx_fifo_level0 - connect \B 1'1 - connect \Y $sub$ls180.v:7203$2236_Y - end - attribute \src "ls180.v:7224.37-7224.72" - cell $sub $sub$ls180.v:7224$2238 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_libresocsim_timer_value - connect \B 1'1 - connect \Y $sub$ls180.v:7224$2238_Y - end - attribute \src "ls180.v:7245.31-7245.61" - cell $sub $sub$ls180.v:7245$2243 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 10 - connect \A \main_sdram_timer_count1 - connect \B 1'1 - connect \Y $sub$ls180.v:7245$2243_Y - end - attribute \src "ls180.v:7251.34-7251.67" - cell $sub $sub$ls180.v:7251$2244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_postponer_count - connect \B 1'1 - connect \Y $sub$ls180.v:7251$2244_Y - end - attribute \src "ls180.v:7262.36-7262.69" - cell $sub $sub$ls180.v:7262$2247 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_count - connect \B 1'1 - connect \Y $sub$ls180.v:7262$2247_Y - end - attribute \src "ls180.v:7326.59-7326.116" - cell $sub $sub$ls180.v:7326$2265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $sub$ls180.v:7326$2265_Y - end - attribute \src "ls180.v:7345.46-7345.90" - cell $sub $sub$ls180.v:7345$2269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine0_twtpcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7345$2269_Y - end - attribute \src "ls180.v:7372.59-7372.116" - cell $sub $sub$ls180.v:7372$2281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $sub$ls180.v:7372$2281_Y - end - attribute \src "ls180.v:7391.46-7391.90" - cell $sub $sub$ls180.v:7391$2285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine1_twtpcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7391$2285_Y - end - attribute \src "ls180.v:7418.59-7418.116" - cell $sub $sub$ls180.v:7418$2297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $sub$ls180.v:7418$2297_Y - end - attribute \src "ls180.v:7437.46-7437.90" - cell $sub $sub$ls180.v:7437$2301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine2_twtpcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7437$2301_Y - end - attribute \src "ls180.v:7464.59-7464.116" - cell $sub $sub$ls180.v:7464$2313 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $sub$ls180.v:7464$2313_Y - end - attribute \src "ls180.v:7483.46-7483.90" - cell $sub $sub$ls180.v:7483$2317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine3_twtpcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7483$2317_Y - end - attribute \src "ls180.v:7494.25-7494.48" - cell $sub $sub$ls180.v:7494$2321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdram_time0 - connect \B 1'1 - connect \Y $sub$ls180.v:7494$2321_Y - end - attribute \src "ls180.v:7501.25-7501.48" - cell $sub $sub$ls180.v:7501$2324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_time1 - connect \B 1'1 - connect \Y $sub$ls180.v:7501$2324_Y - end - attribute \src "ls180.v:7633.33-7633.64" - cell $sub $sub$ls180.v:7633$2329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_tccdcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7633$2329_Y - end - attribute \src "ls180.v:7648.33-7648.64" - cell $sub $sub$ls180.v:7648$2332 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_twtrcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7648$2332_Y - end - attribute \src "ls180.v:7700.22-7700.42" - cell $sub $sub$ls180.v:7700$2365 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_mosi_sel - connect \B 1'1 - connect \Y $sub$ls180.v:7700$2365_Y - end - attribute \src "ls180.v:8113.43-8113.84" - cell $sub $sub$ls180.v:8113$2425 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \libresocsim_sdblock2mem_fifo_level - connect \B 1'1 - connect \Y $sub$ls180.v:8113$2425_Y - end - attribute \src "ls180.v:8199.43-8199.84" - cell $sub $sub$ls180.v:8199$2447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \libresocsim_sdmem2block_fifo_level - connect \B 1'1 - connect \Y $sub$ls180.v:8199$2447_Y - end - attribute \src "ls180.v:8220.29-8220.56" - cell $sub $sub$ls180.v:8220$2452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \libresocsim_mosi_sel - connect \B 1'1 - connect \Y $sub$ls180.v:8220$2452_Y - end - attribute \src "ls180.v:8312.22-8312.42" - cell $sub $sub$ls180.v:8312$2458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 20 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 20 - connect \A \builder_count - connect \B 1'1 - connect \Y $sub$ls180.v:8312$2458_Y - end - attribute \src "ls180.v:9566.22-9566.92" - cell $mux $ternary$ls180.v:9566$2530 - parameter \WIDTH 1 - connect \A 1'z - connect \B \builder_inferedsdrtristate0__o - connect \S \builder_inferedsdrtristate0_oe - connect \Y $ternary$ls180.v:9566$2530_Y - end - attribute \src "ls180.v:9569.22-9569.92" - cell $mux $ternary$ls180.v:9569$2531 - parameter \WIDTH 1 - connect \A 1'z - connect \B \builder_inferedsdrtristate1__o - connect \S \builder_inferedsdrtristate1_oe - connect \Y $ternary$ls180.v:9569$2531_Y - end - attribute \src "ls180.v:9572.22-9572.92" - cell $mux $ternary$ls180.v:9572$2532 - parameter \WIDTH 1 - connect \A 1'z - connect \B \builder_inferedsdrtristate2__o - connect \S \builder_inferedsdrtristate2_oe - connect \Y $ternary$ls180.v:9572$2532_Y - end - attribute \src "ls180.v:9575.22-9575.92" - cell $mux $ternary$ls180.v:9575$2533 - parameter \WIDTH 1 - connect \A 1'z - connect \B \builder_inferedsdrtristate3__o - connect \S \builder_inferedsdrtristate3_oe - connect \Y $ternary$ls180.v:9575$2533_Y - end - attribute \src "ls180.v:9578.22-9578.92" - cell $mux $ternary$ls180.v:9578$2534 - parameter \WIDTH 1 - connect \A 1'z - connect \B \builder_inferedsdrtristate4__o - connect \S \builder_inferedsdrtristate4_oe - connect \Y $ternary$ls180.v:9578$2534_Y - end - attribute \src "ls180.v:9581.22-9581.92" - cell $mux $ternary$ls180.v:9581$2535 - parameter \WIDTH 1 - connect \A 1'z - connect \B \builder_inferedsdrtristate5__o - connect \S \builder_inferedsdrtristate5_oe - connect \Y $ternary$ls180.v:9581$2535_Y - end - attribute \src "ls180.v:9584.22-9584.92" - cell $mux $ternary$ls180.v:9584$2536 - parameter \WIDTH 1 - connect \A 1'z - connect \B \builder_inferedsdrtristate6__o - connect \S \builder_inferedsdrtristate6_oe - connect \Y $ternary$ls180.v:9584$2536_Y - end - attribute \src "ls180.v:9587.22-9587.92" - cell $mux $ternary$ls180.v:9587$2537 - parameter \WIDTH 1 - connect \A 1'z - connect \B \builder_inferedsdrtristate7__o - connect \S \builder_inferedsdrtristate7_oe - connect \Y $ternary$ls180.v:9587$2537_Y - end - attribute \src "ls180.v:9590.22-9590.92" - cell $mux $ternary$ls180.v:9590$2538 - parameter \WIDTH 1 - connect \A 1'z - connect \B \builder_inferedsdrtristate8__o - connect \S \builder_inferedsdrtristate8_oe - connect \Y $ternary$ls180.v:9590$2538_Y - end - attribute \src "ls180.v:9593.22-9593.92" - cell $mux $ternary$ls180.v:9593$2539 - parameter \WIDTH 1 - connect \A 1'z - connect \B \builder_inferedsdrtristate9__o - connect \S \builder_inferedsdrtristate9_oe - connect \Y $ternary$ls180.v:9593$2539_Y - end - attribute \src "ls180.v:9596.23-9596.95" - cell $mux $ternary$ls180.v:9596$2540 - parameter \WIDTH 1 - connect \A 1'z - connect \B \builder_inferedsdrtristate10__o - connect \S \builder_inferedsdrtristate10_oe - connect \Y $ternary$ls180.v:9596$2540_Y - end - attribute \src "ls180.v:9599.23-9599.95" - cell $mux $ternary$ls180.v:9599$2541 - parameter \WIDTH 1 - connect \A 1'z - connect \B \builder_inferedsdrtristate11__o - connect \S \builder_inferedsdrtristate11_oe - connect \Y $ternary$ls180.v:9599$2541_Y - end - attribute \src "ls180.v:9602.23-9602.95" - cell $mux $ternary$ls180.v:9602$2542 - parameter \WIDTH 1 - connect \A 1'z - connect \B \builder_inferedsdrtristate12__o - connect \S \builder_inferedsdrtristate12_oe - connect \Y $ternary$ls180.v:9602$2542_Y - end - attribute \src "ls180.v:9605.23-9605.95" - cell $mux $ternary$ls180.v:9605$2543 - parameter \WIDTH 1 - connect \A 1'z - connect \B \builder_inferedsdrtristate13__o - connect \S \builder_inferedsdrtristate13_oe - connect \Y $ternary$ls180.v:9605$2543_Y - end - attribute \src "ls180.v:9608.23-9608.95" - cell $mux $ternary$ls180.v:9608$2544 - parameter \WIDTH 1 - connect \A 1'z - connect \B \builder_inferedsdrtristate14__o - connect \S \builder_inferedsdrtristate14_oe - connect \Y $ternary$ls180.v:9608$2544_Y - end - attribute \src "ls180.v:9611.23-9611.95" - cell $mux $ternary$ls180.v:9611$2545 - parameter \WIDTH 1 - connect \A 1'z - connect \B \builder_inferedsdrtristate15__o - connect \S \builder_inferedsdrtristate15_oe - connect \Y $ternary$ls180.v:9611$2545_Y - end - attribute \src "ls180.v:9614.21-9614.93" - cell $mux $ternary$ls180.v:9614$2546 - parameter \WIDTH 1 - connect \A 1'z - connect \B \builder_inferedsdrtristate16__o - connect \S \builder_inferedsdrtristate16_oe - connect \Y $ternary$ls180.v:9614$2546_Y - end - attribute \src "ls180.v:9617.25-9617.97" - cell $mux $ternary$ls180.v:9617$2547 - parameter \WIDTH 1 - connect \A 1'z - connect \B \builder_inferedsdrtristate17__o - connect \S \builder_inferedsdrtristate17_oe - connect \Y $ternary$ls180.v:9617$2547_Y - end - attribute \src "ls180.v:9620.25-9620.97" - cell $mux $ternary$ls180.v:9620$2548 - parameter \WIDTH 1 - connect \A 1'z - connect \B \builder_inferedsdrtristate18__o - connect \S \builder_inferedsdrtristate18_oe - connect \Y $ternary$ls180.v:9620$2548_Y - end - attribute \src "ls180.v:9623.25-9623.97" - cell $mux $ternary$ls180.v:9623$2549 - parameter \WIDTH 1 - connect \A 1'z - connect \B \builder_inferedsdrtristate19__o - connect \S \builder_inferedsdrtristate19_oe - connect \Y $ternary$ls180.v:9623$2549_Y - end - attribute \src "ls180.v:9626.25-9626.97" - cell $mux $ternary$ls180.v:9626$2550 - parameter \WIDTH 1 - connect \A 1'z - connect \B \builder_inferedsdrtristate20__o - connect \S \builder_inferedsdrtristate20_oe - connect \Y $ternary$ls180.v:9626$2550_Y - end - attribute \src "ls180.v:4620.416-4620.502" - cell $xor $xor$ls180.v:4620$692 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [39] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:4620$692_Y - end - attribute \src "ls180.v:4620.235-4620.321" - cell $xor $xor$ls180.v:4620$693 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [39] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:4620$693_Y - end - attribute \src "ls180.v:4620.188-4620.322" - cell $xor $xor$ls180.v:4620$694 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg0 [2] - connect \B $xor$ls180.v:4620$693_Y - connect \Y $xor$ls180.v:4620$694_Y - end - attribute \src "ls180.v:4621.416-4621.502" - cell $xor $xor$ls180.v:4621$695 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [38] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:4621$695_Y - end - attribute \src "ls180.v:4621.235-4621.321" - cell $xor $xor$ls180.v:4621$696 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [38] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:4621$696_Y - end - attribute \src "ls180.v:4621.188-4621.322" - cell $xor $xor$ls180.v:4621$697 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg1 [2] - connect \B $xor$ls180.v:4621$696_Y - connect \Y $xor$ls180.v:4621$697_Y - end - attribute \src "ls180.v:4622.416-4622.502" - cell $xor $xor$ls180.v:4622$698 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [37] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:4622$698_Y - end - attribute \src "ls180.v:4622.235-4622.321" - cell $xor $xor$ls180.v:4622$699 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [37] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:4622$699_Y - end - attribute \src "ls180.v:4622.188-4622.322" - cell $xor $xor$ls180.v:4622$700 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg2 [2] - connect \B $xor$ls180.v:4622$699_Y - connect \Y $xor$ls180.v:4622$700_Y - end - attribute \src "ls180.v:4623.416-4623.502" - cell $xor $xor$ls180.v:4623$701 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [36] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:4623$701_Y - end - attribute \src "ls180.v:4623.235-4623.321" - cell $xor $xor$ls180.v:4623$702 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [36] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:4623$702_Y - end - attribute \src "ls180.v:4623.188-4623.322" - cell $xor $xor$ls180.v:4623$703 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg3 [2] - connect \B $xor$ls180.v:4623$702_Y - connect \Y $xor$ls180.v:4623$703_Y - end - attribute \src "ls180.v:4624.416-4624.502" - cell $xor $xor$ls180.v:4624$704 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [35] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:4624$704_Y - end - attribute \src "ls180.v:4624.235-4624.321" - cell $xor $xor$ls180.v:4624$705 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [35] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:4624$705_Y - end - attribute \src "ls180.v:4624.188-4624.322" - cell $xor $xor$ls180.v:4624$706 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg4 [2] - connect \B $xor$ls180.v:4624$705_Y - connect \Y $xor$ls180.v:4624$706_Y - end - attribute \src "ls180.v:4625.416-4625.502" - cell $xor $xor$ls180.v:4625$707 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [34] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:4625$707_Y - end - attribute \src "ls180.v:4625.235-4625.321" - cell $xor $xor$ls180.v:4625$708 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [34] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:4625$708_Y - end - attribute \src "ls180.v:4625.188-4625.322" - cell $xor $xor$ls180.v:4625$709 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg5 [2] - connect \B $xor$ls180.v:4625$708_Y - connect \Y $xor$ls180.v:4625$709_Y - end - attribute \src "ls180.v:4626.416-4626.502" - cell $xor $xor$ls180.v:4626$710 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [33] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:4626$710_Y - end - attribute \src "ls180.v:4626.235-4626.321" - cell $xor $xor$ls180.v:4626$711 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [33] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:4626$711_Y - end - attribute \src "ls180.v:4626.188-4626.322" - cell $xor $xor$ls180.v:4626$712 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg6 [2] - connect \B $xor$ls180.v:4626$711_Y - connect \Y $xor$ls180.v:4626$712_Y - end - attribute \src "ls180.v:4627.416-4627.502" - cell $xor $xor$ls180.v:4627$713 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [32] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:4627$713_Y - end - attribute \src "ls180.v:4627.235-4627.321" - cell $xor $xor$ls180.v:4627$714 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [32] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:4627$714_Y - end - attribute \src "ls180.v:4627.188-4627.322" - cell $xor $xor$ls180.v:4627$715 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg7 [2] - connect \B $xor$ls180.v:4627$714_Y - connect \Y $xor$ls180.v:4627$715_Y - end - attribute \src "ls180.v:4628.416-4628.502" - cell $xor $xor$ls180.v:4628$716 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [31] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:4628$716_Y - end - attribute \src "ls180.v:4628.235-4628.321" - cell $xor $xor$ls180.v:4628$717 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [31] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:4628$717_Y - end - attribute \src "ls180.v:4628.188-4628.322" - cell $xor $xor$ls180.v:4628$718 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg8 [2] - connect \B $xor$ls180.v:4628$717_Y - connect \Y $xor$ls180.v:4628$718_Y - end - attribute \src "ls180.v:4629.417-4629.503" - cell $xor $xor$ls180.v:4629$719 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [30] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:4629$719_Y - end - attribute \src "ls180.v:4629.236-4629.322" - cell $xor $xor$ls180.v:4629$720 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [30] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:4629$720_Y - end - attribute \src "ls180.v:4629.189-4629.323" - cell $xor $xor$ls180.v:4629$721 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg9 [2] - connect \B $xor$ls180.v:4629$720_Y - connect \Y $xor$ls180.v:4629$721_Y - end - attribute \src "ls180.v:4630.424-4630.511" - cell $xor $xor$ls180.v:4630$722 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [29] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:4630$722_Y - end - attribute \src "ls180.v:4630.240-4630.327" - cell $xor $xor$ls180.v:4630$723 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [29] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:4630$723_Y - end - attribute \src "ls180.v:4630.192-4630.328" - cell $xor $xor$ls180.v:4630$724 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg10 [2] - connect \B $xor$ls180.v:4630$723_Y - connect \Y $xor$ls180.v:4630$724_Y - end - attribute \src "ls180.v:4631.424-4631.511" - cell $xor $xor$ls180.v:4631$725 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [28] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:4631$725_Y - end - attribute \src "ls180.v:4631.240-4631.327" - cell $xor $xor$ls180.v:4631$726 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [28] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:4631$726_Y - end - attribute \src "ls180.v:4631.192-4631.328" - cell $xor $xor$ls180.v:4631$727 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg11 [2] - connect \B $xor$ls180.v:4631$726_Y - connect \Y $xor$ls180.v:4631$727_Y - end - attribute \src "ls180.v:4632.424-4632.511" - cell $xor $xor$ls180.v:4632$728 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [27] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:4632$728_Y - end - attribute \src "ls180.v:4632.240-4632.327" - cell $xor $xor$ls180.v:4632$729 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [27] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:4632$729_Y - end - attribute \src "ls180.v:4632.192-4632.328" - cell $xor $xor$ls180.v:4632$730 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg12 [2] - connect \B $xor$ls180.v:4632$729_Y - connect \Y $xor$ls180.v:4632$730_Y - end - attribute \src "ls180.v:4633.424-4633.511" - cell $xor $xor$ls180.v:4633$731 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [26] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:4633$731_Y - end - attribute \src "ls180.v:4633.240-4633.327" - cell $xor $xor$ls180.v:4633$732 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [26] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:4633$732_Y - end - attribute \src "ls180.v:4633.192-4633.328" - cell $xor $xor$ls180.v:4633$733 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg13 [2] - connect \B $xor$ls180.v:4633$732_Y - connect \Y $xor$ls180.v:4633$733_Y - end - attribute \src "ls180.v:4634.424-4634.511" - cell $xor $xor$ls180.v:4634$734 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [25] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:4634$734_Y - end - attribute \src "ls180.v:4634.240-4634.327" - cell $xor $xor$ls180.v:4634$735 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [25] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:4634$735_Y - end - attribute \src "ls180.v:4634.192-4634.328" - cell $xor $xor$ls180.v:4634$736 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg14 [2] - connect \B $xor$ls180.v:4634$735_Y - connect \Y $xor$ls180.v:4634$736_Y - end - attribute \src "ls180.v:4635.424-4635.511" - cell $xor $xor$ls180.v:4635$737 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [24] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:4635$737_Y - end - attribute \src "ls180.v:4635.240-4635.327" - cell $xor $xor$ls180.v:4635$738 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [24] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:4635$738_Y - end - attribute \src "ls180.v:4635.192-4635.328" - cell $xor $xor$ls180.v:4635$739 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg15 [2] - connect \B $xor$ls180.v:4635$738_Y - connect \Y $xor$ls180.v:4635$739_Y - end - attribute \src "ls180.v:4636.424-4636.511" - cell $xor $xor$ls180.v:4636$740 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [23] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:4636$740_Y - end - attribute \src "ls180.v:4636.240-4636.327" - cell $xor $xor$ls180.v:4636$741 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [23] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:4636$741_Y - end - attribute \src "ls180.v:4636.192-4636.328" - cell $xor $xor$ls180.v:4636$742 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg16 [2] - connect \B $xor$ls180.v:4636$741_Y - connect \Y $xor$ls180.v:4636$742_Y - end - attribute \src "ls180.v:4637.424-4637.511" - cell $xor $xor$ls180.v:4637$743 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [22] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:4637$743_Y - end - attribute \src "ls180.v:4637.240-4637.327" - cell $xor $xor$ls180.v:4637$744 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [22] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:4637$744_Y - end - attribute \src "ls180.v:4637.192-4637.328" - cell $xor $xor$ls180.v:4637$745 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg17 [2] - connect \B $xor$ls180.v:4637$744_Y - connect \Y $xor$ls180.v:4637$745_Y - end - attribute \src "ls180.v:4638.424-4638.511" - cell $xor $xor$ls180.v:4638$746 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [21] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:4638$746_Y - end - attribute \src "ls180.v:4638.240-4638.327" - cell $xor $xor$ls180.v:4638$747 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [21] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:4638$747_Y - end - attribute \src "ls180.v:4638.192-4638.328" - cell $xor $xor$ls180.v:4638$748 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg18 [2] - connect \B $xor$ls180.v:4638$747_Y - connect \Y $xor$ls180.v:4638$748_Y - end - attribute \src "ls180.v:4639.424-4639.511" - cell $xor $xor$ls180.v:4639$749 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [20] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:4639$749_Y - end - attribute \src "ls180.v:4639.240-4639.327" - cell $xor $xor$ls180.v:4639$750 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [20] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:4639$750_Y - end - attribute \src "ls180.v:4639.192-4639.328" - cell $xor $xor$ls180.v:4639$751 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg19 [2] - connect \B $xor$ls180.v:4639$750_Y - connect \Y $xor$ls180.v:4639$751_Y - end - attribute \src "ls180.v:4640.424-4640.511" - cell $xor $xor$ls180.v:4640$752 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [19] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:4640$752_Y - end - attribute \src "ls180.v:4640.240-4640.327" - cell $xor $xor$ls180.v:4640$753 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [19] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:4640$753_Y - end - attribute \src "ls180.v:4640.192-4640.328" - cell $xor $xor$ls180.v:4640$754 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg20 [2] - connect \B $xor$ls180.v:4640$753_Y - connect \Y $xor$ls180.v:4640$754_Y - end - attribute \src "ls180.v:4641.424-4641.511" - cell $xor $xor$ls180.v:4641$755 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [18] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:4641$755_Y - end - attribute \src "ls180.v:4641.240-4641.327" - cell $xor $xor$ls180.v:4641$756 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [18] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:4641$756_Y - end - attribute \src "ls180.v:4641.192-4641.328" - cell $xor $xor$ls180.v:4641$757 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg21 [2] - connect \B $xor$ls180.v:4641$756_Y - connect \Y $xor$ls180.v:4641$757_Y - end - attribute \src "ls180.v:4642.424-4642.511" - cell $xor $xor$ls180.v:4642$758 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [17] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:4642$758_Y - end - attribute \src "ls180.v:4642.240-4642.327" - cell $xor $xor$ls180.v:4642$759 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [17] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:4642$759_Y - end - attribute \src "ls180.v:4642.192-4642.328" - cell $xor $xor$ls180.v:4642$760 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg22 [2] - connect \B $xor$ls180.v:4642$759_Y - connect \Y $xor$ls180.v:4642$760_Y - end - attribute \src "ls180.v:4643.424-4643.511" - cell $xor $xor$ls180.v:4643$761 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [16] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:4643$761_Y - end - attribute \src "ls180.v:4643.240-4643.327" - cell $xor $xor$ls180.v:4643$762 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [16] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:4643$762_Y - end - attribute \src "ls180.v:4643.192-4643.328" - cell $xor $xor$ls180.v:4643$763 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg23 [2] - connect \B $xor$ls180.v:4643$762_Y - connect \Y $xor$ls180.v:4643$763_Y - end - attribute \src "ls180.v:4644.424-4644.511" - cell $xor $xor$ls180.v:4644$764 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [15] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:4644$764_Y - end - attribute \src "ls180.v:4644.240-4644.327" - cell $xor $xor$ls180.v:4644$765 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [15] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:4644$765_Y - end - attribute \src "ls180.v:4644.192-4644.328" - cell $xor $xor$ls180.v:4644$766 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg24 [2] - connect \B $xor$ls180.v:4644$765_Y - connect \Y $xor$ls180.v:4644$766_Y - end - attribute \src "ls180.v:4645.424-4645.511" - cell $xor $xor$ls180.v:4645$767 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [14] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:4645$767_Y - end - attribute \src "ls180.v:4645.240-4645.327" - cell $xor $xor$ls180.v:4645$768 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [14] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:4645$768_Y - end - attribute \src "ls180.v:4645.192-4645.328" - cell $xor $xor$ls180.v:4645$769 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg25 [2] - connect \B $xor$ls180.v:4645$768_Y - connect \Y $xor$ls180.v:4645$769_Y - end - attribute \src "ls180.v:4646.424-4646.511" - cell $xor $xor$ls180.v:4646$770 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [13] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:4646$770_Y - end - attribute \src "ls180.v:4646.240-4646.327" - cell $xor $xor$ls180.v:4646$771 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [13] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:4646$771_Y - end - attribute \src "ls180.v:4646.192-4646.328" - cell $xor $xor$ls180.v:4646$772 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg26 [2] - connect \B $xor$ls180.v:4646$771_Y - connect \Y $xor$ls180.v:4646$772_Y - end - attribute \src "ls180.v:4647.424-4647.511" - cell $xor $xor$ls180.v:4647$773 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [12] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:4647$773_Y - end - attribute \src "ls180.v:4647.240-4647.327" - cell $xor $xor$ls180.v:4647$774 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [12] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:4647$774_Y - end - attribute \src "ls180.v:4647.192-4647.328" - cell $xor $xor$ls180.v:4647$775 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg27 [2] - connect \B $xor$ls180.v:4647$774_Y - connect \Y $xor$ls180.v:4647$775_Y - end - attribute \src "ls180.v:4648.424-4648.511" - cell $xor $xor$ls180.v:4648$776 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [11] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:4648$776_Y - end - attribute \src "ls180.v:4648.240-4648.327" - cell $xor $xor$ls180.v:4648$777 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [11] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:4648$777_Y - end - attribute \src "ls180.v:4648.192-4648.328" - cell $xor $xor$ls180.v:4648$778 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg28 [2] - connect \B $xor$ls180.v:4648$777_Y - connect \Y $xor$ls180.v:4648$778_Y - end - attribute \src "ls180.v:4649.424-4649.511" - cell $xor $xor$ls180.v:4649$779 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [10] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:4649$779_Y - end - attribute \src "ls180.v:4649.240-4649.327" - cell $xor $xor$ls180.v:4649$780 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [10] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:4649$780_Y - end - attribute \src "ls180.v:4649.192-4649.328" - cell $xor $xor$ls180.v:4649$781 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg29 [2] - connect \B $xor$ls180.v:4649$780_Y - connect \Y $xor$ls180.v:4649$781_Y - end - attribute \src "ls180.v:4650.423-4650.509" - cell $xor $xor$ls180.v:4650$782 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [9] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:4650$782_Y - end - attribute \src "ls180.v:4650.240-4650.326" - cell $xor $xor$ls180.v:4650$783 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [9] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:4650$783_Y - end - attribute \src "ls180.v:4650.192-4650.327" - cell $xor $xor$ls180.v:4650$784 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg30 [2] - connect \B $xor$ls180.v:4650$783_Y - connect \Y $xor$ls180.v:4650$784_Y - end - attribute \src "ls180.v:4651.423-4651.509" - cell $xor $xor$ls180.v:4651$785 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [8] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:4651$785_Y - end - attribute \src "ls180.v:4651.240-4651.326" - cell $xor $xor$ls180.v:4651$786 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [8] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:4651$786_Y - end - attribute \src "ls180.v:4651.192-4651.327" - cell $xor $xor$ls180.v:4651$787 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg31 [2] - connect \B $xor$ls180.v:4651$786_Y - connect \Y $xor$ls180.v:4651$787_Y - end - attribute \src "ls180.v:4652.423-4652.509" - cell $xor $xor$ls180.v:4652$788 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [7] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:4652$788_Y - end - attribute \src "ls180.v:4652.240-4652.326" - cell $xor $xor$ls180.v:4652$789 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [7] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:4652$789_Y - end - attribute \src "ls180.v:4652.192-4652.327" - cell $xor $xor$ls180.v:4652$790 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg32 [2] - connect \B $xor$ls180.v:4652$789_Y - connect \Y $xor$ls180.v:4652$790_Y - end - attribute \src "ls180.v:4653.423-4653.509" - cell $xor $xor$ls180.v:4653$791 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [6] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:4653$791_Y - end - attribute \src "ls180.v:4653.240-4653.326" - cell $xor $xor$ls180.v:4653$792 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [6] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:4653$792_Y - end - attribute \src "ls180.v:4653.192-4653.327" - cell $xor $xor$ls180.v:4653$793 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg33 [2] - connect \B $xor$ls180.v:4653$792_Y - connect \Y $xor$ls180.v:4653$793_Y - end - attribute \src "ls180.v:4654.423-4654.509" - cell $xor $xor$ls180.v:4654$794 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [5] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:4654$794_Y - end - attribute \src "ls180.v:4654.240-4654.326" - cell $xor $xor$ls180.v:4654$795 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [5] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:4654$795_Y - end - attribute \src "ls180.v:4654.192-4654.327" - cell $xor $xor$ls180.v:4654$796 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg34 [2] - connect \B $xor$ls180.v:4654$795_Y - connect \Y $xor$ls180.v:4654$796_Y - end - attribute \src "ls180.v:4655.423-4655.509" - cell $xor $xor$ls180.v:4655$797 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [4] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:4655$797_Y - end - attribute \src "ls180.v:4655.240-4655.326" - cell $xor $xor$ls180.v:4655$798 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [4] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:4655$798_Y - end - attribute \src "ls180.v:4655.192-4655.327" - cell $xor $xor$ls180.v:4655$799 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg35 [2] - connect \B $xor$ls180.v:4655$798_Y - connect \Y $xor$ls180.v:4655$799_Y - end - attribute \src "ls180.v:4656.423-4656.509" - cell $xor $xor$ls180.v:4656$800 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [3] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:4656$800_Y - end - attribute \src "ls180.v:4656.240-4656.326" - cell $xor $xor$ls180.v:4656$801 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [3] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:4656$801_Y - end - attribute \src "ls180.v:4656.192-4656.327" - cell $xor $xor$ls180.v:4656$802 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg36 [2] - connect \B $xor$ls180.v:4656$801_Y - connect \Y $xor$ls180.v:4656$802_Y - end - attribute \src "ls180.v:4657.423-4657.509" - cell $xor $xor$ls180.v:4657$803 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [2] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:4657$803_Y - end - attribute \src "ls180.v:4657.240-4657.326" - cell $xor $xor$ls180.v:4657$804 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [2] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:4657$804_Y - end - attribute \src "ls180.v:4657.192-4657.327" - cell $xor $xor$ls180.v:4657$805 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg37 [2] - connect \B $xor$ls180.v:4657$804_Y - connect \Y $xor$ls180.v:4657$805_Y - end - attribute \src "ls180.v:4658.423-4658.509" - cell $xor $xor$ls180.v:4658$806 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [1] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:4658$806_Y - end - attribute \src "ls180.v:4658.240-4658.326" - cell $xor $xor$ls180.v:4658$807 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [1] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:4658$807_Y - end - attribute \src "ls180.v:4658.192-4658.327" - cell $xor $xor$ls180.v:4658$808 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg38 [2] - connect \B $xor$ls180.v:4658$807_Y - connect \Y $xor$ls180.v:4658$808_Y - end - attribute \src "ls180.v:4659.423-4659.509" - cell $xor $xor$ls180.v:4659$809 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [0] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:4659$809_Y - end - attribute \src "ls180.v:4659.240-4659.326" - cell $xor $xor$ls180.v:4659$810 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_val [0] - connect \B \libresocsim_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:4659$810_Y - end - attribute \src "ls180.v:4659.192-4659.327" - cell $xor $xor$ls180.v:4659$811 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc7_inserter_crcreg39 [2] - connect \B $xor$ls180.v:4659$810_Y - connect \Y $xor$ls180.v:4659$811_Y - end - attribute \src "ls180.v:4680.1039-4680.1137" - cell $xor $xor$ls180.v:4680$825 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc0_val [1] - connect \B \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:4680$825_Y - end - attribute \src "ls180.v:4680.732-4680.830" - cell $xor $xor$ls180.v:4680$826 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc0_val [1] - connect \B \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:4680$826_Y - end - attribute \src "ls180.v:4680.679-4680.831" - cell $xor $xor$ls180.v:4680$827 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 [4] - connect \B $xor$ls180.v:4680$826_Y - connect \Y $xor$ls180.v:4680$827_Y - end - attribute \src "ls180.v:4680.269-4680.367" - cell $xor $xor$ls180.v:4680$828 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc0_val [1] - connect \B \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:4680$828_Y - end - attribute \src "ls180.v:4680.215-4680.368" - cell $xor $xor$ls180.v:4680$829 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 [11] - connect \B $xor$ls180.v:4680$828_Y - connect \Y $xor$ls180.v:4680$829_Y - end - attribute \src "ls180.v:4681.1039-4681.1137" - cell $xor $xor$ls180.v:4681$830 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc0_val [0] - connect \B \libresocsim_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:4681$830_Y - end - attribute \src "ls180.v:4681.732-4681.830" - cell $xor $xor$ls180.v:4681$831 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc0_val [0] - connect \B \libresocsim_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:4681$831_Y - end - attribute \src "ls180.v:4681.679-4681.831" - cell $xor $xor$ls180.v:4681$832 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc0_crcreg1 [4] - connect \B $xor$ls180.v:4681$831_Y - connect \Y $xor$ls180.v:4681$832_Y - end - attribute \src "ls180.v:4681.269-4681.367" - cell $xor $xor$ls180.v:4681$833 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc0_val [0] - connect \B \libresocsim_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:4681$833_Y - end - attribute \src "ls180.v:4681.215-4681.368" - cell $xor $xor$ls180.v:4681$834 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc0_crcreg1 [11] - connect \B $xor$ls180.v:4681$833_Y - connect \Y $xor$ls180.v:4681$834_Y - end - attribute \src "ls180.v:4690.1039-4690.1137" - cell $xor $xor$ls180.v:4690$836 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc1_val [1] - connect \B \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:4690$836_Y - end - attribute \src "ls180.v:4690.732-4690.830" - cell $xor $xor$ls180.v:4690$837 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc1_val [1] - connect \B \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:4690$837_Y - end - attribute \src "ls180.v:4690.679-4690.831" - cell $xor $xor$ls180.v:4690$838 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 [4] - connect \B $xor$ls180.v:4690$837_Y - connect \Y $xor$ls180.v:4690$838_Y - end - attribute \src "ls180.v:4690.269-4690.367" - cell $xor $xor$ls180.v:4690$839 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc1_val [1] - connect \B \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:4690$839_Y - end - attribute \src "ls180.v:4690.215-4690.368" - cell $xor $xor$ls180.v:4690$840 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 [11] - connect \B $xor$ls180.v:4690$839_Y - connect \Y $xor$ls180.v:4690$840_Y - end - attribute \src "ls180.v:4691.1039-4691.1137" - cell $xor $xor$ls180.v:4691$841 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc1_val [0] - connect \B \libresocsim_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:4691$841_Y - end - attribute \src "ls180.v:4691.732-4691.830" - cell $xor $xor$ls180.v:4691$842 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc1_val [0] - connect \B \libresocsim_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:4691$842_Y - end - attribute \src "ls180.v:4691.679-4691.831" - cell $xor $xor$ls180.v:4691$843 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc1_crcreg1 [4] - connect \B $xor$ls180.v:4691$842_Y - connect \Y $xor$ls180.v:4691$843_Y - end - attribute \src "ls180.v:4691.269-4691.367" - cell $xor $xor$ls180.v:4691$844 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc1_val [0] - connect \B \libresocsim_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:4691$844_Y - end - attribute \src "ls180.v:4691.215-4691.368" - cell $xor $xor$ls180.v:4691$845 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc1_crcreg1 [11] - connect \B $xor$ls180.v:4691$844_Y - connect \Y $xor$ls180.v:4691$845_Y - end - attribute \src "ls180.v:4700.1039-4700.1137" - cell $xor $xor$ls180.v:4700$847 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc2_val [1] - connect \B \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:4700$847_Y - end - attribute \src "ls180.v:4700.732-4700.830" - cell $xor $xor$ls180.v:4700$848 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc2_val [1] - connect \B \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:4700$848_Y - end - attribute \src "ls180.v:4700.679-4700.831" - cell $xor $xor$ls180.v:4700$849 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 [4] - connect \B $xor$ls180.v:4700$848_Y - connect \Y $xor$ls180.v:4700$849_Y - end - attribute \src "ls180.v:4700.269-4700.367" - cell $xor $xor$ls180.v:4700$850 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc2_val [1] - connect \B \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:4700$850_Y - end - attribute \src "ls180.v:4700.215-4700.368" - cell $xor $xor$ls180.v:4700$851 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 [11] - connect \B $xor$ls180.v:4700$850_Y - connect \Y $xor$ls180.v:4700$851_Y - end - attribute \src "ls180.v:4701.1039-4701.1137" - cell $xor $xor$ls180.v:4701$852 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc2_val [0] - connect \B \libresocsim_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:4701$852_Y - end - attribute \src "ls180.v:4701.732-4701.830" - cell $xor $xor$ls180.v:4701$853 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc2_val [0] - connect \B \libresocsim_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:4701$853_Y - end - attribute \src "ls180.v:4701.679-4701.831" - cell $xor $xor$ls180.v:4701$854 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc2_crcreg1 [4] - connect \B $xor$ls180.v:4701$853_Y - connect \Y $xor$ls180.v:4701$854_Y - end - attribute \src "ls180.v:4701.269-4701.367" - cell $xor $xor$ls180.v:4701$855 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc2_val [0] - connect \B \libresocsim_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:4701$855_Y - end - attribute \src "ls180.v:4701.215-4701.368" - cell $xor $xor$ls180.v:4701$856 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc2_crcreg1 [11] - connect \B $xor$ls180.v:4701$855_Y - connect \Y $xor$ls180.v:4701$856_Y - end - attribute \src "ls180.v:4710.1039-4710.1137" - cell $xor $xor$ls180.v:4710$858 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc3_val [1] - connect \B \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:4710$858_Y - end - attribute \src "ls180.v:4710.732-4710.830" - cell $xor $xor$ls180.v:4710$859 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc3_val [1] - connect \B \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:4710$859_Y - end - attribute \src "ls180.v:4710.679-4710.831" - cell $xor $xor$ls180.v:4710$860 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 [4] - connect \B $xor$ls180.v:4710$859_Y - connect \Y $xor$ls180.v:4710$860_Y - end - attribute \src "ls180.v:4710.269-4710.367" - cell $xor $xor$ls180.v:4710$861 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc3_val [1] - connect \B \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:4710$861_Y - end - attribute \src "ls180.v:4710.215-4710.368" - cell $xor $xor$ls180.v:4710$862 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 [11] - connect \B $xor$ls180.v:4710$861_Y - connect \Y $xor$ls180.v:4710$862_Y - end - attribute \src "ls180.v:4711.1039-4711.1137" - cell $xor $xor$ls180.v:4711$863 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc3_val [0] - connect \B \libresocsim_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:4711$863_Y - end - attribute \src "ls180.v:4711.732-4711.830" - cell $xor $xor$ls180.v:4711$864 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc3_val [0] - connect \B \libresocsim_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:4711$864_Y - end - attribute \src "ls180.v:4711.679-4711.831" - cell $xor $xor$ls180.v:4711$865 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc3_crcreg1 [4] - connect \B $xor$ls180.v:4711$864_Y - connect \Y $xor$ls180.v:4711$865_Y - end - attribute \src "ls180.v:4711.269-4711.367" - cell $xor $xor$ls180.v:4711$866 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc3_val [0] - connect \B \libresocsim_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:4711$866_Y - end - attribute \src "ls180.v:4711.215-4711.368" - cell $xor $xor$ls180.v:4711$867 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_inserter_crc3_crcreg1 [11] - connect \B $xor$ls180.v:4711$866_Y - connect \Y $xor$ls180.v:4711$867_Y - end - attribute \src "ls180.v:4862.1019-4862.1115" - cell $xor $xor$ls180.v:4862$900 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc0_val [1] - connect \B \libresocsim_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:4862$900_Y - end - attribute \src "ls180.v:4862.718-4862.814" - cell $xor $xor$ls180.v:4862$901 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc0_val [1] - connect \B \libresocsim_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:4862$901_Y - end - attribute \src "ls180.v:4862.666-4862.815" - cell $xor $xor$ls180.v:4862$902 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc0_crcreg0 [4] - connect \B $xor$ls180.v:4862$901_Y - connect \Y $xor$ls180.v:4862$902_Y - end - attribute \src "ls180.v:4862.264-4862.360" - cell $xor $xor$ls180.v:4862$903 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc0_val [1] - connect \B \libresocsim_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:4862$903_Y - end - attribute \src "ls180.v:4862.211-4862.361" - cell $xor $xor$ls180.v:4862$904 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc0_crcreg0 [11] - connect \B $xor$ls180.v:4862$903_Y - connect \Y $xor$ls180.v:4862$904_Y - end - attribute \src "ls180.v:4863.1019-4863.1115" - cell $xor $xor$ls180.v:4863$905 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc0_val [0] - connect \B \libresocsim_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:4863$905_Y - end - attribute \src "ls180.v:4863.718-4863.814" - cell $xor $xor$ls180.v:4863$906 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc0_val [0] - connect \B \libresocsim_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:4863$906_Y - end - attribute \src "ls180.v:4863.666-4863.815" - cell $xor $xor$ls180.v:4863$907 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc0_crcreg1 [4] - connect \B $xor$ls180.v:4863$906_Y - connect \Y $xor$ls180.v:4863$907_Y - end - attribute \src "ls180.v:4863.264-4863.360" - cell $xor $xor$ls180.v:4863$908 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc0_val [0] - connect \B \libresocsim_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:4863$908_Y - end - attribute \src "ls180.v:4863.211-4863.361" - cell $xor $xor$ls180.v:4863$909 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc0_crcreg1 [11] - connect \B $xor$ls180.v:4863$908_Y - connect \Y $xor$ls180.v:4863$909_Y - end - attribute \src "ls180.v:4872.1019-4872.1115" - cell $xor $xor$ls180.v:4872$911 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc1_val [1] - connect \B \libresocsim_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:4872$911_Y - end - attribute \src "ls180.v:4872.718-4872.814" - cell $xor $xor$ls180.v:4872$912 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc1_val [1] - connect \B \libresocsim_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:4872$912_Y - end - attribute \src "ls180.v:4872.666-4872.815" - cell $xor $xor$ls180.v:4872$913 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc1_crcreg0 [4] - connect \B $xor$ls180.v:4872$912_Y - connect \Y $xor$ls180.v:4872$913_Y - end - attribute \src "ls180.v:4872.264-4872.360" - cell $xor $xor$ls180.v:4872$914 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc1_val [1] - connect \B \libresocsim_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:4872$914_Y - end - attribute \src "ls180.v:4872.211-4872.361" - cell $xor $xor$ls180.v:4872$915 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc1_crcreg0 [11] - connect \B $xor$ls180.v:4872$914_Y - connect \Y $xor$ls180.v:4872$915_Y - end - attribute \src "ls180.v:4873.1019-4873.1115" - cell $xor $xor$ls180.v:4873$916 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc1_val [0] - connect \B \libresocsim_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:4873$916_Y - end - attribute \src "ls180.v:4873.718-4873.814" - cell $xor $xor$ls180.v:4873$917 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc1_val [0] - connect \B \libresocsim_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:4873$917_Y - end - attribute \src "ls180.v:4873.666-4873.815" - cell $xor $xor$ls180.v:4873$918 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc1_crcreg1 [4] - connect \B $xor$ls180.v:4873$917_Y - connect \Y $xor$ls180.v:4873$918_Y - end - attribute \src "ls180.v:4873.264-4873.360" - cell $xor $xor$ls180.v:4873$919 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc1_val [0] - connect \B \libresocsim_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:4873$919_Y - end - attribute \src "ls180.v:4873.211-4873.361" - cell $xor $xor$ls180.v:4873$920 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc1_crcreg1 [11] - connect \B $xor$ls180.v:4873$919_Y - connect \Y $xor$ls180.v:4873$920_Y - end - attribute \src "ls180.v:4882.1019-4882.1115" - cell $xor $xor$ls180.v:4882$922 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc2_val [1] - connect \B \libresocsim_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:4882$922_Y - end - attribute \src "ls180.v:4882.718-4882.814" - cell $xor $xor$ls180.v:4882$923 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc2_val [1] - connect \B \libresocsim_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:4882$923_Y - end - attribute \src "ls180.v:4882.666-4882.815" - cell $xor $xor$ls180.v:4882$924 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc2_crcreg0 [4] - connect \B $xor$ls180.v:4882$923_Y - connect \Y $xor$ls180.v:4882$924_Y - end - attribute \src "ls180.v:4882.264-4882.360" - cell $xor $xor$ls180.v:4882$925 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc2_val [1] - connect \B \libresocsim_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:4882$925_Y - end - attribute \src "ls180.v:4882.211-4882.361" - cell $xor $xor$ls180.v:4882$926 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc2_crcreg0 [11] - connect \B $xor$ls180.v:4882$925_Y - connect \Y $xor$ls180.v:4882$926_Y - end - attribute \src "ls180.v:4883.1019-4883.1115" - cell $xor $xor$ls180.v:4883$927 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc2_val [0] - connect \B \libresocsim_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:4883$927_Y - end - attribute \src "ls180.v:4883.718-4883.814" - cell $xor $xor$ls180.v:4883$928 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc2_val [0] - connect \B \libresocsim_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:4883$928_Y - end - attribute \src "ls180.v:4883.666-4883.815" - cell $xor $xor$ls180.v:4883$929 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc2_crcreg1 [4] - connect \B $xor$ls180.v:4883$928_Y - connect \Y $xor$ls180.v:4883$929_Y - end - attribute \src "ls180.v:4883.264-4883.360" - cell $xor $xor$ls180.v:4883$930 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc2_val [0] - connect \B \libresocsim_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:4883$930_Y - end - attribute \src "ls180.v:4883.211-4883.361" - cell $xor $xor$ls180.v:4883$931 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc2_crcreg1 [11] - connect \B $xor$ls180.v:4883$930_Y - connect \Y $xor$ls180.v:4883$931_Y - end - attribute \src "ls180.v:4892.1019-4892.1115" - cell $xor $xor$ls180.v:4892$933 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc3_val [1] - connect \B \libresocsim_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:4892$933_Y - end - attribute \src "ls180.v:4892.718-4892.814" - cell $xor $xor$ls180.v:4892$934 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc3_val [1] - connect \B \libresocsim_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:4892$934_Y - end - attribute \src "ls180.v:4892.666-4892.815" - cell $xor $xor$ls180.v:4892$935 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc3_crcreg0 [4] - connect \B $xor$ls180.v:4892$934_Y - connect \Y $xor$ls180.v:4892$935_Y - end - attribute \src "ls180.v:4892.264-4892.360" - cell $xor $xor$ls180.v:4892$936 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc3_val [1] - connect \B \libresocsim_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:4892$936_Y - end - attribute \src "ls180.v:4892.211-4892.361" - cell $xor $xor$ls180.v:4892$937 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc3_crcreg0 [11] - connect \B $xor$ls180.v:4892$936_Y - connect \Y $xor$ls180.v:4892$937_Y - end - attribute \src "ls180.v:4893.1019-4893.1115" - cell $xor $xor$ls180.v:4893$938 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc3_val [0] - connect \B \libresocsim_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:4893$938_Y - end - attribute \src "ls180.v:4893.718-4893.814" - cell $xor $xor$ls180.v:4893$939 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc3_val [0] - connect \B \libresocsim_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:4893$939_Y - end - attribute \src "ls180.v:4893.666-4893.815" - cell $xor $xor$ls180.v:4893$940 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc3_crcreg1 [4] - connect \B $xor$ls180.v:4893$939_Y - connect \Y $xor$ls180.v:4893$940_Y - end - attribute \src "ls180.v:4893.264-4893.360" - cell $xor $xor$ls180.v:4893$941 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc3_val [0] - connect \B \libresocsim_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:4893$941_Y - end - attribute \src "ls180.v:4893.211-4893.361" - cell $xor $xor$ls180.v:4893$942 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_sdcore_crc16_checker_crc3_crcreg1 [11] - connect \B $xor$ls180.v:4893$941_Y - connect \Y $xor$ls180.v:4893$942_Y - end - attribute \module_not_derived 1 - attribute \src "ls180.v:9504.13-9564.2" - cell \test_issuer \test_issuer - connect \busy_o \main_libresocsim_libresoc0 - connect \clk \sys_clk_1 - connect \core_bigendian_i 1'0 - connect \dbus__ack \main_libresocsim_libresoc_dbus_ack - connect \dbus__adr \main_libresocsim_libresoc_dbus_adr - connect \dbus__bte \main_libresocsim_libresoc_dbus_bte - connect \dbus__cti \main_libresocsim_libresoc_dbus_cti - connect \dbus__cyc \main_libresocsim_libresoc_dbus_cyc - connect \dbus__dat_r \main_libresocsim_libresoc_dbus_dat_r - connect \dbus__dat_w \main_libresocsim_libresoc_dbus_dat_w - connect \dbus__err \main_libresocsim_libresoc_dbus_err - connect \dbus__sel \main_libresocsim_libresoc_dbus_sel - connect \dbus__stb \main_libresocsim_libresoc_dbus_stb - connect \dbus__we \main_libresocsim_libresoc_dbus_we - connect \dmi_ack_o \main_libresocsim_libresoc_dmi_ack - connect \dmi_addr_i \main_libresocsim_libresoc_dmi_addr - connect \dmi_din \main_libresocsim_libresoc_dmi_din - connect \dmi_dout \main_libresocsim_libresoc_dmi_dout - connect \dmi_req_i \main_libresocsim_libresoc_dmi_req - connect \dmi_we_i \main_libresocsim_libresoc_dmi_wr - connect \ibus__ack \main_libresocsim_libresoc_ibus_ack - connect \ibus__adr \main_libresocsim_libresoc_ibus_adr - connect \ibus__bte \main_libresocsim_libresoc_ibus_bte - connect \ibus__cti \main_libresocsim_libresoc_ibus_cti - connect \ibus__cyc \main_libresocsim_libresoc_ibus_cyc - connect \ibus__dat_r \main_libresocsim_libresoc_ibus_dat_r - connect \ibus__dat_w \main_libresocsim_libresoc_ibus_dat_w - connect \ibus__err \main_libresocsim_libresoc_ibus_err - connect \ibus__sel \main_libresocsim_libresoc_ibus_sel - connect \ibus__stb \main_libresocsim_libresoc_ibus_stb - connect \ibus__we \main_libresocsim_libresoc_ibus_we - connect \icp_wb__ack \main_libresocsim_libresoc_xics_icp_ack - connect \icp_wb__adr \main_libresocsim_libresoc_xics_icp_adr - connect \icp_wb__bte \main_libresocsim_libresoc_xics_icp_bte - connect \icp_wb__cti \main_libresocsim_libresoc_xics_icp_cti - connect \icp_wb__cyc \main_libresocsim_libresoc_xics_icp_cyc - connect \icp_wb__dat_r \main_libresocsim_libresoc_xics_icp_dat_r - connect \icp_wb__dat_w \main_libresocsim_libresoc_xics_icp_dat_w - connect \icp_wb__err \main_libresocsim_libresoc_xics_icp_err - connect \icp_wb__sel \main_libresocsim_libresoc_xics_icp_sel - connect \icp_wb__stb \main_libresocsim_libresoc_xics_icp_stb - connect \icp_wb__we \main_libresocsim_libresoc_xics_icp_we - connect \ics_wb__ack \main_libresocsim_libresoc_xics_ics_ack - connect \ics_wb__adr \main_libresocsim_libresoc_xics_ics_adr - connect \ics_wb__bte \main_libresocsim_libresoc_xics_ics_bte - connect \ics_wb__cti \main_libresocsim_libresoc_xics_ics_cti - connect \ics_wb__cyc \main_libresocsim_libresoc_xics_ics_cyc - connect \ics_wb__dat_r \main_libresocsim_libresoc_xics_ics_dat_r - connect \ics_wb__dat_w \main_libresocsim_libresoc_xics_ics_dat_w - connect \ics_wb__err \main_libresocsim_libresoc_xics_ics_err - connect \ics_wb__sel \main_libresocsim_libresoc_xics_ics_sel - connect \ics_wb__stb \main_libresocsim_libresoc_xics_ics_stb - connect \ics_wb__we \main_libresocsim_libresoc_xics_ics_we - connect \int_level_i \main_libresocsim_libresoc_interrupt - connect \memerr_o \main_libresocsim_libresoc1 - connect \pc_i 1'0 - connect \pc_i_ok 1'0 - connect \pc_o \main_libresocsim_libresoc2 - connect \rst $or$ls180.v:9536$2529_Y - end - attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$3478 - sync always - sync init - end - attribute \src "ls180.v:100.11-100.69" - process $proc$ls180.v:100$2579 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_sel $1\main_libresocsim_interface0_converted_interface_sel[3:0] - end - attribute \src "ls180.v:1000.5-1000.39" - process $proc$ls180.v:1000$2969 - assign { } { } - assign $1\libresocsim_cmdr_sink_ready[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdr_sink_ready $1\libresocsim_cmdr_sink_ready[0:0] - end - attribute \src "ls180.v:1001.5-1001.38" - process $proc$ls180.v:1001$2970 - assign { } { } - assign $1\libresocsim_cmdr_sink_last[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdr_sink_last $1\libresocsim_cmdr_sink_last[0:0] - end - attribute \src "ls180.v:1002.11-1002.54" - process $proc$ls180.v:1002$2971 - assign { } { } - assign $1\libresocsim_cmdr_sink_payload_length[7:0] 8'00000000 - sync always - sync init - update \libresocsim_cmdr_sink_payload_length $1\libresocsim_cmdr_sink_payload_length[7:0] - end - attribute \src "ls180.v:1003.5-1003.41" - process $proc$ls180.v:1003$2972 - assign { } { } - assign $1\libresocsim_cmdr_source_valid[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdr_source_valid $1\libresocsim_cmdr_source_valid[0:0] - end - attribute \src "ls180.v:1004.5-1004.41" - process $proc$ls180.v:1004$2973 - assign { } { } - assign $1\libresocsim_cmdr_source_ready[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdr_source_ready $1\libresocsim_cmdr_source_ready[0:0] - end - attribute \src "ls180.v:1005.5-1005.40" - process $proc$ls180.v:1005$2974 - assign { } { } - assign $1\libresocsim_cmdr_source_last[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdr_source_last $1\libresocsim_cmdr_source_last[0:0] - end - attribute \src "ls180.v:1006.11-1006.54" - process $proc$ls180.v:1006$2975 - assign { } { } - assign $1\libresocsim_cmdr_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \libresocsim_cmdr_source_payload_data $1\libresocsim_cmdr_source_payload_data[7:0] - end - attribute \src "ls180.v:1007.11-1007.56" - process $proc$ls180.v:1007$2976 - assign { } { } - assign $1\libresocsim_cmdr_source_payload_status[2:0] 3'000 - sync always - sync init - update \libresocsim_cmdr_source_payload_status $1\libresocsim_cmdr_source_payload_status[2:0] - end - attribute \src "ls180.v:1008.12-1008.49" - process $proc$ls180.v:1008$2977 - assign { } { } - assign $1\libresocsim_cmdr_timeout[31:0] 500000 - sync always - sync init - update \libresocsim_cmdr_timeout $1\libresocsim_cmdr_timeout[31:0] - end - attribute \src "ls180.v:1009.11-1009.40" - process $proc$ls180.v:1009$2978 - assign { } { } - assign $1\libresocsim_cmdr_count[7:0] 8'00000000 - sync always - sync init - update \libresocsim_cmdr_count $1\libresocsim_cmdr_count[7:0] - end - attribute \src "ls180.v:101.5-101.63" - process $proc$ls180.v:101$2580 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_cyc $1\main_libresocsim_interface0_converted_interface_cyc[0:0] - end - attribute \src "ls180.v:1011.5-1011.47" - process $proc$ls180.v:1011$2979 - assign { } { } - assign $0\libresocsim_cmdr_cmdr_pads_in_ready[0:0] 1'0 - sync always - update \libresocsim_cmdr_cmdr_pads_in_ready $0\libresocsim_cmdr_cmdr_pads_in_ready[0:0] - sync init - end - attribute \src "ls180.v:102.5-102.63" - process $proc$ls180.v:102$2581 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_stb $1\main_libresocsim_interface0_converted_interface_stb[0:0] - end - attribute \src "ls180.v:1022.5-1022.54" - process $proc$ls180.v:1022$2980 - assign { } { } - assign $1\libresocsim_cmdr_cmdr_source_source_ready0[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdr_cmdr_source_source_ready0 $1\libresocsim_cmdr_cmdr_source_source_ready0[0:0] - end - attribute \src "ls180.v:1027.5-1027.37" - process $proc$ls180.v:1027$2981 - assign { } { } - assign $1\libresocsim_cmdr_cmdr_run[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdr_cmdr_run $1\libresocsim_cmdr_cmdr_run[0:0] - end - attribute \src "ls180.v:1030.5-1030.54" - process $proc$ls180.v:1030$2982 - assign { } { } - assign $0\libresocsim_cmdr_cmdr_converter_sink_first[0:0] 1'0 - sync always - update \libresocsim_cmdr_cmdr_converter_sink_first $0\libresocsim_cmdr_cmdr_converter_sink_first[0:0] - sync init - end - attribute \src "ls180.v:1031.5-1031.53" - process $proc$ls180.v:1031$2983 - assign { } { } - assign $0\libresocsim_cmdr_cmdr_converter_sink_last[0:0] 1'0 - sync always - update \libresocsim_cmdr_cmdr_converter_sink_last $0\libresocsim_cmdr_cmdr_converter_sink_last[0:0] - sync init - end - attribute \src "ls180.v:1035.5-1035.56" - process $proc$ls180.v:1035$2984 - assign { } { } - assign $1\libresocsim_cmdr_cmdr_converter_source_first[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdr_cmdr_converter_source_first $1\libresocsim_cmdr_cmdr_converter_source_first[0:0] - end - attribute \src "ls180.v:1036.5-1036.55" - process $proc$ls180.v:1036$2985 - assign { } { } - assign $1\libresocsim_cmdr_cmdr_converter_source_last[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdr_cmdr_converter_source_last $1\libresocsim_cmdr_cmdr_converter_source_last[0:0] - end - attribute \src "ls180.v:1037.11-1037.69" - process $proc$ls180.v:1037$2986 - assign { } { } - assign $1\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \libresocsim_cmdr_cmdr_converter_source_payload_data $1\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:1038.11-1038.82" - process $proc$ls180.v:1038$2987 - assign { } { } - assign $1\libresocsim_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000 - sync always - sync init - update \libresocsim_cmdr_cmdr_converter_source_payload_valid_token_count $1\libresocsim_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - end - attribute \src "ls180.v:1039.11-1039.55" - process $proc$ls180.v:1039$2988 - assign { } { } - assign $1\libresocsim_cmdr_cmdr_converter_demux[2:0] 3'000 - sync always - sync init - update \libresocsim_cmdr_cmdr_converter_demux $1\libresocsim_cmdr_cmdr_converter_demux[2:0] - end - attribute \src "ls180.v:104.5-104.62" - process $proc$ls180.v:104$2582 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_we $1\main_libresocsim_interface0_converted_interface_we[0:0] - end - attribute \src "ls180.v:1041.5-1041.54" - process $proc$ls180.v:1041$2989 - assign { } { } - assign $1\libresocsim_cmdr_cmdr_converter_strobe_all[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdr_cmdr_converter_strobe_all $1\libresocsim_cmdr_cmdr_converter_strobe_all[0:0] - end - attribute \src "ls180.v:105.11-105.69" - process $proc$ls180.v:105$2583 - assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000 - sync always - update \main_libresocsim_interface0_converted_interface_cti $0\main_libresocsim_interface0_converted_interface_cti[2:0] - sync init - end - attribute \src "ls180.v:1052.5-1052.50" - process $proc$ls180.v:1052$2990 - assign { } { } - assign $1\libresocsim_cmdr_cmdr_buf_source_valid[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdr_cmdr_buf_source_valid $1\libresocsim_cmdr_cmdr_buf_source_valid[0:0] - end - attribute \src "ls180.v:1054.5-1054.50" - process $proc$ls180.v:1054$2991 - assign { } { } - assign $1\libresocsim_cmdr_cmdr_buf_source_first[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdr_cmdr_buf_source_first $1\libresocsim_cmdr_cmdr_buf_source_first[0:0] - end - attribute \src "ls180.v:1055.5-1055.49" - process $proc$ls180.v:1055$2992 - assign { } { } - assign $1\libresocsim_cmdr_cmdr_buf_source_last[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdr_cmdr_buf_source_last $1\libresocsim_cmdr_cmdr_buf_source_last[0:0] - end - attribute \src "ls180.v:1056.11-1056.63" - process $proc$ls180.v:1056$2993 - assign { } { } - assign $1\libresocsim_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \libresocsim_cmdr_cmdr_buf_source_payload_data $1\libresocsim_cmdr_cmdr_buf_source_payload_data[7:0] - end - attribute \src "ls180.v:1057.5-1057.39" - process $proc$ls180.v:1057$2994 - assign { } { } - assign $1\libresocsim_cmdr_cmdr_reset[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdr_cmdr_reset $1\libresocsim_cmdr_cmdr_reset[0:0] - end - attribute \src "ls180.v:106.11-106.69" - process $proc$ls180.v:106$2584 - assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_bte[1:0] 2'00 - sync always - update \main_libresocsim_interface0_converted_interface_bte $0\main_libresocsim_interface0_converted_interface_bte[1:0] - sync init - end - attribute \src "ls180.v:1062.5-1062.50" - process $proc$ls180.v:1062$2995 - assign { } { } - assign $1\libresocsim_dataw_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \libresocsim_dataw_pads_out_payload_clk $1\libresocsim_dataw_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1063.5-1063.52" - process $proc$ls180.v:1063$2996 - assign { } { } - assign $0\libresocsim_dataw_pads_out_payload_cmd_o[0:0] 1'0 - sync always - update \libresocsim_dataw_pads_out_payload_cmd_o $0\libresocsim_dataw_pads_out_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1064.5-1064.53" - process $proc$ls180.v:1064$2997 - assign { } { } - assign $0\libresocsim_dataw_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - update \libresocsim_dataw_pads_out_payload_cmd_oe $0\libresocsim_dataw_pads_out_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1065.11-1065.59" - process $proc$ls180.v:1065$2998 - assign { } { } - assign $1\libresocsim_dataw_pads_out_payload_data_o[3:0] 4'0000 - sync always - sync init - update \libresocsim_dataw_pads_out_payload_data_o $1\libresocsim_dataw_pads_out_payload_data_o[3:0] - end - attribute \src "ls180.v:1066.5-1066.54" - process $proc$ls180.v:1066$2999 - assign { } { } - assign $1\libresocsim_dataw_pads_out_payload_data_oe[0:0] 1'0 - sync always - sync init - update \libresocsim_dataw_pads_out_payload_data_oe $1\libresocsim_dataw_pads_out_payload_data_oe[0:0] - end - attribute \src "ls180.v:1067.5-1067.40" - process $proc$ls180.v:1067$3000 - assign { } { } - assign $1\libresocsim_dataw_sink_valid[0:0] 1'0 - sync always - sync init - update \libresocsim_dataw_sink_valid $1\libresocsim_dataw_sink_valid[0:0] - end - attribute \src "ls180.v:1068.5-1068.40" - process $proc$ls180.v:1068$3001 - assign { } { } - assign $1\libresocsim_dataw_sink_ready[0:0] 1'0 - sync always - sync init - update \libresocsim_dataw_sink_ready $1\libresocsim_dataw_sink_ready[0:0] - end - attribute \src "ls180.v:1069.5-1069.40" - process $proc$ls180.v:1069$3002 - assign { } { } - assign $1\libresocsim_dataw_sink_first[0:0] 1'0 - sync always - sync init - update \libresocsim_dataw_sink_first $1\libresocsim_dataw_sink_first[0:0] - end - attribute \src "ls180.v:1070.5-1070.39" - process $proc$ls180.v:1070$3003 - assign { } { } - assign $1\libresocsim_dataw_sink_last[0:0] 1'0 - sync always - sync init - update \libresocsim_dataw_sink_last $1\libresocsim_dataw_sink_last[0:0] - end - attribute \src "ls180.v:1071.11-1071.53" - process $proc$ls180.v:1071$3004 - assign { } { } - assign $1\libresocsim_dataw_sink_payload_data[7:0] 8'00000000 - sync always - sync init - update \libresocsim_dataw_sink_payload_data $1\libresocsim_dataw_sink_payload_data[7:0] - end - attribute \src "ls180.v:1072.5-1072.34" - process $proc$ls180.v:1072$3005 - assign { } { } - assign $1\libresocsim_dataw_stop[0:0] 1'0 - sync always - sync init - update \libresocsim_dataw_stop $1\libresocsim_dataw_stop[0:0] - end - attribute \src "ls180.v:1073.11-1073.41" - process $proc$ls180.v:1073$3006 - assign { } { } - assign $1\libresocsim_dataw_count[7:0] 8'00000000 - sync always - sync init - update \libresocsim_dataw_count $1\libresocsim_dataw_count[7:0] - end - attribute \src "ls180.v:1074.5-1074.51" - process $proc$ls180.v:1074$3007 - assign { } { } - assign $0\libresocsim_dataw_pads_in_pads_in_valid[0:0] 1'0 - sync always - update \libresocsim_dataw_pads_in_pads_in_valid $0\libresocsim_dataw_pads_in_pads_in_valid[0:0] - sync init - end - attribute \src "ls180.v:1076.5-1076.51" - process $proc$ls180.v:1076$3008 - assign { } { } - assign $0\libresocsim_dataw_pads_in_pads_in_first[0:0] 1'0 - sync always - update \libresocsim_dataw_pads_in_pads_in_first $0\libresocsim_dataw_pads_in_pads_in_first[0:0] - sync init - end - attribute \src "ls180.v:1077.5-1077.50" - process $proc$ls180.v:1077$3009 - assign { } { } - assign $0\libresocsim_dataw_pads_in_pads_in_last[0:0] 1'0 - sync always - update \libresocsim_dataw_pads_in_pads_in_last $0\libresocsim_dataw_pads_in_pads_in_last[0:0] - sync init - end - attribute \src "ls180.v:1078.5-1078.57" - process $proc$ls180.v:1078$3010 - assign { } { } - assign $0\libresocsim_dataw_pads_in_pads_in_payload_clk[0:0] 1'0 - sync always - update \libresocsim_dataw_pads_in_pads_in_payload_clk $0\libresocsim_dataw_pads_in_pads_in_payload_clk[0:0] - sync init - end - attribute \src "ls180.v:1079.5-1079.59" - process $proc$ls180.v:1079$3011 - assign { } { } - assign $0\libresocsim_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0 - sync always - update \libresocsim_dataw_pads_in_pads_in_payload_cmd_i $0\libresocsim_dataw_pads_in_pads_in_payload_cmd_i[0:0] - sync init - end - attribute \src "ls180.v:108.5-108.44" - process $proc$ls180.v:108$2585 - assign { } { } - assign $1\main_libresocsim_converter0_skip[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0] - end - attribute \src "ls180.v:1080.5-1080.59" - process $proc$ls180.v:1080$3012 - assign { } { } - assign $0\libresocsim_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0 - sync always - update \libresocsim_dataw_pads_in_pads_in_payload_cmd_o $0\libresocsim_dataw_pads_in_pads_in_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1081.5-1081.60" - process $proc$ls180.v:1081$3013 - assign { } { } - assign $0\libresocsim_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 - sync always - update \libresocsim_dataw_pads_in_pads_in_payload_cmd_oe $0\libresocsim_dataw_pads_in_pads_in_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1082.11-1082.66" - process $proc$ls180.v:1082$3014 - assign { } { } - assign $0\libresocsim_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000 - sync always - update \libresocsim_dataw_pads_in_pads_in_payload_data_i $0\libresocsim_dataw_pads_in_pads_in_payload_data_i[3:0] - sync init - end - attribute \src "ls180.v:1083.11-1083.66" - process $proc$ls180.v:1083$3015 - assign { } { } - assign $0\libresocsim_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000 - sync always - update \libresocsim_dataw_pads_in_pads_in_payload_data_o $0\libresocsim_dataw_pads_in_pads_in_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1084.5-1084.61" - process $proc$ls180.v:1084$3016 - assign { } { } - assign $0\libresocsim_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0 - sync always - update \libresocsim_dataw_pads_in_pads_in_payload_data_oe $0\libresocsim_dataw_pads_in_pads_in_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1085.5-1085.35" - process $proc$ls180.v:1085$3017 - assign { } { } - assign $1\libresocsim_dataw_start[0:0] 1'0 - sync always - sync init - update \libresocsim_dataw_start $1\libresocsim_dataw_start[0:0] - end - attribute \src "ls180.v:1086.5-1086.35" - process $proc$ls180.v:1086$3018 - assign { } { } - assign $1\libresocsim_dataw_valid[0:0] 1'0 - sync always - sync init - update \libresocsim_dataw_valid $1\libresocsim_dataw_valid[0:0] - end - attribute \src "ls180.v:1087.5-1087.35" - process $proc$ls180.v:1087$3019 - assign { } { } - assign $1\libresocsim_dataw_error[0:0] 1'0 - sync always - sync init - update \libresocsim_dataw_error $1\libresocsim_dataw_error[0:0] - end - attribute \src "ls180.v:1089.5-1089.48" - process $proc$ls180.v:1089$3020 - assign { } { } - assign $0\libresocsim_dataw_crcr_pads_in_ready[0:0] 1'0 - sync always - update \libresocsim_dataw_crcr_pads_in_ready $0\libresocsim_dataw_crcr_pads_in_ready[0:0] - sync init - end - attribute \src "ls180.v:109.5-109.47" - process $proc$ls180.v:109$2586 - assign { } { } - assign $1\main_libresocsim_converter0_counter[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0] - end - attribute \src "ls180.v:1100.5-1100.55" - process $proc$ls180.v:1100$3021 - assign { } { } - assign $1\libresocsim_dataw_crcr_source_source_ready0[0:0] 1'0 - sync always - sync init - update \libresocsim_dataw_crcr_source_source_ready0 $1\libresocsim_dataw_crcr_source_source_ready0[0:0] - end - attribute \src "ls180.v:1105.5-1105.38" - process $proc$ls180.v:1105$3022 - assign { } { } - assign $1\libresocsim_dataw_crcr_run[0:0] 1'0 - sync always - sync init - update \libresocsim_dataw_crcr_run $1\libresocsim_dataw_crcr_run[0:0] - end - attribute \src "ls180.v:1108.5-1108.55" - process $proc$ls180.v:1108$3023 - assign { } { } - assign $0\libresocsim_dataw_crcr_converter_sink_first[0:0] 1'0 - sync always - update \libresocsim_dataw_crcr_converter_sink_first $0\libresocsim_dataw_crcr_converter_sink_first[0:0] - sync init - end - attribute \src "ls180.v:1109.5-1109.54" - process $proc$ls180.v:1109$3024 - assign { } { } - assign $0\libresocsim_dataw_crcr_converter_sink_last[0:0] 1'0 - sync always - update \libresocsim_dataw_crcr_converter_sink_last $0\libresocsim_dataw_crcr_converter_sink_last[0:0] - sync init - end - attribute \src "ls180.v:111.12-111.53" - process $proc$ls180.v:111$2587 - assign { } { } - assign $1\main_libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_converter0_dat_r $1\main_libresocsim_converter0_dat_r[63:0] - end - attribute \src "ls180.v:1113.5-1113.57" - process $proc$ls180.v:1113$3025 - assign { } { } - assign $1\libresocsim_dataw_crcr_converter_source_first[0:0] 1'0 - sync always - sync init - update \libresocsim_dataw_crcr_converter_source_first $1\libresocsim_dataw_crcr_converter_source_first[0:0] - end - attribute \src "ls180.v:1114.5-1114.56" - process $proc$ls180.v:1114$3026 - assign { } { } - assign $1\libresocsim_dataw_crcr_converter_source_last[0:0] 1'0 - sync always - sync init - update \libresocsim_dataw_crcr_converter_source_last $1\libresocsim_dataw_crcr_converter_source_last[0:0] - end - attribute \src "ls180.v:1115.11-1115.70" - process $proc$ls180.v:1115$3027 - assign { } { } - assign $1\libresocsim_dataw_crcr_converter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \libresocsim_dataw_crcr_converter_source_payload_data $1\libresocsim_dataw_crcr_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:1116.11-1116.83" - process $proc$ls180.v:1116$3028 - assign { } { } - assign $1\libresocsim_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000 - sync always - sync init - update \libresocsim_dataw_crcr_converter_source_payload_valid_token_count $1\libresocsim_dataw_crcr_converter_source_payload_valid_token_count[3:0] - end - attribute \src "ls180.v:1117.11-1117.56" - process $proc$ls180.v:1117$3029 - assign { } { } - assign $1\libresocsim_dataw_crcr_converter_demux[2:0] 3'000 - sync always - sync init - update \libresocsim_dataw_crcr_converter_demux $1\libresocsim_dataw_crcr_converter_demux[2:0] - end - attribute \src "ls180.v:1119.5-1119.55" - process $proc$ls180.v:1119$3030 - assign { } { } - assign $1\libresocsim_dataw_crcr_converter_strobe_all[0:0] 1'0 - sync always - sync init - update \libresocsim_dataw_crcr_converter_strobe_all $1\libresocsim_dataw_crcr_converter_strobe_all[0:0] - end - attribute \src "ls180.v:112.12-112.71" - process $proc$ls180.v:112$2588 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0] - end - attribute \src "ls180.v:113.12-113.73" - process $proc$ls180.v:113$2589 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:1130.5-1130.51" - process $proc$ls180.v:1130$3031 - assign { } { } - assign $1\libresocsim_dataw_crcr_buf_source_valid[0:0] 1'0 - sync always - sync init - update \libresocsim_dataw_crcr_buf_source_valid $1\libresocsim_dataw_crcr_buf_source_valid[0:0] - end - attribute \src "ls180.v:1132.5-1132.51" - process $proc$ls180.v:1132$3032 - assign { } { } - assign $1\libresocsim_dataw_crcr_buf_source_first[0:0] 1'0 - sync always - sync init - update \libresocsim_dataw_crcr_buf_source_first $1\libresocsim_dataw_crcr_buf_source_first[0:0] - end - attribute \src "ls180.v:1133.5-1133.50" - process $proc$ls180.v:1133$3033 - assign { } { } - assign $1\libresocsim_dataw_crcr_buf_source_last[0:0] 1'0 - sync always - sync init - update \libresocsim_dataw_crcr_buf_source_last $1\libresocsim_dataw_crcr_buf_source_last[0:0] - end - attribute \src "ls180.v:1134.11-1134.64" - process $proc$ls180.v:1134$3034 - assign { } { } - assign $1\libresocsim_dataw_crcr_buf_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \libresocsim_dataw_crcr_buf_source_payload_data $1\libresocsim_dataw_crcr_buf_source_payload_data[7:0] - end - attribute \src "ls180.v:1135.5-1135.40" - process $proc$ls180.v:1135$3035 - assign { } { } - assign $1\libresocsim_dataw_crcr_reset[0:0] 1'0 - sync always - sync init - update \libresocsim_dataw_crcr_reset $1\libresocsim_dataw_crcr_reset[0:0] - end - attribute \src "ls180.v:1138.5-1138.51" - process $proc$ls180.v:1138$3036 - assign { } { } - assign $0\libresocsim_datar_pads_in_pads_in_first[0:0] 1'0 - sync always - update \libresocsim_datar_pads_in_pads_in_first $0\libresocsim_datar_pads_in_pads_in_first[0:0] - sync init - end - attribute \src "ls180.v:1139.5-1139.50" - process $proc$ls180.v:1139$3037 - assign { } { } - assign $0\libresocsim_datar_pads_in_pads_in_last[0:0] 1'0 - sync always - update \libresocsim_datar_pads_in_pads_in_last $0\libresocsim_datar_pads_in_pads_in_last[0:0] - sync init - end - attribute \src "ls180.v:1140.5-1140.57" - process $proc$ls180.v:1140$3038 - assign { } { } - assign $0\libresocsim_datar_pads_in_pads_in_payload_clk[0:0] 1'0 - sync always - update \libresocsim_datar_pads_in_pads_in_payload_clk $0\libresocsim_datar_pads_in_pads_in_payload_clk[0:0] - sync init - end - attribute \src "ls180.v:1142.5-1142.59" - process $proc$ls180.v:1142$3039 - assign { } { } - assign $0\libresocsim_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0 - sync always - update \libresocsim_datar_pads_in_pads_in_payload_cmd_o $0\libresocsim_datar_pads_in_pads_in_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1143.5-1143.60" - process $proc$ls180.v:1143$3040 - assign { } { } - assign $0\libresocsim_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 - sync always - update \libresocsim_datar_pads_in_pads_in_payload_cmd_oe $0\libresocsim_datar_pads_in_pads_in_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1145.11-1145.66" - process $proc$ls180.v:1145$3041 - assign { } { } - assign $0\libresocsim_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000 - sync always - update \libresocsim_datar_pads_in_pads_in_payload_data_o $0\libresocsim_datar_pads_in_pads_in_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1146.5-1146.61" - process $proc$ls180.v:1146$3042 - assign { } { } - assign $0\libresocsim_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0 - sync always - update \libresocsim_datar_pads_in_pads_in_payload_data_oe $0\libresocsim_datar_pads_in_pads_in_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1148.5-1148.50" - process $proc$ls180.v:1148$3043 - assign { } { } - assign $1\libresocsim_datar_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \libresocsim_datar_pads_out_payload_clk $1\libresocsim_datar_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1149.5-1149.52" - process $proc$ls180.v:1149$3044 - assign { } { } - assign $0\libresocsim_datar_pads_out_payload_cmd_o[0:0] 1'0 - sync always - update \libresocsim_datar_pads_out_payload_cmd_o $0\libresocsim_datar_pads_out_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:115.11-115.69" - process $proc$ls180.v:115$2590 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0] - end - attribute \src "ls180.v:1150.5-1150.53" - process $proc$ls180.v:1150$3045 - assign { } { } - assign $0\libresocsim_datar_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - update \libresocsim_datar_pads_out_payload_cmd_oe $0\libresocsim_datar_pads_out_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1151.11-1151.59" - process $proc$ls180.v:1151$3046 - assign { } { } - assign $0\libresocsim_datar_pads_out_payload_data_o[3:0] 4'0000 - sync always - update \libresocsim_datar_pads_out_payload_data_o $0\libresocsim_datar_pads_out_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1152.5-1152.54" - process $proc$ls180.v:1152$3047 - assign { } { } - assign $0\libresocsim_datar_pads_out_payload_data_oe[0:0] 1'0 - sync always - update \libresocsim_datar_pads_out_payload_data_oe $0\libresocsim_datar_pads_out_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1153.5-1153.40" - process $proc$ls180.v:1153$3048 - assign { } { } - assign $1\libresocsim_datar_sink_valid[0:0] 1'0 - sync always - sync init - update \libresocsim_datar_sink_valid $1\libresocsim_datar_sink_valid[0:0] - end - attribute \src "ls180.v:1154.5-1154.40" - process $proc$ls180.v:1154$3049 - assign { } { } - assign $1\libresocsim_datar_sink_ready[0:0] 1'0 - sync always - sync init - update \libresocsim_datar_sink_ready $1\libresocsim_datar_sink_ready[0:0] - end - attribute \src "ls180.v:1155.5-1155.39" - process $proc$ls180.v:1155$3050 - assign { } { } - assign $1\libresocsim_datar_sink_last[0:0] 1'0 - sync always - sync init - update \libresocsim_datar_sink_last $1\libresocsim_datar_sink_last[0:0] - end - attribute \src "ls180.v:1156.11-1156.62" - process $proc$ls180.v:1156$3051 - assign { } { } - assign $1\libresocsim_datar_sink_payload_block_length[9:0] 10'0000000000 - sync always - sync init - update \libresocsim_datar_sink_payload_block_length $1\libresocsim_datar_sink_payload_block_length[9:0] - end - attribute \src "ls180.v:1157.5-1157.42" - process $proc$ls180.v:1157$3052 - assign { } { } - assign $1\libresocsim_datar_source_valid[0:0] 1'0 - sync always - sync init - update \libresocsim_datar_source_valid $1\libresocsim_datar_source_valid[0:0] - end - attribute \src "ls180.v:1158.5-1158.42" - process $proc$ls180.v:1158$3053 - assign { } { } - assign $1\libresocsim_datar_source_ready[0:0] 1'0 - sync always - sync init - update \libresocsim_datar_source_ready $1\libresocsim_datar_source_ready[0:0] - end - attribute \src "ls180.v:1159.5-1159.42" - process $proc$ls180.v:1159$3054 - assign { } { } - assign $0\libresocsim_datar_source_first[0:0] 1'0 - sync always - update \libresocsim_datar_source_first $0\libresocsim_datar_source_first[0:0] - sync init - end - attribute \src "ls180.v:116.5-116.63" - process $proc$ls180.v:116$2591 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_cyc $1\main_libresocsim_interface1_converted_interface_cyc[0:0] - end - attribute \src "ls180.v:1160.5-1160.41" - process $proc$ls180.v:1160$3055 - assign { } { } - assign $1\libresocsim_datar_source_last[0:0] 1'0 - sync always - sync init - update \libresocsim_datar_source_last $1\libresocsim_datar_source_last[0:0] - end - attribute \src "ls180.v:1161.11-1161.55" - process $proc$ls180.v:1161$3056 - assign { } { } - assign $1\libresocsim_datar_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \libresocsim_datar_source_payload_data $1\libresocsim_datar_source_payload_data[7:0] - end - attribute \src "ls180.v:1162.11-1162.57" - process $proc$ls180.v:1162$3057 - assign { } { } - assign $1\libresocsim_datar_source_payload_status[2:0] 3'000 - sync always - sync init - update \libresocsim_datar_source_payload_status $1\libresocsim_datar_source_payload_status[2:0] - end - attribute \src "ls180.v:1163.5-1163.34" - process $proc$ls180.v:1163$3058 - assign { } { } - assign $1\libresocsim_datar_stop[0:0] 1'0 - sync always - sync init - update \libresocsim_datar_stop $1\libresocsim_datar_stop[0:0] - end - attribute \src "ls180.v:1164.12-1164.50" - process $proc$ls180.v:1164$3059 - assign { } { } - assign $1\libresocsim_datar_timeout[31:0] 500000 - sync always - sync init - update \libresocsim_datar_timeout $1\libresocsim_datar_timeout[31:0] - end - attribute \src "ls180.v:1165.11-1165.42" - process $proc$ls180.v:1165$3060 - assign { } { } - assign $1\libresocsim_datar_count[9:0] 10'0000000000 - sync always - sync init - update \libresocsim_datar_count $1\libresocsim_datar_count[9:0] - end - attribute \src "ls180.v:1167.5-1167.49" - process $proc$ls180.v:1167$3061 - assign { } { } - assign $0\libresocsim_datar_datar_pads_in_ready[0:0] 1'0 - sync always - update \libresocsim_datar_datar_pads_in_ready $0\libresocsim_datar_datar_pads_in_ready[0:0] - sync init - end - attribute \src "ls180.v:117.5-117.63" - process $proc$ls180.v:117$2592 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_stb $1\main_libresocsim_interface1_converted_interface_stb[0:0] - end - attribute \src "ls180.v:1178.5-1178.56" - process $proc$ls180.v:1178$3062 - assign { } { } - assign $1\libresocsim_datar_datar_source_source_ready0[0:0] 1'0 - sync always - sync init - update \libresocsim_datar_datar_source_source_ready0 $1\libresocsim_datar_datar_source_source_ready0[0:0] - end - attribute \src "ls180.v:1183.5-1183.39" - process $proc$ls180.v:1183$3063 - assign { } { } - assign $1\libresocsim_datar_datar_run[0:0] 1'0 - sync always - sync init - update \libresocsim_datar_datar_run $1\libresocsim_datar_datar_run[0:0] - end - attribute \src "ls180.v:1186.5-1186.56" - process $proc$ls180.v:1186$3064 - assign { } { } - assign $0\libresocsim_datar_datar_converter_sink_first[0:0] 1'0 - sync always - update \libresocsim_datar_datar_converter_sink_first $0\libresocsim_datar_datar_converter_sink_first[0:0] - sync init - end - attribute \src "ls180.v:1187.5-1187.55" - process $proc$ls180.v:1187$3065 - assign { } { } - assign $0\libresocsim_datar_datar_converter_sink_last[0:0] 1'0 - sync always - update \libresocsim_datar_datar_converter_sink_last $0\libresocsim_datar_datar_converter_sink_last[0:0] - sync init - end - attribute \src "ls180.v:119.5-119.62" - process $proc$ls180.v:119$2593 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_we $1\main_libresocsim_interface1_converted_interface_we[0:0] - end - attribute \src "ls180.v:1191.5-1191.58" - process $proc$ls180.v:1191$3066 - assign { } { } - assign $1\libresocsim_datar_datar_converter_source_first[0:0] 1'0 - sync always - sync init - update \libresocsim_datar_datar_converter_source_first $1\libresocsim_datar_datar_converter_source_first[0:0] - end - attribute \src "ls180.v:1192.5-1192.57" - process $proc$ls180.v:1192$3067 - assign { } { } - assign $1\libresocsim_datar_datar_converter_source_last[0:0] 1'0 - sync always - sync init - update \libresocsim_datar_datar_converter_source_last $1\libresocsim_datar_datar_converter_source_last[0:0] - end - attribute \src "ls180.v:1193.11-1193.71" - process $proc$ls180.v:1193$3068 - assign { } { } - assign $1\libresocsim_datar_datar_converter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \libresocsim_datar_datar_converter_source_payload_data $1\libresocsim_datar_datar_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:1194.11-1194.84" - process $proc$ls180.v:1194$3069 - assign { } { } - assign $1\libresocsim_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00 - sync always - sync init - update \libresocsim_datar_datar_converter_source_payload_valid_token_count $1\libresocsim_datar_datar_converter_source_payload_valid_token_count[1:0] - end - attribute \src "ls180.v:1195.5-1195.51" - process $proc$ls180.v:1195$3070 - assign { } { } - assign $1\libresocsim_datar_datar_converter_demux[0:0] 1'0 - sync always - sync init - update \libresocsim_datar_datar_converter_demux $1\libresocsim_datar_datar_converter_demux[0:0] - end - attribute \src "ls180.v:1197.5-1197.56" - process $proc$ls180.v:1197$3071 - assign { } { } - assign $1\libresocsim_datar_datar_converter_strobe_all[0:0] 1'0 - sync always - sync init - update \libresocsim_datar_datar_converter_strobe_all $1\libresocsim_datar_datar_converter_strobe_all[0:0] - end - attribute \src "ls180.v:120.11-120.69" - process $proc$ls180.v:120$2594 - assign { } { } - assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000 - sync always - update \main_libresocsim_interface1_converted_interface_cti $0\main_libresocsim_interface1_converted_interface_cti[2:0] - sync init - end - attribute \src "ls180.v:1208.5-1208.52" - process $proc$ls180.v:1208$3072 - assign { } { } - assign $1\libresocsim_datar_datar_buf_source_valid[0:0] 1'0 - sync always - sync init - update \libresocsim_datar_datar_buf_source_valid $1\libresocsim_datar_datar_buf_source_valid[0:0] - end - attribute \src "ls180.v:121.11-121.69" - process $proc$ls180.v:121$2595 - assign { } { } - assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00 - sync always - update \main_libresocsim_interface1_converted_interface_bte $0\main_libresocsim_interface1_converted_interface_bte[1:0] - sync init - end - attribute \src "ls180.v:1210.5-1210.52" - process $proc$ls180.v:1210$3073 - assign { } { } - assign $1\libresocsim_datar_datar_buf_source_first[0:0] 1'0 - sync always - sync init - update \libresocsim_datar_datar_buf_source_first $1\libresocsim_datar_datar_buf_source_first[0:0] - end - attribute \src "ls180.v:1211.5-1211.51" - process $proc$ls180.v:1211$3074 - assign { } { } - assign $1\libresocsim_datar_datar_buf_source_last[0:0] 1'0 - sync always - sync init - update \libresocsim_datar_datar_buf_source_last $1\libresocsim_datar_datar_buf_source_last[0:0] - end - attribute \src "ls180.v:1212.11-1212.65" - process $proc$ls180.v:1212$3075 - assign { } { } - assign $1\libresocsim_datar_datar_buf_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \libresocsim_datar_datar_buf_source_payload_data $1\libresocsim_datar_datar_buf_source_payload_data[7:0] - end - attribute \src "ls180.v:1213.5-1213.41" - process $proc$ls180.v:1213$3076 - assign { } { } - assign $1\libresocsim_datar_datar_reset[0:0] 1'0 - sync always - sync init - update \libresocsim_datar_datar_reset $1\libresocsim_datar_datar_reset[0:0] - end - attribute \src "ls180.v:1215.5-1215.36" - process $proc$ls180.v:1215$3077 - assign { } { } - assign $1\libresocsim_sdpads_cmd_i[0:0] 1'0 - sync always - sync init - update \libresocsim_sdpads_cmd_i $1\libresocsim_sdpads_cmd_i[0:0] - end - attribute \src "ls180.v:1218.11-1218.43" - process $proc$ls180.v:1218$3078 - assign { } { } - assign $1\libresocsim_sdpads_data_i[3:0] 4'0000 - sync always - sync init - update \libresocsim_sdpads_data_i $1\libresocsim_sdpads_data_i[3:0] - end - attribute \src "ls180.v:123.5-123.44" - process $proc$ls180.v:123$2596 - assign { } { } - assign $1\main_libresocsim_converter1_skip[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0] - end - attribute \src "ls180.v:1231.12-1231.59" - process $proc$ls180.v:1231$3079 - assign { } { } - assign $1\libresocsim_sdcore_cmd_argument_storage[31:0] 0 - sync always - sync init - update \libresocsim_sdcore_cmd_argument_storage $1\libresocsim_sdcore_cmd_argument_storage[31:0] - end - attribute \src "ls180.v:1232.5-1232.46" - process $proc$ls180.v:1232$3080 - assign { } { } - assign $1\libresocsim_sdcore_cmd_argument_re[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_cmd_argument_re $1\libresocsim_sdcore_cmd_argument_re[0:0] - end - attribute \src "ls180.v:1233.12-1233.58" - process $proc$ls180.v:1233$3081 - assign { } { } - assign $1\libresocsim_sdcore_cmd_command_storage[31:0] 0 - sync always - sync init - update \libresocsim_sdcore_cmd_command_storage $1\libresocsim_sdcore_cmd_command_storage[31:0] - end - attribute \src "ls180.v:1234.5-1234.45" - process $proc$ls180.v:1234$3082 - assign { } { } - assign $1\libresocsim_sdcore_cmd_command_re[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_cmd_command_re $1\libresocsim_sdcore_cmd_command_re[0:0] - end - attribute \src "ls180.v:1238.5-1238.41" - process $proc$ls180.v:1238$3083 - assign { } { } - assign $0\libresocsim_sdcore_cmd_send_w[0:0] 1'0 - sync always - update \libresocsim_sdcore_cmd_send_w $0\libresocsim_sdcore_cmd_send_w[0:0] - sync init - end - attribute \src "ls180.v:1239.13-1239.60" - process $proc$ls180.v:1239$3084 - assign { } { } - assign $1\libresocsim_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \libresocsim_sdcore_cmd_response_status $1\libresocsim_sdcore_cmd_response_status[127:0] - end - attribute \src "ls180.v:124.5-124.47" - process $proc$ls180.v:124$2597 - assign { } { } - assign $1\main_libresocsim_converter1_counter[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0] - end - attribute \src "ls180.v:1245.11-1245.58" - process $proc$ls180.v:1245$3085 - assign { } { } - assign $1\libresocsim_sdcore_block_length_storage[9:0] 10'0000000000 - sync always - sync init - update \libresocsim_sdcore_block_length_storage $1\libresocsim_sdcore_block_length_storage[9:0] - end - attribute \src "ls180.v:1246.5-1246.46" - process $proc$ls180.v:1246$3086 - assign { } { } - assign $1\libresocsim_sdcore_block_length_re[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_block_length_re $1\libresocsim_sdcore_block_length_re[0:0] - end - attribute \src "ls180.v:1247.12-1247.58" - process $proc$ls180.v:1247$3087 - assign { } { } - assign $1\libresocsim_sdcore_block_count_storage[31:0] 0 - sync always - sync init - update \libresocsim_sdcore_block_count_storage $1\libresocsim_sdcore_block_count_storage[31:0] - end - attribute \src "ls180.v:1248.5-1248.45" - process $proc$ls180.v:1248$3088 - assign { } { } - assign $1\libresocsim_sdcore_block_count_re[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_block_count_re $1\libresocsim_sdcore_block_count_re[0:0] - end - attribute \src "ls180.v:1249.11-1249.58" - process $proc$ls180.v:1249$3089 - assign { } { } - assign $1\libresocsim_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - sync always - sync init - update \libresocsim_sdcore_crc7_inserter_crcreg0 $1\libresocsim_sdcore_crc7_inserter_crcreg0[6:0] - end - attribute \src "ls180.v:126.12-126.53" - process $proc$ls180.v:126$2598 - assign { } { } - assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0] - end - attribute \src "ls180.v:1291.11-1291.54" - process $proc$ls180.v:1291$3090 - assign { } { } - assign $1\libresocsim_sdcore_crc7_inserter_crc[6:0] 7'0000000 - sync always - sync init - update \libresocsim_sdcore_crc7_inserter_crc $1\libresocsim_sdcore_crc7_inserter_crc[6:0] - end - attribute \src "ls180.v:1295.5-1295.56" - process $proc$ls180.v:1295$3091 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_sink_ready[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_sink_ready $1\libresocsim_sdcore_crc16_inserter_sink_ready[0:0] - end - attribute \src "ls180.v:1299.5-1299.58" - process $proc$ls180.v:1299$3092 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_source_valid[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_source_valid $1\libresocsim_sdcore_crc16_inserter_source_valid[0:0] - end - attribute \src "ls180.v:1300.5-1300.58" - process $proc$ls180.v:1300$3093 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_source_ready[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_source_ready $1\libresocsim_sdcore_crc16_inserter_source_ready[0:0] - end - attribute \src "ls180.v:1301.5-1301.58" - process $proc$ls180.v:1301$3094 - assign { } { } - assign $0\libresocsim_sdcore_crc16_inserter_source_first[0:0] 1'0 - sync always - update \libresocsim_sdcore_crc16_inserter_source_first $0\libresocsim_sdcore_crc16_inserter_source_first[0:0] - sync init - end - attribute \src "ls180.v:1302.5-1302.57" - process $proc$ls180.v:1302$3095 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_source_last[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_source_last $1\libresocsim_sdcore_crc16_inserter_source_last[0:0] - end - attribute \src "ls180.v:1303.11-1303.71" - process $proc$ls180.v:1303$3096 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_source_payload_data $1\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] - end - attribute \src "ls180.v:1304.11-1304.55" - process $proc$ls180.v:1304$3097 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_cnt[2:0] 3'000 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_cnt $1\libresocsim_sdcore_crc16_inserter_cnt[2:0] - end - attribute \src "ls180.v:1305.12-1305.66" - process $proc$ls180.v:1305$3098 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 $1\libresocsim_sdcore_crc16_inserter_crc0_crcreg0[15:0] - end - attribute \src "ls180.v:1309.12-1309.62" - process $proc$ls180.v:1309$3099 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_crc0_crc $1\libresocsim_sdcore_crc16_inserter_crc0_crc[15:0] - end - attribute \src "ls180.v:1312.12-1312.66" - process $proc$ls180.v:1312$3100 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 $1\libresocsim_sdcore_crc16_inserter_crc1_crcreg0[15:0] - end - attribute \src "ls180.v:1316.12-1316.62" - process $proc$ls180.v:1316$3101 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_crc1_crc $1\libresocsim_sdcore_crc16_inserter_crc1_crc[15:0] - end - attribute \src "ls180.v:1319.12-1319.66" - process $proc$ls180.v:1319$3102 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 $1\libresocsim_sdcore_crc16_inserter_crc2_crcreg0[15:0] - end - attribute \src "ls180.v:1323.12-1323.62" - process $proc$ls180.v:1323$3103 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_crc2_crc $1\libresocsim_sdcore_crc16_inserter_crc2_crc[15:0] - end - attribute \src "ls180.v:1326.12-1326.66" - process $proc$ls180.v:1326$3104 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 $1\libresocsim_sdcore_crc16_inserter_crc3_crcreg0[15:0] - end - attribute \src "ls180.v:133.5-133.40" - process $proc$ls180.v:133$2599 - assign { } { } - assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 - sync always - sync init - update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] - end - attribute \src "ls180.v:1330.12-1330.62" - process $proc$ls180.v:1330$3105 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_crc3_crc $1\libresocsim_sdcore_crc16_inserter_crc3_crc[15:0] - end - attribute \src "ls180.v:1333.12-1333.61" - process $proc$ls180.v:1333$3106 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_crctmp0 $1\libresocsim_sdcore_crc16_inserter_crctmp0[15:0] - end - attribute \src "ls180.v:1334.12-1334.61" - process $proc$ls180.v:1334$3107 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_crctmp1 $1\libresocsim_sdcore_crc16_inserter_crctmp1[15:0] - end - attribute \src "ls180.v:1335.12-1335.61" - process $proc$ls180.v:1335$3108 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_crctmp2 $1\libresocsim_sdcore_crc16_inserter_crctmp2[15:0] - end - attribute \src "ls180.v:1336.12-1336.61" - process $proc$ls180.v:1336$3109 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_crctmp3 $1\libresocsim_sdcore_crc16_inserter_crctmp3[15:0] - end - attribute \src "ls180.v:1337.5-1337.55" - process $proc$ls180.v:1337$3110 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_sink_valid[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_sink_valid $1\libresocsim_sdcore_crc16_checker_sink_valid[0:0] - end - attribute \src "ls180.v:1338.5-1338.55" - process $proc$ls180.v:1338$3111 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_sink_ready[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_sink_ready $1\libresocsim_sdcore_crc16_checker_sink_ready[0:0] - end - attribute \src "ls180.v:1339.5-1339.55" - process $proc$ls180.v:1339$3112 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_sink_first[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_sink_first $1\libresocsim_sdcore_crc16_checker_sink_first[0:0] - end - attribute \src "ls180.v:1340.5-1340.54" - process $proc$ls180.v:1340$3113 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_sink_last[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_sink_last $1\libresocsim_sdcore_crc16_checker_sink_last[0:0] - end - attribute \src "ls180.v:1341.11-1341.68" - process $proc$ls180.v:1341$3114 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_sink_payload_data $1\libresocsim_sdcore_crc16_checker_sink_payload_data[7:0] - end - attribute \src "ls180.v:1342.5-1342.57" - process $proc$ls180.v:1342$3115 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_source_valid[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_source_valid $1\libresocsim_sdcore_crc16_checker_source_valid[0:0] - end - attribute \src "ls180.v:1344.5-1344.57" - process $proc$ls180.v:1344$3116 - assign { } { } - assign $0\libresocsim_sdcore_crc16_checker_source_first[0:0] 1'0 - sync always - update \libresocsim_sdcore_crc16_checker_source_first $0\libresocsim_sdcore_crc16_checker_source_first[0:0] - sync init - end - attribute \src "ls180.v:1347.11-1347.54" - process $proc$ls180.v:1347$3117 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_val[7:0] 8'00000000 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_val $1\libresocsim_sdcore_crc16_checker_val[7:0] - end - attribute \src "ls180.v:1348.11-1348.54" - process $proc$ls180.v:1348$3118 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_cnt[3:0] 4'0000 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_cnt $1\libresocsim_sdcore_crc16_checker_cnt[3:0] - end - attribute \src "ls180.v:1349.12-1349.65" - process $proc$ls180.v:1349$3119 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_crc0_crcreg0 $1\libresocsim_sdcore_crc16_checker_crc0_crcreg0[15:0] - end - attribute \src "ls180.v:1353.12-1353.61" - process $proc$ls180.v:1353$3120 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_crc0_crc $1\libresocsim_sdcore_crc16_checker_crc0_crc[15:0] - end - attribute \src "ls180.v:1354.5-1354.53" - process $proc$ls180.v:1354$3121 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_crc0_clr[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_crc0_clr $1\libresocsim_sdcore_crc16_checker_crc0_clr[0:0] - end - attribute \src "ls180.v:1356.12-1356.65" - process $proc$ls180.v:1356$3122 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_crc1_crcreg0 $1\libresocsim_sdcore_crc16_checker_crc1_crcreg0[15:0] - end - attribute \src "ls180.v:1360.12-1360.61" - process $proc$ls180.v:1360$3123 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_crc1_crc $1\libresocsim_sdcore_crc16_checker_crc1_crc[15:0] - end - attribute \src "ls180.v:1361.5-1361.53" - process $proc$ls180.v:1361$3124 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_crc1_clr[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_crc1_clr $1\libresocsim_sdcore_crc16_checker_crc1_clr[0:0] - end - attribute \src "ls180.v:1363.12-1363.65" - process $proc$ls180.v:1363$3125 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_crc2_crcreg0 $1\libresocsim_sdcore_crc16_checker_crc2_crcreg0[15:0] - end - attribute \src "ls180.v:1367.12-1367.61" - process $proc$ls180.v:1367$3126 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_crc2_crc $1\libresocsim_sdcore_crc16_checker_crc2_crc[15:0] - end - attribute \src "ls180.v:1368.5-1368.53" - process $proc$ls180.v:1368$3127 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_crc2_clr[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_crc2_clr $1\libresocsim_sdcore_crc16_checker_crc2_clr[0:0] - end - attribute \src "ls180.v:137.5-137.40" - process $proc$ls180.v:137$2600 - assign { } { } - assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 - sync always - update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] - sync init - end - attribute \src "ls180.v:1370.12-1370.65" - process $proc$ls180.v:1370$3128 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_crc3_crcreg0 $1\libresocsim_sdcore_crc16_checker_crc3_crcreg0[15:0] - end - attribute \src "ls180.v:1374.12-1374.61" - process $proc$ls180.v:1374$3129 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_crc3_crc $1\libresocsim_sdcore_crc16_checker_crc3_crc[15:0] - end - attribute \src "ls180.v:1375.5-1375.53" - process $proc$ls180.v:1375$3130 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_crc3_clr[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_crc3_clr $1\libresocsim_sdcore_crc16_checker_crc3_clr[0:0] - end - attribute \src "ls180.v:1377.12-1377.60" - process $proc$ls180.v:1377$3131 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_crctmp0 $1\libresocsim_sdcore_crc16_checker_crctmp0[15:0] - end - attribute \src "ls180.v:1378.12-1378.60" - process $proc$ls180.v:1378$3132 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_crctmp1 $1\libresocsim_sdcore_crc16_checker_crctmp1[15:0] - end - attribute \src "ls180.v:1379.12-1379.60" - process $proc$ls180.v:1379$3133 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_crctmp2 $1\libresocsim_sdcore_crc16_checker_crctmp2[15:0] - end - attribute \src "ls180.v:1380.12-1380.60" - process $proc$ls180.v:1380$3134 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_crctmp3 $1\libresocsim_sdcore_crc16_checker_crctmp3[15:0] - end - attribute \src "ls180.v:1381.5-1381.50" - process $proc$ls180.v:1381$3135 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_valid[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_valid $1\libresocsim_sdcore_crc16_checker_valid[0:0] - end - attribute \src "ls180.v:1382.12-1382.58" - process $proc$ls180.v:1382$3136 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_fifo0 $1\libresocsim_sdcore_crc16_checker_fifo0[15:0] - end - attribute \src "ls180.v:1383.12-1383.58" - process $proc$ls180.v:1383$3137 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_fifo1 $1\libresocsim_sdcore_crc16_checker_fifo1[15:0] - end - attribute \src "ls180.v:1384.12-1384.58" - process $proc$ls180.v:1384$3138 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_fifo2 $1\libresocsim_sdcore_crc16_checker_fifo2[15:0] - end - attribute \src "ls180.v:1385.12-1385.58" - process $proc$ls180.v:1385$3139 - assign { } { } - assign $1\libresocsim_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_checker_fifo3 $1\libresocsim_sdcore_crc16_checker_fifo3[15:0] - end - attribute \src "ls180.v:1387.11-1387.46" - process $proc$ls180.v:1387$3140 - assign { } { } - assign $1\libresocsim_sdcore_cmd_count[2:0] 3'000 - sync always - sync init - update \libresocsim_sdcore_cmd_count $1\libresocsim_sdcore_cmd_count[2:0] - end - attribute \src "ls180.v:1388.5-1388.39" - process $proc$ls180.v:1388$3141 - assign { } { } - assign $1\libresocsim_sdcore_cmd_done[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_cmd_done $1\libresocsim_sdcore_cmd_done[0:0] - end - attribute \src "ls180.v:1389.5-1389.40" - process $proc$ls180.v:1389$3142 - assign { } { } - assign $1\libresocsim_sdcore_cmd_error[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_cmd_error $1\libresocsim_sdcore_cmd_error[0:0] - end - attribute \src "ls180.v:1390.5-1390.42" - process $proc$ls180.v:1390$3143 - assign { } { } - assign $1\libresocsim_sdcore_cmd_timeout[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_cmd_timeout $1\libresocsim_sdcore_cmd_timeout[0:0] - end - attribute \src "ls180.v:1392.12-1392.49" - process $proc$ls180.v:1392$3144 - assign { } { } - assign $1\libresocsim_sdcore_data_count[31:0] 0 - sync always - sync init - update \libresocsim_sdcore_data_count $1\libresocsim_sdcore_data_count[31:0] - end - attribute \src "ls180.v:1393.5-1393.40" - process $proc$ls180.v:1393$3145 - assign { } { } - assign $1\libresocsim_sdcore_data_done[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_data_done $1\libresocsim_sdcore_data_done[0:0] - end - attribute \src "ls180.v:1394.5-1394.41" - process $proc$ls180.v:1394$3146 - assign { } { } - assign $1\libresocsim_sdcore_data_error[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_data_error $1\libresocsim_sdcore_data_error[0:0] - end - attribute \src "ls180.v:1395.5-1395.43" - process $proc$ls180.v:1395$3147 - assign { } { } - assign $1\libresocsim_sdcore_data_timeout[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_data_timeout $1\libresocsim_sdcore_data_timeout[0:0] - end - attribute \src "ls180.v:140.11-140.37" - process $proc$ls180.v:140$2601 - assign { } { } - assign $1\main_libresocsim_we[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_we $1\main_libresocsim_we[3:0] - end - attribute \src "ls180.v:1404.11-1404.48" - process $proc$ls180.v:1404$3148 - assign { } { } - assign $0\libresocsim_interface0_bus_cti[2:0] 3'000 - sync always - update \libresocsim_interface0_bus_cti $0\libresocsim_interface0_bus_cti[2:0] - sync init - end - attribute \src "ls180.v:1405.11-1405.48" - process $proc$ls180.v:1405$3149 - assign { } { } - assign $0\libresocsim_interface0_bus_bte[1:0] 2'00 - sync always - update \libresocsim_interface0_bus_bte $0\libresocsim_interface0_bus_bte[1:0] - sync init - end - attribute \src "ls180.v:142.12-142.50" - process $proc$ls180.v:142$2602 - assign { } { } - assign $1\main_libresocsim_storage[31:0] 9895604 - sync always - sync init - update \main_libresocsim_storage $1\main_libresocsim_storage[31:0] - end - attribute \src "ls180.v:1428.11-1428.52" - process $proc$ls180.v:1428$3150 - assign { } { } - assign $1\libresocsim_sdblock2mem_fifo_level[5:0] 6'000000 - sync always - sync init - update \libresocsim_sdblock2mem_fifo_level $1\libresocsim_sdblock2mem_fifo_level[5:0] - end - attribute \src "ls180.v:1429.5-1429.48" - process $proc$ls180.v:1429$3151 - assign { } { } - assign $0\libresocsim_sdblock2mem_fifo_replace[0:0] 1'0 - sync always - update \libresocsim_sdblock2mem_fifo_replace $0\libresocsim_sdblock2mem_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:143.5-143.31" - process $proc$ls180.v:143$2603 - assign { } { } - assign $1\main_libresocsim_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_re $1\main_libresocsim_re[0:0] - end - attribute \src "ls180.v:1430.11-1430.54" - process $proc$ls180.v:1430$3152 - assign { } { } - assign $1\libresocsim_sdblock2mem_fifo_produce[4:0] 5'00000 - sync always - sync init - update \libresocsim_sdblock2mem_fifo_produce $1\libresocsim_sdblock2mem_fifo_produce[4:0] - end - attribute \src "ls180.v:1431.11-1431.54" - process $proc$ls180.v:1431$3153 - assign { } { } - assign $1\libresocsim_sdblock2mem_fifo_consume[4:0] 5'00000 - sync always - sync init - update \libresocsim_sdblock2mem_fifo_consume $1\libresocsim_sdblock2mem_fifo_consume[4:0] - end - attribute \src "ls180.v:1432.11-1432.57" - process $proc$ls180.v:1432$3154 - assign { } { } - assign $1\libresocsim_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 - sync always - sync init - update \libresocsim_sdblock2mem_fifo_wrport_adr $1\libresocsim_sdblock2mem_fifo_wrport_adr[4:0] - end - attribute \src "ls180.v:145.5-145.39" - process $proc$ls180.v:145$2604 - assign { } { } - assign $1\main_libresocsim_sink_ready[0:0] 1'0 - sync always - sync init - update \main_libresocsim_sink_ready $1\main_libresocsim_sink_ready[0:0] - end - attribute \src "ls180.v:1452.5-1452.58" - process $proc$ls180.v:1452$3155 - assign { } { } - assign $1\libresocsim_sdblock2mem_converter_source_first[0:0] 1'0 - sync always - sync init - update \libresocsim_sdblock2mem_converter_source_first $1\libresocsim_sdblock2mem_converter_source_first[0:0] - end - attribute \src "ls180.v:1453.5-1453.57" - process $proc$ls180.v:1453$3156 - assign { } { } - assign $1\libresocsim_sdblock2mem_converter_source_last[0:0] 1'0 - sync always - sync init - update \libresocsim_sdblock2mem_converter_source_last $1\libresocsim_sdblock2mem_converter_source_last[0:0] - end - attribute \src "ls180.v:1454.12-1454.73" - process $proc$ls180.v:1454$3157 - assign { } { } - assign $1\libresocsim_sdblock2mem_converter_source_payload_data[31:0] 0 - sync always - sync init - update \libresocsim_sdblock2mem_converter_source_payload_data $1\libresocsim_sdblock2mem_converter_source_payload_data[31:0] - end - attribute \src "ls180.v:1455.11-1455.84" - process $proc$ls180.v:1455$3158 - assign { } { } - assign $1\libresocsim_sdblock2mem_converter_source_payload_valid_token_count[2:0] 3'000 - sync always - sync init - update \libresocsim_sdblock2mem_converter_source_payload_valid_token_count $1\libresocsim_sdblock2mem_converter_source_payload_valid_token_count[2:0] - end - attribute \src "ls180.v:1456.11-1456.57" - process $proc$ls180.v:1456$3159 - assign { } { } - assign $1\libresocsim_sdblock2mem_converter_demux[1:0] 2'00 - sync always - sync init - update \libresocsim_sdblock2mem_converter_demux $1\libresocsim_sdblock2mem_converter_demux[1:0] - end - attribute \src "ls180.v:1458.5-1458.56" - process $proc$ls180.v:1458$3160 - assign { } { } - assign $1\libresocsim_sdblock2mem_converter_strobe_all[0:0] 1'0 - sync always - sync init - update \libresocsim_sdblock2mem_converter_strobe_all $1\libresocsim_sdblock2mem_converter_strobe_all[0:0] - end - attribute \src "ls180.v:1464.5-1464.52" - process $proc$ls180.v:1464$3161 - assign { } { } - assign $1\libresocsim_sdblock2mem_sink_sink_valid1[0:0] 1'0 - sync always - sync init - update \libresocsim_sdblock2mem_sink_sink_valid1 $1\libresocsim_sdblock2mem_sink_sink_valid1[0:0] - end - attribute \src "ls180.v:1466.12-1466.69" - process $proc$ls180.v:1466$3162 - assign { } { } - assign $1\libresocsim_sdblock2mem_sink_sink_payload_address[31:0] 0 - sync always - sync init - update \libresocsim_sdblock2mem_sink_sink_payload_address $1\libresocsim_sdblock2mem_sink_sink_payload_address[31:0] - end - attribute \src "ls180.v:1467.12-1467.67" - process $proc$ls180.v:1467$3163 - assign { } { } - assign $1\libresocsim_sdblock2mem_sink_sink_payload_data1[31:0] 0 - sync always - sync init - update \libresocsim_sdblock2mem_sink_sink_payload_data1 $1\libresocsim_sdblock2mem_sink_sink_payload_data1[31:0] - end - attribute \src "ls180.v:1469.5-1469.64" - process $proc$ls180.v:1469$3164 - assign { } { } - assign $1\libresocsim_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 - sync always - sync init - update \libresocsim_sdblock2mem_wishbonedmawriter_sink_ready $1\libresocsim_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - end - attribute \src "ls180.v:1473.12-1473.74" - process $proc$ls180.v:1473$3165 - assign { } { } - assign $1\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \libresocsim_sdblock2mem_wishbonedmawriter_base_storage $1\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] - end - attribute \src "ls180.v:1474.5-1474.61" - process $proc$ls180.v:1474$3166 - assign { } { } - assign $1\libresocsim_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 - sync always - sync init - update \libresocsim_sdblock2mem_wishbonedmawriter_base_re $1\libresocsim_sdblock2mem_wishbonedmawriter_base_re[0:0] - end - attribute \src "ls180.v:1475.12-1475.76" - process $proc$ls180.v:1475$3167 - assign { } { } - assign $1\libresocsim_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 - sync always - sync init - update \libresocsim_sdblock2mem_wishbonedmawriter_length_storage $1\libresocsim_sdblock2mem_wishbonedmawriter_length_storage[31:0] - end - attribute \src "ls180.v:1476.5-1476.63" - process $proc$ls180.v:1476$3168 - assign { } { } - assign $1\libresocsim_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 - sync always - sync init - update \libresocsim_sdblock2mem_wishbonedmawriter_length_re $1\libresocsim_sdblock2mem_wishbonedmawriter_length_re[0:0] - end - attribute \src "ls180.v:1477.5-1477.68" - process $proc$ls180.v:1477$3169 - assign { } { } - assign $1\libresocsim_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 - sync always - sync init - update \libresocsim_sdblock2mem_wishbonedmawriter_enable_storage $1\libresocsim_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - end - attribute \src "ls180.v:1478.5-1478.63" - process $proc$ls180.v:1478$3170 - assign { } { } - assign $1\libresocsim_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 - sync always - sync init - update \libresocsim_sdblock2mem_wishbonedmawriter_enable_re $1\libresocsim_sdblock2mem_wishbonedmawriter_enable_re[0:0] - end - attribute \src "ls180.v:1479.5-1479.60" - process $proc$ls180.v:1479$3171 - assign { } { } - assign $1\libresocsim_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 - sync always - sync init - update \libresocsim_sdblock2mem_wishbonedmawriter_status $1\libresocsim_sdblock2mem_wishbonedmawriter_status[0:0] - end - attribute \src "ls180.v:1481.5-1481.66" - process $proc$ls180.v:1481$3172 - assign { } { } - assign $1\libresocsim_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 - sync always - sync init - update \libresocsim_sdblock2mem_wishbonedmawriter_loop_storage $1\libresocsim_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - end - attribute \src "ls180.v:1482.5-1482.61" - process $proc$ls180.v:1482$3173 - assign { } { } - assign $1\libresocsim_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 - sync always - sync init - update \libresocsim_sdblock2mem_wishbonedmawriter_loop_re $1\libresocsim_sdblock2mem_wishbonedmawriter_loop_re[0:0] - end - attribute \src "ls180.v:1484.12-1484.68" - process $proc$ls180.v:1484$3174 - assign { } { } - assign $1\libresocsim_sdblock2mem_wishbonedmawriter_offset[31:0] 0 - sync always - sync init - update \libresocsim_sdblock2mem_wishbonedmawriter_offset $1\libresocsim_sdblock2mem_wishbonedmawriter_offset[31:0] - end - attribute \src "ls180.v:1487.12-1487.50" - process $proc$ls180.v:1487$3175 - assign { } { } - assign $1\libresocsim_interface1_bus_adr[31:0] 0 - sync always - sync init - update \libresocsim_interface1_bus_adr $1\libresocsim_interface1_bus_adr[31:0] - end - attribute \src "ls180.v:1488.12-1488.52" - process $proc$ls180.v:1488$3176 - assign { } { } - assign $0\libresocsim_interface1_bus_dat_w[31:0] 0 - sync always - update \libresocsim_interface1_bus_dat_w $0\libresocsim_interface1_bus_dat_w[31:0] - sync init - end - attribute \src "ls180.v:149.5-149.42" - process $proc$ls180.v:149$2605 - assign { } { } - assign $1\main_libresocsim_uart_clk_txen[0:0] 1'0 - sync always - sync init - update \main_libresocsim_uart_clk_txen $1\main_libresocsim_uart_clk_txen[0:0] - end - attribute \src "ls180.v:1490.11-1490.48" - process $proc$ls180.v:1490$3177 - assign { } { } - assign $1\libresocsim_interface1_bus_sel[3:0] 4'0000 - sync always - sync init - update \libresocsim_interface1_bus_sel $1\libresocsim_interface1_bus_sel[3:0] - end - attribute \src "ls180.v:1491.5-1491.42" - process $proc$ls180.v:1491$3178 - assign { } { } - assign $1\libresocsim_interface1_bus_cyc[0:0] 1'0 - sync always - sync init - update \libresocsim_interface1_bus_cyc $1\libresocsim_interface1_bus_cyc[0:0] - end - attribute \src "ls180.v:1492.5-1492.42" - process $proc$ls180.v:1492$3179 - assign { } { } - assign $1\libresocsim_interface1_bus_stb[0:0] 1'0 - sync always - sync init - update \libresocsim_interface1_bus_stb $1\libresocsim_interface1_bus_stb[0:0] - end - attribute \src "ls180.v:1494.5-1494.41" - process $proc$ls180.v:1494$3180 - assign { } { } - assign $1\libresocsim_interface1_bus_we[0:0] 1'0 - sync always - sync init - update \libresocsim_interface1_bus_we $1\libresocsim_interface1_bus_we[0:0] - end - attribute \src "ls180.v:1495.11-1495.48" - process $proc$ls180.v:1495$3181 - assign { } { } - assign $0\libresocsim_interface1_bus_cti[2:0] 3'000 - sync always - update \libresocsim_interface1_bus_cti $0\libresocsim_interface1_bus_cti[2:0] - sync init - end - attribute \src "ls180.v:1496.11-1496.48" - process $proc$ls180.v:1496$3182 - assign { } { } - assign $0\libresocsim_interface1_bus_bte[1:0] 2'00 - sync always - update \libresocsim_interface1_bus_bte $0\libresocsim_interface1_bus_bte[1:0] - sync init - end - attribute \src "ls180.v:150.12-150.57" - process $proc$ls180.v:150$2606 - assign { } { } - assign $1\main_libresocsim_phase_accumulator_tx[31:0] 0 - sync always - sync init - update \main_libresocsim_phase_accumulator_tx $1\main_libresocsim_phase_accumulator_tx[31:0] - end - attribute \src "ls180.v:1503.5-1503.50" - process $proc$ls180.v:1503$3183 - assign { } { } - assign $1\libresocsim_sdmem2block_dma_sink_valid[0:0] 1'0 - sync always - sync init - update \libresocsim_sdmem2block_dma_sink_valid $1\libresocsim_sdmem2block_dma_sink_valid[0:0] - end - attribute \src "ls180.v:1504.5-1504.50" - process $proc$ls180.v:1504$3184 - assign { } { } - assign $1\libresocsim_sdmem2block_dma_sink_ready[0:0] 1'0 - sync always - sync init - update \libresocsim_sdmem2block_dma_sink_ready $1\libresocsim_sdmem2block_dma_sink_ready[0:0] - end - attribute \src "ls180.v:1505.5-1505.49" - process $proc$ls180.v:1505$3185 - assign { } { } - assign $1\libresocsim_sdmem2block_dma_sink_last[0:0] 1'0 - sync always - sync init - update \libresocsim_sdmem2block_dma_sink_last $1\libresocsim_sdmem2block_dma_sink_last[0:0] - end - attribute \src "ls180.v:1506.12-1506.68" - process $proc$ls180.v:1506$3186 - assign { } { } - assign $1\libresocsim_sdmem2block_dma_sink_payload_address[31:0] 0 - sync always - sync init - update \libresocsim_sdmem2block_dma_sink_payload_address $1\libresocsim_sdmem2block_dma_sink_payload_address[31:0] - end - attribute \src "ls180.v:1507.5-1507.52" - process $proc$ls180.v:1507$3187 - assign { } { } - assign $1\libresocsim_sdmem2block_dma_source_valid[0:0] 1'0 - sync always - sync init - update \libresocsim_sdmem2block_dma_source_valid $1\libresocsim_sdmem2block_dma_source_valid[0:0] - end - attribute \src "ls180.v:1509.5-1509.52" - process $proc$ls180.v:1509$3188 - assign { } { } - assign $0\libresocsim_sdmem2block_dma_source_first[0:0] 1'0 - sync always - update \libresocsim_sdmem2block_dma_source_first $0\libresocsim_sdmem2block_dma_source_first[0:0] - sync init - end - attribute \src "ls180.v:151.11-151.41" - process $proc$ls180.v:151$2607 - assign { } { } - assign $1\main_libresocsim_tx_reg[7:0] 8'00000000 - sync always - sync init - update \main_libresocsim_tx_reg $1\main_libresocsim_tx_reg[7:0] - end - attribute \src "ls180.v:1510.5-1510.51" - process $proc$ls180.v:1510$3189 - assign { } { } - assign $1\libresocsim_sdmem2block_dma_source_last[0:0] 1'0 - sync always - sync init - update \libresocsim_sdmem2block_dma_source_last $1\libresocsim_sdmem2block_dma_source_last[0:0] - end - attribute \src "ls180.v:1511.12-1511.67" - process $proc$ls180.v:1511$3190 - assign { } { } - assign $1\libresocsim_sdmem2block_dma_source_payload_data[31:0] 0 - sync always - sync init - update \libresocsim_sdmem2block_dma_source_payload_data $1\libresocsim_sdmem2block_dma_source_payload_data[31:0] - end - attribute \src "ls180.v:1512.12-1512.52" - process $proc$ls180.v:1512$3191 - assign { } { } - assign $1\libresocsim_sdmem2block_dma_data[31:0] 0 - sync always - sync init - update \libresocsim_sdmem2block_dma_data $1\libresocsim_sdmem2block_dma_data[31:0] - end - attribute \src "ls180.v:1513.12-1513.60" - process $proc$ls180.v:1513$3192 - assign { } { } - assign $1\libresocsim_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \libresocsim_sdmem2block_dma_base_storage $1\libresocsim_sdmem2block_dma_base_storage[63:0] - end - attribute \src "ls180.v:1514.5-1514.47" - process $proc$ls180.v:1514$3193 - assign { } { } - assign $1\libresocsim_sdmem2block_dma_base_re[0:0] 1'0 - sync always - sync init - update \libresocsim_sdmem2block_dma_base_re $1\libresocsim_sdmem2block_dma_base_re[0:0] - end - attribute \src "ls180.v:1515.12-1515.62" - process $proc$ls180.v:1515$3194 - assign { } { } - assign $1\libresocsim_sdmem2block_dma_length_storage[31:0] 0 - sync always - sync init - update \libresocsim_sdmem2block_dma_length_storage $1\libresocsim_sdmem2block_dma_length_storage[31:0] - end - attribute \src "ls180.v:1516.5-1516.49" - process $proc$ls180.v:1516$3195 - assign { } { } - assign $1\libresocsim_sdmem2block_dma_length_re[0:0] 1'0 - sync always - sync init - update \libresocsim_sdmem2block_dma_length_re $1\libresocsim_sdmem2block_dma_length_re[0:0] - end - attribute \src "ls180.v:1517.5-1517.54" - process $proc$ls180.v:1517$3196 - assign { } { } - assign $1\libresocsim_sdmem2block_dma_enable_storage[0:0] 1'0 - sync always - sync init - update \libresocsim_sdmem2block_dma_enable_storage $1\libresocsim_sdmem2block_dma_enable_storage[0:0] - end - attribute \src "ls180.v:1518.5-1518.49" - process $proc$ls180.v:1518$3197 - assign { } { } - assign $1\libresocsim_sdmem2block_dma_enable_re[0:0] 1'0 - sync always - sync init - update \libresocsim_sdmem2block_dma_enable_re $1\libresocsim_sdmem2block_dma_enable_re[0:0] - end - attribute \src "ls180.v:1519.5-1519.51" - process $proc$ls180.v:1519$3198 - assign { } { } - assign $1\libresocsim_sdmem2block_dma_done_status[0:0] 1'0 - sync always - sync init - update \libresocsim_sdmem2block_dma_done_status $1\libresocsim_sdmem2block_dma_done_status[0:0] - end - attribute \src "ls180.v:152.11-152.46" - process $proc$ls180.v:152$2608 - assign { } { } - assign $1\main_libresocsim_tx_bitcount[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_tx_bitcount $1\main_libresocsim_tx_bitcount[3:0] - end - attribute \src "ls180.v:1521.5-1521.52" - process $proc$ls180.v:1521$3199 - assign { } { } - assign $1\libresocsim_sdmem2block_dma_loop_storage[0:0] 1'0 - sync always - sync init - update \libresocsim_sdmem2block_dma_loop_storage $1\libresocsim_sdmem2block_dma_loop_storage[0:0] - end - attribute \src "ls180.v:1522.5-1522.47" - process $proc$ls180.v:1522$3200 - assign { } { } - assign $1\libresocsim_sdmem2block_dma_loop_re[0:0] 1'0 - sync always - sync init - update \libresocsim_sdmem2block_dma_loop_re $1\libresocsim_sdmem2block_dma_loop_re[0:0] - end - attribute \src "ls180.v:1526.12-1526.54" - process $proc$ls180.v:1526$3201 - assign { } { } - assign $1\libresocsim_sdmem2block_dma_offset[31:0] 0 - sync always - sync init - update \libresocsim_sdmem2block_dma_offset $1\libresocsim_sdmem2block_dma_offset[31:0] - end - attribute \src "ls180.v:153.5-153.36" - process $proc$ls180.v:153$2609 - assign { } { } - assign $1\main_libresocsim_tx_busy[0:0] 1'0 - sync always - sync init - update \main_libresocsim_tx_busy $1\main_libresocsim_tx_busy[0:0] - end - attribute \src "ls180.v:1538.11-1538.71" - process $proc$ls180.v:1538$3202 - assign { } { } - assign $1\libresocsim_sdmem2block_converter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \libresocsim_sdmem2block_converter_source_payload_data $1\libresocsim_sdmem2block_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:154.5-154.41" - process $proc$ls180.v:154$2610 - assign { } { } - assign $1\main_libresocsim_source_valid[0:0] 1'0 - sync always - sync init - update \main_libresocsim_source_valid $1\main_libresocsim_source_valid[0:0] - end - attribute \src "ls180.v:1540.11-1540.55" - process $proc$ls180.v:1540$3203 - assign { } { } - assign $1\libresocsim_sdmem2block_converter_mux[1:0] 2'00 - sync always - sync init - update \libresocsim_sdmem2block_converter_mux $1\libresocsim_sdmem2block_converter_mux[1:0] - end - attribute \src "ls180.v:156.5-156.41" - process $proc$ls180.v:156$2611 - assign { } { } - assign $0\main_libresocsim_source_first[0:0] 1'0 - sync always - update \main_libresocsim_source_first $0\main_libresocsim_source_first[0:0] - sync init - end - attribute \src "ls180.v:1564.11-1564.52" - process $proc$ls180.v:1564$3204 - assign { } { } - assign $1\libresocsim_sdmem2block_fifo_level[5:0] 6'000000 - sync always - sync init - update \libresocsim_sdmem2block_fifo_level $1\libresocsim_sdmem2block_fifo_level[5:0] - end - attribute \src "ls180.v:1565.5-1565.48" - process $proc$ls180.v:1565$3205 - assign { } { } - assign $0\libresocsim_sdmem2block_fifo_replace[0:0] 1'0 - sync always - update \libresocsim_sdmem2block_fifo_replace $0\libresocsim_sdmem2block_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:1566.11-1566.54" - process $proc$ls180.v:1566$3206 - assign { } { } - assign $1\libresocsim_sdmem2block_fifo_produce[4:0] 5'00000 - sync always - sync init - update \libresocsim_sdmem2block_fifo_produce $1\libresocsim_sdmem2block_fifo_produce[4:0] - end - attribute \src "ls180.v:1567.11-1567.54" - process $proc$ls180.v:1567$3207 - assign { } { } - assign $1\libresocsim_sdmem2block_fifo_consume[4:0] 5'00000 - sync always - sync init - update \libresocsim_sdmem2block_fifo_consume $1\libresocsim_sdmem2block_fifo_consume[4:0] - end - attribute \src "ls180.v:1568.11-1568.57" - process $proc$ls180.v:1568$3208 - assign { } { } - assign $1\libresocsim_sdmem2block_fifo_wrport_adr[4:0] 5'00000 - sync always - sync init - update \libresocsim_sdmem2block_fifo_wrport_adr $1\libresocsim_sdmem2block_fifo_wrport_adr[4:0] - end - attribute \src "ls180.v:157.5-157.40" - process $proc$ls180.v:157$2612 - assign { } { } - assign $0\main_libresocsim_source_last[0:0] 1'0 - sync always - update \main_libresocsim_source_last $0\main_libresocsim_source_last[0:0] - sync init - end - attribute \src "ls180.v:158.11-158.54" - process $proc$ls180.v:158$2613 - assign { } { } - assign $1\main_libresocsim_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_libresocsim_source_payload_data $1\main_libresocsim_source_payload_data[7:0] - end - attribute \src "ls180.v:1583.5-1583.29" - process $proc$ls180.v:1583$3209 - assign { } { } - assign $1\libresocsim_done0[0:0] 1'0 - sync always - sync init - update \libresocsim_done0 $1\libresocsim_done0[0:0] - end - attribute \src "ls180.v:1584.5-1584.27" - process $proc$ls180.v:1584$3210 - assign { } { } - assign $1\libresocsim_irq[0:0] 1'0 - sync always - sync init - update \libresocsim_irq $1\libresocsim_irq[0:0] - end - attribute \src "ls180.v:1586.11-1586.34" - process $proc$ls180.v:1586$3211 - assign { } { } - assign $1\libresocsim_miso[7:0] 8'00000000 - sync always - sync init - update \libresocsim_miso $1\libresocsim_miso[7:0] - end - attribute \src "ls180.v:159.5-159.42" - process $proc$ls180.v:159$2614 - assign { } { } - assign $1\main_libresocsim_uart_clk_rxen[0:0] 1'0 - sync always - sync init - update \main_libresocsim_uart_clk_rxen $1\main_libresocsim_uart_clk_rxen[0:0] - end - attribute \src "ls180.v:1590.5-1590.30" - process $proc$ls180.v:1590$3212 - assign { } { } - assign $1\libresocsim_start1[0:0] 1'0 - sync always - sync init - update \libresocsim_start1 $1\libresocsim_start1[0:0] - end - attribute \src "ls180.v:1592.12-1592.47" - process $proc$ls180.v:1592$3213 - assign { } { } - assign $1\libresocsim_control_storage[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_control_storage $1\libresocsim_control_storage[15:0] - end - attribute \src "ls180.v:1593.5-1593.34" - process $proc$ls180.v:1593$3214 - assign { } { } - assign $1\libresocsim_control_re[0:0] 1'0 - sync always - sync init - update \libresocsim_control_re $1\libresocsim_control_re[0:0] - end - attribute \src "ls180.v:1597.11-1597.42" - process $proc$ls180.v:1597$3215 - assign { } { } - assign $1\libresocsim_mosi_storage[7:0] 8'00000000 - sync always - sync init - update \libresocsim_mosi_storage $1\libresocsim_mosi_storage[7:0] - end - attribute \src "ls180.v:1598.5-1598.31" - process $proc$ls180.v:1598$3216 - assign { } { } - assign $1\libresocsim_mosi_re[0:0] 1'0 - sync always - sync init - update \libresocsim_mosi_re $1\libresocsim_mosi_re[0:0] - end - attribute \src "ls180.v:160.12-160.57" - process $proc$ls180.v:160$2615 - assign { } { } - assign $1\main_libresocsim_phase_accumulator_rx[31:0] 0 - sync always - sync init - update \main_libresocsim_phase_accumulator_rx $1\main_libresocsim_phase_accumulator_rx[31:0] - end - attribute \src "ls180.v:1602.5-1602.34" - process $proc$ls180.v:1602$3217 - assign { } { } - assign $1\libresocsim_cs_storage[0:0] 1'1 - sync always - sync init - update \libresocsim_cs_storage $1\libresocsim_cs_storage[0:0] - end - attribute \src "ls180.v:1603.5-1603.29" - process $proc$ls180.v:1603$3218 - assign { } { } - assign $1\libresocsim_cs_re[0:0] 1'0 - sync always - sync init - update \libresocsim_cs_re $1\libresocsim_cs_re[0:0] - end - attribute \src "ls180.v:1604.5-1604.40" - process $proc$ls180.v:1604$3219 - assign { } { } - assign $1\libresocsim_loopback_storage[0:0] 1'0 - sync always - sync init - update \libresocsim_loopback_storage $1\libresocsim_loopback_storage[0:0] - end - attribute \src "ls180.v:1605.5-1605.35" - process $proc$ls180.v:1605$3220 - assign { } { } - assign $1\libresocsim_loopback_re[0:0] 1'0 - sync always - sync init - update \libresocsim_loopback_re $1\libresocsim_loopback_re[0:0] - end - attribute \src "ls180.v:1606.5-1606.34" - process $proc$ls180.v:1606$3221 - assign { } { } - assign $1\libresocsim_clk_enable[0:0] 1'0 - sync always - sync init - update \libresocsim_clk_enable $1\libresocsim_clk_enable[0:0] - end - attribute \src "ls180.v:1607.5-1607.33" - process $proc$ls180.v:1607$3222 - assign { } { } - assign $1\libresocsim_cs_enable[0:0] 1'0 - sync always - sync init - update \libresocsim_cs_enable $1\libresocsim_cs_enable[0:0] - end - attribute \src "ls180.v:1608.11-1608.35" - process $proc$ls180.v:1608$3223 - assign { } { } - assign $1\libresocsim_count[2:0] 3'000 - sync always - sync init - update \libresocsim_count $1\libresocsim_count[2:0] - end - attribute \src "ls180.v:1609.5-1609.34" - process $proc$ls180.v:1609$3224 - assign { } { } - assign $1\libresocsim_mosi_latch[0:0] 1'0 - sync always - sync init - update \libresocsim_mosi_latch $1\libresocsim_mosi_latch[0:0] - end - attribute \src "ls180.v:1610.5-1610.34" - process $proc$ls180.v:1610$3225 - assign { } { } - assign $1\libresocsim_miso_latch[0:0] 1'0 - sync always - sync init - update \libresocsim_miso_latch $1\libresocsim_miso_latch[0:0] - end - attribute \src "ls180.v:1611.12-1611.44" - process $proc$ls180.v:1611$3226 - assign { } { } - assign $1\libresocsim_clk_divider1[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_clk_divider1 $1\libresocsim_clk_divider1[15:0] - end - attribute \src "ls180.v:1614.11-1614.39" - process $proc$ls180.v:1614$3227 - assign { } { } - assign $1\libresocsim_mosi_data[7:0] 8'00000000 - sync always - sync init - update \libresocsim_mosi_data $1\libresocsim_mosi_data[7:0] - end - attribute \src "ls180.v:1615.11-1615.38" - process $proc$ls180.v:1615$3228 - assign { } { } - assign $1\libresocsim_mosi_sel[2:0] 3'000 - sync always - sync init - update \libresocsim_mosi_sel $1\libresocsim_mosi_sel[2:0] - end - attribute \src "ls180.v:1616.11-1616.39" - process $proc$ls180.v:1616$3229 - assign { } { } - assign $1\libresocsim_miso_data[7:0] 8'00000000 - sync always - sync init - update \libresocsim_miso_data $1\libresocsim_miso_data[7:0] - end - attribute \src "ls180.v:1617.12-1617.41" - process $proc$ls180.v:1617$3230 - assign { } { } - assign $1\libresocsim_storage[15:0] 16'0000000001111101 - sync always - sync init - update \libresocsim_storage $1\libresocsim_storage[15:0] - end - attribute \src "ls180.v:1618.5-1618.26" - process $proc$ls180.v:1618$3231 - assign { } { } - assign $1\libresocsim_re[0:0] 1'0 - sync always - sync init - update \libresocsim_re $1\libresocsim_re[0:0] - end - attribute \src "ls180.v:1619.5-1619.36" - process $proc$ls180.v:1619$3232 - assign { } { } - assign $1\builder_converter0_state[0:0] 1'0 - sync always - sync init - update \builder_converter0_state $1\builder_converter0_state[0:0] - end - attribute \src "ls180.v:162.5-162.33" - process $proc$ls180.v:162$2616 - assign { } { } - assign $1\main_libresocsim_rx_r[0:0] 1'0 - sync always - sync init - update \main_libresocsim_rx_r $1\main_libresocsim_rx_r[0:0] - end - attribute \src "ls180.v:1620.5-1620.41" - process $proc$ls180.v:1620$3233 - assign { } { } - assign $1\builder_converter0_next_state[0:0] 1'0 - sync always - sync init - update \builder_converter0_next_state $1\builder_converter0_next_state[0:0] - end - attribute \src "ls180.v:1621.5-1621.69" - process $proc$ls180.v:1621$3234 - assign { } { } - assign $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter0_counter_converter0_next_value $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] - end - attribute \src "ls180.v:1622.5-1622.72" - process $proc$ls180.v:1622$3235 - assign { } { } - assign $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter0_counter_converter0_next_value_ce $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] - end - attribute \src "ls180.v:1623.5-1623.36" - process $proc$ls180.v:1623$3236 - assign { } { } - assign $1\builder_converter1_state[0:0] 1'0 - sync always - sync init - update \builder_converter1_state $1\builder_converter1_state[0:0] - end - attribute \src "ls180.v:1624.5-1624.41" - process $proc$ls180.v:1624$3237 - assign { } { } - assign $1\builder_converter1_next_state[0:0] 1'0 - sync always - sync init - update \builder_converter1_next_state $1\builder_converter1_next_state[0:0] - end - attribute \src "ls180.v:1625.5-1625.69" - process $proc$ls180.v:1625$3238 - assign { } { } - assign $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter1_counter_converter1_next_value $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] - end - attribute \src "ls180.v:1626.5-1626.72" - process $proc$ls180.v:1626$3239 - assign { } { } - assign $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter1_counter_converter1_next_value_ce $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] - end - attribute \src "ls180.v:1627.11-1627.41" - process $proc$ls180.v:1627$3240 - assign { } { } - assign $1\builder_refresher_state[1:0] 2'00 - sync always - sync init - update \builder_refresher_state $1\builder_refresher_state[1:0] - end - attribute \src "ls180.v:1628.11-1628.46" - process $proc$ls180.v:1628$3241 - assign { } { } - assign $1\builder_refresher_next_state[1:0] 2'00 - sync always - sync init - update \builder_refresher_next_state $1\builder_refresher_next_state[1:0] - end - attribute \src "ls180.v:1629.11-1629.44" - process $proc$ls180.v:1629$3242 - assign { } { } - assign $1\builder_bankmachine0_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0] - end - attribute \src "ls180.v:163.11-163.41" - process $proc$ls180.v:163$2617 - assign { } { } - assign $1\main_libresocsim_rx_reg[7:0] 8'00000000 - sync always - sync init - update \main_libresocsim_rx_reg $1\main_libresocsim_rx_reg[7:0] - end - attribute \src "ls180.v:1630.11-1630.49" - process $proc$ls180.v:1630$3243 - assign { } { } - assign $1\builder_bankmachine0_next_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] - end - attribute \src "ls180.v:1631.11-1631.44" - process $proc$ls180.v:1631$3244 - assign { } { } - assign $1\builder_bankmachine1_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0] - end - attribute \src "ls180.v:1632.11-1632.49" - process $proc$ls180.v:1632$3245 - assign { } { } - assign $1\builder_bankmachine1_next_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0] - end - attribute \src "ls180.v:1633.11-1633.44" - process $proc$ls180.v:1633$3246 - assign { } { } - assign $1\builder_bankmachine2_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0] - end - attribute \src "ls180.v:1634.11-1634.49" - process $proc$ls180.v:1634$3247 - assign { } { } - assign $1\builder_bankmachine2_next_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0] - end - attribute \src "ls180.v:1635.11-1635.44" - process $proc$ls180.v:1635$3248 - assign { } { } - assign $1\builder_bankmachine3_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0] - end - attribute \src "ls180.v:1636.11-1636.49" - process $proc$ls180.v:1636$3249 - assign { } { } - assign $1\builder_bankmachine3_next_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0] - end - attribute \src "ls180.v:1637.11-1637.43" - process $proc$ls180.v:1637$3250 - assign { } { } - assign $1\builder_multiplexer_state[2:0] 3'000 - sync always - sync init - update \builder_multiplexer_state $1\builder_multiplexer_state[2:0] - end - attribute \src "ls180.v:1638.11-1638.48" - process $proc$ls180.v:1638$3251 - assign { } { } - assign $1\builder_multiplexer_next_state[2:0] 3'000 - sync always - sync init - update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0] - end - attribute \src "ls180.v:164.11-164.46" - process $proc$ls180.v:164$2618 - assign { } { } - assign $1\main_libresocsim_rx_bitcount[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_rx_bitcount $1\main_libresocsim_rx_bitcount[3:0] - end - attribute \src "ls180.v:165.5-165.36" - process $proc$ls180.v:165$2619 - assign { } { } - assign $1\main_libresocsim_rx_busy[0:0] 1'0 - sync always - sync init - update \main_libresocsim_rx_busy $1\main_libresocsim_rx_busy[0:0] - end - attribute \src "ls180.v:1651.5-1651.27" - process $proc$ls180.v:1651$3252 - assign { } { } - assign $0\builder_locked0[0:0] 1'0 - sync always - update \builder_locked0 $0\builder_locked0[0:0] - sync init - end - attribute \src "ls180.v:1652.5-1652.27" - process $proc$ls180.v:1652$3253 - assign { } { } - assign $0\builder_locked1[0:0] 1'0 - sync always - update \builder_locked1 $0\builder_locked1[0:0] - sync init - end - attribute \src "ls180.v:1653.5-1653.27" - process $proc$ls180.v:1653$3254 - assign { } { } - assign $0\builder_locked2[0:0] 1'0 - sync always - update \builder_locked2 $0\builder_locked2[0:0] - sync init - end - attribute \src "ls180.v:1654.5-1654.27" - process $proc$ls180.v:1654$3255 - assign { } { } - assign $0\builder_locked3[0:0] 1'0 - sync always - update \builder_locked3 $0\builder_locked3[0:0] - sync init - end - attribute \src "ls180.v:1655.5-1655.42" - process $proc$ls180.v:1655$3256 - assign { } { } - assign $1\builder_new_master_wdata_ready[0:0] 1'0 - sync always - sync init - update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0] - end - attribute \src "ls180.v:1656.5-1656.43" - process $proc$ls180.v:1656$3257 - assign { } { } - assign $1\builder_new_master_rdata_valid0[0:0] 1'0 - sync always - sync init - update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0] - end - attribute \src "ls180.v:1657.5-1657.43" - process $proc$ls180.v:1657$3258 - assign { } { } - assign $1\builder_new_master_rdata_valid1[0:0] 1'0 - sync always - sync init - update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0] - end - attribute \src "ls180.v:1658.5-1658.43" - process $proc$ls180.v:1658$3259 - assign { } { } - assign $1\builder_new_master_rdata_valid2[0:0] 1'0 - sync always - sync init - update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0] - end - attribute \src "ls180.v:1659.5-1659.43" - process $proc$ls180.v:1659$3260 - assign { } { } - assign $1\builder_new_master_rdata_valid3[0:0] 1'0 - sync always - sync init - update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0] - end - attribute \src "ls180.v:1660.5-1660.35" - process $proc$ls180.v:1660$3261 - assign { } { } - assign $1\builder_converter_state[0:0] 1'0 - sync always - sync init - update \builder_converter_state $1\builder_converter_state[0:0] - end - attribute \src "ls180.v:1661.5-1661.40" - process $proc$ls180.v:1661$3262 - assign { } { } - assign $1\builder_converter_next_state[0:0] 1'0 - sync always - sync init - update \builder_converter_next_state $1\builder_converter_next_state[0:0] - end - attribute \src "ls180.v:1662.5-1662.55" - process $proc$ls180.v:1662$3263 - assign { } { } - assign $1\main_converter_counter_converter_next_value[0:0] 1'0 - sync always - sync init - update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] - end - attribute \src "ls180.v:1663.5-1663.58" - process $proc$ls180.v:1663$3264 - assign { } { } - assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0] - end - attribute \src "ls180.v:1664.11-1664.42" - process $proc$ls180.v:1664$3265 - assign { } { } - assign $1\builder_spimaster0_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster0_state $1\builder_spimaster0_state[1:0] - end - attribute \src "ls180.v:1665.11-1665.47" - process $proc$ls180.v:1665$3266 - assign { } { } - assign $1\builder_spimaster0_next_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0] - end - attribute \src "ls180.v:1666.11-1666.50" - process $proc$ls180.v:1666$3267 - assign { } { } - assign $1\main_count_spimaster0_next_value[2:0] 3'000 - sync always - sync init - update \main_count_spimaster0_next_value $1\main_count_spimaster0_next_value[2:0] - end - attribute \src "ls180.v:1667.5-1667.47" - process $proc$ls180.v:1667$3268 - assign { } { } - assign $1\main_count_spimaster0_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_count_spimaster0_next_value_ce $1\main_count_spimaster0_next_value_ce[0:0] - end - attribute \src "ls180.v:1668.5-1668.41" - process $proc$ls180.v:1668$3269 - assign { } { } - assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0 - sync always - sync init - update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0] - end - attribute \src "ls180.v:1669.5-1669.46" - process $proc$ls180.v:1669$3270 - assign { } { } - assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0 - sync always - sync init - update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0] - end - attribute \src "ls180.v:1670.11-1670.67" - process $proc$ls180.v:1670$3271 - assign { } { } - assign $1\libresocsim_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 - sync always - sync init - update \libresocsim_init_count_sdphy_sdphyinit_next_value $1\libresocsim_init_count_sdphy_sdphyinit_next_value[7:0] - end - attribute \src "ls180.v:1671.5-1671.64" - process $proc$ls180.v:1671$3272 - assign { } { } - assign $1\libresocsim_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 - sync always - sync init - update \libresocsim_init_count_sdphy_sdphyinit_next_value_ce $1\libresocsim_init_count_sdphy_sdphyinit_next_value_ce[0:0] - end - attribute \src "ls180.v:1672.11-1672.47" - process $proc$ls180.v:1672$3273 - assign { } { } - assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00 - sync always - sync init - update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0] - end - attribute \src "ls180.v:1673.11-1673.52" - process $proc$ls180.v:1673$3274 - assign { } { } - assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 - sync always - sync init - update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0] - end - attribute \src "ls180.v:1674.11-1674.67" - process $proc$ls180.v:1674$3275 - assign { } { } - assign $1\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 - sync always - sync init - update \libresocsim_cmdw_count_sdphy_sdphycmdw_next_value $1\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - end - attribute \src "ls180.v:1675.5-1675.64" - process $proc$ls180.v:1675$3276 - assign { } { } - assign $1\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - end - attribute \src "ls180.v:1676.11-1676.47" - process $proc$ls180.v:1676$3277 - assign { } { } - assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0] - end - attribute \src "ls180.v:1677.11-1677.52" - process $proc$ls180.v:1677$3278 - assign { } { } - assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0] - end - attribute \src "ls180.v:1678.11-1678.68" - process $proc$ls180.v:1678$3279 - assign { } { } - assign $1\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - sync always - sync init - update \libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0 $1\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - end - attribute \src "ls180.v:1679.5-1679.65" - process $proc$ls180.v:1679$3280 - assign { } { } - assign $1\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - end - attribute \src "ls180.v:1680.12-1680.72" - process $proc$ls180.v:1680$3281 - assign { } { } - assign $1\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 - sync always - sync init - update \libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - end - attribute \src "ls180.v:1681.5-1681.67" - process $proc$ls180.v:1681$3282 - assign { } { } - assign $1\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - end - attribute \src "ls180.v:1682.5-1682.67" - process $proc$ls180.v:1682$3283 - assign { } { } - assign $1\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - end - attribute \src "ls180.v:1683.5-1683.70" - process $proc$ls180.v:1683$3284 - assign { } { } - assign $1\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - end - attribute \src "ls180.v:1684.5-1684.41" - process $proc$ls180.v:1684$3285 - assign { } { } - assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0 - sync always - sync init - update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0] - end - attribute \src "ls180.v:1685.5-1685.46" - process $proc$ls180.v:1685$3286 - assign { } { } - assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 - sync always - sync init - update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0] - end - attribute \src "ls180.v:1686.5-1686.67" - process $proc$ls180.v:1686$3287 - assign { } { } - assign $1\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 - sync always - sync init - update \libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - end - attribute \src "ls180.v:1687.5-1687.70" - process $proc$ls180.v:1687$3288 - assign { } { } - assign $1\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 - sync always - sync init - update \libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - end - attribute \src "ls180.v:1688.11-1688.41" - process $proc$ls180.v:1688$3289 - assign { } { } - assign $1\builder_sdphy_fsm_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0] - end - attribute \src "ls180.v:1689.11-1689.46" - process $proc$ls180.v:1689$3290 - assign { } { } - assign $1\builder_sdphy_fsm_next_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0] - end - attribute \src "ls180.v:1690.11-1690.62" - process $proc$ls180.v:1690$3291 - assign { } { } - assign $1\libresocsim_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 - sync always - sync init - update \libresocsim_dataw_count_sdphy_fsm_next_value $1\libresocsim_dataw_count_sdphy_fsm_next_value[7:0] - end - attribute \src "ls180.v:1691.5-1691.59" - process $proc$ls180.v:1691$3292 - assign { } { } - assign $1\libresocsim_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 - sync always - sync init - update \libresocsim_dataw_count_sdphy_fsm_next_value_ce $1\libresocsim_dataw_count_sdphy_fsm_next_value_ce[0:0] - end - attribute \src "ls180.v:1692.11-1692.48" - process $proc$ls180.v:1692$3293 - assign { } { } - assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0] - end - attribute \src "ls180.v:1693.11-1693.53" - process $proc$ls180.v:1693$3294 - assign { } { } - assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0] - end - attribute \src "ls180.v:1694.11-1694.71" - process $proc$ls180.v:1694$3295 - assign { } { } - assign $1\libresocsim_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - sync always - sync init - update \libresocsim_datar_count_sdphy_sdphydatar_next_value0 $1\libresocsim_datar_count_sdphy_sdphydatar_next_value0[9:0] - end - attribute \src "ls180.v:1695.5-1695.67" - process $proc$ls180.v:1695$3296 - assign { } { } - assign $1\libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 - sync always - sync init - update \libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0 $1\libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - end - attribute \src "ls180.v:1696.12-1696.74" - process $proc$ls180.v:1696$3297 - assign { } { } - assign $1\libresocsim_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 - sync always - sync init - update \libresocsim_datar_timeout_sdphy_sdphydatar_next_value1 $1\libresocsim_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - end - attribute \src "ls180.v:1697.5-1697.69" - process $proc$ls180.v:1697$3298 - assign { } { } - assign $1\libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 - sync always - sync init - update \libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - end - attribute \src "ls180.v:1698.5-1698.70" - process $proc$ls180.v:1698$3299 - assign { } { } - assign $1\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 - sync always - sync init - update \libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - end - attribute \src "ls180.v:1699.5-1699.73" - process $proc$ls180.v:1699$3300 - assign { } { } - assign $1\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 - sync always - sync init - update \libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - end - attribute \src "ls180.v:1700.5-1700.52" - process $proc$ls180.v:1700$3301 - assign { } { } - assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 - sync always - sync init - update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0] - end - attribute \src "ls180.v:1701.5-1701.57" - process $proc$ls180.v:1701$3302 - assign { } { } - assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 - sync always - sync init - update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0] - end - attribute \src "ls180.v:1702.12-1702.100" - process $proc$ls180.v:1702$3303 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - end - attribute \src "ls180.v:1703.5-1703.95" - process $proc$ls180.v:1703$3304 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - end - attribute \src "ls180.v:1704.12-1704.100" - process $proc$ls180.v:1704$3305 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - end - attribute \src "ls180.v:1705.5-1705.95" - process $proc$ls180.v:1705$3306 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - end - attribute \src "ls180.v:1706.12-1706.100" - process $proc$ls180.v:1706$3307 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - end - attribute \src "ls180.v:1707.5-1707.95" - process $proc$ls180.v:1707$3308 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - end - attribute \src "ls180.v:1708.12-1708.100" - process $proc$ls180.v:1708$3309 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - end - attribute \src "ls180.v:1709.5-1709.95" - process $proc$ls180.v:1709$3310 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - end - attribute \src "ls180.v:1710.11-1710.94" - process $proc$ls180.v:1710$3311 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - end - attribute \src "ls180.v:1711.5-1711.91" - process $proc$ls180.v:1711$3312 - assign { } { } - assign $1\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - end - attribute \src "ls180.v:1712.11-1712.42" - process $proc$ls180.v:1712$3313 - assign { } { } - assign $1\builder_sdcore_fsm_state[2:0] 3'000 - sync always - sync init - update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0] - end - attribute \src "ls180.v:1713.11-1713.47" - process $proc$ls180.v:1713$3314 - assign { } { } - assign $1\builder_sdcore_fsm_next_state[2:0] 3'000 - sync always - sync init - update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0] - end - attribute \src "ls180.v:1714.5-1714.62" - process $proc$ls180.v:1714$3315 - assign { } { } - assign $1\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0 $1\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - end - attribute \src "ls180.v:1715.5-1715.65" - process $proc$ls180.v:1715$3316 - assign { } { } - assign $1\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - end - attribute \src "ls180.v:1716.5-1716.63" - process $proc$ls180.v:1716$3317 - assign { } { } - assign $1\libresocsim_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_data_done_sdcore_fsm_next_value1 $1\libresocsim_sdcore_data_done_sdcore_fsm_next_value1[0:0] - end - attribute \src "ls180.v:1717.5-1717.66" - process $proc$ls180.v:1717$3318 - assign { } { } - assign $1\libresocsim_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\libresocsim_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - end - attribute \src "ls180.v:1718.11-1718.69" - process $proc$ls180.v:1718$3319 - assign { } { } - assign $1\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 - sync always - sync init - update \libresocsim_sdcore_cmd_count_sdcore_fsm_next_value2 $1\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - end - attribute \src "ls180.v:1719.5-1719.66" - process $proc$ls180.v:1719$3320 - assign { } { } - assign $1\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - end - attribute \src "ls180.v:1720.12-1720.72" - process $proc$ls180.v:1720$3321 - assign { } { } - assign $1\libresocsim_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - sync always - sync init - update \libresocsim_sdcore_data_count_sdcore_fsm_next_value3 $1\libresocsim_sdcore_data_count_sdcore_fsm_next_value3[31:0] - end - attribute \src "ls180.v:1721.5-1721.67" - process $proc$ls180.v:1721$3322 - assign { } { } - assign $1\libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - end - attribute \src "ls180.v:1722.5-1722.63" - process $proc$ls180.v:1722$3323 - assign { } { } - assign $1\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_cmd_error_sdcore_fsm_next_value4 $1\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - end - attribute \src "ls180.v:1723.5-1723.66" - process $proc$ls180.v:1723$3324 - assign { } { } - assign $1\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - end - attribute \src "ls180.v:1724.5-1724.65" - process $proc$ls180.v:1724$3325 - assign { } { } - assign $1\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - end - attribute \src "ls180.v:1725.5-1725.68" - process $proc$ls180.v:1725$3326 - assign { } { } - assign $1\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - end - attribute \src "ls180.v:1726.5-1726.64" - process $proc$ls180.v:1726$3327 - assign { } { } - assign $1\libresocsim_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_data_error_sdcore_fsm_next_value6 $1\libresocsim_sdcore_data_error_sdcore_fsm_next_value6[0:0] - end - attribute \src "ls180.v:1727.5-1727.67" - process $proc$ls180.v:1727$3328 - assign { } { } - assign $1\libresocsim_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\libresocsim_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - end - attribute \src "ls180.v:1728.5-1728.66" - process $proc$ls180.v:1728$3329 - assign { } { } - assign $1\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_data_timeout_sdcore_fsm_next_value7 $1\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - end - attribute \src "ls180.v:1729.5-1729.69" - process $proc$ls180.v:1729$3330 - assign { } { } - assign $1\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - end - attribute \src "ls180.v:1730.13-1730.83" - process $proc$ls180.v:1730$3331 - assign { } { } - assign $1\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - end - attribute \src "ls180.v:1731.5-1731.76" - process $proc$ls180.v:1731$3332 - assign { } { } - assign $1\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 - sync always - sync init - update \libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - end - attribute \src "ls180.v:1732.11-1732.46" - process $proc$ls180.v:1732$3333 - assign { } { } - assign $1\builder_sdblock2memdma_state[1:0] 2'00 - sync always - sync init - update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0] - end - attribute \src "ls180.v:1733.11-1733.51" - process $proc$ls180.v:1733$3334 - assign { } { } - assign $1\builder_sdblock2memdma_next_state[1:0] 2'00 - sync always - sync init - update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0] - end - attribute \src "ls180.v:1734.12-1734.94" - process $proc$ls180.v:1734$3335 - assign { } { } - assign $1\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - sync always - sync init - update \libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - end - attribute \src "ls180.v:1735.5-1735.89" - process $proc$ls180.v:1735$3336 - assign { } { } - assign $1\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 - sync always - sync init - update \libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - end - attribute \src "ls180.v:1736.5-1736.44" - process $proc$ls180.v:1736$3337 - assign { } { } - assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0 - sync always - sync init - update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0] - end - attribute \src "ls180.v:1737.5-1737.49" - process $proc$ls180.v:1737$3338 - assign { } { } - assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 - sync always - sync init - update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0] - end - attribute \src "ls180.v:1738.12-1738.82" - process $proc$ls180.v:1738$3339 - assign { } { } - assign $1\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 - sync always - sync init - update \libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] - end - attribute \src "ls180.v:1739.5-1739.77" - process $proc$ls180.v:1739$3340 - assign { } { } - assign $1\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 - sync always - sync init - update \libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - end - attribute \src "ls180.v:1740.11-1740.60" - process $proc$ls180.v:1740$3341 - assign { } { } - assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 - sync always - sync init - update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0] - end - attribute \src "ls180.v:1741.11-1741.65" - process $proc$ls180.v:1741$3342 - assign { } { } - assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00 - sync always - sync init - update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] - end - attribute \src "ls180.v:1742.12-1742.94" - process $proc$ls180.v:1742$3343 - assign { } { } - assign $1\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - sync always - sync init - update \libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - end - attribute \src "ls180.v:1743.5-1743.89" - process $proc$ls180.v:1743$3344 - assign { } { } - assign $1\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 - sync always - sync init - update \libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - end - attribute \src "ls180.v:1744.11-1744.42" - process $proc$ls180.v:1744$3345 - assign { } { } - assign $1\builder_spimaster1_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] - end - attribute \src "ls180.v:1745.11-1745.47" - process $proc$ls180.v:1745$3346 - assign { } { } - assign $1\builder_spimaster1_next_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] - end - attribute \src "ls180.v:1746.11-1746.57" - process $proc$ls180.v:1746$3347 - assign { } { } - assign $1\libresocsim_count_spimaster1_next_value[2:0] 3'000 - sync always - sync init - update \libresocsim_count_spimaster1_next_value $1\libresocsim_count_spimaster1_next_value[2:0] - end - attribute \src "ls180.v:1747.5-1747.54" - process $proc$ls180.v:1747$3348 - assign { } { } - assign $1\libresocsim_count_spimaster1_next_value_ce[0:0] 1'0 - sync always - sync init - update \libresocsim_count_spimaster1_next_value_ce $1\libresocsim_count_spimaster1_next_value_ce[0:0] - end - attribute \src "ls180.v:1748.12-1748.43" - process $proc$ls180.v:1748$3349 - assign { } { } - assign $1\builder_libresocsim_adr[13:0] 14'00000000000000 - sync always - sync init - update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0] - end - attribute \src "ls180.v:1749.5-1749.34" - process $proc$ls180.v:1749$3350 - assign { } { } - assign $1\builder_libresocsim_we[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_we $1\builder_libresocsim_we[0:0] - end - attribute \src "ls180.v:1750.11-1750.43" - process $proc$ls180.v:1750$3351 - assign { } { } - assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 - sync always - sync init - update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] - end - attribute \src "ls180.v:1754.12-1754.54" - process $proc$ls180.v:1754$3352 - assign { } { } - assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 - sync always - sync init - update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] - end - attribute \src "ls180.v:1758.5-1758.44" - process $proc$ls180.v:1758$3353 - assign { } { } - assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] - end - attribute \src "ls180.v:176.5-176.44" - process $proc$ls180.v:176$2620 - assign { } { } - assign $1\main_libresocsim_uart_tx_pending[0:0] 1'0 - sync always - sync init - update \main_libresocsim_uart_tx_pending $1\main_libresocsim_uart_tx_pending[0:0] - end - attribute \src "ls180.v:1762.5-1762.44" - process $proc$ls180.v:1762$3354 - assign { } { } - assign $0\builder_libresocsim_wishbone_err[0:0] 1'0 - sync always - update \builder_libresocsim_wishbone_err $0\builder_libresocsim_wishbone_err[0:0] - sync init - end - attribute \src "ls180.v:1765.12-1765.40" - process $proc$ls180.v:1765$3355 - assign { } { } - assign $1\builder_shared_dat_r[31:0] 0 - sync always - sync init - update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] - end - attribute \src "ls180.v:1769.5-1769.30" - process $proc$ls180.v:1769$3356 - assign { } { } - assign $1\builder_shared_ack[0:0] 1'0 - sync always - sync init - update \builder_shared_ack $1\builder_shared_ack[0:0] - end - attribute \src "ls180.v:1775.11-1775.31" - process $proc$ls180.v:1775$3357 - assign { } { } - assign $1\builder_grant[1:0] 2'00 - sync always - sync init - update \builder_grant $1\builder_grant[1:0] - end - attribute \src "ls180.v:1776.11-1776.35" - process $proc$ls180.v:1776$3358 - assign { } { } - assign $1\builder_slave_sel[4:0] 5'00000 - sync always - sync init - update \builder_slave_sel $1\builder_slave_sel[4:0] - end - attribute \src "ls180.v:1777.11-1777.37" - process $proc$ls180.v:1777$3359 - assign { } { } - assign $1\builder_slave_sel_r[4:0] 5'00000 - sync always - sync init - update \builder_slave_sel_r $1\builder_slave_sel_r[4:0] - end - attribute \src "ls180.v:1778.5-1778.25" - process $proc$ls180.v:1778$3360 - assign { } { } - assign $1\builder_error[0:0] 1'0 - sync always - sync init - update \builder_error $1\builder_error[0:0] - end - attribute \src "ls180.v:178.5-178.42" - process $proc$ls180.v:178$2621 - assign { } { } - assign $1\main_libresocsim_uart_tx_clear[0:0] 1'0 - sync always - sync init - update \main_libresocsim_uart_tx_clear $1\main_libresocsim_uart_tx_clear[0:0] - end - attribute \src "ls180.v:1781.12-1781.39" - process $proc$ls180.v:1781$3361 - assign { } { } - assign $1\builder_count[19:0] 20'11110100001001000000 - sync always - sync init - update \builder_count $1\builder_count[19:0] - end - attribute \src "ls180.v:1785.11-1785.51" - process $proc$ls180.v:1785$3362 - assign { } { } - assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:179.5-179.48" - process $proc$ls180.v:179$2622 - assign { } { } - assign $1\main_libresocsim_uart_tx_old_trigger[0:0] 1'0 - sync always - sync init - update \main_libresocsim_uart_tx_old_trigger $1\main_libresocsim_uart_tx_old_trigger[0:0] - end - attribute \src "ls180.v:181.5-181.44" - process $proc$ls180.v:181$2623 - assign { } { } - assign $1\main_libresocsim_uart_rx_pending[0:0] 1'0 - sync always - sync init - update \main_libresocsim_uart_rx_pending $1\main_libresocsim_uart_rx_pending[0:0] - end - attribute \src "ls180.v:1826.11-1826.51" - process $proc$ls180.v:1826$3363 - assign { } { } - assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:183.5-183.42" - process $proc$ls180.v:183$2624 - assign { } { } - assign $1\main_libresocsim_uart_rx_clear[0:0] 1'0 - sync always - sync init - update \main_libresocsim_uart_rx_clear $1\main_libresocsim_uart_rx_clear[0:0] - end - attribute \src "ls180.v:1835.11-1835.51" - process $proc$ls180.v:1835$3364 - assign { } { } - assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:184.5-184.48" - process $proc$ls180.v:184$2625 - assign { } { } - assign $1\main_libresocsim_uart_rx_old_trigger[0:0] 1'0 - sync always - sync init - update \main_libresocsim_uart_rx_old_trigger $1\main_libresocsim_uart_rx_old_trigger[0:0] - end - attribute \src "ls180.v:1844.11-1844.51" - process $proc$ls180.v:1844$3365 - assign { } { } - assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:188.11-188.61" - process $proc$ls180.v:188$2626 - assign { } { } - assign $1\main_libresocsim_uart_eventmanager_status_w[1:0] 2'00 - sync always - sync init - update \main_libresocsim_uart_eventmanager_status_w $1\main_libresocsim_uart_eventmanager_status_w[1:0] - end - attribute \src "ls180.v:1909.11-1909.51" - process $proc$ls180.v:1909$3366 - assign { } { } - assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:192.11-192.62" - process $proc$ls180.v:192$2627 - assign { } { } - assign $1\main_libresocsim_uart_eventmanager_pending_w[1:0] 2'00 - sync always - sync init - update \main_libresocsim_uart_eventmanager_pending_w $1\main_libresocsim_uart_eventmanager_pending_w[1:0] - end - attribute \src "ls180.v:193.11-193.60" - process $proc$ls180.v:193$2628 - assign { } { } - assign $1\main_libresocsim_uart_eventmanager_storage[1:0] 2'00 - sync always - sync init - update \main_libresocsim_uart_eventmanager_storage $1\main_libresocsim_uart_eventmanager_storage[1:0] - end - attribute \src "ls180.v:194.5-194.49" - process $proc$ls180.v:194$2629 - assign { } { } - assign $1\main_libresocsim_uart_eventmanager_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_uart_eventmanager_re $1\main_libresocsim_uart_eventmanager_re[0:0] - end - attribute \src "ls180.v:2042.11-2042.51" - process $proc$ls180.v:2042$3367 - assign { } { } - assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:211.5-211.52" - process $proc$ls180.v:211$2630 - assign { } { } - assign $0\main_libresocsim_uart_tx_fifo_sink_first[0:0] 1'0 - sync always - update \main_libresocsim_uart_tx_fifo_sink_first $0\main_libresocsim_uart_tx_fifo_sink_first[0:0] - sync init - end - attribute \src "ls180.v:212.5-212.51" - process $proc$ls180.v:212$2631 - assign { } { } - assign $0\main_libresocsim_uart_tx_fifo_sink_last[0:0] 1'0 - sync always - update \main_libresocsim_uart_tx_fifo_sink_last $0\main_libresocsim_uart_tx_fifo_sink_last[0:0] - sync init - end - attribute \src "ls180.v:2123.11-2123.51" - process $proc$ls180.v:2123$3368 - assign { } { } - assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2140.11-2140.51" - process $proc$ls180.v:2140$3369 - assign { } { } - assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2181.11-2181.51" - process $proc$ls180.v:2181$3370 - assign { } { } - assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:220.5-220.50" - process $proc$ls180.v:220$2632 - assign { } { } - assign $1\main_libresocsim_uart_tx_fifo_readable[0:0] 1'0 - sync always - sync init - update \main_libresocsim_uart_tx_fifo_readable $1\main_libresocsim_uart_tx_fifo_readable[0:0] - end - attribute \src "ls180.v:2214.11-2214.51" - process $proc$ls180.v:2214$3371 - assign { } { } - assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2255.11-2255.52" - process $proc$ls180.v:2255$3372 - assign { } { } - assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:227.11-227.54" - process $proc$ls180.v:227$2633 - assign { } { } - assign $1\main_libresocsim_uart_tx_fifo_level0[4:0] 5'00000 - sync always - sync init - update \main_libresocsim_uart_tx_fifo_level0 $1\main_libresocsim_uart_tx_fifo_level0[4:0] - end - attribute \src "ls180.v:228.5-228.49" - process $proc$ls180.v:228$2634 - assign { } { } - assign $0\main_libresocsim_uart_tx_fifo_replace[0:0] 1'0 - sync always - update \main_libresocsim_uart_tx_fifo_replace $0\main_libresocsim_uart_tx_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:229.11-229.55" - process $proc$ls180.v:229$2635 - assign { } { } - assign $1\main_libresocsim_uart_tx_fifo_produce[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_uart_tx_fifo_produce $1\main_libresocsim_uart_tx_fifo_produce[3:0] - end - attribute \src "ls180.v:230.11-230.55" - process $proc$ls180.v:230$2636 - assign { } { } - assign $1\main_libresocsim_uart_tx_fifo_consume[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_uart_tx_fifo_consume $1\main_libresocsim_uart_tx_fifo_consume[3:0] - end - attribute \src "ls180.v:231.11-231.58" - process $proc$ls180.v:231$2637 - assign { } { } - assign $1\main_libresocsim_uart_tx_fifo_wrport_adr[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_uart_tx_fifo_wrport_adr $1\main_libresocsim_uart_tx_fifo_wrport_adr[3:0] - end - attribute \src "ls180.v:2320.11-2320.52" - process $proc$ls180.v:2320$3373 - assign { } { } - assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2345.11-2345.52" - process $proc$ls180.v:2345$3374 - assign { } { } - assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2367.11-2367.31" - process $proc$ls180.v:2367$3375 - assign { } { } - assign $1\builder_state[1:0] 2'00 - sync always - sync init - update \builder_state $1\builder_state[1:0] - end - attribute \src "ls180.v:2368.11-2368.36" - process $proc$ls180.v:2368$3376 - assign { } { } - assign $1\builder_next_state[1:0] 2'00 - sync always - sync init - update \builder_next_state $1\builder_next_state[1:0] - end - attribute \src "ls180.v:2369.11-2369.55" - process $proc$ls180.v:2369$3377 - assign { } { } - assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 - sync always - sync init - update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0] - end - attribute \src "ls180.v:2370.5-2370.52" - process $proc$ls180.v:2370$3378 - assign { } { } - assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0] - end - attribute \src "ls180.v:2371.12-2371.55" - process $proc$ls180.v:2371$3379 - assign { } { } - assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 - sync always - sync init - update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0] - end - attribute \src "ls180.v:2372.5-2372.50" - process $proc$ls180.v:2372$3380 - assign { } { } - assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0] - end - attribute \src "ls180.v:2373.5-2373.46" - process $proc$ls180.v:2373$3381 - assign { } { } - assign $1\builder_libresocsim_we_next_value2[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0] - end - attribute \src "ls180.v:2374.5-2374.49" - process $proc$ls180.v:2374$3382 - assign { } { } - assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0] - end - attribute \src "ls180.v:2375.5-2375.41" - process $proc$ls180.v:2375$3383 - assign { } { } - assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0] - end - attribute \src "ls180.v:2376.12-2376.49" - process $proc$ls180.v:2376$3384 - assign { } { } - assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0] - end - attribute \src "ls180.v:2377.11-2377.47" - process $proc$ls180.v:2377$3385 - assign { } { } - assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00 - sync always - sync init - update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0] - end - attribute \src "ls180.v:2378.5-2378.41" - process $proc$ls180.v:2378$3386 - assign { } { } - assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0] - end - attribute \src "ls180.v:2379.5-2379.41" - process $proc$ls180.v:2379$3387 - assign { } { } - assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0] - end - attribute \src "ls180.v:2380.5-2380.41" - process $proc$ls180.v:2380$3388 - assign { } { } - assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0] - end - attribute \src "ls180.v:2381.5-2381.39" - process $proc$ls180.v:2381$3389 - assign { } { } - assign $1\builder_comb_t_array_muxed0[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0] - end - attribute \src "ls180.v:2382.5-2382.39" - process $proc$ls180.v:2382$3390 - assign { } { } - assign $1\builder_comb_t_array_muxed1[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0] - end - attribute \src "ls180.v:2383.5-2383.39" - process $proc$ls180.v:2383$3391 - assign { } { } - assign $1\builder_comb_t_array_muxed2[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0] - end - attribute \src "ls180.v:2384.5-2384.41" - process $proc$ls180.v:2384$3392 - assign { } { } - assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0] - end - attribute \src "ls180.v:2385.12-2385.49" - process $proc$ls180.v:2385$3393 - assign { } { } - assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0] - end - attribute \src "ls180.v:2386.11-2386.47" - process $proc$ls180.v:2386$3394 - assign { } { } - assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00 - sync always - sync init - update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0] - end - attribute \src "ls180.v:2387.5-2387.41" - process $proc$ls180.v:2387$3395 - assign { } { } - assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0] - end - attribute \src "ls180.v:2388.5-2388.42" - process $proc$ls180.v:2388$3396 - assign { } { } - assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0] - end - attribute \src "ls180.v:2389.5-2389.42" - process $proc$ls180.v:2389$3397 - assign { } { } - assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0] - end - attribute \src "ls180.v:2390.5-2390.39" - process $proc$ls180.v:2390$3398 - assign { } { } - assign $1\builder_comb_t_array_muxed3[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0] - end - attribute \src "ls180.v:2391.5-2391.39" - process $proc$ls180.v:2391$3399 - assign { } { } - assign $1\builder_comb_t_array_muxed4[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0] - end - attribute \src "ls180.v:2392.5-2392.39" - process $proc$ls180.v:2392$3400 - assign { } { } - assign $1\builder_comb_t_array_muxed5[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0] - end - attribute \src "ls180.v:2393.12-2393.50" - process $proc$ls180.v:2393$3401 - assign { } { } - assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0] - end - attribute \src "ls180.v:2394.5-2394.42" - process $proc$ls180.v:2394$3402 - assign { } { } - assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0] - end - attribute \src "ls180.v:2395.5-2395.42" - process $proc$ls180.v:2395$3403 - assign { } { } - assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0] - end - attribute \src "ls180.v:2396.12-2396.50" - process $proc$ls180.v:2396$3404 - assign { } { } - assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0] - end - attribute \src "ls180.v:2397.5-2397.42" - process $proc$ls180.v:2397$3405 - assign { } { } - assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0] - end - attribute \src "ls180.v:2398.5-2398.42" - process $proc$ls180.v:2398$3406 - assign { } { } - assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0] - end - attribute \src "ls180.v:2399.12-2399.50" - process $proc$ls180.v:2399$3407 - assign { } { } - assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0] - end - attribute \src "ls180.v:2400.5-2400.42" - process $proc$ls180.v:2400$3408 - assign { } { } - assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0] - end - attribute \src "ls180.v:2401.5-2401.42" - process $proc$ls180.v:2401$3409 - assign { } { } - assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0] - end - attribute \src "ls180.v:2402.12-2402.50" - process $proc$ls180.v:2402$3410 - assign { } { } - assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0] - end - attribute \src "ls180.v:2403.5-2403.42" - process $proc$ls180.v:2403$3411 - assign { } { } - assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0] - end - attribute \src "ls180.v:2404.5-2404.42" - process $proc$ls180.v:2404$3412 - assign { } { } - assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0] - end - attribute \src "ls180.v:2405.12-2405.50" - process $proc$ls180.v:2405$3413 - assign { } { } - assign $1\builder_comb_rhs_array_muxed24[31:0] 0 - sync always - sync init - update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0] - end - attribute \src "ls180.v:2406.12-2406.50" - process $proc$ls180.v:2406$3414 - assign { } { } - assign $1\builder_comb_rhs_array_muxed25[31:0] 0 - sync always - sync init - update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[31:0] - end - attribute \src "ls180.v:2407.11-2407.48" - process $proc$ls180.v:2407$3415 - assign { } { } - assign $1\builder_comb_rhs_array_muxed26[3:0] 4'0000 - sync always - sync init - update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[3:0] - end - attribute \src "ls180.v:2408.5-2408.42" - process $proc$ls180.v:2408$3416 - assign { } { } - assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] - end - attribute \src "ls180.v:2409.5-2409.42" - process $proc$ls180.v:2409$3417 - assign { } { } - assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0] - end - attribute \src "ls180.v:2410.5-2410.42" - process $proc$ls180.v:2410$3418 - assign { } { } - assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0] - end - attribute \src "ls180.v:2411.11-2411.48" - process $proc$ls180.v:2411$3419 - assign { } { } - assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000 - sync always - sync init - update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0] - end - attribute \src "ls180.v:2412.11-2412.48" - process $proc$ls180.v:2412$3420 - assign { } { } - assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00 - sync always - sync init - update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0] - end - attribute \src "ls180.v:2413.11-2413.47" - process $proc$ls180.v:2413$3421 - assign { } { } - assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00 - sync always - sync init - update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0] - end - attribute \src "ls180.v:2414.12-2414.49" - process $proc$ls180.v:2414$3422 - assign { } { } - assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 - sync always - sync init - update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0] - end - attribute \src "ls180.v:2415.5-2415.41" - process $proc$ls180.v:2415$3423 - assign { } { } - assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0 - sync always - sync init - update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0] - end - attribute \src "ls180.v:2416.5-2416.41" - process $proc$ls180.v:2416$3424 - assign { } { } - assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0 - sync always - sync init - update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0] - end - attribute \src "ls180.v:2417.5-2417.41" - process $proc$ls180.v:2417$3425 - assign { } { } - assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0 - sync always - sync init - update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0] - end - attribute \src "ls180.v:2418.5-2418.41" - process $proc$ls180.v:2418$3426 - assign { } { } - assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0 - sync always - sync init - update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0] - end - attribute \src "ls180.v:2419.5-2419.41" - process $proc$ls180.v:2419$3427 - assign { } { } - assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0 - sync always - sync init - update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0] - end - attribute \src "ls180.v:2420.5-2420.39" - process $proc$ls180.v:2420$3428 - assign { } { } - assign $1\builder_sync_f_array_muxed0[0:0] 1'0 - sync always - sync init - update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0] - end - attribute \src "ls180.v:2421.5-2421.39" - process $proc$ls180.v:2421$3429 - assign { } { } - assign $1\builder_sync_f_array_muxed1[0:0] 1'0 - sync always - sync init - update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0] - end - attribute \src "ls180.v:2422.32-2422.66" - process $proc$ls180.v:2422$3430 - assign { } { } - assign $1\builder_multiregimpl0_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0] - end - attribute \src "ls180.v:2423.32-2423.66" - process $proc$ls180.v:2423$3431 - assign { } { } - assign $1\builder_multiregimpl0_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0] - end - attribute \src "ls180.v:2444.5-2444.42" - process $proc$ls180.v:2444$3432 - assign { } { } - assign $1\builder_inferedsdrtristate0__o[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate0__o $1\builder_inferedsdrtristate0__o[0:0] - end - attribute \src "ls180.v:2445.5-2445.42" - process $proc$ls180.v:2445$3433 - assign { } { } - assign $1\builder_inferedsdrtristate0_oe[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate0_oe $1\builder_inferedsdrtristate0_oe[0:0] - end - attribute \src "ls180.v:2448.5-2448.42" - process $proc$ls180.v:2448$3434 - assign { } { } - assign $1\builder_inferedsdrtristate1__o[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate1__o $1\builder_inferedsdrtristate1__o[0:0] - end - attribute \src "ls180.v:2449.5-2449.42" - process $proc$ls180.v:2449$3435 - assign { } { } - assign $1\builder_inferedsdrtristate1_oe[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate1_oe $1\builder_inferedsdrtristate1_oe[0:0] - end - attribute \src "ls180.v:2452.5-2452.42" - process $proc$ls180.v:2452$3436 - assign { } { } - assign $1\builder_inferedsdrtristate2__o[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate2__o $1\builder_inferedsdrtristate2__o[0:0] - end - attribute \src "ls180.v:2453.5-2453.42" - process $proc$ls180.v:2453$3437 - assign { } { } - assign $1\builder_inferedsdrtristate2_oe[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate2_oe $1\builder_inferedsdrtristate2_oe[0:0] - end - attribute \src "ls180.v:2456.5-2456.42" - process $proc$ls180.v:2456$3438 - assign { } { } - assign $1\builder_inferedsdrtristate3__o[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate3__o $1\builder_inferedsdrtristate3__o[0:0] - end - attribute \src "ls180.v:2457.5-2457.42" - process $proc$ls180.v:2457$3439 - assign { } { } - assign $1\builder_inferedsdrtristate3_oe[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate3_oe $1\builder_inferedsdrtristate3_oe[0:0] - end - attribute \src "ls180.v:2460.5-2460.42" - process $proc$ls180.v:2460$3440 - assign { } { } - assign $1\builder_inferedsdrtristate4__o[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate4__o $1\builder_inferedsdrtristate4__o[0:0] - end - attribute \src "ls180.v:2461.5-2461.42" - process $proc$ls180.v:2461$3441 - assign { } { } - assign $1\builder_inferedsdrtristate4_oe[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate4_oe $1\builder_inferedsdrtristate4_oe[0:0] - end - attribute \src "ls180.v:2464.5-2464.42" - process $proc$ls180.v:2464$3442 - assign { } { } - assign $1\builder_inferedsdrtristate5__o[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate5__o $1\builder_inferedsdrtristate5__o[0:0] - end - attribute \src "ls180.v:2465.5-2465.42" - process $proc$ls180.v:2465$3443 - assign { } { } - assign $1\builder_inferedsdrtristate5_oe[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate5_oe $1\builder_inferedsdrtristate5_oe[0:0] - end - attribute \src "ls180.v:2468.5-2468.42" - process $proc$ls180.v:2468$3444 - assign { } { } - assign $1\builder_inferedsdrtristate6__o[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate6__o $1\builder_inferedsdrtristate6__o[0:0] - end - attribute \src "ls180.v:2469.5-2469.42" - process $proc$ls180.v:2469$3445 - assign { } { } - assign $1\builder_inferedsdrtristate6_oe[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate6_oe $1\builder_inferedsdrtristate6_oe[0:0] - end - attribute \src "ls180.v:2472.5-2472.42" - process $proc$ls180.v:2472$3446 - assign { } { } - assign $1\builder_inferedsdrtristate7__o[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate7__o $1\builder_inferedsdrtristate7__o[0:0] - end - attribute \src "ls180.v:2473.5-2473.42" - process $proc$ls180.v:2473$3447 - assign { } { } - assign $1\builder_inferedsdrtristate7_oe[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate7_oe $1\builder_inferedsdrtristate7_oe[0:0] - end - attribute \src "ls180.v:2476.5-2476.42" - process $proc$ls180.v:2476$3448 - assign { } { } - assign $1\builder_inferedsdrtristate8__o[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate8__o $1\builder_inferedsdrtristate8__o[0:0] - end - attribute \src "ls180.v:2477.5-2477.42" - process $proc$ls180.v:2477$3449 - assign { } { } - assign $1\builder_inferedsdrtristate8_oe[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate8_oe $1\builder_inferedsdrtristate8_oe[0:0] - end - attribute \src "ls180.v:2480.5-2480.42" - process $proc$ls180.v:2480$3450 - assign { } { } - assign $1\builder_inferedsdrtristate9__o[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate9__o $1\builder_inferedsdrtristate9__o[0:0] - end - attribute \src "ls180.v:2481.5-2481.42" - process $proc$ls180.v:2481$3451 - assign { } { } - assign $1\builder_inferedsdrtristate9_oe[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate9_oe $1\builder_inferedsdrtristate9_oe[0:0] - end - attribute \src "ls180.v:2484.5-2484.43" - process $proc$ls180.v:2484$3452 - assign { } { } - assign $1\builder_inferedsdrtristate10__o[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate10__o $1\builder_inferedsdrtristate10__o[0:0] - end - attribute \src "ls180.v:2485.5-2485.43" - process $proc$ls180.v:2485$3453 - assign { } { } - assign $1\builder_inferedsdrtristate10_oe[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate10_oe $1\builder_inferedsdrtristate10_oe[0:0] - end - attribute \src "ls180.v:2488.5-2488.43" - process $proc$ls180.v:2488$3454 - assign { } { } - assign $1\builder_inferedsdrtristate11__o[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate11__o $1\builder_inferedsdrtristate11__o[0:0] - end - attribute \src "ls180.v:2489.5-2489.43" - process $proc$ls180.v:2489$3455 - assign { } { } - assign $1\builder_inferedsdrtristate11_oe[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate11_oe $1\builder_inferedsdrtristate11_oe[0:0] - end - attribute \src "ls180.v:2492.5-2492.43" - process $proc$ls180.v:2492$3456 - assign { } { } - assign $1\builder_inferedsdrtristate12__o[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate12__o $1\builder_inferedsdrtristate12__o[0:0] - end - attribute \src "ls180.v:2493.5-2493.43" - process $proc$ls180.v:2493$3457 - assign { } { } - assign $1\builder_inferedsdrtristate12_oe[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate12_oe $1\builder_inferedsdrtristate12_oe[0:0] - end - attribute \src "ls180.v:2496.5-2496.43" - process $proc$ls180.v:2496$3458 - assign { } { } - assign $1\builder_inferedsdrtristate13__o[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate13__o $1\builder_inferedsdrtristate13__o[0:0] - end - attribute \src "ls180.v:2497.5-2497.43" - process $proc$ls180.v:2497$3459 - assign { } { } - assign $1\builder_inferedsdrtristate13_oe[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate13_oe $1\builder_inferedsdrtristate13_oe[0:0] - end - attribute \src "ls180.v:2500.5-2500.43" - process $proc$ls180.v:2500$3460 - assign { } { } - assign $1\builder_inferedsdrtristate14__o[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate14__o $1\builder_inferedsdrtristate14__o[0:0] - end - attribute \src "ls180.v:2501.5-2501.43" - process $proc$ls180.v:2501$3461 - assign { } { } - assign $1\builder_inferedsdrtristate14_oe[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate14_oe $1\builder_inferedsdrtristate14_oe[0:0] - end - attribute \src "ls180.v:2504.5-2504.43" - process $proc$ls180.v:2504$3462 - assign { } { } - assign $1\builder_inferedsdrtristate15__o[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate15__o $1\builder_inferedsdrtristate15__o[0:0] - end - attribute \src "ls180.v:2505.5-2505.43" - process $proc$ls180.v:2505$3463 - assign { } { } - assign $1\builder_inferedsdrtristate15_oe[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate15_oe $1\builder_inferedsdrtristate15_oe[0:0] - end - attribute \src "ls180.v:2508.38-2508.72" - process $proc$ls180.v:2508$3464 - assign { } { } - assign $1\builder_multiregimpl1_regs0[7:0] 8'00000000 - sync always - sync init - update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[7:0] - end - attribute \src "ls180.v:2509.38-2509.72" - process $proc$ls180.v:2509$3465 - assign { } { } - assign $1\builder_multiregimpl1_regs1[7:0] 8'00000000 - sync always - sync init - update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[7:0] - end - attribute \src "ls180.v:2510.38-2510.72" - process $proc$ls180.v:2510$3466 - assign { } { } - assign $1\builder_multiregimpl2_regs0[7:0] 8'00000000 - sync always - sync init - update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[7:0] - end - attribute \src "ls180.v:2511.38-2511.72" - process $proc$ls180.v:2511$3467 - assign { } { } - assign $1\builder_multiregimpl2_regs1[7:0] 8'00000000 - sync always - sync init - update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[7:0] - end - attribute \src "ls180.v:2513.5-2513.43" - process $proc$ls180.v:2513$3468 - assign { } { } - assign $1\builder_inferedsdrtristate16__o[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate16__o $1\builder_inferedsdrtristate16__o[0:0] - end - attribute \src "ls180.v:2514.5-2514.43" - process $proc$ls180.v:2514$3469 - assign { } { } - assign $1\builder_inferedsdrtristate16_oe[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate16_oe $1\builder_inferedsdrtristate16_oe[0:0] - end - attribute \src "ls180.v:2517.5-2517.43" - process $proc$ls180.v:2517$3470 - assign { } { } - assign $1\builder_inferedsdrtristate17__o[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate17__o $1\builder_inferedsdrtristate17__o[0:0] - end - attribute \src "ls180.v:2518.5-2518.43" - process $proc$ls180.v:2518$3471 - assign { } { } - assign $1\builder_inferedsdrtristate17_oe[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate17_oe $1\builder_inferedsdrtristate17_oe[0:0] - end - attribute \src "ls180.v:2521.5-2521.43" - process $proc$ls180.v:2521$3472 - assign { } { } - assign $1\builder_inferedsdrtristate18__o[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate18__o $1\builder_inferedsdrtristate18__o[0:0] - end - attribute \src "ls180.v:2522.5-2522.43" - process $proc$ls180.v:2522$3473 - assign { } { } - assign $1\builder_inferedsdrtristate18_oe[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate18_oe $1\builder_inferedsdrtristate18_oe[0:0] - end - attribute \src "ls180.v:2525.5-2525.43" - process $proc$ls180.v:2525$3474 - assign { } { } - assign $1\builder_inferedsdrtristate19__o[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate19__o $1\builder_inferedsdrtristate19__o[0:0] - end - attribute \src "ls180.v:2526.5-2526.43" - process $proc$ls180.v:2526$3475 - assign { } { } - assign $1\builder_inferedsdrtristate19_oe[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate19_oe $1\builder_inferedsdrtristate19_oe[0:0] - end - attribute \src "ls180.v:2529.5-2529.43" - process $proc$ls180.v:2529$3476 - assign { } { } - assign $1\builder_inferedsdrtristate20__o[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate20__o $1\builder_inferedsdrtristate20__o[0:0] - end - attribute \src "ls180.v:2530.5-2530.43" - process $proc$ls180.v:2530$3477 - assign { } { } - assign $1\builder_inferedsdrtristate20_oe[0:0] 1'0 - sync always - sync init - update \builder_inferedsdrtristate20_oe $1\builder_inferedsdrtristate20_oe[0:0] - end - attribute \src "ls180.v:257.5-257.50" - process $proc$ls180.v:257$2638 - assign { } { } - assign $1\main_libresocsim_uart_rx_fifo_readable[0:0] 1'0 - sync always - sync init - update \main_libresocsim_uart_rx_fifo_readable $1\main_libresocsim_uart_rx_fifo_readable[0:0] - end - attribute \src "ls180.v:2588.1-2593.4" - process $proc$ls180.v:2588$13 - assign { } { } - assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000 - assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint } - assign $0\main_libresocsim_libresoc_interrupt[15:0] [1] \main_libresocsim_timer_irq - assign $0\main_libresocsim_libresoc_interrupt[15:0] [0] \main_libresocsim_uart_irq - sync always - update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0] - end - attribute \src "ls180.v:2595.1-2605.4" - process $proc$ls180.v:2595$15 - assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:2597.2-2604.9" - switch \main_libresocsim_converter0_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [31:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [63:32] - case - end - sync always - update \main_libresocsim_interface0_converted_interface_dat_w $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:2607.1-2653.4" - process $proc$ls180.v:2607$16 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 - assign $0\main_libresocsim_converter0_skip[0:0] 1'0 - assign { } { } - assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 - assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 - assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 - assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 - assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 - assign $0\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 - assign $0\builder_converter0_next_state[0:0] \builder_converter0_state - attribute \src "ls180.v:2619.2-2652.9" - switch \builder_converter0_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] { \main_libresocsim_libresoc_ibus_adr \main_libresocsim_converter0_counter } - attribute \src "ls180.v:2622.4-2629.11" - switch \main_libresocsim_converter0_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [3:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [7:4] - case - end - attribute \src "ls180.v:2630.4-2643.7" - switch $and$ls180.v:2630$17_Y - attribute \src "ls180.v:2630.8-2630.81" - case 1'1 - assign $0\main_libresocsim_converter0_skip[0:0] $eq$ls180.v:2631$18_Y - assign $0\main_libresocsim_interface0_converted_interface_we[0:0] \main_libresocsim_libresoc_ibus_we - assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:2633$19_Y - assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:2634$20_Y - attribute \src "ls180.v:2635.5-2642.8" - switch $or$ls180.v:2635$21_Y - attribute \src "ls180.v:2635.9-2635.97" - case 1'1 - assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2636$22_Y - assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2638.6-2641.9" - switch $eq$ls180.v:2638$23_Y - attribute \src "ls180.v:2638.10-2638.55" - case 1'1 - assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'1 - assign $0\builder_converter0_next_state[0:0] 1'0 - case - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2648.4-2650.7" - switch $and$ls180.v:2648$24_Y - attribute \src "ls180.v:2648.8-2648.81" - case 1'1 - assign $0\builder_converter0_next_state[0:0] 1'1 - case - end - end - sync always - update \main_libresocsim_libresoc_ibus_ack $0\main_libresocsim_libresoc_ibus_ack[0:0] - update \main_libresocsim_interface0_converted_interface_adr $0\main_libresocsim_interface0_converted_interface_adr[29:0] - update \main_libresocsim_interface0_converted_interface_sel $0\main_libresocsim_interface0_converted_interface_sel[3:0] - update \main_libresocsim_interface0_converted_interface_cyc $0\main_libresocsim_interface0_converted_interface_cyc[0:0] - update \main_libresocsim_interface0_converted_interface_stb $0\main_libresocsim_interface0_converted_interface_stb[0:0] - update \main_libresocsim_interface0_converted_interface_we $0\main_libresocsim_interface0_converted_interface_we[0:0] - update \main_libresocsim_converter0_skip $0\main_libresocsim_converter0_skip[0:0] - update \builder_converter0_next_state $0\builder_converter0_next_state[0:0] - update \main_libresocsim_converter0_counter_converter0_next_value $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] - update \main_libresocsim_converter0_counter_converter0_next_value_ce $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] - end - attribute \src "ls180.v:264.11-264.54" - process $proc$ls180.v:264$2639 - assign { } { } - assign $1\main_libresocsim_uart_rx_fifo_level0[4:0] 5'00000 - sync always - sync init - update \main_libresocsim_uart_rx_fifo_level0 $1\main_libresocsim_uart_rx_fifo_level0[4:0] - end - attribute \src "ls180.v:265.5-265.49" - process $proc$ls180.v:265$2640 - assign { } { } - assign $0\main_libresocsim_uart_rx_fifo_replace[0:0] 1'0 - sync always - update \main_libresocsim_uart_rx_fifo_replace $0\main_libresocsim_uart_rx_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:2655.1-2665.4" - process $proc$ls180.v:2655$26 - assign { } { } - assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:2657.2-2664.9" - switch \main_libresocsim_converter1_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [31:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [63:32] - case - end - sync always - update \main_libresocsim_interface1_converted_interface_dat_w $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:266.11-266.55" - process $proc$ls180.v:266$2641 - assign { } { } - assign $1\main_libresocsim_uart_rx_fifo_produce[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_uart_rx_fifo_produce $1\main_libresocsim_uart_rx_fifo_produce[3:0] - end - attribute \src "ls180.v:2667.1-2713.4" - process $proc$ls180.v:2667$27 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 - assign { } { } - assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 - assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 - assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 - assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 - assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 - assign $0\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 - assign $0\main_libresocsim_converter1_skip[0:0] 1'0 - assign $0\builder_converter1_next_state[0:0] \builder_converter1_state - attribute \src "ls180.v:2679.2-2712.9" - switch \builder_converter1_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] { \main_libresocsim_libresoc_dbus_adr \main_libresocsim_converter1_counter } - attribute \src "ls180.v:2682.4-2689.11" - switch \main_libresocsim_converter1_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [3:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [7:4] - case - end - attribute \src "ls180.v:2690.4-2703.7" - switch $and$ls180.v:2690$28_Y - attribute \src "ls180.v:2690.8-2690.81" - case 1'1 - assign $0\main_libresocsim_converter1_skip[0:0] $eq$ls180.v:2691$29_Y - assign $0\main_libresocsim_interface1_converted_interface_we[0:0] \main_libresocsim_libresoc_dbus_we - assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:2693$30_Y - assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:2694$31_Y - attribute \src "ls180.v:2695.5-2702.8" - switch $or$ls180.v:2695$32_Y - attribute \src "ls180.v:2695.9-2695.97" - case 1'1 - assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2696$33_Y - assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2698.6-2701.9" - switch $eq$ls180.v:2698$34_Y - attribute \src "ls180.v:2698.10-2698.55" - case 1'1 - assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'1 - assign $0\builder_converter1_next_state[0:0] 1'0 - case - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2708.4-2710.7" - switch $and$ls180.v:2708$35_Y - attribute \src "ls180.v:2708.8-2708.81" - case 1'1 - assign $0\builder_converter1_next_state[0:0] 1'1 - case - end - end - sync always - update \main_libresocsim_libresoc_dbus_ack $0\main_libresocsim_libresoc_dbus_ack[0:0] - update \main_libresocsim_interface1_converted_interface_adr $0\main_libresocsim_interface1_converted_interface_adr[29:0] - update \main_libresocsim_interface1_converted_interface_sel $0\main_libresocsim_interface1_converted_interface_sel[3:0] - update \main_libresocsim_interface1_converted_interface_cyc $0\main_libresocsim_interface1_converted_interface_cyc[0:0] - update \main_libresocsim_interface1_converted_interface_stb $0\main_libresocsim_interface1_converted_interface_stb[0:0] - update \main_libresocsim_interface1_converted_interface_we $0\main_libresocsim_interface1_converted_interface_we[0:0] - update \main_libresocsim_converter1_skip $0\main_libresocsim_converter1_skip[0:0] - update \builder_converter1_next_state $0\builder_converter1_next_state[0:0] - update \main_libresocsim_converter1_counter_converter1_next_value $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] - update \main_libresocsim_converter1_counter_converter1_next_value_ce $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] - end - attribute \src "ls180.v:267.11-267.55" - process $proc$ls180.v:267$2642 - assign { } { } - assign $1\main_libresocsim_uart_rx_fifo_consume[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_uart_rx_fifo_consume $1\main_libresocsim_uart_rx_fifo_consume[3:0] - end - attribute \src "ls180.v:268.11-268.58" - process $proc$ls180.v:268$2643 - assign { } { } - assign $1\main_libresocsim_uart_rx_fifo_wrport_adr[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_uart_rx_fifo_wrport_adr $1\main_libresocsim_uart_rx_fifo_wrport_adr[3:0] - end - attribute \src "ls180.v:2716.1-2722.4" - process $proc$ls180.v:2716$36 - assign { } { } - assign { } { } - assign $0\main_libresocsim_we[3:0] [0] $and$ls180.v:2718$39_Y - assign $0\main_libresocsim_we[3:0] [1] $and$ls180.v:2719$42_Y - assign $0\main_libresocsim_we[3:0] [2] $and$ls180.v:2720$45_Y - assign $0\main_libresocsim_we[3:0] [3] $and$ls180.v:2721$48_Y - sync always - update \main_libresocsim_we $0\main_libresocsim_we[3:0] - end - attribute \src "ls180.v:2756.1-2761.4" - process $proc$ls180.v:2756$57 - assign { } { } - assign $0\main_libresocsim_uart_tx_clear[0:0] 1'0 - attribute \src "ls180.v:2758.2-2760.5" - switch $and$ls180.v:2758$58_Y - attribute \src "ls180.v:2758.6-2758.103" - case 1'1 - assign $0\main_libresocsim_uart_tx_clear[0:0] 1'1 - case - end - sync always - update \main_libresocsim_uart_tx_clear $0\main_libresocsim_uart_tx_clear[0:0] - end - attribute \src "ls180.v:2762.1-2766.4" - process $proc$ls180.v:2762$59 - assign { } { } - assign { } { } - assign $0\main_libresocsim_uart_eventmanager_status_w[1:0] [0] \main_libresocsim_uart_tx_status - assign $0\main_libresocsim_uart_eventmanager_status_w[1:0] [1] \main_libresocsim_uart_rx_status - sync always - update \main_libresocsim_uart_eventmanager_status_w $0\main_libresocsim_uart_eventmanager_status_w[1:0] - end - attribute \src "ls180.v:2767.1-2772.4" - process $proc$ls180.v:2767$60 - assign { } { } - assign $0\main_libresocsim_uart_rx_clear[0:0] 1'0 - attribute \src "ls180.v:2769.2-2771.5" - switch $and$ls180.v:2769$61_Y - attribute \src "ls180.v:2769.6-2769.103" - case 1'1 - assign $0\main_libresocsim_uart_rx_clear[0:0] 1'1 - case - end - sync always - update \main_libresocsim_uart_rx_clear $0\main_libresocsim_uart_rx_clear[0:0] - end - attribute \src "ls180.v:2773.1-2777.4" - process $proc$ls180.v:2773$62 - assign { } { } - assign { } { } - assign $0\main_libresocsim_uart_eventmanager_pending_w[1:0] [0] \main_libresocsim_uart_tx_pending - assign $0\main_libresocsim_uart_eventmanager_pending_w[1:0] [1] \main_libresocsim_uart_rx_pending - sync always - update \main_libresocsim_uart_eventmanager_pending_w $0\main_libresocsim_uart_eventmanager_pending_w[1:0] - end - attribute \src "ls180.v:2795.1-2802.4" - process $proc$ls180.v:2795$70 - assign { } { } - assign $0\main_libresocsim_uart_tx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:2797.2-2801.5" - switch \main_libresocsim_uart_tx_fifo_replace - attribute \src "ls180.v:2797.6-2797.43" - case 1'1 - assign $0\main_libresocsim_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:2798$71_Y - attribute \src "ls180.v:2799.6-2799.10" - case - assign $0\main_libresocsim_uart_tx_fifo_wrport_adr[3:0] \main_libresocsim_uart_tx_fifo_produce - end - sync always - update \main_libresocsim_uart_tx_fifo_wrport_adr $0\main_libresocsim_uart_tx_fifo_wrport_adr[3:0] - end - attribute \src "ls180.v:2825.1-2832.4" - process $proc$ls180.v:2825$81 - assign { } { } - assign $0\main_libresocsim_uart_rx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:2827.2-2831.5" - switch \main_libresocsim_uart_rx_fifo_replace - attribute \src "ls180.v:2827.6-2827.43" - case 1'1 - assign $0\main_libresocsim_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:2828$82_Y - attribute \src "ls180.v:2829.6-2829.10" - case - assign $0\main_libresocsim_uart_rx_fifo_wrport_adr[3:0] \main_libresocsim_uart_rx_fifo_produce - end - sync always - update \main_libresocsim_uart_rx_fifo_wrport_adr $0\main_libresocsim_uart_rx_fifo_wrport_adr[3:0] - end - attribute \src "ls180.v:283.5-283.39" - process $proc$ls180.v:283$2644 - assign { } { } - assign $0\main_libresocsim_uart_reset[0:0] 1'0 - sync always - update \main_libresocsim_uart_reset $0\main_libresocsim_uart_reset[0:0] - sync init - end - attribute \src "ls180.v:284.12-284.55" - process $proc$ls180.v:284$2645 - assign { } { } - assign $1\main_libresocsim_timer_load_storage[31:0] 0 - sync always - sync init - update \main_libresocsim_timer_load_storage $1\main_libresocsim_timer_load_storage[31:0] - end - attribute \src "ls180.v:2843.1-2848.4" - process $proc$ls180.v:2843$89 - assign { } { } - assign $0\main_libresocsim_timer_zero_clear[0:0] 1'0 - attribute \src "ls180.v:2845.2-2847.5" - switch $and$ls180.v:2845$90_Y - attribute \src "ls180.v:2845.6-2845.102" - case 1'1 - assign $0\main_libresocsim_timer_zero_clear[0:0] 1'1 - case - end - sync always - update \main_libresocsim_timer_zero_clear $0\main_libresocsim_timer_zero_clear[0:0] - end - attribute \src "ls180.v:285.5-285.42" - process $proc$ls180.v:285$2646 - assign { } { } - assign $1\main_libresocsim_timer_load_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_timer_load_re $1\main_libresocsim_timer_load_re[0:0] - end - attribute \src "ls180.v:2855.1-2859.4" - process $proc$ls180.v:2855$92 - assign { } { } - assign { } { } - assign $0\sdram_dm[1:0] [0] 1'0 - assign $0\sdram_dm[1:0] [1] 1'0 - sync always - update \sdram_dm $0\sdram_dm[1:0] - end - attribute \src "ls180.v:286.12-286.57" - process $proc$ls180.v:286$2647 - assign { } { } - assign $1\main_libresocsim_timer_reload_storage[31:0] 0 - sync always - sync init - update \main_libresocsim_timer_reload_storage $1\main_libresocsim_timer_reload_storage[31:0] - end - attribute \src "ls180.v:287.5-287.44" - process $proc$ls180.v:287$2648 - assign { } { } - assign $1\main_libresocsim_timer_reload_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_timer_reload_re $1\main_libresocsim_timer_reload_re[0:0] - end - attribute \src "ls180.v:288.5-288.45" - process $proc$ls180.v:288$2649 - assign { } { } - assign $1\main_libresocsim_timer_en_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_timer_en_storage $1\main_libresocsim_timer_en_storage[0:0] - end - attribute \src "ls180.v:289.5-289.40" - process $proc$ls180.v:289$2650 - assign { } { } - assign $1\main_libresocsim_timer_en_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_timer_en_re $1\main_libresocsim_timer_en_re[0:0] - end - attribute \src "ls180.v:2892.1-2946.4" - process $proc$ls180.v:2892$93 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_master_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_master_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_master_p0_ras_n[0:0] 1'1 - assign $0\main_sdram_master_p0_we_n[0:0] 1'1 - assign $0\main_sdram_master_p0_cke[0:0] 1'0 - assign $0\main_sdram_master_p0_odt[0:0] 1'0 - assign $0\main_sdram_master_p0_reset_n[0:0] 1'0 - assign $0\main_sdram_master_p0_act_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 - assign $0\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 - assign $0\main_sdram_inti_p0_rddata_valid[0:0] 1'0 - assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0 - assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00 - assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0 - assign $0\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 - assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0 - assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000 - assign $0\main_sdram_master_p0_bank[1:0] 2'00 - attribute \src "ls180.v:2911.2-2945.5" - switch \main_sdram_sel - attribute \src "ls180.v:2911.6-2911.20" - case 1'1 - assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address - assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank - assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_slave_p0_cas_n - assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_slave_p0_cs_n - assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_slave_p0_ras_n - assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_slave_p0_we_n - assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_slave_p0_cke - assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_slave_p0_odt - assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_slave_p0_reset_n - assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_slave_p0_act_n - assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_slave_p0_wrdata - assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_slave_p0_wrdata_en - assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_slave_p0_wrdata_mask - assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en - assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata - assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:2928.6-2928.10" - case - assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address - assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank - assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_inti_p0_cas_n - assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_inti_p0_cs_n - assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_inti_p0_ras_n - assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_inti_p0_we_n - assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_inti_p0_cke - assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_inti_p0_odt - assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_inti_p0_reset_n - assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_inti_p0_act_n - assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_inti_p0_wrdata - assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_inti_p0_wrdata_en - assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_inti_p0_wrdata_mask - assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_inti_p0_rddata_en - assign $0\main_sdram_inti_p0_rddata[15:0] \main_sdram_master_p0_rddata - assign $0\main_sdram_inti_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid - end - sync always - update \main_sdram_inti_p0_rddata $0\main_sdram_inti_p0_rddata[15:0] - update \main_sdram_inti_p0_rddata_valid $0\main_sdram_inti_p0_rddata_valid[0:0] - update \main_sdram_slave_p0_rddata $0\main_sdram_slave_p0_rddata[15:0] - update \main_sdram_slave_p0_rddata_valid $0\main_sdram_slave_p0_rddata_valid[0:0] - update \main_sdram_master_p0_address $0\main_sdram_master_p0_address[12:0] - update \main_sdram_master_p0_bank $0\main_sdram_master_p0_bank[1:0] - update \main_sdram_master_p0_cas_n $0\main_sdram_master_p0_cas_n[0:0] - update \main_sdram_master_p0_cs_n $0\main_sdram_master_p0_cs_n[0:0] - update \main_sdram_master_p0_ras_n $0\main_sdram_master_p0_ras_n[0:0] - update \main_sdram_master_p0_we_n $0\main_sdram_master_p0_we_n[0:0] - update \main_sdram_master_p0_cke $0\main_sdram_master_p0_cke[0:0] - update \main_sdram_master_p0_odt $0\main_sdram_master_p0_odt[0:0] - update \main_sdram_master_p0_reset_n $0\main_sdram_master_p0_reset_n[0:0] - update \main_sdram_master_p0_act_n $0\main_sdram_master_p0_act_n[0:0] - update \main_sdram_master_p0_wrdata $0\main_sdram_master_p0_wrdata[15:0] - update \main_sdram_master_p0_wrdata_en $0\main_sdram_master_p0_wrdata_en[0:0] - update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0] - update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0] - end - attribute \src "ls180.v:290.5-290.55" - process $proc$ls180.v:290$2651 - assign { } { } - assign $1\main_libresocsim_timer_update_value_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_timer_update_value_storage $1\main_libresocsim_timer_update_value_storage[0:0] - end - attribute \src "ls180.v:291.5-291.50" - process $proc$ls180.v:291$2652 - assign { } { } - assign $1\main_libresocsim_timer_update_value_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_timer_update_value_re $1\main_libresocsim_timer_update_value_re[0:0] - end - attribute \src "ls180.v:292.12-292.55" - process $proc$ls180.v:292$2653 - assign { } { } - assign $1\main_libresocsim_timer_value_status[31:0] 0 - sync always - sync init - update \main_libresocsim_timer_value_status $1\main_libresocsim_timer_value_status[31:0] - end - attribute \src "ls180.v:2950.1-2966.4" - process $proc$ls180.v:2950$94 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 - attribute \src "ls180.v:2955.2-2965.5" - switch \main_sdram_command_issue_re - attribute \src "ls180.v:2955.6-2955.33" - case 1'1 - assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:2956$95_Y - assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:2957$96_Y - assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:2958$97_Y - assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:2959$98_Y - attribute \src "ls180.v:2960.6-2960.10" - case - assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 - end - sync always - update \main_sdram_inti_p0_cas_n $0\main_sdram_inti_p0_cas_n[0:0] - update \main_sdram_inti_p0_cs_n $0\main_sdram_inti_p0_cs_n[0:0] - update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0] - update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0] - end - attribute \src "ls180.v:296.5-296.47" - process $proc$ls180.v:296$2654 - assign { } { } - assign $1\main_libresocsim_timer_zero_pending[0:0] 1'0 - sync always - sync init - update \main_libresocsim_timer_zero_pending $1\main_libresocsim_timer_zero_pending[0:0] - end - attribute \src "ls180.v:298.5-298.45" - process $proc$ls180.v:298$2655 - assign { } { } - assign $1\main_libresocsim_timer_zero_clear[0:0] 1'0 - sync always - sync init - update \main_libresocsim_timer_zero_clear $1\main_libresocsim_timer_zero_clear[0:0] - end - attribute \src "ls180.v:299.5-299.51" - process $proc$ls180.v:299$2656 - assign { } { } - assign $1\main_libresocsim_timer_zero_old_trigger[0:0] 1'0 - sync always - sync init - update \main_libresocsim_timer_zero_old_trigger $1\main_libresocsim_timer_zero_old_trigger[0:0] - end - attribute \src "ls180.v:3009.1-3039.4" - process $proc$ls180.v:3009$107 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_cmd_last[0:0] 1'0 - assign $0\main_sdram_sequencer_start0[0:0] 1'0 - assign { } { } - assign $0\main_sdram_cmd_valid[0:0] 1'0 - assign $0\builder_refresher_next_state[1:0] \builder_refresher_state - attribute \src "ls180.v:3015.2-3038.9" - switch \builder_refresher_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3018.4-3021.7" - switch \main_sdram_cmd_ready - attribute \src "ls180.v:3018.8-3018.28" - case 1'1 - assign $0\main_sdram_sequencer_start0[0:0] 1'1 - assign $0\builder_refresher_next_state[1:0] 2'10 - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3025.4-3029.7" - switch \main_sdram_sequencer_done0 - attribute \src "ls180.v:3025.8-3025.34" - case 1'1 - assign $0\main_sdram_cmd_valid[0:0] 1'0 - assign $0\main_sdram_cmd_last[0:0] 1'1 - assign $0\builder_refresher_next_state[1:0] 2'00 - case - end - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3032.4-3036.7" - switch 1'1 - attribute \src "ls180.v:3032.8-3032.12" - case 1'1 - attribute \src "ls180.v:3033.5-3035.8" - switch \main_sdram_wants_refresh - attribute \src "ls180.v:3033.9-3033.33" - case 1'1 - assign $0\builder_refresher_next_state[1:0] 2'01 - case - end - case - end - end - sync always - update \main_sdram_cmd_valid $0\main_sdram_cmd_valid[0:0] - update \main_sdram_cmd_last $0\main_sdram_cmd_last[0:0] - update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0] - update \builder_refresher_next_state $0\builder_refresher_next_state[1:0] - end - attribute \src "ls180.v:3054.1-3061.4" - process $proc$ls180.v:3054$111 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3056.2-3060.5" - switch \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:3056.6-3056.48" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3058.6-3058.10" - case - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3059$113_Y - end - sync always - update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0] - end - attribute \src "ls180.v:3065.1-3072.4" - process $proc$ls180.v:3065$120 - assign { } { } - assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3067.2-3071.5" - switch $and$ls180.v:3067$121_Y - attribute \src "ls180.v:3067.6-3067.115" - case 1'1 - attribute \src "ls180.v:3068.3-3070.6" - switch $ne$ls180.v:3068$122_Y - attribute \src "ls180.v:3068.7-3068.143" - case 1'1 - assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3069$123_Y - case - end - case - end - sync always - update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0] - end - attribute \src "ls180.v:308.5-308.55" - process $proc$ls180.v:308$2657 - assign { } { } - assign $1\main_libresocsim_timer_eventmanager_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_timer_eventmanager_storage $1\main_libresocsim_timer_eventmanager_storage[0:0] - end - attribute \src "ls180.v:3087.1-3094.4" - process $proc$ls180.v:3087$124 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3089.2-3093.5" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3089.6-3089.58" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3090$125_Y - attribute \src "ls180.v:3091.6-3091.10" - case - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - end - sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:309.5-309.50" - process $proc$ls180.v:309$2658 - assign { } { } - assign $1\main_libresocsim_timer_eventmanager_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_timer_eventmanager_re $1\main_libresocsim_timer_eventmanager_re[0:0] - end - attribute \src "ls180.v:310.12-310.48" - process $proc$ls180.v:310$2659 - assign { } { } - assign $1\main_libresocsim_timer_value[31:0] 0 - sync always - sync init - update \main_libresocsim_timer_value $1\main_libresocsim_timer_value[31:0] - end - attribute \src "ls180.v:3103.1-3196.4" - process $proc$ls180.v:3103$133 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 - assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state - attribute \src "ls180.v:3119.2-3195.9" - switch \builder_bankmachine0_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3121.4-3129.7" - switch $and$ls180.v:3121$134_Y - attribute \src "ls180.v:3121.8-3121.87" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3123.5-3125.8" - switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3123.9-3123.42" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'101 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3133.4-3135.7" - switch $and$ls180.v:3133$135_Y - attribute \src "ls180.v:3133.8-3133.87" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'101 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3139.4-3148.7" - switch \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:3139.8-3139.44" - case 1'1 - assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 - assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3144.5-3146.8" - switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3144.9-3144.42" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'110 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3151.4-3153.7" - switch \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:3151.8-3151.45" - case 1'1 - assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1 - case - end - attribute \src "ls180.v:3156.4-3158.7" - switch $not$ls180.v:3156$136_Y - attribute \src "ls180.v:3156.8-3156.46" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_bankmachine0_next_state[2:0] 3'011 - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_bankmachine0_next_state[2:0] 3'000 - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3167.4-3193.7" - switch \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:3167.8-3167.43" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'100 - attribute \src "ls180.v:3169.8-3169.12" - case - attribute \src "ls180.v:3170.5-3192.8" - switch \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:3170.9-3170.56" - case 1'1 - attribute \src "ls180.v:3171.6-3191.9" - switch \main_sdram_bankmachine0_row_opened - attribute \src "ls180.v:3171.10-3171.44" - case 1'1 - attribute \src "ls180.v:3172.7-3188.10" - switch \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:3172.11-3172.42" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3174.8-3181.11" - switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:3174.12-3174.64" - case 1'1 - assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready - assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3178.12-3178.16" - case - assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready - assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 - end - attribute \src "ls180.v:3183.8-3185.11" - switch $and$ls180.v:3183$137_Y - attribute \src "ls180.v:3183.12-3183.88" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:3186.11-3186.15" - case - assign $0\builder_bankmachine0_next_state[2:0] 3'001 - end - attribute \src "ls180.v:3189.10-3189.14" - case - assign $0\builder_bankmachine0_next_state[2:0] 3'011 - end - case - end - end - end - sync always - update \main_sdram_bankmachine0_req_wdata_ready $0\main_sdram_bankmachine0_req_wdata_ready[0:0] - update \main_sdram_bankmachine0_req_rdata_valid $0\main_sdram_bankmachine0_req_rdata_valid[0:0] - update \main_sdram_bankmachine0_refresh_gnt $0\main_sdram_bankmachine0_refresh_gnt[0:0] - update \main_sdram_bankmachine0_cmd_valid $0\main_sdram_bankmachine0_cmd_valid[0:0] - update \main_sdram_bankmachine0_cmd_payload_cas $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] - update \main_sdram_bankmachine0_cmd_payload_ras $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] - update \main_sdram_bankmachine0_cmd_payload_we $0\main_sdram_bankmachine0_cmd_payload_we[0:0] - update \main_sdram_bankmachine0_cmd_payload_is_cmd $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - update \main_sdram_bankmachine0_cmd_payload_is_read $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - update \main_sdram_bankmachine0_cmd_payload_is_write $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - update \main_sdram_bankmachine0_row_open $0\main_sdram_bankmachine0_row_open[0:0] - update \main_sdram_bankmachine0_row_close $0\main_sdram_bankmachine0_row_close[0:0] - update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0] - end - attribute \src "ls180.v:314.5-314.24" - process $proc$ls180.v:314$2660 - assign { } { } - assign $1\main_int_rst[0:0] 1'1 - sync always - sync init - update \main_int_rst $1\main_int_rst[0:0] - end - attribute \src "ls180.v:3211.1-3218.4" - process $proc$ls180.v:3211$141 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3213.2-3217.5" - switch \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:3213.6-3213.48" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3215.6-3215.10" - case - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3216$143_Y - end - sync always - update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0] - end - attribute \src "ls180.v:3222.1-3229.4" - process $proc$ls180.v:3222$150 - assign { } { } - assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3224.2-3228.5" - switch $and$ls180.v:3224$151_Y - attribute \src "ls180.v:3224.6-3224.115" - case 1'1 - attribute \src "ls180.v:3225.3-3227.6" - switch $ne$ls180.v:3225$152_Y - attribute \src "ls180.v:3225.7-3225.143" - case 1'1 - assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3226$153_Y - case - end - case - end - sync always - update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0] - end - attribute \src "ls180.v:3244.1-3251.4" - process $proc$ls180.v:3244$154 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3246.2-3250.5" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3246.6-3246.58" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3247$155_Y - attribute \src "ls180.v:3248.6-3248.10" - case - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - end - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:3260.1-3353.4" - process $proc$ls180.v:3260$163 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 - assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state - attribute \src "ls180.v:3276.2-3352.9" - switch \builder_bankmachine1_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3278.4-3286.7" - switch $and$ls180.v:3278$164_Y - attribute \src "ls180.v:3278.8-3278.87" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3280.5-3282.8" - switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3280.9-3280.42" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'101 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3290.4-3292.7" - switch $and$ls180.v:3290$165_Y - attribute \src "ls180.v:3290.8-3290.87" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'101 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3296.4-3305.7" - switch \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:3296.8-3296.44" - case 1'1 - assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 - assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3301.5-3303.8" - switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3301.9-3301.42" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'110 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3308.4-3310.7" - switch \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:3308.8-3308.45" - case 1'1 - assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1 - case - end - attribute \src "ls180.v:3313.4-3315.7" - switch $not$ls180.v:3313$166_Y - attribute \src "ls180.v:3313.8-3313.46" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_bankmachine1_next_state[2:0] 3'011 - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_bankmachine1_next_state[2:0] 3'000 - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3324.4-3350.7" - switch \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:3324.8-3324.43" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'100 - attribute \src "ls180.v:3326.8-3326.12" - case - attribute \src "ls180.v:3327.5-3349.8" - switch \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:3327.9-3327.56" - case 1'1 - attribute \src "ls180.v:3328.6-3348.9" - switch \main_sdram_bankmachine1_row_opened - attribute \src "ls180.v:3328.10-3328.44" - case 1'1 - attribute \src "ls180.v:3329.7-3345.10" - switch \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:3329.11-3329.42" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3331.8-3338.11" - switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:3331.12-3331.64" - case 1'1 - assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready - assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3335.12-3335.16" - case - assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready - assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 - end - attribute \src "ls180.v:3340.8-3342.11" - switch $and$ls180.v:3340$167_Y - attribute \src "ls180.v:3340.12-3340.88" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:3343.11-3343.15" - case - assign $0\builder_bankmachine1_next_state[2:0] 3'001 - end - attribute \src "ls180.v:3346.10-3346.14" - case - assign $0\builder_bankmachine1_next_state[2:0] 3'011 - end - case - end - end - end - sync always - update \main_sdram_bankmachine1_req_wdata_ready $0\main_sdram_bankmachine1_req_wdata_ready[0:0] - update \main_sdram_bankmachine1_req_rdata_valid $0\main_sdram_bankmachine1_req_rdata_valid[0:0] - update \main_sdram_bankmachine1_refresh_gnt $0\main_sdram_bankmachine1_refresh_gnt[0:0] - update \main_sdram_bankmachine1_cmd_valid $0\main_sdram_bankmachine1_cmd_valid[0:0] - update \main_sdram_bankmachine1_cmd_payload_cas $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] - update \main_sdram_bankmachine1_cmd_payload_ras $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] - update \main_sdram_bankmachine1_cmd_payload_we $0\main_sdram_bankmachine1_cmd_payload_we[0:0] - update \main_sdram_bankmachine1_cmd_payload_is_cmd $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - update \main_sdram_bankmachine1_cmd_payload_is_read $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - update \main_sdram_bankmachine1_cmd_payload_is_write $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - update \main_sdram_bankmachine1_row_open $0\main_sdram_bankmachine1_row_open[0:0] - update \main_sdram_bankmachine1_row_close $0\main_sdram_bankmachine1_row_close[0:0] - update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0] - end - attribute \src "ls180.v:329.12-329.38" - process $proc$ls180.v:329$2661 - assign { } { } - assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] - end - attribute \src "ls180.v:33.5-33.56" - process $proc$ls180.v:33$2563 - assign { } { } - assign $1\main_libresocsim_soccontroller_reset_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_soccontroller_reset_storage $1\main_libresocsim_soccontroller_reset_storage[0:0] - end - attribute \src "ls180.v:330.5-330.36" - process $proc$ls180.v:330$2662 - assign { } { } - assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:331.11-331.32" - process $proc$ls180.v:331$2663 - assign { } { } - assign $1\main_rddata_en[2:0] 3'000 - sync always - sync init - update \main_rddata_en $1\main_rddata_en[2:0] - end - attribute \src "ls180.v:334.5-334.36" - process $proc$ls180.v:334$2664 - assign { } { } - assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] - end - attribute \src "ls180.v:335.5-335.35" - process $proc$ls180.v:335$2665 - assign { } { } - assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] - end - attribute \src "ls180.v:336.5-336.36" - process $proc$ls180.v:336$2666 - assign { } { } - assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] - end - attribute \src "ls180.v:3368.1-3375.4" - process $proc$ls180.v:3368$171 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3370.2-3374.5" - switch \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:3370.6-3370.48" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3372.6-3372.10" - case - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3373$173_Y - end - sync always - update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0] - end - attribute \src "ls180.v:337.5-337.35" - process $proc$ls180.v:337$2667 - assign { } { } - assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] - end - attribute \src "ls180.v:3379.1-3386.4" - process $proc$ls180.v:3379$180 - assign { } { } - assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3381.2-3385.5" - switch $and$ls180.v:3381$181_Y - attribute \src "ls180.v:3381.6-3381.115" - case 1'1 - attribute \src "ls180.v:3382.3-3384.6" - switch $ne$ls180.v:3382$182_Y - attribute \src "ls180.v:3382.7-3382.143" - case 1'1 - assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3383$183_Y - case - end - case - end - sync always - update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0] - end - attribute \src "ls180.v:34.5-34.51" - process $proc$ls180.v:34$2564 - assign { } { } - assign $1\main_libresocsim_soccontroller_reset_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_soccontroller_reset_re $1\main_libresocsim_soccontroller_reset_re[0:0] - end - attribute \src "ls180.v:3401.1-3408.4" - process $proc$ls180.v:3401$184 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3403.2-3407.5" - switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3403.6-3403.58" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3404$185_Y - attribute \src "ls180.v:3405.6-3405.10" - case - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - end - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:341.5-341.36" - process $proc$ls180.v:341$2668 - assign { } { } - assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 - sync always - update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] - sync init - end - attribute \src "ls180.v:3417.1-3510.4" - process $proc$ls180.v:3417$193 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 - assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state - attribute \src "ls180.v:3433.2-3509.9" - switch \builder_bankmachine2_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3435.4-3443.7" - switch $and$ls180.v:3435$194_Y - attribute \src "ls180.v:3435.8-3435.87" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3437.5-3439.8" - switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3437.9-3437.42" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'101 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3447.4-3449.7" - switch $and$ls180.v:3447$195_Y - attribute \src "ls180.v:3447.8-3447.87" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'101 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3453.4-3462.7" - switch \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:3453.8-3453.44" - case 1'1 - assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 - assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3458.5-3460.8" - switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3458.9-3458.42" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'110 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3465.4-3467.7" - switch \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:3465.8-3465.45" - case 1'1 - assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1 - case - end - attribute \src "ls180.v:3470.4-3472.7" - switch $not$ls180.v:3470$196_Y - attribute \src "ls180.v:3470.8-3470.46" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_bankmachine2_next_state[2:0] 3'011 - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_bankmachine2_next_state[2:0] 3'000 - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3481.4-3507.7" - switch \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:3481.8-3481.43" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'100 - attribute \src "ls180.v:3483.8-3483.12" - case - attribute \src "ls180.v:3484.5-3506.8" - switch \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:3484.9-3484.56" - case 1'1 - attribute \src "ls180.v:3485.6-3505.9" - switch \main_sdram_bankmachine2_row_opened - attribute \src "ls180.v:3485.10-3485.44" - case 1'1 - attribute \src "ls180.v:3486.7-3502.10" - switch \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:3486.11-3486.42" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3488.8-3495.11" - switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:3488.12-3488.64" - case 1'1 - assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready - assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3492.12-3492.16" - case - assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready - assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 - end - attribute \src "ls180.v:3497.8-3499.11" - switch $and$ls180.v:3497$197_Y - attribute \src "ls180.v:3497.12-3497.88" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:3500.11-3500.15" - case - assign $0\builder_bankmachine2_next_state[2:0] 3'001 - end - attribute \src "ls180.v:3503.10-3503.14" - case - assign $0\builder_bankmachine2_next_state[2:0] 3'011 - end - case - end - end - end - sync always - update \main_sdram_bankmachine2_req_wdata_ready $0\main_sdram_bankmachine2_req_wdata_ready[0:0] - update \main_sdram_bankmachine2_req_rdata_valid $0\main_sdram_bankmachine2_req_rdata_valid[0:0] - update \main_sdram_bankmachine2_refresh_gnt $0\main_sdram_bankmachine2_refresh_gnt[0:0] - update \main_sdram_bankmachine2_cmd_valid $0\main_sdram_bankmachine2_cmd_valid[0:0] - update \main_sdram_bankmachine2_cmd_payload_cas $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] - update \main_sdram_bankmachine2_cmd_payload_ras $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] - update \main_sdram_bankmachine2_cmd_payload_we $0\main_sdram_bankmachine2_cmd_payload_we[0:0] - update \main_sdram_bankmachine2_cmd_payload_is_cmd $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - update \main_sdram_bankmachine2_cmd_payload_is_read $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - update \main_sdram_bankmachine2_cmd_payload_is_write $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - update \main_sdram_bankmachine2_row_open $0\main_sdram_bankmachine2_row_open[0:0] - update \main_sdram_bankmachine2_row_close $0\main_sdram_bankmachine2_row_close[0:0] - update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0] - end - attribute \src "ls180.v:346.12-346.45" - process $proc$ls180.v:346$2669 - assign { } { } - assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] - end - attribute \src "ls180.v:347.5-347.43" - process $proc$ls180.v:347$2670 - assign { } { } - assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:35.12-35.74" - process $proc$ls180.v:35$2565 - assign { } { } - assign $1\main_libresocsim_soccontroller_scratch_storage[31:0] 305419896 - sync always - sync init - update \main_libresocsim_soccontroller_scratch_storage $1\main_libresocsim_soccontroller_scratch_storage[31:0] - end - attribute \src "ls180.v:3525.1-3532.4" - process $proc$ls180.v:3525$201 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3527.2-3531.5" - switch \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:3527.6-3527.48" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3529.6-3529.10" - case - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3530$203_Y - end - sync always - update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0] - end - attribute \src "ls180.v:3536.1-3543.4" - process $proc$ls180.v:3536$210 - assign { } { } - assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3538.2-3542.5" - switch $and$ls180.v:3538$211_Y - attribute \src "ls180.v:3538.6-3538.115" - case 1'1 - attribute \src "ls180.v:3539.3-3541.6" - switch $ne$ls180.v:3539$212_Y - attribute \src "ls180.v:3539.7-3539.143" - case 1'1 - assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3540$213_Y - case - end - case - end - sync always - update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0] - end - attribute \src "ls180.v:3558.1-3565.4" - process $proc$ls180.v:3558$214 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3560.2-3564.5" - switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3560.6-3560.58" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3561$215_Y - attribute \src "ls180.v:3562.6-3562.10" - case - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - end - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:3574.1-3667.4" - process $proc$ls180.v:3574$223 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 - assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state - attribute \src "ls180.v:3590.2-3666.9" - switch \builder_bankmachine3_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3592.4-3600.7" - switch $and$ls180.v:3592$224_Y - attribute \src "ls180.v:3592.8-3592.87" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3594.5-3596.8" - switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3594.9-3594.42" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'101 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3604.4-3606.7" - switch $and$ls180.v:3604$225_Y - attribute \src "ls180.v:3604.8-3604.87" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'101 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3610.4-3619.7" - switch \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:3610.8-3610.44" - case 1'1 - assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 - assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3615.5-3617.8" - switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3615.9-3615.42" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'110 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3622.4-3624.7" - switch \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:3622.8-3622.45" - case 1'1 - assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1 - case - end - attribute \src "ls180.v:3627.4-3629.7" - switch $not$ls180.v:3627$226_Y - attribute \src "ls180.v:3627.8-3627.46" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_bankmachine3_next_state[2:0] 3'011 - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_bankmachine3_next_state[2:0] 3'000 - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3638.4-3664.7" - switch \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:3638.8-3638.43" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'100 - attribute \src "ls180.v:3640.8-3640.12" - case - attribute \src "ls180.v:3641.5-3663.8" - switch \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:3641.9-3641.56" - case 1'1 - attribute \src "ls180.v:3642.6-3662.9" - switch \main_sdram_bankmachine3_row_opened - attribute \src "ls180.v:3642.10-3642.44" - case 1'1 - attribute \src "ls180.v:3643.7-3659.10" - switch \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:3643.11-3643.42" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3645.8-3652.11" - switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:3645.12-3645.64" - case 1'1 - assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready - assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3649.12-3649.16" - case - assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready - assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 - end - attribute \src "ls180.v:3654.8-3656.11" - switch $and$ls180.v:3654$227_Y - attribute \src "ls180.v:3654.12-3654.88" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:3657.11-3657.15" - case - assign $0\builder_bankmachine3_next_state[2:0] 3'001 - end - attribute \src "ls180.v:3660.10-3660.14" - case - assign $0\builder_bankmachine3_next_state[2:0] 3'011 - end - case - end - end - end - sync always - update \main_sdram_bankmachine3_req_wdata_ready $0\main_sdram_bankmachine3_req_wdata_ready[0:0] - update \main_sdram_bankmachine3_req_rdata_valid $0\main_sdram_bankmachine3_req_rdata_valid[0:0] - update \main_sdram_bankmachine3_refresh_gnt $0\main_sdram_bankmachine3_refresh_gnt[0:0] - update \main_sdram_bankmachine3_cmd_valid $0\main_sdram_bankmachine3_cmd_valid[0:0] - update \main_sdram_bankmachine3_cmd_payload_cas $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] - update \main_sdram_bankmachine3_cmd_payload_ras $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] - update \main_sdram_bankmachine3_cmd_payload_we $0\main_sdram_bankmachine3_cmd_payload_we[0:0] - update \main_sdram_bankmachine3_cmd_payload_is_cmd $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - update \main_sdram_bankmachine3_cmd_payload_is_read $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - update \main_sdram_bankmachine3_cmd_payload_is_write $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - update \main_sdram_bankmachine3_row_open $0\main_sdram_bankmachine3_row_open[0:0] - update \main_sdram_bankmachine3_row_close $0\main_sdram_bankmachine3_row_close[0:0] - update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0] - end - attribute \src "ls180.v:36.5-36.53" - process $proc$ls180.v:36$2566 - assign { } { } - assign $1\main_libresocsim_soccontroller_scratch_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_soccontroller_scratch_re $1\main_libresocsim_soccontroller_scratch_re[0:0] - end - attribute \src "ls180.v:362.12-362.46" - process $proc$ls180.v:362$2671 - assign { } { } - assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] - end - attribute \src "ls180.v:363.5-363.44" - process $proc$ls180.v:363$2672 - assign { } { } - assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:364.12-364.48" - process $proc$ls180.v:364$2673 - assign { } { } - assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] - end - attribute \src "ls180.v:365.11-365.43" - process $proc$ls180.v:365$2674 - assign { } { } - assign $1\main_sdram_master_p0_bank[1:0] 2'00 - sync always - sync init - update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] - end - attribute \src "ls180.v:366.5-366.38" - process $proc$ls180.v:366$2675 - assign { } { } - assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] - end - attribute \src "ls180.v:367.5-367.37" - process $proc$ls180.v:367$2676 - assign { } { } - assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] - end - attribute \src "ls180.v:368.5-368.38" - process $proc$ls180.v:368$2677 - assign { } { } - assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] - end - attribute \src "ls180.v:3687.1-3693.4" - process $proc$ls180.v:3687$266 - assign { } { } - assign { } { } - assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3689$279_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3690$292_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3691$305_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3692$318_Y - sync always - update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] - end - attribute \src "ls180.v:369.5-369.37" - process $proc$ls180.v:369$2678 - assign { } { } - assign $1\main_sdram_master_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] - end - attribute \src "ls180.v:370.5-370.36" - process $proc$ls180.v:370$2679 - assign { } { } - assign $1\main_sdram_master_p0_cke[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] - end - attribute \src "ls180.v:3701.1-3706.4" - process $proc$ls180.v:3701$319 - assign { } { } - assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:3703.2-3705.5" - switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3703.6-3703.37" - case 1'1 - assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0 - case - end - sync always - update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:3707.1-3712.4" - process $proc$ls180.v:3707$320 - assign { } { } - assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:3709.2-3711.5" - switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3709.6-3709.37" - case 1'1 - assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1 - case - end - sync always - update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:371.5-371.36" - process $proc$ls180.v:371$2680 - assign { } { } - assign $1\main_sdram_master_p0_odt[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] - end - attribute \src "ls180.v:3713.1-3718.4" - process $proc$ls180.v:3713$321 - assign { } { } - assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:3715.2-3717.5" - switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3715.6-3715.37" - case 1'1 - assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2 - case - end - sync always - update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0] - end - attribute \src "ls180.v:372.5-372.40" - process $proc$ls180.v:372$2681 - assign { } { } - assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] - end - attribute \src "ls180.v:3720.1-3726.4" - process $proc$ls180.v:3720$324 - assign { } { } - assign { } { } - assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3722$337_Y - assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3723$350_Y - assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3724$363_Y - assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3725$376_Y - sync always - update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] - end - attribute \src "ls180.v:373.5-373.38" - process $proc$ls180.v:373$2682 - assign { } { } - assign $1\main_sdram_master_p0_act_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] - end - attribute \src "ls180.v:3734.1-3739.4" - process $proc$ls180.v:3734$377 - assign { } { } - assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:3736.2-3738.5" - switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3736.6-3736.37" - case 1'1 - assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3 - case - end - sync always - update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:374.12-374.47" - process $proc$ls180.v:374$2683 - assign { } { } - assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] - end - attribute \src "ls180.v:3740.1-3745.4" - process $proc$ls180.v:3740$378 - assign { } { } - assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:3742.2-3744.5" - switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3742.6-3742.37" - case 1'1 - assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4 - case - end - sync always - update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:3746.1-3751.4" - process $proc$ls180.v:3746$379 - assign { } { } - assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:3748.2-3750.5" - switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3748.6-3748.37" - case 1'1 - assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5 - case - end - sync always - update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0] - end - attribute \src "ls180.v:375.5-375.42" - process $proc$ls180.v:375$2684 - assign { } { } - assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] - end - attribute \src "ls180.v:3752.1-3760.4" - process $proc$ls180.v:3752$380 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3754.2-3756.5" - switch $and$ls180.v:3754$383_Y - attribute \src "ls180.v:3754.6-3754.115" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:3757.2-3759.5" - switch $and$ls180.v:3757$386_Y - attribute \src "ls180.v:3757.6-3757.115" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 - case - end - sync always - update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0] - end - attribute \src "ls180.v:376.11-376.50" - process $proc$ls180.v:376$2685 - assign { } { } - assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 - sync always - sync init - update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] - end - attribute \src "ls180.v:3761.1-3769.4" - process $proc$ls180.v:3761$387 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3763.2-3765.5" - switch $and$ls180.v:3763$390_Y - attribute \src "ls180.v:3763.6-3763.115" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:3766.2-3768.5" - switch $and$ls180.v:3766$393_Y - attribute \src "ls180.v:3766.6-3766.115" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 - case - end - sync always - update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0] - end - attribute \src "ls180.v:377.5-377.42" - process $proc$ls180.v:377$2686 - assign { } { } - assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] - end - attribute \src "ls180.v:3770.1-3778.4" - process $proc$ls180.v:3770$394 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3772.2-3774.5" - switch $and$ls180.v:3772$397_Y - attribute \src "ls180.v:3772.6-3772.115" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:3775.2-3777.5" - switch $and$ls180.v:3775$400_Y - attribute \src "ls180.v:3775.6-3775.115" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 - case - end - sync always - update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0] - end - attribute \src "ls180.v:3779.1-3787.4" - process $proc$ls180.v:3779$401 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3781.2-3783.5" - switch $and$ls180.v:3781$404_Y - attribute \src "ls180.v:3781.6-3781.115" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:3784.2-3786.5" - switch $and$ls180.v:3784$407_Y - attribute \src "ls180.v:3784.6-3784.115" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 - case - end - sync always - update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0] - end - attribute \src "ls180.v:3792.1-3864.4" - process $proc$ls180.v:3792$410 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_en1[0:0] 1'0 - assign $0\main_sdram_choose_req_want_reads[0:0] 1'0 - assign $0\main_sdram_choose_req_want_writes[0:0] 1'0 - assign $0\main_sdram_cmd_ready[0:0] 1'0 - assign { } { } - assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 - assign $0\main_sdram_steerer_sel[1:0] 2'00 - assign $0\main_sdram_en0[0:0] 1'0 - assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed - assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state - attribute \src "ls180.v:3804.2-3863.9" - switch \builder_multiplexer_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_en1[0:0] 1'1 - assign $0\main_sdram_choose_req_want_writes[0:0] 1'1 - assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:3808.4-3814.7" - switch 1'1 - attribute \src "ls180.v:3808.8-3808.12" - case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3809$417_Y - case - end - attribute \src "ls180.v:3816.4-3820.7" - switch \main_sdram_read_available - attribute \src "ls180.v:3816.8-3816.33" - case 1'1 - attribute \src "ls180.v:3817.5-3819.8" - switch $or$ls180.v:3817$419_Y - attribute \src "ls180.v:3817.9-3817.63" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'011 - case - end - case - end - attribute \src "ls180.v:3821.4-3823.7" - switch \main_sdram_go_to_refresh - attribute \src "ls180.v:3821.8-3821.32" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_steerer_sel[1:0] 2'11 - assign $0\main_sdram_cmd_ready[0:0] 1'1 - attribute \src "ls180.v:3828.4-3830.7" - switch \main_sdram_cmd_last - attribute \src "ls180.v:3828.8-3828.27" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3833.4-3835.7" - switch \main_sdram_twtrcon_ready - attribute \src "ls180.v:3833.8-3833.32" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_multiplexer_next_state[2:0] 3'101 - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_multiplexer_next_state[2:0] 3'001 - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdram_en0[0:0] 1'1 - assign $0\main_sdram_choose_req_want_reads[0:0] 1'1 - assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:3846.4-3852.7" - switch 1'1 - attribute \src "ls180.v:3846.8-3846.12" - case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3847$426_Y - case - end - attribute \src "ls180.v:3854.4-3858.7" - switch \main_sdram_write_available - attribute \src "ls180.v:3854.8-3854.34" - case 1'1 - attribute \src "ls180.v:3855.5-3857.8" - switch $or$ls180.v:3855$428_Y - attribute \src "ls180.v:3855.9-3855.62" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'100 - case - end - case - end - attribute \src "ls180.v:3859.4-3861.7" - switch \main_sdram_go_to_refresh - attribute \src "ls180.v:3859.8-3859.32" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'010 - case - end - end - sync always - update \main_sdram_cmd_ready $0\main_sdram_cmd_ready[0:0] - update \main_sdram_choose_req_want_reads $0\main_sdram_choose_req_want_reads[0:0] - update \main_sdram_choose_req_want_writes $0\main_sdram_choose_req_want_writes[0:0] - update \main_sdram_choose_req_want_activates $0\main_sdram_choose_req_want_activates[0:0] - update \main_sdram_choose_req_cmd_ready $0\main_sdram_choose_req_cmd_ready[0:0] - update \main_sdram_steerer_sel $0\main_sdram_steerer_sel[1:0] - update \main_sdram_en0 $0\main_sdram_en0[0:0] - update \main_sdram_en1 $0\main_sdram_en1[0:0] - update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0] - end - attribute \src "ls180.v:384.11-384.36" - process $proc$ls180.v:384$2687 - assign { } { } - assign $1\main_sdram_storage[3:0] 4'0001 - sync always - sync init - update \main_sdram_storage $1\main_sdram_storage[3:0] - end - attribute \src "ls180.v:385.5-385.25" - process $proc$ls180.v:385$2688 - assign { } { } - assign $1\main_sdram_re[0:0] 1'0 - sync always - sync init - update \main_sdram_re $1\main_sdram_re[0:0] - end - attribute \src "ls180.v:386.11-386.44" - process $proc$ls180.v:386$2689 - assign { } { } - assign $1\main_sdram_command_storage[5:0] 6'000000 - sync always - sync init - update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] - end - attribute \src "ls180.v:387.5-387.33" - process $proc$ls180.v:387$2690 - assign { } { } - assign $1\main_sdram_command_re[0:0] 1'0 - sync always - sync init - update \main_sdram_command_re $1\main_sdram_command_re[0:0] - end - attribute \src "ls180.v:3888.1-3901.4" - process $proc$ls180.v:3888$557 - assign { } { } - assign { } { } - assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 - assign $0\main_sdram_interface_wdata_we[1:0] 2'00 - attribute \src "ls180.v:3891.2-3900.9" - switch \builder_new_master_wdata_ready - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdram_interface_wdata[15:0] \main_port_wdata_payload_data - assign $0\main_sdram_interface_wdata_we[1:0] \main_port_wdata_payload_we - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 - assign $0\main_sdram_interface_wdata_we[1:0] 2'00 - end - sync always - update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0] - update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0] - end - attribute \src "ls180.v:3908.1-3918.4" - process $proc$ls180.v:3908$559 - assign { } { } - assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000 - attribute \src "ls180.v:3910.2-3917.9" - switch \main_converter_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [15:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [31:16] - case - end - sync always - update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0] - end - attribute \src "ls180.v:391.5-391.38" - process $proc$ls180.v:391$2691 - assign { } { } - assign $0\main_sdram_command_issue_w[0:0] 1'0 - sync always - update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] - sync init - end - attribute \src "ls180.v:392.12-392.46" - process $proc$ls180.v:392$2692 - assign { } { } - assign $1\main_sdram_address_storage[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] - end - attribute \src "ls180.v:3920.1-3966.4" - process $proc$ls180.v:3920$560 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_litedram_wb_sel[1:0] 2'00 - assign { } { } - assign $0\main_litedram_wb_cyc[0:0] 1'0 - assign $0\main_converter_counter_converter_next_value[0:0] 1'0 - assign $0\main_litedram_wb_stb[0:0] 1'0 - assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0 - assign $0\main_wb_sdram_ack[0:0] 1'0 - assign $0\main_litedram_wb_we[0:0] 1'0 - assign $0\main_converter_skip[0:0] 1'0 - assign $0\builder_converter_next_state[0:0] \builder_converter_state - attribute \src "ls180.v:3932.2-3965.9" - switch \builder_converter_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter } - attribute \src "ls180.v:3935.4-3942.11" - switch \main_converter_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [1:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2] - case - end - attribute \src "ls180.v:3943.4-3956.7" - switch $and$ls180.v:3943$561_Y - attribute \src "ls180.v:3943.8-3943.47" - case 1'1 - assign $0\main_converter_skip[0:0] $eq$ls180.v:3944$562_Y - assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we - assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:3946$563_Y - assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:3947$564_Y - attribute \src "ls180.v:3948.5-3955.8" - switch $or$ls180.v:3948$565_Y - attribute \src "ls180.v:3948.9-3948.53" - case 1'1 - assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:3949$566_Y - assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:3951.6-3954.9" - switch $eq$ls180.v:3951$567_Y - attribute \src "ls180.v:3951.10-3951.42" - case 1'1 - assign $0\main_wb_sdram_ack[0:0] 1'1 - assign $0\builder_converter_next_state[0:0] 1'0 - case - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_converter_counter_converter_next_value[0:0] 1'0 - assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:3961.4-3963.7" - switch $and$ls180.v:3961$568_Y - attribute \src "ls180.v:3961.8-3961.47" - case 1'1 - assign $0\builder_converter_next_state[0:0] 1'1 - case - end - end - sync always - update \main_wb_sdram_ack $0\main_wb_sdram_ack[0:0] - update \main_litedram_wb_adr $0\main_litedram_wb_adr[29:0] - update \main_litedram_wb_sel $0\main_litedram_wb_sel[1:0] - update \main_litedram_wb_cyc $0\main_litedram_wb_cyc[0:0] - update \main_litedram_wb_stb $0\main_litedram_wb_stb[0:0] - update \main_litedram_wb_we $0\main_litedram_wb_we[0:0] - update \main_converter_skip $0\main_converter_skip[0:0] - update \builder_converter_next_state $0\builder_converter_next_state[0:0] - update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0] - update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0] - end - attribute \src "ls180.v:393.5-393.33" - process $proc$ls180.v:393$2693 - assign { } { } - assign $1\main_sdram_address_re[0:0] 1'0 - sync always - sync init - update \main_sdram_address_re $1\main_sdram_address_re[0:0] - end - attribute \src "ls180.v:394.11-394.45" - process $proc$ls180.v:394$2694 - assign { } { } - assign $1\main_sdram_baddress_storage[1:0] 2'00 - sync always - sync init - update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] - end - attribute \src "ls180.v:395.5-395.34" - process $proc$ls180.v:395$2695 - assign { } { } - assign $1\main_sdram_baddress_re[0:0] 1'0 - sync always - sync init - update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] - end - attribute \src "ls180.v:396.12-396.45" - process $proc$ls180.v:396$2696 - assign { } { } - assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] - end - attribute \src "ls180.v:397.5-397.32" - process $proc$ls180.v:397$2697 - assign { } { } - assign $1\main_sdram_wrdata_re[0:0] 1'0 - sync always - sync init - update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] - end - attribute \src "ls180.v:398.12-398.37" - process $proc$ls180.v:398$2698 - assign { } { } - assign $1\main_sdram_status[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_status $1\main_sdram_status[15:0] - end - attribute \src "ls180.v:3990.1-4038.4" - process $proc$ls180.v:3990$596 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_irq[0:0] 1'0 - assign { } { } - assign $0\main_count_spimaster0_next_value[2:0] 3'000 - assign $0\main_miso_latch[0:0] 1'0 - assign $0\main_count_spimaster0_next_value_ce[0:0] 1'0 - assign $0\main_clk_enable[0:0] 1'0 - assign $0\main_cs_enable[0:0] 1'0 - assign $0\main_mosi_latch[0:0] 1'0 - assign $0\main_done0[0:0] 1'0 - assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state - attribute \src "ls180.v:4001.2-4037.9" - switch \builder_spimaster0_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_count_spimaster0_next_value[2:0] 3'000 - assign $0\main_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4005.4-4008.7" - switch \main_clk_fall - attribute \src "ls180.v:4005.8-4005.21" - case 1'1 - assign $0\main_cs_enable[0:0] 1'1 - assign $0\builder_spimaster0_next_state[1:0] 2'10 - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_clk_enable[0:0] 1'1 - assign $0\main_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4013.4-4019.7" - switch \main_clk_fall - attribute \src "ls180.v:4013.8-4013.21" - case 1'1 - assign $0\main_count_spimaster0_next_value[2:0] $add$ls180.v:4014$597_Y - assign $0\main_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4016.5-4018.8" - switch $eq$ls180.v:4016$599_Y - attribute \src "ls180.v:4016.9-4016.46" - case 1'1 - assign $0\builder_spimaster0_next_state[1:0] 2'11 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\main_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4023.4-4027.7" - switch \main_clk_rise - attribute \src "ls180.v:4023.8-4023.21" - case 1'1 - assign $0\main_miso_latch[0:0] 1'1 - assign $0\main_irq[0:0] 1'1 - assign $0\builder_spimaster0_next_state[1:0] 2'00 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_done0[0:0] 1'1 - attribute \src "ls180.v:4031.4-4035.7" - switch \main_start0 - attribute \src "ls180.v:4031.8-4031.19" - case 1'1 - assign $0\main_done0[0:0] 1'0 - assign $0\main_mosi_latch[0:0] 1'1 - assign $0\builder_spimaster0_next_state[1:0] 2'01 - case - end - end - sync always - update \main_done0 $0\main_done0[0:0] - update \main_irq $0\main_irq[0:0] - update \main_clk_enable $0\main_clk_enable[0:0] - update \main_cs_enable $0\main_cs_enable[0:0] - update \main_mosi_latch $0\main_mosi_latch[0:0] - update \main_miso_latch $0\main_miso_latch[0:0] - update \builder_spimaster0_next_state $0\builder_spimaster0_next_state[1:0] - update \main_count_spimaster0_next_value $0\main_count_spimaster0_next_value[2:0] - update \main_count_spimaster0_next_value_ce $0\main_count_spimaster0_next_value_ce[0:0] - end - attribute \src "ls180.v:4066.1-4094.4" - process $proc$ls180.v:4066$621 - assign { } { } - assign $0\libresocsim_clocker_clk1[0:0] 1'0 - attribute \src "ls180.v:4068.2-4093.9" - switch \libresocsim_clocker_storage - attribute \src "ls180.v:0.0-0.0" - case 9'000000100 - assign $0\libresocsim_clocker_clk1[0:0] \libresocsim_clocker_clks [1] - attribute \src "ls180.v:0.0-0.0" - case 9'000001000 - assign $0\libresocsim_clocker_clk1[0:0] \libresocsim_clocker_clks [2] - attribute \src "ls180.v:0.0-0.0" - case 9'000010000 - assign $0\libresocsim_clocker_clk1[0:0] \libresocsim_clocker_clks [3] - attribute \src "ls180.v:0.0-0.0" - case 9'000100000 - assign $0\libresocsim_clocker_clk1[0:0] \libresocsim_clocker_clks [4] - attribute \src "ls180.v:0.0-0.0" - case 9'001000000 - assign $0\libresocsim_clocker_clk1[0:0] \libresocsim_clocker_clks [5] - attribute \src "ls180.v:0.0-0.0" - case 9'010000000 - assign $0\libresocsim_clocker_clk1[0:0] \libresocsim_clocker_clks [6] - attribute \src "ls180.v:0.0-0.0" - case 9'100000000 - assign $0\libresocsim_clocker_clk1[0:0] \libresocsim_clocker_clks [7] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\libresocsim_clocker_clk1[0:0] \libresocsim_clocker_clks [0] - end - sync always - update \libresocsim_clocker_clk1 $0\libresocsim_clocker_clk1[0:0] - end - attribute \src "ls180.v:4096.1-4129.4" - process $proc$ls180.v:4096$624 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\libresocsim_init_pads_out_payload_data_o[3:0] 4'0000 - assign $0\libresocsim_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 - assign $0\libresocsim_init_pads_out_payload_data_oe[0:0] 1'0 - assign $0\libresocsim_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 - assign $0\libresocsim_init_pads_out_payload_clk[0:0] 1'0 - assign $0\libresocsim_init_pads_out_payload_cmd_o[0:0] 1'0 - assign $0\libresocsim_init_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:4106.2-4128.9" - switch \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\libresocsim_init_pads_out_payload_clk[0:0] 1'1 - assign $0\libresocsim_init_pads_out_payload_cmd_oe[0:0] 1'1 - assign $0\libresocsim_init_pads_out_payload_cmd_o[0:0] 1'1 - assign $0\libresocsim_init_pads_out_payload_data_oe[0:0] 1'1 - assign $0\libresocsim_init_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4113.4-4119.7" - switch \libresocsim_init_pads_out_ready - attribute \src "ls180.v:4113.8-4113.39" - case 1'1 - assign $0\libresocsim_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4114$625_Y - assign $0\libresocsim_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4116.5-4118.8" - switch $eq$ls180.v:4116$626_Y - attribute \src "ls180.v:4116.9-4116.42" - case 1'1 - assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\libresocsim_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 - assign $0\libresocsim_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4124.4-4126.7" - switch \libresocsim_init_initialize_re - attribute \src "ls180.v:4124.8-4124.38" - case 1'1 - assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1 - case - end - end - sync always - update \libresocsim_init_pads_out_payload_clk $0\libresocsim_init_pads_out_payload_clk[0:0] - update \libresocsim_init_pads_out_payload_cmd_o $0\libresocsim_init_pads_out_payload_cmd_o[0:0] - update \libresocsim_init_pads_out_payload_cmd_oe $0\libresocsim_init_pads_out_payload_cmd_oe[0:0] - update \libresocsim_init_pads_out_payload_data_o $0\libresocsim_init_pads_out_payload_data_o[3:0] - update \libresocsim_init_pads_out_payload_data_oe $0\libresocsim_init_pads_out_payload_data_oe[0:0] - update \builder_sdphy_sdphyinit_next_state $0\builder_sdphy_sdphyinit_next_state[0:0] - update \libresocsim_init_count_sdphy_sdphyinit_next_value $0\libresocsim_init_count_sdphy_sdphyinit_next_value[7:0] - update \libresocsim_init_count_sdphy_sdphyinit_next_value_ce $0\libresocsim_init_count_sdphy_sdphyinit_next_value_ce[0:0] - end - attribute \src "ls180.v:41.12-41.61" - process $proc$ls180.v:41$2567 - assign { } { } - assign $1\main_libresocsim_soccontroller_bus_errors[31:0] 0 - sync always - sync init - update \main_libresocsim_soccontroller_bus_errors $1\main_libresocsim_soccontroller_bus_errors[31:0] - end - attribute \src "ls180.v:4130.1-4206.4" - process $proc$ls180.v:4130$627 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\libresocsim_cmdw_done[0:0] 1'0 - assign $0\libresocsim_cmdw_pads_out_payload_clk[0:0] 1'0 - assign $0\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] 1'0 - assign { } { } - assign $0\libresocsim_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 - assign $0\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 - assign $0\libresocsim_cmdw_sink_ready[0:0] 1'0 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:4140.2-4205.9" - switch \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\libresocsim_cmdw_pads_out_payload_clk[0:0] 1'1 - assign $0\libresocsim_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 - attribute \src "ls180.v:4144.4-4169.11" - switch \libresocsim_cmdw_count - attribute \src "ls180.v:0.0-0.0" - case 8'00000000 - assign $0\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] \libresocsim_cmdw_sink_payload_data [7] - attribute \src "ls180.v:0.0-0.0" - case 8'00000001 - assign $0\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] \libresocsim_cmdw_sink_payload_data [6] - attribute \src "ls180.v:0.0-0.0" - case 8'00000010 - assign $0\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] \libresocsim_cmdw_sink_payload_data [5] - attribute \src "ls180.v:0.0-0.0" - case 8'00000011 - assign $0\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] \libresocsim_cmdw_sink_payload_data [4] - attribute \src "ls180.v:0.0-0.0" - case 8'00000100 - assign $0\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] \libresocsim_cmdw_sink_payload_data [3] - attribute \src "ls180.v:0.0-0.0" - case 8'00000101 - assign $0\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] \libresocsim_cmdw_sink_payload_data [2] - attribute \src "ls180.v:0.0-0.0" - case 8'00000110 - assign $0\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] \libresocsim_cmdw_sink_payload_data [1] - attribute \src "ls180.v:0.0-0.0" - case 8'00000111 - assign $0\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] \libresocsim_cmdw_sink_payload_data [0] - case - end - attribute \src "ls180.v:4170.4-4181.7" - switch \libresocsim_cmdw_pads_out_ready - attribute \src "ls180.v:4170.8-4170.39" - case 1'1 - assign $0\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4171$628_Y - assign $0\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4173.5-4180.8" - switch $eq$ls180.v:4173$629_Y - attribute \src "ls180.v:4173.9-4173.41" - case 1'1 - attribute \src "ls180.v:4174.6-4179.9" - switch \libresocsim_cmdw_sink_last - attribute \src "ls180.v:4174.10-4174.36" - case 1'1 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10 - attribute \src "ls180.v:4176.10-4176.14" - case - assign $0\libresocsim_cmdw_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\libresocsim_cmdw_pads_out_payload_clk[0:0] 1'1 - assign $0\libresocsim_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 - assign $0\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4187.4-4194.7" - switch \libresocsim_cmdw_pads_out_ready - attribute \src "ls180.v:4187.8-4187.39" - case 1'1 - assign $0\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4188$630_Y - assign $0\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4190.5-4193.8" - switch $eq$ls180.v:4190$631_Y - attribute \src "ls180.v:4190.9-4190.41" - case 1'1 - assign $0\libresocsim_cmdw_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 - assign $0\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4199.4-4203.7" - switch $and$ls180.v:4199$632_Y - attribute \src "ls180.v:4199.8-4199.71" - case 1'1 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01 - attribute \src "ls180.v:4201.8-4201.12" - case - assign $0\libresocsim_cmdw_done[0:0] 1'1 - end - end - sync always - update \libresocsim_cmdw_pads_out_payload_clk $0\libresocsim_cmdw_pads_out_payload_clk[0:0] - update \libresocsim_cmdw_pads_out_payload_cmd_o $0\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] - update \libresocsim_cmdw_pads_out_payload_cmd_oe $0\libresocsim_cmdw_pads_out_payload_cmd_oe[0:0] - update \libresocsim_cmdw_sink_ready $0\libresocsim_cmdw_sink_ready[0:0] - update \libresocsim_cmdw_done $0\libresocsim_cmdw_done[0:0] - update \builder_sdphy_sdphycmdw_next_state $0\builder_sdphy_sdphycmdw_next_state[1:0] - update \libresocsim_cmdw_count_sdphy_sdphycmdw_next_value $0\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - update \libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - end - attribute \src "ls180.v:4240.1-4333.4" - process $proc$ls180.v:4240$641 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\libresocsim_cmdr_source_valid[0:0] 1'0 - assign $0\libresocsim_cmdr_source_last[0:0] 1'0 - assign $0\libresocsim_cmdr_source_payload_data[7:0] 8'00000000 - assign $0\libresocsim_cmdr_source_payload_status[2:0] 3'000 - assign { } { } - assign $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - assign $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 - assign $0\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 - assign $0\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 - assign $0\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 - assign $0\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 - assign $0\libresocsim_cmdr_pads_out_payload_clk[0:0] 1'0 - assign $0\libresocsim_cmdr_cmdr_source_source_ready0[0:0] 1'0 - assign $0\libresocsim_cmdr_pads_out_payload_cmd_o[0:0] 1'0 - assign $0\libresocsim_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\libresocsim_cmdr_sink_ready[0:0] 1'0 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:4258.2-4332.9" - switch \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\libresocsim_cmdr_pads_out_payload_clk[0:0] 1'1 - assign $0\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 - assign $0\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 - assign $0\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4266$642_Y - assign $0\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4263.4-4265.7" - switch \libresocsim_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:4263.8-4263.50" - case 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:4268.4-4271.7" - switch $eq$ls180.v:4268$643_Y - attribute \src "ls180.v:4268.8-4268.42" - case 1'1 - assign $0\libresocsim_cmdr_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\libresocsim_cmdr_pads_out_payload_clk[0:0] 1'1 - assign $0\libresocsim_cmdr_source_valid[0:0] \libresocsim_cmdr_cmdr_source_source_valid0 - assign $0\libresocsim_cmdr_source_payload_status[2:0] 3'000 - assign $0\libresocsim_cmdr_source_last[0:0] $eq$ls180.v:4277$645_Y - assign $0\libresocsim_cmdr_source_payload_data[7:0] \libresocsim_cmdr_cmdr_source_source_payload_data0 - assign $0\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4294$648_Y - assign $0\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4279.4-4293.7" - switch $and$ls180.v:4279$646_Y - attribute \src "ls180.v:4279.8-4279.71" - case 1'1 - assign $0\libresocsim_cmdr_cmdr_source_source_ready0[0:0] 1'1 - assign $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4281$647_Y - assign $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4283.5-4292.8" - switch \libresocsim_cmdr_source_last - attribute \src "ls180.v:4283.9-4283.37" - case 1'1 - assign $0\libresocsim_cmdr_sink_ready[0:0] 1'1 - attribute \src "ls180.v:4285.6-4291.9" - switch \libresocsim_cmdr_sink_last - attribute \src "ls180.v:4285.10-4285.36" - case 1'1 - assign $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - assign $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011 - attribute \src "ls180.v:4289.10-4289.14" - case - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 - end - case - end - case - end - attribute \src "ls180.v:4296.4-4299.7" - switch $eq$ls180.v:4296$649_Y - attribute \src "ls180.v:4296.8-4296.42" - case 1'1 - assign $0\libresocsim_cmdr_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\libresocsim_cmdr_pads_out_payload_clk[0:0] 1'1 - assign $0\libresocsim_cmdr_pads_out_payload_cmd_oe[0:0] 1'1 - assign $0\libresocsim_cmdr_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4305.4-4311.7" - switch \libresocsim_cmdr_pads_out_ready - attribute \src "ls180.v:4305.8-4305.39" - case 1'1 - assign $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4306$650_Y - assign $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4308.5-4310.8" - switch $eq$ls180.v:4308$651_Y - attribute \src "ls180.v:4308.9-4308.41" - case 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\libresocsim_cmdr_source_valid[0:0] 1'1 - assign $0\libresocsim_cmdr_source_payload_status[2:0] 3'001 - assign $0\libresocsim_cmdr_source_last[0:0] 1'1 - attribute \src "ls180.v:4317.4-4319.7" - switch $and$ls180.v:4317$652_Y - attribute \src "ls180.v:4317.8-4317.71" - case 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - assign $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - assign $0\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000 - assign $0\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4326.4-4330.7" - switch $and$ls180.v:4326$654_Y - attribute \src "ls180.v:4326.8-4326.97" - case 1'1 - assign $0\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1 - assign $0\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'001 - case - end - end - sync always - update \libresocsim_cmdr_pads_out_payload_clk $0\libresocsim_cmdr_pads_out_payload_clk[0:0] - update \libresocsim_cmdr_pads_out_payload_cmd_o $0\libresocsim_cmdr_pads_out_payload_cmd_o[0:0] - update \libresocsim_cmdr_pads_out_payload_cmd_oe $0\libresocsim_cmdr_pads_out_payload_cmd_oe[0:0] - update \libresocsim_cmdr_sink_ready $0\libresocsim_cmdr_sink_ready[0:0] - update \libresocsim_cmdr_source_valid $0\libresocsim_cmdr_source_valid[0:0] - update \libresocsim_cmdr_source_last $0\libresocsim_cmdr_source_last[0:0] - update \libresocsim_cmdr_source_payload_data $0\libresocsim_cmdr_source_payload_data[7:0] - update \libresocsim_cmdr_source_payload_status $0\libresocsim_cmdr_source_payload_status[2:0] - update \libresocsim_cmdr_cmdr_source_source_ready0 $0\libresocsim_cmdr_cmdr_source_source_ready0[0:0] - update \builder_sdphy_sdphycmdr_next_state $0\builder_sdphy_sdphycmdr_next_state[2:0] - update \libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0 $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - update \libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - update \libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1 $0\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - update \libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $0\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - update \libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - update \libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - end - attribute \src "ls180.v:428.12-428.46" - process $proc$ls180.v:428$2699 - assign { } { } - assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] - end - attribute \src "ls180.v:429.11-429.47" - process $proc$ls180.v:429$2700 - assign { } { } - assign $1\main_sdram_interface_wdata_we[1:0] 2'00 - sync always - sync init - update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] - end - attribute \src "ls180.v:43.12-43.55" - process $proc$ls180.v:43$2568 - assign { } { } - assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 - sync always - sync init - update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] - end - attribute \src "ls180.v:431.12-431.45" - process $proc$ls180.v:431$2701 - assign { } { } - assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] - end - attribute \src "ls180.v:432.11-432.40" - process $proc$ls180.v:432$2702 - assign { } { } - assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 - sync always - sync init - update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] - end - attribute \src "ls180.v:433.5-433.35" - process $proc$ls180.v:433$2703 - assign { } { } - assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] - end - attribute \src "ls180.v:434.5-434.34" - process $proc$ls180.v:434$2704 - assign { } { } - assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] - end - attribute \src "ls180.v:435.5-435.35" - process $proc$ls180.v:435$2705 - assign { } { } - assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] - end - attribute \src "ls180.v:436.5-436.34" - process $proc$ls180.v:436$2706 - assign { } { } - assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] - end - attribute \src "ls180.v:4367.1-4394.4" - process $proc$ls180.v:4367$662 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\libresocsim_dataw_valid[0:0] 1'0 - assign $0\libresocsim_dataw_error[0:0] 1'0 - assign $0\libresocsim_dataw_crcr_source_source_ready0[0:0] 1'0 - assign { } { } - assign $0\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 - assign $0\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 - assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:4375.2-4393.9" - switch \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 - assign $0\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 - assign $0\libresocsim_dataw_crcr_source_source_ready0[0:0] 1'1 - attribute \src "ls180.v:4380.4-4384.7" - switch \libresocsim_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:4380.8-4380.51" - case 1'1 - assign $0\libresocsim_dataw_valid[0:0] $ne$ls180.v:4381$663_Y - assign $0\libresocsim_dataw_error[0:0] $eq$ls180.v:4382$664_Y - assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 - case - end - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:4387.4-4391.7" - switch \libresocsim_dataw_start - attribute \src "ls180.v:4387.8-4387.31" - case 1'1 - assign $0\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1 - assign $0\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 - assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'1 - case - end - end - sync always - update \libresocsim_dataw_valid $0\libresocsim_dataw_valid[0:0] - update \libresocsim_dataw_error $0\libresocsim_dataw_error[0:0] - update \libresocsim_dataw_crcr_source_source_ready0 $0\libresocsim_dataw_crcr_source_source_ready0[0:0] - update \builder_sdphy_sdphycrcr_next_state $0\builder_sdphy_sdphycrcr_next_state[0:0] - update \libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - update \libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - end - attribute \src "ls180.v:4395.1-4467.4" - process $proc$ls180.v:4395$665 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\libresocsim_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 - assign $0\libresocsim_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 - assign $0\libresocsim_dataw_pads_out_payload_data_o[3:0] 4'0000 - assign $0\libresocsim_dataw_pads_out_payload_data_oe[0:0] 1'0 - assign $0\libresocsim_dataw_sink_ready[0:0] 1'0 - assign $0\libresocsim_dataw_start[0:0] 1'0 - assign $0\libresocsim_dataw_stop[0:0] 1'0 - assign $0\libresocsim_dataw_pads_out_payload_clk[0:0] 1'0 - assign { } { } - assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state - attribute \src "ls180.v:4406.2-4466.9" - switch \builder_sdphy_fsm_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\libresocsim_dataw_pads_out_payload_clk[0:0] 1'1 - assign $0\libresocsim_dataw_pads_out_payload_data_oe[0:0] 1'1 - assign $0\libresocsim_dataw_pads_out_payload_data_o[3:0] 4'0000 - attribute \src "ls180.v:4411.4-4413.7" - switch \libresocsim_dataw_pads_out_ready - attribute \src "ls180.v:4411.8-4411.40" - case 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\libresocsim_dataw_stop[0:0] $not$ls180.v:4416$666_Y - assign $0\libresocsim_dataw_pads_out_payload_clk[0:0] 1'1 - assign $0\libresocsim_dataw_pads_out_payload_data_oe[0:0] 1'1 - attribute \src "ls180.v:4419.4-4426.11" - switch \libresocsim_dataw_count - attribute \src "ls180.v:0.0-0.0" - case 8'00000000 - assign $0\libresocsim_dataw_pads_out_payload_data_o[3:0] \libresocsim_dataw_sink_payload_data [7:4] - attribute \src "ls180.v:0.0-0.0" - case 8'00000001 - assign $0\libresocsim_dataw_pads_out_payload_data_o[3:0] \libresocsim_dataw_sink_payload_data [3:0] - case - end - attribute \src "ls180.v:4427.4-4439.7" - switch \libresocsim_dataw_pads_out_ready - attribute \src "ls180.v:4427.8-4427.40" - case 1'1 - assign $0\libresocsim_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4428$667_Y - assign $0\libresocsim_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4430.5-4438.8" - switch $eq$ls180.v:4430$668_Y - attribute \src "ls180.v:4430.9-4430.42" - case 1'1 - assign $0\libresocsim_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 - assign $0\libresocsim_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4433.6-4437.9" - switch \libresocsim_dataw_sink_last - attribute \src "ls180.v:4433.10-4433.37" - case 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:4435.10-4435.14" - case - assign $0\libresocsim_dataw_sink_ready[0:0] 1'1 - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\libresocsim_dataw_pads_out_payload_clk[0:0] 1'1 - assign $0\libresocsim_dataw_pads_out_payload_data_oe[0:0] 1'1 - assign $0\libresocsim_dataw_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4445.4-4448.7" - switch \libresocsim_dataw_pads_out_ready - attribute \src "ls180.v:4445.8-4445.40" - case 1'1 - assign $0\libresocsim_dataw_start[0:0] 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'100 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\libresocsim_dataw_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4452.4-4457.7" - switch \libresocsim_dataw_pads_out_ready - attribute \src "ls180.v:4452.8-4452.40" - case 1'1 - attribute \src "ls180.v:4453.5-4456.8" - switch \libresocsim_dataw_pads_in_payload_data_i [0] - attribute \src "ls180.v:4453.9-4453.52" - case 1'1 - assign $0\libresocsim_dataw_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'000 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\libresocsim_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 - assign $0\libresocsim_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4462.4-4464.7" - switch $and$ls180.v:4462$669_Y - attribute \src "ls180.v:4462.8-4462.73" - case 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'001 - case - end - end - sync always - update \libresocsim_dataw_pads_out_payload_clk $0\libresocsim_dataw_pads_out_payload_clk[0:0] - update \libresocsim_dataw_pads_out_payload_data_o $0\libresocsim_dataw_pads_out_payload_data_o[3:0] - update \libresocsim_dataw_pads_out_payload_data_oe $0\libresocsim_dataw_pads_out_payload_data_oe[0:0] - update \libresocsim_dataw_sink_ready $0\libresocsim_dataw_sink_ready[0:0] - update \libresocsim_dataw_stop $0\libresocsim_dataw_stop[0:0] - update \libresocsim_dataw_start $0\libresocsim_dataw_start[0:0] - update \builder_sdphy_fsm_next_state $0\builder_sdphy_fsm_next_state[2:0] - update \libresocsim_dataw_count_sdphy_fsm_next_value $0\libresocsim_dataw_count_sdphy_fsm_next_value[7:0] - update \libresocsim_dataw_count_sdphy_fsm_next_value_ce $0\libresocsim_dataw_count_sdphy_fsm_next_value_ce[0:0] - end - attribute \src "ls180.v:440.5-440.35" - process $proc$ls180.v:440$2707 - assign { } { } - assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 - sync always - update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] - sync init - end - attribute \src "ls180.v:442.5-442.39" - process $proc$ls180.v:442$2708 - assign { } { } - assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] - end - attribute \src "ls180.v:444.5-444.39" - process $proc$ls180.v:444$2709 - assign { } { } - assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] - end - attribute \src "ls180.v:447.5-447.32" - process $proc$ls180.v:447$2710 - assign { } { } - assign $1\main_sdram_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] - end - attribute \src "ls180.v:448.5-448.32" - process $proc$ls180.v:448$2711 - assign { } { } - assign $1\main_sdram_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] - end - attribute \src "ls180.v:449.5-449.31" - process $proc$ls180.v:449$2712 - assign { } { } - assign $1\main_sdram_cmd_last[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] - end - attribute \src "ls180.v:450.12-450.44" - process $proc$ls180.v:450$2713 - assign { } { } - assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] - end - attribute \src "ls180.v:4501.1-4602.4" - process $proc$ls180.v:4501$677 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\libresocsim_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - assign $0\libresocsim_datar_stop[0:0] 1'0 - assign $0\libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 - assign $0\libresocsim_datar_source_payload_status[2:0] 3'000 - assign $0\libresocsim_datar_datar_source_source_ready0[0:0] 1'0 - assign $0\libresocsim_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 - assign $0\libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 - assign $0\libresocsim_datar_source_payload_data[7:0] 8'00000000 - assign $0\libresocsim_datar_sink_ready[0:0] 1'0 - assign $0\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 - assign $0\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 - assign $0\libresocsim_datar_source_valid[0:0] 1'0 - assign $0\libresocsim_datar_source_last[0:0] 1'0 - assign $0\libresocsim_datar_pads_out_payload_clk[0:0] 1'0 - assign { } { } - assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:4518.2-4601.9" - switch \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\libresocsim_datar_pads_out_payload_clk[0:0] 1'1 - assign $0\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 - assign $0\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 - assign { } { } - assign { } { } - assign $0\libresocsim_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4528$679_Y - assign $0\libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4525.4-4527.7" - switch \libresocsim_datar_datar_source_source_valid0 - attribute \src "ls180.v:4525.8-4525.52" - case 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:4530.4-4533.7" - switch $eq$ls180.v:4530$680_Y - attribute \src "ls180.v:4530.8-4530.43" - case 1'1 - assign $0\libresocsim_datar_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\libresocsim_datar_pads_out_payload_clk[0:0] 1'1 - assign $0\libresocsim_datar_source_valid[0:0] \libresocsim_datar_datar_source_source_valid0 - assign $0\libresocsim_datar_source_payload_status[2:0] 3'000 - assign $0\libresocsim_datar_source_last[0:0] $eq$ls180.v:4539$683_Y - assign $0\libresocsim_datar_source_payload_data[7:0] \libresocsim_datar_datar_source_source_payload_data0 - assign $0\libresocsim_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4560$685_Y - assign $0\libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4541.4-4559.7" - switch \libresocsim_datar_source_valid - attribute \src "ls180.v:4541.8-4541.38" - case 1'1 - attribute \src "ls180.v:4542.5-4558.8" - switch \libresocsim_datar_source_ready - attribute \src "ls180.v:4542.9-4542.39" - case 1'1 - assign $0\libresocsim_datar_datar_source_source_ready0[0:0] 1'1 - assign $0\libresocsim_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4544$684_Y - assign $0\libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4546.6-4555.9" - switch \libresocsim_datar_source_last - attribute \src "ls180.v:4546.10-4546.39" - case 1'1 - assign $0\libresocsim_datar_sink_ready[0:0] 1'1 - attribute \src "ls180.v:4548.7-4554.10" - switch \libresocsim_datar_sink_last - attribute \src "ls180.v:4548.11-4548.38" - case 1'1 - assign $0\libresocsim_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - assign $0\libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011 - attribute \src "ls180.v:4552.11-4552.15" - case - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 - end - case - end - attribute \src "ls180.v:4556.9-4556.13" - case - assign $0\libresocsim_datar_stop[0:0] 1'1 - end - case - end - attribute \src "ls180.v:4562.4-4565.7" - switch $eq$ls180.v:4562$686_Y - attribute \src "ls180.v:4562.8-4562.43" - case 1'1 - assign $0\libresocsim_datar_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\libresocsim_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4569.4-4575.7" - switch \libresocsim_datar_pads_out_ready - attribute \src "ls180.v:4569.8-4569.40" - case 1'1 - assign $0\libresocsim_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4570$687_Y - assign $0\libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4572.5-4574.8" - switch $eq$ls180.v:4572$688_Y - attribute \src "ls180.v:4572.9-4572.43" - case 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\libresocsim_datar_source_valid[0:0] 1'1 - assign $0\libresocsim_datar_source_payload_status[2:0] 3'001 - assign $0\libresocsim_datar_source_last[0:0] 1'1 - attribute \src "ls180.v:4581.4-4583.7" - switch $and$ls180.v:4581$689_Y - attribute \src "ls180.v:4581.8-4581.73" - case 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\libresocsim_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - assign $0\libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4588.4-4599.7" - switch $and$ls180.v:4588$690_Y - attribute \src "ls180.v:4588.8-4588.73" - case 1'1 - assign $0\libresocsim_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4590.5-4598.8" - switch \libresocsim_datar_pads_out_ready - attribute \src "ls180.v:4590.9-4590.41" - case 1'1 - assign $0\libresocsim_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000 - assign $0\libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - assign $0\libresocsim_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - assign $0\libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - assign $0\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'1 - assign $0\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'001 - case - end - case - end - end - sync always - update \libresocsim_datar_pads_out_payload_clk $0\libresocsim_datar_pads_out_payload_clk[0:0] - update \libresocsim_datar_sink_ready $0\libresocsim_datar_sink_ready[0:0] - update \libresocsim_datar_source_valid $0\libresocsim_datar_source_valid[0:0] - update \libresocsim_datar_source_last $0\libresocsim_datar_source_last[0:0] - update \libresocsim_datar_source_payload_data $0\libresocsim_datar_source_payload_data[7:0] - update \libresocsim_datar_source_payload_status $0\libresocsim_datar_source_payload_status[2:0] - update \libresocsim_datar_stop $0\libresocsim_datar_stop[0:0] - update \libresocsim_datar_datar_source_source_ready0 $0\libresocsim_datar_datar_source_source_ready0[0:0] - update \builder_sdphy_sdphydatar_next_state $0\builder_sdphy_sdphydatar_next_state[2:0] - update \libresocsim_datar_count_sdphy_sdphydatar_next_value0 $0\libresocsim_datar_count_sdphy_sdphydatar_next_value0[9:0] - update \libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0 $0\libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - update \libresocsim_datar_timeout_sdphy_sdphydatar_next_value1 $0\libresocsim_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - update \libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1 $0\libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - update \libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - update \libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - end - attribute \src "ls180.v:451.11-451.43" - process $proc$ls180.v:451$2714 - assign { } { } - assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 - sync always - sync init - update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] - end - attribute \src "ls180.v:452.5-452.38" - process $proc$ls180.v:452$2715 - assign { } { } - assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:453.5-453.38" - process $proc$ls180.v:453$2716 - assign { } { } - assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:454.5-454.37" - process $proc$ls180.v:454$2717 - assign { } { } - assign $1\main_sdram_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] - end - attribute \src "ls180.v:455.5-455.42" - process $proc$ls180.v:455$2718 - assign { } { } - assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 - sync always - update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] - sync init - end - attribute \src "ls180.v:456.5-456.43" - process $proc$ls180.v:456$2719 - assign { } { } - assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 - sync always - update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] - sync init - end - attribute \src "ls180.v:462.11-462.44" - process $proc$ls180.v:462$2720 - assign { } { } - assign $1\main_sdram_timer_count1[9:0] 10'1100001101 - sync always - sync init - update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] - end - attribute \src "ls180.v:464.5-464.38" - process $proc$ls180.v:464$2721 - assign { } { } - assign $1\main_sdram_postponer_req_o[0:0] 1'0 - sync always - sync init - update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] - end - attribute \src "ls180.v:465.5-465.38" - process $proc$ls180.v:465$2722 - assign { } { } - assign $1\main_sdram_postponer_count[0:0] 1'0 - sync always - sync init - update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] - end - attribute \src "ls180.v:466.5-466.39" - process $proc$ls180.v:466$2723 - assign { } { } - assign $1\main_sdram_sequencer_start0[0:0] 1'0 - sync always - sync init - update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] - end - attribute \src "ls180.v:4660.1-4667.4" - process $proc$ls180.v:4660$812 - assign { } { } - assign $0\libresocsim_sdcore_crc7_inserter_crc[6:0] 7'0000000 - attribute \src "ls180.v:4662.2-4666.5" - switch \libresocsim_sdcore_crc7_inserter_enable - attribute \src "ls180.v:4662.6-4662.45" - case 1'1 - assign $0\libresocsim_sdcore_crc7_inserter_crc[6:0] \libresocsim_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:4664.6-4664.10" - case - assign $0\libresocsim_sdcore_crc7_inserter_crc[6:0] \libresocsim_sdcore_crc7_inserter_crcreg0 - end - sync always - update \libresocsim_sdcore_crc7_inserter_crc $0\libresocsim_sdcore_crc7_inserter_crc[6:0] - end - attribute \src "ls180.v:4682.1-4689.4" - process $proc$ls180.v:4682$835 - assign { } { } - assign $0\libresocsim_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:4684.2-4688.5" - switch \libresocsim_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:4684.6-4684.51" - case 1'1 - assign $0\libresocsim_sdcore_crc16_inserter_crc0_crc[15:0] \libresocsim_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:4686.6-4686.10" - case - assign $0\libresocsim_sdcore_crc16_inserter_crc0_crc[15:0] \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 - end - sync always - update \libresocsim_sdcore_crc16_inserter_crc0_crc $0\libresocsim_sdcore_crc16_inserter_crc0_crc[15:0] - end - attribute \src "ls180.v:469.5-469.38" - process $proc$ls180.v:469$2724 - assign { } { } - assign $1\main_sdram_sequencer_done1[0:0] 1'0 - sync always - sync init - update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] - end - attribute \src "ls180.v:4692.1-4699.4" - process $proc$ls180.v:4692$846 - assign { } { } - assign $0\libresocsim_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:4694.2-4698.5" - switch \libresocsim_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:4694.6-4694.51" - case 1'1 - assign $0\libresocsim_sdcore_crc16_inserter_crc1_crc[15:0] \libresocsim_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:4696.6-4696.10" - case - assign $0\libresocsim_sdcore_crc16_inserter_crc1_crc[15:0] \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 - end - sync always - update \libresocsim_sdcore_crc16_inserter_crc1_crc $0\libresocsim_sdcore_crc16_inserter_crc1_crc[15:0] - end - attribute \src "ls180.v:470.11-470.46" - process $proc$ls180.v:470$2725 - assign { } { } - assign $1\main_sdram_sequencer_counter[3:0] 4'0000 - sync always - sync init - update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] - end - attribute \src "ls180.v:4702.1-4709.4" - process $proc$ls180.v:4702$857 - assign { } { } - assign $0\libresocsim_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:4704.2-4708.5" - switch \libresocsim_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:4704.6-4704.51" - case 1'1 - assign $0\libresocsim_sdcore_crc16_inserter_crc2_crc[15:0] \libresocsim_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:4706.6-4706.10" - case - assign $0\libresocsim_sdcore_crc16_inserter_crc2_crc[15:0] \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 - end - sync always - update \libresocsim_sdcore_crc16_inserter_crc2_crc $0\libresocsim_sdcore_crc16_inserter_crc2_crc[15:0] - end - attribute \src "ls180.v:471.5-471.38" - process $proc$ls180.v:471$2726 - assign { } { } - assign $1\main_sdram_sequencer_count[0:0] 1'0 - sync always - sync init - update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] - end - attribute \src "ls180.v:4712.1-4719.4" - process $proc$ls180.v:4712$868 - assign { } { } - assign $0\libresocsim_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:4714.2-4718.5" - switch \libresocsim_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:4714.6-4714.51" - case 1'1 - assign $0\libresocsim_sdcore_crc16_inserter_crc3_crc[15:0] \libresocsim_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:4716.6-4716.10" - case - assign $0\libresocsim_sdcore_crc16_inserter_crc3_crc[15:0] \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 - end - sync always - update \libresocsim_sdcore_crc16_inserter_crc3_crc $0\libresocsim_sdcore_crc16_inserter_crc3_crc[15:0] - end - attribute \src "ls180.v:4720.1-4799.4" - process $proc$ls180.v:4720$869 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 - assign $0\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 - assign $0\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 - assign $0\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 - assign $0\libresocsim_sdcore_crc16_inserter_source_valid[0:0] 1'0 - assign $0\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 - assign $0\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 - assign $0\libresocsim_sdcore_crc16_inserter_source_last[0:0] 1'0 - assign $0\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 - assign $0\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 - assign $0\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 - assign { } { } - assign $0\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 - assign $0\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 - assign $0\libresocsim_sdcore_crc16_inserter_sink_ready[0:0] 1'0 - assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:4737.2-4798.9" - switch \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\libresocsim_sdcore_crc16_inserter_sink_ready[0:0] 1'0 - assign $0\libresocsim_sdcore_crc16_inserter_source_valid[0:0] 1'1 - attribute \src "ls180.v:4741.4-4743.7" - switch $eq$ls180.v:4741$870_Y - attribute \src "ls180.v:4741.8-4741.55" - case 1'1 - assign $0\libresocsim_sdcore_crc16_inserter_source_last[0:0] 1'1 - case - end - attribute \src "ls180.v:4744.4-4769.11" - switch \libresocsim_sdcore_crc16_inserter_cnt - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] { \libresocsim_sdcore_crc16_inserter_crctmp3 [15] \libresocsim_sdcore_crc16_inserter_crctmp2 [15] \libresocsim_sdcore_crc16_inserter_crctmp1 [15] \libresocsim_sdcore_crc16_inserter_crctmp0 [15] \libresocsim_sdcore_crc16_inserter_crctmp3 [14] \libresocsim_sdcore_crc16_inserter_crctmp2 [14] \libresocsim_sdcore_crc16_inserter_crctmp1 [14] \libresocsim_sdcore_crc16_inserter_crctmp0 [14] } - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] { \libresocsim_sdcore_crc16_inserter_crctmp3 [13] \libresocsim_sdcore_crc16_inserter_crctmp2 [13] \libresocsim_sdcore_crc16_inserter_crctmp1 [13] \libresocsim_sdcore_crc16_inserter_crctmp0 [13] \libresocsim_sdcore_crc16_inserter_crctmp3 [12] \libresocsim_sdcore_crc16_inserter_crctmp2 [12] \libresocsim_sdcore_crc16_inserter_crctmp1 [12] \libresocsim_sdcore_crc16_inserter_crctmp0 [12] } - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] { \libresocsim_sdcore_crc16_inserter_crctmp3 [11] \libresocsim_sdcore_crc16_inserter_crctmp2 [11] \libresocsim_sdcore_crc16_inserter_crctmp1 [11] \libresocsim_sdcore_crc16_inserter_crctmp0 [11] \libresocsim_sdcore_crc16_inserter_crctmp3 [10] \libresocsim_sdcore_crc16_inserter_crctmp2 [10] \libresocsim_sdcore_crc16_inserter_crctmp1 [10] \libresocsim_sdcore_crc16_inserter_crctmp0 [10] } - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] { \libresocsim_sdcore_crc16_inserter_crctmp3 [9] \libresocsim_sdcore_crc16_inserter_crctmp2 [9] \libresocsim_sdcore_crc16_inserter_crctmp1 [9] \libresocsim_sdcore_crc16_inserter_crctmp0 [9] \libresocsim_sdcore_crc16_inserter_crctmp3 [8] \libresocsim_sdcore_crc16_inserter_crctmp2 [8] \libresocsim_sdcore_crc16_inserter_crctmp1 [8] \libresocsim_sdcore_crc16_inserter_crctmp0 [8] } - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] { \libresocsim_sdcore_crc16_inserter_crctmp3 [7] \libresocsim_sdcore_crc16_inserter_crctmp2 [7] \libresocsim_sdcore_crc16_inserter_crctmp1 [7] \libresocsim_sdcore_crc16_inserter_crctmp0 [7] \libresocsim_sdcore_crc16_inserter_crctmp3 [6] \libresocsim_sdcore_crc16_inserter_crctmp2 [6] \libresocsim_sdcore_crc16_inserter_crctmp1 [6] \libresocsim_sdcore_crc16_inserter_crctmp0 [6] } - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] { \libresocsim_sdcore_crc16_inserter_crctmp3 [5] \libresocsim_sdcore_crc16_inserter_crctmp2 [5] \libresocsim_sdcore_crc16_inserter_crctmp1 [5] \libresocsim_sdcore_crc16_inserter_crctmp0 [5] \libresocsim_sdcore_crc16_inserter_crctmp3 [4] \libresocsim_sdcore_crc16_inserter_crctmp2 [4] \libresocsim_sdcore_crc16_inserter_crctmp1 [4] \libresocsim_sdcore_crc16_inserter_crctmp0 [4] } - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] { \libresocsim_sdcore_crc16_inserter_crctmp3 [3] \libresocsim_sdcore_crc16_inserter_crctmp2 [3] \libresocsim_sdcore_crc16_inserter_crctmp1 [3] \libresocsim_sdcore_crc16_inserter_crctmp0 [3] \libresocsim_sdcore_crc16_inserter_crctmp3 [2] \libresocsim_sdcore_crc16_inserter_crctmp2 [2] \libresocsim_sdcore_crc16_inserter_crctmp1 [2] \libresocsim_sdcore_crc16_inserter_crctmp0 [2] } - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] { \libresocsim_sdcore_crc16_inserter_crctmp3 [1] \libresocsim_sdcore_crc16_inserter_crctmp2 [1] \libresocsim_sdcore_crc16_inserter_crctmp1 [1] \libresocsim_sdcore_crc16_inserter_crctmp0 [1] \libresocsim_sdcore_crc16_inserter_crctmp3 [0] \libresocsim_sdcore_crc16_inserter_crctmp2 [0] \libresocsim_sdcore_crc16_inserter_crctmp1 [0] \libresocsim_sdcore_crc16_inserter_crctmp0 [0] } - case - end - attribute \src "ls180.v:4770.4-4777.7" - switch \libresocsim_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:4770.8-4770.54" - case 1'1 - attribute \src "ls180.v:4771.5-4776.8" - switch $eq$ls180.v:4771$871_Y - attribute \src "ls180.v:4771.9-4771.56" - case 1'1 - assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 - attribute \src "ls180.v:4773.9-4773.13" - case - assign $0\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:4774$872_Y - assign $0\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] \libresocsim_sdcore_crc16_inserter_sink_payload_data - assign $0\libresocsim_sdcore_crc16_inserter_source_valid[0:0] \libresocsim_sdcore_crc16_inserter_sink_valid - assign $0\libresocsim_sdcore_crc16_inserter_sink_ready[0:0] \libresocsim_sdcore_crc16_inserter_source_ready - assign $0\libresocsim_sdcore_crc16_inserter_source_last[0:0] 1'0 - assign $0\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] \libresocsim_sdcore_crc16_inserter_crc0_crc - assign $0\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'1 - assign $0\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] \libresocsim_sdcore_crc16_inserter_crc1_crc - assign $0\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'1 - assign $0\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] \libresocsim_sdcore_crc16_inserter_crc2_crc - assign $0\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1 - assign $0\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \libresocsim_sdcore_crc16_inserter_crc3_crc - assign $0\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:4792.4-4796.7" - switch $and$ls180.v:4792$874_Y - attribute \src "ls180.v:4792.8-4792.149" - case 1'1 - assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1 - assign $0\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 - assign $0\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 - case - end - end - sync always - update \libresocsim_sdcore_crc16_inserter_sink_ready $0\libresocsim_sdcore_crc16_inserter_sink_ready[0:0] - update \libresocsim_sdcore_crc16_inserter_source_valid $0\libresocsim_sdcore_crc16_inserter_source_valid[0:0] - update \libresocsim_sdcore_crc16_inserter_source_last $0\libresocsim_sdcore_crc16_inserter_source_last[0:0] - update \libresocsim_sdcore_crc16_inserter_source_payload_data $0\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] - update \builder_sdcore_crcupstreaminserter_next_state $0\builder_sdcore_crcupstreaminserter_next_state[0:0] - update \libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $0\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - update \libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $0\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - update \libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $0\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - update \libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $0\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - update \libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $0\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - update \libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $0\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - update \libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $0\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - update \libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $0\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - update \libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - update \libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - end - attribute \src "ls180.v:477.5-477.51" - process $proc$ls180.v:477$2727 - assign { } { } - assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] - end - attribute \src "ls180.v:478.5-478.51" - process $proc$ls180.v:478$2728 - assign { } { } - assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] - end - attribute \src "ls180.v:480.5-480.47" - process $proc$ls180.v:480$2729 - assign { } { } - assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] - end - attribute \src "ls180.v:4800.1-4805.4" - process $proc$ls180.v:4800$875 - assign { } { } - assign $0\libresocsim_sdcore_crc16_checker_valid[0:0] 1'0 - attribute \src "ls180.v:4802.2-4804.5" - switch $and$ls180.v:4802$882_Y - attribute \src "ls180.v:4802.6-4802.357" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_valid[0:0] 1'1 - case - end - sync always - update \libresocsim_sdcore_crc16_checker_valid $0\libresocsim_sdcore_crc16_checker_valid[0:0] - end - attribute \src "ls180.v:4808.1-4815.4" - process $proc$ls180.v:4808$884 - assign { } { } - assign $0\libresocsim_sdcore_crc16_checker_crc0_clr[0:0] 1'0 - attribute \src "ls180.v:4810.2-4814.5" - switch $eq$ls180.v:4810$885_Y - attribute \src "ls180.v:4810.6-4810.52" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_crc0_clr[0:0] 1'1 - attribute \src "ls180.v:4812.6-4812.10" - case - assign $0\libresocsim_sdcore_crc16_checker_crc0_clr[0:0] 1'0 - end - sync always - update \libresocsim_sdcore_crc16_checker_crc0_clr $0\libresocsim_sdcore_crc16_checker_crc0_clr[0:0] - end - attribute \src "ls180.v:481.5-481.45" - process $proc$ls180.v:481$2730 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] - end - attribute \src "ls180.v:4818.1-4825.4" - process $proc$ls180.v:4818$887 - assign { } { } - assign $0\libresocsim_sdcore_crc16_checker_crc1_clr[0:0] 1'0 - attribute \src "ls180.v:4820.2-4824.5" - switch $eq$ls180.v:4820$888_Y - attribute \src "ls180.v:4820.6-4820.52" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_crc1_clr[0:0] 1'1 - attribute \src "ls180.v:4822.6-4822.10" - case - assign $0\libresocsim_sdcore_crc16_checker_crc1_clr[0:0] 1'0 - end - sync always - update \libresocsim_sdcore_crc16_checker_crc1_clr $0\libresocsim_sdcore_crc16_checker_crc1_clr[0:0] - end - attribute \src "ls180.v:482.5-482.45" - process $proc$ls180.v:482$2731 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] - end - attribute \src "ls180.v:4828.1-4835.4" - process $proc$ls180.v:4828$890 - assign { } { } - assign $0\libresocsim_sdcore_crc16_checker_crc2_clr[0:0] 1'0 - attribute \src "ls180.v:4830.2-4834.5" - switch $eq$ls180.v:4830$891_Y - attribute \src "ls180.v:4830.6-4830.52" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_crc2_clr[0:0] 1'1 - attribute \src "ls180.v:4832.6-4832.10" - case - assign $0\libresocsim_sdcore_crc16_checker_crc2_clr[0:0] 1'0 - end - sync always - update \libresocsim_sdcore_crc16_checker_crc2_clr $0\libresocsim_sdcore_crc16_checker_crc2_clr[0:0] - end - attribute \src "ls180.v:483.12-483.57" - process $proc$ls180.v:483$2732 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] - end - attribute \src "ls180.v:4838.1-4845.4" - process $proc$ls180.v:4838$893 - assign { } { } - assign $0\libresocsim_sdcore_crc16_checker_crc3_clr[0:0] 1'0 - attribute \src "ls180.v:4840.2-4844.5" - switch $eq$ls180.v:4840$894_Y - attribute \src "ls180.v:4840.6-4840.52" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_crc3_clr[0:0] 1'1 - attribute \src "ls180.v:4842.6-4842.10" - case - assign $0\libresocsim_sdcore_crc16_checker_crc3_clr[0:0] 1'0 - end - sync always - update \libresocsim_sdcore_crc16_checker_crc3_clr $0\libresocsim_sdcore_crc16_checker_crc3_clr[0:0] - end - attribute \src "ls180.v:4847.1-4852.4" - process $proc$ls180.v:4847$895 - assign { } { } - assign $0\libresocsim_sdcore_crc16_checker_source_valid[0:0] 1'0 - attribute \src "ls180.v:4849.2-4851.5" - switch $and$ls180.v:4849$897_Y - attribute \src "ls180.v:4849.6-4849.99" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_source_valid[0:0] 1'1 - case - end - sync always - update \libresocsim_sdcore_crc16_checker_source_valid $0\libresocsim_sdcore_crc16_checker_source_valid[0:0] - end - attribute \src "ls180.v:485.5-485.51" - process $proc$ls180.v:485$2733 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:4853.1-4860.4" - process $proc$ls180.v:4853$898 - assign { } { } - assign $0\libresocsim_sdcore_crc16_checker_sink_ready[0:0] 1'0 - attribute \src "ls180.v:4855.2-4859.5" - switch $lt$ls180.v:4855$899_Y - attribute \src "ls180.v:4855.6-4855.51" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_sink_ready[0:0] 1'1 - attribute \src "ls180.v:4857.6-4857.10" - case - assign $0\libresocsim_sdcore_crc16_checker_sink_ready[0:0] \libresocsim_sdcore_crc16_checker_source_ready - end - sync always - update \libresocsim_sdcore_crc16_checker_sink_ready $0\libresocsim_sdcore_crc16_checker_sink_ready[0:0] - end - attribute \src "ls180.v:486.5-486.51" - process $proc$ls180.v:486$2734 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:4864.1-4871.4" - process $proc$ls180.v:4864$910 - assign { } { } - assign $0\libresocsim_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:4866.2-4870.5" - switch \libresocsim_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:4866.6-4866.50" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_crc0_crc[15:0] \libresocsim_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:4868.6-4868.10" - case - assign $0\libresocsim_sdcore_crc16_checker_crc0_crc[15:0] \libresocsim_sdcore_crc16_checker_crc0_crcreg0 - end - sync always - update \libresocsim_sdcore_crc16_checker_crc0_crc $0\libresocsim_sdcore_crc16_checker_crc0_crc[15:0] - end - attribute \src "ls180.v:487.5-487.50" - process $proc$ls180.v:487$2735 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] - end - attribute \src "ls180.v:4874.1-4881.4" - process $proc$ls180.v:4874$921 - assign { } { } - assign $0\libresocsim_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:4876.2-4880.5" - switch \libresocsim_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:4876.6-4876.50" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_crc1_crc[15:0] \libresocsim_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:4878.6-4878.10" - case - assign $0\libresocsim_sdcore_crc16_checker_crc1_crc[15:0] \libresocsim_sdcore_crc16_checker_crc1_crcreg0 - end - sync always - update \libresocsim_sdcore_crc16_checker_crc1_crc $0\libresocsim_sdcore_crc16_checker_crc1_crc[15:0] - end - attribute \src "ls180.v:488.5-488.54" - process $proc$ls180.v:488$2736 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:4884.1-4891.4" - process $proc$ls180.v:4884$932 - assign { } { } - assign $0\libresocsim_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:4886.2-4890.5" - switch \libresocsim_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:4886.6-4886.50" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_crc2_crc[15:0] \libresocsim_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:4888.6-4888.10" - case - assign $0\libresocsim_sdcore_crc16_checker_crc2_crc[15:0] \libresocsim_sdcore_crc16_checker_crc2_crcreg0 - end - sync always - update \libresocsim_sdcore_crc16_checker_crc2_crc $0\libresocsim_sdcore_crc16_checker_crc2_crc[15:0] - end - attribute \src "ls180.v:489.5-489.55" - process $proc$ls180.v:489$2737 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:4894.1-4901.4" - process $proc$ls180.v:4894$943 - assign { } { } - assign $0\libresocsim_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:4896.2-4900.5" - switch \libresocsim_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:4896.6-4896.50" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_crc3_crc[15:0] \libresocsim_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:4898.6-4898.10" - case - assign $0\libresocsim_sdcore_crc16_checker_crc3_crc[15:0] \libresocsim_sdcore_crc16_checker_crc3_crcreg0 - end - sync always - update \libresocsim_sdcore_crc16_checker_crc3_crc $0\libresocsim_sdcore_crc16_checker_crc3_crc[15:0] - end - attribute \src "ls180.v:490.5-490.56" - process $proc$ls180.v:490$2738 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:4902.1-5092.4" - process $proc$ls180.v:4902$944 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\libresocsim_sdcore_crc16_inserter_source_ready[0:0] 1'0 - assign { } { } - assign $0\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 - assign $0\libresocsim_dataw_sink_valid[0:0] 1'0 - assign $0\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 - assign $0\libresocsim_datar_sink_valid[0:0] 1'0 - assign $0\libresocsim_dataw_sink_first[0:0] 1'0 - assign $0\libresocsim_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 - assign $0\libresocsim_dataw_sink_last[0:0] 1'0 - assign $0\libresocsim_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 - assign $0\libresocsim_dataw_sink_payload_data[7:0] 8'00000000 - assign $0\libresocsim_datar_sink_payload_block_length[9:0] 10'0000000000 - assign $0\libresocsim_cmdr_sink_valid[0:0] 1'0 - assign $0\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 - assign $0\libresocsim_datar_source_ready[0:0] 1'0 - assign $0\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 - assign $0\libresocsim_datar_sink_last[0:0] 1'0 - assign $0\libresocsim_cmdr_sink_last[0:0] 1'0 - assign $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - assign $0\libresocsim_cmdr_sink_payload_length[7:0] 8'00000000 - assign $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 - assign $0\libresocsim_cmdr_source_ready[0:0] 1'0 - assign $0\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 - assign $0\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 - assign $0\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 - assign $0\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 - assign $0\libresocsim_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 - assign $0\libresocsim_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 - assign $0\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 - assign $0\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 - assign $0\libresocsim_cmdw_sink_valid[0:0] 1'0 - assign $0\libresocsim_cmdw_sink_last[0:0] 1'0 - assign $0\libresocsim_cmdw_sink_payload_data[7:0] 8'00000000 - assign $0\libresocsim_sdcore_crc16_checker_sink_valid[0:0] 1'0 - assign $0\libresocsim_sdcore_crc16_checker_sink_first[0:0] 1'0 - assign $0\libresocsim_sdcore_crc16_checker_sink_last[0:0] 1'0 - assign $0\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $0\libresocsim_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 - assign $0\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 - assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state - attribute \src "ls180.v:4943.2-5091.9" - switch \builder_sdcore_fsm_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\libresocsim_cmdw_sink_valid[0:0] 1'1 - attribute \src "ls180.v:4946.4-4966.11" - switch \libresocsim_sdcore_cmd_count - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\libresocsim_cmdw_sink_payload_data[7:0] { 2'01 \libresocsim_sdcore_cmd_command_storage [13:8] } - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\libresocsim_cmdw_sink_payload_data[7:0] \libresocsim_sdcore_cmd_argument_storage [31:24] - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\libresocsim_cmdw_sink_payload_data[7:0] \libresocsim_sdcore_cmd_argument_storage [23:16] - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\libresocsim_cmdw_sink_payload_data[7:0] \libresocsim_sdcore_cmd_argument_storage [15:8] - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\libresocsim_cmdw_sink_payload_data[7:0] \libresocsim_sdcore_cmd_argument_storage [7:0] - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\libresocsim_cmdw_sink_payload_data[7:0] { \libresocsim_sdcore_crc7_inserter_crc 1'1 } - assign $0\libresocsim_cmdw_sink_last[0:0] $eq$ls180.v:4964$945_Y - case - end - attribute \src "ls180.v:4967.4-4979.7" - switch $and$ls180.v:4967$946_Y - attribute \src "ls180.v:4967.8-4967.67" - case 1'1 - assign $0\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:4968$947_Y - assign $0\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 - attribute \src "ls180.v:4970.5-4978.8" - switch $eq$ls180.v:4970$948_Y - attribute \src "ls180.v:4970.9-4970.47" - case 1'1 - attribute \src "ls180.v:4971.6-4977.9" - switch $eq$ls180.v:4971$949_Y - attribute \src "ls180.v:4971.10-4971.47" - case 1'1 - assign $0\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 - assign $0\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:4975.10-4975.14" - case - assign $0\builder_sdcore_fsm_next_state[2:0] 3'010 - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\libresocsim_cmdr_sink_valid[0:0] 1'1 - assign $0\libresocsim_cmdr_sink_last[0:0] $eq$ls180.v:4983$950_Y - assign $0\libresocsim_cmdr_source_ready[0:0] 1'1 - attribute \src "ls180.v:4984.4-4988.7" - switch $eq$ls180.v:4984$951_Y - attribute \src "ls180.v:4984.8-4984.45" - case 1'1 - assign $0\libresocsim_cmdr_sink_payload_length[7:0] 8'00010001 - attribute \src "ls180.v:4986.8-4986.12" - case - assign $0\libresocsim_cmdr_sink_payload_length[7:0] 8'00000110 - end - attribute \src "ls180.v:4990.4-5011.7" - switch \libresocsim_cmdr_source_valid - attribute \src "ls180.v:4990.8-4990.37" - case 1'1 - attribute \src "ls180.v:4991.5-5010.8" - switch $eq$ls180.v:4991$952_Y - attribute \src "ls180.v:4991.9-4991.57" - case 1'1 - assign $0\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1 - assign $0\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:4995.9-4995.13" - case - attribute \src "ls180.v:4996.6-5009.9" - switch \libresocsim_cmdr_source_last - attribute \src "ls180.v:4996.10-4996.38" - case 1'1 - attribute \src "ls180.v:4997.7-5005.10" - switch $eq$ls180.v:4997$953_Y - attribute \src "ls180.v:4997.11-4997.49" - case 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:4999.11-4999.15" - case - attribute \src "ls180.v:5000.8-5004.11" - switch $eq$ls180.v:5000$954_Y - attribute \src "ls180.v:5000.12-5000.50" - case 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 - attribute \src "ls180.v:5002.12-5002.16" - case - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - end - end - attribute \src "ls180.v:5006.10-5006.14" - case - assign $0\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \libresocsim_sdcore_cmd_response_status [119:0] \libresocsim_cmdr_source_payload_data } - assign $0\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1 - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\libresocsim_dataw_sink_valid[0:0] \libresocsim_sdcore_crc16_inserter_source_valid - assign $0\libresocsim_sdcore_crc16_inserter_source_ready[0:0] \libresocsim_dataw_sink_ready - assign $0\libresocsim_dataw_sink_first[0:0] \libresocsim_sdcore_crc16_inserter_source_first - assign $0\libresocsim_dataw_sink_last[0:0] \libresocsim_sdcore_crc16_inserter_source_last - assign $0\libresocsim_dataw_sink_payload_data[7:0] \libresocsim_sdcore_crc16_inserter_source_payload_data - assign $0\libresocsim_datar_source_ready[0:0] 1'1 - attribute \src "ls180.v:5019.4-5025.7" - switch $and$ls180.v:5019$956_Y - attribute \src "ls180.v:5019.8-5019.101" - case 1'1 - assign $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5020$957_Y - assign $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5022.5-5024.8" - switch $eq$ls180.v:5022$959_Y - attribute \src "ls180.v:5022.9-5022.91" - case 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - case - end - case - end - attribute \src "ls180.v:5027.4-5032.7" - switch \libresocsim_datar_source_valid - attribute \src "ls180.v:5027.8-5027.38" - case 1'1 - attribute \src "ls180.v:5028.5-5031.8" - switch $ne$ls180.v:5028$960_Y - attribute \src "ls180.v:5028.9-5028.58" - case 1'1 - assign $0\libresocsim_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1 - assign $0\libresocsim_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\libresocsim_datar_sink_valid[0:0] 1'1 - assign $0\libresocsim_datar_sink_payload_block_length[9:0] \libresocsim_sdcore_block_length_storage - assign $0\libresocsim_datar_sink_last[0:0] $eq$ls180.v:5037$962_Y - attribute \src "ls180.v:5038.4-5064.7" - switch \libresocsim_datar_source_valid - attribute \src "ls180.v:5038.8-5038.38" - case 1'1 - attribute \src "ls180.v:5039.5-5063.8" - switch $eq$ls180.v:5039$963_Y - attribute \src "ls180.v:5039.9-5039.58" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_sink_valid[0:0] \libresocsim_datar_source_valid - assign $0\libresocsim_datar_source_ready[0:0] \libresocsim_sdcore_crc16_checker_sink_ready - assign $0\libresocsim_sdcore_crc16_checker_sink_first[0:0] \libresocsim_datar_source_first - assign $0\libresocsim_sdcore_crc16_checker_sink_last[0:0] \libresocsim_datar_source_last - assign $0\libresocsim_sdcore_crc16_checker_sink_payload_data[7:0] \libresocsim_datar_source_payload_data - attribute \src "ls180.v:5045.6-5053.9" - switch $and$ls180.v:5045$964_Y - attribute \src "ls180.v:5045.10-5045.74" - case 1'1 - assign $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5046$965_Y - assign $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5048.7-5052.10" - switch $eq$ls180.v:5048$967_Y - attribute \src "ls180.v:5048.11-5048.93" - case 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5050.11-5050.15" - case - assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 - end - case - end - attribute \src "ls180.v:5054.9-5054.13" - case - attribute \src "ls180.v:5055.6-5062.9" - switch $eq$ls180.v:5055$968_Y - attribute \src "ls180.v:5055.10-5055.59" - case 1'1 - assign $0\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1 - assign $0\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 - assign $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - assign $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - assign $0\libresocsim_datar_source_ready[0:0] 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - case - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 - assign $0\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 - assign $0\libresocsim_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'1 - assign $0\libresocsim_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 - assign $0\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 - assign $0\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 - assign $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - assign $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5075.4-5089.7" - switch \libresocsim_sdcore_cmd_send_re - attribute \src "ls180.v:5075.8-5075.38" - case 1'1 - assign $0\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 - assign $0\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 - assign $0\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 - assign $0\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'1 - assign $0\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 - assign $0\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 - assign $0\libresocsim_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 - assign $0\libresocsim_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 - assign $0\libresocsim_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 - assign $0\libresocsim_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 - assign $0\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 - assign $0\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'001 - case - end - end - sync always - update \libresocsim_cmdw_sink_valid $0\libresocsim_cmdw_sink_valid[0:0] - update \libresocsim_cmdw_sink_last $0\libresocsim_cmdw_sink_last[0:0] - update \libresocsim_cmdw_sink_payload_data $0\libresocsim_cmdw_sink_payload_data[7:0] - update \libresocsim_cmdr_sink_valid $0\libresocsim_cmdr_sink_valid[0:0] - update \libresocsim_cmdr_sink_last $0\libresocsim_cmdr_sink_last[0:0] - update \libresocsim_cmdr_sink_payload_length $0\libresocsim_cmdr_sink_payload_length[7:0] - update \libresocsim_cmdr_source_ready $0\libresocsim_cmdr_source_ready[0:0] - update \libresocsim_dataw_sink_valid $0\libresocsim_dataw_sink_valid[0:0] - update \libresocsim_dataw_sink_first $0\libresocsim_dataw_sink_first[0:0] - update \libresocsim_dataw_sink_last $0\libresocsim_dataw_sink_last[0:0] - update \libresocsim_dataw_sink_payload_data $0\libresocsim_dataw_sink_payload_data[7:0] - update \libresocsim_datar_sink_valid $0\libresocsim_datar_sink_valid[0:0] - update \libresocsim_datar_sink_last $0\libresocsim_datar_sink_last[0:0] - update \libresocsim_datar_sink_payload_block_length $0\libresocsim_datar_sink_payload_block_length[9:0] - update \libresocsim_datar_source_ready $0\libresocsim_datar_source_ready[0:0] - update \libresocsim_sdcore_crc16_inserter_source_ready $0\libresocsim_sdcore_crc16_inserter_source_ready[0:0] - update \libresocsim_sdcore_crc16_checker_sink_valid $0\libresocsim_sdcore_crc16_checker_sink_valid[0:0] - update \libresocsim_sdcore_crc16_checker_sink_first $0\libresocsim_sdcore_crc16_checker_sink_first[0:0] - update \libresocsim_sdcore_crc16_checker_sink_last $0\libresocsim_sdcore_crc16_checker_sink_last[0:0] - update \libresocsim_sdcore_crc16_checker_sink_payload_data $0\libresocsim_sdcore_crc16_checker_sink_payload_data[7:0] - update \builder_sdcore_fsm_next_state $0\builder_sdcore_fsm_next_state[2:0] - update \libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0 $0\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - update \libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $0\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - update \libresocsim_sdcore_data_done_sdcore_fsm_next_value1 $0\libresocsim_sdcore_data_done_sdcore_fsm_next_value1[0:0] - update \libresocsim_sdcore_data_done_sdcore_fsm_next_value_ce1 $0\libresocsim_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - update \libresocsim_sdcore_cmd_count_sdcore_fsm_next_value2 $0\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - update \libresocsim_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $0\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - update \libresocsim_sdcore_data_count_sdcore_fsm_next_value3 $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value3[31:0] - update \libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3 $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - update \libresocsim_sdcore_cmd_error_sdcore_fsm_next_value4 $0\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - update \libresocsim_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $0\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - update \libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value5 $0\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - update \libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $0\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - update \libresocsim_sdcore_data_error_sdcore_fsm_next_value6 $0\libresocsim_sdcore_data_error_sdcore_fsm_next_value6[0:0] - update \libresocsim_sdcore_data_error_sdcore_fsm_next_value_ce6 $0\libresocsim_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - update \libresocsim_sdcore_data_timeout_sdcore_fsm_next_value7 $0\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - update \libresocsim_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $0\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - update \libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - update \libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - end - attribute \src "ls180.v:491.5-491.50" - process $proc$ls180.v:491$2739 - assign { } { } - assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] - end - attribute \src "ls180.v:494.5-494.67" - process $proc$ls180.v:494$2740 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] - sync init - end - attribute \src "ls180.v:495.5-495.66" - process $proc$ls180.v:495$2741 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] - sync init - end - attribute \src "ls180.v:50.5-50.46" - process $proc$ls180.v:50$2569 - assign { } { } - assign $1\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_dbus_ack $1\main_libresocsim_libresoc_dbus_ack[0:0] - end - attribute \src "ls180.v:510.11-510.68" - process $proc$ls180.v:510$2742 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:511.5-511.64" - process $proc$ls180.v:511$2743 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:512.11-512.70" - process $proc$ls180.v:512$2744 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:5120.1-5127.4" - process $proc$ls180.v:5120$969 - assign { } { } - assign $0\libresocsim_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5122.2-5126.5" - switch \libresocsim_sdblock2mem_fifo_replace - attribute \src "ls180.v:5122.6-5122.42" - case 1'1 - assign $0\libresocsim_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5123$970_Y - attribute \src "ls180.v:5124.6-5124.10" - case - assign $0\libresocsim_sdblock2mem_fifo_wrport_adr[4:0] \libresocsim_sdblock2mem_fifo_produce - end - sync always - update \libresocsim_sdblock2mem_fifo_wrport_adr $0\libresocsim_sdblock2mem_fifo_wrport_adr[4:0] - end - attribute \src "ls180.v:513.11-513.70" - process $proc$ls180.v:513$2745 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - end - attribute \src "ls180.v:514.11-514.73" - process $proc$ls180.v:514$2746 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:5153.1-5192.4" - process $proc$ls180.v:5153$980 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - assign $0\libresocsim_sdblock2mem_sink_sink_valid1[0:0] 1'0 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 - assign $0\libresocsim_sdblock2mem_sink_sink_payload_address[31:0] 0 - assign $0\libresocsim_sdblock2mem_sink_sink_payload_data1[31:0] 0 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 - assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state - attribute \src "ls180.v:5163.2-5191.9" - switch \builder_sdblock2memdma_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\libresocsim_sdblock2mem_sink_sink_valid1[0:0] \libresocsim_sdblock2mem_wishbonedmawriter_sink_valid - assign $0\libresocsim_sdblock2mem_sink_sink_payload_data1[31:0] \libresocsim_sdblock2mem_wishbonedmawriter_sink_payload_data - assign $0\libresocsim_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5167$981_Y - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \libresocsim_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:5169.4-5180.7" - switch $and$ls180.v:5169$982_Y - attribute \src "ls180.v:5169.8-5169.117" - case 1'1 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5170$983_Y - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5172.5-5179.8" - switch $eq$ls180.v:5172$985_Y - attribute \src "ls180.v:5172.9-5172.120" - case 1'1 - attribute \src "ls180.v:5173.6-5178.9" - switch \libresocsim_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:5173.10-5173.64" - case 1'1 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5176.10-5176.14" - case - assign $0\builder_sdblock2memdma_next_state[1:0] 2'10 - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_status[0:0] 1'1 - attribute \src "ls180.v:0.0-0.0" - case - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'1 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - assign $0\builder_sdblock2memdma_next_state[1:0] 2'01 - end - sync always - update \libresocsim_sdblock2mem_sink_sink_valid1 $0\libresocsim_sdblock2mem_sink_sink_valid1[0:0] - update \libresocsim_sdblock2mem_sink_sink_payload_address $0\libresocsim_sdblock2mem_sink_sink_payload_address[31:0] - update \libresocsim_sdblock2mem_sink_sink_payload_data1 $0\libresocsim_sdblock2mem_sink_sink_payload_data1[31:0] - update \libresocsim_sdblock2mem_wishbonedmawriter_sink_ready $0\libresocsim_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - update \libresocsim_sdblock2mem_wishbonedmawriter_status $0\libresocsim_sdblock2mem_wishbonedmawriter_status[0:0] - update \builder_sdblock2memdma_next_state $0\builder_sdblock2memdma_next_state[1:0] - update \libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - update \libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - end - attribute \src "ls180.v:5212.1-5249.4" - process $proc$ls180.v:5212$987 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\libresocsim_interface1_bus_we[0:0] 1'0 - assign $0\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 - assign $0\libresocsim_sdmem2block_dma_source_last[0:0] 1'0 - assign $0\libresocsim_sdmem2block_dma_source_payload_data[31:0] 0 - assign $0\libresocsim_interface1_bus_adr[31:0] 0 - assign $0\libresocsim_sdmem2block_dma_source_valid[0:0] 1'0 - assign $0\libresocsim_sdmem2block_dma_sink_ready[0:0] 1'0 - assign $0\libresocsim_interface1_bus_sel[3:0] 4'0000 - assign $0\libresocsim_interface1_bus_cyc[0:0] 1'0 - assign { } { } - assign $0\libresocsim_interface1_bus_stb[0:0] 1'0 - assign $0\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 - assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:5226.2-5248.9" - switch \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\libresocsim_sdmem2block_dma_source_valid[0:0] 1'1 - assign $0\libresocsim_sdmem2block_dma_source_last[0:0] \libresocsim_sdmem2block_dma_sink_last - assign $0\libresocsim_sdmem2block_dma_source_payload_data[31:0] \libresocsim_sdmem2block_dma_data - attribute \src "ls180.v:5231.4-5234.7" - switch \libresocsim_sdmem2block_dma_source_ready - attribute \src "ls180.v:5231.8-5231.48" - case 1'1 - assign $0\libresocsim_sdmem2block_dma_sink_ready[0:0] 1'1 - assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\libresocsim_interface1_bus_stb[0:0] \libresocsim_sdmem2block_dma_sink_valid - assign $0\libresocsim_interface1_bus_cyc[0:0] \libresocsim_sdmem2block_dma_sink_valid - assign $0\libresocsim_interface1_bus_we[0:0] 1'0 - assign $0\libresocsim_interface1_bus_sel[3:0] 4'1111 - assign $0\libresocsim_interface1_bus_adr[31:0] \libresocsim_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:5242.4-5246.7" - switch $and$ls180.v:5242$988_Y - attribute \src "ls180.v:5242.8-5242.73" - case 1'1 - assign $0\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] { \libresocsim_interface1_bus_dat_r [7:0] \libresocsim_interface1_bus_dat_r [15:8] \libresocsim_interface1_bus_dat_r [23:16] \libresocsim_interface1_bus_dat_r [31:24] } - assign $0\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1 - assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'1 - case - end - end - sync always - update \libresocsim_interface1_bus_adr $0\libresocsim_interface1_bus_adr[31:0] - update \libresocsim_interface1_bus_sel $0\libresocsim_interface1_bus_sel[3:0] - update \libresocsim_interface1_bus_cyc $0\libresocsim_interface1_bus_cyc[0:0] - update \libresocsim_interface1_bus_stb $0\libresocsim_interface1_bus_stb[0:0] - update \libresocsim_interface1_bus_we $0\libresocsim_interface1_bus_we[0:0] - update \libresocsim_sdmem2block_dma_sink_ready $0\libresocsim_sdmem2block_dma_sink_ready[0:0] - update \libresocsim_sdmem2block_dma_source_valid $0\libresocsim_sdmem2block_dma_source_valid[0:0] - update \libresocsim_sdmem2block_dma_source_last $0\libresocsim_sdmem2block_dma_source_last[0:0] - update \libresocsim_sdmem2block_dma_source_payload_data $0\libresocsim_sdmem2block_dma_source_payload_data[31:0] - update \builder_sdmem2blockdma_fsm_next_state $0\builder_sdmem2blockdma_fsm_next_state[0:0] - update \libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] - update \libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - end - attribute \src "ls180.v:5250.1-5286.4" - process $proc$ls180.v:5250$989 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 - assign $0\libresocsim_sdmem2block_dma_done_status[0:0] 1'0 - assign $0\libresocsim_sdmem2block_dma_sink_valid[0:0] 1'0 - assign $0\libresocsim_sdmem2block_dma_sink_last[0:0] 1'0 - assign $0\libresocsim_sdmem2block_dma_sink_payload_address[31:0] 0 - assign { } { } - assign $0\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:5259.2-5285.9" - switch \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\libresocsim_sdmem2block_dma_sink_valid[0:0] 1'1 - assign $0\libresocsim_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5262$991_Y - assign $0\libresocsim_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5263$992_Y - attribute \src "ls180.v:5264.4-5275.7" - switch \libresocsim_sdmem2block_dma_sink_ready - attribute \src "ls180.v:5264.8-5264.46" - case 1'1 - assign $0\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5265$993_Y - assign $0\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5267.5-5274.8" - switch \libresocsim_sdmem2block_dma_sink_last - attribute \src "ls180.v:5267.9-5267.46" - case 1'1 - attribute \src "ls180.v:5268.6-5273.9" - switch \libresocsim_sdmem2block_dma_loop_storage - attribute \src "ls180.v:5268.10-5268.50" - case 1'1 - assign $0\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - assign $0\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5271.10-5271.14" - case - assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10 - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\libresocsim_sdmem2block_dma_done_status[0:0] 1'1 - attribute \src "ls180.v:0.0-0.0" - case - assign $0\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - assign $0\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'01 - end - sync always - update \libresocsim_sdmem2block_dma_sink_valid $0\libresocsim_sdmem2block_dma_sink_valid[0:0] - update \libresocsim_sdmem2block_dma_sink_last $0\libresocsim_sdmem2block_dma_sink_last[0:0] - update \libresocsim_sdmem2block_dma_sink_payload_address $0\libresocsim_sdmem2block_dma_sink_payload_address[31:0] - update \libresocsim_sdmem2block_dma_done_status $0\libresocsim_sdmem2block_dma_done_status[0:0] - update \builder_sdmem2blockdma_resetinserter_next_state $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] - update \libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - update \libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - end - attribute \src "ls180.v:5298.1-5314.4" - process $proc$ls180.v:5298$999 - assign { } { } - assign $0\libresocsim_sdmem2block_converter_source_payload_data[7:0] 8'00000000 - attribute \src "ls180.v:5300.2-5313.9" - switch \libresocsim_sdmem2block_converter_mux - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\libresocsim_sdmem2block_converter_source_payload_data[7:0] \libresocsim_sdmem2block_converter_sink_payload_data [31:24] - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\libresocsim_sdmem2block_converter_source_payload_data[7:0] \libresocsim_sdmem2block_converter_sink_payload_data [23:16] - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\libresocsim_sdmem2block_converter_source_payload_data[7:0] \libresocsim_sdmem2block_converter_sink_payload_data [15:8] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\libresocsim_sdmem2block_converter_source_payload_data[7:0] \libresocsim_sdmem2block_converter_sink_payload_data [7:0] - end - sync always - update \libresocsim_sdmem2block_converter_source_payload_data $0\libresocsim_sdmem2block_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:5328.1-5335.4" - process $proc$ls180.v:5328$1000 - assign { } { } - assign $0\libresocsim_sdmem2block_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5330.2-5334.5" - switch \libresocsim_sdmem2block_fifo_replace - attribute \src "ls180.v:5330.6-5330.42" - case 1'1 - assign $0\libresocsim_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5331$1001_Y - attribute \src "ls180.v:5332.6-5332.10" - case - assign $0\libresocsim_sdmem2block_fifo_wrport_adr[4:0] \libresocsim_sdmem2block_fifo_produce - end - sync always - update \libresocsim_sdmem2block_fifo_wrport_adr $0\libresocsim_sdmem2block_fifo_wrport_adr[4:0] - end - attribute \src "ls180.v:535.5-535.59" - process $proc$ls180.v:535$2747 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:5353.1-5401.4" - process $proc$ls180.v:5353$1011 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\libresocsim_clk_enable[0:0] 1'0 - assign $0\libresocsim_cs_enable[0:0] 1'0 - assign { } { } - assign $0\libresocsim_count_spimaster1_next_value[2:0] 3'000 - assign $0\libresocsim_mosi_latch[0:0] 1'0 - assign $0\libresocsim_done0[0:0] 1'0 - assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'0 - assign $0\libresocsim_miso_latch[0:0] 1'0 - assign $0\libresocsim_irq[0:0] 1'0 - assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state - attribute \src "ls180.v:5364.2-5400.9" - switch \builder_spimaster1_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\libresocsim_count_spimaster1_next_value[2:0] 3'000 - assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5368.4-5371.7" - switch \libresocsim_clk_fall - attribute \src "ls180.v:5368.8-5368.28" - case 1'1 - assign $0\libresocsim_cs_enable[0:0] 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'10 - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\libresocsim_clk_enable[0:0] 1'1 - assign $0\libresocsim_cs_enable[0:0] 1'1 - attribute \src "ls180.v:5376.4-5382.7" - switch \libresocsim_clk_fall - attribute \src "ls180.v:5376.8-5376.28" - case 1'1 - assign $0\libresocsim_count_spimaster1_next_value[2:0] $add$ls180.v:5377$1012_Y - assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5379.5-5381.8" - switch $eq$ls180.v:5379$1014_Y - attribute \src "ls180.v:5379.9-5379.60" - case 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'11 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\libresocsim_cs_enable[0:0] 1'1 - attribute \src "ls180.v:5386.4-5390.7" - switch \libresocsim_clk_rise - attribute \src "ls180.v:5386.8-5386.28" - case 1'1 - assign $0\libresocsim_miso_latch[0:0] 1'1 - assign $0\libresocsim_irq[0:0] 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'00 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\libresocsim_done0[0:0] 1'1 - attribute \src "ls180.v:5394.4-5398.7" - switch \libresocsim_start0 - attribute \src "ls180.v:5394.8-5394.26" - case 1'1 - assign $0\libresocsim_done0[0:0] 1'0 - assign $0\libresocsim_mosi_latch[0:0] 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'01 - case - end - end - sync always - update \libresocsim_done0 $0\libresocsim_done0[0:0] - update \libresocsim_irq $0\libresocsim_irq[0:0] - update \libresocsim_clk_enable $0\libresocsim_clk_enable[0:0] - update \libresocsim_cs_enable $0\libresocsim_cs_enable[0:0] - update \libresocsim_mosi_latch $0\libresocsim_mosi_latch[0:0] - update \libresocsim_miso_latch $0\libresocsim_miso_latch[0:0] - update \builder_spimaster1_next_state $0\builder_spimaster1_next_state[1:0] - update \libresocsim_count_spimaster1_next_value $0\libresocsim_count_spimaster1_next_value[2:0] - update \libresocsim_count_spimaster1_next_value_ce $0\libresocsim_count_spimaster1_next_value_ce[0:0] - end - attribute \src "ls180.v:537.5-537.59" - process $proc$ls180.v:537$2748 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:538.5-538.58" - process $proc$ls180.v:538$2749 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:539.5-539.64" - process $proc$ls180.v:539$2750 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:54.5-54.46" - process $proc$ls180.v:54$2570 - assign { } { } - assign $0\main_libresocsim_libresoc_dbus_err[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_dbus_err $0\main_libresocsim_libresoc_dbus_err[0:0] - sync init - end - attribute \src "ls180.v:540.12-540.74" - process $proc$ls180.v:540$2751 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:5402.1-5438.4" - process $proc$ls180.v:5402$1015 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 - assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 - assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 - assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 - assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 - assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 - assign { } { } - assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 - assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 - assign $0\builder_next_state[1:0] \builder_state - attribute \src "ls180.v:5413.2-5437.9" - switch \builder_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 - assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 - assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 - assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 - assign $0\builder_next_state[1:0] 2'10 - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_libresocsim_wishbone_ack[0:0] 1'1 - assign $0\builder_libresocsim_wishbone_dat_r[31:0] { 24'000000000000000000000000 \builder_libresocsim_dat_r } - assign $0\builder_next_state[1:0] 2'00 - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0] - assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5429.4-5435.7" - switch $and$ls180.v:5429$1016_Y - attribute \src "ls180.v:5429.8-5429.77" - case 1'1 - assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0] - assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 - assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5432$1018_Y - assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 - assign $0\builder_next_state[1:0] 2'01 - case - end - end - sync always - update \builder_libresocsim_wishbone_dat_r $0\builder_libresocsim_wishbone_dat_r[31:0] - update \builder_libresocsim_wishbone_ack $0\builder_libresocsim_wishbone_ack[0:0] - update \builder_next_state $0\builder_next_state[1:0] - update \builder_libresocsim_dat_w_next_value0 $0\builder_libresocsim_dat_w_next_value0[7:0] - update \builder_libresocsim_dat_w_next_value_ce0 $0\builder_libresocsim_dat_w_next_value_ce0[0:0] - update \builder_libresocsim_adr_next_value1 $0\builder_libresocsim_adr_next_value1[13:0] - update \builder_libresocsim_adr_next_value_ce1 $0\builder_libresocsim_adr_next_value_ce1[0:0] - update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0] - update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0] - end - attribute \src "ls180.v:541.12-541.47" - process $proc$ls180.v:541$2752 - assign { } { } - assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] - end - attribute \src "ls180.v:542.5-542.46" - process $proc$ls180.v:542$2753 - assign { } { } - assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] - end - attribute \src "ls180.v:544.5-544.44" - process $proc$ls180.v:544$2754 - assign { } { } - assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] - end - attribute \src "ls180.v:545.5-545.45" - process $proc$ls180.v:545$2755 - assign { } { } - assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] - end - attribute \src "ls180.v:546.5-546.54" - process $proc$ls180.v:546$2756 - assign { } { } - assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:5460.1-5467.4" - process $proc$ls180.v:5460$1035 - assign { } { } - assign { } { } - assign $0\builder_slave_sel[4:0] [0] $eq$ls180.v:5462$1036_Y - assign $0\builder_slave_sel[4:0] [1] $eq$ls180.v:5463$1037_Y - assign $0\builder_slave_sel[4:0] [2] $eq$ls180.v:5464$1038_Y - assign $0\builder_slave_sel[4:0] [3] $eq$ls180.v:5465$1039_Y - assign $0\builder_slave_sel[4:0] [4] $eq$ls180.v:5466$1040_Y - sync always - update \builder_slave_sel $0\builder_slave_sel[4:0] - end - attribute \src "ls180.v:548.32-548.76" - process $proc$ls180.v:548$2757 - assign { } { } - assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] - end - attribute \src "ls180.v:549.11-549.55" - process $proc$ls180.v:549$2758 - assign { } { } - assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] - end - attribute \src "ls180.v:551.32-551.75" - process $proc$ls180.v:551$2759 - assign { } { } - assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:5510.1-5521.4" - process $proc$ls180.v:5510$1053 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\builder_error[0:0] 1'0 - assign $0\builder_shared_ack[0:0] $or$ls180.v:5514$1057_Y - assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5515$1066_Y - attribute \src "ls180.v:5516.2-5520.5" - switch \builder_done - attribute \src "ls180.v:5516.6-5516.18" - case 1'1 - assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111 - assign $0\builder_shared_ack[0:0] 1'1 - assign $0\builder_error[0:0] 1'1 - case - end - sync always - update \builder_shared_dat_r $0\builder_shared_dat_r[31:0] - update \builder_shared_ack $0\builder_shared_ack[0:0] - update \builder_error $0\builder_error[0:0] - end - attribute \src "ls180.v:553.32-553.76" - process $proc$ls180.v:553$2760 - assign { } { } - assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] - sync init - end - attribute \src "ls180.v:559.5-559.51" - process $proc$ls180.v:559$2761 - assign { } { } - assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] - end - attribute \src "ls180.v:560.5-560.51" - process $proc$ls180.v:560$2762 - assign { } { } - assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] - end - attribute \src "ls180.v:562.5-562.47" - process $proc$ls180.v:562$2763 - assign { } { } - assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] - end - attribute \src "ls180.v:563.5-563.45" - process $proc$ls180.v:563$2764 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] - end - attribute \src "ls180.v:564.5-564.45" - process $proc$ls180.v:564$2765 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] - end - attribute \src "ls180.v:565.12-565.57" - process $proc$ls180.v:565$2766 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] - end - attribute \src "ls180.v:567.5-567.51" - process $proc$ls180.v:567$2767 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:568.5-568.51" - process $proc$ls180.v:568$2768 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:569.5-569.50" - process $proc$ls180.v:569$2769 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] - end - attribute \src "ls180.v:570.5-570.54" - process $proc$ls180.v:570$2770 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:571.5-571.55" - process $proc$ls180.v:571$2771 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:572.5-572.56" - process $proc$ls180.v:572$2772 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:573.5-573.50" - process $proc$ls180.v:573$2773 - assign { } { } - assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] - end - attribute \src "ls180.v:576.5-576.67" - process $proc$ls180.v:576$2774 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] - sync init - end - attribute \src "ls180.v:577.5-577.66" - process $proc$ls180.v:577$2775 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] - sync init - end - attribute \src "ls180.v:592.11-592.68" - process $proc$ls180.v:592$2776 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:593.5-593.64" - process $proc$ls180.v:593$2777 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:5933.1-5938.4" - process $proc$ls180.v:5933$1770 - assign { } { } - assign $0\main_start1[0:0] 1'0 - attribute \src "ls180.v:5935.2-5937.5" - switch \main_control_re - attribute \src "ls180.v:5935.6-5935.21" - case 1'1 - assign $0\main_start1[0:0] \main_control_storage [0] - case - end - sync always - update \main_start1 $0\main_start1[0:0] - end - attribute \src "ls180.v:594.11-594.70" - process $proc$ls180.v:594$2778 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:595.11-595.70" - process $proc$ls180.v:595$2779 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - end - attribute \src "ls180.v:596.11-596.73" - process $proc$ls180.v:596$2780 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:5979.1-5984.4" - process $proc$ls180.v:5979$1835 - assign { } { } - assign $0\libresocsim_start1[0:0] 1'0 - attribute \src "ls180.v:5981.2-5983.5" - switch \libresocsim_control_re - attribute \src "ls180.v:5981.6-5981.28" - case 1'1 - assign $0\libresocsim_start1[0:0] \libresocsim_control_storage [0] - case - end - sync always - update \libresocsim_start1 $0\libresocsim_start1[0:0] - end - attribute \src "ls180.v:61.5-61.46" - process $proc$ls180.v:61$2571 - assign { } { } - assign $1\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_ibus_ack $1\main_libresocsim_libresoc_ibus_ack[0:0] - end - attribute \src "ls180.v:6162.1-6178.4" - process $proc$ls180.v:6162$2054 - assign { } { } - assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6164.2-6177.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [0] - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [1] - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [2] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [3] - end - sync always - update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0] - end - attribute \src "ls180.v:617.5-617.59" - process $proc$ls180.v:617$2781 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:6179.1-6195.4" - process $proc$ls180.v:6179$2055 - assign { } { } - assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:6181.2-6194.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine0_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine1_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine2_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine3_cmd_payload_a - end - sync always - update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0] - end - attribute \src "ls180.v:619.5-619.59" - process $proc$ls180.v:619$2782 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:6196.1-6212.4" - process $proc$ls180.v:6196$2056 - assign { } { } - assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00 - attribute \src "ls180.v:6198.2-6211.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine0_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine1_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine2_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine3_cmd_payload_ba - end - sync always - update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0] - end - attribute \src "ls180.v:620.5-620.58" - process $proc$ls180.v:620$2783 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:621.5-621.64" - process $proc$ls180.v:621$2784 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:6213.1-6229.4" - process $proc$ls180.v:6213$2057 - assign { } { } - assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:6215.2-6228.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_is_read - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_is_read - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_is_read - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_is_read - end - sync always - update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0] - end - attribute \src "ls180.v:622.12-622.74" - process $proc$ls180.v:622$2785 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:623.12-623.47" - process $proc$ls180.v:623$2786 - assign { } { } - assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] - end - attribute \src "ls180.v:6230.1-6246.4" - process $proc$ls180.v:6230$2058 - assign { } { } - assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:6232.2-6245.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_is_write - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_is_write - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_is_write - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_is_write - end - sync always - update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0] - end - attribute \src "ls180.v:624.5-624.46" - process $proc$ls180.v:624$2787 - assign { } { } - assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] - end - attribute \src "ls180.v:6247.1-6263.4" - process $proc$ls180.v:6247$2059 - assign { } { } - assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:6249.2-6262.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd - end - sync always - update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0] - end - attribute \src "ls180.v:626.5-626.44" - process $proc$ls180.v:626$2788 - assign { } { } - assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] - end - attribute \src "ls180.v:6264.1-6280.4" - process $proc$ls180.v:6264$2060 - assign { } { } - assign $0\builder_comb_t_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6266.2-6279.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine0_cmd_payload_cas - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine1_cmd_payload_cas - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine2_cmd_payload_cas - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine3_cmd_payload_cas - end - sync always - update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0] - end - attribute \src "ls180.v:627.5-627.45" - process $proc$ls180.v:627$2789 - assign { } { } - assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] - end - attribute \src "ls180.v:628.5-628.54" - process $proc$ls180.v:628$2790 - assign { } { } - assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:6281.1-6297.4" - process $proc$ls180.v:6281$2061 - assign { } { } - assign $0\builder_comb_t_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:6283.2-6296.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine0_cmd_payload_ras - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine1_cmd_payload_ras - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine2_cmd_payload_ras - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine3_cmd_payload_ras - end - sync always - update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0] - end - attribute \src "ls180.v:6298.1-6314.4" - process $proc$ls180.v:6298$2062 - assign { } { } - assign $0\builder_comb_t_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:6300.2-6313.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine0_cmd_payload_we - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine1_cmd_payload_we - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine2_cmd_payload_we - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine3_cmd_payload_we - end - sync always - update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0] - end - attribute \src "ls180.v:630.32-630.76" - process $proc$ls180.v:630$2791 - assign { } { } - assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] - end - attribute \src "ls180.v:631.11-631.55" - process $proc$ls180.v:631$2792 - assign { } { } - assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] - end - attribute \src "ls180.v:6315.1-6331.4" - process $proc$ls180.v:6315$2063 - assign { } { } - assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:6317.2-6330.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [0] - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [1] - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [2] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [3] - end - sync always - update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0] - end - attribute \src "ls180.v:633.32-633.75" - process $proc$ls180.v:633$2793 - assign { } { } - assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:6332.1-6348.4" - process $proc$ls180.v:6332$2064 - assign { } { } - assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 - attribute \src "ls180.v:6334.2-6347.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine0_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine1_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine2_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine3_cmd_payload_a - end - sync always - update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0] - end - attribute \src "ls180.v:6349.1-6365.4" - process $proc$ls180.v:6349$2065 - assign { } { } - assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00 - attribute \src "ls180.v:6351.2-6364.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine0_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine1_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine2_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine3_cmd_payload_ba - end - sync always - update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0] - end - attribute \src "ls180.v:635.32-635.76" - process $proc$ls180.v:635$2794 - assign { } { } - assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] - sync init - end - attribute \src "ls180.v:6366.1-6382.4" - process $proc$ls180.v:6366$2066 - assign { } { } - assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0 - attribute \src "ls180.v:6368.2-6381.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine0_cmd_payload_is_read - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine1_cmd_payload_is_read - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine2_cmd_payload_is_read - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine3_cmd_payload_is_read - end - sync always - update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0] - end - attribute \src "ls180.v:6383.1-6399.4" - process $proc$ls180.v:6383$2067 - assign { } { } - assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0 - attribute \src "ls180.v:6385.2-6398.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine0_cmd_payload_is_write - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine1_cmd_payload_is_write - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine2_cmd_payload_is_write - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine3_cmd_payload_is_write - end - sync always - update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0] - end - attribute \src "ls180.v:6400.1-6416.4" - process $proc$ls180.v:6400$2068 - assign { } { } - assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0 - attribute \src "ls180.v:6402.2-6415.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd - end - sync always - update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0] - end - attribute \src "ls180.v:641.5-641.51" - process $proc$ls180.v:641$2795 - assign { } { } - assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] - end - attribute \src "ls180.v:6417.1-6433.4" - process $proc$ls180.v:6417$2069 - assign { } { } - assign $0\builder_comb_t_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:6419.2-6432.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_cas - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_cas - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_cas - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_cas - end - sync always - update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0] - end - attribute \src "ls180.v:642.5-642.51" - process $proc$ls180.v:642$2796 - assign { } { } - assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] - end - attribute \src "ls180.v:6434.1-6450.4" - process $proc$ls180.v:6434$2070 - assign { } { } - assign $0\builder_comb_t_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:6436.2-6449.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_ras - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_ras - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_ras - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_ras - end - sync always - update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0] - end - attribute \src "ls180.v:644.5-644.47" - process $proc$ls180.v:644$2797 - assign { } { } - assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] - end - attribute \src "ls180.v:645.5-645.45" - process $proc$ls180.v:645$2798 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] - end - attribute \src "ls180.v:6451.1-6467.4" - process $proc$ls180.v:6451$2071 - assign { } { } - assign $0\builder_comb_t_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:6453.2-6466.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_we - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_we - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_we - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_we - end - sync always - update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0] - end - attribute \src "ls180.v:646.5-646.45" - process $proc$ls180.v:646$2799 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] - end - attribute \src "ls180.v:6468.1-6475.4" - process $proc$ls180.v:6468$2072 - assign { } { } - assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6470.2-6474.9" - switch \builder_roundrobin0_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed12[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } - end - sync always - update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0] - end - attribute \src "ls180.v:647.12-647.57" - process $proc$ls180.v:647$2800 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] - end - attribute \src "ls180.v:6476.1-6483.4" - process $proc$ls180.v:6476$2073 - assign { } { } - assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0 - attribute \src "ls180.v:6478.2-6482.9" - switch \builder_roundrobin0_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed13[0:0] \main_port_cmd_payload_we - end - sync always - update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0] - end - attribute \src "ls180.v:6484.1-6491.4" - process $proc$ls180.v:6484$2074 - assign { } { } - assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0 - attribute \src "ls180.v:6486.2-6490.9" - switch \builder_roundrobin0_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6488$2087_Y - end - sync always - update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0] - end - attribute \src "ls180.v:649.5-649.51" - process $proc$ls180.v:649$2801 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:6492.1-6499.4" - process $proc$ls180.v:6492$2088 - assign { } { } - assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6494.2-6498.9" - switch \builder_roundrobin1_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed15[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } - end - sync always - update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0] - end - attribute \src "ls180.v:65.5-65.46" - process $proc$ls180.v:65$2572 - assign { } { } - assign $0\main_libresocsim_libresoc_ibus_err[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_ibus_err $0\main_libresocsim_libresoc_ibus_err[0:0] - sync init - end - attribute \src "ls180.v:650.5-650.51" - process $proc$ls180.v:650$2802 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:6500.1-6507.4" - process $proc$ls180.v:6500$2089 - assign { } { } - assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0 - attribute \src "ls180.v:6502.2-6506.9" - switch \builder_roundrobin1_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed16[0:0] \main_port_cmd_payload_we - end - sync always - update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0] - end - attribute \src "ls180.v:6508.1-6515.4" - process $proc$ls180.v:6508$2090 - assign { } { } - assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0 - attribute \src "ls180.v:6510.2-6514.9" - switch \builder_roundrobin1_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:6512$2103_Y - end - sync always - update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0] - end - attribute \src "ls180.v:651.5-651.50" - process $proc$ls180.v:651$2803 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0] - end - attribute \src "ls180.v:6516.1-6523.4" - process $proc$ls180.v:6516$2104 - assign { } { } - assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6518.2-6522.9" - switch \builder_roundrobin2_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed18[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } - end - sync always - update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0] - end - attribute \src "ls180.v:652.5-652.54" - process $proc$ls180.v:652$2804 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:6524.1-6531.4" - process $proc$ls180.v:6524$2105 - assign { } { } - assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0 - attribute \src "ls180.v:6526.2-6530.9" - switch \builder_roundrobin2_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed19[0:0] \main_port_cmd_payload_we - end - sync always - update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0] - end - attribute \src "ls180.v:653.5-653.55" - process $proc$ls180.v:653$2805 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:6532.1-6539.4" - process $proc$ls180.v:6532$2106 - assign { } { } - assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0 - attribute \src "ls180.v:6534.2-6538.9" - switch \builder_roundrobin2_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:6536$2119_Y - end - sync always - update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0] - end - attribute \src "ls180.v:654.5-654.56" - process $proc$ls180.v:654$2806 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:6540.1-6547.4" - process $proc$ls180.v:6540$2120 - assign { } { } - assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6542.2-6546.9" - switch \builder_roundrobin3_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed21[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } - end - sync always - update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0] - end - attribute \src "ls180.v:6548.1-6555.4" - process $proc$ls180.v:6548$2121 - assign { } { } - assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0 - attribute \src "ls180.v:6550.2-6554.9" - switch \builder_roundrobin3_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed22[0:0] \main_port_cmd_payload_we - end - sync always - update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0] - end - attribute \src "ls180.v:655.5-655.50" - process $proc$ls180.v:655$2807 - assign { } { } - assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] - end - attribute \src "ls180.v:6556.1-6563.4" - process $proc$ls180.v:6556$2122 - assign { } { } - assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0 - attribute \src "ls180.v:6558.2-6562.9" - switch \builder_roundrobin3_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:6560$2135_Y - end - sync always - update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0] - end - attribute \src "ls180.v:6564.1-6580.4" - process $proc$ls180.v:6564$2136 - assign { } { } - assign $0\builder_comb_rhs_array_muxed24[31:0] 0 - attribute \src "ls180.v:6566.2-6579.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface0_converted_interface_adr } - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface1_converted_interface_adr } - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed24[31:0] \libresocsim_interface0_bus_adr - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed24[31:0] \libresocsim_interface1_bus_adr - end - sync always - update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0] - end - attribute \src "ls180.v:658.5-658.67" - process $proc$ls180.v:658$2808 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] - sync init - end - attribute \src "ls180.v:6581.1-6597.4" - process $proc$ls180.v:6581$2137 - assign { } { } - assign $0\builder_comb_rhs_array_muxed25[31:0] 0 - attribute \src "ls180.v:6583.2-6596.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface0_converted_interface_dat_w - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface1_converted_interface_dat_w - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed25[31:0] \libresocsim_interface0_bus_dat_w - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed25[31:0] \libresocsim_interface1_bus_dat_w - end - sync always - update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[31:0] - end - attribute \src "ls180.v:659.5-659.66" - process $proc$ls180.v:659$2809 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] - sync init - end - attribute \src "ls180.v:6598.1-6614.4" - process $proc$ls180.v:6598$2138 - assign { } { } - assign $0\builder_comb_rhs_array_muxed26[3:0] 4'0000 - attribute \src "ls180.v:6600.2-6613.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface0_converted_interface_sel - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface1_converted_interface_sel - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed26[3:0] \libresocsim_interface0_bus_sel - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed26[3:0] \libresocsim_interface1_bus_sel - end - sync always - update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[3:0] - end - attribute \src "ls180.v:6615.1-6631.4" - process $proc$ls180.v:6615$2139 - assign { } { } - assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0 - attribute \src "ls180.v:6617.2-6630.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface0_converted_interface_cyc - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface1_converted_interface_cyc - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed27[0:0] \libresocsim_interface0_bus_cyc - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed27[0:0] \libresocsim_interface1_bus_cyc - end - sync always - update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0] - end - attribute \src "ls180.v:6632.1-6648.4" - process $proc$ls180.v:6632$2140 - assign { } { } - assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0 - attribute \src "ls180.v:6634.2-6647.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface0_converted_interface_stb - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface1_converted_interface_stb - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed28[0:0] \libresocsim_interface0_bus_stb - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed28[0:0] \libresocsim_interface1_bus_stb - end - sync always - update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0] - end - attribute \src "ls180.v:6649.1-6665.4" - process $proc$ls180.v:6649$2141 - assign { } { } - assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0 - attribute \src "ls180.v:6651.2-6664.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface0_converted_interface_we - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface1_converted_interface_we - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed29[0:0] \libresocsim_interface0_bus_we - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed29[0:0] \libresocsim_interface1_bus_we - end - sync always - update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0] - end - attribute \src "ls180.v:6666.1-6682.4" - process $proc$ls180.v:6666$2142 - assign { } { } - assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000 - attribute \src "ls180.v:6668.2-6681.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface0_converted_interface_cti - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface1_converted_interface_cti - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed30[2:0] \libresocsim_interface0_bus_cti - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed30[2:0] \libresocsim_interface1_bus_cti - end - sync always - update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0] - end - attribute \src "ls180.v:6683.1-6699.4" - process $proc$ls180.v:6683$2143 - assign { } { } - assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00 - attribute \src "ls180.v:6685.2-6698.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface0_converted_interface_bte - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface1_converted_interface_bte - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed31[1:0] \libresocsim_interface0_bus_bte - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed31[1:0] \libresocsim_interface1_bus_bte - end - sync always - update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0] - end - attribute \src "ls180.v:6700.1-6716.4" - process $proc$ls180.v:6700$2144 - assign { } { } - assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00 - attribute \src "ls180.v:6702.2-6715.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_nop_ba - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_cmd_payload_ba - end - sync always - update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0] - end - attribute \src "ls180.v:6717.1-6733.4" - process $proc$ls180.v:6717$2145 - assign { } { } - assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:6719.2-6732.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_nop_a - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_cmd_payload_a - end - sync always - update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0] - end - attribute \src "ls180.v:6734.1-6750.4" - process $proc$ls180.v:6734$2146 - assign { } { } - assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:6736.2-6749.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:6741$2148_Y - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:6744$2150_Y - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:6747$2152_Y - end - sync always - update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0] - end - attribute \src "ls180.v:674.11-674.68" - process $proc$ls180.v:674$2810 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:675.5-675.64" - process $proc$ls180.v:675$2811 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:6751.1-6767.4" - process $proc$ls180.v:6751$2153 - assign { } { } - assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:6753.2-6766.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:6758$2155_Y - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:6761$2157_Y - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:6764$2159_Y - end - sync always - update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0] - end - attribute \src "ls180.v:676.11-676.70" - process $proc$ls180.v:676$2812 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:6768.1-6784.4" - process $proc$ls180.v:6768$2160 - assign { } { } - assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:6770.2-6783.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:6775$2162_Y - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:6778$2164_Y - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:6781$2166_Y - end - sync always - update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0] - end - attribute \src "ls180.v:677.11-677.70" - process $proc$ls180.v:677$2813 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - end - attribute \src "ls180.v:678.11-678.73" - process $proc$ls180.v:678$2814 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:6785.1-6801.4" - process $proc$ls180.v:6785$2167 - assign { } { } - assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:6787.2-6800.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:6792$2169_Y - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:6795$2171_Y - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:6798$2173_Y - end - sync always - update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0] - end - attribute \src "ls180.v:6802.1-6818.4" - process $proc$ls180.v:6802$2174 - assign { } { } - assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:6804.2-6817.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:6809$2176_Y - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:6812$2178_Y - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:6815$2180_Y - end - sync always - update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0] - end - attribute \src "ls180.v:6819.1-6847.4" - process $proc$ls180.v:6819$2181 - assign { } { } - assign $0\builder_sync_f_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6821.2-6846.9" - switch \main_mosi_sel - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_sync_f_array_muxed0[0:0] \main_mosi_data [0] - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_sync_f_array_muxed0[0:0] \main_mosi_data [1] - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_sync_f_array_muxed0[0:0] \main_mosi_data [2] - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_sync_f_array_muxed0[0:0] \main_mosi_data [3] - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_sync_f_array_muxed0[0:0] \main_mosi_data [4] - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_sync_f_array_muxed0[0:0] \main_mosi_data [5] - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_sync_f_array_muxed0[0:0] \main_mosi_data [6] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_f_array_muxed0[0:0] \main_mosi_data [7] - end - sync always - update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0] - end - attribute \src "ls180.v:6848.1-6876.4" - process $proc$ls180.v:6848$2182 - assign { } { } - assign $0\builder_sync_f_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:6850.2-6875.9" - switch \libresocsim_mosi_sel - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [0] - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [1] - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [2] - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [3] - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [4] - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [5] - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [6] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [7] - end - sync always - update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0] - end - attribute \src "ls180.v:6965.1-6967.4" - process $proc$ls180.v:6965$2183 - assign { } { } - assign $0\main_int_rst[0:0] 1'0 - sync posedge \por_clk - update \main_int_rst $0\main_int_rst[0:0] - end - attribute \src "ls180.v:6969.1-7054.4" - process $proc$ls180.v:6969$2184 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\sdram_a[12:0] [0] \main_dfi_p0_address [0] - assign $0\sdram_a[12:0] [1] \main_dfi_p0_address [1] - assign $0\sdram_a[12:0] [2] \main_dfi_p0_address [2] - assign $0\sdram_a[12:0] [3] \main_dfi_p0_address [3] - assign $0\sdram_a[12:0] [4] \main_dfi_p0_address [4] - assign $0\sdram_a[12:0] [5] \main_dfi_p0_address [5] - assign $0\sdram_a[12:0] [6] \main_dfi_p0_address [6] - assign $0\sdram_a[12:0] [7] \main_dfi_p0_address [7] - assign $0\sdram_a[12:0] [8] \main_dfi_p0_address [8] - assign $0\sdram_a[12:0] [9] \main_dfi_p0_address [9] - assign $0\sdram_a[12:0] [10] \main_dfi_p0_address [10] - assign $0\sdram_a[12:0] [11] \main_dfi_p0_address [11] - assign $0\sdram_a[12:0] [12] \main_dfi_p0_address [12] - assign $0\sdram_ba[1:0] [0] \main_dfi_p0_bank [0] - assign $0\sdram_ba[1:0] [1] \main_dfi_p0_bank [1] - assign $0\sdram_cas_n[0:0] \main_dfi_p0_cas_n - assign $0\sdram_ras_n[0:0] \main_dfi_p0_ras_n - assign $0\sdram_we_n[0:0] \main_dfi_p0_we_n - assign $0\sdram_cke[0:0] \main_dfi_p0_cke - assign $0\sdram_cs_n[0:0] \main_dfi_p0_cs_n - assign $0\builder_inferedsdrtristate0_oe[0:0] \main_dfi_p0_wrdata_en - assign $0\builder_inferedsdrtristate1_oe[0:0] \main_dfi_p0_wrdata_en - assign $0\builder_inferedsdrtristate2_oe[0:0] \main_dfi_p0_wrdata_en - assign $0\builder_inferedsdrtristate3_oe[0:0] \main_dfi_p0_wrdata_en - assign $0\builder_inferedsdrtristate4_oe[0:0] \main_dfi_p0_wrdata_en - assign $0\builder_inferedsdrtristate5_oe[0:0] \main_dfi_p0_wrdata_en - assign $0\builder_inferedsdrtristate6_oe[0:0] \main_dfi_p0_wrdata_en - assign $0\builder_inferedsdrtristate7_oe[0:0] \main_dfi_p0_wrdata_en - assign $0\builder_inferedsdrtristate8_oe[0:0] \main_dfi_p0_wrdata_en - assign $0\builder_inferedsdrtristate9_oe[0:0] \main_dfi_p0_wrdata_en - assign $0\builder_inferedsdrtristate10_oe[0:0] \main_dfi_p0_wrdata_en - assign $0\builder_inferedsdrtristate11_oe[0:0] \main_dfi_p0_wrdata_en - assign $0\builder_inferedsdrtristate12_oe[0:0] \main_dfi_p0_wrdata_en - assign $0\builder_inferedsdrtristate13_oe[0:0] \main_dfi_p0_wrdata_en - assign $0\builder_inferedsdrtristate14_oe[0:0] \main_dfi_p0_wrdata_en - assign $0\builder_inferedsdrtristate15_oe[0:0] \main_dfi_p0_wrdata_en - assign $0\sdcard_clk[0:0] $and$ls180.v:7006$2186_Y - assign $0\builder_inferedsdrtristate16_oe[0:0] \libresocsim_sdpads_cmd_oe - assign $0\builder_inferedsdrtristate17_oe[0:0] \libresocsim_sdpads_data_oe - assign $0\builder_inferedsdrtristate18_oe[0:0] \libresocsim_sdpads_data_oe - assign $0\builder_inferedsdrtristate19_oe[0:0] \libresocsim_sdpads_data_oe - assign $0\builder_inferedsdrtristate20_oe[0:0] \libresocsim_sdpads_data_oe - assign $0\builder_inferedsdrtristate0__o[0:0] \main_dfi_p0_wrdata [0] - assign $0\main_dfi_p0_rddata[15:0] [0] \builder_inferedsdrtristate0__i - assign $0\builder_inferedsdrtristate1__o[0:0] \main_dfi_p0_wrdata [1] - assign $0\main_dfi_p0_rddata[15:0] [1] \builder_inferedsdrtristate1__i - assign $0\builder_inferedsdrtristate2__o[0:0] \main_dfi_p0_wrdata [2] - assign $0\main_dfi_p0_rddata[15:0] [2] \builder_inferedsdrtristate2__i - assign $0\builder_inferedsdrtristate3__o[0:0] \main_dfi_p0_wrdata [3] - assign $0\main_dfi_p0_rddata[15:0] [3] \builder_inferedsdrtristate3__i - assign $0\builder_inferedsdrtristate4__o[0:0] \main_dfi_p0_wrdata [4] - assign $0\main_dfi_p0_rddata[15:0] [4] \builder_inferedsdrtristate4__i - assign $0\builder_inferedsdrtristate5__o[0:0] \main_dfi_p0_wrdata [5] - assign $0\main_dfi_p0_rddata[15:0] [5] \builder_inferedsdrtristate5__i - assign $0\builder_inferedsdrtristate6__o[0:0] \main_dfi_p0_wrdata [6] - assign $0\main_dfi_p0_rddata[15:0] [6] \builder_inferedsdrtristate6__i - assign $0\builder_inferedsdrtristate7__o[0:0] \main_dfi_p0_wrdata [7] - assign $0\main_dfi_p0_rddata[15:0] [7] \builder_inferedsdrtristate7__i - assign $0\builder_inferedsdrtristate8__o[0:0] \main_dfi_p0_wrdata [8] - assign $0\main_dfi_p0_rddata[15:0] [8] \builder_inferedsdrtristate8__i - assign $0\builder_inferedsdrtristate9__o[0:0] \main_dfi_p0_wrdata [9] - assign $0\main_dfi_p0_rddata[15:0] [9] \builder_inferedsdrtristate9__i - assign $0\builder_inferedsdrtristate10__o[0:0] \main_dfi_p0_wrdata [10] - assign $0\main_dfi_p0_rddata[15:0] [10] \builder_inferedsdrtristate10__i - assign $0\builder_inferedsdrtristate11__o[0:0] \main_dfi_p0_wrdata [11] - assign $0\main_dfi_p0_rddata[15:0] [11] \builder_inferedsdrtristate11__i - assign $0\builder_inferedsdrtristate12__o[0:0] \main_dfi_p0_wrdata [12] - assign $0\main_dfi_p0_rddata[15:0] [12] \builder_inferedsdrtristate12__i - assign $0\builder_inferedsdrtristate13__o[0:0] \main_dfi_p0_wrdata [13] - assign $0\main_dfi_p0_rddata[15:0] [13] \builder_inferedsdrtristate13__i - assign $0\builder_inferedsdrtristate14__o[0:0] \main_dfi_p0_wrdata [14] - assign $0\main_dfi_p0_rddata[15:0] [14] \builder_inferedsdrtristate14__i - assign $0\builder_inferedsdrtristate15__o[0:0] \main_dfi_p0_wrdata [15] - assign $0\main_dfi_p0_rddata[15:0] [15] \builder_inferedsdrtristate15__i - assign $0\builder_inferedsdrtristate16__o[0:0] \libresocsim_sdpads_cmd_o - assign $0\libresocsim_sdpads_cmd_i[0:0] \builder_inferedsdrtristate16__i - assign $0\builder_inferedsdrtristate17__o[0:0] \libresocsim_sdpads_data_o [0] - assign $0\libresocsim_sdpads_data_i[3:0] [0] \builder_inferedsdrtristate17__i - assign $0\builder_inferedsdrtristate18__o[0:0] \libresocsim_sdpads_data_o [1] - assign $0\libresocsim_sdpads_data_i[3:0] [1] \builder_inferedsdrtristate18__i - assign $0\builder_inferedsdrtristate19__o[0:0] \libresocsim_sdpads_data_o [2] - assign $0\libresocsim_sdpads_data_i[3:0] [2] \builder_inferedsdrtristate19__i - assign $0\builder_inferedsdrtristate20__o[0:0] \libresocsim_sdpads_data_o [3] - assign $0\libresocsim_sdpads_data_i[3:0] [3] \builder_inferedsdrtristate20__i - sync posedge \sdrio_clk - update \sdram_a $0\sdram_a[12:0] - update \sdram_we_n $0\sdram_we_n[0:0] - update \sdram_ras_n $0\sdram_ras_n[0:0] - update \sdram_cas_n $0\sdram_cas_n[0:0] - update \sdram_cs_n $0\sdram_cs_n[0:0] - update \sdram_cke $0\sdram_cke[0:0] - update \sdram_ba $0\sdram_ba[1:0] - update \sdcard_clk $0\sdcard_clk[0:0] - update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0] - update \libresocsim_sdpads_cmd_i $0\libresocsim_sdpads_cmd_i[0:0] - update \libresocsim_sdpads_data_i $0\libresocsim_sdpads_data_i[3:0] - update \builder_inferedsdrtristate0__o $0\builder_inferedsdrtristate0__o[0:0] - update \builder_inferedsdrtristate0_oe $0\builder_inferedsdrtristate0_oe[0:0] - update \builder_inferedsdrtristate1__o $0\builder_inferedsdrtristate1__o[0:0] - update \builder_inferedsdrtristate1_oe $0\builder_inferedsdrtristate1_oe[0:0] - update \builder_inferedsdrtristate2__o $0\builder_inferedsdrtristate2__o[0:0] - update \builder_inferedsdrtristate2_oe $0\builder_inferedsdrtristate2_oe[0:0] - update \builder_inferedsdrtristate3__o $0\builder_inferedsdrtristate3__o[0:0] - update \builder_inferedsdrtristate3_oe $0\builder_inferedsdrtristate3_oe[0:0] - update \builder_inferedsdrtristate4__o $0\builder_inferedsdrtristate4__o[0:0] - update \builder_inferedsdrtristate4_oe $0\builder_inferedsdrtristate4_oe[0:0] - update \builder_inferedsdrtristate5__o $0\builder_inferedsdrtristate5__o[0:0] - update \builder_inferedsdrtristate5_oe $0\builder_inferedsdrtristate5_oe[0:0] - update \builder_inferedsdrtristate6__o $0\builder_inferedsdrtristate6__o[0:0] - update \builder_inferedsdrtristate6_oe $0\builder_inferedsdrtristate6_oe[0:0] - update \builder_inferedsdrtristate7__o $0\builder_inferedsdrtristate7__o[0:0] - update \builder_inferedsdrtristate7_oe $0\builder_inferedsdrtristate7_oe[0:0] - update \builder_inferedsdrtristate8__o $0\builder_inferedsdrtristate8__o[0:0] - update \builder_inferedsdrtristate8_oe $0\builder_inferedsdrtristate8_oe[0:0] - update \builder_inferedsdrtristate9__o $0\builder_inferedsdrtristate9__o[0:0] - update \builder_inferedsdrtristate9_oe $0\builder_inferedsdrtristate9_oe[0:0] - update \builder_inferedsdrtristate10__o $0\builder_inferedsdrtristate10__o[0:0] - update \builder_inferedsdrtristate10_oe $0\builder_inferedsdrtristate10_oe[0:0] - update \builder_inferedsdrtristate11__o $0\builder_inferedsdrtristate11__o[0:0] - update \builder_inferedsdrtristate11_oe $0\builder_inferedsdrtristate11_oe[0:0] - update \builder_inferedsdrtristate12__o $0\builder_inferedsdrtristate12__o[0:0] - update \builder_inferedsdrtristate12_oe $0\builder_inferedsdrtristate12_oe[0:0] - update \builder_inferedsdrtristate13__o $0\builder_inferedsdrtristate13__o[0:0] - update \builder_inferedsdrtristate13_oe $0\builder_inferedsdrtristate13_oe[0:0] - update \builder_inferedsdrtristate14__o $0\builder_inferedsdrtristate14__o[0:0] - update \builder_inferedsdrtristate14_oe $0\builder_inferedsdrtristate14_oe[0:0] - update \builder_inferedsdrtristate15__o $0\builder_inferedsdrtristate15__o[0:0] - update \builder_inferedsdrtristate15_oe $0\builder_inferedsdrtristate15_oe[0:0] - update \builder_inferedsdrtristate16__o $0\builder_inferedsdrtristate16__o[0:0] - update \builder_inferedsdrtristate16_oe $0\builder_inferedsdrtristate16_oe[0:0] - update \builder_inferedsdrtristate17__o $0\builder_inferedsdrtristate17__o[0:0] - update \builder_inferedsdrtristate17_oe $0\builder_inferedsdrtristate17_oe[0:0] - update \builder_inferedsdrtristate18__o $0\builder_inferedsdrtristate18__o[0:0] - update \builder_inferedsdrtristate18_oe $0\builder_inferedsdrtristate18_oe[0:0] - update \builder_inferedsdrtristate19__o $0\builder_inferedsdrtristate19__o[0:0] - update \builder_inferedsdrtristate19_oe $0\builder_inferedsdrtristate19_oe[0:0] - update \builder_inferedsdrtristate20__o $0\builder_inferedsdrtristate20__o[0:0] - update \builder_inferedsdrtristate20_oe $0\builder_inferedsdrtristate20_oe[0:0] - end - attribute \src "ls180.v:699.5-699.59" - process $proc$ls180.v:699$2815 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:701.5-701.59" - process $proc$ls180.v:701$2816 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:702.5-702.58" - process $proc$ls180.v:702$2817 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:703.5-703.64" - process $proc$ls180.v:703$2818 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:704.12-704.74" - process $proc$ls180.v:704$2819 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:705.12-705.47" - process $proc$ls180.v:705$2820 - assign { } { } - assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] - end - attribute \src "ls180.v:7056.1-9364.4" - process $proc$ls180.v:7056$2187 - assign $0\serial_tx[0:0] \serial_tx - assign $0\spi_master_clk[0:0] \spi_master_clk - assign $0\spi_master_mosi[0:0] \spi_master_mosi - assign { } { } - assign $0\spisdcard_clk[0:0] \spisdcard_clk - assign $0\spisdcard_mosi[0:0] \spisdcard_mosi - assign { } { } - assign $0\main_libresocsim_soccontroller_reset_storage[0:0] \main_libresocsim_soccontroller_reset_storage - assign { } { } - assign $0\main_libresocsim_soccontroller_scratch_storage[31:0] \main_libresocsim_soccontroller_scratch_storage - assign { } { } - assign $0\main_libresocsim_soccontroller_bus_errors[31:0] \main_libresocsim_soccontroller_bus_errors - assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter - assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_converter0_dat_r - assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter - assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_converter1_dat_r - assign { } { } - assign $0\main_libresocsim_storage[31:0] \main_libresocsim_storage - assign { } { } - assign { } { } - assign $0\main_libresocsim_uart_clk_txen[0:0] \main_libresocsim_uart_clk_txen - assign $0\main_libresocsim_phase_accumulator_tx[31:0] \main_libresocsim_phase_accumulator_tx - assign $0\main_libresocsim_tx_reg[7:0] \main_libresocsim_tx_reg - assign $0\main_libresocsim_tx_bitcount[3:0] \main_libresocsim_tx_bitcount - assign $0\main_libresocsim_tx_busy[0:0] \main_libresocsim_tx_busy - assign { } { } - assign $0\main_libresocsim_source_payload_data[7:0] \main_libresocsim_source_payload_data - assign $0\main_libresocsim_uart_clk_rxen[0:0] \main_libresocsim_uart_clk_rxen - assign $0\main_libresocsim_phase_accumulator_rx[31:0] \main_libresocsim_phase_accumulator_rx - assign { } { } - assign $0\main_libresocsim_rx_reg[7:0] \main_libresocsim_rx_reg - assign $0\main_libresocsim_rx_bitcount[3:0] \main_libresocsim_rx_bitcount - assign $0\main_libresocsim_rx_busy[0:0] \main_libresocsim_rx_busy - assign $0\main_libresocsim_uart_tx_pending[0:0] \main_libresocsim_uart_tx_pending - assign { } { } - assign $0\main_libresocsim_uart_rx_pending[0:0] \main_libresocsim_uart_rx_pending - assign { } { } - assign $0\main_libresocsim_uart_eventmanager_storage[1:0] \main_libresocsim_uart_eventmanager_storage - assign { } { } - assign $0\main_libresocsim_uart_tx_fifo_readable[0:0] \main_libresocsim_uart_tx_fifo_readable - assign $0\main_libresocsim_uart_tx_fifo_level0[4:0] \main_libresocsim_uart_tx_fifo_level0 - assign $0\main_libresocsim_uart_tx_fifo_produce[3:0] \main_libresocsim_uart_tx_fifo_produce - assign $0\main_libresocsim_uart_tx_fifo_consume[3:0] \main_libresocsim_uart_tx_fifo_consume - assign $0\main_libresocsim_uart_rx_fifo_readable[0:0] \main_libresocsim_uart_rx_fifo_readable - assign $0\main_libresocsim_uart_rx_fifo_level0[4:0] \main_libresocsim_uart_rx_fifo_level0 - assign $0\main_libresocsim_uart_rx_fifo_produce[3:0] \main_libresocsim_uart_rx_fifo_produce - assign $0\main_libresocsim_uart_rx_fifo_consume[3:0] \main_libresocsim_uart_rx_fifo_consume - assign $0\main_libresocsim_timer_load_storage[31:0] \main_libresocsim_timer_load_storage - assign { } { } - assign $0\main_libresocsim_timer_reload_storage[31:0] \main_libresocsim_timer_reload_storage - assign { } { } - assign $0\main_libresocsim_timer_en_storage[0:0] \main_libresocsim_timer_en_storage - assign { } { } - assign $0\main_libresocsim_timer_update_value_storage[0:0] \main_libresocsim_timer_update_value_storage - assign { } { } - assign $0\main_libresocsim_timer_value_status[31:0] \main_libresocsim_timer_value_status - assign $0\main_libresocsim_timer_zero_pending[0:0] \main_libresocsim_timer_zero_pending - assign { } { } - assign $0\main_libresocsim_timer_eventmanager_storage[0:0] \main_libresocsim_timer_eventmanager_storage - assign { } { } - assign $0\main_libresocsim_timer_value[31:0] \main_libresocsim_timer_value - assign { } { } - assign { } { } - assign $0\main_sdram_storage[3:0] \main_sdram_storage - assign { } { } - assign $0\main_sdram_command_storage[5:0] \main_sdram_command_storage - assign { } { } - assign $0\main_sdram_address_storage[12:0] \main_sdram_address_storage - assign { } { } - assign $0\main_sdram_baddress_storage[1:0] \main_sdram_baddress_storage - assign { } { } - assign $0\main_sdram_wrdata_storage[15:0] \main_sdram_wrdata_storage - assign { } { } - assign $0\main_sdram_status[15:0] \main_sdram_status - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_timer_count1[9:0] \main_sdram_timer_count1 - assign { } { } - assign $0\main_sdram_postponer_count[0:0] \main_sdram_postponer_count - assign { } { } - assign $0\main_sdram_sequencer_counter[3:0] \main_sdram_sequencer_counter - assign $0\main_sdram_sequencer_count[0:0] \main_sdram_sequencer_count - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_level - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_source_valid - assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_source_first - assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_source_last - assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_we - assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr - assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_row - assign $0\main_sdram_bankmachine0_row_opened[0:0] \main_sdram_bankmachine0_row_opened - assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] \main_sdram_bankmachine0_twtpcon_ready - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] \main_sdram_bankmachine0_twtpcon_count - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_level - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_source_valid - assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_source_first - assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_source_last - assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_we - assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr - assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_row - assign $0\main_sdram_bankmachine1_row_opened[0:0] \main_sdram_bankmachine1_row_opened - assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] \main_sdram_bankmachine1_twtpcon_ready - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] \main_sdram_bankmachine1_twtpcon_count - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_level - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_source_valid - assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_source_first - assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_source_last - assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_we - assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr - assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_row - assign $0\main_sdram_bankmachine2_row_opened[0:0] \main_sdram_bankmachine2_row_opened - assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] \main_sdram_bankmachine2_twtpcon_ready - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] \main_sdram_bankmachine2_twtpcon_count - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_level - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_source_valid - assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_source_first - assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_source_last - assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_we - assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr - assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_row - assign $0\main_sdram_bankmachine3_row_opened[0:0] \main_sdram_bankmachine3_row_opened - assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] \main_sdram_bankmachine3_twtpcon_ready - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] \main_sdram_bankmachine3_twtpcon_count - assign $0\main_sdram_choose_cmd_grant[1:0] \main_sdram_choose_cmd_grant - assign $0\main_sdram_choose_req_grant[1:0] \main_sdram_choose_req_grant - assign $0\main_sdram_tccdcon_ready[0:0] \main_sdram_tccdcon_ready - assign $0\main_sdram_tccdcon_count[0:0] \main_sdram_tccdcon_count - assign $0\main_sdram_twtrcon_ready[0:0] \main_sdram_twtrcon_ready - assign $0\main_sdram_twtrcon_count[2:0] \main_sdram_twtrcon_count - assign $0\main_sdram_time0[4:0] \main_sdram_time0 - assign $0\main_sdram_time1[3:0] \main_sdram_time1 - assign $0\main_converter_counter[0:0] \main_converter_counter - assign $0\main_converter_dat_r[31:0] \main_converter_dat_r - assign $0\main_cmd_consumed[0:0] \main_cmd_consumed - assign $0\main_wdata_consumed[0:0] \main_wdata_consumed - assign $0\main_miso[7:0] \main_miso - assign $0\main_control_storage[15:0] \main_control_storage - assign { } { } - assign $0\main_mosi_storage[7:0] \main_mosi_storage - assign { } { } - assign $0\main_cs_storage[0:0] \main_cs_storage - assign { } { } - assign $0\main_loopback_storage[0:0] \main_loopback_storage - assign { } { } - assign $0\main_count[2:0] \main_count - assign { } { } - assign $0\main_mosi_data[7:0] \main_mosi_data - assign $0\main_mosi_sel[2:0] \main_mosi_sel - assign $0\main_miso_data[7:0] \main_miso_data - assign $0\libresocsim_clocker_storage[8:0] \libresocsim_clocker_storage - assign { } { } - assign { } { } - assign $0\libresocsim_clocker_clks[8:0] \libresocsim_clocker_clks - assign { } { } - assign $0\libresocsim_init_count[7:0] \libresocsim_init_count - assign $0\libresocsim_cmdw_count[7:0] \libresocsim_cmdw_count - assign $0\libresocsim_cmdr_timeout[31:0] \libresocsim_cmdr_timeout - assign $0\libresocsim_cmdr_count[7:0] \libresocsim_cmdr_count - assign $0\libresocsim_cmdr_cmdr_run[0:0] \libresocsim_cmdr_cmdr_run - assign $0\libresocsim_cmdr_cmdr_converter_source_first[0:0] \libresocsim_cmdr_cmdr_converter_source_first - assign $0\libresocsim_cmdr_cmdr_converter_source_last[0:0] \libresocsim_cmdr_cmdr_converter_source_last - assign $0\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] \libresocsim_cmdr_cmdr_converter_source_payload_data - assign $0\libresocsim_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] \libresocsim_cmdr_cmdr_converter_source_payload_valid_token_count - assign $0\libresocsim_cmdr_cmdr_converter_demux[2:0] \libresocsim_cmdr_cmdr_converter_demux - assign $0\libresocsim_cmdr_cmdr_converter_strobe_all[0:0] \libresocsim_cmdr_cmdr_converter_strobe_all - assign $0\libresocsim_cmdr_cmdr_buf_source_valid[0:0] \libresocsim_cmdr_cmdr_buf_source_valid - assign $0\libresocsim_cmdr_cmdr_buf_source_first[0:0] \libresocsim_cmdr_cmdr_buf_source_first - assign $0\libresocsim_cmdr_cmdr_buf_source_last[0:0] \libresocsim_cmdr_cmdr_buf_source_last - assign $0\libresocsim_cmdr_cmdr_buf_source_payload_data[7:0] \libresocsim_cmdr_cmdr_buf_source_payload_data - assign $0\libresocsim_cmdr_cmdr_reset[0:0] \libresocsim_cmdr_cmdr_reset - assign $0\libresocsim_dataw_count[7:0] \libresocsim_dataw_count - assign $0\libresocsim_dataw_crcr_run[0:0] \libresocsim_dataw_crcr_run - assign $0\libresocsim_dataw_crcr_converter_source_first[0:0] \libresocsim_dataw_crcr_converter_source_first - assign $0\libresocsim_dataw_crcr_converter_source_last[0:0] \libresocsim_dataw_crcr_converter_source_last - assign $0\libresocsim_dataw_crcr_converter_source_payload_data[7:0] \libresocsim_dataw_crcr_converter_source_payload_data - assign $0\libresocsim_dataw_crcr_converter_source_payload_valid_token_count[3:0] \libresocsim_dataw_crcr_converter_source_payload_valid_token_count - assign $0\libresocsim_dataw_crcr_converter_demux[2:0] \libresocsim_dataw_crcr_converter_demux - assign $0\libresocsim_dataw_crcr_converter_strobe_all[0:0] \libresocsim_dataw_crcr_converter_strobe_all - assign $0\libresocsim_dataw_crcr_buf_source_valid[0:0] \libresocsim_dataw_crcr_buf_source_valid - assign $0\libresocsim_dataw_crcr_buf_source_first[0:0] \libresocsim_dataw_crcr_buf_source_first - assign $0\libresocsim_dataw_crcr_buf_source_last[0:0] \libresocsim_dataw_crcr_buf_source_last - assign $0\libresocsim_dataw_crcr_buf_source_payload_data[7:0] \libresocsim_dataw_crcr_buf_source_payload_data - assign $0\libresocsim_dataw_crcr_reset[0:0] \libresocsim_dataw_crcr_reset - assign $0\libresocsim_datar_timeout[31:0] \libresocsim_datar_timeout - assign $0\libresocsim_datar_count[9:0] \libresocsim_datar_count - assign $0\libresocsim_datar_datar_run[0:0] \libresocsim_datar_datar_run - assign $0\libresocsim_datar_datar_converter_source_first[0:0] \libresocsim_datar_datar_converter_source_first - assign $0\libresocsim_datar_datar_converter_source_last[0:0] \libresocsim_datar_datar_converter_source_last - assign $0\libresocsim_datar_datar_converter_source_payload_data[7:0] \libresocsim_datar_datar_converter_source_payload_data - assign $0\libresocsim_datar_datar_converter_source_payload_valid_token_count[1:0] \libresocsim_datar_datar_converter_source_payload_valid_token_count - assign $0\libresocsim_datar_datar_converter_demux[0:0] \libresocsim_datar_datar_converter_demux - assign $0\libresocsim_datar_datar_converter_strobe_all[0:0] \libresocsim_datar_datar_converter_strobe_all - assign $0\libresocsim_datar_datar_buf_source_valid[0:0] \libresocsim_datar_datar_buf_source_valid - assign $0\libresocsim_datar_datar_buf_source_first[0:0] \libresocsim_datar_datar_buf_source_first - assign $0\libresocsim_datar_datar_buf_source_last[0:0] \libresocsim_datar_datar_buf_source_last - assign $0\libresocsim_datar_datar_buf_source_payload_data[7:0] \libresocsim_datar_datar_buf_source_payload_data - assign $0\libresocsim_datar_datar_reset[0:0] \libresocsim_datar_datar_reset - assign $0\libresocsim_sdcore_cmd_argument_storage[31:0] \libresocsim_sdcore_cmd_argument_storage - assign { } { } - assign $0\libresocsim_sdcore_cmd_command_storage[31:0] \libresocsim_sdcore_cmd_command_storage - assign { } { } - assign $0\libresocsim_sdcore_cmd_response_status[127:0] \libresocsim_sdcore_cmd_response_status - assign $0\libresocsim_sdcore_block_length_storage[9:0] \libresocsim_sdcore_block_length_storage - assign { } { } - assign $0\libresocsim_sdcore_block_count_storage[31:0] \libresocsim_sdcore_block_count_storage - assign { } { } - assign $0\libresocsim_sdcore_crc7_inserter_crcreg0[6:0] \libresocsim_sdcore_crc7_inserter_crcreg0 - assign $0\libresocsim_sdcore_crc16_inserter_cnt[2:0] \libresocsim_sdcore_crc16_inserter_cnt - assign $0\libresocsim_sdcore_crc16_inserter_crc0_crcreg0[15:0] \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 - assign $0\libresocsim_sdcore_crc16_inserter_crc1_crcreg0[15:0] \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 - assign $0\libresocsim_sdcore_crc16_inserter_crc2_crcreg0[15:0] \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 - assign $0\libresocsim_sdcore_crc16_inserter_crc3_crcreg0[15:0] \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 - assign $0\libresocsim_sdcore_crc16_inserter_crctmp0[15:0] \libresocsim_sdcore_crc16_inserter_crctmp0 - assign $0\libresocsim_sdcore_crc16_inserter_crctmp1[15:0] \libresocsim_sdcore_crc16_inserter_crctmp1 - assign $0\libresocsim_sdcore_crc16_inserter_crctmp2[15:0] \libresocsim_sdcore_crc16_inserter_crctmp2 - assign $0\libresocsim_sdcore_crc16_inserter_crctmp3[15:0] \libresocsim_sdcore_crc16_inserter_crctmp3 - assign $0\libresocsim_sdcore_crc16_checker_val[7:0] \libresocsim_sdcore_crc16_checker_val - assign $0\libresocsim_sdcore_crc16_checker_cnt[3:0] \libresocsim_sdcore_crc16_checker_cnt - assign $0\libresocsim_sdcore_crc16_checker_crc0_crcreg0[15:0] \libresocsim_sdcore_crc16_checker_crc0_crcreg0 - assign $0\libresocsim_sdcore_crc16_checker_crc1_crcreg0[15:0] \libresocsim_sdcore_crc16_checker_crc1_crcreg0 - assign $0\libresocsim_sdcore_crc16_checker_crc2_crcreg0[15:0] \libresocsim_sdcore_crc16_checker_crc2_crcreg0 - assign $0\libresocsim_sdcore_crc16_checker_crc3_crcreg0[15:0] \libresocsim_sdcore_crc16_checker_crc3_crcreg0 - assign $0\libresocsim_sdcore_crc16_checker_crctmp0[15:0] \libresocsim_sdcore_crc16_checker_crctmp0 - assign $0\libresocsim_sdcore_crc16_checker_crctmp1[15:0] \libresocsim_sdcore_crc16_checker_crctmp1 - assign $0\libresocsim_sdcore_crc16_checker_crctmp2[15:0] \libresocsim_sdcore_crc16_checker_crctmp2 - assign $0\libresocsim_sdcore_crc16_checker_crctmp3[15:0] \libresocsim_sdcore_crc16_checker_crctmp3 - assign $0\libresocsim_sdcore_crc16_checker_fifo0[15:0] \libresocsim_sdcore_crc16_checker_fifo0 - assign $0\libresocsim_sdcore_crc16_checker_fifo1[15:0] \libresocsim_sdcore_crc16_checker_fifo1 - assign $0\libresocsim_sdcore_crc16_checker_fifo2[15:0] \libresocsim_sdcore_crc16_checker_fifo2 - assign $0\libresocsim_sdcore_crc16_checker_fifo3[15:0] \libresocsim_sdcore_crc16_checker_fifo3 - assign $0\libresocsim_sdcore_cmd_count[2:0] \libresocsim_sdcore_cmd_count - assign $0\libresocsim_sdcore_cmd_done[0:0] \libresocsim_sdcore_cmd_done - assign $0\libresocsim_sdcore_cmd_error[0:0] \libresocsim_sdcore_cmd_error - assign $0\libresocsim_sdcore_cmd_timeout[0:0] \libresocsim_sdcore_cmd_timeout - assign $0\libresocsim_sdcore_data_count[31:0] \libresocsim_sdcore_data_count - assign $0\libresocsim_sdcore_data_done[0:0] \libresocsim_sdcore_data_done - assign $0\libresocsim_sdcore_data_error[0:0] \libresocsim_sdcore_data_error - assign $0\libresocsim_sdcore_data_timeout[0:0] \libresocsim_sdcore_data_timeout - assign $0\libresocsim_sdblock2mem_fifo_level[5:0] \libresocsim_sdblock2mem_fifo_level - assign $0\libresocsim_sdblock2mem_fifo_produce[4:0] \libresocsim_sdblock2mem_fifo_produce - assign $0\libresocsim_sdblock2mem_fifo_consume[4:0] \libresocsim_sdblock2mem_fifo_consume - assign $0\libresocsim_sdblock2mem_converter_source_first[0:0] \libresocsim_sdblock2mem_converter_source_first - assign $0\libresocsim_sdblock2mem_converter_source_last[0:0] \libresocsim_sdblock2mem_converter_source_last - assign $0\libresocsim_sdblock2mem_converter_source_payload_data[31:0] \libresocsim_sdblock2mem_converter_source_payload_data - assign $0\libresocsim_sdblock2mem_converter_source_payload_valid_token_count[2:0] \libresocsim_sdblock2mem_converter_source_payload_valid_token_count - assign $0\libresocsim_sdblock2mem_converter_demux[1:0] \libresocsim_sdblock2mem_converter_demux - assign $0\libresocsim_sdblock2mem_converter_strobe_all[0:0] \libresocsim_sdblock2mem_converter_strobe_all - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] \libresocsim_sdblock2mem_wishbonedmawriter_base_storage - assign { } { } - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_length_storage[31:0] \libresocsim_sdblock2mem_wishbonedmawriter_length_storage - assign { } { } - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \libresocsim_sdblock2mem_wishbonedmawriter_enable_storage - assign { } { } - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \libresocsim_sdblock2mem_wishbonedmawriter_loop_storage - assign { } { } - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_offset[31:0] \libresocsim_sdblock2mem_wishbonedmawriter_offset - assign $0\libresocsim_sdmem2block_dma_data[31:0] \libresocsim_sdmem2block_dma_data - assign $0\libresocsim_sdmem2block_dma_base_storage[63:0] \libresocsim_sdmem2block_dma_base_storage - assign { } { } - assign $0\libresocsim_sdmem2block_dma_length_storage[31:0] \libresocsim_sdmem2block_dma_length_storage - assign { } { } - assign $0\libresocsim_sdmem2block_dma_enable_storage[0:0] \libresocsim_sdmem2block_dma_enable_storage - assign { } { } - assign $0\libresocsim_sdmem2block_dma_loop_storage[0:0] \libresocsim_sdmem2block_dma_loop_storage - assign { } { } - assign $0\libresocsim_sdmem2block_dma_offset[31:0] \libresocsim_sdmem2block_dma_offset - assign $0\libresocsim_sdmem2block_converter_mux[1:0] \libresocsim_sdmem2block_converter_mux - assign $0\libresocsim_sdmem2block_fifo_level[5:0] \libresocsim_sdmem2block_fifo_level - assign $0\libresocsim_sdmem2block_fifo_produce[4:0] \libresocsim_sdmem2block_fifo_produce - assign $0\libresocsim_sdmem2block_fifo_consume[4:0] \libresocsim_sdmem2block_fifo_consume - assign $0\libresocsim_miso[7:0] \libresocsim_miso - assign $0\libresocsim_control_storage[15:0] \libresocsim_control_storage - assign { } { } - assign $0\libresocsim_mosi_storage[7:0] \libresocsim_mosi_storage - assign { } { } - assign $0\libresocsim_cs_storage[0:0] \libresocsim_cs_storage - assign { } { } - assign $0\libresocsim_loopback_storage[0:0] \libresocsim_loopback_storage - assign { } { } - assign $0\libresocsim_count[2:0] \libresocsim_count - assign { } { } - assign $0\libresocsim_mosi_data[7:0] \libresocsim_mosi_data - assign $0\libresocsim_mosi_sel[2:0] \libresocsim_mosi_sel - assign $0\libresocsim_miso_data[7:0] \libresocsim_miso_data - assign $0\libresocsim_storage[15:0] \libresocsim_storage - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr - assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we - assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w - assign $0\builder_grant[1:0] \builder_grant - assign { } { } - assign $0\builder_count[19:0] \builder_count - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\builder_converter0_state[0:0] \builder_converter0_next_state - assign $0\builder_converter1_state[0:0] \builder_converter1_next_state - assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 - assign $0\main_libresocsim_sink_ready[0:0] 1'0 - assign $0\main_libresocsim_source_valid[0:0] 1'0 - assign $0\main_libresocsim_rx_r[0:0] \main_libresocsim_rx - assign $0\main_libresocsim_uart_tx_old_trigger[0:0] \main_libresocsim_uart_tx_trigger - assign $0\main_libresocsim_uart_rx_old_trigger[0:0] \main_libresocsim_uart_rx_trigger - assign $0\main_libresocsim_timer_zero_old_trigger[0:0] \main_libresocsim_timer_zero_trigger - assign $0\main_rddata_en[2:0] { \main_rddata_en [1:0] \main_dfi_p0_rddata_en } - assign $0\main_dfi_p0_rddata_valid[0:0] \main_rddata_en [2] - assign $0\main_sdram_postponer_req_o[0:0] 1'0 - assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 - assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_sequencer_done1[0:0] 1'0 - assign $0\builder_refresher_state[1:0] \builder_refresher_next_state - assign $0\builder_bankmachine0_state[2:0] \builder_bankmachine0_next_state - assign $0\builder_bankmachine1_state[2:0] \builder_bankmachine1_next_state - assign $0\builder_bankmachine2_state[2:0] \builder_bankmachine2_next_state - assign $0\builder_bankmachine3_state[2:0] \builder_bankmachine3_next_state - assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0 - assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0 - assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1 - assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:7619$2325_Y - assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:7620$2326_Y - assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:7621$2327_Y - assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5 - assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6 - assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state - assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:7655$2345_Y - assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:7656$2357_Y - assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0 - assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1 - assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2 - assign $0\builder_converter_state[0:0] \builder_converter_next_state - assign $0\main_clk_divider1[15:0] $add$ls180.v:7682$2361_Y - assign $0\spi_master_cs_n[0:0] $or$ls180.v:7691$2364_Y - assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state - assign $0\libresocsim_clocker_clk_d[0:0] \libresocsim_clocker_clk1 - assign $0\libresocsim_clocker_clk0[0:0] \libresocsim_clocker_clk1 - assign $0\builder_sdphy_sdphyinit_state[0:0] \builder_sdphy_sdphyinit_next_state - assign $0\builder_sdphy_sdphycmdw_state[1:0] \builder_sdphy_sdphycmdw_next_state - assign $0\builder_sdphy_sdphycmdr_state[2:0] \builder_sdphy_sdphycmdr_next_state - assign $0\builder_sdphy_sdphycrcr_state[0:0] \builder_sdphy_sdphycrcr_next_state - assign $0\builder_sdphy_fsm_state[2:0] \builder_sdphy_fsm_next_state - assign $0\builder_sdphy_sdphydatar_state[2:0] \builder_sdphy_sdphydatar_next_state - assign $0\builder_sdcore_crcupstreaminserter_state[0:0] \builder_sdcore_crcupstreaminserter_next_state - assign $0\builder_sdcore_fsm_state[2:0] \builder_sdcore_fsm_next_state - assign $0\builder_sdblock2memdma_state[1:0] \builder_sdblock2memdma_next_state - assign $0\builder_sdmem2blockdma_fsm_state[0:0] \builder_sdmem2blockdma_fsm_next_state - assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] \builder_sdmem2blockdma_resetinserter_next_state - assign $0\libresocsim_clk_divider1[15:0] $add$ls180.v:8202$2448_Y - assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8211$2451_Y - assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state - assign $0\builder_state[1:0] \builder_next_state - assign $0\builder_slave_sel_r[4:0] \builder_slave_sel - assign $0\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_libresocsim_soccontroller_reset_re[0:0] \builder_csrbank0_reset0_re - assign $0\main_libresocsim_soccontroller_scratch_re[0:0] \builder_csrbank0_scratch0_re - assign $0\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 - assign $0\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 - assign $0\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_base_re[0:0] \builder_csrbank3_dma_base0_re - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_length_re[0:0] \builder_csrbank3_dma_length0_re - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_enable_re[0:0] \builder_csrbank3_dma_enable0_re - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_loop_re[0:0] \builder_csrbank3_dma_loop0_re - assign $0\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 - assign $0\libresocsim_sdcore_cmd_argument_re[0:0] \builder_csrbank4_cmd_argument0_re - assign $0\libresocsim_sdcore_cmd_command_re[0:0] \builder_csrbank4_cmd_command0_re - assign $0\libresocsim_sdcore_block_length_re[0:0] \builder_csrbank4_block_length0_re - assign $0\libresocsim_sdcore_block_count_re[0:0] \builder_csrbank4_block_count0_re - assign $0\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 - assign $0\libresocsim_sdmem2block_dma_base_re[0:0] \builder_csrbank5_dma_base0_re - assign $0\libresocsim_sdmem2block_dma_length_re[0:0] \builder_csrbank5_dma_length0_re - assign $0\libresocsim_sdmem2block_dma_enable_re[0:0] \builder_csrbank5_dma_enable0_re - assign $0\libresocsim_sdmem2block_dma_loop_re[0:0] \builder_csrbank5_dma_loop0_re - assign $0\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 - assign $0\libresocsim_clocker_re[0:0] \builder_csrbank6_clocker_divider0_re - assign $0\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdram_re[0:0] \builder_csrbank7_dfii_control0_re - assign $0\main_sdram_command_re[0:0] \builder_csrbank7_dfii_pi0_command0_re - assign $0\main_sdram_address_re[0:0] \builder_csrbank7_dfii_pi0_address0_re - assign $0\main_sdram_baddress_re[0:0] \builder_csrbank7_dfii_pi0_baddress0_re - assign $0\main_sdram_wrdata_re[0:0] \builder_csrbank7_dfii_pi0_wrdata0_re - assign $0\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_control_re[0:0] \builder_csrbank8_control0_re - assign $0\main_mosi_re[0:0] \builder_csrbank8_mosi0_re - assign $0\main_cs_re[0:0] \builder_csrbank8_cs0_re - assign $0\main_loopback_re[0:0] \builder_csrbank8_loopback0_re - assign $0\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 - assign $0\libresocsim_control_re[0:0] \builder_csrbank9_control0_re - assign $0\libresocsim_mosi_re[0:0] \builder_csrbank9_mosi0_re - assign $0\libresocsim_cs_re[0:0] \builder_csrbank9_cs0_re - assign $0\libresocsim_loopback_re[0:0] \builder_csrbank9_loopback0_re - assign $0\libresocsim_re[0:0] \builder_csrbank9_clk_divider0_re - assign $0\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_libresocsim_timer_load_re[0:0] \builder_csrbank10_load0_re - assign $0\main_libresocsim_timer_reload_re[0:0] \builder_csrbank10_reload0_re - assign $0\main_libresocsim_timer_en_re[0:0] \builder_csrbank10_en0_re - assign $0\main_libresocsim_timer_update_value_re[0:0] \builder_csrbank10_update_value0_re - assign $0\main_libresocsim_timer_eventmanager_re[0:0] \builder_csrbank10_ev_enable0_re - assign $0\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_libresocsim_uart_eventmanager_re[0:0] \builder_csrbank11_ev_enable0_re - assign $0\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_libresocsim_re[0:0] \builder_csrbank12_tuning_word0_re - assign $0\builder_multiregimpl0_regs0[0:0] \serial_rx - assign $0\builder_multiregimpl0_regs1[0:0] \builder_multiregimpl0_regs0 - assign $0\builder_multiregimpl1_regs0[7:0] \gpio_in - assign $0\builder_multiregimpl1_regs1[7:0] \builder_multiregimpl1_regs0 - assign $0\builder_multiregimpl2_regs0[7:0] \gpio_out - assign $0\builder_multiregimpl2_regs1[7:0] \builder_multiregimpl2_regs0 - attribute \src "ls180.v:7057.2-7059.5" - switch $or$ls180.v:7057$2188_Y - attribute \src "ls180.v:7057.6-7057.94" - case 1'1 - assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_libresoc_ibus_dat_r - case - end - attribute \src "ls180.v:7061.2-7063.5" - switch \main_libresocsim_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:7061.6-7061.66" - case 1'1 - assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter_converter0_next_value - case - end - attribute \src "ls180.v:7064.2-7067.5" - switch \main_libresocsim_converter0_reset - attribute \src "ls180.v:7064.6-7064.39" - case 1'1 - assign $0\main_libresocsim_converter0_counter[0:0] 1'0 - assign $0\builder_converter0_state[0:0] 1'0 - case - end - attribute \src "ls180.v:7068.2-7070.5" - switch $or$ls180.v:7068$2189_Y - attribute \src "ls180.v:7068.6-7068.94" - case 1'1 - assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_libresoc_dbus_dat_r - case - end - attribute \src "ls180.v:7072.2-7074.5" - switch \main_libresocsim_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:7072.6-7072.66" - case 1'1 - assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter_converter1_next_value - case - end - attribute \src "ls180.v:7075.2-7078.5" - switch \main_libresocsim_converter1_reset - attribute \src "ls180.v:7075.6-7075.39" - case 1'1 - assign $0\main_libresocsim_converter1_counter[0:0] 1'0 - assign $0\builder_converter1_state[0:0] 1'0 - case - end - attribute \src "ls180.v:7079.2-7083.5" - switch $ne$ls180.v:7079$2190_Y - attribute \src "ls180.v:7079.6-7079.67" - case 1'1 - attribute \src "ls180.v:7080.3-7082.6" - switch \main_libresocsim_soccontroller_bus_error - attribute \src "ls180.v:7080.7-7080.47" - case 1'1 - assign $0\main_libresocsim_soccontroller_bus_errors[31:0] $add$ls180.v:7081$2191_Y - case - end - case - end - attribute \src "ls180.v:7085.2-7087.5" - switch $and$ls180.v:7085$2194_Y - attribute \src "ls180.v:7085.6-7085.103" - case 1'1 - assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1 - case - end - attribute \src "ls180.v:7089.2-7110.5" - switch $and$ls180.v:7089$2198_Y - attribute \src "ls180.v:7089.6-7089.100" - case 1'1 - assign $0\main_libresocsim_tx_reg[7:0] \main_libresocsim_sink_payload_data - assign $0\main_libresocsim_tx_bitcount[3:0] 4'0000 - assign $0\main_libresocsim_tx_busy[0:0] 1'1 - assign $0\serial_tx[0:0] 1'0 - attribute \src "ls180.v:7094.6-7094.10" - case - attribute \src "ls180.v:7095.3-7109.6" - switch $and$ls180.v:7095$2199_Y - attribute \src "ls180.v:7095.7-7095.66" - case 1'1 - assign $0\main_libresocsim_tx_bitcount[3:0] $add$ls180.v:7096$2200_Y - attribute \src "ls180.v:7097.4-7108.7" - switch $eq$ls180.v:7097$2201_Y - attribute \src "ls180.v:7097.8-7097.46" - case 1'1 - assign $0\serial_tx[0:0] 1'1 - attribute \src "ls180.v:7099.8-7099.12" - case - attribute \src "ls180.v:7100.5-7107.8" - switch $eq$ls180.v:7100$2202_Y - attribute \src "ls180.v:7100.9-7100.47" - case 1'1 - assign $0\serial_tx[0:0] 1'1 - assign $0\main_libresocsim_tx_busy[0:0] 1'0 - assign $0\main_libresocsim_sink_ready[0:0] 1'1 - attribute \src "ls180.v:7104.9-7104.13" - case - assign $0\serial_tx[0:0] \main_libresocsim_tx_reg [0] - assign $0\main_libresocsim_tx_reg[7:0] { 1'0 \main_libresocsim_tx_reg [7:1] } - end - end - case - end - end - attribute \src "ls180.v:7111.2-7115.5" - switch \main_libresocsim_tx_busy - attribute \src "ls180.v:7111.6-7111.30" - case 1'1 - assign { $0\main_libresocsim_uart_clk_txen[0:0] $0\main_libresocsim_phase_accumulator_tx[31:0] } $add$ls180.v:7112$2203_Y - attribute \src "ls180.v:7113.6-7113.10" - case - assign { $0\main_libresocsim_uart_clk_txen[0:0] $0\main_libresocsim_phase_accumulator_tx[31:0] } { 1'0 \main_libresocsim_storage } - end - attribute \src "ls180.v:7118.2-7142.5" - switch $not$ls180.v:7118$2204_Y - attribute \src "ls180.v:7118.6-7118.33" - case 1'1 - attribute \src "ls180.v:7119.3-7122.6" - switch $and$ls180.v:7119$2206_Y - attribute \src "ls180.v:7119.7-7119.55" - case 1'1 - assign $0\main_libresocsim_rx_busy[0:0] 1'1 - assign $0\main_libresocsim_rx_bitcount[3:0] 4'0000 - case - end - attribute \src "ls180.v:7123.6-7123.10" - case - attribute \src "ls180.v:7124.3-7141.6" - switch \main_libresocsim_uart_clk_rxen - attribute \src "ls180.v:7124.7-7124.37" - case 1'1 - assign $0\main_libresocsim_rx_bitcount[3:0] $add$ls180.v:7125$2207_Y - attribute \src "ls180.v:7126.4-7140.7" - switch $eq$ls180.v:7126$2208_Y - attribute \src "ls180.v:7126.8-7126.46" - case 1'1 - attribute \src "ls180.v:7127.5-7129.8" - switch \main_libresocsim_rx - attribute \src "ls180.v:7127.9-7127.28" - case 1'1 - assign $0\main_libresocsim_rx_busy[0:0] 1'0 - case - end - attribute \src "ls180.v:7130.8-7130.12" - case - attribute \src "ls180.v:7131.5-7139.8" - switch $eq$ls180.v:7131$2209_Y - attribute \src "ls180.v:7131.9-7131.47" - case 1'1 - assign $0\main_libresocsim_rx_busy[0:0] 1'0 - attribute \src "ls180.v:7133.6-7136.9" - switch \main_libresocsim_rx - attribute \src "ls180.v:7133.10-7133.29" - case 1'1 - assign $0\main_libresocsim_source_payload_data[7:0] \main_libresocsim_rx_reg - assign $0\main_libresocsim_source_valid[0:0] 1'1 - case - end - attribute \src "ls180.v:7137.9-7137.13" - case - assign $0\main_libresocsim_rx_reg[7:0] { \main_libresocsim_rx \main_libresocsim_rx_reg [7:1] } - end - end - case - end - end - attribute \src "ls180.v:7143.2-7147.5" - switch \main_libresocsim_rx_busy - attribute \src "ls180.v:7143.6-7143.30" - case 1'1 - assign { $0\main_libresocsim_uart_clk_rxen[0:0] $0\main_libresocsim_phase_accumulator_rx[31:0] } $add$ls180.v:7144$2210_Y - attribute \src "ls180.v:7145.6-7145.10" - case - assign { $0\main_libresocsim_uart_clk_rxen[0:0] $0\main_libresocsim_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 - end - attribute \src "ls180.v:7148.2-7150.5" - switch \main_libresocsim_uart_tx_clear - attribute \src "ls180.v:7148.6-7148.36" - case 1'1 - assign $0\main_libresocsim_uart_tx_pending[0:0] 1'0 - case - end - attribute \src "ls180.v:7152.2-7154.5" - switch $and$ls180.v:7152$2212_Y - attribute \src "ls180.v:7152.6-7152.82" - case 1'1 - assign $0\main_libresocsim_uart_tx_pending[0:0] 1'1 - case - end - attribute \src "ls180.v:7155.2-7157.5" - switch \main_libresocsim_uart_rx_clear - attribute \src "ls180.v:7155.6-7155.36" - case 1'1 - assign $0\main_libresocsim_uart_rx_pending[0:0] 1'0 - case - end - attribute \src "ls180.v:7159.2-7161.5" - switch $and$ls180.v:7159$2214_Y - attribute \src "ls180.v:7159.6-7159.82" - case 1'1 - assign $0\main_libresocsim_uart_rx_pending[0:0] 1'1 - case - end - attribute \src "ls180.v:7162.2-7168.5" - switch \main_libresocsim_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:7162.6-7162.47" - case 1'1 - assign $0\main_libresocsim_uart_tx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:7164.6-7164.10" - case - attribute \src "ls180.v:7165.3-7167.6" - switch \main_libresocsim_uart_tx_fifo_re - attribute \src "ls180.v:7165.7-7165.39" - case 1'1 - assign $0\main_libresocsim_uart_tx_fifo_readable[0:0] 1'0 - case - end - end - attribute \src "ls180.v:7169.2-7171.5" - switch $and$ls180.v:7169$2217_Y - attribute \src "ls180.v:7169.6-7169.144" - case 1'1 - assign $0\main_libresocsim_uart_tx_fifo_produce[3:0] $add$ls180.v:7170$2218_Y - case - end - attribute \src "ls180.v:7172.2-7174.5" - switch \main_libresocsim_uart_tx_fifo_do_read - attribute \src "ls180.v:7172.6-7172.43" - case 1'1 - assign $0\main_libresocsim_uart_tx_fifo_consume[3:0] $add$ls180.v:7173$2219_Y - case - end - attribute \src "ls180.v:7175.2-7183.5" - switch $and$ls180.v:7175$2222_Y - attribute \src "ls180.v:7175.6-7175.144" - case 1'1 - attribute \src "ls180.v:7176.3-7178.6" - switch $not$ls180.v:7176$2223_Y - attribute \src "ls180.v:7176.7-7176.47" - case 1'1 - assign $0\main_libresocsim_uart_tx_fifo_level0[4:0] $add$ls180.v:7177$2224_Y - case - end - attribute \src "ls180.v:7179.6-7179.10" - case - attribute \src "ls180.v:7180.3-7182.6" - switch \main_libresocsim_uart_tx_fifo_do_read - attribute \src "ls180.v:7180.7-7180.44" - case 1'1 - assign $0\main_libresocsim_uart_tx_fifo_level0[4:0] $sub$ls180.v:7181$2225_Y - case - end - end - attribute \src "ls180.v:7184.2-7190.5" - switch \main_libresocsim_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:7184.6-7184.47" - case 1'1 - assign $0\main_libresocsim_uart_rx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:7186.6-7186.10" - case - attribute \src "ls180.v:7187.3-7189.6" - switch \main_libresocsim_uart_rx_fifo_re - attribute \src "ls180.v:7187.7-7187.39" - case 1'1 - assign $0\main_libresocsim_uart_rx_fifo_readable[0:0] 1'0 - case - end - end - attribute \src "ls180.v:7191.2-7193.5" - switch $and$ls180.v:7191$2228_Y - attribute \src "ls180.v:7191.6-7191.144" - case 1'1 - assign $0\main_libresocsim_uart_rx_fifo_produce[3:0] $add$ls180.v:7192$2229_Y - case - end - attribute \src "ls180.v:7194.2-7196.5" - switch \main_libresocsim_uart_rx_fifo_do_read - attribute \src "ls180.v:7194.6-7194.43" - case 1'1 - assign $0\main_libresocsim_uart_rx_fifo_consume[3:0] $add$ls180.v:7195$2230_Y - case - end - attribute \src "ls180.v:7197.2-7205.5" - switch $and$ls180.v:7197$2233_Y - attribute \src "ls180.v:7197.6-7197.144" - case 1'1 - attribute \src "ls180.v:7198.3-7200.6" - switch $not$ls180.v:7198$2234_Y - attribute \src "ls180.v:7198.7-7198.47" - case 1'1 - assign $0\main_libresocsim_uart_rx_fifo_level0[4:0] $add$ls180.v:7199$2235_Y - case - end - attribute \src "ls180.v:7201.6-7201.10" - case - attribute \src "ls180.v:7202.3-7204.6" - switch \main_libresocsim_uart_rx_fifo_do_read - attribute \src "ls180.v:7202.7-7202.44" - case 1'1 - assign $0\main_libresocsim_uart_rx_fifo_level0[4:0] $sub$ls180.v:7203$2236_Y - case - end - end - attribute \src "ls180.v:7206.2-7219.5" - switch \main_libresocsim_uart_reset - attribute \src "ls180.v:7206.6-7206.33" - case 1'1 - assign $0\main_libresocsim_uart_tx_pending[0:0] 1'0 - assign $0\main_libresocsim_uart_tx_old_trigger[0:0] 1'0 - assign $0\main_libresocsim_uart_rx_pending[0:0] 1'0 - assign $0\main_libresocsim_uart_rx_old_trigger[0:0] 1'0 - assign $0\main_libresocsim_uart_tx_fifo_readable[0:0] 1'0 - assign $0\main_libresocsim_uart_tx_fifo_level0[4:0] 5'00000 - assign $0\main_libresocsim_uart_tx_fifo_produce[3:0] 4'0000 - assign $0\main_libresocsim_uart_tx_fifo_consume[3:0] 4'0000 - assign $0\main_libresocsim_uart_rx_fifo_readable[0:0] 1'0 - assign $0\main_libresocsim_uart_rx_fifo_level0[4:0] 5'00000 - assign $0\main_libresocsim_uart_rx_fifo_produce[3:0] 4'0000 - assign $0\main_libresocsim_uart_rx_fifo_consume[3:0] 4'0000 - case - end - attribute \src "ls180.v:7220.2-7228.5" - switch \main_libresocsim_timer_en_storage - attribute \src "ls180.v:7220.6-7220.39" - case 1'1 - attribute \src "ls180.v:7221.3-7225.6" - switch $eq$ls180.v:7221$2237_Y - attribute \src "ls180.v:7221.7-7221.45" - case 1'1 - assign $0\main_libresocsim_timer_value[31:0] \main_libresocsim_timer_reload_storage - attribute \src "ls180.v:7223.7-7223.11" - case - assign $0\main_libresocsim_timer_value[31:0] $sub$ls180.v:7224$2238_Y - end - attribute \src "ls180.v:7226.6-7226.10" - case - assign $0\main_libresocsim_timer_value[31:0] \main_libresocsim_timer_load_storage - end - attribute \src "ls180.v:7229.2-7231.5" - switch \main_libresocsim_timer_update_value_re - attribute \src "ls180.v:7229.6-7229.44" - case 1'1 - assign $0\main_libresocsim_timer_value_status[31:0] \main_libresocsim_timer_value - case - end - attribute \src "ls180.v:7232.2-7234.5" - switch \main_libresocsim_timer_zero_clear - attribute \src "ls180.v:7232.6-7232.39" - case 1'1 - assign $0\main_libresocsim_timer_zero_pending[0:0] 1'0 - case - end - attribute \src "ls180.v:7236.2-7238.5" - switch $and$ls180.v:7236$2240_Y - attribute \src "ls180.v:7236.6-7236.88" - case 1'1 - assign $0\main_libresocsim_timer_zero_pending[0:0] 1'1 - case - end - attribute \src "ls180.v:7241.2-7243.5" - switch \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:7241.6-7241.37" - case 1'1 - assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata - case - end - attribute \src "ls180.v:7244.2-7248.5" - switch $and$ls180.v:7244$2242_Y - attribute \src "ls180.v:7244.6-7244.57" - case 1'1 - assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7245$2243_Y - attribute \src "ls180.v:7246.6-7246.10" - case - assign $0\main_sdram_timer_count1[9:0] 10'1100001101 - end - attribute \src "ls180.v:7250.2-7256.5" - switch \main_sdram_postponer_req_i - attribute \src "ls180.v:7250.6-7250.32" - case 1'1 - assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7251$2244_Y - attribute \src "ls180.v:7252.3-7255.6" - switch $eq$ls180.v:7252$2245_Y - attribute \src "ls180.v:7252.7-7252.43" - case 1'1 - assign $0\main_sdram_postponer_count[0:0] 1'0 - assign $0\main_sdram_postponer_req_o[0:0] 1'1 - case - end - case - end - attribute \src "ls180.v:7257.2-7265.5" - switch \main_sdram_sequencer_start0 - attribute \src "ls180.v:7257.6-7257.33" - case 1'1 - assign $0\main_sdram_sequencer_count[0:0] 1'0 - attribute \src "ls180.v:7259.6-7259.10" - case - attribute \src "ls180.v:7260.3-7264.6" - switch \main_sdram_sequencer_done1 - attribute \src "ls180.v:7260.7-7260.33" - case 1'1 - attribute \src "ls180.v:7261.4-7263.7" - switch $ne$ls180.v:7261$2246_Y - attribute \src "ls180.v:7261.8-7261.44" - case 1'1 - assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7262$2247_Y - case - end - case - end - end - attribute \src "ls180.v:7272.2-7278.5" - switch $and$ls180.v:7272$2249_Y - attribute \src "ls180.v:7272.6-7272.76" - case 1'1 - assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000 - assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 - assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_cmd_payload_we[0:0] 1'1 - case - end - attribute \src "ls180.v:7279.2-7285.5" - switch $eq$ls180.v:7279$2250_Y - attribute \src "ls180.v:7279.6-7279.44" - case 1'1 - assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 - assign $0\main_sdram_cmd_payload_cas[0:0] 1'1 - assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_cmd_payload_we[0:0] 1'0 - case - end - attribute \src "ls180.v:7286.2-7293.5" - switch $eq$ls180.v:7286$2251_Y - attribute \src "ls180.v:7286.6-7286.44" - case 1'1 - assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 - assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_sequencer_done1[0:0] 1'1 - case - end - attribute \src "ls180.v:7294.2-7304.5" - switch $eq$ls180.v:7294$2252_Y - attribute \src "ls180.v:7294.6-7294.44" - case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] 4'0000 - attribute \src "ls180.v:7296.6-7296.10" - case - attribute \src "ls180.v:7297.3-7303.6" - switch $ne$ls180.v:7297$2253_Y - attribute \src "ls180.v:7297.7-7297.45" - case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7298$2254_Y - attribute \src "ls180.v:7299.7-7299.11" - case - attribute \src "ls180.v:7300.4-7302.7" - switch \main_sdram_sequencer_start1 - attribute \src "ls180.v:7300.8-7300.35" - case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] 4'0001 - case - end - end - end - attribute \src "ls180.v:7306.2-7313.5" - switch \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:7306.6-7306.39" - case 1'1 - assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 - attribute \src "ls180.v:7308.6-7308.10" - case - attribute \src "ls180.v:7309.3-7312.6" - switch \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:7309.7-7309.39" - case 1'1 - assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1 - assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - case - end - end - attribute \src "ls180.v:7314.2-7316.5" - switch $and$ls180.v:7314$2257_Y - attribute \src "ls180.v:7314.6-7314.191" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7315$2258_Y - case - end - attribute \src "ls180.v:7317.2-7319.5" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7317.6-7317.58" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7318$2259_Y - case - end - attribute \src "ls180.v:7320.2-7328.5" - switch $and$ls180.v:7320$2262_Y - attribute \src "ls180.v:7320.6-7320.191" - case 1'1 - attribute \src "ls180.v:7321.3-7323.6" - switch $not$ls180.v:7321$2263_Y - attribute \src "ls180.v:7321.7-7321.62" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7322$2264_Y - case - end - attribute \src "ls180.v:7324.6-7324.10" - case - attribute \src "ls180.v:7325.3-7327.6" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7325.7-7325.59" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7326$2265_Y - case - end - end - attribute \src "ls180.v:7329.2-7335.5" - switch $or$ls180.v:7329$2267_Y - attribute \src "ls180.v:7329.6-7329.108" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid - assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first - assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_last - assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_we - assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr - case - end - attribute \src "ls180.v:7336.2-7350.5" - switch \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:7336.6-7336.43" - case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7338.3-7342.6" - switch 1'0 - attribute \src "ls180.v:7340.7-7340.11" - case - assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 - end - attribute \src "ls180.v:7343.6-7343.10" - case - attribute \src "ls180.v:7344.3-7349.6" - switch $not$ls180.v:7344$2268_Y - attribute \src "ls180.v:7344.7-7344.47" - case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7345$2269_Y - attribute \src "ls180.v:7346.4-7348.7" - switch $eq$ls180.v:7346$2270_Y - attribute \src "ls180.v:7346.8-7346.55" - case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1 - case - end - case - end - end - attribute \src "ls180.v:7352.2-7359.5" - switch \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:7352.6-7352.39" - case 1'1 - assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 - attribute \src "ls180.v:7354.6-7354.10" - case - attribute \src "ls180.v:7355.3-7358.6" - switch \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:7355.7-7355.39" - case 1'1 - assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1 - assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - case - end - end - attribute \src "ls180.v:7360.2-7362.5" - switch $and$ls180.v:7360$2273_Y - attribute \src "ls180.v:7360.6-7360.191" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7361$2274_Y - case - end - attribute \src "ls180.v:7363.2-7365.5" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7363.6-7363.58" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7364$2275_Y - case - end - attribute \src "ls180.v:7366.2-7374.5" - switch $and$ls180.v:7366$2278_Y - attribute \src "ls180.v:7366.6-7366.191" - case 1'1 - attribute \src "ls180.v:7367.3-7369.6" - switch $not$ls180.v:7367$2279_Y - attribute \src "ls180.v:7367.7-7367.62" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7368$2280_Y - case - end - attribute \src "ls180.v:7370.6-7370.10" - case - attribute \src "ls180.v:7371.3-7373.6" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7371.7-7371.59" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7372$2281_Y - case - end - end - attribute \src "ls180.v:7375.2-7381.5" - switch $or$ls180.v:7375$2283_Y - attribute \src "ls180.v:7375.6-7375.108" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid - assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first - assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_last - assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_we - assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr - case - end - attribute \src "ls180.v:7382.2-7396.5" - switch \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:7382.6-7382.43" - case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7384.3-7388.6" - switch 1'0 - attribute \src "ls180.v:7386.7-7386.11" - case - assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 - end - attribute \src "ls180.v:7389.6-7389.10" - case - attribute \src "ls180.v:7390.3-7395.6" - switch $not$ls180.v:7390$2284_Y - attribute \src "ls180.v:7390.7-7390.47" - case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7391$2285_Y - attribute \src "ls180.v:7392.4-7394.7" - switch $eq$ls180.v:7392$2286_Y - attribute \src "ls180.v:7392.8-7392.55" - case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1 - case - end - case - end - end - attribute \src "ls180.v:7398.2-7405.5" - switch \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:7398.6-7398.39" - case 1'1 - assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 - attribute \src "ls180.v:7400.6-7400.10" - case - attribute \src "ls180.v:7401.3-7404.6" - switch \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:7401.7-7401.39" - case 1'1 - assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1 - assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - case - end - end - attribute \src "ls180.v:7406.2-7408.5" - switch $and$ls180.v:7406$2289_Y - attribute \src "ls180.v:7406.6-7406.191" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7407$2290_Y - case - end - attribute \src "ls180.v:7409.2-7411.5" - switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7409.6-7409.58" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7410$2291_Y - case - end - attribute \src "ls180.v:7412.2-7420.5" - switch $and$ls180.v:7412$2294_Y - attribute \src "ls180.v:7412.6-7412.191" - case 1'1 - attribute \src "ls180.v:7413.3-7415.6" - switch $not$ls180.v:7413$2295_Y - attribute \src "ls180.v:7413.7-7413.62" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7414$2296_Y - case - end - attribute \src "ls180.v:7416.6-7416.10" - case - attribute \src "ls180.v:7417.3-7419.6" - switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7417.7-7417.59" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7418$2297_Y - case - end - end - attribute \src "ls180.v:7421.2-7427.5" - switch $or$ls180.v:7421$2299_Y - attribute \src "ls180.v:7421.6-7421.108" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid - assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first - assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_last - assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_we - assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr - case - end - attribute \src "ls180.v:7428.2-7442.5" - switch \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:7428.6-7428.43" - case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7430.3-7434.6" - switch 1'0 - attribute \src "ls180.v:7432.7-7432.11" - case - assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 - end - attribute \src "ls180.v:7435.6-7435.10" - case - attribute \src "ls180.v:7436.3-7441.6" - switch $not$ls180.v:7436$2300_Y - attribute \src "ls180.v:7436.7-7436.47" - case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7437$2301_Y - attribute \src "ls180.v:7438.4-7440.7" - switch $eq$ls180.v:7438$2302_Y - attribute \src "ls180.v:7438.8-7438.55" - case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1 - case - end - case - end - end - attribute \src "ls180.v:7444.2-7451.5" - switch \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:7444.6-7444.39" - case 1'1 - assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 - attribute \src "ls180.v:7446.6-7446.10" - case - attribute \src "ls180.v:7447.3-7450.6" - switch \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:7447.7-7447.39" - case 1'1 - assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1 - assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - case - end - end - attribute \src "ls180.v:7452.2-7454.5" - switch $and$ls180.v:7452$2305_Y - attribute \src "ls180.v:7452.6-7452.191" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7453$2306_Y - case - end - attribute \src "ls180.v:7455.2-7457.5" - switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7455.6-7455.58" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7456$2307_Y - case - end - attribute \src "ls180.v:7458.2-7466.5" - switch $and$ls180.v:7458$2310_Y - attribute \src "ls180.v:7458.6-7458.191" - case 1'1 - attribute \src "ls180.v:7459.3-7461.6" - switch $not$ls180.v:7459$2311_Y - attribute \src "ls180.v:7459.7-7459.62" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7460$2312_Y - case - end - attribute \src "ls180.v:7462.6-7462.10" - case - attribute \src "ls180.v:7463.3-7465.6" - switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7463.7-7463.59" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7464$2313_Y - case - end - end - attribute \src "ls180.v:7467.2-7473.5" - switch $or$ls180.v:7467$2315_Y - attribute \src "ls180.v:7467.6-7467.108" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid - assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first - assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_last - assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_we - assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr - case - end - attribute \src "ls180.v:7474.2-7488.5" - switch \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:7474.6-7474.43" - case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7476.3-7480.6" - switch 1'0 - attribute \src "ls180.v:7478.7-7478.11" - case - assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 - end - attribute \src "ls180.v:7481.6-7481.10" - case - attribute \src "ls180.v:7482.3-7487.6" - switch $not$ls180.v:7482$2316_Y - attribute \src "ls180.v:7482.7-7482.47" - case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7483$2317_Y - attribute \src "ls180.v:7484.4-7486.7" - switch $eq$ls180.v:7484$2318_Y - attribute \src "ls180.v:7484.8-7484.55" - case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1 - case - end - case - end - end - attribute \src "ls180.v:7490.2-7496.5" - switch $not$ls180.v:7490$2319_Y - attribute \src "ls180.v:7490.6-7490.23" - case 1'1 - assign $0\main_sdram_time0[4:0] 5'11111 - attribute \src "ls180.v:7492.6-7492.10" - case - attribute \src "ls180.v:7493.3-7495.6" - switch $not$ls180.v:7493$2320_Y - attribute \src "ls180.v:7493.7-7493.30" - case 1'1 - assign $0\main_sdram_time0[4:0] $sub$ls180.v:7494$2321_Y - case - end - end - attribute \src "ls180.v:7497.2-7503.5" - switch $not$ls180.v:7497$2322_Y - attribute \src "ls180.v:7497.6-7497.23" - case 1'1 - assign $0\main_sdram_time1[3:0] 4'1111 - attribute \src "ls180.v:7499.6-7499.10" - case - attribute \src "ls180.v:7500.3-7502.6" - switch $not$ls180.v:7500$2323_Y - attribute \src "ls180.v:7500.7-7500.30" - case 1'1 - assign $0\main_sdram_time1[3:0] $sub$ls180.v:7501$2324_Y - case - end - end - attribute \src "ls180.v:7504.2-7559.5" - switch \main_sdram_choose_cmd_ce - attribute \src "ls180.v:7504.6-7504.30" - case 1'1 - attribute \src "ls180.v:7505.3-7558.10" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - attribute \src "ls180.v:7507.5-7517.8" - switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7507.9-7507.41" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:7509.9-7509.13" - case - attribute \src "ls180.v:7510.6-7516.9" - switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7510.10-7510.42" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:7512.10-7512.14" - case - attribute \src "ls180.v:7513.7-7515.10" - switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7513.11-7513.43" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - case - end - end - end - attribute \src "ls180.v:0.0-0.0" - case 2'01 - attribute \src "ls180.v:7520.5-7530.8" - switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7520.9-7520.41" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:7522.9-7522.13" - case - attribute \src "ls180.v:7523.6-7529.9" - switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7523.10-7523.42" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:7525.10-7525.14" - case - attribute \src "ls180.v:7526.7-7528.10" - switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7526.11-7526.43" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - case - end - end - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - attribute \src "ls180.v:7533.5-7543.8" - switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7533.9-7533.41" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:7535.9-7535.13" - case - attribute \src "ls180.v:7536.6-7542.9" - switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7536.10-7536.42" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:7538.10-7538.14" - case - attribute \src "ls180.v:7539.7-7541.10" - switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7539.11-7539.43" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - case - end - end - end - attribute \src "ls180.v:0.0-0.0" - case 2'11 - attribute \src "ls180.v:7546.5-7556.8" - switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7546.9-7546.41" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:7548.9-7548.13" - case - attribute \src "ls180.v:7549.6-7555.9" - switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7549.10-7549.42" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:7551.10-7551.14" - case - attribute \src "ls180.v:7552.7-7554.10" - switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7552.11-7552.43" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - case - end - end - end - case - end - case - end - attribute \src "ls180.v:7560.2-7615.5" - switch \main_sdram_choose_req_ce - attribute \src "ls180.v:7560.6-7560.30" - case 1'1 - attribute \src "ls180.v:7561.3-7614.10" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - attribute \src "ls180.v:7563.5-7573.8" - switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7563.9-7563.41" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:7565.9-7565.13" - case - attribute \src "ls180.v:7566.6-7572.9" - switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7566.10-7566.42" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:7568.10-7568.14" - case - attribute \src "ls180.v:7569.7-7571.10" - switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7569.11-7569.43" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'11 - case - end - end - end - attribute \src "ls180.v:0.0-0.0" - case 2'01 - attribute \src "ls180.v:7576.5-7586.8" - switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7576.9-7576.41" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:7578.9-7578.13" - case - attribute \src "ls180.v:7579.6-7585.9" - switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7579.10-7579.42" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:7581.10-7581.14" - case - attribute \src "ls180.v:7582.7-7584.10" - switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7582.11-7582.43" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'00 - case - end - end - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - attribute \src "ls180.v:7589.5-7599.8" - switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7589.9-7589.41" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:7591.9-7591.13" - case - attribute \src "ls180.v:7592.6-7598.9" - switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7592.10-7592.42" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:7594.10-7594.14" - case - attribute \src "ls180.v:7595.7-7597.10" - switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7595.11-7595.43" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'01 - case - end - end - end - attribute \src "ls180.v:0.0-0.0" - case 2'11 - attribute \src "ls180.v:7602.5-7612.8" - switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7602.9-7602.41" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:7604.9-7604.13" - case - attribute \src "ls180.v:7605.6-7611.9" - switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7605.10-7605.42" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:7607.10-7607.14" - case - attribute \src "ls180.v:7608.7-7610.10" - switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7608.11-7608.43" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'10 - case - end - end - end - case - end - case - end - attribute \src "ls180.v:7624.2-7638.5" - switch \main_sdram_tccdcon_valid - attribute \src "ls180.v:7624.6-7624.30" - case 1'1 - assign $0\main_sdram_tccdcon_count[0:0] 1'0 - attribute \src "ls180.v:7626.3-7630.6" - switch 1'1 - attribute \src "ls180.v:7626.7-7626.11" - case 1'1 - assign $0\main_sdram_tccdcon_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:7631.6-7631.10" - case - attribute \src "ls180.v:7632.3-7637.6" - switch $not$ls180.v:7632$2328_Y - attribute \src "ls180.v:7632.7-7632.34" - case 1'1 - assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:7633$2329_Y - attribute \src "ls180.v:7634.4-7636.7" - switch $eq$ls180.v:7634$2330_Y - attribute \src "ls180.v:7634.8-7634.42" - case 1'1 - assign $0\main_sdram_tccdcon_ready[0:0] 1'1 - case - end - case - end - end - attribute \src "ls180.v:7639.2-7653.5" - switch \main_sdram_twtrcon_valid - attribute \src "ls180.v:7639.6-7639.30" - case 1'1 - assign $0\main_sdram_twtrcon_count[2:0] 3'100 - attribute \src "ls180.v:7641.3-7645.6" - switch 1'0 - attribute \src "ls180.v:7643.7-7643.11" - case - assign $0\main_sdram_twtrcon_ready[0:0] 1'0 - end - attribute \src "ls180.v:7646.6-7646.10" - case - attribute \src "ls180.v:7647.3-7652.6" - switch $not$ls180.v:7647$2331_Y - attribute \src "ls180.v:7647.7-7647.34" - case 1'1 - assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:7648$2332_Y - attribute \src "ls180.v:7649.4-7651.7" - switch $eq$ls180.v:7649$2333_Y - attribute \src "ls180.v:7649.8-7649.42" - case 1'1 - assign $0\main_sdram_twtrcon_ready[0:0] 1'1 - case - end - case - end - end - attribute \src "ls180.v:7660.2-7662.5" - switch $or$ls180.v:7660$2358_Y - attribute \src "ls180.v:7660.6-7660.50" - case 1'1 - assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r - case - end - attribute \src "ls180.v:7664.2-7666.5" - switch \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:7664.6-7664.52" - case 1'1 - assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value - case - end - attribute \src "ls180.v:7667.2-7670.5" - switch \main_converter_reset - attribute \src "ls180.v:7667.6-7667.26" - case 1'1 - assign $0\main_converter_counter[0:0] 1'0 - assign $0\builder_converter_state[0:0] 1'0 - case - end - attribute \src "ls180.v:7671.2-7681.5" - switch \main_litedram_wb_ack - attribute \src "ls180.v:7671.6-7671.26" - case 1'1 - assign $0\main_cmd_consumed[0:0] 1'0 - assign $0\main_wdata_consumed[0:0] 1'0 - attribute \src "ls180.v:7674.6-7674.10" - case - attribute \src "ls180.v:7675.3-7677.6" - switch $and$ls180.v:7675$2359_Y - attribute \src "ls180.v:7675.7-7675.50" - case 1'1 - assign $0\main_cmd_consumed[0:0] 1'1 - case - end - attribute \src "ls180.v:7678.3-7680.6" - switch $and$ls180.v:7678$2360_Y - attribute \src "ls180.v:7678.7-7678.54" - case 1'1 - assign $0\main_wdata_consumed[0:0] 1'1 - case - end - end - attribute \src "ls180.v:7683.2-7690.5" - switch \main_clk_rise - attribute \src "ls180.v:7683.6-7683.19" - case 1'1 - assign $0\spi_master_clk[0:0] \main_clk_enable - attribute \src "ls180.v:7685.6-7685.10" - case - attribute \src "ls180.v:7686.3-7689.6" - switch \main_clk_fall - attribute \src "ls180.v:7686.7-7686.20" - case 1'1 - assign $0\main_clk_divider1[15:0] 16'0000000000000000 - assign $0\spi_master_clk[0:0] 1'0 - case - end - end - attribute \src "ls180.v:7692.2-7702.5" - switch \main_mosi_latch - attribute \src "ls180.v:7692.6-7692.21" - case 1'1 - assign $0\main_mosi_data[7:0] \main_mosi - assign $0\main_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:7695.6-7695.10" - case - attribute \src "ls180.v:7696.3-7701.6" - switch \main_clk_fall - attribute \src "ls180.v:7696.7-7696.20" - case 1'1 - assign $0\main_mosi_sel[2:0] $sub$ls180.v:7700$2365_Y - attribute \src "ls180.v:7697.4-7699.7" - switch \main_cs_enable - attribute \src "ls180.v:7697.8-7697.22" - case 1'1 - assign $0\spi_master_mosi[0:0] \builder_sync_f_array_muxed0 - case - end - case - end - end - attribute \src "ls180.v:7703.2-7709.5" - switch \main_clk_rise - attribute \src "ls180.v:7703.6-7703.19" - case 1'1 - attribute \src "ls180.v:7704.3-7708.6" - switch \main_loopback - attribute \src "ls180.v:7704.7-7704.20" - case 1'1 - assign $0\main_miso_data[7:0] { \main_miso_data [6:0] \spi_master_mosi } - attribute \src "ls180.v:7706.7-7706.11" - case - assign $0\main_miso_data[7:0] { \main_miso_data [6:0] \spi_master_miso } - end - case - end - attribute \src "ls180.v:7710.2-7712.5" - switch \main_miso_latch - attribute \src "ls180.v:7710.6-7710.21" - case 1'1 - assign $0\main_miso[7:0] \main_miso_data - case - end - attribute \src "ls180.v:7714.2-7716.5" - switch \main_count_spimaster0_next_value_ce - attribute \src "ls180.v:7714.6-7714.41" - case 1'1 - assign $0\main_count[2:0] \main_count_spimaster0_next_value - case - end - attribute \src "ls180.v:7717.2-7719.5" - switch $not$ls180.v:7717$2366_Y - attribute \src "ls180.v:7717.6-7717.33" - case 1'1 - assign $0\libresocsim_clocker_clks[8:0] $add$ls180.v:7718$2367_Y - case - end - attribute \src "ls180.v:7723.2-7725.5" - switch \libresocsim_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:7723.6-7723.58" - case 1'1 - assign $0\libresocsim_init_count[7:0] \libresocsim_init_count_sdphy_sdphyinit_next_value - case - end - attribute \src "ls180.v:7727.2-7729.5" - switch \libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:7727.6-7727.58" - case 1'1 - assign $0\libresocsim_cmdw_count[7:0] \libresocsim_cmdw_count_sdphy_sdphycmdw_next_value - case - end - attribute \src "ls180.v:7730.2-7732.5" - switch \libresocsim_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:7730.6-7730.41" - case 1'1 - assign $0\libresocsim_cmdr_cmdr_run[0:0] $or$ls180.v:7731$2368_Y - case - end - attribute \src "ls180.v:7733.2-7735.5" - switch \libresocsim_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:7733.6-7733.50" - case 1'1 - assign $0\libresocsim_cmdr_cmdr_converter_strobe_all[0:0] 1'0 - case - end - attribute \src "ls180.v:7736.2-7743.5" - switch \libresocsim_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:7736.6-7736.47" - case 1'1 - attribute \src "ls180.v:7737.3-7742.6" - switch $or$ls180.v:7737$2370_Y - attribute \src "ls180.v:7737.7-7737.100" - case 1'1 - assign $0\libresocsim_cmdr_cmdr_converter_demux[2:0] 3'000 - assign $0\libresocsim_cmdr_cmdr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:7740.7-7740.11" - case - assign $0\libresocsim_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:7741$2371_Y - end - case - end - attribute \src "ls180.v:7744.2-7757.5" - switch $and$ls180.v:7744$2372_Y - attribute \src "ls180.v:7744.6-7744.99" - case 1'1 - attribute \src "ls180.v:7745.3-7751.6" - switch $and$ls180.v:7745$2373_Y - attribute \src "ls180.v:7745.7-7745.96" - case 1'1 - assign $0\libresocsim_cmdr_cmdr_converter_source_first[0:0] \libresocsim_cmdr_cmdr_converter_sink_first - assign $0\libresocsim_cmdr_cmdr_converter_source_last[0:0] \libresocsim_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:7748.7-7748.11" - case - assign $0\libresocsim_cmdr_cmdr_converter_source_first[0:0] 1'0 - assign $0\libresocsim_cmdr_cmdr_converter_source_last[0:0] 1'0 - end - attribute \src "ls180.v:7752.6-7752.10" - case - attribute \src "ls180.v:7753.3-7756.6" - switch $and$ls180.v:7753$2374_Y - attribute \src "ls180.v:7753.7-7753.96" - case 1'1 - assign $0\libresocsim_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:7754$2375_Y - assign $0\libresocsim_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:7755$2376_Y - case - end - end - attribute \src "ls180.v:7758.2-7785.5" - switch \libresocsim_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:7758.6-7758.47" - case 1'1 - attribute \src "ls180.v:7759.3-7784.10" - switch \libresocsim_cmdr_cmdr_converter_demux - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] [7] \libresocsim_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] [6] \libresocsim_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] [5] \libresocsim_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] [4] \libresocsim_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] [3] \libresocsim_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] [2] \libresocsim_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] [1] \libresocsim_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] [0] \libresocsim_cmdr_cmdr_converter_sink_payload_data - case - end - case - end - attribute \src "ls180.v:7786.2-7788.5" - switch \libresocsim_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:7786.6-7786.47" - case 1'1 - assign $0\libresocsim_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:7787$2377_Y - case - end - attribute \src "ls180.v:7789.2-7794.5" - switch $or$ls180.v:7789$2379_Y - attribute \src "ls180.v:7789.6-7789.90" - case 1'1 - assign $0\libresocsim_cmdr_cmdr_buf_source_valid[0:0] \libresocsim_cmdr_cmdr_buf_sink_valid - assign $0\libresocsim_cmdr_cmdr_buf_source_first[0:0] \libresocsim_cmdr_cmdr_buf_sink_first - assign $0\libresocsim_cmdr_cmdr_buf_source_last[0:0] \libresocsim_cmdr_cmdr_buf_sink_last - assign $0\libresocsim_cmdr_cmdr_buf_source_payload_data[7:0] \libresocsim_cmdr_cmdr_buf_sink_payload_data - case - end - attribute \src "ls180.v:7795.2-7800.5" - switch \libresocsim_cmdr_cmdr_reset - attribute \src "ls180.v:7795.6-7795.33" - case 1'1 - assign $0\libresocsim_cmdr_cmdr_run[0:0] 1'0 - assign $0\libresocsim_cmdr_cmdr_converter_demux[2:0] 3'000 - assign $0\libresocsim_cmdr_cmdr_converter_strobe_all[0:0] 1'0 - assign $0\libresocsim_cmdr_cmdr_buf_source_valid[0:0] 1'0 - case - end - attribute \src "ls180.v:7802.2-7804.5" - switch \libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:7802.6-7802.59" - case 1'1 - assign $0\libresocsim_cmdr_count[7:0] \libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0 - case - end - attribute \src "ls180.v:7805.2-7807.5" - switch \libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:7805.6-7805.61" - case 1'1 - assign $0\libresocsim_cmdr_timeout[31:0] \libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1 - case - end - attribute \src "ls180.v:7808.2-7810.5" - switch \libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:7808.6-7808.64" - case 1'1 - assign $0\libresocsim_cmdr_cmdr_reset[0:0] \libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 - case - end - attribute \src "ls180.v:7811.2-7813.5" - switch \libresocsim_dataw_crcr_pads_in_valid - attribute \src "ls180.v:7811.6-7811.42" - case 1'1 - assign $0\libresocsim_dataw_crcr_run[0:0] $or$ls180.v:7812$2380_Y - case - end - attribute \src "ls180.v:7814.2-7816.5" - switch \libresocsim_dataw_crcr_converter_source_ready - attribute \src "ls180.v:7814.6-7814.51" - case 1'1 - assign $0\libresocsim_dataw_crcr_converter_strobe_all[0:0] 1'0 - case - end - attribute \src "ls180.v:7817.2-7824.5" - switch \libresocsim_dataw_crcr_converter_load_part - attribute \src "ls180.v:7817.6-7817.48" - case 1'1 - attribute \src "ls180.v:7818.3-7823.6" - switch $or$ls180.v:7818$2382_Y - attribute \src "ls180.v:7818.7-7818.102" - case 1'1 - assign $0\libresocsim_dataw_crcr_converter_demux[2:0] 3'000 - assign $0\libresocsim_dataw_crcr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:7821.7-7821.11" - case - assign $0\libresocsim_dataw_crcr_converter_demux[2:0] $add$ls180.v:7822$2383_Y - end - case - end - attribute \src "ls180.v:7825.2-7838.5" - switch $and$ls180.v:7825$2384_Y - attribute \src "ls180.v:7825.6-7825.101" - case 1'1 - attribute \src "ls180.v:7826.3-7832.6" - switch $and$ls180.v:7826$2385_Y - attribute \src "ls180.v:7826.7-7826.98" - case 1'1 - assign $0\libresocsim_dataw_crcr_converter_source_first[0:0] \libresocsim_dataw_crcr_converter_sink_first - assign $0\libresocsim_dataw_crcr_converter_source_last[0:0] \libresocsim_dataw_crcr_converter_sink_last - attribute \src "ls180.v:7829.7-7829.11" - case - assign $0\libresocsim_dataw_crcr_converter_source_first[0:0] 1'0 - assign $0\libresocsim_dataw_crcr_converter_source_last[0:0] 1'0 - end - attribute \src "ls180.v:7833.6-7833.10" - case - attribute \src "ls180.v:7834.3-7837.6" - switch $and$ls180.v:7834$2386_Y - attribute \src "ls180.v:7834.7-7834.98" - case 1'1 - assign $0\libresocsim_dataw_crcr_converter_source_first[0:0] $or$ls180.v:7835$2387_Y - assign $0\libresocsim_dataw_crcr_converter_source_last[0:0] $or$ls180.v:7836$2388_Y - case - end - end - attribute \src "ls180.v:7839.2-7866.5" - switch \libresocsim_dataw_crcr_converter_load_part - attribute \src "ls180.v:7839.6-7839.48" - case 1'1 - attribute \src "ls180.v:7840.3-7865.10" - switch \libresocsim_dataw_crcr_converter_demux - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\libresocsim_dataw_crcr_converter_source_payload_data[7:0] [7] \libresocsim_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\libresocsim_dataw_crcr_converter_source_payload_data[7:0] [6] \libresocsim_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\libresocsim_dataw_crcr_converter_source_payload_data[7:0] [5] \libresocsim_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\libresocsim_dataw_crcr_converter_source_payload_data[7:0] [4] \libresocsim_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\libresocsim_dataw_crcr_converter_source_payload_data[7:0] [3] \libresocsim_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\libresocsim_dataw_crcr_converter_source_payload_data[7:0] [2] \libresocsim_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\libresocsim_dataw_crcr_converter_source_payload_data[7:0] [1] \libresocsim_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\libresocsim_dataw_crcr_converter_source_payload_data[7:0] [0] \libresocsim_dataw_crcr_converter_sink_payload_data - case - end - case - end - attribute \src "ls180.v:7867.2-7869.5" - switch \libresocsim_dataw_crcr_converter_load_part - attribute \src "ls180.v:7867.6-7867.48" - case 1'1 - assign $0\libresocsim_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:7868$2389_Y - case - end - attribute \src "ls180.v:7870.2-7875.5" - switch $or$ls180.v:7870$2391_Y - attribute \src "ls180.v:7870.6-7870.92" - case 1'1 - assign $0\libresocsim_dataw_crcr_buf_source_valid[0:0] \libresocsim_dataw_crcr_buf_sink_valid - assign $0\libresocsim_dataw_crcr_buf_source_first[0:0] \libresocsim_dataw_crcr_buf_sink_first - assign $0\libresocsim_dataw_crcr_buf_source_last[0:0] \libresocsim_dataw_crcr_buf_sink_last - assign $0\libresocsim_dataw_crcr_buf_source_payload_data[7:0] \libresocsim_dataw_crcr_buf_sink_payload_data - case - end - attribute \src "ls180.v:7876.2-7881.5" - switch \libresocsim_dataw_crcr_reset - attribute \src "ls180.v:7876.6-7876.34" - case 1'1 - assign $0\libresocsim_dataw_crcr_run[0:0] 1'0 - assign $0\libresocsim_dataw_crcr_converter_demux[2:0] 3'000 - assign $0\libresocsim_dataw_crcr_converter_strobe_all[0:0] 1'0 - assign $0\libresocsim_dataw_crcr_buf_source_valid[0:0] 1'0 - case - end - attribute \src "ls180.v:7883.2-7885.5" - switch \libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:7883.6-7883.64" - case 1'1 - assign $0\libresocsim_dataw_crcr_reset[0:0] \libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value - case - end - attribute \src "ls180.v:7887.2-7889.5" - switch \libresocsim_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:7887.6-7887.53" - case 1'1 - assign $0\libresocsim_dataw_count[7:0] \libresocsim_dataw_count_sdphy_fsm_next_value - case - end - attribute \src "ls180.v:7890.2-7892.5" - switch \libresocsim_datar_datar_pads_in_valid - attribute \src "ls180.v:7890.6-7890.43" - case 1'1 - assign $0\libresocsim_datar_datar_run[0:0] $or$ls180.v:7891$2392_Y - case - end - attribute \src "ls180.v:7893.2-7895.5" - switch \libresocsim_datar_datar_converter_source_ready - attribute \src "ls180.v:7893.6-7893.52" - case 1'1 - assign $0\libresocsim_datar_datar_converter_strobe_all[0:0] 1'0 - case - end - attribute \src "ls180.v:7896.2-7903.5" - switch \libresocsim_datar_datar_converter_load_part - attribute \src "ls180.v:7896.6-7896.49" - case 1'1 - attribute \src "ls180.v:7897.3-7902.6" - switch $or$ls180.v:7897$2394_Y - attribute \src "ls180.v:7897.7-7897.104" - case 1'1 - assign $0\libresocsim_datar_datar_converter_demux[0:0] 1'0 - assign $0\libresocsim_datar_datar_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:7900.7-7900.11" - case - assign $0\libresocsim_datar_datar_converter_demux[0:0] $add$ls180.v:7901$2395_Y - end - case - end - attribute \src "ls180.v:7904.2-7917.5" - switch $and$ls180.v:7904$2396_Y - attribute \src "ls180.v:7904.6-7904.103" - case 1'1 - attribute \src "ls180.v:7905.3-7911.6" - switch $and$ls180.v:7905$2397_Y - attribute \src "ls180.v:7905.7-7905.100" - case 1'1 - assign $0\libresocsim_datar_datar_converter_source_first[0:0] \libresocsim_datar_datar_converter_sink_first - assign $0\libresocsim_datar_datar_converter_source_last[0:0] \libresocsim_datar_datar_converter_sink_last - attribute \src "ls180.v:7908.7-7908.11" - case - assign $0\libresocsim_datar_datar_converter_source_first[0:0] 1'0 - assign $0\libresocsim_datar_datar_converter_source_last[0:0] 1'0 - end - attribute \src "ls180.v:7912.6-7912.10" - case - attribute \src "ls180.v:7913.3-7916.6" - switch $and$ls180.v:7913$2398_Y - attribute \src "ls180.v:7913.7-7913.100" - case 1'1 - assign $0\libresocsim_datar_datar_converter_source_first[0:0] $or$ls180.v:7914$2399_Y - assign $0\libresocsim_datar_datar_converter_source_last[0:0] $or$ls180.v:7915$2400_Y - case - end - end - attribute \src "ls180.v:7918.2-7927.5" - switch \libresocsim_datar_datar_converter_load_part - attribute \src "ls180.v:7918.6-7918.49" - case 1'1 - attribute \src "ls180.v:7919.3-7926.10" - switch \libresocsim_datar_datar_converter_demux - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\libresocsim_datar_datar_converter_source_payload_data[7:0] [7:4] \libresocsim_datar_datar_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\libresocsim_datar_datar_converter_source_payload_data[7:0] [3:0] \libresocsim_datar_datar_converter_sink_payload_data - case - end - case - end - attribute \src "ls180.v:7928.2-7930.5" - switch \libresocsim_datar_datar_converter_load_part - attribute \src "ls180.v:7928.6-7928.49" - case 1'1 - assign $0\libresocsim_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:7929$2401_Y - case - end - attribute \src "ls180.v:7931.2-7936.5" - switch $or$ls180.v:7931$2403_Y - attribute \src "ls180.v:7931.6-7931.94" - case 1'1 - assign $0\libresocsim_datar_datar_buf_source_valid[0:0] \libresocsim_datar_datar_buf_sink_valid - assign $0\libresocsim_datar_datar_buf_source_first[0:0] \libresocsim_datar_datar_buf_sink_first - assign $0\libresocsim_datar_datar_buf_source_last[0:0] \libresocsim_datar_datar_buf_sink_last - assign $0\libresocsim_datar_datar_buf_source_payload_data[7:0] \libresocsim_datar_datar_buf_sink_payload_data - case - end - attribute \src "ls180.v:7937.2-7942.5" - switch \libresocsim_datar_datar_reset - attribute \src "ls180.v:7937.6-7937.35" - case 1'1 - assign $0\libresocsim_datar_datar_run[0:0] 1'0 - assign $0\libresocsim_datar_datar_converter_demux[0:0] 1'0 - assign $0\libresocsim_datar_datar_converter_strobe_all[0:0] 1'0 - assign $0\libresocsim_datar_datar_buf_source_valid[0:0] 1'0 - case - end - attribute \src "ls180.v:7944.2-7946.5" - switch \libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:7944.6-7944.61" - case 1'1 - assign $0\libresocsim_datar_count[9:0] \libresocsim_datar_count_sdphy_sdphydatar_next_value0 - case - end - attribute \src "ls180.v:7947.2-7949.5" - switch \libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:7947.6-7947.63" - case 1'1 - assign $0\libresocsim_datar_timeout[31:0] \libresocsim_datar_timeout_sdphy_sdphydatar_next_value1 - case - end - attribute \src "ls180.v:7950.2-7952.5" - switch \libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:7950.6-7950.67" - case 1'1 - assign $0\libresocsim_datar_datar_reset[0:0] \libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value2 - case - end - attribute \src "ls180.v:7953.2-7959.5" - switch \libresocsim_sdcore_crc7_inserter_clr - attribute \src "ls180.v:7953.6-7953.42" - case 1'1 - assign $0\libresocsim_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - attribute \src "ls180.v:7955.6-7955.10" - case - attribute \src "ls180.v:7956.3-7958.6" - switch \libresocsim_sdcore_crc7_inserter_enable - attribute \src "ls180.v:7956.7-7956.46" - case 1'1 - assign $0\libresocsim_sdcore_crc7_inserter_crcreg0[6:0] \libresocsim_sdcore_crc7_inserter_crcreg40 - case - end - end - attribute \src "ls180.v:7960.2-7966.5" - switch \libresocsim_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:7960.6-7960.48" - case 1'1 - assign $0\libresocsim_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:7962.6-7962.10" - case - attribute \src "ls180.v:7963.3-7965.6" - switch \libresocsim_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:7963.7-7963.52" - case 1'1 - assign $0\libresocsim_sdcore_crc16_inserter_crc0_crcreg0[15:0] \libresocsim_sdcore_crc16_inserter_crc0_crcreg2 - case - end - end - attribute \src "ls180.v:7967.2-7973.5" - switch \libresocsim_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:7967.6-7967.48" - case 1'1 - assign $0\libresocsim_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:7969.6-7969.10" - case - attribute \src "ls180.v:7970.3-7972.6" - switch \libresocsim_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:7970.7-7970.52" - case 1'1 - assign $0\libresocsim_sdcore_crc16_inserter_crc1_crcreg0[15:0] \libresocsim_sdcore_crc16_inserter_crc1_crcreg2 - case - end - end - attribute \src "ls180.v:7974.2-7980.5" - switch \libresocsim_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:7974.6-7974.48" - case 1'1 - assign $0\libresocsim_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:7976.6-7976.10" - case - attribute \src "ls180.v:7977.3-7979.6" - switch \libresocsim_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:7977.7-7977.52" - case 1'1 - assign $0\libresocsim_sdcore_crc16_inserter_crc2_crcreg0[15:0] \libresocsim_sdcore_crc16_inserter_crc2_crcreg2 - case - end - end - attribute \src "ls180.v:7981.2-7987.5" - switch \libresocsim_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:7981.6-7981.48" - case 1'1 - assign $0\libresocsim_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:7983.6-7983.10" - case - attribute \src "ls180.v:7984.3-7986.6" - switch \libresocsim_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:7984.7-7984.52" - case 1'1 - assign $0\libresocsim_sdcore_crc16_inserter_crc3_crcreg0[15:0] \libresocsim_sdcore_crc16_inserter_crc3_crcreg2 - case - end - end - attribute \src "ls180.v:7989.2-7991.5" - switch \libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:7989.6-7989.89" - case 1'1 - assign $0\libresocsim_sdcore_crc16_inserter_crctmp0[15:0] \libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 - case - end - attribute \src "ls180.v:7992.2-7994.5" - switch \libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:7992.6-7992.89" - case 1'1 - assign $0\libresocsim_sdcore_crc16_inserter_crctmp1[15:0] \libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 - case - end - attribute \src "ls180.v:7995.2-7997.5" - switch \libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:7995.6-7995.89" - case 1'1 - assign $0\libresocsim_sdcore_crc16_inserter_crctmp2[15:0] \libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 - case - end - attribute \src "ls180.v:7998.2-8000.5" - switch \libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:7998.6-7998.89" - case 1'1 - assign $0\libresocsim_sdcore_crc16_inserter_crctmp3[15:0] \libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 - case - end - attribute \src "ls180.v:8001.2-8003.5" - switch \libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:8001.6-8001.85" - case 1'1 - assign $0\libresocsim_sdcore_crc16_inserter_cnt[2:0] \libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 - case - end - attribute \src "ls180.v:8004.2-8006.5" - switch $and$ls180.v:8004$2404_Y - attribute \src "ls180.v:8004.6-8004.97" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_crctmp0[15:0] \libresocsim_sdcore_crc16_checker_crc0_crc - case - end - attribute \src "ls180.v:8007.2-8009.5" - switch $and$ls180.v:8007$2405_Y - attribute \src "ls180.v:8007.6-8007.97" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_crctmp1[15:0] \libresocsim_sdcore_crc16_checker_crc1_crc - case - end - attribute \src "ls180.v:8010.2-8012.5" - switch $and$ls180.v:8010$2406_Y - attribute \src "ls180.v:8010.6-8010.97" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_crctmp2[15:0] \libresocsim_sdcore_crc16_checker_crc2_crc - case - end - attribute \src "ls180.v:8013.2-8015.5" - switch $and$ls180.v:8013$2407_Y - attribute \src "ls180.v:8013.6-8013.97" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_crctmp3[15:0] \libresocsim_sdcore_crc16_checker_crc3_crc - case - end - attribute \src "ls180.v:8016.2-8020.5" - switch $and$ls180.v:8016$2408_Y - attribute \src "ls180.v:8016.6-8016.97" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_fifo0[15:0] { \libresocsim_sdcore_crc16_checker_fifo0 [13:0] \libresocsim_sdcore_crc16_checker_sink_payload_data [7] \libresocsim_sdcore_crc16_checker_sink_payload_data [3] } - assign $0\libresocsim_sdcore_crc16_checker_val[7:0] [7] \libresocsim_sdcore_crc16_checker_fifo0 [13] - assign $0\libresocsim_sdcore_crc16_checker_val[7:0] [3] \libresocsim_sdcore_crc16_checker_fifo0 [12] - case - end - attribute \src "ls180.v:8021.2-8025.5" - switch $and$ls180.v:8021$2409_Y - attribute \src "ls180.v:8021.6-8021.97" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_fifo1[15:0] { \libresocsim_sdcore_crc16_checker_fifo1 [13:0] \libresocsim_sdcore_crc16_checker_sink_payload_data [6] \libresocsim_sdcore_crc16_checker_sink_payload_data [2] } - assign $0\libresocsim_sdcore_crc16_checker_val[7:0] [6] \libresocsim_sdcore_crc16_checker_fifo1 [13] - assign $0\libresocsim_sdcore_crc16_checker_val[7:0] [2] \libresocsim_sdcore_crc16_checker_fifo1 [12] - case - end - attribute \src "ls180.v:8026.2-8030.5" - switch $and$ls180.v:8026$2410_Y - attribute \src "ls180.v:8026.6-8026.97" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_fifo2[15:0] { \libresocsim_sdcore_crc16_checker_fifo2 [13:0] \libresocsim_sdcore_crc16_checker_sink_payload_data [5] \libresocsim_sdcore_crc16_checker_sink_payload_data [1] } - assign $0\libresocsim_sdcore_crc16_checker_val[7:0] [5] \libresocsim_sdcore_crc16_checker_fifo2 [13] - assign $0\libresocsim_sdcore_crc16_checker_val[7:0] [1] \libresocsim_sdcore_crc16_checker_fifo2 [12] - case - end - attribute \src "ls180.v:8031.2-8035.5" - switch $and$ls180.v:8031$2411_Y - attribute \src "ls180.v:8031.6-8031.97" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_fifo3[15:0] { \libresocsim_sdcore_crc16_checker_fifo3 [13:0] \libresocsim_sdcore_crc16_checker_sink_payload_data [4] \libresocsim_sdcore_crc16_checker_sink_payload_data [0] } - assign $0\libresocsim_sdcore_crc16_checker_val[7:0] [4] \libresocsim_sdcore_crc16_checker_fifo3 [13] - assign $0\libresocsim_sdcore_crc16_checker_val[7:0] [0] \libresocsim_sdcore_crc16_checker_fifo3 [12] - case - end - attribute \src "ls180.v:8036.2-8044.5" - switch $and$ls180.v:8036$2412_Y - attribute \src "ls180.v:8036.6-8036.97" - case 1'1 - attribute \src "ls180.v:8037.3-8043.6" - switch \libresocsim_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:8037.7-8037.49" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_cnt[3:0] 4'0000 - attribute \src "ls180.v:8039.7-8039.11" - case - attribute \src "ls180.v:8040.4-8042.7" - switch $ne$ls180.v:8040$2413_Y - attribute \src "ls180.v:8040.8-8040.55" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8041$2414_Y - case - end - end - case - end - attribute \src "ls180.v:8045.2-8051.5" - switch \libresocsim_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:8045.6-8045.47" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8047.6-8047.10" - case - attribute \src "ls180.v:8048.3-8050.6" - switch \libresocsim_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:8048.7-8048.51" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_crc0_crcreg0[15:0] \libresocsim_sdcore_crc16_checker_crc0_crcreg2 - case - end - end - attribute \src "ls180.v:8052.2-8058.5" - switch \libresocsim_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:8052.6-8052.47" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8054.6-8054.10" - case - attribute \src "ls180.v:8055.3-8057.6" - switch \libresocsim_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:8055.7-8055.51" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_crc1_crcreg0[15:0] \libresocsim_sdcore_crc16_checker_crc1_crcreg2 - case - end - end - attribute \src "ls180.v:8059.2-8065.5" - switch \libresocsim_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:8059.6-8059.47" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8061.6-8061.10" - case - attribute \src "ls180.v:8062.3-8064.6" - switch \libresocsim_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:8062.7-8062.51" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_crc2_crcreg0[15:0] \libresocsim_sdcore_crc16_checker_crc2_crcreg2 - case - end - end - attribute \src "ls180.v:8066.2-8072.5" - switch \libresocsim_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:8066.6-8066.47" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8068.6-8068.10" - case - attribute \src "ls180.v:8069.3-8071.6" - switch \libresocsim_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:8069.7-8069.51" - case 1'1 - assign $0\libresocsim_sdcore_crc16_checker_crc3_crcreg0[15:0] \libresocsim_sdcore_crc16_checker_crc3_crcreg2 - case - end - end - attribute \src "ls180.v:8074.2-8076.5" - switch \libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:8074.6-8074.59" - case 1'1 - assign $0\libresocsim_sdcore_cmd_done[0:0] \libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0 - case - end - attribute \src "ls180.v:8077.2-8079.5" - switch \libresocsim_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:8077.6-8077.60" - case 1'1 - assign $0\libresocsim_sdcore_data_done[0:0] \libresocsim_sdcore_data_done_sdcore_fsm_next_value1 - case - end - attribute \src "ls180.v:8080.2-8082.5" - switch \libresocsim_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:8080.6-8080.60" - case 1'1 - assign $0\libresocsim_sdcore_cmd_count[2:0] \libresocsim_sdcore_cmd_count_sdcore_fsm_next_value2 - case - end - attribute \src "ls180.v:8083.2-8085.5" - switch \libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:8083.6-8083.61" - case 1'1 - assign $0\libresocsim_sdcore_data_count[31:0] \libresocsim_sdcore_data_count_sdcore_fsm_next_value3 - case - end - attribute \src "ls180.v:8086.2-8088.5" - switch \libresocsim_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:8086.6-8086.60" - case 1'1 - assign $0\libresocsim_sdcore_cmd_error[0:0] \libresocsim_sdcore_cmd_error_sdcore_fsm_next_value4 - case - end - attribute \src "ls180.v:8089.2-8091.5" - switch \libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:8089.6-8089.62" - case 1'1 - assign $0\libresocsim_sdcore_cmd_timeout[0:0] \libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value5 - case - end - attribute \src "ls180.v:8092.2-8094.5" - switch \libresocsim_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:8092.6-8092.61" - case 1'1 - assign $0\libresocsim_sdcore_data_error[0:0] \libresocsim_sdcore_data_error_sdcore_fsm_next_value6 - case - end - attribute \src "ls180.v:8095.2-8097.5" - switch \libresocsim_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:8095.6-8095.63" - case 1'1 - assign $0\libresocsim_sdcore_data_timeout[0:0] \libresocsim_sdcore_data_timeout_sdcore_fsm_next_value7 - case - end - attribute \src "ls180.v:8098.2-8100.5" - switch \libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:8098.6-8098.70" - case 1'1 - assign $0\libresocsim_sdcore_cmd_response_status[127:0] \libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value8 - case - end - attribute \src "ls180.v:8101.2-8103.5" - switch $and$ls180.v:8101$2417_Y - attribute \src "ls180.v:8101.6-8101.141" - case 1'1 - assign $0\libresocsim_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8102$2418_Y - case - end - attribute \src "ls180.v:8104.2-8106.5" - switch \libresocsim_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8104.6-8104.42" - case 1'1 - assign $0\libresocsim_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8105$2419_Y - case - end - attribute \src "ls180.v:8107.2-8115.5" - switch $and$ls180.v:8107$2422_Y - attribute \src "ls180.v:8107.6-8107.141" - case 1'1 - attribute \src "ls180.v:8108.3-8110.6" - switch $not$ls180.v:8108$2423_Y - attribute \src "ls180.v:8108.7-8108.46" - case 1'1 - assign $0\libresocsim_sdblock2mem_fifo_level[5:0] $add$ls180.v:8109$2424_Y - case - end - attribute \src "ls180.v:8111.6-8111.10" - case - attribute \src "ls180.v:8112.3-8114.6" - switch \libresocsim_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8112.7-8112.43" - case 1'1 - assign $0\libresocsim_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8113$2425_Y - case - end - end - attribute \src "ls180.v:8116.2-8118.5" - switch \libresocsim_sdblock2mem_converter_source_ready - attribute \src "ls180.v:8116.6-8116.52" - case 1'1 - assign $0\libresocsim_sdblock2mem_converter_strobe_all[0:0] 1'0 - case - end - attribute \src "ls180.v:8119.2-8126.5" - switch \libresocsim_sdblock2mem_converter_load_part - attribute \src "ls180.v:8119.6-8119.49" - case 1'1 - attribute \src "ls180.v:8120.3-8125.6" - switch $or$ls180.v:8120$2427_Y - attribute \src "ls180.v:8120.7-8120.104" - case 1'1 - assign $0\libresocsim_sdblock2mem_converter_demux[1:0] 2'00 - assign $0\libresocsim_sdblock2mem_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8123.7-8123.11" - case - assign $0\libresocsim_sdblock2mem_converter_demux[1:0] $add$ls180.v:8124$2428_Y - end - case - end - attribute \src "ls180.v:8127.2-8140.5" - switch $and$ls180.v:8127$2429_Y - attribute \src "ls180.v:8127.6-8127.103" - case 1'1 - attribute \src "ls180.v:8128.3-8134.6" - switch $and$ls180.v:8128$2430_Y - attribute \src "ls180.v:8128.7-8128.100" - case 1'1 - assign $0\libresocsim_sdblock2mem_converter_source_first[0:0] \libresocsim_sdblock2mem_converter_sink_first - assign $0\libresocsim_sdblock2mem_converter_source_last[0:0] \libresocsim_sdblock2mem_converter_sink_last - attribute \src "ls180.v:8131.7-8131.11" - case - assign $0\libresocsim_sdblock2mem_converter_source_first[0:0] 1'0 - assign $0\libresocsim_sdblock2mem_converter_source_last[0:0] 1'0 - end - attribute \src "ls180.v:8135.6-8135.10" - case - attribute \src "ls180.v:8136.3-8139.6" - switch $and$ls180.v:8136$2431_Y - attribute \src "ls180.v:8136.7-8136.100" - case 1'1 - assign $0\libresocsim_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8137$2432_Y - assign $0\libresocsim_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8138$2433_Y - case - end - end - attribute \src "ls180.v:8141.2-8156.5" - switch \libresocsim_sdblock2mem_converter_load_part - attribute \src "ls180.v:8141.6-8141.49" - case 1'1 - attribute \src "ls180.v:8142.3-8155.10" - switch \libresocsim_sdblock2mem_converter_demux - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\libresocsim_sdblock2mem_converter_source_payload_data[31:0] [31:24] \libresocsim_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\libresocsim_sdblock2mem_converter_source_payload_data[31:0] [23:16] \libresocsim_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\libresocsim_sdblock2mem_converter_source_payload_data[31:0] [15:8] \libresocsim_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\libresocsim_sdblock2mem_converter_source_payload_data[31:0] [7:0] \libresocsim_sdblock2mem_converter_sink_payload_data - case - end - case - end - attribute \src "ls180.v:8157.2-8159.5" - switch \libresocsim_sdblock2mem_converter_load_part - attribute \src "ls180.v:8157.6-8157.49" - case 1'1 - assign $0\libresocsim_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$ls180.v:8158$2434_Y - case - end - attribute \src "ls180.v:8161.2-8163.5" - switch \libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:8161.6-8161.83" - case 1'1 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_offset[31:0] \libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value - case - end - attribute \src "ls180.v:8164.2-8167.5" - switch \libresocsim_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:8164.6-8164.53" - case 1'1 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_offset[31:0] 0 - assign $0\builder_sdblock2memdma_state[1:0] 2'00 - case - end - attribute \src "ls180.v:8169.2-8171.5" - switch \libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:8169.6-8169.71" - case 1'1 - assign $0\libresocsim_sdmem2block_dma_data[31:0] \libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value - case - end - attribute \src "ls180.v:8173.2-8175.5" - switch \libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:8173.6-8173.83" - case 1'1 - assign $0\libresocsim_sdmem2block_dma_offset[31:0] \libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value - case - end - attribute \src "ls180.v:8176.2-8179.5" - switch \libresocsim_sdmem2block_dma_reset - attribute \src "ls180.v:8176.6-8176.39" - case 1'1 - assign $0\libresocsim_sdmem2block_dma_offset[31:0] 0 - assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 - case - end - attribute \src "ls180.v:8180.2-8186.5" - switch $and$ls180.v:8180$2435_Y - attribute \src "ls180.v:8180.6-8180.103" - case 1'1 - attribute \src "ls180.v:8181.3-8185.6" - switch \libresocsim_sdmem2block_converter_last - attribute \src "ls180.v:8181.7-8181.45" - case 1'1 - assign $0\libresocsim_sdmem2block_converter_mux[1:0] 2'00 - attribute \src "ls180.v:8183.7-8183.11" - case - assign $0\libresocsim_sdmem2block_converter_mux[1:0] $add$ls180.v:8184$2436_Y - end - case - end - attribute \src "ls180.v:8187.2-8189.5" - switch $and$ls180.v:8187$2439_Y - attribute \src "ls180.v:8187.6-8187.141" - case 1'1 - assign $0\libresocsim_sdmem2block_fifo_produce[4:0] $add$ls180.v:8188$2440_Y - case - end - attribute \src "ls180.v:8190.2-8192.5" - switch \libresocsim_sdmem2block_fifo_do_read - attribute \src "ls180.v:8190.6-8190.42" - case 1'1 - assign $0\libresocsim_sdmem2block_fifo_consume[4:0] $add$ls180.v:8191$2441_Y - case - end - attribute \src "ls180.v:8193.2-8201.5" - switch $and$ls180.v:8193$2444_Y - attribute \src "ls180.v:8193.6-8193.141" - case 1'1 - attribute \src "ls180.v:8194.3-8196.6" - switch $not$ls180.v:8194$2445_Y - attribute \src "ls180.v:8194.7-8194.46" - case 1'1 - assign $0\libresocsim_sdmem2block_fifo_level[5:0] $add$ls180.v:8195$2446_Y - case - end - attribute \src "ls180.v:8197.6-8197.10" - case - attribute \src "ls180.v:8198.3-8200.6" - switch \libresocsim_sdmem2block_fifo_do_read - attribute \src "ls180.v:8198.7-8198.43" - case 1'1 - assign $0\libresocsim_sdmem2block_fifo_level[5:0] $sub$ls180.v:8199$2447_Y - case - end - end - attribute \src "ls180.v:8203.2-8210.5" - switch \libresocsim_clk_rise - attribute \src "ls180.v:8203.6-8203.26" - case 1'1 - assign $0\spisdcard_clk[0:0] \libresocsim_clk_enable - attribute \src "ls180.v:8205.6-8205.10" - case - attribute \src "ls180.v:8206.3-8209.6" - switch \libresocsim_clk_fall - attribute \src "ls180.v:8206.7-8206.27" - case 1'1 - assign $0\libresocsim_clk_divider1[15:0] 16'0000000000000000 - assign $0\spisdcard_clk[0:0] 1'0 - case - end - end - attribute \src "ls180.v:8212.2-8222.5" - switch \libresocsim_mosi_latch - attribute \src "ls180.v:8212.6-8212.28" - case 1'1 - assign $0\libresocsim_mosi_data[7:0] \libresocsim_mosi - assign $0\libresocsim_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8215.6-8215.10" - case - attribute \src "ls180.v:8216.3-8221.6" - switch \libresocsim_clk_fall - attribute \src "ls180.v:8216.7-8216.27" - case 1'1 - assign $0\libresocsim_mosi_sel[2:0] $sub$ls180.v:8220$2452_Y - attribute \src "ls180.v:8217.4-8219.7" - switch \libresocsim_cs_enable - attribute \src "ls180.v:8217.8-8217.29" - case 1'1 - assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed1 - case - end - case - end - end - attribute \src "ls180.v:8223.2-8229.5" - switch \libresocsim_clk_rise - attribute \src "ls180.v:8223.6-8223.26" - case 1'1 - attribute \src "ls180.v:8224.3-8228.6" - switch \libresocsim_loopback - attribute \src "ls180.v:8224.7-8224.27" - case 1'1 - assign $0\libresocsim_miso_data[7:0] { \libresocsim_miso_data [6:0] \spisdcard_mosi } - attribute \src "ls180.v:8226.7-8226.11" - case - assign $0\libresocsim_miso_data[7:0] { \libresocsim_miso_data [6:0] \spisdcard_miso } - end - case - end - attribute \src "ls180.v:8230.2-8232.5" - switch \libresocsim_miso_latch - attribute \src "ls180.v:8230.6-8230.28" - case 1'1 - assign $0\libresocsim_miso[7:0] \libresocsim_miso_data - case - end - attribute \src "ls180.v:8234.2-8236.5" - switch \libresocsim_count_spimaster1_next_value_ce - attribute \src "ls180.v:8234.6-8234.48" - case 1'1 - assign $0\libresocsim_count[2:0] \libresocsim_count_spimaster1_next_value - case - end - attribute \src "ls180.v:8238.2-8240.5" - switch \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:8238.6-8238.46" - case 1'1 - assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0 - case - end - attribute \src "ls180.v:8241.2-8243.5" - switch \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:8241.6-8241.44" - case 1'1 - assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1 - case - end - attribute \src "ls180.v:8244.2-8246.5" - switch \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:8244.6-8244.43" - case 1'1 - assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2 - case - end - attribute \src "ls180.v:8247.2-8308.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - attribute \src "ls180.v:8249.4-8261.7" - switch $not$ls180.v:8249$2453_Y - attribute \src "ls180.v:8249.8-8249.29" - case 1'1 - attribute \src "ls180.v:8250.5-8260.8" - switch \builder_request [1] - attribute \src "ls180.v:8250.9-8250.27" - case 1'1 - assign $0\builder_grant[1:0] 2'01 - attribute \src "ls180.v:8252.9-8252.13" - case - attribute \src "ls180.v:8253.6-8259.9" - switch \builder_request [2] - attribute \src "ls180.v:8253.10-8253.28" - case 1'1 - assign $0\builder_grant[1:0] 2'10 - attribute \src "ls180.v:8255.10-8255.14" - case - attribute \src "ls180.v:8256.7-8258.10" - switch \builder_request [3] - attribute \src "ls180.v:8256.11-8256.29" - case 1'1 - assign $0\builder_grant[1:0] 2'11 - case - end - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'01 - attribute \src "ls180.v:8264.4-8276.7" - switch $not$ls180.v:8264$2454_Y - attribute \src "ls180.v:8264.8-8264.29" - case 1'1 - attribute \src "ls180.v:8265.5-8275.8" - switch \builder_request [2] - attribute \src "ls180.v:8265.9-8265.27" - case 1'1 - assign $0\builder_grant[1:0] 2'10 - attribute \src "ls180.v:8267.9-8267.13" - case - attribute \src "ls180.v:8268.6-8274.9" - switch \builder_request [3] - attribute \src "ls180.v:8268.10-8268.28" - case 1'1 - assign $0\builder_grant[1:0] 2'11 - attribute \src "ls180.v:8270.10-8270.14" - case - attribute \src "ls180.v:8271.7-8273.10" - switch \builder_request [0] - attribute \src "ls180.v:8271.11-8271.29" - case 1'1 - assign $0\builder_grant[1:0] 2'00 - case - end - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - attribute \src "ls180.v:8279.4-8291.7" - switch $not$ls180.v:8279$2455_Y - attribute \src "ls180.v:8279.8-8279.29" - case 1'1 - attribute \src "ls180.v:8280.5-8290.8" - switch \builder_request [3] - attribute \src "ls180.v:8280.9-8280.27" - case 1'1 - assign $0\builder_grant[1:0] 2'11 - attribute \src "ls180.v:8282.9-8282.13" - case - attribute \src "ls180.v:8283.6-8289.9" - switch \builder_request [0] - attribute \src "ls180.v:8283.10-8283.28" - case 1'1 - assign $0\builder_grant[1:0] 2'00 - attribute \src "ls180.v:8285.10-8285.14" - case - attribute \src "ls180.v:8286.7-8288.10" - switch \builder_request [1] - attribute \src "ls180.v:8286.11-8286.29" - case 1'1 - assign $0\builder_grant[1:0] 2'01 - case - end - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'11 - attribute \src "ls180.v:8294.4-8306.7" - switch $not$ls180.v:8294$2456_Y - attribute \src "ls180.v:8294.8-8294.29" - case 1'1 - attribute \src "ls180.v:8295.5-8305.8" - switch \builder_request [0] - attribute \src "ls180.v:8295.9-8295.27" - case 1'1 - assign $0\builder_grant[1:0] 2'00 - attribute \src "ls180.v:8297.9-8297.13" - case - attribute \src "ls180.v:8298.6-8304.9" - switch \builder_request [1] - attribute \src "ls180.v:8298.10-8298.28" - case 1'1 - assign $0\builder_grant[1:0] 2'01 - attribute \src "ls180.v:8300.10-8300.14" - case - attribute \src "ls180.v:8301.7-8303.10" - switch \builder_request [2] - attribute \src "ls180.v:8301.11-8301.29" - case 1'1 - assign $0\builder_grant[1:0] 2'10 - case - end - end - end - case - end - case - end - attribute \src "ls180.v:8310.2-8316.5" - switch \builder_wait - attribute \src "ls180.v:8310.6-8310.18" - case 1'1 - attribute \src "ls180.v:8311.3-8313.6" - switch $not$ls180.v:8311$2457_Y - attribute \src "ls180.v:8311.7-8311.22" - case 1'1 - assign $0\builder_count[19:0] $sub$ls180.v:8312$2458_Y - case - end - attribute \src "ls180.v:8314.6-8314.10" - case - assign $0\builder_count[19:0] 20'11110100001001000000 - end - attribute \src "ls180.v:8318.2-8348.5" - switch \builder_csrbank0_sel - attribute \src "ls180.v:8318.6-8318.26" - case 1'1 - attribute \src "ls180.v:8319.3-8347.10" - switch \builder_interface0_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface0_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank0_reset0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors0_w - case - end - case - end - attribute \src "ls180.v:8349.2-8351.5" - switch \builder_csrbank0_reset0_re - attribute \src "ls180.v:8349.6-8349.32" - case 1'1 - assign $0\main_libresocsim_soccontroller_reset_storage[0:0] \builder_csrbank0_reset0_r - case - end - attribute \src "ls180.v:8353.2-8355.5" - switch \builder_csrbank0_scratch3_re - attribute \src "ls180.v:8353.6-8353.34" - case 1'1 - assign $0\main_libresocsim_soccontroller_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r - case - end - attribute \src "ls180.v:8356.2-8358.5" - switch \builder_csrbank0_scratch2_re - attribute \src "ls180.v:8356.6-8356.34" - case 1'1 - assign $0\main_libresocsim_soccontroller_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r - case - end - attribute \src "ls180.v:8359.2-8361.5" - switch \builder_csrbank0_scratch1_re - attribute \src "ls180.v:8359.6-8359.34" - case 1'1 - assign $0\main_libresocsim_soccontroller_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r - case - end - attribute \src "ls180.v:8362.2-8364.5" - switch \builder_csrbank0_scratch0_re - attribute \src "ls180.v:8362.6-8362.34" - case 1'1 - assign $0\main_libresocsim_soccontroller_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r - case - end - attribute \src "ls180.v:8367.2-8373.5" - switch \builder_csrbank1_sel - attribute \src "ls180.v:8367.6-8367.26" - case 1'1 - attribute \src "ls180.v:8368.3-8372.10" - switch \builder_interface1_bank_bus_adr [0] - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in_w - case - end - case - end - attribute \src "ls180.v:8375.2-8381.5" - switch \builder_csrbank2_sel - attribute \src "ls180.v:8375.6-8375.26" - case 1'1 - attribute \src "ls180.v:8376.3-8380.10" - switch \builder_interface2_bank_bus_adr [0] - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_in_w - case - end - case - end - attribute \src "ls180.v:8383.2-8431.5" - switch \builder_csrbank3_sel - attribute \src "ls180.v:8383.6-8383.26" - case 1'1 - attribute \src "ls180.v:8384.3-8430.10" - switch \builder_interface3_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_dma_base7_w - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_dma_base6_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_dma_base5_w - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_dma_base4_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_dma_base3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_dma_base2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_dma_base1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_dma_base0_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_dma_length3_w - attribute \src "ls180.v:0.0-0.0" - case 4'1001 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_dma_length2_w - attribute \src "ls180.v:0.0-0.0" - case 4'1010 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_dma_length1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1011 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_dma_length0_w - attribute \src "ls180.v:0.0-0.0" - case 4'1100 - assign $0\builder_interface3_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank3_dma_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'1101 - assign $0\builder_interface3_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank3_dma_done_w } - attribute \src "ls180.v:0.0-0.0" - case 4'1110 - assign $0\builder_interface3_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank3_dma_loop0_w } - case - end - case - end - attribute \src "ls180.v:8432.2-8434.5" - switch \builder_csrbank3_dma_base7_re - attribute \src "ls180.v:8432.6-8432.35" - case 1'1 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank3_dma_base7_r - case - end - attribute \src "ls180.v:8435.2-8437.5" - switch \builder_csrbank3_dma_base6_re - attribute \src "ls180.v:8435.6-8435.35" - case 1'1 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank3_dma_base6_r - case - end - attribute \src "ls180.v:8438.2-8440.5" - switch \builder_csrbank3_dma_base5_re - attribute \src "ls180.v:8438.6-8438.35" - case 1'1 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank3_dma_base5_r - case - end - attribute \src "ls180.v:8441.2-8443.5" - switch \builder_csrbank3_dma_base4_re - attribute \src "ls180.v:8441.6-8441.35" - case 1'1 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank3_dma_base4_r - case - end - attribute \src "ls180.v:8444.2-8446.5" - switch \builder_csrbank3_dma_base3_re - attribute \src "ls180.v:8444.6-8444.35" - case 1'1 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank3_dma_base3_r - case - end - attribute \src "ls180.v:8447.2-8449.5" - switch \builder_csrbank3_dma_base2_re - attribute \src "ls180.v:8447.6-8447.35" - case 1'1 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank3_dma_base2_r - case - end - attribute \src "ls180.v:8450.2-8452.5" - switch \builder_csrbank3_dma_base1_re - attribute \src "ls180.v:8450.6-8450.35" - case 1'1 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank3_dma_base1_r - case - end - attribute \src "ls180.v:8453.2-8455.5" - switch \builder_csrbank3_dma_base0_re - attribute \src "ls180.v:8453.6-8453.35" - case 1'1 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank3_dma_base0_r - case - end - attribute \src "ls180.v:8457.2-8459.5" - switch \builder_csrbank3_dma_length3_re - attribute \src "ls180.v:8457.6-8457.37" - case 1'1 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank3_dma_length3_r - case - end - attribute \src "ls180.v:8460.2-8462.5" - switch \builder_csrbank3_dma_length2_re - attribute \src "ls180.v:8460.6-8460.37" - case 1'1 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank3_dma_length2_r - case - end - attribute \src "ls180.v:8463.2-8465.5" - switch \builder_csrbank3_dma_length1_re - attribute \src "ls180.v:8463.6-8463.37" - case 1'1 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank3_dma_length1_r - case - end - attribute \src "ls180.v:8466.2-8468.5" - switch \builder_csrbank3_dma_length0_re - attribute \src "ls180.v:8466.6-8466.37" - case 1'1 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank3_dma_length0_r - case - end - attribute \src "ls180.v:8470.2-8472.5" - switch \builder_csrbank3_dma_enable0_re - attribute \src "ls180.v:8470.6-8470.37" - case 1'1 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank3_dma_enable0_r - case - end - attribute \src "ls180.v:8474.2-8476.5" - switch \builder_csrbank3_dma_loop0_re - attribute \src "ls180.v:8474.6-8474.35" - case 1'1 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank3_dma_loop0_r - case - end - attribute \src "ls180.v:8479.2-8581.5" - switch \builder_csrbank4_sel - attribute \src "ls180.v:8479.6-8479.26" - case 1'1 - attribute \src "ls180.v:8480.3-8580.10" - switch \builder_interface4_bank_bus_adr [5:0] - attribute \src "ls180.v:0.0-0.0" - case 6'000000 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_argument3_w - attribute \src "ls180.v:0.0-0.0" - case 6'000001 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_argument2_w - attribute \src "ls180.v:0.0-0.0" - case 6'000010 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_argument1_w - attribute \src "ls180.v:0.0-0.0" - case 6'000011 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_argument0_w - attribute \src "ls180.v:0.0-0.0" - case 6'000100 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_command3_w - attribute \src "ls180.v:0.0-0.0" - case 6'000101 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_command2_w - attribute \src "ls180.v:0.0-0.0" - case 6'000110 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_command1_w - attribute \src "ls180.v:0.0-0.0" - case 6'000111 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_command0_w - attribute \src "ls180.v:0.0-0.0" - case 6'001000 - assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_sdcore_cmd_send_w } - attribute \src "ls180.v:0.0-0.0" - case 6'001001 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response15_w - attribute \src "ls180.v:0.0-0.0" - case 6'001010 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response14_w - attribute \src "ls180.v:0.0-0.0" - case 6'001011 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response13_w - attribute \src "ls180.v:0.0-0.0" - case 6'001100 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response12_w - attribute \src "ls180.v:0.0-0.0" - case 6'001101 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response11_w - attribute \src "ls180.v:0.0-0.0" - case 6'001110 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response10_w - attribute \src "ls180.v:0.0-0.0" - case 6'001111 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response9_w - attribute \src "ls180.v:0.0-0.0" - case 6'010000 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response8_w - attribute \src "ls180.v:0.0-0.0" - case 6'010001 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response7_w - attribute \src "ls180.v:0.0-0.0" - case 6'010010 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response6_w - attribute \src "ls180.v:0.0-0.0" - case 6'010011 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response5_w - attribute \src "ls180.v:0.0-0.0" - case 6'010100 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response4_w - attribute \src "ls180.v:0.0-0.0" - case 6'010101 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response3_w - attribute \src "ls180.v:0.0-0.0" - case 6'010110 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response2_w - attribute \src "ls180.v:0.0-0.0" - case 6'010111 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response1_w - attribute \src "ls180.v:0.0-0.0" - case 6'011000 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response0_w - attribute \src "ls180.v:0.0-0.0" - case 6'011001 - assign $0\builder_interface4_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank4_cmd_event_w } - attribute \src "ls180.v:0.0-0.0" - case 6'011010 - assign $0\builder_interface4_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank4_data_event_w } - attribute \src "ls180.v:0.0-0.0" - case 6'011011 - assign $0\builder_interface4_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank4_block_length1_w } - attribute \src "ls180.v:0.0-0.0" - case 6'011100 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_block_length0_w - attribute \src "ls180.v:0.0-0.0" - case 6'011101 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_block_count3_w - attribute \src "ls180.v:0.0-0.0" - case 6'011110 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_block_count2_w - attribute \src "ls180.v:0.0-0.0" - case 6'011111 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_block_count1_w - attribute \src "ls180.v:0.0-0.0" - case 6'100000 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_block_count0_w - case - end - case - end - attribute \src "ls180.v:8582.2-8584.5" - switch \builder_csrbank4_cmd_argument3_re - attribute \src "ls180.v:8582.6-8582.39" - case 1'1 - assign $0\libresocsim_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank4_cmd_argument3_r - case - end - attribute \src "ls180.v:8585.2-8587.5" - switch \builder_csrbank4_cmd_argument2_re - attribute \src "ls180.v:8585.6-8585.39" - case 1'1 - assign $0\libresocsim_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank4_cmd_argument2_r - case - end - attribute \src "ls180.v:8588.2-8590.5" - switch \builder_csrbank4_cmd_argument1_re - attribute \src "ls180.v:8588.6-8588.39" - case 1'1 - assign $0\libresocsim_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank4_cmd_argument1_r - case - end - attribute \src "ls180.v:8591.2-8593.5" - switch \builder_csrbank4_cmd_argument0_re - attribute \src "ls180.v:8591.6-8591.39" - case 1'1 - assign $0\libresocsim_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank4_cmd_argument0_r - case - end - attribute \src "ls180.v:8595.2-8597.5" - switch \builder_csrbank4_cmd_command3_re - attribute \src "ls180.v:8595.6-8595.38" - case 1'1 - assign $0\libresocsim_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank4_cmd_command3_r - case - end - attribute \src "ls180.v:8598.2-8600.5" - switch \builder_csrbank4_cmd_command2_re - attribute \src "ls180.v:8598.6-8598.38" - case 1'1 - assign $0\libresocsim_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank4_cmd_command2_r - case - end - attribute \src "ls180.v:8601.2-8603.5" - switch \builder_csrbank4_cmd_command1_re - attribute \src "ls180.v:8601.6-8601.38" - case 1'1 - assign $0\libresocsim_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank4_cmd_command1_r - case - end - attribute \src "ls180.v:8604.2-8606.5" - switch \builder_csrbank4_cmd_command0_re - attribute \src "ls180.v:8604.6-8604.38" - case 1'1 - assign $0\libresocsim_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank4_cmd_command0_r - case - end - attribute \src "ls180.v:8608.2-8610.5" - switch \builder_csrbank4_block_length1_re - attribute \src "ls180.v:8608.6-8608.39" - case 1'1 - assign $0\libresocsim_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank4_block_length1_r - case - end - attribute \src "ls180.v:8611.2-8613.5" - switch \builder_csrbank4_block_length0_re - attribute \src "ls180.v:8611.6-8611.39" - case 1'1 - assign $0\libresocsim_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank4_block_length0_r - case - end - attribute \src "ls180.v:8615.2-8617.5" - switch \builder_csrbank4_block_count3_re - attribute \src "ls180.v:8615.6-8615.38" - case 1'1 - assign $0\libresocsim_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank4_block_count3_r - case - end - attribute \src "ls180.v:8618.2-8620.5" - switch \builder_csrbank4_block_count2_re - attribute \src "ls180.v:8618.6-8618.38" - case 1'1 - assign $0\libresocsim_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank4_block_count2_r - case - end - attribute \src "ls180.v:8621.2-8623.5" - switch \builder_csrbank4_block_count1_re - attribute \src "ls180.v:8621.6-8621.38" - case 1'1 - assign $0\libresocsim_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank4_block_count1_r - case - end - attribute \src "ls180.v:8624.2-8626.5" - switch \builder_csrbank4_block_count0_re - attribute \src "ls180.v:8624.6-8624.38" - case 1'1 - assign $0\libresocsim_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank4_block_count0_r - case - end - attribute \src "ls180.v:8629.2-8689.5" - switch \builder_csrbank5_sel - attribute \src "ls180.v:8629.6-8629.26" - case 1'1 - attribute \src "ls180.v:8630.3-8688.10" - switch \builder_interface5_bank_bus_adr [4:0] - attribute \src "ls180.v:0.0-0.0" - case 5'00000 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base7_w - attribute \src "ls180.v:0.0-0.0" - case 5'00001 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base6_w - attribute \src "ls180.v:0.0-0.0" - case 5'00010 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base5_w - attribute \src "ls180.v:0.0-0.0" - case 5'00011 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base4_w - attribute \src "ls180.v:0.0-0.0" - case 5'00100 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base3_w - attribute \src "ls180.v:0.0-0.0" - case 5'00101 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base2_w - attribute \src "ls180.v:0.0-0.0" - case 5'00110 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base1_w - attribute \src "ls180.v:0.0-0.0" - case 5'00111 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base0_w - attribute \src "ls180.v:0.0-0.0" - case 5'01000 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length3_w - attribute \src "ls180.v:0.0-0.0" - case 5'01001 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length2_w - attribute \src "ls180.v:0.0-0.0" - case 5'01010 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length1_w - attribute \src "ls180.v:0.0-0.0" - case 5'01011 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length0_w - attribute \src "ls180.v:0.0-0.0" - case 5'01100 - assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01101 - assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_done_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01110 - assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_loop0_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01111 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_offset3_w - attribute \src "ls180.v:0.0-0.0" - case 5'10000 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_offset2_w - attribute \src "ls180.v:0.0-0.0" - case 5'10001 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_offset1_w - attribute \src "ls180.v:0.0-0.0" - case 5'10010 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_offset0_w - case - end - case - end - attribute \src "ls180.v:8690.2-8692.5" - switch \builder_csrbank5_dma_base7_re - attribute \src "ls180.v:8690.6-8690.35" - case 1'1 - assign $0\libresocsim_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank5_dma_base7_r - case - end - attribute \src "ls180.v:8693.2-8695.5" - switch \builder_csrbank5_dma_base6_re - attribute \src "ls180.v:8693.6-8693.35" - case 1'1 - assign $0\libresocsim_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank5_dma_base6_r - case - end - attribute \src "ls180.v:8696.2-8698.5" - switch \builder_csrbank5_dma_base5_re - attribute \src "ls180.v:8696.6-8696.35" - case 1'1 - assign $0\libresocsim_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank5_dma_base5_r - case - end - attribute \src "ls180.v:8699.2-8701.5" - switch \builder_csrbank5_dma_base4_re - attribute \src "ls180.v:8699.6-8699.35" - case 1'1 - assign $0\libresocsim_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank5_dma_base4_r - case - end - attribute \src "ls180.v:8702.2-8704.5" - switch \builder_csrbank5_dma_base3_re - attribute \src "ls180.v:8702.6-8702.35" - case 1'1 - assign $0\libresocsim_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank5_dma_base3_r - case - end - attribute \src "ls180.v:8705.2-8707.5" - switch \builder_csrbank5_dma_base2_re - attribute \src "ls180.v:8705.6-8705.35" - case 1'1 - assign $0\libresocsim_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank5_dma_base2_r - case - end - attribute \src "ls180.v:8708.2-8710.5" - switch \builder_csrbank5_dma_base1_re - attribute \src "ls180.v:8708.6-8708.35" - case 1'1 - assign $0\libresocsim_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank5_dma_base1_r - case - end - attribute \src "ls180.v:8711.2-8713.5" - switch \builder_csrbank5_dma_base0_re - attribute \src "ls180.v:8711.6-8711.35" - case 1'1 - assign $0\libresocsim_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank5_dma_base0_r - case - end - attribute \src "ls180.v:8715.2-8717.5" - switch \builder_csrbank5_dma_length3_re - attribute \src "ls180.v:8715.6-8715.37" - case 1'1 - assign $0\libresocsim_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank5_dma_length3_r - case - end - attribute \src "ls180.v:8718.2-8720.5" - switch \builder_csrbank5_dma_length2_re - attribute \src "ls180.v:8718.6-8718.37" - case 1'1 - assign $0\libresocsim_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank5_dma_length2_r - case - end - attribute \src "ls180.v:8721.2-8723.5" - switch \builder_csrbank5_dma_length1_re - attribute \src "ls180.v:8721.6-8721.37" - case 1'1 - assign $0\libresocsim_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank5_dma_length1_r - case - end - attribute \src "ls180.v:8724.2-8726.5" - switch \builder_csrbank5_dma_length0_re - attribute \src "ls180.v:8724.6-8724.37" - case 1'1 - assign $0\libresocsim_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank5_dma_length0_r - case - end - attribute \src "ls180.v:8728.2-8730.5" - switch \builder_csrbank5_dma_enable0_re - attribute \src "ls180.v:8728.6-8728.37" - case 1'1 - assign $0\libresocsim_sdmem2block_dma_enable_storage[0:0] \builder_csrbank5_dma_enable0_r - case - end - attribute \src "ls180.v:8732.2-8734.5" - switch \builder_csrbank5_dma_loop0_re - attribute \src "ls180.v:8732.6-8732.35" - case 1'1 - assign $0\libresocsim_sdmem2block_dma_loop_storage[0:0] \builder_csrbank5_dma_loop0_r - case - end - attribute \src "ls180.v:8737.2-8752.5" - switch \builder_csrbank6_sel - attribute \src "ls180.v:8737.6-8737.26" - case 1'1 - attribute \src "ls180.v:8738.3-8751.10" - switch \builder_interface6_bank_bus_adr [1:0] - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank6_card_detect_w } - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank6_clocker_divider1_w } - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_clocker_divider0_w - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_init_initialize_w } - case - end - case - end - attribute \src "ls180.v:8753.2-8755.5" - switch \builder_csrbank6_clocker_divider1_re - attribute \src "ls180.v:8753.6-8753.42" - case 1'1 - assign $0\libresocsim_clocker_storage[8:0] [8] \builder_csrbank6_clocker_divider1_r - case - end - attribute \src "ls180.v:8756.2-8758.5" - switch \builder_csrbank6_clocker_divider0_re - attribute \src "ls180.v:8756.6-8756.42" - case 1'1 - assign $0\libresocsim_clocker_storage[8:0] [7:0] \builder_csrbank6_clocker_divider0_r - case - end - attribute \src "ls180.v:8761.2-8794.5" - switch \builder_csrbank7_sel - attribute \src "ls180.v:8761.6-8761.26" - case 1'1 - attribute \src "ls180.v:8762.3-8793.10" - switch \builder_interface7_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface7_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank7_dfii_control0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface7_bank_bus_dat_r[7:0] { 2'00 \builder_csrbank7_dfii_pi0_command0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \main_sdram_command_issue_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface7_bank_bus_dat_r[7:0] { 3'000 \builder_csrbank7_dfii_pi0_address1_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dfii_pi0_address0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface7_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank7_dfii_pi0_baddress0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dfii_pi0_wrdata1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dfii_pi0_wrdata0_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dfii_pi0_rddata1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1001 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dfii_pi0_rddata0_w - case - end - case - end - attribute \src "ls180.v:8795.2-8797.5" - switch \builder_csrbank7_dfii_control0_re - attribute \src "ls180.v:8795.6-8795.39" - case 1'1 - assign $0\main_sdram_storage[3:0] \builder_csrbank7_dfii_control0_r - case - end - attribute \src "ls180.v:8799.2-8801.5" - switch \builder_csrbank7_dfii_pi0_command0_re - attribute \src "ls180.v:8799.6-8799.43" - case 1'1 - assign $0\main_sdram_command_storage[5:0] \builder_csrbank7_dfii_pi0_command0_r - case - end - attribute \src "ls180.v:8803.2-8805.5" - switch \builder_csrbank7_dfii_pi0_address1_re - attribute \src "ls180.v:8803.6-8803.43" - case 1'1 - assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank7_dfii_pi0_address1_r - case - end - attribute \src "ls180.v:8806.2-8808.5" - switch \builder_csrbank7_dfii_pi0_address0_re - attribute \src "ls180.v:8806.6-8806.43" - case 1'1 - assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank7_dfii_pi0_address0_r - case - end - attribute \src "ls180.v:8810.2-8812.5" - switch \builder_csrbank7_dfii_pi0_baddress0_re - attribute \src "ls180.v:8810.6-8810.44" - case 1'1 - assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank7_dfii_pi0_baddress0_r - case - end - attribute \src "ls180.v:8814.2-8816.5" - switch \builder_csrbank7_dfii_pi0_wrdata1_re - attribute \src "ls180.v:8814.6-8814.42" - case 1'1 - assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank7_dfii_pi0_wrdata1_r - case - end - attribute \src "ls180.v:8817.2-8819.5" - switch \builder_csrbank7_dfii_pi0_wrdata0_re - attribute \src "ls180.v:8817.6-8817.42" - case 1'1 - assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank7_dfii_pi0_wrdata0_r - case - end - attribute \src "ls180.v:8822.2-8846.5" - switch \builder_csrbank8_sel - attribute \src "ls180.v:8822.6-8822.26" - case 1'1 - attribute \src "ls180.v:8823.3-8845.10" - switch \builder_interface8_bank_bus_adr [2:0] - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_control1_w - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_control0_w - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_status_w } - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_mosi0_w - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_miso_w - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_cs0_w } - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_loopback0_w } - case - end - case - end - attribute \src "ls180.v:8847.2-8849.5" - switch \builder_csrbank8_control1_re - attribute \src "ls180.v:8847.6-8847.34" - case 1'1 - assign $0\main_control_storage[15:0] [15:8] \builder_csrbank8_control1_r - case - end - attribute \src "ls180.v:8850.2-8852.5" - switch \builder_csrbank8_control0_re - attribute \src "ls180.v:8850.6-8850.34" - case 1'1 - assign $0\main_control_storage[15:0] [7:0] \builder_csrbank8_control0_r - case - end - attribute \src "ls180.v:8854.2-8856.5" - switch \builder_csrbank8_mosi0_re - attribute \src "ls180.v:8854.6-8854.31" - case 1'1 - assign $0\main_mosi_storage[7:0] \builder_csrbank8_mosi0_r - case - end - attribute \src "ls180.v:8858.2-8860.5" - switch \builder_csrbank8_cs0_re - attribute \src "ls180.v:8858.6-8858.29" - case 1'1 - assign $0\main_cs_storage[0:0] \builder_csrbank8_cs0_r - case - end - attribute \src "ls180.v:8862.2-8864.5" - switch \builder_csrbank8_loopback0_re - attribute \src "ls180.v:8862.6-8862.35" - case 1'1 - assign $0\main_loopback_storage[0:0] \builder_csrbank8_loopback0_r - case - end - attribute \src "ls180.v:8867.2-8897.5" - switch \builder_csrbank9_sel - attribute \src "ls180.v:8867.6-8867.26" - case 1'1 - attribute \src "ls180.v:8868.3-8896.10" - switch \builder_interface9_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_control1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_control0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank9_status_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_mosi0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_miso_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank9_cs0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank9_loopback0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_clk_divider1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_clk_divider0_w - case - end - case - end - attribute \src "ls180.v:8898.2-8900.5" - switch \builder_csrbank9_control1_re - attribute \src "ls180.v:8898.6-8898.34" - case 1'1 - assign $0\libresocsim_control_storage[15:0] [15:8] \builder_csrbank9_control1_r - case - end - attribute \src "ls180.v:8901.2-8903.5" - switch \builder_csrbank9_control0_re - attribute \src "ls180.v:8901.6-8901.34" - case 1'1 - assign $0\libresocsim_control_storage[15:0] [7:0] \builder_csrbank9_control0_r - case - end - attribute \src "ls180.v:8905.2-8907.5" - switch \builder_csrbank9_mosi0_re - attribute \src "ls180.v:8905.6-8905.31" - case 1'1 - assign $0\libresocsim_mosi_storage[7:0] \builder_csrbank9_mosi0_r - case - end - attribute \src "ls180.v:8909.2-8911.5" - switch \builder_csrbank9_cs0_re - attribute \src "ls180.v:8909.6-8909.29" - case 1'1 - assign $0\libresocsim_cs_storage[0:0] \builder_csrbank9_cs0_r - case - end - attribute \src "ls180.v:8913.2-8915.5" - switch \builder_csrbank9_loopback0_re - attribute \src "ls180.v:8913.6-8913.35" - case 1'1 - assign $0\libresocsim_loopback_storage[0:0] \builder_csrbank9_loopback0_r - case - end - attribute \src "ls180.v:8917.2-8919.5" - switch \builder_csrbank9_clk_divider1_re - attribute \src "ls180.v:8917.6-8917.38" - case 1'1 - assign $0\libresocsim_storage[15:0] [15:8] \builder_csrbank9_clk_divider1_r - case - end - attribute \src "ls180.v:8920.2-8922.5" - switch \builder_csrbank9_clk_divider0_re - attribute \src "ls180.v:8920.6-8920.38" - case 1'1 - assign $0\libresocsim_storage[15:0] [7:0] \builder_csrbank9_clk_divider0_r - case - end - attribute \src "ls180.v:8925.2-8979.5" - switch \builder_csrbank10_sel - attribute \src "ls180.v:8925.6-8925.27" - case 1'1 - attribute \src "ls180.v:8926.3-8978.10" - switch \builder_interface10_bank_bus_adr [4:0] - attribute \src "ls180.v:0.0-0.0" - case 5'00000 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_load3_w - attribute \src "ls180.v:0.0-0.0" - case 5'00001 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_load2_w - attribute \src "ls180.v:0.0-0.0" - case 5'00010 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_load1_w - attribute \src "ls180.v:0.0-0.0" - case 5'00011 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_load0_w - attribute \src "ls180.v:0.0-0.0" - case 5'00100 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_reload3_w - attribute \src "ls180.v:0.0-0.0" - case 5'00101 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_reload2_w - attribute \src "ls180.v:0.0-0.0" - case 5'00110 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_reload1_w - attribute \src "ls180.v:0.0-0.0" - case 5'00111 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_reload0_w - attribute \src "ls180.v:0.0-0.0" - case 5'01000 - assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_en0_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01001 - assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_update_value0_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01010 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_value3_w - attribute \src "ls180.v:0.0-0.0" - case 5'01011 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_value2_w - attribute \src "ls180.v:0.0-0.0" - case 5'01100 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_value1_w - attribute \src "ls180.v:0.0-0.0" - case 5'01101 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_value0_w - attribute \src "ls180.v:0.0-0.0" - case 5'01110 - assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_timer_eventmanager_status_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01111 - assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_timer_eventmanager_pending_w } - attribute \src "ls180.v:0.0-0.0" - case 5'10000 - assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_ev_enable0_w } - case - end - case - end - attribute \src "ls180.v:8980.2-8982.5" - switch \builder_csrbank10_load3_re - attribute \src "ls180.v:8980.6-8980.32" - case 1'1 - assign $0\main_libresocsim_timer_load_storage[31:0] [31:24] \builder_csrbank10_load3_r - case - end - attribute \src "ls180.v:8983.2-8985.5" - switch \builder_csrbank10_load2_re - attribute \src "ls180.v:8983.6-8983.32" - case 1'1 - assign $0\main_libresocsim_timer_load_storage[31:0] [23:16] \builder_csrbank10_load2_r - case - end - attribute \src "ls180.v:8986.2-8988.5" - switch \builder_csrbank10_load1_re - attribute \src "ls180.v:8986.6-8986.32" - case 1'1 - assign $0\main_libresocsim_timer_load_storage[31:0] [15:8] \builder_csrbank10_load1_r - case - end - attribute \src "ls180.v:8989.2-8991.5" - switch \builder_csrbank10_load0_re - attribute \src "ls180.v:8989.6-8989.32" - case 1'1 - assign $0\main_libresocsim_timer_load_storage[31:0] [7:0] \builder_csrbank10_load0_r - case - end - attribute \src "ls180.v:8993.2-8995.5" - switch \builder_csrbank10_reload3_re - attribute \src "ls180.v:8993.6-8993.34" - case 1'1 - assign $0\main_libresocsim_timer_reload_storage[31:0] [31:24] \builder_csrbank10_reload3_r - case - end - attribute \src "ls180.v:8996.2-8998.5" - switch \builder_csrbank10_reload2_re - attribute \src "ls180.v:8996.6-8996.34" - case 1'1 - assign $0\main_libresocsim_timer_reload_storage[31:0] [23:16] \builder_csrbank10_reload2_r - case - end - attribute \src "ls180.v:8999.2-9001.5" - switch \builder_csrbank10_reload1_re - attribute \src "ls180.v:8999.6-8999.34" - case 1'1 - assign $0\main_libresocsim_timer_reload_storage[31:0] [15:8] \builder_csrbank10_reload1_r - case - end - attribute \src "ls180.v:9002.2-9004.5" - switch \builder_csrbank10_reload0_re - attribute \src "ls180.v:9002.6-9002.34" - case 1'1 - assign $0\main_libresocsim_timer_reload_storage[31:0] [7:0] \builder_csrbank10_reload0_r - case - end - attribute \src "ls180.v:9006.2-9008.5" - switch \builder_csrbank10_en0_re - attribute \src "ls180.v:9006.6-9006.30" - case 1'1 - assign $0\main_libresocsim_timer_en_storage[0:0] \builder_csrbank10_en0_r - case - end - attribute \src "ls180.v:9010.2-9012.5" - switch \builder_csrbank10_update_value0_re - attribute \src "ls180.v:9010.6-9010.40" - case 1'1 - assign $0\main_libresocsim_timer_update_value_storage[0:0] \builder_csrbank10_update_value0_r - case - end - attribute \src "ls180.v:9014.2-9016.5" - switch \builder_csrbank10_ev_enable0_re - attribute \src "ls180.v:9014.6-9014.37" - case 1'1 - assign $0\main_libresocsim_timer_eventmanager_storage[0:0] \builder_csrbank10_ev_enable0_r - case - end - attribute \src "ls180.v:9019.2-9046.5" - switch \builder_csrbank11_sel - attribute \src "ls180.v:9019.6-9019.27" - case 1'1 - attribute \src "ls180.v:9020.3-9045.10" - switch \builder_interface11_bank_bus_adr [2:0] - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \main_libresocsim_uart_rxtx_w - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_txfull_w } - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_rxempty_w } - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 6'000000 \main_libresocsim_uart_eventmanager_status_w } - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 6'000000 \main_libresocsim_uart_eventmanager_pending_w } - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank11_ev_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_txempty_w } - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_rxfull_w } - case - end - case - end - attribute \src "ls180.v:9047.2-9049.5" - switch \builder_csrbank11_ev_enable0_re - attribute \src "ls180.v:9047.6-9047.37" - case 1'1 - assign $0\main_libresocsim_uart_eventmanager_storage[1:0] \builder_csrbank11_ev_enable0_r - case - end - attribute \src "ls180.v:9052.2-9067.5" - switch \builder_csrbank12_sel - attribute \src "ls180.v:9052.6-9052.27" - case 1'1 - attribute \src "ls180.v:9053.3-9066.10" - switch \builder_interface12_bank_bus_adr [1:0] - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_tuning_word3_w - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_tuning_word2_w - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_tuning_word1_w - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_tuning_word0_w - case - end - case - end - attribute \src "ls180.v:9068.2-9070.5" - switch \builder_csrbank12_tuning_word3_re - attribute \src "ls180.v:9068.6-9068.39" - case 1'1 - assign $0\main_libresocsim_storage[31:0] [31:24] \builder_csrbank12_tuning_word3_r - case - end - attribute \src "ls180.v:9071.2-9073.5" - switch \builder_csrbank12_tuning_word2_re - attribute \src "ls180.v:9071.6-9071.39" - case 1'1 - assign $0\main_libresocsim_storage[31:0] [23:16] \builder_csrbank12_tuning_word2_r - case - end - attribute \src "ls180.v:9074.2-9076.5" - switch \builder_csrbank12_tuning_word1_re - attribute \src "ls180.v:9074.6-9074.39" - case 1'1 - assign $0\main_libresocsim_storage[31:0] [15:8] \builder_csrbank12_tuning_word1_r - case - end - attribute \src "ls180.v:9077.2-9079.5" - switch \builder_csrbank12_tuning_word0_re - attribute \src "ls180.v:9077.6-9077.39" - case 1'1 - assign $0\main_libresocsim_storage[31:0] [7:0] \builder_csrbank12_tuning_word0_r - case - end - attribute \src "ls180.v:9081.2-9357.5" - switch \sys_rst - attribute \src "ls180.v:9081.6-9081.13" - case 1'1 - assign $0\main_libresocsim_soccontroller_reset_storage[0:0] 1'0 - assign $0\main_libresocsim_soccontroller_reset_re[0:0] 1'0 - assign $0\main_libresocsim_soccontroller_scratch_storage[31:0] 305419896 - assign $0\main_libresocsim_soccontroller_scratch_re[0:0] 1'0 - assign $0\main_libresocsim_soccontroller_bus_errors[31:0] 0 - assign $0\main_libresocsim_converter0_counter[0:0] 1'0 - assign $0\main_libresocsim_converter1_counter[0:0] 1'0 - assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 - assign $0\serial_tx[0:0] 1'1 - assign $0\main_libresocsim_storage[31:0] 9895604 - assign $0\main_libresocsim_re[0:0] 1'0 - assign $0\main_libresocsim_sink_ready[0:0] 1'0 - assign $0\main_libresocsim_uart_clk_txen[0:0] 1'0 - assign $0\main_libresocsim_tx_busy[0:0] 1'0 - assign $0\main_libresocsim_source_valid[0:0] 1'0 - assign $0\main_libresocsim_uart_clk_rxen[0:0] 1'0 - assign $0\main_libresocsim_rx_r[0:0] 1'0 - assign $0\main_libresocsim_rx_busy[0:0] 1'0 - assign $0\main_libresocsim_uart_tx_pending[0:0] 1'0 - assign $0\main_libresocsim_uart_tx_old_trigger[0:0] 1'0 - assign $0\main_libresocsim_uart_rx_pending[0:0] 1'0 - assign $0\main_libresocsim_uart_rx_old_trigger[0:0] 1'0 - assign $0\main_libresocsim_uart_eventmanager_storage[1:0] 2'00 - assign $0\main_libresocsim_uart_eventmanager_re[0:0] 1'0 - assign $0\main_libresocsim_uart_tx_fifo_readable[0:0] 1'0 - assign $0\main_libresocsim_uart_tx_fifo_level0[4:0] 5'00000 - assign $0\main_libresocsim_uart_tx_fifo_produce[3:0] 4'0000 - assign $0\main_libresocsim_uart_tx_fifo_consume[3:0] 4'0000 - assign $0\main_libresocsim_uart_rx_fifo_readable[0:0] 1'0 - assign $0\main_libresocsim_uart_rx_fifo_level0[4:0] 5'00000 - assign $0\main_libresocsim_uart_rx_fifo_produce[3:0] 4'0000 - assign $0\main_libresocsim_uart_rx_fifo_consume[3:0] 4'0000 - assign $0\main_libresocsim_timer_load_storage[31:0] 0 - assign $0\main_libresocsim_timer_load_re[0:0] 1'0 - assign $0\main_libresocsim_timer_reload_storage[31:0] 0 - assign $0\main_libresocsim_timer_reload_re[0:0] 1'0 - assign $0\main_libresocsim_timer_en_storage[0:0] 1'0 - assign $0\main_libresocsim_timer_en_re[0:0] 1'0 - assign $0\main_libresocsim_timer_update_value_storage[0:0] 1'0 - assign $0\main_libresocsim_timer_update_value_re[0:0] 1'0 - assign $0\main_libresocsim_timer_value_status[31:0] 0 - assign $0\main_libresocsim_timer_zero_pending[0:0] 1'0 - assign $0\main_libresocsim_timer_zero_old_trigger[0:0] 1'0 - assign $0\main_libresocsim_timer_eventmanager_storage[0:0] 1'0 - assign $0\main_libresocsim_timer_eventmanager_re[0:0] 1'0 - assign $0\main_libresocsim_timer_value[31:0] 0 - assign $0\main_dfi_p0_rddata_valid[0:0] 1'0 - assign $0\main_rddata_en[2:0] 3'000 - assign $0\main_sdram_storage[3:0] 4'0001 - assign $0\main_sdram_re[0:0] 1'0 - assign $0\main_sdram_command_storage[5:0] 6'000000 - assign $0\main_sdram_command_re[0:0] 1'0 - assign $0\main_sdram_address_re[0:0] 1'0 - assign $0\main_sdram_baddress_re[0:0] 1'0 - assign $0\main_sdram_wrdata_re[0:0] 1'0 - assign $0\main_sdram_status[15:0] 16'0000000000000000 - assign $0\main_sdram_dfi_p0_address[12:0] 13'0000000000000 - assign $0\main_sdram_dfi_p0_bank[1:0] 2'00 - assign $0\main_sdram_dfi_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_dfi_p0_ras_n[0:0] 1'1 - assign $0\main_sdram_dfi_p0_we_n[0:0] 1'1 - assign $0\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 - assign $0\main_sdram_dfi_p0_rddata_en[0:0] 1'0 - assign $0\main_sdram_timer_count1[9:0] 10'1100001101 - assign $0\main_sdram_postponer_req_o[0:0] 1'0 - assign $0\main_sdram_postponer_count[0:0] 1'0 - assign $0\main_sdram_sequencer_done1[0:0] 1'0 - assign $0\main_sdram_sequencer_counter[3:0] 4'0000 - assign $0\main_sdram_sequencer_count[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 - assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row[12:0] 13'0000000000000 - assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 - assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 - assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine1_row[12:0] 13'0000000000000 - assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 - assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 - assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row[12:0] 13'0000000000000 - assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 - assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 - assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row[12:0] 13'0000000000000 - assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 - assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - assign $0\main_sdram_choose_req_grant[1:0] 2'00 - assign $0\main_sdram_tccdcon_ready[0:0] 1'0 - assign $0\main_sdram_tccdcon_count[0:0] 1'0 - assign $0\main_sdram_twtrcon_ready[0:0] 1'0 - assign $0\main_sdram_twtrcon_count[2:0] 3'000 - assign $0\main_sdram_time0[4:0] 5'00000 - assign $0\main_sdram_time1[3:0] 4'0000 - assign $0\main_converter_counter[0:0] 1'0 - assign $0\main_cmd_consumed[0:0] 1'0 - assign $0\main_wdata_consumed[0:0] 1'0 - assign $0\spi_master_clk[0:0] 1'0 - assign $0\spi_master_mosi[0:0] 1'0 - assign $0\spi_master_cs_n[0:0] 1'0 - assign $0\main_miso[7:0] 8'00000000 - assign $0\main_control_storage[15:0] 16'0000000000000000 - assign $0\main_control_re[0:0] 1'0 - assign $0\main_mosi_re[0:0] 1'0 - assign $0\main_cs_storage[0:0] 1'1 - assign $0\main_cs_re[0:0] 1'0 - assign $0\main_loopback_storage[0:0] 1'0 - assign $0\main_loopback_re[0:0] 1'0 - assign $0\main_count[2:0] 3'000 - assign $0\main_clk_divider1[15:0] 16'0000000000000000 - assign $0\main_mosi_data[7:0] 8'00000000 - assign $0\main_mosi_sel[2:0] 3'000 - assign $0\main_miso_data[7:0] 8'00000000 - assign $0\libresocsim_clocker_storage[8:0] 9'100000000 - assign $0\libresocsim_clocker_re[0:0] 1'0 - assign $0\libresocsim_clocker_clk0[0:0] 1'0 - assign $0\libresocsim_clocker_clks[8:0] 9'000000000 - assign $0\libresocsim_clocker_clk_d[0:0] 1'0 - assign $0\libresocsim_init_count[7:0] 8'00000000 - assign $0\libresocsim_cmdw_count[7:0] 8'00000000 - assign $0\libresocsim_cmdr_timeout[31:0] 500000 - assign $0\libresocsim_cmdr_count[7:0] 8'00000000 - assign $0\libresocsim_cmdr_cmdr_run[0:0] 1'0 - assign $0\libresocsim_cmdr_cmdr_converter_demux[2:0] 3'000 - assign $0\libresocsim_cmdr_cmdr_converter_strobe_all[0:0] 1'0 - assign $0\libresocsim_cmdr_cmdr_buf_source_valid[0:0] 1'0 - assign $0\libresocsim_cmdr_cmdr_reset[0:0] 1'0 - assign $0\libresocsim_dataw_count[7:0] 8'00000000 - assign $0\libresocsim_dataw_crcr_run[0:0] 1'0 - assign $0\libresocsim_dataw_crcr_converter_demux[2:0] 3'000 - assign $0\libresocsim_dataw_crcr_converter_strobe_all[0:0] 1'0 - assign $0\libresocsim_dataw_crcr_buf_source_valid[0:0] 1'0 - assign $0\libresocsim_dataw_crcr_reset[0:0] 1'0 - assign $0\libresocsim_datar_timeout[31:0] 500000 - assign $0\libresocsim_datar_count[9:0] 10'0000000000 - assign $0\libresocsim_datar_datar_run[0:0] 1'0 - assign $0\libresocsim_datar_datar_converter_demux[0:0] 1'0 - assign $0\libresocsim_datar_datar_converter_strobe_all[0:0] 1'0 - assign $0\libresocsim_datar_datar_buf_source_valid[0:0] 1'0 - assign $0\libresocsim_datar_datar_reset[0:0] 1'0 - assign $0\libresocsim_sdcore_cmd_argument_storage[31:0] 0 - assign $0\libresocsim_sdcore_cmd_argument_re[0:0] 1'0 - assign $0\libresocsim_sdcore_cmd_command_storage[31:0] 0 - assign $0\libresocsim_sdcore_cmd_command_re[0:0] 1'0 - assign $0\libresocsim_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $0\libresocsim_sdcore_block_length_storage[9:0] 10'0000000000 - assign $0\libresocsim_sdcore_block_length_re[0:0] 1'0 - assign $0\libresocsim_sdcore_block_count_storage[31:0] 0 - assign $0\libresocsim_sdcore_block_count_re[0:0] 1'0 - assign $0\libresocsim_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - assign $0\libresocsim_sdcore_crc16_inserter_cnt[2:0] 3'000 - assign $0\libresocsim_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - assign $0\libresocsim_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - assign $0\libresocsim_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - assign $0\libresocsim_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - assign $0\libresocsim_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 - assign $0\libresocsim_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 - assign $0\libresocsim_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 - assign $0\libresocsim_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 - assign $0\libresocsim_sdcore_crc16_checker_val[7:0] 8'00000000 - assign $0\libresocsim_sdcore_crc16_checker_cnt[3:0] 4'0000 - assign $0\libresocsim_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - assign $0\libresocsim_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - assign $0\libresocsim_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - assign $0\libresocsim_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - assign $0\libresocsim_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 - assign $0\libresocsim_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 - assign $0\libresocsim_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 - assign $0\libresocsim_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 - assign $0\libresocsim_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 - assign $0\libresocsim_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 - assign $0\libresocsim_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 - assign $0\libresocsim_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 - assign $0\libresocsim_sdcore_cmd_count[2:0] 3'000 - assign $0\libresocsim_sdcore_cmd_done[0:0] 1'0 - assign $0\libresocsim_sdcore_cmd_error[0:0] 1'0 - assign $0\libresocsim_sdcore_cmd_timeout[0:0] 1'0 - assign $0\libresocsim_sdcore_data_count[31:0] 0 - assign $0\libresocsim_sdcore_data_done[0:0] 1'0 - assign $0\libresocsim_sdcore_data_error[0:0] 1'0 - assign $0\libresocsim_sdcore_data_timeout[0:0] 1'0 - assign $0\libresocsim_sdblock2mem_fifo_level[5:0] 6'000000 - assign $0\libresocsim_sdblock2mem_fifo_produce[4:0] 5'00000 - assign $0\libresocsim_sdblock2mem_fifo_consume[4:0] 5'00000 - assign $0\libresocsim_sdblock2mem_converter_demux[1:0] 2'00 - assign $0\libresocsim_sdblock2mem_converter_strobe_all[0:0] 1'0 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 - assign $0\libresocsim_sdblock2mem_wishbonedmawriter_offset[31:0] 0 - assign $0\libresocsim_sdmem2block_dma_data[31:0] 0 - assign $0\libresocsim_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\libresocsim_sdmem2block_dma_base_re[0:0] 1'0 - assign $0\libresocsim_sdmem2block_dma_length_storage[31:0] 0 - assign $0\libresocsim_sdmem2block_dma_length_re[0:0] 1'0 - assign $0\libresocsim_sdmem2block_dma_enable_storage[0:0] 1'0 - assign $0\libresocsim_sdmem2block_dma_enable_re[0:0] 1'0 - assign $0\libresocsim_sdmem2block_dma_loop_storage[0:0] 1'0 - assign $0\libresocsim_sdmem2block_dma_loop_re[0:0] 1'0 - assign $0\libresocsim_sdmem2block_dma_offset[31:0] 0 - assign $0\libresocsim_sdmem2block_converter_mux[1:0] 2'00 - assign $0\libresocsim_sdmem2block_fifo_level[5:0] 6'000000 - assign $0\libresocsim_sdmem2block_fifo_produce[4:0] 5'00000 - assign $0\libresocsim_sdmem2block_fifo_consume[4:0] 5'00000 - assign $0\spisdcard_clk[0:0] 1'0 - assign $0\spisdcard_mosi[0:0] 1'0 - assign $0\spisdcard_cs_n[0:0] 1'0 - assign $0\libresocsim_miso[7:0] 8'00000000 - assign $0\libresocsim_control_storage[15:0] 16'0000000000000000 - assign $0\libresocsim_control_re[0:0] 1'0 - assign $0\libresocsim_mosi_re[0:0] 1'0 - assign $0\libresocsim_cs_storage[0:0] 1'1 - assign $0\libresocsim_cs_re[0:0] 1'0 - assign $0\libresocsim_loopback_storage[0:0] 1'0 - assign $0\libresocsim_loopback_re[0:0] 1'0 - assign $0\libresocsim_count[2:0] 3'000 - assign $0\libresocsim_clk_divider1[15:0] 16'0000000000000000 - assign $0\libresocsim_mosi_data[7:0] 8'00000000 - assign $0\libresocsim_mosi_sel[2:0] 3'000 - assign $0\libresocsim_miso_data[7:0] 8'00000000 - assign $0\libresocsim_storage[15:0] 16'0000000001111101 - assign $0\libresocsim_re[0:0] 1'0 - assign $0\builder_converter0_state[0:0] 1'0 - assign $0\builder_converter1_state[0:0] 1'0 - assign $0\builder_refresher_state[1:0] 2'00 - assign $0\builder_bankmachine0_state[2:0] 3'000 - assign $0\builder_bankmachine1_state[2:0] 3'000 - assign $0\builder_bankmachine2_state[2:0] 3'000 - assign $0\builder_bankmachine3_state[2:0] 3'000 - assign $0\builder_multiplexer_state[2:0] 3'000 - assign $0\builder_new_master_wdata_ready[0:0] 1'0 - assign $0\builder_new_master_rdata_valid0[0:0] 1'0 - assign $0\builder_new_master_rdata_valid1[0:0] 1'0 - assign $0\builder_new_master_rdata_valid2[0:0] 1'0 - assign $0\builder_new_master_rdata_valid3[0:0] 1'0 - assign $0\builder_converter_state[0:0] 1'0 - assign $0\builder_spimaster0_state[1:0] 2'00 - assign $0\builder_sdphy_sdphyinit_state[0:0] 1'0 - assign $0\builder_sdphy_sdphycmdw_state[1:0] 2'00 - assign $0\builder_sdphy_sdphycmdr_state[2:0] 3'000 - assign $0\builder_sdphy_sdphycrcr_state[0:0] 1'0 - assign $0\builder_sdphy_fsm_state[2:0] 3'000 - assign $0\builder_sdphy_sdphydatar_state[2:0] 3'000 - assign $0\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 - assign $0\builder_sdcore_fsm_state[2:0] 3'000 - assign $0\builder_sdblock2memdma_state[1:0] 2'00 - assign $0\builder_sdmem2blockdma_fsm_state[0:0] 1'0 - assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 - assign $0\builder_spimaster1_state[1:0] 2'00 - assign $0\builder_libresocsim_we[0:0] 1'0 - assign $0\builder_grant[1:0] 2'00 - assign $0\builder_slave_sel_r[4:0] 5'00000 - assign $0\builder_count[19:0] 20'11110100001001000000 - assign $0\builder_state[1:0] 2'00 - case - end - sync posedge \sys_clk_1 - update \serial_tx $0\serial_tx[0:0] - update \spi_master_clk $0\spi_master_clk[0:0] - update \spi_master_mosi $0\spi_master_mosi[0:0] - update \spi_master_cs_n $0\spi_master_cs_n[0:0] - update \spisdcard_clk $0\spisdcard_clk[0:0] - update \spisdcard_mosi $0\spisdcard_mosi[0:0] - update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] - update \main_libresocsim_soccontroller_reset_storage $0\main_libresocsim_soccontroller_reset_storage[0:0] - update \main_libresocsim_soccontroller_reset_re $0\main_libresocsim_soccontroller_reset_re[0:0] - update \main_libresocsim_soccontroller_scratch_storage $0\main_libresocsim_soccontroller_scratch_storage[31:0] - update \main_libresocsim_soccontroller_scratch_re $0\main_libresocsim_soccontroller_scratch_re[0:0] - update \main_libresocsim_soccontroller_bus_errors $0\main_libresocsim_soccontroller_bus_errors[31:0] - update \main_libresocsim_converter0_counter $0\main_libresocsim_converter0_counter[0:0] - update \main_libresocsim_converter0_dat_r $0\main_libresocsim_converter0_dat_r[63:0] - update \main_libresocsim_converter1_counter $0\main_libresocsim_converter1_counter[0:0] - update \main_libresocsim_converter1_dat_r $0\main_libresocsim_converter1_dat_r[63:0] - update \main_libresocsim_ram_bus_ack $0\main_libresocsim_ram_bus_ack[0:0] - update \main_libresocsim_storage $0\main_libresocsim_storage[31:0] - update \main_libresocsim_re $0\main_libresocsim_re[0:0] - update \main_libresocsim_sink_ready $0\main_libresocsim_sink_ready[0:0] - update \main_libresocsim_uart_clk_txen $0\main_libresocsim_uart_clk_txen[0:0] - update \main_libresocsim_phase_accumulator_tx $0\main_libresocsim_phase_accumulator_tx[31:0] - update \main_libresocsim_tx_reg $0\main_libresocsim_tx_reg[7:0] - update \main_libresocsim_tx_bitcount $0\main_libresocsim_tx_bitcount[3:0] - update \main_libresocsim_tx_busy $0\main_libresocsim_tx_busy[0:0] - update \main_libresocsim_source_valid $0\main_libresocsim_source_valid[0:0] - update \main_libresocsim_source_payload_data $0\main_libresocsim_source_payload_data[7:0] - update \main_libresocsim_uart_clk_rxen $0\main_libresocsim_uart_clk_rxen[0:0] - update \main_libresocsim_phase_accumulator_rx $0\main_libresocsim_phase_accumulator_rx[31:0] - update \main_libresocsim_rx_r $0\main_libresocsim_rx_r[0:0] - update \main_libresocsim_rx_reg $0\main_libresocsim_rx_reg[7:0] - update \main_libresocsim_rx_bitcount $0\main_libresocsim_rx_bitcount[3:0] - update \main_libresocsim_rx_busy $0\main_libresocsim_rx_busy[0:0] - update \main_libresocsim_uart_tx_pending $0\main_libresocsim_uart_tx_pending[0:0] - update \main_libresocsim_uart_tx_old_trigger $0\main_libresocsim_uart_tx_old_trigger[0:0] - update \main_libresocsim_uart_rx_pending $0\main_libresocsim_uart_rx_pending[0:0] - update \main_libresocsim_uart_rx_old_trigger $0\main_libresocsim_uart_rx_old_trigger[0:0] - update \main_libresocsim_uart_eventmanager_storage $0\main_libresocsim_uart_eventmanager_storage[1:0] - update \main_libresocsim_uart_eventmanager_re $0\main_libresocsim_uart_eventmanager_re[0:0] - update \main_libresocsim_uart_tx_fifo_readable $0\main_libresocsim_uart_tx_fifo_readable[0:0] - update \main_libresocsim_uart_tx_fifo_level0 $0\main_libresocsim_uart_tx_fifo_level0[4:0] - update \main_libresocsim_uart_tx_fifo_produce $0\main_libresocsim_uart_tx_fifo_produce[3:0] - update \main_libresocsim_uart_tx_fifo_consume $0\main_libresocsim_uart_tx_fifo_consume[3:0] - update \main_libresocsim_uart_rx_fifo_readable $0\main_libresocsim_uart_rx_fifo_readable[0:0] - update \main_libresocsim_uart_rx_fifo_level0 $0\main_libresocsim_uart_rx_fifo_level0[4:0] - update \main_libresocsim_uart_rx_fifo_produce $0\main_libresocsim_uart_rx_fifo_produce[3:0] - update \main_libresocsim_uart_rx_fifo_consume $0\main_libresocsim_uart_rx_fifo_consume[3:0] - update \main_libresocsim_timer_load_storage $0\main_libresocsim_timer_load_storage[31:0] - update \main_libresocsim_timer_load_re $0\main_libresocsim_timer_load_re[0:0] - update \main_libresocsim_timer_reload_storage $0\main_libresocsim_timer_reload_storage[31:0] - update \main_libresocsim_timer_reload_re $0\main_libresocsim_timer_reload_re[0:0] - update \main_libresocsim_timer_en_storage $0\main_libresocsim_timer_en_storage[0:0] - update \main_libresocsim_timer_en_re $0\main_libresocsim_timer_en_re[0:0] - update \main_libresocsim_timer_update_value_storage $0\main_libresocsim_timer_update_value_storage[0:0] - update \main_libresocsim_timer_update_value_re $0\main_libresocsim_timer_update_value_re[0:0] - update \main_libresocsim_timer_value_status $0\main_libresocsim_timer_value_status[31:0] - update \main_libresocsim_timer_zero_pending $0\main_libresocsim_timer_zero_pending[0:0] - update \main_libresocsim_timer_zero_old_trigger $0\main_libresocsim_timer_zero_old_trigger[0:0] - update \main_libresocsim_timer_eventmanager_storage $0\main_libresocsim_timer_eventmanager_storage[0:0] - update \main_libresocsim_timer_eventmanager_re $0\main_libresocsim_timer_eventmanager_re[0:0] - update \main_libresocsim_timer_value $0\main_libresocsim_timer_value[31:0] - update \main_dfi_p0_rddata_valid $0\main_dfi_p0_rddata_valid[0:0] - update \main_rddata_en $0\main_rddata_en[2:0] - update \main_sdram_storage $0\main_sdram_storage[3:0] - update \main_sdram_re $0\main_sdram_re[0:0] - update \main_sdram_command_storage $0\main_sdram_command_storage[5:0] - update \main_sdram_command_re $0\main_sdram_command_re[0:0] - update \main_sdram_address_storage $0\main_sdram_address_storage[12:0] - update \main_sdram_address_re $0\main_sdram_address_re[0:0] - update \main_sdram_baddress_storage $0\main_sdram_baddress_storage[1:0] - update \main_sdram_baddress_re $0\main_sdram_baddress_re[0:0] - update \main_sdram_wrdata_storage $0\main_sdram_wrdata_storage[15:0] - update \main_sdram_wrdata_re $0\main_sdram_wrdata_re[0:0] - update \main_sdram_status $0\main_sdram_status[15:0] - update \main_sdram_dfi_p0_address $0\main_sdram_dfi_p0_address[12:0] - update \main_sdram_dfi_p0_bank $0\main_sdram_dfi_p0_bank[1:0] - update \main_sdram_dfi_p0_cas_n $0\main_sdram_dfi_p0_cas_n[0:0] - update \main_sdram_dfi_p0_cs_n $0\main_sdram_dfi_p0_cs_n[0:0] - update \main_sdram_dfi_p0_ras_n $0\main_sdram_dfi_p0_ras_n[0:0] - update \main_sdram_dfi_p0_we_n $0\main_sdram_dfi_p0_we_n[0:0] - update \main_sdram_dfi_p0_wrdata_en $0\main_sdram_dfi_p0_wrdata_en[0:0] - update \main_sdram_dfi_p0_rddata_en $0\main_sdram_dfi_p0_rddata_en[0:0] - update \main_sdram_cmd_payload_a $0\main_sdram_cmd_payload_a[12:0] - update \main_sdram_cmd_payload_ba $0\main_sdram_cmd_payload_ba[1:0] - update \main_sdram_cmd_payload_cas $0\main_sdram_cmd_payload_cas[0:0] - update \main_sdram_cmd_payload_ras $0\main_sdram_cmd_payload_ras[0:0] - update \main_sdram_cmd_payload_we $0\main_sdram_cmd_payload_we[0:0] - update \main_sdram_timer_count1 $0\main_sdram_timer_count1[9:0] - update \main_sdram_postponer_req_o $0\main_sdram_postponer_req_o[0:0] - update \main_sdram_postponer_count $0\main_sdram_postponer_count[0:0] - update \main_sdram_sequencer_done1 $0\main_sdram_sequencer_done1[0:0] - update \main_sdram_sequencer_counter $0\main_sdram_sequencer_counter[3:0] - update \main_sdram_sequencer_count $0\main_sdram_sequencer_count[0:0] - update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - update \main_sdram_bankmachine0_cmd_buffer_source_valid $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - update \main_sdram_bankmachine0_cmd_buffer_source_first $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - update \main_sdram_bankmachine0_cmd_buffer_source_last $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - update \main_sdram_bankmachine0_row $0\main_sdram_bankmachine0_row[12:0] - update \main_sdram_bankmachine0_row_opened $0\main_sdram_bankmachine0_row_opened[0:0] - update \main_sdram_bankmachine0_twtpcon_ready $0\main_sdram_bankmachine0_twtpcon_ready[0:0] - update \main_sdram_bankmachine0_twtpcon_count $0\main_sdram_bankmachine0_twtpcon_count[2:0] - update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - update \main_sdram_bankmachine1_cmd_buffer_source_valid $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - update \main_sdram_bankmachine1_cmd_buffer_source_first $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - update \main_sdram_bankmachine1_cmd_buffer_source_last $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - update \main_sdram_bankmachine1_row $0\main_sdram_bankmachine1_row[12:0] - update \main_sdram_bankmachine1_row_opened $0\main_sdram_bankmachine1_row_opened[0:0] - update \main_sdram_bankmachine1_twtpcon_ready $0\main_sdram_bankmachine1_twtpcon_ready[0:0] - update \main_sdram_bankmachine1_twtpcon_count $0\main_sdram_bankmachine1_twtpcon_count[2:0] - update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - update \main_sdram_bankmachine2_cmd_buffer_source_valid $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - update \main_sdram_bankmachine2_cmd_buffer_source_first $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - update \main_sdram_bankmachine2_cmd_buffer_source_last $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - update \main_sdram_bankmachine2_row $0\main_sdram_bankmachine2_row[12:0] - update \main_sdram_bankmachine2_row_opened $0\main_sdram_bankmachine2_row_opened[0:0] - update \main_sdram_bankmachine2_twtpcon_ready $0\main_sdram_bankmachine2_twtpcon_ready[0:0] - update \main_sdram_bankmachine2_twtpcon_count $0\main_sdram_bankmachine2_twtpcon_count[2:0] - update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - update \main_sdram_bankmachine3_cmd_buffer_source_valid $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - update \main_sdram_bankmachine3_cmd_buffer_source_first $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - update \main_sdram_bankmachine3_cmd_buffer_source_last $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - update \main_sdram_bankmachine3_row $0\main_sdram_bankmachine3_row[12:0] - update \main_sdram_bankmachine3_row_opened $0\main_sdram_bankmachine3_row_opened[0:0] - update \main_sdram_bankmachine3_twtpcon_ready $0\main_sdram_bankmachine3_twtpcon_ready[0:0] - update \main_sdram_bankmachine3_twtpcon_count $0\main_sdram_bankmachine3_twtpcon_count[2:0] - update \main_sdram_choose_cmd_grant $0\main_sdram_choose_cmd_grant[1:0] - update \main_sdram_choose_req_grant $0\main_sdram_choose_req_grant[1:0] - update \main_sdram_tccdcon_ready $0\main_sdram_tccdcon_ready[0:0] - update \main_sdram_tccdcon_count $0\main_sdram_tccdcon_count[0:0] - update \main_sdram_twtrcon_ready $0\main_sdram_twtrcon_ready[0:0] - update \main_sdram_twtrcon_count $0\main_sdram_twtrcon_count[2:0] - update \main_sdram_time0 $0\main_sdram_time0[4:0] - update \main_sdram_time1 $0\main_sdram_time1[3:0] - update \main_converter_counter $0\main_converter_counter[0:0] - update \main_converter_dat_r $0\main_converter_dat_r[31:0] - update \main_cmd_consumed $0\main_cmd_consumed[0:0] - update \main_wdata_consumed $0\main_wdata_consumed[0:0] - update \main_miso $0\main_miso[7:0] - update \main_control_storage $0\main_control_storage[15:0] - update \main_control_re $0\main_control_re[0:0] - update \main_mosi_storage $0\main_mosi_storage[7:0] - update \main_mosi_re $0\main_mosi_re[0:0] - update \main_cs_storage $0\main_cs_storage[0:0] - update \main_cs_re $0\main_cs_re[0:0] - update \main_loopback_storage $0\main_loopback_storage[0:0] - update \main_loopback_re $0\main_loopback_re[0:0] - update \main_count $0\main_count[2:0] - update \main_clk_divider1 $0\main_clk_divider1[15:0] - update \main_mosi_data $0\main_mosi_data[7:0] - update \main_mosi_sel $0\main_mosi_sel[2:0] - update \main_miso_data $0\main_miso_data[7:0] - update \libresocsim_clocker_storage $0\libresocsim_clocker_storage[8:0] - update \libresocsim_clocker_re $0\libresocsim_clocker_re[0:0] - update \libresocsim_clocker_clk0 $0\libresocsim_clocker_clk0[0:0] - update \libresocsim_clocker_clks $0\libresocsim_clocker_clks[8:0] - update \libresocsim_clocker_clk_d $0\libresocsim_clocker_clk_d[0:0] - update \libresocsim_init_count $0\libresocsim_init_count[7:0] - update \libresocsim_cmdw_count $0\libresocsim_cmdw_count[7:0] - update \libresocsim_cmdr_timeout $0\libresocsim_cmdr_timeout[31:0] - update \libresocsim_cmdr_count $0\libresocsim_cmdr_count[7:0] - update \libresocsim_cmdr_cmdr_run $0\libresocsim_cmdr_cmdr_run[0:0] - update \libresocsim_cmdr_cmdr_converter_source_first $0\libresocsim_cmdr_cmdr_converter_source_first[0:0] - update \libresocsim_cmdr_cmdr_converter_source_last $0\libresocsim_cmdr_cmdr_converter_source_last[0:0] - update \libresocsim_cmdr_cmdr_converter_source_payload_data $0\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] - update \libresocsim_cmdr_cmdr_converter_source_payload_valid_token_count $0\libresocsim_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - update \libresocsim_cmdr_cmdr_converter_demux $0\libresocsim_cmdr_cmdr_converter_demux[2:0] - update \libresocsim_cmdr_cmdr_converter_strobe_all $0\libresocsim_cmdr_cmdr_converter_strobe_all[0:0] - update \libresocsim_cmdr_cmdr_buf_source_valid $0\libresocsim_cmdr_cmdr_buf_source_valid[0:0] - update \libresocsim_cmdr_cmdr_buf_source_first $0\libresocsim_cmdr_cmdr_buf_source_first[0:0] - update \libresocsim_cmdr_cmdr_buf_source_last $0\libresocsim_cmdr_cmdr_buf_source_last[0:0] - update \libresocsim_cmdr_cmdr_buf_source_payload_data $0\libresocsim_cmdr_cmdr_buf_source_payload_data[7:0] - update \libresocsim_cmdr_cmdr_reset $0\libresocsim_cmdr_cmdr_reset[0:0] - update \libresocsim_dataw_count $0\libresocsim_dataw_count[7:0] - update \libresocsim_dataw_crcr_run $0\libresocsim_dataw_crcr_run[0:0] - update \libresocsim_dataw_crcr_converter_source_first $0\libresocsim_dataw_crcr_converter_source_first[0:0] - update \libresocsim_dataw_crcr_converter_source_last $0\libresocsim_dataw_crcr_converter_source_last[0:0] - update \libresocsim_dataw_crcr_converter_source_payload_data $0\libresocsim_dataw_crcr_converter_source_payload_data[7:0] - update \libresocsim_dataw_crcr_converter_source_payload_valid_token_count $0\libresocsim_dataw_crcr_converter_source_payload_valid_token_count[3:0] - update \libresocsim_dataw_crcr_converter_demux $0\libresocsim_dataw_crcr_converter_demux[2:0] - update \libresocsim_dataw_crcr_converter_strobe_all $0\libresocsim_dataw_crcr_converter_strobe_all[0:0] - update \libresocsim_dataw_crcr_buf_source_valid $0\libresocsim_dataw_crcr_buf_source_valid[0:0] - update \libresocsim_dataw_crcr_buf_source_first $0\libresocsim_dataw_crcr_buf_source_first[0:0] - update \libresocsim_dataw_crcr_buf_source_last $0\libresocsim_dataw_crcr_buf_source_last[0:0] - update \libresocsim_dataw_crcr_buf_source_payload_data $0\libresocsim_dataw_crcr_buf_source_payload_data[7:0] - update \libresocsim_dataw_crcr_reset $0\libresocsim_dataw_crcr_reset[0:0] - update \libresocsim_datar_timeout $0\libresocsim_datar_timeout[31:0] - update \libresocsim_datar_count $0\libresocsim_datar_count[9:0] - update \libresocsim_datar_datar_run $0\libresocsim_datar_datar_run[0:0] - update \libresocsim_datar_datar_converter_source_first $0\libresocsim_datar_datar_converter_source_first[0:0] - update \libresocsim_datar_datar_converter_source_last $0\libresocsim_datar_datar_converter_source_last[0:0] - update \libresocsim_datar_datar_converter_source_payload_data $0\libresocsim_datar_datar_converter_source_payload_data[7:0] - update \libresocsim_datar_datar_converter_source_payload_valid_token_count $0\libresocsim_datar_datar_converter_source_payload_valid_token_count[1:0] - update \libresocsim_datar_datar_converter_demux $0\libresocsim_datar_datar_converter_demux[0:0] - update \libresocsim_datar_datar_converter_strobe_all $0\libresocsim_datar_datar_converter_strobe_all[0:0] - update \libresocsim_datar_datar_buf_source_valid $0\libresocsim_datar_datar_buf_source_valid[0:0] - update \libresocsim_datar_datar_buf_source_first $0\libresocsim_datar_datar_buf_source_first[0:0] - update \libresocsim_datar_datar_buf_source_last $0\libresocsim_datar_datar_buf_source_last[0:0] - update \libresocsim_datar_datar_buf_source_payload_data $0\libresocsim_datar_datar_buf_source_payload_data[7:0] - update \libresocsim_datar_datar_reset $0\libresocsim_datar_datar_reset[0:0] - update \libresocsim_sdcore_cmd_argument_storage $0\libresocsim_sdcore_cmd_argument_storage[31:0] - update \libresocsim_sdcore_cmd_argument_re $0\libresocsim_sdcore_cmd_argument_re[0:0] - update \libresocsim_sdcore_cmd_command_storage $0\libresocsim_sdcore_cmd_command_storage[31:0] - update \libresocsim_sdcore_cmd_command_re $0\libresocsim_sdcore_cmd_command_re[0:0] - update \libresocsim_sdcore_cmd_response_status $0\libresocsim_sdcore_cmd_response_status[127:0] - update \libresocsim_sdcore_block_length_storage $0\libresocsim_sdcore_block_length_storage[9:0] - update \libresocsim_sdcore_block_length_re $0\libresocsim_sdcore_block_length_re[0:0] - update \libresocsim_sdcore_block_count_storage $0\libresocsim_sdcore_block_count_storage[31:0] - update \libresocsim_sdcore_block_count_re $0\libresocsim_sdcore_block_count_re[0:0] - update \libresocsim_sdcore_crc7_inserter_crcreg0 $0\libresocsim_sdcore_crc7_inserter_crcreg0[6:0] - update \libresocsim_sdcore_crc16_inserter_cnt $0\libresocsim_sdcore_crc16_inserter_cnt[2:0] - update \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 $0\libresocsim_sdcore_crc16_inserter_crc0_crcreg0[15:0] - update \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 $0\libresocsim_sdcore_crc16_inserter_crc1_crcreg0[15:0] - update \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 $0\libresocsim_sdcore_crc16_inserter_crc2_crcreg0[15:0] - update \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 $0\libresocsim_sdcore_crc16_inserter_crc3_crcreg0[15:0] - update \libresocsim_sdcore_crc16_inserter_crctmp0 $0\libresocsim_sdcore_crc16_inserter_crctmp0[15:0] - update \libresocsim_sdcore_crc16_inserter_crctmp1 $0\libresocsim_sdcore_crc16_inserter_crctmp1[15:0] - update \libresocsim_sdcore_crc16_inserter_crctmp2 $0\libresocsim_sdcore_crc16_inserter_crctmp2[15:0] - update \libresocsim_sdcore_crc16_inserter_crctmp3 $0\libresocsim_sdcore_crc16_inserter_crctmp3[15:0] - update \libresocsim_sdcore_crc16_checker_val $0\libresocsim_sdcore_crc16_checker_val[7:0] - update \libresocsim_sdcore_crc16_checker_cnt $0\libresocsim_sdcore_crc16_checker_cnt[3:0] - update \libresocsim_sdcore_crc16_checker_crc0_crcreg0 $0\libresocsim_sdcore_crc16_checker_crc0_crcreg0[15:0] - update \libresocsim_sdcore_crc16_checker_crc1_crcreg0 $0\libresocsim_sdcore_crc16_checker_crc1_crcreg0[15:0] - update \libresocsim_sdcore_crc16_checker_crc2_crcreg0 $0\libresocsim_sdcore_crc16_checker_crc2_crcreg0[15:0] - update \libresocsim_sdcore_crc16_checker_crc3_crcreg0 $0\libresocsim_sdcore_crc16_checker_crc3_crcreg0[15:0] - update \libresocsim_sdcore_crc16_checker_crctmp0 $0\libresocsim_sdcore_crc16_checker_crctmp0[15:0] - update \libresocsim_sdcore_crc16_checker_crctmp1 $0\libresocsim_sdcore_crc16_checker_crctmp1[15:0] - update \libresocsim_sdcore_crc16_checker_crctmp2 $0\libresocsim_sdcore_crc16_checker_crctmp2[15:0] - update \libresocsim_sdcore_crc16_checker_crctmp3 $0\libresocsim_sdcore_crc16_checker_crctmp3[15:0] - update \libresocsim_sdcore_crc16_checker_fifo0 $0\libresocsim_sdcore_crc16_checker_fifo0[15:0] - update \libresocsim_sdcore_crc16_checker_fifo1 $0\libresocsim_sdcore_crc16_checker_fifo1[15:0] - update \libresocsim_sdcore_crc16_checker_fifo2 $0\libresocsim_sdcore_crc16_checker_fifo2[15:0] - update \libresocsim_sdcore_crc16_checker_fifo3 $0\libresocsim_sdcore_crc16_checker_fifo3[15:0] - update \libresocsim_sdcore_cmd_count $0\libresocsim_sdcore_cmd_count[2:0] - update \libresocsim_sdcore_cmd_done $0\libresocsim_sdcore_cmd_done[0:0] - update \libresocsim_sdcore_cmd_error $0\libresocsim_sdcore_cmd_error[0:0] - update \libresocsim_sdcore_cmd_timeout $0\libresocsim_sdcore_cmd_timeout[0:0] - update \libresocsim_sdcore_data_count $0\libresocsim_sdcore_data_count[31:0] - update \libresocsim_sdcore_data_done $0\libresocsim_sdcore_data_done[0:0] - update \libresocsim_sdcore_data_error $0\libresocsim_sdcore_data_error[0:0] - update \libresocsim_sdcore_data_timeout $0\libresocsim_sdcore_data_timeout[0:0] - update \libresocsim_sdblock2mem_fifo_level $0\libresocsim_sdblock2mem_fifo_level[5:0] - update \libresocsim_sdblock2mem_fifo_produce $0\libresocsim_sdblock2mem_fifo_produce[4:0] - update \libresocsim_sdblock2mem_fifo_consume $0\libresocsim_sdblock2mem_fifo_consume[4:0] - update \libresocsim_sdblock2mem_converter_source_first $0\libresocsim_sdblock2mem_converter_source_first[0:0] - update \libresocsim_sdblock2mem_converter_source_last $0\libresocsim_sdblock2mem_converter_source_last[0:0] - update \libresocsim_sdblock2mem_converter_source_payload_data $0\libresocsim_sdblock2mem_converter_source_payload_data[31:0] - update \libresocsim_sdblock2mem_converter_source_payload_valid_token_count $0\libresocsim_sdblock2mem_converter_source_payload_valid_token_count[2:0] - update \libresocsim_sdblock2mem_converter_demux $0\libresocsim_sdblock2mem_converter_demux[1:0] - update \libresocsim_sdblock2mem_converter_strobe_all $0\libresocsim_sdblock2mem_converter_strobe_all[0:0] - update \libresocsim_sdblock2mem_wishbonedmawriter_base_storage $0\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] - update \libresocsim_sdblock2mem_wishbonedmawriter_base_re $0\libresocsim_sdblock2mem_wishbonedmawriter_base_re[0:0] - update \libresocsim_sdblock2mem_wishbonedmawriter_length_storage $0\libresocsim_sdblock2mem_wishbonedmawriter_length_storage[31:0] - update \libresocsim_sdblock2mem_wishbonedmawriter_length_re $0\libresocsim_sdblock2mem_wishbonedmawriter_length_re[0:0] - update \libresocsim_sdblock2mem_wishbonedmawriter_enable_storage $0\libresocsim_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - update \libresocsim_sdblock2mem_wishbonedmawriter_enable_re $0\libresocsim_sdblock2mem_wishbonedmawriter_enable_re[0:0] - update \libresocsim_sdblock2mem_wishbonedmawriter_loop_storage $0\libresocsim_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - update \libresocsim_sdblock2mem_wishbonedmawriter_loop_re $0\libresocsim_sdblock2mem_wishbonedmawriter_loop_re[0:0] - update \libresocsim_sdblock2mem_wishbonedmawriter_offset $0\libresocsim_sdblock2mem_wishbonedmawriter_offset[31:0] - update \libresocsim_sdmem2block_dma_data $0\libresocsim_sdmem2block_dma_data[31:0] - update \libresocsim_sdmem2block_dma_base_storage $0\libresocsim_sdmem2block_dma_base_storage[63:0] - update \libresocsim_sdmem2block_dma_base_re $0\libresocsim_sdmem2block_dma_base_re[0:0] - update \libresocsim_sdmem2block_dma_length_storage $0\libresocsim_sdmem2block_dma_length_storage[31:0] - update \libresocsim_sdmem2block_dma_length_re $0\libresocsim_sdmem2block_dma_length_re[0:0] - update \libresocsim_sdmem2block_dma_enable_storage $0\libresocsim_sdmem2block_dma_enable_storage[0:0] - update \libresocsim_sdmem2block_dma_enable_re $0\libresocsim_sdmem2block_dma_enable_re[0:0] - update \libresocsim_sdmem2block_dma_loop_storage $0\libresocsim_sdmem2block_dma_loop_storage[0:0] - update \libresocsim_sdmem2block_dma_loop_re $0\libresocsim_sdmem2block_dma_loop_re[0:0] - update \libresocsim_sdmem2block_dma_offset $0\libresocsim_sdmem2block_dma_offset[31:0] - update \libresocsim_sdmem2block_converter_mux $0\libresocsim_sdmem2block_converter_mux[1:0] - update \libresocsim_sdmem2block_fifo_level $0\libresocsim_sdmem2block_fifo_level[5:0] - update \libresocsim_sdmem2block_fifo_produce $0\libresocsim_sdmem2block_fifo_produce[4:0] - update \libresocsim_sdmem2block_fifo_consume $0\libresocsim_sdmem2block_fifo_consume[4:0] - update \libresocsim_miso $0\libresocsim_miso[7:0] - update \libresocsim_control_storage $0\libresocsim_control_storage[15:0] - update \libresocsim_control_re $0\libresocsim_control_re[0:0] - update \libresocsim_mosi_storage $0\libresocsim_mosi_storage[7:0] - update \libresocsim_mosi_re $0\libresocsim_mosi_re[0:0] - update \libresocsim_cs_storage $0\libresocsim_cs_storage[0:0] - update \libresocsim_cs_re $0\libresocsim_cs_re[0:0] - update \libresocsim_loopback_storage $0\libresocsim_loopback_storage[0:0] - update \libresocsim_loopback_re $0\libresocsim_loopback_re[0:0] - update \libresocsim_count $0\libresocsim_count[2:0] - update \libresocsim_clk_divider1 $0\libresocsim_clk_divider1[15:0] - update \libresocsim_mosi_data $0\libresocsim_mosi_data[7:0] - update \libresocsim_mosi_sel $0\libresocsim_mosi_sel[2:0] - update \libresocsim_miso_data $0\libresocsim_miso_data[7:0] - update \libresocsim_storage $0\libresocsim_storage[15:0] - update \libresocsim_re $0\libresocsim_re[0:0] - update \builder_converter0_state $0\builder_converter0_state[0:0] - update \builder_converter1_state $0\builder_converter1_state[0:0] - update \builder_refresher_state $0\builder_refresher_state[1:0] - update \builder_bankmachine0_state $0\builder_bankmachine0_state[2:0] - update \builder_bankmachine1_state $0\builder_bankmachine1_state[2:0] - update \builder_bankmachine2_state $0\builder_bankmachine2_state[2:0] - update \builder_bankmachine3_state $0\builder_bankmachine3_state[2:0] - update \builder_multiplexer_state $0\builder_multiplexer_state[2:0] - update \builder_new_master_wdata_ready $0\builder_new_master_wdata_ready[0:0] - update \builder_new_master_rdata_valid0 $0\builder_new_master_rdata_valid0[0:0] - update \builder_new_master_rdata_valid1 $0\builder_new_master_rdata_valid1[0:0] - update \builder_new_master_rdata_valid2 $0\builder_new_master_rdata_valid2[0:0] - update \builder_new_master_rdata_valid3 $0\builder_new_master_rdata_valid3[0:0] - update \builder_converter_state $0\builder_converter_state[0:0] - update \builder_spimaster0_state $0\builder_spimaster0_state[1:0] - update \builder_sdphy_sdphyinit_state $0\builder_sdphy_sdphyinit_state[0:0] - update \builder_sdphy_sdphycmdw_state $0\builder_sdphy_sdphycmdw_state[1:0] - update \builder_sdphy_sdphycmdr_state $0\builder_sdphy_sdphycmdr_state[2:0] - update \builder_sdphy_sdphycrcr_state $0\builder_sdphy_sdphycrcr_state[0:0] - update \builder_sdphy_fsm_state $0\builder_sdphy_fsm_state[2:0] - update \builder_sdphy_sdphydatar_state $0\builder_sdphy_sdphydatar_state[2:0] - update \builder_sdcore_crcupstreaminserter_state $0\builder_sdcore_crcupstreaminserter_state[0:0] - update \builder_sdcore_fsm_state $0\builder_sdcore_fsm_state[2:0] - update \builder_sdblock2memdma_state $0\builder_sdblock2memdma_state[1:0] - update \builder_sdmem2blockdma_fsm_state $0\builder_sdmem2blockdma_fsm_state[0:0] - update \builder_sdmem2blockdma_resetinserter_state $0\builder_sdmem2blockdma_resetinserter_state[1:0] - update \builder_spimaster1_state $0\builder_spimaster1_state[1:0] - update \builder_libresocsim_adr $0\builder_libresocsim_adr[13:0] - update \builder_libresocsim_we $0\builder_libresocsim_we[0:0] - update \builder_libresocsim_dat_w $0\builder_libresocsim_dat_w[7:0] - update \builder_grant $0\builder_grant[1:0] - update \builder_slave_sel_r $0\builder_slave_sel_r[4:0] - update \builder_count $0\builder_count[19:0] - update \builder_interface0_bank_bus_dat_r $0\builder_interface0_bank_bus_dat_r[7:0] - update \builder_interface1_bank_bus_dat_r $0\builder_interface1_bank_bus_dat_r[7:0] - update \builder_interface2_bank_bus_dat_r $0\builder_interface2_bank_bus_dat_r[7:0] - update \builder_interface3_bank_bus_dat_r $0\builder_interface3_bank_bus_dat_r[7:0] - update \builder_interface4_bank_bus_dat_r $0\builder_interface4_bank_bus_dat_r[7:0] - update \builder_interface5_bank_bus_dat_r $0\builder_interface5_bank_bus_dat_r[7:0] - update \builder_interface6_bank_bus_dat_r $0\builder_interface6_bank_bus_dat_r[7:0] - update \builder_interface7_bank_bus_dat_r $0\builder_interface7_bank_bus_dat_r[7:0] - update \builder_interface8_bank_bus_dat_r $0\builder_interface8_bank_bus_dat_r[7:0] - update \builder_interface9_bank_bus_dat_r $0\builder_interface9_bank_bus_dat_r[7:0] - update \builder_interface10_bank_bus_dat_r $0\builder_interface10_bank_bus_dat_r[7:0] - update \builder_interface11_bank_bus_dat_r $0\builder_interface11_bank_bus_dat_r[7:0] - update \builder_interface12_bank_bus_dat_r $0\builder_interface12_bank_bus_dat_r[7:0] - update \builder_state $0\builder_state[1:0] - update \builder_multiregimpl0_regs0 $0\builder_multiregimpl0_regs0[0:0] - update \builder_multiregimpl0_regs1 $0\builder_multiregimpl0_regs1[0:0] - update \builder_multiregimpl1_regs0 $0\builder_multiregimpl1_regs0[7:0] - update \builder_multiregimpl1_regs1 $0\builder_multiregimpl1_regs1[7:0] - update \builder_multiregimpl2_regs0 $0\builder_multiregimpl2_regs0[7:0] - update \builder_multiregimpl2_regs1 $0\builder_multiregimpl2_regs1[7:0] - end - attribute \src "ls180.v:706.5-706.46" - process $proc$ls180.v:706$2821 - assign { } { } - assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] - end - attribute \src "ls180.v:708.5-708.44" - process $proc$ls180.v:708$2822 - assign { } { } - assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] - end - attribute \src "ls180.v:709.5-709.45" - process $proc$ls180.v:709$2823 - assign { } { } - assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] - end - attribute \src "ls180.v:710.5-710.54" - process $proc$ls180.v:710$2824 - assign { } { } - assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:712.32-712.76" - process $proc$ls180.v:712$2825 - assign { } { } - assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] - end - attribute \src "ls180.v:713.11-713.55" - process $proc$ls180.v:713$2826 - assign { } { } - assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] - end - attribute \src "ls180.v:715.32-715.75" - process $proc$ls180.v:715$2827 - assign { } { } - assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:717.32-717.76" - process $proc$ls180.v:717$2828 - assign { } { } - assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] - sync init - end - attribute \src "ls180.v:723.5-723.51" - process $proc$ls180.v:723$2829 - assign { } { } - assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] - end - attribute \src "ls180.v:724.5-724.51" - process $proc$ls180.v:724$2830 - assign { } { } - assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] - end - attribute \src "ls180.v:726.5-726.47" - process $proc$ls180.v:726$2831 - assign { } { } - assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] - end - attribute \src "ls180.v:727.5-727.45" - process $proc$ls180.v:727$2832 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] - end - attribute \src "ls180.v:728.5-728.45" - process $proc$ls180.v:728$2833 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] - end - attribute \src "ls180.v:729.12-729.57" - process $proc$ls180.v:729$2834 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] - end - attribute \src "ls180.v:731.5-731.51" - process $proc$ls180.v:731$2835 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:732.5-732.51" - process $proc$ls180.v:732$2836 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:733.5-733.50" - process $proc$ls180.v:733$2837 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] - end - attribute \src "ls180.v:734.5-734.54" - process $proc$ls180.v:734$2838 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:735.5-735.55" - process $proc$ls180.v:735$2839 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:736.5-736.56" - process $proc$ls180.v:736$2840 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:737.5-737.50" - process $proc$ls180.v:737$2841 - assign { } { } - assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] - end - attribute \src "ls180.v:740.5-740.67" - process $proc$ls180.v:740$2842 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] - sync init - end - attribute \src "ls180.v:741.5-741.66" - process $proc$ls180.v:741$2843 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] - sync init - end - attribute \src "ls180.v:756.11-756.68" - process $proc$ls180.v:756$2844 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:757.5-757.64" - process $proc$ls180.v:757$2845 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:758.11-758.70" - process $proc$ls180.v:758$2846 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:759.11-759.70" - process $proc$ls180.v:759$2847 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - end - attribute \src "ls180.v:760.11-760.73" - process $proc$ls180.v:760$2848 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:781.5-781.59" - process $proc$ls180.v:781$2849 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:783.5-783.59" - process $proc$ls180.v:783$2850 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:784.5-784.58" - process $proc$ls180.v:784$2851 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:785.5-785.64" - process $proc$ls180.v:785$2852 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:786.12-786.74" - process $proc$ls180.v:786$2853 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:787.12-787.47" - process $proc$ls180.v:787$2854 - assign { } { } - assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] - end - attribute \src "ls180.v:788.5-788.46" - process $proc$ls180.v:788$2855 - assign { } { } - assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] - end - attribute \src "ls180.v:790.5-790.44" - process $proc$ls180.v:790$2856 - assign { } { } - assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] - end - attribute \src "ls180.v:791.5-791.45" - process $proc$ls180.v:791$2857 - assign { } { } - assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] - end - attribute \src "ls180.v:792.5-792.54" - process $proc$ls180.v:792$2858 - assign { } { } - assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:794.32-794.76" - process $proc$ls180.v:794$2859 - assign { } { } - assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] - end - attribute \src "ls180.v:795.11-795.55" - process $proc$ls180.v:795$2860 - assign { } { } - assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] - end - attribute \src "ls180.v:797.32-797.75" - process $proc$ls180.v:797$2861 - assign { } { } - assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:799.32-799.76" - process $proc$ls180.v:799$2862 - assign { } { } - assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] - sync init - end - attribute \src "ls180.v:802.5-802.44" - process $proc$ls180.v:802$2863 - assign { } { } - assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] - sync init - end - attribute \src "ls180.v:803.5-803.45" - process $proc$ls180.v:803$2864 - assign { } { } - assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] - sync init - end - attribute \src "ls180.v:804.5-804.43" - process $proc$ls180.v:804$2865 - assign { } { } - assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] - sync init - end - attribute \src "ls180.v:805.5-805.48" - process $proc$ls180.v:805$2866 - assign { } { } - assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] - sync init - end - attribute \src "ls180.v:807.5-807.43" - process $proc$ls180.v:807$2867 - assign { } { } - assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] - sync init - end - attribute \src "ls180.v:810.5-810.49" - process $proc$ls180.v:810$2868 - assign { } { } - assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:811.5-811.49" - process $proc$ls180.v:811$2869 - assign { } { } - assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:812.5-812.48" - process $proc$ls180.v:812$2870 - assign { } { } - assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] - end - attribute \src "ls180.v:816.11-816.46" - process $proc$ls180.v:816$2871 - assign { } { } - assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 - sync always - sync init - update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] - end - attribute \src "ls180.v:818.11-818.45" - process $proc$ls180.v:818$2872 - assign { } { } - assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 - sync always - sync init - update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] - end - attribute \src "ls180.v:820.5-820.44" - process $proc$ls180.v:820$2873 - assign { } { } - assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] - end - attribute \src "ls180.v:821.5-821.45" - process $proc$ls180.v:821$2874 - assign { } { } - assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] - end - attribute \src "ls180.v:823.5-823.48" - process $proc$ls180.v:823$2875 - assign { } { } - assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] - end - attribute \src "ls180.v:825.5-825.43" - process $proc$ls180.v:825$2876 - assign { } { } - assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] - end - attribute \src "ls180.v:828.5-828.49" - process $proc$ls180.v:828$2877 - assign { } { } - assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:829.5-829.49" - process $proc$ls180.v:829$2878 - assign { } { } - assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:830.5-830.48" - process $proc$ls180.v:830$2879 - assign { } { } - assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0] - end - attribute \src "ls180.v:834.11-834.46" - process $proc$ls180.v:834$2880 - assign { } { } - assign $1\main_sdram_choose_req_valids[3:0] 4'0000 - sync always - sync init - update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] - end - attribute \src "ls180.v:836.11-836.45" - process $proc$ls180.v:836$2881 - assign { } { } - assign $1\main_sdram_choose_req_grant[1:0] 2'00 - sync always - sync init - update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0] - end - attribute \src "ls180.v:838.12-838.36" - process $proc$ls180.v:838$2882 - assign { } { } - assign $0\main_sdram_nop_a[12:0] 13'0000000000000 - sync always - update \main_sdram_nop_a $0\main_sdram_nop_a[12:0] - sync init - end - attribute \src "ls180.v:839.11-839.35" - process $proc$ls180.v:839$2883 - assign { } { } - assign $0\main_sdram_nop_ba[1:0] 2'00 - sync always - update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0] - sync init - end - attribute \src "ls180.v:840.11-840.40" - process $proc$ls180.v:840$2884 - assign { } { } - assign $1\main_sdram_steerer_sel[1:0] 2'00 - sync always - sync init - update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0] - end - attribute \src "ls180.v:841.5-841.31" - process $proc$ls180.v:841$2885 - assign { } { } - assign $0\main_sdram_steerer0[0:0] 1'1 - sync always - update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0] - sync init - end - attribute \src "ls180.v:842.5-842.31" - process $proc$ls180.v:842$2886 - assign { } { } - assign $0\main_sdram_steerer1[0:0] 1'1 - sync always - update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0] - sync init - end - attribute \src "ls180.v:844.32-844.63" - process $proc$ls180.v:844$2887 - assign { } { } - assign $0\main_sdram_trrdcon_ready[0:0] 1'1 - sync always - update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0] - sync init - end - attribute \src "ls180.v:846.32-846.63" - process $proc$ls180.v:846$2888 - assign { } { } - assign $0\main_sdram_tfawcon_ready[0:0] 1'1 - sync always - update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0] - sync init - end - attribute \src "ls180.v:848.32-848.63" - process $proc$ls180.v:848$2889 - assign { } { } - assign $1\main_sdram_tccdcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0] - end - attribute \src "ls180.v:849.5-849.36" - process $proc$ls180.v:849$2890 - assign { } { } - assign $1\main_sdram_tccdcon_count[0:0] 1'0 - sync always - sync init - update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0] - end - attribute \src "ls180.v:851.32-851.63" - process $proc$ls180.v:851$2891 - assign { } { } - assign $1\main_sdram_twtrcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] - end - attribute \src "ls180.v:852.11-852.42" - process $proc$ls180.v:852$2892 - assign { } { } - assign $1\main_sdram_twtrcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] - end - attribute \src "ls180.v:855.5-855.26" - process $proc$ls180.v:855$2893 - assign { } { } - assign $1\main_sdram_en0[0:0] 1'0 - sync always - sync init - update \main_sdram_en0 $1\main_sdram_en0[0:0] - end - attribute \src "ls180.v:857.11-857.34" - process $proc$ls180.v:857$2894 - assign { } { } - assign $1\main_sdram_time0[4:0] 5'00000 - sync always - sync init - update \main_sdram_time0 $1\main_sdram_time0[4:0] - end - attribute \src "ls180.v:858.5-858.26" - process $proc$ls180.v:858$2895 - assign { } { } - assign $1\main_sdram_en1[0:0] 1'0 - sync always - sync init - update \main_sdram_en1 $1\main_sdram_en1[0:0] - end - attribute \src "ls180.v:860.11-860.34" - process $proc$ls180.v:860$2896 - assign { } { } - assign $1\main_sdram_time1[3:0] 4'0000 - sync always - sync init - update \main_sdram_time1 $1\main_sdram_time1[3:0] - end - attribute \src "ls180.v:88.11-88.52" - process $proc$ls180.v:88$2573 - assign { } { } - assign $0\main_libresocsim_libresoc_dmi_addr[3:0] 4'0000 - sync always - update \main_libresocsim_libresoc_dmi_addr $0\main_libresocsim_libresoc_dmi_addr[3:0] - sync init - end - attribute \src "ls180.v:881.5-881.29" - process $proc$ls180.v:881$2897 - assign { } { } - assign $1\main_wb_sdram_ack[0:0] 1'0 - sync always - sync init - update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] - end - attribute \src "ls180.v:885.5-885.29" - process $proc$ls180.v:885$2898 - assign { } { } - assign $0\main_wb_sdram_err[0:0] 1'0 - sync always - update \main_wb_sdram_err $0\main_wb_sdram_err[0:0] - sync init - end - attribute \src "ls180.v:886.12-886.40" - process $proc$ls180.v:886$2899 - assign { } { } - assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 - sync always - sync init - update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0] - end - attribute \src "ls180.v:887.12-887.42" - process $proc$ls180.v:887$2900 - assign { } { } - assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000 - sync always - sync init - update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0] - end - attribute \src "ls180.v:889.11-889.38" - process $proc$ls180.v:889$2901 - assign { } { } - assign $1\main_litedram_wb_sel[1:0] 2'00 - sync always - sync init - update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0] - end - attribute \src "ls180.v:89.12-89.53" - process $proc$ls180.v:89$2574 - assign { } { } - assign $0\main_libresocsim_libresoc_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - update \main_libresocsim_libresoc_dmi_din $0\main_libresocsim_libresoc_dmi_din[63:0] - sync init - end - attribute \src "ls180.v:890.5-890.32" - process $proc$ls180.v:890$2902 - assign { } { } - assign $1\main_litedram_wb_cyc[0:0] 1'0 - sync always - sync init - update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] - end - attribute \src "ls180.v:891.5-891.32" - process $proc$ls180.v:891$2903 - assign { } { } - assign $1\main_litedram_wb_stb[0:0] 1'0 - sync always - sync init - update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] - end - attribute \src "ls180.v:893.5-893.31" - process $proc$ls180.v:893$2904 - assign { } { } - assign $1\main_litedram_wb_we[0:0] 1'0 - sync always - sync init - update \main_litedram_wb_we $1\main_litedram_wb_we[0:0] - end - attribute \src "ls180.v:894.5-894.31" - process $proc$ls180.v:894$2905 - assign { } { } - assign $1\main_converter_skip[0:0] 1'0 - sync always - sync init - update \main_converter_skip $1\main_converter_skip[0:0] - end - attribute \src "ls180.v:895.5-895.34" - process $proc$ls180.v:895$2906 - assign { } { } - assign $1\main_converter_counter[0:0] 1'0 - sync always - sync init - update \main_converter_counter $1\main_converter_counter[0:0] - end - attribute \src "ls180.v:897.12-897.40" - process $proc$ls180.v:897$2907 - assign { } { } - assign $1\main_converter_dat_r[31:0] 0 - sync always - sync init - update \main_converter_dat_r $1\main_converter_dat_r[31:0] - end - attribute \src "ls180.v:898.5-898.29" - process $proc$ls180.v:898$2908 - assign { } { } - assign $1\main_cmd_consumed[0:0] 1'0 - sync always - sync init - update \main_cmd_consumed $1\main_cmd_consumed[0:0] - end - attribute \src "ls180.v:899.5-899.31" - process $proc$ls180.v:899$2909 - assign { } { } - assign $1\main_wdata_consumed[0:0] 1'0 - sync always - sync init - update \main_wdata_consumed $1\main_wdata_consumed[0:0] - end - attribute \src "ls180.v:909.5-909.22" - process $proc$ls180.v:909$2910 - assign { } { } - assign $1\main_done0[0:0] 1'0 - sync always - sync init - update \main_done0 $1\main_done0[0:0] - end - attribute \src "ls180.v:91.5-91.44" - process $proc$ls180.v:91$2575 - assign { } { } - assign $0\main_libresocsim_libresoc_dmi_wr[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_dmi_wr $0\main_libresocsim_libresoc_dmi_wr[0:0] - sync init - end - attribute \src "ls180.v:910.5-910.20" - process $proc$ls180.v:910$2911 - assign { } { } - assign $1\main_irq[0:0] 1'0 - sync always - sync init - update \main_irq $1\main_irq[0:0] - end - attribute \src "ls180.v:912.11-912.27" - process $proc$ls180.v:912$2912 - assign { } { } - assign $1\main_miso[7:0] 8'00000000 - sync always - sync init - update \main_miso $1\main_miso[7:0] - end - attribute \src "ls180.v:915.12-915.37" - process $proc$ls180.v:915$2913 - assign { } { } - assign $0\main_clk_divider0[15:0] 16'0000000000000111 - sync always - update \main_clk_divider0 $0\main_clk_divider0[15:0] - sync init - end - attribute \src "ls180.v:916.5-916.23" - process $proc$ls180.v:916$2914 - assign { } { } - assign $1\main_start1[0:0] 1'0 - sync always - sync init - update \main_start1 $1\main_start1[0:0] - end - attribute \src "ls180.v:918.12-918.40" - process $proc$ls180.v:918$2915 - assign { } { } - assign $1\main_control_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_control_storage $1\main_control_storage[15:0] - end - attribute \src "ls180.v:919.5-919.27" - process $proc$ls180.v:919$2916 - assign { } { } - assign $1\main_control_re[0:0] 1'0 - sync always - sync init - update \main_control_re $1\main_control_re[0:0] - end - attribute \src "ls180.v:923.11-923.35" - process $proc$ls180.v:923$2917 - assign { } { } - assign $1\main_mosi_storage[7:0] 8'00000000 - sync always - sync init - update \main_mosi_storage $1\main_mosi_storage[7:0] - end - attribute \src "ls180.v:924.5-924.24" - process $proc$ls180.v:924$2918 - assign { } { } - assign $1\main_mosi_re[0:0] 1'0 - sync always - sync init - update \main_mosi_re $1\main_mosi_re[0:0] - end - attribute \src "ls180.v:928.5-928.27" - process $proc$ls180.v:928$2919 - assign { } { } - assign $1\main_cs_storage[0:0] 1'1 - sync always - sync init - update \main_cs_storage $1\main_cs_storage[0:0] - end - attribute \src "ls180.v:929.5-929.22" - process $proc$ls180.v:929$2920 - assign { } { } - assign $1\main_cs_re[0:0] 1'0 - sync always - sync init - update \main_cs_re $1\main_cs_re[0:0] - end - attribute \src "ls180.v:93.5-93.45" - process $proc$ls180.v:93$2576 - assign { } { } - assign $0\main_libresocsim_libresoc_dmi_req[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_dmi_req $0\main_libresocsim_libresoc_dmi_req[0:0] - sync init - end - attribute \src "ls180.v:930.5-930.33" - process $proc$ls180.v:930$2921 - assign { } { } - assign $1\main_loopback_storage[0:0] 1'0 - sync always - sync init - update \main_loopback_storage $1\main_loopback_storage[0:0] - end - attribute \src "ls180.v:931.5-931.28" - process $proc$ls180.v:931$2922 - assign { } { } - assign $1\main_loopback_re[0:0] 1'0 - sync always - sync init - update \main_loopback_re $1\main_loopback_re[0:0] - end - attribute \src "ls180.v:932.5-932.27" - process $proc$ls180.v:932$2923 - assign { } { } - assign $1\main_clk_enable[0:0] 1'0 - sync always - sync init - update \main_clk_enable $1\main_clk_enable[0:0] - end - attribute \src "ls180.v:933.5-933.26" - process $proc$ls180.v:933$2924 - assign { } { } - assign $1\main_cs_enable[0:0] 1'0 - sync always - sync init - update \main_cs_enable $1\main_cs_enable[0:0] - end - attribute \src "ls180.v:934.11-934.28" - process $proc$ls180.v:934$2925 - assign { } { } - assign $1\main_count[2:0] 3'000 - sync always - sync init - update \main_count $1\main_count[2:0] - end - attribute \src "ls180.v:935.5-935.27" - process $proc$ls180.v:935$2926 - assign { } { } - assign $1\main_mosi_latch[0:0] 1'0 - sync always - sync init - update \main_mosi_latch $1\main_mosi_latch[0:0] - end - attribute \src "ls180.v:936.5-936.27" - process $proc$ls180.v:936$2927 - assign { } { } - assign $1\main_miso_latch[0:0] 1'0 - sync always - sync init - update \main_miso_latch $1\main_miso_latch[0:0] - end - attribute \src "ls180.v:9368.1-9378.4" - process $proc$ls180.v:9368$2459 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\mem$ls180.v:9376$4_ADDR[6:0]$2469 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:9376$4_DATA[31:0]$2470 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:9376$4_EN[31:0]$2471 0 - assign $0$memwr$\mem$ls180.v:9374$3_ADDR[6:0]$2466 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:9374$3_DATA[31:0]$2467 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:9374$3_EN[31:0]$2468 0 - assign $0$memwr$\mem$ls180.v:9372$2_ADDR[6:0]$2463 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:9372$2_DATA[31:0]$2464 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:9372$2_EN[31:0]$2465 0 - assign $0$memwr$\mem$ls180.v:9370$1_ADDR[6:0]$2460 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:9370$1_DATA[31:0]$2461 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:9370$1_EN[31:0]$2462 0 - assign $0\memadr[6:0] \main_libresocsim_adr - attribute \src "ls180.v:9369.2-9370.65" - switch \main_libresocsim_we [0] - attribute \src "ls180.v:9369.6-9369.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:9370$1_ADDR[6:0]$2460 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:9370$1_DATA[31:0]$2461 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] } - assign $0$memwr$\mem$ls180.v:9370$1_EN[31:0]$2462 255 - case - end - attribute \src "ls180.v:9371.2-9372.67" - switch \main_libresocsim_we [1] - attribute \src "ls180.v:9371.6-9371.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:9372$2_ADDR[6:0]$2463 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:9372$2_DATA[31:0]$2464 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem$ls180.v:9372$2_EN[31:0]$2465 65280 - case - end - attribute \src "ls180.v:9373.2-9374.69" - switch \main_libresocsim_we [2] - attribute \src "ls180.v:9373.6-9373.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:9374$3_ADDR[6:0]$2466 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:9374$3_DATA[31:0]$2467 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:9374$3_EN[31:0]$2468 16711680 - case - end - attribute \src "ls180.v:9375.2-9376.69" - switch \main_libresocsim_we [3] - attribute \src "ls180.v:9375.6-9375.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:9376$4_ADDR[6:0]$2469 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:9376$4_DATA[31:0]$2470 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:9376$4_EN[31:0]$2471 32'11111111000000000000000000000000 - case - end - sync posedge \sys_clk_1 - update \memadr $0\memadr[6:0] - update $memwr$\mem$ls180.v:9370$1_ADDR $0$memwr$\mem$ls180.v:9370$1_ADDR[6:0]$2460 - update $memwr$\mem$ls180.v:9370$1_DATA $0$memwr$\mem$ls180.v:9370$1_DATA[31:0]$2461 - update $memwr$\mem$ls180.v:9370$1_EN $0$memwr$\mem$ls180.v:9370$1_EN[31:0]$2462 - update $memwr$\mem$ls180.v:9372$2_ADDR $0$memwr$\mem$ls180.v:9372$2_ADDR[6:0]$2463 - update $memwr$\mem$ls180.v:9372$2_DATA $0$memwr$\mem$ls180.v:9372$2_DATA[31:0]$2464 - update $memwr$\mem$ls180.v:9372$2_EN $0$memwr$\mem$ls180.v:9372$2_EN[31:0]$2465 - update $memwr$\mem$ls180.v:9374$3_ADDR $0$memwr$\mem$ls180.v:9374$3_ADDR[6:0]$2466 - update $memwr$\mem$ls180.v:9374$3_DATA $0$memwr$\mem$ls180.v:9374$3_DATA[31:0]$2467 - update $memwr$\mem$ls180.v:9374$3_EN $0$memwr$\mem$ls180.v:9374$3_EN[31:0]$2468 - update $memwr$\mem$ls180.v:9376$4_ADDR $0$memwr$\mem$ls180.v:9376$4_ADDR[6:0]$2469 - update $memwr$\mem$ls180.v:9376$4_DATA $0$memwr$\mem$ls180.v:9376$4_DATA[31:0]$2470 - update $memwr$\mem$ls180.v:9376$4_EN $0$memwr$\mem$ls180.v:9376$4_EN[31:0]$2471 - end - attribute \src "ls180.v:937.12-937.37" - process $proc$ls180.v:937$2928 - assign { } { } - assign $1\main_clk_divider1[15:0] 16'0000000000000000 - sync always - sync init - update \main_clk_divider1 $1\main_clk_divider1[15:0] - end - attribute \src "ls180.v:9389.1-9393.4" - process $proc$ls180.v:9389$2473 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage$ls180.v:9391$5_ADDR[3:0]$2474 4'xxxx - assign $0$memwr$\storage$ls180.v:9391$5_DATA[9:0]$2475 10'xxxxxxxxxx - assign $0$memwr$\storage$ls180.v:9391$5_EN[9:0]$2476 10'0000000000 - assign $0\memdat[9:0] $memrd$\storage$ls180.v:9392$2477_DATA - attribute \src "ls180.v:9390.2-9391.99" - switch \main_libresocsim_uart_tx_fifo_wrport_we - attribute \src "ls180.v:9390.6-9390.45" - case 1'1 - assign $0$memwr$\storage$ls180.v:9391$5_ADDR[3:0]$2474 \main_libresocsim_uart_tx_fifo_wrport_adr - assign $0$memwr$\storage$ls180.v:9391$5_DATA[9:0]$2475 \main_libresocsim_uart_tx_fifo_wrport_dat_w - assign $0$memwr$\storage$ls180.v:9391$5_EN[9:0]$2476 10'1111111111 - case - end - sync posedge \sys_clk_1 - update \memdat $0\memdat[9:0] - update $memwr$\storage$ls180.v:9391$5_ADDR $0$memwr$\storage$ls180.v:9391$5_ADDR[3:0]$2474 - update $memwr$\storage$ls180.v:9391$5_DATA $0$memwr$\storage$ls180.v:9391$5_DATA[9:0]$2475 - update $memwr$\storage$ls180.v:9391$5_EN $0$memwr$\storage$ls180.v:9391$5_EN[9:0]$2476 - end - attribute \src "ls180.v:9395.1-9398.4" - process $proc$ls180.v:9395$2478 - assign $0\memdat_1[9:0] \memdat_1 - attribute \src "ls180.v:9396.2-9397.65" - switch \main_libresocsim_uart_tx_fifo_rdport_re - attribute \src "ls180.v:9396.6-9396.45" - case 1'1 - assign $0\memdat_1[9:0] $memrd$\storage$ls180.v:9397$2479_DATA - case - end - sync posedge \sys_clk_1 - update \memdat_1 $0\memdat_1[9:0] - end - attribute \src "ls180.v:940.11-940.32" - process $proc$ls180.v:940$2929 - assign { } { } - assign $1\main_mosi_data[7:0] 8'00000000 - sync always - sync init - update \main_mosi_data $1\main_mosi_data[7:0] - end - attribute \src "ls180.v:9406.1-9410.4" - process $proc$ls180.v:9406$2480 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_1$ls180.v:9408$6_ADDR[3:0]$2481 4'xxxx - assign $0$memwr$\storage_1$ls180.v:9408$6_DATA[9:0]$2482 10'xxxxxxxxxx - assign $0$memwr$\storage_1$ls180.v:9408$6_EN[9:0]$2483 10'0000000000 - assign $0\memdat_2[9:0] $memrd$\storage_1$ls180.v:9409$2484_DATA - attribute \src "ls180.v:9407.2-9408.101" - switch \main_libresocsim_uart_rx_fifo_wrport_we - attribute \src "ls180.v:9407.6-9407.45" - case 1'1 - assign $0$memwr$\storage_1$ls180.v:9408$6_ADDR[3:0]$2481 \main_libresocsim_uart_rx_fifo_wrport_adr - assign $0$memwr$\storage_1$ls180.v:9408$6_DATA[9:0]$2482 \main_libresocsim_uart_rx_fifo_wrport_dat_w - assign $0$memwr$\storage_1$ls180.v:9408$6_EN[9:0]$2483 10'1111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_2 $0\memdat_2[9:0] - update $memwr$\storage_1$ls180.v:9408$6_ADDR $0$memwr$\storage_1$ls180.v:9408$6_ADDR[3:0]$2481 - update $memwr$\storage_1$ls180.v:9408$6_DATA $0$memwr$\storage_1$ls180.v:9408$6_DATA[9:0]$2482 - update $memwr$\storage_1$ls180.v:9408$6_EN $0$memwr$\storage_1$ls180.v:9408$6_EN[9:0]$2483 - end - attribute \src "ls180.v:941.11-941.31" - process $proc$ls180.v:941$2930 - assign { } { } - assign $1\main_mosi_sel[2:0] 3'000 - sync always - sync init - update \main_mosi_sel $1\main_mosi_sel[2:0] - end - attribute \src "ls180.v:9412.1-9415.4" - process $proc$ls180.v:9412$2485 - assign $0\memdat_3[9:0] \memdat_3 - attribute \src "ls180.v:9413.2-9414.67" - switch \main_libresocsim_uart_rx_fifo_rdport_re - attribute \src "ls180.v:9413.6-9413.45" - case 1'1 - assign $0\memdat_3[9:0] $memrd$\storage_1$ls180.v:9414$2486_DATA - case - end - sync posedge \sys_clk_1 - update \memdat_3 $0\memdat_3[9:0] - end - attribute \src "ls180.v:942.11-942.32" - process $proc$ls180.v:942$2931 - assign { } { } - assign $1\main_miso_data[7:0] 8'00000000 - sync always - sync init - update \main_miso_data $1\main_miso_data[7:0] - end - attribute \src "ls180.v:9422.1-9426.4" - process $proc$ls180.v:9422$2487 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_2$ls180.v:9424$7_ADDR[2:0]$2488 3'xxx - assign $0$memwr$\storage_2$ls180.v:9424$7_DATA[24:0]$2489 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_2$ls180.v:9424$7_EN[24:0]$2490 25'0000000000000000000000000 - assign $0\memdat_4[24:0] $memrd$\storage_2$ls180.v:9425$2491_DATA - attribute \src "ls180.v:9423.2-9424.131" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:9423.6-9423.60" - case 1'1 - assign $0$memwr$\storage_2$ls180.v:9424$7_ADDR[2:0]$2488 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_2$ls180.v:9424$7_DATA[24:0]$2489 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_2$ls180.v:9424$7_EN[24:0]$2490 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_4 $0\memdat_4[24:0] - update $memwr$\storage_2$ls180.v:9424$7_ADDR $0$memwr$\storage_2$ls180.v:9424$7_ADDR[2:0]$2488 - update $memwr$\storage_2$ls180.v:9424$7_DATA $0$memwr$\storage_2$ls180.v:9424$7_DATA[24:0]$2489 - update $memwr$\storage_2$ls180.v:9424$7_EN $0$memwr$\storage_2$ls180.v:9424$7_EN[24:0]$2490 - end - attribute \src "ls180.v:9428.1-9429.4" - process $proc$ls180.v:9428$2492 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:9436.1-9440.4" - process $proc$ls180.v:9436$2494 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_3$ls180.v:9438$8_ADDR[2:0]$2495 3'xxx - assign $0$memwr$\storage_3$ls180.v:9438$8_DATA[24:0]$2496 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_3$ls180.v:9438$8_EN[24:0]$2497 25'0000000000000000000000000 - assign $0\memdat_5[24:0] $memrd$\storage_3$ls180.v:9439$2498_DATA - attribute \src "ls180.v:9437.2-9438.131" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:9437.6-9437.60" - case 1'1 - assign $0$memwr$\storage_3$ls180.v:9438$8_ADDR[2:0]$2495 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_3$ls180.v:9438$8_DATA[24:0]$2496 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_3$ls180.v:9438$8_EN[24:0]$2497 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_5 $0\memdat_5[24:0] - update $memwr$\storage_3$ls180.v:9438$8_ADDR $0$memwr$\storage_3$ls180.v:9438$8_ADDR[2:0]$2495 - update $memwr$\storage_3$ls180.v:9438$8_DATA $0$memwr$\storage_3$ls180.v:9438$8_DATA[24:0]$2496 - update $memwr$\storage_3$ls180.v:9438$8_EN $0$memwr$\storage_3$ls180.v:9438$8_EN[24:0]$2497 - end - attribute \src "ls180.v:9442.1-9443.4" - process $proc$ls180.v:9442$2499 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:945.11-945.47" - process $proc$ls180.v:945$2932 - assign { } { } - assign $1\libresocsim_clocker_storage[8:0] 9'100000000 - sync always - sync init - update \libresocsim_clocker_storage $1\libresocsim_clocker_storage[8:0] - end - attribute \src "ls180.v:9450.1-9454.4" - process $proc$ls180.v:9450$2501 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_4$ls180.v:9452$9_ADDR[2:0]$2502 3'xxx - assign $0$memwr$\storage_4$ls180.v:9452$9_DATA[24:0]$2503 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_4$ls180.v:9452$9_EN[24:0]$2504 25'0000000000000000000000000 - assign $0\memdat_6[24:0] $memrd$\storage_4$ls180.v:9453$2505_DATA - attribute \src "ls180.v:9451.2-9452.131" - switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:9451.6-9451.60" - case 1'1 - assign $0$memwr$\storage_4$ls180.v:9452$9_ADDR[2:0]$2502 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_4$ls180.v:9452$9_DATA[24:0]$2503 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_4$ls180.v:9452$9_EN[24:0]$2504 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_6 $0\memdat_6[24:0] - update $memwr$\storage_4$ls180.v:9452$9_ADDR $0$memwr$\storage_4$ls180.v:9452$9_ADDR[2:0]$2502 - update $memwr$\storage_4$ls180.v:9452$9_DATA $0$memwr$\storage_4$ls180.v:9452$9_DATA[24:0]$2503 - update $memwr$\storage_4$ls180.v:9452$9_EN $0$memwr$\storage_4$ls180.v:9452$9_EN[24:0]$2504 - end - attribute \src "ls180.v:9456.1-9457.4" - process $proc$ls180.v:9456$2506 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:946.5-946.34" - process $proc$ls180.v:946$2933 - assign { } { } - assign $1\libresocsim_clocker_re[0:0] 1'0 - sync always - sync init - update \libresocsim_clocker_re $1\libresocsim_clocker_re[0:0] - end - attribute \src "ls180.v:9464.1-9468.4" - process $proc$ls180.v:9464$2508 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_5$ls180.v:9466$10_ADDR[2:0]$2509 3'xxx - assign $0$memwr$\storage_5$ls180.v:9466$10_DATA[24:0]$2510 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_5$ls180.v:9466$10_EN[24:0]$2511 25'0000000000000000000000000 - assign $0\memdat_7[24:0] $memrd$\storage_5$ls180.v:9467$2512_DATA - attribute \src "ls180.v:9465.2-9466.131" - switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:9465.6-9465.60" - case 1'1 - assign $0$memwr$\storage_5$ls180.v:9466$10_ADDR[2:0]$2509 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_5$ls180.v:9466$10_DATA[24:0]$2510 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_5$ls180.v:9466$10_EN[24:0]$2511 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_7 $0\memdat_7[24:0] - update $memwr$\storage_5$ls180.v:9466$10_ADDR $0$memwr$\storage_5$ls180.v:9466$10_ADDR[2:0]$2509 - update $memwr$\storage_5$ls180.v:9466$10_DATA $0$memwr$\storage_5$ls180.v:9466$10_DATA[24:0]$2510 - update $memwr$\storage_5$ls180.v:9466$10_EN $0$memwr$\storage_5$ls180.v:9466$10_EN[24:0]$2511 - end - attribute \src "ls180.v:9470.1-9471.4" - process $proc$ls180.v:9470$2513 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:9478.1-9482.4" - process $proc$ls180.v:9478$2515 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_6$ls180.v:9480$11_ADDR[4:0]$2516 5'xxxxx - assign $0$memwr$\storage_6$ls180.v:9480$11_DATA[9:0]$2517 10'xxxxxxxxxx - assign $0$memwr$\storage_6$ls180.v:9480$11_EN[9:0]$2518 10'0000000000 - assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:9481$2519_DATA - attribute \src "ls180.v:9479.2-9480.99" - switch \libresocsim_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:9479.6-9479.44" - case 1'1 - assign $0$memwr$\storage_6$ls180.v:9480$11_ADDR[4:0]$2516 \libresocsim_sdblock2mem_fifo_wrport_adr - assign $0$memwr$\storage_6$ls180.v:9480$11_DATA[9:0]$2517 \libresocsim_sdblock2mem_fifo_wrport_dat_w - assign $0$memwr$\storage_6$ls180.v:9480$11_EN[9:0]$2518 10'1111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_8 $0\memdat_8[9:0] - update $memwr$\storage_6$ls180.v:9480$11_ADDR $0$memwr$\storage_6$ls180.v:9480$11_ADDR[4:0]$2516 - update $memwr$\storage_6$ls180.v:9480$11_DATA $0$memwr$\storage_6$ls180.v:9480$11_DATA[9:0]$2517 - update $memwr$\storage_6$ls180.v:9480$11_EN $0$memwr$\storage_6$ls180.v:9480$11_EN[9:0]$2518 - end - attribute \src "ls180.v:948.5-948.36" - process $proc$ls180.v:948$2934 - assign { } { } - assign $1\libresocsim_clocker_clk0[0:0] 1'0 - sync always - sync init - update \libresocsim_clocker_clk0 $1\libresocsim_clocker_clk0[0:0] - end - attribute \src "ls180.v:9484.1-9485.4" - process $proc$ls180.v:9484$2520 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:9492.1-9496.4" - process $proc$ls180.v:9492$2522 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_7$ls180.v:9494$12_ADDR[4:0]$2523 5'xxxxx - assign $0$memwr$\storage_7$ls180.v:9494$12_DATA[9:0]$2524 10'xxxxxxxxxx - assign $0$memwr$\storage_7$ls180.v:9494$12_EN[9:0]$2525 10'0000000000 - assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:9495$2526_DATA - attribute \src "ls180.v:9493.2-9494.99" - switch \libresocsim_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:9493.6-9493.44" - case 1'1 - assign $0$memwr$\storage_7$ls180.v:9494$12_ADDR[4:0]$2523 \libresocsim_sdmem2block_fifo_wrport_adr - assign $0$memwr$\storage_7$ls180.v:9494$12_DATA[9:0]$2524 \libresocsim_sdmem2block_fifo_wrport_dat_w - assign $0$memwr$\storage_7$ls180.v:9494$12_EN[9:0]$2525 10'1111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_9 $0\memdat_9[9:0] - update $memwr$\storage_7$ls180.v:9494$12_ADDR $0$memwr$\storage_7$ls180.v:9494$12_ADDR[4:0]$2523 - update $memwr$\storage_7$ls180.v:9494$12_DATA $0$memwr$\storage_7$ls180.v:9494$12_DATA[9:0]$2524 - update $memwr$\storage_7$ls180.v:9494$12_EN $0$memwr$\storage_7$ls180.v:9494$12_EN[9:0]$2525 - end - attribute \src "ls180.v:9498.1-9499.4" - process $proc$ls180.v:9498$2527 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:950.11-950.42" - process $proc$ls180.v:950$2935 - assign { } { } - assign $1\libresocsim_clocker_clks[8:0] 9'000000000 - sync always - sync init - update \libresocsim_clocker_clks $1\libresocsim_clocker_clks[8:0] - end - attribute \src "ls180.v:951.5-951.36" - process $proc$ls180.v:951$2936 - assign { } { } - assign $1\libresocsim_clocker_clk1[0:0] 1'0 - sync always - sync init - update \libresocsim_clocker_clk1 $1\libresocsim_clocker_clk1[0:0] - end - attribute \src "ls180.v:952.5-952.37" - process $proc$ls180.v:952$2937 - assign { } { } - assign $1\libresocsim_clocker_clk_d[0:0] 1'0 - sync always - sync init - update \libresocsim_clocker_clk_d $1\libresocsim_clocker_clk_d[0:0] - end - attribute \src "ls180.v:956.5-956.41" - process $proc$ls180.v:956$2938 - assign { } { } - assign $0\libresocsim_init_initialize_w[0:0] 1'0 - sync always - update \libresocsim_init_initialize_w $0\libresocsim_init_initialize_w[0:0] - sync init - end - attribute \src "ls180.v:961.5-961.49" - process $proc$ls180.v:961$2939 - assign { } { } - assign $1\libresocsim_init_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \libresocsim_init_pads_out_payload_clk $1\libresocsim_init_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:962.5-962.51" - process $proc$ls180.v:962$2940 - assign { } { } - assign $1\libresocsim_init_pads_out_payload_cmd_o[0:0] 1'0 - sync always - sync init - update \libresocsim_init_pads_out_payload_cmd_o $1\libresocsim_init_pads_out_payload_cmd_o[0:0] - end - attribute \src "ls180.v:963.5-963.52" - process $proc$ls180.v:963$2941 - assign { } { } - assign $1\libresocsim_init_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - sync init - update \libresocsim_init_pads_out_payload_cmd_oe $1\libresocsim_init_pads_out_payload_cmd_oe[0:0] - end - attribute \src "ls180.v:964.11-964.58" - process $proc$ls180.v:964$2942 - assign { } { } - assign $1\libresocsim_init_pads_out_payload_data_o[3:0] 4'0000 - sync always - sync init - update \libresocsim_init_pads_out_payload_data_o $1\libresocsim_init_pads_out_payload_data_o[3:0] - end - attribute \src "ls180.v:965.5-965.53" - process $proc$ls180.v:965$2943 - assign { } { } - assign $1\libresocsim_init_pads_out_payload_data_oe[0:0] 1'0 - sync always - sync init - update \libresocsim_init_pads_out_payload_data_oe $1\libresocsim_init_pads_out_payload_data_oe[0:0] - end - attribute \src "ls180.v:966.11-966.40" - process $proc$ls180.v:966$2944 - assign { } { } - assign $1\libresocsim_init_count[7:0] 8'00000000 - sync always - sync init - update \libresocsim_init_count $1\libresocsim_init_count[7:0] - end - attribute \src "ls180.v:97.12-97.71" - process $proc$ls180.v:97$2577 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_adr $1\main_libresocsim_interface0_converted_interface_adr[29:0] - end - attribute \src "ls180.v:971.5-971.49" - process $proc$ls180.v:971$2945 - assign { } { } - assign $1\libresocsim_cmdw_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdw_pads_out_payload_clk $1\libresocsim_cmdw_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:972.5-972.51" - process $proc$ls180.v:972$2946 - assign { } { } - assign $1\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdw_pads_out_payload_cmd_o $1\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] - end - attribute \src "ls180.v:973.5-973.52" - process $proc$ls180.v:973$2947 - assign { } { } - assign $1\libresocsim_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdw_pads_out_payload_cmd_oe $1\libresocsim_cmdw_pads_out_payload_cmd_oe[0:0] - end - attribute \src "ls180.v:974.11-974.58" - process $proc$ls180.v:974$2948 - assign { } { } - assign $0\libresocsim_cmdw_pads_out_payload_data_o[3:0] 4'0000 - sync always - update \libresocsim_cmdw_pads_out_payload_data_o $0\libresocsim_cmdw_pads_out_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:975.5-975.53" - process $proc$ls180.v:975$2949 - assign { } { } - assign $0\libresocsim_cmdw_pads_out_payload_data_oe[0:0] 1'0 - sync always - update \libresocsim_cmdw_pads_out_payload_data_oe $0\libresocsim_cmdw_pads_out_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:976.5-976.39" - process $proc$ls180.v:976$2950 - assign { } { } - assign $1\libresocsim_cmdw_sink_valid[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdw_sink_valid $1\libresocsim_cmdw_sink_valid[0:0] - end - attribute \src "ls180.v:977.5-977.39" - process $proc$ls180.v:977$2951 - assign { } { } - assign $1\libresocsim_cmdw_sink_ready[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdw_sink_ready $1\libresocsim_cmdw_sink_ready[0:0] - end - attribute \src "ls180.v:978.5-978.38" - process $proc$ls180.v:978$2952 - assign { } { } - assign $1\libresocsim_cmdw_sink_last[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdw_sink_last $1\libresocsim_cmdw_sink_last[0:0] - end - attribute \src "ls180.v:979.11-979.52" - process $proc$ls180.v:979$2953 - assign { } { } - assign $1\libresocsim_cmdw_sink_payload_data[7:0] 8'00000000 - sync always - sync init - update \libresocsim_cmdw_sink_payload_data $1\libresocsim_cmdw_sink_payload_data[7:0] - end - attribute \src "ls180.v:98.12-98.73" - process $proc$ls180.v:98$2578 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:980.5-980.33" - process $proc$ls180.v:980$2954 - assign { } { } - assign $1\libresocsim_cmdw_done[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdw_done $1\libresocsim_cmdw_done[0:0] - end - attribute \src "ls180.v:981.11-981.40" - process $proc$ls180.v:981$2955 - assign { } { } - assign $1\libresocsim_cmdw_count[7:0] 8'00000000 - sync always - sync init - update \libresocsim_cmdw_count $1\libresocsim_cmdw_count[7:0] - end - attribute \src "ls180.v:984.5-984.50" - process $proc$ls180.v:984$2956 - assign { } { } - assign $0\libresocsim_cmdr_pads_in_pads_in_first[0:0] 1'0 - sync always - update \libresocsim_cmdr_pads_in_pads_in_first $0\libresocsim_cmdr_pads_in_pads_in_first[0:0] - sync init - end - attribute \src "ls180.v:985.5-985.49" - process $proc$ls180.v:985$2957 - assign { } { } - assign $0\libresocsim_cmdr_pads_in_pads_in_last[0:0] 1'0 - sync always - update \libresocsim_cmdr_pads_in_pads_in_last $0\libresocsim_cmdr_pads_in_pads_in_last[0:0] - sync init - end - attribute \src "ls180.v:986.5-986.56" - process $proc$ls180.v:986$2958 - assign { } { } - assign $0\libresocsim_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0 - sync always - update \libresocsim_cmdr_pads_in_pads_in_payload_clk $0\libresocsim_cmdr_pads_in_pads_in_payload_clk[0:0] - sync init - end - attribute \src "ls180.v:988.5-988.58" - process $proc$ls180.v:988$2959 - assign { } { } - assign $0\libresocsim_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0 - sync always - update \libresocsim_cmdr_pads_in_pads_in_payload_cmd_o $0\libresocsim_cmdr_pads_in_pads_in_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:989.5-989.59" - process $proc$ls180.v:989$2960 - assign { } { } - assign $0\libresocsim_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 - sync always - update \libresocsim_cmdr_pads_in_pads_in_payload_cmd_oe $0\libresocsim_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:991.11-991.65" - process $proc$ls180.v:991$2961 - assign { } { } - assign $0\libresocsim_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000 - sync always - update \libresocsim_cmdr_pads_in_pads_in_payload_data_o $0\libresocsim_cmdr_pads_in_pads_in_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:992.5-992.60" - process $proc$ls180.v:992$2962 - assign { } { } - assign $0\libresocsim_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0 - sync always - update \libresocsim_cmdr_pads_in_pads_in_payload_data_oe $0\libresocsim_cmdr_pads_in_pads_in_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:994.5-994.49" - process $proc$ls180.v:994$2963 - assign { } { } - assign $1\libresocsim_cmdr_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdr_pads_out_payload_clk $1\libresocsim_cmdr_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:995.5-995.51" - process $proc$ls180.v:995$2964 - assign { } { } - assign $1\libresocsim_cmdr_pads_out_payload_cmd_o[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdr_pads_out_payload_cmd_o $1\libresocsim_cmdr_pads_out_payload_cmd_o[0:0] - end - attribute \src "ls180.v:996.5-996.52" - process $proc$ls180.v:996$2965 - assign { } { } - assign $1\libresocsim_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdr_pads_out_payload_cmd_oe $1\libresocsim_cmdr_pads_out_payload_cmd_oe[0:0] - end - attribute \src "ls180.v:997.11-997.58" - process $proc$ls180.v:997$2966 - assign { } { } - assign $0\libresocsim_cmdr_pads_out_payload_data_o[3:0] 4'0000 - sync always - update \libresocsim_cmdr_pads_out_payload_data_o $0\libresocsim_cmdr_pads_out_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:998.5-998.53" - process $proc$ls180.v:998$2967 - assign { } { } - assign $0\libresocsim_cmdr_pads_out_payload_data_oe[0:0] 1'0 - sync always - update \libresocsim_cmdr_pads_out_payload_data_oe $0\libresocsim_cmdr_pads_out_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:999.5-999.39" - process $proc$ls180.v:999$2968 - assign { } { } - assign $1\libresocsim_cmdr_sink_valid[0:0] 1'0 - sync always - sync init - update \libresocsim_cmdr_sink_valid $1\libresocsim_cmdr_sink_valid[0:0] - end - connect \main_libresocsim_libresoc_reset \main_libresocsim_soccontroller_reset - connect \libresocsim_sdblock2mem_sink_sink_valid0 \libresocsim_sdcore_source_source_valid - connect \libresocsim_sdcore_source_source_ready \libresocsim_sdblock2mem_sink_sink_ready0 - connect \libresocsim_sdblock2mem_sink_sink_first \libresocsim_sdcore_source_source_first - connect \libresocsim_sdblock2mem_sink_sink_last \libresocsim_sdcore_source_source_last - connect \libresocsim_sdblock2mem_sink_sink_payload_data0 \libresocsim_sdcore_source_source_payload_data - connect \libresocsim_sdcore_sink_sink_valid \libresocsim_sdmem2block_source_source_valid0 - connect \libresocsim_sdmem2block_source_source_ready0 \libresocsim_sdcore_sink_sink_ready - connect \libresocsim_sdcore_sink_sink_first \libresocsim_sdmem2block_source_source_first0 - connect \libresocsim_sdcore_sink_sink_last \libresocsim_sdmem2block_source_source_last0 - connect \libresocsim_sdcore_sink_sink_payload_data \libresocsim_sdmem2block_source_source_payload_data0 - connect \main_libresocsim_soccontroller_bus_error \builder_error - connect \main_libresocsim_converter0_reset $not$ls180.v:2594$14_Y - connect \main_libresocsim_libresoc_ibus_dat_r { \main_libresocsim_interface0_converted_interface_dat_r \main_libresocsim_converter0_dat_r [63:32] } - connect \main_libresocsim_converter1_reset $not$ls180.v:2654$25_Y - connect \main_libresocsim_libresoc_dbus_dat_r { \main_libresocsim_interface1_converted_interface_dat_r \main_libresocsim_converter1_dat_r [63:32] } - connect \main_libresocsim_soccontroller_reset \main_libresocsim_soccontroller_reset_re - connect \main_libresocsim_soccontroller_bus_errors_status \main_libresocsim_soccontroller_bus_errors - connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [6:0] - connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r - connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w - connect \main_libresocsim_uart_uart_sink_valid \main_libresocsim_source_valid - connect \main_libresocsim_source_ready \main_libresocsim_uart_uart_sink_ready - connect \main_libresocsim_uart_uart_sink_first \main_libresocsim_source_first - connect \main_libresocsim_uart_uart_sink_last \main_libresocsim_source_last - connect \main_libresocsim_uart_uart_sink_payload_data \main_libresocsim_source_payload_data - connect \main_libresocsim_sink_valid \main_libresocsim_uart_uart_source_valid - connect \main_libresocsim_uart_uart_source_ready \main_libresocsim_sink_ready - connect \main_libresocsim_sink_first \main_libresocsim_uart_uart_source_first - connect \main_libresocsim_sink_last \main_libresocsim_uart_uart_source_last - connect \main_libresocsim_sink_payload_data \main_libresocsim_uart_uart_source_payload_data - connect \main_libresocsim_uart_tx_fifo_sink_valid \main_libresocsim_uart_rxtx_re - connect \main_libresocsim_uart_tx_fifo_sink_payload_data \main_libresocsim_uart_rxtx_r - connect \main_libresocsim_uart_txfull_status $not$ls180.v:2738$49_Y - connect \main_libresocsim_uart_txempty_status $not$ls180.v:2739$50_Y - connect \main_libresocsim_uart_uart_source_valid \main_libresocsim_uart_tx_fifo_source_valid - connect \main_libresocsim_uart_tx_fifo_source_ready \main_libresocsim_uart_uart_source_ready - connect \main_libresocsim_uart_uart_source_first \main_libresocsim_uart_tx_fifo_source_first - connect \main_libresocsim_uart_uart_source_last \main_libresocsim_uart_tx_fifo_source_last - connect \main_libresocsim_uart_uart_source_payload_data \main_libresocsim_uart_tx_fifo_source_payload_data - connect \main_libresocsim_uart_tx_trigger $not$ls180.v:2745$51_Y - connect \main_libresocsim_uart_rx_fifo_sink_valid \main_libresocsim_uart_uart_sink_valid - connect \main_libresocsim_uart_uart_sink_ready \main_libresocsim_uart_rx_fifo_sink_ready - connect \main_libresocsim_uart_rx_fifo_sink_first \main_libresocsim_uart_uart_sink_first - connect \main_libresocsim_uart_rx_fifo_sink_last \main_libresocsim_uart_uart_sink_last - connect \main_libresocsim_uart_rx_fifo_sink_payload_data \main_libresocsim_uart_uart_sink_payload_data - connect \main_libresocsim_uart_rxempty_status $not$ls180.v:2751$52_Y - connect \main_libresocsim_uart_rxfull_status $not$ls180.v:2752$53_Y - connect \main_libresocsim_uart_rxtx_w \main_libresocsim_uart_rx_fifo_source_payload_data - connect \main_libresocsim_uart_rx_fifo_source_ready $or$ls180.v:2754$55_Y - connect \main_libresocsim_uart_rx_trigger $not$ls180.v:2755$56_Y - connect \main_libresocsim_uart_irq $or$ls180.v:2778$65_Y - connect \main_libresocsim_uart_tx_status \main_libresocsim_uart_tx_trigger - connect \main_libresocsim_uart_rx_status \main_libresocsim_uart_rx_trigger - connect \main_libresocsim_uart_tx_fifo_syncfifo_din { \main_libresocsim_uart_tx_fifo_fifo_in_last \main_libresocsim_uart_tx_fifo_fifo_in_first \main_libresocsim_uart_tx_fifo_fifo_in_payload_data } - connect { \main_libresocsim_uart_tx_fifo_fifo_out_last \main_libresocsim_uart_tx_fifo_fifo_out_first \main_libresocsim_uart_tx_fifo_fifo_out_payload_data } \main_libresocsim_uart_tx_fifo_syncfifo_dout - connect \main_libresocsim_uart_tx_fifo_sink_ready \main_libresocsim_uart_tx_fifo_syncfifo_writable - connect \main_libresocsim_uart_tx_fifo_syncfifo_we \main_libresocsim_uart_tx_fifo_sink_valid - connect \main_libresocsim_uart_tx_fifo_fifo_in_first \main_libresocsim_uart_tx_fifo_sink_first - connect \main_libresocsim_uart_tx_fifo_fifo_in_last \main_libresocsim_uart_tx_fifo_sink_last - connect \main_libresocsim_uart_tx_fifo_fifo_in_payload_data \main_libresocsim_uart_tx_fifo_sink_payload_data - connect \main_libresocsim_uart_tx_fifo_source_valid \main_libresocsim_uart_tx_fifo_readable - connect \main_libresocsim_uart_tx_fifo_source_first \main_libresocsim_uart_tx_fifo_fifo_out_first - connect \main_libresocsim_uart_tx_fifo_source_last \main_libresocsim_uart_tx_fifo_fifo_out_last - connect \main_libresocsim_uart_tx_fifo_source_payload_data \main_libresocsim_uart_tx_fifo_fifo_out_payload_data - connect \main_libresocsim_uart_tx_fifo_re \main_libresocsim_uart_tx_fifo_source_ready - connect \main_libresocsim_uart_tx_fifo_syncfifo_re $and$ls180.v:2793$68_Y - connect \main_libresocsim_uart_tx_fifo_level1 $add$ls180.v:2794$69_Y - connect \main_libresocsim_uart_tx_fifo_wrport_dat_w \main_libresocsim_uart_tx_fifo_syncfifo_din - connect \main_libresocsim_uart_tx_fifo_wrport_we $and$ls180.v:2804$73_Y - connect \main_libresocsim_uart_tx_fifo_do_read $and$ls180.v:2805$74_Y - connect \main_libresocsim_uart_tx_fifo_rdport_adr \main_libresocsim_uart_tx_fifo_consume - connect \main_libresocsim_uart_tx_fifo_syncfifo_dout \main_libresocsim_uart_tx_fifo_rdport_dat_r - connect \main_libresocsim_uart_tx_fifo_rdport_re \main_libresocsim_uart_tx_fifo_do_read - connect \main_libresocsim_uart_tx_fifo_syncfifo_writable $ne$ls180.v:2809$75_Y - connect \main_libresocsim_uart_tx_fifo_syncfifo_readable $ne$ls180.v:2810$76_Y - connect \main_libresocsim_uart_rx_fifo_syncfifo_din { \main_libresocsim_uart_rx_fifo_fifo_in_last \main_libresocsim_uart_rx_fifo_fifo_in_first \main_libresocsim_uart_rx_fifo_fifo_in_payload_data } - connect { \main_libresocsim_uart_rx_fifo_fifo_out_last \main_libresocsim_uart_rx_fifo_fifo_out_first \main_libresocsim_uart_rx_fifo_fifo_out_payload_data } \main_libresocsim_uart_rx_fifo_syncfifo_dout - connect \main_libresocsim_uart_rx_fifo_sink_ready \main_libresocsim_uart_rx_fifo_syncfifo_writable - connect \main_libresocsim_uart_rx_fifo_syncfifo_we \main_libresocsim_uart_rx_fifo_sink_valid - connect \main_libresocsim_uart_rx_fifo_fifo_in_first \main_libresocsim_uart_rx_fifo_sink_first - connect \main_libresocsim_uart_rx_fifo_fifo_in_last \main_libresocsim_uart_rx_fifo_sink_last - connect \main_libresocsim_uart_rx_fifo_fifo_in_payload_data \main_libresocsim_uart_rx_fifo_sink_payload_data - connect \main_libresocsim_uart_rx_fifo_source_valid \main_libresocsim_uart_rx_fifo_readable - connect \main_libresocsim_uart_rx_fifo_source_first \main_libresocsim_uart_rx_fifo_fifo_out_first - connect \main_libresocsim_uart_rx_fifo_source_last \main_libresocsim_uart_rx_fifo_fifo_out_last - connect \main_libresocsim_uart_rx_fifo_source_payload_data \main_libresocsim_uart_rx_fifo_fifo_out_payload_data - connect \main_libresocsim_uart_rx_fifo_re \main_libresocsim_uart_rx_fifo_source_ready - connect \main_libresocsim_uart_rx_fifo_syncfifo_re $and$ls180.v:2823$79_Y - connect \main_libresocsim_uart_rx_fifo_level1 $add$ls180.v:2824$80_Y - connect \main_libresocsim_uart_rx_fifo_wrport_dat_w \main_libresocsim_uart_rx_fifo_syncfifo_din - connect \main_libresocsim_uart_rx_fifo_wrport_we $and$ls180.v:2834$84_Y - connect \main_libresocsim_uart_rx_fifo_do_read $and$ls180.v:2835$85_Y - connect \main_libresocsim_uart_rx_fifo_rdport_adr \main_libresocsim_uart_rx_fifo_consume - connect \main_libresocsim_uart_rx_fifo_syncfifo_dout \main_libresocsim_uart_rx_fifo_rdport_dat_r - connect \main_libresocsim_uart_rx_fifo_rdport_re \main_libresocsim_uart_rx_fifo_do_read - connect \main_libresocsim_uart_rx_fifo_syncfifo_writable $ne$ls180.v:2839$86_Y - connect \main_libresocsim_uart_rx_fifo_syncfifo_readable $ne$ls180.v:2840$87_Y - connect \main_libresocsim_timer_zero_trigger $ne$ls180.v:2841$88_Y - connect \main_libresocsim_timer_eventmanager_status_w \main_libresocsim_timer_zero_status - connect \main_libresocsim_timer_eventmanager_pending_w \main_libresocsim_timer_zero_pending - connect \main_libresocsim_timer_irq $and$ls180.v:2850$91_Y - connect \main_libresocsim_timer_zero_status \main_libresocsim_timer_zero_trigger - connect \sys_clk_1 \sys_clk - connect \por_clk \sys_clk - connect \sys_rst \main_int_rst - connect \main_dfi_p0_address \main_sdram_master_p0_address - connect \main_dfi_p0_bank \main_sdram_master_p0_bank - connect \main_dfi_p0_cas_n \main_sdram_master_p0_cas_n - connect \main_dfi_p0_cs_n \main_sdram_master_p0_cs_n - connect \main_dfi_p0_ras_n \main_sdram_master_p0_ras_n - connect \main_dfi_p0_we_n \main_sdram_master_p0_we_n - connect \main_dfi_p0_cke \main_sdram_master_p0_cke - connect \main_dfi_p0_odt \main_sdram_master_p0_odt - connect \main_dfi_p0_reset_n \main_sdram_master_p0_reset_n - connect \main_dfi_p0_act_n \main_sdram_master_p0_act_n - connect \main_dfi_p0_wrdata \main_sdram_master_p0_wrdata - connect \main_dfi_p0_wrdata_en \main_sdram_master_p0_wrdata_en - connect \main_dfi_p0_wrdata_mask \main_sdram_master_p0_wrdata_mask - connect \main_dfi_p0_rddata_en \main_sdram_master_p0_rddata_en - connect \main_sdram_master_p0_rddata \main_dfi_p0_rddata - connect \main_sdram_master_p0_rddata_valid \main_dfi_p0_rddata_valid - connect \main_sdram_slave_p0_address \main_sdram_dfi_p0_address - connect \main_sdram_slave_p0_bank \main_sdram_dfi_p0_bank - connect \main_sdram_slave_p0_cas_n \main_sdram_dfi_p0_cas_n - connect \main_sdram_slave_p0_cs_n \main_sdram_dfi_p0_cs_n - connect \main_sdram_slave_p0_ras_n \main_sdram_dfi_p0_ras_n - connect \main_sdram_slave_p0_we_n \main_sdram_dfi_p0_we_n - connect \main_sdram_slave_p0_cke \main_sdram_dfi_p0_cke - connect \main_sdram_slave_p0_odt \main_sdram_dfi_p0_odt - connect \main_sdram_slave_p0_reset_n \main_sdram_dfi_p0_reset_n - connect \main_sdram_slave_p0_act_n \main_sdram_dfi_p0_act_n - connect \main_sdram_slave_p0_wrdata \main_sdram_dfi_p0_wrdata - connect \main_sdram_slave_p0_wrdata_en \main_sdram_dfi_p0_wrdata_en - connect \main_sdram_slave_p0_wrdata_mask \main_sdram_dfi_p0_wrdata_mask - connect \main_sdram_slave_p0_rddata_en \main_sdram_dfi_p0_rddata_en - connect \main_sdram_dfi_p0_rddata \main_sdram_slave_p0_rddata - connect \main_sdram_dfi_p0_rddata_valid \main_sdram_slave_p0_rddata_valid - connect \main_sdram_inti_p0_cke \main_sdram_cke - connect \main_sdram_inti_p0_odt \main_sdram_odt - connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n - connect \main_sdram_inti_p0_address \main_sdram_address_storage - connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage - connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:2969$99_Y - connect \main_sdram_inti_p0_rddata_en $and$ls180.v:2970$100_Y - connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage - connect \main_sdram_inti_p0_wrdata_mask 2'00 - connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid - connect \main_sdram_interface_bank0_ready \main_sdram_bankmachine0_req_ready - connect \main_sdram_bankmachine0_req_we \main_sdram_interface_bank0_we - connect \main_sdram_bankmachine0_req_addr \main_sdram_interface_bank0_addr - connect \main_sdram_interface_bank0_lock \main_sdram_bankmachine0_req_lock - connect \main_sdram_interface_bank0_wdata_ready \main_sdram_bankmachine0_req_wdata_ready - connect \main_sdram_interface_bank0_rdata_valid \main_sdram_bankmachine0_req_rdata_valid - connect \main_sdram_bankmachine1_req_valid \main_sdram_interface_bank1_valid - connect \main_sdram_interface_bank1_ready \main_sdram_bankmachine1_req_ready - connect \main_sdram_bankmachine1_req_we \main_sdram_interface_bank1_we - connect \main_sdram_bankmachine1_req_addr \main_sdram_interface_bank1_addr - connect \main_sdram_interface_bank1_lock \main_sdram_bankmachine1_req_lock - connect \main_sdram_interface_bank1_wdata_ready \main_sdram_bankmachine1_req_wdata_ready - connect \main_sdram_interface_bank1_rdata_valid \main_sdram_bankmachine1_req_rdata_valid - connect \main_sdram_bankmachine2_req_valid \main_sdram_interface_bank2_valid - connect \main_sdram_interface_bank2_ready \main_sdram_bankmachine2_req_ready - connect \main_sdram_bankmachine2_req_we \main_sdram_interface_bank2_we - connect \main_sdram_bankmachine2_req_addr \main_sdram_interface_bank2_addr - connect \main_sdram_interface_bank2_lock \main_sdram_bankmachine2_req_lock - connect \main_sdram_interface_bank2_wdata_ready \main_sdram_bankmachine2_req_wdata_ready - connect \main_sdram_interface_bank2_rdata_valid \main_sdram_bankmachine2_req_rdata_valid - connect \main_sdram_bankmachine3_req_valid \main_sdram_interface_bank3_valid - connect \main_sdram_interface_bank3_ready \main_sdram_bankmachine3_req_ready - connect \main_sdram_bankmachine3_req_we \main_sdram_interface_bank3_we - connect \main_sdram_bankmachine3_req_addr \main_sdram_interface_bank3_addr - connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock - connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready - connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid - connect \main_sdram_timer_wait $not$ls180.v:3001$101_Y - connect \main_sdram_postponer_req_i \main_sdram_timer_done0 - connect \main_sdram_wants_refresh \main_sdram_postponer_req_o - connect \main_sdram_timer_done1 $eq$ls180.v:3004$102_Y - connect \main_sdram_timer_done0 \main_sdram_timer_done1 - connect \main_sdram_timer_count0 \main_sdram_timer_count1 - connect \main_sdram_sequencer_start1 $or$ls180.v:3007$104_Y - connect \main_sdram_sequencer_done0 $and$ls180.v:3008$106_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid - connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine0_req_addr - connect \main_sdram_bankmachine0_cmd_buffer_sink_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine0_cmd_buffer_sink_ready - connect \main_sdram_bankmachine0_cmd_buffer_sink_first \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first - connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last - connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we - connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3050$108_Y - connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3051$109_Y - connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3052$110_Y - connect \main_sdram_bankmachine0_cmd_payload_ba 2'00 - connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3062$115_Y - connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3063$117_Y - connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3064$119_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } - connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3096$127_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3097$128_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3100$129_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3101$130_Y - connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3102$132_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid - connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine1_req_addr - connect \main_sdram_bankmachine1_cmd_buffer_sink_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine1_cmd_buffer_sink_ready - connect \main_sdram_bankmachine1_cmd_buffer_sink_first \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first - connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last - connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we - connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3207$138_Y - connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3208$139_Y - connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3209$140_Y - connect \main_sdram_bankmachine1_cmd_payload_ba 2'01 - connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3219$145_Y - connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3220$147_Y - connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3221$149_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } - connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3253$157_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3254$158_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3257$159_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3258$160_Y - connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3259$162_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid - connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine2_req_addr - connect \main_sdram_bankmachine2_cmd_buffer_sink_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine2_cmd_buffer_sink_ready - connect \main_sdram_bankmachine2_cmd_buffer_sink_first \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first - connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last - connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we - connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3364$168_Y - connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3365$169_Y - connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3366$170_Y - connect \main_sdram_bankmachine2_cmd_payload_ba 2'10 - connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3376$175_Y - connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3377$177_Y - connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3378$179_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } - connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3410$187_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3411$188_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3414$189_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3415$190_Y - connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3416$192_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid - connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine3_req_addr - connect \main_sdram_bankmachine3_cmd_buffer_sink_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine3_cmd_buffer_sink_ready - connect \main_sdram_bankmachine3_cmd_buffer_sink_first \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first - connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last - connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we - connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3521$198_Y - connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3522$199_Y - connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3523$200_Y - connect \main_sdram_bankmachine3_cmd_payload_ba 2'11 - connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3533$205_Y - connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3534$207_Y - connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3535$209_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } - connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3567$217_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3568$218_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3571$219_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3572$220_Y - connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3573$222_Y - connect \main_sdram_choose_req_want_cmds 1'1 - connect \main_sdram_trrdcon_valid $and$ls180.v:3669$233_Y - connect \main_sdram_tfawcon_valid $and$ls180.v:3670$239_Y - connect \main_sdram_ras_allowed $and$ls180.v:3671$240_Y - connect \main_sdram_tccdcon_valid $and$ls180.v:3672$243_Y - connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready - connect \main_sdram_twtrcon_valid $and$ls180.v:3674$245_Y - connect \main_sdram_read_available $or$ls180.v:3675$252_Y - connect \main_sdram_write_available $or$ls180.v:3676$259_Y - connect \main_sdram_max_time0 $eq$ls180.v:3677$260_Y - connect \main_sdram_max_time1 $eq$ls180.v:3678$261_Y - connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid - connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid - connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid - connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid - connect \main_sdram_go_to_refresh $and$ls180.v:3683$264_Y - connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata - connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata - connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3686$265_Y - connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids - connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0 - connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1 - connect \main_sdram_choose_cmd_cmd_payload_ba \builder_comb_rhs_array_muxed2 - connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3 - connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4 - connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5 - connect \main_sdram_choose_cmd_ce $or$ls180.v:3719$323_Y - connect \main_sdram_choose_req_request \main_sdram_choose_req_valids - connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6 - connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7 - connect \main_sdram_choose_req_cmd_payload_ba \builder_comb_rhs_array_muxed8 - connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9 - connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10 - connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11 - connect \main_sdram_choose_req_ce $or$ls180.v:3788$409_Y - connect \main_sdram_dfi_p0_reset_n 1'1 - connect \main_sdram_dfi_p0_cke \main_sdram_steerer0 - connect \main_sdram_dfi_p0_odt \main_sdram_steerer1 - connect \builder_roundrobin0_request $and$ls180.v:3865$441_Y - connect \builder_roundrobin0_ce $and$ls180.v:3866$444_Y - connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12 - connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13 - connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14 - connect \builder_roundrobin1_request $and$ls180.v:3870$457_Y - connect \builder_roundrobin1_ce $and$ls180.v:3871$460_Y - connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15 - connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16 - connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17 - connect \builder_roundrobin2_request $and$ls180.v:3875$473_Y - connect \builder_roundrobin2_ce $and$ls180.v:3876$476_Y - connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18 - connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19 - connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20 - connect \builder_roundrobin3_request $and$ls180.v:3880$489_Y - connect \builder_roundrobin3_ce $and$ls180.v:3881$492_Y - connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21 - connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22 - connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23 - connect \main_port_cmd_ready $or$ls180.v:3885$556_Y - connect \main_port_wdata_ready \builder_new_master_wdata_ready - connect \main_port_rdata_valid \builder_new_master_rdata_valid3 - connect \main_port_rdata_payload_data \main_sdram_interface_rdata - connect \builder_roundrobin0_grant 1'0 - connect \builder_roundrobin1_grant 1'0 - connect \builder_roundrobin2_grant 1'0 - connect \builder_roundrobin3_grant 1'0 - connect \main_converter_reset $not$ls180.v:3907$558_Y - connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] } - connect \main_port_cmd_payload_addr $sub$ls180.v:3967$569_Y [23:0] - connect \main_port_cmd_payload_we \main_litedram_wb_we - connect \main_port_wdata_payload_data \main_litedram_wb_dat_w - connect \main_port_wdata_payload_we \main_litedram_wb_sel - connect \main_litedram_wb_dat_r \main_port_rdata_payload_data - connect \main_port_flush $not$ls180.v:3972$570_Y - connect \main_port_cmd_last $not$ls180.v:3973$571_Y - connect \main_port_cmd_valid $and$ls180.v:3974$574_Y - connect \main_port_wdata_valid $and$ls180.v:3975$578_Y - connect \main_port_rdata_ready $and$ls180.v:3976$581_Y - connect \main_litedram_wb_ack $and$ls180.v:3977$586_Y - connect \main_ack_cmd $or$ls180.v:3978$588_Y - connect \main_ack_wdata $or$ls180.v:3979$590_Y - connect \main_ack_rdata $and$ls180.v:3980$591_Y - connect \main_start0 \main_start1 - connect \main_length0 \main_length1 - connect \main_mosi \main_mosi_storage - connect \main_done1 \main_done0 - connect \main_miso_status \main_miso - connect \main_cs \main_cs_storage - connect \main_loopback \main_loopback_storage - connect \main_clk_rise $eq$ls180.v:3988$593_Y - connect \main_clk_fall $eq$ls180.v:3989$595_Y - connect \libresocsim_status 1'0 - connect \libresocsim_sdpads_clk $or$ls180.v:4040$603_Y - connect \libresocsim_sdpads_cmd_oe $or$ls180.v:4041$607_Y - connect \libresocsim_sdpads_cmd_o $or$ls180.v:4042$611_Y - connect \libresocsim_sdpads_data_oe $or$ls180.v:4043$615_Y - connect \libresocsim_sdpads_data_o $or$ls180.v:4044$619_Y - connect \libresocsim_init_pads_out_ready \libresocsim_clocker_ce - connect \libresocsim_cmdw_pads_out_ready \libresocsim_clocker_ce - connect \libresocsim_cmdr_pads_out_ready \libresocsim_clocker_ce - connect \libresocsim_dataw_pads_out_ready \libresocsim_clocker_ce - connect \libresocsim_datar_pads_out_ready \libresocsim_clocker_ce - connect \libresocsim_init_pads_in_valid \libresocsim_clocker_ce - connect \libresocsim_init_pads_in_payload_cmd_i \libresocsim_sdpads_cmd_i - connect \libresocsim_init_pads_in_payload_data_i \libresocsim_sdpads_data_i - connect \libresocsim_cmdw_pads_in_valid \libresocsim_clocker_ce - connect \libresocsim_cmdw_pads_in_payload_cmd_i \libresocsim_sdpads_cmd_i - connect \libresocsim_cmdw_pads_in_payload_data_i \libresocsim_sdpads_data_i - connect \libresocsim_cmdr_pads_in_pads_in_valid \libresocsim_clocker_ce - connect \libresocsim_cmdr_pads_in_pads_in_payload_cmd_i \libresocsim_sdpads_cmd_i - connect \libresocsim_cmdr_pads_in_pads_in_payload_data_i \libresocsim_sdpads_data_i - connect \libresocsim_dataw_pads_in_valid \libresocsim_clocker_ce - connect \libresocsim_dataw_pads_in_payload_cmd_i \libresocsim_sdpads_cmd_i - connect \libresocsim_dataw_pads_in_payload_data_i \libresocsim_sdpads_data_i - connect \libresocsim_datar_pads_in_pads_in_valid \libresocsim_clocker_ce - connect \libresocsim_datar_pads_in_pads_in_payload_cmd_i \libresocsim_sdpads_cmd_i - connect \libresocsim_datar_pads_in_pads_in_payload_data_i \libresocsim_sdpads_data_i - connect \libresocsim_clocker_stop $or$ls180.v:4065$620_Y - connect \libresocsim_clocker_ce $and$ls180.v:4095$623_Y - connect \libresocsim_cmdr_cmdr_pads_in_valid \libresocsim_cmdr_pads_in_pads_in_valid - connect \libresocsim_cmdr_pads_in_pads_in_ready \libresocsim_cmdr_cmdr_pads_in_ready - connect \libresocsim_cmdr_cmdr_pads_in_first \libresocsim_cmdr_pads_in_pads_in_first - connect \libresocsim_cmdr_cmdr_pads_in_last \libresocsim_cmdr_pads_in_pads_in_last - connect \libresocsim_cmdr_cmdr_pads_in_payload_clk \libresocsim_cmdr_pads_in_pads_in_payload_clk - connect \libresocsim_cmdr_cmdr_pads_in_payload_cmd_i \libresocsim_cmdr_pads_in_pads_in_payload_cmd_i - connect \libresocsim_cmdr_cmdr_pads_in_payload_cmd_o \libresocsim_cmdr_pads_in_pads_in_payload_cmd_o - connect \libresocsim_cmdr_cmdr_pads_in_payload_cmd_oe \libresocsim_cmdr_pads_in_pads_in_payload_cmd_oe - connect \libresocsim_cmdr_cmdr_pads_in_payload_data_i \libresocsim_cmdr_pads_in_pads_in_payload_data_i - connect \libresocsim_cmdr_cmdr_pads_in_payload_data_o \libresocsim_cmdr_pads_in_pads_in_payload_data_o - connect \libresocsim_cmdr_cmdr_pads_in_payload_data_oe \libresocsim_cmdr_pads_in_pads_in_payload_data_oe - connect \libresocsim_cmdr_cmdr_start $eq$ls180.v:4218$633_Y - connect \libresocsim_cmdr_cmdr_converter_sink_valid $and$ls180.v:4219$635_Y - connect \libresocsim_cmdr_cmdr_converter_sink_payload_data \libresocsim_cmdr_cmdr_pads_in_payload_cmd_i - connect \libresocsim_cmdr_cmdr_buf_sink_valid \libresocsim_cmdr_cmdr_source_source_valid1 - connect \libresocsim_cmdr_cmdr_source_source_ready1 \libresocsim_cmdr_cmdr_buf_sink_ready - connect \libresocsim_cmdr_cmdr_buf_sink_first \libresocsim_cmdr_cmdr_source_source_first1 - connect \libresocsim_cmdr_cmdr_buf_sink_last \libresocsim_cmdr_cmdr_source_source_last1 - connect \libresocsim_cmdr_cmdr_buf_sink_payload_data \libresocsim_cmdr_cmdr_source_source_payload_data1 - connect \libresocsim_cmdr_cmdr_source_source_valid0 \libresocsim_cmdr_cmdr_buf_source_valid - connect \libresocsim_cmdr_cmdr_buf_source_ready \libresocsim_cmdr_cmdr_source_source_ready0 - connect \libresocsim_cmdr_cmdr_source_source_first0 \libresocsim_cmdr_cmdr_buf_source_first - connect \libresocsim_cmdr_cmdr_source_source_last0 \libresocsim_cmdr_cmdr_buf_source_last - connect \libresocsim_cmdr_cmdr_source_source_payload_data0 \libresocsim_cmdr_cmdr_buf_source_payload_data - connect \libresocsim_cmdr_cmdr_source_source_valid1 \libresocsim_cmdr_cmdr_converter_source_valid - connect \libresocsim_cmdr_cmdr_converter_source_ready \libresocsim_cmdr_cmdr_source_source_ready1 - connect \libresocsim_cmdr_cmdr_source_source_first1 \libresocsim_cmdr_cmdr_converter_source_first - connect \libresocsim_cmdr_cmdr_source_source_last1 \libresocsim_cmdr_cmdr_converter_source_last - connect \libresocsim_cmdr_cmdr_source_source_payload_data1 \libresocsim_cmdr_cmdr_converter_source_payload_data - connect \libresocsim_cmdr_cmdr_converter_sink_ready $or$ls180.v:4236$637_Y - connect \libresocsim_cmdr_cmdr_converter_source_valid \libresocsim_cmdr_cmdr_converter_strobe_all - connect \libresocsim_cmdr_cmdr_converter_load_part $and$ls180.v:4238$638_Y - connect \libresocsim_cmdr_cmdr_buf_sink_ready $or$ls180.v:4239$640_Y - connect \libresocsim_dataw_crcr_pads_in_valid \libresocsim_dataw_pads_in_pads_in_valid - connect \libresocsim_dataw_pads_in_pads_in_ready \libresocsim_dataw_crcr_pads_in_ready - connect \libresocsim_dataw_crcr_pads_in_first \libresocsim_dataw_pads_in_pads_in_first - connect \libresocsim_dataw_crcr_pads_in_last \libresocsim_dataw_pads_in_pads_in_last - connect \libresocsim_dataw_crcr_pads_in_payload_clk \libresocsim_dataw_pads_in_pads_in_payload_clk - connect \libresocsim_dataw_crcr_pads_in_payload_cmd_i \libresocsim_dataw_pads_in_pads_in_payload_cmd_i - connect \libresocsim_dataw_crcr_pads_in_payload_cmd_o \libresocsim_dataw_pads_in_pads_in_payload_cmd_o - connect \libresocsim_dataw_crcr_pads_in_payload_cmd_oe \libresocsim_dataw_pads_in_pads_in_payload_cmd_oe - connect \libresocsim_dataw_crcr_pads_in_payload_data_i \libresocsim_dataw_pads_in_pads_in_payload_data_i - connect \libresocsim_dataw_crcr_pads_in_payload_data_o \libresocsim_dataw_pads_in_pads_in_payload_data_o - connect \libresocsim_dataw_crcr_pads_in_payload_data_oe \libresocsim_dataw_pads_in_pads_in_payload_data_oe - connect \libresocsim_dataw_crcr_start $eq$ls180.v:4345$655_Y - connect \libresocsim_dataw_crcr_converter_sink_valid $and$ls180.v:4346$656_Y - connect \libresocsim_dataw_crcr_converter_sink_payload_data \libresocsim_dataw_crcr_pads_in_payload_data_i [0] - connect \libresocsim_dataw_crcr_buf_sink_valid \libresocsim_dataw_crcr_source_source_valid1 - connect \libresocsim_dataw_crcr_source_source_ready1 \libresocsim_dataw_crcr_buf_sink_ready - connect \libresocsim_dataw_crcr_buf_sink_first \libresocsim_dataw_crcr_source_source_first1 - connect \libresocsim_dataw_crcr_buf_sink_last \libresocsim_dataw_crcr_source_source_last1 - connect \libresocsim_dataw_crcr_buf_sink_payload_data \libresocsim_dataw_crcr_source_source_payload_data1 - connect \libresocsim_dataw_crcr_source_source_valid0 \libresocsim_dataw_crcr_buf_source_valid - connect \libresocsim_dataw_crcr_buf_source_ready \libresocsim_dataw_crcr_source_source_ready0 - connect \libresocsim_dataw_crcr_source_source_first0 \libresocsim_dataw_crcr_buf_source_first - connect \libresocsim_dataw_crcr_source_source_last0 \libresocsim_dataw_crcr_buf_source_last - connect \libresocsim_dataw_crcr_source_source_payload_data0 \libresocsim_dataw_crcr_buf_source_payload_data - connect \libresocsim_dataw_crcr_source_source_valid1 \libresocsim_dataw_crcr_converter_source_valid - connect \libresocsim_dataw_crcr_converter_source_ready \libresocsim_dataw_crcr_source_source_ready1 - connect \libresocsim_dataw_crcr_source_source_first1 \libresocsim_dataw_crcr_converter_source_first - connect \libresocsim_dataw_crcr_source_source_last1 \libresocsim_dataw_crcr_converter_source_last - connect \libresocsim_dataw_crcr_source_source_payload_data1 \libresocsim_dataw_crcr_converter_source_payload_data - connect \libresocsim_dataw_crcr_converter_sink_ready $or$ls180.v:4363$658_Y - connect \libresocsim_dataw_crcr_converter_source_valid \libresocsim_dataw_crcr_converter_strobe_all - connect \libresocsim_dataw_crcr_converter_load_part $and$ls180.v:4365$659_Y - connect \libresocsim_dataw_crcr_buf_sink_ready $or$ls180.v:4366$661_Y - connect \libresocsim_datar_datar_pads_in_valid \libresocsim_datar_pads_in_pads_in_valid - connect \libresocsim_datar_pads_in_pads_in_ready \libresocsim_datar_datar_pads_in_ready - connect \libresocsim_datar_datar_pads_in_first \libresocsim_datar_pads_in_pads_in_first - connect \libresocsim_datar_datar_pads_in_last \libresocsim_datar_pads_in_pads_in_last - connect \libresocsim_datar_datar_pads_in_payload_clk \libresocsim_datar_pads_in_pads_in_payload_clk - connect \libresocsim_datar_datar_pads_in_payload_cmd_i \libresocsim_datar_pads_in_pads_in_payload_cmd_i - connect \libresocsim_datar_datar_pads_in_payload_cmd_o \libresocsim_datar_pads_in_pads_in_payload_cmd_o - connect \libresocsim_datar_datar_pads_in_payload_cmd_oe \libresocsim_datar_pads_in_pads_in_payload_cmd_oe - connect \libresocsim_datar_datar_pads_in_payload_data_i \libresocsim_datar_pads_in_pads_in_payload_data_i - connect \libresocsim_datar_datar_pads_in_payload_data_o \libresocsim_datar_pads_in_pads_in_payload_data_o - connect \libresocsim_datar_datar_pads_in_payload_data_oe \libresocsim_datar_pads_in_pads_in_payload_data_oe - connect \libresocsim_datar_datar_start $eq$ls180.v:4479$670_Y - connect \libresocsim_datar_datar_converter_sink_valid $and$ls180.v:4480$671_Y - connect \libresocsim_datar_datar_converter_sink_payload_data \libresocsim_datar_datar_pads_in_payload_data_i - connect \libresocsim_datar_datar_buf_sink_valid \libresocsim_datar_datar_source_source_valid1 - connect \libresocsim_datar_datar_source_source_ready1 \libresocsim_datar_datar_buf_sink_ready - connect \libresocsim_datar_datar_buf_sink_first \libresocsim_datar_datar_source_source_first1 - connect \libresocsim_datar_datar_buf_sink_last \libresocsim_datar_datar_source_source_last1 - connect \libresocsim_datar_datar_buf_sink_payload_data \libresocsim_datar_datar_source_source_payload_data1 - connect \libresocsim_datar_datar_source_source_valid0 \libresocsim_datar_datar_buf_source_valid - connect \libresocsim_datar_datar_buf_source_ready \libresocsim_datar_datar_source_source_ready0 - connect \libresocsim_datar_datar_source_source_first0 \libresocsim_datar_datar_buf_source_first - connect \libresocsim_datar_datar_source_source_last0 \libresocsim_datar_datar_buf_source_last - connect \libresocsim_datar_datar_source_source_payload_data0 \libresocsim_datar_datar_buf_source_payload_data - connect \libresocsim_datar_datar_source_source_valid1 \libresocsim_datar_datar_converter_source_valid - connect \libresocsim_datar_datar_converter_source_ready \libresocsim_datar_datar_source_source_ready1 - connect \libresocsim_datar_datar_source_source_first1 \libresocsim_datar_datar_converter_source_first - connect \libresocsim_datar_datar_source_source_last1 \libresocsim_datar_datar_converter_source_last - connect \libresocsim_datar_datar_source_source_payload_data1 \libresocsim_datar_datar_converter_source_payload_data - connect \libresocsim_datar_datar_converter_sink_ready $or$ls180.v:4497$673_Y - connect \libresocsim_datar_datar_converter_source_valid \libresocsim_datar_datar_converter_strobe_all - connect \libresocsim_datar_datar_converter_load_part $and$ls180.v:4499$674_Y - connect \libresocsim_datar_datar_buf_sink_ready $or$ls180.v:4500$676_Y - connect \libresocsim_sdcore_crc16_inserter_sink_valid \libresocsim_sdcore_sink_sink_valid - connect \libresocsim_sdcore_sink_sink_ready \libresocsim_sdcore_crc16_inserter_sink_ready - connect \libresocsim_sdcore_crc16_inserter_sink_first \libresocsim_sdcore_sink_sink_first - connect \libresocsim_sdcore_crc16_inserter_sink_last \libresocsim_sdcore_sink_sink_last - connect \libresocsim_sdcore_crc16_inserter_sink_payload_data \libresocsim_sdcore_sink_sink_payload_data - connect \libresocsim_sdcore_source_source_valid \libresocsim_sdcore_crc16_checker_source_valid - connect \libresocsim_sdcore_crc16_checker_source_ready \libresocsim_sdcore_source_source_ready - connect \libresocsim_sdcore_source_source_first \libresocsim_sdcore_crc16_checker_source_first - connect \libresocsim_sdcore_source_source_last \libresocsim_sdcore_crc16_checker_source_last - connect \libresocsim_sdcore_source_source_payload_data \libresocsim_sdcore_crc16_checker_source_payload_data - connect \libresocsim_sdcore_cmd_type \libresocsim_sdcore_cmd_command_storage [1:0] - connect \libresocsim_sdcore_data_type \libresocsim_sdcore_cmd_command_storage [6:5] - connect \libresocsim_sdcore_cmd_event_status { 1'0 \libresocsim_sdcore_cmd_timeout \libresocsim_sdcore_cmd_error \libresocsim_sdcore_cmd_done } - connect \libresocsim_sdcore_data_event_status { $not$ls180.v:4616$691_Y \libresocsim_sdcore_data_timeout \libresocsim_sdcore_data_error \libresocsim_sdcore_data_done } - connect \libresocsim_sdcore_crc7_inserter_val { 2'01 \libresocsim_sdcore_cmd_command_storage [13:8] \libresocsim_sdcore_cmd_argument_storage } - connect \libresocsim_sdcore_crc7_inserter_clr 1'1 - connect \libresocsim_sdcore_crc7_inserter_enable 1'1 - connect \libresocsim_sdcore_crc7_inserter_crcreg1 { \libresocsim_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:4620$694_Y \libresocsim_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:4620$692_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg2 { \libresocsim_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:4621$697_Y \libresocsim_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:4621$695_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg3 { \libresocsim_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:4622$700_Y \libresocsim_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:4622$698_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg4 { \libresocsim_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:4623$703_Y \libresocsim_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:4623$701_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg5 { \libresocsim_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:4624$706_Y \libresocsim_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:4624$704_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg6 { \libresocsim_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:4625$709_Y \libresocsim_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:4625$707_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg7 { \libresocsim_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:4626$712_Y \libresocsim_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:4626$710_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg8 { \libresocsim_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:4627$715_Y \libresocsim_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:4627$713_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg9 { \libresocsim_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:4628$718_Y \libresocsim_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:4628$716_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg10 { \libresocsim_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:4629$721_Y \libresocsim_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:4629$719_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg11 { \libresocsim_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:4630$724_Y \libresocsim_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:4630$722_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg12 { \libresocsim_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:4631$727_Y \libresocsim_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:4631$725_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg13 { \libresocsim_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:4632$730_Y \libresocsim_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:4632$728_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg14 { \libresocsim_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:4633$733_Y \libresocsim_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:4633$731_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg15 { \libresocsim_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:4634$736_Y \libresocsim_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:4634$734_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg16 { \libresocsim_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:4635$739_Y \libresocsim_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:4635$737_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg17 { \libresocsim_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:4636$742_Y \libresocsim_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:4636$740_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg18 { \libresocsim_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:4637$745_Y \libresocsim_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:4637$743_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg19 { \libresocsim_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:4638$748_Y \libresocsim_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:4638$746_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg20 { \libresocsim_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:4639$751_Y \libresocsim_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:4639$749_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg21 { \libresocsim_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:4640$754_Y \libresocsim_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:4640$752_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg22 { \libresocsim_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:4641$757_Y \libresocsim_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:4641$755_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg23 { \libresocsim_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:4642$760_Y \libresocsim_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:4642$758_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg24 { \libresocsim_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:4643$763_Y \libresocsim_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:4643$761_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg25 { \libresocsim_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:4644$766_Y \libresocsim_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:4644$764_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg26 { \libresocsim_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:4645$769_Y \libresocsim_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:4645$767_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg27 { \libresocsim_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:4646$772_Y \libresocsim_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:4646$770_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg28 { \libresocsim_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:4647$775_Y \libresocsim_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:4647$773_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg29 { \libresocsim_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:4648$778_Y \libresocsim_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:4648$776_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg30 { \libresocsim_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:4649$781_Y \libresocsim_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:4649$779_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg31 { \libresocsim_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:4650$784_Y \libresocsim_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:4650$782_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg32 { \libresocsim_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:4651$787_Y \libresocsim_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:4651$785_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg33 { \libresocsim_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:4652$790_Y \libresocsim_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:4652$788_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg34 { \libresocsim_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:4653$793_Y \libresocsim_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:4653$791_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg35 { \libresocsim_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:4654$796_Y \libresocsim_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:4654$794_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg36 { \libresocsim_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:4655$799_Y \libresocsim_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:4655$797_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg37 { \libresocsim_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:4656$802_Y \libresocsim_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:4656$800_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg38 { \libresocsim_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:4657$805_Y \libresocsim_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:4657$803_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg39 { \libresocsim_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:4658$808_Y \libresocsim_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:4658$806_Y } - connect \libresocsim_sdcore_crc7_inserter_crcreg40 { \libresocsim_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:4659$811_Y \libresocsim_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:4659$809_Y } - connect \libresocsim_sdcore_crc16_inserter_crc0_val { \libresocsim_sdcore_crc16_inserter_sink_payload_data [4] \libresocsim_sdcore_crc16_inserter_sink_payload_data [0] } - connect \libresocsim_sdcore_crc16_inserter_crc0_clr $and$ls180.v:4669$814_Y - connect \libresocsim_sdcore_crc16_inserter_crc0_enable $and$ls180.v:4670$815_Y - connect \libresocsim_sdcore_crc16_inserter_crc1_val { \libresocsim_sdcore_crc16_inserter_sink_payload_data [5] \libresocsim_sdcore_crc16_inserter_sink_payload_data [1] } - connect \libresocsim_sdcore_crc16_inserter_crc1_clr $and$ls180.v:4672$817_Y - connect \libresocsim_sdcore_crc16_inserter_crc1_enable $and$ls180.v:4673$818_Y - connect \libresocsim_sdcore_crc16_inserter_crc2_val { \libresocsim_sdcore_crc16_inserter_sink_payload_data [6] \libresocsim_sdcore_crc16_inserter_sink_payload_data [2] } - connect \libresocsim_sdcore_crc16_inserter_crc2_clr $and$ls180.v:4675$820_Y - connect \libresocsim_sdcore_crc16_inserter_crc2_enable $and$ls180.v:4676$821_Y - connect \libresocsim_sdcore_crc16_inserter_crc3_val { \libresocsim_sdcore_crc16_inserter_sink_payload_data [7] \libresocsim_sdcore_crc16_inserter_sink_payload_data [3] } - connect \libresocsim_sdcore_crc16_inserter_crc3_clr $and$ls180.v:4678$823_Y - connect \libresocsim_sdcore_crc16_inserter_crc3_enable $and$ls180.v:4679$824_Y - connect \libresocsim_sdcore_crc16_inserter_crc0_crcreg1 { \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:4680$829_Y \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:4680$827_Y \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:4680$825_Y } - connect \libresocsim_sdcore_crc16_inserter_crc0_crcreg2 { \libresocsim_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:4681$834_Y \libresocsim_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:4681$832_Y \libresocsim_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:4681$830_Y } - connect \libresocsim_sdcore_crc16_inserter_crc1_crcreg1 { \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:4690$840_Y \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:4690$838_Y \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:4690$836_Y } - connect \libresocsim_sdcore_crc16_inserter_crc1_crcreg2 { \libresocsim_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:4691$845_Y \libresocsim_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:4691$843_Y \libresocsim_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:4691$841_Y } - connect \libresocsim_sdcore_crc16_inserter_crc2_crcreg1 { \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:4700$851_Y \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:4700$849_Y \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:4700$847_Y } - connect \libresocsim_sdcore_crc16_inserter_crc2_crcreg2 { \libresocsim_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:4701$856_Y \libresocsim_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:4701$854_Y \libresocsim_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:4701$852_Y } - connect \libresocsim_sdcore_crc16_inserter_crc3_crcreg1 { \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:4710$862_Y \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:4710$860_Y \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:4710$858_Y } - connect \libresocsim_sdcore_crc16_inserter_crc3_crcreg2 { \libresocsim_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:4711$867_Y \libresocsim_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:4711$865_Y \libresocsim_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:4711$863_Y } - connect \libresocsim_sdcore_crc16_checker_crc0_val { \libresocsim_sdcore_crc16_checker_val [7] \libresocsim_sdcore_crc16_checker_val [3] } - connect \libresocsim_sdcore_crc16_checker_crc0_enable $and$ls180.v:4807$883_Y - connect \libresocsim_sdcore_crc16_checker_crc1_val { \libresocsim_sdcore_crc16_checker_val [6] \libresocsim_sdcore_crc16_checker_val [2] } - connect \libresocsim_sdcore_crc16_checker_crc1_enable $and$ls180.v:4817$886_Y - connect \libresocsim_sdcore_crc16_checker_crc2_val { \libresocsim_sdcore_crc16_checker_val [5] \libresocsim_sdcore_crc16_checker_val [1] } - connect \libresocsim_sdcore_crc16_checker_crc2_enable $and$ls180.v:4827$889_Y - connect \libresocsim_sdcore_crc16_checker_crc3_val { \libresocsim_sdcore_crc16_checker_val [4] \libresocsim_sdcore_crc16_checker_val [0] } - connect \libresocsim_sdcore_crc16_checker_crc3_enable $and$ls180.v:4837$892_Y - connect \libresocsim_sdcore_crc16_checker_source_payload_data \libresocsim_sdcore_crc16_checker_val - connect \libresocsim_sdcore_crc16_checker_source_last \libresocsim_sdcore_crc16_checker_sink_last - connect \libresocsim_sdcore_crc16_checker_crc0_crcreg1 { \libresocsim_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:4862$904_Y \libresocsim_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:4862$902_Y \libresocsim_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:4862$900_Y } - connect \libresocsim_sdcore_crc16_checker_crc0_crcreg2 { \libresocsim_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:4863$909_Y \libresocsim_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:4863$907_Y \libresocsim_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:4863$905_Y } - connect \libresocsim_sdcore_crc16_checker_crc1_crcreg1 { \libresocsim_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:4872$915_Y \libresocsim_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:4872$913_Y \libresocsim_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:4872$911_Y } - connect \libresocsim_sdcore_crc16_checker_crc1_crcreg2 { \libresocsim_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:4873$920_Y \libresocsim_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:4873$918_Y \libresocsim_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:4873$916_Y } - connect \libresocsim_sdcore_crc16_checker_crc2_crcreg1 { \libresocsim_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:4882$926_Y \libresocsim_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:4882$924_Y \libresocsim_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:4882$922_Y } - connect \libresocsim_sdcore_crc16_checker_crc2_crcreg2 { \libresocsim_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:4883$931_Y \libresocsim_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:4883$929_Y \libresocsim_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:4883$927_Y } - connect \libresocsim_sdcore_crc16_checker_crc3_crcreg1 { \libresocsim_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:4892$937_Y \libresocsim_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:4892$935_Y \libresocsim_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:4892$933_Y } - connect \libresocsim_sdcore_crc16_checker_crc3_crcreg2 { \libresocsim_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:4893$942_Y \libresocsim_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:4893$940_Y \libresocsim_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:4893$938_Y } - connect \libresocsim_sdblock2mem_fifo_sink_valid \libresocsim_sdblock2mem_sink_sink_valid0 - connect \libresocsim_sdblock2mem_sink_sink_ready0 \libresocsim_sdblock2mem_fifo_sink_ready - connect \libresocsim_sdblock2mem_fifo_sink_first \libresocsim_sdblock2mem_sink_sink_first - connect \libresocsim_sdblock2mem_fifo_sink_last \libresocsim_sdblock2mem_sink_sink_last - connect \libresocsim_sdblock2mem_fifo_sink_payload_data \libresocsim_sdblock2mem_sink_sink_payload_data0 - connect \libresocsim_sdblock2mem_converter_sink_valid \libresocsim_sdblock2mem_fifo_source_valid - connect \libresocsim_sdblock2mem_fifo_source_ready \libresocsim_sdblock2mem_converter_sink_ready - connect \libresocsim_sdblock2mem_converter_sink_first \libresocsim_sdblock2mem_fifo_source_first - connect \libresocsim_sdblock2mem_converter_sink_last \libresocsim_sdblock2mem_fifo_source_last - connect \libresocsim_sdblock2mem_converter_sink_payload_data \libresocsim_sdblock2mem_fifo_source_payload_data - connect \libresocsim_sdblock2mem_wishbonedmawriter_sink_valid \libresocsim_sdblock2mem_source_source_valid - connect \libresocsim_sdblock2mem_source_source_ready \libresocsim_sdblock2mem_wishbonedmawriter_sink_ready - connect \libresocsim_sdblock2mem_wishbonedmawriter_sink_first \libresocsim_sdblock2mem_source_source_first - connect \libresocsim_sdblock2mem_wishbonedmawriter_sink_last \libresocsim_sdblock2mem_source_source_last - connect \libresocsim_sdblock2mem_wishbonedmawriter_sink_payload_data \libresocsim_sdblock2mem_source_source_payload_data - connect \libresocsim_sdblock2mem_fifo_syncfifo_din { \libresocsim_sdblock2mem_fifo_fifo_in_last \libresocsim_sdblock2mem_fifo_fifo_in_first \libresocsim_sdblock2mem_fifo_fifo_in_payload_data } - connect { \libresocsim_sdblock2mem_fifo_fifo_out_last \libresocsim_sdblock2mem_fifo_fifo_out_first \libresocsim_sdblock2mem_fifo_fifo_out_payload_data } \libresocsim_sdblock2mem_fifo_syncfifo_dout - connect \libresocsim_sdblock2mem_fifo_sink_ready \libresocsim_sdblock2mem_fifo_syncfifo_writable - connect \libresocsim_sdblock2mem_fifo_syncfifo_we \libresocsim_sdblock2mem_fifo_sink_valid - connect \libresocsim_sdblock2mem_fifo_fifo_in_first \libresocsim_sdblock2mem_fifo_sink_first - connect \libresocsim_sdblock2mem_fifo_fifo_in_last \libresocsim_sdblock2mem_fifo_sink_last - connect \libresocsim_sdblock2mem_fifo_fifo_in_payload_data \libresocsim_sdblock2mem_fifo_sink_payload_data - connect \libresocsim_sdblock2mem_fifo_source_valid \libresocsim_sdblock2mem_fifo_syncfifo_readable - connect \libresocsim_sdblock2mem_fifo_source_first \libresocsim_sdblock2mem_fifo_fifo_out_first - connect \libresocsim_sdblock2mem_fifo_source_last \libresocsim_sdblock2mem_fifo_fifo_out_last - connect \libresocsim_sdblock2mem_fifo_source_payload_data \libresocsim_sdblock2mem_fifo_fifo_out_payload_data - connect \libresocsim_sdblock2mem_fifo_syncfifo_re \libresocsim_sdblock2mem_fifo_source_ready - connect \libresocsim_sdblock2mem_fifo_wrport_dat_w \libresocsim_sdblock2mem_fifo_syncfifo_din - connect \libresocsim_sdblock2mem_fifo_wrport_we $and$ls180.v:5129$972_Y - connect \libresocsim_sdblock2mem_fifo_do_read $and$ls180.v:5130$973_Y - connect \libresocsim_sdblock2mem_fifo_rdport_adr \libresocsim_sdblock2mem_fifo_consume - connect \libresocsim_sdblock2mem_fifo_syncfifo_dout \libresocsim_sdblock2mem_fifo_rdport_dat_r - connect \libresocsim_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5133$974_Y - connect \libresocsim_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5134$975_Y - connect \libresocsim_sdblock2mem_source_source_valid \libresocsim_sdblock2mem_converter_source_valid - connect \libresocsim_sdblock2mem_converter_source_ready \libresocsim_sdblock2mem_source_source_ready - connect \libresocsim_sdblock2mem_source_source_first \libresocsim_sdblock2mem_converter_source_first - connect \libresocsim_sdblock2mem_source_source_last \libresocsim_sdblock2mem_converter_source_last - connect \libresocsim_sdblock2mem_source_source_payload_data \libresocsim_sdblock2mem_converter_source_payload_data - connect \libresocsim_sdblock2mem_converter_sink_ready $or$ls180.v:5140$977_Y - connect \libresocsim_sdblock2mem_converter_source_valid \libresocsim_sdblock2mem_converter_strobe_all - connect \libresocsim_sdblock2mem_converter_load_part $and$ls180.v:5142$978_Y - connect \libresocsim_interface0_bus_stb \libresocsim_sdblock2mem_sink_sink_valid1 - connect \libresocsim_interface0_bus_cyc \libresocsim_sdblock2mem_sink_sink_valid1 - connect \libresocsim_interface0_bus_we 1'1 - connect \libresocsim_interface0_bus_sel 4'1111 - connect \libresocsim_interface0_bus_adr \libresocsim_sdblock2mem_sink_sink_payload_address - connect \libresocsim_interface0_bus_dat_w { \libresocsim_sdblock2mem_sink_sink_payload_data1 [7:0] \libresocsim_sdblock2mem_sink_sink_payload_data1 [15:8] \libresocsim_sdblock2mem_sink_sink_payload_data1 [23:16] \libresocsim_sdblock2mem_sink_sink_payload_data1 [31:24] } - connect \libresocsim_sdblock2mem_sink_sink_ready1 \libresocsim_interface0_bus_ack - connect \libresocsim_sdblock2mem_wishbonedmawriter_base \libresocsim_sdblock2mem_wishbonedmawriter_base_storage [33:2] - connect \libresocsim_sdblock2mem_wishbonedmawriter_length { 2'00 \libresocsim_sdblock2mem_wishbonedmawriter_length_storage [31:2] } - connect \libresocsim_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5152$979_Y - connect \libresocsim_sdmem2block_converter_sink_valid \libresocsim_sdmem2block_dma_source_valid - connect \libresocsim_sdmem2block_dma_source_ready \libresocsim_sdmem2block_converter_sink_ready - connect \libresocsim_sdmem2block_converter_sink_first \libresocsim_sdmem2block_dma_source_first - connect \libresocsim_sdmem2block_converter_sink_last \libresocsim_sdmem2block_dma_source_last - connect \libresocsim_sdmem2block_converter_sink_payload_data \libresocsim_sdmem2block_dma_source_payload_data - connect \libresocsim_sdmem2block_fifo_sink_valid \libresocsim_sdmem2block_source_source_valid1 - connect \libresocsim_sdmem2block_source_source_ready1 \libresocsim_sdmem2block_fifo_sink_ready - connect \libresocsim_sdmem2block_fifo_sink_first \libresocsim_sdmem2block_source_source_first1 - connect \libresocsim_sdmem2block_fifo_sink_last \libresocsim_sdmem2block_source_source_last1 - connect \libresocsim_sdmem2block_fifo_sink_payload_data \libresocsim_sdmem2block_source_source_payload_data1 - connect \libresocsim_sdmem2block_source_source_valid0 \libresocsim_sdmem2block_fifo_source_valid - connect \libresocsim_sdmem2block_fifo_source_ready \libresocsim_sdmem2block_source_source_ready0 - connect \libresocsim_sdmem2block_source_source_first0 \libresocsim_sdmem2block_fifo_source_first - connect \libresocsim_sdmem2block_source_source_last0 \libresocsim_sdmem2block_fifo_source_last - connect \libresocsim_sdmem2block_source_source_payload_data0 \libresocsim_sdmem2block_fifo_source_payload_data - connect \libresocsim_sdmem2block_dma_base \libresocsim_sdmem2block_dma_base_storage [33:2] - connect \libresocsim_sdmem2block_dma_length { 2'00 \libresocsim_sdmem2block_dma_length_storage [31:2] } - connect \libresocsim_sdmem2block_dma_offset_status \libresocsim_sdmem2block_dma_offset - connect \libresocsim_sdmem2block_dma_reset $not$ls180.v:5211$986_Y - connect \libresocsim_sdmem2block_source_source_valid1 \libresocsim_sdmem2block_converter_source_valid - connect \libresocsim_sdmem2block_converter_source_ready \libresocsim_sdmem2block_source_source_ready1 - connect \libresocsim_sdmem2block_source_source_first1 \libresocsim_sdmem2block_converter_source_first - connect \libresocsim_sdmem2block_source_source_last1 \libresocsim_sdmem2block_converter_source_last - connect \libresocsim_sdmem2block_source_source_payload_data1 \libresocsim_sdmem2block_converter_source_payload_data - connect \libresocsim_sdmem2block_converter_first $eq$ls180.v:5292$994_Y - connect \libresocsim_sdmem2block_converter_last $eq$ls180.v:5293$995_Y - connect \libresocsim_sdmem2block_converter_source_valid \libresocsim_sdmem2block_converter_sink_valid - connect \libresocsim_sdmem2block_converter_source_first $and$ls180.v:5295$996_Y - connect \libresocsim_sdmem2block_converter_source_last $and$ls180.v:5296$997_Y - connect \libresocsim_sdmem2block_converter_sink_ready $and$ls180.v:5297$998_Y - connect \libresocsim_sdmem2block_converter_source_payload_valid_token_count \libresocsim_sdmem2block_converter_last - connect \libresocsim_sdmem2block_fifo_syncfifo_din { \libresocsim_sdmem2block_fifo_fifo_in_last \libresocsim_sdmem2block_fifo_fifo_in_first \libresocsim_sdmem2block_fifo_fifo_in_payload_data } - connect { \libresocsim_sdmem2block_fifo_fifo_out_last \libresocsim_sdmem2block_fifo_fifo_out_first \libresocsim_sdmem2block_fifo_fifo_out_payload_data } \libresocsim_sdmem2block_fifo_syncfifo_dout - connect \libresocsim_sdmem2block_fifo_sink_ready \libresocsim_sdmem2block_fifo_syncfifo_writable - connect \libresocsim_sdmem2block_fifo_syncfifo_we \libresocsim_sdmem2block_fifo_sink_valid - connect \libresocsim_sdmem2block_fifo_fifo_in_first \libresocsim_sdmem2block_fifo_sink_first - connect \libresocsim_sdmem2block_fifo_fifo_in_last \libresocsim_sdmem2block_fifo_sink_last - connect \libresocsim_sdmem2block_fifo_fifo_in_payload_data \libresocsim_sdmem2block_fifo_sink_payload_data - connect \libresocsim_sdmem2block_fifo_source_valid \libresocsim_sdmem2block_fifo_syncfifo_readable - connect \libresocsim_sdmem2block_fifo_source_first \libresocsim_sdmem2block_fifo_fifo_out_first - connect \libresocsim_sdmem2block_fifo_source_last \libresocsim_sdmem2block_fifo_fifo_out_last - connect \libresocsim_sdmem2block_fifo_source_payload_data \libresocsim_sdmem2block_fifo_fifo_out_payload_data - connect \libresocsim_sdmem2block_fifo_syncfifo_re \libresocsim_sdmem2block_fifo_source_ready - connect \libresocsim_sdmem2block_fifo_wrport_dat_w \libresocsim_sdmem2block_fifo_syncfifo_din - connect \libresocsim_sdmem2block_fifo_wrport_we $and$ls180.v:5337$1003_Y - connect \libresocsim_sdmem2block_fifo_do_read $and$ls180.v:5338$1004_Y - connect \libresocsim_sdmem2block_fifo_rdport_adr \libresocsim_sdmem2block_fifo_consume - connect \libresocsim_sdmem2block_fifo_syncfifo_dout \libresocsim_sdmem2block_fifo_rdport_dat_r - connect \libresocsim_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5341$1005_Y - connect \libresocsim_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5342$1006_Y - connect \libresocsim_start0 \libresocsim_start1 - connect \libresocsim_length0 \libresocsim_length1 - connect \libresocsim_mosi \libresocsim_mosi_storage - connect \libresocsim_done1 \libresocsim_done0 - connect \libresocsim_miso_status \libresocsim_miso - connect \libresocsim_cs \libresocsim_cs_storage - connect \libresocsim_loopback \libresocsim_loopback_storage - connect \libresocsim_clk_rise $eq$ls180.v:5350$1008_Y - connect \libresocsim_clk_fall $eq$ls180.v:5351$1010_Y - connect \libresocsim_clk_divider0 \libresocsim_storage - connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0] - connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 - connect \builder_shared_sel \builder_comb_rhs_array_muxed26 - connect \builder_shared_cyc \builder_comb_rhs_array_muxed27 - connect \builder_shared_stb \builder_comb_rhs_array_muxed28 - connect \builder_shared_we \builder_comb_rhs_array_muxed29 - connect \builder_shared_cti \builder_comb_rhs_array_muxed30 - connect \builder_shared_bte \builder_comb_rhs_array_muxed31 - connect \main_libresocsim_interface0_converted_interface_dat_r \builder_shared_dat_r - connect \main_libresocsim_interface1_converted_interface_dat_r \builder_shared_dat_r - connect \libresocsim_interface0_bus_dat_r \builder_shared_dat_r - connect \libresocsim_interface1_bus_dat_r \builder_shared_dat_r - connect \main_libresocsim_interface0_converted_interface_ack $and$ls180.v:5451$1020_Y - connect \main_libresocsim_interface1_converted_interface_ack $and$ls180.v:5452$1022_Y - connect \libresocsim_interface0_bus_ack $and$ls180.v:5453$1024_Y - connect \libresocsim_interface1_bus_ack $and$ls180.v:5454$1026_Y - connect \main_libresocsim_interface0_converted_interface_err $and$ls180.v:5455$1028_Y - connect \main_libresocsim_interface1_converted_interface_err $and$ls180.v:5456$1030_Y - connect \libresocsim_interface0_bus_err $and$ls180.v:5457$1032_Y - connect \libresocsim_interface1_bus_err $and$ls180.v:5458$1034_Y - connect \builder_request { \libresocsim_interface1_bus_cyc \libresocsim_interface0_bus_cyc \main_libresocsim_interface1_converted_interface_cyc \main_libresocsim_interface0_converted_interface_cyc } - connect \main_libresocsim_ram_bus_adr \builder_shared_adr - connect \main_libresocsim_ram_bus_dat_w \builder_shared_dat_w - connect \main_libresocsim_ram_bus_sel \builder_shared_sel - connect \main_libresocsim_ram_bus_stb \builder_shared_stb - connect \main_libresocsim_ram_bus_we \builder_shared_we - connect \main_libresocsim_ram_bus_cti \builder_shared_cti - connect \main_libresocsim_ram_bus_bte \builder_shared_bte - connect \main_libresocsim_libresoc_xics_icp_adr \builder_shared_adr - connect \main_libresocsim_libresoc_xics_icp_dat_w \builder_shared_dat_w - connect \main_libresocsim_libresoc_xics_icp_sel \builder_shared_sel - connect \main_libresocsim_libresoc_xics_icp_stb \builder_shared_stb - connect \main_libresocsim_libresoc_xics_icp_we \builder_shared_we - connect \main_libresocsim_libresoc_xics_icp_cti \builder_shared_cti - connect \main_libresocsim_libresoc_xics_icp_bte \builder_shared_bte - connect \main_libresocsim_libresoc_xics_ics_adr \builder_shared_adr - connect \main_libresocsim_libresoc_xics_ics_dat_w \builder_shared_dat_w - connect \main_libresocsim_libresoc_xics_ics_sel \builder_shared_sel - connect \main_libresocsim_libresoc_xics_ics_stb \builder_shared_stb - connect \main_libresocsim_libresoc_xics_ics_we \builder_shared_we - connect \main_libresocsim_libresoc_xics_ics_cti \builder_shared_cti - connect \main_libresocsim_libresoc_xics_ics_bte \builder_shared_bte - connect \main_wb_sdram_adr \builder_shared_adr - connect \main_wb_sdram_dat_w \builder_shared_dat_w - connect \main_wb_sdram_sel \builder_shared_sel - connect \main_wb_sdram_stb \builder_shared_stb - connect \main_wb_sdram_we \builder_shared_we - connect \main_wb_sdram_cti \builder_shared_cti - connect \main_wb_sdram_bte \builder_shared_bte - connect \builder_libresocsim_wishbone_adr \builder_shared_adr - connect \builder_libresocsim_wishbone_dat_w \builder_shared_dat_w - connect \builder_libresocsim_wishbone_sel \builder_shared_sel - connect \builder_libresocsim_wishbone_stb \builder_shared_stb - connect \builder_libresocsim_wishbone_we \builder_shared_we - connect \builder_libresocsim_wishbone_cti \builder_shared_cti - connect \builder_libresocsim_wishbone_bte \builder_shared_bte - connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5503$1041_Y - connect \main_libresocsim_libresoc_xics_icp_cyc $and$ls180.v:5504$1042_Y - connect \main_libresocsim_libresoc_xics_ics_cyc $and$ls180.v:5505$1043_Y - connect \main_wb_sdram_cyc $and$ls180.v:5506$1044_Y - connect \builder_libresocsim_wishbone_cyc $and$ls180.v:5507$1045_Y - connect \builder_shared_err $or$ls180.v:5508$1049_Y - connect \builder_wait $and$ls180.v:5509$1052_Y - connect \builder_done $eq$ls180.v:5522$1067_Y - connect \builder_csrbank0_sel $eq$ls180.v:5523$1068_Y - connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0] - connect \builder_csrbank0_reset0_re $and$ls180.v:5525$1071_Y - connect \builder_csrbank0_reset0_we $and$ls180.v:5526$1075_Y - connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch3_re $and$ls180.v:5528$1078_Y - connect \builder_csrbank0_scratch3_we $and$ls180.v:5529$1082_Y - connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch2_re $and$ls180.v:5531$1085_Y - connect \builder_csrbank0_scratch2_we $and$ls180.v:5532$1089_Y - connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch1_re $and$ls180.v:5534$1092_Y - connect \builder_csrbank0_scratch1_we $and$ls180.v:5535$1096_Y - connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch0_re $and$ls180.v:5537$1099_Y - connect \builder_csrbank0_scratch0_we $and$ls180.v:5538$1103_Y - connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5540$1106_Y - connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5541$1110_Y - connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5543$1113_Y - connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5544$1117_Y - connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5546$1120_Y - connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5547$1124_Y - connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5549$1127_Y - connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5550$1131_Y - connect \builder_csrbank0_reset0_w \main_libresocsim_soccontroller_reset_storage - connect \builder_csrbank0_scratch3_w \main_libresocsim_soccontroller_scratch_storage [31:24] - connect \builder_csrbank0_scratch2_w \main_libresocsim_soccontroller_scratch_storage [23:16] - connect \builder_csrbank0_scratch1_w \main_libresocsim_soccontroller_scratch_storage [15:8] - connect \builder_csrbank0_scratch0_w \main_libresocsim_soccontroller_scratch_storage [7:0] - connect \builder_csrbank0_bus_errors3_w \main_libresocsim_soccontroller_bus_errors_status [31:24] - connect \builder_csrbank0_bus_errors2_w \main_libresocsim_soccontroller_bus_errors_status [23:16] - connect \builder_csrbank0_bus_errors1_w \main_libresocsim_soccontroller_bus_errors_status [15:8] - connect \builder_csrbank0_bus_errors0_w \main_libresocsim_soccontroller_bus_errors_status [7:0] - connect \main_libresocsim_soccontroller_bus_errors_we \builder_csrbank0_bus_errors0_we - connect \builder_csrbank1_sel $eq$ls180.v:5561$1132_Y - connect \builder_csrbank1_in_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in_re $and$ls180.v:5563$1135_Y - connect \builder_csrbank1_in_we $and$ls180.v:5564$1139_Y - connect \builder_csrbank1_in_w \main_gpio_in_status - connect \main_gpio_in_we \builder_csrbank1_in_we - connect \builder_csrbank2_sel $eq$ls180.v:5567$1140_Y - connect \builder_csrbank2_in_r \builder_interface2_bank_bus_dat_w - connect \builder_csrbank2_in_re $and$ls180.v:5569$1143_Y - connect \builder_csrbank2_in_we $and$ls180.v:5570$1147_Y - connect \builder_csrbank2_in_w \main_gpio_out_status - connect \main_gpio_out_we \builder_csrbank2_in_we - connect \builder_csrbank3_sel $eq$ls180.v:5573$1148_Y - connect \builder_csrbank3_dma_base7_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_dma_base7_re $and$ls180.v:5575$1151_Y - connect \builder_csrbank3_dma_base7_we $and$ls180.v:5576$1155_Y - connect \builder_csrbank3_dma_base6_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_dma_base6_re $and$ls180.v:5578$1158_Y - connect \builder_csrbank3_dma_base6_we $and$ls180.v:5579$1162_Y - connect \builder_csrbank3_dma_base5_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_dma_base5_re $and$ls180.v:5581$1165_Y - connect \builder_csrbank3_dma_base5_we $and$ls180.v:5582$1169_Y - connect \builder_csrbank3_dma_base4_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_dma_base4_re $and$ls180.v:5584$1172_Y - connect \builder_csrbank3_dma_base4_we $and$ls180.v:5585$1176_Y - connect \builder_csrbank3_dma_base3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_dma_base3_re $and$ls180.v:5587$1179_Y - connect \builder_csrbank3_dma_base3_we $and$ls180.v:5588$1183_Y - connect \builder_csrbank3_dma_base2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_dma_base2_re $and$ls180.v:5590$1186_Y - connect \builder_csrbank3_dma_base2_we $and$ls180.v:5591$1190_Y - connect \builder_csrbank3_dma_base1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_dma_base1_re $and$ls180.v:5593$1193_Y - connect \builder_csrbank3_dma_base1_we $and$ls180.v:5594$1197_Y - connect \builder_csrbank3_dma_base0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_dma_base0_re $and$ls180.v:5596$1200_Y - connect \builder_csrbank3_dma_base0_we $and$ls180.v:5597$1204_Y - connect \builder_csrbank3_dma_length3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_dma_length3_re $and$ls180.v:5599$1207_Y - connect \builder_csrbank3_dma_length3_we $and$ls180.v:5600$1211_Y - connect \builder_csrbank3_dma_length2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_dma_length2_re $and$ls180.v:5602$1214_Y - connect \builder_csrbank3_dma_length2_we $and$ls180.v:5603$1218_Y - connect \builder_csrbank3_dma_length1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_dma_length1_re $and$ls180.v:5605$1221_Y - connect \builder_csrbank3_dma_length1_we $and$ls180.v:5606$1225_Y - connect \builder_csrbank3_dma_length0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_dma_length0_re $and$ls180.v:5608$1228_Y - connect \builder_csrbank3_dma_length0_we $and$ls180.v:5609$1232_Y - connect \builder_csrbank3_dma_enable0_r \builder_interface3_bank_bus_dat_w [0] - connect \builder_csrbank3_dma_enable0_re $and$ls180.v:5611$1235_Y - connect \builder_csrbank3_dma_enable0_we $and$ls180.v:5612$1239_Y - connect \builder_csrbank3_dma_done_r \builder_interface3_bank_bus_dat_w [0] - connect \builder_csrbank3_dma_done_re $and$ls180.v:5614$1242_Y - connect \builder_csrbank3_dma_done_we $and$ls180.v:5615$1246_Y - connect \builder_csrbank3_dma_loop0_r \builder_interface3_bank_bus_dat_w [0] - connect \builder_csrbank3_dma_loop0_re $and$ls180.v:5617$1249_Y - connect \builder_csrbank3_dma_loop0_we $and$ls180.v:5618$1253_Y - connect \builder_csrbank3_dma_base7_w \libresocsim_sdblock2mem_wishbonedmawriter_base_storage [63:56] - connect \builder_csrbank3_dma_base6_w \libresocsim_sdblock2mem_wishbonedmawriter_base_storage [55:48] - connect \builder_csrbank3_dma_base5_w \libresocsim_sdblock2mem_wishbonedmawriter_base_storage [47:40] - connect \builder_csrbank3_dma_base4_w \libresocsim_sdblock2mem_wishbonedmawriter_base_storage [39:32] - connect \builder_csrbank3_dma_base3_w \libresocsim_sdblock2mem_wishbonedmawriter_base_storage [31:24] - connect \builder_csrbank3_dma_base2_w \libresocsim_sdblock2mem_wishbonedmawriter_base_storage [23:16] - connect \builder_csrbank3_dma_base1_w \libresocsim_sdblock2mem_wishbonedmawriter_base_storage [15:8] - connect \builder_csrbank3_dma_base0_w \libresocsim_sdblock2mem_wishbonedmawriter_base_storage [7:0] - connect \builder_csrbank3_dma_length3_w \libresocsim_sdblock2mem_wishbonedmawriter_length_storage [31:24] - connect \builder_csrbank3_dma_length2_w \libresocsim_sdblock2mem_wishbonedmawriter_length_storage [23:16] - connect \builder_csrbank3_dma_length1_w \libresocsim_sdblock2mem_wishbonedmawriter_length_storage [15:8] - connect \builder_csrbank3_dma_length0_w \libresocsim_sdblock2mem_wishbonedmawriter_length_storage [7:0] - connect \builder_csrbank3_dma_enable0_w \libresocsim_sdblock2mem_wishbonedmawriter_enable_storage - connect \builder_csrbank3_dma_done_w \libresocsim_sdblock2mem_wishbonedmawriter_status - connect \libresocsim_sdblock2mem_wishbonedmawriter_we \builder_csrbank3_dma_done_we - connect \builder_csrbank3_dma_loop0_w \libresocsim_sdblock2mem_wishbonedmawriter_loop_storage - connect \builder_csrbank4_sel $eq$ls180.v:5635$1254_Y - connect \builder_csrbank4_cmd_argument3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_cmd_argument3_re $and$ls180.v:5637$1257_Y - connect \builder_csrbank4_cmd_argument3_we $and$ls180.v:5638$1261_Y - connect \builder_csrbank4_cmd_argument2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_cmd_argument2_re $and$ls180.v:5640$1264_Y - connect \builder_csrbank4_cmd_argument2_we $and$ls180.v:5641$1268_Y - connect \builder_csrbank4_cmd_argument1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_cmd_argument1_re $and$ls180.v:5643$1271_Y - connect \builder_csrbank4_cmd_argument1_we $and$ls180.v:5644$1275_Y - connect \builder_csrbank4_cmd_argument0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_cmd_argument0_re $and$ls180.v:5646$1278_Y - connect \builder_csrbank4_cmd_argument0_we $and$ls180.v:5647$1282_Y - connect \builder_csrbank4_cmd_command3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_cmd_command3_re $and$ls180.v:5649$1285_Y - connect \builder_csrbank4_cmd_command3_we $and$ls180.v:5650$1289_Y - connect \builder_csrbank4_cmd_command2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_cmd_command2_re $and$ls180.v:5652$1292_Y - connect \builder_csrbank4_cmd_command2_we $and$ls180.v:5653$1296_Y - connect \builder_csrbank4_cmd_command1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_cmd_command1_re $and$ls180.v:5655$1299_Y - connect \builder_csrbank4_cmd_command1_we $and$ls180.v:5656$1303_Y - connect \builder_csrbank4_cmd_command0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_cmd_command0_re $and$ls180.v:5658$1306_Y - connect \builder_csrbank4_cmd_command0_we $and$ls180.v:5659$1310_Y - connect \libresocsim_sdcore_cmd_send_r \builder_interface4_bank_bus_dat_w [0] - connect \libresocsim_sdcore_cmd_send_re $and$ls180.v:5661$1313_Y - connect \libresocsim_sdcore_cmd_send_we $and$ls180.v:5662$1317_Y - connect \builder_csrbank4_cmd_response15_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_cmd_response15_re $and$ls180.v:5664$1320_Y - connect \builder_csrbank4_cmd_response15_we $and$ls180.v:5665$1324_Y - connect \builder_csrbank4_cmd_response14_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_cmd_response14_re $and$ls180.v:5667$1327_Y - connect \builder_csrbank4_cmd_response14_we $and$ls180.v:5668$1331_Y - connect \builder_csrbank4_cmd_response13_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_cmd_response13_re $and$ls180.v:5670$1334_Y - connect \builder_csrbank4_cmd_response13_we $and$ls180.v:5671$1338_Y - connect \builder_csrbank4_cmd_response12_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_cmd_response12_re $and$ls180.v:5673$1341_Y - connect \builder_csrbank4_cmd_response12_we $and$ls180.v:5674$1345_Y - connect \builder_csrbank4_cmd_response11_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_cmd_response11_re $and$ls180.v:5676$1348_Y - connect \builder_csrbank4_cmd_response11_we $and$ls180.v:5677$1352_Y - connect \builder_csrbank4_cmd_response10_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_cmd_response10_re $and$ls180.v:5679$1355_Y - connect \builder_csrbank4_cmd_response10_we $and$ls180.v:5680$1359_Y - connect \builder_csrbank4_cmd_response9_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_cmd_response9_re $and$ls180.v:5682$1362_Y - connect \builder_csrbank4_cmd_response9_we $and$ls180.v:5683$1366_Y - connect \builder_csrbank4_cmd_response8_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_cmd_response8_re $and$ls180.v:5685$1369_Y - connect \builder_csrbank4_cmd_response8_we $and$ls180.v:5686$1373_Y - connect \builder_csrbank4_cmd_response7_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_cmd_response7_re $and$ls180.v:5688$1376_Y - connect \builder_csrbank4_cmd_response7_we $and$ls180.v:5689$1380_Y - connect \builder_csrbank4_cmd_response6_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_cmd_response6_re $and$ls180.v:5691$1383_Y - connect \builder_csrbank4_cmd_response6_we $and$ls180.v:5692$1387_Y - connect \builder_csrbank4_cmd_response5_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_cmd_response5_re $and$ls180.v:5694$1390_Y - connect \builder_csrbank4_cmd_response5_we $and$ls180.v:5695$1394_Y - connect \builder_csrbank4_cmd_response4_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_cmd_response4_re $and$ls180.v:5697$1397_Y - connect \builder_csrbank4_cmd_response4_we $and$ls180.v:5698$1401_Y - connect \builder_csrbank4_cmd_response3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_cmd_response3_re $and$ls180.v:5700$1404_Y - connect \builder_csrbank4_cmd_response3_we $and$ls180.v:5701$1408_Y - connect \builder_csrbank4_cmd_response2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_cmd_response2_re $and$ls180.v:5703$1411_Y - connect \builder_csrbank4_cmd_response2_we $and$ls180.v:5704$1415_Y - connect \builder_csrbank4_cmd_response1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_cmd_response1_re $and$ls180.v:5706$1418_Y - connect \builder_csrbank4_cmd_response1_we $and$ls180.v:5707$1422_Y - connect \builder_csrbank4_cmd_response0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_cmd_response0_re $and$ls180.v:5709$1425_Y - connect \builder_csrbank4_cmd_response0_we $and$ls180.v:5710$1429_Y - connect \builder_csrbank4_cmd_event_r \builder_interface4_bank_bus_dat_w [3:0] - connect \builder_csrbank4_cmd_event_re $and$ls180.v:5712$1432_Y - connect \builder_csrbank4_cmd_event_we $and$ls180.v:5713$1436_Y - connect \builder_csrbank4_data_event_r \builder_interface4_bank_bus_dat_w [3:0] - connect \builder_csrbank4_data_event_re $and$ls180.v:5715$1439_Y - connect \builder_csrbank4_data_event_we $and$ls180.v:5716$1443_Y - connect \builder_csrbank4_block_length1_r \builder_interface4_bank_bus_dat_w [1:0] - connect \builder_csrbank4_block_length1_re $and$ls180.v:5718$1446_Y - connect \builder_csrbank4_block_length1_we $and$ls180.v:5719$1450_Y - connect \builder_csrbank4_block_length0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_block_length0_re $and$ls180.v:5721$1453_Y - connect \builder_csrbank4_block_length0_we $and$ls180.v:5722$1457_Y - connect \builder_csrbank4_block_count3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_block_count3_re $and$ls180.v:5724$1460_Y - connect \builder_csrbank4_block_count3_we $and$ls180.v:5725$1464_Y - connect \builder_csrbank4_block_count2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_block_count2_re $and$ls180.v:5727$1467_Y - connect \builder_csrbank4_block_count2_we $and$ls180.v:5728$1471_Y - connect \builder_csrbank4_block_count1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_block_count1_re $and$ls180.v:5730$1474_Y - connect \builder_csrbank4_block_count1_we $and$ls180.v:5731$1478_Y - connect \builder_csrbank4_block_count0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_block_count0_re $and$ls180.v:5733$1481_Y - connect \builder_csrbank4_block_count0_we $and$ls180.v:5734$1485_Y - connect \builder_csrbank4_cmd_argument3_w \libresocsim_sdcore_cmd_argument_storage [31:24] - connect \builder_csrbank4_cmd_argument2_w \libresocsim_sdcore_cmd_argument_storage [23:16] - connect \builder_csrbank4_cmd_argument1_w \libresocsim_sdcore_cmd_argument_storage [15:8] - connect \builder_csrbank4_cmd_argument0_w \libresocsim_sdcore_cmd_argument_storage [7:0] - connect \builder_csrbank4_cmd_command3_w \libresocsim_sdcore_cmd_command_storage [31:24] - connect \builder_csrbank4_cmd_command2_w \libresocsim_sdcore_cmd_command_storage [23:16] - connect \builder_csrbank4_cmd_command1_w \libresocsim_sdcore_cmd_command_storage [15:8] - connect \builder_csrbank4_cmd_command0_w \libresocsim_sdcore_cmd_command_storage [7:0] - connect \builder_csrbank4_cmd_response15_w \libresocsim_sdcore_cmd_response_status [127:120] - connect \builder_csrbank4_cmd_response14_w \libresocsim_sdcore_cmd_response_status [119:112] - connect \builder_csrbank4_cmd_response13_w \libresocsim_sdcore_cmd_response_status [111:104] - connect \builder_csrbank4_cmd_response12_w \libresocsim_sdcore_cmd_response_status [103:96] - connect \builder_csrbank4_cmd_response11_w \libresocsim_sdcore_cmd_response_status [95:88] - connect \builder_csrbank4_cmd_response10_w \libresocsim_sdcore_cmd_response_status [87:80] - connect \builder_csrbank4_cmd_response9_w \libresocsim_sdcore_cmd_response_status [79:72] - connect \builder_csrbank4_cmd_response8_w \libresocsim_sdcore_cmd_response_status [71:64] - connect \builder_csrbank4_cmd_response7_w \libresocsim_sdcore_cmd_response_status [63:56] - connect \builder_csrbank4_cmd_response6_w \libresocsim_sdcore_cmd_response_status [55:48] - connect \builder_csrbank4_cmd_response5_w \libresocsim_sdcore_cmd_response_status [47:40] - connect \builder_csrbank4_cmd_response4_w \libresocsim_sdcore_cmd_response_status [39:32] - connect \builder_csrbank4_cmd_response3_w \libresocsim_sdcore_cmd_response_status [31:24] - connect \builder_csrbank4_cmd_response2_w \libresocsim_sdcore_cmd_response_status [23:16] - connect \builder_csrbank4_cmd_response1_w \libresocsim_sdcore_cmd_response_status [15:8] - connect \builder_csrbank4_cmd_response0_w \libresocsim_sdcore_cmd_response_status [7:0] - connect \libresocsim_sdcore_cmd_response_we \builder_csrbank4_cmd_response0_we - connect \builder_csrbank4_cmd_event_w \libresocsim_sdcore_cmd_event_status - connect \libresocsim_sdcore_cmd_event_we \builder_csrbank4_cmd_event_we - connect \builder_csrbank4_data_event_w \libresocsim_sdcore_data_event_status - connect \libresocsim_sdcore_data_event_we \builder_csrbank4_data_event_we - connect \builder_csrbank4_block_length1_w \libresocsim_sdcore_block_length_storage [9:8] - connect \builder_csrbank4_block_length0_w \libresocsim_sdcore_block_length_storage [7:0] - connect \builder_csrbank4_block_count3_w \libresocsim_sdcore_block_count_storage [31:24] - connect \builder_csrbank4_block_count2_w \libresocsim_sdcore_block_count_storage [23:16] - connect \builder_csrbank4_block_count1_w \libresocsim_sdcore_block_count_storage [15:8] - connect \builder_csrbank4_block_count0_w \libresocsim_sdcore_block_count_storage [7:0] - connect \builder_csrbank5_sel $eq$ls180.v:5770$1486_Y - connect \builder_csrbank5_dma_base7_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base7_re $and$ls180.v:5772$1489_Y - connect \builder_csrbank5_dma_base7_we $and$ls180.v:5773$1493_Y - connect \builder_csrbank5_dma_base6_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base6_re $and$ls180.v:5775$1496_Y - connect \builder_csrbank5_dma_base6_we $and$ls180.v:5776$1500_Y - connect \builder_csrbank5_dma_base5_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base5_re $and$ls180.v:5778$1503_Y - connect \builder_csrbank5_dma_base5_we $and$ls180.v:5779$1507_Y - connect \builder_csrbank5_dma_base4_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base4_re $and$ls180.v:5781$1510_Y - connect \builder_csrbank5_dma_base4_we $and$ls180.v:5782$1514_Y - connect \builder_csrbank5_dma_base3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base3_re $and$ls180.v:5784$1517_Y - connect \builder_csrbank5_dma_base3_we $and$ls180.v:5785$1521_Y - connect \builder_csrbank5_dma_base2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base2_re $and$ls180.v:5787$1524_Y - connect \builder_csrbank5_dma_base2_we $and$ls180.v:5788$1528_Y - connect \builder_csrbank5_dma_base1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base1_re $and$ls180.v:5790$1531_Y - connect \builder_csrbank5_dma_base1_we $and$ls180.v:5791$1535_Y - connect \builder_csrbank5_dma_base0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base0_re $and$ls180.v:5793$1538_Y - connect \builder_csrbank5_dma_base0_we $and$ls180.v:5794$1542_Y - connect \builder_csrbank5_dma_length3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length3_re $and$ls180.v:5796$1545_Y - connect \builder_csrbank5_dma_length3_we $and$ls180.v:5797$1549_Y - connect \builder_csrbank5_dma_length2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length2_re $and$ls180.v:5799$1552_Y - connect \builder_csrbank5_dma_length2_we $and$ls180.v:5800$1556_Y - connect \builder_csrbank5_dma_length1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length1_re $and$ls180.v:5802$1559_Y - connect \builder_csrbank5_dma_length1_we $and$ls180.v:5803$1563_Y - connect \builder_csrbank5_dma_length0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length0_re $and$ls180.v:5805$1566_Y - connect \builder_csrbank5_dma_length0_we $and$ls180.v:5806$1570_Y - connect \builder_csrbank5_dma_enable0_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_enable0_re $and$ls180.v:5808$1573_Y - connect \builder_csrbank5_dma_enable0_we $and$ls180.v:5809$1577_Y - connect \builder_csrbank5_dma_done_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_done_re $and$ls180.v:5811$1580_Y - connect \builder_csrbank5_dma_done_we $and$ls180.v:5812$1584_Y - connect \builder_csrbank5_dma_loop0_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_loop0_re $and$ls180.v:5814$1587_Y - connect \builder_csrbank5_dma_loop0_we $and$ls180.v:5815$1591_Y - connect \builder_csrbank5_dma_offset3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_offset3_re $and$ls180.v:5817$1594_Y - connect \builder_csrbank5_dma_offset3_we $and$ls180.v:5818$1598_Y - connect \builder_csrbank5_dma_offset2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_offset2_re $and$ls180.v:5820$1601_Y - connect \builder_csrbank5_dma_offset2_we $and$ls180.v:5821$1605_Y - connect \builder_csrbank5_dma_offset1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_offset1_re $and$ls180.v:5823$1608_Y - connect \builder_csrbank5_dma_offset1_we $and$ls180.v:5824$1612_Y - connect \builder_csrbank5_dma_offset0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_offset0_re $and$ls180.v:5826$1615_Y - connect \builder_csrbank5_dma_offset0_we $and$ls180.v:5827$1619_Y - connect \builder_csrbank5_dma_base7_w \libresocsim_sdmem2block_dma_base_storage [63:56] - connect \builder_csrbank5_dma_base6_w \libresocsim_sdmem2block_dma_base_storage [55:48] - connect \builder_csrbank5_dma_base5_w \libresocsim_sdmem2block_dma_base_storage [47:40] - connect \builder_csrbank5_dma_base4_w \libresocsim_sdmem2block_dma_base_storage [39:32] - connect \builder_csrbank5_dma_base3_w \libresocsim_sdmem2block_dma_base_storage [31:24] - connect \builder_csrbank5_dma_base2_w \libresocsim_sdmem2block_dma_base_storage [23:16] - connect \builder_csrbank5_dma_base1_w \libresocsim_sdmem2block_dma_base_storage [15:8] - connect \builder_csrbank5_dma_base0_w \libresocsim_sdmem2block_dma_base_storage [7:0] - connect \builder_csrbank5_dma_length3_w \libresocsim_sdmem2block_dma_length_storage [31:24] - connect \builder_csrbank5_dma_length2_w \libresocsim_sdmem2block_dma_length_storage [23:16] - connect \builder_csrbank5_dma_length1_w \libresocsim_sdmem2block_dma_length_storage [15:8] - connect \builder_csrbank5_dma_length0_w \libresocsim_sdmem2block_dma_length_storage [7:0] - connect \builder_csrbank5_dma_enable0_w \libresocsim_sdmem2block_dma_enable_storage - connect \builder_csrbank5_dma_done_w \libresocsim_sdmem2block_dma_done_status - connect \libresocsim_sdmem2block_dma_done_we \builder_csrbank5_dma_done_we - connect \builder_csrbank5_dma_loop0_w \libresocsim_sdmem2block_dma_loop_storage - connect \builder_csrbank5_dma_offset3_w \libresocsim_sdmem2block_dma_offset_status [31:24] - connect \builder_csrbank5_dma_offset2_w \libresocsim_sdmem2block_dma_offset_status [23:16] - connect \builder_csrbank5_dma_offset1_w \libresocsim_sdmem2block_dma_offset_status [15:8] - connect \builder_csrbank5_dma_offset0_w \libresocsim_sdmem2block_dma_offset_status [7:0] - connect \libresocsim_sdmem2block_dma_offset_we \builder_csrbank5_dma_offset0_we - connect \builder_csrbank6_sel $eq$ls180.v:5849$1620_Y - connect \builder_csrbank6_card_detect_r \builder_interface6_bank_bus_dat_w [0] - connect \builder_csrbank6_card_detect_re $and$ls180.v:5851$1623_Y - connect \builder_csrbank6_card_detect_we $and$ls180.v:5852$1627_Y - connect \builder_csrbank6_clocker_divider1_r \builder_interface6_bank_bus_dat_w [0] - connect \builder_csrbank6_clocker_divider1_re $and$ls180.v:5854$1630_Y - connect \builder_csrbank6_clocker_divider1_we $and$ls180.v:5855$1634_Y - connect \builder_csrbank6_clocker_divider0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_clocker_divider0_re $and$ls180.v:5857$1637_Y - connect \builder_csrbank6_clocker_divider0_we $and$ls180.v:5858$1641_Y - connect \libresocsim_init_initialize_r \builder_interface6_bank_bus_dat_w [0] - connect \libresocsim_init_initialize_re $and$ls180.v:5860$1644_Y - connect \libresocsim_init_initialize_we $and$ls180.v:5861$1648_Y - connect \builder_csrbank6_card_detect_w \libresocsim_status - connect \libresocsim_we \builder_csrbank6_card_detect_we - connect \builder_csrbank6_clocker_divider1_w \libresocsim_clocker_storage [8] - connect \builder_csrbank6_clocker_divider0_w \libresocsim_clocker_storage [7:0] - connect \builder_csrbank7_sel $eq$ls180.v:5866$1649_Y - connect \builder_csrbank7_dfii_control0_r \builder_interface7_bank_bus_dat_w [3:0] - connect \builder_csrbank7_dfii_control0_re $and$ls180.v:5868$1652_Y - connect \builder_csrbank7_dfii_control0_we $and$ls180.v:5869$1656_Y - connect \builder_csrbank7_dfii_pi0_command0_r \builder_interface7_bank_bus_dat_w [5:0] - connect \builder_csrbank7_dfii_pi0_command0_re $and$ls180.v:5871$1659_Y - connect \builder_csrbank7_dfii_pi0_command0_we $and$ls180.v:5872$1663_Y - connect \main_sdram_command_issue_r \builder_interface7_bank_bus_dat_w [0] - connect \main_sdram_command_issue_re $and$ls180.v:5874$1666_Y - connect \main_sdram_command_issue_we $and$ls180.v:5875$1670_Y - connect \builder_csrbank7_dfii_pi0_address1_r \builder_interface7_bank_bus_dat_w [4:0] - connect \builder_csrbank7_dfii_pi0_address1_re $and$ls180.v:5877$1673_Y - connect \builder_csrbank7_dfii_pi0_address1_we $and$ls180.v:5878$1677_Y - connect \builder_csrbank7_dfii_pi0_address0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dfii_pi0_address0_re $and$ls180.v:5880$1680_Y - connect \builder_csrbank7_dfii_pi0_address0_we $and$ls180.v:5881$1684_Y - connect \builder_csrbank7_dfii_pi0_baddress0_r \builder_interface7_bank_bus_dat_w [1:0] - connect \builder_csrbank7_dfii_pi0_baddress0_re $and$ls180.v:5883$1687_Y - connect \builder_csrbank7_dfii_pi0_baddress0_we $and$ls180.v:5884$1691_Y - connect \builder_csrbank7_dfii_pi0_wrdata1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dfii_pi0_wrdata1_re $and$ls180.v:5886$1694_Y - connect \builder_csrbank7_dfii_pi0_wrdata1_we $and$ls180.v:5887$1698_Y - connect \builder_csrbank7_dfii_pi0_wrdata0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dfii_pi0_wrdata0_re $and$ls180.v:5889$1701_Y - connect \builder_csrbank7_dfii_pi0_wrdata0_we $and$ls180.v:5890$1705_Y - connect \builder_csrbank7_dfii_pi0_rddata1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dfii_pi0_rddata1_re $and$ls180.v:5892$1708_Y - connect \builder_csrbank7_dfii_pi0_rddata1_we $and$ls180.v:5893$1712_Y - connect \builder_csrbank7_dfii_pi0_rddata0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dfii_pi0_rddata0_re $and$ls180.v:5895$1715_Y - connect \builder_csrbank7_dfii_pi0_rddata0_we $and$ls180.v:5896$1719_Y - connect \main_sdram_sel \main_sdram_storage [0] - connect \main_sdram_cke \main_sdram_storage [1] - connect \main_sdram_odt \main_sdram_storage [2] - connect \main_sdram_reset_n \main_sdram_storage [3] - connect \builder_csrbank7_dfii_control0_w \main_sdram_storage - connect \builder_csrbank7_dfii_pi0_command0_w \main_sdram_command_storage - connect \builder_csrbank7_dfii_pi0_address1_w \main_sdram_address_storage [12:8] - connect \builder_csrbank7_dfii_pi0_address0_w \main_sdram_address_storage [7:0] - connect \builder_csrbank7_dfii_pi0_baddress0_w \main_sdram_baddress_storage - connect \builder_csrbank7_dfii_pi0_wrdata1_w \main_sdram_wrdata_storage [15:8] - connect \builder_csrbank7_dfii_pi0_wrdata0_w \main_sdram_wrdata_storage [7:0] - connect \builder_csrbank7_dfii_pi0_rddata1_w \main_sdram_status [15:8] - connect \builder_csrbank7_dfii_pi0_rddata0_w \main_sdram_status [7:0] - connect \main_sdram_we \builder_csrbank7_dfii_pi0_rddata0_we - connect \builder_csrbank8_sel $eq$ls180.v:5911$1720_Y - connect \builder_csrbank8_control1_r \builder_interface8_bank_bus_dat_w - connect \builder_csrbank8_control1_re $and$ls180.v:5913$1723_Y - connect \builder_csrbank8_control1_we $and$ls180.v:5914$1727_Y - connect \builder_csrbank8_control0_r \builder_interface8_bank_bus_dat_w - connect \builder_csrbank8_control0_re $and$ls180.v:5916$1730_Y - connect \builder_csrbank8_control0_we $and$ls180.v:5917$1734_Y - connect \builder_csrbank8_status_r \builder_interface8_bank_bus_dat_w [0] - connect \builder_csrbank8_status_re $and$ls180.v:5919$1737_Y - connect \builder_csrbank8_status_we $and$ls180.v:5920$1741_Y - connect \builder_csrbank8_mosi0_r \builder_interface8_bank_bus_dat_w - connect \builder_csrbank8_mosi0_re $and$ls180.v:5922$1744_Y - connect \builder_csrbank8_mosi0_we $and$ls180.v:5923$1748_Y - connect \builder_csrbank8_miso_r \builder_interface8_bank_bus_dat_w - connect \builder_csrbank8_miso_re $and$ls180.v:5925$1751_Y - connect \builder_csrbank8_miso_we $and$ls180.v:5926$1755_Y - connect \builder_csrbank8_cs0_r \builder_interface8_bank_bus_dat_w [0] - connect \builder_csrbank8_cs0_re $and$ls180.v:5928$1758_Y - connect \builder_csrbank8_cs0_we $and$ls180.v:5929$1762_Y - connect \builder_csrbank8_loopback0_r \builder_interface8_bank_bus_dat_w [0] - connect \builder_csrbank8_loopback0_re $and$ls180.v:5931$1765_Y - connect \builder_csrbank8_loopback0_we $and$ls180.v:5932$1769_Y - connect \main_length1 \main_control_storage [15:8] - connect \builder_csrbank8_control1_w \main_control_storage [15:8] - connect \builder_csrbank8_control0_w \main_control_storage [7:0] - connect \main_status_status \main_done1 - connect \builder_csrbank8_status_w \main_status_status - connect \main_status_we \builder_csrbank8_status_we - connect \builder_csrbank8_mosi0_w \main_mosi_storage - connect \builder_csrbank8_miso_w \main_miso_status - connect \main_miso_we \builder_csrbank8_miso_we - connect \main_sel \main_cs_storage - connect \builder_csrbank8_cs0_w \main_cs_storage - connect \builder_csrbank8_loopback0_w \main_loopback_storage - connect \builder_csrbank9_sel $eq$ls180.v:5951$1771_Y - connect \builder_csrbank9_control1_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_control1_re $and$ls180.v:5953$1774_Y - connect \builder_csrbank9_control1_we $and$ls180.v:5954$1778_Y - connect \builder_csrbank9_control0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_control0_re $and$ls180.v:5956$1781_Y - connect \builder_csrbank9_control0_we $and$ls180.v:5957$1785_Y - connect \builder_csrbank9_status_r \builder_interface9_bank_bus_dat_w [0] - connect \builder_csrbank9_status_re $and$ls180.v:5959$1788_Y - connect \builder_csrbank9_status_we $and$ls180.v:5960$1792_Y - connect \builder_csrbank9_mosi0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_mosi0_re $and$ls180.v:5962$1795_Y - connect \builder_csrbank9_mosi0_we $and$ls180.v:5963$1799_Y - connect \builder_csrbank9_miso_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_miso_re $and$ls180.v:5965$1802_Y - connect \builder_csrbank9_miso_we $and$ls180.v:5966$1806_Y - connect \builder_csrbank9_cs0_r \builder_interface9_bank_bus_dat_w [0] - connect \builder_csrbank9_cs0_re $and$ls180.v:5968$1809_Y - connect \builder_csrbank9_cs0_we $and$ls180.v:5969$1813_Y - connect \builder_csrbank9_loopback0_r \builder_interface9_bank_bus_dat_w [0] - connect \builder_csrbank9_loopback0_re $and$ls180.v:5971$1816_Y - connect \builder_csrbank9_loopback0_we $and$ls180.v:5972$1820_Y - connect \builder_csrbank9_clk_divider1_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_clk_divider1_re $and$ls180.v:5974$1823_Y - connect \builder_csrbank9_clk_divider1_we $and$ls180.v:5975$1827_Y - connect \builder_csrbank9_clk_divider0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_clk_divider0_re $and$ls180.v:5977$1830_Y - connect \builder_csrbank9_clk_divider0_we $and$ls180.v:5978$1834_Y - connect \libresocsim_length1 \libresocsim_control_storage [15:8] - connect \builder_csrbank9_control1_w \libresocsim_control_storage [15:8] - connect \builder_csrbank9_control0_w \libresocsim_control_storage [7:0] - connect \libresocsim_status_status \libresocsim_done1 - connect \builder_csrbank9_status_w \libresocsim_status_status - connect \libresocsim_status_we \builder_csrbank9_status_we - connect \builder_csrbank9_mosi0_w \libresocsim_mosi_storage - connect \builder_csrbank9_miso_w \libresocsim_miso_status - connect \libresocsim_miso_we \builder_csrbank9_miso_we - connect \libresocsim_sel \libresocsim_cs_storage - connect \builder_csrbank9_cs0_w \libresocsim_cs_storage - connect \builder_csrbank9_loopback0_w \libresocsim_loopback_storage - connect \builder_csrbank9_clk_divider1_w \libresocsim_storage [15:8] - connect \builder_csrbank9_clk_divider0_w \libresocsim_storage [7:0] - connect \builder_csrbank10_sel $eq$ls180.v:5999$1836_Y - connect \builder_csrbank10_load3_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_load3_re $and$ls180.v:6001$1839_Y - connect \builder_csrbank10_load3_we $and$ls180.v:6002$1843_Y - connect \builder_csrbank10_load2_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_load2_re $and$ls180.v:6004$1846_Y - connect \builder_csrbank10_load2_we $and$ls180.v:6005$1850_Y - connect \builder_csrbank10_load1_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_load1_re $and$ls180.v:6007$1853_Y - connect \builder_csrbank10_load1_we $and$ls180.v:6008$1857_Y - connect \builder_csrbank10_load0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_load0_re $and$ls180.v:6010$1860_Y - connect \builder_csrbank10_load0_we $and$ls180.v:6011$1864_Y - connect \builder_csrbank10_reload3_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_reload3_re $and$ls180.v:6013$1867_Y - connect \builder_csrbank10_reload3_we $and$ls180.v:6014$1871_Y - connect \builder_csrbank10_reload2_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_reload2_re $and$ls180.v:6016$1874_Y - connect \builder_csrbank10_reload2_we $and$ls180.v:6017$1878_Y - connect \builder_csrbank10_reload1_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_reload1_re $and$ls180.v:6019$1881_Y - connect \builder_csrbank10_reload1_we $and$ls180.v:6020$1885_Y - connect \builder_csrbank10_reload0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_reload0_re $and$ls180.v:6022$1888_Y - connect \builder_csrbank10_reload0_we $and$ls180.v:6023$1892_Y - connect \builder_csrbank10_en0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_en0_re $and$ls180.v:6025$1895_Y - connect \builder_csrbank10_en0_we $and$ls180.v:6026$1899_Y - connect \builder_csrbank10_update_value0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_update_value0_re $and$ls180.v:6028$1902_Y - connect \builder_csrbank10_update_value0_we $and$ls180.v:6029$1906_Y - connect \builder_csrbank10_value3_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_value3_re $and$ls180.v:6031$1909_Y - connect \builder_csrbank10_value3_we $and$ls180.v:6032$1913_Y - connect \builder_csrbank10_value2_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_value2_re $and$ls180.v:6034$1916_Y - connect \builder_csrbank10_value2_we $and$ls180.v:6035$1920_Y - connect \builder_csrbank10_value1_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_value1_re $and$ls180.v:6037$1923_Y - connect \builder_csrbank10_value1_we $and$ls180.v:6038$1927_Y - connect \builder_csrbank10_value0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_value0_re $and$ls180.v:6040$1930_Y - connect \builder_csrbank10_value0_we $and$ls180.v:6041$1934_Y - connect \main_libresocsim_timer_eventmanager_status_r \builder_interface10_bank_bus_dat_w [0] - connect \main_libresocsim_timer_eventmanager_status_re $and$ls180.v:6043$1937_Y - connect \main_libresocsim_timer_eventmanager_status_we $and$ls180.v:6044$1941_Y - connect \main_libresocsim_timer_eventmanager_pending_r \builder_interface10_bank_bus_dat_w [0] - connect \main_libresocsim_timer_eventmanager_pending_re $and$ls180.v:6046$1944_Y - connect \main_libresocsim_timer_eventmanager_pending_we $and$ls180.v:6047$1948_Y - connect \builder_csrbank10_ev_enable0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_ev_enable0_re $and$ls180.v:6049$1951_Y - connect \builder_csrbank10_ev_enable0_we $and$ls180.v:6050$1955_Y - connect \builder_csrbank10_load3_w \main_libresocsim_timer_load_storage [31:24] - connect \builder_csrbank10_load2_w \main_libresocsim_timer_load_storage [23:16] - connect \builder_csrbank10_load1_w \main_libresocsim_timer_load_storage [15:8] - connect \builder_csrbank10_load0_w \main_libresocsim_timer_load_storage [7:0] - connect \builder_csrbank10_reload3_w \main_libresocsim_timer_reload_storage [31:24] - connect \builder_csrbank10_reload2_w \main_libresocsim_timer_reload_storage [23:16] - connect \builder_csrbank10_reload1_w \main_libresocsim_timer_reload_storage [15:8] - connect \builder_csrbank10_reload0_w \main_libresocsim_timer_reload_storage [7:0] - connect \builder_csrbank10_en0_w \main_libresocsim_timer_en_storage - connect \builder_csrbank10_update_value0_w \main_libresocsim_timer_update_value_storage - connect \builder_csrbank10_value3_w \main_libresocsim_timer_value_status [31:24] - connect \builder_csrbank10_value2_w \main_libresocsim_timer_value_status [23:16] - connect \builder_csrbank10_value1_w \main_libresocsim_timer_value_status [15:8] - connect \builder_csrbank10_value0_w \main_libresocsim_timer_value_status [7:0] - connect \main_libresocsim_timer_value_we \builder_csrbank10_value0_we - connect \builder_csrbank10_ev_enable0_w \main_libresocsim_timer_eventmanager_storage - connect \builder_csrbank11_sel $eq$ls180.v:6067$1956_Y - connect \main_libresocsim_uart_rxtx_r \builder_interface11_bank_bus_dat_w - connect \main_libresocsim_uart_rxtx_re $and$ls180.v:6069$1959_Y - connect \main_libresocsim_uart_rxtx_we $and$ls180.v:6070$1963_Y - connect \builder_csrbank11_txfull_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_txfull_re $and$ls180.v:6072$1966_Y - connect \builder_csrbank11_txfull_we $and$ls180.v:6073$1970_Y - connect \builder_csrbank11_rxempty_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_rxempty_re $and$ls180.v:6075$1973_Y - connect \builder_csrbank11_rxempty_we $and$ls180.v:6076$1977_Y - connect \main_libresocsim_uart_eventmanager_status_r \builder_interface11_bank_bus_dat_w [1:0] - connect \main_libresocsim_uart_eventmanager_status_re $and$ls180.v:6078$1980_Y - connect \main_libresocsim_uart_eventmanager_status_we $and$ls180.v:6079$1984_Y - connect \main_libresocsim_uart_eventmanager_pending_r \builder_interface11_bank_bus_dat_w [1:0] - connect \main_libresocsim_uart_eventmanager_pending_re $and$ls180.v:6081$1987_Y - connect \main_libresocsim_uart_eventmanager_pending_we $and$ls180.v:6082$1991_Y - connect \builder_csrbank11_ev_enable0_r \builder_interface11_bank_bus_dat_w [1:0] - connect \builder_csrbank11_ev_enable0_re $and$ls180.v:6084$1994_Y - connect \builder_csrbank11_ev_enable0_we $and$ls180.v:6085$1998_Y - connect \builder_csrbank11_txempty_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_txempty_re $and$ls180.v:6087$2001_Y - connect \builder_csrbank11_txempty_we $and$ls180.v:6088$2005_Y - connect \builder_csrbank11_rxfull_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_rxfull_re $and$ls180.v:6090$2008_Y - connect \builder_csrbank11_rxfull_we $and$ls180.v:6091$2012_Y - connect \builder_csrbank11_txfull_w \main_libresocsim_uart_txfull_status - connect \main_libresocsim_uart_txfull_we \builder_csrbank11_txfull_we - connect \builder_csrbank11_rxempty_w \main_libresocsim_uart_rxempty_status - connect \main_libresocsim_uart_rxempty_we \builder_csrbank11_rxempty_we - connect \builder_csrbank11_ev_enable0_w \main_libresocsim_uart_eventmanager_storage - connect \builder_csrbank11_txempty_w \main_libresocsim_uart_txempty_status - connect \main_libresocsim_uart_txempty_we \builder_csrbank11_txempty_we - connect \builder_csrbank11_rxfull_w \main_libresocsim_uart_rxfull_status - connect \main_libresocsim_uart_rxfull_we \builder_csrbank11_rxfull_we - connect \builder_csrbank12_sel $eq$ls180.v:6101$2013_Y - connect \builder_csrbank12_tuning_word3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_tuning_word3_re $and$ls180.v:6103$2016_Y - connect \builder_csrbank12_tuning_word3_we $and$ls180.v:6104$2020_Y - connect \builder_csrbank12_tuning_word2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_tuning_word2_re $and$ls180.v:6106$2023_Y - connect \builder_csrbank12_tuning_word2_we $and$ls180.v:6107$2027_Y - connect \builder_csrbank12_tuning_word1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_tuning_word1_re $and$ls180.v:6109$2030_Y - connect \builder_csrbank12_tuning_word1_we $and$ls180.v:6110$2034_Y - connect \builder_csrbank12_tuning_word0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_tuning_word0_re $and$ls180.v:6112$2037_Y - connect \builder_csrbank12_tuning_word0_we $and$ls180.v:6113$2041_Y - connect \builder_csrbank12_tuning_word3_w \main_libresocsim_storage [31:24] - connect \builder_csrbank12_tuning_word2_w \main_libresocsim_storage [23:16] - connect \builder_csrbank12_tuning_word1_w \main_libresocsim_storage [15:8] - connect \builder_csrbank12_tuning_word0_w \main_libresocsim_storage [7:0] - connect \builder_csr_interconnect_adr \builder_libresocsim_adr - connect \builder_csr_interconnect_we \builder_libresocsim_we - connect \builder_csr_interconnect_dat_w \builder_libresocsim_dat_w - connect \builder_libresocsim_dat_r \builder_csr_interconnect_dat_r - connect \builder_interface0_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface1_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface2_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface3_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface4_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface5_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface6_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface7_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface8_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface9_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface10_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface11_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface12_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface0_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface1_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface2_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface3_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface4_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface5_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface6_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface7_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface8_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface9_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface10_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface11_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface12_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface0_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface1_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface2_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface3_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface4_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface5_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface6_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface7_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface8_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface9_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface10_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface11_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_csr_interconnect_dat_r $or$ls180.v:6161$2053_Y - connect \main_libresocsim_rx \builder_multiregimpl0_regs1 - connect \sdrio_clk \sys_clk_1 - connect \sdrio_clk_1 \sys_clk_1 - connect \sdrio_clk_2 \sys_clk_1 - connect \sdrio_clk_3 \sys_clk_1 - connect \sdrio_clk_4 \sys_clk_1 - connect \sdrio_clk_5 \sys_clk_1 - connect \sdrio_clk_6 \sys_clk_1 - connect \sdrio_clk_7 \sys_clk_1 - connect \sdrio_clk_8 \sys_clk_1 - connect \sdrio_clk_9 \sys_clk_1 - connect \sdrio_clk_10 \sys_clk_1 - connect \sdrio_clk_11 \sys_clk_1 - connect \sdrio_clk_12 \sys_clk_1 - connect \sdrio_clk_13 \sys_clk_1 - connect \sdrio_clk_14 \sys_clk_1 - connect \sdrio_clk_15 \sys_clk_1 - connect \sdrio_clk_16 \sys_clk_1 - connect \sdrio_clk_17 \sys_clk_1 - connect \sdrio_clk_18 \sys_clk_1 - connect \sdrio_clk_19 \sys_clk_1 - connect \sdrio_clk_20 \sys_clk_1 - connect \sdrio_clk_21 \sys_clk_1 - connect \sdrio_clk_22 \sys_clk_1 - connect \sdrio_clk_23 \sys_clk_1 - connect \sdrio_clk_24 \sys_clk_1 - connect \sdrio_clk_25 \sys_clk_1 - connect \sdrio_clk_26 \sys_clk_1 - connect \sdrio_clk_27 \sys_clk_1 - connect \sdrio_clk_28 \sys_clk_1 - connect \sdrio_clk_29 \sys_clk_1 - connect \sdrio_clk_30 \sys_clk_1 - connect \sdrio_clk_31 \sys_clk_1 - connect \sdrio_clk_32 \sys_clk_1 - connect \sdrio_clk_33 \sys_clk_1 - connect \sdrio_clk_34 \sys_clk_1 - connect \sdrio_clk_35 \sys_clk_1 - connect \main_gpio_in_status \builder_multiregimpl1_regs1 - connect \main_gpio_out_status \builder_multiregimpl2_regs1 - connect \sdrio_clk_36 \sys_clk_1 - connect \sdrio_clk_37 \sys_clk_1 - connect \sdrio_clk_38 \sys_clk_1 - connect \sdrio_clk_39 \sys_clk_1 - connect \sdrio_clk_40 \sys_clk_1 - connect \sdrio_clk_41 \sys_clk_1 - connect \sdrio_clk_42 \sys_clk_1 - connect \sdrio_clk_43 \sys_clk_1 - connect \sdrio_clk_44 \sys_clk_1 - connect \sdrio_clk_45 \sys_clk_1 - connect \sdrio_clk_46 \sys_clk_1 - connect \sdrio_clk_47 \sys_clk_1 - connect \sdrio_clk_48 \sys_clk_1 - connect \sdrio_clk_49 \sys_clk_1 - connect \sdrio_clk_50 \sys_clk_1 - connect \sdrio_clk_51 \sys_clk_1 - connect \sdrio_clk_52 \sys_clk_1 - connect \sdrio_clk_53 \sys_clk_1 - connect \sdrio_clk_54 \sys_clk_1 - connect \sdrio_clk_55 \sys_clk_1 - connect \sdrio_clk_56 \sys_clk_1 - connect \sdrio_clk_57 \sys_clk_1 - connect \sdrio_clk_58 \sys_clk_1 - connect \sdrio_clk_59 \sys_clk_1 - connect \sdrio_clk_60 \sys_clk_1 - connect \sdrio_clk_61 \sys_clk_1 - connect \sdrio_clk_62 \sys_clk_1 - connect \sdrio_clk_63 \sys_clk_1 - connect \sdrio_clk_64 \sys_clk_1 - connect \sdrio_clk_65 \sys_clk_1 - connect \sdrio_clk_66 \sys_clk_1 - connect \sdrio_clk_67 \sys_clk_1 - connect \sdrio_clk_68 \sys_clk_1 - connect \sdrio_clk_69 \sys_clk_1 - connect \sdrio_clk_70 \sys_clk_1 - connect \sdrio_clk_71 \sys_clk_1 - connect \sdrio_clk_72 \sys_clk_1 - connect \sdrio_clk_73 \sys_clk_1 - connect \sdrio_clk_74 \sys_clk_1 - connect \sdrio_clk_75 \sys_clk_1 - connect \sdrio_clk_76 \sys_clk_1 - connect \sdrio_clk_77 \sys_clk_1 - connect \sdrio_clk_78 \sys_clk_1 - connect \sdrio_clk_79 \sys_clk_1 - connect \sdrio_clk_80 \sys_clk_1 - connect \sdrio_clk_81 \sys_clk_1 - connect \sdrio_clk_82 \sys_clk_1 - connect \sdrio_clk_83 \sys_clk_1 - connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:9380$2472_DATA - connect \main_libresocsim_uart_tx_fifo_wrport_dat_r \memdat - connect \main_libresocsim_uart_tx_fifo_rdport_dat_r \memdat_1 - connect \main_libresocsim_uart_rx_fifo_wrport_dat_r \memdat_2 - connect \main_libresocsim_uart_rx_fifo_rdport_dat_r \memdat_3 - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat_4 - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:9432$2493_DATA - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_5 - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:9446$2500_DATA - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_6 - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_4$ls180.v:9460$2507_DATA - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_7 - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_5$ls180.v:9474$2514_DATA - connect \libresocsim_sdblock2mem_fifo_wrport_dat_r \memdat_8 - connect \libresocsim_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:9488$2521_DATA - connect \libresocsim_sdmem2block_fifo_wrport_dat_r \memdat_9 - connect \libresocsim_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:9502$2528_DATA - connect \sdram_dq [0] $ternary$ls180.v:9566$2530_Y - connect \builder_inferedsdrtristate0__i \sdram_dq [0] - connect \sdram_dq [1] $ternary$ls180.v:9569$2531_Y - connect \builder_inferedsdrtristate1__i \sdram_dq [1] - connect \sdram_dq [2] $ternary$ls180.v:9572$2532_Y - connect \builder_inferedsdrtristate2__i \sdram_dq [2] - connect \sdram_dq [3] $ternary$ls180.v:9575$2533_Y - connect \builder_inferedsdrtristate3__i \sdram_dq [3] - connect \sdram_dq [4] $ternary$ls180.v:9578$2534_Y - connect \builder_inferedsdrtristate4__i \sdram_dq [4] - connect \sdram_dq [5] $ternary$ls180.v:9581$2535_Y - connect \builder_inferedsdrtristate5__i \sdram_dq [5] - connect \sdram_dq [6] $ternary$ls180.v:9584$2536_Y - connect \builder_inferedsdrtristate6__i \sdram_dq [6] - connect \sdram_dq [7] $ternary$ls180.v:9587$2537_Y - connect \builder_inferedsdrtristate7__i \sdram_dq [7] - connect \sdram_dq [8] $ternary$ls180.v:9590$2538_Y - connect \builder_inferedsdrtristate8__i \sdram_dq [8] - connect \sdram_dq [9] $ternary$ls180.v:9593$2539_Y - connect \builder_inferedsdrtristate9__i \sdram_dq [9] - connect \sdram_dq [10] $ternary$ls180.v:9596$2540_Y - connect \builder_inferedsdrtristate10__i \sdram_dq [10] - connect \sdram_dq [11] $ternary$ls180.v:9599$2541_Y - connect \builder_inferedsdrtristate11__i \sdram_dq [11] - connect \sdram_dq [12] $ternary$ls180.v:9602$2542_Y - connect \builder_inferedsdrtristate12__i \sdram_dq [12] - connect \sdram_dq [13] $ternary$ls180.v:9605$2543_Y - connect \builder_inferedsdrtristate13__i \sdram_dq [13] - connect \sdram_dq [14] $ternary$ls180.v:9608$2544_Y - connect \builder_inferedsdrtristate14__i \sdram_dq [14] - connect \sdram_dq [15] $ternary$ls180.v:9611$2545_Y - connect \builder_inferedsdrtristate15__i \sdram_dq [15] - connect \sdcard_cmd $ternary$ls180.v:9614$2546_Y - connect \builder_inferedsdrtristate16__i \sdcard_cmd - connect \sdcard_data [0] $ternary$ls180.v:9617$2547_Y - connect \builder_inferedsdrtristate17__i \sdcard_data [0] - connect \sdcard_data [1] $ternary$ls180.v:9620$2548_Y - connect \builder_inferedsdrtristate18__i \sdcard_data [1] - connect \sdcard_data [2] $ternary$ls180.v:9623$2549_Y - connect \builder_inferedsdrtristate19__i \sdcard_data [2] - connect \sdcard_data [3] $ternary$ls180.v:9626$2550_Y - connect \builder_inferedsdrtristate20__i \sdcard_data [3] -end -attribute \src "issuer_ls180.v:130593.1-130651.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.lsd_l" -attribute \generator "nMigen" -module \lsd_l - attribute \src "issuer_ls180.v:130594.7-130594.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:130639.3-130647.6" - wire $0\q_int$next[0:0]$6138 - attribute \src "issuer_ls180.v:130637.3-130638.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:130639.3-130647.6" - wire $1\q_int$next[0:0]$6139 - attribute \src "issuer_ls180.v:130616.7-130616.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:130629.17-130629.96" - wire $and$issuer_ls180.v:130629$6128_Y - attribute \src "issuer_ls180.v:130634.17-130634.96" - wire $and$issuer_ls180.v:130634$6133_Y - attribute \src "issuer_ls180.v:130631.18-130631.93" - wire $not$issuer_ls180.v:130631$6130_Y - attribute \src "issuer_ls180.v:130633.17-130633.92" - wire $not$issuer_ls180.v:130633$6132_Y - attribute \src "issuer_ls180.v:130636.17-130636.92" - wire $not$issuer_ls180.v:130636$6135_Y - attribute \src "issuer_ls180.v:130630.18-130630.98" - wire $or$issuer_ls180.v:130630$6129_Y - attribute \src "issuer_ls180.v:130632.18-130632.99" - wire $or$issuer_ls180.v:130632$6131_Y - attribute \src "issuer_ls180.v:130635.17-130635.97" - wire $or$issuer_ls180.v:130635$6134_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:130594.7-130594.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:130629$6128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:130629$6128_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:130634$6133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:130634$6133_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:130631$6130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_lsd - connect \Y $not$issuer_ls180.v:130631$6130_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:130633$6132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_lsd - connect \Y $not$issuer_ls180.v:130633$6132_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:130636$6135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_lsd - connect \Y $not$issuer_ls180.v:130636$6135_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:130630$6129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_lsd - connect \Y $or$issuer_ls180.v:130630$6129_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:130632$6131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_lsd - connect \B \q_int - connect \Y $or$issuer_ls180.v:130632$6131_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:130635$6134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_lsd - connect \Y $or$issuer_ls180.v:130635$6134_Y - end - attribute \src "issuer_ls180.v:130594.7-130594.20" - process $proc$issuer_ls180.v:130594$6140 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:130616.7-130616.19" - process $proc$issuer_ls180.v:130616$6141 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:130637.3-130638.27" - process $proc$issuer_ls180.v:130637$6136 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:130639.3-130647.6" - process $proc$issuer_ls180.v:130639$6137 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$6138 $1\q_int$next[0:0]$6139 - attribute \src "issuer_ls180.v:130640.5-130640.29" - switch \initial - attribute \src "issuer_ls180.v:130640.9-130640.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$6139 1'0 - case - assign $1\q_int$next[0:0]$6139 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$6138 - end - connect \$9 $and$issuer_ls180.v:130629$6128_Y - connect \$11 $or$issuer_ls180.v:130630$6129_Y - connect \$13 $not$issuer_ls180.v:130631$6130_Y - connect \$15 $or$issuer_ls180.v:130632$6131_Y - connect \$1 $not$issuer_ls180.v:130633$6132_Y - connect \$3 $and$issuer_ls180.v:130634$6133_Y - connect \$5 $or$issuer_ls180.v:130635$6134_Y - connect \$7 $not$issuer_ls180.v:130636$6135_Y - connect \qlq_lsd \$15 - connect \qn_lsd \$13 - connect \q_lsd \$11 -end -attribute \src "issuer_ls180.v:130655.1-131121.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.lsmem" -attribute \generator "nMigen" -module \lsmem - attribute \src "issuer_ls180.v:131004.3-131024.6" - wire width 45 $0\dbus__adr$next[44:0]$6222 - attribute \src "issuer_ls180.v:130890.3-130891.35" - wire width 45 $0\dbus__adr[44:0] - attribute \src "issuer_ls180.v:130900.3-130922.6" - wire $0\dbus__cyc$next[0:0]$6201 - attribute \src "issuer_ls180.v:130898.3-130899.35" - wire $0\dbus__cyc[0:0] - attribute \src "issuer_ls180.v:131046.3-131066.6" - wire width 64 $0\dbus__dat_w$next[63:0]$6230 - attribute \src "issuer_ls180.v:130886.3-130887.39" - wire width 64 $0\dbus__dat_w[63:0] - attribute \src "issuer_ls180.v:130958.3-130983.6" - wire width 8 $0\dbus__sel$next[7:0]$6212 - attribute \src "issuer_ls180.v:130894.3-130895.35" - wire width 8 $0\dbus__sel[7:0] - attribute \src "issuer_ls180.v:130923.3-130945.6" - wire $0\dbus__stb$next[0:0]$6206 - attribute \src "issuer_ls180.v:130896.3-130897.35" - wire $0\dbus__stb[0:0] - attribute \src "issuer_ls180.v:131025.3-131045.6" - wire $0\dbus__we$next[0:0]$6226 - attribute \src "issuer_ls180.v:130888.3-130889.33" - wire $0\dbus__we[0:0] - attribute \src "issuer_ls180.v:130656.7-130656.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:131103.3-131117.6" - wire width 45 $0\m_badaddr_o$next[44:0]$6242 - attribute \src "issuer_ls180.v:130880.3-130881.39" - wire width 45 $0\m_badaddr_o[44:0] - attribute \src "issuer_ls180.v:130946.3-130957.6" - wire $0\m_busy_o[0:0] - attribute \src "issuer_ls180.v:130984.3-131003.6" - wire width 64 $0\m_ld_data_o$next[63:0]$6217 - attribute \src "issuer_ls180.v:130892.3-130893.39" - wire width 64 $0\m_ld_data_o[63:0] - attribute \src "issuer_ls180.v:131067.3-131084.6" - wire $0\m_load_err_o$next[0:0]$6234 - attribute \src "issuer_ls180.v:130884.3-130885.41" - wire $0\m_load_err_o[0:0] - attribute \src "issuer_ls180.v:131085.3-131102.6" - wire $0\m_store_err_o$next[0:0]$6238 - attribute \src "issuer_ls180.v:130882.3-130883.43" - wire $0\m_store_err_o[0:0] - attribute \src "issuer_ls180.v:131004.3-131024.6" - wire width 45 $1\dbus__adr$next[44:0]$6223 - attribute \src "issuer_ls180.v:130761.14-130761.42" - wire width 45 $1\dbus__adr[44:0] - attribute \src "issuer_ls180.v:130900.3-130922.6" - wire $1\dbus__cyc$next[0:0]$6202 - attribute \src "issuer_ls180.v:130766.7-130766.23" - wire $1\dbus__cyc[0:0] - attribute \src "issuer_ls180.v:131046.3-131066.6" - wire width 64 $1\dbus__dat_w$next[63:0]$6231 - attribute \src "issuer_ls180.v:130773.14-130773.48" - wire width 64 $1\dbus__dat_w[63:0] - attribute \src "issuer_ls180.v:130958.3-130983.6" - wire width 8 $1\dbus__sel$next[7:0]$6213 - attribute \src "issuer_ls180.v:130780.13-130780.30" - wire width 8 $1\dbus__sel[7:0] - attribute \src "issuer_ls180.v:130923.3-130945.6" - wire $1\dbus__stb$next[0:0]$6207 - attribute \src "issuer_ls180.v:130785.7-130785.23" - wire $1\dbus__stb[0:0] - attribute \src "issuer_ls180.v:131025.3-131045.6" - wire $1\dbus__we$next[0:0]$6227 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"issuer_ls180.v:130900.3-130922.6" - wire $2\dbus__cyc$next[0:0]$6203 - attribute \src "issuer_ls180.v:131046.3-131066.6" - wire width 64 $2\dbus__dat_w$next[63:0]$6232 - attribute \src "issuer_ls180.v:130958.3-130983.6" - wire width 8 $2\dbus__sel$next[7:0]$6214 - attribute \src "issuer_ls180.v:130923.3-130945.6" - wire $2\dbus__stb$next[0:0]$6208 - attribute \src "issuer_ls180.v:131025.3-131045.6" - wire $2\dbus__we$next[0:0]$6228 - attribute \src "issuer_ls180.v:131103.3-131117.6" - wire width 45 $2\m_badaddr_o$next[44:0]$6244 - attribute \src "issuer_ls180.v:130984.3-131003.6" - wire width 64 $2\m_ld_data_o$next[63:0]$6219 - attribute \src "issuer_ls180.v:131067.3-131084.6" - wire $2\m_load_err_o$next[0:0]$6236 - attribute \src "issuer_ls180.v:131085.3-131102.6" - wire $2\m_store_err_o$next[0:0]$6240 - attribute \src "issuer_ls180.v:130900.3-130922.6" - wire $3\dbus__cyc$next[0:0]$6204 - attribute \src "issuer_ls180.v:130958.3-130983.6" - wire width 8 $3\dbus__sel$next[7:0]$6215 - attribute \src "issuer_ls180.v:130923.3-130945.6" - wire $3\dbus__stb$next[0:0]$6209 - attribute \src "issuer_ls180.v:130984.3-131003.6" - wire width 64 $3\m_ld_data_o$next[63:0]$6220 - attribute \src "issuer_ls180.v:130836.18-130836.116" - wire $and$issuer_ls180.v:130836$6146_Y - attribute \src "issuer_ls180.v:130839.18-130839.111" - wire $and$issuer_ls180.v:130839$6149_Y - attribute \src "issuer_ls180.v:130844.18-130844.116" - wire $and$issuer_ls180.v:130844$6154_Y - attribute \src "issuer_ls180.v:130846.18-130846.111" - wire $and$issuer_ls180.v:130846$6156_Y - attribute \src "issuer_ls180.v:130848.17-130848.114" - wire $and$issuer_ls180.v:130848$6158_Y - attribute \src "issuer_ls180.v:130852.18-130852.116" - wire $and$issuer_ls180.v:130852$6162_Y - attribute \src "issuer_ls180.v:130854.18-130854.111" - wire $and$issuer_ls180.v:130854$6164_Y - attribute \src "issuer_ls180.v:130860.18-130860.116" - wire $and$issuer_ls180.v:130860$6170_Y - attribute \src "issuer_ls180.v:130862.18-130862.111" - wire $and$issuer_ls180.v:130862$6172_Y - attribute \src "issuer_ls180.v:130864.18-130864.116" - wire $and$issuer_ls180.v:130864$6174_Y - attribute \src "issuer_ls180.v:130866.18-130866.111" - wire $and$issuer_ls180.v:130866$6176_Y - attribute \src "issuer_ls180.v:130868.18-130868.116" - wire $and$issuer_ls180.v:130868$6178_Y - attribute \src "issuer_ls180.v:130870.17-130870.108" - wire $and$issuer_ls180.v:130870$6180_Y - attribute \src "issuer_ls180.v:130871.18-130871.111" - wire $and$issuer_ls180.v:130871$6181_Y - attribute \src "issuer_ls180.v:130872.18-130872.120" - wire $and$issuer_ls180.v:130872$6182_Y - attribute \src "issuer_ls180.v:130875.18-130875.120" - wire $and$issuer_ls180.v:130875$6185_Y - attribute \src "issuer_ls180.v:130877.18-130877.120" - wire $and$issuer_ls180.v:130877$6187_Y - attribute \src "issuer_ls180.v:130833.18-130833.110" - wire $not$issuer_ls180.v:130833$6143_Y - attribute \src "issuer_ls180.v:130838.18-130838.110" - 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attribute \src "issuer_ls180.v:130874.18-130874.109" - wire $not$issuer_ls180.v:130874$6184_Y - attribute \src "issuer_ls180.v:130876.18-130876.110" - wire $not$issuer_ls180.v:130876$6186_Y - attribute \src "issuer_ls180.v:130878.18-130878.110" - wire $not$issuer_ls180.v:130878$6188_Y - attribute \src "issuer_ls180.v:130832.17-130832.119" - wire $or$issuer_ls180.v:130832$6142_Y - attribute \src "issuer_ls180.v:130834.18-130834.110" - wire $or$issuer_ls180.v:130834$6144_Y - attribute \src "issuer_ls180.v:130835.18-130835.114" - wire $or$issuer_ls180.v:130835$6145_Y - attribute \src "issuer_ls180.v:130837.17-130837.113" - wire $or$issuer_ls180.v:130837$6147_Y - attribute \src "issuer_ls180.v:130840.18-130840.120" - wire $or$issuer_ls180.v:130840$6150_Y - attribute \src "issuer_ls180.v:130842.18-130842.111" - wire $or$issuer_ls180.v:130842$6152_Y - attribute \src "issuer_ls180.v:130843.18-130843.114" - wire $or$issuer_ls180.v:130843$6153_Y - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - wire \$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - wire \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire \$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire \$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire \$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire \$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire \$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire \$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" - wire \$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" - wire \$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:133" - wire \$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" - wire \$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" - wire \$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" - wire \$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" - wire \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:145" - wire \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 20 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 12 \dbus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 output 17 \dbus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 \dbus__adr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 11 \dbus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire \dbus__cyc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 input 16 \dbus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 output 19 \dbus__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 \dbus__dat_w$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 13 \dbus__err - attribute \src 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connect \A \x_ld_i - connect \B \x_st_i - connect \Y $or$issuer_ls180.v:130867$6177_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:145" - cell $or $or$issuer_ls180.v:130879$6189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_load_err_o - connect \B \m_store_err_o - connect \Y $or$issuer_ls180.v:130879$6189_Y - end - attribute \src "issuer_ls180.v:130656.7-130656.20" - process $proc$issuer_ls180.v:130656$6245 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:130761.14-130761.42" - process $proc$issuer_ls180.v:130761$6246 - assign { } { } - assign $1\dbus__adr[44:0] 45'000000000000000000000000000000000000000000000 - sync always - sync init - update \dbus__adr $1\dbus__adr[44:0] - end - attribute \src "issuer_ls180.v:130766.7-130766.23" - process $proc$issuer_ls180.v:130766$6247 - assign { } { } - assign $1\dbus__cyc[0:0] 1'0 - sync always - sync init - update \dbus__cyc $1\dbus__cyc[0:0] - end - attribute \src "issuer_ls180.v:130773.14-130773.48" - process $proc$issuer_ls180.v:130773$6248 - assign { } { } - assign $1\dbus__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dbus__dat_w $1\dbus__dat_w[63:0] - end - attribute \src "issuer_ls180.v:130780.13-130780.30" - process $proc$issuer_ls180.v:130780$6249 - assign { } { } - assign $1\dbus__sel[7:0] 8'00000000 - sync always - sync init - update \dbus__sel $1\dbus__sel[7:0] - end - attribute \src "issuer_ls180.v:130785.7-130785.23" - process $proc$issuer_ls180.v:130785$6250 - assign { } { } - assign $1\dbus__stb[0:0] 1'0 - sync always - sync init - update \dbus__stb $1\dbus__stb[0:0] - end - attribute \src "issuer_ls180.v:130790.7-130790.22" - process $proc$issuer_ls180.v:130790$6251 - assign { } { } - assign $1\dbus__we[0:0] 1'0 - sync always - sync init - update \dbus__we $1\dbus__we[0:0] - end - attribute \src "issuer_ls180.v:130794.14-130794.44" - process $proc$issuer_ls180.v:130794$6252 - assign { } { } - assign $1\m_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 - sync always - sync init - update \m_badaddr_o $1\m_badaddr_o[44:0] - end - attribute \src "issuer_ls180.v:130801.14-130801.48" - process $proc$issuer_ls180.v:130801$6253 - assign { } { } - assign $1\m_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \m_ld_data_o $1\m_ld_data_o[63:0] - end - attribute \src "issuer_ls180.v:130805.7-130805.26" - process $proc$issuer_ls180.v:130805$6254 - assign { } { } - assign $1\m_load_err_o[0:0] 1'0 - sync always - sync init - update \m_load_err_o $1\m_load_err_o[0:0] - end - attribute \src "issuer_ls180.v:130811.7-130811.27" - process $proc$issuer_ls180.v:130811$6255 - assign { } { } - assign $1\m_store_err_o[0:0] 1'0 - sync always - sync init - update \m_store_err_o $1\m_store_err_o[0:0] - end - attribute \src "issuer_ls180.v:130880.3-130881.39" - process $proc$issuer_ls180.v:130880$6190 - assign { } { } - assign $0\m_badaddr_o[44:0] \m_badaddr_o$next - sync posedge \coresync_clk - update \m_badaddr_o $0\m_badaddr_o[44:0] - end - attribute \src "issuer_ls180.v:130882.3-130883.43" - process $proc$issuer_ls180.v:130882$6191 - assign { } { } - assign $0\m_store_err_o[0:0] \m_store_err_o$next - sync posedge \coresync_clk - update \m_store_err_o $0\m_store_err_o[0:0] - end - attribute \src "issuer_ls180.v:130884.3-130885.41" - process $proc$issuer_ls180.v:130884$6192 - assign { } { } - assign $0\m_load_err_o[0:0] \m_load_err_o$next - sync posedge \coresync_clk - update \m_load_err_o $0\m_load_err_o[0:0] - end - attribute \src "issuer_ls180.v:130886.3-130887.39" - process $proc$issuer_ls180.v:130886$6193 - assign { } { } - assign $0\dbus__dat_w[63:0] \dbus__dat_w$next - sync posedge \coresync_clk - update \dbus__dat_w $0\dbus__dat_w[63:0] - end - attribute \src "issuer_ls180.v:130888.3-130889.33" - process $proc$issuer_ls180.v:130888$6194 - assign { } { } - assign $0\dbus__we[0:0] \dbus__we$next - sync posedge \coresync_clk - update \dbus__we $0\dbus__we[0:0] - end - attribute \src "issuer_ls180.v:130890.3-130891.35" - process $proc$issuer_ls180.v:130890$6195 - assign { } { } - assign $0\dbus__adr[44:0] \dbus__adr$next - sync posedge \coresync_clk - update \dbus__adr $0\dbus__adr[44:0] - end - attribute \src "issuer_ls180.v:130892.3-130893.39" - process $proc$issuer_ls180.v:130892$6196 - assign { } { } - assign $0\m_ld_data_o[63:0] \m_ld_data_o$next - sync posedge \coresync_clk - update \m_ld_data_o $0\m_ld_data_o[63:0] - end - attribute \src "issuer_ls180.v:130894.3-130895.35" - process $proc$issuer_ls180.v:130894$6197 - assign { } { } - assign $0\dbus__sel[7:0] \dbus__sel$next - sync posedge \coresync_clk - update \dbus__sel $0\dbus__sel[7:0] - end - attribute \src "issuer_ls180.v:130896.3-130897.35" - process $proc$issuer_ls180.v:130896$6198 - assign { } { } - assign $0\dbus__stb[0:0] \dbus__stb$next - sync posedge \coresync_clk - update \dbus__stb $0\dbus__stb[0:0] - end - attribute \src "issuer_ls180.v:130898.3-130899.35" - process $proc$issuer_ls180.v:130898$6199 - assign { } { } - assign $0\dbus__cyc[0:0] \dbus__cyc$next - sync posedge \coresync_clk - update \dbus__cyc $0\dbus__cyc[0:0] - end - attribute \src "issuer_ls180.v:130900.3-130922.6" - process $proc$issuer_ls180.v:130900$6200 - assign { } { } - assign { } { } - assign { } { } - assign $0\dbus__cyc$next[0:0]$6201 $3\dbus__cyc$next[0:0]$6204 - attribute \src "issuer_ls180.v:130901.5-130901.29" - switch \initial - attribute \src "issuer_ls180.v:130901.9-130901.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - switch { \$7 \dbus__cyc } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\dbus__cyc$next[0:0]$6202 $2\dbus__cyc$next[0:0]$6203 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - switch \$13 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dbus__cyc$next[0:0]$6203 1'0 - case - assign $2\dbus__cyc$next[0:0]$6203 \dbus__cyc - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\dbus__cyc$next[0:0]$6202 1'1 - case - assign $1\dbus__cyc$next[0:0]$6202 \dbus__cyc - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dbus__cyc$next[0:0]$6204 1'0 - case - assign $3\dbus__cyc$next[0:0]$6204 $1\dbus__cyc$next[0:0]$6202 - end - sync always - update \dbus__cyc$next $0\dbus__cyc$next[0:0]$6201 - end - attribute \src "issuer_ls180.v:130923.3-130945.6" - process $proc$issuer_ls180.v:130923$6205 - assign { } { } - assign { } { } - assign { } { } - assign $0\dbus__stb$next[0:0]$6206 $3\dbus__stb$next[0:0]$6209 - attribute \src "issuer_ls180.v:130924.5-130924.29" - switch \initial - attribute \src "issuer_ls180.v:130924.9-130924.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - switch { \$21 \dbus__cyc } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\dbus__stb$next[0:0]$6207 $2\dbus__stb$next[0:0]$6208 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - switch \$27 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dbus__stb$next[0:0]$6208 1'0 - case - assign $2\dbus__stb$next[0:0]$6208 \dbus__stb - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\dbus__stb$next[0:0]$6207 1'1 - case - assign $1\dbus__stb$next[0:0]$6207 \dbus__stb - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dbus__stb$next[0:0]$6209 1'0 - case - assign $3\dbus__stb$next[0:0]$6209 $1\dbus__stb$next[0:0]$6207 - end - sync always - update \dbus__stb$next $0\dbus__stb$next[0:0]$6206 - end - attribute \src "issuer_ls180.v:130946.3-130957.6" - process $proc$issuer_ls180.v:130946$6210 - assign { } { } - assign $0\m_busy_o[0:0] $1\m_busy_o[0:0] - attribute \src "issuer_ls180.v:130947.5-130947.29" - switch \initial - attribute \src "issuer_ls180.v:130947.9-130947.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:145" - switch \$95 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\m_busy_o[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\m_busy_o[0:0] \dbus__cyc - end - sync always - update \m_busy_o $0\m_busy_o[0:0] - end - attribute \src "issuer_ls180.v:130958.3-130983.6" - process $proc$issuer_ls180.v:130958$6211 - assign { } { } - assign { } { } - assign { } { } - assign $0\dbus__sel$next[7:0]$6212 $3\dbus__sel$next[7:0]$6215 - attribute \src "issuer_ls180.v:130959.5-130959.29" - switch \initial - attribute \src "issuer_ls180.v:130959.9-130959.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - switch { \$35 \dbus__cyc } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\dbus__sel$next[7:0]$6213 $2\dbus__sel$next[7:0]$6214 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - switch \$41 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dbus__sel$next[7:0]$6214 8'00000000 - case - assign $2\dbus__sel$next[7:0]$6214 \dbus__sel - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\dbus__sel$next[7:0]$6213 \x_mask_i - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\dbus__sel$next[7:0]$6213 8'00000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dbus__sel$next[7:0]$6215 8'00000000 - case - assign $3\dbus__sel$next[7:0]$6215 $1\dbus__sel$next[7:0]$6213 - end - sync always - update \dbus__sel$next $0\dbus__sel$next[7:0]$6212 - end - attribute \src "issuer_ls180.v:130984.3-131003.6" - process $proc$issuer_ls180.v:130984$6216 - assign { } { } - assign { } { } - assign { } { } - assign $0\m_ld_data_o$next[63:0]$6217 $3\m_ld_data_o$next[63:0]$6220 - attribute \src "issuer_ls180.v:130985.5-130985.29" - switch \initial - attribute \src "issuer_ls180.v:130985.9-130985.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - switch { \$49 \dbus__cyc } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\m_ld_data_o$next[63:0]$6218 $2\m_ld_data_o$next[63:0]$6219 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - switch \$55 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\m_ld_data_o$next[63:0]$6219 \dbus__dat_r - case - assign $2\m_ld_data_o$next[63:0]$6219 \m_ld_data_o - end - case - assign $1\m_ld_data_o$next[63:0]$6218 \m_ld_data_o - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\m_ld_data_o$next[63:0]$6220 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\m_ld_data_o$next[63:0]$6220 $1\m_ld_data_o$next[63:0]$6218 - end - sync always - update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$6217 - end - attribute \src "issuer_ls180.v:131004.3-131024.6" - process $proc$issuer_ls180.v:131004$6221 - assign { } { } - assign { } { } - assign { } { } - assign $0\dbus__adr$next[44:0]$6222 $2\dbus__adr$next[44:0]$6224 - attribute \src "issuer_ls180.v:131005.5-131005.29" - switch \initial - attribute \src "issuer_ls180.v:131005.9-131005.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - switch { \$63 \dbus__cyc } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign $1\dbus__adr$next[44:0]$6223 \dbus__adr - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\dbus__adr$next[44:0]$6223 \x_addr_i [47:3] - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\dbus__adr$next[44:0]$6223 45'000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dbus__adr$next[44:0]$6224 45'000000000000000000000000000000000000000000000 - case - assign $2\dbus__adr$next[44:0]$6224 $1\dbus__adr$next[44:0]$6223 - end - sync always - update \dbus__adr$next $0\dbus__adr$next[44:0]$6222 - end - attribute \src "issuer_ls180.v:131025.3-131045.6" - process $proc$issuer_ls180.v:131025$6225 - assign { } { } - assign { } { } - assign { } { } - assign $0\dbus__we$next[0:0]$6226 $2\dbus__we$next[0:0]$6228 - attribute \src "issuer_ls180.v:131026.5-131026.29" - switch \initial - attribute \src "issuer_ls180.v:131026.9-131026.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - switch { \$71 \dbus__cyc } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign $1\dbus__we$next[0:0]$6227 \dbus__we - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\dbus__we$next[0:0]$6227 \x_st_i - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\dbus__we$next[0:0]$6227 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dbus__we$next[0:0]$6228 1'0 - case - assign $2\dbus__we$next[0:0]$6228 $1\dbus__we$next[0:0]$6227 - end - sync always - update \dbus__we$next $0\dbus__we$next[0:0]$6226 - end - attribute \src "issuer_ls180.v:131046.3-131066.6" - process $proc$issuer_ls180.v:131046$6229 - assign { } { } - assign { } { } - assign { } { } - assign $0\dbus__dat_w$next[63:0]$6230 $2\dbus__dat_w$next[63:0]$6232 - attribute \src "issuer_ls180.v:131047.5-131047.29" - switch \initial - attribute \src "issuer_ls180.v:131047.9-131047.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - switch { \$79 \dbus__cyc } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign $1\dbus__dat_w$next[63:0]$6231 \dbus__dat_w - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\dbus__dat_w$next[63:0]$6231 \x_st_data_i - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\dbus__dat_w$next[63:0]$6231 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dbus__dat_w$next[63:0]$6232 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\dbus__dat_w$next[63:0]$6232 $1\dbus__dat_w$next[63:0]$6231 - end - sync always - update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$6230 - end - attribute \src "issuer_ls180.v:131067.3-131084.6" - process $proc$issuer_ls180.v:131067$6233 - assign { } { } - assign { } { } - assign { } { } - assign $0\m_load_err_o$next[0:0]$6234 $2\m_load_err_o$next[0:0]$6236 - attribute \src "issuer_ls180.v:131068.5-131068.29" - switch \initial - attribute \src "issuer_ls180.v:131068.9-131068.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" - switch { \$83 \$81 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\m_load_err_o$next[0:0]$6235 \$85 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\m_load_err_o$next[0:0]$6235 1'0 - case - assign $1\m_load_err_o$next[0:0]$6235 \m_load_err_o - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\m_load_err_o$next[0:0]$6236 1'0 - case - assign $2\m_load_err_o$next[0:0]$6236 $1\m_load_err_o$next[0:0]$6235 - end - sync always - update \m_load_err_o$next $0\m_load_err_o$next[0:0]$6234 - end - attribute \src "issuer_ls180.v:131085.3-131102.6" - process $proc$issuer_ls180.v:131085$6237 - assign { } { } - assign { } { } - assign { } { } - assign $0\m_store_err_o$next[0:0]$6238 $2\m_store_err_o$next[0:0]$6240 - attribute \src "issuer_ls180.v:131086.5-131086.29" - switch \initial - attribute \src "issuer_ls180.v:131086.9-131086.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" - switch { \$89 \$87 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\m_store_err_o$next[0:0]$6239 \dbus__we - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\m_store_err_o$next[0:0]$6239 1'0 - case - assign $1\m_store_err_o$next[0:0]$6239 \m_store_err_o - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\m_store_err_o$next[0:0]$6240 1'0 - case - assign $2\m_store_err_o$next[0:0]$6240 $1\m_store_err_o$next[0:0]$6239 - end - sync always - update \m_store_err_o$next $0\m_store_err_o$next[0:0]$6238 - end - attribute \src "issuer_ls180.v:131103.3-131117.6" - process $proc$issuer_ls180.v:131103$6241 - assign { } { } - assign { } { } - assign { } { } - assign $0\m_badaddr_o$next[44:0]$6242 $2\m_badaddr_o$next[44:0]$6244 - attribute \src "issuer_ls180.v:131104.5-131104.29" - switch \initial - attribute \src "issuer_ls180.v:131104.9-131104.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" - switch { \$93 \$91 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\m_badaddr_o$next[44:0]$6243 \dbus__adr - case - assign $1\m_badaddr_o$next[44:0]$6243 \m_badaddr_o - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\m_badaddr_o$next[44:0]$6244 45'000000000000000000000000000000000000000000000 - case - assign $2\m_badaddr_o$next[44:0]$6244 $1\m_badaddr_o$next[44:0]$6243 - end - sync always - update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$6242 - end - connect \$9 $or$issuer_ls180.v:130832$6142_Y - connect \$11 $not$issuer_ls180.v:130833$6143_Y - connect \$13 $or$issuer_ls180.v:130834$6144_Y - connect \$15 $or$issuer_ls180.v:130835$6145_Y - connect \$17 $and$issuer_ls180.v:130836$6146_Y - connect \$1 $or$issuer_ls180.v:130837$6147_Y - connect \$19 $not$issuer_ls180.v:130838$6148_Y - connect \$21 $and$issuer_ls180.v:130839$6149_Y - connect \$23 $or$issuer_ls180.v:130840$6150_Y - connect \$25 $not$issuer_ls180.v:130841$6151_Y - connect \$27 $or$issuer_ls180.v:130842$6152_Y - connect \$29 $or$issuer_ls180.v:130843$6153_Y - connect \$31 $and$issuer_ls180.v:130844$6154_Y - connect \$33 $not$issuer_ls180.v:130845$6155_Y - connect \$35 $and$issuer_ls180.v:130846$6156_Y - connect \$37 $or$issuer_ls180.v:130847$6157_Y - connect \$3 $and$issuer_ls180.v:130848$6158_Y - connect \$39 $not$issuer_ls180.v:130849$6159_Y - connect \$41 $or$issuer_ls180.v:130850$6160_Y - connect \$43 $or$issuer_ls180.v:130851$6161_Y - connect \$45 $and$issuer_ls180.v:130852$6162_Y - connect \$47 $not$issuer_ls180.v:130853$6163_Y - connect \$49 $and$issuer_ls180.v:130854$6164_Y - connect \$51 $or$issuer_ls180.v:130855$6165_Y - connect \$53 $not$issuer_ls180.v:130856$6166_Y - connect \$55 $or$issuer_ls180.v:130857$6167_Y - connect \$57 $or$issuer_ls180.v:130858$6168_Y - connect \$5 $not$issuer_ls180.v:130859$6169_Y - connect \$59 $and$issuer_ls180.v:130860$6170_Y - connect \$61 $not$issuer_ls180.v:130861$6171_Y - connect \$63 $and$issuer_ls180.v:130862$6172_Y - connect \$65 $or$issuer_ls180.v:130863$6173_Y - connect \$67 $and$issuer_ls180.v:130864$6174_Y - connect \$69 $not$issuer_ls180.v:130865$6175_Y - connect \$71 $and$issuer_ls180.v:130866$6176_Y - connect \$73 $or$issuer_ls180.v:130867$6177_Y - connect \$75 $and$issuer_ls180.v:130868$6178_Y - connect \$77 $not$issuer_ls180.v:130869$6179_Y - connect \$7 $and$issuer_ls180.v:130870$6180_Y - connect \$79 $and$issuer_ls180.v:130871$6181_Y - connect \$81 $and$issuer_ls180.v:130872$6182_Y - connect \$83 $not$issuer_ls180.v:130873$6183_Y - connect \$85 $not$issuer_ls180.v:130874$6184_Y - connect \$87 $and$issuer_ls180.v:130875$6185_Y - connect \$89 $not$issuer_ls180.v:130876$6186_Y - connect \$91 $and$issuer_ls180.v:130877$6187_Y - connect \$93 $not$issuer_ls180.v:130878$6188_Y - connect \$95 $or$issuer_ls180.v:130879$6189_Y - connect \x_stall_i 1'0 - connect \m_stall_i 1'0 - connect \x_busy_o \dbus__cyc -end -attribute \src "issuer_ls180.v:131125.1-132080.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1.main" -attribute \generator "nMigen" -module \main - attribute \src "issuer_ls180.v:131652.3-131674.6" - wire width 64 $0\a_i[63:0] - attribute \src "issuer_ls180.v:131751.3-131777.6" - wire $0\a_lt[0:0] - attribute \src "issuer_ls180.v:132032.3-132042.6" - wire width 64 $0\a_n[63:0] - attribute \src "issuer_ls180.v:132002.3-132011.6" - wire width 66 $0\add_a[65:0] - attribute \src "issuer_ls180.v:132012.3-132021.6" - wire width 66 $0\add_b[65:0] - attribute \src "issuer_ls180.v:132022.3-132031.6" - wire width 66 $0\add_o[65:0] - attribute \src "issuer_ls180.v:131890.3-131912.6" - wire width 64 $0\b_i[63:0] - attribute \src "issuer_ls180.v:131876.3-131889.6" - wire width 2 $0\ca[1:0] - attribute \src "issuer_ls180.v:132043.3-132053.6" - wire $0\carry_32[0:0] - attribute \src "issuer_ls180.v:132054.3-132064.6" - wire $0\carry_64[0:0] - attribute \src "issuer_ls180.v:131778.3-131803.6" - wire width 4 $0\cr_a[3:0] - attribute \src "issuer_ls180.v:131804.3-131818.6" - wire $0\cr_a_ok[0:0] - attribute \src "issuer_ls180.v:131982.3-132001.6" - wire width 8 $0\eqs[7:0] - attribute \src "issuer_ls180.v:131126.7-131126.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:131642.3-131651.6" - wire $0\is_32bit[0:0] - attribute \src "issuer_ls180.v:131713.3-131731.6" - wire $0\msb_a[0:0] - attribute \src "issuer_ls180.v:131732.3-131750.6" - wire $0\msb_b[0:0] - attribute \src "issuer_ls180.v:131819.3-131856.6" - wire width 64 $0\o[63:0] - attribute \src "issuer_ls180.v:131857.3-131875.6" - wire $0\o_ok[0:0] - attribute \src "issuer_ls180.v:131935.3-131948.6" - wire width 2 $0\ov[1:0] - attribute \src "issuer_ls180.v:131971.3-131981.6" - wire width 8 $0\src1[7:0] - attribute \src "issuer_ls180.v:131686.3-131712.6" - wire width 5 $0\tval[4:0] - attribute \src "issuer_ls180.v:131913.3-131923.6" - wire width 2 $0\xer_ca$20[1:0]$6331 - attribute \src "issuer_ls180.v:131924.3-131934.6" - wire $0\xer_ca_ok[0:0] - attribute \src "issuer_ls180.v:131949.3-131959.6" - wire width 2 $0\xer_ov[1:0] - attribute \src "issuer_ls180.v:131960.3-131970.6" - wire $0\xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:131675.3-131685.6" - wire $0\zerohi[0:0] - attribute \src "issuer_ls180.v:132065.3-132075.6" - wire $0\zerolo[0:0] - attribute \src "issuer_ls180.v:131652.3-131674.6" - wire width 64 $1\a_i[63:0] - attribute \src "issuer_ls180.v:131751.3-131777.6" - wire $1\a_lt[0:0] - attribute \src "issuer_ls180.v:132032.3-132042.6" - wire width 64 $1\a_n[63:0] - attribute \src "issuer_ls180.v:132002.3-132011.6" - wire width 66 $1\add_a[65:0] - attribute \src "issuer_ls180.v:132012.3-132021.6" - wire width 66 $1\add_b[65:0] - attribute \src "issuer_ls180.v:132022.3-132031.6" - wire width 66 $1\add_o[65:0] - attribute \src "issuer_ls180.v:131890.3-131912.6" - wire width 64 $1\b_i[63:0] - attribute \src "issuer_ls180.v:131876.3-131889.6" - wire width 2 $1\ca[1:0] - attribute \src "issuer_ls180.v:132043.3-132053.6" - wire $1\carry_32[0:0] - attribute \src "issuer_ls180.v:132054.3-132064.6" - wire $1\carry_64[0:0] - attribute \src "issuer_ls180.v:131778.3-131803.6" - wire width 4 $1\cr_a[3:0] - attribute \src "issuer_ls180.v:131804.3-131818.6" - wire $1\cr_a_ok[0:0] - attribute \src "issuer_ls180.v:131982.3-132001.6" - wire width 8 $1\eqs[7:0] - attribute \src "issuer_ls180.v:131642.3-131651.6" - wire $1\is_32bit[0:0] - attribute \src "issuer_ls180.v:131713.3-131731.6" - wire $1\msb_a[0:0] - attribute \src "issuer_ls180.v:131732.3-131750.6" - wire $1\msb_b[0:0] - attribute \src "issuer_ls180.v:131819.3-131856.6" - wire width 64 $1\o[63:0] - attribute \src "issuer_ls180.v:131857.3-131875.6" - wire $1\o_ok[0:0] - attribute \src "issuer_ls180.v:131935.3-131948.6" - wire width 2 $1\ov[1:0] - attribute \src "issuer_ls180.v:131971.3-131981.6" - wire width 8 $1\src1[7:0] - attribute \src "issuer_ls180.v:131686.3-131712.6" - wire width 5 $1\tval[4:0] - attribute \src "issuer_ls180.v:131913.3-131923.6" - wire width 2 $1\xer_ca$20[1:0]$6332 - attribute \src "issuer_ls180.v:131924.3-131934.6" - wire $1\xer_ca_ok[0:0] - attribute \src "issuer_ls180.v:131949.3-131959.6" - wire width 2 $1\xer_ov[1:0] - attribute \src "issuer_ls180.v:131960.3-131970.6" - wire $1\xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:131675.3-131685.6" - wire $1\zerohi[0:0] - attribute \src "issuer_ls180.v:132065.3-132075.6" - wire $1\zerolo[0:0] - attribute \src "issuer_ls180.v:131652.3-131674.6" - wire width 64 $2\a_i[63:0] - attribute \src "issuer_ls180.v:131751.3-131777.6" - wire $2\a_lt[0:0] - attribute \src "issuer_ls180.v:131890.3-131912.6" - wire width 64 $2\b_i[63:0] - attribute \src "issuer_ls180.v:131778.3-131803.6" - wire width 2 $2\cr_a[3:2] - attribute \src "issuer_ls180.v:131713.3-131731.6" - wire $2\msb_a[0:0] - attribute \src "issuer_ls180.v:131732.3-131750.6" - wire $2\msb_b[0:0] - attribute \src "issuer_ls180.v:131819.3-131856.6" - wire width 64 $2\o[63:0] - attribute \src "issuer_ls180.v:131686.3-131712.6" - wire width 5 $2\tval[4:0] - attribute \src "issuer_ls180.v:131751.3-131777.6" - wire $3\a_lt[0:0] - attribute \src "issuer_ls180.v:131819.3-131856.6" - wire width 64 $3\o[63:0] - attribute \src "issuer_ls180.v:131686.3-131712.6" - wire width 5 $3\tval[4:0] - attribute \src "issuer_ls180.v:131819.3-131856.6" - wire width 64 $4\o[63:0] - attribute \src "issuer_ls180.v:131617.18-131617.105" - wire width 67 $add$issuer_ls180.v:131617$6292_Y - attribute \src "issuer_ls180.v:131591.19-131591.107" - wire $and$issuer_ls180.v:131591$6266_Y - attribute \src "issuer_ls180.v:131595.19-131595.107" - wire $and$issuer_ls180.v:131595$6270_Y - attribute \src "issuer_ls180.v:131628.18-131628.106" - wire $and$issuer_ls180.v:131628$6303_Y - attribute \src "issuer_ls180.v:131633.18-131633.106" - wire $and$issuer_ls180.v:131633$6308_Y - attribute \src "issuer_ls180.v:131636.18-131636.106" - wire $and$issuer_ls180.v:131636$6311_Y - attribute \src "issuer_ls180.v:131639.18-131639.106" - wire $and$issuer_ls180.v:131639$6314_Y - attribute \src "issuer_ls180.v:131582.19-131582.118" - wire $eq$issuer_ls180.v:131582$6257_Y - attribute \src "issuer_ls180.v:131583.19-131583.118" - wire $eq$issuer_ls180.v:131583$6258_Y - attribute \src "issuer_ls180.v:131584.19-131584.118" - wire $eq$issuer_ls180.v:131584$6259_Y - attribute \src "issuer_ls180.v:131596.19-131596.109" - wire $eq$issuer_ls180.v:131596$6271_Y - attribute \src "issuer_ls180.v:131597.19-131597.110" - wire $eq$issuer_ls180.v:131597$6272_Y - attribute \src "issuer_ls180.v:131598.19-131598.111" - wire $eq$issuer_ls180.v:131598$6273_Y - attribute \src "issuer_ls180.v:131599.19-131599.111" - wire $eq$issuer_ls180.v:131599$6274_Y - attribute \src "issuer_ls180.v:131600.19-131600.111" - wire $eq$issuer_ls180.v:131600$6275_Y - attribute \src "issuer_ls180.v:131601.19-131601.111" - wire $eq$issuer_ls180.v:131601$6276_Y - attribute \src "issuer_ls180.v:131602.19-131602.111" - wire $eq$issuer_ls180.v:131602$6277_Y - attribute \src "issuer_ls180.v:131603.19-131603.111" - wire $eq$issuer_ls180.v:131603$6278_Y - attribute \src "issuer_ls180.v:131604.18-131604.118" - wire $eq$issuer_ls180.v:131604$6279_Y - attribute \src "issuer_ls180.v:131606.18-131606.118" - wire $eq$issuer_ls180.v:131606$6281_Y - attribute \src "issuer_ls180.v:131607.18-131607.118" - wire $eq$issuer_ls180.v:131607$6282_Y - attribute \src "issuer_ls180.v:131608.18-131608.118" - wire $eq$issuer_ls180.v:131608$6283_Y - attribute \src "issuer_ls180.v:131609.18-131609.118" - wire $eq$issuer_ls180.v:131609$6284_Y - attribute \src "issuer_ls180.v:131611.18-131611.118" - wire $eq$issuer_ls180.v:131611$6286_Y - attribute \src "issuer_ls180.v:131612.18-131612.118" - wire $eq$issuer_ls180.v:131612$6287_Y - attribute \src "issuer_ls180.v:131614.18-131614.118" - wire $eq$issuer_ls180.v:131614$6289_Y - attribute \src "issuer_ls180.v:131615.18-131615.118" - wire $eq$issuer_ls180.v:131615$6290_Y - attribute \src "issuer_ls180.v:131629.18-131629.107" - wire $ne$issuer_ls180.v:131629$6304_Y - attribute \src "issuer_ls180.v:131640.18-131640.107" - wire $ne$issuer_ls180.v:131640$6315_Y - attribute \src "issuer_ls180.v:131590.19-131590.100" - wire $not$issuer_ls180.v:131590$6265_Y - attribute \src "issuer_ls180.v:131594.19-131594.100" - wire $not$issuer_ls180.v:131594$6269_Y - attribute \src "issuer_ls180.v:131605.18-131605.110" - wire $not$issuer_ls180.v:131605$6280_Y - attribute \src "issuer_ls180.v:131618.18-131618.97" - wire width 64 $not$issuer_ls180.v:131618$6293_Y - attribute \src "issuer_ls180.v:131623.18-131623.99" - wire $not$issuer_ls180.v:131623$6298_Y - attribute \src "issuer_ls180.v:131626.18-131626.99" - wire $not$issuer_ls180.v:131626$6301_Y - attribute \src "issuer_ls180.v:131630.18-131630.99" - wire $not$issuer_ls180.v:131630$6305_Y - attribute \src "issuer_ls180.v:131631.18-131631.99" - wire $not$issuer_ls180.v:131631$6306_Y - attribute \src "issuer_ls180.v:131610.18-131610.104" - wire $or$issuer_ls180.v:131610$6285_Y - attribute \src "issuer_ls180.v:131613.18-131613.104" - wire $or$issuer_ls180.v:131613$6288_Y - attribute \src "issuer_ls180.v:131616.18-131616.104" - wire $or$issuer_ls180.v:131616$6291_Y - attribute \src "issuer_ls180.v:131627.18-131627.110" - wire $or$issuer_ls180.v:131627$6302_Y - attribute \src "issuer_ls180.v:131632.18-131632.110" - wire $or$issuer_ls180.v:131632$6307_Y - attribute \src "issuer_ls180.v:131635.18-131635.110" - wire $or$issuer_ls180.v:131635$6310_Y - attribute \src "issuer_ls180.v:131638.18-131638.110" - wire $or$issuer_ls180.v:131638$6313_Y - attribute \src "issuer_ls180.v:131581.18-131581.98" - wire $reduce_or$issuer_ls180.v:131581$6256_Y - attribute \src "issuer_ls180.v:131585.19-131585.99" - wire $reduce_or$issuer_ls180.v:131585$6260_Y - attribute \src "issuer_ls180.v:131622.18-131622.99" - wire $reduce_or$issuer_ls180.v:131622$6297_Y - attribute \src "issuer_ls180.v:131625.18-131625.99" - wire $reduce_or$issuer_ls180.v:131625$6300_Y - attribute \src "issuer_ls180.v:131634.18-131634.121" - wire $ternary$issuer_ls180.v:131634$6309_Y - attribute \src "issuer_ls180.v:131637.18-131637.119" - wire $ternary$issuer_ls180.v:131637$6312_Y - attribute \src "issuer_ls180.v:131641.18-131641.123" - wire $ternary$issuer_ls180.v:131641$6316_Y - attribute \src "issuer_ls180.v:131586.19-131586.111" - wire $xor$issuer_ls180.v:131586$6261_Y - attribute \src "issuer_ls180.v:131587.19-131587.111" - wire $xor$issuer_ls180.v:131587$6262_Y - attribute \src "issuer_ls180.v:131588.19-131588.110" - wire $xor$issuer_ls180.v:131588$6263_Y - attribute \src "issuer_ls180.v:131589.19-131589.110" - wire $xor$issuer_ls180.v:131589$6264_Y - attribute \src "issuer_ls180.v:131592.19-131592.110" - wire $xor$issuer_ls180.v:131592$6267_Y - attribute \src "issuer_ls180.v:131593.19-131593.110" - wire $xor$issuer_ls180.v:131593$6268_Y - attribute \src "issuer_ls180.v:131619.18-131619.111" - wire $xor$issuer_ls180.v:131619$6294_Y - attribute \src "issuer_ls180.v:131620.18-131620.107" - wire $xor$issuer_ls180.v:131620$6295_Y - attribute \src "issuer_ls180.v:131621.18-131621.113" - wire width 32 $xor$issuer_ls180.v:131621$6296_Y - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - wire \$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - wire \$143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:52" - wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:53" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" - wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" - wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" - wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" - wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - wire width 67 \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - wire width 67 \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" - wire width 64 \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106" - wire \$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106" - wire \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - wire \$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - wire \$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - wire width 32 \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - wire \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - wire \$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - wire width 32 \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - wire \$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - wire \$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" - wire \$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" - wire \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" - wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" 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"/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61" - wire width 64 \a_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:95" - wire \a_lt - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:93" - wire width 64 \a_n - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" - wire width 66 \add_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:58" - wire width 66 \add_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59" - wire width 66 \add_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 40 \alu_op__data_len$18 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \alu_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 25 \alu_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 26 \alu_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \alu_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 13 \alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 36 \alu_op__input_carry$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 41 \alu_op__insn$19 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \alu_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 24 \alu_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \alu_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \alu_op__invert_out$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \alu_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \alu_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \alu_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \alu_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \alu_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \alu_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \alu_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \alu_op__write_cr0$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \alu_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:62" - wire width 64 \b_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:146" - wire width 2 \ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" - wire \carry_32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97" - wire \carry_64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 44 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 45 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:174" - wire width 8 \eqs - attribute \src "issuer_ls180.v:131126.7-131126.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50" - wire \is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100" - wire \msb_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:101" - wire \msb_b - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 51 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 23 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 42 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 43 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" - wire width 2 \ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:175" - wire width 8 \src1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:94" - wire width 5 \tval - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 22 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 46 \xer_ca$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 47 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 48 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 49 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 50 \xer_so$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:99" - wire \zerohi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98" - wire \zerolo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $add $add$issuer_ls180.v:131617$6292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 66 - parameter \B_SIGNED 0 - parameter \B_WIDTH 66 - parameter \Y_WIDTH 67 - connect \A \add_a - connect \B \add_b - connect \Y $add$issuer_ls180.v:131617$6292_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $and $and$issuer_ls180.v:131591$6266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$113 - connect \B \$115 - connect \Y $and$issuer_ls180.v:131591$6266_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $and $and$issuer_ls180.v:131595$6270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$121 - connect \B \$123 - connect \Y $and$issuer_ls180.v:131595$6270_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - cell $and $and$issuer_ls180.v:131628$6303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \zerolo - connect \B \$69 - connect \Y $and$issuer_ls180.v:131628$6303_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - cell $and $and$issuer_ls180.v:131633$6308 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \zerolo - connect \B \$79 - connect \Y $and$issuer_ls180.v:131633$6308_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - cell $and $and$issuer_ls180.v:131636$6311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \zerolo - connect \B \$85 - connect \Y $and$issuer_ls180.v:131636$6311_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - cell $and $and$issuer_ls180.v:131639$6314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \zerolo - connect \B \$91 - connect \Y $and$issuer_ls180.v:131639$6314_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:162" - cell $eq $eq$issuer_ls180.v:131582$6257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_op__data_len - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:131582$6257_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:164" - cell $eq $eq$issuer_ls180.v:131583$6258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \alu_op__data_len - connect \B 2'10 - connect \Y $eq$issuer_ls180.v:131583$6258_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" - cell $eq $eq$issuer_ls180.v:131584$6259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_op__data_len - connect \B 3'100 - connect \Y $eq$issuer_ls180.v:131584$6259_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - cell $eq $eq$issuer_ls180.v:131596$6271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [7:0] - connect \Y $eq$issuer_ls180.v:131596$6271_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - cell $eq $eq$issuer_ls180.v:131597$6272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [15:8] - connect \Y $eq$issuer_ls180.v:131597$6272_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - cell $eq $eq$issuer_ls180.v:131598$6273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [23:16] - connect \Y $eq$issuer_ls180.v:131598$6273_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - cell $eq $eq$issuer_ls180.v:131599$6274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [31:24] - connect \Y $eq$issuer_ls180.v:131599$6274_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - cell $eq $eq$issuer_ls180.v:131600$6275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [39:32] - connect \Y $eq$issuer_ls180.v:131600$6275_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - cell $eq $eq$issuer_ls180.v:131601$6276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [47:40] - connect \Y $eq$issuer_ls180.v:131601$6276_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - cell $eq $eq$issuer_ls180.v:131602$6277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [55:48] - connect \Y $eq$issuer_ls180.v:131602$6277_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - cell $eq $eq$issuer_ls180.v:131603$6278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [63:56] - connect \Y $eq$issuer_ls180.v:131603$6278_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:52" - cell $eq $eq$issuer_ls180.v:131604$6279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $eq$issuer_ls180.v:131604$6279_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" - cell $eq $eq$issuer_ls180.v:131606$6281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $eq$issuer_ls180.v:131606$6281_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" - cell $eq $eq$issuer_ls180.v:131607$6282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $eq$issuer_ls180.v:131607$6282_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" - cell $eq $eq$issuer_ls180.v:131608$6283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0000010 - connect \Y $eq$issuer_ls180.v:131608$6283_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - cell $eq $eq$issuer_ls180.v:131609$6284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $eq$issuer_ls180.v:131609$6284_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" - cell $eq $eq$issuer_ls180.v:131611$6286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0000010 - connect \Y $eq$issuer_ls180.v:131611$6286_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - cell $eq $eq$issuer_ls180.v:131612$6287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $eq$issuer_ls180.v:131612$6287_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" - cell $eq $eq$issuer_ls180.v:131614$6289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0000010 - connect \Y $eq$issuer_ls180.v:131614$6289_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - cell $eq $eq$issuer_ls180.v:131615$6290 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $eq$issuer_ls180.v:131615$6290_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" - cell $ne $ne$issuer_ls180.v:131629$6304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_a - connect \B \msb_b - connect \Y $ne$issuer_ls180.v:131629$6304_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" - cell $ne $ne$issuer_ls180.v:131640$6315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_a - connect \B \msb_b - connect \Y $ne$issuer_ls180.v:131640$6315_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $not $not$issuer_ls180.v:131590$6265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$116 - connect \Y $not$issuer_ls180.v:131590$6265_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $not $not$issuer_ls180.v:131594$6269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$124 - connect \Y $not$issuer_ls180.v:131594$6269_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:53" - cell $not $not$issuer_ls180.v:131605$6280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn [21] - connect \Y $not$issuer_ls180.v:131605$6280_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" - cell $not $not$issuer_ls180.v:131618$6293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \Y $not$issuer_ls180.v:131618$6293_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - cell $not $not$issuer_ls180.v:131623$6298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$58 - connect \Y $not$issuer_ls180.v:131623$6298_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $not $not$issuer_ls180.v:131626$6301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$64 - connect \Y $not$issuer_ls180.v:131626$6301_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" - cell $not $not$issuer_ls180.v:131630$6305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_lt - connect \Y $not$issuer_ls180.v:131630$6305_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" - cell $not $not$issuer_ls180.v:131631$6306 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_lt - connect \Y $not$issuer_ls180.v:131631$6306_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - cell $or $or$issuer_ls180.v:131610$6285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$30 - connect \B \$32 - connect \Y $or$issuer_ls180.v:131610$6285_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - cell $or $or$issuer_ls180.v:131613$6288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$36 - connect \B \$38 - connect \Y $or$issuer_ls180.v:131613$6288_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - cell $or $or$issuer_ls180.v:131616$6291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$42 - connect \B \$44 - connect \Y $or$issuer_ls180.v:131616$6291_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - cell $or $or$issuer_ls180.v:131627$6302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_32bit - connect \B \zerohi - connect \Y $or$issuer_ls180.v:131627$6302_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - cell $or $or$issuer_ls180.v:131632$6307 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_32bit - connect \B \zerohi - connect \Y $or$issuer_ls180.v:131632$6307_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - cell $or $or$issuer_ls180.v:131635$6310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_32bit - connect \B \zerohi - connect \Y $or$issuer_ls180.v:131635$6310_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - cell $or $or$issuer_ls180.v:131638$6313 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_32bit - connect \B \zerohi - connect \Y $or$issuer_ls180.v:131638$6313_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:181" - cell $reduce_or $reduce_or$issuer_ls180.v:131581$6256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \eqs - connect \Y $reduce_or$issuer_ls180.v:131581$6256_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:179" - cell $reduce_or $reduce_or$issuer_ls180.v:131585$6260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \eqs - connect \Y $reduce_or$issuer_ls180.v:131585$6260_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - cell $reduce_or $reduce_or$issuer_ls180.v:131622$6297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \$59 - connect \Y $reduce_or$issuer_ls180.v:131622$6297_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $reduce_or $reduce_or$issuer_ls180.v:131625$6300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \$65 - connect \Y $reduce_or$issuer_ls180.v:131625$6300_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $mux $ternary$issuer_ls180.v:131634$6309 - parameter \WIDTH 1 - connect \A \a_n [63] - connect \B \a_n [31] - connect \S \is_32bit - connect \Y $ternary$issuer_ls180.v:131634$6309_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:117" - cell $mux $ternary$issuer_ls180.v:131637$6312 - parameter \WIDTH 1 - connect \A \rb [63] - connect \B \rb [31] - connect \S \is_32bit - connect \Y $ternary$issuer_ls180.v:131637$6312_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:127" - cell $mux $ternary$issuer_ls180.v:131641$6316 - parameter \WIDTH 1 - connect \A \carry_64 - connect \B \carry_32 - connect \S \is_32bit - connect \Y $ternary$issuer_ls180.v:131641$6316_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:148" - cell $xor $xor$issuer_ls180.v:131586$6261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_i [32] - connect \B \b_i [32] - connect \Y $xor$issuer_ls180.v:131586$6261_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:148" - cell $xor $xor$issuer_ls180.v:131587$6262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \add_o [33] - connect \B \$109 - connect \Y $xor$issuer_ls180.v:131587$6262_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $xor $xor$issuer_ls180.v:131588$6263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ca [0] - connect \B \add_o [64] - connect \Y $xor$issuer_ls180.v:131588$6263_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $xor $xor$issuer_ls180.v:131589$6264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_i [63] - connect \B \b_i [63] - connect \Y $xor$issuer_ls180.v:131589$6264_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $xor $xor$issuer_ls180.v:131592$6267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ca [1] - connect \B \add_o [32] - connect \Y $xor$issuer_ls180.v:131592$6267_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $xor $xor$issuer_ls180.v:131593$6268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_i [31] - connect \B \b_i [31] - connect \Y $xor$issuer_ls180.v:131593$6268_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106" - cell $xor $xor$issuer_ls180.v:131619$6294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \add_o [33] - connect \B \ra [32] - connect \Y $xor$issuer_ls180.v:131619$6294_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106" - cell $xor $xor$issuer_ls180.v:131620$6295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$53 - connect \B \rb [32] - connect \Y $xor$issuer_ls180.v:131620$6295_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - cell $xor $xor$issuer_ls180.v:131621$6296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \a_n [31:0] - connect \B \rb [31:0] - connect \Y $xor$issuer_ls180.v:131621$6296_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $xor $xor$issuer_ls180.v:131624$6299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \a_n [63:32] - connect \B \rb [63:32] - connect \Y $xor$issuer_ls180.v:131624$6299_Y - end - attribute \src "issuer_ls180.v:131126.7-131126.20" - process $proc$issuer_ls180.v:131126$6346 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:131642.3-131651.6" - process $proc$issuer_ls180.v:131642$6317 - assign { } { } - assign { } { } - assign $0\is_32bit[0:0] $1\is_32bit[0:0] - attribute \src "issuer_ls180.v:131643.5-131643.29" - switch \initial - attribute \src "issuer_ls180.v:131643.9-131643.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:52" - switch \$22 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\is_32bit[0:0] \$24 - case - assign $1\is_32bit[0:0] 1'0 - end - sync always - update \is_32bit $0\is_32bit[0:0] - end - attribute \src "issuer_ls180.v:131652.3-131674.6" - process $proc$issuer_ls180.v:131652$6318 - assign { } { } - assign $0\a_i[63:0] $1\a_i[63:0] - attribute \src "issuer_ls180.v:131653.5-131653.29" - switch \initial - attribute \src "issuer_ls180.v:131653.9-131653.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" - switch { \is_32bit \$26 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\a_i[63:0] \ra - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\a_i[63:0] $2\a_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - switch \alu_op__is_signed - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\a_i[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\a_i[63:0] { 32'00000000000000000000000000000000 \ra [31:0] } - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\a_i[63:0] \ra - end - sync always - update \a_i $0\a_i[63:0] - end - attribute \src "issuer_ls180.v:131675.3-131685.6" - process $proc$issuer_ls180.v:131675$6319 - assign { } { } - assign { } { } - assign $0\zerohi[0:0] $1\zerohi[0:0] - attribute \src "issuer_ls180.v:131676.5-131676.29" - switch \initial - attribute \src "issuer_ls180.v:131676.9-131676.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\zerohi[0:0] \$63 - case - assign $1\zerohi[0:0] 1'0 - end - sync always - update \zerohi $0\zerohi[0:0] - end - attribute \src "issuer_ls180.v:131686.3-131712.6" - process $proc$issuer_ls180.v:131686$6320 - assign { } { } - assign { } { } - assign $0\tval[4:0] $1\tval[4:0] - attribute \src "issuer_ls180.v:131687.5-131687.29" - switch \initial - attribute \src "issuer_ls180.v:131687.9-131687.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\tval[4:0] $2\tval[4:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - switch \$71 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { $2\tval[4:0] [4:3] $2\tval[4:0] [1:0] } 4'0000 - assign $2\tval[4:0] [2] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\tval[4:0] $3\tval[4:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" - switch \$73 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\tval[4:0] { \msb_a \msb_b 1'0 \msb_b \msb_a } - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $3\tval[4:0] { \a_lt \$77 1'0 \a_lt \$75 } - end - end - case - assign $1\tval[4:0] 5'00000 - end - sync always - update \tval $0\tval[4:0] - end - attribute \src "issuer_ls180.v:131713.3-131731.6" - process $proc$issuer_ls180.v:131713$6321 - assign { } { } - assign { } { } - assign $0\msb_a[0:0] $1\msb_a[0:0] - attribute \src "issuer_ls180.v:131714.5-131714.29" - switch \initial - attribute \src "issuer_ls180.v:131714.9-131714.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\msb_a[0:0] $2\msb_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - switch \$81 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign $2\msb_a[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\msb_a[0:0] \$83 - end - case - assign $1\msb_a[0:0] 1'0 - end - sync always - update \msb_a $0\msb_a[0:0] - end - attribute \src "issuer_ls180.v:131732.3-131750.6" - process $proc$issuer_ls180.v:131732$6322 - assign { } { } - assign { } { } - assign $0\msb_b[0:0] $1\msb_b[0:0] - attribute \src "issuer_ls180.v:131733.5-131733.29" - switch \initial - attribute \src "issuer_ls180.v:131733.9-131733.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\msb_b[0:0] $2\msb_b[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - switch \$87 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign $2\msb_b[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\msb_b[0:0] \$89 - end - case - assign $1\msb_b[0:0] 1'0 - end - sync always - update \msb_b $0\msb_b[0:0] - end - attribute \src "issuer_ls180.v:131751.3-131777.6" - process $proc$issuer_ls180.v:131751$6323 - assign { } { } - assign { } { } - assign $0\a_lt[0:0] $1\a_lt[0:0] - attribute \src "issuer_ls180.v:131752.5-131752.29" - switch \initial - attribute \src "issuer_ls180.v:131752.9-131752.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\a_lt[0:0] $2\a_lt[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - switch \$93 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign $2\a_lt[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\a_lt[0:0] $3\a_lt[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" - switch \$95 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign $3\a_lt[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $3\a_lt[0:0] \$97 - end - end - case - assign $1\a_lt[0:0] 1'0 - end - sync always - update \a_lt $0\a_lt[0:0] - end - attribute \src "issuer_ls180.v:131778.3-131803.6" - process $proc$issuer_ls180.v:131778$6324 - assign { } { } - assign { } { } - assign $0\cr_a[3:0] $1\cr_a[3:0] - attribute \src "issuer_ls180.v:131779.5-131779.29" - switch \initial - attribute \src "issuer_ls180.v:131779.9-131779.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\cr_a[3:0] [1:0] { \tval [2] \xer_so } - assign $1\cr_a[3:0] [3:2] $2\cr_a[3:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" - switch \alu_op__is_signed - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_a[3:2] \tval [4:3] - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cr_a[3:2] \tval [1:0] - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001100 - assign { } { } - assign $1\cr_a[3:0] { 1'0 \$99 2'00 } - case - assign $1\cr_a[3:0] 4'0000 - end - sync always - update \cr_a $0\cr_a[3:0] - end - attribute \src "issuer_ls180.v:131804.3-131818.6" - process $proc$issuer_ls180.v:131804$6325 - assign { } { } - assign { } { } - assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] - attribute \src "issuer_ls180.v:131805.5-131805.29" - switch \initial - attribute \src "issuer_ls180.v:131805.9-131805.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\cr_a_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001100 - assign { } { } - assign $1\cr_a_ok[0:0] 1'1 - case - assign $1\cr_a_ok[0:0] 1'0 - end - sync always - update \cr_a_ok $0\cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:131819.3-131856.6" - process $proc$issuer_ls180.v:131819$6326 - assign { } { } - assign { } { } - assign $0\o[63:0] $1\o[63:0] - attribute \src "issuer_ls180.v:131820.5-131820.29" - switch \initial - attribute \src "issuer_ls180.v:131820.9-131820.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000010 - assign { } { } - assign $1\o[63:0] \add_o [64:1] - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0011111 - assign { } { } - assign { } { } - assign { } { } - assign $1\o[63:0] $4\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:162" - switch \$101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o[63:0] { \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7:0] } - case - assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:164" - switch \$103 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\o[63:0] { \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15:0] } - case - assign $3\o[63:0] $2\o[63:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" - switch \$105 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\o[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } - case - assign $4\o[63:0] $3\o[63:0] - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001100 - assign $1\o[63:0] [63:1] 63'000000000000000000000000000000000000000000000000000000000000000 - assign $1\o[63:0] [0] \$107 - case - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \o $0\o[63:0] - end - attribute \src "issuer_ls180.v:131857.3-131875.6" - process $proc$issuer_ls180.v:131857$6327 - assign { } { } - assign { } { } - assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "issuer_ls180.v:131858.5-131858.29" - switch \initial - attribute \src "issuer_ls180.v:131858.9-131858.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000010 - assign { } { } - assign $1\o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0011111 - assign { } { } - assign $1\o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001100 - assign { } { } - assign $1\o_ok[0:0] 1'0 - case - assign $1\o_ok[0:0] 1'0 - end - sync always - update \o_ok $0\o_ok[0:0] - end - attribute \src "issuer_ls180.v:131876.3-131889.6" - process $proc$issuer_ls180.v:131876$6328 - assign { } { } - assign { } { } - assign $0\ca[1:0] $1\ca[1:0] - attribute \src "issuer_ls180.v:131877.5-131877.29" - switch \initial - attribute \src "issuer_ls180.v:131877.9-131877.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000010 - assign { } { } - assign $1\ca[1:0] [0] \add_o [65] - assign $1\ca[1:0] [1] \$111 - case - assign $1\ca[1:0] 2'00 - end - sync always - update \ca $0\ca[1:0] - end - attribute \src "issuer_ls180.v:131890.3-131912.6" - process $proc$issuer_ls180.v:131890$6329 - assign { } { } - assign $0\b_i[63:0] $1\b_i[63:0] - attribute \src "issuer_ls180.v:131891.5-131891.29" - switch \initial - attribute \src "issuer_ls180.v:131891.9-131891.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" - switch { \is_32bit \$28 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\b_i[63:0] \rb - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\b_i[63:0] $2\b_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - switch \alu_op__is_signed - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\b_i[63:0] { \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31:0] } - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\b_i[63:0] { 32'00000000000000000000000000000000 \rb [31:0] } - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\b_i[63:0] \rb - end - sync always - update \b_i $0\b_i[63:0] - end - attribute \src "issuer_ls180.v:131913.3-131923.6" - process $proc$issuer_ls180.v:131913$6330 - assign { } { } - assign { } { } - assign $0\xer_ca$20[1:0]$6331 $1\xer_ca$20[1:0]$6332 - attribute \src "issuer_ls180.v:131914.5-131914.29" - switch \initial - attribute \src "issuer_ls180.v:131914.9-131914.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000010 - assign { } { } - assign $1\xer_ca$20[1:0]$6332 \ca - case - assign $1\xer_ca$20[1:0]$6332 2'00 - end - sync always - update \xer_ca$20 $0\xer_ca$20[1:0]$6331 - end - attribute \src "issuer_ls180.v:131924.3-131934.6" - process $proc$issuer_ls180.v:131924$6333 - assign { } { } - assign { } { } - assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] - attribute \src "issuer_ls180.v:131925.5-131925.29" - switch \initial - attribute \src "issuer_ls180.v:131925.9-131925.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000010 - assign { } { } - assign $1\xer_ca_ok[0:0] 1'1 - case - assign $1\xer_ca_ok[0:0] 1'0 - end - sync always - update \xer_ca_ok $0\xer_ca_ok[0:0] - end - attribute \src "issuer_ls180.v:131935.3-131948.6" - process $proc$issuer_ls180.v:131935$6334 - assign { } { } - assign { } { } - assign $0\ov[1:0] $1\ov[1:0] - attribute \src "issuer_ls180.v:131936.5-131936.29" - switch \initial - attribute \src "issuer_ls180.v:131936.9-131936.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000010 - assign { } { } - assign $1\ov[1:0] [0] \$119 - assign $1\ov[1:0] [1] \$127 - case - assign $1\ov[1:0] 2'00 - end - sync always - update \ov $0\ov[1:0] - end - attribute \src "issuer_ls180.v:131949.3-131959.6" - process $proc$issuer_ls180.v:131949$6335 - assign { } { } - assign { } { } - assign $0\xer_ov[1:0] $1\xer_ov[1:0] - attribute \src "issuer_ls180.v:131950.5-131950.29" - switch \initial - attribute \src "issuer_ls180.v:131950.9-131950.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000010 - assign { } { } - assign $1\xer_ov[1:0] \ov - case - assign $1\xer_ov[1:0] 2'00 - end - sync always - update \xer_ov $0\xer_ov[1:0] - end - attribute \src "issuer_ls180.v:131960.3-131970.6" - process $proc$issuer_ls180.v:131960$6336 - assign { } { } - assign { } { } - assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:131961.5-131961.29" - switch \initial - attribute \src "issuer_ls180.v:131961.9-131961.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000010 - assign { } { } - assign $1\xer_ov_ok[0:0] 1'1 - case - assign $1\xer_ov_ok[0:0] 1'0 - end - sync always - update \xer_ov_ok $0\xer_ov_ok[0:0] - end - attribute \src "issuer_ls180.v:131971.3-131981.6" - process $proc$issuer_ls180.v:131971$6337 - assign { } { } - assign { } { } - assign $0\src1[7:0] $1\src1[7:0] - attribute \src "issuer_ls180.v:131972.5-131972.29" - switch \initial - attribute \src "issuer_ls180.v:131972.9-131972.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001100 - assign { } { } - assign $1\src1[7:0] \ra [7:0] - case - assign $1\src1[7:0] 8'00000000 - end - sync always - update \src1 $0\src1[7:0] - end - attribute \src "issuer_ls180.v:131982.3-132001.6" - process $proc$issuer_ls180.v:131982$6338 - assign { } { } - assign { } { } - assign $0\eqs[7:0] $1\eqs[7:0] - attribute \src "issuer_ls180.v:131983.5-131983.29" - switch \initial - attribute \src "issuer_ls180.v:131983.9-131983.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001100 - assign { } { } - assign $1\eqs[7:0] [0] \$129 - assign $1\eqs[7:0] [1] \$131 - assign $1\eqs[7:0] [2] \$133 - assign $1\eqs[7:0] [3] \$135 - assign $1\eqs[7:0] [4] \$137 - assign $1\eqs[7:0] [5] \$139 - assign $1\eqs[7:0] [6] \$141 - assign $1\eqs[7:0] [7] \$143 - case - assign $1\eqs[7:0] 8'00000000 - end - sync always - update \eqs $0\eqs[7:0] - end - attribute \src "issuer_ls180.v:132002.3-132011.6" - process $proc$issuer_ls180.v:132002$6339 - assign { } { } - assign { } { } - assign $0\add_a[65:0] $1\add_a[65:0] - attribute \src "issuer_ls180.v:132003.5-132003.29" - switch \initial - attribute \src "issuer_ls180.v:132003.9-132003.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - switch \$34 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\add_a[65:0] { 1'0 \a_i \xer_ca [0] } - case - assign $1\add_a[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \add_a $0\add_a[65:0] - end - attribute \src "issuer_ls180.v:132012.3-132021.6" - process $proc$issuer_ls180.v:132012$6340 - assign { } { } - assign { } { } - assign $0\add_b[65:0] $1\add_b[65:0] - attribute \src "issuer_ls180.v:132013.5-132013.29" - switch \initial - attribute \src "issuer_ls180.v:132013.9-132013.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - switch \$40 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\add_b[65:0] { 1'0 \b_i 1'1 } - case - assign $1\add_b[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \add_b $0\add_b[65:0] - end - attribute \src "issuer_ls180.v:132022.3-132031.6" - process $proc$issuer_ls180.v:132022$6341 - assign { } { } - assign { } { } - assign $0\add_o[65:0] $1\add_o[65:0] - attribute \src "issuer_ls180.v:132023.5-132023.29" - switch \initial - attribute \src "issuer_ls180.v:132023.9-132023.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - switch \$46 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\add_o[65:0] \$48 [65:0] - case - assign $1\add_o[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \add_o $0\add_o[65:0] - end - attribute \src "issuer_ls180.v:132032.3-132042.6" - process $proc$issuer_ls180.v:132032$6342 - assign { } { } - assign { } { } - assign $0\a_n[63:0] $1\a_n[63:0] - attribute \src "issuer_ls180.v:132033.5-132033.29" - switch \initial - attribute \src "issuer_ls180.v:132033.9-132033.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\a_n[63:0] \$51 - case - assign $1\a_n[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \a_n $0\a_n[63:0] - end - attribute \src "issuer_ls180.v:132043.3-132053.6" - process $proc$issuer_ls180.v:132043$6343 - assign { } { } - assign { } { } - assign $0\carry_32[0:0] $1\carry_32[0:0] - attribute \src "issuer_ls180.v:132044.5-132044.29" - switch \initial - attribute \src "issuer_ls180.v:132044.9-132044.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\carry_32[0:0] \$55 - case - assign $1\carry_32[0:0] 1'0 - end - sync always - update \carry_32 $0\carry_32[0:0] - end - attribute \src "issuer_ls180.v:132054.3-132064.6" - process $proc$issuer_ls180.v:132054$6344 - assign { } { } - assign { } { } - assign $0\carry_64[0:0] $1\carry_64[0:0] - attribute \src "issuer_ls180.v:132055.5-132055.29" - switch \initial - attribute \src "issuer_ls180.v:132055.9-132055.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\carry_64[0:0] \add_o [65] - case - assign $1\carry_64[0:0] 1'0 - end - sync always - update \carry_64 $0\carry_64[0:0] - end - attribute \src "issuer_ls180.v:132065.3-132075.6" - process $proc$issuer_ls180.v:132065$6345 - assign { } { } - assign { } { } - assign $0\zerolo[0:0] $1\zerolo[0:0] - attribute \src "issuer_ls180.v:132066.5-132066.29" - switch \initial - attribute \src "issuer_ls180.v:132066.9-132066.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\zerolo[0:0] \$57 - case - assign $1\zerolo[0:0] 1'0 - end - sync always - update \zerolo $0\zerolo[0:0] - end - connect \$99 $reduce_or$issuer_ls180.v:131581$6256_Y - connect \$101 $eq$issuer_ls180.v:131582$6257_Y - connect \$103 $eq$issuer_ls180.v:131583$6258_Y - connect \$105 $eq$issuer_ls180.v:131584$6259_Y - connect \$107 $reduce_or$issuer_ls180.v:131585$6260_Y - connect \$109 $xor$issuer_ls180.v:131586$6261_Y - connect \$111 $xor$issuer_ls180.v:131587$6262_Y - connect \$113 $xor$issuer_ls180.v:131588$6263_Y - connect \$116 $xor$issuer_ls180.v:131589$6264_Y - connect \$115 $not$issuer_ls180.v:131590$6265_Y - connect \$119 $and$issuer_ls180.v:131591$6266_Y - connect \$121 $xor$issuer_ls180.v:131592$6267_Y - connect \$124 $xor$issuer_ls180.v:131593$6268_Y - connect \$123 $not$issuer_ls180.v:131594$6269_Y - connect \$127 $and$issuer_ls180.v:131595$6270_Y - connect \$129 $eq$issuer_ls180.v:131596$6271_Y - connect \$131 $eq$issuer_ls180.v:131597$6272_Y - connect \$133 $eq$issuer_ls180.v:131598$6273_Y - connect \$135 $eq$issuer_ls180.v:131599$6274_Y - connect \$137 $eq$issuer_ls180.v:131600$6275_Y - connect \$139 $eq$issuer_ls180.v:131601$6276_Y - connect \$141 $eq$issuer_ls180.v:131602$6277_Y - connect \$143 $eq$issuer_ls180.v:131603$6278_Y - connect \$22 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attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 10 \sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 31 \sr_op__input_carry$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \sr_op__input_cr$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 16 \sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 37 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 40 \xer_so$18 - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:132389.11-132404.4" - cell \rotator \rotator - connect \arith \rotator_arith - connect \carry_out_o \rotator_carry_out_o - connect \clear_left \rotator_clear_left - connect \clear_right \rotator_clear_right - connect \is_32bit \rotator_is_32bit - connect \mb \rotator_mb - connect \mb_extra \rotator_mb_extra - connect \me \rotator_me - connect \ra \rotator_ra - connect \result_o \rotator_result_o - connect \right_shift \rotator_right_shift - connect \rs \rotator_rs - connect \shift \rotator_shift - connect \sign_ext_rs \rotator_sign_ext_rs - end - attribute \src "issuer_ls180.v:132085.7-132085.20" - process $proc$issuer_ls180.v:132085$6349 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:132405.3-132439.6" - process $proc$issuer_ls180.v:132405$6347 - assign { } { } - assign { } { } - assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "issuer_ls180.v:132406.5-132406.29" - switch \initial - attribute \src "issuer_ls180.v:132406.9-132406.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" - switch \sr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0111100 - assign $1\o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0111101 - assign $1\o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0111000 - assign $1\o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0111001 - assign $1\o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0111010 - assign $1\o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0100000 - assign $1\o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\o_ok[0:0] 1'0 - end - sync always - update \o_ok $0\o_ok[0:0] - end - attribute \src "issuer_ls180.v:132440.3-132470.6" - process $proc$issuer_ls180.v:132440$6348 - assign { } { } - assign { } { } - assign $0\mode[3:0] $1\mode[3:0] - attribute \src "issuer_ls180.v:132441.5-132441.29" - switch \initial - attribute \src "issuer_ls180.v:132441.9-132441.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" - switch \sr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0111100 - assign { } { } - assign $1\mode[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0111101 - assign { } { } - assign $1\mode[3:0] 4'0001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0111000 - assign { } { } - assign $1\mode[3:0] 4'0110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0111001 - assign { } { } - assign $1\mode[3:0] 4'0010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0111010 - assign { } { } - assign $1\mode[3:0] 4'0100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0100000 - assign { } { } - assign $1\mode[3:0] 4'1000 - case - assign $1\mode[3:0] 4'0000 - end - sync always - update \mode $0\mode[3:0] - end - connect { \sr_op__insn$17 \sr_op__is_signed$16 \sr_op__is_32bit$15 \sr_op__output_cr$14 \sr_op__input_cr$13 \sr_op__output_carry$12 \sr_op__input_carry$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } - connect \muxid$1 \muxid - connect \xer_so$18 \xer_so - connect \xer_ca { \rotator_carry_out_o \rotator_carry_out_o } - connect \o \rotator_result_o - connect { \rotator_sign_ext_rs \rotator_clear_right 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"issuer_ls180.v:132901.3-132915.6" - wire $0\cr_bit[0:0] - attribute \src "issuer_ls180.v:132979.3-132999.6" - wire width 64 $0\ctr_m[63:0] - attribute \src "issuer_ls180.v:132953.3-132965.6" - wire width 64 $0\ctr_n[63:0] - attribute \src "issuer_ls180.v:132916.3-132928.6" - wire $0\ctr_write[0:0] - attribute \src "issuer_ls180.v:133000.3-133012.6" - wire $0\ctr_zero_bo1[0:0] - attribute \src "issuer_ls180.v:132966.3-132978.6" - wire width 64 $0\fast1$10[63:0]$6382 - attribute \src "issuer_ls180.v:132866.3-132880.6" - wire $0\fast1_ok[0:0] - attribute \src "issuer_ls180.v:132881.3-132890.6" - wire width 64 $0\fast2$11[63:0]$6374 - attribute \src "issuer_ls180.v:132891.3-132900.6" - wire $0\fast2_ok[0:0] - attribute \src "issuer_ls180.v:132493.7-132493.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:132929.3-132952.6" - wire $1\bc_taken[0:0] - attribute \src "issuer_ls180.v:132808.3-132819.6" - wire width 64 $1\br_addr[63:0] - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" - wire width 65 \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:119" - wire \bc_taken - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:109" - wire width 2 \bi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:105" - wire width 5 \bo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:88" - wire width 64 \br_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:87" - wire width 64 \br_imm_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 1 \br_op__cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 13 \br_op__cia$2 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute 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attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 15 \br_op__fn_unit$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 5 \br_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 17 \br_op__imm_data__data$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \br_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 18 \br_op__imm_data__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 4 \br_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 16 \br_op__insn$5 - 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attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 14 \br_op__insn_type$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \br_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \br_op__is_32bit$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \br_op__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 19 \br_op__lk$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:89" - wire \br_taken - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 11 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:110" - wire \cr_bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129" - wire width 64 \ctr_m - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:124" - wire width 64 \ctr_n - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:115" - wire \ctr_write - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135" - wire \ctr_zero_bo1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 9 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 21 \fast1$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 22 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 10 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 23 \fast2$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 24 \fast2_ok - attribute \src "issuer_ls180.v:132493.7-132493.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 27 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 12 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 25 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 26 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" - cell $add $add$issuer_ls180.v:132792$6352 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \br_imm_addr - connect \B \br_op__cia - connect \Y $add$issuer_ls180.v:132792$6352_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" - cell $add $add$issuer_ls180.v:132807$6368 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 65 - connect \A \br_op__cia - connect \B 3'100 - connect \Y $add$issuer_ls180.v:132807$6368_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $and $and$issuer_ls180.v:132799$6359 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ctr_zero_bo1 - connect \B \$29 - connect \Y $and$issuer_ls180.v:132799$6359_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" - cell $and $and$issuer_ls180.v:132800$6360 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ctr_zero_bo1 - connect \B \cr_bit - connect \Y $and$issuer_ls180.v:132800$6360_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $and $and$issuer_ls180.v:132806$6367 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \br_op__insn [10] - connect \B \$44 - connect \Y $and$issuer_ls180.v:132806$6367_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $eq $eq$issuer_ls180.v:132790$6350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \br_op__insn_type - connect \B 7'0001000 - connect \Y $eq$issuer_ls180.v:132790$6350_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $eq $eq$issuer_ls180.v:132793$6353 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cr_bit - connect \B \bo [3] - connect \Y $eq$issuer_ls180.v:132793$6353_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" - cell $eq $eq$issuer_ls180.v:132795$6355 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \bo [4:3] - connect \B 1'0 - connect \Y $eq$issuer_ls180.v:132795$6355_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" - cell $eq $eq$issuer_ls180.v:132796$6356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \bo [4:3] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:132796$6356_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" - cell $eq $eq$issuer_ls180.v:132797$6357 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \bo [4] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:132797$6357_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$issuer_ls180.v:132802$6362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \fast1 [31:0] - connect \Y $extend$issuer_ls180.v:132802$6362_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $not $not$issuer_ls180.v:132798$6358 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cr_bit - connect \Y $not$issuer_ls180.v:132798$6358_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $not $not$issuer_ls180.v:132805$6366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \br_op__insn [6] - connect \Y $not$issuer_ls180.v:132805$6366_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $or $or$issuer_ls180.v:132791$6351 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \br_op__insn [1] - connect \B \$12 - connect \Y $or$issuer_ls180.v:132791$6351_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $or $or$issuer_ls180.v:132794$6354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$19 - connect \B \bo [4] - connect \Y $or$issuer_ls180.v:132794$6354_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$issuer_ls180.v:132802$6363 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:132802$6362_Y - connect \Y $pos$issuer_ls180.v:132802$6363_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $reduce_or $reduce_or$issuer_ls180.v:132803$6364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \ctr_n - connect \Y $reduce_or$issuer_ls180.v:132803$6364_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" - cell $sub $sub$issuer_ls180.v:132801$6361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \fast1 - connect \B 1'1 - connect \Y $sub$issuer_ls180.v:132801$6361_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $xor $xor$issuer_ls180.v:132804$6365 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \bo [1] - connect \B \$40 - connect \Y $xor$issuer_ls180.v:132804$6365_Y - end - attribute \src "issuer_ls180.v:132493.7-132493.20" - process $proc$issuer_ls180.v:132493$6386 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:132808.3-132819.6" - process $proc$issuer_ls180.v:132808$6369 - assign { } { } - assign $0\br_addr[63:0] $1\br_addr[63:0] - attribute \src "issuer_ls180.v:132809.5-132809.29" - switch \initial - attribute \src "issuer_ls180.v:132809.9-132809.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - switch \$14 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\br_addr[63:0] \br_imm_addr - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\br_addr[63:0] \$16 [63:0] - end - sync always - update \br_addr $0\br_addr[63:0] - end - attribute \src "issuer_ls180.v:132820.3-132846.6" - process $proc$issuer_ls180.v:132820$6370 - assign { } { } - assign { } { } - assign $0\br_imm_addr[63:0] $1\br_imm_addr[63:0] - attribute \src "issuer_ls180.v:132821.5-132821.29" - switch \initial - attribute \src "issuer_ls180.v:132821.9-132821.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" - switch \br_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000110 - assign { } { } - assign $1\br_imm_addr[63:0] { \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25:2] 2'00 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000111 - assign { } { } - assign $1\br_imm_addr[63:0] { \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15:2] 2'00 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001000 - assign { } { } - assign $1\br_imm_addr[63:0] $2\br_imm_addr[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - switch \$46 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\br_imm_addr[63:0] { \fast1 [63:2] 2'00 } - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\br_imm_addr[63:0] { \fast2 [63:2] 2'00 } - end - case - assign $1\br_imm_addr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \br_imm_addr $0\br_imm_addr[63:0] - end - attribute \src "issuer_ls180.v:132847.3-132865.6" - process $proc$issuer_ls180.v:132847$6371 - assign { } { } - assign { } { } - assign $0\br_taken[0:0] $1\br_taken[0:0] - attribute \src "issuer_ls180.v:132848.5-132848.29" - switch \initial - attribute \src "issuer_ls180.v:132848.9-132848.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" - switch \br_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000110 - assign { } { } - assign $1\br_taken[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000111 - assign { } { } - assign $1\br_taken[0:0] \bc_taken - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001000 - assign { } { } - assign $1\br_taken[0:0] \bc_taken - case - assign $1\br_taken[0:0] 1'0 - end - sync always - update \br_taken $0\br_taken[0:0] - end - attribute \src "issuer_ls180.v:132866.3-132880.6" - process $proc$issuer_ls180.v:132866$6372 - assign { } { } - assign { } { } - assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "issuer_ls180.v:132867.5-132867.29" - switch \initial - attribute \src "issuer_ls180.v:132867.9-132867.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" - switch \br_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000111 - assign { } { } - assign $1\fast1_ok[0:0] \ctr_write - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001000 - assign { } { } - assign $1\fast1_ok[0:0] \ctr_write - case - assign $1\fast1_ok[0:0] 1'0 - end - sync always - update \fast1_ok $0\fast1_ok[0:0] - end - attribute \src "issuer_ls180.v:132881.3-132890.6" - process $proc$issuer_ls180.v:132881$6373 - assign { } { } - assign { } { } - assign $0\fast2$11[63:0]$6374 $1\fast2$11[63:0]$6375 - attribute \src "issuer_ls180.v:132882.5-132882.29" - switch \initial - attribute \src "issuer_ls180.v:132882.9-132882.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" - switch \br_op__lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fast2$11[63:0]$6375 \$48 [63:0] - case - assign $1\fast2$11[63:0]$6375 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fast2$11 $0\fast2$11[63:0]$6374 - end - attribute \src "issuer_ls180.v:132891.3-132900.6" - process $proc$issuer_ls180.v:132891$6376 - assign { } { } - assign { } { } - assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] - attribute \src "issuer_ls180.v:132892.5-132892.29" - switch \initial - attribute \src "issuer_ls180.v:132892.9-132892.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" - switch \br_op__lk - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fast2_ok[0:0] 1'1 - case - assign $1\fast2_ok[0:0] 1'0 - end - sync always - update \fast2_ok $0\fast2_ok[0:0] - end - attribute \src "issuer_ls180.v:132901.3-132915.6" - process $proc$issuer_ls180.v:132901$6377 - assign { } { } - assign { } { } - assign $0\cr_bit[0:0] $1\cr_bit[0:0] - attribute \src "issuer_ls180.v:132902.5-132902.29" - switch \initial - attribute \src "issuer_ls180.v:132902.9-132902.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" - switch \bi - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cr_bit[0:0] \cr_a [3] - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cr_bit[0:0] \cr_a [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\cr_bit[0:0] \cr_a [1] - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-- - assign { } { } - assign $1\cr_bit[0:0] \cr_a [0] - case - assign $1\cr_bit[0:0] 1'0 - end - sync always - update \cr_bit $0\cr_bit[0:0] - end - attribute \src "issuer_ls180.v:132916.3-132928.6" - process $proc$issuer_ls180.v:132916$6378 - assign { } { } - assign { } { } - assign $0\ctr_write[0:0] $1\ctr_write[0:0] - attribute \src "issuer_ls180.v:132917.5-132917.29" - switch \initial - attribute \src "issuer_ls180.v:132917.9-132917.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - switch \bo [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign $1\ctr_write[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\ctr_write[0:0] 1'1 - end - sync always - update \ctr_write $0\ctr_write[0:0] - end - attribute \src "issuer_ls180.v:132929.3-132952.6" - process $proc$issuer_ls180.v:132929$6379 - assign { } { } - assign { } { } - assign $0\bc_taken[0:0] $1\bc_taken[0:0] - attribute \src "issuer_ls180.v:132930.5-132930.29" - switch \initial - attribute \src "issuer_ls180.v:132930.9-132930.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - switch \bo [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\bc_taken[0:0] \$21 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\bc_taken[0:0] $2\bc_taken[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" - switch { \$27 \$25 \$23 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $2\bc_taken[0:0] \$31 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $2\bc_taken[0:0] \$33 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $2\bc_taken[0:0] \ctr_zero_bo1 - case - assign $2\bc_taken[0:0] 1'0 - end - end - sync always - update \bc_taken $0\bc_taken[0:0] - end - attribute \src "issuer_ls180.v:132953.3-132965.6" - process $proc$issuer_ls180.v:132953$6380 - assign { } { } - assign { } { } - assign $0\ctr_n[63:0] $1\ctr_n[63:0] - attribute \src "issuer_ls180.v:132954.5-132954.29" - switch \initial - attribute \src "issuer_ls180.v:132954.9-132954.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - switch \bo [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign $1\ctr_n[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\ctr_n[63:0] \$35 [63:0] - end - sync always - update \ctr_n $0\ctr_n[63:0] - end - attribute \src "issuer_ls180.v:132966.3-132978.6" - process $proc$issuer_ls180.v:132966$6381 - assign { } { } - assign { } { } - assign $0\fast1$10[63:0]$6382 $1\fast1$10[63:0]$6383 - attribute \src "issuer_ls180.v:132967.5-132967.29" - switch \initial - attribute \src "issuer_ls180.v:132967.9-132967.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - switch \bo [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign $1\fast1$10[63:0]$6383 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\fast1$10[63:0]$6383 \ctr_n - end - sync always - update \fast1$10 $0\fast1$10[63:0]$6382 - end - attribute \src "issuer_ls180.v:132979.3-132999.6" - process $proc$issuer_ls180.v:132979$6384 - assign { } { } - assign { } { } - assign $0\ctr_m[63:0] $1\ctr_m[63:0] - attribute \src "issuer_ls180.v:132980.5-132980.29" - switch \initial - attribute \src "issuer_ls180.v:132980.9-132980.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - switch \bo [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign $1\ctr_m[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\ctr_m[63:0] $2\ctr_m[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" - switch \br_op__is_32bit - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ctr_m[63:0] \$38 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\ctr_m[63:0] \fast1 - end - end - sync always - update \ctr_m $0\ctr_m[63:0] - end - attribute \src "issuer_ls180.v:133000.3-133012.6" - process $proc$issuer_ls180.v:133000$6385 - assign { } { } - assign { } { } - assign $0\ctr_zero_bo1[0:0] $1\ctr_zero_bo1[0:0] - attribute \src "issuer_ls180.v:133001.5-133001.29" - switch \initial - attribute \src "issuer_ls180.v:133001.9-133001.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - switch \bo [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign $1\ctr_zero_bo1[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\ctr_zero_bo1[0:0] \$42 - end - sync always - update \ctr_zero_bo1 $0\ctr_zero_bo1[0:0] - end - connect \$12 $eq$issuer_ls180.v:132790$6350_Y - connect \$14 $or$issuer_ls180.v:132791$6351_Y - connect \$17 $add$issuer_ls180.v:132792$6352_Y - connect \$19 $eq$issuer_ls180.v:132793$6353_Y - connect \$21 $or$issuer_ls180.v:132794$6354_Y - connect \$23 $eq$issuer_ls180.v:132795$6355_Y - connect \$25 $eq$issuer_ls180.v:132796$6356_Y - connect \$27 $eq$issuer_ls180.v:132797$6357_Y - connect \$29 $not$issuer_ls180.v:132798$6358_Y - connect \$31 $and$issuer_ls180.v:132799$6359_Y - connect \$33 $and$issuer_ls180.v:132800$6360_Y - connect \$36 $sub$issuer_ls180.v:132801$6361_Y - connect \$38 $pos$issuer_ls180.v:132802$6363_Y - connect \$40 $reduce_or$issuer_ls180.v:132803$6364_Y - connect \$42 $xor$issuer_ls180.v:132804$6365_Y - connect \$44 $not$issuer_ls180.v:132805$6366_Y - connect \$46 $and$issuer_ls180.v:132806$6367_Y - connect \$49 $add$issuer_ls180.v:132807$6368_Y - connect \$16 \$17 - connect \$35 \$36 - connect \$48 \$49 - connect { \br_op__is_32bit$9 \br_op__lk$8 \br_op__imm_data__ok$7 \br_op__imm_data__data$6 \br_op__insn$5 \br_op__fn_unit$4 \br_op__insn_type$3 \br_op__cia$2 } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } - connect \muxid$1 \muxid - connect \nia_ok \br_taken - connect \nia \br_addr - connect \bi \br_op__insn [17:16] - connect \bo \br_op__insn [25:21] -end -attribute \src "issuer_ls180.v:133026.1-133899.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.main" -attribute \generator "nMigen" -module \main$35 - attribute \src "issuer_ls180.v:133864.3-133875.6" - wire width 64 $0\a[63:0] - attribute \src "issuer_ls180.v:133401.3-133412.6" - wire width 64 $0\a_s[63:0] - attribute \src "issuer_ls180.v:133876.3-133887.6" - wire width 64 $0\b[63:0] - attribute \src "issuer_ls180.v:133814.3-133825.6" - wire width 64 $0\b_s[63:0] - attribute \src "issuer_ls180.v:133477.3-133508.6" - wire width 64 $0\fast1$10[63:0]$6428 - attribute \src "issuer_ls180.v:133509.3-133540.6" - wire $0\fast1_ok[0:0] - attribute \src "issuer_ls180.v:133541.3-133612.6" - wire width 64 $0\fast2$11[63:0]$6433 - attribute \src "issuer_ls180.v:133613.3-133644.6" - wire $0\fast2_ok[0:0] - attribute \src "issuer_ls180.v:133027.7-133027.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:133645.3-133813.6" - wire width 64 $0\msr[63:0] - attribute \src "issuer_ls180.v:133645.3-133813.6" - wire $0\msr_ok[0:0] - attribute \src "issuer_ls180.v:133413.3-133444.6" - wire width 64 $0\nia[63:0] - attribute \src "issuer_ls180.v:133445.3-133476.6" - wire $0\nia_ok[0:0] - attribute \src "issuer_ls180.v:133826.3-133844.6" - wire width 64 $0\o[63:0] - attribute \src "issuer_ls180.v:133845.3-133863.6" - wire $0\o_ok[0:0] - attribute \src "issuer_ls180.v:133645.3-133813.6" - wire width 2 $10\msr[5:4] - attribute \src "issuer_ls180.v:133645.3-133813.6" - wire $11\msr[15:15] - attribute \src "issuer_ls180.v:133645.3-133813.6" - wire $12\msr[12:12] - attribute \src "issuer_ls180.v:133645.3-133813.6" - wire $13\msr[60:60] - attribute \src "issuer_ls180.v:133645.3-133813.6" - wire $14\msr[12:12] - attribute \src "issuer_ls180.v:133645.3-133813.6" - wire $15\msr[12:12] - attribute \src "issuer_ls180.v:133645.3-133813.6" - wire width 2 $16\msr[5:4] - attribute \src "issuer_ls180.v:133645.3-133813.6" - wire $17\msr[15:15] - attribute \src "issuer_ls180.v:133645.3-133813.6" - wire width 3 $18\msr[34:32] - attribute \src "issuer_ls180.v:133864.3-133875.6" - wire width 64 $1\a[63:0] - attribute \src "issuer_ls180.v:133401.3-133412.6" - wire width 64 $1\a_s[63:0] - attribute \src "issuer_ls180.v:133876.3-133887.6" - wire width 64 $1\b[63:0] - attribute \src "issuer_ls180.v:133814.3-133825.6" - wire width 64 $1\b_s[63:0] - attribute \src "issuer_ls180.v:133477.3-133508.6" - wire width 64 $1\fast1$10[63:0]$6429 - attribute \src "issuer_ls180.v:133509.3-133540.6" - wire $1\fast1_ok[0:0] - attribute \src "issuer_ls180.v:133541.3-133612.6" - wire width 64 $1\fast2$11[63:0]$6434 - attribute \src "issuer_ls180.v:133613.3-133644.6" - wire $1\fast2_ok[0:0] - attribute \src "issuer_ls180.v:133645.3-133813.6" - wire width 64 $1\msr[63:0] - attribute \src "issuer_ls180.v:133645.3-133813.6" - wire $1\msr_ok[0:0] - attribute \src "issuer_ls180.v:133413.3-133444.6" - wire width 64 $1\nia[63:0] - attribute \src "issuer_ls180.v:133445.3-133476.6" - wire $1\nia_ok[0:0] - attribute \src "issuer_ls180.v:133826.3-133844.6" - wire width 64 $1\o[63:0] - attribute \src "issuer_ls180.v:133845.3-133863.6" - wire $1\o_ok[0:0] - attribute \src "issuer_ls180.v:133477.3-133508.6" - wire width 64 $2\fast1$10[63:0]$6430 - attribute \src "issuer_ls180.v:133509.3-133540.6" - wire $2\fast1_ok[0:0] - attribute \src "issuer_ls180.v:133541.3-133612.6" - wire width 64 $2\fast2$11[63:0]$6435 - attribute \src "issuer_ls180.v:133613.3-133644.6" - wire $2\fast2_ok[0:0] - attribute \src "issuer_ls180.v:133645.3-133813.6" - wire width 64 $2\msr[63:0] - attribute \src "issuer_ls180.v:133645.3-133813.6" - wire $2\msr_ok[0:0] - attribute \src "issuer_ls180.v:133413.3-133444.6" - wire width 64 $2\nia[63:0] - attribute \src "issuer_ls180.v:133445.3-133476.6" - wire $2\nia_ok[0:0] - attribute \src "issuer_ls180.v:133541.3-133612.6" - wire $3\fast2$11[17:17]$6436 - attribute \src "issuer_ls180.v:133645.3-133813.6" - wire width 11 $3\msr[11:1] - attribute \src "issuer_ls180.v:133541.3-133612.6" - wire $4\fast2$11[18:18]$6437 - attribute \src "issuer_ls180.v:133645.3-133813.6" - wire width 47 $4\msr[59:13] - attribute \src "issuer_ls180.v:133541.3-133612.6" - wire $5\fast2$11[20:20]$6438 - attribute \src "issuer_ls180.v:133645.3-133813.6" - wire width 3 $5\msr[63:61] - attribute \src "issuer_ls180.v:133541.3-133612.6" - wire $6\fast2$11[16:16]$6439 - attribute \src "issuer_ls180.v:133645.3-133813.6" - wire width 11 $6\msr[11:1] - attribute \src "issuer_ls180.v:133541.3-133612.6" - wire $7\fast2$11[19:19]$6440 - attribute \src "issuer_ls180.v:133645.3-133813.6" - wire width 47 $7\msr[59:13] - attribute \src "issuer_ls180.v:133645.3-133813.6" - wire width 3 $8\msr[63:61] - attribute \src "issuer_ls180.v:133645.3-133813.6" - wire width 3 $9\msr[34:32] - attribute \src "issuer_ls180.v:133381.18-133381.113" - wire width 65 $add$issuer_ls180.v:133381$6403_Y - attribute \src "issuer_ls180.v:133375.18-133375.108" - wire width 5 $and$issuer_ls180.v:133375$6396_Y - attribute \src "issuer_ls180.v:133383.18-133383.118" - wire width 7 $and$issuer_ls180.v:133383$6405_Y - attribute \src "issuer_ls180.v:133385.18-133385.118" - wire width 7 $and$issuer_ls180.v:133385$6407_Y - attribute \src "issuer_ls180.v:133387.18-133387.118" - wire width 7 $and$issuer_ls180.v:133387$6409_Y - attribute \src "issuer_ls180.v:133389.18-133389.119" - wire width 7 $and$issuer_ls180.v:133389$6411_Y - attribute \src "issuer_ls180.v:133395.18-133395.106" - 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connect \Y $and$issuer_ls180.v:133383$6405_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194" - cell $and $and$issuer_ls180.v:133385$6407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 7 - connect \A \trap_op__traptype - connect \B 1'1 - connect \Y $and$issuer_ls180.v:133385$6407_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196" - cell $and $and$issuer_ls180.v:133387$6409 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 7 - connect \A \trap_op__traptype - connect \B 4'1000 - connect \Y $and$issuer_ls180.v:133387$6409_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" - cell $and $and$issuer_ls180.v:133389$6411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 7 - connect \A \trap_op__traptype - connect \B 7'1000000 - connect \Y $and$issuer_ls180.v:133389$6411_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" - cell $and $and$issuer_ls180.v:133395$6418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$63 - connect \B \$65 - connect \Y $and$issuer_ls180.v:133395$6418_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" - cell $and $and$issuer_ls180.v:133400$6423 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$73 - connect \B \$75 - connect \Y $and$issuer_ls180.v:133400$6423_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" - cell $eq $eq$issuer_ls180.v:133374$6395 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \a - connect \B \b - connect \Y $eq$issuer_ls180.v:133374$6395_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $eq $eq$issuer_ls180.v:133382$6404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \trap_op__traptype - connect \B 1'0 - connect \Y $eq$issuer_ls180.v:133382$6404_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225" - cell $eq $eq$issuer_ls180.v:133392$6415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \trap_op__insn_type - connect \B 7'1001000 - connect \Y $eq$issuer_ls180.v:133392$6415_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:231" - cell $eq $eq$issuer_ls180.v:133393$6416 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \trap_op__msr [34:32] - connect \B 3'010 - connect \Y $eq$issuer_ls180.v:133393$6416_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" - cell $eq $eq$issuer_ls180.v:133394$6417 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \ra [34:32] - connect \B 3'000 - connect \Y $eq$issuer_ls180.v:133394$6417_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:286" - cell $eq $eq$issuer_ls180.v:133398$6421 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \trap_op__msr [34:32] - connect \B 3'010 - connect \Y $eq$issuer_ls180.v:133398$6421_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" - cell $eq $eq$issuer_ls180.v:133399$6422 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \fast2 [34:32] - connect \B 3'000 - connect \Y $eq$issuer_ls180.v:133399$6422_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$issuer_ls180.v:133368$6387 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \ra [31:0] - connect \Y $extend$issuer_ls180.v:133368$6387_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$issuer_ls180.v:133369$6389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \rb [31:0] - connect \Y $extend$issuer_ls180.v:133369$6389_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" - cell $pos $extend$issuer_ls180.v:133380$6401 - parameter \A_SIGNED 0 - parameter \A_WIDTH 20 - parameter \Y_WIDTH 64 - connect \A \$35 - connect \Y $extend$issuer_ls180.v:133380$6401_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $extend$issuer_ls180.v:133391$6413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \trap_op__msr - connect \Y $extend$issuer_ls180.v:133391$6413_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" - cell $gt $gt$issuer_ls180.v:133371$6392 - parameter \A_SIGNED 1 - parameter \A_WIDTH 64 - parameter \B_SIGNED 1 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \a_s - connect \B \b_s - connect \Y $gt$issuer_ls180.v:133371$6392_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" - cell $gt $gt$issuer_ls180.v:133373$6394 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \a - connect \B \b - connect \Y $gt$issuer_ls180.v:133373$6394_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:162" - cell $lt $lt$issuer_ls180.v:133370$6391 - parameter \A_SIGNED 1 - parameter \A_WIDTH 64 - parameter \B_SIGNED 1 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \a_s - connect \B \b_s - connect \Y $lt$issuer_ls180.v:133370$6391_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" - cell $lt $lt$issuer_ls180.v:133372$6393 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \a - connect \B \b - connect \Y $lt$issuer_ls180.v:133372$6393_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:247" - cell $not $not$issuer_ls180.v:133396$6419 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \trap_op__msr [60] - connect \Y $not$issuer_ls180.v:133396$6419_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" - cell $not $not$issuer_ls180.v:133397$6420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \trap_op__insn [9] - connect \Y $not$issuer_ls180.v:133397$6420_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" - cell $or $or$issuer_ls180.v:133378$6399 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$26 - connect \B \$30 - connect \Y $or$issuer_ls180.v:133378$6399_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$issuer_ls180.v:133368$6388 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:133368$6387_Y - connect \Y $pos$issuer_ls180.v:133368$6388_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$issuer_ls180.v:133369$6390 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:133369$6389_Y - connect \Y $pos$issuer_ls180.v:133369$6390_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" - cell $pos $pos$issuer_ls180.v:133380$6402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:133380$6401_Y - connect \Y $pos$issuer_ls180.v:133380$6402_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $pos$issuer_ls180.v:133391$6414 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$issuer_ls180.v:133391$6413_Y - connect \Y $pos$issuer_ls180.v:133391$6414_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" - cell $reduce_or $reduce_or$issuer_ls180.v:133376$6397 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \$27 - connect \Y $reduce_or$issuer_ls180.v:133376$6397_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" - cell $reduce_or $reduce_or$issuer_ls180.v:133377$6398 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \trap_op__traptype - connect \Y $reduce_or$issuer_ls180.v:133377$6398_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$issuer_ls180.v:133384$6406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \$44 - connect \Y $reduce_or$issuer_ls180.v:133384$6406_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$issuer_ls180.v:133386$6408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \$48 - connect \Y $reduce_or$issuer_ls180.v:133386$6408_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$issuer_ls180.v:133388$6410 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \$52 - connect \Y $reduce_or$issuer_ls180.v:133388$6410_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$issuer_ls180.v:133390$6412 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \$56 - connect \Y $reduce_or$issuer_ls180.v:133390$6412_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" - cell $sshl $sshl$issuer_ls180.v:133379$6400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 20 - connect \A \trap_op__trapaddr - connect \B 3'100 - connect \Y $sshl$issuer_ls180.v:133379$6400_Y - end - attribute \src "issuer_ls180.v:133027.7-133027.20" - process $proc$issuer_ls180.v:133027$6448 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:133401.3-133412.6" - process $proc$issuer_ls180.v:133401$6424 - assign { } { } - assign $0\a_s[63:0] $1\a_s[63:0] - attribute \src "issuer_ls180.v:133402.5-133402.29" - switch \initial - attribute \src "issuer_ls180.v:133402.9-133402.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" - switch \trap_op__is_32bit - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\a_s[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\a_s[63:0] \ra - end - sync always - update \a_s $0\a_s[63:0] - end - attribute \src "issuer_ls180.v:133413.3-133444.6" - process $proc$issuer_ls180.v:133413$6425 - assign { } { } - assign { } { } - assign $0\nia[63:0] $1\nia[63:0] - attribute \src "issuer_ls180.v:133414.5-133414.29" - switch \initial - attribute \src "issuer_ls180.v:133414.9-133414.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0111111 - assign { } { } - assign $1\nia[63:0] $2\nia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - switch \should_trap - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\nia[63:0] \$34 - case - assign $2\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000111 - assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000110 - assign { } { } - assign $1\nia[63:0] { \fast1 [63:2] 2'00 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1001001 - assign { } { } - assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000110000000000 - case - assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \nia $0\nia[63:0] - end - attribute \src "issuer_ls180.v:133445.3-133476.6" - process $proc$issuer_ls180.v:133445$6426 - assign { } { } - assign { } { } - assign $0\nia_ok[0:0] $1\nia_ok[0:0] - attribute \src "issuer_ls180.v:133446.5-133446.29" - switch \initial - attribute \src "issuer_ls180.v:133446.9-133446.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0111111 - assign { } { } - assign $1\nia_ok[0:0] $2\nia_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - switch \should_trap - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\nia_ok[0:0] 1'1 - case - assign $2\nia_ok[0:0] 1'0 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign $1\nia_ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000111 - assign $1\nia_ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000110 - assign { } { } - assign $1\nia_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1001001 - assign { } { } - assign $1\nia_ok[0:0] 1'1 - case - assign $1\nia_ok[0:0] 1'0 - end - sync always - update \nia_ok $0\nia_ok[0:0] - end - attribute \src "issuer_ls180.v:133477.3-133508.6" - process $proc$issuer_ls180.v:133477$6427 - assign { } { } - assign { } { } - assign $0\fast1$10[63:0]$6428 $1\fast1$10[63:0]$6429 - attribute \src "issuer_ls180.v:133478.5-133478.29" - switch \initial - attribute \src "issuer_ls180.v:133478.9-133478.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0111111 - assign { } { } - assign $1\fast1$10[63:0]$6429 $2\fast1$10[63:0]$6430 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - switch \should_trap - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fast1$10[63:0]$6430 \trap_op__cia - case - assign $2\fast1$10[63:0]$6430 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign $1\fast1$10[63:0]$6429 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000111 - assign $1\fast1$10[63:0]$6429 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000110 - assign $1\fast1$10[63:0]$6429 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1001001 - assign { } { } - assign $1\fast1$10[63:0]$6429 \$38 [63:0] - case - assign $1\fast1$10[63:0]$6429 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fast1$10 $0\fast1$10[63:0]$6428 - end - attribute \src "issuer_ls180.v:133509.3-133540.6" - process $proc$issuer_ls180.v:133509$6431 - assign { } { } - assign { } { } - assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "issuer_ls180.v:133510.5-133510.29" - switch \initial - attribute \src "issuer_ls180.v:133510.9-133510.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0111111 - assign { } { } - assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - switch \should_trap - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fast1_ok[0:0] 1'1 - case - assign $2\fast1_ok[0:0] 1'0 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign $1\fast1_ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000111 - assign $1\fast1_ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000110 - assign $1\fast1_ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1001001 - assign { } { } - assign $1\fast1_ok[0:0] 1'1 - case - assign $1\fast1_ok[0:0] 1'0 - end - sync always - update \fast1_ok $0\fast1_ok[0:0] - end - attribute \src "issuer_ls180.v:133541.3-133612.6" - process $proc$issuer_ls180.v:133541$6432 - assign { } { } - assign { } { } - assign $0\fast2$11[63:0]$6433 $1\fast2$11[63:0]$6434 - attribute \src "issuer_ls180.v:133542.5-133542.29" - switch \initial - attribute \src "issuer_ls180.v:133542.9-133542.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0111111 - assign { } { } - assign $1\fast2$11[63:0]$6434 $2\fast2$11[63:0]$6435 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - switch \should_trap - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { $2\fast2$11[63:0]$6435 [30:27] $2\fast2$11[63:0]$6435 [21] } 5'00000 - assign $2\fast2$11[63:0]$6435 [15:0] \trap_op__msr [15:0] - assign $2\fast2$11[63:0]$6435 [26:22] \trap_op__msr [26:22] - assign $2\fast2$11[63:0]$6435 [63:31] \trap_op__msr [63:31] - assign $2\fast2$11[63:0]$6435 [17] $3\fast2$11[17:17]$6436 - assign $2\fast2$11[63:0]$6435 [18] $4\fast2$11[18:18]$6437 - assign $2\fast2$11[63:0]$6435 [20] $5\fast2$11[20:20]$6438 - assign $2\fast2$11[63:0]$6435 [16] $6\fast2$11[16:16]$6439 - assign $2\fast2$11[63:0]$6435 [19] $7\fast2$11[19:19]$6440 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - switch \$41 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fast2$11[17:17]$6436 1'1 - case - assign $3\fast2$11[17:17]$6436 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192" - switch \$43 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fast2$11[18:18]$6437 1'1 - case - assign $4\fast2$11[18:18]$6437 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194" - switch \$47 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\fast2$11[20:20]$6438 1'1 - case - assign $5\fast2$11[20:20]$6438 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196" - switch \$51 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\fast2$11[16:16]$6439 1'1 - case - assign $6\fast2$11[16:16]$6439 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" - switch \$55 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\fast2$11[19:19]$6440 1'1 - case - assign $7\fast2$11[19:19]$6440 1'0 - end - case - assign $2\fast2$11[63:0]$6435 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign $1\fast2$11[63:0]$6434 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000111 - assign $1\fast2$11[63:0]$6434 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000110 - assign $1\fast2$11[63:0]$6434 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1001001 - assign { } { } - assign { $1\fast2$11[63:0]$6434 [30:27] $1\fast2$11[63:0]$6434 [21:16] } 10'0000000000 - assign $1\fast2$11[63:0]$6434 [15:0] \trap_op__msr [15:0] - assign $1\fast2$11[63:0]$6434 [26:22] \trap_op__msr [26:22] - assign $1\fast2$11[63:0]$6434 [63:31] \trap_op__msr [63:31] - case - assign $1\fast2$11[63:0]$6434 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fast2$11 $0\fast2$11[63:0]$6433 - end - attribute \src "issuer_ls180.v:133613.3-133644.6" - process $proc$issuer_ls180.v:133613$6441 - assign { } { } - assign { } { } - assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] - attribute \src "issuer_ls180.v:133614.5-133614.29" - switch \initial - attribute \src "issuer_ls180.v:133614.9-133614.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0111111 - assign { } { } - assign $1\fast2_ok[0:0] $2\fast2_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - switch \should_trap - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fast2_ok[0:0] 1'1 - case - assign $2\fast2_ok[0:0] 1'0 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign $1\fast2_ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000111 - assign $1\fast2_ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000110 - assign $1\fast2_ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1001001 - assign { } { } - assign $1\fast2_ok[0:0] 1'1 - case - assign $1\fast2_ok[0:0] 1'0 - end - sync always - update \fast2_ok $0\fast2_ok[0:0] - end - attribute \src "issuer_ls180.v:133645.3-133813.6" - process $proc$issuer_ls180.v:133645$6442 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\msr[63:0] $1\msr[63:0] - assign $0\msr_ok[0:0] $1\msr_ok[0:0] - attribute \src "issuer_ls180.v:133646.5-133646.29" - switch \initial - attribute \src "issuer_ls180.v:133646.9-133646.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0111111 - assign { } { } - assign { } { } - assign $1\msr[63:0] $2\msr[63:0] - assign $1\msr_ok[0:0] $2\msr_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - switch \should_trap - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\msr[63:0] [62:59] $2\msr[63:0] [57:33] $2\msr[63:0] [31:26] $2\msr[63:0] [24] $2\msr[63:0] [22:16] $2\msr[63:0] [12] $2\msr[63:0] [7:6] $2\msr[63:0] [2] } { \trap_op__msr [62:59] \trap_op__msr [57:33] \trap_op__msr [31:26] \trap_op__msr [24] \trap_op__msr [22:16] \trap_op__msr [12] \trap_op__msr [7:6] \trap_op__msr [2] } - assign $2\msr[63:0] [63] 1'1 - assign $2\msr[63:0] [15] 1'0 - assign $2\msr[63:0] [14] 1'0 - assign $2\msr[63:0] [5] 1'0 - assign $2\msr[63:0] [4] 1'0 - assign $2\msr[63:0] [1] 1'0 - assign $2\msr[63:0] [0] 1'1 - assign $2\msr[63:0] [11] 1'0 - assign $2\msr[63:0] [8] 1'0 - assign $2\msr[63:0] [23] 1'0 - assign $2\msr[63:0] [32] 1'0 - assign $2\msr[63:0] [25] 1'0 - assign $2\msr[63:0] [13] 1'0 - assign $2\msr[63:0] [3] 1'0 - assign $2\msr[63:0] [10] 1'0 - assign $2\msr[63:0] [9] 1'0 - assign $2\msr[63:0] [58] 1'0 - assign $2\msr_ok[0:0] 1'1 - case - assign $2\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\msr_ok[0:0] 1'0 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign { } { } - assign { } { } - assign $1\msr[63:0] [0] \$59 [0] - assign $1\msr[63:0] [11:1] $3\msr[11:1] - assign $1\msr[63:0] [59:13] $4\msr[59:13] - assign $1\msr[63:0] [63:61] $5\msr[63:61] - assign $1\msr[63:0] [12] $12\msr[12:12] - assign $1\msr[63:0] [60] $13\msr[60:60] - assign $1\msr_ok[0:0] 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218" - switch \trap_op__insn [21] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign $3\msr[11:1] [10:1] \$59 [11:2] - assign { $4\msr[59:13] [46:3] $4\msr[59:13] [1:0] } { \$59 [59:16] \$59 [14:13] } - assign $5\msr[63:61] \$59 [63:61] - assign $3\msr[11:1] [0] \ra [1] - assign $4\msr[59:13] [2] \ra [15] - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { $3\msr[11:1] [10:5] $3\msr[11:1] [2:0] } { $6\msr[11:1] [10:5] $6\msr[11:1] [2:0] } - assign { $4\msr[59:13] [46:3] $4\msr[59:13] [1:0] } { $7\msr[59:13] [46:3] $7\msr[59:13] [1:0] } - assign $5\msr[63:61] $8\msr[63:61] - assign $3\msr[11:1] [4:3] $10\msr[5:4] - assign $4\msr[59:13] [2] $11\msr[15:15] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225" - switch \$61 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign $6\msr[11:1] \ra [11:1] - assign { $7\msr[59:13] [46:22] $7\msr[59:13] [18:0] } { \ra [59:35] \ra [31:13] } - assign $8\msr[63:61] \ra [63:61] - assign $7\msr[59:13] [21:19] $9\msr[34:32] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" - switch \$67 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $9\msr[34:32] \trap_op__msr [34:32] - case - assign $9\msr[34:32] \ra [34:32] - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $7\msr[59:13] [46:19] \$59 [59:32] - assign $8\msr[63:61] \$59 [63:61] - assign $6\msr[11:1] \ra [11:1] - assign $7\msr[59:13] [18:0] \ra [31:13] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48" - switch $7\msr[59:13] [1] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $11\msr[15:15] 1'1 - assign $10\msr[5:4] [1] 1'1 - assign $10\msr[5:4] [0] 1'1 - case - assign $10\msr[5:4] $6\msr[11:1] [4:3] - assign $11\msr[15:15] $7\msr[59:13] [2] - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:247" - switch \$69 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $13\msr[60:60] \trap_op__msr [60] - assign $12\msr[12:12] \trap_op__msr [12] - case - assign $12\msr[12:12] \$59 [12] - assign $13\msr[60:60] \$59 [60] - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000111 - assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\msr_ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000110 - assign { $1\msr[63:0] [30:27] $1\msr[63:0] [21:16] } 10'0000000000 - assign { } { } - assign { $1\msr[63:0] [14:13] $1\msr[63:0] [11:6] $1\msr[63:0] [3:0] } { \fast2 [14:13] \fast2 [11:6] \fast2 [3:0] } - assign $1\msr[63:0] [26:22] \fast2 [26:22] - assign { $1\msr[63:0] [63:35] $1\msr[63:0] [31] } { \fast2 [63:35] \fast2 [31] } - assign $1\msr[63:0] [12] $14\msr[12:12] - assign $1\msr[63:0] [5:4] $16\msr[5:4] - assign $1\msr[63:0] [15] $17\msr[15:15] - assign $1\msr[63:0] [34:32] $18\msr[34:32] - assign $1\msr_ok[0:0] 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" - switch \$71 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $14\msr[12:12] $15\msr[12:12] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:274" - switch \trap_op__msr [60] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $15\msr[12:12] \fast2 [12] - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $15\msr[12:12] \trap_op__msr [12] - end - case - assign $14\msr[12:12] \fast2 [12] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48" - switch \fast2 [14] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $17\msr[15:15] 1'1 - assign $16\msr[5:4] [1] 1'1 - assign $16\msr[5:4] [0] 1'1 - case - assign $16\msr[5:4] \fast2 [5:4] - assign $17\msr[15:15] \fast2 [15] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" - switch \$77 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $18\msr[34:32] \trap_op__msr [34:32] - case - assign $18\msr[34:32] \fast2 [34:32] - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1001001 - assign { } { } - assign { } { } - assign { $1\msr[63:0] [62:59] $1\msr[63:0] [57:33] $1\msr[63:0] [31:26] $1\msr[63:0] [24] $1\msr[63:0] [22:16] $1\msr[63:0] [12] $1\msr[63:0] [7:6] $1\msr[63:0] [2] } { \trap_op__msr [62:59] \trap_op__msr [57:33] \trap_op__msr [31:26] \trap_op__msr [24] \trap_op__msr [22:16] \trap_op__msr [12] \trap_op__msr [7:6] \trap_op__msr [2] } - assign $1\msr[63:0] [63] 1'1 - assign $1\msr[63:0] [15] 1'0 - assign $1\msr[63:0] [14] 1'0 - assign $1\msr[63:0] [5] 1'0 - assign $1\msr[63:0] [4] 1'0 - assign $1\msr[63:0] [1] 1'0 - assign $1\msr[63:0] [0] 1'1 - assign $1\msr[63:0] [11] 1'0 - assign $1\msr[63:0] [8] 1'0 - assign $1\msr[63:0] [23] 1'0 - assign $1\msr[63:0] [32] 1'0 - assign $1\msr[63:0] [25] 1'0 - assign $1\msr[63:0] [13] 1'0 - assign $1\msr[63:0] [3] 1'0 - assign $1\msr[63:0] [10] 1'0 - assign $1\msr[63:0] [9] 1'0 - assign $1\msr[63:0] [58] 1'0 - assign $1\msr_ok[0:0] 1'1 - case - assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\msr_ok[0:0] 1'0 - end - sync always - update \msr $0\msr[63:0] - update \msr_ok $0\msr_ok[0:0] - end - attribute \src "issuer_ls180.v:133814.3-133825.6" - process $proc$issuer_ls180.v:133814$6443 - assign { } { } - assign $0\b_s[63:0] $1\b_s[63:0] - attribute \src "issuer_ls180.v:133815.5-133815.29" - switch \initial - attribute \src "issuer_ls180.v:133815.9-133815.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" - switch \trap_op__is_32bit - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\b_s[63:0] { \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31:0] } - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\b_s[63:0] \rb - end - sync always - update \b_s $0\b_s[63:0] - end - attribute \src "issuer_ls180.v:133826.3-133844.6" - process $proc$issuer_ls180.v:133826$6444 - assign { } { } - assign { } { } - assign $0\o[63:0] $1\o[63:0] - attribute \src "issuer_ls180.v:133827.5-133827.29" - switch \initial - attribute \src "issuer_ls180.v:133827.9-133827.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0111111 - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000111 - assign { } { } - assign $1\o[63:0] \trap_op__msr - case - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \o $0\o[63:0] - end - attribute \src "issuer_ls180.v:133845.3-133863.6" - process $proc$issuer_ls180.v:133845$6445 - assign { } { } - assign { } { } - assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "issuer_ls180.v:133846.5-133846.29" - switch \initial - attribute \src "issuer_ls180.v:133846.9-133846.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0111111 - assign $1\o_ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign $1\o_ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000111 - assign { } { } - assign $1\o_ok[0:0] 1'1 - case - assign $1\o_ok[0:0] 1'0 - end - sync always - update \o_ok $0\o_ok[0:0] - end - attribute \src "issuer_ls180.v:133864.3-133875.6" - process $proc$issuer_ls180.v:133864$6446 - assign { } { } - assign $0\a[63:0] $1\a[63:0] - attribute \src "issuer_ls180.v:133865.5-133865.29" - switch \initial - attribute \src "issuer_ls180.v:133865.9-133865.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" - switch \trap_op__is_32bit - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\a[63:0] \$12 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\a[63:0] \ra - end - sync always - update \a $0\a[63:0] - end - attribute \src "issuer_ls180.v:133876.3-133887.6" - process $proc$issuer_ls180.v:133876$6447 - assign { } { } - assign $0\b[63:0] $1\b[63:0] - attribute \src "issuer_ls180.v:133877.5-133877.29" - switch \initial - attribute \src "issuer_ls180.v:133877.9-133877.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" - switch \trap_op__is_32bit - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\b[63:0] \$14 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\b[63:0] \rb - end - sync always - update \b $0\b[63:0] - end - connect \$12 $pos$issuer_ls180.v:133368$6388_Y - connect \$14 $pos$issuer_ls180.v:133369$6390_Y - connect \$16 $lt$issuer_ls180.v:133370$6391_Y - connect \$18 $gt$issuer_ls180.v:133371$6392_Y - connect \$20 $lt$issuer_ls180.v:133372$6393_Y - connect \$22 $gt$issuer_ls180.v:133373$6394_Y - connect \$24 $eq$issuer_ls180.v:133374$6395_Y - connect \$27 $and$issuer_ls180.v:133375$6396_Y - connect \$26 $reduce_or$issuer_ls180.v:133376$6397_Y - connect \$30 $reduce_or$issuer_ls180.v:133377$6398_Y - connect \$32 $or$issuer_ls180.v:133378$6399_Y - connect \$35 $sshl$issuer_ls180.v:133379$6400_Y - connect \$34 $pos$issuer_ls180.v:133380$6402_Y - connect \$39 $add$issuer_ls180.v:133381$6403_Y - connect \$41 $eq$issuer_ls180.v:133382$6404_Y - connect \$44 $and$issuer_ls180.v:133383$6405_Y - connect \$43 $reduce_or$issuer_ls180.v:133384$6406_Y - connect \$48 $and$issuer_ls180.v:133385$6407_Y - connect \$47 $reduce_or$issuer_ls180.v:133386$6408_Y - connect \$52 $and$issuer_ls180.v:133387$6409_Y - connect \$51 $reduce_or$issuer_ls180.v:133388$6410_Y - connect \$56 $and$issuer_ls180.v:133389$6411_Y - connect \$55 $reduce_or$issuer_ls180.v:133390$6412_Y - connect \$59 $pos$issuer_ls180.v:133391$6414_Y - connect \$61 $eq$issuer_ls180.v:133392$6415_Y - connect \$63 $eq$issuer_ls180.v:133393$6416_Y - connect \$65 $eq$issuer_ls180.v:133394$6417_Y - connect \$67 $and$issuer_ls180.v:133395$6418_Y - connect \$69 $not$issuer_ls180.v:133396$6419_Y - connect \$71 $not$issuer_ls180.v:133397$6420_Y - connect \$73 $eq$issuer_ls180.v:133398$6421_Y - connect \$75 $eq$issuer_ls180.v:133399$6422_Y - connect \$77 $and$issuer_ls180.v:133400$6423_Y - connect \$38 \$39 - connect { \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } - connect \muxid$1 \muxid - connect \should_trap \$32 - connect \trap_bits { \lt_s \gt_s \equal \lt_u \gt_u } - connect \equal \$24 - connect \gt_u \$22 - connect \lt_u \$20 - connect \gt_s \$18 - connect \lt_s \$16 - connect \to \trap_op__insn [25:21] -end -attribute \src "issuer_ls180.v:133903.1-134646.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.main" -attribute \generator "nMigen" -module \main$48 - attribute \src "issuer_ls180.v:134613.3-134623.6" - wire width 32 $0\a32[31:0] - attribute \src "issuer_ls180.v:134558.3-134568.6" - wire width 64 $0\b[63:0] - attribute \src "issuer_ls180.v:134536.3-134546.6" - wire width 64 $0\bpermd_rb[63:0] - attribute \src "issuer_ls180.v:134525.3-134535.6" - wire width 64 $0\bpermd_rs[63:0] - attribute \src "issuer_ls180.v:134514.3-134524.6" - wire width 64 $0\clz_sig_in[63:0] - attribute \src "issuer_ls180.v:134624.3-134642.6" - wire width 64 $0\cntz_i[63:0] - attribute \src "issuer_ls180.v:134602.3-134612.6" - wire $0\count_right[0:0] - attribute \src "issuer_ls180.v:133904.7-133904.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:134459.3-134513.6" - wire width 64 $0\o[63:0] - attribute \src "issuer_ls180.v:134459.3-134513.6" - wire $0\o_ok[0:0] - attribute \src "issuer_ls180.v:134580.3-134590.6" - wire $0\par0[0:0] - attribute \src "issuer_ls180.v:134591.3-134601.6" - wire $0\par1[0:0] - attribute \src "issuer_ls180.v:134547.3-134557.6" - wire width 64 $0\popcount_a[63:0] - attribute \src "issuer_ls180.v:134569.3-134579.6" - wire width 64 $0\popcount_data_len[63:0] - attribute \src "issuer_ls180.v:134613.3-134623.6" - wire width 32 $1\a32[31:0] - attribute \src "issuer_ls180.v:134558.3-134568.6" - wire width 64 $1\b[63:0] - attribute \src "issuer_ls180.v:134536.3-134546.6" - wire width 64 $1\bpermd_rb[63:0] - attribute \src "issuer_ls180.v:134525.3-134535.6" - wire width 64 $1\bpermd_rs[63:0] - attribute \src "issuer_ls180.v:134514.3-134524.6" - wire width 64 $1\clz_sig_in[63:0] - attribute \src "issuer_ls180.v:134624.3-134642.6" - wire width 64 $1\cntz_i[63:0] - attribute \src "issuer_ls180.v:134602.3-134612.6" - wire $1\count_right[0:0] - attribute \src "issuer_ls180.v:134459.3-134513.6" - wire width 64 $1\o[63:0] - attribute \src "issuer_ls180.v:134459.3-134513.6" - wire $1\o_ok[0:0] - attribute \src "issuer_ls180.v:134580.3-134590.6" - wire $1\par0[0:0] - attribute \src "issuer_ls180.v:134591.3-134601.6" - wire $1\par1[0:0] - attribute \src "issuer_ls180.v:134547.3-134557.6" - wire width 64 $1\popcount_a[63:0] - attribute \src "issuer_ls180.v:134569.3-134579.6" - wire width 64 $1\popcount_data_len[63:0] - attribute \src "issuer_ls180.v:134624.3-134642.6" - wire width 64 $2\cntz_i[63:0] - attribute \src "issuer_ls180.v:134459.3-134513.6" - wire width 64 $2\o[63:0] - attribute \src "issuer_ls180.v:134406.18-134406.103" - wire width 64 $and$issuer_ls180.v:134406$6495_Y - attribute \src "issuer_ls180.v:134365.18-134365.118" - wire $eq$issuer_ls180.v:134365$6449_Y - attribute \src "issuer_ls180.v:134366.19-134366.119" - wire $eq$issuer_ls180.v:134366$6450_Y - attribute \src "issuer_ls180.v:134367.19-134367.119" - wire $eq$issuer_ls180.v:134367$6451_Y - attribute \src "issuer_ls180.v:134368.19-134368.119" - wire $eq$issuer_ls180.v:134368$6452_Y - attribute \src "issuer_ls180.v:134369.19-134369.119" - wire $eq$issuer_ls180.v:134369$6453_Y - attribute \src "issuer_ls180.v:134370.19-134370.119" - wire $eq$issuer_ls180.v:134370$6454_Y - attribute \src "issuer_ls180.v:134371.19-134371.119" - wire $eq$issuer_ls180.v:134371$6455_Y - attribute \src "issuer_ls180.v:134372.19-134372.119" - wire $eq$issuer_ls180.v:134372$6456_Y - attribute \src "issuer_ls180.v:134373.19-134373.119" - wire $eq$issuer_ls180.v:134373$6457_Y - attribute \src "issuer_ls180.v:134374.19-134374.119" - wire $eq$issuer_ls180.v:134374$6458_Y - attribute \src "issuer_ls180.v:134375.19-134375.119" - wire $eq$issuer_ls180.v:134375$6459_Y - attribute \src "issuer_ls180.v:134376.19-134376.119" - wire $eq$issuer_ls180.v:134376$6460_Y - attribute \src "issuer_ls180.v:134377.19-134377.119" - wire $eq$issuer_ls180.v:134377$6461_Y - attribute \src "issuer_ls180.v:134378.19-134378.119" - wire $eq$issuer_ls180.v:134378$6462_Y - attribute \src "issuer_ls180.v:134379.19-134379.119" - wire $eq$issuer_ls180.v:134379$6463_Y - attribute \src "issuer_ls180.v:134380.19-134380.119" - wire $eq$issuer_ls180.v:134380$6464_Y - attribute \src "issuer_ls180.v:134381.19-134381.119" - wire $eq$issuer_ls180.v:134381$6465_Y - attribute \src "issuer_ls180.v:134382.19-134382.119" - wire $eq$issuer_ls180.v:134382$6466_Y - attribute \src "issuer_ls180.v:134383.19-134383.119" - wire $eq$issuer_ls180.v:134383$6467_Y - attribute \src "issuer_ls180.v:134384.19-134384.119" - wire $eq$issuer_ls180.v:134384$6468_Y - attribute \src "issuer_ls180.v:134385.19-134385.119" - wire $eq$issuer_ls180.v:134385$6469_Y - attribute \src "issuer_ls180.v:134386.19-134386.119" - wire $eq$issuer_ls180.v:134386$6470_Y - attribute \src "issuer_ls180.v:134387.19-134387.119" - wire $eq$issuer_ls180.v:134387$6471_Y - attribute \src "issuer_ls180.v:134388.19-134388.119" - wire $eq$issuer_ls180.v:134388$6472_Y - attribute \src "issuer_ls180.v:134389.19-134389.119" - wire $eq$issuer_ls180.v:134389$6473_Y - attribute \src "issuer_ls180.v:134390.19-134390.119" - wire $eq$issuer_ls180.v:134390$6474_Y - attribute \src "issuer_ls180.v:134391.19-134391.119" - wire $eq$issuer_ls180.v:134391$6475_Y - attribute \src "issuer_ls180.v:134392.19-134392.119" - wire $eq$issuer_ls180.v:134392$6476_Y - attribute \src "issuer_ls180.v:134393.19-134393.128" - wire $eq$issuer_ls180.v:134393$6477_Y - attribute \src "issuer_ls180.v:134409.18-134409.114" - wire $eq$issuer_ls180.v:134409$6498_Y - attribute \src "issuer_ls180.v:134410.18-134410.114" - wire $eq$issuer_ls180.v:134410$6499_Y - attribute \src "issuer_ls180.v:134411.18-134411.114" - wire $eq$issuer_ls180.v:134411$6500_Y - attribute \src "issuer_ls180.v:134412.18-134412.114" - wire $eq$issuer_ls180.v:134412$6501_Y - attribute \src "issuer_ls180.v:134413.18-134413.114" - wire $eq$issuer_ls180.v:134413$6502_Y - attribute \src "issuer_ls180.v:134414.18-134414.114" - wire $eq$issuer_ls180.v:134414$6503_Y - attribute \src "issuer_ls180.v:134415.18-134415.114" - wire $eq$issuer_ls180.v:134415$6504_Y - attribute \src "issuer_ls180.v:134416.18-134416.114" - wire $eq$issuer_ls180.v:134416$6505_Y - attribute \src "issuer_ls180.v:134417.18-134417.116" - wire $eq$issuer_ls180.v:134417$6506_Y - attribute \src "issuer_ls180.v:134418.18-134418.116" - wire $eq$issuer_ls180.v:134418$6507_Y - attribute \src "issuer_ls180.v:134419.18-134419.116" - wire $eq$issuer_ls180.v:134419$6508_Y - attribute \src "issuer_ls180.v:134420.18-134420.116" - wire $eq$issuer_ls180.v:134420$6509_Y - attribute \src "issuer_ls180.v:134421.18-134421.116" - wire $eq$issuer_ls180.v:134421$6510_Y - attribute \src "issuer_ls180.v:134422.18-134422.116" - wire $eq$issuer_ls180.v:134422$6511_Y - attribute \src "issuer_ls180.v:134423.18-134423.116" - wire $eq$issuer_ls180.v:134423$6512_Y - attribute \src "issuer_ls180.v:134424.18-134424.116" - wire $eq$issuer_ls180.v:134424$6513_Y - attribute \src "issuer_ls180.v:134425.18-134425.118" - wire $eq$issuer_ls180.v:134425$6514_Y - attribute \src "issuer_ls180.v:134426.18-134426.118" - wire $eq$issuer_ls180.v:134426$6515_Y - attribute \src "issuer_ls180.v:134427.18-134427.118" - wire $eq$issuer_ls180.v:134427$6516_Y - attribute \src "issuer_ls180.v:134428.18-134428.118" - wire $eq$issuer_ls180.v:134428$6517_Y - attribute \src "issuer_ls180.v:134429.18-134429.118" - wire $eq$issuer_ls180.v:134429$6518_Y - attribute \src "issuer_ls180.v:134430.18-134430.118" - wire $eq$issuer_ls180.v:134430$6519_Y - attribute \src "issuer_ls180.v:134431.18-134431.118" - wire $eq$issuer_ls180.v:134431$6520_Y - attribute \src "issuer_ls180.v:134432.18-134432.118" - wire $eq$issuer_ls180.v:134432$6521_Y - attribute \src "issuer_ls180.v:134433.18-134433.118" - wire $eq$issuer_ls180.v:134433$6522_Y - attribute \src "issuer_ls180.v:134434.18-134434.118" - wire $eq$issuer_ls180.v:134434$6523_Y - attribute \src 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\enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 23 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 44 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 22 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 41 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 42 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:84" - wire \par0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:85" - wire \par1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:27" - wire width 64 \popcount_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" - wire width 64 \popcount_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" - wire width 64 \popcount_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 43 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - cell $and $and$issuer_ls180.v:134406$6495 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \B \rb - connect \Y $and$issuer_ls180.v:134406$6495_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134365$6449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $eq$issuer_ls180.v:134365$6449_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134366$6450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $eq$issuer_ls180.v:134366$6450_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134367$6451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $eq$issuer_ls180.v:134367$6451_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134368$6452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $eq$issuer_ls180.v:134368$6452_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134369$6453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $eq$issuer_ls180.v:134369$6453_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134370$6454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $eq$issuer_ls180.v:134370$6454_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134371$6455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $eq$issuer_ls180.v:134371$6455_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134372$6456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $eq$issuer_ls180.v:134372$6456_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134373$6457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $eq$issuer_ls180.v:134373$6457_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134374$6458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $eq$issuer_ls180.v:134374$6458_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134375$6459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $eq$issuer_ls180.v:134375$6459_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134376$6460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $eq$issuer_ls180.v:134376$6460_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134377$6461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $eq$issuer_ls180.v:134377$6461_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134378$6462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $eq$issuer_ls180.v:134378$6462_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134379$6463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $eq$issuer_ls180.v:134379$6463_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134380$6464 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $eq$issuer_ls180.v:134380$6464_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134381$6465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $eq$issuer_ls180.v:134381$6465_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134382$6466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $eq$issuer_ls180.v:134382$6466_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134383$6467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $eq$issuer_ls180.v:134383$6467_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134384$6468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $eq$issuer_ls180.v:134384$6468_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134385$6469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $eq$issuer_ls180.v:134385$6469_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134386$6470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $eq$issuer_ls180.v:134386$6470_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134387$6471 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $eq$issuer_ls180.v:134387$6471_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134388$6472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $eq$issuer_ls180.v:134388$6472_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134389$6473 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $eq$issuer_ls180.v:134389$6473_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134390$6474 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $eq$issuer_ls180.v:134390$6474_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134391$6475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $eq$issuer_ls180.v:134391$6475_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134392$6476 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $eq$issuer_ls180.v:134392$6476_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - cell $eq $eq$issuer_ls180.v:134393$6477 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \logical_op__data_len [3] - connect \B 1'1 - connect \Y $eq$issuer_ls180.v:134393$6477_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134409$6498 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $eq$issuer_ls180.v:134409$6498_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134410$6499 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $eq$issuer_ls180.v:134410$6499_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134411$6500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $eq$issuer_ls180.v:134411$6500_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134412$6501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $eq$issuer_ls180.v:134412$6501_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134413$6502 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $eq$issuer_ls180.v:134413$6502_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134414$6503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $eq$issuer_ls180.v:134414$6503_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134415$6504 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $eq$issuer_ls180.v:134415$6504_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134416$6505 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $eq$issuer_ls180.v:134416$6505_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134417$6506 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $eq$issuer_ls180.v:134417$6506_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134418$6507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $eq$issuer_ls180.v:134418$6507_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134419$6508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $eq$issuer_ls180.v:134419$6508_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134420$6509 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $eq$issuer_ls180.v:134420$6509_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134421$6510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $eq$issuer_ls180.v:134421$6510_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134422$6511 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $eq$issuer_ls180.v:134422$6511_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134423$6512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $eq$issuer_ls180.v:134423$6512_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134424$6513 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $eq$issuer_ls180.v:134424$6513_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134425$6514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $eq$issuer_ls180.v:134425$6514_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134426$6515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $eq$issuer_ls180.v:134426$6515_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134427$6516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $eq$issuer_ls180.v:134427$6516_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134428$6517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $eq$issuer_ls180.v:134428$6517_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134429$6518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $eq$issuer_ls180.v:134429$6518_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134430$6519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $eq$issuer_ls180.v:134430$6519_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134431$6520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $eq$issuer_ls180.v:134431$6520_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134432$6521 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $eq$issuer_ls180.v:134432$6521_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134433$6522 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $eq$issuer_ls180.v:134433$6522_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134434$6523 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $eq$issuer_ls180.v:134434$6523_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134435$6524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $eq$issuer_ls180.v:134435$6524_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134436$6525 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $eq$issuer_ls180.v:134436$6525_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134437$6526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $eq$issuer_ls180.v:134437$6526_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134438$6527 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $eq$issuer_ls180.v:134438$6527_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134439$6528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $eq$issuer_ls180.v:134439$6528_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134440$6529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $eq$issuer_ls180.v:134440$6529_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134441$6530 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $eq$issuer_ls180.v:134441$6530_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134442$6531 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $eq$issuer_ls180.v:134442$6531_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134443$6532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $eq$issuer_ls180.v:134443$6532_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$issuer_ls180.v:134444$6533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $eq$issuer_ls180.v:134444$6533_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $extend$issuer_ls180.v:134395$6479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 64 - connect \A \$158 - connect \Y $extend$issuer_ls180.v:134395$6479_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" - cell $pos $extend$issuer_ls180.v:134397$6482 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 8 - connect \A \clz_lz - connect \Y $extend$issuer_ls180.v:134397$6482_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $extend$issuer_ls180.v:134399$6485 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 64 - connect \A \$166 - connect \Y $extend$issuer_ls180.v:134399$6485_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $extend$issuer_ls180.v:134400$6487 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 64 - connect \A \logical_op__data_len - connect \Y $extend$issuer_ls180.v:134400$6487_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $extend$issuer_ls180.v:134404$6492 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \$176 - connect \Y $extend$issuer_ls180.v:134404$6492_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - cell $or $or$issuer_ls180.v:134407$6496 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \B \rb - connect \Y $or$issuer_ls180.v:134407$6496_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $pos$issuer_ls180.v:134395$6480 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:134395$6479_Y - connect \Y $pos$issuer_ls180.v:134395$6480_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" - cell $pos $pos$issuer_ls180.v:134397$6483 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$issuer_ls180.v:134397$6482_Y - connect \Y $pos$issuer_ls180.v:134397$6483_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $pos$issuer_ls180.v:134399$6486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:134399$6485_Y - connect \Y $pos$issuer_ls180.v:134399$6486_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $pos$issuer_ls180.v:134400$6488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:134400$6487_Y - connect \Y $pos$issuer_ls180.v:134400$6488_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $pos$issuer_ls180.v:134404$6493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:134404$6492_Y - connect \Y $pos$issuer_ls180.v:134404$6493_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" - cell $reduce_xor $reduce_xor$issuer_ls180.v:134401$6489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \ra [24] \ra [16] \ra [8] \ra [0] } - connect \Y $reduce_xor$issuer_ls180.v:134401$6489_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" - cell $reduce_xor $reduce_xor$issuer_ls180.v:134402$6490 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \ra [56] \ra [48] \ra [40] \ra [32] } - connect \Y $reduce_xor$issuer_ls180.v:134402$6490_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $sub $sub$issuer_ls180.v:134396$6481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 8 - connect \A \clz_lz - connect \B 6'100000 - connect \Y $sub$issuer_ls180.v:134396$6481_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $mux $ternary$issuer_ls180.v:134398$6484 - parameter \WIDTH 8 - connect \A \$164 - connect \B \$162 - connect \S \logical_op__is_32bit - connect \Y $ternary$issuer_ls180.v:134398$6484_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $mux $ternary$issuer_ls180.v:134403$6491 - parameter \WIDTH 32 - connect \A \a32 - connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] } - connect \S \count_right - connect \Y $ternary$issuer_ls180.v:134403$6491_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" - cell $mux $ternary$issuer_ls180.v:134405$6494 - parameter \WIDTH 64 - connect \A \ra - connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] } - connect \S \count_right - connect \Y $ternary$issuer_ls180.v:134405$6494_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $xor $xor$issuer_ls180.v:134394$6478 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \par0 - connect \B \par1 - connect \Y $xor$issuer_ls180.v:134394$6478_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" - cell $xor $xor$issuer_ls180.v:134408$6497 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \B \rb - connect \Y $xor$issuer_ls180.v:134408$6497_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:134445.10-134449.4" - cell \bpermd \bpermd - connect \ra \bpermd_ra - connect \rb \bpermd_rb - connect \rs \bpermd_rs - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:134450.7-134453.4" - cell \clz \clz - connect \lz \clz_lz - connect \sig_in \clz_sig_in - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:134454.12-134458.4" - cell \popcount \popcount - connect \a \popcount_a - connect \data_len \popcount_data_len - connect \o \popcount_o - end - attribute \src "issuer_ls180.v:133904.7-133904.20" - process $proc$issuer_ls180.v:133904$6546 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:134459.3-134513.6" - process $proc$issuer_ls180.v:134459$6534 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o_ok[0:0] $1\o_ok[0:0] - assign $0\o[63:0] $1\o[63:0] - attribute \src "issuer_ls180.v:134460.5-134460.29" - switch \initial - attribute \src "issuer_ls180.v:134460.9-134460.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0000100 - assign $1\o_ok[0:0] 1'1 - assign { } { } - assign $1\o[63:0] \$21 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110101 - assign $1\o_ok[0:0] 1'1 - assign { } { } - assign $1\o[63:0] \$23 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000011 - assign $1\o_ok[0:0] 1'1 - assign { } { } - assign $1\o[63:0] \$25 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001011 - assign $1\o_ok[0:0] 1'1 - assign { } { } - assign $1\o[63:0] { \$139 \$141 \$143 \$145 \$147 \$149 \$151 \$153 \$123 \$125 \$127 \$129 \$131 \$133 \$135 \$137 \$107 \$109 \$111 \$113 \$115 \$117 \$119 \$121 \$91 \$93 \$95 \$97 \$99 \$101 \$103 \$105 \$75 \$77 \$79 \$81 \$83 \$85 \$87 \$89 \$59 \$61 \$63 \$65 \$67 \$69 \$71 \$73 \$43 \$45 \$47 \$49 \$51 \$53 \$55 \$57 \$27 \$29 \$31 \$33 \$35 \$37 \$39 \$41 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110110 - assign $1\o_ok[0:0] 1'1 - assign { } { } - assign $1\o[63:0] \popcount_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110111 - assign $1\o_ok[0:0] 1'1 - assign { } { } - assign $1\o[63:0] $2\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - switch \$155 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o[63:0] \$157 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { $2\o[63:0] [63:33] $2\o[63:0] [31:1] } 62'00000000000000000000000000000000000000000000000000000000000000 - assign $2\o[63:0] [0] \par0 - assign $2\o[63:0] [32] \par1 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001110 - assign $1\o_ok[0:0] 1'1 - assign { } { } - assign $1\o[63:0] \$161 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001001 - assign $1\o_ok[0:0] 1'1 - assign { } { } - assign $1\o[63:0] \bpermd_ra - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\o_ok[0:0] 1'0 - end - sync always - update \o_ok $0\o_ok[0:0] - update \o $0\o[63:0] - end - attribute \src "issuer_ls180.v:134514.3-134524.6" - process $proc$issuer_ls180.v:134514$6535 - assign { } { } - assign { } { } - assign $0\clz_sig_in[63:0] $1\clz_sig_in[63:0] - attribute \src "issuer_ls180.v:134515.5-134515.29" - switch \initial - attribute \src "issuer_ls180.v:134515.9-134515.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001110 - assign { } { } - assign $1\clz_sig_in[63:0] \cntz_i - case - assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \clz_sig_in $0\clz_sig_in[63:0] - end - attribute \src "issuer_ls180.v:134525.3-134535.6" - process $proc$issuer_ls180.v:134525$6536 - assign { } { } - assign { } { } - assign $0\bpermd_rs[63:0] $1\bpermd_rs[63:0] - attribute \src "issuer_ls180.v:134526.5-134526.29" - switch \initial - attribute \src "issuer_ls180.v:134526.9-134526.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001001 - assign { } { } - assign $1\bpermd_rs[63:0] \ra - case - assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \bpermd_rs $0\bpermd_rs[63:0] - end - attribute \src "issuer_ls180.v:134536.3-134546.6" - process $proc$issuer_ls180.v:134536$6537 - assign { } { } - assign { } { } - assign $0\bpermd_rb[63:0] $1\bpermd_rb[63:0] - attribute \src "issuer_ls180.v:134537.5-134537.29" - switch \initial - attribute \src "issuer_ls180.v:134537.9-134537.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001001 - assign { } { } - assign $1\bpermd_rb[63:0] \rb - case - assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \bpermd_rb $0\bpermd_rb[63:0] - end - attribute \src "issuer_ls180.v:134547.3-134557.6" - process $proc$issuer_ls180.v:134547$6538 - assign { } { } - assign { } { } - assign $0\popcount_a[63:0] $1\popcount_a[63:0] - attribute \src "issuer_ls180.v:134548.5-134548.29" - switch \initial - attribute \src "issuer_ls180.v:134548.9-134548.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110110 - assign { } { } - assign $1\popcount_a[63:0] \ra - case - assign $1\popcount_a[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \popcount_a $0\popcount_a[63:0] - end - attribute \src "issuer_ls180.v:134558.3-134568.6" - process $proc$issuer_ls180.v:134558$6539 - assign { } { } - assign { } { } - assign $0\b[63:0] $1\b[63:0] - attribute \src "issuer_ls180.v:134559.5-134559.29" - switch \initial - attribute \src "issuer_ls180.v:134559.9-134559.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110110 - assign { } { } - assign $1\b[63:0] \rb - case - assign $1\b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \b $0\b[63:0] - end - attribute \src "issuer_ls180.v:134569.3-134579.6" - process $proc$issuer_ls180.v:134569$6540 - assign { } { } - assign { } { } - assign $0\popcount_data_len[63:0] $1\popcount_data_len[63:0] - attribute \src "issuer_ls180.v:134570.5-134570.29" - switch \initial - attribute \src "issuer_ls180.v:134570.9-134570.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110110 - assign { } { } - assign $1\popcount_data_len[63:0] \$169 - case - assign $1\popcount_data_len[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \popcount_data_len $0\popcount_data_len[63:0] - end - attribute \src "issuer_ls180.v:134580.3-134590.6" - process $proc$issuer_ls180.v:134580$6541 - assign { } { } - assign { } { } - assign $0\par0[0:0] $1\par0[0:0] - attribute \src "issuer_ls180.v:134581.5-134581.29" - switch \initial - attribute \src "issuer_ls180.v:134581.9-134581.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110111 - assign { } { } - assign $1\par0[0:0] \$171 - case - assign $1\par0[0:0] 1'0 - end - sync always - update \par0 $0\par0[0:0] - end - attribute \src "issuer_ls180.v:134591.3-134601.6" - process $proc$issuer_ls180.v:134591$6542 - assign { } { } - assign { } { } - assign $0\par1[0:0] $1\par1[0:0] - attribute \src "issuer_ls180.v:134592.5-134592.29" - switch \initial - attribute \src "issuer_ls180.v:134592.9-134592.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110111 - assign { } { } - assign $1\par1[0:0] \$173 - case - assign $1\par1[0:0] 1'0 - end - sync always - update \par1 $0\par1[0:0] - end - attribute \src "issuer_ls180.v:134602.3-134612.6" - process $proc$issuer_ls180.v:134602$6543 - assign { } { } - assign { } { } - assign $0\count_right[0:0] $1\count_right[0:0] - attribute \src "issuer_ls180.v:134603.5-134603.29" - switch \initial - attribute \src "issuer_ls180.v:134603.9-134603.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001110 - assign { } { } - assign $1\count_right[0:0] \logical_op__insn [10] - case - assign $1\count_right[0:0] 1'0 - end - sync always - update \count_right $0\count_right[0:0] - end - attribute \src "issuer_ls180.v:134613.3-134623.6" - process $proc$issuer_ls180.v:134613$6544 - assign { } { } - assign { } { } - assign $0\a32[31:0] $1\a32[31:0] - attribute \src "issuer_ls180.v:134614.5-134614.29" - switch \initial - attribute \src "issuer_ls180.v:134614.9-134614.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001110 - assign { } { } - assign $1\a32[31:0] \ra [31:0] - case - assign $1\a32[31:0] 0 - end - sync always - update \a32 $0\a32[31:0] - end - attribute \src "issuer_ls180.v:134624.3-134642.6" - process $proc$issuer_ls180.v:134624$6545 - assign { } { } - assign { } { } - assign $0\cntz_i[63:0] $1\cntz_i[63:0] - attribute \src "issuer_ls180.v:134625.5-134625.29" - switch \initial - attribute \src "issuer_ls180.v:134625.9-134625.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0001110 - assign { } { } - assign $1\cntz_i[63:0] $2\cntz_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106" - switch \logical_op__is_32bit - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cntz_i[63:0] \$175 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\cntz_i[63:0] \$179 - end - case - assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \cntz_i $0\cntz_i[63:0] - end - connect \$99 $eq$issuer_ls180.v:134365$6449_Y - connect \$101 $eq$issuer_ls180.v:134366$6450_Y - connect \$103 $eq$issuer_ls180.v:134367$6451_Y - connect \$105 $eq$issuer_ls180.v:134368$6452_Y - connect \$107 $eq$issuer_ls180.v:134369$6453_Y - connect \$109 $eq$issuer_ls180.v:134370$6454_Y - connect \$111 $eq$issuer_ls180.v:134371$6455_Y - connect \$113 $eq$issuer_ls180.v:134372$6456_Y - connect \$115 $eq$issuer_ls180.v:134373$6457_Y - connect \$117 $eq$issuer_ls180.v:134374$6458_Y - connect \$119 $eq$issuer_ls180.v:134375$6459_Y - connect \$121 $eq$issuer_ls180.v:134376$6460_Y - connect \$123 $eq$issuer_ls180.v:134377$6461_Y - connect \$125 $eq$issuer_ls180.v:134378$6462_Y - connect \$127 $eq$issuer_ls180.v:134379$6463_Y - connect \$129 $eq$issuer_ls180.v:134380$6464_Y - connect \$131 $eq$issuer_ls180.v:134381$6465_Y - connect \$133 $eq$issuer_ls180.v:134382$6466_Y - connect \$135 $eq$issuer_ls180.v:134383$6467_Y - connect \$137 $eq$issuer_ls180.v:134384$6468_Y - connect \$139 $eq$issuer_ls180.v:134385$6469_Y - connect \$141 $eq$issuer_ls180.v:134386$6470_Y - connect \$143 $eq$issuer_ls180.v:134387$6471_Y - connect \$145 $eq$issuer_ls180.v:134388$6472_Y - connect \$147 $eq$issuer_ls180.v:134389$6473_Y - connect \$149 $eq$issuer_ls180.v:134390$6474_Y - connect \$151 $eq$issuer_ls180.v:134391$6475_Y - connect \$153 $eq$issuer_ls180.v:134392$6476_Y - connect \$155 $eq$issuer_ls180.v:134393$6477_Y - connect \$158 $xor$issuer_ls180.v:134394$6478_Y - connect \$157 $pos$issuer_ls180.v:134395$6480_Y - connect \$162 $sub$issuer_ls180.v:134396$6481_Y - connect \$164 $pos$issuer_ls180.v:134397$6483_Y - connect \$166 $ternary$issuer_ls180.v:134398$6484_Y - connect \$161 $pos$issuer_ls180.v:134399$6486_Y - connect \$169 $pos$issuer_ls180.v:134400$6488_Y - connect \$171 $reduce_xor$issuer_ls180.v:134401$6489_Y - connect \$173 $reduce_xor$issuer_ls180.v:134402$6490_Y - connect \$176 $ternary$issuer_ls180.v:134403$6491_Y - connect \$175 $pos$issuer_ls180.v:134404$6493_Y - connect \$179 $ternary$issuer_ls180.v:134405$6494_Y - connect \$21 $and$issuer_ls180.v:134406$6495_Y - connect \$23 $or$issuer_ls180.v:134407$6496_Y - connect \$25 $xor$issuer_ls180.v:134408$6497_Y - connect \$27 $eq$issuer_ls180.v:134409$6498_Y - connect \$29 $eq$issuer_ls180.v:134410$6499_Y - connect \$31 $eq$issuer_ls180.v:134411$6500_Y - connect \$33 $eq$issuer_ls180.v:134412$6501_Y - connect \$35 $eq$issuer_ls180.v:134413$6502_Y - connect \$37 $eq$issuer_ls180.v:134414$6503_Y - connect \$39 $eq$issuer_ls180.v:134415$6504_Y - connect \$41 $eq$issuer_ls180.v:134416$6505_Y - connect \$43 $eq$issuer_ls180.v:134417$6506_Y - connect \$45 $eq$issuer_ls180.v:134418$6507_Y - connect \$47 $eq$issuer_ls180.v:134419$6508_Y - connect \$49 $eq$issuer_ls180.v:134420$6509_Y - connect \$51 $eq$issuer_ls180.v:134421$6510_Y - connect \$53 $eq$issuer_ls180.v:134422$6511_Y - connect \$55 $eq$issuer_ls180.v:134423$6512_Y - connect \$57 $eq$issuer_ls180.v:134424$6513_Y - connect \$59 $eq$issuer_ls180.v:134425$6514_Y - connect \$61 $eq$issuer_ls180.v:134426$6515_Y - connect \$63 $eq$issuer_ls180.v:134427$6516_Y - connect \$65 $eq$issuer_ls180.v:134428$6517_Y - connect \$67 $eq$issuer_ls180.v:134429$6518_Y - connect \$69 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"/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 5 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$issuer_ls180.v:134922$6553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \full_cr - connect \Y $extend$issuer_ls180.v:134922$6553_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $extend$issuer_ls180.v:134924$6556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \$27 - connect \Y $extend$issuer_ls180.v:134924$6556_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$issuer_ls180.v:134925$6558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A \cr_a - connect \Y $extend$issuer_ls180.v:134925$6558_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$issuer_ls180.v:134922$6554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:134922$6553_Y - connect \Y $pos$issuer_ls180.v:134922$6554_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $pos$issuer_ls180.v:134924$6557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$issuer_ls180.v:134924$6556_Y - connect \Y $pos$issuer_ls180.v:134924$6557_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$issuer_ls180.v:134925$6559 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $extend$issuer_ls180.v:134925$6558_Y - connect \Y $pos$issuer_ls180.v:134925$6559_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" - cell $sub $sub$issuer_ls180.v:134916$6547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A 2'11 - connect \B \cr_op__insn [22:21] - connect \Y $sub$issuer_ls180.v:134916$6547_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" - cell $sub $sub$issuer_ls180.v:134917$6548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A 2'11 - connect \B \cr_op__insn [17:16] - connect \Y $sub$issuer_ls180.v:134917$6548_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" - cell $sub $sub$issuer_ls180.v:134918$6549 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A 2'11 - connect \B \cr_op__insn [12:11] - connect \Y $sub$issuer_ls180.v:134918$6549_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" - cell $mux $ternary$issuer_ls180.v:134919$6550 - parameter \WIDTH 1 - connect \A \lut [1] - connect \B \lut [3] - connect \S \bit_a - connect \Y $ternary$issuer_ls180.v:134919$6550_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $ternary$issuer_ls180.v:134920$6551 - parameter \WIDTH 1 - connect \A \lut [0] - connect \B \lut [2] - connect \S \bit_a - connect \Y $ternary$issuer_ls180.v:134920$6551_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $ternary$issuer_ls180.v:134921$6552 - parameter \WIDTH 1 - connect \A \$20 - connect \B \$18 - connect \S \bit_b - connect \Y $ternary$issuer_ls180.v:134921$6552_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $mux $ternary$issuer_ls180.v:134923$6555 - parameter \WIDTH 64 - connect \A \rb - connect \B \ra - connect \S \cr_bit - connect \Y $ternary$issuer_ls180.v:134923$6555_Y - end - attribute \src "issuer_ls180.v:134651.7-134651.20" - process $proc$issuer_ls180.v:134651$6578 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:134926.3-134960.6" - process $proc$issuer_ls180.v:134926$6560 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] - assign $0\cr_a$6[3:0]$6561 $1\cr_a$6[3:0]$6562 - attribute \src "issuer_ls180.v:134927.5-134927.29" - switch \initial - attribute \src "issuer_ls180.v:134927.9-134927.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0101010 - assign { } { } - assign { } { } - assign $1\cr_a$6[3:0]$6562 \$7 [3:0] - assign $1\cr_a_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000101 - assign { } { } - assign { } { } - assign { } { } - assign $1\cr_a$6[3:0]$6562 $2\cr_a$6[3:0]$6563 - assign $1\cr_a_ok[0:0] 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105" - switch \bt - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign $2\cr_a$6[3:0]$6563 [3:1] \cr_c [3:1] - assign $2\cr_a$6[3:0]$6563 [0] \bit_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { $2\cr_a$6[3:0]$6563 [3:2] $2\cr_a$6[3:0]$6563 [0] } { \cr_c [3:2] \cr_c [0] } - assign $2\cr_a$6[3:0]$6563 [1] \bit_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { $2\cr_a$6[3:0]$6563 [3] $2\cr_a$6[3:0]$6563 [1:0] } { \cr_c [3] \cr_c [1:0] } - assign $2\cr_a$6[3:0]$6563 [2] \bit_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-- - assign $2\cr_a$6[3:0]$6563 [2:0] \cr_c [2:0] - assign $2\cr_a$6[3:0]$6563 [3] \bit_o - case - assign $2\cr_a$6[3:0]$6563 \cr_c - end - case - assign $1\cr_a_ok[0:0] 1'0 - assign $1\cr_a$6[3:0]$6562 4'0000 - end - sync always - update \cr_a_ok $0\cr_a_ok[0:0] - update \cr_a$6 $0\cr_a$6[3:0]$6561 - end - attribute \src "issuer_ls180.v:134961.3-134971.6" - process $proc$issuer_ls180.v:134961$6564 - assign { } { } - assign { } { } - assign $0\full_cr_ok[0:0] $1\full_cr_ok[0:0] - attribute \src "issuer_ls180.v:134962.5-134962.29" - switch \initial - attribute \src "issuer_ls180.v:134962.9-134962.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110000 - assign { } { } - assign $1\full_cr_ok[0:0] 1'1 - case - assign $1\full_cr_ok[0:0] 1'0 - end - sync always - update \full_cr_ok $0\full_cr_ok[0:0] - end - attribute \src "issuer_ls180.v:134972.3-135013.6" - process $proc$issuer_ls180.v:134972$6565 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o_ok[0:0] $1\o_ok[0:0] - assign $0\o[63:0] $1\o[63:0] - attribute \src "issuer_ls180.v:134973.5-134973.29" - switch \initial - attribute \src "issuer_ls180.v:134973.9-134973.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0101101 - assign { } { } - assign { } { } - assign $1\o[63:0] \$24 - assign $1\o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0100011 - assign { } { } - assign { } { } - assign $1\o[63:0] \$26 [63:0] - assign $1\o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0111011 - assign { } { } - assign { } { } - assign $1\o[63:0] $2\o[63:0] - assign $1\o_ok[0:0] 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:144" - switch { \cr_a [2] \cr_a [3] } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\o[63:0] 64'1111111111111111111111111111111111111111111111111111111111111111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000001 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\o_ok[0:0] 1'0 - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \o_ok $0\o_ok[0:0] - update \o $0\o[63:0] - end - attribute \src "issuer_ls180.v:135014.3-135024.6" - process $proc$issuer_ls180.v:135014$6566 - assign { } { } - assign { } { } - assign $0\BC[1:0] $1\BC[1:0] - attribute \src "issuer_ls180.v:135015.5-135015.29" - switch \initial - attribute \src "issuer_ls180.v:135015.9-135015.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0100011 - assign { } { } - assign $1\BC[1:0] \cr_op__insn [7:6] - case - assign $1\BC[1:0] 2'00 - end - sync always - update \BC $0\BC[1:0] - end - attribute \src "issuer_ls180.v:135025.3-135045.6" - process $proc$issuer_ls180.v:135025$6567 - assign { } { } - assign { } { } - assign $0\cr_bit[0:0] $1\cr_bit[0:0] - attribute \src "issuer_ls180.v:135026.5-135026.29" - switch \initial - attribute \src "issuer_ls180.v:135026.9-135026.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0100011 - assign { } { } - assign $1\cr_bit[0:0] $2\cr_bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:137" - switch \BC - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $2\cr_bit[0:0] \cr_a [3] - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $2\cr_bit[0:0] \cr_a [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\cr_bit[0:0] \cr_a [1] - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-- - assign { } { } - assign $2\cr_bit[0:0] \cr_a [0] - case - assign $2\cr_bit[0:0] 1'0 - end - case - assign $1\cr_bit[0:0] 1'0 - end - sync always - update \cr_bit $0\cr_bit[0:0] - end - attribute \src "issuer_ls180.v:135046.3-135056.6" - process $proc$issuer_ls180.v:135046$6568 - assign { } { } - assign { } { } - assign $0\lut[3:0] $1\lut[3:0] - attribute \src "issuer_ls180.v:135047.5-135047.29" - switch \initial - attribute \src "issuer_ls180.v:135047.9-135047.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000101 - assign { } { } - assign $1\lut[3:0] \cr_op__insn [9:6] - case - assign $1\lut[3:0] 4'0000 - end - sync always - update \lut $0\lut[3:0] - end - attribute \src "issuer_ls180.v:135057.3-135067.6" - process $proc$issuer_ls180.v:135057$6569 - assign { } { } - assign { } { } - assign $0\bt[1:0] $1\bt[1:0] - attribute \src "issuer_ls180.v:135058.5-135058.29" - switch \initial - attribute \src "issuer_ls180.v:135058.9-135058.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000101 - assign { } { } - assign $1\bt[1:0] \$9 [1:0] - case - assign $1\bt[1:0] 2'00 - end - sync always - update \bt $0\bt[1:0] - end - attribute \src "issuer_ls180.v:135068.3-135078.6" - process $proc$issuer_ls180.v:135068$6570 - assign { } { } - assign { } { } - assign $0\ba[1:0] $1\ba[1:0] - attribute \src "issuer_ls180.v:135069.5-135069.29" - switch \initial - attribute \src "issuer_ls180.v:135069.9-135069.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000101 - assign { } { } - assign $1\ba[1:0] \$12 [1:0] - case - assign $1\ba[1:0] 2'00 - end - sync always - update \ba $0\ba[1:0] - end - attribute \src "issuer_ls180.v:135079.3-135089.6" - process $proc$issuer_ls180.v:135079$6571 - assign { } { } - assign { } { } - assign $0\bb[1:0] $1\bb[1:0] - attribute \src "issuer_ls180.v:135080.5-135080.29" - switch \initial - attribute \src "issuer_ls180.v:135080.9-135080.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000101 - assign { } { } - assign $1\bb[1:0] \$15 [1:0] - case - assign $1\bb[1:0] 2'00 - end - sync always - update \bb $0\bb[1:0] - end - attribute \src "issuer_ls180.v:135090.3-135110.6" - process $proc$issuer_ls180.v:135090$6572 - assign { } { } - assign { } { } - assign $0\bit_a[0:0] $1\bit_a[0:0] - attribute \src "issuer_ls180.v:135091.5-135091.29" - switch \initial - attribute \src "issuer_ls180.v:135091.9-135091.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000101 - assign { } { } - assign $1\bit_a[0:0] $2\bit_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:93" - switch \ba - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $2\bit_a[0:0] \cr_a [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $2\bit_a[0:0] \cr_a [1] - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\bit_a[0:0] \cr_a [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-- - assign { } { } - assign $2\bit_a[0:0] \cr_a [3] - case - assign $2\bit_a[0:0] 1'0 - end - case - assign $1\bit_a[0:0] 1'0 - end - sync always - update \bit_a $0\bit_a[0:0] - end - attribute \src "issuer_ls180.v:135111.3-135131.6" - process $proc$issuer_ls180.v:135111$6573 - assign { } { } - assign { } { } - assign $0\bit_b[0:0] $1\bit_b[0:0] - attribute \src "issuer_ls180.v:135112.5-135112.29" - switch \initial - attribute \src "issuer_ls180.v:135112.9-135112.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000101 - assign { } { } - assign $1\bit_b[0:0] $2\bit_b[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:94" - switch \bb - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $2\bit_b[0:0] \cr_b [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $2\bit_b[0:0] \cr_b [1] - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\bit_b[0:0] \cr_b [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-- - assign { } { } - assign $2\bit_b[0:0] \cr_b [3] - case - assign $2\bit_b[0:0] 1'0 - end - case - assign $1\bit_b[0:0] 1'0 - end - sync always - update \bit_b $0\bit_b[0:0] - end - attribute \src "issuer_ls180.v:135132.3-135142.6" - process $proc$issuer_ls180.v:135132$6574 - assign { } { } - assign { } { } - assign $0\bit_o[0:0] $1\bit_o[0:0] - attribute \src "issuer_ls180.v:135133.5-135133.29" - switch \initial - attribute \src "issuer_ls180.v:135133.9-135133.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'1000101 - assign { } { } - assign $1\bit_o[0:0] \$22 - case - assign $1\bit_o[0:0] 1'0 - end - sync always - update \bit_o $0\bit_o[0:0] - end - attribute \src "issuer_ls180.v:135143.3-135153.6" - process $proc$issuer_ls180.v:135143$6575 - assign { } { } - assign { } { } - assign $0\full_cr$5[31:0]$6576 $1\full_cr$5[31:0]$6577 - attribute \src "issuer_ls180.v:135144.5-135144.29" - switch \initial - attribute \src "issuer_ls180.v:135144.9-135144.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110000 - assign { } { } - assign $1\full_cr$5[31:0]$6577 \ra [31:0] - case - assign $1\full_cr$5[31:0]$6577 0 - end - sync always - update \full_cr$5 $0\full_cr$5[31:0]$6576 - end - connect \$10 $sub$issuer_ls180.v:134916$6547_Y - connect \$13 $sub$issuer_ls180.v:134917$6548_Y - connect \$16 $sub$issuer_ls180.v:134918$6549_Y - connect \$18 $ternary$issuer_ls180.v:134919$6550_Y - connect \$20 $ternary$issuer_ls180.v:134920$6551_Y - connect \$22 $ternary$issuer_ls180.v:134921$6552_Y - connect \$24 $pos$issuer_ls180.v:134922$6554_Y - connect \$27 $ternary$issuer_ls180.v:134923$6555_Y - connect \$26 $pos$issuer_ls180.v:134924$6557_Y - connect \$7 $pos$issuer_ls180.v:134925$6559_Y - connect \$9 \$10 - connect \$12 \$13 - connect \$15 \$16 - connect { \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } - connect \muxid$1 \muxid -end -attribute \src "issuer_ls180.v:135163.1-136318.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0" -attribute \generator "nMigen" -module \mul0 - attribute \src "issuer_ls180.v:135889.3-135890.25" - wire $0\all_rd_dly[0:0] - attribute \src "issuer_ls180.v:135887.3-135888.40" - wire $0\alu_done_dly[0:0] - attribute \src "issuer_ls180.v:136230.3-136238.6" - wire $0\alu_l_r_alu$next[0:0]$6784 - attribute \src "issuer_ls180.v:135815.3-135816.39" - wire $0\alu_l_r_alu[0:0] - attribute \src "issuer_ls180.v:136070.3-136102.6" - wire width 12 $0\alu_mul0_mul_op__fn_unit$next[11:0]$6709 - attribute \src "issuer_ls180.v:135843.3-135844.65" - wire width 12 $0\alu_mul0_mul_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:136070.3-136102.6" - wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$6710 - attribute \src "issuer_ls180.v:135845.3-135846.79" - wire width 64 $0\alu_mul0_mul_op__imm_data__data[63:0] - attribute \src "issuer_ls180.v:136070.3-136102.6" - wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$6711 - attribute \src "issuer_ls180.v:135847.3-135848.75" - wire $0\alu_mul0_mul_op__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:136070.3-136102.6" - wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$6712 - attribute \src "issuer_ls180.v:135863.3-135864.59" - wire width 32 $0\alu_mul0_mul_op__insn[31:0] - attribute \src "issuer_ls180.v:136070.3-136102.6" - wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$6713 - attribute \src "issuer_ls180.v:135841.3-135842.69" - wire width 7 $0\alu_mul0_mul_op__insn_type[6:0] - attribute \src "issuer_ls180.v:136070.3-136102.6" - wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$6714 - attribute \src "issuer_ls180.v:135859.3-135860.67" - wire $0\alu_mul0_mul_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:136070.3-136102.6" - wire $0\alu_mul0_mul_op__is_signed$next[0:0]$6715 - attribute \src "issuer_ls180.v:135861.3-135862.69" - wire $0\alu_mul0_mul_op__is_signed[0:0] - attribute \src "issuer_ls180.v:136070.3-136102.6" - wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$6716 - attribute \src "issuer_ls180.v:135853.3-135854.63" - wire $0\alu_mul0_mul_op__oe__oe[0:0] - attribute \src "issuer_ls180.v:136070.3-136102.6" - wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$6717 - attribute \src "issuer_ls180.v:135855.3-135856.63" - wire $0\alu_mul0_mul_op__oe__ok[0:0] - attribute \src "issuer_ls180.v:136070.3-136102.6" - wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$6718 - attribute \src "issuer_ls180.v:135851.3-135852.63" - wire $0\alu_mul0_mul_op__rc__ok[0:0] - attribute \src "issuer_ls180.v:136070.3-136102.6" - wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$6719 - attribute \src "issuer_ls180.v:135849.3-135850.63" - wire $0\alu_mul0_mul_op__rc__rc[0:0] - attribute \src "issuer_ls180.v:136070.3-136102.6" - wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$6720 - attribute \src "issuer_ls180.v:135857.3-135858.69" - wire $0\alu_mul0_mul_op__write_cr0[0:0] - attribute \src "issuer_ls180.v:136221.3-136229.6" - wire $0\alui_l_r_alui$next[0:0]$6781 - attribute \src "issuer_ls180.v:135817.3-135818.43" - wire $0\alui_l_r_alui[0:0] - attribute \src "issuer_ls180.v:136103.3-136124.6" - wire width 64 $0\data_r0__o$next[63:0]$6740 - attribute \src "issuer_ls180.v:135837.3-135838.37" - wire width 64 $0\data_r0__o[63:0] - attribute \src "issuer_ls180.v:136103.3-136124.6" - wire $0\data_r0__o_ok$next[0:0]$6741 - attribute \src "issuer_ls180.v:135839.3-135840.43" - wire $0\data_r0__o_ok[0:0] - attribute \src "issuer_ls180.v:136125.3-136146.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$6748 - attribute \src "issuer_ls180.v:135833.3-135834.43" - wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "issuer_ls180.v:136125.3-136146.6" - wire $0\data_r1__cr_a_ok$next[0:0]$6749 - attribute \src "issuer_ls180.v:135835.3-135836.49" - wire $0\data_r1__cr_a_ok[0:0] - attribute \src "issuer_ls180.v:136147.3-136168.6" - wire width 2 $0\data_r2__xer_ov$next[1:0]$6756 - attribute \src "issuer_ls180.v:135829.3-135830.47" - wire width 2 $0\data_r2__xer_ov[1:0] - attribute \src "issuer_ls180.v:136147.3-136168.6" - wire $0\data_r2__xer_ov_ok$next[0:0]$6757 - attribute \src "issuer_ls180.v:135831.3-135832.53" - wire $0\data_r2__xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:136169.3-136190.6" - wire $0\data_r3__xer_so$next[0:0]$6764 - attribute \src "issuer_ls180.v:135825.3-135826.47" - wire $0\data_r3__xer_so[0:0] - attribute \src "issuer_ls180.v:136169.3-136190.6" - wire $0\data_r3__xer_so_ok$next[0:0]$6765 - attribute \src "issuer_ls180.v:135827.3-135828.53" - wire $0\data_r3__xer_so_ok[0:0] - attribute \src "issuer_ls180.v:136239.3-136248.6" - wire width 64 $0\dest1_o[63:0] - attribute \src "issuer_ls180.v:136249.3-136258.6" - wire width 4 $0\dest2_o[3:0] - attribute \src "issuer_ls180.v:136259.3-136268.6" - wire width 2 $0\dest3_o[1:0] - attribute \src "issuer_ls180.v:136269.3-136278.6" - wire $0\dest4_o[0:0] - attribute \src "issuer_ls180.v:135164.7-135164.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:136025.3-136033.6" - wire $0\opc_l_r_opc$next[0:0]$6694 - attribute \src "issuer_ls180.v:135873.3-135874.39" - wire $0\opc_l_r_opc[0:0] - attribute \src "issuer_ls180.v:136016.3-136024.6" - wire $0\opc_l_s_opc$next[0:0]$6691 - attribute \src "issuer_ls180.v:135875.3-135876.39" - wire $0\opc_l_s_opc[0:0] - attribute \src "issuer_ls180.v:136279.3-136287.6" - wire width 4 $0\prev_wr_go$next[3:0]$6791 - attribute \src "issuer_ls180.v:135885.3-135886.37" - wire width 4 $0\prev_wr_go[3:0] - attribute \src "issuer_ls180.v:135970.3-135979.6" - wire $0\req_done[0:0] - attribute \src "issuer_ls180.v:136061.3-136069.6" - wire width 4 $0\req_l_r_req$next[3:0]$6706 - attribute \src "issuer_ls180.v:135865.3-135866.39" - wire width 4 $0\req_l_r_req[3:0] - attribute \src "issuer_ls180.v:136052.3-136060.6" - wire width 4 $0\req_l_s_req$next[3:0]$6703 - attribute \src "issuer_ls180.v:135867.3-135868.39" - wire width 4 $0\req_l_s_req[3:0] - attribute \src "issuer_ls180.v:135989.3-135997.6" - wire $0\rok_l_r_rdok$next[0:0]$6682 - attribute \src "issuer_ls180.v:135881.3-135882.41" - wire $0\rok_l_r_rdok[0:0] - attribute \src "issuer_ls180.v:135980.3-135988.6" - wire $0\rok_l_s_rdok$next[0:0]$6679 - attribute \src "issuer_ls180.v:135883.3-135884.41" - wire $0\rok_l_s_rdok[0:0] - attribute \src "issuer_ls180.v:136007.3-136015.6" - wire $0\rst_l_r_rst$next[0:0]$6688 - attribute \src "issuer_ls180.v:135877.3-135878.39" - wire $0\rst_l_r_rst[0:0] - attribute \src "issuer_ls180.v:135998.3-136006.6" - wire $0\rst_l_s_rst$next[0:0]$6685 - attribute \src "issuer_ls180.v:135879.3-135880.39" - wire $0\rst_l_s_rst[0:0] - attribute \src "issuer_ls180.v:136043.3-136051.6" - wire width 3 $0\src_l_r_src$next[2:0]$6700 - attribute \src "issuer_ls180.v:135869.3-135870.39" - wire width 3 $0\src_l_r_src[2:0] - attribute \src "issuer_ls180.v:136034.3-136042.6" - wire width 3 $0\src_l_s_src$next[2:0]$6697 - attribute \src "issuer_ls180.v:135871.3-135872.39" - wire width 3 $0\src_l_s_src[2:0] - attribute \src "issuer_ls180.v:136191.3-136200.6" - wire width 64 $0\src_r0$next[63:0]$6772 - attribute \src "issuer_ls180.v:135823.3-135824.29" - wire width 64 $0\src_r0[63:0] - attribute \src "issuer_ls180.v:136201.3-136210.6" - wire width 64 $0\src_r1$next[63:0]$6775 - attribute \src "issuer_ls180.v:135821.3-135822.29" - wire width 64 $0\src_r1[63:0] - attribute \src "issuer_ls180.v:136211.3-136220.6" - wire $0\src_r2$next[0:0]$6778 - attribute \src "issuer_ls180.v:135819.3-135820.29" - wire $0\src_r2[0:0] - attribute \src "issuer_ls180.v:135288.7-135288.24" - wire $1\all_rd_dly[0:0] - attribute \src "issuer_ls180.v:135298.7-135298.26" - wire $1\alu_done_dly[0:0] - attribute \src "issuer_ls180.v:136230.3-136238.6" - wire $1\alu_l_r_alu$next[0:0]$6785 - attribute \src "issuer_ls180.v:135306.7-135306.25" - wire $1\alu_l_r_alu[0:0] - attribute \src "issuer_ls180.v:136070.3-136102.6" - wire width 12 $1\alu_mul0_mul_op__fn_unit$next[11:0]$6721 - attribute \src "issuer_ls180.v:135327.14-135327.48" - wire width 12 $1\alu_mul0_mul_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:136070.3-136102.6" - wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$6722 - attribute \src "issuer_ls180.v:135331.14-135331.68" - wire width 64 $1\alu_mul0_mul_op__imm_data__data[63:0] - attribute \src "issuer_ls180.v:136070.3-136102.6" - wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$6723 - attribute \src "issuer_ls180.v:135335.7-135335.43" - wire $1\alu_mul0_mul_op__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:136070.3-136102.6" - wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$6724 - attribute \src "issuer_ls180.v:135339.14-135339.43" - wire width 32 $1\alu_mul0_mul_op__insn[31:0] - attribute \src "issuer_ls180.v:136070.3-136102.6" - wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$6725 - attribute \src "issuer_ls180.v:135417.13-135417.47" - wire width 7 $1\alu_mul0_mul_op__insn_type[6:0] - attribute \src "issuer_ls180.v:136070.3-136102.6" - wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$6726 - attribute \src "issuer_ls180.v:135421.7-135421.39" - wire $1\alu_mul0_mul_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:136070.3-136102.6" - wire $1\alu_mul0_mul_op__is_signed$next[0:0]$6727 - attribute \src "issuer_ls180.v:135425.7-135425.40" - wire $1\alu_mul0_mul_op__is_signed[0:0] - attribute \src "issuer_ls180.v:136070.3-136102.6" - wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$6728 - attribute \src "issuer_ls180.v:135429.7-135429.37" - wire $1\alu_mul0_mul_op__oe__oe[0:0] - attribute \src "issuer_ls180.v:136070.3-136102.6" - wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$6729 - attribute \src "issuer_ls180.v:135433.7-135433.37" - wire $1\alu_mul0_mul_op__oe__ok[0:0] - attribute \src "issuer_ls180.v:136070.3-136102.6" - wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$6730 - attribute \src "issuer_ls180.v:135437.7-135437.37" - wire $1\alu_mul0_mul_op__rc__ok[0:0] - attribute \src "issuer_ls180.v:136070.3-136102.6" - wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$6731 - attribute \src "issuer_ls180.v:135441.7-135441.37" - wire $1\alu_mul0_mul_op__rc__rc[0:0] - attribute \src "issuer_ls180.v:136070.3-136102.6" - wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$6732 - attribute \src "issuer_ls180.v:135445.7-135445.40" - wire $1\alu_mul0_mul_op__write_cr0[0:0] - attribute \src "issuer_ls180.v:136221.3-136229.6" - wire $1\alui_l_r_alui$next[0:0]$6782 - attribute \src "issuer_ls180.v:135475.7-135475.27" - wire $1\alui_l_r_alui[0:0] - attribute \src "issuer_ls180.v:136103.3-136124.6" - wire width 64 $1\data_r0__o$next[63:0]$6742 - attribute \src "issuer_ls180.v:135509.14-135509.47" - wire width 64 $1\data_r0__o[63:0] - attribute \src "issuer_ls180.v:136103.3-136124.6" - wire $1\data_r0__o_ok$next[0:0]$6743 - attribute \src "issuer_ls180.v:135513.7-135513.27" - wire $1\data_r0__o_ok[0:0] - attribute \src "issuer_ls180.v:136125.3-136146.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$6750 - attribute \src "issuer_ls180.v:135517.13-135517.33" - wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "issuer_ls180.v:136125.3-136146.6" - wire $1\data_r1__cr_a_ok$next[0:0]$6751 - attribute \src "issuer_ls180.v:135521.7-135521.30" - wire $1\data_r1__cr_a_ok[0:0] - attribute \src "issuer_ls180.v:136147.3-136168.6" - wire width 2 $1\data_r2__xer_ov$next[1:0]$6758 - attribute \src "issuer_ls180.v:135525.13-135525.35" - wire width 2 $1\data_r2__xer_ov[1:0] - attribute \src "issuer_ls180.v:136147.3-136168.6" - wire $1\data_r2__xer_ov_ok$next[0:0]$6759 - attribute \src "issuer_ls180.v:135529.7-135529.32" - wire $1\data_r2__xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:136169.3-136190.6" - wire $1\data_r3__xer_so$next[0:0]$6766 - attribute \src "issuer_ls180.v:135533.7-135533.29" - wire $1\data_r3__xer_so[0:0] - attribute \src "issuer_ls180.v:136169.3-136190.6" - wire $1\data_r3__xer_so_ok$next[0:0]$6767 - attribute \src "issuer_ls180.v:135537.7-135537.32" - wire $1\data_r3__xer_so_ok[0:0] - attribute \src "issuer_ls180.v:136239.3-136248.6" - wire width 64 $1\dest1_o[63:0] - attribute \src "issuer_ls180.v:136249.3-136258.6" - wire width 4 $1\dest2_o[3:0] - attribute \src "issuer_ls180.v:136259.3-136268.6" - wire width 2 $1\dest3_o[1:0] - attribute \src "issuer_ls180.v:136269.3-136278.6" - wire $1\dest4_o[0:0] - attribute \src "issuer_ls180.v:136025.3-136033.6" - wire $1\opc_l_r_opc$next[0:0]$6695 - attribute \src "issuer_ls180.v:135557.7-135557.25" - wire $1\opc_l_r_opc[0:0] - attribute \src "issuer_ls180.v:136016.3-136024.6" - wire $1\opc_l_s_opc$next[0:0]$6692 - attribute \src "issuer_ls180.v:135561.7-135561.25" - wire $1\opc_l_s_opc[0:0] - attribute \src "issuer_ls180.v:136279.3-136287.6" - wire width 4 $1\prev_wr_go$next[3:0]$6792 - attribute \src "issuer_ls180.v:135676.13-135676.30" - wire width 4 $1\prev_wr_go[3:0] - attribute \src "issuer_ls180.v:135970.3-135979.6" - wire $1\req_done[0:0] - attribute \src "issuer_ls180.v:136061.3-136069.6" - wire width 4 $1\req_l_r_req$next[3:0]$6707 - attribute \src "issuer_ls180.v:135684.13-135684.31" - wire width 4 $1\req_l_r_req[3:0] - attribute \src "issuer_ls180.v:136052.3-136060.6" - wire width 4 $1\req_l_s_req$next[3:0]$6704 - attribute \src "issuer_ls180.v:135688.13-135688.31" - wire width 4 $1\req_l_s_req[3:0] - attribute \src "issuer_ls180.v:135989.3-135997.6" - wire $1\rok_l_r_rdok$next[0:0]$6683 - attribute \src "issuer_ls180.v:135700.7-135700.26" - wire $1\rok_l_r_rdok[0:0] - attribute \src "issuer_ls180.v:135980.3-135988.6" - wire $1\rok_l_s_rdok$next[0:0]$6680 - attribute \src "issuer_ls180.v:135704.7-135704.26" - wire $1\rok_l_s_rdok[0:0] - attribute \src "issuer_ls180.v:136007.3-136015.6" - wire $1\rst_l_r_rst$next[0:0]$6689 - attribute \src "issuer_ls180.v:135708.7-135708.25" - wire $1\rst_l_r_rst[0:0] - attribute \src "issuer_ls180.v:135998.3-136006.6" - wire $1\rst_l_s_rst$next[0:0]$6686 - attribute \src "issuer_ls180.v:135712.7-135712.25" - wire $1\rst_l_s_rst[0:0] - attribute \src "issuer_ls180.v:136043.3-136051.6" - wire width 3 $1\src_l_r_src$next[2:0]$6701 - attribute \src "issuer_ls180.v:135726.13-135726.31" - wire width 3 $1\src_l_r_src[2:0] - attribute \src "issuer_ls180.v:136034.3-136042.6" - wire width 3 $1\src_l_s_src$next[2:0]$6698 - attribute \src "issuer_ls180.v:135730.13-135730.31" - wire width 3 $1\src_l_s_src[2:0] - attribute \src "issuer_ls180.v:136191.3-136200.6" - wire width 64 $1\src_r0$next[63:0]$6773 - attribute \src "issuer_ls180.v:135736.14-135736.43" - wire width 64 $1\src_r0[63:0] - attribute \src "issuer_ls180.v:136201.3-136210.6" - wire width 64 $1\src_r1$next[63:0]$6776 - attribute \src "issuer_ls180.v:135740.14-135740.43" - wire width 64 $1\src_r1[63:0] - attribute \src "issuer_ls180.v:136211.3-136220.6" - wire $1\src_r2$next[0:0]$6779 - attribute \src "issuer_ls180.v:135744.7-135744.20" - wire $1\src_r2[0:0] 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wire \all_rd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \all_rd_dly$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" - wire \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \all_rd_rise - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" - wire \alu_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \alu_done_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \alu_l_s_alu - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \alu_mul0_cr_a - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_mul0_mul_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_mul0_mul_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_mul0_mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_mul0_mul_op__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_mul0_mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_mul0_mul_op__imm_data__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_mul0_mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_mul0_mul_op__insn$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_mul0_mul_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_mul0_mul_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_mul0_mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_mul0_mul_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_mul0_mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_mul0_mul_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_mul0_mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_mul0_mul_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_mul0_mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_mul0_mul_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_mul0_mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_mul0_mul_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_mul0_mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_mul0_mul_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_mul0_mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_mul0_mul_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \alu_mul0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \alu_mul0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_mul0_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \alu_mul0_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \alu_mul0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_mul0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_mul0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \alu_mul0_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \alu_mul0_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \alu_mul0_xer_so$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 4 \alu_pulsem - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 32 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 31 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 25 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 14 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 13 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 17 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 16 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 15 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" - wire \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 23 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 22 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 4 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r0__o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r1__cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r2__xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r2__xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r2__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r2__xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r3__xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r3__xer_so$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r3__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r3__xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 24 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 26 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 28 \dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire output 30 \dest4_o - attribute \src "issuer_ls180.v:135164.7-135164.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 21 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \opc_l_s_opc$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \oper_i_alu_mul0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \oper_i_alu_mul0__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \oper_i_alu_mul0__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 12 \oper_i_alu_mul0__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 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$not$issuer_ls180.v:135781$6605_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$issuer_ls180.v:135792$6616 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__rel_o - connect \Y $not$issuer_ls180.v:135792$6616_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$issuer_ls180.v:135812$6636 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_mul0_mul_op__imm_data__ok - connect \Y $not$issuer_ls180.v:135812$6636_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$issuer_ls180.v:135814$6638 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rdmaskn_i - connect \Y $not$issuer_ls180.v:135814$6638_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$issuer_ls180.v:135780$6604 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$32 - connect \B \$34 - connect \Y $or$issuer_ls180.v:135780$6604_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$issuer_ls180.v:135790$6614 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $or$issuer_ls180.v:135790$6614_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$issuer_ls180.v:135791$6615 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $or$issuer_ls180.v:135791$6615_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$issuer_ls180.v:135793$6617 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$issuer_ls180.v:135793$6617_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$issuer_ls180.v:135794$6618 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$issuer_ls180.v:135794$6618_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$issuer_ls180.v:135797$6621 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $or$issuer_ls180.v:135797$6621_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$issuer_ls180.v:135803$6627 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$5 - connect \B \cu_rd__go_i - connect \Y $or$issuer_ls180.v:135803$6627_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$issuer_ls180.v:135809$6633 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \$7 - connect \Y $reduce_and$issuer_ls180.v:135809$6633_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$issuer_ls180.v:135774$6598 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \$26 - connect \Y $reduce_or$issuer_ls180.v:135774$6598_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$issuer_ls180.v:135778$6602 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $reduce_or$issuer_ls180.v:135778$6602_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$issuer_ls180.v:135779$6603 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $reduce_or$issuer_ls180.v:135779$6603_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$issuer_ls180.v:135802$6626 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $ternary$issuer_ls180.v:135802$6626_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$issuer_ls180.v:135804$6628 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \alu_mul0_mul_op__imm_data__data - connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $ternary$issuer_ls180.v:135804$6628_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:135805$6629 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src1_i - connect \S \src_l_q_src [0] - connect \Y $ternary$issuer_ls180.v:135805$6629_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:135806$6630 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $ternary$issuer_ls180.v:135806$6630_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:135807$6631 - parameter \WIDTH 1 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $ternary$issuer_ls180.v:135807$6631_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:135891.15-135897.4" - cell \alu_l$104 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:135898.12-135928.4" - cell \alu_mul0 \alu_mul0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \alu_mul0_cr_a - connect \cr_a_ok \cr_a_ok - connect \mul_op__fn_unit \alu_mul0_mul_op__fn_unit - connect \mul_op__imm_data__data \alu_mul0_mul_op__imm_data__data - connect \mul_op__imm_data__ok \alu_mul0_mul_op__imm_data__ok - connect \mul_op__insn \alu_mul0_mul_op__insn - connect \mul_op__insn_type \alu_mul0_mul_op__insn_type - connect \mul_op__is_32bit \alu_mul0_mul_op__is_32bit - connect \mul_op__is_signed \alu_mul0_mul_op__is_signed - connect \mul_op__oe__oe \alu_mul0_mul_op__oe__oe - connect \mul_op__oe__ok \alu_mul0_mul_op__oe__ok - connect \mul_op__rc__ok \alu_mul0_mul_op__rc__ok - connect \mul_op__rc__rc \alu_mul0_mul_op__rc__rc - connect \mul_op__write_cr0 \alu_mul0_mul_op__write_cr0 - connect \n_ready_i \alu_mul0_n_ready_i - connect \n_valid_o \alu_mul0_n_valid_o - connect \o \alu_mul0_o - connect \o_ok \o_ok - connect \p_ready_o \alu_mul0_p_ready_o - connect \p_valid_i \alu_mul0_p_valid_i - connect \ra \alu_mul0_ra - connect \rb \alu_mul0_rb - connect \xer_ov \alu_mul0_xer_ov - connect \xer_ov_ok \xer_ov_ok - connect \xer_so \alu_mul0_xer_so - connect \xer_so$1 \alu_mul0_xer_so$1 - connect \xer_so_ok \xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:135929.16-135935.4" - cell \alui_l$103 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:135936.14-135942.4" - cell \opc_l$99 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_opc \opc_l_q_opc - connect \r_opc \opc_l_r_opc - connect \s_opc \opc_l_s_opc - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:135943.15-135949.4" - cell \req_l$100 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \r_req \req_l_r_req - connect \s_req \req_l_s_req - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:135950.15-135956.4" - cell \rok_l$102 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \r_rdok \rok_l_r_rdok - connect \s_rdok \rok_l_s_rdok - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:135957.15-135962.4" - cell \rst_l$101 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_rst \rst_l_r_rst - connect \s_rst \rst_l_s_rst - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:135963.14-135969.4" - cell \src_l$98 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_src \src_l_q_src - connect \r_src \src_l_r_src - connect \s_src \src_l_s_src - end - attribute \src "issuer_ls180.v:135164.7-135164.20" - process $proc$issuer_ls180.v:135164$6793 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:135288.7-135288.24" - process $proc$issuer_ls180.v:135288$6794 - assign { } { } - assign $1\all_rd_dly[0:0] 1'0 - sync always - sync init - update \all_rd_dly $1\all_rd_dly[0:0] - end - attribute \src "issuer_ls180.v:135298.7-135298.26" - process $proc$issuer_ls180.v:135298$6795 - assign { } { } - assign $1\alu_done_dly[0:0] 1'0 - sync always - sync init - update \alu_done_dly $1\alu_done_dly[0:0] - end - attribute \src "issuer_ls180.v:135306.7-135306.25" - process $proc$issuer_ls180.v:135306$6796 - assign { } { } - assign $1\alu_l_r_alu[0:0] 1'1 - sync always - sync init - update \alu_l_r_alu $1\alu_l_r_alu[0:0] - end - attribute \src "issuer_ls180.v:135327.14-135327.48" - process $proc$issuer_ls180.v:135327$6797 - assign { } { } - assign $1\alu_mul0_mul_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \alu_mul0_mul_op__fn_unit $1\alu_mul0_mul_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:135331.14-135331.68" - process $proc$issuer_ls180.v:135331$6798 - assign { } { } - assign $1\alu_mul0_mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_mul0_mul_op__imm_data__data $1\alu_mul0_mul_op__imm_data__data[63:0] - end - attribute \src "issuer_ls180.v:135335.7-135335.43" - process $proc$issuer_ls180.v:135335$6799 - assign { } { } - assign $1\alu_mul0_mul_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \alu_mul0_mul_op__imm_data__ok $1\alu_mul0_mul_op__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:135339.14-135339.43" - process $proc$issuer_ls180.v:135339$6800 - assign { } { } - assign $1\alu_mul0_mul_op__insn[31:0] 0 - sync always - sync init - update \alu_mul0_mul_op__insn $1\alu_mul0_mul_op__insn[31:0] - end - attribute \src "issuer_ls180.v:135417.13-135417.47" - process $proc$issuer_ls180.v:135417$6801 - assign { } { } - assign $1\alu_mul0_mul_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \alu_mul0_mul_op__insn_type $1\alu_mul0_mul_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:135421.7-135421.39" - process $proc$issuer_ls180.v:135421$6802 - assign { } { } - assign $1\alu_mul0_mul_op__is_32bit[0:0] 1'0 - sync always - sync init - update \alu_mul0_mul_op__is_32bit $1\alu_mul0_mul_op__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:135425.7-135425.40" - process $proc$issuer_ls180.v:135425$6803 - assign { } { } - assign $1\alu_mul0_mul_op__is_signed[0:0] 1'0 - sync always - sync init - update \alu_mul0_mul_op__is_signed $1\alu_mul0_mul_op__is_signed[0:0] - end - attribute \src "issuer_ls180.v:135429.7-135429.37" - process $proc$issuer_ls180.v:135429$6804 - assign { } { } - assign $1\alu_mul0_mul_op__oe__oe[0:0] 1'0 - sync always - sync init - update \alu_mul0_mul_op__oe__oe $1\alu_mul0_mul_op__oe__oe[0:0] - end - attribute \src "issuer_ls180.v:135433.7-135433.37" - process $proc$issuer_ls180.v:135433$6805 - assign { } { } - assign $1\alu_mul0_mul_op__oe__ok[0:0] 1'0 - sync always - sync init - update \alu_mul0_mul_op__oe__ok $1\alu_mul0_mul_op__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:135437.7-135437.37" - process $proc$issuer_ls180.v:135437$6806 - assign { } { } - assign $1\alu_mul0_mul_op__rc__ok[0:0] 1'0 - sync always - sync init - update \alu_mul0_mul_op__rc__ok $1\alu_mul0_mul_op__rc__ok[0:0] - end - attribute \src "issuer_ls180.v:135441.7-135441.37" - process $proc$issuer_ls180.v:135441$6807 - assign { } { } - assign $1\alu_mul0_mul_op__rc__rc[0:0] 1'0 - sync always - sync init - update \alu_mul0_mul_op__rc__rc $1\alu_mul0_mul_op__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:135445.7-135445.40" - process $proc$issuer_ls180.v:135445$6808 - assign { } { } - assign $1\alu_mul0_mul_op__write_cr0[0:0] 1'0 - sync always - sync init - update \alu_mul0_mul_op__write_cr0 $1\alu_mul0_mul_op__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:135475.7-135475.27" - process $proc$issuer_ls180.v:135475$6809 - assign { } { } - assign $1\alui_l_r_alui[0:0] 1'1 - sync always - sync init - update \alui_l_r_alui $1\alui_l_r_alui[0:0] - end - attribute \src "issuer_ls180.v:135509.14-135509.47" - process $proc$issuer_ls180.v:135509$6810 - assign { } { } - assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r0__o $1\data_r0__o[63:0] - end - attribute \src "issuer_ls180.v:135513.7-135513.27" - process $proc$issuer_ls180.v:135513$6811 - assign { } { } - assign $1\data_r0__o_ok[0:0] 1'0 - sync always - sync init - update \data_r0__o_ok $1\data_r0__o_ok[0:0] - end - attribute \src "issuer_ls180.v:135517.13-135517.33" - process $proc$issuer_ls180.v:135517$6812 - assign { } { } - assign $1\data_r1__cr_a[3:0] 4'0000 - sync always - sync init - update \data_r1__cr_a $1\data_r1__cr_a[3:0] - end - attribute \src "issuer_ls180.v:135521.7-135521.30" - process $proc$issuer_ls180.v:135521$6813 - assign { } { } - assign $1\data_r1__cr_a_ok[0:0] 1'0 - sync always - sync init - update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:135525.13-135525.35" - process $proc$issuer_ls180.v:135525$6814 - assign { } { } - assign $1\data_r2__xer_ov[1:0] 2'00 - sync always - sync init - update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] - end - attribute \src "issuer_ls180.v:135529.7-135529.32" - process $proc$issuer_ls180.v:135529$6815 - assign { } { } - assign $1\data_r2__xer_ov_ok[0:0] 1'0 - sync always - sync init - update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] - end - attribute \src "issuer_ls180.v:135533.7-135533.29" - process $proc$issuer_ls180.v:135533$6816 - assign { } { } - assign $1\data_r3__xer_so[0:0] 1'0 - sync always - sync init - update \data_r3__xer_so $1\data_r3__xer_so[0:0] - end - attribute \src "issuer_ls180.v:135537.7-135537.32" - process $proc$issuer_ls180.v:135537$6817 - assign { } { } - assign $1\data_r3__xer_so_ok[0:0] 1'0 - sync always - sync init - update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] - end - attribute \src "issuer_ls180.v:135557.7-135557.25" - process $proc$issuer_ls180.v:135557$6818 - assign { } { } - assign $1\opc_l_r_opc[0:0] 1'1 - sync always - sync init - update \opc_l_r_opc $1\opc_l_r_opc[0:0] - end - attribute \src "issuer_ls180.v:135561.7-135561.25" - process $proc$issuer_ls180.v:135561$6819 - assign { } { } - assign $1\opc_l_s_opc[0:0] 1'0 - sync always - sync init - update \opc_l_s_opc $1\opc_l_s_opc[0:0] - end - attribute \src "issuer_ls180.v:135676.13-135676.30" - process $proc$issuer_ls180.v:135676$6820 - assign { } { } - assign $1\prev_wr_go[3:0] 4'0000 - sync always - sync init - update \prev_wr_go $1\prev_wr_go[3:0] - end - attribute \src "issuer_ls180.v:135684.13-135684.31" - process $proc$issuer_ls180.v:135684$6821 - assign { } { } - assign $1\req_l_r_req[3:0] 4'1111 - sync always - sync init - update \req_l_r_req $1\req_l_r_req[3:0] - end - attribute \src "issuer_ls180.v:135688.13-135688.31" - process $proc$issuer_ls180.v:135688$6822 - assign { } { } - assign $1\req_l_s_req[3:0] 4'0000 - sync always - sync init - update \req_l_s_req $1\req_l_s_req[3:0] - end - attribute \src "issuer_ls180.v:135700.7-135700.26" - process $proc$issuer_ls180.v:135700$6823 - assign { } { } - assign $1\rok_l_r_rdok[0:0] 1'1 - sync always - sync init - update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] - end - attribute \src "issuer_ls180.v:135704.7-135704.26" - process $proc$issuer_ls180.v:135704$6824 - assign { } { } - assign $1\rok_l_s_rdok[0:0] 1'0 - sync always - sync init - update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] - end - attribute \src "issuer_ls180.v:135708.7-135708.25" - process $proc$issuer_ls180.v:135708$6825 - assign { } { } - assign $1\rst_l_r_rst[0:0] 1'1 - sync always - sync init - update \rst_l_r_rst $1\rst_l_r_rst[0:0] - end - attribute \src "issuer_ls180.v:135712.7-135712.25" - process $proc$issuer_ls180.v:135712$6826 - assign { } { } - assign $1\rst_l_s_rst[0:0] 1'0 - sync always - sync init - update \rst_l_s_rst $1\rst_l_s_rst[0:0] - end - attribute \src "issuer_ls180.v:135726.13-135726.31" - process $proc$issuer_ls180.v:135726$6827 - assign { } { } - assign $1\src_l_r_src[2:0] 3'111 - sync always - sync init - update \src_l_r_src $1\src_l_r_src[2:0] - end - attribute \src "issuer_ls180.v:135730.13-135730.31" - process $proc$issuer_ls180.v:135730$6828 - assign { } { } - assign $1\src_l_s_src[2:0] 3'000 - sync always - sync init - update \src_l_s_src $1\src_l_s_src[2:0] - end - attribute \src "issuer_ls180.v:135736.14-135736.43" - process $proc$issuer_ls180.v:135736$6829 - assign { } { } - assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r0 $1\src_r0[63:0] - end - attribute \src "issuer_ls180.v:135740.14-135740.43" - process $proc$issuer_ls180.v:135740$6830 - assign { } { } - assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r1 $1\src_r1[63:0] - end - attribute \src "issuer_ls180.v:135744.7-135744.20" - process $proc$issuer_ls180.v:135744$6831 - assign { } { } - assign $1\src_r2[0:0] 1'0 - sync always - sync init - update \src_r2 $1\src_r2[0:0] - end - attribute \src "issuer_ls180.v:135815.3-135816.39" - process $proc$issuer_ls180.v:135815$6639 - assign { } { } - assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next - sync posedge \coresync_clk - update \alu_l_r_alu $0\alu_l_r_alu[0:0] - end - attribute \src "issuer_ls180.v:135817.3-135818.43" - process $proc$issuer_ls180.v:135817$6640 - assign { } { } - assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next - sync posedge \coresync_clk - update \alui_l_r_alui $0\alui_l_r_alui[0:0] - end - attribute \src "issuer_ls180.v:135819.3-135820.29" - process $proc$issuer_ls180.v:135819$6641 - assign { } { } - assign $0\src_r2[0:0] \src_r2$next - sync posedge \coresync_clk - update \src_r2 $0\src_r2[0:0] - end - attribute \src "issuer_ls180.v:135821.3-135822.29" - process $proc$issuer_ls180.v:135821$6642 - assign { } { } - assign $0\src_r1[63:0] \src_r1$next - sync posedge \coresync_clk - update \src_r1 $0\src_r1[63:0] - end - attribute \src "issuer_ls180.v:135823.3-135824.29" - process $proc$issuer_ls180.v:135823$6643 - assign { } { } - assign $0\src_r0[63:0] \src_r0$next - sync posedge \coresync_clk - update \src_r0 $0\src_r0[63:0] - end - attribute \src "issuer_ls180.v:135825.3-135826.47" - process $proc$issuer_ls180.v:135825$6644 - assign { } { } - assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next - sync posedge \coresync_clk - update \data_r3__xer_so $0\data_r3__xer_so[0:0] - end - attribute \src "issuer_ls180.v:135827.3-135828.53" - process $proc$issuer_ls180.v:135827$6645 - assign { } { } - assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next - sync posedge \coresync_clk - update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] - end - attribute \src "issuer_ls180.v:135829.3-135830.47" - process $proc$issuer_ls180.v:135829$6646 - assign { } { } - assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next - sync posedge \coresync_clk - update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] - end - attribute \src "issuer_ls180.v:135831.3-135832.53" - process $proc$issuer_ls180.v:135831$6647 - assign { } { } - assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next - sync posedge \coresync_clk - update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] - end - attribute \src "issuer_ls180.v:135833.3-135834.43" - process $proc$issuer_ls180.v:135833$6648 - assign { } { } - assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next - sync posedge \coresync_clk - update \data_r1__cr_a $0\data_r1__cr_a[3:0] - end - attribute \src "issuer_ls180.v:135835.3-135836.49" - process $proc$issuer_ls180.v:135835$6649 - assign { } { } - assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next - sync posedge \coresync_clk - update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:135837.3-135838.37" - process $proc$issuer_ls180.v:135837$6650 - assign { } { } - assign $0\data_r0__o[63:0] \data_r0__o$next - sync posedge \coresync_clk - update \data_r0__o $0\data_r0__o[63:0] - end - attribute \src "issuer_ls180.v:135839.3-135840.43" - process $proc$issuer_ls180.v:135839$6651 - assign { } { } - assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next - sync posedge \coresync_clk - update \data_r0__o_ok $0\data_r0__o_ok[0:0] - end - attribute \src "issuer_ls180.v:135841.3-135842.69" - process $proc$issuer_ls180.v:135841$6652 - assign { } { } - assign $0\alu_mul0_mul_op__insn_type[6:0] \alu_mul0_mul_op__insn_type$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__insn_type $0\alu_mul0_mul_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:135843.3-135844.65" - process $proc$issuer_ls180.v:135843$6653 - assign { } { } - assign $0\alu_mul0_mul_op__fn_unit[11:0] \alu_mul0_mul_op__fn_unit$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__fn_unit $0\alu_mul0_mul_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:135845.3-135846.79" - process $proc$issuer_ls180.v:135845$6654 - assign { } { } - assign $0\alu_mul0_mul_op__imm_data__data[63:0] \alu_mul0_mul_op__imm_data__data$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__imm_data__data $0\alu_mul0_mul_op__imm_data__data[63:0] - end - attribute \src "issuer_ls180.v:135847.3-135848.75" - process $proc$issuer_ls180.v:135847$6655 - assign { } { } - assign $0\alu_mul0_mul_op__imm_data__ok[0:0] \alu_mul0_mul_op__imm_data__ok$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__imm_data__ok $0\alu_mul0_mul_op__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:135849.3-135850.63" - process $proc$issuer_ls180.v:135849$6656 - assign { } { } - assign $0\alu_mul0_mul_op__rc__rc[0:0] \alu_mul0_mul_op__rc__rc$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__rc__rc $0\alu_mul0_mul_op__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:135851.3-135852.63" - process $proc$issuer_ls180.v:135851$6657 - assign { } { } - assign $0\alu_mul0_mul_op__rc__ok[0:0] \alu_mul0_mul_op__rc__ok$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__rc__ok $0\alu_mul0_mul_op__rc__ok[0:0] - end - attribute \src "issuer_ls180.v:135853.3-135854.63" - process $proc$issuer_ls180.v:135853$6658 - assign { } { } - assign $0\alu_mul0_mul_op__oe__oe[0:0] \alu_mul0_mul_op__oe__oe$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__oe__oe $0\alu_mul0_mul_op__oe__oe[0:0] - end - attribute \src "issuer_ls180.v:135855.3-135856.63" - process $proc$issuer_ls180.v:135855$6659 - assign { } { } - assign $0\alu_mul0_mul_op__oe__ok[0:0] \alu_mul0_mul_op__oe__ok$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__oe__ok $0\alu_mul0_mul_op__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:135857.3-135858.69" - process $proc$issuer_ls180.v:135857$6660 - assign { } { } - assign $0\alu_mul0_mul_op__write_cr0[0:0] \alu_mul0_mul_op__write_cr0$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__write_cr0 $0\alu_mul0_mul_op__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:135859.3-135860.67" - process $proc$issuer_ls180.v:135859$6661 - assign { } { } - assign $0\alu_mul0_mul_op__is_32bit[0:0] \alu_mul0_mul_op__is_32bit$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__is_32bit $0\alu_mul0_mul_op__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:135861.3-135862.69" - process $proc$issuer_ls180.v:135861$6662 - assign { } { } - assign $0\alu_mul0_mul_op__is_signed[0:0] \alu_mul0_mul_op__is_signed$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__is_signed $0\alu_mul0_mul_op__is_signed[0:0] - end - attribute \src "issuer_ls180.v:135863.3-135864.59" - process $proc$issuer_ls180.v:135863$6663 - assign { } { } - assign $0\alu_mul0_mul_op__insn[31:0] \alu_mul0_mul_op__insn$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__insn $0\alu_mul0_mul_op__insn[31:0] - end - attribute \src "issuer_ls180.v:135865.3-135866.39" - process $proc$issuer_ls180.v:135865$6664 - assign { } { } - assign $0\req_l_r_req[3:0] \req_l_r_req$next - sync posedge \coresync_clk - update \req_l_r_req $0\req_l_r_req[3:0] - end - attribute \src "issuer_ls180.v:135867.3-135868.39" - process $proc$issuer_ls180.v:135867$6665 - assign { } { } - assign $0\req_l_s_req[3:0] \req_l_s_req$next - sync posedge \coresync_clk - update \req_l_s_req $0\req_l_s_req[3:0] - end - attribute \src "issuer_ls180.v:135869.3-135870.39" - process $proc$issuer_ls180.v:135869$6666 - assign { } { } - assign $0\src_l_r_src[2:0] \src_l_r_src$next - sync posedge \coresync_clk - update \src_l_r_src $0\src_l_r_src[2:0] - end - attribute \src "issuer_ls180.v:135871.3-135872.39" - process $proc$issuer_ls180.v:135871$6667 - assign { } { } - assign $0\src_l_s_src[2:0] \src_l_s_src$next - sync posedge \coresync_clk - update \src_l_s_src $0\src_l_s_src[2:0] - end - attribute \src "issuer_ls180.v:135873.3-135874.39" - process $proc$issuer_ls180.v:135873$6668 - assign { } { } - assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next - sync posedge \coresync_clk - update \opc_l_r_opc $0\opc_l_r_opc[0:0] - end - attribute \src "issuer_ls180.v:135875.3-135876.39" - process $proc$issuer_ls180.v:135875$6669 - assign { } { } - assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next - sync posedge \coresync_clk - update \opc_l_s_opc $0\opc_l_s_opc[0:0] - end - attribute \src "issuer_ls180.v:135877.3-135878.39" - process $proc$issuer_ls180.v:135877$6670 - assign { } { } - assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next - sync posedge \coresync_clk - update \rst_l_r_rst $0\rst_l_r_rst[0:0] - end - attribute \src "issuer_ls180.v:135879.3-135880.39" - process $proc$issuer_ls180.v:135879$6671 - assign { } { } - assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next - sync posedge \coresync_clk - update \rst_l_s_rst $0\rst_l_s_rst[0:0] - end - attribute \src "issuer_ls180.v:135881.3-135882.41" - process $proc$issuer_ls180.v:135881$6672 - assign { } { } - assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next - sync posedge \coresync_clk - update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] - end - attribute \src "issuer_ls180.v:135883.3-135884.41" - process $proc$issuer_ls180.v:135883$6673 - assign { } { } - assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next - sync posedge \coresync_clk - update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] - end - attribute \src "issuer_ls180.v:135885.3-135886.37" - process $proc$issuer_ls180.v:135885$6674 - assign { } { } - assign $0\prev_wr_go[3:0] \prev_wr_go$next - sync posedge \coresync_clk - update \prev_wr_go $0\prev_wr_go[3:0] - end - attribute \src "issuer_ls180.v:135887.3-135888.40" - process $proc$issuer_ls180.v:135887$6675 - assign { } { } - assign $0\alu_done_dly[0:0] \alu_mul0_n_valid_o - sync posedge \coresync_clk - update \alu_done_dly $0\alu_done_dly[0:0] - end - attribute \src "issuer_ls180.v:135889.3-135890.25" - process $proc$issuer_ls180.v:135889$6676 - assign { } { } - assign $0\all_rd_dly[0:0] \$10 - sync posedge \coresync_clk - update \all_rd_dly $0\all_rd_dly[0:0] - end - attribute \src "issuer_ls180.v:135970.3-135979.6" - process $proc$issuer_ls180.v:135970$6677 - assign { } { } - assign { } { } - assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "issuer_ls180.v:135971.5-135971.29" - switch \initial - attribute \src "issuer_ls180.v:135971.9-135971.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch \$54 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_done[0:0] 1'1 - case - assign $1\req_done[0:0] \$46 - end - sync always - update \req_done $0\req_done[0:0] - end - attribute \src "issuer_ls180.v:135980.3-135988.6" - process $proc$issuer_ls180.v:135980$6678 - assign { } { } - assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$6679 $1\rok_l_s_rdok$next[0:0]$6680 - attribute \src "issuer_ls180.v:135981.5-135981.29" - switch \initial - attribute \src "issuer_ls180.v:135981.9-135981.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$6680 1'0 - case - assign $1\rok_l_s_rdok$next[0:0]$6680 \cu_issue_i - end - sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6679 - end - attribute \src "issuer_ls180.v:135989.3-135997.6" - process $proc$issuer_ls180.v:135989$6681 - assign { } { } - assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$6682 $1\rok_l_r_rdok$next[0:0]$6683 - attribute \src "issuer_ls180.v:135990.5-135990.29" - switch \initial - attribute \src "issuer_ls180.v:135990.9-135990.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$6683 1'1 - case - assign $1\rok_l_r_rdok$next[0:0]$6683 \$64 - end - sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6682 - end - attribute \src "issuer_ls180.v:135998.3-136006.6" - process $proc$issuer_ls180.v:135998$6684 - assign { } { } - assign { } { } - assign $0\rst_l_s_rst$next[0:0]$6685 $1\rst_l_s_rst$next[0:0]$6686 - attribute \src "issuer_ls180.v:135999.5-135999.29" - switch \initial - attribute \src "issuer_ls180.v:135999.9-135999.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_s_rst$next[0:0]$6686 1'0 - case - assign $1\rst_l_s_rst$next[0:0]$6686 \all_rd - end - sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6685 - end - attribute \src "issuer_ls180.v:136007.3-136015.6" - process $proc$issuer_ls180.v:136007$6687 - assign { } { } - assign { } { } - assign $0\rst_l_r_rst$next[0:0]$6688 $1\rst_l_r_rst$next[0:0]$6689 - attribute \src "issuer_ls180.v:136008.5-136008.29" - switch \initial - attribute \src "issuer_ls180.v:136008.9-136008.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_r_rst$next[0:0]$6689 1'1 - case - assign $1\rst_l_r_rst$next[0:0]$6689 \rst_r - end - sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6688 - end - attribute \src "issuer_ls180.v:136016.3-136024.6" - process $proc$issuer_ls180.v:136016$6690 - assign { } { } - assign { } { } - assign $0\opc_l_s_opc$next[0:0]$6691 $1\opc_l_s_opc$next[0:0]$6692 - attribute \src "issuer_ls180.v:136017.5-136017.29" - switch \initial - attribute \src "issuer_ls180.v:136017.9-136017.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_s_opc$next[0:0]$6692 1'0 - case - assign $1\opc_l_s_opc$next[0:0]$6692 \cu_issue_i - end - sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6691 - end - attribute \src "issuer_ls180.v:136025.3-136033.6" - process $proc$issuer_ls180.v:136025$6693 - assign { } { } - assign { } { } - assign $0\opc_l_r_opc$next[0:0]$6694 $1\opc_l_r_opc$next[0:0]$6695 - attribute \src "issuer_ls180.v:136026.5-136026.29" - switch \initial - attribute \src "issuer_ls180.v:136026.9-136026.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_r_opc$next[0:0]$6695 1'1 - case - assign $1\opc_l_r_opc$next[0:0]$6695 \req_done - end - sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6694 - end - attribute \src "issuer_ls180.v:136034.3-136042.6" - process $proc$issuer_ls180.v:136034$6696 - assign { } { } - assign { } { } - assign $0\src_l_s_src$next[2:0]$6697 $1\src_l_s_src$next[2:0]$6698 - attribute \src "issuer_ls180.v:136035.5-136035.29" - switch \initial - attribute \src "issuer_ls180.v:136035.9-136035.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_s_src$next[2:0]$6698 3'000 - case - assign $1\src_l_s_src$next[2:0]$6698 { \cu_issue_i \cu_issue_i \cu_issue_i } - end - sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6697 - end - attribute \src "issuer_ls180.v:136043.3-136051.6" - process $proc$issuer_ls180.v:136043$6699 - assign { } { } - assign { } { } - assign $0\src_l_r_src$next[2:0]$6700 $1\src_l_r_src$next[2:0]$6701 - attribute \src "issuer_ls180.v:136044.5-136044.29" - switch \initial - attribute \src "issuer_ls180.v:136044.9-136044.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_r_src$next[2:0]$6701 3'111 - case - assign $1\src_l_r_src$next[2:0]$6701 \reset_r - end - sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6700 - end - attribute \src "issuer_ls180.v:136052.3-136060.6" - process $proc$issuer_ls180.v:136052$6702 - assign { } { } - assign { } { } - assign $0\req_l_s_req$next[3:0]$6703 $1\req_l_s_req$next[3:0]$6704 - attribute \src "issuer_ls180.v:136053.5-136053.29" - switch \initial - attribute \src "issuer_ls180.v:136053.9-136053.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_s_req$next[3:0]$6704 4'0000 - case - assign $1\req_l_s_req$next[3:0]$6704 \$66 - end - sync always - update \req_l_s_req$next $0\req_l_s_req$next[3:0]$6703 - end - attribute \src "issuer_ls180.v:136061.3-136069.6" - process $proc$issuer_ls180.v:136061$6705 - assign { } { } - assign { } { } - assign $0\req_l_r_req$next[3:0]$6706 $1\req_l_r_req$next[3:0]$6707 - attribute \src "issuer_ls180.v:136062.5-136062.29" - switch \initial - attribute \src "issuer_ls180.v:136062.9-136062.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_r_req$next[3:0]$6707 4'1111 - case - assign $1\req_l_r_req$next[3:0]$6707 \$68 - end - sync always - update \req_l_r_req$next $0\req_l_r_req$next[3:0]$6706 - end - attribute \src "issuer_ls180.v:136070.3-136102.6" - process $proc$issuer_ls180.v:136070$6708 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_mul0_mul_op__fn_unit$next[11:0]$6709 $1\alu_mul0_mul_op__fn_unit$next[11:0]$6721 - assign { } { } - assign { } { } - assign $0\alu_mul0_mul_op__insn$next[31:0]$6712 $1\alu_mul0_mul_op__insn$next[31:0]$6724 - assign $0\alu_mul0_mul_op__insn_type$next[6:0]$6713 $1\alu_mul0_mul_op__insn_type$next[6:0]$6725 - assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$6714 $1\alu_mul0_mul_op__is_32bit$next[0:0]$6726 - assign $0\alu_mul0_mul_op__is_signed$next[0:0]$6715 $1\alu_mul0_mul_op__is_signed$next[0:0]$6727 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$6720 $1\alu_mul0_mul_op__write_cr0$next[0:0]$6732 - assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$6710 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$6733 - assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$6711 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$6734 - assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$6716 $2\alu_mul0_mul_op__oe__oe$next[0:0]$6735 - assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$6717 $2\alu_mul0_mul_op__oe__ok$next[0:0]$6736 - assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$6718 $2\alu_mul0_mul_op__rc__ok$next[0:0]$6737 - assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$6719 $2\alu_mul0_mul_op__rc__rc$next[0:0]$6738 - attribute \src "issuer_ls180.v:136071.5-136071.29" - switch \initial - attribute \src "issuer_ls180.v:136071.9-136071.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_mul0_mul_op__insn$next[31:0]$6724 $1\alu_mul0_mul_op__is_signed$next[0:0]$6727 $1\alu_mul0_mul_op__is_32bit$next[0:0]$6726 $1\alu_mul0_mul_op__write_cr0$next[0:0]$6732 $1\alu_mul0_mul_op__oe__ok$next[0:0]$6729 $1\alu_mul0_mul_op__oe__oe$next[0:0]$6728 $1\alu_mul0_mul_op__rc__ok$next[0:0]$6730 $1\alu_mul0_mul_op__rc__rc$next[0:0]$6731 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$6723 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$6722 $1\alu_mul0_mul_op__fn_unit$next[11:0]$6721 $1\alu_mul0_mul_op__insn_type$next[6:0]$6725 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } - case - assign $1\alu_mul0_mul_op__fn_unit$next[11:0]$6721 \alu_mul0_mul_op__fn_unit - assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$6722 \alu_mul0_mul_op__imm_data__data - assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$6723 \alu_mul0_mul_op__imm_data__ok - assign $1\alu_mul0_mul_op__insn$next[31:0]$6724 \alu_mul0_mul_op__insn - assign $1\alu_mul0_mul_op__insn_type$next[6:0]$6725 \alu_mul0_mul_op__insn_type - assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$6726 \alu_mul0_mul_op__is_32bit - assign $1\alu_mul0_mul_op__is_signed$next[0:0]$6727 \alu_mul0_mul_op__is_signed - assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$6728 \alu_mul0_mul_op__oe__oe - assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$6729 \alu_mul0_mul_op__oe__ok - assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$6730 \alu_mul0_mul_op__rc__ok - assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$6731 \alu_mul0_mul_op__rc__rc - assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$6732 \alu_mul0_mul_op__write_cr0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$6733 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$6734 1'0 - assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$6738 1'0 - assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$6737 1'0 - assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$6735 1'0 - assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$6736 1'0 - case - assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$6733 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$6722 - assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$6734 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$6723 - assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$6735 $1\alu_mul0_mul_op__oe__oe$next[0:0]$6728 - assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$6736 $1\alu_mul0_mul_op__oe__ok$next[0:0]$6729 - assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$6737 $1\alu_mul0_mul_op__rc__ok$next[0:0]$6730 - assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$6738 $1\alu_mul0_mul_op__rc__rc$next[0:0]$6731 - end - sync always - update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[11:0]$6709 - update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$6710 - update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$6711 - update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$6712 - update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$6713 - update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$6714 - update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$6715 - update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$6716 - update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$6717 - update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$6718 - update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$6719 - update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$6720 - end - attribute \src "issuer_ls180.v:136103.3-136124.6" - process $proc$issuer_ls180.v:136103$6739 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r0__o$next[63:0]$6740 $2\data_r0__o$next[63:0]$6744 - assign { } { } - assign $0\data_r0__o_ok$next[0:0]$6741 $3\data_r0__o_ok$next[0:0]$6746 - attribute \src "issuer_ls180.v:136104.5-136104.29" - switch \initial - attribute \src "issuer_ls180.v:136104.9-136104.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$6743 $1\data_r0__o$next[63:0]$6742 } { \o_ok \alu_mul0_o } - case - assign $1\data_r0__o$next[63:0]$6742 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$6743 \data_r0__o_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$6745 $2\data_r0__o$next[63:0]$6744 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r0__o$next[63:0]$6744 $1\data_r0__o$next[63:0]$6742 - assign $2\data_r0__o_ok$next[0:0]$6745 $1\data_r0__o_ok$next[0:0]$6743 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r0__o_ok$next[0:0]$6746 1'0 - case - assign $3\data_r0__o_ok$next[0:0]$6746 $2\data_r0__o_ok$next[0:0]$6745 - end - sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$6740 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6741 - end - attribute \src "issuer_ls180.v:136125.3-136146.6" - process $proc$issuer_ls180.v:136125$6747 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r1__cr_a$next[3:0]$6748 $2\data_r1__cr_a$next[3:0]$6752 - assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$6749 $3\data_r1__cr_a_ok$next[0:0]$6754 - attribute \src "issuer_ls180.v:136126.5-136126.29" - switch \initial - attribute \src "issuer_ls180.v:136126.9-136126.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$6751 $1\data_r1__cr_a$next[3:0]$6750 } { \cr_a_ok \alu_mul0_cr_a } - case - assign $1\data_r1__cr_a$next[3:0]$6750 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$6751 \data_r1__cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$6753 $2\data_r1__cr_a$next[3:0]$6752 } 5'00000 - case - assign $2\data_r1__cr_a$next[3:0]$6752 $1\data_r1__cr_a$next[3:0]$6750 - assign $2\data_r1__cr_a_ok$next[0:0]$6753 $1\data_r1__cr_a_ok$next[0:0]$6751 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$6754 1'0 - case - assign $3\data_r1__cr_a_ok$next[0:0]$6754 $2\data_r1__cr_a_ok$next[0:0]$6753 - end - sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6748 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6749 - end - attribute \src "issuer_ls180.v:136147.3-136168.6" - process $proc$issuer_ls180.v:136147$6755 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r2__xer_ov$next[1:0]$6756 $2\data_r2__xer_ov$next[1:0]$6760 - assign { } { } - assign $0\data_r2__xer_ov_ok$next[0:0]$6757 $3\data_r2__xer_ov_ok$next[0:0]$6762 - attribute \src "issuer_ls180.v:136148.5-136148.29" - switch \initial - attribute \src "issuer_ls180.v:136148.9-136148.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r2__xer_ov_ok$next[0:0]$6759 $1\data_r2__xer_ov$next[1:0]$6758 } { \xer_ov_ok \alu_mul0_xer_ov } - case - assign $1\data_r2__xer_ov$next[1:0]$6758 \data_r2__xer_ov - assign $1\data_r2__xer_ov_ok$next[0:0]$6759 \data_r2__xer_ov_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r2__xer_ov_ok$next[0:0]$6761 $2\data_r2__xer_ov$next[1:0]$6760 } 3'000 - case - assign $2\data_r2__xer_ov$next[1:0]$6760 $1\data_r2__xer_ov$next[1:0]$6758 - assign $2\data_r2__xer_ov_ok$next[0:0]$6761 $1\data_r2__xer_ov_ok$next[0:0]$6759 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r2__xer_ov_ok$next[0:0]$6762 1'0 - case - assign $3\data_r2__xer_ov_ok$next[0:0]$6762 $2\data_r2__xer_ov_ok$next[0:0]$6761 - end - sync always - update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$6756 - update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$6757 - end - attribute \src "issuer_ls180.v:136169.3-136190.6" - process $proc$issuer_ls180.v:136169$6763 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r3__xer_so$next[0:0]$6764 $2\data_r3__xer_so$next[0:0]$6768 - assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$6765 $3\data_r3__xer_so_ok$next[0:0]$6770 - attribute \src "issuer_ls180.v:136170.5-136170.29" - switch \initial - attribute \src "issuer_ls180.v:136170.9-136170.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$6767 $1\data_r3__xer_so$next[0:0]$6766 } { \xer_so_ok \alu_mul0_xer_so } - case - assign $1\data_r3__xer_so$next[0:0]$6766 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$6767 \data_r3__xer_so_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$6769 $2\data_r3__xer_so$next[0:0]$6768 } 2'00 - case - assign $2\data_r3__xer_so$next[0:0]$6768 $1\data_r3__xer_so$next[0:0]$6766 - assign $2\data_r3__xer_so_ok$next[0:0]$6769 $1\data_r3__xer_so_ok$next[0:0]$6767 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$6770 1'0 - case - assign $3\data_r3__xer_so_ok$next[0:0]$6770 $2\data_r3__xer_so_ok$next[0:0]$6769 - end - sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$6764 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$6765 - end - attribute \src "issuer_ls180.v:136191.3-136200.6" - process $proc$issuer_ls180.v:136191$6771 - assign { } { } - assign { } { } - assign $0\src_r0$next[63:0]$6772 $1\src_r0$next[63:0]$6773 - attribute \src "issuer_ls180.v:136192.5-136192.29" - switch \initial - attribute \src "issuer_ls180.v:136192.9-136192.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r0$next[63:0]$6773 \src1_i - case - assign $1\src_r0$next[63:0]$6773 \src_r0 - end - sync always - update \src_r0$next $0\src_r0$next[63:0]$6772 - end - attribute \src "issuer_ls180.v:136201.3-136210.6" - process $proc$issuer_ls180.v:136201$6774 - assign { } { } - assign { } { } - assign $0\src_r1$next[63:0]$6775 $1\src_r1$next[63:0]$6776 - attribute \src "issuer_ls180.v:136202.5-136202.29" - switch \initial - attribute \src "issuer_ls180.v:136202.9-136202.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r1$next[63:0]$6776 \src_or_imm - case - assign $1\src_r1$next[63:0]$6776 \src_r1 - end - sync always - update \src_r1$next $0\src_r1$next[63:0]$6775 - end - attribute \src "issuer_ls180.v:136211.3-136220.6" - process $proc$issuer_ls180.v:136211$6777 - assign { } { } - assign { } { } - assign $0\src_r2$next[0:0]$6778 $1\src_r2$next[0:0]$6779 - attribute \src "issuer_ls180.v:136212.5-136212.29" - switch \initial - attribute \src "issuer_ls180.v:136212.9-136212.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r2$next[0:0]$6779 \src3_i - case - assign $1\src_r2$next[0:0]$6779 \src_r2 - end - sync always - update \src_r2$next $0\src_r2$next[0:0]$6778 - end - attribute \src "issuer_ls180.v:136221.3-136229.6" - process $proc$issuer_ls180.v:136221$6780 - assign { } { } - assign { } { } - assign $0\alui_l_r_alui$next[0:0]$6781 $1\alui_l_r_alui$next[0:0]$6782 - attribute \src "issuer_ls180.v:136222.5-136222.29" - switch \initial - attribute \src "issuer_ls180.v:136222.9-136222.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alui_l_r_alui$next[0:0]$6782 1'1 - case - assign $1\alui_l_r_alui$next[0:0]$6782 \$88 - end - sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6781 - end - attribute \src "issuer_ls180.v:136230.3-136238.6" - process $proc$issuer_ls180.v:136230$6783 - assign { } { } - assign { } { } - assign $0\alu_l_r_alu$next[0:0]$6784 $1\alu_l_r_alu$next[0:0]$6785 - attribute \src "issuer_ls180.v:136231.5-136231.29" - switch \initial - attribute \src "issuer_ls180.v:136231.9-136231.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alu_l_r_alu$next[0:0]$6785 1'1 - case - assign $1\alu_l_r_alu$next[0:0]$6785 \$90 - end - sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6784 - end - attribute \src "issuer_ls180.v:136239.3-136248.6" - process $proc$issuer_ls180.v:136239$6786 - assign { } { } - assign { } { } - assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "issuer_ls180.v:136240.5-136240.29" - switch \initial - attribute \src "issuer_ls180.v:136240.9-136240.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$114 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest1_o[63:0] \data_r0__o - case - assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest1_o $0\dest1_o[63:0] - end - attribute \src "issuer_ls180.v:136249.3-136258.6" - process $proc$issuer_ls180.v:136249$6787 - assign { } { } - assign { } { } - assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "issuer_ls180.v:136250.5-136250.29" - switch \initial - attribute \src "issuer_ls180.v:136250.9-136250.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$116 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest2_o[3:0] \data_r1__cr_a - case - assign $1\dest2_o[3:0] 4'0000 - end - sync always - update \dest2_o $0\dest2_o[3:0] - end - attribute \src "issuer_ls180.v:136259.3-136268.6" - process $proc$issuer_ls180.v:136259$6788 - assign { } { } - assign { } { } - assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "issuer_ls180.v:136260.5-136260.29" - switch \initial - attribute \src "issuer_ls180.v:136260.9-136260.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$118 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest3_o[1:0] \data_r2__xer_ov - case - assign $1\dest3_o[1:0] 2'00 - end - sync always - update \dest3_o $0\dest3_o[1:0] - end - attribute \src "issuer_ls180.v:136269.3-136278.6" - process $proc$issuer_ls180.v:136269$6789 - assign { } { } - assign { } { } - assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "issuer_ls180.v:136270.5-136270.29" - switch \initial - attribute \src "issuer_ls180.v:136270.9-136270.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$120 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest4_o[0:0] \data_r3__xer_so - case - assign $1\dest4_o[0:0] 1'0 - end - sync always - update \dest4_o $0\dest4_o[0:0] - end - attribute \src "issuer_ls180.v:136279.3-136287.6" - process $proc$issuer_ls180.v:136279$6790 - assign { } { } - assign { } { } - assign $0\prev_wr_go$next[3:0]$6791 $1\prev_wr_go$next[3:0]$6792 - attribute \src "issuer_ls180.v:136280.5-136280.29" - switch \initial - attribute \src "issuer_ls180.v:136280.9-136280.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\prev_wr_go$next[3:0]$6792 4'0000 - case - assign $1\prev_wr_go$next[3:0]$6792 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[3:0]$6791 - end - connect \$100 $and$issuer_ls180.v:135755$6579_Y - connect \$102 $and$issuer_ls180.v:135756$6580_Y - connect \$104 $and$issuer_ls180.v:135757$6581_Y - connect \$106 $and$issuer_ls180.v:135758$6582_Y - connect \$108 $and$issuer_ls180.v:135759$6583_Y - connect \$10 $and$issuer_ls180.v:135760$6584_Y - connect \$110 $and$issuer_ls180.v:135761$6585_Y - connect \$112 $and$issuer_ls180.v:135762$6586_Y - connect \$114 $and$issuer_ls180.v:135763$6587_Y - connect \$116 $and$issuer_ls180.v:135764$6588_Y - connect \$118 $and$issuer_ls180.v:135765$6589_Y - connect \$120 $and$issuer_ls180.v:135766$6590_Y - connect \$12 $not$issuer_ls180.v:135767$6591_Y - connect \$14 $and$issuer_ls180.v:135768$6592_Y - connect \$16 $not$issuer_ls180.v:135769$6593_Y - connect \$18 $and$issuer_ls180.v:135770$6594_Y - connect \$20 $and$issuer_ls180.v:135771$6595_Y - connect \$24 $not$issuer_ls180.v:135772$6596_Y - connect \$26 $and$issuer_ls180.v:135773$6597_Y - connect \$23 $reduce_or$issuer_ls180.v:135774$6598_Y - connect \$22 $not$issuer_ls180.v:135775$6599_Y - connect \$2 $and$issuer_ls180.v:135776$6600_Y - connect \$30 $and$issuer_ls180.v:135777$6601_Y - connect \$32 $reduce_or$issuer_ls180.v:135778$6602_Y - connect \$34 $reduce_or$issuer_ls180.v:135779$6603_Y - connect \$36 $or$issuer_ls180.v:135780$6604_Y - connect \$38 $not$issuer_ls180.v:135781$6605_Y - connect \$40 $and$issuer_ls180.v:135782$6606_Y - connect \$42 $and$issuer_ls180.v:135783$6607_Y - connect \$44 $eq$issuer_ls180.v:135784$6608_Y - connect \$46 $and$issuer_ls180.v:135785$6609_Y - connect \$48 $eq$issuer_ls180.v:135786$6610_Y - connect \$50 $and$issuer_ls180.v:135787$6611_Y - connect \$52 $and$issuer_ls180.v:135788$6612_Y - connect \$54 $and$issuer_ls180.v:135789$6613_Y - connect \$56 $or$issuer_ls180.v:135790$6614_Y - connect \$58 $or$issuer_ls180.v:135791$6615_Y - connect \$5 $not$issuer_ls180.v:135792$6616_Y - connect \$60 $or$issuer_ls180.v:135793$6617_Y - connect \$62 $or$issuer_ls180.v:135794$6618_Y - connect \$64 $and$issuer_ls180.v:135795$6619_Y - connect \$66 $and$issuer_ls180.v:135796$6620_Y - connect \$68 $or$issuer_ls180.v:135797$6621_Y - connect \$70 $and$issuer_ls180.v:135798$6622_Y - connect \$72 $and$issuer_ls180.v:135799$6623_Y - connect \$74 $and$issuer_ls180.v:135800$6624_Y - connect \$76 $and$issuer_ls180.v:135801$6625_Y - connect \$78 $ternary$issuer_ls180.v:135802$6626_Y - connect \$7 $or$issuer_ls180.v:135803$6627_Y - connect \$80 $ternary$issuer_ls180.v:135804$6628_Y - connect \$82 $ternary$issuer_ls180.v:135805$6629_Y - connect \$84 $ternary$issuer_ls180.v:135806$6630_Y - connect \$86 $ternary$issuer_ls180.v:135807$6631_Y - connect \$88 $and$issuer_ls180.v:135808$6632_Y - connect \$4 $reduce_and$issuer_ls180.v:135809$6633_Y - connect \$90 $and$issuer_ls180.v:135810$6634_Y - connect \$92 $and$issuer_ls180.v:135811$6635_Y - connect \$94 $not$issuer_ls180.v:135812$6636_Y - connect \$96 $and$issuer_ls180.v:135813$6637_Y - connect \$98 $not$issuer_ls180.v:135814$6638_Y - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 - connect \cu_wr__rel_o \$112 - connect \cu_rd__rel_o \$100 - connect \cu_busy_o \opc_l_q_opc - connect \alu_l_s_alu \all_rd_pulse - connect \alu_mul0_n_ready_i \alu_l_q_alu - connect \alui_l_s_alui \all_rd_pulse - connect \alu_mul0_p_valid_i \alui_l_q_alui - connect \alu_mul0_xer_so$1 \$86 - connect \alu_mul0_rb \$84 - connect \alu_mul0_ra \$82 - connect \src_or_imm \$80 - connect \src_sel \$78 - connect \cu_wrmask_o { \$76 \$74 \$72 \$70 } - connect \reset_r \$62 - connect \reset_w \$60 - connect \rst_r \$58 - connect \reset \$56 - connect \wr_any \$36 - connect \cu_done_o \$30 - connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse } - connect \alu_pulse \alu_done_rise - connect \alu_done_rise \$18 - connect \alu_done_dly$next \alu_done - connect \alu_done \alu_mul0_n_valid_o - connect \all_rd_pulse \all_rd_rise - connect \all_rd_rise \$14 - connect \all_rd_dly$next \all_rd - connect \all_rd \$10 -end -attribute \src "issuer_ls180.v:136322.1-136649.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.mul1" -attribute \generator "nMigen" -module \mul1 - attribute \src "issuer_ls180.v:136616.18-136616.116" - wire $and$issuer_ls180.v:136616$6833_Y - attribute \src "issuer_ls180.v:136618.18-136618.116" - wire $and$issuer_ls180.v:136618$6835_Y - attribute \src "issuer_ls180.v:136619.18-136619.117" - wire $and$issuer_ls180.v:136619$6836_Y - attribute \src "issuer_ls180.v:136620.18-136620.117" - wire $and$issuer_ls180.v:136620$6837_Y - attribute \src "issuer_ls180.v:136623.18-136623.95" - wire width 65 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\enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \mul_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute 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"OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 17 \mul_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \mul_op__is_32bit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \mul_op__is_signed$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 23 \mul_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 24 \mul_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 22 \mul_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 21 \mul_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 25 \mul_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 34 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 16 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire output 32 \neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire output 33 \neg_res32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 13 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 29 \ra$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 14 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 30 \rb$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:33" - wire \sign32_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:34" - wire \sign32_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:31" - wire \sign_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:32" - wire \sign_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 15 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 31 \xer_so$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $and $and$issuer_ls180.v:136616$6833 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$17 - connect \B \mul_op__is_signed - connect \Y $and$issuer_ls180.v:136616$6833_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $and 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attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute 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wire output 24 \mul_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 23 \mul_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \mul_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 35 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 18 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire input 16 \neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire output 33 \neg_res$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire input 17 \neg_res32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire output 34 \neg_res32$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 output 31 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 13 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 14 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 15 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 32 \xer_so$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $pos $extend$issuer_ls180.v:136903$6853 - parameter \A_SIGNED 0 - parameter \A_WIDTH 128 - parameter \Y_WIDTH 129 - connect \A \$18 - connect \Y $extend$issuer_ls180.v:136903$6853_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $mul $mul$issuer_ls180.v:136902$6852 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 128 - connect \A \ra - connect \B \rb - connect \Y $mul$issuer_ls180.v:136902$6852_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $pos $pos$issuer_ls180.v:136903$6854 - parameter \A_SIGNED 0 - parameter \A_WIDTH 129 - parameter \Y_WIDTH 129 - connect \A $extend$issuer_ls180.v:136903$6853_Y - connect \Y $pos$issuer_ls180.v:136903$6854_Y - end - connect \$18 $mul$issuer_ls180.v:136902$6852_Y - connect \$17 $pos$issuer_ls180.v:136903$6854_Y - connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } - connect \muxid$1 \muxid - connect \xer_so$14 \xer_so - connect \neg_res32$16 \neg_res32 - connect \neg_res$15 \neg_res - connect \o \$17 -end -attribute \src "issuer_ls180.v:136914.1-137293.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.mul3" -attribute \generator "nMigen" -module \mul3 - attribute \src "issuer_ls180.v:136915.7-136915.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:137246.3-137264.6" - wire $0\mul_ov[0:0] - attribute \src "issuer_ls180.v:137208.3-137226.6" - wire width 64 $0\o$14[63:0]$6871 - attribute \src "issuer_ls180.v:137227.3-137245.6" - wire $0\o_ok[0:0] - attribute \src "issuer_ls180.v:137265.3-137275.6" - wire width 2 $0\xer_ov[1:0] - attribute \src "issuer_ls180.v:137276.3-137286.6" - wire $0\xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:137246.3-137264.6" - wire $1\mul_ov[0:0] - attribute \src "issuer_ls180.v:137208.3-137226.6" - wire width 64 $1\o$14[63:0]$6872 - attribute \src "issuer_ls180.v:137227.3-137245.6" - wire $1\o_ok[0:0] - attribute \src "issuer_ls180.v:137265.3-137275.6" - wire width 2 $1\xer_ov[1:0] - attribute \src "issuer_ls180.v:137276.3-137286.6" - wire $1\xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:137246.3-137264.6" - wire $2\mul_ov[0:0] - attribute \src "issuer_ls180.v:137202.18-137202.104" - wire $and$issuer_ls180.v:137202$6863_Y - attribute \src "issuer_ls180.v:137206.18-137206.104" - wire $and$issuer_ls180.v:137206$6867_Y - attribute \src "issuer_ls180.v:137196.18-137196.95" - wire width 130 $extend$issuer_ls180.v:137196$6855_Y - attribute \src "issuer_ls180.v:137197.18-137197.90" - wire width 130 $extend$issuer_ls180.v:137197$6857_Y - attribute \src "issuer_ls180.v:137207.18-137207.95" - wire width 2 $extend$issuer_ls180.v:137207$6868_Y - attribute \src "issuer_ls180.v:137196.18-137196.95" - wire width 130 $neg$issuer_ls180.v:137196$6856_Y - attribute \src "issuer_ls180.v:137201.18-137201.98" - wire $not$issuer_ls180.v:137201$6862_Y - attribute \src "issuer_ls180.v:137205.18-137205.98" - wire $not$issuer_ls180.v:137205$6866_Y - attribute \src "issuer_ls180.v:137197.18-137197.90" - wire width 130 $pos$issuer_ls180.v:137197$6858_Y - attribute \src "issuer_ls180.v:137207.18-137207.95" - wire width 2 $pos$issuer_ls180.v:137207$6869_Y - attribute \src "issuer_ls180.v:137200.18-137200.106" - wire $reduce_and$issuer_ls180.v:137200$6861_Y - attribute \src "issuer_ls180.v:137204.18-137204.107" - wire $reduce_and$issuer_ls180.v:137204$6865_Y - attribute \src "issuer_ls180.v:137199.18-137199.106" - wire $reduce_or$issuer_ls180.v:137199$6860_Y - attribute \src "issuer_ls180.v:137203.18-137203.107" - wire $reduce_or$issuer_ls180.v:137203$6864_Y - attribute \src "issuer_ls180.v:137198.18-137198.114" - wire width 130 $ternary$issuer_ls180.v:137198$6859_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - wire width 130 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - wire width 130 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 130 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - wire width 130 \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - wire \$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - wire \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \$39 - attribute \src "issuer_ls180.v:136915.7-136915.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" - wire \is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:40" - wire width 129 \mul_o - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \mul_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 18 \mul_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 19 \mul_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \mul_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 12 \mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 28 \mul_op__insn$13 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \mul_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 17 \mul_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \mul_op__is_32bit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \mul_op__is_signed$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 23 \mul_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 24 \mul_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 22 \mul_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 21 \mul_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 25 \mul_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:60" - wire \mul_ov - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 35 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 16 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire input 15 \neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 input 13 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 29 \o$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 30 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 31 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 32 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 14 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 33 \xer_so$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 34 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $and $and$issuer_ls180.v:137202$6863 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$23 - connect \B \$25 - connect \Y $and$issuer_ls180.v:137202$6863_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $and $and$issuer_ls180.v:137206$6867 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$31 - connect \B \$33 - connect \Y $and$issuer_ls180.v:137206$6867_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $pos $extend$issuer_ls180.v:137196$6855 - parameter \A_SIGNED 0 - parameter \A_WIDTH 129 - parameter \Y_WIDTH 130 - connect \A \o - connect \Y $extend$issuer_ls180.v:137196$6855_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$issuer_ls180.v:137197$6857 - parameter \A_SIGNED 0 - parameter \A_WIDTH 129 - parameter \Y_WIDTH 130 - connect \A \o - connect \Y $extend$issuer_ls180.v:137197$6857_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$issuer_ls180.v:137207$6868 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \xer_so - connect \Y $extend$issuer_ls180.v:137207$6868_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $neg $neg$issuer_ls180.v:137196$6856 - parameter \A_SIGNED 0 - parameter \A_WIDTH 130 - parameter \Y_WIDTH 130 - connect \A $extend$issuer_ls180.v:137196$6855_Y - connect \Y $neg$issuer_ls180.v:137196$6856_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $not $not$issuer_ls180.v:137201$6862 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$26 - connect \Y $not$issuer_ls180.v:137201$6862_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $not $not$issuer_ls180.v:137205$6866 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$34 - connect \Y $not$issuer_ls180.v:137205$6866_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$issuer_ls180.v:137197$6858 - parameter \A_SIGNED 0 - parameter \A_WIDTH 130 - parameter \Y_WIDTH 130 - connect \A $extend$issuer_ls180.v:137197$6857_Y - connect \Y $pos$issuer_ls180.v:137197$6858_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$issuer_ls180.v:137207$6869 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A $extend$issuer_ls180.v:137207$6868_Y - connect \Y $pos$issuer_ls180.v:137207$6869_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_and $reduce_and$issuer_ls180.v:137200$6861 - parameter \A_SIGNED 0 - parameter \A_WIDTH 33 - parameter \Y_WIDTH 1 - connect \A \mul_o [63:31] - connect \Y $reduce_and$issuer_ls180.v:137200$6861_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_and $reduce_and$issuer_ls180.v:137204$6865 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 1 - connect \A \mul_o [127:63] - connect \Y $reduce_and$issuer_ls180.v:137204$6865_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_or $reduce_or$issuer_ls180.v:137199$6860 - parameter \A_SIGNED 0 - parameter \A_WIDTH 33 - parameter \Y_WIDTH 1 - connect \A \mul_o [63:31] - connect \Y $reduce_or$issuer_ls180.v:137199$6860_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_or $reduce_or$issuer_ls180.v:137203$6864 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 1 - connect \A \mul_o [127:63] - connect \Y $reduce_or$issuer_ls180.v:137203$6864_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $mux $ternary$issuer_ls180.v:137198$6859 - parameter \WIDTH 130 - connect \A \$19 - connect \B \$17 - connect \S \neg_res - connect \Y $ternary$issuer_ls180.v:137198$6859_Y - end - attribute \src "issuer_ls180.v:136915.7-136915.20" - process $proc$issuer_ls180.v:136915$6877 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:137208.3-137226.6" - process $proc$issuer_ls180.v:137208$6870 - assign { } { } - assign { } { } - assign $0\o$14[63:0]$6871 $1\o$14[63:0]$6872 - attribute \src "issuer_ls180.v:137209.5-137209.29" - switch \initial - attribute \src "issuer_ls180.v:137209.9-137209.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" - switch \mul_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110100 - assign { } { } - assign $1\o$14[63:0]$6872 { \mul_o [63:32] \mul_o [63:32] } - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110011 - assign { } { } - assign $1\o$14[63:0]$6872 \mul_o [127:64] - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110010 - assign { } { } - assign $1\o$14[63:0]$6872 \mul_o [63:0] - case - assign $1\o$14[63:0]$6872 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \o$14 $0\o$14[63:0]$6871 - end - attribute \src "issuer_ls180.v:137227.3-137245.6" - process $proc$issuer_ls180.v:137227$6873 - assign { } { } - assign { } { } - assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "issuer_ls180.v:137228.5-137228.29" - switch \initial - attribute \src "issuer_ls180.v:137228.9-137228.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" - switch \mul_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110100 - assign { } { } - assign $1\o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110011 - assign { } { } - assign $1\o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110010 - assign { } { } - assign $1\o_ok[0:0] 1'1 - case - assign $1\o_ok[0:0] 1'0 - end - sync always - update \o_ok $0\o_ok[0:0] - end - attribute \src "issuer_ls180.v:137246.3-137264.6" - process $proc$issuer_ls180.v:137246$6874 - assign { } { } - assign { } { } - assign $0\mul_ov[0:0] $1\mul_ov[0:0] - attribute \src "issuer_ls180.v:137247.5-137247.29" - switch \initial - attribute \src "issuer_ls180.v:137247.9-137247.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" - switch \mul_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110010 - assign { } { } - assign $1\mul_ov[0:0] $2\mul_ov[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:61" - switch \is_32bit - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\mul_ov[0:0] \$29 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\mul_ov[0:0] \$37 - end - case - assign $1\mul_ov[0:0] 1'0 - end - sync always - update \mul_ov $0\mul_ov[0:0] - end - attribute \src "issuer_ls180.v:137265.3-137275.6" - process $proc$issuer_ls180.v:137265$6875 - assign { } { } - assign { } { } - assign $0\xer_ov[1:0] $1\xer_ov[1:0] - attribute \src "issuer_ls180.v:137266.5-137266.29" - switch \initial - attribute \src "issuer_ls180.v:137266.9-137266.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" - switch \mul_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110010 - assign { } { } - assign $1\xer_ov[1:0] { \mul_ov \mul_ov } - case - assign $1\xer_ov[1:0] 2'00 - end - sync always - update \xer_ov $0\xer_ov[1:0] - end - attribute \src "issuer_ls180.v:137276.3-137286.6" - process $proc$issuer_ls180.v:137276$6876 - assign { } { } - assign { } { } - assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:137277.5-137277.29" - switch \initial - attribute \src "issuer_ls180.v:137277.9-137277.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" - switch \mul_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110010 - assign { } { } - assign $1\xer_ov_ok[0:0] 1'1 - case - assign $1\xer_ov_ok[0:0] 1'0 - end - sync always - update \xer_ov_ok $0\xer_ov_ok[0:0] - end - connect \$17 $neg$issuer_ls180.v:137196$6856_Y - connect \$19 $pos$issuer_ls180.v:137197$6858_Y - connect \$21 $ternary$issuer_ls180.v:137198$6859_Y - connect \$23 $reduce_or$issuer_ls180.v:137199$6860_Y - connect \$26 $reduce_and$issuer_ls180.v:137200$6861_Y - connect \$25 $not$issuer_ls180.v:137201$6862_Y - connect \$29 $and$issuer_ls180.v:137202$6863_Y - connect \$31 $reduce_or$issuer_ls180.v:137203$6864_Y - connect \$34 $reduce_and$issuer_ls180.v:137204$6865_Y - connect \$33 $not$issuer_ls180.v:137205$6866_Y - connect \$37 $and$issuer_ls180.v:137206$6867_Y - connect \$39 $pos$issuer_ls180.v:137207$6869_Y - connect \$16 \$21 - connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } - connect \muxid$1 \muxid - connect { \xer_so_ok \xer_so$15 } \$39 - connect \mul_o \$21 [128:0] - connect \is_32bit \mul_op__is_32bit -end -attribute \src "issuer_ls180.v:137297.1-138493.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1" -attribute \generator "nMigen" -module \mul_pipe1 - attribute \src "issuer_ls180.v:137298.7-137298.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire width 12 $0\mul_op__fn_unit$next[11:0]$6906 - attribute \src "issuer_ls180.v:138235.3-138236.47" - wire width 12 $0\mul_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire width 64 $0\mul_op__imm_data__data$next[63:0]$6907 - attribute \src "issuer_ls180.v:138237.3-138238.61" - wire width 64 $0\mul_op__imm_data__data[63:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire $0\mul_op__imm_data__ok$next[0:0]$6908 - attribute \src "issuer_ls180.v:138239.3-138240.57" - wire $0\mul_op__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire width 32 $0\mul_op__insn$next[31:0]$6909 - attribute \src "issuer_ls180.v:138255.3-138256.41" - wire width 32 $0\mul_op__insn[31:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire width 7 $0\mul_op__insn_type$next[6:0]$6910 - attribute \src "issuer_ls180.v:138233.3-138234.51" - wire width 7 $0\mul_op__insn_type[6:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire $0\mul_op__is_32bit$next[0:0]$6911 - attribute \src "issuer_ls180.v:138251.3-138252.49" - wire $0\mul_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire $0\mul_op__is_signed$next[0:0]$6912 - attribute \src "issuer_ls180.v:138253.3-138254.51" - wire $0\mul_op__is_signed[0:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire $0\mul_op__oe__oe$next[0:0]$6913 - attribute \src "issuer_ls180.v:138245.3-138246.45" - wire $0\mul_op__oe__oe[0:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire $0\mul_op__oe__ok$next[0:0]$6914 - attribute \src "issuer_ls180.v:138247.3-138248.45" - wire $0\mul_op__oe__ok[0:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire $0\mul_op__rc__ok$next[0:0]$6915 - attribute \src "issuer_ls180.v:138243.3-138244.45" - wire $0\mul_op__rc__ok[0:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire $0\mul_op__rc__rc$next[0:0]$6916 - attribute \src "issuer_ls180.v:138241.3-138242.45" - wire $0\mul_op__rc__rc[0:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire $0\mul_op__write_cr0$next[0:0]$6917 - attribute \src "issuer_ls180.v:138249.3-138250.51" - wire $0\mul_op__write_cr0[0:0] - attribute \src "issuer_ls180.v:138357.3-138369.6" - wire width 2 $0\muxid$next[1:0]$6903 - attribute \src "issuer_ls180.v:138257.3-138258.27" - wire width 2 $0\muxid[1:0] - attribute \src "issuer_ls180.v:138445.3-138457.6" - wire $0\neg_res$next[0:0]$6946 - attribute \src "issuer_ls180.v:138458.3-138470.6" - wire $0\neg_res32$next[0:0]$6949 - attribute \src "issuer_ls180.v:138223.3-138224.35" - wire $0\neg_res32[0:0] - attribute \src "issuer_ls180.v:138225.3-138226.31" - wire $0\neg_res[0:0] - attribute \src "issuer_ls180.v:138339.3-138356.6" - wire $0\r_busy$next[0:0]$6899 - attribute \src "issuer_ls180.v:138259.3-138260.29" - wire $0\r_busy[0:0] - attribute \src "issuer_ls180.v:138406.3-138418.6" - wire width 64 $0\ra$next[63:0]$6937 - attribute \src "issuer_ls180.v:138231.3-138232.21" - wire width 64 $0\ra[63:0] - attribute \src "issuer_ls180.v:138419.3-138431.6" - wire width 64 $0\rb$next[63:0]$6940 - attribute \src "issuer_ls180.v:138229.3-138230.21" - wire width 64 $0\rb[63:0] - attribute \src "issuer_ls180.v:138432.3-138444.6" - wire $0\xer_so$next[0:0]$6943 - attribute \src "issuer_ls180.v:138227.3-138228.29" - wire $0\xer_so[0:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire width 12 $1\mul_op__fn_unit$next[11:0]$6918 - attribute \src "issuer_ls180.v:137800.14-137800.39" - wire width 12 $1\mul_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire width 64 $1\mul_op__imm_data__data$next[63:0]$6919 - attribute \src "issuer_ls180.v:137835.14-137835.59" - wire width 64 $1\mul_op__imm_data__data[63:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire $1\mul_op__imm_data__ok$next[0:0]$6920 - attribute \src "issuer_ls180.v:137844.7-137844.34" - wire $1\mul_op__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire width 32 $1\mul_op__insn$next[31:0]$6921 - attribute \src "issuer_ls180.v:137853.14-137853.34" - wire width 32 $1\mul_op__insn[31:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire width 7 $1\mul_op__insn_type$next[6:0]$6922 - attribute \src "issuer_ls180.v:137936.13-137936.38" - wire width 7 $1\mul_op__insn_type[6:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire $1\mul_op__is_32bit$next[0:0]$6923 - attribute \src "issuer_ls180.v:138093.7-138093.30" - wire $1\mul_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire $1\mul_op__is_signed$next[0:0]$6924 - attribute \src "issuer_ls180.v:138102.7-138102.31" - wire $1\mul_op__is_signed[0:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire $1\mul_op__oe__oe$next[0:0]$6925 - attribute \src "issuer_ls180.v:138111.7-138111.28" - wire $1\mul_op__oe__oe[0:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire $1\mul_op__oe__ok$next[0:0]$6926 - attribute \src "issuer_ls180.v:138120.7-138120.28" - wire $1\mul_op__oe__ok[0:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire $1\mul_op__rc__ok$next[0:0]$6927 - attribute \src "issuer_ls180.v:138129.7-138129.28" - wire $1\mul_op__rc__ok[0:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire $1\mul_op__rc__rc$next[0:0]$6928 - attribute \src "issuer_ls180.v:138138.7-138138.28" - wire $1\mul_op__rc__rc[0:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire $1\mul_op__write_cr0$next[0:0]$6929 - attribute \src "issuer_ls180.v:138147.7-138147.31" - wire $1\mul_op__write_cr0[0:0] - attribute \src "issuer_ls180.v:138357.3-138369.6" - wire width 2 $1\muxid$next[1:0]$6904 - attribute \src "issuer_ls180.v:138156.13-138156.25" - wire width 2 $1\muxid[1:0] - attribute \src "issuer_ls180.v:138445.3-138457.6" - wire $1\neg_res$next[0:0]$6947 - attribute \src "issuer_ls180.v:138458.3-138470.6" - wire $1\neg_res32$next[0:0]$6950 - attribute \src "issuer_ls180.v:138178.7-138178.23" - wire $1\neg_res32[0:0] - attribute \src "issuer_ls180.v:138171.7-138171.21" - wire $1\neg_res[0:0] - attribute \src "issuer_ls180.v:138339.3-138356.6" - wire $1\r_busy$next[0:0]$6900 - attribute \src "issuer_ls180.v:138192.7-138192.20" - wire $1\r_busy[0:0] - attribute \src "issuer_ls180.v:138406.3-138418.6" - wire width 64 $1\ra$next[63:0]$6938 - attribute \src "issuer_ls180.v:138197.14-138197.39" - wire width 64 $1\ra[63:0] - attribute \src "issuer_ls180.v:138419.3-138431.6" - wire width 64 $1\rb$next[63:0]$6941 - attribute \src "issuer_ls180.v:138206.14-138206.39" - wire width 64 $1\rb[63:0] - attribute \src "issuer_ls180.v:138432.3-138444.6" - wire $1\xer_so$next[0:0]$6944 - attribute \src "issuer_ls180.v:138215.7-138215.20" - wire $1\xer_so[0:0] - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire width 64 $2\mul_op__imm_data__data$next[63:0]$6930 - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire $2\mul_op__imm_data__ok$next[0:0]$6931 - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire $2\mul_op__oe__oe$next[0:0]$6932 - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire $2\mul_op__oe__ok$next[0:0]$6933 - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire $2\mul_op__rc__ok$next[0:0]$6934 - attribute \src "issuer_ls180.v:138370.3-138405.6" - wire $2\mul_op__rc__rc$next[0:0]$6935 - attribute \src "issuer_ls180.v:138339.3-138356.6" - wire $2\r_busy$next[0:0]$6901 - attribute \src "issuer_ls180.v:138222.18-138222.118" - wire $and$issuer_ls180.v:138222$6878_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 40 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:137298.7-137298.15" - wire \initial - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_mul_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_mul_op__fn_unit$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_mul_op__imm_data__data$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__imm_data__ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_mul_op__insn$29 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_mul_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_mul_op__insn_type$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__is_32bit$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__is_signed$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__oe__oe$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__oe__ok$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__rc__ok$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__rc__rc$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__write_cr0$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so$32 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul1_mul_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul1_mul_op__fn_unit$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul1_mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul1_mul_op__imm_data__data$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul1_mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul1_mul_op__imm_data__ok$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul1_mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul1_mul_op__insn$45 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute 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attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute 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\enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 34 \mul_op__is_32bit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_32bit$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 35 \mul_op__is_signed$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_signed$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__oe$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 31 \mul_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__ok$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 32 \mul_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__ok$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 30 \mul_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__rc$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 29 \mul_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 33 \mul_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__write_cr0$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 24 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$52 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 3 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire output 20 \neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire \neg_res$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire \neg_res$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire output 21 \neg_res32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire \neg_res32$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire \neg_res32$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 23 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 22 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$49 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 17 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 37 \ra$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 18 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 38 \rb$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 19 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 39 \xer_so$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \xer_so$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \xer_so$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$issuer_ls180.v:138222$6878 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$49 - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:138222$6878_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:138261.14-138294.4" - cell \input$92 \input - connect \mul_op__fn_unit \input_mul_op__fn_unit - connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$19 - connect \mul_op__imm_data__data \input_mul_op__imm_data__data - connect \mul_op__imm_data__data$4 \input_mul_op__imm_data__data$20 - connect \mul_op__imm_data__ok \input_mul_op__imm_data__ok - connect \mul_op__imm_data__ok$5 \input_mul_op__imm_data__ok$21 - connect \mul_op__insn \input_mul_op__insn - connect \mul_op__insn$13 \input_mul_op__insn$29 - connect \mul_op__insn_type \input_mul_op__insn_type - connect \mul_op__insn_type$2 \input_mul_op__insn_type$18 - connect \mul_op__is_32bit \input_mul_op__is_32bit - connect \mul_op__is_32bit$11 \input_mul_op__is_32bit$27 - connect \mul_op__is_signed \input_mul_op__is_signed - connect \mul_op__is_signed$12 \input_mul_op__is_signed$28 - connect \mul_op__oe__oe \input_mul_op__oe__oe - connect \mul_op__oe__oe$8 \input_mul_op__oe__oe$24 - connect \mul_op__oe__ok \input_mul_op__oe__ok - connect \mul_op__oe__ok$9 \input_mul_op__oe__ok$25 - connect \mul_op__rc__ok \input_mul_op__rc__ok - connect \mul_op__rc__ok$7 \input_mul_op__rc__ok$23 - connect \mul_op__rc__rc \input_mul_op__rc__rc - connect \mul_op__rc__rc$6 \input_mul_op__rc__rc$22 - connect \mul_op__write_cr0 \input_mul_op__write_cr0 - connect \mul_op__write_cr0$10 \input_mul_op__write_cr0$26 - connect \muxid \input_muxid - connect \muxid$1 \input_muxid$17 - connect \ra \input_ra - connect \ra$14 \input_ra$30 - connect \rb \input_rb - connect \rb$15 \input_rb$31 - connect \xer_so \input_xer_so - connect \xer_so$16 \input_xer_so$32 - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:138295.8-138330.4" - cell \mul1 \mul1 - connect \mul_op__fn_unit \mul1_mul_op__fn_unit - connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$35 - connect \mul_op__imm_data__data \mul1_mul_op__imm_data__data - connect \mul_op__imm_data__data$4 \mul1_mul_op__imm_data__data$36 - connect \mul_op__imm_data__ok \mul1_mul_op__imm_data__ok - connect \mul_op__imm_data__ok$5 \mul1_mul_op__imm_data__ok$37 - connect \mul_op__insn \mul1_mul_op__insn - connect \mul_op__insn$13 \mul1_mul_op__insn$45 - connect \mul_op__insn_type \mul1_mul_op__insn_type - connect \mul_op__insn_type$2 \mul1_mul_op__insn_type$34 - connect \mul_op__is_32bit \mul1_mul_op__is_32bit - connect \mul_op__is_32bit$11 \mul1_mul_op__is_32bit$43 - connect \mul_op__is_signed \mul1_mul_op__is_signed - connect \mul_op__is_signed$12 \mul1_mul_op__is_signed$44 - connect \mul_op__oe__oe \mul1_mul_op__oe__oe - connect \mul_op__oe__oe$8 \mul1_mul_op__oe__oe$40 - connect \mul_op__oe__ok \mul1_mul_op__oe__ok - connect \mul_op__oe__ok$9 \mul1_mul_op__oe__ok$41 - connect \mul_op__rc__ok \mul1_mul_op__rc__ok - connect \mul_op__rc__ok$7 \mul1_mul_op__rc__ok$39 - connect \mul_op__rc__rc \mul1_mul_op__rc__rc - connect \mul_op__rc__rc$6 \mul1_mul_op__rc__rc$38 - connect \mul_op__write_cr0 \mul1_mul_op__write_cr0 - connect \mul_op__write_cr0$10 \mul1_mul_op__write_cr0$42 - connect \muxid \mul1_muxid - connect \muxid$1 \mul1_muxid$33 - connect \neg_res \mul1_neg_res - connect \neg_res32 \mul1_neg_res32 - connect \ra \mul1_ra - connect \ra$14 \mul1_ra$46 - connect \rb \mul1_rb - connect \rb$15 \mul1_rb$47 - connect \xer_so \mul1_xer_so - connect \xer_so$16 \mul1_xer_so$48 - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:138331.10-138334.4" - cell \n$91 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:138335.10-138338.4" - cell \p$90 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "issuer_ls180.v:137298.7-137298.20" - process $proc$issuer_ls180.v:137298$6951 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:137800.14-137800.39" - process $proc$issuer_ls180.v:137800$6952 - assign { } { } - assign $1\mul_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \mul_op__fn_unit $1\mul_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:137835.14-137835.59" - process $proc$issuer_ls180.v:137835$6953 - assign { } { } - assign $1\mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \mul_op__imm_data__data $1\mul_op__imm_data__data[63:0] - end - attribute \src "issuer_ls180.v:137844.7-137844.34" - process $proc$issuer_ls180.v:137844$6954 - assign { } { } - assign $1\mul_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \mul_op__imm_data__ok $1\mul_op__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:137853.14-137853.34" - process $proc$issuer_ls180.v:137853$6955 - assign { } { } - assign $1\mul_op__insn[31:0] 0 - sync always - sync init - update \mul_op__insn $1\mul_op__insn[31:0] - end - attribute \src "issuer_ls180.v:137936.13-137936.38" - process $proc$issuer_ls180.v:137936$6956 - assign { } { } - assign $1\mul_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \mul_op__insn_type $1\mul_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:138093.7-138093.30" - process $proc$issuer_ls180.v:138093$6957 - assign { } { } - assign $1\mul_op__is_32bit[0:0] 1'0 - sync always - sync init - update \mul_op__is_32bit $1\mul_op__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:138102.7-138102.31" - process $proc$issuer_ls180.v:138102$6958 - assign { } { } - assign $1\mul_op__is_signed[0:0] 1'0 - sync always - sync init - update \mul_op__is_signed $1\mul_op__is_signed[0:0] - end - attribute \src "issuer_ls180.v:138111.7-138111.28" - process $proc$issuer_ls180.v:138111$6959 - assign { } { } - assign $1\mul_op__oe__oe[0:0] 1'0 - sync always - sync init - update \mul_op__oe__oe $1\mul_op__oe__oe[0:0] - end - attribute \src "issuer_ls180.v:138120.7-138120.28" - process $proc$issuer_ls180.v:138120$6960 - assign { } { } - assign $1\mul_op__oe__ok[0:0] 1'0 - sync always - sync init - update \mul_op__oe__ok $1\mul_op__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:138129.7-138129.28" - process $proc$issuer_ls180.v:138129$6961 - assign { } { } - assign $1\mul_op__rc__ok[0:0] 1'0 - sync always - sync init - update \mul_op__rc__ok $1\mul_op__rc__ok[0:0] - end - attribute \src "issuer_ls180.v:138138.7-138138.28" - process $proc$issuer_ls180.v:138138$6962 - assign { } { } - assign $1\mul_op__rc__rc[0:0] 1'0 - sync always - sync init - update \mul_op__rc__rc $1\mul_op__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:138147.7-138147.31" - process $proc$issuer_ls180.v:138147$6963 - assign { } { } - assign $1\mul_op__write_cr0[0:0] 1'0 - sync always - sync init - update \mul_op__write_cr0 $1\mul_op__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:138156.13-138156.25" - process $proc$issuer_ls180.v:138156$6964 - assign { } { } - assign $1\muxid[1:0] 2'00 - sync always - sync init - update \muxid $1\muxid[1:0] - end - attribute \src "issuer_ls180.v:138171.7-138171.21" - process $proc$issuer_ls180.v:138171$6965 - assign { } { } - assign $1\neg_res[0:0] 1'0 - sync always - sync init - update \neg_res $1\neg_res[0:0] - end - attribute \src "issuer_ls180.v:138178.7-138178.23" - process $proc$issuer_ls180.v:138178$6966 - assign { } { } - assign $1\neg_res32[0:0] 1'0 - sync always - sync init - update \neg_res32 $1\neg_res32[0:0] - end - attribute \src "issuer_ls180.v:138192.7-138192.20" - process $proc$issuer_ls180.v:138192$6967 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "issuer_ls180.v:138197.14-138197.39" - process $proc$issuer_ls180.v:138197$6968 - assign { } { } - assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \ra $1\ra[63:0] - end - attribute \src "issuer_ls180.v:138206.14-138206.39" - process $proc$issuer_ls180.v:138206$6969 - assign { } { } - assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \rb $1\rb[63:0] - end - attribute \src "issuer_ls180.v:138215.7-138215.20" - process $proc$issuer_ls180.v:138215$6970 - assign { } { } - assign $1\xer_so[0:0] 1'0 - sync always - sync init - update \xer_so $1\xer_so[0:0] - end - attribute \src "issuer_ls180.v:138223.3-138224.35" - process $proc$issuer_ls180.v:138223$6879 - assign { } { } - assign $0\neg_res32[0:0] \neg_res32$next - sync posedge \coresync_clk - update \neg_res32 $0\neg_res32[0:0] - end - attribute \src "issuer_ls180.v:138225.3-138226.31" - process $proc$issuer_ls180.v:138225$6880 - assign { } { } - assign $0\neg_res[0:0] \neg_res$next - sync posedge \coresync_clk - update \neg_res $0\neg_res[0:0] - end - attribute \src "issuer_ls180.v:138227.3-138228.29" - process $proc$issuer_ls180.v:138227$6881 - assign { } { } - assign $0\xer_so[0:0] \xer_so$next - sync posedge \coresync_clk - update \xer_so $0\xer_so[0:0] - end - attribute \src "issuer_ls180.v:138229.3-138230.21" - process $proc$issuer_ls180.v:138229$6882 - assign { } { } - assign $0\rb[63:0] \rb$next - sync posedge \coresync_clk - update \rb $0\rb[63:0] - end - attribute \src "issuer_ls180.v:138231.3-138232.21" - process $proc$issuer_ls180.v:138231$6883 - assign { } { } - assign $0\ra[63:0] \ra$next - sync posedge \coresync_clk - update \ra $0\ra[63:0] - end - attribute \src "issuer_ls180.v:138233.3-138234.51" - process $proc$issuer_ls180.v:138233$6884 - assign { } { } - assign $0\mul_op__insn_type[6:0] \mul_op__insn_type$next - sync posedge \coresync_clk - update \mul_op__insn_type $0\mul_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:138235.3-138236.47" - process $proc$issuer_ls180.v:138235$6885 - assign { } { } - assign $0\mul_op__fn_unit[11:0] \mul_op__fn_unit$next - sync posedge \coresync_clk - update \mul_op__fn_unit $0\mul_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:138237.3-138238.61" - process $proc$issuer_ls180.v:138237$6886 - assign { } { } - assign $0\mul_op__imm_data__data[63:0] \mul_op__imm_data__data$next - sync posedge \coresync_clk - update \mul_op__imm_data__data $0\mul_op__imm_data__data[63:0] - end - attribute \src "issuer_ls180.v:138239.3-138240.57" - process $proc$issuer_ls180.v:138239$6887 - assign { } { } - assign $0\mul_op__imm_data__ok[0:0] \mul_op__imm_data__ok$next - sync posedge \coresync_clk - update \mul_op__imm_data__ok $0\mul_op__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:138241.3-138242.45" - process $proc$issuer_ls180.v:138241$6888 - assign { } { } - assign $0\mul_op__rc__rc[0:0] \mul_op__rc__rc$next - sync posedge \coresync_clk - update \mul_op__rc__rc $0\mul_op__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:138243.3-138244.45" - process $proc$issuer_ls180.v:138243$6889 - assign { } { } - assign $0\mul_op__rc__ok[0:0] \mul_op__rc__ok$next - sync posedge \coresync_clk - update \mul_op__rc__ok $0\mul_op__rc__ok[0:0] - end - attribute \src "issuer_ls180.v:138245.3-138246.45" - process $proc$issuer_ls180.v:138245$6890 - assign { } { } - assign $0\mul_op__oe__oe[0:0] \mul_op__oe__oe$next - sync posedge \coresync_clk - update \mul_op__oe__oe $0\mul_op__oe__oe[0:0] - end - attribute \src "issuer_ls180.v:138247.3-138248.45" - process $proc$issuer_ls180.v:138247$6891 - assign { } { } - assign $0\mul_op__oe__ok[0:0] \mul_op__oe__ok$next - sync posedge \coresync_clk - update \mul_op__oe__ok $0\mul_op__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:138249.3-138250.51" - process $proc$issuer_ls180.v:138249$6892 - assign { } { } - assign $0\mul_op__write_cr0[0:0] \mul_op__write_cr0$next - sync posedge \coresync_clk - update \mul_op__write_cr0 $0\mul_op__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:138251.3-138252.49" - process $proc$issuer_ls180.v:138251$6893 - assign { } { } - assign $0\mul_op__is_32bit[0:0] \mul_op__is_32bit$next - sync posedge \coresync_clk - update \mul_op__is_32bit $0\mul_op__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:138253.3-138254.51" - process $proc$issuer_ls180.v:138253$6894 - assign { } { } - assign $0\mul_op__is_signed[0:0] \mul_op__is_signed$next - sync posedge \coresync_clk - update \mul_op__is_signed $0\mul_op__is_signed[0:0] - end - attribute \src "issuer_ls180.v:138255.3-138256.41" - process $proc$issuer_ls180.v:138255$6895 - assign { } { } - assign $0\mul_op__insn[31:0] \mul_op__insn$next - sync posedge \coresync_clk - update \mul_op__insn $0\mul_op__insn[31:0] - end - attribute \src "issuer_ls180.v:138257.3-138258.27" - process $proc$issuer_ls180.v:138257$6896 - assign { } { } - assign $0\muxid[1:0] \muxid$next - sync posedge \coresync_clk - update \muxid $0\muxid[1:0] - end - attribute \src "issuer_ls180.v:138259.3-138260.29" - process $proc$issuer_ls180.v:138259$6897 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "issuer_ls180.v:138339.3-138356.6" - process $proc$issuer_ls180.v:138339$6898 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$6899 $2\r_busy$next[0:0]$6901 - attribute \src "issuer_ls180.v:138340.5-138340.29" - switch \initial - attribute \src "issuer_ls180.v:138340.9-138340.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$6900 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\r_busy$next[0:0]$6900 1'0 - case - assign $1\r_busy$next[0:0]$6900 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$6901 1'0 - case - assign $2\r_busy$next[0:0]$6901 $1\r_busy$next[0:0]$6900 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$6899 - end - attribute \src "issuer_ls180.v:138357.3-138369.6" - process $proc$issuer_ls180.v:138357$6902 - assign { } { } - assign { } { } - assign $0\muxid$next[1:0]$6903 $1\muxid$next[1:0]$6904 - attribute \src "issuer_ls180.v:138358.5-138358.29" - switch \initial - attribute \src "issuer_ls180.v:138358.9-138358.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$next[1:0]$6904 \muxid$52 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$next[1:0]$6904 \muxid$52 - case - assign $1\muxid$next[1:0]$6904 \muxid - end - sync always - update \muxid$next $0\muxid$next[1:0]$6903 - end - attribute \src "issuer_ls180.v:138370.3-138405.6" - process $proc$issuer_ls180.v:138370$6905 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\mul_op__fn_unit$next[11:0]$6906 $1\mul_op__fn_unit$next[11:0]$6918 - assign { } { } - assign { } { } - assign $0\mul_op__insn$next[31:0]$6909 $1\mul_op__insn$next[31:0]$6921 - assign $0\mul_op__insn_type$next[6:0]$6910 $1\mul_op__insn_type$next[6:0]$6922 - assign $0\mul_op__is_32bit$next[0:0]$6911 $1\mul_op__is_32bit$next[0:0]$6923 - assign $0\mul_op__is_signed$next[0:0]$6912 $1\mul_op__is_signed$next[0:0]$6924 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\mul_op__write_cr0$next[0:0]$6917 $1\mul_op__write_cr0$next[0:0]$6929 - assign $0\mul_op__imm_data__data$next[63:0]$6907 $2\mul_op__imm_data__data$next[63:0]$6930 - assign $0\mul_op__imm_data__ok$next[0:0]$6908 $2\mul_op__imm_data__ok$next[0:0]$6931 - assign $0\mul_op__oe__oe$next[0:0]$6913 $2\mul_op__oe__oe$next[0:0]$6932 - assign $0\mul_op__oe__ok$next[0:0]$6914 $2\mul_op__oe__ok$next[0:0]$6933 - assign $0\mul_op__rc__ok$next[0:0]$6915 $2\mul_op__rc__ok$next[0:0]$6934 - assign $0\mul_op__rc__rc$next[0:0]$6916 $2\mul_op__rc__rc$next[0:0]$6935 - attribute \src "issuer_ls180.v:138371.5-138371.29" - switch \initial - attribute \src "issuer_ls180.v:138371.9-138371.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\mul_op__insn$next[31:0]$6921 $1\mul_op__is_signed$next[0:0]$6924 $1\mul_op__is_32bit$next[0:0]$6923 $1\mul_op__write_cr0$next[0:0]$6929 $1\mul_op__oe__ok$next[0:0]$6926 $1\mul_op__oe__oe$next[0:0]$6925 $1\mul_op__rc__ok$next[0:0]$6927 $1\mul_op__rc__rc$next[0:0]$6928 $1\mul_op__imm_data__ok$next[0:0]$6920 $1\mul_op__imm_data__data$next[63:0]$6919 $1\mul_op__fn_unit$next[11:0]$6918 $1\mul_op__insn_type$next[6:0]$6922 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\mul_op__insn$next[31:0]$6921 $1\mul_op__is_signed$next[0:0]$6924 $1\mul_op__is_32bit$next[0:0]$6923 $1\mul_op__write_cr0$next[0:0]$6929 $1\mul_op__oe__ok$next[0:0]$6926 $1\mul_op__oe__oe$next[0:0]$6925 $1\mul_op__rc__ok$next[0:0]$6927 $1\mul_op__rc__rc$next[0:0]$6928 $1\mul_op__imm_data__ok$next[0:0]$6920 $1\mul_op__imm_data__data$next[63:0]$6919 $1\mul_op__fn_unit$next[11:0]$6918 $1\mul_op__insn_type$next[6:0]$6922 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } - case - assign $1\mul_op__fn_unit$next[11:0]$6918 \mul_op__fn_unit - assign $1\mul_op__imm_data__data$next[63:0]$6919 \mul_op__imm_data__data - assign $1\mul_op__imm_data__ok$next[0:0]$6920 \mul_op__imm_data__ok - assign $1\mul_op__insn$next[31:0]$6921 \mul_op__insn - assign $1\mul_op__insn_type$next[6:0]$6922 \mul_op__insn_type - assign $1\mul_op__is_32bit$next[0:0]$6923 \mul_op__is_32bit - assign $1\mul_op__is_signed$next[0:0]$6924 \mul_op__is_signed - assign $1\mul_op__oe__oe$next[0:0]$6925 \mul_op__oe__oe - assign $1\mul_op__oe__ok$next[0:0]$6926 \mul_op__oe__ok - assign $1\mul_op__rc__ok$next[0:0]$6927 \mul_op__rc__ok - assign $1\mul_op__rc__rc$next[0:0]$6928 \mul_op__rc__rc - assign $1\mul_op__write_cr0$next[0:0]$6929 \mul_op__write_cr0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\mul_op__imm_data__data$next[63:0]$6930 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$next[0:0]$6931 1'0 - assign $2\mul_op__rc__rc$next[0:0]$6935 1'0 - assign $2\mul_op__rc__ok$next[0:0]$6934 1'0 - assign $2\mul_op__oe__oe$next[0:0]$6932 1'0 - assign $2\mul_op__oe__ok$next[0:0]$6933 1'0 - case - assign $2\mul_op__imm_data__data$next[63:0]$6930 $1\mul_op__imm_data__data$next[63:0]$6919 - assign $2\mul_op__imm_data__ok$next[0:0]$6931 $1\mul_op__imm_data__ok$next[0:0]$6920 - assign $2\mul_op__oe__oe$next[0:0]$6932 $1\mul_op__oe__oe$next[0:0]$6925 - assign $2\mul_op__oe__ok$next[0:0]$6933 $1\mul_op__oe__ok$next[0:0]$6926 - assign $2\mul_op__rc__ok$next[0:0]$6934 $1\mul_op__rc__ok$next[0:0]$6927 - assign $2\mul_op__rc__rc$next[0:0]$6935 $1\mul_op__rc__rc$next[0:0]$6928 - end - sync always - update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[11:0]$6906 - update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$6907 - update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$6908 - update \mul_op__insn$next $0\mul_op__insn$next[31:0]$6909 - update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$6910 - update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$6911 - update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$6912 - update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$6913 - update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$6914 - update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$6915 - update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$6916 - update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$6917 - end - attribute \src "issuer_ls180.v:138406.3-138418.6" - process $proc$issuer_ls180.v:138406$6936 - assign { } { } - assign { } { } - assign $0\ra$next[63:0]$6937 $1\ra$next[63:0]$6938 - attribute \src "issuer_ls180.v:138407.5-138407.29" - switch \initial - attribute \src "issuer_ls180.v:138407.9-138407.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\ra$next[63:0]$6938 \ra$65 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\ra$next[63:0]$6938 \ra$65 - case - assign $1\ra$next[63:0]$6938 \ra - end - sync always - update \ra$next $0\ra$next[63:0]$6937 - end - attribute \src "issuer_ls180.v:138419.3-138431.6" - process $proc$issuer_ls180.v:138419$6939 - assign { } { } - assign { } { } - assign $0\rb$next[63:0]$6940 $1\rb$next[63:0]$6941 - attribute \src "issuer_ls180.v:138420.5-138420.29" - switch \initial - attribute \src "issuer_ls180.v:138420.9-138420.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\rb$next[63:0]$6941 \rb$66 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\rb$next[63:0]$6941 \rb$66 - case - assign $1\rb$next[63:0]$6941 \rb - end - sync always - update \rb$next $0\rb$next[63:0]$6940 - end - attribute \src "issuer_ls180.v:138432.3-138444.6" - process $proc$issuer_ls180.v:138432$6942 - assign { } { } - assign { } { } - assign $0\xer_so$next[0:0]$6943 $1\xer_so$next[0:0]$6944 - attribute \src "issuer_ls180.v:138433.5-138433.29" - switch \initial - attribute \src "issuer_ls180.v:138433.9-138433.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\xer_so$next[0:0]$6944 \xer_so$67 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\xer_so$next[0:0]$6944 \xer_so$67 - case - assign $1\xer_so$next[0:0]$6944 \xer_so - end - sync always - update \xer_so$next $0\xer_so$next[0:0]$6943 - end - attribute \src "issuer_ls180.v:138445.3-138457.6" - process $proc$issuer_ls180.v:138445$6945 - assign { } { } - assign { } { } - assign $0\neg_res$next[0:0]$6946 $1\neg_res$next[0:0]$6947 - attribute \src "issuer_ls180.v:138446.5-138446.29" - switch \initial - attribute \src "issuer_ls180.v:138446.9-138446.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\neg_res$next[0:0]$6947 \neg_res$68 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\neg_res$next[0:0]$6947 \neg_res$68 - case - assign $1\neg_res$next[0:0]$6947 \neg_res - end - sync always - update \neg_res$next $0\neg_res$next[0:0]$6946 - end - attribute \src "issuer_ls180.v:138458.3-138470.6" - process $proc$issuer_ls180.v:138458$6948 - assign { } { } - assign { } { } - assign $0\neg_res32$next[0:0]$6949 $1\neg_res32$next[0:0]$6950 - attribute \src "issuer_ls180.v:138459.5-138459.29" - switch \initial - attribute \src "issuer_ls180.v:138459.9-138459.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\neg_res32$next[0:0]$6950 \neg_res32$69 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\neg_res32$next[0:0]$6950 \neg_res32$69 - case - assign $1\neg_res32$next[0:0]$6950 \neg_res32 - end - sync always - update \neg_res32$next $0\neg_res32$next[0:0]$6949 - end - connect \$50 $and$issuer_ls180.v:138222$6878_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect \neg_res32$69 \mul1_neg_res32 - connect \neg_res$68 \mul1_neg_res - connect \xer_so$67 \mul1_xer_so$48 - connect \rb$66 \mul1_rb$47 - connect \ra$65 \mul1_ra$46 - connect { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } { \mul1_mul_op__insn$45 \mul1_mul_op__is_signed$44 \mul1_mul_op__is_32bit$43 \mul1_mul_op__write_cr0$42 \mul1_mul_op__oe__ok$41 \mul1_mul_op__oe__oe$40 \mul1_mul_op__rc__ok$39 \mul1_mul_op__rc__rc$38 \mul1_mul_op__imm_data__ok$37 \mul1_mul_op__imm_data__data$36 \mul1_mul_op__fn_unit$35 \mul1_mul_op__insn_type$34 } - connect \muxid$52 \mul1_muxid$33 - connect \p_valid_i_p_ready_o \$50 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$49 \p_valid_i - connect \mul1_xer_so \input_xer_so$32 - connect \mul1_rb \input_rb$31 - connect \mul1_ra \input_ra$30 - connect { \mul1_mul_op__insn \mul1_mul_op__is_signed \mul1_mul_op__is_32bit \mul1_mul_op__write_cr0 \mul1_mul_op__oe__ok \mul1_mul_op__oe__oe \mul1_mul_op__rc__ok \mul1_mul_op__rc__rc \mul1_mul_op__imm_data__ok \mul1_mul_op__imm_data__data \mul1_mul_op__fn_unit \mul1_mul_op__insn_type } { \input_mul_op__insn$29 \input_mul_op__is_signed$28 \input_mul_op__is_32bit$27 \input_mul_op__write_cr0$26 \input_mul_op__oe__ok$25 \input_mul_op__oe__oe$24 \input_mul_op__rc__ok$23 \input_mul_op__rc__rc$22 \input_mul_op__imm_data__ok$21 \input_mul_op__imm_data__data$20 \input_mul_op__fn_unit$19 \input_mul_op__insn_type$18 } - connect \mul1_muxid \input_muxid$17 - connect \input_xer_so \xer_so$16 - connect \input_rb \rb$15 - connect \input_ra \ra$14 - connect { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__oe__ok \input_mul_op__oe__oe \input_mul_op__rc__ok \input_mul_op__rc__rc \input_mul_op__imm_data__ok \input_mul_op__imm_data__data \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } - connect \input_muxid \muxid$1 -end -attribute \src "issuer_ls180.v:138497.1-139402.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2" -attribute \generator "nMigen" -module \mul_pipe2 - attribute \src "issuer_ls180.v:138498.7-138498.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire width 12 $0\mul_op__fn_unit$3$next[11:0]$7014 - attribute \src "issuer_ls180.v:139194.3-139195.53" - wire width 12 $0\mul_op__fn_unit$3[11:0]$6982 - attribute \src "issuer_ls180.v:138779.14-138779.43" - wire width 12 $0\mul_op__fn_unit$3[11:0]$7058 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$7015 - attribute \src "issuer_ls180.v:139196.3-139197.67" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$6984 - attribute \src "issuer_ls180.v:138803.14-138803.63" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$7060 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire $0\mul_op__imm_data__ok$5$next[0:0]$7016 - attribute \src "issuer_ls180.v:139198.3-139199.63" - wire $0\mul_op__imm_data__ok$5[0:0]$6986 - attribute \src "issuer_ls180.v:138812.7-138812.38" - wire $0\mul_op__imm_data__ok$5[0:0]$7062 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire width 32 $0\mul_op__insn$13$next[31:0]$7017 - attribute \src "issuer_ls180.v:139214.3-139215.49" - wire width 32 $0\mul_op__insn$13[31:0]$7002 - attribute \src "issuer_ls180.v:138819.14-138819.39" - wire width 32 $0\mul_op__insn$13[31:0]$7064 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire width 7 $0\mul_op__insn_type$2$next[6:0]$7018 - attribute \src "issuer_ls180.v:139192.3-139193.57" - wire width 7 $0\mul_op__insn_type$2[6:0]$6980 - attribute \src "issuer_ls180.v:138976.13-138976.42" - wire width 7 $0\mul_op__insn_type$2[6:0]$7066 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire $0\mul_op__is_32bit$11$next[0:0]$7019 - attribute \src "issuer_ls180.v:139210.3-139211.57" - wire $0\mul_op__is_32bit$11[0:0]$6998 - attribute \src "issuer_ls180.v:139059.7-139059.35" - wire $0\mul_op__is_32bit$11[0:0]$7068 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire $0\mul_op__is_signed$12$next[0:0]$7020 - attribute \src "issuer_ls180.v:139212.3-139213.59" - wire $0\mul_op__is_signed$12[0:0]$7000 - attribute \src "issuer_ls180.v:139068.7-139068.36" - wire $0\mul_op__is_signed$12[0:0]$7070 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire $0\mul_op__oe__oe$8$next[0:0]$7021 - attribute \src "issuer_ls180.v:139204.3-139205.51" - wire $0\mul_op__oe__oe$8[0:0]$6992 - attribute \src "issuer_ls180.v:139079.7-139079.32" - wire $0\mul_op__oe__oe$8[0:0]$7072 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire $0\mul_op__oe__ok$9$next[0:0]$7022 - attribute \src "issuer_ls180.v:139206.3-139207.51" - wire $0\mul_op__oe__ok$9[0:0]$6994 - attribute \src "issuer_ls180.v:139088.7-139088.32" - wire $0\mul_op__oe__ok$9[0:0]$7074 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire $0\mul_op__rc__ok$7$next[0:0]$7023 - attribute \src "issuer_ls180.v:139202.3-139203.51" - wire $0\mul_op__rc__ok$7[0:0]$6990 - attribute \src "issuer_ls180.v:139097.7-139097.32" - wire $0\mul_op__rc__ok$7[0:0]$7076 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire $0\mul_op__rc__rc$6$next[0:0]$7024 - attribute \src "issuer_ls180.v:139200.3-139201.51" - wire $0\mul_op__rc__rc$6[0:0]$6988 - attribute \src "issuer_ls180.v:139106.7-139106.32" - wire $0\mul_op__rc__rc$6[0:0]$7078 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire $0\mul_op__write_cr0$10$next[0:0]$7025 - attribute \src "issuer_ls180.v:139208.3-139209.59" - wire $0\mul_op__write_cr0$10[0:0]$6996 - attribute \src "issuer_ls180.v:139113.7-139113.36" - wire $0\mul_op__write_cr0$10[0:0]$7080 - attribute \src "issuer_ls180.v:139283.3-139295.6" - wire width 2 $0\muxid$1$next[1:0]$7011 - attribute \src "issuer_ls180.v:139216.3-139217.33" - wire width 2 $0\muxid$1[1:0]$7004 - attribute \src "issuer_ls180.v:139122.13-139122.29" - wire width 2 $0\muxid$1[1:0]$7082 - attribute \src "issuer_ls180.v:139358.3-139370.6" - wire $0\neg_res$15$next[0:0]$7051 - attribute \src "issuer_ls180.v:139186.3-139187.39" - wire $0\neg_res$15[0:0]$6975 - attribute \src "issuer_ls180.v:139137.7-139137.26" - wire $0\neg_res$15[0:0]$7084 - attribute \src "issuer_ls180.v:139371.3-139383.6" - wire $0\neg_res32$16$next[0:0]$7054 - attribute \src "issuer_ls180.v:139184.3-139185.43" - wire $0\neg_res32$16[0:0]$6973 - attribute \src "issuer_ls180.v:139146.7-139146.28" - wire $0\neg_res32$16[0:0]$7086 - attribute \src "issuer_ls180.v:139332.3-139344.6" - wire width 129 $0\o$next[128:0]$7045 - attribute \src "issuer_ls180.v:139190.3-139191.19" - wire width 129 $0\o[128:0] - attribute \src "issuer_ls180.v:139265.3-139282.6" - wire $0\r_busy$next[0:0]$7007 - attribute \src "issuer_ls180.v:139218.3-139219.29" - wire $0\r_busy[0:0] - attribute \src "issuer_ls180.v:139345.3-139357.6" - wire $0\xer_so$14$next[0:0]$7048 - attribute \src "issuer_ls180.v:139188.3-139189.37" - wire $0\xer_so$14[0:0]$6977 - attribute \src "issuer_ls180.v:139178.7-139178.25" - wire $0\xer_so$14[0:0]$7090 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire width 12 $1\mul_op__fn_unit$3$next[11:0]$7026 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$7027 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire $1\mul_op__imm_data__ok$5$next[0:0]$7028 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire width 32 $1\mul_op__insn$13$next[31:0]$7029 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire width 7 $1\mul_op__insn_type$2$next[6:0]$7030 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire $1\mul_op__is_32bit$11$next[0:0]$7031 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire $1\mul_op__is_signed$12$next[0:0]$7032 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire $1\mul_op__oe__oe$8$next[0:0]$7033 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire $1\mul_op__oe__ok$9$next[0:0]$7034 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire $1\mul_op__rc__ok$7$next[0:0]$7035 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire $1\mul_op__rc__rc$6$next[0:0]$7036 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire $1\mul_op__write_cr0$10$next[0:0]$7037 - attribute \src "issuer_ls180.v:139283.3-139295.6" - wire width 2 $1\muxid$1$next[1:0]$7012 - attribute \src "issuer_ls180.v:139358.3-139370.6" - wire $1\neg_res$15$next[0:0]$7052 - attribute \src "issuer_ls180.v:139371.3-139383.6" - wire $1\neg_res32$16$next[0:0]$7055 - attribute \src "issuer_ls180.v:139332.3-139344.6" - wire width 129 $1\o$next[128:0]$7046 - attribute \src "issuer_ls180.v:139153.15-139153.57" - wire width 129 $1\o[128:0] - attribute \src "issuer_ls180.v:139265.3-139282.6" - wire $1\r_busy$next[0:0]$7008 - attribute \src "issuer_ls180.v:139167.7-139167.20" - wire $1\r_busy[0:0] - attribute \src "issuer_ls180.v:139345.3-139357.6" - wire $1\xer_so$14$next[0:0]$7049 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$7038 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire $2\mul_op__imm_data__ok$5$next[0:0]$7039 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire $2\mul_op__oe__oe$8$next[0:0]$7040 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire $2\mul_op__oe__ok$9$next[0:0]$7041 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire $2\mul_op__rc__ok$7$next[0:0]$7042 - attribute \src "issuer_ls180.v:139296.3-139331.6" - wire $2\mul_op__rc__rc$6$next[0:0]$7043 - attribute \src "issuer_ls180.v:139265.3-139282.6" - wire $2\r_busy$next[0:0]$7009 - attribute \src "issuer_ls180.v:139183.18-139183.118" - wire $and$issuer_ls180.v:139183$6971_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 41 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:138498.7-138498.15" - wire \initial - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul2_mul_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul2_mul_op__fn_unit$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul2_mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul2_mul_op__imm_data__data$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul2_mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul2_mul_op__imm_data__ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul2_mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul2_mul_op__insn$29 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul2_mul_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute 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attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 25 \mul_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$2$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute 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\enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \mul_op__is_32bit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_32bit$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_32bit$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \mul_op__is_signed$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_signed$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_signed$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__oe$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \mul_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__ok$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \mul_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__ok$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \mul_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__rc$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \mul_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \mul_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__write_cr0$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__write_cr0$45 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 24 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$36 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 23 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 22 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire input 20 \neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire output 39 \neg_res$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire \neg_res$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire \neg_res$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire input 21 \neg_res32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire output 40 \neg_res32$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire \neg_res32$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire \neg_res32$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 output 37 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 \o$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 \o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 17 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 18 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 19 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 38 \xer_so$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \xer_so$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \xer_so$50 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$issuer_ls180.v:139183$6971 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$33 - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:139183$6971_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:139220.8-139256.4" - cell \mul2 \mul2 - connect \mul_op__fn_unit \mul2_mul_op__fn_unit - connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$19 - connect \mul_op__imm_data__data \mul2_mul_op__imm_data__data - connect \mul_op__imm_data__data$4 \mul2_mul_op__imm_data__data$20 - connect \mul_op__imm_data__ok \mul2_mul_op__imm_data__ok - connect \mul_op__imm_data__ok$5 \mul2_mul_op__imm_data__ok$21 - connect \mul_op__insn \mul2_mul_op__insn - connect \mul_op__insn$13 \mul2_mul_op__insn$29 - connect \mul_op__insn_type \mul2_mul_op__insn_type - connect \mul_op__insn_type$2 \mul2_mul_op__insn_type$18 - connect \mul_op__is_32bit \mul2_mul_op__is_32bit - connect \mul_op__is_32bit$11 \mul2_mul_op__is_32bit$27 - connect \mul_op__is_signed \mul2_mul_op__is_signed - connect \mul_op__is_signed$12 \mul2_mul_op__is_signed$28 - connect \mul_op__oe__oe \mul2_mul_op__oe__oe - connect \mul_op__oe__oe$8 \mul2_mul_op__oe__oe$24 - connect \mul_op__oe__ok \mul2_mul_op__oe__ok - connect \mul_op__oe__ok$9 \mul2_mul_op__oe__ok$25 - connect \mul_op__rc__ok \mul2_mul_op__rc__ok - connect \mul_op__rc__ok$7 \mul2_mul_op__rc__ok$23 - connect \mul_op__rc__rc \mul2_mul_op__rc__rc - connect \mul_op__rc__rc$6 \mul2_mul_op__rc__rc$22 - connect \mul_op__write_cr0 \mul2_mul_op__write_cr0 - connect \mul_op__write_cr0$10 \mul2_mul_op__write_cr0$26 - connect \muxid \mul2_muxid - connect \muxid$1 \mul2_muxid$17 - connect \neg_res \mul2_neg_res - connect \neg_res$15 \mul2_neg_res$31 - connect \neg_res32 \mul2_neg_res32 - connect \neg_res32$16 \mul2_neg_res32$32 - connect \o \mul2_o - connect \ra \mul2_ra - connect \rb \mul2_rb - connect \xer_so \mul2_xer_so - connect \xer_so$14 \mul2_xer_so$30 - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:139257.10-139260.4" - cell \n$94 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:139261.10-139264.4" - cell \p$93 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "issuer_ls180.v:138498.7-138498.20" - process $proc$issuer_ls180.v:138498$7056 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:138779.14-138779.43" - process $proc$issuer_ls180.v:138779$7057 - assign { } { } - assign $0\mul_op__fn_unit$3[11:0]$7058 12'000000000000 - sync always - sync init - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7058 - end - attribute \src "issuer_ls180.v:138803.14-138803.63" - process $proc$issuer_ls180.v:138803$7059 - assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$7060 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7060 - end - attribute \src "issuer_ls180.v:138812.7-138812.38" - process $proc$issuer_ls180.v:138812$7061 - assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$7062 1'0 - sync always - sync init - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7062 - end - attribute \src "issuer_ls180.v:138819.14-138819.39" - process $proc$issuer_ls180.v:138819$7063 - assign { } { } - assign $0\mul_op__insn$13[31:0]$7064 0 - sync always - sync init - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7064 - end - attribute \src "issuer_ls180.v:138976.13-138976.42" - process $proc$issuer_ls180.v:138976$7065 - assign { } { } - assign $0\mul_op__insn_type$2[6:0]$7066 7'0000000 - sync always - sync init - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7066 - end - attribute \src "issuer_ls180.v:139059.7-139059.35" - process $proc$issuer_ls180.v:139059$7067 - assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$7068 1'0 - sync always - sync init - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7068 - end - attribute \src "issuer_ls180.v:139068.7-139068.36" - process $proc$issuer_ls180.v:139068$7069 - assign { } { } - assign $0\mul_op__is_signed$12[0:0]$7070 1'0 - sync always - sync init - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7070 - end - attribute \src "issuer_ls180.v:139079.7-139079.32" - process $proc$issuer_ls180.v:139079$7071 - assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$7072 1'0 - sync always - sync init - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7072 - end - attribute \src "issuer_ls180.v:139088.7-139088.32" - process $proc$issuer_ls180.v:139088$7073 - assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$7074 1'0 - sync always - sync init - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7074 - end - attribute \src "issuer_ls180.v:139097.7-139097.32" - process $proc$issuer_ls180.v:139097$7075 - assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$7076 1'0 - sync always - sync init - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7076 - end - attribute \src "issuer_ls180.v:139106.7-139106.32" - process $proc$issuer_ls180.v:139106$7077 - assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$7078 1'0 - sync always - sync init - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7078 - end - attribute \src "issuer_ls180.v:139113.7-139113.36" - process $proc$issuer_ls180.v:139113$7079 - assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$7080 1'0 - sync always - sync init - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7080 - end - attribute \src "issuer_ls180.v:139122.13-139122.29" - process $proc$issuer_ls180.v:139122$7081 - assign { } { } - assign $0\muxid$1[1:0]$7082 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$7082 - end - attribute \src "issuer_ls180.v:139137.7-139137.26" - process $proc$issuer_ls180.v:139137$7083 - assign { } { } - assign $0\neg_res$15[0:0]$7084 1'0 - sync always - sync init - update \neg_res$15 $0\neg_res$15[0:0]$7084 - end - attribute \src "issuer_ls180.v:139146.7-139146.28" - process $proc$issuer_ls180.v:139146$7085 - assign { } { } - assign $0\neg_res32$16[0:0]$7086 1'0 - sync always - sync init - update \neg_res32$16 $0\neg_res32$16[0:0]$7086 - end - attribute \src "issuer_ls180.v:139153.15-139153.57" - process $proc$issuer_ls180.v:139153$7087 - assign { } { } - assign $1\o[128:0] 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o $1\o[128:0] - end - attribute \src "issuer_ls180.v:139167.7-139167.20" - process $proc$issuer_ls180.v:139167$7088 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "issuer_ls180.v:139178.7-139178.25" - process $proc$issuer_ls180.v:139178$7089 - assign { } { } - assign $0\xer_so$14[0:0]$7090 1'0 - sync always - sync init - update \xer_so$14 $0\xer_so$14[0:0]$7090 - end - attribute \src "issuer_ls180.v:139184.3-139185.43" - process $proc$issuer_ls180.v:139184$6972 - assign { } { } - assign $0\neg_res32$16[0:0]$6973 \neg_res32$16$next - sync posedge \coresync_clk - update \neg_res32$16 $0\neg_res32$16[0:0]$6973 - end - attribute \src "issuer_ls180.v:139186.3-139187.39" - process $proc$issuer_ls180.v:139186$6974 - assign { } { } - assign $0\neg_res$15[0:0]$6975 \neg_res$15$next - sync posedge \coresync_clk - update \neg_res$15 $0\neg_res$15[0:0]$6975 - end - attribute \src "issuer_ls180.v:139188.3-139189.37" - process $proc$issuer_ls180.v:139188$6976 - assign { } { } - assign $0\xer_so$14[0:0]$6977 \xer_so$14$next - sync posedge \coresync_clk - update \xer_so$14 $0\xer_so$14[0:0]$6977 - end - attribute \src "issuer_ls180.v:139190.3-139191.19" - process $proc$issuer_ls180.v:139190$6978 - assign { } { } - assign $0\o[128:0] \o$next - sync posedge \coresync_clk - update \o $0\o[128:0] - end - attribute \src "issuer_ls180.v:139192.3-139193.57" - process $proc$issuer_ls180.v:139192$6979 - assign { } { } - assign $0\mul_op__insn_type$2[6:0]$6980 \mul_op__insn_type$2$next - sync posedge \coresync_clk - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$6980 - end - attribute \src "issuer_ls180.v:139194.3-139195.53" - process $proc$issuer_ls180.v:139194$6981 - assign { } { } - assign $0\mul_op__fn_unit$3[11:0]$6982 \mul_op__fn_unit$3$next - sync posedge \coresync_clk - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$6982 - end - attribute \src "issuer_ls180.v:139196.3-139197.67" - process $proc$issuer_ls180.v:139196$6983 - assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$6984 \mul_op__imm_data__data$4$next - sync posedge \coresync_clk - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$6984 - end - attribute \src "issuer_ls180.v:139198.3-139199.63" - process $proc$issuer_ls180.v:139198$6985 - assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$6986 \mul_op__imm_data__ok$5$next - sync posedge \coresync_clk - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$6986 - end - attribute \src "issuer_ls180.v:139200.3-139201.51" - process $proc$issuer_ls180.v:139200$6987 - assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$6988 \mul_op__rc__rc$6$next - sync posedge \coresync_clk - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$6988 - end - attribute \src "issuer_ls180.v:139202.3-139203.51" - process $proc$issuer_ls180.v:139202$6989 - assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$6990 \mul_op__rc__ok$7$next - sync posedge \coresync_clk - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$6990 - end - attribute \src "issuer_ls180.v:139204.3-139205.51" - process $proc$issuer_ls180.v:139204$6991 - assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$6992 \mul_op__oe__oe$8$next - sync posedge \coresync_clk - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$6992 - end - attribute \src "issuer_ls180.v:139206.3-139207.51" - process $proc$issuer_ls180.v:139206$6993 - assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$6994 \mul_op__oe__ok$9$next - sync posedge \coresync_clk - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$6994 - end - attribute \src "issuer_ls180.v:139208.3-139209.59" - process $proc$issuer_ls180.v:139208$6995 - assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$6996 \mul_op__write_cr0$10$next - sync posedge \coresync_clk - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$6996 - end - attribute \src "issuer_ls180.v:139210.3-139211.57" - process $proc$issuer_ls180.v:139210$6997 - assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$6998 \mul_op__is_32bit$11$next - sync posedge \coresync_clk - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$6998 - end - attribute \src "issuer_ls180.v:139212.3-139213.59" - process $proc$issuer_ls180.v:139212$6999 - assign { } { } - assign $0\mul_op__is_signed$12[0:0]$7000 \mul_op__is_signed$12$next - sync posedge \coresync_clk - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7000 - end - attribute \src "issuer_ls180.v:139214.3-139215.49" - process $proc$issuer_ls180.v:139214$7001 - assign { } { } - assign $0\mul_op__insn$13[31:0]$7002 \mul_op__insn$13$next - sync posedge \coresync_clk - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7002 - end - attribute \src "issuer_ls180.v:139216.3-139217.33" - process $proc$issuer_ls180.v:139216$7003 - assign { } { } - assign $0\muxid$1[1:0]$7004 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$7004 - end - attribute \src "issuer_ls180.v:139218.3-139219.29" - process $proc$issuer_ls180.v:139218$7005 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "issuer_ls180.v:139265.3-139282.6" - process $proc$issuer_ls180.v:139265$7006 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$7007 $2\r_busy$next[0:0]$7009 - attribute \src "issuer_ls180.v:139266.5-139266.29" - switch \initial - attribute \src "issuer_ls180.v:139266.9-139266.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$7008 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\r_busy$next[0:0]$7008 1'0 - case - assign $1\r_busy$next[0:0]$7008 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$7009 1'0 - case - assign $2\r_busy$next[0:0]$7009 $1\r_busy$next[0:0]$7008 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$7007 - end - attribute \src "issuer_ls180.v:139283.3-139295.6" - process $proc$issuer_ls180.v:139283$7010 - assign { } { } - assign { } { } - assign $0\muxid$1$next[1:0]$7011 $1\muxid$1$next[1:0]$7012 - attribute \src "issuer_ls180.v:139284.5-139284.29" - switch \initial - attribute \src "issuer_ls180.v:139284.9-139284.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$1$next[1:0]$7012 \muxid$36 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$1$next[1:0]$7012 \muxid$36 - case - assign $1\muxid$1$next[1:0]$7012 \muxid$1 - end - sync always - update \muxid$1$next $0\muxid$1$next[1:0]$7011 - end - attribute \src "issuer_ls180.v:139296.3-139331.6" - process $proc$issuer_ls180.v:139296$7013 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\mul_op__fn_unit$3$next[11:0]$7014 $1\mul_op__fn_unit$3$next[11:0]$7026 - assign { } { } - assign { } { } - assign $0\mul_op__insn$13$next[31:0]$7017 $1\mul_op__insn$13$next[31:0]$7029 - assign $0\mul_op__insn_type$2$next[6:0]$7018 $1\mul_op__insn_type$2$next[6:0]$7030 - assign $0\mul_op__is_32bit$11$next[0:0]$7019 $1\mul_op__is_32bit$11$next[0:0]$7031 - assign $0\mul_op__is_signed$12$next[0:0]$7020 $1\mul_op__is_signed$12$next[0:0]$7032 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\mul_op__write_cr0$10$next[0:0]$7025 $1\mul_op__write_cr0$10$next[0:0]$7037 - assign $0\mul_op__imm_data__data$4$next[63:0]$7015 $2\mul_op__imm_data__data$4$next[63:0]$7038 - assign $0\mul_op__imm_data__ok$5$next[0:0]$7016 $2\mul_op__imm_data__ok$5$next[0:0]$7039 - assign $0\mul_op__oe__oe$8$next[0:0]$7021 $2\mul_op__oe__oe$8$next[0:0]$7040 - assign $0\mul_op__oe__ok$9$next[0:0]$7022 $2\mul_op__oe__ok$9$next[0:0]$7041 - assign $0\mul_op__rc__ok$7$next[0:0]$7023 $2\mul_op__rc__ok$7$next[0:0]$7042 - assign $0\mul_op__rc__rc$6$next[0:0]$7024 $2\mul_op__rc__rc$6$next[0:0]$7043 - attribute \src "issuer_ls180.v:139297.5-139297.29" - switch \initial - attribute \src "issuer_ls180.v:139297.9-139297.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$7029 $1\mul_op__is_signed$12$next[0:0]$7032 $1\mul_op__is_32bit$11$next[0:0]$7031 $1\mul_op__write_cr0$10$next[0:0]$7037 $1\mul_op__oe__ok$9$next[0:0]$7034 $1\mul_op__oe__oe$8$next[0:0]$7033 $1\mul_op__rc__ok$7$next[0:0]$7035 $1\mul_op__rc__rc$6$next[0:0]$7036 $1\mul_op__imm_data__ok$5$next[0:0]$7028 $1\mul_op__imm_data__data$4$next[63:0]$7027 $1\mul_op__fn_unit$3$next[11:0]$7026 $1\mul_op__insn_type$2$next[6:0]$7030 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$7029 $1\mul_op__is_signed$12$next[0:0]$7032 $1\mul_op__is_32bit$11$next[0:0]$7031 $1\mul_op__write_cr0$10$next[0:0]$7037 $1\mul_op__oe__ok$9$next[0:0]$7034 $1\mul_op__oe__oe$8$next[0:0]$7033 $1\mul_op__rc__ok$7$next[0:0]$7035 $1\mul_op__rc__rc$6$next[0:0]$7036 $1\mul_op__imm_data__ok$5$next[0:0]$7028 $1\mul_op__imm_data__data$4$next[63:0]$7027 $1\mul_op__fn_unit$3$next[11:0]$7026 $1\mul_op__insn_type$2$next[6:0]$7030 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } - case - assign $1\mul_op__fn_unit$3$next[11:0]$7026 \mul_op__fn_unit$3 - assign $1\mul_op__imm_data__data$4$next[63:0]$7027 \mul_op__imm_data__data$4 - assign $1\mul_op__imm_data__ok$5$next[0:0]$7028 \mul_op__imm_data__ok$5 - assign $1\mul_op__insn$13$next[31:0]$7029 \mul_op__insn$13 - assign $1\mul_op__insn_type$2$next[6:0]$7030 \mul_op__insn_type$2 - assign $1\mul_op__is_32bit$11$next[0:0]$7031 \mul_op__is_32bit$11 - assign $1\mul_op__is_signed$12$next[0:0]$7032 \mul_op__is_signed$12 - assign $1\mul_op__oe__oe$8$next[0:0]$7033 \mul_op__oe__oe$8 - assign $1\mul_op__oe__ok$9$next[0:0]$7034 \mul_op__oe__ok$9 - assign $1\mul_op__rc__ok$7$next[0:0]$7035 \mul_op__rc__ok$7 - assign $1\mul_op__rc__rc$6$next[0:0]$7036 \mul_op__rc__rc$6 - assign $1\mul_op__write_cr0$10$next[0:0]$7037 \mul_op__write_cr0$10 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\mul_op__imm_data__data$4$next[63:0]$7038 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$5$next[0:0]$7039 1'0 - assign $2\mul_op__rc__rc$6$next[0:0]$7043 1'0 - assign $2\mul_op__rc__ok$7$next[0:0]$7042 1'0 - assign $2\mul_op__oe__oe$8$next[0:0]$7040 1'0 - assign $2\mul_op__oe__ok$9$next[0:0]$7041 1'0 - case - assign $2\mul_op__imm_data__data$4$next[63:0]$7038 $1\mul_op__imm_data__data$4$next[63:0]$7027 - assign $2\mul_op__imm_data__ok$5$next[0:0]$7039 $1\mul_op__imm_data__ok$5$next[0:0]$7028 - assign $2\mul_op__oe__oe$8$next[0:0]$7040 $1\mul_op__oe__oe$8$next[0:0]$7033 - assign $2\mul_op__oe__ok$9$next[0:0]$7041 $1\mul_op__oe__ok$9$next[0:0]$7034 - assign $2\mul_op__rc__ok$7$next[0:0]$7042 $1\mul_op__rc__ok$7$next[0:0]$7035 - assign $2\mul_op__rc__rc$6$next[0:0]$7043 $1\mul_op__rc__rc$6$next[0:0]$7036 - end - sync always - update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[11:0]$7014 - update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$7015 - update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$7016 - update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$7017 - update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$7018 - update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$7019 - update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$7020 - update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$7021 - update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$7022 - update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$7023 - update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$7024 - update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$7025 - end - attribute \src "issuer_ls180.v:139332.3-139344.6" - process $proc$issuer_ls180.v:139332$7044 - assign { } { } - assign { } { } - assign $0\o$next[128:0]$7045 $1\o$next[128:0]$7046 - attribute \src "issuer_ls180.v:139333.5-139333.29" - switch \initial - attribute \src "issuer_ls180.v:139333.9-139333.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\o$next[128:0]$7046 \o$49 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\o$next[128:0]$7046 \o$49 - case - assign $1\o$next[128:0]$7046 \o - end - sync always - update \o$next $0\o$next[128:0]$7045 - end - attribute \src "issuer_ls180.v:139345.3-139357.6" - process $proc$issuer_ls180.v:139345$7047 - assign { } { } - assign { } { } - assign $0\xer_so$14$next[0:0]$7048 $1\xer_so$14$next[0:0]$7049 - attribute \src "issuer_ls180.v:139346.5-139346.29" - switch \initial - attribute \src "issuer_ls180.v:139346.9-139346.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\xer_so$14$next[0:0]$7049 \xer_so$50 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\xer_so$14$next[0:0]$7049 \xer_so$50 - case - assign $1\xer_so$14$next[0:0]$7049 \xer_so$14 - end - sync always - update \xer_so$14$next $0\xer_so$14$next[0:0]$7048 - end - attribute \src "issuer_ls180.v:139358.3-139370.6" - process $proc$issuer_ls180.v:139358$7050 - assign { } { } - assign { } { } - assign $0\neg_res$15$next[0:0]$7051 $1\neg_res$15$next[0:0]$7052 - attribute \src "issuer_ls180.v:139359.5-139359.29" - switch \initial - attribute \src "issuer_ls180.v:139359.9-139359.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\neg_res$15$next[0:0]$7052 \neg_res$51 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\neg_res$15$next[0:0]$7052 \neg_res$51 - case - assign $1\neg_res$15$next[0:0]$7052 \neg_res$15 - end - sync always - update \neg_res$15$next $0\neg_res$15$next[0:0]$7051 - end - attribute \src "issuer_ls180.v:139371.3-139383.6" - process $proc$issuer_ls180.v:139371$7053 - assign { } { } - assign { } { } - assign $0\neg_res32$16$next[0:0]$7054 $1\neg_res32$16$next[0:0]$7055 - attribute \src "issuer_ls180.v:139372.5-139372.29" - switch \initial - attribute \src "issuer_ls180.v:139372.9-139372.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\neg_res32$16$next[0:0]$7055 \neg_res32$52 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\neg_res32$16$next[0:0]$7055 \neg_res32$52 - case - assign $1\neg_res32$16$next[0:0]$7055 \neg_res32$16 - end - sync always - update \neg_res32$16$next $0\neg_res32$16$next[0:0]$7054 - end - connect \$34 $and$issuer_ls180.v:139183$6971_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect \neg_res32$52 \mul2_neg_res32$32 - connect \neg_res$51 \mul2_neg_res$31 - connect \xer_so$50 \mul2_xer_so$30 - connect \o$49 \mul2_o - connect { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } { \mul2_mul_op__insn$29 \mul2_mul_op__is_signed$28 \mul2_mul_op__is_32bit$27 \mul2_mul_op__write_cr0$26 \mul2_mul_op__oe__ok$25 \mul2_mul_op__oe__oe$24 \mul2_mul_op__rc__ok$23 \mul2_mul_op__rc__rc$22 \mul2_mul_op__imm_data__ok$21 \mul2_mul_op__imm_data__data$20 \mul2_mul_op__fn_unit$19 \mul2_mul_op__insn_type$18 } - connect \muxid$36 \mul2_muxid$17 - connect \p_valid_i_p_ready_o \$34 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$33 \p_valid_i - connect \mul2_neg_res32 \neg_res32 - connect \mul2_neg_res \neg_res - connect \mul2_xer_so \xer_so - connect \mul2_rb \rb - connect \mul2_ra \ra - connect { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__oe__ok \mul2_mul_op__oe__oe \mul2_mul_op__rc__ok \mul2_mul_op__rc__rc \mul2_mul_op__imm_data__ok \mul2_mul_op__imm_data__data \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } - connect \mul2_muxid \muxid -end -attribute \src "issuer_ls180.v:139406.1-140681.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3" -attribute \generator "nMigen" -module \mul_pipe3 - attribute \src "issuer_ls180.v:140599.3-140617.6" - wire width 4 $0\cr_a$next[3:0]$7174 - attribute \src "issuer_ls180.v:140391.3-140392.25" - wire width 4 $0\cr_a[3:0] - attribute \src "issuer_ls180.v:140599.3-140617.6" - wire $0\cr_a_ok$next[0:0]$7175 - attribute \src "issuer_ls180.v:140393.3-140394.31" - wire $0\cr_a_ok[0:0] - attribute \src "issuer_ls180.v:139407.7-139407.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire width 12 $0\mul_op__fn_unit$3$next[11:0]$7137 - attribute \src "issuer_ls180.v:140401.3-140402.53" - wire width 12 $0\mul_op__fn_unit$3[11:0]$7105 - attribute \src "issuer_ls180.v:139708.14-139708.43" - wire width 12 $0\mul_op__fn_unit$3[11:0]$7195 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$7138 - attribute \src "issuer_ls180.v:140403.3-140404.67" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$7107 - attribute \src "issuer_ls180.v:139730.14-139730.63" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$7197 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire $0\mul_op__imm_data__ok$5$next[0:0]$7139 - attribute \src "issuer_ls180.v:140405.3-140406.63" - wire $0\mul_op__imm_data__ok$5[0:0]$7109 - attribute \src "issuer_ls180.v:139739.7-139739.38" - wire $0\mul_op__imm_data__ok$5[0:0]$7199 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire width 32 $0\mul_op__insn$13$next[31:0]$7140 - attribute \src "issuer_ls180.v:140421.3-140422.49" - wire width 32 $0\mul_op__insn$13[31:0]$7125 - attribute \src "issuer_ls180.v:139748.14-139748.39" - wire width 32 $0\mul_op__insn$13[31:0]$7201 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire width 7 $0\mul_op__insn_type$2$next[6:0]$7141 - attribute \src "issuer_ls180.v:140399.3-140400.57" - wire width 7 $0\mul_op__insn_type$2[6:0]$7103 - attribute \src "issuer_ls180.v:139905.13-139905.42" - wire width 7 $0\mul_op__insn_type$2[6:0]$7203 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire $0\mul_op__is_32bit$11$next[0:0]$7142 - attribute \src "issuer_ls180.v:140417.3-140418.57" - wire $0\mul_op__is_32bit$11[0:0]$7121 - attribute \src "issuer_ls180.v:139988.7-139988.35" - wire $0\mul_op__is_32bit$11[0:0]$7205 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire $0\mul_op__is_signed$12$next[0:0]$7143 - attribute \src "issuer_ls180.v:140419.3-140420.59" - wire $0\mul_op__is_signed$12[0:0]$7123 - attribute \src "issuer_ls180.v:139997.7-139997.36" - wire $0\mul_op__is_signed$12[0:0]$7207 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire $0\mul_op__oe__oe$8$next[0:0]$7144 - attribute \src "issuer_ls180.v:140411.3-140412.51" - wire $0\mul_op__oe__oe$8[0:0]$7115 - attribute \src "issuer_ls180.v:140008.7-140008.32" - wire $0\mul_op__oe__oe$8[0:0]$7209 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire $0\mul_op__oe__ok$9$next[0:0]$7145 - attribute \src "issuer_ls180.v:140413.3-140414.51" - wire $0\mul_op__oe__ok$9[0:0]$7117 - attribute \src "issuer_ls180.v:140017.7-140017.32" - wire $0\mul_op__oe__ok$9[0:0]$7211 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire $0\mul_op__rc__ok$7$next[0:0]$7146 - attribute \src "issuer_ls180.v:140409.3-140410.51" - wire $0\mul_op__rc__ok$7[0:0]$7113 - attribute \src "issuer_ls180.v:140026.7-140026.32" - wire $0\mul_op__rc__ok$7[0:0]$7213 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire $0\mul_op__rc__rc$6$next[0:0]$7147 - attribute \src "issuer_ls180.v:140407.3-140408.51" - wire $0\mul_op__rc__rc$6[0:0]$7111 - attribute \src "issuer_ls180.v:140033.7-140033.32" - wire $0\mul_op__rc__rc$6[0:0]$7215 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire $0\mul_op__write_cr0$10$next[0:0]$7148 - attribute \src "issuer_ls180.v:140415.3-140416.59" - wire $0\mul_op__write_cr0$10[0:0]$7119 - attribute \src "issuer_ls180.v:140042.7-140042.36" - wire $0\mul_op__write_cr0$10[0:0]$7217 - attribute \src "issuer_ls180.v:140531.3-140543.6" - wire width 2 $0\muxid$1$next[1:0]$7134 - attribute \src "issuer_ls180.v:140423.3-140424.33" - wire width 2 $0\muxid$1[1:0]$7127 - attribute \src "issuer_ls180.v:140051.13-140051.29" - wire width 2 $0\muxid$1[1:0]$7219 - attribute \src "issuer_ls180.v:140580.3-140598.6" - wire width 64 $0\o$14$next[63:0]$7169 - attribute \src "issuer_ls180.v:140395.3-140396.27" - wire width 64 $0\o$14[63:0]$7100 - attribute \src "issuer_ls180.v:140072.14-140072.43" - wire width 64 $0\o$14[63:0]$7221 - attribute \src "issuer_ls180.v:140580.3-140598.6" - wire $0\o_ok$next[0:0]$7168 - attribute \src "issuer_ls180.v:140397.3-140398.25" - wire $0\o_ok[0:0] - attribute \src "issuer_ls180.v:140513.3-140530.6" - wire $0\r_busy$next[0:0]$7130 - attribute \src "issuer_ls180.v:140425.3-140426.29" - wire $0\r_busy[0:0] - attribute \src "issuer_ls180.v:140618.3-140636.6" - wire width 2 $0\xer_ov$next[1:0]$7180 - attribute \src "issuer_ls180.v:140387.3-140388.29" - wire width 2 $0\xer_ov[1:0] - attribute \src "issuer_ls180.v:140618.3-140636.6" - wire $0\xer_ov_ok$next[0:0]$7181 - attribute \src "issuer_ls180.v:140389.3-140390.35" - wire $0\xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:140637.3-140655.6" - wire $0\xer_so$15$next[0:0]$7187 - attribute \src "issuer_ls180.v:140383.3-140384.37" - wire $0\xer_so$15[0:0]$7093 - attribute \src "issuer_ls180.v:140368.7-140368.25" - wire $0\xer_so$15[0:0]$7227 - attribute \src "issuer_ls180.v:140637.3-140655.6" - wire $0\xer_so_ok$next[0:0]$7186 - attribute \src "issuer_ls180.v:140385.3-140386.35" - wire $0\xer_so_ok[0:0] - attribute \src "issuer_ls180.v:140599.3-140617.6" - wire width 4 $1\cr_a$next[3:0]$7176 - attribute \src "issuer_ls180.v:139416.13-139416.24" - wire width 4 $1\cr_a[3:0] - attribute \src "issuer_ls180.v:140599.3-140617.6" - wire $1\cr_a_ok$next[0:0]$7177 - attribute \src "issuer_ls180.v:139425.7-139425.21" - wire $1\cr_a_ok[0:0] - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire width 12 $1\mul_op__fn_unit$3$next[11:0]$7149 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$7150 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire $1\mul_op__imm_data__ok$5$next[0:0]$7151 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire width 32 $1\mul_op__insn$13$next[31:0]$7152 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire width 7 $1\mul_op__insn_type$2$next[6:0]$7153 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire $1\mul_op__is_32bit$11$next[0:0]$7154 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire $1\mul_op__is_signed$12$next[0:0]$7155 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire $1\mul_op__oe__oe$8$next[0:0]$7156 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire $1\mul_op__oe__ok$9$next[0:0]$7157 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire $1\mul_op__rc__ok$7$next[0:0]$7158 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire $1\mul_op__rc__rc$6$next[0:0]$7159 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire $1\mul_op__write_cr0$10$next[0:0]$7160 - attribute \src "issuer_ls180.v:140531.3-140543.6" - wire width 2 $1\muxid$1$next[1:0]$7135 - attribute \src "issuer_ls180.v:140580.3-140598.6" - wire width 64 $1\o$14$next[63:0]$7171 - attribute \src "issuer_ls180.v:140580.3-140598.6" - wire $1\o_ok$next[0:0]$7170 - attribute \src "issuer_ls180.v:140079.7-140079.18" - wire $1\o_ok[0:0] - attribute \src "issuer_ls180.v:140513.3-140530.6" - wire $1\r_busy$next[0:0]$7131 - attribute \src "issuer_ls180.v:140345.7-140345.20" - wire $1\r_busy[0:0] - attribute \src "issuer_ls180.v:140618.3-140636.6" - wire width 2 $1\xer_ov$next[1:0]$7182 - attribute \src "issuer_ls180.v:140350.13-140350.26" - wire width 2 $1\xer_ov[1:0] - attribute \src "issuer_ls180.v:140618.3-140636.6" - wire $1\xer_ov_ok$next[0:0]$7183 - attribute \src "issuer_ls180.v:140357.7-140357.23" - wire $1\xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:140637.3-140655.6" - wire $1\xer_so$15$next[0:0]$7189 - attribute \src "issuer_ls180.v:140637.3-140655.6" - wire $1\xer_so_ok$next[0:0]$7188 - attribute \src "issuer_ls180.v:140375.7-140375.23" - wire $1\xer_so_ok[0:0] - attribute \src "issuer_ls180.v:140599.3-140617.6" - wire $2\cr_a_ok$next[0:0]$7178 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$7161 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire $2\mul_op__imm_data__ok$5$next[0:0]$7162 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire $2\mul_op__oe__oe$8$next[0:0]$7163 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire $2\mul_op__oe__ok$9$next[0:0]$7164 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire $2\mul_op__rc__ok$7$next[0:0]$7165 - attribute \src "issuer_ls180.v:140544.3-140579.6" - wire $2\mul_op__rc__rc$6$next[0:0]$7166 - attribute \src "issuer_ls180.v:140580.3-140598.6" - wire $2\o_ok$next[0:0]$7172 - attribute \src "issuer_ls180.v:140513.3-140530.6" - wire $2\r_busy$next[0:0]$7132 - attribute \src "issuer_ls180.v:140618.3-140636.6" - wire $2\xer_ov_ok$next[0:0]$7184 - attribute \src "issuer_ls180.v:140637.3-140655.6" - wire $2\xer_so_ok$next[0:0]$7190 - attribute \src "issuer_ls180.v:140382.18-140382.118" - wire $and$issuer_ls180.v:140382$7091_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 44 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 38 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 39 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$next - attribute \src "issuer_ls180.v:139407.7-139407.15" - wire \initial - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul3_mul_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul3_mul_op__fn_unit$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul3_mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul3_mul_op__imm_data__data$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul3_mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul3_mul_op__imm_data__ok$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul3_mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul3_mul_op__insn$28 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute 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attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \mul_op__is_32bit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_32bit$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_32bit$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \mul_op__is_signed$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_signed$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_signed$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__oe$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \mul_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__ok$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \mul_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__ok$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \mul_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \mul_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__rc$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \mul_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__write_cr0$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__write_cr0$67 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 23 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$58 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 22 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 21 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire input 19 \neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire input 20 \neg_res32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire \neg_res32$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 input 17 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 36 \o$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 37 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_cr_a_ok - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_mul_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_mul_op__fn_unit$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_mul_op__imm_data__data$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__imm_data__ok$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_mul_op__insn$43 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_mul_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_mul_op__insn_type$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__is_32bit$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__is_signed$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__oe__oe$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__oe__ok$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__rc__ok$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__rc__rc$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__write_cr0$40 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_o$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_o_ok$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ov$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_xer_so$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$55 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 40 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 41 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ov_ok$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ov_ok$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 18 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 42 \xer_so$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 43 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$issuer_ls180.v:140382$7091 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$55 - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:140382$7091_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:140427.8-140463.4" - cell \mul3 \mul3 - connect \mul_op__fn_unit \mul3_mul_op__fn_unit - connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$18 - connect \mul_op__imm_data__data \mul3_mul_op__imm_data__data - connect \mul_op__imm_data__data$4 \mul3_mul_op__imm_data__data$19 - connect \mul_op__imm_data__ok \mul3_mul_op__imm_data__ok - connect \mul_op__imm_data__ok$5 \mul3_mul_op__imm_data__ok$20 - connect \mul_op__insn \mul3_mul_op__insn - connect \mul_op__insn$13 \mul3_mul_op__insn$28 - connect \mul_op__insn_type \mul3_mul_op__insn_type - connect \mul_op__insn_type$2 \mul3_mul_op__insn_type$17 - connect \mul_op__is_32bit \mul3_mul_op__is_32bit - connect \mul_op__is_32bit$11 \mul3_mul_op__is_32bit$26 - connect \mul_op__is_signed \mul3_mul_op__is_signed - connect \mul_op__is_signed$12 \mul3_mul_op__is_signed$27 - connect \mul_op__oe__oe \mul3_mul_op__oe__oe - connect \mul_op__oe__oe$8 \mul3_mul_op__oe__oe$23 - connect \mul_op__oe__ok \mul3_mul_op__oe__ok - connect \mul_op__oe__ok$9 \mul3_mul_op__oe__ok$24 - connect \mul_op__rc__ok \mul3_mul_op__rc__ok - connect \mul_op__rc__ok$7 \mul3_mul_op__rc__ok$22 - connect \mul_op__rc__rc \mul3_mul_op__rc__rc - connect \mul_op__rc__rc$6 \mul3_mul_op__rc__rc$21 - connect \mul_op__write_cr0 \mul3_mul_op__write_cr0 - connect \mul_op__write_cr0$10 \mul3_mul_op__write_cr0$25 - connect \muxid \mul3_muxid - connect \muxid$1 \mul3_muxid$16 - connect \neg_res \mul3_neg_res - connect \o \mul3_o - connect \o$14 \mul3_o$29 - connect \o_ok \mul3_o_ok - connect \xer_ov \mul3_xer_ov - connect \xer_ov_ok \mul3_xer_ov_ok - connect \xer_so \mul3_xer_so - connect \xer_so$15 \mul3_xer_so$30 - connect \xer_so_ok \mul3_xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:140464.10-140467.4" - cell \n$96 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:140468.15-140508.4" - cell \output$97 \output - connect \cr_a \output_cr_a - connect \cr_a$16 \output_cr_a$46 - connect \cr_a_ok \output_cr_a_ok - connect \mul_op__fn_unit \output_mul_op__fn_unit - connect \mul_op__fn_unit$3 \output_mul_op__fn_unit$33 - connect \mul_op__imm_data__data \output_mul_op__imm_data__data - connect \mul_op__imm_data__data$4 \output_mul_op__imm_data__data$34 - connect \mul_op__imm_data__ok \output_mul_op__imm_data__ok - connect \mul_op__imm_data__ok$5 \output_mul_op__imm_data__ok$35 - connect \mul_op__insn \output_mul_op__insn - connect \mul_op__insn$13 \output_mul_op__insn$43 - connect \mul_op__insn_type \output_mul_op__insn_type - connect \mul_op__insn_type$2 \output_mul_op__insn_type$32 - connect \mul_op__is_32bit \output_mul_op__is_32bit - connect \mul_op__is_32bit$11 \output_mul_op__is_32bit$41 - connect \mul_op__is_signed \output_mul_op__is_signed - connect \mul_op__is_signed$12 \output_mul_op__is_signed$42 - connect \mul_op__oe__oe \output_mul_op__oe__oe - connect \mul_op__oe__oe$8 \output_mul_op__oe__oe$38 - connect \mul_op__oe__ok \output_mul_op__oe__ok - connect \mul_op__oe__ok$9 \output_mul_op__oe__ok$39 - connect \mul_op__rc__ok \output_mul_op__rc__ok - connect \mul_op__rc__ok$7 \output_mul_op__rc__ok$37 - connect \mul_op__rc__rc \output_mul_op__rc__rc - connect \mul_op__rc__rc$6 \output_mul_op__rc__rc$36 - connect \mul_op__write_cr0 \output_mul_op__write_cr0 - connect \mul_op__write_cr0$10 \output_mul_op__write_cr0$40 - connect \muxid \output_muxid - connect \muxid$1 \output_muxid$31 - connect \o \output_o - connect \o$14 \output_o$44 - connect \o_ok \output_o_ok - connect \o_ok$15 \output_o_ok$45 - connect \xer_ov \output_xer_ov - connect \xer_ov$17 \output_xer_ov$47 - connect \xer_ov_ok \output_xer_ov_ok - connect \xer_so \output_xer_so - connect \xer_so$18 \output_xer_so$48 - connect \xer_so_ok \output_xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:140509.10-140512.4" - cell \p$95 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "issuer_ls180.v:139407.7-139407.20" - process $proc$issuer_ls180.v:139407$7191 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:139416.13-139416.24" - process $proc$issuer_ls180.v:139416$7192 - assign { } { } - assign $1\cr_a[3:0] 4'0000 - sync always - sync init - update \cr_a $1\cr_a[3:0] - end - attribute \src "issuer_ls180.v:139425.7-139425.21" - process $proc$issuer_ls180.v:139425$7193 - assign { } { } - assign $1\cr_a_ok[0:0] 1'0 - sync always - sync init - update \cr_a_ok $1\cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:139708.14-139708.43" - process $proc$issuer_ls180.v:139708$7194 - assign { } { } - assign $0\mul_op__fn_unit$3[11:0]$7195 12'000000000000 - sync always - sync init - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7195 - end - attribute \src "issuer_ls180.v:139730.14-139730.63" - process $proc$issuer_ls180.v:139730$7196 - assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$7197 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7197 - end - attribute \src "issuer_ls180.v:139739.7-139739.38" - process $proc$issuer_ls180.v:139739$7198 - assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$7199 1'0 - sync always - sync init - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7199 - end - attribute \src "issuer_ls180.v:139748.14-139748.39" - process $proc$issuer_ls180.v:139748$7200 - assign { } { } - assign $0\mul_op__insn$13[31:0]$7201 0 - sync always - sync init - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7201 - end - attribute \src "issuer_ls180.v:139905.13-139905.42" - process $proc$issuer_ls180.v:139905$7202 - assign { } { } - assign $0\mul_op__insn_type$2[6:0]$7203 7'0000000 - sync always - sync init - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7203 - end - attribute \src "issuer_ls180.v:139988.7-139988.35" - process $proc$issuer_ls180.v:139988$7204 - assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$7205 1'0 - sync always - sync init - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7205 - end - attribute \src "issuer_ls180.v:139997.7-139997.36" - process $proc$issuer_ls180.v:139997$7206 - assign { } { } - assign $0\mul_op__is_signed$12[0:0]$7207 1'0 - sync always - sync init - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7207 - end - attribute \src "issuer_ls180.v:140008.7-140008.32" - process $proc$issuer_ls180.v:140008$7208 - assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$7209 1'0 - sync always - sync init - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7209 - end - attribute \src "issuer_ls180.v:140017.7-140017.32" - process $proc$issuer_ls180.v:140017$7210 - assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$7211 1'0 - sync always - sync init - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7211 - end - attribute \src "issuer_ls180.v:140026.7-140026.32" - process $proc$issuer_ls180.v:140026$7212 - assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$7213 1'0 - sync always - sync init - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7213 - end - attribute \src "issuer_ls180.v:140033.7-140033.32" - process $proc$issuer_ls180.v:140033$7214 - assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$7215 1'0 - sync always - sync init - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7215 - end - attribute \src "issuer_ls180.v:140042.7-140042.36" - process $proc$issuer_ls180.v:140042$7216 - assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$7217 1'0 - sync always - sync init - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7217 - end - attribute \src "issuer_ls180.v:140051.13-140051.29" - process $proc$issuer_ls180.v:140051$7218 - assign { } { } - assign $0\muxid$1[1:0]$7219 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$7219 - end - attribute \src "issuer_ls180.v:140072.14-140072.43" - process $proc$issuer_ls180.v:140072$7220 - assign { } { } - assign $0\o$14[63:0]$7221 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o$14 $0\o$14[63:0]$7221 - end - attribute \src "issuer_ls180.v:140079.7-140079.18" - process $proc$issuer_ls180.v:140079$7222 - assign { } { } - assign $1\o_ok[0:0] 1'0 - sync always - sync init - update \o_ok $1\o_ok[0:0] - end - attribute \src "issuer_ls180.v:140345.7-140345.20" - process $proc$issuer_ls180.v:140345$7223 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "issuer_ls180.v:140350.13-140350.26" - process $proc$issuer_ls180.v:140350$7224 - assign { } { } - assign $1\xer_ov[1:0] 2'00 - sync always - sync init - update \xer_ov $1\xer_ov[1:0] - end - attribute \src "issuer_ls180.v:140357.7-140357.23" - process $proc$issuer_ls180.v:140357$7225 - assign { } { } - assign $1\xer_ov_ok[0:0] 1'0 - sync always - sync init - update \xer_ov_ok $1\xer_ov_ok[0:0] - end - attribute \src "issuer_ls180.v:140368.7-140368.25" - process $proc$issuer_ls180.v:140368$7226 - assign { } { } - assign $0\xer_so$15[0:0]$7227 1'0 - sync always - sync init - update \xer_so$15 $0\xer_so$15[0:0]$7227 - end - attribute \src "issuer_ls180.v:140375.7-140375.23" - process $proc$issuer_ls180.v:140375$7228 - assign { } { } - assign $1\xer_so_ok[0:0] 1'0 - sync always - sync init - update \xer_so_ok $1\xer_so_ok[0:0] - end - attribute \src "issuer_ls180.v:140383.3-140384.37" - process $proc$issuer_ls180.v:140383$7092 - assign { } { } - assign $0\xer_so$15[0:0]$7093 \xer_so$15$next - sync posedge \coresync_clk - update \xer_so$15 $0\xer_so$15[0:0]$7093 - end - attribute \src "issuer_ls180.v:140385.3-140386.35" - process $proc$issuer_ls180.v:140385$7094 - assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next - sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] - end - attribute \src "issuer_ls180.v:140387.3-140388.29" - process $proc$issuer_ls180.v:140387$7095 - assign { } { } - assign $0\xer_ov[1:0] \xer_ov$next - sync posedge \coresync_clk - update \xer_ov $0\xer_ov[1:0] - end - attribute \src "issuer_ls180.v:140389.3-140390.35" - process $proc$issuer_ls180.v:140389$7096 - assign { } { } - assign $0\xer_ov_ok[0:0] \xer_ov_ok$next - sync posedge \coresync_clk - update \xer_ov_ok $0\xer_ov_ok[0:0] - end - attribute \src "issuer_ls180.v:140391.3-140392.25" - process $proc$issuer_ls180.v:140391$7097 - assign { } { } - assign $0\cr_a[3:0] \cr_a$next - sync posedge \coresync_clk - update \cr_a $0\cr_a[3:0] - end - attribute \src "issuer_ls180.v:140393.3-140394.31" - process $proc$issuer_ls180.v:140393$7098 - assign { } { } - assign $0\cr_a_ok[0:0] \cr_a_ok$next - sync posedge \coresync_clk - update \cr_a_ok $0\cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:140395.3-140396.27" - process $proc$issuer_ls180.v:140395$7099 - assign { } { } - assign $0\o$14[63:0]$7100 \o$14$next - sync posedge \coresync_clk - update \o$14 $0\o$14[63:0]$7100 - end - attribute \src "issuer_ls180.v:140397.3-140398.25" - process $proc$issuer_ls180.v:140397$7101 - assign { } { } - assign $0\o_ok[0:0] \o_ok$next - sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] - end - attribute \src "issuer_ls180.v:140399.3-140400.57" - process $proc$issuer_ls180.v:140399$7102 - assign { } { } - assign $0\mul_op__insn_type$2[6:0]$7103 \mul_op__insn_type$2$next - sync posedge \coresync_clk - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7103 - end - attribute \src "issuer_ls180.v:140401.3-140402.53" - process $proc$issuer_ls180.v:140401$7104 - assign { } { } - assign $0\mul_op__fn_unit$3[11:0]$7105 \mul_op__fn_unit$3$next - sync posedge \coresync_clk - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7105 - end - attribute \src "issuer_ls180.v:140403.3-140404.67" - process $proc$issuer_ls180.v:140403$7106 - assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$7107 \mul_op__imm_data__data$4$next - sync posedge \coresync_clk - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7107 - end - attribute \src "issuer_ls180.v:140405.3-140406.63" - process $proc$issuer_ls180.v:140405$7108 - assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$7109 \mul_op__imm_data__ok$5$next - sync posedge \coresync_clk - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7109 - end - attribute \src "issuer_ls180.v:140407.3-140408.51" - process $proc$issuer_ls180.v:140407$7110 - assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$7111 \mul_op__rc__rc$6$next - sync posedge \coresync_clk - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7111 - end - attribute \src "issuer_ls180.v:140409.3-140410.51" - process $proc$issuer_ls180.v:140409$7112 - assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$7113 \mul_op__rc__ok$7$next - sync posedge \coresync_clk - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7113 - end - attribute \src "issuer_ls180.v:140411.3-140412.51" - process $proc$issuer_ls180.v:140411$7114 - assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$7115 \mul_op__oe__oe$8$next - sync posedge \coresync_clk - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7115 - end - attribute \src "issuer_ls180.v:140413.3-140414.51" - process $proc$issuer_ls180.v:140413$7116 - assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$7117 \mul_op__oe__ok$9$next - sync posedge \coresync_clk - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7117 - end - attribute \src "issuer_ls180.v:140415.3-140416.59" - process $proc$issuer_ls180.v:140415$7118 - assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$7119 \mul_op__write_cr0$10$next - sync posedge \coresync_clk - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7119 - end - attribute \src "issuer_ls180.v:140417.3-140418.57" - process $proc$issuer_ls180.v:140417$7120 - assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$7121 \mul_op__is_32bit$11$next - sync posedge \coresync_clk - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7121 - end - attribute \src "issuer_ls180.v:140419.3-140420.59" - process $proc$issuer_ls180.v:140419$7122 - assign { } { } - assign $0\mul_op__is_signed$12[0:0]$7123 \mul_op__is_signed$12$next - sync posedge \coresync_clk - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7123 - end - attribute \src "issuer_ls180.v:140421.3-140422.49" - process $proc$issuer_ls180.v:140421$7124 - assign { } { } - assign $0\mul_op__insn$13[31:0]$7125 \mul_op__insn$13$next - sync posedge \coresync_clk - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7125 - end - attribute \src "issuer_ls180.v:140423.3-140424.33" - process $proc$issuer_ls180.v:140423$7126 - assign { } { } - assign $0\muxid$1[1:0]$7127 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$7127 - end - attribute \src "issuer_ls180.v:140425.3-140426.29" - process $proc$issuer_ls180.v:140425$7128 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "issuer_ls180.v:140513.3-140530.6" - process $proc$issuer_ls180.v:140513$7129 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$7130 $2\r_busy$next[0:0]$7132 - attribute \src "issuer_ls180.v:140514.5-140514.29" - switch \initial - attribute \src "issuer_ls180.v:140514.9-140514.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$7131 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\r_busy$next[0:0]$7131 1'0 - case - assign $1\r_busy$next[0:0]$7131 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$7132 1'0 - case - assign $2\r_busy$next[0:0]$7132 $1\r_busy$next[0:0]$7131 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$7130 - end - attribute \src "issuer_ls180.v:140531.3-140543.6" - process $proc$issuer_ls180.v:140531$7133 - assign { } { } - assign { } { } - assign $0\muxid$1$next[1:0]$7134 $1\muxid$1$next[1:0]$7135 - attribute \src "issuer_ls180.v:140532.5-140532.29" - switch \initial - attribute \src "issuer_ls180.v:140532.9-140532.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$1$next[1:0]$7135 \muxid$58 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$1$next[1:0]$7135 \muxid$58 - case - assign $1\muxid$1$next[1:0]$7135 \muxid$1 - end - sync always - update \muxid$1$next $0\muxid$1$next[1:0]$7134 - end - attribute \src "issuer_ls180.v:140544.3-140579.6" - process $proc$issuer_ls180.v:140544$7136 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\mul_op__fn_unit$3$next[11:0]$7137 $1\mul_op__fn_unit$3$next[11:0]$7149 - assign { } { } - assign { } { } - assign $0\mul_op__insn$13$next[31:0]$7140 $1\mul_op__insn$13$next[31:0]$7152 - assign $0\mul_op__insn_type$2$next[6:0]$7141 $1\mul_op__insn_type$2$next[6:0]$7153 - assign $0\mul_op__is_32bit$11$next[0:0]$7142 $1\mul_op__is_32bit$11$next[0:0]$7154 - assign $0\mul_op__is_signed$12$next[0:0]$7143 $1\mul_op__is_signed$12$next[0:0]$7155 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\mul_op__write_cr0$10$next[0:0]$7148 $1\mul_op__write_cr0$10$next[0:0]$7160 - assign $0\mul_op__imm_data__data$4$next[63:0]$7138 $2\mul_op__imm_data__data$4$next[63:0]$7161 - assign $0\mul_op__imm_data__ok$5$next[0:0]$7139 $2\mul_op__imm_data__ok$5$next[0:0]$7162 - assign $0\mul_op__oe__oe$8$next[0:0]$7144 $2\mul_op__oe__oe$8$next[0:0]$7163 - assign $0\mul_op__oe__ok$9$next[0:0]$7145 $2\mul_op__oe__ok$9$next[0:0]$7164 - assign $0\mul_op__rc__ok$7$next[0:0]$7146 $2\mul_op__rc__ok$7$next[0:0]$7165 - assign $0\mul_op__rc__rc$6$next[0:0]$7147 $2\mul_op__rc__rc$6$next[0:0]$7166 - attribute \src "issuer_ls180.v:140545.5-140545.29" - switch \initial - attribute \src "issuer_ls180.v:140545.9-140545.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$7152 $1\mul_op__is_signed$12$next[0:0]$7155 $1\mul_op__is_32bit$11$next[0:0]$7154 $1\mul_op__write_cr0$10$next[0:0]$7160 $1\mul_op__oe__ok$9$next[0:0]$7157 $1\mul_op__oe__oe$8$next[0:0]$7156 $1\mul_op__rc__ok$7$next[0:0]$7158 $1\mul_op__rc__rc$6$next[0:0]$7159 $1\mul_op__imm_data__ok$5$next[0:0]$7151 $1\mul_op__imm_data__data$4$next[63:0]$7150 $1\mul_op__fn_unit$3$next[11:0]$7149 $1\mul_op__insn_type$2$next[6:0]$7153 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$7152 $1\mul_op__is_signed$12$next[0:0]$7155 $1\mul_op__is_32bit$11$next[0:0]$7154 $1\mul_op__write_cr0$10$next[0:0]$7160 $1\mul_op__oe__ok$9$next[0:0]$7157 $1\mul_op__oe__oe$8$next[0:0]$7156 $1\mul_op__rc__ok$7$next[0:0]$7158 $1\mul_op__rc__rc$6$next[0:0]$7159 $1\mul_op__imm_data__ok$5$next[0:0]$7151 $1\mul_op__imm_data__data$4$next[63:0]$7150 $1\mul_op__fn_unit$3$next[11:0]$7149 $1\mul_op__insn_type$2$next[6:0]$7153 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } - case - assign $1\mul_op__fn_unit$3$next[11:0]$7149 \mul_op__fn_unit$3 - assign $1\mul_op__imm_data__data$4$next[63:0]$7150 \mul_op__imm_data__data$4 - assign $1\mul_op__imm_data__ok$5$next[0:0]$7151 \mul_op__imm_data__ok$5 - assign $1\mul_op__insn$13$next[31:0]$7152 \mul_op__insn$13 - assign $1\mul_op__insn_type$2$next[6:0]$7153 \mul_op__insn_type$2 - assign $1\mul_op__is_32bit$11$next[0:0]$7154 \mul_op__is_32bit$11 - assign $1\mul_op__is_signed$12$next[0:0]$7155 \mul_op__is_signed$12 - assign $1\mul_op__oe__oe$8$next[0:0]$7156 \mul_op__oe__oe$8 - assign $1\mul_op__oe__ok$9$next[0:0]$7157 \mul_op__oe__ok$9 - assign $1\mul_op__rc__ok$7$next[0:0]$7158 \mul_op__rc__ok$7 - assign $1\mul_op__rc__rc$6$next[0:0]$7159 \mul_op__rc__rc$6 - assign $1\mul_op__write_cr0$10$next[0:0]$7160 \mul_op__write_cr0$10 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\mul_op__imm_data__data$4$next[63:0]$7161 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$5$next[0:0]$7162 1'0 - assign $2\mul_op__rc__rc$6$next[0:0]$7166 1'0 - assign $2\mul_op__rc__ok$7$next[0:0]$7165 1'0 - assign $2\mul_op__oe__oe$8$next[0:0]$7163 1'0 - assign $2\mul_op__oe__ok$9$next[0:0]$7164 1'0 - case - assign $2\mul_op__imm_data__data$4$next[63:0]$7161 $1\mul_op__imm_data__data$4$next[63:0]$7150 - assign $2\mul_op__imm_data__ok$5$next[0:0]$7162 $1\mul_op__imm_data__ok$5$next[0:0]$7151 - assign $2\mul_op__oe__oe$8$next[0:0]$7163 $1\mul_op__oe__oe$8$next[0:0]$7156 - assign $2\mul_op__oe__ok$9$next[0:0]$7164 $1\mul_op__oe__ok$9$next[0:0]$7157 - assign $2\mul_op__rc__ok$7$next[0:0]$7165 $1\mul_op__rc__ok$7$next[0:0]$7158 - assign $2\mul_op__rc__rc$6$next[0:0]$7166 $1\mul_op__rc__rc$6$next[0:0]$7159 - end - sync always - update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[11:0]$7137 - update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$7138 - update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$7139 - update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$7140 - update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$7141 - update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$7142 - update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$7143 - update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$7144 - update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$7145 - update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$7146 - update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$7147 - update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$7148 - end - attribute \src "issuer_ls180.v:140580.3-140598.6" - process $proc$issuer_ls180.v:140580$7167 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$14$next[63:0]$7169 $1\o$14$next[63:0]$7171 - assign $0\o_ok$next[0:0]$7168 $2\o_ok$next[0:0]$7172 - attribute \src "issuer_ls180.v:140581.5-140581.29" - switch \initial - attribute \src "issuer_ls180.v:140581.9-140581.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$7170 $1\o$14$next[63:0]$7171 } { \o_ok$72 \o$71 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$7170 $1\o$14$next[63:0]$7171 } { \o_ok$72 \o$71 } - case - assign $1\o_ok$next[0:0]$7170 \o_ok - assign $1\o$14$next[63:0]$7171 \o$14 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o_ok$next[0:0]$7172 1'0 - case - assign $2\o_ok$next[0:0]$7172 $1\o_ok$next[0:0]$7170 - end - sync always - update \o_ok$next $0\o_ok$next[0:0]$7168 - update \o$14$next $0\o$14$next[63:0]$7169 - end - attribute \src "issuer_ls180.v:140599.3-140617.6" - process $proc$issuer_ls180.v:140599$7173 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$next[3:0]$7174 $1\cr_a$next[3:0]$7176 - assign { } { } - assign $0\cr_a_ok$next[0:0]$7175 $2\cr_a_ok$next[0:0]$7178 - attribute \src "issuer_ls180.v:140600.5-140600.29" - switch \initial - attribute \src "issuer_ls180.v:140600.9-140600.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$7177 $1\cr_a$next[3:0]$7176 } { \cr_a_ok$74 \cr_a$73 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$7177 $1\cr_a$next[3:0]$7176 } { \cr_a_ok$74 \cr_a$73 } - case - assign $1\cr_a$next[3:0]$7176 \cr_a - assign $1\cr_a_ok$next[0:0]$7177 \cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_a_ok$next[0:0]$7178 1'0 - case - assign $2\cr_a_ok$next[0:0]$7178 $1\cr_a_ok$next[0:0]$7177 - end - sync always - update \cr_a$next $0\cr_a$next[3:0]$7174 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$7175 - end - attribute \src "issuer_ls180.v:140618.3-140636.6" - process $proc$issuer_ls180.v:140618$7179 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_ov$next[1:0]$7180 $1\xer_ov$next[1:0]$7182 - assign { } { } - assign $0\xer_ov_ok$next[0:0]$7181 $2\xer_ov_ok$next[0:0]$7184 - attribute \src "issuer_ls180.v:140619.5-140619.29" - switch \initial - attribute \src "issuer_ls180.v:140619.9-140619.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_ov_ok$next[0:0]$7183 $1\xer_ov$next[1:0]$7182 } { \xer_ov_ok$76 \xer_ov$75 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_ov_ok$next[0:0]$7183 $1\xer_ov$next[1:0]$7182 } { \xer_ov_ok$76 \xer_ov$75 } - case - assign $1\xer_ov$next[1:0]$7182 \xer_ov - assign $1\xer_ov_ok$next[0:0]$7183 \xer_ov_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_ov_ok$next[0:0]$7184 1'0 - case - assign $2\xer_ov_ok$next[0:0]$7184 $1\xer_ov_ok$next[0:0]$7183 - end - sync always - update \xer_ov$next $0\xer_ov$next[1:0]$7180 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$7181 - end - attribute \src "issuer_ls180.v:140637.3-140655.6" - process $proc$issuer_ls180.v:140637$7185 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_so$15$next[0:0]$7187 $1\xer_so$15$next[0:0]$7189 - assign $0\xer_so_ok$next[0:0]$7186 $2\xer_so_ok$next[0:0]$7190 - attribute \src "issuer_ls180.v:140638.5-140638.29" - switch \initial - attribute \src "issuer_ls180.v:140638.9-140638.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_so_ok$next[0:0]$7188 $1\xer_so$15$next[0:0]$7189 } { \xer_so_ok$78 \xer_so$77 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_so_ok$next[0:0]$7188 $1\xer_so$15$next[0:0]$7189 } { \xer_so_ok$78 \xer_so$77 } - case - assign $1\xer_so_ok$next[0:0]$7188 \xer_so_ok - assign $1\xer_so$15$next[0:0]$7189 \xer_so$15 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_so_ok$next[0:0]$7190 1'0 - case - assign $2\xer_so_ok$next[0:0]$7190 $1\xer_so_ok$next[0:0]$7188 - end - sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$7186 - update \xer_so$15$next $0\xer_so$15$next[0:0]$7187 - end - connect \$56 $and$issuer_ls180.v:140382$7091_Y - connect \cr_a$51 4'0000 - connect \cr_a_ok$52 1'0 - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \xer_so_ok$78 \xer_so$77 } { \output_xer_so_ok \output_xer_so$48 } - connect { \xer_ov_ok$76 \xer_ov$75 } { \output_xer_ov_ok \output_xer_ov$47 } - connect { \cr_a_ok$74 \cr_a$73 } { \output_cr_a_ok \output_cr_a$46 } - connect { \o_ok$72 \o$71 } { \output_o_ok$45 \output_o$44 } - connect { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } { \output_mul_op__insn$43 \output_mul_op__is_signed$42 \output_mul_op__is_32bit$41 \output_mul_op__write_cr0$40 \output_mul_op__oe__ok$39 \output_mul_op__oe__oe$38 \output_mul_op__rc__ok$37 \output_mul_op__rc__rc$36 \output_mul_op__imm_data__ok$35 \output_mul_op__imm_data__data$34 \output_mul_op__fn_unit$33 \output_mul_op__insn_type$32 } - connect \muxid$58 \output_muxid$31 - connect \p_valid_i_p_ready_o \$56 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$55 \p_valid_i - connect { \xer_so_ok$54 \output_xer_so } { \mul3_xer_so_ok \mul3_xer_so$30 } - connect { \xer_ov_ok$53 \output_xer_ov } { \mul3_xer_ov_ok \mul3_xer_ov } - connect { \cr_a_ok$50 \output_cr_a } 5'00000 - connect { \output_o_ok \output_o } { \mul3_o_ok \mul3_o$29 } - connect { \output_mul_op__insn \output_mul_op__is_signed \output_mul_op__is_32bit \output_mul_op__write_cr0 \output_mul_op__oe__ok \output_mul_op__oe__oe \output_mul_op__rc__ok \output_mul_op__rc__rc \output_mul_op__imm_data__ok \output_mul_op__imm_data__data \output_mul_op__fn_unit \output_mul_op__insn_type } { \mul3_mul_op__insn$28 \mul3_mul_op__is_signed$27 \mul3_mul_op__is_32bit$26 \mul3_mul_op__write_cr0$25 \mul3_mul_op__oe__ok$24 \mul3_mul_op__oe__oe$23 \mul3_mul_op__rc__ok$22 \mul3_mul_op__rc__rc$21 \mul3_mul_op__imm_data__ok$20 \mul3_mul_op__imm_data__data$19 \mul3_mul_op__fn_unit$18 \mul3_mul_op__insn_type$17 } - connect \output_muxid \mul3_muxid$16 - connect \neg_res32$49 \neg_res32 - connect \mul3_neg_res \neg_res - connect \mul3_xer_so \xer_so - connect \mul3_o \o - connect { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__oe__ok \mul3_mul_op__oe__oe \mul3_mul_op__rc__ok \mul3_mul_op__rc__rc \mul3_mul_op__imm_data__ok \mul3_mul_op__imm_data__data \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } - connect \mul3_muxid \muxid -end -attribute \src "issuer_ls180.v:140685.1-140696.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.n" -attribute \generator "nMigen" -module \n - attribute \src "issuer_ls180.v:140694.17-140694.111" - wire $and$issuer_ls180.v:140694$7229_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:140694$7229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:140694$7229_Y - end - connect \$1 $and$issuer_ls180.v:140694$7229_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:140700.1-140711.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.n" -attribute \generator "nMigen" -module \n$106 - attribute \src "issuer_ls180.v:140709.17-140709.111" - wire $and$issuer_ls180.v:140709$7230_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:140709$7230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:140709$7230_Y - end - connect \$1 $and$issuer_ls180.v:140709$7230_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:140715.1-140726.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.n" -attribute \generator "nMigen" -module \n$109 - attribute \src "issuer_ls180.v:140724.17-140724.111" - wire $and$issuer_ls180.v:140724$7231_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:140724$7231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:140724$7231_Y - end - connect \$1 $and$issuer_ls180.v:140724$7231_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:140730.1-140741.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2.n" -attribute \generator "nMigen" -module \n$114 - attribute \src "issuer_ls180.v:140739.17-140739.111" - wire $and$issuer_ls180.v:140739$7232_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:140739$7232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:140739$7232_Y - end - connect \$1 $and$issuer_ls180.v:140739$7232_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:140745.1-140756.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.n" -attribute \generator "nMigen" -module \n$18 - attribute \src "issuer_ls180.v:140754.17-140754.111" - wire $and$issuer_ls180.v:140754$7233_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:140754$7233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:140754$7233_Y - end - connect \$1 $and$issuer_ls180.v:140754$7233_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:140760.1-140771.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1.n" -attribute \generator "nMigen" -module \n$2 - attribute \src "issuer_ls180.v:140769.17-140769.111" - wire $and$issuer_ls180.v:140769$7234_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:140769$7234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:140769$7234_Y - end - connect \$1 $and$issuer_ls180.v:140769$7234_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:140775.1-140786.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.n" -attribute \generator "nMigen" -module \n$21 - attribute \src "issuer_ls180.v:140784.17-140784.111" - wire $and$issuer_ls180.v:140784$7235_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:140784$7235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:140784$7235_Y - end - connect \$1 $and$issuer_ls180.v:140784$7235_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:140790.1-140801.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.n" -attribute \generator "nMigen" -module \n$31 - attribute \src "issuer_ls180.v:140799.17-140799.111" - wire $and$issuer_ls180.v:140799$7236_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:140799$7236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:140799$7236_Y - end - connect \$1 $and$issuer_ls180.v:140799$7236_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:140805.1-140816.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.n" -attribute \generator "nMigen" -module \n$34 - attribute \src "issuer_ls180.v:140814.17-140814.111" - wire $and$issuer_ls180.v:140814$7237_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:140814$7237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:140814$7237_Y - end - connect \$1 $and$issuer_ls180.v:140814$7237_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:140820.1-140831.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe2.n" -attribute \generator "nMigen" -module \n$4 - attribute \src "issuer_ls180.v:140829.17-140829.111" - wire $and$issuer_ls180.v:140829$7238_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:140829$7238 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:140829$7238_Y - end - connect \$1 $and$issuer_ls180.v:140829$7238_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:140835.1-140846.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.n" -attribute \generator "nMigen" -module \n$44 - attribute \src "issuer_ls180.v:140844.17-140844.111" - wire $and$issuer_ls180.v:140844$7239_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:140844$7239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:140844$7239_Y - end - connect \$1 $and$issuer_ls180.v:140844$7239_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:140850.1-140861.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.n" -attribute \generator "nMigen" -module \n$46 - attribute \src "issuer_ls180.v:140859.17-140859.111" - wire $and$issuer_ls180.v:140859$7240_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:140859$7240 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:140859$7240_Y - end - connect \$1 $and$issuer_ls180.v:140859$7240_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:140865.1-140876.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe2.n" -attribute \generator "nMigen" -module \n$50 - attribute \src "issuer_ls180.v:140874.17-140874.111" - wire $and$issuer_ls180.v:140874$7241_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:140874$7241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:140874$7241_Y - end - connect \$1 $and$issuer_ls180.v:140874$7241_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:140880.1-140891.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.n" -attribute \generator "nMigen" -module \n$6 - attribute \src "issuer_ls180.v:140889.17-140889.111" - wire $and$issuer_ls180.v:140889$7242_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:140889$7242 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:140889$7242_Y - end - connect \$1 $and$issuer_ls180.v:140889$7242_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:140895.1-140906.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.n" -attribute \generator "nMigen" -module \n$60 - attribute \src "issuer_ls180.v:140904.17-140904.111" - wire $and$issuer_ls180.v:140904$7243_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:140904$7243 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:140904$7243_Y - end - connect \$1 $and$issuer_ls180.v:140904$7243_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:140910.1-140921.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.n" -attribute \generator "nMigen" -module \n$63 - attribute \src "issuer_ls180.v:140919.17-140919.111" - wire $and$issuer_ls180.v:140919$7244_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:140919$7244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:140919$7244_Y - end - connect \$1 $and$issuer_ls180.v:140919$7244_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:140925.1-140936.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.n" -attribute \generator "nMigen" -module \n$72 - attribute \src "issuer_ls180.v:140934.17-140934.111" - wire $and$issuer_ls180.v:140934$7245_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:140934$7245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:140934$7245_Y - end - connect \$1 $and$issuer_ls180.v:140934$7245_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:140940.1-140951.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.n" -attribute \generator "nMigen" -module \n$74 - attribute \src "issuer_ls180.v:140949.17-140949.111" - wire $and$issuer_ls180.v:140949$7246_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:140949$7246 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:140949$7246_Y - end - connect \$1 $and$issuer_ls180.v:140949$7246_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:140955.1-140966.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.n" -attribute \generator "nMigen" -module \n$77 - attribute \src "issuer_ls180.v:140964.17-140964.111" - wire $and$issuer_ls180.v:140964$7247_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:140964$7247 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:140964$7247_Y - end - connect \$1 $and$issuer_ls180.v:140964$7247_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:140970.1-140981.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.n" -attribute \generator "nMigen" -module \n$79 - attribute \src "issuer_ls180.v:140979.17-140979.111" - wire $and$issuer_ls180.v:140979$7248_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:140979$7248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:140979$7248_Y - end - connect \$1 $and$issuer_ls180.v:140979$7248_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:140985.1-140996.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.n" -attribute \generator "nMigen" -module \n$8 - attribute \src "issuer_ls180.v:140994.17-140994.111" - wire $and$issuer_ls180.v:140994$7249_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:140994$7249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:140994$7249_Y - end - connect \$1 $and$issuer_ls180.v:140994$7249_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:141000.1-141011.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.n" -attribute \generator "nMigen" -module \n$89 - attribute \src "issuer_ls180.v:141009.17-141009.111" - wire $and$issuer_ls180.v:141009$7250_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:141009$7250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:141009$7250_Y - end - connect \$1 $and$issuer_ls180.v:141009$7250_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:141015.1-141026.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.n" -attribute \generator "nMigen" -module \n$91 - attribute \src "issuer_ls180.v:141024.17-141024.111" - wire $and$issuer_ls180.v:141024$7251_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:141024$7251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:141024$7251_Y - end - connect \$1 $and$issuer_ls180.v:141024$7251_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:141030.1-141041.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.n" -attribute \generator "nMigen" -module \n$94 - attribute \src "issuer_ls180.v:141039.17-141039.111" - wire $and$issuer_ls180.v:141039$7252_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:141039$7252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:141039$7252_Y - end - connect \$1 $and$issuer_ls180.v:141039$7252_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:141045.1-141056.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.n" -attribute \generator "nMigen" -module \n$96 - attribute \src "issuer_ls180.v:141054.17-141054.111" - wire $and$issuer_ls180.v:141054$7253_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$issuer_ls180.v:141054$7253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:141054$7253_Y - end - connect \$1 $and$issuer_ls180.v:141054$7253_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:141060.1-141118.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.opc_l" -attribute \generator "nMigen" -module \opc_l - attribute \src "issuer_ls180.v:141061.7-141061.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:141106.3-141114.6" - wire $0\q_int$next[0:0]$7264 - attribute \src "issuer_ls180.v:141104.3-141105.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:141106.3-141114.6" - wire $1\q_int$next[0:0]$7265 - attribute \src "issuer_ls180.v:141083.7-141083.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:141096.17-141096.96" - wire $and$issuer_ls180.v:141096$7254_Y - attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:141096$7254 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:141096$7254_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:141101$7259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:141101$7259_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:141098$7256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$issuer_ls180.v:141098$7256_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:141100$7258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$issuer_ls180.v:141100$7258_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:141103$7261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$issuer_ls180.v:141103$7261_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:141097$7255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$issuer_ls180.v:141097$7255_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:141099$7257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$issuer_ls180.v:141099$7257_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:141102$7260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$issuer_ls180.v:141102$7260_Y - end - attribute \src "issuer_ls180.v:141061.7-141061.20" - process $proc$issuer_ls180.v:141061$7266 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:141083.7-141083.19" - process $proc$issuer_ls180.v:141083$7267 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:141104.3-141105.27" - process $proc$issuer_ls180.v:141104$7262 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:141106.3-141114.6" - process $proc$issuer_ls180.v:141106$7263 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$7264 $1\q_int$next[0:0]$7265 - attribute \src "issuer_ls180.v:141107.5-141107.29" - switch \initial - attribute \src "issuer_ls180.v:141107.9-141107.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$7265 1'0 - case - assign $1\q_int$next[0:0]$7265 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$7264 - end - connect \$9 $and$issuer_ls180.v:141096$7254_Y - connect \$11 $or$issuer_ls180.v:141097$7255_Y - connect \$13 $not$issuer_ls180.v:141098$7256_Y - connect \$15 $or$issuer_ls180.v:141099$7257_Y - connect \$1 $not$issuer_ls180.v:141100$7258_Y - connect \$3 $and$issuer_ls180.v:141101$7259_Y - connect \$5 $or$issuer_ls180.v:141102$7260_Y - connect \$7 $not$issuer_ls180.v:141103$7261_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "issuer_ls180.v:141122.1-141180.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.opc_l" -attribute \generator "nMigen" -module \opc_l$11 - attribute \src "issuer_ls180.v:141123.7-141123.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:141168.3-141176.6" - wire $0\q_int$next[0:0]$7278 - attribute \src "issuer_ls180.v:141166.3-141167.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:141168.3-141176.6" - wire $1\q_int$next[0:0]$7279 - attribute \src "issuer_ls180.v:141145.7-141145.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:141158.17-141158.96" - wire $and$issuer_ls180.v:141158$7268_Y - attribute \src "issuer_ls180.v:141163.17-141163.96" - wire $and$issuer_ls180.v:141163$7273_Y - attribute \src "issuer_ls180.v:141160.18-141160.93" - wire $not$issuer_ls180.v:141160$7270_Y - attribute \src "issuer_ls180.v:141162.17-141162.92" - wire $not$issuer_ls180.v:141162$7272_Y - attribute \src "issuer_ls180.v:141165.17-141165.92" - wire $not$issuer_ls180.v:141165$7275_Y - attribute \src "issuer_ls180.v:141159.18-141159.98" - wire $or$issuer_ls180.v:141159$7269_Y - attribute \src "issuer_ls180.v:141161.18-141161.99" - wire $or$issuer_ls180.v:141161$7271_Y - attribute \src "issuer_ls180.v:141164.17-141164.97" - wire $or$issuer_ls180.v:141164$7274_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:141123.7-141123.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:141158$7268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:141158$7268_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:141163$7273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:141163$7273_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:141160$7270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$issuer_ls180.v:141160$7270_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:141162$7272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$issuer_ls180.v:141162$7272_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:141165$7275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$issuer_ls180.v:141165$7275_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:141159$7269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$issuer_ls180.v:141159$7269_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:141161$7271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$issuer_ls180.v:141161$7271_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:141164$7274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$issuer_ls180.v:141164$7274_Y - end - attribute \src "issuer_ls180.v:141123.7-141123.20" - process $proc$issuer_ls180.v:141123$7280 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:141145.7-141145.19" - process $proc$issuer_ls180.v:141145$7281 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:141166.3-141167.27" - process $proc$issuer_ls180.v:141166$7276 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:141168.3-141176.6" - process $proc$issuer_ls180.v:141168$7277 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$7278 $1\q_int$next[0:0]$7279 - attribute \src "issuer_ls180.v:141169.5-141169.29" - switch \initial - attribute \src "issuer_ls180.v:141169.9-141169.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$7279 1'0 - case - assign $1\q_int$next[0:0]$7279 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$7278 - end - connect \$9 $and$issuer_ls180.v:141158$7268_Y - connect \$11 $or$issuer_ls180.v:141159$7269_Y - connect \$13 $not$issuer_ls180.v:141160$7270_Y - connect \$15 $or$issuer_ls180.v:141161$7271_Y - connect \$1 $not$issuer_ls180.v:141162$7272_Y - connect \$3 $and$issuer_ls180.v:141163$7273_Y - connect \$5 $or$issuer_ls180.v:141164$7274_Y - connect \$7 $not$issuer_ls180.v:141165$7275_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "issuer_ls180.v:141184.1-141242.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.opc_l" -attribute \generator "nMigen" -module \opc_l$117 - attribute \src "issuer_ls180.v:141185.7-141185.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:141230.3-141238.6" - wire $0\q_int$next[0:0]$7292 - attribute \src "issuer_ls180.v:141228.3-141229.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:141230.3-141238.6" - wire $1\q_int$next[0:0]$7293 - attribute \src "issuer_ls180.v:141207.7-141207.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:141220.17-141220.96" - wire $and$issuer_ls180.v:141220$7282_Y - attribute \src "issuer_ls180.v:141225.17-141225.96" - wire $and$issuer_ls180.v:141225$7287_Y - attribute \src "issuer_ls180.v:141222.18-141222.93" - wire $not$issuer_ls180.v:141222$7284_Y - attribute \src "issuer_ls180.v:141224.17-141224.92" - wire $not$issuer_ls180.v:141224$7286_Y - attribute \src "issuer_ls180.v:141227.17-141227.92" - wire $not$issuer_ls180.v:141227$7289_Y - attribute \src "issuer_ls180.v:141221.18-141221.98" - wire $or$issuer_ls180.v:141221$7283_Y - attribute \src "issuer_ls180.v:141223.18-141223.99" - wire $or$issuer_ls180.v:141223$7285_Y - attribute \src "issuer_ls180.v:141226.17-141226.97" - wire $or$issuer_ls180.v:141226$7288_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:141185.7-141185.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:141220$7282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:141220$7282_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:141225$7287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:141225$7287_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:141222$7284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$issuer_ls180.v:141222$7284_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:141224$7286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$issuer_ls180.v:141224$7286_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:141227$7289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$issuer_ls180.v:141227$7289_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:141221$7283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$issuer_ls180.v:141221$7283_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:141223$7285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$issuer_ls180.v:141223$7285_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:141226$7288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$issuer_ls180.v:141226$7288_Y - end - attribute \src "issuer_ls180.v:141185.7-141185.20" - process $proc$issuer_ls180.v:141185$7294 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:141207.7-141207.19" - process $proc$issuer_ls180.v:141207$7295 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:141228.3-141229.27" - process $proc$issuer_ls180.v:141228$7290 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:141230.3-141238.6" - process $proc$issuer_ls180.v:141230$7291 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$7292 $1\q_int$next[0:0]$7293 - attribute \src "issuer_ls180.v:141231.5-141231.29" - switch \initial - attribute \src "issuer_ls180.v:141231.9-141231.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$7293 1'0 - case - assign $1\q_int$next[0:0]$7293 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$7292 - end - connect \$9 $and$issuer_ls180.v:141220$7282_Y - connect \$11 $or$issuer_ls180.v:141221$7283_Y - connect \$13 $not$issuer_ls180.v:141222$7284_Y - connect \$15 $or$issuer_ls180.v:141223$7285_Y - connect \$1 $not$issuer_ls180.v:141224$7286_Y - connect \$3 $and$issuer_ls180.v:141225$7287_Y - connect \$5 $or$issuer_ls180.v:141226$7288_Y - connect \$7 $not$issuer_ls180.v:141227$7289_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "issuer_ls180.v:141246.1-141304.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.opc_l" -attribute \generator "nMigen" -module \opc_l$123 - attribute \src "issuer_ls180.v:141247.7-141247.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:141292.3-141300.6" - wire $0\q_int$next[0:0]$7306 - attribute \src "issuer_ls180.v:141290.3-141291.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:141292.3-141300.6" - wire $1\q_int$next[0:0]$7307 - attribute \src "issuer_ls180.v:141269.7-141269.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:141282.17-141282.96" - wire $and$issuer_ls180.v:141282$7296_Y - attribute \src "issuer_ls180.v:141287.17-141287.96" - wire $and$issuer_ls180.v:141287$7301_Y - attribute \src "issuer_ls180.v:141284.18-141284.93" - wire $not$issuer_ls180.v:141284$7298_Y - attribute \src "issuer_ls180.v:141286.17-141286.92" - wire $not$issuer_ls180.v:141286$7300_Y - attribute \src "issuer_ls180.v:141289.17-141289.92" - wire $not$issuer_ls180.v:141289$7303_Y - attribute \src "issuer_ls180.v:141283.18-141283.98" - wire $or$issuer_ls180.v:141283$7297_Y - attribute \src "issuer_ls180.v:141285.18-141285.99" - wire $or$issuer_ls180.v:141285$7299_Y - attribute \src "issuer_ls180.v:141288.17-141288.97" - wire $or$issuer_ls180.v:141288$7302_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:141247.7-141247.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:141282$7296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:141282$7296_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:141287$7301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:141287$7301_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:141284$7298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$issuer_ls180.v:141284$7298_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:141286$7300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$issuer_ls180.v:141286$7300_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:141289$7303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$issuer_ls180.v:141289$7303_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:141283$7297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$issuer_ls180.v:141283$7297_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:141285$7299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$issuer_ls180.v:141285$7299_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:141288$7302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$issuer_ls180.v:141288$7302_Y - end - attribute \src "issuer_ls180.v:141247.7-141247.20" - process $proc$issuer_ls180.v:141247$7308 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:141269.7-141269.19" - process $proc$issuer_ls180.v:141269$7309 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:141290.3-141291.27" - process $proc$issuer_ls180.v:141290$7304 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:141292.3-141300.6" - process $proc$issuer_ls180.v:141292$7305 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$7306 $1\q_int$next[0:0]$7307 - attribute \src "issuer_ls180.v:141293.5-141293.29" - switch \initial - attribute \src "issuer_ls180.v:141293.9-141293.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$7307 1'0 - case - assign $1\q_int$next[0:0]$7307 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$7306 - end - connect \$9 $and$issuer_ls180.v:141282$7296_Y - connect \$11 $or$issuer_ls180.v:141283$7297_Y - connect \$13 $not$issuer_ls180.v:141284$7298_Y - connect \$15 $or$issuer_ls180.v:141285$7299_Y - connect \$1 $not$issuer_ls180.v:141286$7300_Y - connect \$3 $and$issuer_ls180.v:141287$7301_Y - connect \$5 $or$issuer_ls180.v:141288$7302_Y - connect \$7 $not$issuer_ls180.v:141289$7303_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "issuer_ls180.v:141308.1-141366.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.opc_l" -attribute \generator "nMigen" -module \opc_l$24 - attribute \src "issuer_ls180.v:141309.7-141309.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:141354.3-141362.6" - wire $0\q_int$next[0:0]$7320 - attribute \src "issuer_ls180.v:141352.3-141353.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:141354.3-141362.6" - wire $1\q_int$next[0:0]$7321 - attribute \src "issuer_ls180.v:141331.7-141331.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:141344.17-141344.96" - wire $and$issuer_ls180.v:141344$7310_Y - attribute \src "issuer_ls180.v:141349.17-141349.96" - wire $and$issuer_ls180.v:141349$7315_Y - attribute \src "issuer_ls180.v:141346.18-141346.93" - wire $not$issuer_ls180.v:141346$7312_Y - attribute \src "issuer_ls180.v:141348.17-141348.92" - wire $not$issuer_ls180.v:141348$7314_Y - attribute \src "issuer_ls180.v:141351.17-141351.92" - wire $not$issuer_ls180.v:141351$7317_Y - attribute \src "issuer_ls180.v:141345.18-141345.98" - wire $or$issuer_ls180.v:141345$7311_Y - attribute \src "issuer_ls180.v:141347.18-141347.99" - wire $or$issuer_ls180.v:141347$7313_Y - attribute \src "issuer_ls180.v:141350.17-141350.97" - wire $or$issuer_ls180.v:141350$7316_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:141309.7-141309.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:141344$7310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:141344$7310_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:141349$7315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:141349$7315_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:141346$7312 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$issuer_ls180.v:141346$7312_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:141348$7314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$issuer_ls180.v:141348$7314_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:141351$7317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$issuer_ls180.v:141351$7317_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:141345$7311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$issuer_ls180.v:141345$7311_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:141347$7313 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$issuer_ls180.v:141347$7313_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:141350$7316 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$issuer_ls180.v:141350$7316_Y - end - attribute \src "issuer_ls180.v:141309.7-141309.20" - process $proc$issuer_ls180.v:141309$7322 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:141331.7-141331.19" - process $proc$issuer_ls180.v:141331$7323 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:141352.3-141353.27" - process $proc$issuer_ls180.v:141352$7318 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:141354.3-141362.6" - process $proc$issuer_ls180.v:141354$7319 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$7320 $1\q_int$next[0:0]$7321 - attribute \src "issuer_ls180.v:141355.5-141355.29" - switch \initial - attribute \src "issuer_ls180.v:141355.9-141355.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$7321 1'0 - case - assign $1\q_int$next[0:0]$7321 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$7320 - end - connect \$9 $and$issuer_ls180.v:141344$7310_Y - connect \$11 $or$issuer_ls180.v:141345$7311_Y - connect \$13 $not$issuer_ls180.v:141346$7312_Y - connect \$15 $or$issuer_ls180.v:141347$7313_Y - connect \$1 $not$issuer_ls180.v:141348$7314_Y - connect \$3 $and$issuer_ls180.v:141349$7315_Y - connect \$5 $or$issuer_ls180.v:141350$7316_Y - connect \$7 $not$issuer_ls180.v:141351$7317_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "issuer_ls180.v:141370.1-141428.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.opc_l" -attribute \generator "nMigen" -module \opc_l$37 - attribute \src "issuer_ls180.v:141371.7-141371.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:141416.3-141424.6" - wire $0\q_int$next[0:0]$7334 - attribute \src "issuer_ls180.v:141414.3-141415.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:141416.3-141424.6" - wire $1\q_int$next[0:0]$7335 - attribute \src "issuer_ls180.v:141393.7-141393.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:141406.17-141406.96" - wire $and$issuer_ls180.v:141406$7324_Y - attribute \src "issuer_ls180.v:141411.17-141411.96" - wire $and$issuer_ls180.v:141411$7329_Y - attribute \src "issuer_ls180.v:141408.18-141408.93" - wire $not$issuer_ls180.v:141408$7326_Y - attribute \src "issuer_ls180.v:141410.17-141410.92" - wire $not$issuer_ls180.v:141410$7328_Y - attribute \src "issuer_ls180.v:141413.17-141413.92" - wire $not$issuer_ls180.v:141413$7331_Y - attribute \src "issuer_ls180.v:141407.18-141407.98" - wire $or$issuer_ls180.v:141407$7325_Y - attribute \src "issuer_ls180.v:141409.18-141409.99" - wire $or$issuer_ls180.v:141409$7327_Y - attribute \src "issuer_ls180.v:141412.17-141412.97" - wire $or$issuer_ls180.v:141412$7330_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:141371.7-141371.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:141406$7324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:141406$7324_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:141411$7329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:141411$7329_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:141408$7326 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$issuer_ls180.v:141408$7326_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:141410$7328 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$issuer_ls180.v:141410$7328_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:141413$7331 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$issuer_ls180.v:141413$7331_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:141407$7325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$issuer_ls180.v:141407$7325_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:141409$7327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$issuer_ls180.v:141409$7327_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:141412$7330 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$issuer_ls180.v:141412$7330_Y - end - attribute \src "issuer_ls180.v:141371.7-141371.20" - process $proc$issuer_ls180.v:141371$7336 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:141393.7-141393.19" - process $proc$issuer_ls180.v:141393$7337 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:141414.3-141415.27" - process $proc$issuer_ls180.v:141414$7332 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:141416.3-141424.6" - process $proc$issuer_ls180.v:141416$7333 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$7334 $1\q_int$next[0:0]$7335 - attribute \src "issuer_ls180.v:141417.5-141417.29" - switch \initial - attribute \src "issuer_ls180.v:141417.9-141417.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$7335 1'0 - case - assign $1\q_int$next[0:0]$7335 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$7334 - end - connect \$9 $and$issuer_ls180.v:141406$7324_Y - connect \$11 $or$issuer_ls180.v:141407$7325_Y - connect \$13 $not$issuer_ls180.v:141408$7326_Y - connect \$15 $or$issuer_ls180.v:141409$7327_Y - connect \$1 $not$issuer_ls180.v:141410$7328_Y - connect \$3 $and$issuer_ls180.v:141411$7329_Y - connect \$5 $or$issuer_ls180.v:141412$7330_Y - connect \$7 $not$issuer_ls180.v:141413$7331_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "issuer_ls180.v:141432.1-141490.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.opc_l" -attribute \generator "nMigen" -module \opc_l$53 - attribute \src "issuer_ls180.v:141433.7-141433.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:141478.3-141486.6" - wire $0\q_int$next[0:0]$7348 - attribute \src "issuer_ls180.v:141476.3-141477.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:141478.3-141486.6" - wire $1\q_int$next[0:0]$7349 - attribute \src "issuer_ls180.v:141455.7-141455.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:141468.17-141468.96" - wire $and$issuer_ls180.v:141468$7338_Y - attribute \src "issuer_ls180.v:141473.17-141473.96" - wire $and$issuer_ls180.v:141473$7343_Y - attribute \src "issuer_ls180.v:141470.18-141470.93" - wire $not$issuer_ls180.v:141470$7340_Y - attribute \src "issuer_ls180.v:141472.17-141472.92" - wire $not$issuer_ls180.v:141472$7342_Y - attribute \src "issuer_ls180.v:141475.17-141475.92" - wire $not$issuer_ls180.v:141475$7345_Y - attribute \src "issuer_ls180.v:141469.18-141469.98" - wire $or$issuer_ls180.v:141469$7339_Y - attribute \src "issuer_ls180.v:141471.18-141471.99" - wire $or$issuer_ls180.v:141471$7341_Y - attribute \src "issuer_ls180.v:141474.17-141474.97" - wire $or$issuer_ls180.v:141474$7344_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:141433.7-141433.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:141468$7338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:141468$7338_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:141473$7343 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:141473$7343_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:141470$7340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$issuer_ls180.v:141470$7340_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:141472$7342 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$issuer_ls180.v:141472$7342_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:141475$7345 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$issuer_ls180.v:141475$7345_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:141469$7339 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$issuer_ls180.v:141469$7339_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:141471$7341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$issuer_ls180.v:141471$7341_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:141474$7344 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$issuer_ls180.v:141474$7344_Y - end - attribute \src "issuer_ls180.v:141433.7-141433.20" - process $proc$issuer_ls180.v:141433$7350 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:141455.7-141455.19" - process $proc$issuer_ls180.v:141455$7351 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:141476.3-141477.27" - process $proc$issuer_ls180.v:141476$7346 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:141478.3-141486.6" - process $proc$issuer_ls180.v:141478$7347 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$7348 $1\q_int$next[0:0]$7349 - attribute \src "issuer_ls180.v:141479.5-141479.29" - switch \initial - attribute \src "issuer_ls180.v:141479.9-141479.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$7349 1'0 - case - assign $1\q_int$next[0:0]$7349 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$7348 - end - connect \$9 $and$issuer_ls180.v:141468$7338_Y - connect \$11 $or$issuer_ls180.v:141469$7339_Y - connect \$13 $not$issuer_ls180.v:141470$7340_Y - connect \$15 $or$issuer_ls180.v:141471$7341_Y - connect \$1 $not$issuer_ls180.v:141472$7342_Y - connect \$3 $and$issuer_ls180.v:141473$7343_Y - connect \$5 $or$issuer_ls180.v:141474$7344_Y - connect \$7 $not$issuer_ls180.v:141475$7345_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "issuer_ls180.v:141494.1-141552.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.opc_l" -attribute \generator "nMigen" -module \opc_l$65 - attribute \src "issuer_ls180.v:141495.7-141495.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:141540.3-141548.6" - wire $0\q_int$next[0:0]$7362 - attribute \src "issuer_ls180.v:141538.3-141539.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:141540.3-141548.6" - wire $1\q_int$next[0:0]$7363 - attribute \src "issuer_ls180.v:141517.7-141517.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:141530.17-141530.96" - wire $and$issuer_ls180.v:141530$7352_Y - attribute \src "issuer_ls180.v:141535.17-141535.96" - wire $and$issuer_ls180.v:141535$7357_Y - attribute \src "issuer_ls180.v:141532.18-141532.93" - wire $not$issuer_ls180.v:141532$7354_Y - attribute \src "issuer_ls180.v:141534.17-141534.92" - wire $not$issuer_ls180.v:141534$7356_Y - attribute \src "issuer_ls180.v:141537.17-141537.92" - wire $not$issuer_ls180.v:141537$7359_Y - attribute \src "issuer_ls180.v:141531.18-141531.98" - wire $or$issuer_ls180.v:141531$7353_Y - attribute \src "issuer_ls180.v:141533.18-141533.99" - wire $or$issuer_ls180.v:141533$7355_Y - attribute \src "issuer_ls180.v:141536.17-141536.97" - wire $or$issuer_ls180.v:141536$7358_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:141495.7-141495.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:141530$7352 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:141530$7352_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:141535$7357 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:141535$7357_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:141532$7354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$issuer_ls180.v:141532$7354_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:141534$7356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$issuer_ls180.v:141534$7356_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:141537$7359 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$issuer_ls180.v:141537$7359_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:141531$7353 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$issuer_ls180.v:141531$7353_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:141533$7355 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$issuer_ls180.v:141533$7355_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:141536$7358 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$issuer_ls180.v:141536$7358_Y - end - attribute \src "issuer_ls180.v:141495.7-141495.20" - process $proc$issuer_ls180.v:141495$7364 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:141517.7-141517.19" - process $proc$issuer_ls180.v:141517$7365 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:141538.3-141539.27" - process $proc$issuer_ls180.v:141538$7360 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:141540.3-141548.6" - process $proc$issuer_ls180.v:141540$7361 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$7362 $1\q_int$next[0:0]$7363 - attribute \src "issuer_ls180.v:141541.5-141541.29" - switch \initial - attribute \src "issuer_ls180.v:141541.9-141541.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$7363 1'0 - case - assign $1\q_int$next[0:0]$7363 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$7362 - end - connect \$9 $and$issuer_ls180.v:141530$7352_Y - connect \$11 $or$issuer_ls180.v:141531$7353_Y - connect \$13 $not$issuer_ls180.v:141532$7354_Y - connect \$15 $or$issuer_ls180.v:141533$7355_Y - connect \$1 $not$issuer_ls180.v:141534$7356_Y - connect \$3 $and$issuer_ls180.v:141535$7357_Y - connect \$5 $or$issuer_ls180.v:141536$7358_Y - connect \$7 $not$issuer_ls180.v:141537$7359_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "issuer_ls180.v:141556.1-141614.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.opc_l" -attribute \generator "nMigen" -module \opc_l$82 - attribute \src "issuer_ls180.v:141557.7-141557.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:141602.3-141610.6" - wire $0\q_int$next[0:0]$7376 - attribute \src "issuer_ls180.v:141600.3-141601.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:141602.3-141610.6" - wire $1\q_int$next[0:0]$7377 - attribute \src "issuer_ls180.v:141579.7-141579.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:141592.17-141592.96" - wire $and$issuer_ls180.v:141592$7366_Y - attribute \src "issuer_ls180.v:141597.17-141597.96" - wire $and$issuer_ls180.v:141597$7371_Y - attribute \src "issuer_ls180.v:141594.18-141594.93" - wire $not$issuer_ls180.v:141594$7368_Y - attribute \src "issuer_ls180.v:141596.17-141596.92" - wire $not$issuer_ls180.v:141596$7370_Y - attribute \src "issuer_ls180.v:141599.17-141599.92" - wire $not$issuer_ls180.v:141599$7373_Y - attribute \src "issuer_ls180.v:141593.18-141593.98" - wire $or$issuer_ls180.v:141593$7367_Y - attribute \src "issuer_ls180.v:141595.18-141595.99" - wire $or$issuer_ls180.v:141595$7369_Y - attribute \src "issuer_ls180.v:141598.17-141598.97" - wire $or$issuer_ls180.v:141598$7372_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:141557.7-141557.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:141592$7366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:141592$7366_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:141597$7371 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:141597$7371_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:141594$7368 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$issuer_ls180.v:141594$7368_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:141596$7370 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$issuer_ls180.v:141596$7370_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:141599$7373 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$issuer_ls180.v:141599$7373_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:141593$7367 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$issuer_ls180.v:141593$7367_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:141595$7369 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$issuer_ls180.v:141595$7369_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:141598$7372 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$issuer_ls180.v:141598$7372_Y - end - attribute \src "issuer_ls180.v:141557.7-141557.20" - process $proc$issuer_ls180.v:141557$7378 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:141579.7-141579.19" - process $proc$issuer_ls180.v:141579$7379 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:141600.3-141601.27" - process $proc$issuer_ls180.v:141600$7374 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:141602.3-141610.6" - process $proc$issuer_ls180.v:141602$7375 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$7376 $1\q_int$next[0:0]$7377 - attribute \src "issuer_ls180.v:141603.5-141603.29" - switch \initial - attribute \src "issuer_ls180.v:141603.9-141603.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$7377 1'0 - case - assign $1\q_int$next[0:0]$7377 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$7376 - end - connect \$9 $and$issuer_ls180.v:141592$7366_Y - connect \$11 $or$issuer_ls180.v:141593$7367_Y - connect \$13 $not$issuer_ls180.v:141594$7368_Y - connect \$15 $or$issuer_ls180.v:141595$7369_Y - connect \$1 $not$issuer_ls180.v:141596$7370_Y - connect \$3 $and$issuer_ls180.v:141597$7371_Y - connect \$5 $or$issuer_ls180.v:141598$7372_Y - connect \$7 $not$issuer_ls180.v:141599$7373_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "issuer_ls180.v:141618.1-141676.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.opc_l" -attribute \generator "nMigen" -module \opc_l$99 - attribute \src "issuer_ls180.v:141619.7-141619.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:141664.3-141672.6" - wire $0\q_int$next[0:0]$7390 - attribute \src "issuer_ls180.v:141662.3-141663.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:141664.3-141672.6" - wire $1\q_int$next[0:0]$7391 - attribute \src "issuer_ls180.v:141641.7-141641.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:141654.17-141654.96" - wire $and$issuer_ls180.v:141654$7380_Y - attribute \src "issuer_ls180.v:141659.17-141659.96" - wire $and$issuer_ls180.v:141659$7385_Y - attribute \src "issuer_ls180.v:141656.18-141656.93" - wire $not$issuer_ls180.v:141656$7382_Y - attribute \src "issuer_ls180.v:141658.17-141658.92" - wire $not$issuer_ls180.v:141658$7384_Y - attribute \src "issuer_ls180.v:141661.17-141661.92" - wire $not$issuer_ls180.v:141661$7387_Y - attribute \src "issuer_ls180.v:141655.18-141655.98" - wire $or$issuer_ls180.v:141655$7381_Y - attribute \src "issuer_ls180.v:141657.18-141657.99" - wire $or$issuer_ls180.v:141657$7383_Y - attribute \src "issuer_ls180.v:141660.17-141660.97" - wire $or$issuer_ls180.v:141660$7386_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:141619.7-141619.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:141654$7380 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:141654$7380_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:141659$7385 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:141659$7385_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:141656$7382 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$issuer_ls180.v:141656$7382_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:141658$7384 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$issuer_ls180.v:141658$7384_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:141661$7387 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$issuer_ls180.v:141661$7387_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:141655$7381 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$issuer_ls180.v:141655$7381_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:141657$7383 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$issuer_ls180.v:141657$7383_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:141660$7386 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$issuer_ls180.v:141660$7386_Y - end - attribute \src "issuer_ls180.v:141619.7-141619.20" - process $proc$issuer_ls180.v:141619$7392 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:141641.7-141641.19" - process $proc$issuer_ls180.v:141641$7393 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:141662.3-141663.27" - process $proc$issuer_ls180.v:141662$7388 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:141664.3-141672.6" - process $proc$issuer_ls180.v:141664$7389 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$7390 $1\q_int$next[0:0]$7391 - attribute \src "issuer_ls180.v:141665.5-141665.29" - switch \initial - attribute \src "issuer_ls180.v:141665.9-141665.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$7391 1'0 - case - assign $1\q_int$next[0:0]$7391 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$7390 - end - connect \$9 $and$issuer_ls180.v:141654$7380_Y - connect \$11 $or$issuer_ls180.v:141655$7381_Y - connect \$13 $not$issuer_ls180.v:141656$7382_Y - connect \$15 $or$issuer_ls180.v:141657$7383_Y - connect \$1 $not$issuer_ls180.v:141658$7384_Y - connect \$3 $and$issuer_ls180.v:141659$7385_Y - connect \$5 $or$issuer_ls180.v:141660$7386_Y - connect \$7 $not$issuer_ls180.v:141661$7387_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "issuer_ls180.v:141680.1-142132.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe2.output" -attribute \generator "nMigen" -module \output - attribute \src "issuer_ls180.v:142051.3-142062.6" - wire width 4 $0\cr0[3:0] - attribute \src "issuer_ls180.v:141681.7-141681.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:142063.3-142074.6" - wire width 65 $0\o$28[64:0]$7412 - attribute \src "issuer_ls180.v:142039.3-142050.6" - wire $0\so[0:0] - attribute \src "issuer_ls180.v:142095.3-142104.6" - wire width 2 $0\xer_ov$24[1:0]$7419 - attribute \src "issuer_ls180.v:142105.3-142114.6" - wire $0\xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:142075.3-142084.6" - wire $0\xer_so$25[0:0]$7415 - attribute \src "issuer_ls180.v:142085.3-142094.6" - wire $0\xer_so_ok[0:0] - attribute \src "issuer_ls180.v:142051.3-142062.6" - wire width 4 $1\cr0[3:0] - attribute \src "issuer_ls180.v:142063.3-142074.6" - wire width 65 $1\o$28[64:0]$7413 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wire input 12 \alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \alu_op__write_cr0$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \alu_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 input 21 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 46 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 47 \cr_a_ok - attribute \src "issuer_ls180.v:141681.7-141681.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" - wire \is_cmp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" - wire \is_cmpeqb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" - wire \is_negative - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" - wire \is_nzero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" - wire \is_positive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" - wire \msb_test - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 54 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 25 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 19 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 44 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" - wire width 65 \o$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 20 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 45 \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" - wire \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" - wire \oe$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" - wire \so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" - wire width 64 \target - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 22 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 48 \xer_ca$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 49 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 23 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 50 \xer_ov$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 51 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 24 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 52 \xer_so$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 53 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$issuer_ls180.v:142026$7394 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_op__oe__oe - connect \B \alu_op__oe__ok - connect \Y $and$issuer_ls180.v:142026$7394_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$issuer_ls180.v:142034$7404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B \$41 - connect \Y $and$issuer_ls180.v:142034$7404_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$issuer_ls180.v:142037$7407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_op__oe__oe - connect \B \alu_op__oe__ok - connect \Y $and$issuer_ls180.v:142037$7407_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$issuer_ls180.v:142030$7400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $eq$issuer_ls180.v:142030$7400_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$issuer_ls180.v:142031$7401 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001100 - connect \Y $eq$issuer_ls180.v:142031$7401_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$issuer_ls180.v:142028$7396 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \$30 - connect \Y $extend$issuer_ls180.v:142028$7396_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $extend$issuer_ls180.v:142029$7398 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \o - connect \Y $extend$issuer_ls180.v:142029$7398_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$issuer_ls180.v:142027$7395 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \o - connect \Y $not$issuer_ls180.v:142027$7395_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$issuer_ls180.v:142033$7403 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $not$issuer_ls180.v:142033$7403_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$issuer_ls180.v:142036$7406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \Y $not$issuer_ls180.v:142036$7406_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$issuer_ls180.v:142035$7405 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_cmpeqb - connect \B \is_cmp - connect \Y $or$issuer_ls180.v:142035$7405_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$issuer_ls180.v:142038$7408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_so - connect \B \xer_ov [0] - connect \Y $or$issuer_ls180.v:142038$7408_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$issuer_ls180.v:142028$7397 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$issuer_ls180.v:142028$7396_Y - connect \Y $pos$issuer_ls180.v:142028$7397_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $pos$issuer_ls180.v:142029$7399 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$issuer_ls180.v:142029$7398_Y - connect \Y $pos$issuer_ls180.v:142029$7399_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$issuer_ls180.v:142032$7402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \target - connect \Y $reduce_or$issuer_ls180.v:142032$7402_Y - end - attribute \src "issuer_ls180.v:141681.7-141681.20" - process $proc$issuer_ls180.v:141681$7422 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:142039.3-142050.6" - process $proc$issuer_ls180.v:142039$7409 - assign { } { } - assign $0\so[0:0] $1\so[0:0] - attribute \src "issuer_ls180.v:142040.5-142040.29" - switch \initial - attribute \src "issuer_ls180.v:142040.9-142040.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" - switch \oe - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\so[0:0] \xer_so$25 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\so[0:0] \xer_so - end - sync always - update \so $0\so[0:0] - end - attribute \src "issuer_ls180.v:142051.3-142062.6" - process $proc$issuer_ls180.v:142051$7410 - assign { } { } - assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "issuer_ls180.v:142052.5-142052.29" - switch \initial - attribute \src "issuer_ls180.v:142052.9-142052.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - switch \$45 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cr0[3:0] \cr_a - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\cr0[3:0] { \is_negative \is_positive \$47 \so } - end - sync always - update \cr0 $0\cr0[3:0] - end - attribute \src "issuer_ls180.v:142063.3-142074.6" - process $proc$issuer_ls180.v:142063$7411 - assign { } { } - assign $0\o$28[64:0]$7412 $1\o$28[64:0]$7413 - attribute \src "issuer_ls180.v:142064.5-142064.29" - switch \initial - attribute \src "issuer_ls180.v:142064.9-142064.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" - switch \alu_op__invert_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\o$28[64:0]$7413 \$29 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\o$28[64:0]$7413 \$33 - end - sync always - update \o$28 $0\o$28[64:0]$7412 - end - attribute \src "issuer_ls180.v:142075.3-142084.6" - process $proc$issuer_ls180.v:142075$7414 - assign { } { } - assign { } { } - assign $0\xer_so$25[0:0]$7415 $1\xer_so$25[0:0]$7416 - attribute \src "issuer_ls180.v:142076.5-142076.29" - switch \initial - attribute \src "issuer_ls180.v:142076.9-142076.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch \oe$49 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\xer_so$25[0:0]$7416 \$52 - case - assign $1\xer_so$25[0:0]$7416 1'0 - end - sync always - update \xer_so$25 $0\xer_so$25[0:0]$7415 - end - attribute \src "issuer_ls180.v:142085.3-142094.6" - process $proc$issuer_ls180.v:142085$7417 - assign { } { } - assign { } { } - assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "issuer_ls180.v:142086.5-142086.29" - switch \initial - attribute \src "issuer_ls180.v:142086.9-142086.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch \oe$49 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\xer_so_ok[0:0] 1'1 - case - assign $1\xer_so_ok[0:0] 1'0 - end - sync always - update \xer_so_ok $0\xer_so_ok[0:0] - end - attribute \src "issuer_ls180.v:142095.3-142104.6" - process $proc$issuer_ls180.v:142095$7418 - assign { } { } - assign { } { } - assign $0\xer_ov$24[1:0]$7419 $1\xer_ov$24[1:0]$7420 - attribute \src "issuer_ls180.v:142096.5-142096.29" - switch \initial - attribute \src "issuer_ls180.v:142096.9-142096.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch \oe$49 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\xer_ov$24[1:0]$7420 \xer_ov - case - assign $1\xer_ov$24[1:0]$7420 2'00 - end - sync always - update \xer_ov$24 $0\xer_ov$24[1:0]$7419 - end - attribute \src "issuer_ls180.v:142105.3-142114.6" - process $proc$issuer_ls180.v:142105$7421 - assign { } { } - assign { } { } - assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:142106.5-142106.29" - switch \initial - attribute \src "issuer_ls180.v:142106.9-142106.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch \oe$49 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\xer_ov_ok[0:0] 1'1 - case - assign $1\xer_ov_ok[0:0] 1'0 - end - sync always - update \xer_ov_ok $0\xer_ov_ok[0:0] - end - connect \$26 $and$issuer_ls180.v:142026$7394_Y - connect \$30 $not$issuer_ls180.v:142027$7395_Y - connect \$29 $pos$issuer_ls180.v:142028$7397_Y - connect \$33 $pos$issuer_ls180.v:142029$7399_Y - connect \$35 $eq$issuer_ls180.v:142030$7400_Y - connect \$37 $eq$issuer_ls180.v:142031$7401_Y - connect \$39 $reduce_or$issuer_ls180.v:142032$7402_Y - connect \$41 $not$issuer_ls180.v:142033$7403_Y - connect \$43 $and$issuer_ls180.v:142034$7404_Y - connect \$45 $or$issuer_ls180.v:142035$7405_Y - connect \$47 $not$issuer_ls180.v:142036$7406_Y - connect \$50 $and$issuer_ls180.v:142037$7407_Y - connect \$52 $or$issuer_ls180.v:142038$7408_Y - connect \oe$49 \$50 - connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } - connect \muxid$1 \muxid - connect \cr_a_ok \alu_op__write_cr0 - connect \cr_a$22 \cr0 - connect \o_ok$21 \o_ok - connect \o$20 \o$28 [63:0] - connect \is_positive \$43 - connect \is_negative \msb_test - connect \is_nzero \$39 - connect \msb_test \target [63] - connect \is_cmpeqb \$37 - connect \is_cmp \$35 - connect \xer_ca_ok \alu_op__output_carry - connect \xer_ca$23 \xer_ca - connect \target \o$28 [63:0] - connect \oe \$26 -end -attribute \src "issuer_ls180.v:142136.1-142480.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2.output" -attribute \generator "nMigen" -module \output$115 - attribute \src "issuer_ls180.v:142452.3-142463.6" - wire width 4 $0\cr0[3:0] - attribute \src "issuer_ls180.v:142137.7-142137.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:142452.3-142463.6" - wire width 4 $1\cr0[3:0] - attribute \src "issuer_ls180.v:142449.18-142449.112" - wire $and$issuer_ls180.v:142449$7429_Y - attribute \src "issuer_ls180.v:142445.18-142445.122" - wire $eq$issuer_ls180.v:142445$7425_Y - attribute \src "issuer_ls180.v:142446.18-142446.122" - wire $eq$issuer_ls180.v:142446$7426_Y - attribute \src "issuer_ls180.v:142444.18-142444.101" - wire width 65 $extend$issuer_ls180.v:142444$7423_Y - attribute \src "issuer_ls180.v:142448.18-142448.107" - wire $not$issuer_ls180.v:142448$7428_Y - attribute \src "issuer_ls180.v:142451.18-142451.107" - wire $not$issuer_ls180.v:142451$7431_Y - attribute \src "issuer_ls180.v:142450.18-142450.115" - wire $or$issuer_ls180.v:142450$7430_Y - attribute \src "issuer_ls180.v:142444.18-142444.101" - wire width 65 $pos$issuer_ls180.v:142444$7424_Y - attribute \src "issuer_ls180.v:142447.18-142447.105" - wire $reduce_or$issuer_ls180.v:142447$7427_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 65 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - wire \$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - wire \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 input 19 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 41 \cr_a$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 42 \cr_a_ok - attribute \src "issuer_ls180.v:142137.7-142137.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" - wire \is_cmp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" - wire \is_cmpeqb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" - wire \is_negative - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" - wire \is_nzero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" - wire \is_positive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" - wire \msb_test - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 45 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 22 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 17 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 39 \o$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" - wire width 65 \o$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 18 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 40 \o_ok$19 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \sr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute 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"issuer_ls180.v:142807.18-142807.107" - wire $not$issuer_ls180.v:142807$7445_Y - attribute \src "issuer_ls180.v:142806.18-142806.115" - wire $or$issuer_ls180.v:142806$7444_Y - attribute \src "issuer_ls180.v:142799.18-142799.103" - wire width 65 $pos$issuer_ls180.v:142799$7436_Y - attribute \src "issuer_ls180.v:142800.18-142800.101" - wire width 65 $pos$issuer_ls180.v:142800$7438_Y - attribute \src "issuer_ls180.v:142803.18-142803.105" - wire $reduce_or$issuer_ls180.v:142803$7441_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - wire width 65 \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - wire width 64 \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 65 \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 input 21 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 44 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 45 \cr_a_ok - attribute \src "issuer_ls180.v:142485.7-142485.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" - wire \is_cmp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" - wire \is_cmpeqb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" - wire \is_negative - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" - wire \is_nzero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" - wire \is_positive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 40 \logical_op__data_len$18 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 25 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 26 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \logical_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 34 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 41 \logical_op__insn$19 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 24 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" - wire \msb_test - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 46 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 23 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 19 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 42 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" - wire width 65 \o$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 20 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 43 \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" - wire width 64 \target - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 22 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$issuer_ls180.v:142805$7443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B \$36 - connect \Y $and$issuer_ls180.v:142805$7443_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$issuer_ls180.v:142801$7439 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0001010 - connect \Y $eq$issuer_ls180.v:142801$7439_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$issuer_ls180.v:142802$7440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0001100 - connect \Y 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\enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 25 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" - wire \msb_test - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 51 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 24 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 19 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 43 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" - wire width 65 \o$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 20 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 44 \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" - wire \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" - wire \oe$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" - wire \so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" - wire width 64 \target - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 22 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 47 \xer_ov$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 48 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 23 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 49 \xer_so$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 50 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$issuer_ls180.v:143189$7451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \logical_op__oe__oe - connect \B \logical_op__oe__ok - connect \Y $and$issuer_ls180.v:143189$7451_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$issuer_ls180.v:143197$7461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B \$40 - connect \Y $and$issuer_ls180.v:143197$7461_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$issuer_ls180.v:143200$7464 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \logical_op__oe__oe - connect \B \logical_op__oe__ok - connect \Y $and$issuer_ls180.v:143200$7464_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$issuer_ls180.v:143193$7457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0001010 - connect \Y $eq$issuer_ls180.v:143193$7457_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$issuer_ls180.v:143194$7458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0001100 - connect \Y $eq$issuer_ls180.v:143194$7458_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$issuer_ls180.v:143191$7453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \$29 - connect \Y $extend$issuer_ls180.v:143191$7453_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $extend$issuer_ls180.v:143192$7455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \o - connect \Y $extend$issuer_ls180.v:143192$7455_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$issuer_ls180.v:143190$7452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \o - connect \Y $not$issuer_ls180.v:143190$7452_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$issuer_ls180.v:143196$7460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $not$issuer_ls180.v:143196$7460_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$issuer_ls180.v:143199$7463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \Y $not$issuer_ls180.v:143199$7463_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$issuer_ls180.v:143198$7462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_cmpeqb - connect \B \is_cmp - connect \Y $or$issuer_ls180.v:143198$7462_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$issuer_ls180.v:143201$7465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_so - connect \B \xer_ov [0] - connect \Y $or$issuer_ls180.v:143201$7465_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$issuer_ls180.v:143191$7454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$issuer_ls180.v:143191$7453_Y - connect \Y $pos$issuer_ls180.v:143191$7454_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $pos$issuer_ls180.v:143192$7456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$issuer_ls180.v:143192$7455_Y - connect \Y $pos$issuer_ls180.v:143192$7456_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$issuer_ls180.v:143195$7459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \target - connect \Y $reduce_or$issuer_ls180.v:143195$7459_Y - end - attribute \src "issuer_ls180.v:142850.7-142850.20" - process $proc$issuer_ls180.v:142850$7479 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:143202.3-143213.6" - process $proc$issuer_ls180.v:143202$7466 - assign { } { } - assign $0\so[0:0] $1\so[0:0] - attribute \src "issuer_ls180.v:143203.5-143203.29" - switch \initial - attribute \src "issuer_ls180.v:143203.9-143203.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" - switch \oe - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\so[0:0] \xer_so$24 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\so[0:0] \xer_so - end - sync always - update \so $0\so[0:0] - end - attribute \src "issuer_ls180.v:143214.3-143225.6" - process $proc$issuer_ls180.v:143214$7467 - assign { } { } - assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "issuer_ls180.v:143215.5-143215.29" - switch \initial - attribute \src "issuer_ls180.v:143215.9-143215.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - switch \$44 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cr0[3:0] \cr_a - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\cr0[3:0] { \is_negative \is_positive \$46 \so } - end - sync always - update \cr0 $0\cr0[3:0] - end - attribute \src "issuer_ls180.v:143226.3-143237.6" - process $proc$issuer_ls180.v:143226$7468 - assign { } { } - assign $0\o$27[64:0]$7469 $1\o$27[64:0]$7470 - attribute \src "issuer_ls180.v:143227.5-143227.29" - switch \initial - attribute \src "issuer_ls180.v:143227.9-143227.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" - switch \logical_op__invert_out - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\o$27[64:0]$7470 \$28 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\o$27[64:0]$7470 \$32 - end - sync always - update \o$27 $0\o$27[64:0]$7469 - end - attribute \src "issuer_ls180.v:143238.3-143247.6" - process $proc$issuer_ls180.v:143238$7471 - assign { } { } - assign { } { } - assign $0\xer_so$24[0:0]$7472 $1\xer_so$24[0:0]$7473 - attribute \src "issuer_ls180.v:143239.5-143239.29" - switch \initial - attribute \src "issuer_ls180.v:143239.9-143239.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch \oe$48 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\xer_so$24[0:0]$7473 \$51 - case - assign $1\xer_so$24[0:0]$7473 1'0 - end - sync always - update \xer_so$24 $0\xer_so$24[0:0]$7472 - end - attribute \src "issuer_ls180.v:143248.3-143257.6" - process $proc$issuer_ls180.v:143248$7474 - assign { } { } - assign { } { } - assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "issuer_ls180.v:143249.5-143249.29" - switch \initial - attribute \src "issuer_ls180.v:143249.9-143249.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch \oe$48 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\xer_so_ok[0:0] 1'1 - case - assign $1\xer_so_ok[0:0] 1'0 - end - sync always - update \xer_so_ok $0\xer_so_ok[0:0] - end - attribute \src "issuer_ls180.v:143258.3-143267.6" - process $proc$issuer_ls180.v:143258$7475 - assign { } { } - assign { } { } - assign $0\xer_ov$23[1:0]$7476 $1\xer_ov$23[1:0]$7477 - attribute \src "issuer_ls180.v:143259.5-143259.29" - switch \initial - attribute \src "issuer_ls180.v:143259.9-143259.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch \oe$48 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\xer_ov$23[1:0]$7477 \xer_ov - case - assign $1\xer_ov$23[1:0]$7477 2'00 - end - sync always - update \xer_ov$23 $0\xer_ov$23[1:0]$7476 - end - attribute \src "issuer_ls180.v:143268.3-143277.6" - process $proc$issuer_ls180.v:143268$7478 - assign { } { } - assign { } { } - assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:143269.5-143269.29" - switch \initial - attribute \src "issuer_ls180.v:143269.9-143269.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch \oe$48 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\xer_ov_ok[0:0] 1'1 - case - assign $1\xer_ov_ok[0:0] 1'0 - end - sync always - update \xer_ov_ok $0\xer_ov_ok[0:0] - end - connect \$25 $and$issuer_ls180.v:143189$7451_Y - connect \$29 $not$issuer_ls180.v:143190$7452_Y - connect \$28 $pos$issuer_ls180.v:143191$7454_Y - connect \$32 $pos$issuer_ls180.v:143192$7456_Y - connect \$34 $eq$issuer_ls180.v:143193$7457_Y - connect \$36 $eq$issuer_ls180.v:143194$7458_Y - connect \$38 $reduce_or$issuer_ls180.v:143195$7459_Y - connect \$40 $not$issuer_ls180.v:143196$7460_Y - connect \$42 $and$issuer_ls180.v:143197$7461_Y - connect \$44 $or$issuer_ls180.v:143198$7462_Y - connect \$46 $not$issuer_ls180.v:143199$7463_Y - connect \$49 $and$issuer_ls180.v:143200$7464_Y - connect \$51 $or$issuer_ls180.v:143201$7465_Y - connect \oe$48 \$49 - connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - connect \muxid$1 \muxid - connect \cr_a_ok \logical_op__write_cr0 - connect \cr_a$22 \cr0 - connect \o_ok$21 \o_ok - connect \o$20 \o$27 [63:0] - connect \is_positive \$42 - connect \is_negative \msb_test - connect \is_nzero \$38 - connect \msb_test \target [63] - connect \is_cmpeqb \$36 - connect \is_cmp \$34 - connect \target \o$27 [63:0] - connect \oe \$25 -end -attribute \src "issuer_ls180.v:143297.1-143692.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.output" -attribute \generator "nMigen" -module \output$97 - attribute \src "issuer_ls180.v:143624.3-143635.6" - wire width 4 $0\cr0[3:0] - attribute \src "issuer_ls180.v:143298.7-143298.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:143612.3-143623.6" - wire $0\so[0:0] - attribute \src "issuer_ls180.v:143656.3-143665.6" - wire width 2 $0\xer_ov$17[1:0]$7499 - attribute \src "issuer_ls180.v:143666.3-143675.6" - wire $0\xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:143636.3-143645.6" - wire $0\xer_so$18[0:0]$7495 - attribute \src "issuer_ls180.v:143646.3-143655.6" - wire $0\xer_so_ok[0:0] - attribute \src "issuer_ls180.v:143624.3-143635.6" - wire width 4 $1\cr0[3:0] - attribute \src "issuer_ls180.v:143612.3-143623.6" - wire $1\so[0:0] - attribute \src "issuer_ls180.v:143656.3-143665.6" - wire width 2 $1\xer_ov$17[1:0]$7500 - attribute \src "issuer_ls180.v:143666.3-143675.6" - wire $1\xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:143636.3-143645.6" - wire $1\xer_so$18[0:0]$7496 - attribute \src "issuer_ls180.v:143646.3-143655.6" - wire $1\xer_so_ok[0:0] - attribute \src "issuer_ls180.v:143601.18-143601.128" - wire $and$issuer_ls180.v:143601$7480_Y - attribute \src "issuer_ls180.v:143607.18-143607.112" - wire $and$issuer_ls180.v:143607$7487_Y - attribute \src "issuer_ls180.v:143610.18-143610.125" - wire $and$issuer_ls180.v:143610$7490_Y - attribute \src "issuer_ls180.v:143603.18-143603.123" - wire $eq$issuer_ls180.v:143603$7483_Y - attribute \src "issuer_ls180.v:143604.18-143604.123" - wire $eq$issuer_ls180.v:143604$7484_Y - attribute \src "issuer_ls180.v:143602.18-143602.101" - wire width 65 $extend$issuer_ls180.v:143602$7481_Y - attribute \src "issuer_ls180.v:143606.18-143606.107" - wire $not$issuer_ls180.v:143606$7486_Y - attribute \src "issuer_ls180.v:143609.18-143609.107" - wire $not$issuer_ls180.v:143609$7489_Y - attribute \src "issuer_ls180.v:143608.18-143608.115" - wire $or$issuer_ls180.v:143608$7488_Y - attribute \src "issuer_ls180.v:143611.18-143611.112" - wire $or$issuer_ls180.v:143611$7491_Y - attribute \src "issuer_ls180.v:143602.18-143602.101" - wire width 65 $pos$issuer_ls180.v:143602$7482_Y - attribute \src "issuer_ls180.v:143605.18-143605.105" - wire $reduce_or$issuer_ls180.v:143605$7485_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 65 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - wire \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - wire \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 input 15 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 33 \cr_a$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 34 \cr_a_ok - attribute \src "issuer_ls180.v:143298.7-143298.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" - wire \is_cmp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" - wire \is_cmpeqb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" - wire \is_negative - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" - wire \is_nzero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" - wire \is_positive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" - wire \msb_test - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \mul_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 20 \mul_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 21 \mul_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 22 \mul_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 12 \mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 30 \mul_op__insn$13 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \mul_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 19 \mul_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \mul_op__is_32bit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \mul_op__is_signed$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 25 \mul_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \mul_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 24 \mul_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 23 \mul_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \mul_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 39 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 18 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 13 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 31 \o$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" - wire width 65 \o$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 14 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 32 \o_ok$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" - wire \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" - wire \oe$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" - wire \so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" - wire width 64 \target - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 16 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 35 \xer_ov$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 36 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 17 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 37 \xer_so$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 38 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$issuer_ls180.v:143601$7480 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \mul_op__oe__oe - connect \B \mul_op__oe__ok - connect \Y $and$issuer_ls180.v:143601$7480_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$issuer_ls180.v:143607$7487 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B \$30 - connect \Y $and$issuer_ls180.v:143607$7487_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$issuer_ls180.v:143610$7490 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter 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\enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 29 \logical_op__fn_unit$3 - attribute \src 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2 output 38 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 45 \logical_op__insn$19 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 28 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 42 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 43 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 41 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 51 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 27 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 46 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 47 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:75" - wire \ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:26" - wire width 65 \quotient_65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:24" - wire \quotient_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 64 input 25 \quotient_root - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" - wire width 192 input 26 \remainder - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:27" - wire width 64 \remainder_64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:25" - wire \remainder_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 48 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 49 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 19 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 50 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $and $and$issuer_ls180.v:144040$7516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \logical_op__is_signed - connect \B \$38 - connect \Y $and$issuer_ls180.v:144040$7516_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $pos $extend$issuer_ls180.v:144032$7504 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \quotient_root - connect \Y $extend$issuer_ls180.v:144032$7504_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - cell $pos $extend$issuer_ls180.v:144033$7506 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \quotient_root - connect \Y $extend$issuer_ls180.v:144033$7506_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $pos $extend$issuer_ls180.v:144035$7509 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \remainder [127:64] - connect \Y $extend$issuer_ls180.v:144035$7509_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$issuer_ls180.v:144036$7511 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \remainder [127:64] - connect \Y $extend$issuer_ls180.v:144036$7511_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" - cell $pos $extend$issuer_ls180.v:144043$7519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \quotient_65 [31:0] - connect \Y $extend$issuer_ls180.v:144043$7519_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:104" - cell $pos $extend$issuer_ls180.v:144044$7521 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \quotient_65 [31:0] - connect \Y $extend$issuer_ls180.v:144044$7521_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" - cell $pos $extend$issuer_ls180.v:144045$7523 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \quotient_65 [31:0] - connect \Y $extend$issuer_ls180.v:144045$7523_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:113" - cell $pos $extend$issuer_ls180.v:144046$7525 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \quotient_65 [31:0] - connect \Y $extend$issuer_ls180.v:144046$7525_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:122" - cell $pos $extend$issuer_ls180.v:144048$7528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \remainder_64 [31:0] - connect \Y $extend$issuer_ls180.v:144048$7528_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - cell $ne $ne$issuer_ls180.v:144041$7517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \quotient_65 [32] - connect \B \quotient_65 [31] - connect \Y $ne$issuer_ls180.v:144041$7517_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $neg $neg$issuer_ls180.v:144032$7505 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$issuer_ls180.v:144032$7504_Y - connect \Y $neg$issuer_ls180.v:144032$7505_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $neg $neg$issuer_ls180.v:144035$7510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$issuer_ls180.v:144035$7509_Y - connect \Y $neg$issuer_ls180.v:144035$7510_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" - cell $not $not$issuer_ls180.v:144038$7514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \logical_op__is_32bit - connect \Y $not$issuer_ls180.v:144038$7514_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" - cell $not $not$issuer_ls180.v:144042$7518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ov - connect \Y $not$issuer_ls180.v:144042$7518_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - cell $pos $pos$issuer_ls180.v:144033$7507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$issuer_ls180.v:144033$7506_Y - connect \Y $pos$issuer_ls180.v:144033$7507_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$issuer_ls180.v:144036$7512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$issuer_ls180.v:144036$7511_Y - connect \Y $pos$issuer_ls180.v:144036$7512_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" - cell $pos $pos$issuer_ls180.v:144043$7520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:144043$7519_Y - connect \Y $pos$issuer_ls180.v:144043$7520_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:104" - cell $pos $pos$issuer_ls180.v:144044$7522 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:144044$7521_Y - connect \Y $pos$issuer_ls180.v:144044$7522_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" - cell $pos $pos$issuer_ls180.v:144045$7524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:144045$7523_Y - connect \Y $pos$issuer_ls180.v:144045$7524_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:113" - cell $pos $pos$issuer_ls180.v:144046$7526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:144046$7525_Y - connect \Y $pos$issuer_ls180.v:144046$7526_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:120" - cell $pos $pos$issuer_ls180.v:144047$7527 - parameter \A_SIGNED 1 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31:0] } - connect \Y $pos$issuer_ls180.v:144047$7527_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:122" - cell $pos $pos$issuer_ls180.v:144048$7529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:144048$7528_Y - connect \Y $pos$issuer_ls180.v:144048$7529_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $mux $ternary$issuer_ls180.v:144034$7508 - parameter \WIDTH 65 - connect \A \$25 - connect \B \$23 - connect \S \quotient_neg - connect \Y $ternary$issuer_ls180.v:144034$7508_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $mux $ternary$issuer_ls180.v:144037$7513 - parameter \WIDTH 65 - connect \A \$32 - connect \B \$30 - connect \S \remainder_neg - connect \Y $ternary$issuer_ls180.v:144037$7513_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" - cell $xor $xor$issuer_ls180.v:144031$7503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dividend_neg - connect \B \divisor_neg - connect \Y $xor$issuer_ls180.v:144031$7503_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $xor $xor$issuer_ls180.v:144039$7515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \quotient_65 [64] - connect \B \quotient_65 [63] - connect \Y $xor$issuer_ls180.v:144039$7515_Y - end - attribute \src "issuer_ls180.v:143697.7-143697.20" - process $proc$issuer_ls180.v:143697$7532 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:144049.3-144082.6" - process $proc$issuer_ls180.v:144049$7530 - assign { } { } - assign $0\ov[0:0] $1\ov[0:0] - attribute \src "issuer_ls180.v:144050.5-144050.29" - switch \initial - attribute \src "issuer_ls180.v:144050.9-144050.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" - switch { \logical_op__is_signed \$36 \div_by_zero } - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $1\ov[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'-1- - assign { } { } - assign { } { } - assign $1\ov[0:0] $2\ov[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - switch \$40 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ov[0:0] 1'1 - case - assign $2\ov[0:0] \dive_abs_ov64 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 3'1-- - assign { } { } - assign { } { } - assign $1\ov[0:0] $3\ov[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - switch \$42 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ov[0:0] 1'1 - case - assign $3\ov[0:0] \dive_abs_ov32 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\ov[0:0] \dive_abs_ov32 - end - sync always - update \ov $0\ov[0:0] - end - attribute \src "issuer_ls180.v:144083.3-144154.6" - process $proc$issuer_ls180.v:144083$7531 - assign { } { } - assign { } { } - assign $0\o[63:0] $1\o[63:0] - attribute \src "issuer_ls180.v:144084.5-144084.29" - switch \initial - attribute \src "issuer_ls180.v:144084.9-144084.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" - switch \$44 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\o[63:0] $2\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" - switch \logical_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0011110 - assign { } { } - assign $2\o[63:0] $3\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" - switch \logical_op__is_32bit - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\o[63:0] $4\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:100" - switch \logical_op__is_signed - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\o[63:0] \$46 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $4\o[63:0] \$48 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $3\o[63:0] \quotient_65 [63:0] - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0011101 - assign { } { } - assign $2\o[63:0] $5\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - switch \logical_op__is_32bit - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\o[63:0] $6\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:109" - switch \logical_op__is_signed - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\o[63:0] \$50 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $6\o[63:0] \$52 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $5\o[63:0] \quotient_65 [63:0] - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0101111 - assign { } { } - assign $2\o[63:0] $7\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" - switch \logical_op__is_32bit - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\o[63:0] $8\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:118" - switch \logical_op__is_signed - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $8\o[63:0] \$54 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $8\o[63:0] \$56 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $7\o[63:0] \remainder_64 - end - case - assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \o $0\o[63:0] - end - connect \$21 $xor$issuer_ls180.v:144031$7503_Y - connect \$23 $neg$issuer_ls180.v:144032$7505_Y - connect \$25 $pos$issuer_ls180.v:144033$7507_Y - connect \$27 $ternary$issuer_ls180.v:144034$7508_Y - connect \$30 $neg$issuer_ls180.v:144035$7510_Y - connect \$32 $pos$issuer_ls180.v:144036$7512_Y - connect \$34 $ternary$issuer_ls180.v:144037$7513_Y - connect \$36 $not$issuer_ls180.v:144038$7514_Y - connect \$38 $xor$issuer_ls180.v:144039$7515_Y - connect \$40 $and$issuer_ls180.v:144040$7516_Y - connect \$42 $ne$issuer_ls180.v:144041$7517_Y - connect \$44 $not$issuer_ls180.v:144042$7518_Y - connect \$46 $pos$issuer_ls180.v:144043$7520_Y - connect \$48 $pos$issuer_ls180.v:144044$7522_Y - connect \$50 $pos$issuer_ls180.v:144045$7524_Y - connect \$52 $pos$issuer_ls180.v:144046$7526_Y - connect \$54 $pos$issuer_ls180.v:144047$7527_Y - connect \$56 $pos$issuer_ls180.v:144048$7529_Y - connect \$29 \$34 - connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - connect \muxid$1 \muxid - connect \xer_so$20 \xer_so - connect \o_ok 1'1 - connect \xer_ov { \ov \ov } - connect \xer_ov_ok 1'1 - connect \remainder_64 \$34 [63:0] - connect \quotient_65 \$27 - connect \remainder_neg \dividend_neg - connect \quotient_neg \$21 -end -attribute \src "issuer_ls180.v:144170.1-144181.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.p" -attribute \generator "nMigen" -module \p - attribute \src "issuer_ls180.v:144179.17-144179.111" - wire $and$issuer_ls180.v:144179$7533_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144179$7533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144179$7533_Y - end - connect \$1 $and$issuer_ls180.v:144179$7533_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144185.1-144196.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1.p" -attribute \generator "nMigen" -module \p$1 - attribute \src "issuer_ls180.v:144194.17-144194.111" - wire $and$issuer_ls180.v:144194$7534_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144194$7534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144194$7534_Y - end - connect \$1 $and$issuer_ls180.v:144194$7534_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144200.1-144211.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.p" -attribute \generator "nMigen" -module \p$105 - attribute \src "issuer_ls180.v:144209.17-144209.111" - wire $and$issuer_ls180.v:144209$7535_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144209$7535 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144209$7535_Y - end - connect \$1 $and$issuer_ls180.v:144209$7535_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144215.1-144226.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.p" -attribute \generator "nMigen" -module \p$108 - attribute \src "issuer_ls180.v:144224.17-144224.111" - wire $and$issuer_ls180.v:144224$7536_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144224$7536 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144224$7536_Y - end - connect \$1 $and$issuer_ls180.v:144224$7536_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144230.1-144241.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2.p" -attribute \generator "nMigen" -module \p$113 - attribute \src "issuer_ls180.v:144239.17-144239.111" - wire $and$issuer_ls180.v:144239$7537_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144239$7537 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144239$7537_Y - end - connect \$1 $and$issuer_ls180.v:144239$7537_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144245.1-144256.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.p" -attribute \generator "nMigen" -module \p$17 - attribute \src "issuer_ls180.v:144254.17-144254.111" - wire $and$issuer_ls180.v:144254$7538_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144254$7538 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144254$7538_Y - end - connect \$1 $and$issuer_ls180.v:144254$7538_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144260.1-144271.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.p" -attribute \generator "nMigen" -module \p$20 - attribute \src "issuer_ls180.v:144269.17-144269.111" - wire $and$issuer_ls180.v:144269$7539_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144269$7539 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144269$7539_Y - end - connect \$1 $and$issuer_ls180.v:144269$7539_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144275.1-144286.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe2.p" -attribute \generator "nMigen" -module \p$3 - attribute \src "issuer_ls180.v:144284.17-144284.111" - wire $and$issuer_ls180.v:144284$7540_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144284$7540 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144284$7540_Y - end - connect \$1 $and$issuer_ls180.v:144284$7540_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144290.1-144301.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.p" -attribute \generator "nMigen" -module \p$30 - attribute \src "issuer_ls180.v:144299.17-144299.111" - wire $and$issuer_ls180.v:144299$7541_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144299$7541 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144299$7541_Y - end - connect \$1 $and$issuer_ls180.v:144299$7541_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144305.1-144316.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.p" -attribute \generator "nMigen" -module \p$33 - attribute \src "issuer_ls180.v:144314.17-144314.111" - wire $and$issuer_ls180.v:144314$7542_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144314$7542 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144314$7542_Y - end - connect \$1 $and$issuer_ls180.v:144314$7542_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144320.1-144331.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.p" -attribute \generator "nMigen" -module \p$43 - attribute \src "issuer_ls180.v:144329.17-144329.111" - wire $and$issuer_ls180.v:144329$7543_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144329$7543 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144329$7543_Y - end - connect \$1 $and$issuer_ls180.v:144329$7543_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144335.1-144346.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.p" -attribute \generator "nMigen" -module \p$45 - attribute \src "issuer_ls180.v:144344.17-144344.111" - wire $and$issuer_ls180.v:144344$7544_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144344$7544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144344$7544_Y - end - connect \$1 $and$issuer_ls180.v:144344$7544_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144350.1-144361.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe2.p" -attribute \generator "nMigen" -module \p$49 - attribute \src "issuer_ls180.v:144359.17-144359.111" - wire $and$issuer_ls180.v:144359$7545_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144359$7545 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144359$7545_Y - end - connect \$1 $and$issuer_ls180.v:144359$7545_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144365.1-144376.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.p" -attribute \generator "nMigen" -module \p$5 - attribute \src "issuer_ls180.v:144374.17-144374.111" - wire $and$issuer_ls180.v:144374$7546_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144374$7546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144374$7546_Y - end - connect \$1 $and$issuer_ls180.v:144374$7546_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144380.1-144391.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.p" -attribute \generator "nMigen" -module \p$59 - attribute \src "issuer_ls180.v:144389.17-144389.111" - wire $and$issuer_ls180.v:144389$7547_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144389$7547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144389$7547_Y - end - connect \$1 $and$issuer_ls180.v:144389$7547_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144395.1-144406.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.p" -attribute \generator "nMigen" -module \p$62 - attribute \src "issuer_ls180.v:144404.17-144404.111" - wire $and$issuer_ls180.v:144404$7548_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144404$7548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144404$7548_Y - end - connect \$1 $and$issuer_ls180.v:144404$7548_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144410.1-144421.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.p" -attribute \generator "nMigen" -module \p$7 - attribute \src "issuer_ls180.v:144419.17-144419.111" - wire $and$issuer_ls180.v:144419$7549_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144419$7549 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144419$7549_Y - end - connect \$1 $and$issuer_ls180.v:144419$7549_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144425.1-144436.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.p" -attribute \generator "nMigen" -module \p$71 - attribute \src "issuer_ls180.v:144434.17-144434.111" - wire $and$issuer_ls180.v:144434$7550_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144434$7550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144434$7550_Y - end - connect \$1 $and$issuer_ls180.v:144434$7550_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144440.1-144451.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.p" -attribute \generator "nMigen" -module \p$73 - attribute \src "issuer_ls180.v:144449.17-144449.111" - wire $and$issuer_ls180.v:144449$7551_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144449$7551 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144449$7551_Y - end - connect \$1 $and$issuer_ls180.v:144449$7551_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144455.1-144466.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.p" -attribute \generator "nMigen" -module \p$76 - attribute \src "issuer_ls180.v:144464.17-144464.111" - wire $and$issuer_ls180.v:144464$7552_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144464$7552 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144464$7552_Y - end - connect \$1 $and$issuer_ls180.v:144464$7552_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144470.1-144481.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.p" -attribute \generator "nMigen" -module \p$78 - attribute \src "issuer_ls180.v:144479.17-144479.111" - wire $and$issuer_ls180.v:144479$7553_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144479$7553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144479$7553_Y - end - connect \$1 $and$issuer_ls180.v:144479$7553_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144485.1-144496.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.p" -attribute \generator "nMigen" -module \p$88 - attribute \src "issuer_ls180.v:144494.17-144494.111" - wire $and$issuer_ls180.v:144494$7554_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144494$7554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144494$7554_Y - end - connect \$1 $and$issuer_ls180.v:144494$7554_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144500.1-144511.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.p" -attribute \generator "nMigen" -module \p$90 - attribute \src "issuer_ls180.v:144509.17-144509.111" - wire $and$issuer_ls180.v:144509$7555_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144509$7555 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144509$7555_Y - end - connect \$1 $and$issuer_ls180.v:144509$7555_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144515.1-144526.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.p" -attribute \generator "nMigen" -module \p$93 - attribute \src "issuer_ls180.v:144524.17-144524.111" - wire $and$issuer_ls180.v:144524$7556_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144524$7556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144524$7556_Y - end - connect \$1 $and$issuer_ls180.v:144524$7556_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144530.1-144541.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.p" -attribute \generator "nMigen" -module \p$95 - attribute \src "issuer_ls180.v:144539.17-144539.111" - wire $and$issuer_ls180.v:144539$7557_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$issuer_ls180.v:144539$7557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:144539$7557_Y - end - connect \$1 $and$issuer_ls180.v:144539$7557_Y - connect \trigger \$1 -end -attribute \src "issuer_ls180.v:144545.1-144568.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.l0.pick" -attribute \generator "nMigen" -module \pick - attribute \src "issuer_ls180.v:144546.7-144546.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:144557.3-144566.6" - wire $0\o[0:0] - attribute \src "issuer_ls180.v:144557.3-144566.6" - wire $1\o[0:0] - attribute \src "issuer_ls180.v:144556.17-144556.95" - wire $eq$issuer_ls180.v:144556$7558_Y - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire input 3 \i - attribute \src "issuer_ls180.v:144546.7-144546.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire output 2 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $eq$issuer_ls180.v:144556$7558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $eq$issuer_ls180.v:144556$7558_Y - end - attribute \src "issuer_ls180.v:144546.7-144546.20" - process $proc$issuer_ls180.v:144546$7560 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:144557.3-144566.6" - process $proc$issuer_ls180.v:144557$7559 - assign { } { } - assign { } { } - assign $0\o[0:0] $1\o[0:0] - attribute \src "issuer_ls180.v:144558.5-144558.29" - switch \initial - attribute \src "issuer_ls180.v:144558.9-144558.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch \i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\o[0:0] 1'0 - case - assign $1\o[0:0] 1'0 - end - sync always - update \o $0\o[0:0] - end - connect \$1 $eq$issuer_ls180.v:144556$7558_Y - connect \n \$1 -end -attribute \src "issuer_ls180.v:144572.1-145386.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem" -attribute \generator "nMigen" -module \pimem - attribute \src "issuer_ls180.v:145349.3-145364.6" - wire $0\adrok_l_r_addr_acked[0:0] - attribute \src "issuer_ls180.v:145313.3-145348.6" - wire $0\adrok_l_s_addr_acked$next[0:0]$7650 - attribute \src "issuer_ls180.v:144871.3-144872.57" - wire $0\adrok_l_s_addr_acked[0:0] - attribute \src "issuer_ls180.v:144963.3-144971.6" - wire $0\busy_delay$next[0:0]$7618 - attribute \src "issuer_ls180.v:144869.3-144870.37" - wire $0\busy_delay[0:0] - attribute \src "issuer_ls180.v:145297.3-145312.6" - wire $0\busy_l_r_busy[0:0] - attribute \src "issuer_ls180.v:145287.3-145296.6" - wire $0\busy_l_s_busy[0:0] - attribute \src "issuer_ls180.v:145277.3-145286.6" - wire $0\cyc_l_r_cyc[0:0] - attribute \src "issuer_ls180.v:145258.3-145267.6" - wire $0\cyc_l_s_cyc[0:0] - attribute \src "issuer_ls180.v:145219.3-145257.6" - wire width 2 $0\fsm_state$next[1:0]$7636 - attribute \src "issuer_ls180.v:144861.3-144862.35" - wire width 2 $0\fsm_state[1:0] - attribute \src "issuer_ls180.v:144573.7-144573.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:145159.3-145168.6" - wire $0\ld_active_r_ld_active[0:0] - attribute \src "issuer_ls180.v:144867.3-144868.35" - wire $0\lds_dly[0:0] - attribute \src "issuer_ls180.v:145092.3-145122.6" - wire $0\ldst_port0_addr_ok_o[0:0] - attribute \src "issuer_ls180.v:145149.3-145158.6" - wire width 64 $0\ldst_port0_ld_data_o[63:0] - attribute \src "issuer_ls180.v:145169.3-145178.6" - wire $0\ldst_port0_ld_data_o_ok[0:0] - attribute \src "issuer_ls180.v:144998.3-145013.6" - wire width 4 $0\lenexp_addr_i[3:0] - attribute \src "issuer_ls180.v:144982.3-144997.6" - wire width 4 $0\lenexp_len_i[3:0] - attribute \src "issuer_ls180.v:145268.3-145276.6" - wire $0\lsui_active_dly$next[0:0]$7644 - attribute \src "issuer_ls180.v:144859.3-144860.47" - wire $0\lsui_active_dly[0:0] - attribute \src "issuer_ls180.v:145199.3-145218.6" - wire $0\lsui_busy[0:0] - attribute \src "issuer_ls180.v:144863.3-144864.36" - wire $0\reset_delay[0:0] - attribute \src "issuer_ls180.v:145139.3-145148.6" - wire $0\reset_l_r_reset[0:0] - attribute \src "issuer_ls180.v:145123.3-145138.6" - wire $0\reset_l_s_reset[0:0] - attribute \src "issuer_ls180.v:144972.3-144981.6" - wire $0\st_active_r_st_active[0:0] - attribute \src "issuer_ls180.v:144953.3-144962.6" - wire $0\st_done_r_st_done[0:0] - attribute \src "issuer_ls180.v:144938.3-144952.6" - wire $0\st_done_s_st_done$next[0:0]$7613 - attribute \src "issuer_ls180.v:144873.3-144874.51" - wire $0\st_done_s_st_done[0:0] - attribute \src "issuer_ls180.v:145179.3-145188.6" - wire width 64 $0\stdata[63:0] - attribute \src "issuer_ls180.v:144865.3-144866.35" - wire $0\sts_dly[0:0] - attribute \src "issuer_ls180.v:145014.3-145039.6" - wire $0\valid_l_s_valid[0:0] - attribute \src "issuer_ls180.v:145066.3-145091.6" - wire width 48 $0\x_addr_i[47:0] - attribute \src "issuer_ls180.v:145040.3-145065.6" - wire width 8 $0\x_mask_i[7:0] - attribute \src "issuer_ls180.v:145189.3-145198.6" - wire width 64 $0\x_st_data_i[63:0] - attribute \src "issuer_ls180.v:145349.3-145364.6" - wire $1\adrok_l_r_addr_acked[0:0] - attribute \src "issuer_ls180.v:145313.3-145348.6" - wire $1\adrok_l_s_addr_acked$next[0:0]$7651 - attribute \src "issuer_ls180.v:144667.7-144667.34" - wire $1\adrok_l_s_addr_acked[0:0] - attribute \src "issuer_ls180.v:144963.3-144971.6" - wire $1\busy_delay$next[0:0]$7619 - attribute \src "issuer_ls180.v:144671.7-144671.24" - wire $1\busy_delay[0:0] - attribute \src "issuer_ls180.v:145297.3-145312.6" - wire $1\busy_l_r_busy[0:0] - attribute \src "issuer_ls180.v:145287.3-145296.6" - wire $1\busy_l_s_busy[0:0] - attribute \src "issuer_ls180.v:145277.3-145286.6" - wire $1\cyc_l_r_cyc[0:0] - attribute \src "issuer_ls180.v:145258.3-145267.6" - wire $1\cyc_l_s_cyc[0:0] - attribute \src "issuer_ls180.v:145219.3-145257.6" - wire width 2 $1\fsm_state$next[1:0]$7637 - attribute \src "issuer_ls180.v:144693.13-144693.29" - wire width 2 $1\fsm_state[1:0] - attribute \src "issuer_ls180.v:145159.3-145168.6" - wire $1\ld_active_r_ld_active[0:0] - attribute \src "issuer_ls180.v:144707.7-144707.21" - wire $1\lds_dly[0:0] - attribute \src "issuer_ls180.v:145092.3-145122.6" - wire $1\ldst_port0_addr_ok_o[0:0] - attribute \src "issuer_ls180.v:145149.3-145158.6" - wire width 64 $1\ldst_port0_ld_data_o[63:0] - attribute \src "issuer_ls180.v:145169.3-145178.6" - wire $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "issuer_ls180.v:144998.3-145013.6" - wire width 4 $1\lenexp_addr_i[3:0] - attribute \src "issuer_ls180.v:144982.3-144997.6" - wire width 4 $1\lenexp_len_i[3:0] - attribute \src "issuer_ls180.v:145268.3-145276.6" - wire $1\lsui_active_dly$next[0:0]$7645 - attribute \src "issuer_ls180.v:144750.7-144750.29" - wire $1\lsui_active_dly[0:0] - attribute \src "issuer_ls180.v:145199.3-145218.6" - wire $1\lsui_busy[0:0] - attribute \src "issuer_ls180.v:144762.7-144762.25" - wire $1\reset_delay[0:0] - attribute \src "issuer_ls180.v:145139.3-145148.6" - wire $1\reset_l_r_reset[0:0] - attribute \src "issuer_ls180.v:145123.3-145138.6" - wire $1\reset_l_s_reset[0:0] - attribute \src "issuer_ls180.v:144972.3-144981.6" - wire $1\st_active_r_st_active[0:0] - attribute \src "issuer_ls180.v:144953.3-144962.6" - wire $1\st_done_r_st_done[0:0] - attribute \src "issuer_ls180.v:144938.3-144952.6" - wire $1\st_done_s_st_done$next[0:0]$7614 - attribute \src "issuer_ls180.v:144782.7-144782.31" - wire $1\st_done_s_st_done[0:0] - attribute \src "issuer_ls180.v:145179.3-145188.6" - wire width 64 $1\stdata[63:0] - attribute \src "issuer_ls180.v:144790.7-144790.21" - wire $1\sts_dly[0:0] - attribute \src "issuer_ls180.v:145014.3-145039.6" - wire $1\valid_l_s_valid[0:0] - attribute \src "issuer_ls180.v:145066.3-145091.6" - wire width 48 $1\x_addr_i[47:0] - attribute \src "issuer_ls180.v:145040.3-145065.6" - wire width 8 $1\x_mask_i[7:0] - attribute \src "issuer_ls180.v:145189.3-145198.6" - wire width 64 $1\x_st_data_i[63:0] - attribute \src "issuer_ls180.v:145349.3-145364.6" - wire $2\adrok_l_r_addr_acked[0:0] - attribute \src "issuer_ls180.v:145313.3-145348.6" - wire $2\adrok_l_s_addr_acked$next[0:0]$7652 - attribute \src "issuer_ls180.v:145297.3-145312.6" - wire $2\busy_l_r_busy[0:0] - attribute \src "issuer_ls180.v:145219.3-145257.6" - wire width 2 $2\fsm_state$next[1:0]$7638 - attribute \src "issuer_ls180.v:145092.3-145122.6" - wire $2\ldst_port0_addr_ok_o[0:0] - attribute \src "issuer_ls180.v:144998.3-145013.6" - wire width 4 $2\lenexp_addr_i[3:0] - attribute \src "issuer_ls180.v:144982.3-144997.6" - wire width 4 $2\lenexp_len_i[3:0] - attribute \src "issuer_ls180.v:145199.3-145218.6" - wire $2\lsui_busy[0:0] - attribute \src "issuer_ls180.v:145123.3-145138.6" - wire $2\reset_l_s_reset[0:0] - attribute \src "issuer_ls180.v:144938.3-144952.6" - wire $2\st_done_s_st_done$next[0:0]$7615 - attribute \src "issuer_ls180.v:145014.3-145039.6" - wire $2\valid_l_s_valid[0:0] - attribute \src "issuer_ls180.v:145066.3-145091.6" - wire width 48 $2\x_addr_i[47:0] - attribute \src "issuer_ls180.v:145040.3-145065.6" - wire width 8 $2\x_mask_i[7:0] - attribute \src "issuer_ls180.v:145313.3-145348.6" - wire $3\adrok_l_s_addr_acked$next[0:0]$7653 - attribute \src "issuer_ls180.v:145219.3-145257.6" - wire width 2 $3\fsm_state$next[1:0]$7639 - attribute \src "issuer_ls180.v:145092.3-145122.6" - wire $3\ldst_port0_addr_ok_o[0:0] - attribute \src "issuer_ls180.v:145014.3-145039.6" - wire $3\valid_l_s_valid[0:0] - attribute \src "issuer_ls180.v:145066.3-145091.6" - wire width 48 $3\x_addr_i[47:0] - attribute \src "issuer_ls180.v:145040.3-145065.6" - wire width 8 $3\x_mask_i[7:0] - attribute \src "issuer_ls180.v:145313.3-145348.6" - wire $4\adrok_l_s_addr_acked$next[0:0]$7654 - attribute \src "issuer_ls180.v:145219.3-145257.6" - wire width 2 $4\fsm_state$next[1:0]$7640 - attribute \src "issuer_ls180.v:145092.3-145122.6" - wire $4\ldst_port0_addr_ok_o[0:0] - attribute \src "issuer_ls180.v:145014.3-145039.6" - wire $4\valid_l_s_valid[0:0] - attribute \src "issuer_ls180.v:145066.3-145091.6" - wire width 48 $4\x_addr_i[47:0] - attribute \src "issuer_ls180.v:145040.3-145065.6" - wire width 8 $4\x_mask_i[7:0] - attribute \src "issuer_ls180.v:145313.3-145348.6" - wire $5\adrok_l_s_addr_acked$next[0:0]$7655 - attribute \src "issuer_ls180.v:145219.3-145257.6" - wire width 2 $5\fsm_state$next[1:0]$7641 - attribute \src "issuer_ls180.v:145092.3-145122.6" - wire $5\ldst_port0_addr_ok_o[0:0] - attribute \src "issuer_ls180.v:145313.3-145348.6" - wire $6\adrok_l_s_addr_acked$next[0:0]$7656 - attribute \src "issuer_ls180.v:144819.18-144819.115" - wire $and$issuer_ls180.v:144819$7562_Y - attribute \src "issuer_ls180.v:144821.18-144821.95" - wire $and$issuer_ls180.v:144821$7564_Y - attribute \src "issuer_ls180.v:144823.17-144823.138" - wire $and$issuer_ls180.v:144823$7566_Y - attribute \src "issuer_ls180.v:144824.18-144824.95" - wire $and$issuer_ls180.v:144824$7567_Y - attribute \src "issuer_ls180.v:144827.18-144827.136" - wire $and$issuer_ls180.v:144827$7572_Y - attribute \src "issuer_ls180.v:144828.18-144828.136" - wire $and$issuer_ls180.v:144828$7573_Y - attribute \src "issuer_ls180.v:144829.18-144829.136" - wire $and$issuer_ls180.v:144829$7574_Y - attribute \src "issuer_ls180.v:144830.18-144830.136" - wire $and$issuer_ls180.v:144830$7575_Y - attribute \src "issuer_ls180.v:144831.18-144831.136" - wire $and$issuer_ls180.v:144831$7576_Y - attribute \src "issuer_ls180.v:144836.18-144836.119" - wire width 176 $and$issuer_ls180.v:144836$7581_Y - attribute \src "issuer_ls180.v:144839.18-144839.136" - wire $and$issuer_ls180.v:144839$7584_Y - attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \busy_l_q_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \busy_l_r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \busy_l_s_busy - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 23 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \cyc_l_q_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \cyc_l_r_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \cyc_l_s_cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" - wire width 2 \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" - wire width 2 \fsm_state$next - attribute \src "issuer_ls180.v:144573.7-144573.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \ld_active_q_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \ld_active_r_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \ld_active_s_ld_active - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" - wire width 64 \lddata - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195" - wire \lds - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \lds_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \lds_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \lds_rise - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" - wire input 18 \ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 48 input 6 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 7 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire output 10 \ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire output 4 \ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 input 5 \ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire input 2 \ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire input 3 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 12 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 13 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 15 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 14 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" - wire width 4 \lenexp_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130" - wire width 4 \lenexp_len_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132" - wire width 64 \lenexp_lexp_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" - wire width 176 \lenexp_rexp_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:107" - wire \lsui_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \lsui_active_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \lsui_active_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \lsui_active_rise - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:46" - wire \lsui_busy - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:62" - wire width 64 input 11 \m_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" - wire output 21 \m_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" - wire \reset_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" - wire \reset_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \reset_l_q_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \reset_l_r_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \reset_l_s_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \st_active_q_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \st_active_r_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \st_active_s_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \st_done_q_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \st_done_r_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \st_done_s_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \st_done_s_st_done$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - wire width 64 \stdata - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:196" - wire \sts - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \sts_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \sts_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \sts_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \valid_l_q_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \valid_l_r_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \valid_l_s_valid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43" - wire width 48 output 9 \x_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:59" - wire input 17 \x_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45" - wire output 19 \x_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:44" - wire width 8 output 8 \x_mask_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:47" - wire width 64 output 16 \x_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:46" - wire output 20 \x_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" - wire output 22 \x_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" - cell $and $and$issuer_ls180.v:144819$7562 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_busy_o - connect \B \$9 - connect \Y $and$issuer_ls180.v:144819$7562_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:144821$7564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \lds - connect \B \$13 - connect \Y $and$issuer_ls180.v:144821$7564_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" - cell $and $and$issuer_ls180.v:144823$7566 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \st_active_q_st_active - connect \B \ldst_port0_st_data_i_ok - connect \Y $and$issuer_ls180.v:144823$7566_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:144824$7567 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sts - connect \B \$17 - connect \Y $and$issuer_ls180.v:144824$7567_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - cell $and $and$issuer_ls180.v:144827$7572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $and$issuer_ls180.v:144827$7572_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - cell $and $and$issuer_ls180.v:144828$7573 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $and$issuer_ls180.v:144828$7573_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - cell $and $and$issuer_ls180.v:144829$7574 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $and$issuer_ls180.v:144829$7574_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - cell $and $and$issuer_ls180.v:144830$7575 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $and$issuer_ls180.v:144830$7575_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" - cell $and $and$issuer_ls180.v:144831$7576 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ld_active_q_ld_active - connect \B \adrok_l_q_addr_acked - connect \Y $and$issuer_ls180.v:144831$7576_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246" - cell $and $and$issuer_ls180.v:144836$7581 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 176 - parameter \Y_WIDTH 176 - connect \A \m_ld_data_o - connect \B \lenexp_rexp_o - connect \Y $and$issuer_ls180.v:144836$7581_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" 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$and$issuer_ls180.v:144842$7587_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" - cell $and $and$issuer_ls180.v:144846$7591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \st_active_q_st_active - connect \B \ldst_port0_st_data_i_ok - connect \Y $and$issuer_ls180.v:144846$7591_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $and$issuer_ls180.v:144848$7593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$63 - connect \B \valid_l_q_valid - connect \Y $and$issuer_ls180.v:144848$7593_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $and$issuer_ls180.v:144850$7595 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$67 - connect \B \valid_l_q_valid - connect \Y $and$issuer_ls180.v:144850$7595_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $and $and$issuer_ls180.v:144854$7599 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$73 - connect \B \$75 - connect \Y $and$issuer_ls180.v:144854$7599_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - cell $and $and$issuer_ls180.v:144855$7600 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $and$issuer_ls180.v:144855$7600_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:144858$7603 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:212" - cell $or $or$issuer_ls180.v:144834$7579 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_is_ld_i - connect \B \ldst_port0_is_st_i - connect \Y $or$issuer_ls180.v:144834$7579_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $or$issuer_ls180.v:144847$7592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_is_ld_i - connect \B \ldst_port0_is_st_i - connect \Y $or$issuer_ls180.v:144847$7592_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $or$issuer_ls180.v:144849$7594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_is_ld_i - connect \B \ldst_port0_is_st_i - connect \Y $or$issuer_ls180.v:144849$7594_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$issuer_ls180.v:144825$7569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $extend$issuer_ls180.v:144825$7568_Y - connect \Y $pos$issuer_ls180.v:144825$7569_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$issuer_ls180.v:144826$7571 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $extend$issuer_ls180.v:144826$7570_Y - connect \Y $pos$issuer_ls180.v:144826$7571_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:260" - cell $sshl $sshl$issuer_ls180.v:144845$7590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 319 - connect \A \ldst_port0_st_data_i - connect \B \$57 - connect \Y $sshl$issuer_ls180.v:144845$7590_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" - cell $sshr $sshr$issuer_ls180.v:144838$7583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 176 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 176 - connect \A \$42 - connect \B \$44 - connect \Y $sshr$issuer_ls180.v:144838$7583_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:144875.11-144882.4" - cell \adrok_l \adrok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_addr_acked \adrok_l_q_addr_acked - connect \qn_addr_acked \adrok_l_qn_addr_acked - connect \r_addr_acked \adrok_l_r_addr_acked - connect \s_addr_acked \adrok_l_s_addr_acked - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:144883.10-144889.4" - cell \busy_l \busy_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_busy \busy_l_q_busy - connect \r_busy \busy_l_r_busy - connect \s_busy \busy_l_s_busy - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:144890.9-144896.4" - cell \cyc_l \cyc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_cyc \cyc_l_q_cyc - connect \r_cyc \cyc_l_r_cyc - connect \s_cyc \cyc_l_s_cyc - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:144897.13-144903.4" - cell \ld_active \ld_active - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_ld_active \ld_active_q_ld_active - connect \r_ld_active \ld_active_r_ld_active - connect \s_ld_active \ld_active_s_ld_active - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:144904.10-144909.4" - cell \lenexp \lenexp - connect \addr_i \lenexp_addr_i - connect \len_i \lenexp_len_i - connect \lexp_o \lenexp_lexp_o - connect \rexp_o \lenexp_rexp_o - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:144910.11-144916.4" - cell \reset_l \reset_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_reset \reset_l_q_reset - connect \r_reset \reset_l_r_reset - connect \s_reset \reset_l_s_reset - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:144917.13-144923.4" - cell \st_active \st_active - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_st_active \st_active_q_st_active - connect \r_st_active \st_active_r_st_active - connect \s_st_active \st_active_s_st_active - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:144924.11-144930.4" - cell \st_done \st_done - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_st_done \st_done_q_st_done - connect \r_st_done \st_done_r_st_done - connect \s_st_done \st_done_s_st_done - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:144931.11-144937.4" - cell \valid_l \valid_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_valid \valid_l_q_valid - connect \r_valid \valid_l_r_valid - connect \s_valid \valid_l_s_valid - end - attribute \src "issuer_ls180.v:144573.7-144573.20" - process $proc$issuer_ls180.v:144573$7658 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:144667.7-144667.34" - process $proc$issuer_ls180.v:144667$7659 - assign { } { } - assign $1\adrok_l_s_addr_acked[0:0] 1'0 - sync always - sync init - update \adrok_l_s_addr_acked $1\adrok_l_s_addr_acked[0:0] - end - attribute \src "issuer_ls180.v:144671.7-144671.24" - process $proc$issuer_ls180.v:144671$7660 - assign { } { } - assign $1\busy_delay[0:0] 1'0 - sync always - sync init - update \busy_delay $1\busy_delay[0:0] - end - attribute \src "issuer_ls180.v:144693.13-144693.29" - process $proc$issuer_ls180.v:144693$7661 - assign { } { } - assign $1\fsm_state[1:0] 2'00 - sync always - sync init - update \fsm_state $1\fsm_state[1:0] - end - attribute \src "issuer_ls180.v:144707.7-144707.21" - process $proc$issuer_ls180.v:144707$7662 - assign { } { } - assign $1\lds_dly[0:0] 1'0 - sync always - sync init - update \lds_dly $1\lds_dly[0:0] - end - attribute \src "issuer_ls180.v:144750.7-144750.29" - process $proc$issuer_ls180.v:144750$7663 - assign { } { } - assign $1\lsui_active_dly[0:0] 1'0 - sync always - sync init - update \lsui_active_dly $1\lsui_active_dly[0:0] - end - attribute \src "issuer_ls180.v:144762.7-144762.25" - process $proc$issuer_ls180.v:144762$7664 - assign { } { } - assign $1\reset_delay[0:0] 1'0 - sync always - sync init - update \reset_delay $1\reset_delay[0:0] - end - attribute \src "issuer_ls180.v:144782.7-144782.31" - process $proc$issuer_ls180.v:144782$7665 - assign { } { } - assign $1\st_done_s_st_done[0:0] 1'0 - sync always - sync init - update \st_done_s_st_done $1\st_done_s_st_done[0:0] - end - attribute \src "issuer_ls180.v:144790.7-144790.21" - process $proc$issuer_ls180.v:144790$7666 - assign { } { } - assign $1\sts_dly[0:0] 1'0 - sync always - sync init - update \sts_dly $1\sts_dly[0:0] - end - attribute \src "issuer_ls180.v:144859.3-144860.47" - process $proc$issuer_ls180.v:144859$7604 - assign { } { } - assign $0\lsui_active_dly[0:0] \lsui_active_dly$next - sync posedge \coresync_clk - update \lsui_active_dly $0\lsui_active_dly[0:0] - end - attribute \src "issuer_ls180.v:144861.3-144862.35" - process $proc$issuer_ls180.v:144861$7605 - assign { } { } - assign $0\fsm_state[1:0] \fsm_state$next - sync posedge \coresync_clk - update \fsm_state $0\fsm_state[1:0] - end - attribute \src "issuer_ls180.v:144863.3-144864.36" - process $proc$issuer_ls180.v:144863$7606 - assign { } { } - assign $0\reset_delay[0:0] \reset_l_q_reset - sync posedge \coresync_clk - update \reset_delay $0\reset_delay[0:0] - end - attribute \src "issuer_ls180.v:144865.3-144866.35" - process $proc$issuer_ls180.v:144865$7607 - assign { } { } - assign $0\sts_dly[0:0] \ldst_port0_is_st_i - sync posedge \coresync_clk - update \sts_dly $0\sts_dly[0:0] - end - attribute \src "issuer_ls180.v:144867.3-144868.35" - process $proc$issuer_ls180.v:144867$7608 - assign { } { } - assign $0\lds_dly[0:0] \ldst_port0_is_ld_i - sync posedge \coresync_clk - update \lds_dly $0\lds_dly[0:0] - end - attribute \src "issuer_ls180.v:144869.3-144870.37" - process $proc$issuer_ls180.v:144869$7609 - assign { } { } - assign $0\busy_delay[0:0] \busy_delay$next - sync posedge \coresync_clk - update \busy_delay $0\busy_delay[0:0] - end - attribute \src "issuer_ls180.v:144871.3-144872.57" - process $proc$issuer_ls180.v:144871$7610 - assign { } { } - assign $0\adrok_l_s_addr_acked[0:0] \adrok_l_s_addr_acked$next - sync posedge \coresync_clk - update \adrok_l_s_addr_acked $0\adrok_l_s_addr_acked[0:0] - end - attribute \src "issuer_ls180.v:144873.3-144874.51" - process $proc$issuer_ls180.v:144873$7611 - assign { } { } - assign $0\st_done_s_st_done[0:0] \st_done_s_st_done$next - sync posedge \coresync_clk - update \st_done_s_st_done $0\st_done_s_st_done[0:0] - end - attribute \src "issuer_ls180.v:144938.3-144952.6" - process $proc$issuer_ls180.v:144938$7612 - assign { } { } - assign { } { } - assign { } { } - assign $0\st_done_s_st_done$next[0:0]$7613 $2\st_done_s_st_done$next[0:0]$7615 - attribute \src "issuer_ls180.v:144939.5-144939.29" - switch \initial - attribute \src "issuer_ls180.v:144939.9-144939.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\st_done_s_st_done$next[0:0]$7614 1'1 - case - assign $1\st_done_s_st_done$next[0:0]$7614 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\st_done_s_st_done$next[0:0]$7615 1'0 - case - assign $2\st_done_s_st_done$next[0:0]$7615 $1\st_done_s_st_done$next[0:0]$7614 - end - sync always - update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$7613 - end - attribute \src "issuer_ls180.v:144953.3-144962.6" - process $proc$issuer_ls180.v:144953$7616 - assign { } { } - assign { } { } - assign $0\st_done_r_st_done[0:0] $1\st_done_r_st_done[0:0] - attribute \src "issuer_ls180.v:144954.5-144954.29" - switch \initial - attribute \src "issuer_ls180.v:144954.9-144954.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:275" - switch \reset_l_q_reset - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\st_done_r_st_done[0:0] 1'1 - case - assign $1\st_done_r_st_done[0:0] 1'0 - end - sync always - update \st_done_r_st_done $0\st_done_r_st_done[0:0] - end - attribute \src "issuer_ls180.v:144963.3-144971.6" - process $proc$issuer_ls180.v:144963$7617 - assign { } { } - assign { } { } - assign $0\busy_delay$next[0:0]$7618 $1\busy_delay$next[0:0]$7619 - attribute \src "issuer_ls180.v:144964.5-144964.29" - switch \initial - attribute \src "issuer_ls180.v:144964.9-144964.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\busy_delay$next[0:0]$7619 1'0 - case - assign $1\busy_delay$next[0:0]$7619 \ldst_port0_busy_o - end - sync always - update \busy_delay$next $0\busy_delay$next[0:0]$7618 - end - attribute \src "issuer_ls180.v:144972.3-144981.6" - process $proc$issuer_ls180.v:144972$7620 - assign { } { } - assign { } { } - assign $0\st_active_r_st_active[0:0] $1\st_active_r_st_active[0:0] - attribute \src "issuer_ls180.v:144973.5-144973.29" - switch \initial - attribute \src "issuer_ls180.v:144973.9-144973.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:275" - switch \reset_l_q_reset - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\st_active_r_st_active[0:0] 1'1 - case - assign $1\st_active_r_st_active[0:0] 1'0 - end - sync always - update \st_active_r_st_active $0\st_active_r_st_active[0:0] - end - attribute \src "issuer_ls180.v:144982.3-144997.6" - process $proc$issuer_ls180.v:144982$7621 - assign { } { } - assign { } { } - assign { } { } - assign $0\lenexp_len_i[3:0] $2\lenexp_len_i[3:0] - attribute \src "issuer_ls180.v:144983.5-144983.29" - switch \initial - attribute \src "issuer_ls180.v:144983.9-144983.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" - switch \ld_active_q_ld_active - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\lenexp_len_i[3:0] \ldst_port0_data_len - case - assign $1\lenexp_len_i[3:0] 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" - switch \st_active_q_st_active - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\lenexp_len_i[3:0] \ldst_port0_data_len - case - assign $2\lenexp_len_i[3:0] $1\lenexp_len_i[3:0] - end - sync always - update \lenexp_len_i $0\lenexp_len_i[3:0] - end - attribute \src "issuer_ls180.v:144998.3-145013.6" - process $proc$issuer_ls180.v:144998$7622 - assign { } { } - assign { } { } - assign { } { } - assign $0\lenexp_addr_i[3:0] $2\lenexp_addr_i[3:0] - attribute \src "issuer_ls180.v:144999.5-144999.29" - switch \initial - attribute \src "issuer_ls180.v:144999.9-144999.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" - switch \ld_active_q_ld_active - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\lenexp_addr_i[3:0] \$21 - case - assign $1\lenexp_addr_i[3:0] 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" - switch \st_active_q_st_active - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\lenexp_addr_i[3:0] \$23 - case - assign $2\lenexp_addr_i[3:0] $1\lenexp_addr_i[3:0] - end - sync always - update \lenexp_addr_i $0\lenexp_addr_i[3:0] - end - attribute \src "issuer_ls180.v:145014.3-145039.6" - process $proc$issuer_ls180.v:145014$7623 - assign { } { } - assign { } { } - assign { } { } - assign $0\valid_l_s_valid[0:0] $3\valid_l_s_valid[0:0] - attribute \src "issuer_ls180.v:145015.5-145015.29" - switch \initial - attribute \src "issuer_ls180.v:145015.9-145015.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" - switch \ld_active_q_ld_active - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\valid_l_s_valid[0:0] $2\valid_l_s_valid[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - switch \$25 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\valid_l_s_valid[0:0] 1'1 - case - assign $2\valid_l_s_valid[0:0] 1'0 - end - case - assign $1\valid_l_s_valid[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" - switch \st_active_q_st_active - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\valid_l_s_valid[0:0] $4\valid_l_s_valid[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" - switch \ldst_port0_addr_i_ok - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\valid_l_s_valid[0:0] 1'1 - case - assign $4\valid_l_s_valid[0:0] $1\valid_l_s_valid[0:0] - end - case - assign $3\valid_l_s_valid[0:0] $1\valid_l_s_valid[0:0] - end - sync always - update \valid_l_s_valid $0\valid_l_s_valid[0:0] - end - attribute \src "issuer_ls180.v:145040.3-145065.6" - process $proc$issuer_ls180.v:145040$7624 - assign { } { } - assign { } { } - assign { } { } - assign $0\x_mask_i[7:0] $3\x_mask_i[7:0] - attribute \src "issuer_ls180.v:145041.5-145041.29" - switch \initial - attribute \src "issuer_ls180.v:145041.9-145041.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" - switch \ld_active_q_ld_active - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\x_mask_i[7:0] $2\x_mask_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - switch \$27 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\x_mask_i[7:0] \lenexp_lexp_o [7:0] - case - assign $2\x_mask_i[7:0] 8'00000000 - end - case - assign $1\x_mask_i[7:0] 8'00000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" - switch \st_active_q_st_active - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\x_mask_i[7:0] $4\x_mask_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" - switch \ldst_port0_addr_i_ok - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\x_mask_i[7:0] \lenexp_lexp_o [7:0] - case - assign $4\x_mask_i[7:0] $1\x_mask_i[7:0] - end - case - assign $3\x_mask_i[7:0] $1\x_mask_i[7:0] - end - sync always - update \x_mask_i $0\x_mask_i[7:0] - end - attribute \src "issuer_ls180.v:145066.3-145091.6" - process $proc$issuer_ls180.v:145066$7625 - assign { } { } - assign { } { } - assign { } { } - assign $0\x_addr_i[47:0] $3\x_addr_i[47:0] - attribute \src "issuer_ls180.v:145067.5-145067.29" - switch \initial - attribute \src "issuer_ls180.v:145067.9-145067.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" - switch \ld_active_q_ld_active - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\x_addr_i[47:0] $2\x_addr_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - switch \$29 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\x_addr_i[47:0] \ldst_port0_addr_i - case - assign $2\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 - end - case - assign $1\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" - switch \st_active_q_st_active - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\x_addr_i[47:0] $4\x_addr_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" - switch \ldst_port0_addr_i_ok - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\x_addr_i[47:0] \ldst_port0_addr_i - case - assign $4\x_addr_i[47:0] $1\x_addr_i[47:0] - end - case - assign $3\x_addr_i[47:0] $1\x_addr_i[47:0] - end - sync always - update \x_addr_i $0\x_addr_i[47:0] - end - attribute \src "issuer_ls180.v:145092.3-145122.6" - process $proc$issuer_ls180.v:145092$7626 - assign { } { } - assign { } { } - assign { } { } - assign $0\ldst_port0_addr_ok_o[0:0] $3\ldst_port0_addr_ok_o[0:0] - attribute \src "issuer_ls180.v:145093.5-145093.29" - switch \initial - attribute \src "issuer_ls180.v:145093.9-145093.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" - switch \ld_active_q_ld_active - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_addr_ok_o[0:0] $2\ldst_port0_addr_ok_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - switch \$31 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ldst_port0_addr_ok_o[0:0] 1'1 - case - assign $2\ldst_port0_addr_ok_o[0:0] 1'0 - end - case - assign $1\ldst_port0_addr_ok_o[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" - switch \st_active_q_st_active - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ldst_port0_addr_ok_o[0:0] $4\ldst_port0_addr_ok_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" - switch \ldst_port0_addr_i_ok - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\ldst_port0_addr_ok_o[0:0] $5\ldst_port0_addr_ok_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236" - switch \adrok_l_qn_addr_acked - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\ldst_port0_addr_ok_o[0:0] 1'1 - case - assign $5\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] - end - case - assign $4\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] - end - case - assign $3\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] - end - sync always - update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] - end - attribute \src "issuer_ls180.v:145123.3-145138.6" - process $proc$issuer_ls180.v:145123$7627 - assign { } { } - assign { } { } - assign { } { } - assign $0\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] - attribute \src "issuer_ls180.v:145124.5-145124.29" - switch \initial - attribute \src "issuer_ls180.v:145124.9-145124.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" - switch \$33 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reset_l_s_reset[0:0] \$35 - case - assign $1\reset_l_s_reset[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:265" - switch \st_done_q_st_done - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reset_l_s_reset[0:0] \$37 - case - assign $2\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] - end - sync always - update \reset_l_s_reset $0\reset_l_s_reset[0:0] - end - attribute \src "issuer_ls180.v:145139.3-145148.6" - process $proc$issuer_ls180.v:145139$7628 - assign { } { } - assign { } { } - assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] - attribute \src "issuer_ls180.v:145140.5-145140.29" - switch \initial - attribute \src "issuer_ls180.v:145140.9-145140.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:275" - switch \reset_l_q_reset - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reset_l_r_reset[0:0] 1'1 - case - assign $1\reset_l_r_reset[0:0] 1'0 - end - sync always - update \reset_l_r_reset $0\reset_l_r_reset[0:0] - end - attribute \src "issuer_ls180.v:145149.3-145158.6" - process $proc$issuer_ls180.v:145149$7629 - assign { } { } - assign { } { } - assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] - attribute \src "issuer_ls180.v:145150.5-145150.29" - switch \initial - attribute \src "issuer_ls180.v:145150.9-145150.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" - switch \$48 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_ld_data_o[63:0] \lddata - case - assign $1\ldst_port0_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] - end - attribute \src "issuer_ls180.v:145159.3-145168.6" - process $proc$issuer_ls180.v:145159$7630 - assign { } { } - assign { } { } - assign $0\ld_active_r_ld_active[0:0] $1\ld_active_r_ld_active[0:0] - attribute \src "issuer_ls180.v:145160.5-145160.29" - switch \initial - attribute \src "issuer_ls180.v:145160.9-145160.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:275" - switch \reset_l_q_reset - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ld_active_r_ld_active[0:0] 1'1 - case - assign $1\ld_active_r_ld_active[0:0] 1'0 - end - sync always - update \ld_active_r_ld_active $0\ld_active_r_ld_active[0:0] - end - attribute \src "issuer_ls180.v:145169.3-145178.6" - process $proc$issuer_ls180.v:145169$7631 - assign { } { } - assign { } { } - assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "issuer_ls180.v:145170.5-145170.29" - switch \initial - attribute \src "issuer_ls180.v:145170.9-145170.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" - switch \$50 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_ld_data_o_ok[0:0] \$52 - case - assign $1\ldst_port0_ld_data_o_ok[0:0] 1'0 - end - sync always - update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] - end - attribute \src "issuer_ls180.v:145179.3-145188.6" - process $proc$issuer_ls180.v:145179$7632 - assign { } { } - assign { } { } - assign $0\stdata[63:0] $1\stdata[63:0] - attribute \src "issuer_ls180.v:145180.5-145180.29" - switch \initial - attribute \src "issuer_ls180.v:145180.9-145180.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" - switch \$54 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\stdata[63:0] \$56 [63:0] - case - assign $1\stdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \stdata $0\stdata[63:0] - end - attribute \src "issuer_ls180.v:145189.3-145198.6" - process $proc$issuer_ls180.v:145189$7633 - assign { } { } - assign { } { } - assign $0\x_st_data_i[63:0] $1\x_st_data_i[63:0] - attribute \src "issuer_ls180.v:145190.5-145190.29" - switch \initial - attribute \src "issuer_ls180.v:145190.9-145190.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" - switch \$61 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\x_st_data_i[63:0] \stdata - case - assign $1\x_st_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \x_st_data_i $0\x_st_data_i[63:0] - end - attribute \src "issuer_ls180.v:145199.3-145218.6" - process $proc$issuer_ls180.v:145199$7634 - assign { } { } - assign { } { } - assign $0\lsui_busy[0:0] $1\lsui_busy[0:0] - attribute \src "issuer_ls180.v:145200.5-145200.29" - switch \initial - attribute \src "issuer_ls180.v:145200.9-145200.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" - switch \fsm_state - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\lsui_busy[0:0] $2\lsui_busy[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - switch \$65 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\lsui_busy[0:0] 1'1 - case - assign $2\lsui_busy[0:0] 1'0 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\lsui_busy[0:0] 1'1 - case - assign $1\lsui_busy[0:0] 1'0 - end - sync always - update \lsui_busy $0\lsui_busy[0:0] - end - attribute \src "issuer_ls180.v:145219.3-145257.6" - process $proc$issuer_ls180.v:145219$7635 - assign { } { } - assign { } { } - assign { } { } - assign $0\fsm_state$next[1:0]$7636 $5\fsm_state$next[1:0]$7641 - attribute \src "issuer_ls180.v:145220.5-145220.29" - switch \initial - attribute \src "issuer_ls180.v:145220.9-145220.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" - switch \fsm_state - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\fsm_state$next[1:0]$7637 $2\fsm_state$next[1:0]$7638 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - switch \$69 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fsm_state$next[1:0]$7638 2'01 - case - assign $2\fsm_state$next[1:0]$7638 \fsm_state - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\fsm_state$next[1:0]$7637 $3\fsm_state$next[1:0]$7639 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" - switch \$71 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fsm_state$next[1:0]$7639 2'10 - case - assign $3\fsm_state$next[1:0]$7639 \fsm_state - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\fsm_state$next[1:0]$7637 $4\fsm_state$next[1:0]$7640 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - switch \$77 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fsm_state$next[1:0]$7640 2'00 - case - assign $4\fsm_state$next[1:0]$7640 \fsm_state - end - case - assign $1\fsm_state$next[1:0]$7637 \fsm_state - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\fsm_state$next[1:0]$7641 2'00 - case - assign $5\fsm_state$next[1:0]$7641 $1\fsm_state$next[1:0]$7637 - end - sync always - update \fsm_state$next $0\fsm_state$next[1:0]$7636 - end - attribute \src "issuer_ls180.v:145258.3-145267.6" - process $proc$issuer_ls180.v:145258$7642 - assign { } { } - assign { } { } - assign $0\cyc_l_s_cyc[0:0] $1\cyc_l_s_cyc[0:0] - attribute \src "issuer_ls180.v:145259.5-145259.29" - switch \initial - attribute \src "issuer_ls180.v:145259.9-145259.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:288" - switch \reset_l_s_reset - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cyc_l_s_cyc[0:0] 1'1 - case - assign $1\cyc_l_s_cyc[0:0] 1'0 - end - sync always - update \cyc_l_s_cyc $0\cyc_l_s_cyc[0:0] - end - attribute \src "issuer_ls180.v:145268.3-145276.6" - process $proc$issuer_ls180.v:145268$7643 - assign { } { } - assign { } { } - assign $0\lsui_active_dly$next[0:0]$7644 $1\lsui_active_dly$next[0:0]$7645 - attribute \src "issuer_ls180.v:145269.5-145269.29" - switch \initial - attribute \src "issuer_ls180.v:145269.9-145269.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\lsui_active_dly$next[0:0]$7645 1'0 - case - assign $1\lsui_active_dly$next[0:0]$7645 \lsui_active - end - sync always - update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$7644 - end - attribute \src "issuer_ls180.v:145277.3-145286.6" - process $proc$issuer_ls180.v:145277$7646 - assign { } { } - assign { } { } - assign $0\cyc_l_r_cyc[0:0] $1\cyc_l_r_cyc[0:0] - attribute \src "issuer_ls180.v:145278.5-145278.29" - switch \initial - attribute \src "issuer_ls180.v:145278.9-145278.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:291" - switch \cyc_l_q_cyc - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cyc_l_r_cyc[0:0] 1'1 - case - assign $1\cyc_l_r_cyc[0:0] 1'0 - end - sync always - update \cyc_l_r_cyc $0\cyc_l_r_cyc[0:0] - end - attribute \src "issuer_ls180.v:145287.3-145296.6" - process $proc$issuer_ls180.v:145287$7647 - assign { } { } - assign { } { } - assign $0\busy_l_s_busy[0:0] $1\busy_l_s_busy[0:0] - attribute \src "issuer_ls180.v:145288.5-145288.29" - switch \initial - attribute \src "issuer_ls180.v:145288.9-145288.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:212" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\busy_l_s_busy[0:0] \$5 - case - assign $1\busy_l_s_busy[0:0] 1'0 - end - sync always - update \busy_l_s_busy $0\busy_l_s_busy[0:0] - end - attribute \src "issuer_ls180.v:145297.3-145312.6" - process $proc$issuer_ls180.v:145297$7648 - assign { } { } - assign { } { } - assign { } { } - assign $0\busy_l_r_busy[0:0] $2\busy_l_r_busy[0:0] - attribute \src "issuer_ls180.v:145298.5-145298.29" - switch \initial - attribute \src "issuer_ls180.v:145298.9-145298.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:283" - switch \ldst_port0_addr_exc_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\busy_l_r_busy[0:0] 1'1 - case - assign $1\busy_l_r_busy[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:291" - switch \cyc_l_q_cyc - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\busy_l_r_busy[0:0] 1'1 - case - assign $2\busy_l_r_busy[0:0] $1\busy_l_r_busy[0:0] - end - sync always - update \busy_l_r_busy $0\busy_l_r_busy[0:0] - end - attribute \src "issuer_ls180.v:145313.3-145348.6" - process $proc$issuer_ls180.v:145313$7649 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\adrok_l_s_addr_acked$next[0:0]$7650 $6\adrok_l_s_addr_acked$next[0:0]$7656 - attribute \src "issuer_ls180.v:145314.5-145314.29" - switch \initial - attribute \src "issuer_ls180.v:145314.9-145314.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" - switch \ld_active_q_ld_active - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\adrok_l_s_addr_acked$next[0:0]$7651 $2\adrok_l_s_addr_acked$next[0:0]$7652 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - switch \$7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\adrok_l_s_addr_acked$next[0:0]$7652 1'1 - case - assign $2\adrok_l_s_addr_acked$next[0:0]$7652 1'0 - end - case - assign $1\adrok_l_s_addr_acked$next[0:0]$7651 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" - switch \st_active_q_st_active - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\adrok_l_s_addr_acked$next[0:0]$7653 $4\adrok_l_s_addr_acked$next[0:0]$7654 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" - switch \ldst_port0_addr_i_ok - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\adrok_l_s_addr_acked$next[0:0]$7654 $5\adrok_l_s_addr_acked$next[0:0]$7655 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236" - switch \adrok_l_qn_addr_acked - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\adrok_l_s_addr_acked$next[0:0]$7655 1'1 - case - assign $5\adrok_l_s_addr_acked$next[0:0]$7655 $1\adrok_l_s_addr_acked$next[0:0]$7651 - end - case - assign $4\adrok_l_s_addr_acked$next[0:0]$7654 $1\adrok_l_s_addr_acked$next[0:0]$7651 - end - case - assign $3\adrok_l_s_addr_acked$next[0:0]$7653 $1\adrok_l_s_addr_acked$next[0:0]$7651 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\adrok_l_s_addr_acked$next[0:0]$7656 1'0 - case - assign $6\adrok_l_s_addr_acked$next[0:0]$7656 $3\adrok_l_s_addr_acked$next[0:0]$7653 - end - sync always - update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$7650 - end - attribute \src "issuer_ls180.v:145349.3-145364.6" - process $proc$issuer_ls180.v:145349$7657 - assign { } { } - assign { } { } - assign { } { } - assign $0\adrok_l_r_addr_acked[0:0] $2\adrok_l_r_addr_acked[0:0] - attribute \src "issuer_ls180.v:145350.5-145350.29" - switch \initial - attribute \src "issuer_ls180.v:145350.9-145350.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - switch \reset_delay - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\adrok_l_r_addr_acked[0:0] 1'1 - case - assign $1\adrok_l_r_addr_acked[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:275" - switch \reset_l_q_reset - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\adrok_l_r_addr_acked[0:0] 1'1 - case - assign $2\adrok_l_r_addr_acked[0:0] $1\adrok_l_r_addr_acked[0:0] - end - sync always - update \adrok_l_r_addr_acked $0\adrok_l_r_addr_acked[0:0] - end - connect \$9 $not$issuer_ls180.v:144818$7561_Y - connect \$11 $and$issuer_ls180.v:144819$7562_Y - connect \$13 $not$issuer_ls180.v:144820$7563_Y - connect \$15 $and$issuer_ls180.v:144821$7564_Y - connect \$17 $not$issuer_ls180.v:144822$7565_Y - connect \$1 $and$issuer_ls180.v:144823$7566_Y - connect \$19 $and$issuer_ls180.v:144824$7567_Y - connect \$21 $pos$issuer_ls180.v:144825$7569_Y - connect \$23 $pos$issuer_ls180.v:144826$7571_Y - connect \$25 $and$issuer_ls180.v:144827$7572_Y - connect \$27 $and$issuer_ls180.v:144828$7573_Y - connect \$29 $and$issuer_ls180.v:144829$7574_Y - connect \$31 $and$issuer_ls180.v:144830$7575_Y - connect \$33 $and$issuer_ls180.v:144831$7576_Y - connect \$35 $not$issuer_ls180.v:144832$7577_Y - connect \$38 $or$issuer_ls180.v:144833$7578_Y - connect \$3 $or$issuer_ls180.v:144834$7579_Y - connect \$37 $not$issuer_ls180.v:144835$7580_Y - connect \$42 $and$issuer_ls180.v:144836$7581_Y - connect \$44 $mul$issuer_ls180.v:144837$7582_Y - connect \$46 $sshr$issuer_ls180.v:144838$7583_Y - connect \$48 $and$issuer_ls180.v:144839$7584_Y - connect \$50 $and$issuer_ls180.v:144840$7585_Y - connect \$52 $not$issuer_ls180.v:144841$7586_Y - connect \$54 $and$issuer_ls180.v:144842$7587_Y - connect \$57 $mul$issuer_ls180.v:144843$7588_Y - connect \$5 $not$issuer_ls180.v:144844$7589_Y - connect \$59 $sshl$issuer_ls180.v:144845$7590_Y - connect \$61 $and$issuer_ls180.v:144846$7591_Y - connect \$63 $or$issuer_ls180.v:144847$7592_Y - connect \$65 $and$issuer_ls180.v:144848$7593_Y - connect \$67 $or$issuer_ls180.v:144849$7594_Y - connect \$69 $and$issuer_ls180.v:144850$7595_Y - connect \$71 $not$issuer_ls180.v:144851$7596_Y - connect \$73 $not$issuer_ls180.v:144852$7597_Y - connect \$75 $not$issuer_ls180.v:144853$7598_Y - connect \$77 $and$issuer_ls180.v:144854$7599_Y - connect \$7 $and$issuer_ls180.v:144855$7600_Y - connect \$79 $not$issuer_ls180.v:144856$7601_Y - connect \$81 $not$issuer_ls180.v:144857$7602_Y - connect \$83 $and$issuer_ls180.v:144858$7603_Y - connect \$41 \$46 - connect \$56 \$59 - connect \valid_l_r_valid \lsui_active_rise - connect \lsui_active_rise \$83 - connect \lsui_active \$79 - connect \x_valid_i \valid_l_q_valid - connect \m_valid_i \valid_l_q_valid - connect \x_st_i \ldst_port0_is_st_i - connect \x_ld_i \ldst_port0_is_ld_i - connect \ldst_port0_busy_o \busy_l_q_busy - connect \reset_delay$next \reset_l_q_reset - connect \lddata \$46 [63:0] - connect \st_active_s_st_active \sts_rise - connect \sts_rise \$19 - connect \sts_dly$next \sts - connect \ld_active_s_ld_active \lds_rise - connect \lds_rise \$15 - connect \lds_dly$next \lds - connect \busy_edge \$11 - connect \sts \ldst_port0_is_st_i - connect \lds \ldst_port0_is_ld_i -end -attribute \src "issuer_ls180.v:145390.1-146155.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe" -attribute \generator "nMigen" -module \pipe - attribute \src "issuer_ls180.v:146118.3-146136.6" - wire width 4 $0\cr_a$6$next[3:0]$7713 - attribute \src "issuer_ls180.v:145982.3-145983.31" - wire width 4 $0\cr_a$6[3:0]$7669 - attribute \src "issuer_ls180.v:145404.13-145404.28" - wire width 4 $0\cr_a$6[3:0]$7719 - attribute \src "issuer_ls180.v:146118.3-146136.6" - wire $0\cr_a_ok$next[0:0]$7712 - attribute \src "issuer_ls180.v:145984.3-145985.31" - wire $0\cr_a_ok[0:0] - attribute \src "issuer_ls180.v:146065.3-146079.6" - wire width 12 $0\cr_op__fn_unit$3$next[11:0]$7693 - attribute \src "issuer_ls180.v:145996.3-145997.51" - wire width 12 $0\cr_op__fn_unit$3[11:0]$7679 - attribute \src "issuer_ls180.v:145463.14-145463.42" - wire width 12 $0\cr_op__fn_unit$3[11:0]$7722 - attribute \src "issuer_ls180.v:146065.3-146079.6" - wire width 32 $0\cr_op__insn$4$next[31:0]$7694 - attribute \src "issuer_ls180.v:145998.3-145999.45" - wire width 32 $0\cr_op__insn$4[31:0]$7681 - attribute \src "issuer_ls180.v:145472.14-145472.37" - wire width 32 $0\cr_op__insn$4[31:0]$7724 - attribute \src "issuer_ls180.v:146065.3-146079.6" - wire width 7 $0\cr_op__insn_type$2$next[6:0]$7695 - attribute \src "issuer_ls180.v:145994.3-145995.55" - wire width 7 $0\cr_op__insn_type$2[6:0]$7677 - attribute \src "issuer_ls180.v:145703.13-145703.41" - wire width 7 $0\cr_op__insn_type$2[6:0]$7726 - attribute \src "issuer_ls180.v:146099.3-146117.6" - wire width 32 $0\full_cr$5$next[31:0]$7706 - attribute \src "issuer_ls180.v:145986.3-145987.37" - wire width 32 $0\full_cr$5[31:0]$7672 - attribute \src "issuer_ls180.v:145712.14-145712.33" - wire width 32 $0\full_cr$5[31:0]$7728 - attribute \src "issuer_ls180.v:146099.3-146117.6" - wire $0\full_cr_ok$next[0:0]$7707 - attribute \src "issuer_ls180.v:145988.3-145989.37" - wire $0\full_cr_ok[0:0] - attribute \src "issuer_ls180.v:145391.7-145391.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:146052.3-146064.6" - wire width 2 $0\muxid$1$next[1:0]$7690 - attribute \src "issuer_ls180.v:146000.3-146001.33" - wire width 2 $0\muxid$1[1:0]$7683 - attribute \src "issuer_ls180.v:145940.13-145940.29" - wire width 2 $0\muxid$1[1:0]$7731 - attribute \src "issuer_ls180.v:146080.3-146098.6" - wire width 64 $0\o$next[63:0]$7700 - attribute \src "issuer_ls180.v:145990.3-145991.19" - wire width 64 $0\o[63:0] - attribute \src "issuer_ls180.v:146080.3-146098.6" - wire $0\o_ok$next[0:0]$7701 - attribute \src "issuer_ls180.v:145992.3-145993.25" - wire $0\o_ok[0:0] - attribute \src "issuer_ls180.v:146034.3-146051.6" - wire $0\r_busy$next[0:0]$7686 - attribute \src "issuer_ls180.v:146002.3-146003.29" - wire $0\r_busy[0:0] - attribute \src "issuer_ls180.v:146118.3-146136.6" - wire width 4 $1\cr_a$6$next[3:0]$7715 - attribute \src "issuer_ls180.v:146118.3-146136.6" - wire $1\cr_a_ok$next[0:0]$7714 - attribute \src "issuer_ls180.v:145409.7-145409.21" - wire $1\cr_a_ok[0:0] - attribute \src "issuer_ls180.v:146065.3-146079.6" - wire width 12 $1\cr_op__fn_unit$3$next[11:0]$7696 - attribute \src "issuer_ls180.v:146065.3-146079.6" - wire width 32 $1\cr_op__insn$4$next[31:0]$7697 - attribute \src "issuer_ls180.v:146065.3-146079.6" - wire width 7 $1\cr_op__insn_type$2$next[6:0]$7698 - attribute \src "issuer_ls180.v:146099.3-146117.6" - wire width 32 $1\full_cr$5$next[31:0]$7708 - attribute \src "issuer_ls180.v:146099.3-146117.6" - wire $1\full_cr_ok$next[0:0]$7709 - attribute \src "issuer_ls180.v:145717.7-145717.24" - wire $1\full_cr_ok[0:0] - attribute \src "issuer_ls180.v:146052.3-146064.6" - wire width 2 $1\muxid$1$next[1:0]$7691 - attribute \src "issuer_ls180.v:146080.3-146098.6" - wire width 64 $1\o$next[63:0]$7702 - attribute \src "issuer_ls180.v:145953.14-145953.38" - wire width 64 $1\o[63:0] - attribute \src "issuer_ls180.v:146080.3-146098.6" - wire $1\o_ok$next[0:0]$7703 - attribute \src "issuer_ls180.v:145960.7-145960.18" - wire $1\o_ok[0:0] - attribute \src "issuer_ls180.v:146034.3-146051.6" - wire $1\r_busy$next[0:0]$7687 - attribute \src "issuer_ls180.v:145974.7-145974.20" - wire $1\r_busy[0:0] - attribute \src "issuer_ls180.v:146118.3-146136.6" - wire $2\cr_a_ok$next[0:0]$7716 - attribute \src "issuer_ls180.v:146099.3-146117.6" - wire $2\full_cr_ok$next[0:0]$7710 - attribute \src "issuer_ls180.v:146080.3-146098.6" - wire $2\o_ok$next[0:0]$7704 - attribute \src "issuer_ls180.v:146034.3-146051.6" - wire $2\r_busy$next[0:0]$7688 - attribute \src "issuer_ls180.v:145981.18-145981.118" - wire $and$issuer_ls180.v:145981$7667_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 26 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 11 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 24 \cr_a$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 25 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 12 \cr_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 13 \cr_c - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \cr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \cr_op__fn_unit$18 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 18 \cr_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \cr_op__fn_unit$3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 7 \cr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \cr_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 19 \cr_op__insn$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \cr_op__insn$4$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute 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attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute 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"OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \cr_op__insn_type$17 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 17 \cr_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \cr_op__insn_type$2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 input 10 \full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 \full_cr$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 output 22 \full_cr$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 \full_cr$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 23 \full_cr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \full_cr_ok$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \full_cr_ok$next - attribute \src "issuer_ls180.v:145391.7-145391.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \main_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \main_cr_a$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \main_cr_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \main_cr_c - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_cr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_cr_op__fn_unit$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_cr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_cr_op__insn$10 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_cr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_cr_op__insn_type$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 \main_full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 \main_full_cr$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_full_cr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 16 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 15 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 14 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 20 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 21 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 8 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 9 \rb - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$issuer_ls180.v:145981$7667 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$13 - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:145981$7667_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:146004.12-146025.4" - cell \main$9 \main - connect \cr_a \main_cr_a - connect \cr_a$6 \main_cr_a$12 - connect \cr_a_ok \main_cr_a_ok - connect \cr_b \main_cr_b - connect \cr_c \main_cr_c - connect \cr_op__fn_unit \main_cr_op__fn_unit - connect \cr_op__fn_unit$3 \main_cr_op__fn_unit$9 - connect \cr_op__insn \main_cr_op__insn - connect \cr_op__insn$4 \main_cr_op__insn$10 - connect \cr_op__insn_type \main_cr_op__insn_type - connect \cr_op__insn_type$2 \main_cr_op__insn_type$8 - connect \full_cr \main_full_cr - connect \full_cr$5 \main_full_cr$11 - connect \full_cr_ok \main_full_cr_ok - connect \muxid \main_muxid - connect \muxid$1 \main_muxid$7 - connect \o \main_o - connect \o_ok \main_o_ok - connect \ra \main_ra - connect \rb \main_rb - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:146026.9-146029.4" - cell \n$8 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:146030.9-146033.4" - cell \p$7 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "issuer_ls180.v:145391.7-145391.20" - process $proc$issuer_ls180.v:145391$7717 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:145404.13-145404.28" - process $proc$issuer_ls180.v:145404$7718 - assign { } { } - assign $0\cr_a$6[3:0]$7719 4'0000 - sync always - sync init - update \cr_a$6 $0\cr_a$6[3:0]$7719 - end - attribute \src "issuer_ls180.v:145409.7-145409.21" - process $proc$issuer_ls180.v:145409$7720 - assign { } { } - assign $1\cr_a_ok[0:0] 1'0 - sync always - sync init - update \cr_a_ok $1\cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:145463.14-145463.42" - process $proc$issuer_ls180.v:145463$7721 - assign { } { } - assign $0\cr_op__fn_unit$3[11:0]$7722 12'000000000000 - sync always - sync init - update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[11:0]$7722 - end - attribute \src "issuer_ls180.v:145472.14-145472.37" - process $proc$issuer_ls180.v:145472$7723 - assign { } { } - assign $0\cr_op__insn$4[31:0]$7724 0 - sync always - sync init - update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$7724 - end - attribute \src "issuer_ls180.v:145703.13-145703.41" - process $proc$issuer_ls180.v:145703$7725 - assign { } { } - assign $0\cr_op__insn_type$2[6:0]$7726 7'0000000 - sync always - sync init - update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$7726 - end - attribute \src "issuer_ls180.v:145712.14-145712.33" - process $proc$issuer_ls180.v:145712$7727 - assign { } { } - assign $0\full_cr$5[31:0]$7728 0 - sync always - sync init - update \full_cr$5 $0\full_cr$5[31:0]$7728 - end - attribute \src "issuer_ls180.v:145717.7-145717.24" - process $proc$issuer_ls180.v:145717$7729 - assign { } { } - assign $1\full_cr_ok[0:0] 1'0 - sync always - sync init - update \full_cr_ok $1\full_cr_ok[0:0] - end - attribute \src "issuer_ls180.v:145940.13-145940.29" - process $proc$issuer_ls180.v:145940$7730 - assign { } { } - assign $0\muxid$1[1:0]$7731 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$7731 - end - attribute \src "issuer_ls180.v:145953.14-145953.38" - process $proc$issuer_ls180.v:145953$7732 - assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o $1\o[63:0] - end - attribute \src "issuer_ls180.v:145960.7-145960.18" - process $proc$issuer_ls180.v:145960$7733 - assign { } { } - assign $1\o_ok[0:0] 1'0 - sync always - sync init - update \o_ok $1\o_ok[0:0] - end - attribute \src "issuer_ls180.v:145974.7-145974.20" - process $proc$issuer_ls180.v:145974$7734 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "issuer_ls180.v:145982.3-145983.31" - process $proc$issuer_ls180.v:145982$7668 - assign { } { } - assign $0\cr_a$6[3:0]$7669 \cr_a$6$next - sync posedge \coresync_clk - update \cr_a$6 $0\cr_a$6[3:0]$7669 - end - attribute \src "issuer_ls180.v:145984.3-145985.31" - process $proc$issuer_ls180.v:145984$7670 - assign { } { } - assign $0\cr_a_ok[0:0] \cr_a_ok$next - sync posedge \coresync_clk - update \cr_a_ok $0\cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:145986.3-145987.37" - process $proc$issuer_ls180.v:145986$7671 - assign { } { } - assign $0\full_cr$5[31:0]$7672 \full_cr$5$next - sync posedge \coresync_clk - update \full_cr$5 $0\full_cr$5[31:0]$7672 - end - attribute \src "issuer_ls180.v:145988.3-145989.37" - process $proc$issuer_ls180.v:145988$7673 - assign { } { } - assign $0\full_cr_ok[0:0] \full_cr_ok$next - sync posedge \coresync_clk - update \full_cr_ok $0\full_cr_ok[0:0] - end - attribute \src "issuer_ls180.v:145990.3-145991.19" - process $proc$issuer_ls180.v:145990$7674 - assign { } { } - assign $0\o[63:0] \o$next - sync posedge \coresync_clk - update \o $0\o[63:0] - end - attribute \src "issuer_ls180.v:145992.3-145993.25" - process $proc$issuer_ls180.v:145992$7675 - assign { } { } - assign $0\o_ok[0:0] \o_ok$next - sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] - end - attribute \src "issuer_ls180.v:145994.3-145995.55" - process $proc$issuer_ls180.v:145994$7676 - assign { } { } - assign $0\cr_op__insn_type$2[6:0]$7677 \cr_op__insn_type$2$next - sync posedge \coresync_clk - update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$7677 - end - attribute \src "issuer_ls180.v:145996.3-145997.51" - process $proc$issuer_ls180.v:145996$7678 - assign { } { } - assign $0\cr_op__fn_unit$3[11:0]$7679 \cr_op__fn_unit$3$next - sync posedge \coresync_clk - update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[11:0]$7679 - end - attribute \src "issuer_ls180.v:145998.3-145999.45" - process $proc$issuer_ls180.v:145998$7680 - assign { } { } - assign $0\cr_op__insn$4[31:0]$7681 \cr_op__insn$4$next - sync posedge \coresync_clk - update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$7681 - end - attribute \src "issuer_ls180.v:146000.3-146001.33" - process $proc$issuer_ls180.v:146000$7682 - assign { } { } - assign $0\muxid$1[1:0]$7683 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$7683 - end - attribute \src "issuer_ls180.v:146002.3-146003.29" - process $proc$issuer_ls180.v:146002$7684 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "issuer_ls180.v:146034.3-146051.6" - process $proc$issuer_ls180.v:146034$7685 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$7686 $2\r_busy$next[0:0]$7688 - attribute \src "issuer_ls180.v:146035.5-146035.29" - switch \initial - attribute \src "issuer_ls180.v:146035.9-146035.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$7687 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\r_busy$next[0:0]$7687 1'0 - case - assign $1\r_busy$next[0:0]$7687 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$7688 1'0 - case - assign $2\r_busy$next[0:0]$7688 $1\r_busy$next[0:0]$7687 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$7686 - end - attribute \src "issuer_ls180.v:146052.3-146064.6" - process $proc$issuer_ls180.v:146052$7689 - assign { } { } - assign { } { } - assign $0\muxid$1$next[1:0]$7690 $1\muxid$1$next[1:0]$7691 - attribute \src "issuer_ls180.v:146053.5-146053.29" - switch \initial - attribute \src "issuer_ls180.v:146053.9-146053.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$1$next[1:0]$7691 \muxid$16 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$1$next[1:0]$7691 \muxid$16 - case - assign $1\muxid$1$next[1:0]$7691 \muxid$1 - end - sync always - update \muxid$1$next $0\muxid$1$next[1:0]$7690 - end - attribute \src "issuer_ls180.v:146065.3-146079.6" - process $proc$issuer_ls180.v:146065$7692 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_op__fn_unit$3$next[11:0]$7693 $1\cr_op__fn_unit$3$next[11:0]$7696 - assign $0\cr_op__insn$4$next[31:0]$7694 $1\cr_op__insn$4$next[31:0]$7697 - assign $0\cr_op__insn_type$2$next[6:0]$7695 $1\cr_op__insn_type$2$next[6:0]$7698 - attribute \src "issuer_ls180.v:146066.5-146066.29" - switch \initial - attribute \src "issuer_ls180.v:146066.9-146066.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { $1\cr_op__insn$4$next[31:0]$7697 $1\cr_op__fn_unit$3$next[11:0]$7696 $1\cr_op__insn_type$2$next[6:0]$7698 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { $1\cr_op__insn$4$next[31:0]$7697 $1\cr_op__fn_unit$3$next[11:0]$7696 $1\cr_op__insn_type$2$next[6:0]$7698 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } - case - assign $1\cr_op__fn_unit$3$next[11:0]$7696 \cr_op__fn_unit$3 - assign $1\cr_op__insn$4$next[31:0]$7697 \cr_op__insn$4 - assign $1\cr_op__insn_type$2$next[6:0]$7698 \cr_op__insn_type$2 - end - sync always - update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[11:0]$7693 - update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$7694 - update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$7695 - end - attribute \src "issuer_ls180.v:146080.3-146098.6" - process $proc$issuer_ls180.v:146080$7699 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$next[63:0]$7700 $1\o$next[63:0]$7702 - assign { } { } - assign $0\o_ok$next[0:0]$7701 $2\o_ok$next[0:0]$7704 - attribute \src "issuer_ls180.v:146081.5-146081.29" - switch \initial - attribute \src "issuer_ls180.v:146081.9-146081.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$7703 $1\o$next[63:0]$7702 } { \o_ok$21 \o$20 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$7703 $1\o$next[63:0]$7702 } { \o_ok$21 \o$20 } - case - assign $1\o$next[63:0]$7702 \o - assign $1\o_ok$next[0:0]$7703 \o_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o_ok$next[0:0]$7704 1'0 - case - assign $2\o_ok$next[0:0]$7704 $1\o_ok$next[0:0]$7703 - end - sync always - update \o$next $0\o$next[63:0]$7700 - update \o_ok$next $0\o_ok$next[0:0]$7701 - end - attribute \src "issuer_ls180.v:146099.3-146117.6" - process $proc$issuer_ls180.v:146099$7705 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\full_cr$5$next[31:0]$7706 $1\full_cr$5$next[31:0]$7708 - assign { } { } - assign $0\full_cr_ok$next[0:0]$7707 $2\full_cr_ok$next[0:0]$7710 - attribute \src "issuer_ls180.v:146100.5-146100.29" - switch \initial - attribute \src "issuer_ls180.v:146100.9-146100.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\full_cr_ok$next[0:0]$7709 $1\full_cr$5$next[31:0]$7708 } { \full_cr_ok$23 \full_cr$22 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\full_cr_ok$next[0:0]$7709 $1\full_cr$5$next[31:0]$7708 } { \full_cr_ok$23 \full_cr$22 } - case - assign $1\full_cr$5$next[31:0]$7708 \full_cr$5 - assign $1\full_cr_ok$next[0:0]$7709 \full_cr_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\full_cr_ok$next[0:0]$7710 1'0 - case - assign $2\full_cr_ok$next[0:0]$7710 $1\full_cr_ok$next[0:0]$7709 - end - sync always - update \full_cr$5$next $0\full_cr$5$next[31:0]$7706 - update \full_cr_ok$next $0\full_cr_ok$next[0:0]$7707 - end - attribute \src "issuer_ls180.v:146118.3-146136.6" - process $proc$issuer_ls180.v:146118$7711 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$6$next[3:0]$7713 $1\cr_a$6$next[3:0]$7715 - assign $0\cr_a_ok$next[0:0]$7712 $2\cr_a_ok$next[0:0]$7716 - attribute \src "issuer_ls180.v:146119.5-146119.29" - switch \initial - attribute \src "issuer_ls180.v:146119.9-146119.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$7714 $1\cr_a$6$next[3:0]$7715 } { \cr_a_ok$25 \cr_a$24 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$7714 $1\cr_a$6$next[3:0]$7715 } { \cr_a_ok$25 \cr_a$24 } - case - assign $1\cr_a_ok$next[0:0]$7714 \cr_a_ok - assign $1\cr_a$6$next[3:0]$7715 \cr_a$6 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_a_ok$next[0:0]$7716 1'0 - case - assign $2\cr_a_ok$next[0:0]$7716 $1\cr_a_ok$next[0:0]$7714 - end - sync always - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$7712 - update \cr_a$6$next $0\cr_a$6$next[3:0]$7713 - end - connect \$14 $and$issuer_ls180.v:145981$7667_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \cr_a_ok$25 \cr_a$24 } { \main_cr_a_ok \main_cr_a$12 } - connect { \full_cr_ok$23 \full_cr$22 } { \main_full_cr_ok \main_full_cr$11 } - connect { \o_ok$21 \o$20 } { \main_o_ok \main_o } - connect { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } { \main_cr_op__insn$10 \main_cr_op__fn_unit$9 \main_cr_op__insn_type$8 } - connect \muxid$16 \main_muxid$7 - connect \p_valid_i_p_ready_o \$14 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$13 \p_valid_i - connect \main_cr_c \cr_c - connect \main_cr_b \cr_b - connect \main_cr_a \cr_a - connect \main_full_cr \full_cr - connect \main_rb \rb - connect \main_ra \ra - connect { \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } - connect \main_muxid \muxid -end -attribute \src "issuer_ls180.v:146159.1-147004.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe" -attribute \generator "nMigen" -module \pipe$19 - attribute \src "issuer_ls180.v:146904.3-146931.6" - wire width 64 $0\br_op__cia$2$next[63:0]$7771 - attribute \src "issuer_ls180.v:146816.3-146817.43" - wire width 64 $0\br_op__cia$2[63:0]$7745 - attribute \src "issuer_ls180.v:146167.14-146167.51" - wire width 64 $0\br_op__cia$2[63:0]$7809 - attribute \src "issuer_ls180.v:146904.3-146931.6" - wire width 12 $0\br_op__fn_unit$4$next[11:0]$7772 - attribute \src "issuer_ls180.v:146820.3-146821.51" - wire width 12 $0\br_op__fn_unit$4[11:0]$7749 - attribute \src "issuer_ls180.v:146217.14-146217.42" - wire width 12 $0\br_op__fn_unit$4[11:0]$7811 - attribute \src "issuer_ls180.v:146904.3-146931.6" - wire width 64 $0\br_op__imm_data__data$6$next[63:0]$7773 - attribute \src "issuer_ls180.v:146824.3-146825.65" - wire width 64 $0\br_op__imm_data__data$6[63:0]$7753 - attribute \src "issuer_ls180.v:146226.14-146226.62" - wire width 64 $0\br_op__imm_data__data$6[63:0]$7813 - attribute \src "issuer_ls180.v:146904.3-146931.6" - wire $0\br_op__imm_data__ok$7$next[0:0]$7774 - attribute \src "issuer_ls180.v:146826.3-146827.61" - wire $0\br_op__imm_data__ok$7[0:0]$7755 - attribute \src "issuer_ls180.v:146235.7-146235.37" - wire $0\br_op__imm_data__ok$7[0:0]$7815 - attribute \src "issuer_ls180.v:146904.3-146931.6" - wire width 32 $0\br_op__insn$5$next[31:0]$7775 - attribute \src "issuer_ls180.v:146822.3-146823.45" - wire width 32 $0\br_op__insn$5[31:0]$7751 - attribute \src "issuer_ls180.v:146244.14-146244.37" - wire width 32 $0\br_op__insn$5[31:0]$7817 - attribute \src "issuer_ls180.v:146904.3-146931.6" - wire width 7 $0\br_op__insn_type$3$next[6:0]$7776 - attribute \src "issuer_ls180.v:146818.3-146819.55" - wire width 7 $0\br_op__insn_type$3[6:0]$7747 - attribute \src "issuer_ls180.v:146475.13-146475.41" - wire width 7 $0\br_op__insn_type$3[6:0]$7819 - attribute \src "issuer_ls180.v:146904.3-146931.6" - wire $0\br_op__is_32bit$9$next[0:0]$7777 - attribute \src "issuer_ls180.v:146830.3-146831.53" - wire $0\br_op__is_32bit$9[0:0]$7759 - attribute \src "issuer_ls180.v:146484.7-146484.33" - wire $0\br_op__is_32bit$9[0:0]$7821 - attribute \src "issuer_ls180.v:146904.3-146931.6" - wire $0\br_op__lk$8$next[0:0]$7778 - attribute \src "issuer_ls180.v:146828.3-146829.41" - wire $0\br_op__lk$8[0:0]$7757 - attribute \src "issuer_ls180.v:146493.7-146493.27" - wire $0\br_op__lk$8[0:0]$7823 - attribute \src "issuer_ls180.v:146932.3-146950.6" - wire width 64 $0\fast1$10$next[63:0]$7790 - attribute \src "issuer_ls180.v:146812.3-146813.35" - wire width 64 $0\fast1$10[63:0]$7742 - attribute \src "issuer_ls180.v:146506.14-146506.47" - wire width 64 $0\fast1$10[63:0]$7825 - attribute \src "issuer_ls180.v:146932.3-146950.6" - wire $0\fast1_ok$next[0:0]$7791 - attribute \src "issuer_ls180.v:146814.3-146815.33" - wire $0\fast1_ok[0:0] - attribute \src "issuer_ls180.v:146951.3-146969.6" - wire width 64 $0\fast2$11$next[63:0]$7796 - attribute \src "issuer_ls180.v:146808.3-146809.35" - wire width 64 $0\fast2$11[63:0]$7739 - attribute \src "issuer_ls180.v:146522.14-146522.47" - wire width 64 $0\fast2$11[63:0]$7828 - attribute \src "issuer_ls180.v:146951.3-146969.6" - wire $0\fast2_ok$next[0:0]$7797 - attribute \src "issuer_ls180.v:146810.3-146811.33" - wire $0\fast2_ok[0:0] - attribute \src "issuer_ls180.v:146160.7-146160.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:146891.3-146903.6" - wire width 2 $0\muxid$1$next[1:0]$7768 - attribute \src "issuer_ls180.v:146832.3-146833.33" - wire width 2 $0\muxid$1[1:0]$7761 - attribute \src "issuer_ls180.v:146766.13-146766.29" - wire width 2 $0\muxid$1[1:0]$7831 - attribute \src "issuer_ls180.v:146970.3-146988.6" - wire width 64 $0\nia$next[63:0]$7802 - attribute \src "issuer_ls180.v:146804.3-146805.23" - wire width 64 $0\nia[63:0] - attribute \src "issuer_ls180.v:146970.3-146988.6" - wire $0\nia_ok$next[0:0]$7803 - attribute \src "issuer_ls180.v:146806.3-146807.29" - wire $0\nia_ok[0:0] - attribute \src "issuer_ls180.v:146873.3-146890.6" - wire $0\r_busy$next[0:0]$7764 - attribute \src "issuer_ls180.v:146834.3-146835.29" - wire $0\r_busy[0:0] - attribute \src "issuer_ls180.v:146904.3-146931.6" - wire width 64 $1\br_op__cia$2$next[63:0]$7779 - attribute \src "issuer_ls180.v:146904.3-146931.6" - wire width 12 $1\br_op__fn_unit$4$next[11:0]$7780 - attribute \src "issuer_ls180.v:146904.3-146931.6" - wire width 64 $1\br_op__imm_data__data$6$next[63:0]$7781 - attribute \src "issuer_ls180.v:146904.3-146931.6" - wire $1\br_op__imm_data__ok$7$next[0:0]$7782 - attribute \src "issuer_ls180.v:146904.3-146931.6" - wire width 32 $1\br_op__insn$5$next[31:0]$7783 - attribute \src "issuer_ls180.v:146904.3-146931.6" - wire width 7 $1\br_op__insn_type$3$next[6:0]$7784 - attribute \src "issuer_ls180.v:146904.3-146931.6" - wire $1\br_op__is_32bit$9$next[0:0]$7785 - attribute \src "issuer_ls180.v:146904.3-146931.6" - wire $1\br_op__lk$8$next[0:0]$7786 - attribute \src "issuer_ls180.v:146932.3-146950.6" - wire width 64 $1\fast1$10$next[63:0]$7792 - attribute \src "issuer_ls180.v:146932.3-146950.6" - wire $1\fast1_ok$next[0:0]$7793 - attribute \src "issuer_ls180.v:146513.7-146513.22" - wire $1\fast1_ok[0:0] - attribute \src "issuer_ls180.v:146951.3-146969.6" - wire width 64 $1\fast2$11$next[63:0]$7798 - attribute \src "issuer_ls180.v:146951.3-146969.6" - wire $1\fast2_ok$next[0:0]$7799 - attribute \src "issuer_ls180.v:146529.7-146529.22" - wire $1\fast2_ok[0:0] - attribute \src "issuer_ls180.v:146891.3-146903.6" - wire width 2 $1\muxid$1$next[1:0]$7769 - attribute \src "issuer_ls180.v:146970.3-146988.6" - wire width 64 $1\nia$next[63:0]$7804 - attribute \src "issuer_ls180.v:146779.14-146779.40" - wire width 64 $1\nia[63:0] - attribute \src "issuer_ls180.v:146970.3-146988.6" - wire $1\nia_ok$next[0:0]$7805 - attribute \src "issuer_ls180.v:146786.7-146786.20" - wire $1\nia_ok[0:0] - attribute \src "issuer_ls180.v:146873.3-146890.6" - wire $1\r_busy$next[0:0]$7765 - attribute \src "issuer_ls180.v:146800.7-146800.20" - wire $1\r_busy[0:0] - attribute \src "issuer_ls180.v:146904.3-146931.6" - wire width 64 $2\br_op__imm_data__data$6$next[63:0]$7787 - attribute \src "issuer_ls180.v:146904.3-146931.6" - wire $2\br_op__imm_data__ok$7$next[0:0]$7788 - attribute \src "issuer_ls180.v:146932.3-146950.6" - wire $2\fast1_ok$next[0:0]$7794 - attribute \src "issuer_ls180.v:146951.3-146969.6" - wire $2\fast2_ok$next[0:0]$7800 - attribute \src "issuer_ls180.v:146970.3-146988.6" - wire $2\nia_ok$next[0:0]$7806 - attribute \src "issuer_ls180.v:146873.3-146890.6" - wire $2\r_busy$next[0:0]$7766 - attribute \src "issuer_ls180.v:146803.18-146803.118" - wire $and$issuer_ls180.v:146803$7735_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 5 \br_op__cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 19 \br_op__cia$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \br_op__cia$2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \br_op__cia$27 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 7 \br_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \br_op__fn_unit$29 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 21 \br_op__fn_unit$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \br_op__fn_unit$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 9 \br_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \br_op__imm_data__data$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 23 \br_op__imm_data__data$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \br_op__imm_data__data$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \br_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \br_op__imm_data__ok$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 24 \br_op__imm_data__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \br_op__imm_data__ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 8 \br_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \br_op__insn$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 22 \br_op__insn$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \br_op__insn$5$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 6 \br_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \br_op__insn_type$28 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute 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"OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 20 \br_op__insn_type$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \br_op__insn_type$3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \br_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \br_op__is_32bit$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \br_op__is_32bit$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \br_op__is_32bit$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \br_op__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \br_op__lk$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 25 \br_op__lk$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \br_op__lk$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 33 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 15 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 13 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 27 \fast1$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast1$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast1$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 28 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fast1_ok$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fast1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 14 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 29 \fast2$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast2$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast2$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 30 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fast2_ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fast2_ok$next - attribute \src "issuer_ls180.v:146160.7-146160.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_br_op__cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_br_op__cia$13 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_br_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_br_op__fn_unit$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_br_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_br_op__imm_data__data$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_br_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_br_op__imm_data__ok$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_br_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_br_op__insn$16 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute 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\enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_br_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_br_op__insn_type$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_br_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_br_op__is_32bit$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_br_op__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_br_op__lk$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \main_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_fast1$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_fast2$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_fast2_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_nia_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 18 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 17 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 16 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 31 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \nia$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \nia$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 32 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \nia_ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \nia_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$issuer_ls180.v:146803$7735 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$23 - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:146803$7735_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:146836.13-146864.4" - cell \main$22 \main - connect \br_op__cia \main_br_op__cia - connect \br_op__cia$2 \main_br_op__cia$13 - connect \br_op__fn_unit \main_br_op__fn_unit - connect \br_op__fn_unit$4 \main_br_op__fn_unit$15 - connect \br_op__imm_data__data \main_br_op__imm_data__data - connect \br_op__imm_data__data$6 \main_br_op__imm_data__data$17 - connect \br_op__imm_data__ok \main_br_op__imm_data__ok - connect \br_op__imm_data__ok$7 \main_br_op__imm_data__ok$18 - connect \br_op__insn \main_br_op__insn - connect \br_op__insn$5 \main_br_op__insn$16 - connect \br_op__insn_type \main_br_op__insn_type - connect \br_op__insn_type$3 \main_br_op__insn_type$14 - connect \br_op__is_32bit \main_br_op__is_32bit - connect \br_op__is_32bit$9 \main_br_op__is_32bit$20 - connect \br_op__lk \main_br_op__lk - connect \br_op__lk$8 \main_br_op__lk$19 - connect \cr_a \main_cr_a - connect \fast1 \main_fast1 - connect \fast1$10 \main_fast1$21 - connect \fast1_ok \main_fast1_ok - connect \fast2 \main_fast2 - connect \fast2$11 \main_fast2$22 - connect \fast2_ok \main_fast2_ok - connect \muxid \main_muxid - connect \muxid$1 \main_muxid$12 - connect \nia \main_nia - connect \nia_ok \main_nia_ok - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:146865.10-146868.4" - cell \n$21 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:146869.10-146872.4" - cell \p$20 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "issuer_ls180.v:146160.7-146160.20" - process $proc$issuer_ls180.v:146160$7807 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:146167.14-146167.51" - process $proc$issuer_ls180.v:146167$7808 - assign { } { } - assign $0\br_op__cia$2[63:0]$7809 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \br_op__cia$2 $0\br_op__cia$2[63:0]$7809 - end - attribute \src "issuer_ls180.v:146217.14-146217.42" - process $proc$issuer_ls180.v:146217$7810 - assign { } { } - assign $0\br_op__fn_unit$4[11:0]$7811 12'000000000000 - sync always - sync init - update \br_op__fn_unit$4 $0\br_op__fn_unit$4[11:0]$7811 - end - attribute \src "issuer_ls180.v:146226.14-146226.62" - process $proc$issuer_ls180.v:146226$7812 - assign { } { } - assign $0\br_op__imm_data__data$6[63:0]$7813 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$7813 - end - attribute \src "issuer_ls180.v:146235.7-146235.37" - process $proc$issuer_ls180.v:146235$7814 - assign { } { } - assign $0\br_op__imm_data__ok$7[0:0]$7815 1'0 - sync always - sync init - update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$7815 - end - attribute \src "issuer_ls180.v:146244.14-146244.37" - process $proc$issuer_ls180.v:146244$7816 - assign { } { } - assign $0\br_op__insn$5[31:0]$7817 0 - sync always - sync init - update \br_op__insn$5 $0\br_op__insn$5[31:0]$7817 - end - attribute \src "issuer_ls180.v:146475.13-146475.41" - process $proc$issuer_ls180.v:146475$7818 - assign { } { } - assign $0\br_op__insn_type$3[6:0]$7819 7'0000000 - sync always - sync init - update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$7819 - end - attribute \src "issuer_ls180.v:146484.7-146484.33" - process $proc$issuer_ls180.v:146484$7820 - assign { } { } - assign $0\br_op__is_32bit$9[0:0]$7821 1'0 - sync always - sync init - update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$7821 - end - attribute \src "issuer_ls180.v:146493.7-146493.27" - process $proc$issuer_ls180.v:146493$7822 - assign { } { } - assign $0\br_op__lk$8[0:0]$7823 1'0 - sync always - sync init - update \br_op__lk$8 $0\br_op__lk$8[0:0]$7823 - end - attribute \src "issuer_ls180.v:146506.14-146506.47" - process $proc$issuer_ls180.v:146506$7824 - assign { } { } - assign $0\fast1$10[63:0]$7825 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \fast1$10 $0\fast1$10[63:0]$7825 - end - attribute \src "issuer_ls180.v:146513.7-146513.22" - process $proc$issuer_ls180.v:146513$7826 - assign { } { } - assign $1\fast1_ok[0:0] 1'0 - sync always - sync init - update \fast1_ok $1\fast1_ok[0:0] - end - attribute \src "issuer_ls180.v:146522.14-146522.47" - process $proc$issuer_ls180.v:146522$7827 - assign { } { } - assign $0\fast2$11[63:0]$7828 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \fast2$11 $0\fast2$11[63:0]$7828 - end - attribute \src "issuer_ls180.v:146529.7-146529.22" - process $proc$issuer_ls180.v:146529$7829 - assign { } { } - assign $1\fast2_ok[0:0] 1'0 - sync always - sync init - update \fast2_ok $1\fast2_ok[0:0] - end - attribute \src "issuer_ls180.v:146766.13-146766.29" - process $proc$issuer_ls180.v:146766$7830 - assign { } { } - assign $0\muxid$1[1:0]$7831 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$7831 - end - attribute \src "issuer_ls180.v:146779.14-146779.40" - process $proc$issuer_ls180.v:146779$7832 - assign { } { } - assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \nia $1\nia[63:0] - end - attribute \src "issuer_ls180.v:146786.7-146786.20" - process $proc$issuer_ls180.v:146786$7833 - assign { } { } - assign $1\nia_ok[0:0] 1'0 - sync always - sync init - update \nia_ok $1\nia_ok[0:0] - end - attribute \src "issuer_ls180.v:146800.7-146800.20" - process $proc$issuer_ls180.v:146800$7834 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "issuer_ls180.v:146804.3-146805.23" - process $proc$issuer_ls180.v:146804$7736 - assign { } { } - assign $0\nia[63:0] \nia$next - sync posedge \coresync_clk - update \nia $0\nia[63:0] - end - attribute \src "issuer_ls180.v:146806.3-146807.29" - process $proc$issuer_ls180.v:146806$7737 - assign { } { } - assign $0\nia_ok[0:0] \nia_ok$next - sync posedge \coresync_clk - update \nia_ok $0\nia_ok[0:0] - end - attribute \src "issuer_ls180.v:146808.3-146809.35" - process $proc$issuer_ls180.v:146808$7738 - assign { } { } - assign $0\fast2$11[63:0]$7739 \fast2$11$next - sync posedge \coresync_clk - update \fast2$11 $0\fast2$11[63:0]$7739 - end - attribute \src "issuer_ls180.v:146810.3-146811.33" - process $proc$issuer_ls180.v:146810$7740 - assign { } { } - assign $0\fast2_ok[0:0] \fast2_ok$next - sync posedge \coresync_clk - update \fast2_ok $0\fast2_ok[0:0] - end - attribute \src "issuer_ls180.v:146812.3-146813.35" - process $proc$issuer_ls180.v:146812$7741 - assign { } { } - assign $0\fast1$10[63:0]$7742 \fast1$10$next - sync posedge \coresync_clk - update \fast1$10 $0\fast1$10[63:0]$7742 - end - attribute \src "issuer_ls180.v:146814.3-146815.33" - process $proc$issuer_ls180.v:146814$7743 - assign { } { } - assign $0\fast1_ok[0:0] \fast1_ok$next - sync posedge \coresync_clk - update \fast1_ok $0\fast1_ok[0:0] - end - attribute \src "issuer_ls180.v:146816.3-146817.43" - process $proc$issuer_ls180.v:146816$7744 - assign { } { } - assign $0\br_op__cia$2[63:0]$7745 \br_op__cia$2$next - sync posedge \coresync_clk - update \br_op__cia$2 $0\br_op__cia$2[63:0]$7745 - end - attribute \src "issuer_ls180.v:146818.3-146819.55" - process $proc$issuer_ls180.v:146818$7746 - assign { } { } - assign $0\br_op__insn_type$3[6:0]$7747 \br_op__insn_type$3$next - sync posedge \coresync_clk - update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$7747 - end - attribute \src "issuer_ls180.v:146820.3-146821.51" - process $proc$issuer_ls180.v:146820$7748 - assign { } { } - assign $0\br_op__fn_unit$4[11:0]$7749 \br_op__fn_unit$4$next - sync posedge \coresync_clk - update \br_op__fn_unit$4 $0\br_op__fn_unit$4[11:0]$7749 - end - attribute \src "issuer_ls180.v:146822.3-146823.45" - process $proc$issuer_ls180.v:146822$7750 - assign { } { } - assign $0\br_op__insn$5[31:0]$7751 \br_op__insn$5$next - sync posedge \coresync_clk - update \br_op__insn$5 $0\br_op__insn$5[31:0]$7751 - end - attribute \src "issuer_ls180.v:146824.3-146825.65" - process $proc$issuer_ls180.v:146824$7752 - assign { } { } - assign $0\br_op__imm_data__data$6[63:0]$7753 \br_op__imm_data__data$6$next - sync posedge \coresync_clk - update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$7753 - end - attribute \src "issuer_ls180.v:146826.3-146827.61" - process $proc$issuer_ls180.v:146826$7754 - assign { } { } - assign $0\br_op__imm_data__ok$7[0:0]$7755 \br_op__imm_data__ok$7$next - sync posedge \coresync_clk - update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$7755 - end - attribute \src "issuer_ls180.v:146828.3-146829.41" - process $proc$issuer_ls180.v:146828$7756 - assign { } { } - assign $0\br_op__lk$8[0:0]$7757 \br_op__lk$8$next - sync posedge \coresync_clk - update \br_op__lk$8 $0\br_op__lk$8[0:0]$7757 - end - attribute \src "issuer_ls180.v:146830.3-146831.53" - process $proc$issuer_ls180.v:146830$7758 - assign { } { } - assign $0\br_op__is_32bit$9[0:0]$7759 \br_op__is_32bit$9$next - sync posedge \coresync_clk - update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$7759 - end - attribute \src "issuer_ls180.v:146832.3-146833.33" - process $proc$issuer_ls180.v:146832$7760 - assign { } { } - assign $0\muxid$1[1:0]$7761 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$7761 - end - attribute \src "issuer_ls180.v:146834.3-146835.29" - process $proc$issuer_ls180.v:146834$7762 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "issuer_ls180.v:146873.3-146890.6" - process $proc$issuer_ls180.v:146873$7763 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$7764 $2\r_busy$next[0:0]$7766 - attribute \src "issuer_ls180.v:146874.5-146874.29" - switch \initial - attribute \src "issuer_ls180.v:146874.9-146874.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$7765 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\r_busy$next[0:0]$7765 1'0 - case - assign $1\r_busy$next[0:0]$7765 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$7766 1'0 - case - assign $2\r_busy$next[0:0]$7766 $1\r_busy$next[0:0]$7765 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$7764 - end - attribute \src "issuer_ls180.v:146891.3-146903.6" - process $proc$issuer_ls180.v:146891$7767 - assign { } { } - assign { } { } - assign $0\muxid$1$next[1:0]$7768 $1\muxid$1$next[1:0]$7769 - attribute \src "issuer_ls180.v:146892.5-146892.29" - switch \initial - attribute \src "issuer_ls180.v:146892.9-146892.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$1$next[1:0]$7769 \muxid$26 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$1$next[1:0]$7769 \muxid$26 - case - assign $1\muxid$1$next[1:0]$7769 \muxid$1 - end - sync always - update \muxid$1$next $0\muxid$1$next[1:0]$7768 - end - attribute \src "issuer_ls180.v:146904.3-146931.6" - process $proc$issuer_ls180.v:146904$7770 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\br_op__cia$2$next[63:0]$7771 $1\br_op__cia$2$next[63:0]$7779 - assign $0\br_op__fn_unit$4$next[11:0]$7772 $1\br_op__fn_unit$4$next[11:0]$7780 - assign { } { } - assign { } { } - assign $0\br_op__insn$5$next[31:0]$7775 $1\br_op__insn$5$next[31:0]$7783 - assign $0\br_op__insn_type$3$next[6:0]$7776 $1\br_op__insn_type$3$next[6:0]$7784 - assign $0\br_op__is_32bit$9$next[0:0]$7777 $1\br_op__is_32bit$9$next[0:0]$7785 - assign $0\br_op__lk$8$next[0:0]$7778 $1\br_op__lk$8$next[0:0]$7786 - assign $0\br_op__imm_data__data$6$next[63:0]$7773 $2\br_op__imm_data__data$6$next[63:0]$7787 - assign $0\br_op__imm_data__ok$7$next[0:0]$7774 $2\br_op__imm_data__ok$7$next[0:0]$7788 - attribute \src "issuer_ls180.v:146905.5-146905.29" - switch \initial - attribute \src "issuer_ls180.v:146905.9-146905.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\br_op__is_32bit$9$next[0:0]$7785 $1\br_op__lk$8$next[0:0]$7786 $1\br_op__imm_data__ok$7$next[0:0]$7782 $1\br_op__imm_data__data$6$next[63:0]$7781 $1\br_op__insn$5$next[31:0]$7783 $1\br_op__fn_unit$4$next[11:0]$7780 $1\br_op__insn_type$3$next[6:0]$7784 $1\br_op__cia$2$next[63:0]$7779 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\br_op__is_32bit$9$next[0:0]$7785 $1\br_op__lk$8$next[0:0]$7786 $1\br_op__imm_data__ok$7$next[0:0]$7782 $1\br_op__imm_data__data$6$next[63:0]$7781 $1\br_op__insn$5$next[31:0]$7783 $1\br_op__fn_unit$4$next[11:0]$7780 $1\br_op__insn_type$3$next[6:0]$7784 $1\br_op__cia$2$next[63:0]$7779 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } - case - assign $1\br_op__cia$2$next[63:0]$7779 \br_op__cia$2 - assign $1\br_op__fn_unit$4$next[11:0]$7780 \br_op__fn_unit$4 - assign $1\br_op__imm_data__data$6$next[63:0]$7781 \br_op__imm_data__data$6 - assign $1\br_op__imm_data__ok$7$next[0:0]$7782 \br_op__imm_data__ok$7 - assign $1\br_op__insn$5$next[31:0]$7783 \br_op__insn$5 - assign $1\br_op__insn_type$3$next[6:0]$7784 \br_op__insn_type$3 - assign $1\br_op__is_32bit$9$next[0:0]$7785 \br_op__is_32bit$9 - assign $1\br_op__lk$8$next[0:0]$7786 \br_op__lk$8 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $2\br_op__imm_data__data$6$next[63:0]$7787 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\br_op__imm_data__ok$7$next[0:0]$7788 1'0 - case - assign $2\br_op__imm_data__data$6$next[63:0]$7787 $1\br_op__imm_data__data$6$next[63:0]$7781 - assign $2\br_op__imm_data__ok$7$next[0:0]$7788 $1\br_op__imm_data__ok$7$next[0:0]$7782 - end - sync always - update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$7771 - update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[11:0]$7772 - update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$7773 - update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$7774 - update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$7775 - update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$7776 - update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$7777 - update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$7778 - end - attribute \src "issuer_ls180.v:146932.3-146950.6" - process $proc$issuer_ls180.v:146932$7789 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fast1$10$next[63:0]$7790 $1\fast1$10$next[63:0]$7792 - assign { } { } - assign $0\fast1_ok$next[0:0]$7791 $2\fast1_ok$next[0:0]$7794 - attribute \src "issuer_ls180.v:146933.5-146933.29" - switch \initial - attribute \src "issuer_ls180.v:146933.9-146933.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\fast1_ok$next[0:0]$7793 $1\fast1$10$next[63:0]$7792 } { \fast1_ok$36 \fast1$35 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\fast1_ok$next[0:0]$7793 $1\fast1$10$next[63:0]$7792 } { \fast1_ok$36 \fast1$35 } - case - assign $1\fast1$10$next[63:0]$7792 \fast1$10 - assign $1\fast1_ok$next[0:0]$7793 \fast1_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fast1_ok$next[0:0]$7794 1'0 - case - assign $2\fast1_ok$next[0:0]$7794 $1\fast1_ok$next[0:0]$7793 - end - sync always - update \fast1$10$next $0\fast1$10$next[63:0]$7790 - update \fast1_ok$next $0\fast1_ok$next[0:0]$7791 - end - attribute \src "issuer_ls180.v:146951.3-146969.6" - process $proc$issuer_ls180.v:146951$7795 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fast2$11$next[63:0]$7796 $1\fast2$11$next[63:0]$7798 - assign { } { } - assign $0\fast2_ok$next[0:0]$7797 $2\fast2_ok$next[0:0]$7800 - attribute \src "issuer_ls180.v:146952.5-146952.29" - switch \initial - attribute \src "issuer_ls180.v:146952.9-146952.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\fast2_ok$next[0:0]$7799 $1\fast2$11$next[63:0]$7798 } { \fast2_ok$38 \fast2$37 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\fast2_ok$next[0:0]$7799 $1\fast2$11$next[63:0]$7798 } { \fast2_ok$38 \fast2$37 } - case - assign $1\fast2$11$next[63:0]$7798 \fast2$11 - assign $1\fast2_ok$next[0:0]$7799 \fast2_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fast2_ok$next[0:0]$7800 1'0 - case - assign $2\fast2_ok$next[0:0]$7800 $1\fast2_ok$next[0:0]$7799 - end - sync always - update \fast2$11$next $0\fast2$11$next[63:0]$7796 - update \fast2_ok$next $0\fast2_ok$next[0:0]$7797 - end - attribute \src "issuer_ls180.v:146970.3-146988.6" - process $proc$issuer_ls180.v:146970$7801 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\nia$next[63:0]$7802 $1\nia$next[63:0]$7804 - assign { } { } - assign $0\nia_ok$next[0:0]$7803 $2\nia_ok$next[0:0]$7806 - attribute \src "issuer_ls180.v:146971.5-146971.29" - switch \initial - attribute \src "issuer_ls180.v:146971.9-146971.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\nia_ok$next[0:0]$7805 $1\nia$next[63:0]$7804 } { \nia_ok$40 \nia$39 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\nia_ok$next[0:0]$7805 $1\nia$next[63:0]$7804 } { \nia_ok$40 \nia$39 } - case - assign $1\nia$next[63:0]$7804 \nia - assign $1\nia_ok$next[0:0]$7805 \nia_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\nia_ok$next[0:0]$7806 1'0 - case - assign $2\nia_ok$next[0:0]$7806 $1\nia_ok$next[0:0]$7805 - end - sync always - update \nia$next $0\nia$next[63:0]$7802 - update \nia_ok$next $0\nia_ok$next[0:0]$7803 - end - connect \$24 $and$issuer_ls180.v:146803$7735_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia } - connect { \fast2_ok$38 \fast2$37 } { \main_fast2_ok \main_fast2$22 } - connect { \fast1_ok$36 \fast1$35 } { \main_fast1_ok \main_fast1$21 } - connect { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } { \main_br_op__is_32bit$20 \main_br_op__lk$19 \main_br_op__imm_data__ok$18 \main_br_op__imm_data__data$17 \main_br_op__insn$16 \main_br_op__fn_unit$15 \main_br_op__insn_type$14 \main_br_op__cia$13 } - connect \muxid$26 \main_muxid$12 - connect \p_valid_i_p_ready_o \$24 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$23 \p_valid_i - connect \main_cr_a \cr_a - connect \main_fast2 \fast2 - connect \main_fast1 \fast1 - connect { \main_br_op__is_32bit \main_br_op__lk \main_br_op__imm_data__ok \main_br_op__imm_data__data \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } - connect \main_muxid \muxid -end -attribute \src "issuer_ls180.v:147008.1-147939.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe" -attribute \generator "nMigen" -module \pipe$32 - attribute \src "issuer_ls180.v:147845.3-147863.6" - wire width 64 $0\fast1$10$next[63:0]$7898 - attribute \src "issuer_ls180.v:147705.3-147706.35" - wire width 64 $0\fast1$10[63:0]$7844 - attribute \src "issuer_ls180.v:147020.14-147020.47" - wire width 64 $0\fast1$10[63:0]$7923 - attribute \src "issuer_ls180.v:147845.3-147863.6" - wire $0\fast1_ok$next[0:0]$7899 - attribute \src "issuer_ls180.v:147707.3-147708.33" - wire $0\fast1_ok[0:0] - attribute \src "issuer_ls180.v:147864.3-147882.6" - wire width 64 $0\fast2$11$next[63:0]$7904 - attribute \src "issuer_ls180.v:147701.3-147702.35" - wire width 64 $0\fast2$11[63:0]$7841 - attribute \src "issuer_ls180.v:147036.14-147036.47" - wire width 64 $0\fast2$11[63:0]$7926 - attribute \src "issuer_ls180.v:147864.3-147882.6" - wire $0\fast2_ok$next[0:0]$7905 - attribute \src "issuer_ls180.v:147703.3-147704.33" - wire $0\fast2_ok[0:0] - attribute \src "issuer_ls180.v:147009.7-147009.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:147902.3-147920.6" - wire width 64 $0\msr$next[63:0]$7916 - attribute \src "issuer_ls180.v:147693.3-147694.23" - wire width 64 $0\msr[63:0] - attribute \src "issuer_ls180.v:147902.3-147920.6" - wire $0\msr_ok$next[0:0]$7917 - attribute \src "issuer_ls180.v:147695.3-147696.29" - wire $0\msr_ok[0:0] - attribute \src "issuer_ls180.v:147793.3-147805.6" - wire width 2 $0\muxid$1$next[1:0]$7872 - attribute \src "issuer_ls180.v:147729.3-147730.33" - wire width 2 $0\muxid$1[1:0]$7865 - attribute \src "issuer_ls180.v:147304.13-147304.29" - wire width 2 $0\muxid$1[1:0]$7931 - attribute \src "issuer_ls180.v:147883.3-147901.6" - wire width 64 $0\nia$next[63:0]$7910 - attribute \src "issuer_ls180.v:147697.3-147698.23" - wire width 64 $0\nia[63:0] - attribute \src "issuer_ls180.v:147883.3-147901.6" - wire $0\nia_ok$next[0:0]$7911 - attribute \src "issuer_ls180.v:147699.3-147700.29" - wire $0\nia_ok[0:0] - attribute \src "issuer_ls180.v:147826.3-147844.6" - wire width 64 $0\o$next[63:0]$7892 - attribute \src "issuer_ls180.v:147709.3-147710.19" - wire width 64 $0\o[63:0] - attribute \src "issuer_ls180.v:147826.3-147844.6" - wire $0\o_ok$next[0:0]$7893 - attribute \src "issuer_ls180.v:147711.3-147712.25" - wire $0\o_ok[0:0] - attribute \src "issuer_ls180.v:147775.3-147792.6" - wire $0\r_busy$next[0:0]$7868 - attribute \src "issuer_ls180.v:147731.3-147732.29" - wire $0\r_busy[0:0] - attribute \src "issuer_ls180.v:147806.3-147825.6" - wire width 64 $0\trap_op__cia$6$next[63:0]$7875 - attribute \src "issuer_ls180.v:147721.3-147722.47" - wire width 64 $0\trap_op__cia$6[63:0]$7857 - attribute \src "issuer_ls180.v:147365.14-147365.53" - wire width 64 $0\trap_op__cia$6[63:0]$7938 - attribute \src "issuer_ls180.v:147806.3-147825.6" - wire width 12 $0\trap_op__fn_unit$3$next[11:0]$7876 - attribute \src "issuer_ls180.v:147715.3-147716.55" - wire width 12 $0\trap_op__fn_unit$3[11:0]$7851 - attribute \src "issuer_ls180.v:147413.14-147413.44" - wire width 12 $0\trap_op__fn_unit$3[11:0]$7940 - attribute \src "issuer_ls180.v:147806.3-147825.6" - wire width 32 $0\trap_op__insn$4$next[31:0]$7877 - attribute \src "issuer_ls180.v:147717.3-147718.49" - wire width 32 $0\trap_op__insn$4[31:0]$7853 - attribute \src "issuer_ls180.v:147422.14-147422.39" - wire width 32 $0\trap_op__insn$4[31:0]$7942 - attribute \src "issuer_ls180.v:147806.3-147825.6" - wire width 7 $0\trap_op__insn_type$2$next[6:0]$7878 - attribute \src "issuer_ls180.v:147713.3-147714.59" - wire width 7 $0\trap_op__insn_type$2[6:0]$7849 - attribute \src "issuer_ls180.v:147577.13-147577.43" - wire width 7 $0\trap_op__insn_type$2[6:0]$7944 - attribute \src "issuer_ls180.v:147806.3-147825.6" - wire $0\trap_op__is_32bit$7$next[0:0]$7879 - attribute \src "issuer_ls180.v:147723.3-147724.57" - wire $0\trap_op__is_32bit$7[0:0]$7859 - attribute \src "issuer_ls180.v:147662.7-147662.35" - wire $0\trap_op__is_32bit$7[0:0]$7946 - attribute \src "issuer_ls180.v:147806.3-147825.6" - wire width 64 $0\trap_op__msr$5$next[63:0]$7880 - attribute \src "issuer_ls180.v:147719.3-147720.47" - wire width 64 $0\trap_op__msr$5[63:0]$7855 - attribute \src "issuer_ls180.v:147671.14-147671.53" - wire width 64 $0\trap_op__msr$5[63:0]$7948 - attribute \src "issuer_ls180.v:147806.3-147825.6" - wire width 13 $0\trap_op__trapaddr$9$next[12:0]$7881 - attribute \src "issuer_ls180.v:147727.3-147728.57" - wire width 13 $0\trap_op__trapaddr$9[12:0]$7863 - attribute \src "issuer_ls180.v:147680.14-147680.46" - wire width 13 $0\trap_op__trapaddr$9[12:0]$7950 - attribute \src "issuer_ls180.v:147806.3-147825.6" - wire width 7 $0\trap_op__traptype$8$next[6:0]$7882 - attribute \src "issuer_ls180.v:147725.3-147726.57" - wire width 7 $0\trap_op__traptype$8[6:0]$7861 - attribute \src "issuer_ls180.v:147689.13-147689.42" - wire width 7 $0\trap_op__traptype$8[6:0]$7952 - attribute \src "issuer_ls180.v:147845.3-147863.6" - wire width 64 $1\fast1$10$next[63:0]$7900 - attribute \src "issuer_ls180.v:147845.3-147863.6" - wire $1\fast1_ok$next[0:0]$7901 - attribute \src "issuer_ls180.v:147027.7-147027.22" - wire $1\fast1_ok[0:0] - attribute \src "issuer_ls180.v:147864.3-147882.6" - wire width 64 $1\fast2$11$next[63:0]$7906 - attribute \src "issuer_ls180.v:147864.3-147882.6" - wire $1\fast2_ok$next[0:0]$7907 - attribute \src "issuer_ls180.v:147043.7-147043.22" - wire $1\fast2_ok[0:0] - attribute \src "issuer_ls180.v:147902.3-147920.6" - wire width 64 $1\msr$next[63:0]$7918 - attribute \src "issuer_ls180.v:147288.14-147288.40" - wire width 64 $1\msr[63:0] - attribute \src "issuer_ls180.v:147902.3-147920.6" - wire $1\msr_ok$next[0:0]$7919 - attribute \src "issuer_ls180.v:147295.7-147295.20" - wire $1\msr_ok[0:0] - attribute \src "issuer_ls180.v:147793.3-147805.6" - wire width 2 $1\muxid$1$next[1:0]$7873 - attribute \src "issuer_ls180.v:147883.3-147901.6" - wire width 64 $1\nia$next[63:0]$7912 - attribute \src "issuer_ls180.v:147317.14-147317.40" - wire width 64 $1\nia[63:0] - attribute \src "issuer_ls180.v:147883.3-147901.6" - wire $1\nia_ok$next[0:0]$7913 - attribute \src "issuer_ls180.v:147324.7-147324.20" - wire $1\nia_ok[0:0] - attribute \src "issuer_ls180.v:147826.3-147844.6" - wire width 64 $1\o$next[63:0]$7894 - attribute \src "issuer_ls180.v:147331.14-147331.38" - wire width 64 $1\o[63:0] - attribute \src "issuer_ls180.v:147826.3-147844.6" - wire $1\o_ok$next[0:0]$7895 - attribute \src "issuer_ls180.v:147338.7-147338.18" - wire $1\o_ok[0:0] - attribute \src "issuer_ls180.v:147775.3-147792.6" - wire $1\r_busy$next[0:0]$7869 - attribute \src "issuer_ls180.v:147352.7-147352.20" - wire $1\r_busy[0:0] - attribute \src "issuer_ls180.v:147806.3-147825.6" - wire width 64 $1\trap_op__cia$6$next[63:0]$7883 - attribute \src "issuer_ls180.v:147806.3-147825.6" - wire width 12 $1\trap_op__fn_unit$3$next[11:0]$7884 - attribute \src "issuer_ls180.v:147806.3-147825.6" - wire width 32 $1\trap_op__insn$4$next[31:0]$7885 - attribute \src "issuer_ls180.v:147806.3-147825.6" - wire width 7 $1\trap_op__insn_type$2$next[6:0]$7886 - attribute \src "issuer_ls180.v:147806.3-147825.6" - wire $1\trap_op__is_32bit$7$next[0:0]$7887 - attribute \src "issuer_ls180.v:147806.3-147825.6" - wire width 64 $1\trap_op__msr$5$next[63:0]$7888 - attribute \src "issuer_ls180.v:147806.3-147825.6" - wire width 13 $1\trap_op__trapaddr$9$next[12:0]$7889 - attribute \src "issuer_ls180.v:147806.3-147825.6" - wire width 7 $1\trap_op__traptype$8$next[6:0]$7890 - attribute \src "issuer_ls180.v:147845.3-147863.6" - wire $2\fast1_ok$next[0:0]$7902 - attribute \src "issuer_ls180.v:147864.3-147882.6" - wire $2\fast2_ok$next[0:0]$7908 - attribute \src "issuer_ls180.v:147902.3-147920.6" - wire $2\msr_ok$next[0:0]$7920 - attribute \src "issuer_ls180.v:147883.3-147901.6" - wire $2\nia_ok$next[0:0]$7914 - attribute \src "issuer_ls180.v:147826.3-147844.6" - wire $2\o_ok$next[0:0]$7896 - attribute \src "issuer_ls180.v:147775.3-147792.6" - wire $2\r_busy$next[0:0]$7870 - attribute \src "issuer_ls180.v:147692.18-147692.118" - wire $and$issuer_ls180.v:147692$7835_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 38 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 15 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 30 \fast1$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast1$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast1$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 31 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fast1_ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fast1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 16 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 32 \fast2$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast2$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast2$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 33 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fast2_ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fast2_ok$next - attribute \src "issuer_ls180.v:147009.7-147009.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_fast1$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_fast2$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_msr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_trap_op__cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_trap_op__cia$17 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_trap_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_trap_op__fn_unit$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_trap_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_trap_op__insn$15 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 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\enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__insn_type$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \trap_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \trap_op__is_32bit$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 25 \trap_op__is_32bit$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \trap_op__is_32bit$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 8 \trap_op__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__msr$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 23 \trap_op__msr$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__msr$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 12 \trap_op__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__trapaddr$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 27 \trap_op__trapaddr$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__trapaddr$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 11 \trap_op__traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__traptype$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 26 \trap_op__traptype$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__traptype$8$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$issuer_ls180.v:147692$7835 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$23 - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:147692$7835_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:147733.13-147766.4" - cell \main$35 \main - connect \fast1 \main_fast1 - connect \fast1$10 \main_fast1$21 - connect \fast1_ok \main_fast1_ok - connect \fast2 \main_fast2 - connect \fast2$11 \main_fast2$22 - connect \fast2_ok \main_fast2_ok - connect \msr \main_msr - connect \msr_ok \main_msr_ok - connect \muxid \main_muxid - connect \muxid$1 \main_muxid$12 - connect \nia \main_nia - connect \nia_ok \main_nia_ok - connect \o \main_o - connect \o_ok \main_o_ok - connect \ra \main_ra - connect \rb \main_rb - connect \trap_op__cia \main_trap_op__cia - connect \trap_op__cia$6 \main_trap_op__cia$17 - connect \trap_op__fn_unit \main_trap_op__fn_unit - connect \trap_op__fn_unit$3 \main_trap_op__fn_unit$14 - connect \trap_op__insn \main_trap_op__insn - connect \trap_op__insn$4 \main_trap_op__insn$15 - connect \trap_op__insn_type \main_trap_op__insn_type - connect \trap_op__insn_type$2 \main_trap_op__insn_type$13 - connect \trap_op__is_32bit \main_trap_op__is_32bit - connect \trap_op__is_32bit$7 \main_trap_op__is_32bit$18 - connect \trap_op__msr \main_trap_op__msr - connect \trap_op__msr$5 \main_trap_op__msr$16 - connect \trap_op__trapaddr \main_trap_op__trapaddr - connect \trap_op__trapaddr$9 \main_trap_op__trapaddr$20 - connect \trap_op__traptype \main_trap_op__traptype - connect \trap_op__traptype$8 \main_trap_op__traptype$19 - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:147767.10-147770.4" - cell \n$34 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:147771.10-147774.4" - cell \p$33 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "issuer_ls180.v:147009.7-147009.20" - process $proc$issuer_ls180.v:147009$7921 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:147020.14-147020.47" - process $proc$issuer_ls180.v:147020$7922 - assign { } { } - assign $0\fast1$10[63:0]$7923 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \fast1$10 $0\fast1$10[63:0]$7923 - end - attribute \src "issuer_ls180.v:147027.7-147027.22" - process $proc$issuer_ls180.v:147027$7924 - assign { } { } - assign $1\fast1_ok[0:0] 1'0 - sync always - sync init - update \fast1_ok $1\fast1_ok[0:0] - end - attribute \src "issuer_ls180.v:147036.14-147036.47" - process $proc$issuer_ls180.v:147036$7925 - assign { } { } - assign $0\fast2$11[63:0]$7926 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \fast2$11 $0\fast2$11[63:0]$7926 - end - attribute \src "issuer_ls180.v:147043.7-147043.22" - process $proc$issuer_ls180.v:147043$7927 - assign { } { } - assign $1\fast2_ok[0:0] 1'0 - sync always - sync init - update \fast2_ok $1\fast2_ok[0:0] - end - attribute \src "issuer_ls180.v:147288.14-147288.40" - process $proc$issuer_ls180.v:147288$7928 - assign { } { } - assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \msr $1\msr[63:0] - end - attribute \src "issuer_ls180.v:147295.7-147295.20" - process $proc$issuer_ls180.v:147295$7929 - assign { } { } - assign $1\msr_ok[0:0] 1'0 - sync always - sync init - update \msr_ok $1\msr_ok[0:0] - end - attribute \src "issuer_ls180.v:147304.13-147304.29" - process $proc$issuer_ls180.v:147304$7930 - assign { } { } - assign $0\muxid$1[1:0]$7931 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$7931 - end - attribute \src "issuer_ls180.v:147317.14-147317.40" - process $proc$issuer_ls180.v:147317$7932 - assign { } { } - assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \nia $1\nia[63:0] - end - attribute \src "issuer_ls180.v:147324.7-147324.20" - process $proc$issuer_ls180.v:147324$7933 - assign { } { } - assign $1\nia_ok[0:0] 1'0 - sync always - sync init - update \nia_ok $1\nia_ok[0:0] - end - attribute \src "issuer_ls180.v:147331.14-147331.38" - process $proc$issuer_ls180.v:147331$7934 - assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o $1\o[63:0] - end - attribute \src "issuer_ls180.v:147338.7-147338.18" - process $proc$issuer_ls180.v:147338$7935 - assign { } { } - assign $1\o_ok[0:0] 1'0 - sync always - sync init - update \o_ok $1\o_ok[0:0] - end - attribute \src "issuer_ls180.v:147352.7-147352.20" - process $proc$issuer_ls180.v:147352$7936 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "issuer_ls180.v:147365.14-147365.53" - process $proc$issuer_ls180.v:147365$7937 - assign { } { } - assign $0\trap_op__cia$6[63:0]$7938 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$7938 - end - attribute \src "issuer_ls180.v:147413.14-147413.44" - process $proc$issuer_ls180.v:147413$7939 - assign { } { } - assign $0\trap_op__fn_unit$3[11:0]$7940 12'000000000000 - sync always - sync init - update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[11:0]$7940 - end - attribute \src "issuer_ls180.v:147422.14-147422.39" - process $proc$issuer_ls180.v:147422$7941 - assign { } { } - assign $0\trap_op__insn$4[31:0]$7942 0 - sync always - sync init - update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$7942 - end - attribute \src "issuer_ls180.v:147577.13-147577.43" - process $proc$issuer_ls180.v:147577$7943 - assign { } { } - assign $0\trap_op__insn_type$2[6:0]$7944 7'0000000 - sync always - sync init - update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$7944 - end - attribute \src "issuer_ls180.v:147662.7-147662.35" - process $proc$issuer_ls180.v:147662$7945 - assign { } { } - assign $0\trap_op__is_32bit$7[0:0]$7946 1'0 - sync always - sync init - update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$7946 - end - attribute \src "issuer_ls180.v:147671.14-147671.53" - process $proc$issuer_ls180.v:147671$7947 - assign { } { } - assign $0\trap_op__msr$5[63:0]$7948 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$7948 - end - attribute \src "issuer_ls180.v:147680.14-147680.46" - process $proc$issuer_ls180.v:147680$7949 - assign { } { } - assign $0\trap_op__trapaddr$9[12:0]$7950 13'0000000000000 - sync always - sync init - update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$7950 - end - attribute \src "issuer_ls180.v:147689.13-147689.42" - process $proc$issuer_ls180.v:147689$7951 - assign { } { } - assign $0\trap_op__traptype$8[6:0]$7952 7'0000000 - sync always - sync init - update \trap_op__traptype$8 $0\trap_op__traptype$8[6:0]$7952 - end - attribute \src "issuer_ls180.v:147693.3-147694.23" - process $proc$issuer_ls180.v:147693$7836 - assign { } { } - assign $0\msr[63:0] \msr$next - sync posedge \coresync_clk - update \msr $0\msr[63:0] - end - attribute \src "issuer_ls180.v:147695.3-147696.29" - process $proc$issuer_ls180.v:147695$7837 - assign { } { } - assign $0\msr_ok[0:0] \msr_ok$next - sync posedge \coresync_clk - update \msr_ok $0\msr_ok[0:0] - end - attribute \src "issuer_ls180.v:147697.3-147698.23" - process $proc$issuer_ls180.v:147697$7838 - assign { } { } - assign $0\nia[63:0] \nia$next - sync posedge \coresync_clk - update \nia $0\nia[63:0] - end - attribute \src "issuer_ls180.v:147699.3-147700.29" - process $proc$issuer_ls180.v:147699$7839 - assign { } { } - assign $0\nia_ok[0:0] \nia_ok$next - sync posedge \coresync_clk - update \nia_ok $0\nia_ok[0:0] - end - attribute \src "issuer_ls180.v:147701.3-147702.35" - process $proc$issuer_ls180.v:147701$7840 - assign { } { } - assign $0\fast2$11[63:0]$7841 \fast2$11$next - sync posedge \coresync_clk - update \fast2$11 $0\fast2$11[63:0]$7841 - end - attribute \src "issuer_ls180.v:147703.3-147704.33" - process $proc$issuer_ls180.v:147703$7842 - assign { } { } - assign $0\fast2_ok[0:0] \fast2_ok$next - sync posedge \coresync_clk - update \fast2_ok $0\fast2_ok[0:0] - end - attribute \src "issuer_ls180.v:147705.3-147706.35" - process $proc$issuer_ls180.v:147705$7843 - assign { } { } - assign $0\fast1$10[63:0]$7844 \fast1$10$next - sync posedge \coresync_clk - update \fast1$10 $0\fast1$10[63:0]$7844 - end - attribute \src "issuer_ls180.v:147707.3-147708.33" - process $proc$issuer_ls180.v:147707$7845 - assign { } { } - assign $0\fast1_ok[0:0] \fast1_ok$next - sync posedge \coresync_clk - update \fast1_ok $0\fast1_ok[0:0] - end - attribute \src "issuer_ls180.v:147709.3-147710.19" - process $proc$issuer_ls180.v:147709$7846 - assign { } { } - assign $0\o[63:0] \o$next - sync posedge \coresync_clk - update \o $0\o[63:0] - end - attribute \src "issuer_ls180.v:147711.3-147712.25" - process $proc$issuer_ls180.v:147711$7847 - assign { } { } - assign $0\o_ok[0:0] \o_ok$next - sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] - end - attribute \src "issuer_ls180.v:147713.3-147714.59" - process $proc$issuer_ls180.v:147713$7848 - assign { } { } - assign $0\trap_op__insn_type$2[6:0]$7849 \trap_op__insn_type$2$next - sync posedge \coresync_clk - update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$7849 - end - attribute \src "issuer_ls180.v:147715.3-147716.55" - process $proc$issuer_ls180.v:147715$7850 - assign { } { } - assign $0\trap_op__fn_unit$3[11:0]$7851 \trap_op__fn_unit$3$next - sync posedge \coresync_clk - update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[11:0]$7851 - end - attribute \src "issuer_ls180.v:147717.3-147718.49" - process $proc$issuer_ls180.v:147717$7852 - assign { } { } - assign $0\trap_op__insn$4[31:0]$7853 \trap_op__insn$4$next - sync posedge \coresync_clk - update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$7853 - end - attribute \src "issuer_ls180.v:147719.3-147720.47" - process $proc$issuer_ls180.v:147719$7854 - assign { } { } - assign $0\trap_op__msr$5[63:0]$7855 \trap_op__msr$5$next - sync posedge \coresync_clk - update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$7855 - end - attribute \src "issuer_ls180.v:147721.3-147722.47" - process $proc$issuer_ls180.v:147721$7856 - assign { } { } - assign $0\trap_op__cia$6[63:0]$7857 \trap_op__cia$6$next - sync posedge \coresync_clk - update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$7857 - end - attribute \src "issuer_ls180.v:147723.3-147724.57" - process $proc$issuer_ls180.v:147723$7858 - assign { } { } - assign $0\trap_op__is_32bit$7[0:0]$7859 \trap_op__is_32bit$7$next - sync posedge \coresync_clk - update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$7859 - end - attribute \src "issuer_ls180.v:147725.3-147726.57" - process $proc$issuer_ls180.v:147725$7860 - assign { } { } - assign $0\trap_op__traptype$8[6:0]$7861 \trap_op__traptype$8$next - sync posedge \coresync_clk - update \trap_op__traptype$8 $0\trap_op__traptype$8[6:0]$7861 - end - attribute \src "issuer_ls180.v:147727.3-147728.57" - process $proc$issuer_ls180.v:147727$7862 - assign { } { } - assign $0\trap_op__trapaddr$9[12:0]$7863 \trap_op__trapaddr$9$next - sync posedge \coresync_clk - update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$7863 - end - attribute \src "issuer_ls180.v:147729.3-147730.33" - process $proc$issuer_ls180.v:147729$7864 - assign { } { } - assign $0\muxid$1[1:0]$7865 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$7865 - end - attribute \src "issuer_ls180.v:147731.3-147732.29" - process $proc$issuer_ls180.v:147731$7866 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "issuer_ls180.v:147775.3-147792.6" - process $proc$issuer_ls180.v:147775$7867 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$7868 $2\r_busy$next[0:0]$7870 - attribute \src "issuer_ls180.v:147776.5-147776.29" - switch \initial - attribute \src "issuer_ls180.v:147776.9-147776.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$7869 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\r_busy$next[0:0]$7869 1'0 - case - assign $1\r_busy$next[0:0]$7869 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$7870 1'0 - case - assign $2\r_busy$next[0:0]$7870 $1\r_busy$next[0:0]$7869 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$7868 - end - attribute \src "issuer_ls180.v:147793.3-147805.6" - process $proc$issuer_ls180.v:147793$7871 - assign { } { } - assign { } { } - assign $0\muxid$1$next[1:0]$7872 $1\muxid$1$next[1:0]$7873 - attribute \src "issuer_ls180.v:147794.5-147794.29" - switch \initial - attribute \src "issuer_ls180.v:147794.9-147794.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$1$next[1:0]$7873 \muxid$26 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$1$next[1:0]$7873 \muxid$26 - case - assign $1\muxid$1$next[1:0]$7873 \muxid$1 - end - sync always - update \muxid$1$next $0\muxid$1$next[1:0]$7872 - end - attribute \src "issuer_ls180.v:147806.3-147825.6" - process $proc$issuer_ls180.v:147806$7874 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\trap_op__cia$6$next[63:0]$7875 $1\trap_op__cia$6$next[63:0]$7883 - assign $0\trap_op__fn_unit$3$next[11:0]$7876 $1\trap_op__fn_unit$3$next[11:0]$7884 - assign $0\trap_op__insn$4$next[31:0]$7877 $1\trap_op__insn$4$next[31:0]$7885 - assign $0\trap_op__insn_type$2$next[6:0]$7878 $1\trap_op__insn_type$2$next[6:0]$7886 - assign $0\trap_op__is_32bit$7$next[0:0]$7879 $1\trap_op__is_32bit$7$next[0:0]$7887 - assign $0\trap_op__msr$5$next[63:0]$7880 $1\trap_op__msr$5$next[63:0]$7888 - assign $0\trap_op__trapaddr$9$next[12:0]$7881 $1\trap_op__trapaddr$9$next[12:0]$7889 - assign $0\trap_op__traptype$8$next[6:0]$7882 $1\trap_op__traptype$8$next[6:0]$7890 - attribute \src "issuer_ls180.v:147807.5-147807.29" - switch \initial - attribute \src "issuer_ls180.v:147807.9-147807.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\trap_op__trapaddr$9$next[12:0]$7889 $1\trap_op__traptype$8$next[6:0]$7890 $1\trap_op__is_32bit$7$next[0:0]$7887 $1\trap_op__cia$6$next[63:0]$7883 $1\trap_op__msr$5$next[63:0]$7888 $1\trap_op__insn$4$next[31:0]$7885 $1\trap_op__fn_unit$3$next[11:0]$7884 $1\trap_op__insn_type$2$next[6:0]$7886 } { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\trap_op__trapaddr$9$next[12:0]$7889 $1\trap_op__traptype$8$next[6:0]$7890 $1\trap_op__is_32bit$7$next[0:0]$7887 $1\trap_op__cia$6$next[63:0]$7883 $1\trap_op__msr$5$next[63:0]$7888 $1\trap_op__insn$4$next[31:0]$7885 $1\trap_op__fn_unit$3$next[11:0]$7884 $1\trap_op__insn_type$2$next[6:0]$7886 } { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 } - case - assign $1\trap_op__cia$6$next[63:0]$7883 \trap_op__cia$6 - assign $1\trap_op__fn_unit$3$next[11:0]$7884 \trap_op__fn_unit$3 - assign $1\trap_op__insn$4$next[31:0]$7885 \trap_op__insn$4 - assign $1\trap_op__insn_type$2$next[6:0]$7886 \trap_op__insn_type$2 - assign $1\trap_op__is_32bit$7$next[0:0]$7887 \trap_op__is_32bit$7 - assign $1\trap_op__msr$5$next[63:0]$7888 \trap_op__msr$5 - assign $1\trap_op__trapaddr$9$next[12:0]$7889 \trap_op__trapaddr$9 - assign $1\trap_op__traptype$8$next[6:0]$7890 \trap_op__traptype$8 - end - sync always - update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$7875 - update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[11:0]$7876 - update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$7877 - update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$7878 - update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$7879 - update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$7880 - update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$7881 - update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[6:0]$7882 - end - attribute \src "issuer_ls180.v:147826.3-147844.6" - process $proc$issuer_ls180.v:147826$7891 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$next[63:0]$7892 $1\o$next[63:0]$7894 - assign { } { } - assign $0\o_ok$next[0:0]$7893 $2\o_ok$next[0:0]$7896 - attribute \src "issuer_ls180.v:147827.5-147827.29" - switch \initial - attribute \src "issuer_ls180.v:147827.9-147827.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$7895 $1\o$next[63:0]$7894 } { \o_ok$36 \o$35 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$7895 $1\o$next[63:0]$7894 } { \o_ok$36 \o$35 } - case - assign $1\o$next[63:0]$7894 \o - assign $1\o_ok$next[0:0]$7895 \o_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o_ok$next[0:0]$7896 1'0 - case - assign $2\o_ok$next[0:0]$7896 $1\o_ok$next[0:0]$7895 - end - sync always - update \o$next $0\o$next[63:0]$7892 - update \o_ok$next $0\o_ok$next[0:0]$7893 - end - attribute \src "issuer_ls180.v:147845.3-147863.6" - process $proc$issuer_ls180.v:147845$7897 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fast1$10$next[63:0]$7898 $1\fast1$10$next[63:0]$7900 - assign { } { } - assign $0\fast1_ok$next[0:0]$7899 $2\fast1_ok$next[0:0]$7902 - attribute \src "issuer_ls180.v:147846.5-147846.29" - switch \initial - attribute \src "issuer_ls180.v:147846.9-147846.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\fast1_ok$next[0:0]$7901 $1\fast1$10$next[63:0]$7900 } { \fast1_ok$38 \fast1$37 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\fast1_ok$next[0:0]$7901 $1\fast1$10$next[63:0]$7900 } { \fast1_ok$38 \fast1$37 } - case - assign $1\fast1$10$next[63:0]$7900 \fast1$10 - assign $1\fast1_ok$next[0:0]$7901 \fast1_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fast1_ok$next[0:0]$7902 1'0 - case - assign $2\fast1_ok$next[0:0]$7902 $1\fast1_ok$next[0:0]$7901 - end - sync always - update \fast1$10$next $0\fast1$10$next[63:0]$7898 - update \fast1_ok$next $0\fast1_ok$next[0:0]$7899 - end - attribute \src "issuer_ls180.v:147864.3-147882.6" - process $proc$issuer_ls180.v:147864$7903 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fast2$11$next[63:0]$7904 $1\fast2$11$next[63:0]$7906 - assign { } { } - assign $0\fast2_ok$next[0:0]$7905 $2\fast2_ok$next[0:0]$7908 - attribute \src "issuer_ls180.v:147865.5-147865.29" - switch \initial - attribute \src "issuer_ls180.v:147865.9-147865.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\fast2_ok$next[0:0]$7907 $1\fast2$11$next[63:0]$7906 } { \fast2_ok$40 \fast2$39 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\fast2_ok$next[0:0]$7907 $1\fast2$11$next[63:0]$7906 } { \fast2_ok$40 \fast2$39 } - case - assign $1\fast2$11$next[63:0]$7906 \fast2$11 - assign $1\fast2_ok$next[0:0]$7907 \fast2_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fast2_ok$next[0:0]$7908 1'0 - case - assign $2\fast2_ok$next[0:0]$7908 $1\fast2_ok$next[0:0]$7907 - end - sync always - update \fast2$11$next $0\fast2$11$next[63:0]$7904 - update \fast2_ok$next $0\fast2_ok$next[0:0]$7905 - end - attribute \src "issuer_ls180.v:147883.3-147901.6" - process $proc$issuer_ls180.v:147883$7909 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\nia$next[63:0]$7910 $1\nia$next[63:0]$7912 - assign { } { } - assign $0\nia_ok$next[0:0]$7911 $2\nia_ok$next[0:0]$7914 - attribute \src "issuer_ls180.v:147884.5-147884.29" - switch \initial - attribute \src "issuer_ls180.v:147884.9-147884.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\nia_ok$next[0:0]$7913 $1\nia$next[63:0]$7912 } { \nia_ok$42 \nia$41 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\nia_ok$next[0:0]$7913 $1\nia$next[63:0]$7912 } { \nia_ok$42 \nia$41 } - case - assign $1\nia$next[63:0]$7912 \nia - assign $1\nia_ok$next[0:0]$7913 \nia_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\nia_ok$next[0:0]$7914 1'0 - case - assign $2\nia_ok$next[0:0]$7914 $1\nia_ok$next[0:0]$7913 - end - sync always - update \nia$next $0\nia$next[63:0]$7910 - update \nia_ok$next $0\nia_ok$next[0:0]$7911 - end - attribute \src "issuer_ls180.v:147902.3-147920.6" - process $proc$issuer_ls180.v:147902$7915 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\msr$next[63:0]$7916 $1\msr$next[63:0]$7918 - assign { } { } - assign $0\msr_ok$next[0:0]$7917 $2\msr_ok$next[0:0]$7920 - attribute \src "issuer_ls180.v:147903.5-147903.29" - switch \initial - attribute \src "issuer_ls180.v:147903.9-147903.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\msr_ok$next[0:0]$7919 $1\msr$next[63:0]$7918 } { \msr_ok$44 \msr$43 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\msr_ok$next[0:0]$7919 $1\msr$next[63:0]$7918 } { \msr_ok$44 \msr$43 } - case - assign $1\msr$next[63:0]$7918 \msr - assign $1\msr_ok$next[0:0]$7919 \msr_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\msr_ok$next[0:0]$7920 1'0 - case - assign $2\msr_ok$next[0:0]$7920 $1\msr_ok$next[0:0]$7919 - end - sync always - update \msr$next $0\msr$next[63:0]$7916 - update \msr_ok$next $0\msr_ok$next[0:0]$7917 - end - connect \$24 $and$issuer_ls180.v:147692$7835_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \msr_ok$44 \msr$43 } { \main_msr_ok \main_msr } - connect { \nia_ok$42 \nia$41 } { \main_nia_ok \main_nia } - connect { \fast2_ok$40 \fast2$39 } { \main_fast2_ok \main_fast2$22 } - connect { \fast1_ok$38 \fast1$37 } { \main_fast1_ok \main_fast1$21 } - connect { \o_ok$36 \o$35 } { \main_o_ok \main_o } - connect { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 } { \main_trap_op__trapaddr$20 \main_trap_op__traptype$19 \main_trap_op__is_32bit$18 \main_trap_op__cia$17 \main_trap_op__msr$16 \main_trap_op__insn$15 \main_trap_op__fn_unit$14 \main_trap_op__insn_type$13 } - connect \muxid$26 \main_muxid$12 - connect \p_valid_i_p_ready_o \$24 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$23 \p_valid_i - connect \main_fast2 \fast2 - connect \main_fast1 \fast1 - connect \main_rb \rb - connect \main_ra \ra - connect { \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } - connect \main_muxid \muxid -end -attribute \src "issuer_ls180.v:147943.1-148858.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe" -attribute \generator "nMigen" -module \pipe$61 - attribute \src "issuer_ls180.v:148761.3-148779.6" - wire width 64 $0\fast1$7$next[63:0]$8012 - attribute \src "issuer_ls180.v:148614.3-148615.33" - wire width 64 $0\fast1$7[63:0]$7964 - attribute \src "issuer_ls180.v:147957.14-147957.46" - wire width 64 $0\fast1$7[63:0]$8036 - attribute \src "issuer_ls180.v:148761.3-148779.6" - wire $0\fast1_ok$next[0:0]$8011 - attribute \src "issuer_ls180.v:148616.3-148617.33" - wire $0\fast1_ok[0:0] - attribute \src "issuer_ls180.v:147944.7-147944.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:148694.3-148706.6" - wire width 2 $0\muxid$1$next[1:0]$7987 - attribute \src "issuer_ls180.v:148634.3-148635.33" - wire width 2 $0\muxid$1[1:0]$7980 - attribute \src "issuer_ls180.v:147971.13-147971.29" - wire width 2 $0\muxid$1[1:0]$8039 - attribute \src "issuer_ls180.v:148723.3-148741.6" - wire width 64 $0\o$next[63:0]$7999 - attribute \src "issuer_ls180.v:148622.3-148623.19" - wire width 64 $0\o[63:0] - attribute \src "issuer_ls180.v:148723.3-148741.6" - wire $0\o_ok$next[0:0]$8000 - attribute \src "issuer_ls180.v:148624.3-148625.25" - wire $0\o_ok[0:0] - attribute \src "issuer_ls180.v:148676.3-148693.6" - wire $0\r_busy$next[0:0]$7983 - attribute \src "issuer_ls180.v:148636.3-148637.29" - wire $0\r_busy[0:0] - attribute \src "issuer_ls180.v:148742.3-148760.6" - wire width 64 $0\spr1$6$next[63:0]$8005 - attribute \src "issuer_ls180.v:148618.3-148619.31" - wire width 64 $0\spr1$6[63:0]$7967 - attribute \src "issuer_ls180.v:148016.14-148016.45" - wire width 64 $0\spr1$6[63:0]$8044 - attribute \src "issuer_ls180.v:148742.3-148760.6" - wire $0\spr1_ok$next[0:0]$8006 - attribute \src "issuer_ls180.v:148620.3-148621.31" - wire $0\spr1_ok[0:0] - attribute \src "issuer_ls180.v:148707.3-148722.6" - wire width 12 $0\spr_op__fn_unit$3$next[11:0]$7990 - attribute \src "issuer_ls180.v:148628.3-148629.53" - wire width 12 $0\spr_op__fn_unit$3[11:0]$7974 - attribute \src "issuer_ls180.v:148301.14-148301.43" - wire width 12 $0\spr_op__fn_unit$3[11:0]$8047 - attribute \src "issuer_ls180.v:148707.3-148722.6" - wire width 32 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ca_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 13 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 30 \xer_ov$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 31 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ov_ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 12 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 28 \xer_so$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 29 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$issuer_ls180.v:148601$7953 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$21 - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:148601$7953_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:148638.10-148641.4" - cell \n$63 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:148642.10-148645.4" - cell \p$62 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:148646.12-148675.4" - cell \spr_main \spr_main - connect \fast1 \spr_main_fast1 - connect \fast1$7 \spr_main_fast1$17 - connect \fast1_ok \spr_main_fast1_ok - connect \muxid \spr_main_muxid - connect \muxid$1 \spr_main_muxid$11 - connect \o \spr_main_o - connect \o_ok \spr_main_o_ok - connect \ra \spr_main_ra - connect \spr1 \spr_main_spr1 - connect \spr1$6 \spr_main_spr1$16 - connect \spr1_ok \spr_main_spr1_ok - connect \spr_op__fn_unit \spr_main_spr_op__fn_unit - connect \spr_op__fn_unit$3 \spr_main_spr_op__fn_unit$13 - connect \spr_op__insn \spr_main_spr_op__insn - connect \spr_op__insn$4 \spr_main_spr_op__insn$14 - connect \spr_op__insn_type \spr_main_spr_op__insn_type - connect \spr_op__insn_type$2 \spr_main_spr_op__insn_type$12 - connect \spr_op__is_32bit \spr_main_spr_op__is_32bit - connect \spr_op__is_32bit$5 \spr_main_spr_op__is_32bit$15 - connect \xer_ca \spr_main_xer_ca - connect \xer_ca$10 \spr_main_xer_ca$20 - connect \xer_ca_ok \spr_main_xer_ca_ok - connect \xer_ov \spr_main_xer_ov - connect \xer_ov$9 \spr_main_xer_ov$19 - connect \xer_ov_ok \spr_main_xer_ov_ok - connect \xer_so \spr_main_xer_so - connect \xer_so$8 \spr_main_xer_so$18 - connect \xer_so_ok \spr_main_xer_so_ok - end - attribute \src "issuer_ls180.v:147944.7-147944.20" - process $proc$issuer_ls180.v:147944$8034 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:147957.14-147957.46" - process $proc$issuer_ls180.v:147957$8035 - assign { } { } - assign $0\fast1$7[63:0]$8036 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \fast1$7 $0\fast1$7[63:0]$8036 - end - attribute \src "issuer_ls180.v:147962.7-147962.22" - process $proc$issuer_ls180.v:147962$8037 - assign { } { } - assign $1\fast1_ok[0:0] 1'0 - sync always - sync init - update \fast1_ok $1\fast1_ok[0:0] - end - attribute \src "issuer_ls180.v:147971.13-147971.29" - process $proc$issuer_ls180.v:147971$8038 - assign { } { } - assign $0\muxid$1[1:0]$8039 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$8039 - end - attribute \src "issuer_ls180.v:147984.14-147984.38" - process $proc$issuer_ls180.v:147984$8040 - assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o $1\o[63:0] - end - attribute \src "issuer_ls180.v:147991.7-147991.18" - process $proc$issuer_ls180.v:147991$8041 - assign { } { } - assign $1\o_ok[0:0] 1'0 - sync always - sync init - update \o_ok $1\o_ok[0:0] - end - attribute \src "issuer_ls180.v:148005.7-148005.20" - process $proc$issuer_ls180.v:148005$8042 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "issuer_ls180.v:148016.14-148016.45" - process $proc$issuer_ls180.v:148016$8043 - assign { } { } - assign $0\spr1$6[63:0]$8044 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \spr1$6 $0\spr1$6[63:0]$8044 - end - attribute \src "issuer_ls180.v:148021.7-148021.21" - process $proc$issuer_ls180.v:148021$8045 - assign { } { } - assign $1\spr1_ok[0:0] 1'0 - sync always - sync init - update \spr1_ok $1\spr1_ok[0:0] - end - attribute \src "issuer_ls180.v:148301.14-148301.43" - process $proc$issuer_ls180.v:148301$8046 - assign { } { } - assign $0\spr_op__fn_unit$3[11:0]$8047 12'000000000000 - sync always - sync init - update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[11:0]$8047 - end - attribute \src "issuer_ls180.v:148310.14-148310.38" - process $proc$issuer_ls180.v:148310$8048 - assign { } { } - assign $0\spr_op__insn$4[31:0]$8049 0 - sync always - sync init - update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8049 - end - attribute \src "issuer_ls180.v:148465.13-148465.42" - process $proc$issuer_ls180.v:148465$8050 - assign { } { } - assign $0\spr_op__insn_type$2[6:0]$8051 7'0000000 - sync always - sync init - update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8051 - end - attribute \src "issuer_ls180.v:148550.7-148550.34" - process $proc$issuer_ls180.v:148550$8052 - assign { } { } - assign $0\spr_op__is_32bit$5[0:0]$8053 1'0 - sync always - sync init - update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8053 - end - attribute \src "issuer_ls180.v:148557.13-148557.31" - process $proc$issuer_ls180.v:148557$8054 - assign { } { } - assign $0\xer_ca$10[1:0]$8055 2'00 - sync always - sync init - update \xer_ca$10 $0\xer_ca$10[1:0]$8055 - end - attribute \src "issuer_ls180.v:148564.7-148564.23" - process $proc$issuer_ls180.v:148564$8056 - assign { } { } - assign $1\xer_ca_ok[0:0] 1'0 - sync always - sync init - update \xer_ca_ok $1\xer_ca_ok[0:0] - end - attribute \src "issuer_ls180.v:148575.13-148575.30" - process $proc$issuer_ls180.v:148575$8057 - assign { } { } - assign $0\xer_ov$9[1:0]$8058 2'00 - sync always - sync init - update \xer_ov$9 $0\xer_ov$9[1:0]$8058 - end - attribute \src "issuer_ls180.v:148580.7-148580.23" - process $proc$issuer_ls180.v:148580$8059 - assign { } { } - assign $1\xer_ov_ok[0:0] 1'0 - sync always - sync init - update \xer_ov_ok $1\xer_ov_ok[0:0] - end - attribute \src "issuer_ls180.v:148591.7-148591.24" - process $proc$issuer_ls180.v:148591$8060 - assign { } { } - assign $0\xer_so$8[0:0]$8061 1'0 - sync always - sync init - update \xer_so$8 $0\xer_so$8[0:0]$8061 - end - attribute \src "issuer_ls180.v:148596.7-148596.23" - process $proc$issuer_ls180.v:148596$8062 - assign { } { } - assign $1\xer_so_ok[0:0] 1'0 - sync always - sync init - update \xer_so_ok $1\xer_so_ok[0:0] - end - attribute \src "issuer_ls180.v:148602.3-148603.37" - process $proc$issuer_ls180.v:148602$7954 - assign { } { } - assign $0\xer_ca$10[1:0]$7955 \xer_ca$10$next - sync posedge \coresync_clk - update \xer_ca$10 $0\xer_ca$10[1:0]$7955 - end - attribute \src "issuer_ls180.v:148604.3-148605.35" - process $proc$issuer_ls180.v:148604$7956 - assign { } { } - assign $0\xer_ca_ok[0:0] \xer_ca_ok$next - sync posedge \coresync_clk - update \xer_ca_ok $0\xer_ca_ok[0:0] - end - attribute \src "issuer_ls180.v:148606.3-148607.35" - process $proc$issuer_ls180.v:148606$7957 - assign { } { } - assign $0\xer_ov$9[1:0]$7958 \xer_ov$9$next - sync posedge \coresync_clk - update \xer_ov$9 $0\xer_ov$9[1:0]$7958 - end - attribute \src "issuer_ls180.v:148608.3-148609.35" - process $proc$issuer_ls180.v:148608$7959 - assign { } { } - assign $0\xer_ov_ok[0:0] \xer_ov_ok$next - sync posedge \coresync_clk - update \xer_ov_ok $0\xer_ov_ok[0:0] - end - attribute \src "issuer_ls180.v:148610.3-148611.35" - process $proc$issuer_ls180.v:148610$7960 - assign { } { } - assign $0\xer_so$8[0:0]$7961 \xer_so$8$next - sync posedge \coresync_clk - update \xer_so$8 $0\xer_so$8[0:0]$7961 - end - attribute \src "issuer_ls180.v:148612.3-148613.35" - process $proc$issuer_ls180.v:148612$7962 - assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next - sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] - end - attribute \src "issuer_ls180.v:148614.3-148615.33" - process $proc$issuer_ls180.v:148614$7963 - assign { } { } - assign $0\fast1$7[63:0]$7964 \fast1$7$next - sync posedge \coresync_clk - update \fast1$7 $0\fast1$7[63:0]$7964 - end - attribute \src "issuer_ls180.v:148616.3-148617.33" - process $proc$issuer_ls180.v:148616$7965 - assign { } { } - assign $0\fast1_ok[0:0] \fast1_ok$next - sync posedge \coresync_clk - update \fast1_ok $0\fast1_ok[0:0] - end - attribute \src "issuer_ls180.v:148618.3-148619.31" - process $proc$issuer_ls180.v:148618$7966 - assign { } { } - assign $0\spr1$6[63:0]$7967 \spr1$6$next - sync posedge \coresync_clk - update \spr1$6 $0\spr1$6[63:0]$7967 - end - attribute \src "issuer_ls180.v:148620.3-148621.31" - process $proc$issuer_ls180.v:148620$7968 - assign { } { } - assign $0\spr1_ok[0:0] \spr1_ok$next - sync posedge \coresync_clk - update \spr1_ok $0\spr1_ok[0:0] - end - attribute \src "issuer_ls180.v:148622.3-148623.19" - process $proc$issuer_ls180.v:148622$7969 - assign { } { } - assign $0\o[63:0] \o$next - sync posedge \coresync_clk - update \o $0\o[63:0] - end - attribute \src "issuer_ls180.v:148624.3-148625.25" - process $proc$issuer_ls180.v:148624$7970 - assign { } { } - assign $0\o_ok[0:0] \o_ok$next - sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] - end - attribute \src "issuer_ls180.v:148626.3-148627.57" - process $proc$issuer_ls180.v:148626$7971 - assign { } { } - assign $0\spr_op__insn_type$2[6:0]$7972 \spr_op__insn_type$2$next - sync posedge \coresync_clk - update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$7972 - end - attribute \src "issuer_ls180.v:148628.3-148629.53" - process $proc$issuer_ls180.v:148628$7973 - assign { } { } - assign $0\spr_op__fn_unit$3[11:0]$7974 \spr_op__fn_unit$3$next - sync posedge \coresync_clk - update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[11:0]$7974 - end - attribute \src "issuer_ls180.v:148630.3-148631.47" - process $proc$issuer_ls180.v:148630$7975 - assign { } { } - assign $0\spr_op__insn$4[31:0]$7976 \spr_op__insn$4$next - sync posedge \coresync_clk - update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$7976 - end - attribute \src "issuer_ls180.v:148632.3-148633.55" - process $proc$issuer_ls180.v:148632$7977 - assign { } { } - assign $0\spr_op__is_32bit$5[0:0]$7978 \spr_op__is_32bit$5$next - sync posedge \coresync_clk - update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$7978 - end - attribute \src "issuer_ls180.v:148634.3-148635.33" - process $proc$issuer_ls180.v:148634$7979 - assign { } { } - assign $0\muxid$1[1:0]$7980 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$7980 - end - attribute \src "issuer_ls180.v:148636.3-148637.29" - process $proc$issuer_ls180.v:148636$7981 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "issuer_ls180.v:148676.3-148693.6" - process $proc$issuer_ls180.v:148676$7982 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$7983 $2\r_busy$next[0:0]$7985 - attribute \src "issuer_ls180.v:148677.5-148677.29" - switch \initial - attribute \src "issuer_ls180.v:148677.9-148677.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$7984 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\r_busy$next[0:0]$7984 1'0 - case - assign $1\r_busy$next[0:0]$7984 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$7985 1'0 - case - assign $2\r_busy$next[0:0]$7985 $1\r_busy$next[0:0]$7984 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$7983 - end - attribute \src "issuer_ls180.v:148694.3-148706.6" - process $proc$issuer_ls180.v:148694$7986 - assign { } { } - assign { } { } - assign $0\muxid$1$next[1:0]$7987 $1\muxid$1$next[1:0]$7988 - attribute \src "issuer_ls180.v:148695.5-148695.29" - switch \initial - attribute \src "issuer_ls180.v:148695.9-148695.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$1$next[1:0]$7988 \muxid$24 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$1$next[1:0]$7988 \muxid$24 - case - assign $1\muxid$1$next[1:0]$7988 \muxid$1 - end - sync always - update \muxid$1$next $0\muxid$1$next[1:0]$7987 - end - attribute \src "issuer_ls180.v:148707.3-148722.6" - process $proc$issuer_ls180.v:148707$7989 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\spr_op__fn_unit$3$next[11:0]$7990 $1\spr_op__fn_unit$3$next[11:0]$7994 - assign $0\spr_op__insn$4$next[31:0]$7991 $1\spr_op__insn$4$next[31:0]$7995 - assign $0\spr_op__insn_type$2$next[6:0]$7992 $1\spr_op__insn_type$2$next[6:0]$7996 - assign $0\spr_op__is_32bit$5$next[0:0]$7993 $1\spr_op__is_32bit$5$next[0:0]$7997 - attribute \src "issuer_ls180.v:148708.5-148708.29" - switch \initial - attribute \src "issuer_ls180.v:148708.9-148708.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\spr_op__is_32bit$5$next[0:0]$7997 $1\spr_op__insn$4$next[31:0]$7995 $1\spr_op__fn_unit$3$next[11:0]$7994 $1\spr_op__insn_type$2$next[6:0]$7996 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\spr_op__is_32bit$5$next[0:0]$7997 $1\spr_op__insn$4$next[31:0]$7995 $1\spr_op__fn_unit$3$next[11:0]$7994 $1\spr_op__insn_type$2$next[6:0]$7996 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } - case - assign $1\spr_op__fn_unit$3$next[11:0]$7994 \spr_op__fn_unit$3 - assign $1\spr_op__insn$4$next[31:0]$7995 \spr_op__insn$4 - assign $1\spr_op__insn_type$2$next[6:0]$7996 \spr_op__insn_type$2 - assign $1\spr_op__is_32bit$5$next[0:0]$7997 \spr_op__is_32bit$5 - end - sync always - update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[11:0]$7990 - update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$7991 - update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$7992 - update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$7993 - end - attribute \src "issuer_ls180.v:148723.3-148741.6" - process $proc$issuer_ls180.v:148723$7998 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$next[63:0]$7999 $1\o$next[63:0]$8001 - assign { } { } - assign $0\o_ok$next[0:0]$8000 $2\o_ok$next[0:0]$8003 - attribute \src "issuer_ls180.v:148724.5-148724.29" - switch \initial - attribute \src "issuer_ls180.v:148724.9-148724.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$8002 $1\o$next[63:0]$8001 } { \o_ok$30 \o$29 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$8002 $1\o$next[63:0]$8001 } { \o_ok$30 \o$29 } - case - assign $1\o$next[63:0]$8001 \o - assign $1\o_ok$next[0:0]$8002 \o_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o_ok$next[0:0]$8003 1'0 - case - assign $2\o_ok$next[0:0]$8003 $1\o_ok$next[0:0]$8002 - end - sync always - update \o$next $0\o$next[63:0]$7999 - update \o_ok$next $0\o_ok$next[0:0]$8000 - end - attribute \src "issuer_ls180.v:148742.3-148760.6" - process $proc$issuer_ls180.v:148742$8004 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\spr1$6$next[63:0]$8005 $1\spr1$6$next[63:0]$8007 - assign { } { } - assign $0\spr1_ok$next[0:0]$8006 $2\spr1_ok$next[0:0]$8009 - attribute \src "issuer_ls180.v:148743.5-148743.29" - switch \initial - attribute \src "issuer_ls180.v:148743.9-148743.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\spr1_ok$next[0:0]$8008 $1\spr1$6$next[63:0]$8007 } { \spr1_ok$32 \spr1$31 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\spr1_ok$next[0:0]$8008 $1\spr1$6$next[63:0]$8007 } { \spr1_ok$32 \spr1$31 } - case - assign $1\spr1$6$next[63:0]$8007 \spr1$6 - assign $1\spr1_ok$next[0:0]$8008 \spr1_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\spr1_ok$next[0:0]$8009 1'0 - case - assign $2\spr1_ok$next[0:0]$8009 $1\spr1_ok$next[0:0]$8008 - end - sync always - update \spr1$6$next $0\spr1$6$next[63:0]$8005 - update \spr1_ok$next $0\spr1_ok$next[0:0]$8006 - end - attribute \src "issuer_ls180.v:148761.3-148779.6" - process $proc$issuer_ls180.v:148761$8010 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fast1$7$next[63:0]$8012 $1\fast1$7$next[63:0]$8014 - assign $0\fast1_ok$next[0:0]$8011 $2\fast1_ok$next[0:0]$8015 - attribute \src "issuer_ls180.v:148762.5-148762.29" - switch \initial - attribute \src "issuer_ls180.v:148762.9-148762.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\fast1_ok$next[0:0]$8013 $1\fast1$7$next[63:0]$8014 } { \fast1_ok$34 \fast1$33 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\fast1_ok$next[0:0]$8013 $1\fast1$7$next[63:0]$8014 } { \fast1_ok$34 \fast1$33 } - case - assign $1\fast1_ok$next[0:0]$8013 \fast1_ok - assign $1\fast1$7$next[63:0]$8014 \fast1$7 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fast1_ok$next[0:0]$8015 1'0 - case - assign $2\fast1_ok$next[0:0]$8015 $1\fast1_ok$next[0:0]$8013 - end - sync always - update \fast1_ok$next $0\fast1_ok$next[0:0]$8011 - update \fast1$7$next $0\fast1$7$next[63:0]$8012 - end - attribute \src "issuer_ls180.v:148780.3-148798.6" - process $proc$issuer_ls180.v:148780$8016 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_so$8$next[0:0]$8018 $1\xer_so$8$next[0:0]$8020 - assign $0\xer_so_ok$next[0:0]$8017 $2\xer_so_ok$next[0:0]$8021 - attribute \src "issuer_ls180.v:148781.5-148781.29" - switch \initial - attribute \src "issuer_ls180.v:148781.9-148781.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_so_ok$next[0:0]$8019 $1\xer_so$8$next[0:0]$8020 } { \xer_so_ok$36 \xer_so$35 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_so_ok$next[0:0]$8019 $1\xer_so$8$next[0:0]$8020 } { \xer_so_ok$36 \xer_so$35 } - case - assign $1\xer_so_ok$next[0:0]$8019 \xer_so_ok - assign $1\xer_so$8$next[0:0]$8020 \xer_so$8 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_so_ok$next[0:0]$8021 1'0 - case - assign $2\xer_so_ok$next[0:0]$8021 $1\xer_so_ok$next[0:0]$8019 - end - sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8017 - update \xer_so$8$next $0\xer_so$8$next[0:0]$8018 - end - attribute \src "issuer_ls180.v:148799.3-148817.6" - process $proc$issuer_ls180.v:148799$8022 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_ov$9$next[1:0]$8024 $1\xer_ov$9$next[1:0]$8026 - assign $0\xer_ov_ok$next[0:0]$8023 $2\xer_ov_ok$next[0:0]$8027 - attribute \src "issuer_ls180.v:148800.5-148800.29" - switch \initial - attribute \src "issuer_ls180.v:148800.9-148800.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8025 $1\xer_ov$9$next[1:0]$8026 } { \xer_ov_ok$38 \xer_ov$37 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8025 $1\xer_ov$9$next[1:0]$8026 } { \xer_ov_ok$38 \xer_ov$37 } - case - assign $1\xer_ov_ok$next[0:0]$8025 \xer_ov_ok - assign $1\xer_ov$9$next[1:0]$8026 \xer_ov$9 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_ov_ok$next[0:0]$8027 1'0 - case - assign $2\xer_ov_ok$next[0:0]$8027 $1\xer_ov_ok$next[0:0]$8025 - end - sync always - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8023 - update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8024 - end - attribute \src "issuer_ls180.v:148818.3-148836.6" - process $proc$issuer_ls180.v:148818$8028 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_ca$10$next[1:0]$8029 $1\xer_ca$10$next[1:0]$8031 - assign { } { } - assign $0\xer_ca_ok$next[0:0]$8030 $2\xer_ca_ok$next[0:0]$8033 - attribute \src "issuer_ls180.v:148819.5-148819.29" - switch \initial - attribute \src "issuer_ls180.v:148819.9-148819.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8032 $1\xer_ca$10$next[1:0]$8031 } { \xer_ca_ok$40 \xer_ca$39 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8032 $1\xer_ca$10$next[1:0]$8031 } { \xer_ca_ok$40 \xer_ca$39 } - case - assign $1\xer_ca$10$next[1:0]$8031 \xer_ca$10 - assign $1\xer_ca_ok$next[0:0]$8032 \xer_ca_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_ca_ok$next[0:0]$8033 1'0 - case - assign $2\xer_ca_ok$next[0:0]$8033 $1\xer_ca_ok$next[0:0]$8032 - end - sync always - update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8029 - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8030 - end - connect \$22 $and$issuer_ls180.v:148601$7953_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 } - connect { \xer_ov_ok$38 \xer_ov$37 } { \spr_main_xer_ov_ok \spr_main_xer_ov$19 } - connect { \xer_so_ok$36 \xer_so$35 } { \spr_main_xer_so_ok \spr_main_xer_so$18 } - connect { \fast1_ok$34 \fast1$33 } { \spr_main_fast1_ok \spr_main_fast1$17 } - connect { \spr1_ok$32 \spr1$31 } { \spr_main_spr1_ok \spr_main_spr1$16 } - connect { \o_ok$30 \o$29 } { \spr_main_o_ok \spr_main_o } - connect { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } { \spr_main_spr_op__is_32bit$15 \spr_main_spr_op__insn$14 \spr_main_spr_op__fn_unit$13 \spr_main_spr_op__insn_type$12 } - connect \muxid$24 \spr_main_muxid$11 - connect \p_valid_i_p_ready_o \$22 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$21 \p_valid_i - connect \spr_main_xer_ca \xer_ca - connect \spr_main_xer_ov \xer_ov - connect \spr_main_xer_so \xer_so - connect \spr_main_fast1 \fast1 - connect \spr_main_spr1 \spr1 - connect \spr_main_ra \ra - connect { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } - connect \spr_main_muxid \muxid -end -attribute \src "issuer_ls180.v:148862.1-150333.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1" -attribute \generator "nMigen" -module \pipe1 - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire width 4 $0\alu_op__data_len$next[3:0]$8126 - attribute \src "issuer_ls180.v:150023.3-150024.49" - wire width 4 $0\alu_op__data_len[3:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire width 12 $0\alu_op__fn_unit$next[11:0]$8127 - attribute \src "issuer_ls180.v:149993.3-149994.47" - wire width 12 $0\alu_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire width 64 $0\alu_op__imm_data__data$next[63:0]$8128 - attribute \src "issuer_ls180.v:149995.3-149996.61" - wire width 64 $0\alu_op__imm_data__data[63:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $0\alu_op__imm_data__ok$next[0:0]$8129 - attribute \src "issuer_ls180.v:149997.3-149998.57" - wire $0\alu_op__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire width 2 $0\alu_op__input_carry$next[1:0]$8130 - attribute \src "issuer_ls180.v:150015.3-150016.55" - wire width 2 $0\alu_op__input_carry[1:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire width 32 $0\alu_op__insn$next[31:0]$8131 - attribute \src "issuer_ls180.v:150025.3-150026.41" - wire width 32 $0\alu_op__insn[31:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire width 7 $0\alu_op__insn_type$next[6:0]$8132 - attribute \src "issuer_ls180.v:149991.3-149992.51" - wire width 7 $0\alu_op__insn_type[6:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $0\alu_op__invert_in$next[0:0]$8133 - attribute \src "issuer_ls180.v:150007.3-150008.51" - wire $0\alu_op__invert_in[0:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $0\alu_op__invert_out$next[0:0]$8134 - attribute \src "issuer_ls180.v:150011.3-150012.53" - wire $0\alu_op__invert_out[0:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $0\alu_op__is_32bit$next[0:0]$8135 - attribute \src "issuer_ls180.v:150019.3-150020.49" - wire $0\alu_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $0\alu_op__is_signed$next[0:0]$8136 - attribute \src "issuer_ls180.v:150021.3-150022.51" - wire $0\alu_op__is_signed[0:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $0\alu_op__oe__oe$next[0:0]$8137 - attribute \src "issuer_ls180.v:150003.3-150004.45" - wire $0\alu_op__oe__oe[0:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $0\alu_op__oe__ok$next[0:0]$8138 - attribute \src "issuer_ls180.v:150005.3-150006.45" - wire $0\alu_op__oe__ok[0:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $0\alu_op__output_carry$next[0:0]$8139 - attribute \src "issuer_ls180.v:150017.3-150018.57" - wire $0\alu_op__output_carry[0:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $0\alu_op__rc__ok$next[0:0]$8140 - attribute \src "issuer_ls180.v:150001.3-150002.45" - wire $0\alu_op__rc__ok[0:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $0\alu_op__rc__rc$next[0:0]$8141 - attribute \src "issuer_ls180.v:149999.3-150000.45" - wire $0\alu_op__rc__rc[0:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $0\alu_op__write_cr0$next[0:0]$8142 - attribute \src "issuer_ls180.v:150013.3-150014.51" - wire $0\alu_op__write_cr0[0:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $0\alu_op__zero_a$next[0:0]$8143 - attribute \src "issuer_ls180.v:150009.3-150010.45" - wire $0\alu_op__zero_a[0:0] - attribute \src "issuer_ls180.v:150140.3-150158.6" - wire width 4 $0\cr_a$next[3:0]$8095 - attribute \src "issuer_ls180.v:149983.3-149984.25" - wire width 4 $0\cr_a[3:0] - attribute \src "issuer_ls180.v:150140.3-150158.6" - wire $0\cr_a_ok$next[0:0]$8096 - attribute \src "issuer_ls180.v:149985.3-149986.31" - wire $0\cr_a_ok[0:0] - attribute \src "issuer_ls180.v:148863.7-148863.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:150234.3-150246.6" - wire width 2 $0\muxid$next[1:0]$8123 - attribute \src "issuer_ls180.v:150027.3-150028.27" - wire width 2 $0\muxid[1:0] - attribute \src "issuer_ls180.v:150289.3-150307.6" - wire width 64 $0\o$next[63:0]$8169 - attribute \src "issuer_ls180.v:149987.3-149988.19" - wire width 64 $0\o[63:0] - attribute \src "issuer_ls180.v:150289.3-150307.6" - wire $0\o_ok$next[0:0]$8170 - attribute \src "issuer_ls180.v:149989.3-149990.25" - wire $0\o_ok[0:0] - attribute \src "issuer_ls180.v:150216.3-150233.6" - wire $0\r_busy$next[0:0]$8119 - attribute \src "issuer_ls180.v:150029.3-150030.29" - wire $0\r_busy[0:0] - attribute \src "issuer_ls180.v:150159.3-150177.6" - wire width 2 $0\xer_ca$next[1:0]$8102 - attribute \src "issuer_ls180.v:149979.3-149980.29" - wire width 2 $0\xer_ca[1:0] - attribute \src "issuer_ls180.v:150159.3-150177.6" - wire $0\xer_ca_ok$next[0:0]$8101 - attribute \src "issuer_ls180.v:149981.3-149982.35" - wire $0\xer_ca_ok[0:0] - attribute \src "issuer_ls180.v:150178.3-150196.6" - wire width 2 $0\xer_ov$next[1:0]$8107 - attribute \src "issuer_ls180.v:149975.3-149976.29" - wire width 2 $0\xer_ov[1:0] - attribute \src "issuer_ls180.v:150178.3-150196.6" - wire $0\xer_ov_ok$next[0:0]$8108 - attribute \src "issuer_ls180.v:149977.3-149978.35" - wire $0\xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:150197.3-150215.6" - wire $0\xer_so$next[0:0]$8113 - attribute \src "issuer_ls180.v:149971.3-149972.29" - wire $0\xer_so[0:0] - attribute \src "issuer_ls180.v:150197.3-150215.6" - wire $0\xer_so_ok$next[0:0]$8114 - attribute \src "issuer_ls180.v:149973.3-149974.35" - wire $0\xer_so_ok[0:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire width 4 $1\alu_op__data_len$next[3:0]$8144 - attribute \src "issuer_ls180.v:148868.13-148868.36" - wire width 4 $1\alu_op__data_len[3:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire width 12 $1\alu_op__fn_unit$next[11:0]$8145 - attribute \src "issuer_ls180.v:148890.14-148890.39" - wire width 12 $1\alu_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire width 64 $1\alu_op__imm_data__data$next[63:0]$8146 - attribute \src "issuer_ls180.v:148925.14-148925.59" - wire width 64 $1\alu_op__imm_data__data[63:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $1\alu_op__imm_data__ok$next[0:0]$8147 - attribute \src "issuer_ls180.v:148934.7-148934.34" - wire $1\alu_op__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire width 2 $1\alu_op__input_carry$next[1:0]$8148 - attribute \src "issuer_ls180.v:148947.13-148947.39" - wire width 2 $1\alu_op__input_carry[1:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire width 32 $1\alu_op__insn$next[31:0]$8149 - attribute \src "issuer_ls180.v:148964.14-148964.34" - wire width 32 $1\alu_op__insn[31:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire width 7 $1\alu_op__insn_type$next[6:0]$8150 - attribute \src "issuer_ls180.v:149047.13-149047.38" - wire width 7 $1\alu_op__insn_type[6:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $1\alu_op__invert_in$next[0:0]$8151 - attribute \src "issuer_ls180.v:149204.7-149204.31" - wire $1\alu_op__invert_in[0:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $1\alu_op__invert_out$next[0:0]$8152 - attribute \src "issuer_ls180.v:149213.7-149213.32" - wire $1\alu_op__invert_out[0:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $1\alu_op__is_32bit$next[0:0]$8153 - attribute \src "issuer_ls180.v:149222.7-149222.30" - wire $1\alu_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $1\alu_op__is_signed$next[0:0]$8154 - attribute \src "issuer_ls180.v:149231.7-149231.31" - wire $1\alu_op__is_signed[0:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $1\alu_op__oe__oe$next[0:0]$8155 - attribute \src "issuer_ls180.v:149240.7-149240.28" - wire $1\alu_op__oe__oe[0:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $1\alu_op__oe__ok$next[0:0]$8156 - attribute \src "issuer_ls180.v:149249.7-149249.28" - wire $1\alu_op__oe__ok[0:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $1\alu_op__output_carry$next[0:0]$8157 - attribute \src "issuer_ls180.v:149258.7-149258.34" - wire $1\alu_op__output_carry[0:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $1\alu_op__rc__ok$next[0:0]$8158 - attribute \src "issuer_ls180.v:149267.7-149267.28" - wire $1\alu_op__rc__ok[0:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $1\alu_op__rc__rc$next[0:0]$8159 - attribute \src "issuer_ls180.v:149276.7-149276.28" - wire $1\alu_op__rc__rc[0:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $1\alu_op__write_cr0$next[0:0]$8160 - attribute \src "issuer_ls180.v:149285.7-149285.31" - wire $1\alu_op__write_cr0[0:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $1\alu_op__zero_a$next[0:0]$8161 - attribute \src "issuer_ls180.v:149294.7-149294.28" - wire $1\alu_op__zero_a[0:0] - attribute \src "issuer_ls180.v:150140.3-150158.6" - wire width 4 $1\cr_a$next[3:0]$8097 - attribute \src "issuer_ls180.v:149307.13-149307.24" - wire width 4 $1\cr_a[3:0] - attribute \src "issuer_ls180.v:150140.3-150158.6" - wire $1\cr_a_ok$next[0:0]$8098 - attribute \src "issuer_ls180.v:149314.7-149314.21" - wire $1\cr_a_ok[0:0] - attribute \src "issuer_ls180.v:150234.3-150246.6" - wire width 2 $1\muxid$next[1:0]$8124 - attribute \src "issuer_ls180.v:149879.13-149879.25" - wire width 2 $1\muxid[1:0] - attribute \src "issuer_ls180.v:150289.3-150307.6" - wire width 64 $1\o$next[63:0]$8171 - attribute \src "issuer_ls180.v:149894.14-149894.38" - wire width 64 $1\o[63:0] - attribute \src "issuer_ls180.v:150289.3-150307.6" - wire $1\o_ok$next[0:0]$8172 - attribute \src "issuer_ls180.v:149901.7-149901.18" - wire $1\o_ok[0:0] - attribute \src "issuer_ls180.v:150216.3-150233.6" - wire $1\r_busy$next[0:0]$8120 - attribute \src "issuer_ls180.v:149915.7-149915.20" - wire $1\r_busy[0:0] - attribute \src "issuer_ls180.v:150159.3-150177.6" - wire width 2 $1\xer_ca$next[1:0]$8104 - attribute \src "issuer_ls180.v:149924.13-149924.26" - wire width 2 $1\xer_ca[1:0] - attribute \src "issuer_ls180.v:150159.3-150177.6" - wire $1\xer_ca_ok$next[0:0]$8103 - attribute \src "issuer_ls180.v:149933.7-149933.23" - wire $1\xer_ca_ok[0:0] - attribute \src "issuer_ls180.v:150178.3-150196.6" - wire width 2 $1\xer_ov$next[1:0]$8109 - attribute \src "issuer_ls180.v:149940.13-149940.26" - wire width 2 $1\xer_ov[1:0] - attribute \src "issuer_ls180.v:150178.3-150196.6" - wire $1\xer_ov_ok$next[0:0]$8110 - attribute \src "issuer_ls180.v:149947.7-149947.23" - wire $1\xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:150197.3-150215.6" - wire $1\xer_so$next[0:0]$8115 - attribute \src "issuer_ls180.v:149954.7-149954.20" - wire $1\xer_so[0:0] - attribute \src "issuer_ls180.v:150197.3-150215.6" - wire $1\xer_so_ok$next[0:0]$8116 - attribute \src "issuer_ls180.v:149963.7-149963.23" - wire $1\xer_so_ok[0:0] - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire width 64 $2\alu_op__imm_data__data$next[63:0]$8162 - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $2\alu_op__imm_data__ok$next[0:0]$8163 - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $2\alu_op__oe__oe$next[0:0]$8164 - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $2\alu_op__oe__ok$next[0:0]$8165 - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $2\alu_op__rc__ok$next[0:0]$8166 - attribute \src "issuer_ls180.v:150247.3-150288.6" - wire $2\alu_op__rc__rc$next[0:0]$8167 - attribute \src "issuer_ls180.v:150140.3-150158.6" - wire $2\cr_a_ok$next[0:0]$8099 - attribute \src "issuer_ls180.v:150289.3-150307.6" - wire $2\o_ok$next[0:0]$8173 - attribute \src "issuer_ls180.v:150216.3-150233.6" - wire $2\r_busy$next[0:0]$8121 - attribute \src "issuer_ls180.v:150159.3-150177.6" - wire $2\xer_ca_ok$next[0:0]$8105 - attribute \src "issuer_ls180.v:150178.3-150196.6" - wire $2\xer_ov_ok$next[0:0]$8111 - attribute \src "issuer_ls180.v:150197.3-150215.6" - wire $2\xer_so_ok$next[0:0]$8117 - attribute \src "issuer_ls180.v:149970.18-149970.118" - wire $and$issuer_ls180.v:149970$8063_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 21 \alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 52 \alu_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 6 \alu_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 37 \alu_op__fn_unit$3 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_op__fn_unit$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 38 \alu_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__data$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 39 \alu_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__imm_data__ok$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__imm_data__ok$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 17 \alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 48 \alu_op__input_carry$14 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 22 \alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 53 \alu_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 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attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 5 \alu_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 36 \alu_op__insn_type$2 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 44 \alu_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_in$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 46 \alu_op__invert_out$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_out$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 19 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 50 \alu_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_32bit$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 51 \alu_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_signed$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__oe$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 42 \alu_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__ok$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 43 \alu_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 18 \alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 49 \alu_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__output_carry$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 41 \alu_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__ok$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 40 \alu_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__rc$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 47 \alu_op__write_cr0$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__write_cr0$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 45 \alu_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__zero_a$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 58 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 26 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$next - attribute \src "issuer_ls180.v:148863.7-148863.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_alu_op__data_len$39 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_alu_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_alu_op__fn_unit$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_alu_op__imm_data__data$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__imm_data__ok$26 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_alu_op__input_carry$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_alu_op__insn$40 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_alu_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__is_32bit$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__is_signed$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__oe__oe$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__oe__ok$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__zero_a$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \input_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \input_xer_ca$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \main_alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \main_alu_op__data_len$62 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_alu_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_alu_op__fn_unit$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_alu_op__imm_data__data$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__imm_data__ok$49 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_alu_op__input_carry$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_alu_op__insn - attribute \src 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attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__invert_out$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__is_32bit$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__is_signed$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__oe__oe$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire 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"/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \main_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \main_xer_ca$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \main_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \main_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_xer_so$65 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 35 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$69 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 3 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 23 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 24 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 34 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 33 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$66 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 54 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 55 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 27 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 57 \xer_ca$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 28 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ca_ok$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ca_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 29 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 30 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ov_ok$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 31 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 56 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 32 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$issuer_ls180.v:149970$8063 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$66 - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:149970$8063_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:150031.11-150078.4" - cell \input \input - connect \alu_op__data_len \input_alu_op__data_len - connect \alu_op__data_len$18 \input_alu_op__data_len$39 - connect \alu_op__fn_unit \input_alu_op__fn_unit - connect \alu_op__fn_unit$3 \input_alu_op__fn_unit$24 - connect \alu_op__imm_data__data \input_alu_op__imm_data__data - connect \alu_op__imm_data__data$4 \input_alu_op__imm_data__data$25 - connect \alu_op__imm_data__ok \input_alu_op__imm_data__ok - connect \alu_op__imm_data__ok$5 \input_alu_op__imm_data__ok$26 - connect \alu_op__input_carry \input_alu_op__input_carry - connect \alu_op__input_carry$14 \input_alu_op__input_carry$35 - connect \alu_op__insn \input_alu_op__insn - connect \alu_op__insn$19 \input_alu_op__insn$40 - connect \alu_op__insn_type \input_alu_op__insn_type - connect \alu_op__insn_type$2 \input_alu_op__insn_type$23 - connect \alu_op__invert_in \input_alu_op__invert_in - connect \alu_op__invert_in$10 \input_alu_op__invert_in$31 - connect \alu_op__invert_out \input_alu_op__invert_out - connect \alu_op__invert_out$12 \input_alu_op__invert_out$33 - connect \alu_op__is_32bit \input_alu_op__is_32bit - connect \alu_op__is_32bit$16 \input_alu_op__is_32bit$37 - connect \alu_op__is_signed \input_alu_op__is_signed - connect \alu_op__is_signed$17 \input_alu_op__is_signed$38 - connect \alu_op__oe__oe \input_alu_op__oe__oe - connect \alu_op__oe__oe$8 \input_alu_op__oe__oe$29 - connect \alu_op__oe__ok \input_alu_op__oe__ok - connect \alu_op__oe__ok$9 \input_alu_op__oe__ok$30 - connect \alu_op__output_carry \input_alu_op__output_carry - connect \alu_op__output_carry$15 \input_alu_op__output_carry$36 - connect \alu_op__rc__ok \input_alu_op__rc__ok - connect \alu_op__rc__ok$7 \input_alu_op__rc__ok$28 - connect \alu_op__rc__rc \input_alu_op__rc__rc - connect \alu_op__rc__rc$6 \input_alu_op__rc__rc$27 - connect \alu_op__write_cr0 \input_alu_op__write_cr0 - connect \alu_op__write_cr0$13 \input_alu_op__write_cr0$34 - connect \alu_op__zero_a \input_alu_op__zero_a - connect \alu_op__zero_a$11 \input_alu_op__zero_a$32 - connect \muxid \input_muxid - connect \muxid$1 \input_muxid$22 - connect \ra \input_ra - connect \ra$20 \input_ra$41 - connect \rb \input_rb - connect \rb$21 \input_rb$42 - connect \xer_ca \input_xer_ca - connect \xer_ca$23 \input_xer_ca$44 - connect \xer_so \input_xer_so - connect \xer_so$22 \input_xer_so$43 - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:150079.8-150131.4" - cell \main \main - connect \alu_op__data_len \main_alu_op__data_len - connect \alu_op__data_len$18 \main_alu_op__data_len$62 - connect \alu_op__fn_unit \main_alu_op__fn_unit - connect \alu_op__fn_unit$3 \main_alu_op__fn_unit$47 - connect \alu_op__imm_data__data \main_alu_op__imm_data__data - connect \alu_op__imm_data__data$4 \main_alu_op__imm_data__data$48 - connect \alu_op__imm_data__ok \main_alu_op__imm_data__ok - connect \alu_op__imm_data__ok$5 \main_alu_op__imm_data__ok$49 - connect \alu_op__input_carry \main_alu_op__input_carry - connect \alu_op__input_carry$14 \main_alu_op__input_carry$58 - connect \alu_op__insn \main_alu_op__insn - connect \alu_op__insn$19 \main_alu_op__insn$63 - connect \alu_op__insn_type \main_alu_op__insn_type - connect \alu_op__insn_type$2 \main_alu_op__insn_type$46 - connect \alu_op__invert_in \main_alu_op__invert_in - connect \alu_op__invert_in$10 \main_alu_op__invert_in$54 - connect \alu_op__invert_out \main_alu_op__invert_out - connect \alu_op__invert_out$12 \main_alu_op__invert_out$56 - connect \alu_op__is_32bit \main_alu_op__is_32bit - connect \alu_op__is_32bit$16 \main_alu_op__is_32bit$60 - connect \alu_op__is_signed \main_alu_op__is_signed - connect \alu_op__is_signed$17 \main_alu_op__is_signed$61 - connect \alu_op__oe__oe \main_alu_op__oe__oe - connect \alu_op__oe__oe$8 \main_alu_op__oe__oe$52 - connect \alu_op__oe__ok \main_alu_op__oe__ok - connect \alu_op__oe__ok$9 \main_alu_op__oe__ok$53 - connect \alu_op__output_carry \main_alu_op__output_carry - connect \alu_op__output_carry$15 \main_alu_op__output_carry$59 - connect \alu_op__rc__ok \main_alu_op__rc__ok - connect \alu_op__rc__ok$7 \main_alu_op__rc__ok$51 - connect \alu_op__rc__rc \main_alu_op__rc__rc - connect \alu_op__rc__rc$6 \main_alu_op__rc__rc$50 - connect \alu_op__write_cr0 \main_alu_op__write_cr0 - connect \alu_op__write_cr0$13 \main_alu_op__write_cr0$57 - connect \alu_op__zero_a \main_alu_op__zero_a - connect \alu_op__zero_a$11 \main_alu_op__zero_a$55 - connect \cr_a \main_cr_a - connect \cr_a_ok \main_cr_a_ok - connect \muxid \main_muxid - connect \muxid$1 \main_muxid$45 - connect \o \main_o - connect \o_ok \main_o_ok - connect \ra \main_ra - connect \rb \main_rb - connect \xer_ca \main_xer_ca - connect \xer_ca$20 \main_xer_ca$64 - connect \xer_ca_ok \main_xer_ca_ok - connect \xer_ov \main_xer_ov - connect \xer_ov_ok \main_xer_ov_ok - connect \xer_so \main_xer_so - connect \xer_so$21 \main_xer_so$65 - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:150132.9-150135.4" - cell \n$2 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:150136.9-150139.4" - cell \p$1 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "issuer_ls180.v:148863.7-148863.20" - process $proc$issuer_ls180.v:148863$8174 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:148868.13-148868.36" - process $proc$issuer_ls180.v:148868$8175 - assign { } { } - assign $1\alu_op__data_len[3:0] 4'0000 - sync always - sync init - update \alu_op__data_len $1\alu_op__data_len[3:0] - end - attribute \src "issuer_ls180.v:148890.14-148890.39" - process $proc$issuer_ls180.v:148890$8176 - assign { } { } - assign $1\alu_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \alu_op__fn_unit $1\alu_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:148925.14-148925.59" - process $proc$issuer_ls180.v:148925$8177 - assign { } { } - assign $1\alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_op__imm_data__data $1\alu_op__imm_data__data[63:0] - end - attribute \src "issuer_ls180.v:148934.7-148934.34" - process $proc$issuer_ls180.v:148934$8178 - assign { } { } - assign $1\alu_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \alu_op__imm_data__ok $1\alu_op__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:148947.13-148947.39" - process $proc$issuer_ls180.v:148947$8179 - assign { } { } - assign $1\alu_op__input_carry[1:0] 2'00 - sync always - sync init - update \alu_op__input_carry $1\alu_op__input_carry[1:0] - end - attribute \src "issuer_ls180.v:148964.14-148964.34" - process $proc$issuer_ls180.v:148964$8180 - assign { } { } - assign $1\alu_op__insn[31:0] 0 - sync always - sync init - update \alu_op__insn $1\alu_op__insn[31:0] - end - attribute \src "issuer_ls180.v:149047.13-149047.38" - process $proc$issuer_ls180.v:149047$8181 - assign { } { } - assign $1\alu_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \alu_op__insn_type $1\alu_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:149204.7-149204.31" - process $proc$issuer_ls180.v:149204$8182 - assign { } { } - assign $1\alu_op__invert_in[0:0] 1'0 - sync always - sync init - update \alu_op__invert_in $1\alu_op__invert_in[0:0] - end - attribute \src "issuer_ls180.v:149213.7-149213.32" - process $proc$issuer_ls180.v:149213$8183 - assign { } { } - assign $1\alu_op__invert_out[0:0] 1'0 - sync always - sync init - update \alu_op__invert_out $1\alu_op__invert_out[0:0] - end - attribute \src "issuer_ls180.v:149222.7-149222.30" - process $proc$issuer_ls180.v:149222$8184 - assign { } { } - assign $1\alu_op__is_32bit[0:0] 1'0 - sync always - sync init - update \alu_op__is_32bit $1\alu_op__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:149231.7-149231.31" - process $proc$issuer_ls180.v:149231$8185 - assign { } { } - assign $1\alu_op__is_signed[0:0] 1'0 - sync always - sync init - update \alu_op__is_signed $1\alu_op__is_signed[0:0] - end - attribute \src "issuer_ls180.v:149240.7-149240.28" - process $proc$issuer_ls180.v:149240$8186 - assign { } { } - assign $1\alu_op__oe__oe[0:0] 1'0 - sync always - sync init - update \alu_op__oe__oe $1\alu_op__oe__oe[0:0] - end - attribute \src "issuer_ls180.v:149249.7-149249.28" - process $proc$issuer_ls180.v:149249$8187 - assign { } { } - assign $1\alu_op__oe__ok[0:0] 1'0 - sync always - sync init - update \alu_op__oe__ok $1\alu_op__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:149258.7-149258.34" - process $proc$issuer_ls180.v:149258$8188 - assign { } { } - assign $1\alu_op__output_carry[0:0] 1'0 - sync always - sync init - update \alu_op__output_carry $1\alu_op__output_carry[0:0] - end - attribute \src "issuer_ls180.v:149267.7-149267.28" - process $proc$issuer_ls180.v:149267$8189 - assign { } { } - assign $1\alu_op__rc__ok[0:0] 1'0 - sync always - sync init - update \alu_op__rc__ok $1\alu_op__rc__ok[0:0] - end - attribute \src "issuer_ls180.v:149276.7-149276.28" - process $proc$issuer_ls180.v:149276$8190 - assign { } { } - assign $1\alu_op__rc__rc[0:0] 1'0 - sync always - sync init - update \alu_op__rc__rc $1\alu_op__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:149285.7-149285.31" - process $proc$issuer_ls180.v:149285$8191 - assign { } { } - assign $1\alu_op__write_cr0[0:0] 1'0 - sync always - sync init - update \alu_op__write_cr0 $1\alu_op__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:149294.7-149294.28" - process $proc$issuer_ls180.v:149294$8192 - assign { } { } - assign $1\alu_op__zero_a[0:0] 1'0 - sync always - sync init - update \alu_op__zero_a $1\alu_op__zero_a[0:0] - end - attribute \src "issuer_ls180.v:149307.13-149307.24" - process $proc$issuer_ls180.v:149307$8193 - assign { } { } - assign $1\cr_a[3:0] 4'0000 - sync always - sync init - update \cr_a $1\cr_a[3:0] - end - attribute \src "issuer_ls180.v:149314.7-149314.21" - process $proc$issuer_ls180.v:149314$8194 - assign { } { } - assign $1\cr_a_ok[0:0] 1'0 - sync always - sync init - update \cr_a_ok $1\cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:149879.13-149879.25" - process $proc$issuer_ls180.v:149879$8195 - assign { } { } - assign $1\muxid[1:0] 2'00 - sync always - sync init - update \muxid $1\muxid[1:0] - end - attribute \src "issuer_ls180.v:149894.14-149894.38" - process $proc$issuer_ls180.v:149894$8196 - assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o $1\o[63:0] - end - attribute \src "issuer_ls180.v:149901.7-149901.18" - process $proc$issuer_ls180.v:149901$8197 - assign { } { } - assign $1\o_ok[0:0] 1'0 - sync always - sync init - update \o_ok $1\o_ok[0:0] - end - attribute \src "issuer_ls180.v:149915.7-149915.20" - process $proc$issuer_ls180.v:149915$8198 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "issuer_ls180.v:149924.13-149924.26" - process $proc$issuer_ls180.v:149924$8199 - assign { } { } - assign $1\xer_ca[1:0] 2'00 - sync always - sync init - update \xer_ca $1\xer_ca[1:0] - end - attribute \src "issuer_ls180.v:149933.7-149933.23" - process $proc$issuer_ls180.v:149933$8200 - assign { } { } - assign $1\xer_ca_ok[0:0] 1'0 - sync always - sync init - update \xer_ca_ok $1\xer_ca_ok[0:0] - end - attribute \src "issuer_ls180.v:149940.13-149940.26" - process $proc$issuer_ls180.v:149940$8201 - assign { } { } - assign $1\xer_ov[1:0] 2'00 - sync always - sync init - update \xer_ov $1\xer_ov[1:0] - end - attribute \src "issuer_ls180.v:149947.7-149947.23" - process $proc$issuer_ls180.v:149947$8202 - assign { } { } - assign $1\xer_ov_ok[0:0] 1'0 - sync always - sync init - update \xer_ov_ok $1\xer_ov_ok[0:0] - end - attribute \src "issuer_ls180.v:149954.7-149954.20" - process $proc$issuer_ls180.v:149954$8203 - assign { } { } - assign $1\xer_so[0:0] 1'0 - sync always - sync init - update \xer_so $1\xer_so[0:0] - end - attribute \src "issuer_ls180.v:149963.7-149963.23" - process $proc$issuer_ls180.v:149963$8204 - assign { } { } - assign $1\xer_so_ok[0:0] 1'0 - sync always - sync init - update \xer_so_ok $1\xer_so_ok[0:0] - end - attribute \src "issuer_ls180.v:149971.3-149972.29" - process $proc$issuer_ls180.v:149971$8064 - assign { } { } - assign $0\xer_so[0:0] \xer_so$next - sync posedge \coresync_clk - update \xer_so $0\xer_so[0:0] - end - attribute \src "issuer_ls180.v:149973.3-149974.35" - process $proc$issuer_ls180.v:149973$8065 - assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next - sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] - end - attribute \src "issuer_ls180.v:149975.3-149976.29" - process $proc$issuer_ls180.v:149975$8066 - assign { } { } - assign $0\xer_ov[1:0] \xer_ov$next - sync posedge \coresync_clk - update \xer_ov $0\xer_ov[1:0] - end - attribute \src "issuer_ls180.v:149977.3-149978.35" - process $proc$issuer_ls180.v:149977$8067 - assign { } { } - assign $0\xer_ov_ok[0:0] \xer_ov_ok$next - sync posedge \coresync_clk - update \xer_ov_ok $0\xer_ov_ok[0:0] - end - attribute \src "issuer_ls180.v:149979.3-149980.29" - process $proc$issuer_ls180.v:149979$8068 - assign { } { } - assign $0\xer_ca[1:0] \xer_ca$next - sync posedge \coresync_clk - update \xer_ca $0\xer_ca[1:0] - end - attribute \src "issuer_ls180.v:149981.3-149982.35" - process $proc$issuer_ls180.v:149981$8069 - assign { } { } - assign $0\xer_ca_ok[0:0] \xer_ca_ok$next - sync posedge \coresync_clk - update \xer_ca_ok $0\xer_ca_ok[0:0] - end - attribute \src "issuer_ls180.v:149983.3-149984.25" - process $proc$issuer_ls180.v:149983$8070 - assign { } { } - assign $0\cr_a[3:0] \cr_a$next - sync posedge \coresync_clk - update \cr_a $0\cr_a[3:0] - end - attribute \src "issuer_ls180.v:149985.3-149986.31" - process $proc$issuer_ls180.v:149985$8071 - assign { } { } - assign $0\cr_a_ok[0:0] \cr_a_ok$next - sync posedge \coresync_clk - update \cr_a_ok $0\cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:149987.3-149988.19" - process $proc$issuer_ls180.v:149987$8072 - assign { } { } - assign $0\o[63:0] \o$next - sync posedge \coresync_clk - update \o $0\o[63:0] - end - attribute \src "issuer_ls180.v:149989.3-149990.25" - process $proc$issuer_ls180.v:149989$8073 - assign { } { } - assign $0\o_ok[0:0] \o_ok$next - sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] - end - attribute \src "issuer_ls180.v:149991.3-149992.51" - process $proc$issuer_ls180.v:149991$8074 - assign { } { } - assign $0\alu_op__insn_type[6:0] \alu_op__insn_type$next - sync posedge \coresync_clk - update \alu_op__insn_type $0\alu_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:149993.3-149994.47" - process $proc$issuer_ls180.v:149993$8075 - assign { } { } - assign $0\alu_op__fn_unit[11:0] \alu_op__fn_unit$next - sync posedge \coresync_clk - update \alu_op__fn_unit $0\alu_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:149995.3-149996.61" - process $proc$issuer_ls180.v:149995$8076 - assign { } { } - assign $0\alu_op__imm_data__data[63:0] \alu_op__imm_data__data$next - sync posedge \coresync_clk - update \alu_op__imm_data__data $0\alu_op__imm_data__data[63:0] - end - attribute \src "issuer_ls180.v:149997.3-149998.57" - process $proc$issuer_ls180.v:149997$8077 - assign { } { } - assign $0\alu_op__imm_data__ok[0:0] \alu_op__imm_data__ok$next - sync posedge \coresync_clk - update \alu_op__imm_data__ok $0\alu_op__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:149999.3-150000.45" - process $proc$issuer_ls180.v:149999$8078 - assign { } { } - assign $0\alu_op__rc__rc[0:0] \alu_op__rc__rc$next - sync posedge \coresync_clk - update \alu_op__rc__rc $0\alu_op__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:150001.3-150002.45" - process $proc$issuer_ls180.v:150001$8079 - assign { } { } - assign $0\alu_op__rc__ok[0:0] \alu_op__rc__ok$next - sync posedge \coresync_clk - update \alu_op__rc__ok $0\alu_op__rc__ok[0:0] - end - attribute \src "issuer_ls180.v:150003.3-150004.45" - process $proc$issuer_ls180.v:150003$8080 - assign { } { } - assign $0\alu_op__oe__oe[0:0] \alu_op__oe__oe$next - sync posedge \coresync_clk - update \alu_op__oe__oe $0\alu_op__oe__oe[0:0] - end - attribute \src "issuer_ls180.v:150005.3-150006.45" - process $proc$issuer_ls180.v:150005$8081 - assign { } { } - assign $0\alu_op__oe__ok[0:0] \alu_op__oe__ok$next - sync posedge \coresync_clk - update \alu_op__oe__ok $0\alu_op__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:150007.3-150008.51" - process $proc$issuer_ls180.v:150007$8082 - assign { } { } - assign $0\alu_op__invert_in[0:0] \alu_op__invert_in$next - sync posedge \coresync_clk - update \alu_op__invert_in $0\alu_op__invert_in[0:0] - end - attribute \src "issuer_ls180.v:150009.3-150010.45" - process $proc$issuer_ls180.v:150009$8083 - assign { } { } - assign $0\alu_op__zero_a[0:0] \alu_op__zero_a$next - sync posedge \coresync_clk - update \alu_op__zero_a $0\alu_op__zero_a[0:0] - end - attribute \src "issuer_ls180.v:150011.3-150012.53" - process $proc$issuer_ls180.v:150011$8084 - assign { } { } - assign $0\alu_op__invert_out[0:0] \alu_op__invert_out$next - sync posedge \coresync_clk - update \alu_op__invert_out $0\alu_op__invert_out[0:0] - end - attribute \src "issuer_ls180.v:150013.3-150014.51" - process $proc$issuer_ls180.v:150013$8085 - assign { } { } - assign $0\alu_op__write_cr0[0:0] \alu_op__write_cr0$next - sync posedge \coresync_clk - update \alu_op__write_cr0 $0\alu_op__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:150015.3-150016.55" - process $proc$issuer_ls180.v:150015$8086 - assign { } { } - assign $0\alu_op__input_carry[1:0] \alu_op__input_carry$next - sync posedge \coresync_clk - update \alu_op__input_carry $0\alu_op__input_carry[1:0] - end - attribute \src "issuer_ls180.v:150017.3-150018.57" - process $proc$issuer_ls180.v:150017$8087 - assign { } { } - assign $0\alu_op__output_carry[0:0] \alu_op__output_carry$next - sync posedge \coresync_clk - update \alu_op__output_carry $0\alu_op__output_carry[0:0] - end - attribute \src "issuer_ls180.v:150019.3-150020.49" - process $proc$issuer_ls180.v:150019$8088 - assign { } { } - assign $0\alu_op__is_32bit[0:0] \alu_op__is_32bit$next - sync posedge \coresync_clk - update \alu_op__is_32bit $0\alu_op__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:150021.3-150022.51" - process $proc$issuer_ls180.v:150021$8089 - assign { } { } - assign $0\alu_op__is_signed[0:0] \alu_op__is_signed$next - sync posedge \coresync_clk - update \alu_op__is_signed $0\alu_op__is_signed[0:0] - end - attribute \src "issuer_ls180.v:150023.3-150024.49" - process $proc$issuer_ls180.v:150023$8090 - assign { } { } - assign $0\alu_op__data_len[3:0] \alu_op__data_len$next - sync posedge \coresync_clk - update \alu_op__data_len $0\alu_op__data_len[3:0] - end - attribute \src "issuer_ls180.v:150025.3-150026.41" - process $proc$issuer_ls180.v:150025$8091 - assign { } { } - assign $0\alu_op__insn[31:0] \alu_op__insn$next - sync posedge \coresync_clk - update \alu_op__insn $0\alu_op__insn[31:0] - end - attribute \src "issuer_ls180.v:150027.3-150028.27" - process $proc$issuer_ls180.v:150027$8092 - assign { } { } - assign $0\muxid[1:0] \muxid$next - sync posedge \coresync_clk - update \muxid $0\muxid[1:0] - end - attribute \src "issuer_ls180.v:150029.3-150030.29" - process $proc$issuer_ls180.v:150029$8093 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "issuer_ls180.v:150140.3-150158.6" - process $proc$issuer_ls180.v:150140$8094 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$next[3:0]$8095 $1\cr_a$next[3:0]$8097 - assign { } { } - assign $0\cr_a_ok$next[0:0]$8096 $2\cr_a_ok$next[0:0]$8099 - attribute \src "issuer_ls180.v:150141.5-150141.29" - switch \initial - attribute \src "issuer_ls180.v:150141.9-150141.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$8098 $1\cr_a$next[3:0]$8097 } { \cr_a_ok$91 \cr_a$90 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$8098 $1\cr_a$next[3:0]$8097 } { \cr_a_ok$91 \cr_a$90 } - case - assign $1\cr_a$next[3:0]$8097 \cr_a - assign $1\cr_a_ok$next[0:0]$8098 \cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_a_ok$next[0:0]$8099 1'0 - case - assign $2\cr_a_ok$next[0:0]$8099 $1\cr_a_ok$next[0:0]$8098 - end - sync always - update \cr_a$next $0\cr_a$next[3:0]$8095 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8096 - end - attribute \src "issuer_ls180.v:150159.3-150177.6" - process $proc$issuer_ls180.v:150159$8100 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_ca$next[1:0]$8102 $1\xer_ca$next[1:0]$8104 - assign $0\xer_ca_ok$next[0:0]$8101 $2\xer_ca_ok$next[0:0]$8105 - attribute \src "issuer_ls180.v:150160.5-150160.29" - switch \initial - attribute \src "issuer_ls180.v:150160.9-150160.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8103 $1\xer_ca$next[1:0]$8104 } { \xer_ca_ok$93 \xer_ca$92 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8103 $1\xer_ca$next[1:0]$8104 } { \xer_ca_ok$93 \xer_ca$92 } - case - assign $1\xer_ca_ok$next[0:0]$8103 \xer_ca_ok - assign $1\xer_ca$next[1:0]$8104 \xer_ca - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_ca_ok$next[0:0]$8105 1'0 - case - assign $2\xer_ca_ok$next[0:0]$8105 $1\xer_ca_ok$next[0:0]$8103 - end - sync always - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8101 - update \xer_ca$next $0\xer_ca$next[1:0]$8102 - end - attribute \src "issuer_ls180.v:150178.3-150196.6" - process $proc$issuer_ls180.v:150178$8106 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_ov$next[1:0]$8107 $1\xer_ov$next[1:0]$8109 - assign { } { } - assign $0\xer_ov_ok$next[0:0]$8108 $2\xer_ov_ok$next[0:0]$8111 - attribute \src "issuer_ls180.v:150179.5-150179.29" - switch \initial - attribute \src "issuer_ls180.v:150179.9-150179.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8110 $1\xer_ov$next[1:0]$8109 } { \xer_ov_ok$95 \xer_ov$94 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8110 $1\xer_ov$next[1:0]$8109 } { \xer_ov_ok$95 \xer_ov$94 } - case - assign $1\xer_ov$next[1:0]$8109 \xer_ov - assign $1\xer_ov_ok$next[0:0]$8110 \xer_ov_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_ov_ok$next[0:0]$8111 1'0 - case - assign $2\xer_ov_ok$next[0:0]$8111 $1\xer_ov_ok$next[0:0]$8110 - end - sync always - update \xer_ov$next $0\xer_ov$next[1:0]$8107 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8108 - end - attribute \src "issuer_ls180.v:150197.3-150215.6" - process $proc$issuer_ls180.v:150197$8112 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_so$next[0:0]$8113 $1\xer_so$next[0:0]$8115 - assign { } { } - assign $0\xer_so_ok$next[0:0]$8114 $2\xer_so_ok$next[0:0]$8117 - attribute \src "issuer_ls180.v:150198.5-150198.29" - switch \initial - attribute \src "issuer_ls180.v:150198.9-150198.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_so_ok$next[0:0]$8116 $1\xer_so$next[0:0]$8115 } { \xer_so_ok$97 \xer_so$96 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_so_ok$next[0:0]$8116 $1\xer_so$next[0:0]$8115 } { \xer_so_ok$97 \xer_so$96 } - case - assign $1\xer_so$next[0:0]$8115 \xer_so - assign $1\xer_so_ok$next[0:0]$8116 \xer_so_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_so_ok$next[0:0]$8117 1'0 - case - assign $2\xer_so_ok$next[0:0]$8117 $1\xer_so_ok$next[0:0]$8116 - end - sync always - update \xer_so$next $0\xer_so$next[0:0]$8113 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8114 - end - attribute \src "issuer_ls180.v:150216.3-150233.6" - process $proc$issuer_ls180.v:150216$8118 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$8119 $2\r_busy$next[0:0]$8121 - attribute \src "issuer_ls180.v:150217.5-150217.29" - switch \initial - attribute \src "issuer_ls180.v:150217.9-150217.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$8120 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\r_busy$next[0:0]$8120 1'0 - case - assign $1\r_busy$next[0:0]$8120 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$8121 1'0 - case - assign $2\r_busy$next[0:0]$8121 $1\r_busy$next[0:0]$8120 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$8119 - end - attribute \src "issuer_ls180.v:150234.3-150246.6" - process $proc$issuer_ls180.v:150234$8122 - assign { } { } - assign { } { } - assign $0\muxid$next[1:0]$8123 $1\muxid$next[1:0]$8124 - attribute \src "issuer_ls180.v:150235.5-150235.29" - switch \initial - attribute \src "issuer_ls180.v:150235.9-150235.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$next[1:0]$8124 \muxid$69 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$next[1:0]$8124 \muxid$69 - case - assign $1\muxid$next[1:0]$8124 \muxid - end - sync always - update \muxid$next $0\muxid$next[1:0]$8123 - end - attribute \src "issuer_ls180.v:150247.3-150288.6" - process $proc$issuer_ls180.v:150247$8125 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_op__data_len$next[3:0]$8126 $1\alu_op__data_len$next[3:0]$8144 - assign $0\alu_op__fn_unit$next[11:0]$8127 $1\alu_op__fn_unit$next[11:0]$8145 - assign { } { } - assign { } { } - assign $0\alu_op__input_carry$next[1:0]$8130 $1\alu_op__input_carry$next[1:0]$8148 - assign $0\alu_op__insn$next[31:0]$8131 $1\alu_op__insn$next[31:0]$8149 - assign $0\alu_op__insn_type$next[6:0]$8132 $1\alu_op__insn_type$next[6:0]$8150 - assign $0\alu_op__invert_in$next[0:0]$8133 $1\alu_op__invert_in$next[0:0]$8151 - assign $0\alu_op__invert_out$next[0:0]$8134 $1\alu_op__invert_out$next[0:0]$8152 - assign $0\alu_op__is_32bit$next[0:0]$8135 $1\alu_op__is_32bit$next[0:0]$8153 - assign $0\alu_op__is_signed$next[0:0]$8136 $1\alu_op__is_signed$next[0:0]$8154 - assign { } { } - assign { } { } - assign $0\alu_op__output_carry$next[0:0]$8139 $1\alu_op__output_carry$next[0:0]$8157 - assign { } { } - assign { } { } - assign $0\alu_op__write_cr0$next[0:0]$8142 $1\alu_op__write_cr0$next[0:0]$8160 - assign $0\alu_op__zero_a$next[0:0]$8143 $1\alu_op__zero_a$next[0:0]$8161 - assign $0\alu_op__imm_data__data$next[63:0]$8128 $2\alu_op__imm_data__data$next[63:0]$8162 - assign $0\alu_op__imm_data__ok$next[0:0]$8129 $2\alu_op__imm_data__ok$next[0:0]$8163 - assign $0\alu_op__oe__oe$next[0:0]$8137 $2\alu_op__oe__oe$next[0:0]$8164 - assign $0\alu_op__oe__ok$next[0:0]$8138 $2\alu_op__oe__ok$next[0:0]$8165 - assign $0\alu_op__rc__ok$next[0:0]$8140 $2\alu_op__rc__ok$next[0:0]$8166 - assign $0\alu_op__rc__rc$next[0:0]$8141 $2\alu_op__rc__rc$next[0:0]$8167 - attribute \src "issuer_ls180.v:150248.5-150248.29" - switch \initial - attribute \src "issuer_ls180.v:150248.9-150248.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_op__insn$next[31:0]$8149 $1\alu_op__data_len$next[3:0]$8144 $1\alu_op__is_signed$next[0:0]$8154 $1\alu_op__is_32bit$next[0:0]$8153 $1\alu_op__output_carry$next[0:0]$8157 $1\alu_op__input_carry$next[1:0]$8148 $1\alu_op__write_cr0$next[0:0]$8160 $1\alu_op__invert_out$next[0:0]$8152 $1\alu_op__zero_a$next[0:0]$8161 $1\alu_op__invert_in$next[0:0]$8151 $1\alu_op__oe__ok$next[0:0]$8156 $1\alu_op__oe__oe$next[0:0]$8155 $1\alu_op__rc__ok$next[0:0]$8158 $1\alu_op__rc__rc$next[0:0]$8159 $1\alu_op__imm_data__ok$next[0:0]$8147 $1\alu_op__imm_data__data$next[63:0]$8146 $1\alu_op__fn_unit$next[11:0]$8145 $1\alu_op__insn_type$next[6:0]$8150 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_op__insn$next[31:0]$8149 $1\alu_op__data_len$next[3:0]$8144 $1\alu_op__is_signed$next[0:0]$8154 $1\alu_op__is_32bit$next[0:0]$8153 $1\alu_op__output_carry$next[0:0]$8157 $1\alu_op__input_carry$next[1:0]$8148 $1\alu_op__write_cr0$next[0:0]$8160 $1\alu_op__invert_out$next[0:0]$8152 $1\alu_op__zero_a$next[0:0]$8161 $1\alu_op__invert_in$next[0:0]$8151 $1\alu_op__oe__ok$next[0:0]$8156 $1\alu_op__oe__oe$next[0:0]$8155 $1\alu_op__rc__ok$next[0:0]$8158 $1\alu_op__rc__rc$next[0:0]$8159 $1\alu_op__imm_data__ok$next[0:0]$8147 $1\alu_op__imm_data__data$next[63:0]$8146 $1\alu_op__fn_unit$next[11:0]$8145 $1\alu_op__insn_type$next[6:0]$8150 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } - case - assign $1\alu_op__data_len$next[3:0]$8144 \alu_op__data_len - assign $1\alu_op__fn_unit$next[11:0]$8145 \alu_op__fn_unit - assign $1\alu_op__imm_data__data$next[63:0]$8146 \alu_op__imm_data__data - assign $1\alu_op__imm_data__ok$next[0:0]$8147 \alu_op__imm_data__ok - assign $1\alu_op__input_carry$next[1:0]$8148 \alu_op__input_carry - assign $1\alu_op__insn$next[31:0]$8149 \alu_op__insn - assign $1\alu_op__insn_type$next[6:0]$8150 \alu_op__insn_type - assign $1\alu_op__invert_in$next[0:0]$8151 \alu_op__invert_in - assign $1\alu_op__invert_out$next[0:0]$8152 \alu_op__invert_out - assign $1\alu_op__is_32bit$next[0:0]$8153 \alu_op__is_32bit - assign $1\alu_op__is_signed$next[0:0]$8154 \alu_op__is_signed - assign $1\alu_op__oe__oe$next[0:0]$8155 \alu_op__oe__oe - assign $1\alu_op__oe__ok$next[0:0]$8156 \alu_op__oe__ok - assign $1\alu_op__output_carry$next[0:0]$8157 \alu_op__output_carry - assign $1\alu_op__rc__ok$next[0:0]$8158 \alu_op__rc__ok - assign $1\alu_op__rc__rc$next[0:0]$8159 \alu_op__rc__rc - assign $1\alu_op__write_cr0$next[0:0]$8160 \alu_op__write_cr0 - assign $1\alu_op__zero_a$next[0:0]$8161 \alu_op__zero_a - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\alu_op__imm_data__data$next[63:0]$8162 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_op__imm_data__ok$next[0:0]$8163 1'0 - assign $2\alu_op__rc__rc$next[0:0]$8167 1'0 - assign $2\alu_op__rc__ok$next[0:0]$8166 1'0 - assign $2\alu_op__oe__oe$next[0:0]$8164 1'0 - assign $2\alu_op__oe__ok$next[0:0]$8165 1'0 - case - assign $2\alu_op__imm_data__data$next[63:0]$8162 $1\alu_op__imm_data__data$next[63:0]$8146 - assign $2\alu_op__imm_data__ok$next[0:0]$8163 $1\alu_op__imm_data__ok$next[0:0]$8147 - assign $2\alu_op__oe__oe$next[0:0]$8164 $1\alu_op__oe__oe$next[0:0]$8155 - assign $2\alu_op__oe__ok$next[0:0]$8165 $1\alu_op__oe__ok$next[0:0]$8156 - assign $2\alu_op__rc__ok$next[0:0]$8166 $1\alu_op__rc__ok$next[0:0]$8158 - assign $2\alu_op__rc__rc$next[0:0]$8167 $1\alu_op__rc__rc$next[0:0]$8159 - end - sync always - update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$8126 - update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[11:0]$8127 - update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$8128 - update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$8129 - update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$8130 - update \alu_op__insn$next $0\alu_op__insn$next[31:0]$8131 - update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$8132 - update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$8133 - update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$8134 - update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$8135 - update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$8136 - update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$8137 - update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$8138 - update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$8139 - update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$8140 - update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$8141 - update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$8142 - update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$8143 - end - attribute \src "issuer_ls180.v:150289.3-150307.6" - process $proc$issuer_ls180.v:150289$8168 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$next[63:0]$8169 $1\o$next[63:0]$8171 - assign { } { } - assign $0\o_ok$next[0:0]$8170 $2\o_ok$next[0:0]$8173 - attribute \src "issuer_ls180.v:150290.5-150290.29" - switch \initial - attribute \src "issuer_ls180.v:150290.9-150290.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$8172 $1\o$next[63:0]$8171 } { \o_ok$89 \o$88 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$8172 $1\o$next[63:0]$8171 } { \o_ok$89 \o$88 } - case - assign $1\o$next[63:0]$8171 \o - assign $1\o_ok$next[0:0]$8172 \o_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o_ok$next[0:0]$8173 1'0 - case - assign $2\o_ok$next[0:0]$8173 $1\o_ok$next[0:0]$8172 - end - sync always - update \o$next $0\o$next[63:0]$8169 - update \o_ok$next $0\o_ok$next[0:0]$8170 - end - connect \$67 $and$issuer_ls180.v:149970$8063_Y - connect \xer_so_ok$98 1'0 - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \xer_so_ok$97 \xer_so$96 } { 1'0 \main_xer_so$65 } - connect { \xer_ov_ok$95 \xer_ov$94 } { \main_xer_ov_ok \main_xer_ov } - connect { \xer_ca_ok$93 \xer_ca$92 } { \main_xer_ca_ok \main_xer_ca$64 } - connect { \cr_a_ok$91 \cr_a$90 } { \main_cr_a_ok \main_cr_a } - connect { \o_ok$89 \o$88 } { \main_o_ok \main_o } - connect { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } { \main_alu_op__insn$63 \main_alu_op__data_len$62 \main_alu_op__is_signed$61 \main_alu_op__is_32bit$60 \main_alu_op__output_carry$59 \main_alu_op__input_carry$58 \main_alu_op__write_cr0$57 \main_alu_op__invert_out$56 \main_alu_op__zero_a$55 \main_alu_op__invert_in$54 \main_alu_op__oe__ok$53 \main_alu_op__oe__oe$52 \main_alu_op__rc__ok$51 \main_alu_op__rc__rc$50 \main_alu_op__imm_data__ok$49 \main_alu_op__imm_data__data$48 \main_alu_op__fn_unit$47 \main_alu_op__insn_type$46 } - connect \muxid$69 \main_muxid$45 - connect \p_valid_i_p_ready_o \$67 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$66 \p_valid_i - connect \main_xer_ca \input_xer_ca$44 - connect \main_xer_so \input_xer_so$43 - connect \main_rb \input_rb$42 - connect \main_ra \input_ra$41 - connect { \main_alu_op__insn \main_alu_op__data_len \main_alu_op__is_signed \main_alu_op__is_32bit \main_alu_op__output_carry \main_alu_op__input_carry \main_alu_op__write_cr0 \main_alu_op__invert_out \main_alu_op__zero_a \main_alu_op__invert_in \main_alu_op__oe__ok \main_alu_op__oe__oe \main_alu_op__rc__ok \main_alu_op__rc__rc \main_alu_op__imm_data__ok \main_alu_op__imm_data__data \main_alu_op__fn_unit \main_alu_op__insn_type } { \input_alu_op__insn$40 \input_alu_op__data_len$39 \input_alu_op__is_signed$38 \input_alu_op__is_32bit$37 \input_alu_op__output_carry$36 \input_alu_op__input_carry$35 \input_alu_op__write_cr0$34 \input_alu_op__invert_out$33 \input_alu_op__zero_a$32 \input_alu_op__invert_in$31 \input_alu_op__oe__ok$30 \input_alu_op__oe__oe$29 \input_alu_op__rc__ok$28 \input_alu_op__rc__rc$27 \input_alu_op__imm_data__ok$26 \input_alu_op__imm_data__data$25 \input_alu_op__fn_unit$24 \input_alu_op__insn_type$23 } - connect \main_muxid \input_muxid$22 - connect \input_xer_ca \xer_ca$21 - connect \input_xer_so \xer_so$20 - connect \input_rb \rb - connect \input_ra \ra - connect { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in \input_alu_op__oe__ok \input_alu_op__oe__oe \input_alu_op__rc__ok \input_alu_op__rc__rc \input_alu_op__imm_data__ok \input_alu_op__imm_data__data \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } - connect \input_muxid \muxid$1 -end -attribute \src "issuer_ls180.v:150337.1-151728.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1" -attribute \generator "nMigen" -module \pipe1$107 - attribute \src "issuer_ls180.v:151642.3-151660.6" - wire width 4 $0\cr_a$next[3:0]$8285 - attribute \src "issuer_ls180.v:151410.3-151411.25" - wire width 4 $0\cr_a[3:0] - attribute \src "issuer_ls180.v:151642.3-151660.6" - wire $0\cr_a_ok$next[0:0]$8286 - attribute \src "issuer_ls180.v:151412.3-151413.31" - wire $0\cr_a_ok[0:0] - attribute \src "issuer_ls180.v:150338.7-150338.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:151570.3-151582.6" - wire width 2 $0\muxid$next[1:0]$8237 - attribute \src "issuer_ls180.v:151450.3-151451.27" - wire width 2 $0\muxid[1:0] - attribute \src "issuer_ls180.v:151623.3-151641.6" - wire width 64 $0\o$next[63:0]$8279 - attribute \src "issuer_ls180.v:151414.3-151415.19" - wire width 64 $0\o[63:0] - attribute \src "issuer_ls180.v:151623.3-151641.6" - wire $0\o_ok$next[0:0]$8280 - attribute \src "issuer_ls180.v:151416.3-151417.25" - wire $0\o_ok[0:0] - attribute \src "issuer_ls180.v:151552.3-151569.6" - wire $0\r_busy$next[0:0]$8233 - attribute \src "issuer_ls180.v:151452.3-151453.29" - wire $0\r_busy[0:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire width 12 $0\sr_op__fn_unit$next[11:0]$8240 - attribute \src "issuer_ls180.v:151420.3-151421.45" - wire width 12 $0\sr_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire width 64 $0\sr_op__imm_data__data$next[63:0]$8241 - attribute \src "issuer_ls180.v:151422.3-151423.59" - wire width 64 $0\sr_op__imm_data__data[63:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $0\sr_op__imm_data__ok$next[0:0]$8242 - attribute \src "issuer_ls180.v:151424.3-151425.55" - wire $0\sr_op__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire width 2 $0\sr_op__input_carry$next[1:0]$8243 - attribute \src "issuer_ls180.v:151436.3-151437.53" - wire width 2 $0\sr_op__input_carry[1:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $0\sr_op__input_cr$next[0:0]$8244 - attribute \src "issuer_ls180.v:151440.3-151441.47" - wire $0\sr_op__input_cr[0:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire width 32 $0\sr_op__insn$next[31:0]$8245 - attribute \src "issuer_ls180.v:151448.3-151449.39" - wire width 32 $0\sr_op__insn[31:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire width 7 $0\sr_op__insn_type$next[6:0]$8246 - attribute \src "issuer_ls180.v:151418.3-151419.49" - wire width 7 $0\sr_op__insn_type[6:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $0\sr_op__is_32bit$next[0:0]$8247 - attribute \src "issuer_ls180.v:151444.3-151445.47" - wire $0\sr_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $0\sr_op__is_signed$next[0:0]$8248 - attribute \src "issuer_ls180.v:151446.3-151447.49" - wire $0\sr_op__is_signed[0:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $0\sr_op__oe__oe$next[0:0]$8249 - attribute \src "issuer_ls180.v:151430.3-151431.43" - wire $0\sr_op__oe__oe[0:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $0\sr_op__oe__ok$next[0:0]$8250 - attribute \src "issuer_ls180.v:151432.3-151433.43" - wire $0\sr_op__oe__ok[0:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $0\sr_op__output_carry$next[0:0]$8251 - attribute \src "issuer_ls180.v:151438.3-151439.55" - wire $0\sr_op__output_carry[0:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $0\sr_op__output_cr$next[0:0]$8252 - attribute \src "issuer_ls180.v:151442.3-151443.49" - wire $0\sr_op__output_cr[0:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $0\sr_op__rc__ok$next[0:0]$8253 - attribute \src "issuer_ls180.v:151428.3-151429.43" - wire $0\sr_op__rc__ok[0:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $0\sr_op__rc__rc$next[0:0]$8254 - attribute \src "issuer_ls180.v:151426.3-151427.43" - wire $0\sr_op__rc__rc[0:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $0\sr_op__write_cr0$next[0:0]$8255 - attribute \src "issuer_ls180.v:151434.3-151435.49" - wire $0\sr_op__write_cr0[0:0] - attribute \src "issuer_ls180.v:151680.3-151698.6" - wire width 2 $0\xer_ca$next[1:0]$8298 - attribute \src "issuer_ls180.v:151402.3-151403.29" - wire width 2 $0\xer_ca[1:0] - attribute \src "issuer_ls180.v:151680.3-151698.6" - wire $0\xer_ca_ok$next[0:0]$8297 - attribute \src "issuer_ls180.v:151404.3-151405.35" - wire $0\xer_ca_ok[0:0] - attribute \src "issuer_ls180.v:151661.3-151679.6" - wire $0\xer_so$next[0:0]$8291 - attribute \src "issuer_ls180.v:151406.3-151407.29" - wire $0\xer_so[0:0] - attribute \src "issuer_ls180.v:151661.3-151679.6" - wire $0\xer_so_ok$next[0:0]$8292 - attribute \src "issuer_ls180.v:151408.3-151409.35" - wire $0\xer_so_ok[0:0] - attribute \src "issuer_ls180.v:151642.3-151660.6" - wire width 4 $1\cr_a$next[3:0]$8287 - attribute \src "issuer_ls180.v:150347.13-150347.24" - wire width 4 $1\cr_a[3:0] - attribute \src "issuer_ls180.v:151642.3-151660.6" - wire $1\cr_a_ok$next[0:0]$8288 - attribute \src "issuer_ls180.v:150356.7-150356.21" - wire $1\cr_a_ok[0:0] - attribute \src "issuer_ls180.v:151570.3-151582.6" - wire width 2 $1\muxid$next[1:0]$8238 - attribute \src "issuer_ls180.v:150901.13-150901.25" - wire width 2 $1\muxid[1:0] - attribute \src "issuer_ls180.v:151623.3-151641.6" - wire width 64 $1\o$next[63:0]$8281 - attribute \src "issuer_ls180.v:150916.14-150916.38" - wire width 64 $1\o[63:0] - attribute \src "issuer_ls180.v:151623.3-151641.6" - wire $1\o_ok$next[0:0]$8282 - attribute \src "issuer_ls180.v:150923.7-150923.18" - wire $1\o_ok[0:0] - attribute \src "issuer_ls180.v:151552.3-151569.6" - wire $1\r_busy$next[0:0]$8234 - attribute \src "issuer_ls180.v:150937.7-150937.20" - wire $1\r_busy[0:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire width 12 $1\sr_op__fn_unit$next[11:0]$8256 - attribute \src "issuer_ls180.v:150961.14-150961.38" - wire width 12 $1\sr_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire width 64 $1\sr_op__imm_data__data$next[63:0]$8257 - attribute \src "issuer_ls180.v:150996.14-150996.58" - wire width 64 $1\sr_op__imm_data__data[63:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $1\sr_op__imm_data__ok$next[0:0]$8258 - attribute \src "issuer_ls180.v:151005.7-151005.33" - wire $1\sr_op__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire width 2 $1\sr_op__input_carry$next[1:0]$8259 - attribute \src "issuer_ls180.v:151018.13-151018.38" - wire width 2 $1\sr_op__input_carry[1:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $1\sr_op__input_cr$next[0:0]$8260 - attribute \src "issuer_ls180.v:151035.7-151035.29" - wire $1\sr_op__input_cr[0:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire width 32 $1\sr_op__insn$next[31:0]$8261 - attribute \src "issuer_ls180.v:151044.14-151044.33" - wire width 32 $1\sr_op__insn[31:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire width 7 $1\sr_op__insn_type$next[6:0]$8262 - attribute \src "issuer_ls180.v:151127.13-151127.37" - wire width 7 $1\sr_op__insn_type[6:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $1\sr_op__is_32bit$next[0:0]$8263 - attribute \src "issuer_ls180.v:151284.7-151284.29" - wire $1\sr_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $1\sr_op__is_signed$next[0:0]$8264 - attribute \src "issuer_ls180.v:151293.7-151293.30" - wire $1\sr_op__is_signed[0:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $1\sr_op__oe__oe$next[0:0]$8265 - attribute \src "issuer_ls180.v:151302.7-151302.27" - wire $1\sr_op__oe__oe[0:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $1\sr_op__oe__ok$next[0:0]$8266 - attribute \src "issuer_ls180.v:151311.7-151311.27" - wire $1\sr_op__oe__ok[0:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $1\sr_op__output_carry$next[0:0]$8267 - attribute \src "issuer_ls180.v:151320.7-151320.33" - wire $1\sr_op__output_carry[0:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $1\sr_op__output_cr$next[0:0]$8268 - attribute \src "issuer_ls180.v:151329.7-151329.30" - wire $1\sr_op__output_cr[0:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $1\sr_op__rc__ok$next[0:0]$8269 - attribute \src "issuer_ls180.v:151338.7-151338.27" - wire $1\sr_op__rc__ok[0:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $1\sr_op__rc__rc$next[0:0]$8270 - attribute \src "issuer_ls180.v:151347.7-151347.27" - wire $1\sr_op__rc__rc[0:0] - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $1\sr_op__write_cr0$next[0:0]$8271 - attribute \src "issuer_ls180.v:151356.7-151356.30" - wire $1\sr_op__write_cr0[0:0] - attribute \src "issuer_ls180.v:151680.3-151698.6" - wire width 2 $1\xer_ca$next[1:0]$8300 - attribute \src "issuer_ls180.v:151365.13-151365.26" - wire width 2 $1\xer_ca[1:0] - attribute \src "issuer_ls180.v:151680.3-151698.6" - wire $1\xer_ca_ok$next[0:0]$8299 - attribute \src "issuer_ls180.v:151376.7-151376.23" - wire $1\xer_ca_ok[0:0] - attribute \src "issuer_ls180.v:151661.3-151679.6" - wire $1\xer_so$next[0:0]$8293 - attribute \src "issuer_ls180.v:151385.7-151385.20" - wire $1\xer_so[0:0] - attribute \src "issuer_ls180.v:151661.3-151679.6" - wire $1\xer_so_ok$next[0:0]$8294 - attribute \src "issuer_ls180.v:151394.7-151394.23" - wire $1\xer_so_ok[0:0] - attribute \src "issuer_ls180.v:151642.3-151660.6" - wire $2\cr_a_ok$next[0:0]$8289 - attribute \src "issuer_ls180.v:151623.3-151641.6" - wire $2\o_ok$next[0:0]$8283 - attribute \src "issuer_ls180.v:151552.3-151569.6" - wire $2\r_busy$next[0:0]$8235 - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire width 64 $2\sr_op__imm_data__data$next[63:0]$8272 - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $2\sr_op__imm_data__ok$next[0:0]$8273 - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $2\sr_op__oe__oe$next[0:0]$8274 - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $2\sr_op__oe__ok$next[0:0]$8275 - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $2\sr_op__rc__ok$next[0:0]$8276 - attribute \src "issuer_ls180.v:151583.3-151622.6" - wire $2\sr_op__rc__rc$next[0:0]$8277 - attribute \src "issuer_ls180.v:151680.3-151698.6" - wire $2\xer_ca_ok$next[0:0]$8301 - attribute \src "issuer_ls180.v:151661.3-151679.6" - wire $2\xer_so_ok$next[0:0]$8295 - attribute \src "issuer_ls180.v:151401.18-151401.118" - wire $and$issuer_ls180.v:151401$8205_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 53 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 23 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 24 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$next - attribute \src "issuer_ls180.v:150338.7-150338.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rc$39 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_sr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_sr_op__fn_unit$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_sr_op__imm_data__data$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__imm_data__ok$24 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_sr_op__input_carry$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__input_cr$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 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50 \rc - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 6 \sr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute 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\src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \sr_op__fn_unit$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \sr_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 34 \sr_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__data$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 35 \sr_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__imm_data__ok$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__imm_data__ok$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 14 \sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 41 \sr_op__input_carry$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 43 \sr_op__input_cr$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__input_cr$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__input_cr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 20 \sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 47 \sr_op__insn$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute 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\enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 5 \sr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 32 \sr_op__insn_type$2 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute 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\enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 18 \sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 45 \sr_op__is_32bit$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_32bit$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 19 \sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 46 \sr_op__is_signed$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_signed$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__oe$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 38 \sr_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__ok$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 39 \sr_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 42 \sr_op__output_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_carry$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 44 \sr_op__output_cr$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_cr$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_cr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 37 \sr_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__ok$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 36 \sr_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__rc$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \sr_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 40 \sr_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__write_cr0$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 27 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 52 \xer_ca$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \xer_ca$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 28 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ca_ok$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ca_ok$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ca_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 25 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 51 \xer_so$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 26 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$issuer_ls180.v:151401$8205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$61 - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:151401$8205_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:151454.15-151499.4" - cell \input$110 \input - connect \muxid \input_muxid - connect \muxid$1 \input_muxid$20 - connect \ra \input_ra - connect \ra$18 \input_ra$37 - connect \rb \input_rb - connect \rb$19 \input_rb$38 - connect \rc \input_rc - connect \rc$20 \input_rc$39 - connect \sr_op__fn_unit \input_sr_op__fn_unit - connect \sr_op__fn_unit$3 \input_sr_op__fn_unit$22 - connect \sr_op__imm_data__data \input_sr_op__imm_data__data - connect \sr_op__imm_data__data$4 \input_sr_op__imm_data__data$23 - connect \sr_op__imm_data__ok \input_sr_op__imm_data__ok - connect \sr_op__imm_data__ok$5 \input_sr_op__imm_data__ok$24 - connect \sr_op__input_carry \input_sr_op__input_carry - connect \sr_op__input_carry$11 \input_sr_op__input_carry$30 - connect \sr_op__input_cr \input_sr_op__input_cr - connect \sr_op__input_cr$13 \input_sr_op__input_cr$32 - connect \sr_op__insn \input_sr_op__insn - connect \sr_op__insn$17 \input_sr_op__insn$36 - connect \sr_op__insn_type \input_sr_op__insn_type - connect \sr_op__insn_type$2 \input_sr_op__insn_type$21 - connect \sr_op__is_32bit \input_sr_op__is_32bit - connect \sr_op__is_32bit$15 \input_sr_op__is_32bit$34 - connect \sr_op__is_signed \input_sr_op__is_signed - connect \sr_op__is_signed$16 \input_sr_op__is_signed$35 - connect \sr_op__oe__oe \input_sr_op__oe__oe - connect \sr_op__oe__oe$8 \input_sr_op__oe__oe$27 - connect \sr_op__oe__ok \input_sr_op__oe__ok - connect \sr_op__oe__ok$9 \input_sr_op__oe__ok$28 - connect \sr_op__output_carry \input_sr_op__output_carry - connect \sr_op__output_carry$12 \input_sr_op__output_carry$31 - connect \sr_op__output_cr \input_sr_op__output_cr - connect \sr_op__output_cr$14 \input_sr_op__output_cr$33 - connect \sr_op__rc__ok \input_sr_op__rc__ok - connect \sr_op__rc__ok$7 \input_sr_op__rc__ok$26 - connect \sr_op__rc__rc \input_sr_op__rc__rc - connect \sr_op__rc__rc$6 \input_sr_op__rc__rc$25 - connect \sr_op__write_cr0 \input_sr_op__write_cr0 - connect \sr_op__write_cr0$10 \input_sr_op__write_cr0$29 - connect \xer_ca \input_xer_ca - connect \xer_ca$22 \input_xer_ca$41 - connect \xer_so \input_xer_so - connect \xer_so$21 \input_xer_so$40 - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:151500.14-151543.4" - cell \main$111 \main - connect \muxid \main_muxid - connect \muxid$1 \main_muxid$42 - connect \o \main_o - connect \o_ok \main_o_ok - connect \ra \main_ra - connect \rb \main_rb - connect \rc \main_rc - connect \sr_op__fn_unit \main_sr_op__fn_unit - connect \sr_op__fn_unit$3 \main_sr_op__fn_unit$44 - connect \sr_op__imm_data__data \main_sr_op__imm_data__data - connect \sr_op__imm_data__data$4 \main_sr_op__imm_data__data$45 - connect \sr_op__imm_data__ok \main_sr_op__imm_data__ok - connect \sr_op__imm_data__ok$5 \main_sr_op__imm_data__ok$46 - connect \sr_op__input_carry \main_sr_op__input_carry - connect \sr_op__input_carry$11 \main_sr_op__input_carry$52 - connect \sr_op__input_cr \main_sr_op__input_cr - connect \sr_op__input_cr$13 \main_sr_op__input_cr$54 - connect \sr_op__insn \main_sr_op__insn - connect \sr_op__insn$17 \main_sr_op__insn$58 - connect \sr_op__insn_type \main_sr_op__insn_type - connect \sr_op__insn_type$2 \main_sr_op__insn_type$43 - connect \sr_op__is_32bit \main_sr_op__is_32bit - connect \sr_op__is_32bit$15 \main_sr_op__is_32bit$56 - connect \sr_op__is_signed \main_sr_op__is_signed - connect \sr_op__is_signed$16 \main_sr_op__is_signed$57 - connect \sr_op__oe__oe \main_sr_op__oe__oe - connect \sr_op__oe__oe$8 \main_sr_op__oe__oe$49 - connect \sr_op__oe__ok \main_sr_op__oe__ok - connect \sr_op__oe__ok$9 \main_sr_op__oe__ok$50 - connect \sr_op__output_carry \main_sr_op__output_carry - connect \sr_op__output_carry$12 \main_sr_op__output_carry$53 - connect \sr_op__output_cr \main_sr_op__output_cr - connect \sr_op__output_cr$14 \main_sr_op__output_cr$55 - connect \sr_op__rc__ok \main_sr_op__rc__ok - connect \sr_op__rc__ok$7 \main_sr_op__rc__ok$48 - connect \sr_op__rc__rc \main_sr_op__rc__rc - connect \sr_op__rc__rc$6 \main_sr_op__rc__rc$47 - connect \sr_op__write_cr0 \main_sr_op__write_cr0 - connect \sr_op__write_cr0$10 \main_sr_op__write_cr0$51 - connect \xer_ca \main_xer_ca - connect \xer_so \main_xer_so - connect \xer_so$18 \main_xer_so$59 - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:151544.11-151547.4" - cell \n$109 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:151548.11-151551.4" - cell \p$108 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "issuer_ls180.v:150338.7-150338.20" - process $proc$issuer_ls180.v:150338$8302 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:150347.13-150347.24" - process $proc$issuer_ls180.v:150347$8303 - assign { } { } - assign $1\cr_a[3:0] 4'0000 - sync always - sync init - update \cr_a $1\cr_a[3:0] - end - attribute \src "issuer_ls180.v:150356.7-150356.21" - process $proc$issuer_ls180.v:150356$8304 - assign { } { } - assign $1\cr_a_ok[0:0] 1'0 - sync always - sync init - update \cr_a_ok $1\cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:150901.13-150901.25" - process $proc$issuer_ls180.v:150901$8305 - assign { } { } - assign $1\muxid[1:0] 2'00 - sync always - sync init - update \muxid $1\muxid[1:0] - end - attribute \src "issuer_ls180.v:150916.14-150916.38" - process $proc$issuer_ls180.v:150916$8306 - assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o $1\o[63:0] - end - attribute \src "issuer_ls180.v:150923.7-150923.18" - process $proc$issuer_ls180.v:150923$8307 - assign { } { } - assign $1\o_ok[0:0] 1'0 - sync always - sync init - update \o_ok $1\o_ok[0:0] - end - attribute \src "issuer_ls180.v:150937.7-150937.20" - process $proc$issuer_ls180.v:150937$8308 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "issuer_ls180.v:150961.14-150961.38" - process $proc$issuer_ls180.v:150961$8309 - assign { } { } - assign $1\sr_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \sr_op__fn_unit $1\sr_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:150996.14-150996.58" - process $proc$issuer_ls180.v:150996$8310 - assign { } { } - assign $1\sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \sr_op__imm_data__data $1\sr_op__imm_data__data[63:0] - end - attribute \src "issuer_ls180.v:151005.7-151005.33" - process $proc$issuer_ls180.v:151005$8311 - assign { } { } - assign $1\sr_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \sr_op__imm_data__ok $1\sr_op__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:151018.13-151018.38" - process $proc$issuer_ls180.v:151018$8312 - assign { } { } - assign $1\sr_op__input_carry[1:0] 2'00 - sync always - sync init - update \sr_op__input_carry $1\sr_op__input_carry[1:0] - end - attribute \src "issuer_ls180.v:151035.7-151035.29" - process $proc$issuer_ls180.v:151035$8313 - assign { } { } - assign $1\sr_op__input_cr[0:0] 1'0 - sync always - sync init - update \sr_op__input_cr $1\sr_op__input_cr[0:0] - end - attribute \src "issuer_ls180.v:151044.14-151044.33" - process $proc$issuer_ls180.v:151044$8314 - assign { } { } - assign $1\sr_op__insn[31:0] 0 - sync always - sync init - update \sr_op__insn $1\sr_op__insn[31:0] - end - attribute \src "issuer_ls180.v:151127.13-151127.37" - process $proc$issuer_ls180.v:151127$8315 - assign { } { } - assign $1\sr_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \sr_op__insn_type $1\sr_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:151284.7-151284.29" - process $proc$issuer_ls180.v:151284$8316 - assign { } { } - assign $1\sr_op__is_32bit[0:0] 1'0 - sync always - sync init - update \sr_op__is_32bit $1\sr_op__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:151293.7-151293.30" - process $proc$issuer_ls180.v:151293$8317 - assign { } { } - assign $1\sr_op__is_signed[0:0] 1'0 - sync always - sync init - update \sr_op__is_signed $1\sr_op__is_signed[0:0] - end - attribute \src "issuer_ls180.v:151302.7-151302.27" - process $proc$issuer_ls180.v:151302$8318 - assign { } { } - assign $1\sr_op__oe__oe[0:0] 1'0 - sync always - sync init - update \sr_op__oe__oe $1\sr_op__oe__oe[0:0] - end - attribute \src "issuer_ls180.v:151311.7-151311.27" - process $proc$issuer_ls180.v:151311$8319 - assign { } { } - assign $1\sr_op__oe__ok[0:0] 1'0 - sync always - sync init - update \sr_op__oe__ok $1\sr_op__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:151320.7-151320.33" - process $proc$issuer_ls180.v:151320$8320 - assign { } { } - assign $1\sr_op__output_carry[0:0] 1'0 - sync always - sync init - update \sr_op__output_carry $1\sr_op__output_carry[0:0] - end - attribute \src "issuer_ls180.v:151329.7-151329.30" - process $proc$issuer_ls180.v:151329$8321 - assign { } { } - assign $1\sr_op__output_cr[0:0] 1'0 - sync always - sync init - update \sr_op__output_cr $1\sr_op__output_cr[0:0] - end - attribute \src "issuer_ls180.v:151338.7-151338.27" - process $proc$issuer_ls180.v:151338$8322 - assign { } { } - assign $1\sr_op__rc__ok[0:0] 1'0 - sync always - sync init - update \sr_op__rc__ok $1\sr_op__rc__ok[0:0] - end - attribute \src "issuer_ls180.v:151347.7-151347.27" - process $proc$issuer_ls180.v:151347$8323 - assign { } { } - assign $1\sr_op__rc__rc[0:0] 1'0 - sync always - sync init - update \sr_op__rc__rc $1\sr_op__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:151356.7-151356.30" - process $proc$issuer_ls180.v:151356$8324 - assign { } { } - assign $1\sr_op__write_cr0[0:0] 1'0 - sync always - sync init - update \sr_op__write_cr0 $1\sr_op__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:151365.13-151365.26" - process $proc$issuer_ls180.v:151365$8325 - assign { } { } - assign $1\xer_ca[1:0] 2'00 - sync always - sync init - update \xer_ca $1\xer_ca[1:0] - end - attribute \src "issuer_ls180.v:151376.7-151376.23" - process $proc$issuer_ls180.v:151376$8326 - assign { } { } - assign $1\xer_ca_ok[0:0] 1'0 - sync always - sync init - update \xer_ca_ok $1\xer_ca_ok[0:0] - end - attribute \src "issuer_ls180.v:151385.7-151385.20" - process $proc$issuer_ls180.v:151385$8327 - assign { } { } - assign $1\xer_so[0:0] 1'0 - sync always - sync init - update \xer_so $1\xer_so[0:0] - end - attribute \src "issuer_ls180.v:151394.7-151394.23" - process $proc$issuer_ls180.v:151394$8328 - assign { } { } - assign $1\xer_so_ok[0:0] 1'0 - sync always - sync init - update \xer_so_ok $1\xer_so_ok[0:0] - end - attribute \src "issuer_ls180.v:151402.3-151403.29" - process $proc$issuer_ls180.v:151402$8206 - assign { } { } - assign $0\xer_ca[1:0] \xer_ca$next - sync posedge \coresync_clk - update \xer_ca $0\xer_ca[1:0] - end - attribute \src "issuer_ls180.v:151404.3-151405.35" - process $proc$issuer_ls180.v:151404$8207 - assign { } { } - assign $0\xer_ca_ok[0:0] \xer_ca_ok$next - sync posedge \coresync_clk - update \xer_ca_ok $0\xer_ca_ok[0:0] - end - attribute \src "issuer_ls180.v:151406.3-151407.29" - process $proc$issuer_ls180.v:151406$8208 - assign { } { } - assign $0\xer_so[0:0] \xer_so$next - sync posedge \coresync_clk - update \xer_so $0\xer_so[0:0] - end - attribute \src "issuer_ls180.v:151408.3-151409.35" - process $proc$issuer_ls180.v:151408$8209 - assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next - sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] - end - attribute \src "issuer_ls180.v:151410.3-151411.25" - process $proc$issuer_ls180.v:151410$8210 - assign { } { } - assign $0\cr_a[3:0] \cr_a$next - sync posedge \coresync_clk - update \cr_a $0\cr_a[3:0] - end - attribute \src "issuer_ls180.v:151412.3-151413.31" - process $proc$issuer_ls180.v:151412$8211 - assign { } { } - assign $0\cr_a_ok[0:0] \cr_a_ok$next - sync posedge \coresync_clk - update \cr_a_ok $0\cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:151414.3-151415.19" - process $proc$issuer_ls180.v:151414$8212 - assign { } { } - assign $0\o[63:0] \o$next - sync posedge \coresync_clk - update \o $0\o[63:0] - end - attribute \src "issuer_ls180.v:151416.3-151417.25" - process $proc$issuer_ls180.v:151416$8213 - assign { } { } - assign $0\o_ok[0:0] \o_ok$next - sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] - end - attribute \src "issuer_ls180.v:151418.3-151419.49" - process $proc$issuer_ls180.v:151418$8214 - assign { } { } - assign $0\sr_op__insn_type[6:0] \sr_op__insn_type$next - sync posedge \coresync_clk - update \sr_op__insn_type $0\sr_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:151420.3-151421.45" - process $proc$issuer_ls180.v:151420$8215 - assign { } { } - assign $0\sr_op__fn_unit[11:0] \sr_op__fn_unit$next - sync posedge \coresync_clk - update \sr_op__fn_unit $0\sr_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:151422.3-151423.59" - process $proc$issuer_ls180.v:151422$8216 - assign { } { } - assign $0\sr_op__imm_data__data[63:0] \sr_op__imm_data__data$next - sync posedge \coresync_clk - update \sr_op__imm_data__data $0\sr_op__imm_data__data[63:0] - end - attribute \src "issuer_ls180.v:151424.3-151425.55" - process $proc$issuer_ls180.v:151424$8217 - assign { } { } - assign $0\sr_op__imm_data__ok[0:0] \sr_op__imm_data__ok$next - sync posedge \coresync_clk - update \sr_op__imm_data__ok $0\sr_op__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:151426.3-151427.43" - process $proc$issuer_ls180.v:151426$8218 - assign { } { } - assign $0\sr_op__rc__rc[0:0] \sr_op__rc__rc$next - sync posedge \coresync_clk - update \sr_op__rc__rc $0\sr_op__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:151428.3-151429.43" - process $proc$issuer_ls180.v:151428$8219 - assign { } { } - assign $0\sr_op__rc__ok[0:0] \sr_op__rc__ok$next - sync posedge \coresync_clk - update \sr_op__rc__ok $0\sr_op__rc__ok[0:0] - end - attribute \src "issuer_ls180.v:151430.3-151431.43" - process $proc$issuer_ls180.v:151430$8220 - assign { } { } - assign $0\sr_op__oe__oe[0:0] \sr_op__oe__oe$next - sync posedge \coresync_clk - update \sr_op__oe__oe $0\sr_op__oe__oe[0:0] - end - attribute \src "issuer_ls180.v:151432.3-151433.43" - process $proc$issuer_ls180.v:151432$8221 - assign { } { } - assign $0\sr_op__oe__ok[0:0] \sr_op__oe__ok$next - sync posedge \coresync_clk - update \sr_op__oe__ok $0\sr_op__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:151434.3-151435.49" - process $proc$issuer_ls180.v:151434$8222 - assign { } { } - assign $0\sr_op__write_cr0[0:0] \sr_op__write_cr0$next - sync posedge \coresync_clk - update \sr_op__write_cr0 $0\sr_op__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:151436.3-151437.53" - process $proc$issuer_ls180.v:151436$8223 - assign { } { } - assign $0\sr_op__input_carry[1:0] \sr_op__input_carry$next - sync posedge \coresync_clk - update \sr_op__input_carry $0\sr_op__input_carry[1:0] - end - attribute \src "issuer_ls180.v:151438.3-151439.55" - process $proc$issuer_ls180.v:151438$8224 - assign { } { } - assign $0\sr_op__output_carry[0:0] \sr_op__output_carry$next - sync posedge \coresync_clk - update \sr_op__output_carry $0\sr_op__output_carry[0:0] - end - attribute \src "issuer_ls180.v:151440.3-151441.47" - process $proc$issuer_ls180.v:151440$8225 - assign { } { } - assign $0\sr_op__input_cr[0:0] \sr_op__input_cr$next - sync posedge \coresync_clk - update \sr_op__input_cr $0\sr_op__input_cr[0:0] - end - attribute \src "issuer_ls180.v:151442.3-151443.49" - process $proc$issuer_ls180.v:151442$8226 - assign { } { } - assign $0\sr_op__output_cr[0:0] \sr_op__output_cr$next - sync posedge \coresync_clk - update \sr_op__output_cr $0\sr_op__output_cr[0:0] - end - attribute \src "issuer_ls180.v:151444.3-151445.47" - process $proc$issuer_ls180.v:151444$8227 - assign { } { } - assign $0\sr_op__is_32bit[0:0] \sr_op__is_32bit$next - sync posedge \coresync_clk - update \sr_op__is_32bit $0\sr_op__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:151446.3-151447.49" - process $proc$issuer_ls180.v:151446$8228 - assign { } { } - assign $0\sr_op__is_signed[0:0] \sr_op__is_signed$next - sync posedge \coresync_clk - update \sr_op__is_signed $0\sr_op__is_signed[0:0] - end - attribute \src "issuer_ls180.v:151448.3-151449.39" - process $proc$issuer_ls180.v:151448$8229 - assign { } { } - assign $0\sr_op__insn[31:0] \sr_op__insn$next - sync posedge \coresync_clk - update \sr_op__insn $0\sr_op__insn[31:0] - end - attribute \src "issuer_ls180.v:151450.3-151451.27" - process $proc$issuer_ls180.v:151450$8230 - assign { } { } - assign $0\muxid[1:0] \muxid$next - sync posedge \coresync_clk - update \muxid $0\muxid[1:0] - end - attribute \src "issuer_ls180.v:151452.3-151453.29" - process $proc$issuer_ls180.v:151452$8231 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "issuer_ls180.v:151552.3-151569.6" - process $proc$issuer_ls180.v:151552$8232 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$8233 $2\r_busy$next[0:0]$8235 - attribute \src "issuer_ls180.v:151553.5-151553.29" - switch \initial - attribute \src "issuer_ls180.v:151553.9-151553.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$8234 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\r_busy$next[0:0]$8234 1'0 - case - assign $1\r_busy$next[0:0]$8234 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$8235 1'0 - case - assign $2\r_busy$next[0:0]$8235 $1\r_busy$next[0:0]$8234 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$8233 - end - attribute \src "issuer_ls180.v:151570.3-151582.6" - process $proc$issuer_ls180.v:151570$8236 - assign { } { } - assign { } { } - assign $0\muxid$next[1:0]$8237 $1\muxid$next[1:0]$8238 - attribute \src "issuer_ls180.v:151571.5-151571.29" - switch \initial - attribute \src "issuer_ls180.v:151571.9-151571.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$next[1:0]$8238 \muxid$64 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$next[1:0]$8238 \muxid$64 - case - assign $1\muxid$next[1:0]$8238 \muxid - end - sync always - update \muxid$next $0\muxid$next[1:0]$8237 - end - attribute \src "issuer_ls180.v:151583.3-151622.6" - process $proc$issuer_ls180.v:151583$8239 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\sr_op__fn_unit$next[11:0]$8240 $1\sr_op__fn_unit$next[11:0]$8256 - assign { } { } - assign { } { } - assign $0\sr_op__input_carry$next[1:0]$8243 $1\sr_op__input_carry$next[1:0]$8259 - assign $0\sr_op__input_cr$next[0:0]$8244 $1\sr_op__input_cr$next[0:0]$8260 - assign $0\sr_op__insn$next[31:0]$8245 $1\sr_op__insn$next[31:0]$8261 - assign $0\sr_op__insn_type$next[6:0]$8246 $1\sr_op__insn_type$next[6:0]$8262 - assign $0\sr_op__is_32bit$next[0:0]$8247 $1\sr_op__is_32bit$next[0:0]$8263 - assign $0\sr_op__is_signed$next[0:0]$8248 $1\sr_op__is_signed$next[0:0]$8264 - assign { } { } - assign { } { } - assign $0\sr_op__output_carry$next[0:0]$8251 $1\sr_op__output_carry$next[0:0]$8267 - assign $0\sr_op__output_cr$next[0:0]$8252 $1\sr_op__output_cr$next[0:0]$8268 - assign { } { } - assign { } { } - assign $0\sr_op__write_cr0$next[0:0]$8255 $1\sr_op__write_cr0$next[0:0]$8271 - assign $0\sr_op__imm_data__data$next[63:0]$8241 $2\sr_op__imm_data__data$next[63:0]$8272 - assign $0\sr_op__imm_data__ok$next[0:0]$8242 $2\sr_op__imm_data__ok$next[0:0]$8273 - assign $0\sr_op__oe__oe$next[0:0]$8249 $2\sr_op__oe__oe$next[0:0]$8274 - assign $0\sr_op__oe__ok$next[0:0]$8250 $2\sr_op__oe__ok$next[0:0]$8275 - assign $0\sr_op__rc__ok$next[0:0]$8253 $2\sr_op__rc__ok$next[0:0]$8276 - assign $0\sr_op__rc__rc$next[0:0]$8254 $2\sr_op__rc__rc$next[0:0]$8277 - attribute \src "issuer_ls180.v:151584.5-151584.29" - switch \initial - attribute \src "issuer_ls180.v:151584.9-151584.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\sr_op__insn$next[31:0]$8261 $1\sr_op__is_signed$next[0:0]$8264 $1\sr_op__is_32bit$next[0:0]$8263 $1\sr_op__output_cr$next[0:0]$8268 $1\sr_op__input_cr$next[0:0]$8260 $1\sr_op__output_carry$next[0:0]$8267 $1\sr_op__input_carry$next[1:0]$8259 $1\sr_op__write_cr0$next[0:0]$8271 $1\sr_op__oe__ok$next[0:0]$8266 $1\sr_op__oe__oe$next[0:0]$8265 $1\sr_op__rc__ok$next[0:0]$8269 $1\sr_op__rc__rc$next[0:0]$8270 $1\sr_op__imm_data__ok$next[0:0]$8258 $1\sr_op__imm_data__data$next[63:0]$8257 $1\sr_op__fn_unit$next[11:0]$8256 $1\sr_op__insn_type$next[6:0]$8262 } { \sr_op__insn$80 \sr_op__is_signed$79 \sr_op__is_32bit$78 \sr_op__output_cr$77 \sr_op__input_cr$76 \sr_op__output_carry$75 \sr_op__input_carry$74 \sr_op__write_cr0$73 \sr_op__oe__ok$72 \sr_op__oe__oe$71 \sr_op__rc__ok$70 \sr_op__rc__rc$69 \sr_op__imm_data__ok$68 \sr_op__imm_data__data$67 \sr_op__fn_unit$66 \sr_op__insn_type$65 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\sr_op__insn$next[31:0]$8261 $1\sr_op__is_signed$next[0:0]$8264 $1\sr_op__is_32bit$next[0:0]$8263 $1\sr_op__output_cr$next[0:0]$8268 $1\sr_op__input_cr$next[0:0]$8260 $1\sr_op__output_carry$next[0:0]$8267 $1\sr_op__input_carry$next[1:0]$8259 $1\sr_op__write_cr0$next[0:0]$8271 $1\sr_op__oe__ok$next[0:0]$8266 $1\sr_op__oe__oe$next[0:0]$8265 $1\sr_op__rc__ok$next[0:0]$8269 $1\sr_op__rc__rc$next[0:0]$8270 $1\sr_op__imm_data__ok$next[0:0]$8258 $1\sr_op__imm_data__data$next[63:0]$8257 $1\sr_op__fn_unit$next[11:0]$8256 $1\sr_op__insn_type$next[6:0]$8262 } { \sr_op__insn$80 \sr_op__is_signed$79 \sr_op__is_32bit$78 \sr_op__output_cr$77 \sr_op__input_cr$76 \sr_op__output_carry$75 \sr_op__input_carry$74 \sr_op__write_cr0$73 \sr_op__oe__ok$72 \sr_op__oe__oe$71 \sr_op__rc__ok$70 \sr_op__rc__rc$69 \sr_op__imm_data__ok$68 \sr_op__imm_data__data$67 \sr_op__fn_unit$66 \sr_op__insn_type$65 } - case - assign $1\sr_op__fn_unit$next[11:0]$8256 \sr_op__fn_unit - assign $1\sr_op__imm_data__data$next[63:0]$8257 \sr_op__imm_data__data - assign $1\sr_op__imm_data__ok$next[0:0]$8258 \sr_op__imm_data__ok - assign $1\sr_op__input_carry$next[1:0]$8259 \sr_op__input_carry - assign $1\sr_op__input_cr$next[0:0]$8260 \sr_op__input_cr - assign $1\sr_op__insn$next[31:0]$8261 \sr_op__insn - assign $1\sr_op__insn_type$next[6:0]$8262 \sr_op__insn_type - assign $1\sr_op__is_32bit$next[0:0]$8263 \sr_op__is_32bit - assign $1\sr_op__is_signed$next[0:0]$8264 \sr_op__is_signed - assign $1\sr_op__oe__oe$next[0:0]$8265 \sr_op__oe__oe - assign $1\sr_op__oe__ok$next[0:0]$8266 \sr_op__oe__ok - assign $1\sr_op__output_carry$next[0:0]$8267 \sr_op__output_carry - assign $1\sr_op__output_cr$next[0:0]$8268 \sr_op__output_cr - assign $1\sr_op__rc__ok$next[0:0]$8269 \sr_op__rc__ok - assign $1\sr_op__rc__rc$next[0:0]$8270 \sr_op__rc__rc - assign $1\sr_op__write_cr0$next[0:0]$8271 \sr_op__write_cr0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\sr_op__imm_data__data$next[63:0]$8272 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\sr_op__imm_data__ok$next[0:0]$8273 1'0 - assign $2\sr_op__rc__rc$next[0:0]$8277 1'0 - assign $2\sr_op__rc__ok$next[0:0]$8276 1'0 - assign $2\sr_op__oe__oe$next[0:0]$8274 1'0 - assign $2\sr_op__oe__ok$next[0:0]$8275 1'0 - case - assign $2\sr_op__imm_data__data$next[63:0]$8272 $1\sr_op__imm_data__data$next[63:0]$8257 - assign $2\sr_op__imm_data__ok$next[0:0]$8273 $1\sr_op__imm_data__ok$next[0:0]$8258 - assign $2\sr_op__oe__oe$next[0:0]$8274 $1\sr_op__oe__oe$next[0:0]$8265 - assign $2\sr_op__oe__ok$next[0:0]$8275 $1\sr_op__oe__ok$next[0:0]$8266 - assign $2\sr_op__rc__ok$next[0:0]$8276 $1\sr_op__rc__ok$next[0:0]$8269 - assign $2\sr_op__rc__rc$next[0:0]$8277 $1\sr_op__rc__rc$next[0:0]$8270 - end - sync always - update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[11:0]$8240 - update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$8241 - update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$8242 - update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$8243 - update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$8244 - update \sr_op__insn$next $0\sr_op__insn$next[31:0]$8245 - update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$8246 - update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$8247 - update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$8248 - update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$8249 - update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$8250 - update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$8251 - update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$8252 - update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$8253 - update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$8254 - update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$8255 - end - attribute \src "issuer_ls180.v:151623.3-151641.6" - process $proc$issuer_ls180.v:151623$8278 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$next[63:0]$8279 $1\o$next[63:0]$8281 - assign { } { } - assign $0\o_ok$next[0:0]$8280 $2\o_ok$next[0:0]$8283 - attribute \src "issuer_ls180.v:151624.5-151624.29" - switch \initial - attribute \src "issuer_ls180.v:151624.9-151624.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$8282 $1\o$next[63:0]$8281 } { \o_ok$82 \o$81 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$8282 $1\o$next[63:0]$8281 } { \o_ok$82 \o$81 } - case - assign $1\o$next[63:0]$8281 \o - assign $1\o_ok$next[0:0]$8282 \o_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o_ok$next[0:0]$8283 1'0 - case - assign $2\o_ok$next[0:0]$8283 $1\o_ok$next[0:0]$8282 - end - sync always - update \o$next $0\o$next[63:0]$8279 - update \o_ok$next $0\o_ok$next[0:0]$8280 - end - attribute \src "issuer_ls180.v:151642.3-151660.6" - process $proc$issuer_ls180.v:151642$8284 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$next[3:0]$8285 $1\cr_a$next[3:0]$8287 - assign { } { } - assign $0\cr_a_ok$next[0:0]$8286 $2\cr_a_ok$next[0:0]$8289 - attribute \src "issuer_ls180.v:151643.5-151643.29" - switch \initial - attribute \src "issuer_ls180.v:151643.9-151643.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$8288 $1\cr_a$next[3:0]$8287 } { \cr_a_ok$84 \cr_a$83 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$8288 $1\cr_a$next[3:0]$8287 } { \cr_a_ok$84 \cr_a$83 } - case - assign $1\cr_a$next[3:0]$8287 \cr_a - assign $1\cr_a_ok$next[0:0]$8288 \cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_a_ok$next[0:0]$8289 1'0 - case - assign $2\cr_a_ok$next[0:0]$8289 $1\cr_a_ok$next[0:0]$8288 - end - sync always - update \cr_a$next $0\cr_a$next[3:0]$8285 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8286 - end - attribute \src "issuer_ls180.v:151661.3-151679.6" - process $proc$issuer_ls180.v:151661$8290 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_so$next[0:0]$8291 $1\xer_so$next[0:0]$8293 - assign { } { } - assign $0\xer_so_ok$next[0:0]$8292 $2\xer_so_ok$next[0:0]$8295 - attribute \src "issuer_ls180.v:151662.5-151662.29" - switch \initial - attribute \src "issuer_ls180.v:151662.9-151662.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_so_ok$next[0:0]$8294 $1\xer_so$next[0:0]$8293 } { \xer_so_ok$88 \xer_so$87 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_so_ok$next[0:0]$8294 $1\xer_so$next[0:0]$8293 } { \xer_so_ok$88 \xer_so$87 } - case - assign $1\xer_so$next[0:0]$8293 \xer_so - assign $1\xer_so_ok$next[0:0]$8294 \xer_so_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_so_ok$next[0:0]$8295 1'0 - case - assign $2\xer_so_ok$next[0:0]$8295 $1\xer_so_ok$next[0:0]$8294 - end - sync always - update \xer_so$next $0\xer_so$next[0:0]$8291 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8292 - end - attribute \src "issuer_ls180.v:151680.3-151698.6" - process $proc$issuer_ls180.v:151680$8296 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_ca$next[1:0]$8298 $1\xer_ca$next[1:0]$8300 - assign $0\xer_ca_ok$next[0:0]$8297 $2\xer_ca_ok$next[0:0]$8301 - attribute \src "issuer_ls180.v:151681.5-151681.29" - switch \initial - attribute \src "issuer_ls180.v:151681.9-151681.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8299 $1\xer_ca$next[1:0]$8300 } { \xer_ca_ok$91 \xer_ca$90 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8299 $1\xer_ca$next[1:0]$8300 } { \xer_ca_ok$91 \xer_ca$90 } - case - assign $1\xer_ca_ok$next[0:0]$8299 \xer_ca_ok - assign $1\xer_ca$next[1:0]$8300 \xer_ca - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_ca_ok$next[0:0]$8301 1'0 - case - assign $2\xer_ca_ok$next[0:0]$8301 $1\xer_ca_ok$next[0:0]$8299 - end - sync always - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8297 - update \xer_ca$next $0\xer_ca$next[1:0]$8298 - end - connect \$62 $and$issuer_ls180.v:151401$8205_Y - connect \cr_a$85 4'0000 - connect \cr_a_ok$86 1'0 - connect \xer_so_ok$89 1'0 - connect \xer_ca_ok$92 1'0 - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \xer_ca_ok$91 \xer_ca$90 } { 1'0 \main_xer_ca } - connect { \xer_so_ok$88 \xer_so$87 } { 1'0 \main_xer_so$59 } - connect { \cr_a_ok$84 \cr_a$83 } 5'00000 - connect { \o_ok$82 \o$81 } { \main_o_ok \main_o } - connect { \sr_op__insn$80 \sr_op__is_signed$79 \sr_op__is_32bit$78 \sr_op__output_cr$77 \sr_op__input_cr$76 \sr_op__output_carry$75 \sr_op__input_carry$74 \sr_op__write_cr0$73 \sr_op__oe__ok$72 \sr_op__oe__oe$71 \sr_op__rc__ok$70 \sr_op__rc__rc$69 \sr_op__imm_data__ok$68 \sr_op__imm_data__data$67 \sr_op__fn_unit$66 \sr_op__insn_type$65 } { \main_sr_op__insn$58 \main_sr_op__is_signed$57 \main_sr_op__is_32bit$56 \main_sr_op__output_cr$55 \main_sr_op__input_cr$54 \main_sr_op__output_carry$53 \main_sr_op__input_carry$52 \main_sr_op__write_cr0$51 \main_sr_op__oe__ok$50 \main_sr_op__oe__oe$49 \main_sr_op__rc__ok$48 \main_sr_op__rc__rc$47 \main_sr_op__imm_data__ok$46 \main_sr_op__imm_data__data$45 \main_sr_op__fn_unit$44 \main_sr_op__insn_type$43 } - connect \muxid$64 \main_muxid$42 - connect \p_valid_i_p_ready_o \$62 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$61 \p_valid_i - connect \xer_ca$60 \input_xer_ca$41 - connect \main_xer_so \input_xer_so$40 - connect \main_rc \input_rc$39 - connect \main_rb \input_rb$38 - connect \main_ra \input_ra$37 - connect { \main_sr_op__insn \main_sr_op__is_signed \main_sr_op__is_32bit \main_sr_op__output_cr \main_sr_op__input_cr \main_sr_op__output_carry \main_sr_op__input_carry \main_sr_op__write_cr0 \main_sr_op__oe__ok \main_sr_op__oe__oe \main_sr_op__rc__ok \main_sr_op__rc__rc \main_sr_op__imm_data__ok \main_sr_op__imm_data__data \main_sr_op__fn_unit \main_sr_op__insn_type } { \input_sr_op__insn$36 \input_sr_op__is_signed$35 \input_sr_op__is_32bit$34 \input_sr_op__output_cr$33 \input_sr_op__input_cr$32 \input_sr_op__output_carry$31 \input_sr_op__input_carry$30 \input_sr_op__write_cr0$29 \input_sr_op__oe__ok$28 \input_sr_op__oe__oe$27 \input_sr_op__rc__ok$26 \input_sr_op__rc__rc$25 \input_sr_op__imm_data__ok$24 \input_sr_op__imm_data__data$23 \input_sr_op__fn_unit$22 \input_sr_op__insn_type$21 } - connect \main_muxid \input_muxid$20 - connect \input_xer_ca \xer_ca$19 - connect \input_xer_so \xer_so$18 - connect \input_rc \rc - connect \input_rb \rb - connect \input_ra \ra - connect { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry \input_sr_op__write_cr0 \input_sr_op__oe__ok \input_sr_op__oe__oe \input_sr_op__rc__ok \input_sr_op__rc__rc \input_sr_op__imm_data__ok \input_sr_op__imm_data__data \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$17 \sr_op__is_signed$16 \sr_op__is_32bit$15 \sr_op__output_cr$14 \sr_op__input_cr$13 \sr_op__output_carry$12 \sr_op__input_carry$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } - connect \input_muxid \muxid$1 -end -attribute \src "issuer_ls180.v:151732.1-152902.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe2" -attribute \generator "nMigen" -module \pipe2 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire width 4 $0\alu_op__data_len$18$next[3:0]$8397 - attribute \src "issuer_ls180.v:152643.3-152644.57" - wire width 4 $0\alu_op__data_len$18[3:0]$8383 - attribute \src "issuer_ls180.v:151740.13-151740.41" - wire width 4 $0\alu_op__data_len$18[3:0]$8471 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire width 12 $0\alu_op__fn_unit$3$next[11:0]$8398 - attribute \src "issuer_ls180.v:152613.3-152614.53" - wire width 12 $0\alu_op__fn_unit$3[11:0]$8353 - attribute \src "issuer_ls180.v:151775.14-151775.43" - wire width 12 $0\alu_op__fn_unit$3[11:0]$8473 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$8399 - attribute \src "issuer_ls180.v:152615.3-152616.67" - wire width 64 $0\alu_op__imm_data__data$4[63:0]$8355 - attribute \src "issuer_ls180.v:151797.14-151797.63" - wire width 64 $0\alu_op__imm_data__data$4[63:0]$8475 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $0\alu_op__imm_data__ok$5$next[0:0]$8400 - attribute \src "issuer_ls180.v:152617.3-152618.63" - wire $0\alu_op__imm_data__ok$5[0:0]$8357 - attribute \src "issuer_ls180.v:151806.7-151806.38" - wire $0\alu_op__imm_data__ok$5[0:0]$8477 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire width 2 $0\alu_op__input_carry$14$next[1:0]$8401 - attribute \src "issuer_ls180.v:152635.3-152636.63" - wire width 2 $0\alu_op__input_carry$14[1:0]$8375 - attribute \src "issuer_ls180.v:151823.13-151823.44" - wire width 2 $0\alu_op__input_carry$14[1:0]$8479 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire width 32 $0\alu_op__insn$19$next[31:0]$8402 - attribute \src "issuer_ls180.v:152645.3-152646.49" - wire width 32 $0\alu_op__insn$19[31:0]$8385 - attribute \src "issuer_ls180.v:151836.14-151836.39" - wire width 32 $0\alu_op__insn$19[31:0]$8481 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire width 7 $0\alu_op__insn_type$2$next[6:0]$8403 - attribute \src "issuer_ls180.v:152611.3-152612.57" - wire width 7 $0\alu_op__insn_type$2[6:0]$8351 - attribute \src "issuer_ls180.v:151993.13-151993.42" - wire width 7 $0\alu_op__insn_type$2[6:0]$8483 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $0\alu_op__invert_in$10$next[0:0]$8404 - attribute \src "issuer_ls180.v:152627.3-152628.59" - wire $0\alu_op__invert_in$10[0:0]$8367 - attribute \src "issuer_ls180.v:152076.7-152076.36" - wire $0\alu_op__invert_in$10[0:0]$8485 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $0\alu_op__invert_out$12$next[0:0]$8405 - attribute \src "issuer_ls180.v:152631.3-152632.61" - wire $0\alu_op__invert_out$12[0:0]$8371 - attribute \src "issuer_ls180.v:152085.7-152085.37" - wire $0\alu_op__invert_out$12[0:0]$8487 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $0\alu_op__is_32bit$16$next[0:0]$8406 - attribute \src "issuer_ls180.v:152639.3-152640.57" - wire $0\alu_op__is_32bit$16[0:0]$8379 - attribute \src "issuer_ls180.v:152094.7-152094.35" - wire $0\alu_op__is_32bit$16[0:0]$8489 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $0\alu_op__is_signed$17$next[0:0]$8407 - attribute \src "issuer_ls180.v:152641.3-152642.59" - wire $0\alu_op__is_signed$17[0:0]$8381 - attribute \src "issuer_ls180.v:152103.7-152103.36" - wire $0\alu_op__is_signed$17[0:0]$8491 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $0\alu_op__oe__oe$8$next[0:0]$8408 - attribute \src "issuer_ls180.v:152623.3-152624.51" - wire $0\alu_op__oe__oe$8[0:0]$8363 - attribute \src "issuer_ls180.v:152114.7-152114.32" - wire $0\alu_op__oe__oe$8[0:0]$8493 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $0\alu_op__oe__ok$9$next[0:0]$8409 - attribute \src "issuer_ls180.v:152625.3-152626.51" - wire $0\alu_op__oe__ok$9[0:0]$8365 - attribute \src "issuer_ls180.v:152123.7-152123.32" - wire $0\alu_op__oe__ok$9[0:0]$8495 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $0\alu_op__output_carry$15$next[0:0]$8410 - attribute \src "issuer_ls180.v:152637.3-152638.65" - wire $0\alu_op__output_carry$15[0:0]$8377 - attribute \src "issuer_ls180.v:152130.7-152130.39" - wire $0\alu_op__output_carry$15[0:0]$8497 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $0\alu_op__rc__ok$7$next[0:0]$8411 - attribute \src "issuer_ls180.v:152621.3-152622.51" - wire $0\alu_op__rc__ok$7[0:0]$8361 - attribute \src "issuer_ls180.v:152141.7-152141.32" - wire $0\alu_op__rc__ok$7[0:0]$8499 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $0\alu_op__rc__rc$6$next[0:0]$8412 - attribute \src "issuer_ls180.v:152619.3-152620.51" - wire $0\alu_op__rc__rc$6[0:0]$8359 - attribute \src "issuer_ls180.v:152148.7-152148.32" - wire $0\alu_op__rc__rc$6[0:0]$8501 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $0\alu_op__write_cr0$13$next[0:0]$8413 - attribute \src "issuer_ls180.v:152633.3-152634.59" - wire $0\alu_op__write_cr0$13[0:0]$8373 - attribute \src "issuer_ls180.v:152157.7-152157.36" - wire $0\alu_op__write_cr0$13[0:0]$8503 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $0\alu_op__zero_a$11$next[0:0]$8414 - attribute \src "issuer_ls180.v:152629.3-152630.53" - wire $0\alu_op__zero_a$11[0:0]$8369 - attribute \src "issuer_ls180.v:152166.7-152166.33" - wire $0\alu_op__zero_a$11[0:0]$8505 - attribute \src "issuer_ls180.v:152807.3-152825.6" - wire width 4 $0\cr_a$22$next[3:0]$8446 - attribute \src "issuer_ls180.v:152603.3-152604.33" - wire width 4 $0\cr_a$22[3:0]$8343 - attribute \src "issuer_ls180.v:152179.13-152179.29" - wire width 4 $0\cr_a$22[3:0]$8507 - attribute \src "issuer_ls180.v:152807.3-152825.6" - wire $0\cr_a_ok$23$next[0:0]$8447 - attribute \src "issuer_ls180.v:152605.3-152606.39" - wire $0\cr_a_ok$23[0:0]$8345 - attribute \src "issuer_ls180.v:152188.7-152188.26" - wire $0\cr_a_ok$23[0:0]$8509 - attribute \src "issuer_ls180.v:151733.7-151733.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:152733.3-152745.6" - wire width 2 $0\muxid$1$next[1:0]$8394 - attribute \src "issuer_ls180.v:152647.3-152648.33" - wire width 2 $0\muxid$1[1:0]$8387 - attribute \src "issuer_ls180.v:152199.13-152199.29" - wire width 2 $0\muxid$1[1:0]$8511 - attribute \src "issuer_ls180.v:152788.3-152806.6" - wire width 64 $0\o$20$next[63:0]$8440 - attribute \src "issuer_ls180.v:152607.3-152608.27" - wire width 64 $0\o$20[63:0]$8347 - attribute \src "issuer_ls180.v:152214.14-152214.43" - wire width 64 $0\o$20[63:0]$8513 - attribute \src "issuer_ls180.v:152788.3-152806.6" - wire $0\o_ok$21$next[0:0]$8441 - attribute \src "issuer_ls180.v:152609.3-152610.33" - wire $0\o_ok$21[0:0]$8349 - attribute \src "issuer_ls180.v:152223.7-152223.23" - wire $0\o_ok$21[0:0]$8515 - attribute \src "issuer_ls180.v:152715.3-152732.6" - wire $0\r_busy$next[0:0]$8390 - attribute \src "issuer_ls180.v:152649.3-152650.29" - wire $0\r_busy[0:0] - attribute \src "issuer_ls180.v:152826.3-152844.6" - wire width 2 $0\xer_ca$24$next[1:0]$8452 - attribute \src "issuer_ls180.v:152599.3-152600.37" - wire width 2 $0\xer_ca$24[1:0]$8339 - attribute \src "issuer_ls180.v:152534.13-152534.31" - wire width 2 $0\xer_ca$24[1:0]$8518 - attribute \src "issuer_ls180.v:152826.3-152844.6" - wire $0\xer_ca_ok$25$next[0:0]$8453 - attribute \src "issuer_ls180.v:152601.3-152602.43" - wire $0\xer_ca_ok$25[0:0]$8341 - attribute \src "issuer_ls180.v:152543.7-152543.28" - wire $0\xer_ca_ok$25[0:0]$8520 - attribute \src "issuer_ls180.v:152845.3-152863.6" - wire width 2 $0\xer_ov$26$next[1:0]$8458 - attribute \src "issuer_ls180.v:152595.3-152596.37" - wire width 2 $0\xer_ov$26[1:0]$8335 - attribute \src "issuer_ls180.v:152554.13-152554.31" - wire width 2 $0\xer_ov$26[1:0]$8522 - attribute \src "issuer_ls180.v:152845.3-152863.6" - wire $0\xer_ov_ok$27$next[0:0]$8459 - attribute \src "issuer_ls180.v:152597.3-152598.43" - wire $0\xer_ov_ok$27[0:0]$8337 - attribute \src "issuer_ls180.v:152563.7-152563.28" - wire $0\xer_ov_ok$27[0:0]$8524 - attribute \src "issuer_ls180.v:152864.3-152882.6" - wire $0\xer_so$28$next[0:0]$8464 - attribute \src "issuer_ls180.v:152591.3-152592.37" - wire $0\xer_so$28[0:0]$8331 - attribute \src "issuer_ls180.v:152574.7-152574.25" - wire $0\xer_so$28[0:0]$8526 - attribute \src "issuer_ls180.v:152864.3-152882.6" - wire $0\xer_so_ok$29$next[0:0]$8465 - attribute \src "issuer_ls180.v:152593.3-152594.43" - wire $0\xer_so_ok$29[0:0]$8333 - attribute \src "issuer_ls180.v:152583.7-152583.28" - wire $0\xer_so_ok$29[0:0]$8528 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire width 4 $1\alu_op__data_len$18$next[3:0]$8415 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire width 12 $1\alu_op__fn_unit$3$next[11:0]$8416 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$8417 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $1\alu_op__imm_data__ok$5$next[0:0]$8418 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire width 2 $1\alu_op__input_carry$14$next[1:0]$8419 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire width 32 $1\alu_op__insn$19$next[31:0]$8420 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire width 7 $1\alu_op__insn_type$2$next[6:0]$8421 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $1\alu_op__invert_in$10$next[0:0]$8422 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $1\alu_op__invert_out$12$next[0:0]$8423 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $1\alu_op__is_32bit$16$next[0:0]$8424 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $1\alu_op__is_signed$17$next[0:0]$8425 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $1\alu_op__oe__oe$8$next[0:0]$8426 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $1\alu_op__oe__ok$9$next[0:0]$8427 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $1\alu_op__output_carry$15$next[0:0]$8428 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $1\alu_op__rc__ok$7$next[0:0]$8429 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $1\alu_op__rc__rc$6$next[0:0]$8430 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $1\alu_op__write_cr0$13$next[0:0]$8431 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $1\alu_op__zero_a$11$next[0:0]$8432 - attribute \src "issuer_ls180.v:152807.3-152825.6" - wire width 4 $1\cr_a$22$next[3:0]$8448 - attribute \src "issuer_ls180.v:152807.3-152825.6" - wire $1\cr_a_ok$23$next[0:0]$8449 - attribute \src "issuer_ls180.v:152733.3-152745.6" - wire width 2 $1\muxid$1$next[1:0]$8395 - attribute \src "issuer_ls180.v:152788.3-152806.6" - wire width 64 $1\o$20$next[63:0]$8442 - attribute \src "issuer_ls180.v:152788.3-152806.6" - wire $1\o_ok$21$next[0:0]$8443 - attribute \src "issuer_ls180.v:152715.3-152732.6" - wire $1\r_busy$next[0:0]$8391 - attribute \src "issuer_ls180.v:152527.7-152527.20" - wire $1\r_busy[0:0] - attribute \src "issuer_ls180.v:152826.3-152844.6" - wire width 2 $1\xer_ca$24$next[1:0]$8454 - attribute \src "issuer_ls180.v:152826.3-152844.6" - wire $1\xer_ca_ok$25$next[0:0]$8455 - attribute \src "issuer_ls180.v:152845.3-152863.6" - wire width 2 $1\xer_ov$26$next[1:0]$8460 - attribute \src "issuer_ls180.v:152845.3-152863.6" - wire $1\xer_ov_ok$27$next[0:0]$8461 - attribute \src "issuer_ls180.v:152864.3-152882.6" - wire $1\xer_so$28$next[0:0]$8466 - attribute \src "issuer_ls180.v:152864.3-152882.6" - wire $1\xer_so_ok$29$next[0:0]$8467 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$8433 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $2\alu_op__imm_data__ok$5$next[0:0]$8434 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $2\alu_op__oe__oe$8$next[0:0]$8435 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $2\alu_op__oe__ok$9$next[0:0]$8436 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $2\alu_op__rc__ok$7$next[0:0]$8437 - attribute \src "issuer_ls180.v:152746.3-152787.6" - wire $2\alu_op__rc__rc$6$next[0:0]$8438 - attribute \src "issuer_ls180.v:152807.3-152825.6" - wire $2\cr_a_ok$23$next[0:0]$8450 - attribute \src "issuer_ls180.v:152788.3-152806.6" - wire $2\o_ok$21$next[0:0]$8444 - attribute \src "issuer_ls180.v:152715.3-152732.6" - wire $2\r_busy$next[0:0]$8392 - attribute \src "issuer_ls180.v:152826.3-152844.6" - wire $2\xer_ca_ok$25$next[0:0]$8456 - attribute \src "issuer_ls180.v:152845.3-152863.6" - wire $2\xer_ov_ok$27$next[0:0]$8462 - attribute \src "issuer_ls180.v:152864.3-152882.6" - wire $2\xer_so_ok$29$next[0:0]$8468 - attribute \src "issuer_ls180.v:152590.18-152590.118" - wire $and$issuer_ls180.v:152590$8329_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 52 \alu_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$79 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \alu_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 37 \alu_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_op__fn_unit$3$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_op__fn_unit$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 38 \alu_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__data$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__data$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \alu_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__imm_data__ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__imm_data__ok$66 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 17 \alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 48 \alu_op__input_carry$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$14$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 53 \alu_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$80 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \alu_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 36 \alu_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$2$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 44 \alu_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_in$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_in$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 46 \alu_op__invert_out$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_out$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_out$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 50 \alu_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_32bit$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 51 \alu_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_signed$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__oe$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 42 \alu_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__ok$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 43 \alu_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 49 \alu_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__output_carry$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__output_carry$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__ok$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 41 \alu_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \alu_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__rc$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 47 \alu_op__write_cr0$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__write_cr0$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__write_cr0$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 45 \alu_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__zero_a$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__zero_a$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 64 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 input 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 56 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 26 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 57 \cr_a_ok$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$84 - attribute \src "issuer_ls180.v:151733.7-151733.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 35 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$62 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 34 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 33 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 23 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 54 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 24 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 55 \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$21$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_alu_op__data_len$47 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_alu_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_alu_op__fn_unit$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_alu_op__imm_data__data$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__imm_data__ok - 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so$28$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 32 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 63 \xer_so_ok$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$29$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$90 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$issuer_ls180.v:152590$8329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 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connect \alu_op__rc__ok \output_alu_op__rc__ok - connect \alu_op__rc__ok$7 \output_alu_op__rc__ok$36 - connect \alu_op__rc__rc \output_alu_op__rc__rc - connect \alu_op__rc__rc$6 \output_alu_op__rc__rc$35 - connect \alu_op__write_cr0 \output_alu_op__write_cr0 - connect \alu_op__write_cr0$13 \output_alu_op__write_cr0$42 - connect \alu_op__zero_a \output_alu_op__zero_a - connect \alu_op__zero_a$11 \output_alu_op__zero_a$40 - connect \cr_a \output_cr_a - connect \cr_a$22 \output_cr_a$51 - connect \cr_a_ok \output_cr_a_ok - connect \muxid \output_muxid - connect \muxid$1 \output_muxid$30 - connect \o \output_o - connect \o$20 \output_o$49 - connect \o_ok \output_o_ok - connect \o_ok$21 \output_o_ok$50 - connect \xer_ca \output_xer_ca - connect \xer_ca$23 \output_xer_ca$52 - connect \xer_ca_ok \output_xer_ca_ok - connect \xer_ov \output_xer_ov - connect \xer_ov$24 \output_xer_ov$53 - connect \xer_ov_ok \output_xer_ov_ok - connect \xer_so \output_xer_so - connect \xer_so$25 \output_xer_so$54 - connect \xer_so_ok \output_xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:152711.9-152714.4" - cell \p$3 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "issuer_ls180.v:151733.7-151733.20" - process $proc$issuer_ls180.v:151733$8469 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:151740.13-151740.41" - process $proc$issuer_ls180.v:151740$8470 - assign { } { } - assign $0\alu_op__data_len$18[3:0]$8471 4'0000 - sync always - sync init - update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$8471 - end - attribute \src "issuer_ls180.v:151775.14-151775.43" - process $proc$issuer_ls180.v:151775$8472 - assign { } { } - assign $0\alu_op__fn_unit$3[11:0]$8473 12'000000000000 - sync always - sync init - update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[11:0]$8473 - end - attribute \src "issuer_ls180.v:151797.14-151797.63" - process $proc$issuer_ls180.v:151797$8474 - assign { } { } - assign $0\alu_op__imm_data__data$4[63:0]$8475 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$8475 - end - attribute \src "issuer_ls180.v:151806.7-151806.38" - process $proc$issuer_ls180.v:151806$8476 - assign { } { } - assign $0\alu_op__imm_data__ok$5[0:0]$8477 1'0 - sync always - sync init - update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$8477 - end - attribute \src "issuer_ls180.v:151823.13-151823.44" - process $proc$issuer_ls180.v:151823$8478 - assign { } { } - assign $0\alu_op__input_carry$14[1:0]$8479 2'00 - sync always - sync init - update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$8479 - end - attribute \src "issuer_ls180.v:151836.14-151836.39" - process $proc$issuer_ls180.v:151836$8480 - assign { } { } - assign $0\alu_op__insn$19[31:0]$8481 0 - sync always - sync init - update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$8481 - end - attribute \src "issuer_ls180.v:151993.13-151993.42" - process $proc$issuer_ls180.v:151993$8482 - assign { } { } - assign $0\alu_op__insn_type$2[6:0]$8483 7'0000000 - sync always - sync init - update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$8483 - end - attribute \src "issuer_ls180.v:152076.7-152076.36" - process $proc$issuer_ls180.v:152076$8484 - assign { } { } - assign $0\alu_op__invert_in$10[0:0]$8485 1'0 - sync always - sync init - update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$8485 - end - attribute \src "issuer_ls180.v:152085.7-152085.37" - process $proc$issuer_ls180.v:152085$8486 - assign { } { } - assign $0\alu_op__invert_out$12[0:0]$8487 1'0 - sync always - sync init - update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$8487 - end - attribute \src "issuer_ls180.v:152094.7-152094.35" - process $proc$issuer_ls180.v:152094$8488 - assign { } { } - assign $0\alu_op__is_32bit$16[0:0]$8489 1'0 - sync always - sync init - update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$8489 - end - attribute \src "issuer_ls180.v:152103.7-152103.36" - process $proc$issuer_ls180.v:152103$8490 - assign { } { } - assign $0\alu_op__is_signed$17[0:0]$8491 1'0 - sync always - sync init - update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$8491 - end - attribute \src "issuer_ls180.v:152114.7-152114.32" - process $proc$issuer_ls180.v:152114$8492 - assign { } { } - assign $0\alu_op__oe__oe$8[0:0]$8493 1'0 - sync always - sync init - update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$8493 - end - attribute \src "issuer_ls180.v:152123.7-152123.32" - process $proc$issuer_ls180.v:152123$8494 - assign { } { } - assign $0\alu_op__oe__ok$9[0:0]$8495 1'0 - sync always - sync init - update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$8495 - end - attribute \src "issuer_ls180.v:152130.7-152130.39" - process $proc$issuer_ls180.v:152130$8496 - assign { } { } - assign $0\alu_op__output_carry$15[0:0]$8497 1'0 - sync always - sync init - update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$8497 - end - attribute \src "issuer_ls180.v:152141.7-152141.32" - process $proc$issuer_ls180.v:152141$8498 - assign { } { } - assign $0\alu_op__rc__ok$7[0:0]$8499 1'0 - sync always - sync init - update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$8499 - end - attribute \src "issuer_ls180.v:152148.7-152148.32" - process $proc$issuer_ls180.v:152148$8500 - assign { } { } - assign $0\alu_op__rc__rc$6[0:0]$8501 1'0 - sync always - sync init - update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$8501 - end - attribute \src "issuer_ls180.v:152157.7-152157.36" - process $proc$issuer_ls180.v:152157$8502 - assign { } { } - assign $0\alu_op__write_cr0$13[0:0]$8503 1'0 - sync always - sync init - update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$8503 - end - attribute \src "issuer_ls180.v:152166.7-152166.33" - process $proc$issuer_ls180.v:152166$8504 - assign { } { } - assign $0\alu_op__zero_a$11[0:0]$8505 1'0 - sync always - sync init - update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$8505 - end - attribute \src "issuer_ls180.v:152179.13-152179.29" - process $proc$issuer_ls180.v:152179$8506 - assign { } { } - assign $0\cr_a$22[3:0]$8507 4'0000 - sync always - sync init - update \cr_a$22 $0\cr_a$22[3:0]$8507 - end - attribute \src "issuer_ls180.v:152188.7-152188.26" - process $proc$issuer_ls180.v:152188$8508 - assign { } { } - assign $0\cr_a_ok$23[0:0]$8509 1'0 - sync always - sync init - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$8509 - end - attribute \src "issuer_ls180.v:152199.13-152199.29" - process $proc$issuer_ls180.v:152199$8510 - assign { } { } - assign $0\muxid$1[1:0]$8511 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$8511 - end - attribute \src "issuer_ls180.v:152214.14-152214.43" - process $proc$issuer_ls180.v:152214$8512 - assign { } { } - assign $0\o$20[63:0]$8513 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o$20 $0\o$20[63:0]$8513 - end - attribute \src "issuer_ls180.v:152223.7-152223.23" - process $proc$issuer_ls180.v:152223$8514 - assign { } { } - assign $0\o_ok$21[0:0]$8515 1'0 - sync always - sync init - update \o_ok$21 $0\o_ok$21[0:0]$8515 - end - attribute \src "issuer_ls180.v:152527.7-152527.20" - process $proc$issuer_ls180.v:152527$8516 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "issuer_ls180.v:152534.13-152534.31" - process $proc$issuer_ls180.v:152534$8517 - assign { } { } - assign $0\xer_ca$24[1:0]$8518 2'00 - sync always - sync init - update \xer_ca$24 $0\xer_ca$24[1:0]$8518 - end - attribute \src "issuer_ls180.v:152543.7-152543.28" - process $proc$issuer_ls180.v:152543$8519 - assign { } { } - assign $0\xer_ca_ok$25[0:0]$8520 1'0 - sync always - sync init - update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$8520 - end - attribute \src "issuer_ls180.v:152554.13-152554.31" - process $proc$issuer_ls180.v:152554$8521 - assign { } { } - assign $0\xer_ov$26[1:0]$8522 2'00 - sync always - sync init - update \xer_ov$26 $0\xer_ov$26[1:0]$8522 - end - attribute \src "issuer_ls180.v:152563.7-152563.28" - process $proc$issuer_ls180.v:152563$8523 - assign { } { } - assign $0\xer_ov_ok$27[0:0]$8524 1'0 - sync always - sync init - update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$8524 - end - attribute \src "issuer_ls180.v:152574.7-152574.25" - process $proc$issuer_ls180.v:152574$8525 - assign { } { } - assign $0\xer_so$28[0:0]$8526 1'0 - sync always - sync init - update \xer_so$28 $0\xer_so$28[0:0]$8526 - end - attribute \src "issuer_ls180.v:152583.7-152583.28" - process $proc$issuer_ls180.v:152583$8527 - assign { } { } - assign $0\xer_so_ok$29[0:0]$8528 1'0 - sync always - sync init - update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$8528 - end - attribute \src "issuer_ls180.v:152591.3-152592.37" - process $proc$issuer_ls180.v:152591$8330 - assign { } { } - assign $0\xer_so$28[0:0]$8331 \xer_so$28$next - sync posedge \coresync_clk - update \xer_so$28 $0\xer_so$28[0:0]$8331 - end - attribute \src "issuer_ls180.v:152593.3-152594.43" - process $proc$issuer_ls180.v:152593$8332 - assign { } { } - assign $0\xer_so_ok$29[0:0]$8333 \xer_so_ok$29$next - sync posedge \coresync_clk - update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$8333 - end - attribute \src "issuer_ls180.v:152595.3-152596.37" - process $proc$issuer_ls180.v:152595$8334 - assign { } { } - assign $0\xer_ov$26[1:0]$8335 \xer_ov$26$next - sync posedge \coresync_clk - update \xer_ov$26 $0\xer_ov$26[1:0]$8335 - end - attribute \src "issuer_ls180.v:152597.3-152598.43" - process $proc$issuer_ls180.v:152597$8336 - assign { } { } - assign $0\xer_ov_ok$27[0:0]$8337 \xer_ov_ok$27$next - sync posedge \coresync_clk - update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$8337 - end - attribute \src "issuer_ls180.v:152599.3-152600.37" - process $proc$issuer_ls180.v:152599$8338 - assign { } { } - assign $0\xer_ca$24[1:0]$8339 \xer_ca$24$next - sync posedge \coresync_clk - update \xer_ca$24 $0\xer_ca$24[1:0]$8339 - end - attribute \src "issuer_ls180.v:152601.3-152602.43" - process $proc$issuer_ls180.v:152601$8340 - assign { } { } - assign $0\xer_ca_ok$25[0:0]$8341 \xer_ca_ok$25$next - sync posedge \coresync_clk - update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$8341 - end - attribute \src "issuer_ls180.v:152603.3-152604.33" - process $proc$issuer_ls180.v:152603$8342 - assign { } { } - assign $0\cr_a$22[3:0]$8343 \cr_a$22$next - sync posedge \coresync_clk - update \cr_a$22 $0\cr_a$22[3:0]$8343 - end - attribute \src "issuer_ls180.v:152605.3-152606.39" - process $proc$issuer_ls180.v:152605$8344 - assign { } { } - assign $0\cr_a_ok$23[0:0]$8345 \cr_a_ok$23$next - sync posedge \coresync_clk - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$8345 - end - attribute \src "issuer_ls180.v:152607.3-152608.27" - process $proc$issuer_ls180.v:152607$8346 - assign { } { } - assign $0\o$20[63:0]$8347 \o$20$next - sync posedge \coresync_clk - update \o$20 $0\o$20[63:0]$8347 - end - attribute \src "issuer_ls180.v:152609.3-152610.33" - process $proc$issuer_ls180.v:152609$8348 - assign { } { } - assign $0\o_ok$21[0:0]$8349 \o_ok$21$next - sync posedge \coresync_clk - update \o_ok$21 $0\o_ok$21[0:0]$8349 - end - attribute \src "issuer_ls180.v:152611.3-152612.57" - process $proc$issuer_ls180.v:152611$8350 - assign { } { } - assign $0\alu_op__insn_type$2[6:0]$8351 \alu_op__insn_type$2$next - sync posedge \coresync_clk - update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$8351 - end - attribute \src "issuer_ls180.v:152613.3-152614.53" - process $proc$issuer_ls180.v:152613$8352 - assign { } { } - assign $0\alu_op__fn_unit$3[11:0]$8353 \alu_op__fn_unit$3$next - sync posedge \coresync_clk - update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[11:0]$8353 - end - attribute \src "issuer_ls180.v:152615.3-152616.67" - process $proc$issuer_ls180.v:152615$8354 - assign { } { } - assign $0\alu_op__imm_data__data$4[63:0]$8355 \alu_op__imm_data__data$4$next - sync posedge \coresync_clk - update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$8355 - end - attribute \src "issuer_ls180.v:152617.3-152618.63" - process $proc$issuer_ls180.v:152617$8356 - assign { } { } - assign $0\alu_op__imm_data__ok$5[0:0]$8357 \alu_op__imm_data__ok$5$next - sync posedge \coresync_clk - update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$8357 - end - attribute \src "issuer_ls180.v:152619.3-152620.51" - process $proc$issuer_ls180.v:152619$8358 - assign { } { } - assign $0\alu_op__rc__rc$6[0:0]$8359 \alu_op__rc__rc$6$next - sync posedge \coresync_clk - update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$8359 - end - attribute \src "issuer_ls180.v:152621.3-152622.51" - process $proc$issuer_ls180.v:152621$8360 - assign { } { } - assign $0\alu_op__rc__ok$7[0:0]$8361 \alu_op__rc__ok$7$next - sync posedge \coresync_clk - update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$8361 - end - attribute \src "issuer_ls180.v:152623.3-152624.51" - process $proc$issuer_ls180.v:152623$8362 - assign { } { } - assign $0\alu_op__oe__oe$8[0:0]$8363 \alu_op__oe__oe$8$next - sync posedge \coresync_clk - update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$8363 - end - attribute \src "issuer_ls180.v:152625.3-152626.51" - process $proc$issuer_ls180.v:152625$8364 - assign { } { } - assign $0\alu_op__oe__ok$9[0:0]$8365 \alu_op__oe__ok$9$next - sync posedge \coresync_clk - update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$8365 - end - attribute \src "issuer_ls180.v:152627.3-152628.59" - process $proc$issuer_ls180.v:152627$8366 - assign { } { } - assign $0\alu_op__invert_in$10[0:0]$8367 \alu_op__invert_in$10$next - sync posedge \coresync_clk - update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$8367 - end - attribute \src "issuer_ls180.v:152629.3-152630.53" - process $proc$issuer_ls180.v:152629$8368 - assign { } { } - assign $0\alu_op__zero_a$11[0:0]$8369 \alu_op__zero_a$11$next - sync posedge \coresync_clk - update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$8369 - end - attribute \src "issuer_ls180.v:152631.3-152632.61" - process $proc$issuer_ls180.v:152631$8370 - assign { } { } - assign $0\alu_op__invert_out$12[0:0]$8371 \alu_op__invert_out$12$next - sync posedge \coresync_clk - update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$8371 - end - attribute \src "issuer_ls180.v:152633.3-152634.59" - process $proc$issuer_ls180.v:152633$8372 - assign { } { } - assign $0\alu_op__write_cr0$13[0:0]$8373 \alu_op__write_cr0$13$next - sync posedge \coresync_clk - update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$8373 - end - attribute \src "issuer_ls180.v:152635.3-152636.63" - process $proc$issuer_ls180.v:152635$8374 - assign { } { } - assign $0\alu_op__input_carry$14[1:0]$8375 \alu_op__input_carry$14$next - sync posedge \coresync_clk - update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$8375 - end - attribute \src "issuer_ls180.v:152637.3-152638.65" - process $proc$issuer_ls180.v:152637$8376 - assign { } { } - assign $0\alu_op__output_carry$15[0:0]$8377 \alu_op__output_carry$15$next - sync posedge \coresync_clk - update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$8377 - end - attribute \src "issuer_ls180.v:152639.3-152640.57" - process $proc$issuer_ls180.v:152639$8378 - assign { } { } - assign $0\alu_op__is_32bit$16[0:0]$8379 \alu_op__is_32bit$16$next - sync posedge \coresync_clk - update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$8379 - end - attribute \src "issuer_ls180.v:152641.3-152642.59" - process $proc$issuer_ls180.v:152641$8380 - assign { } { } - assign $0\alu_op__is_signed$17[0:0]$8381 \alu_op__is_signed$17$next - sync posedge \coresync_clk - update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$8381 - end - attribute \src "issuer_ls180.v:152643.3-152644.57" - process $proc$issuer_ls180.v:152643$8382 - assign { } { } - assign $0\alu_op__data_len$18[3:0]$8383 \alu_op__data_len$18$next - sync posedge \coresync_clk - update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$8383 - end - attribute \src "issuer_ls180.v:152645.3-152646.49" - process $proc$issuer_ls180.v:152645$8384 - assign { } { } - assign $0\alu_op__insn$19[31:0]$8385 \alu_op__insn$19$next - sync posedge \coresync_clk - update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$8385 - end - attribute \src "issuer_ls180.v:152647.3-152648.33" - process $proc$issuer_ls180.v:152647$8386 - assign { } { } - assign $0\muxid$1[1:0]$8387 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8387 - end - attribute \src "issuer_ls180.v:152649.3-152650.29" - process $proc$issuer_ls180.v:152649$8388 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "issuer_ls180.v:152715.3-152732.6" - process $proc$issuer_ls180.v:152715$8389 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$8390 $2\r_busy$next[0:0]$8392 - attribute \src "issuer_ls180.v:152716.5-152716.29" - switch \initial - attribute \src "issuer_ls180.v:152716.9-152716.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$8391 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\r_busy$next[0:0]$8391 1'0 - case - assign $1\r_busy$next[0:0]$8391 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$8392 1'0 - case - assign $2\r_busy$next[0:0]$8392 $1\r_busy$next[0:0]$8391 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$8390 - end - attribute \src "issuer_ls180.v:152733.3-152745.6" - process $proc$issuer_ls180.v:152733$8393 - assign { } { } - assign { } { } - assign $0\muxid$1$next[1:0]$8394 $1\muxid$1$next[1:0]$8395 - attribute \src "issuer_ls180.v:152734.5-152734.29" - switch \initial - attribute \src "issuer_ls180.v:152734.9-152734.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$1$next[1:0]$8395 \muxid$62 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$1$next[1:0]$8395 \muxid$62 - case - assign $1\muxid$1$next[1:0]$8395 \muxid$1 - end - sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8394 - end - attribute \src "issuer_ls180.v:152746.3-152787.6" - process $proc$issuer_ls180.v:152746$8396 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_op__data_len$18$next[3:0]$8397 $1\alu_op__data_len$18$next[3:0]$8415 - assign $0\alu_op__fn_unit$3$next[11:0]$8398 $1\alu_op__fn_unit$3$next[11:0]$8416 - assign { } { } - assign { } { } - assign $0\alu_op__input_carry$14$next[1:0]$8401 $1\alu_op__input_carry$14$next[1:0]$8419 - assign $0\alu_op__insn$19$next[31:0]$8402 $1\alu_op__insn$19$next[31:0]$8420 - assign $0\alu_op__insn_type$2$next[6:0]$8403 $1\alu_op__insn_type$2$next[6:0]$8421 - assign $0\alu_op__invert_in$10$next[0:0]$8404 $1\alu_op__invert_in$10$next[0:0]$8422 - assign $0\alu_op__invert_out$12$next[0:0]$8405 $1\alu_op__invert_out$12$next[0:0]$8423 - assign $0\alu_op__is_32bit$16$next[0:0]$8406 $1\alu_op__is_32bit$16$next[0:0]$8424 - assign $0\alu_op__is_signed$17$next[0:0]$8407 $1\alu_op__is_signed$17$next[0:0]$8425 - assign { } { } - assign { } { } - assign $0\alu_op__output_carry$15$next[0:0]$8410 $1\alu_op__output_carry$15$next[0:0]$8428 - assign { } { } - assign { } { } - assign $0\alu_op__write_cr0$13$next[0:0]$8413 $1\alu_op__write_cr0$13$next[0:0]$8431 - assign $0\alu_op__zero_a$11$next[0:0]$8414 $1\alu_op__zero_a$11$next[0:0]$8432 - assign $0\alu_op__imm_data__data$4$next[63:0]$8399 $2\alu_op__imm_data__data$4$next[63:0]$8433 - assign $0\alu_op__imm_data__ok$5$next[0:0]$8400 $2\alu_op__imm_data__ok$5$next[0:0]$8434 - assign $0\alu_op__oe__oe$8$next[0:0]$8408 $2\alu_op__oe__oe$8$next[0:0]$8435 - assign $0\alu_op__oe__ok$9$next[0:0]$8409 $2\alu_op__oe__ok$9$next[0:0]$8436 - assign $0\alu_op__rc__ok$7$next[0:0]$8411 $2\alu_op__rc__ok$7$next[0:0]$8437 - assign $0\alu_op__rc__rc$6$next[0:0]$8412 $2\alu_op__rc__rc$6$next[0:0]$8438 - attribute \src "issuer_ls180.v:152747.5-152747.29" - switch \initial - attribute \src "issuer_ls180.v:152747.9-152747.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_op__insn$19$next[31:0]$8420 $1\alu_op__data_len$18$next[3:0]$8415 $1\alu_op__is_signed$17$next[0:0]$8425 $1\alu_op__is_32bit$16$next[0:0]$8424 $1\alu_op__output_carry$15$next[0:0]$8428 $1\alu_op__input_carry$14$next[1:0]$8419 $1\alu_op__write_cr0$13$next[0:0]$8431 $1\alu_op__invert_out$12$next[0:0]$8423 $1\alu_op__zero_a$11$next[0:0]$8432 $1\alu_op__invert_in$10$next[0:0]$8422 $1\alu_op__oe__ok$9$next[0:0]$8427 $1\alu_op__oe__oe$8$next[0:0]$8426 $1\alu_op__rc__ok$7$next[0:0]$8429 $1\alu_op__rc__rc$6$next[0:0]$8430 $1\alu_op__imm_data__ok$5$next[0:0]$8418 $1\alu_op__imm_data__data$4$next[63:0]$8417 $1\alu_op__fn_unit$3$next[11:0]$8416 $1\alu_op__insn_type$2$next[6:0]$8421 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_op__insn$19$next[31:0]$8420 $1\alu_op__data_len$18$next[3:0]$8415 $1\alu_op__is_signed$17$next[0:0]$8425 $1\alu_op__is_32bit$16$next[0:0]$8424 $1\alu_op__output_carry$15$next[0:0]$8428 $1\alu_op__input_carry$14$next[1:0]$8419 $1\alu_op__write_cr0$13$next[0:0]$8431 $1\alu_op__invert_out$12$next[0:0]$8423 $1\alu_op__zero_a$11$next[0:0]$8432 $1\alu_op__invert_in$10$next[0:0]$8422 $1\alu_op__oe__ok$9$next[0:0]$8427 $1\alu_op__oe__oe$8$next[0:0]$8426 $1\alu_op__rc__ok$7$next[0:0]$8429 $1\alu_op__rc__rc$6$next[0:0]$8430 $1\alu_op__imm_data__ok$5$next[0:0]$8418 $1\alu_op__imm_data__data$4$next[63:0]$8417 $1\alu_op__fn_unit$3$next[11:0]$8416 $1\alu_op__insn_type$2$next[6:0]$8421 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } - case - assign $1\alu_op__data_len$18$next[3:0]$8415 \alu_op__data_len$18 - assign $1\alu_op__fn_unit$3$next[11:0]$8416 \alu_op__fn_unit$3 - assign $1\alu_op__imm_data__data$4$next[63:0]$8417 \alu_op__imm_data__data$4 - assign $1\alu_op__imm_data__ok$5$next[0:0]$8418 \alu_op__imm_data__ok$5 - assign $1\alu_op__input_carry$14$next[1:0]$8419 \alu_op__input_carry$14 - assign $1\alu_op__insn$19$next[31:0]$8420 \alu_op__insn$19 - assign $1\alu_op__insn_type$2$next[6:0]$8421 \alu_op__insn_type$2 - assign $1\alu_op__invert_in$10$next[0:0]$8422 \alu_op__invert_in$10 - assign $1\alu_op__invert_out$12$next[0:0]$8423 \alu_op__invert_out$12 - assign $1\alu_op__is_32bit$16$next[0:0]$8424 \alu_op__is_32bit$16 - assign $1\alu_op__is_signed$17$next[0:0]$8425 \alu_op__is_signed$17 - assign $1\alu_op__oe__oe$8$next[0:0]$8426 \alu_op__oe__oe$8 - assign $1\alu_op__oe__ok$9$next[0:0]$8427 \alu_op__oe__ok$9 - assign $1\alu_op__output_carry$15$next[0:0]$8428 \alu_op__output_carry$15 - assign $1\alu_op__rc__ok$7$next[0:0]$8429 \alu_op__rc__ok$7 - assign $1\alu_op__rc__rc$6$next[0:0]$8430 \alu_op__rc__rc$6 - assign $1\alu_op__write_cr0$13$next[0:0]$8431 \alu_op__write_cr0$13 - assign $1\alu_op__zero_a$11$next[0:0]$8432 \alu_op__zero_a$11 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\alu_op__imm_data__data$4$next[63:0]$8433 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_op__imm_data__ok$5$next[0:0]$8434 1'0 - assign $2\alu_op__rc__rc$6$next[0:0]$8438 1'0 - assign $2\alu_op__rc__ok$7$next[0:0]$8437 1'0 - assign $2\alu_op__oe__oe$8$next[0:0]$8435 1'0 - assign $2\alu_op__oe__ok$9$next[0:0]$8436 1'0 - case - assign $2\alu_op__imm_data__data$4$next[63:0]$8433 $1\alu_op__imm_data__data$4$next[63:0]$8417 - assign $2\alu_op__imm_data__ok$5$next[0:0]$8434 $1\alu_op__imm_data__ok$5$next[0:0]$8418 - assign $2\alu_op__oe__oe$8$next[0:0]$8435 $1\alu_op__oe__oe$8$next[0:0]$8426 - assign $2\alu_op__oe__ok$9$next[0:0]$8436 $1\alu_op__oe__ok$9$next[0:0]$8427 - assign $2\alu_op__rc__ok$7$next[0:0]$8437 $1\alu_op__rc__ok$7$next[0:0]$8429 - assign $2\alu_op__rc__rc$6$next[0:0]$8438 $1\alu_op__rc__rc$6$next[0:0]$8430 - end - sync always - update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$8397 - update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[11:0]$8398 - update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$8399 - update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$8400 - update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$8401 - update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$8402 - update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$8403 - update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$8404 - update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$8405 - update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$8406 - update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$8407 - update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$8408 - update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$8409 - update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$8410 - update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$8411 - update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$8412 - update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$8413 - update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$8414 - end - attribute \src "issuer_ls180.v:152788.3-152806.6" - process $proc$issuer_ls180.v:152788$8439 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$20$next[63:0]$8440 $1\o$20$next[63:0]$8442 - assign { } { } - assign $0\o_ok$21$next[0:0]$8441 $2\o_ok$21$next[0:0]$8444 - attribute \src "issuer_ls180.v:152789.5-152789.29" - switch \initial - attribute \src "issuer_ls180.v:152789.9-152789.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$21$next[0:0]$8443 $1\o$20$next[63:0]$8442 } { \o_ok$82 \o$81 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\o_ok$21$next[0:0]$8443 $1\o$20$next[63:0]$8442 } { \o_ok$82 \o$81 } - case - assign $1\o$20$next[63:0]$8442 \o$20 - assign $1\o_ok$21$next[0:0]$8443 \o_ok$21 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o_ok$21$next[0:0]$8444 1'0 - case - assign $2\o_ok$21$next[0:0]$8444 $1\o_ok$21$next[0:0]$8443 - end - sync always - update \o$20$next $0\o$20$next[63:0]$8440 - update \o_ok$21$next $0\o_ok$21$next[0:0]$8441 - end - attribute \src "issuer_ls180.v:152807.3-152825.6" - process $proc$issuer_ls180.v:152807$8445 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$22$next[3:0]$8446 $1\cr_a$22$next[3:0]$8448 - assign { } { } - assign $0\cr_a_ok$23$next[0:0]$8447 $2\cr_a_ok$23$next[0:0]$8450 - attribute \src "issuer_ls180.v:152808.5-152808.29" - switch \initial - attribute \src "issuer_ls180.v:152808.9-152808.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$8449 $1\cr_a$22$next[3:0]$8448 } { \cr_a_ok$84 \cr_a$83 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$8449 $1\cr_a$22$next[3:0]$8448 } { \cr_a_ok$84 \cr_a$83 } - case - assign $1\cr_a$22$next[3:0]$8448 \cr_a$22 - assign $1\cr_a_ok$23$next[0:0]$8449 \cr_a_ok$23 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_a_ok$23$next[0:0]$8450 1'0 - case - assign $2\cr_a_ok$23$next[0:0]$8450 $1\cr_a_ok$23$next[0:0]$8449 - end - sync always - update \cr_a$22$next $0\cr_a$22$next[3:0]$8446 - update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$8447 - end - attribute \src "issuer_ls180.v:152826.3-152844.6" - process $proc$issuer_ls180.v:152826$8451 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_ca$24$next[1:0]$8452 $1\xer_ca$24$next[1:0]$8454 - assign { } { } - assign $0\xer_ca_ok$25$next[0:0]$8453 $2\xer_ca_ok$25$next[0:0]$8456 - attribute \src "issuer_ls180.v:152827.5-152827.29" - switch \initial - attribute \src "issuer_ls180.v:152827.9-152827.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_ca_ok$25$next[0:0]$8455 $1\xer_ca$24$next[1:0]$8454 } { \xer_ca_ok$86 \xer_ca$85 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_ca_ok$25$next[0:0]$8455 $1\xer_ca$24$next[1:0]$8454 } { \xer_ca_ok$86 \xer_ca$85 } - case - assign $1\xer_ca$24$next[1:0]$8454 \xer_ca$24 - assign $1\xer_ca_ok$25$next[0:0]$8455 \xer_ca_ok$25 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_ca_ok$25$next[0:0]$8456 1'0 - case - assign $2\xer_ca_ok$25$next[0:0]$8456 $1\xer_ca_ok$25$next[0:0]$8455 - end - sync always - update \xer_ca$24$next $0\xer_ca$24$next[1:0]$8452 - update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$8453 - end - attribute \src "issuer_ls180.v:152845.3-152863.6" - process $proc$issuer_ls180.v:152845$8457 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_ov$26$next[1:0]$8458 $1\xer_ov$26$next[1:0]$8460 - assign { } { } - assign $0\xer_ov_ok$27$next[0:0]$8459 $2\xer_ov_ok$27$next[0:0]$8462 - attribute \src "issuer_ls180.v:152846.5-152846.29" - switch \initial - attribute \src "issuer_ls180.v:152846.9-152846.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_ov_ok$27$next[0:0]$8461 $1\xer_ov$26$next[1:0]$8460 } { \xer_ov_ok$88 \xer_ov$87 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_ov_ok$27$next[0:0]$8461 $1\xer_ov$26$next[1:0]$8460 } { \xer_ov_ok$88 \xer_ov$87 } - case - assign $1\xer_ov$26$next[1:0]$8460 \xer_ov$26 - assign $1\xer_ov_ok$27$next[0:0]$8461 \xer_ov_ok$27 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_ov_ok$27$next[0:0]$8462 1'0 - case - assign $2\xer_ov_ok$27$next[0:0]$8462 $1\xer_ov_ok$27$next[0:0]$8461 - end - sync always - update \xer_ov$26$next $0\xer_ov$26$next[1:0]$8458 - update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$8459 - end - attribute \src "issuer_ls180.v:152864.3-152882.6" - process $proc$issuer_ls180.v:152864$8463 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_so$28$next[0:0]$8464 $1\xer_so$28$next[0:0]$8466 - assign { } { } - assign $0\xer_so_ok$29$next[0:0]$8465 $2\xer_so_ok$29$next[0:0]$8468 - attribute \src "issuer_ls180.v:152865.5-152865.29" - switch \initial - attribute \src "issuer_ls180.v:152865.9-152865.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_so_ok$29$next[0:0]$8467 $1\xer_so$28$next[0:0]$8466 } { \xer_so_ok$90 \xer_so$89 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_so_ok$29$next[0:0]$8467 $1\xer_so$28$next[0:0]$8466 } { \xer_so_ok$90 \xer_so$89 } - case - assign $1\xer_so$28$next[0:0]$8466 \xer_so$28 - assign $1\xer_so_ok$29$next[0:0]$8467 \xer_so_ok$29 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_so_ok$29$next[0:0]$8468 1'0 - case - assign $2\xer_so_ok$29$next[0:0]$8468 $1\xer_so_ok$29$next[0:0]$8467 - end - sync always - update \xer_so$28$next $0\xer_so$28$next[0:0]$8464 - update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$8465 - end - connect \$60 $and$issuer_ls180.v:152590$8329_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 } - connect { \xer_ov_ok$88 \xer_ov$87 } { \output_xer_ov_ok \output_xer_ov$53 } - connect { \xer_ca_ok$86 \xer_ca$85 } { \output_xer_ca_ok \output_xer_ca$52 } - connect { \cr_a_ok$84 \cr_a$83 } { \output_cr_a_ok \output_cr_a$51 } - connect { \o_ok$82 \o$81 } { \output_o_ok$50 \output_o$49 } - connect { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } { \output_alu_op__insn$48 \output_alu_op__data_len$47 \output_alu_op__is_signed$46 \output_alu_op__is_32bit$45 \output_alu_op__output_carry$44 \output_alu_op__input_carry$43 \output_alu_op__write_cr0$42 \output_alu_op__invert_out$41 \output_alu_op__zero_a$40 \output_alu_op__invert_in$39 \output_alu_op__oe__ok$38 \output_alu_op__oe__oe$37 \output_alu_op__rc__ok$36 \output_alu_op__rc__rc$35 \output_alu_op__imm_data__ok$34 \output_alu_op__imm_data__data$33 \output_alu_op__fn_unit$32 \output_alu_op__insn_type$31 } - connect \muxid$62 \output_muxid$30 - connect \p_valid_i_p_ready_o \$60 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$59 \p_valid_i - connect { \xer_so_ok$58 \output_xer_so } { \xer_so_ok \xer_so } - connect { \xer_ov_ok$57 \output_xer_ov } { \xer_ov_ok \xer_ov } - connect { \xer_ca_ok$56 \output_xer_ca } { \xer_ca_ok \xer_ca } - connect { \cr_a_ok$55 \output_cr_a } { \cr_a_ok \cr_a } - connect { \output_o_ok \output_o } { \o_ok \o } - connect { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in \output_alu_op__oe__ok \output_alu_op__oe__oe \output_alu_op__rc__ok \output_alu_op__rc__rc \output_alu_op__imm_data__ok \output_alu_op__imm_data__data \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } - connect \output_muxid \muxid -end -attribute \src "issuer_ls180.v:152906.1-153942.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2" -attribute \generator "nMigen" -module \pipe2$112 - attribute \src "issuer_ls180.v:153888.3-153906.6" - wire width 4 $0\cr_a$20$next[3:0]$8630 - attribute \src "issuer_ls180.v:153699.3-153700.33" - wire width 4 $0\cr_a$20[3:0]$8535 - attribute \src "issuer_ls180.v:152918.13-152918.29" - wire width 4 $0\cr_a$20[3:0]$8643 - attribute \src "issuer_ls180.v:153888.3-153906.6" - wire $0\cr_a_ok$21$next[0:0]$8631 - attribute \src "issuer_ls180.v:153701.3-153702.39" - wire $0\cr_a_ok$21[0:0]$8537 - attribute \src "issuer_ls180.v:152927.7-152927.26" - wire $0\cr_a_ok$21[0:0]$8645 - attribute \src "issuer_ls180.v:152907.7-152907.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:153816.3-153828.6" - wire width 2 $0\muxid$1$next[1:0]$8582 - attribute \src "issuer_ls180.v:153739.3-153740.33" - wire width 2 $0\muxid$1[1:0]$8575 - attribute \src "issuer_ls180.v:152938.13-152938.29" - wire width 2 $0\muxid$1[1:0]$8647 - attribute \src "issuer_ls180.v:153869.3-153887.6" - wire width 64 $0\o$18$next[63:0]$8624 - attribute \src "issuer_ls180.v:153703.3-153704.27" - wire width 64 $0\o$18[63:0]$8539 - attribute \src "issuer_ls180.v:152953.14-152953.43" - wire width 64 $0\o$18[63:0]$8649 - attribute \src "issuer_ls180.v:153869.3-153887.6" - wire $0\o_ok$19$next[0:0]$8625 - attribute \src "issuer_ls180.v:153705.3-153706.33" - wire $0\o_ok$19[0:0]$8541 - attribute \src "issuer_ls180.v:152962.7-152962.23" - wire $0\o_ok$19[0:0]$8651 - attribute \src "issuer_ls180.v:153798.3-153815.6" - wire $0\r_busy$next[0:0]$8578 - attribute \src "issuer_ls180.v:153741.3-153742.29" - wire $0\r_busy[0:0] - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire width 12 $0\sr_op__fn_unit$3$next[11:0]$8585 - attribute \src "issuer_ls180.v:153709.3-153710.51" - wire width 12 $0\sr_op__fn_unit$3[11:0]$8545 - attribute \src "issuer_ls180.v:153281.14-153281.42" - wire width 12 $0\sr_op__fn_unit$3[11:0]$8654 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$8586 - attribute \src "issuer_ls180.v:153711.3-153712.65" - wire width 64 $0\sr_op__imm_data__data$4[63:0]$8547 - attribute \src "issuer_ls180.v:153303.14-153303.62" - wire width 64 $0\sr_op__imm_data__data$4[63:0]$8656 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $0\sr_op__imm_data__ok$5$next[0:0]$8587 - attribute \src "issuer_ls180.v:153713.3-153714.61" - wire $0\sr_op__imm_data__ok$5[0:0]$8549 - attribute \src "issuer_ls180.v:153312.7-153312.37" - wire $0\sr_op__imm_data__ok$5[0:0]$8658 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire width 2 $0\sr_op__input_carry$11$next[1:0]$8588 - attribute \src "issuer_ls180.v:153725.3-153726.61" - wire width 2 $0\sr_op__input_carry$11[1:0]$8561 - attribute \src "issuer_ls180.v:153329.13-153329.43" - wire width 2 $0\sr_op__input_carry$11[1:0]$8660 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $0\sr_op__input_cr$13$next[0:0]$8589 - attribute \src "issuer_ls180.v:153729.3-153730.55" - wire $0\sr_op__input_cr$13[0:0]$8565 - attribute \src "issuer_ls180.v:153342.7-153342.34" - wire $0\sr_op__input_cr$13[0:0]$8662 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire width 32 $0\sr_op__insn$17$next[31:0]$8590 - attribute \src "issuer_ls180.v:153737.3-153738.47" - wire width 32 $0\sr_op__insn$17[31:0]$8573 - attribute \src "issuer_ls180.v:153351.14-153351.38" - wire width 32 $0\sr_op__insn$17[31:0]$8664 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire width 7 $0\sr_op__insn_type$2$next[6:0]$8591 - attribute \src "issuer_ls180.v:153707.3-153708.55" - wire width 7 $0\sr_op__insn_type$2[6:0]$8543 - attribute \src "issuer_ls180.v:153508.13-153508.41" - wire width 7 $0\sr_op__insn_type$2[6:0]$8666 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $0\sr_op__is_32bit$15$next[0:0]$8592 - attribute \src "issuer_ls180.v:153733.3-153734.55" - wire $0\sr_op__is_32bit$15[0:0]$8569 - attribute \src "issuer_ls180.v:153591.7-153591.34" - wire $0\sr_op__is_32bit$15[0:0]$8668 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $0\sr_op__is_signed$16$next[0:0]$8593 - attribute \src "issuer_ls180.v:153735.3-153736.57" - wire $0\sr_op__is_signed$16[0:0]$8571 - attribute \src "issuer_ls180.v:153600.7-153600.35" - wire $0\sr_op__is_signed$16[0:0]$8670 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $0\sr_op__oe__oe$8$next[0:0]$8594 - attribute \src "issuer_ls180.v:153719.3-153720.49" - wire $0\sr_op__oe__oe$8[0:0]$8555 - attribute \src "issuer_ls180.v:153611.7-153611.31" - wire $0\sr_op__oe__oe$8[0:0]$8672 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $0\sr_op__oe__ok$9$next[0:0]$8595 - attribute \src "issuer_ls180.v:153721.3-153722.49" - wire $0\sr_op__oe__ok$9[0:0]$8557 - attribute \src "issuer_ls180.v:153620.7-153620.31" - wire $0\sr_op__oe__ok$9[0:0]$8674 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $0\sr_op__output_carry$12$next[0:0]$8596 - attribute \src "issuer_ls180.v:153727.3-153728.63" - wire $0\sr_op__output_carry$12[0:0]$8563 - attribute \src "issuer_ls180.v:153627.7-153627.38" - wire $0\sr_op__output_carry$12[0:0]$8676 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $0\sr_op__output_cr$14$next[0:0]$8597 - attribute \src "issuer_ls180.v:153731.3-153732.57" - wire $0\sr_op__output_cr$14[0:0]$8567 - attribute \src "issuer_ls180.v:153636.7-153636.35" - wire $0\sr_op__output_cr$14[0:0]$8678 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $0\sr_op__rc__ok$7$next[0:0]$8598 - attribute \src "issuer_ls180.v:153717.3-153718.49" - wire $0\sr_op__rc__ok$7[0:0]$8553 - attribute \src "issuer_ls180.v:153647.7-153647.31" - wire $0\sr_op__rc__ok$7[0:0]$8680 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $0\sr_op__rc__rc$6$next[0:0]$8599 - attribute \src "issuer_ls180.v:153715.3-153716.49" - wire $0\sr_op__rc__rc$6[0:0]$8551 - attribute \src "issuer_ls180.v:153656.7-153656.31" - wire $0\sr_op__rc__rc$6[0:0]$8682 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $0\sr_op__write_cr0$10$next[0:0]$8600 - attribute \src "issuer_ls180.v:153723.3-153724.57" - wire $0\sr_op__write_cr0$10[0:0]$8559 - attribute \src "issuer_ls180.v:153663.7-153663.35" - wire $0\sr_op__write_cr0$10[0:0]$8684 - attribute \src "issuer_ls180.v:153907.3-153925.6" - wire width 2 $0\xer_ca$22$next[1:0]$8636 - attribute \src "issuer_ls180.v:153695.3-153696.37" - wire width 2 $0\xer_ca$22[1:0]$8531 - attribute \src "issuer_ls180.v:153672.13-153672.31" - wire width 2 $0\xer_ca$22[1:0]$8686 - attribute \src "issuer_ls180.v:153907.3-153925.6" - wire $0\xer_ca_ok$23$next[0:0]$8637 - attribute \src "issuer_ls180.v:153697.3-153698.43" - wire $0\xer_ca_ok$23[0:0]$8533 - attribute \src "issuer_ls180.v:153681.7-153681.28" - wire $0\xer_ca_ok$23[0:0]$8688 - attribute \src "issuer_ls180.v:153888.3-153906.6" - wire width 4 $1\cr_a$20$next[3:0]$8632 - attribute \src "issuer_ls180.v:153888.3-153906.6" - wire $1\cr_a_ok$21$next[0:0]$8633 - attribute \src "issuer_ls180.v:153816.3-153828.6" - wire width 2 $1\muxid$1$next[1:0]$8583 - attribute \src "issuer_ls180.v:153869.3-153887.6" - wire width 64 $1\o$18$next[63:0]$8626 - attribute \src "issuer_ls180.v:153869.3-153887.6" - wire $1\o_ok$19$next[0:0]$8627 - attribute \src "issuer_ls180.v:153798.3-153815.6" - wire $1\r_busy$next[0:0]$8579 - attribute \src "issuer_ls180.v:153248.7-153248.20" - wire $1\r_busy[0:0] - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire width 12 $1\sr_op__fn_unit$3$next[11:0]$8601 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire width 64 $1\sr_op__imm_data__data$4$next[63:0]$8602 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $1\sr_op__imm_data__ok$5$next[0:0]$8603 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire width 2 $1\sr_op__input_carry$11$next[1:0]$8604 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $1\sr_op__input_cr$13$next[0:0]$8605 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire width 32 $1\sr_op__insn$17$next[31:0]$8606 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire width 7 $1\sr_op__insn_type$2$next[6:0]$8607 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $1\sr_op__is_32bit$15$next[0:0]$8608 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $1\sr_op__is_signed$16$next[0:0]$8609 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $1\sr_op__oe__oe$8$next[0:0]$8610 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $1\sr_op__oe__ok$9$next[0:0]$8611 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $1\sr_op__output_carry$12$next[0:0]$8612 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $1\sr_op__output_cr$14$next[0:0]$8613 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $1\sr_op__rc__ok$7$next[0:0]$8614 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $1\sr_op__rc__rc$6$next[0:0]$8615 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $1\sr_op__write_cr0$10$next[0:0]$8616 - attribute \src "issuer_ls180.v:153907.3-153925.6" - wire width 2 $1\xer_ca$22$next[1:0]$8638 - attribute \src "issuer_ls180.v:153907.3-153925.6" - wire $1\xer_ca_ok$23$next[0:0]$8639 - attribute \src "issuer_ls180.v:153888.3-153906.6" - wire $2\cr_a_ok$21$next[0:0]$8634 - attribute \src "issuer_ls180.v:153869.3-153887.6" - wire $2\o_ok$19$next[0:0]$8628 - attribute \src "issuer_ls180.v:153798.3-153815.6" - wire $2\r_busy$next[0:0]$8580 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire width 64 $2\sr_op__imm_data__data$4$next[63:0]$8617 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $2\sr_op__imm_data__ok$5$next[0:0]$8618 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $2\sr_op__oe__oe$8$next[0:0]$8619 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $2\sr_op__oe__ok$9$next[0:0]$8620 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $2\sr_op__rc__ok$7$next[0:0]$8621 - attribute \src "issuer_ls180.v:153829.3-153868.6" - wire $2\sr_op__rc__rc$6$next[0:0]$8622 - attribute \src "issuer_ls180.v:153907.3-153925.6" - wire $2\xer_ca_ok$23$next[0:0]$8640 - attribute \src "issuer_ls180.v:153694.18-153694.118" - wire $and$issuer_ls180.v:153694$8529_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 54 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 input 23 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 50 \cr_a$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 24 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 51 \cr_a_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$21$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$71 - attribute \src "issuer_ls180.v:152907.7-152907.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 31 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 30 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 29 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 21 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 48 \o$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 22 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 49 \o_ok$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_o$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_o_ok$42 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_sr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_sr_op__fn_unit$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_sr_op__imm_data__data$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__imm_data__ok$28 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_sr_op__input_carry$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__input_cr$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_sr_op__insn$40 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_sr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 46 \sr_op__is_signed$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_signed$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_signed$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__oe$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \sr_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__ok$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \sr_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 42 \sr_op__output_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_carry$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_carry$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 44 \sr_op__output_cr$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_cr$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_cr$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__ok$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \sr_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__rc$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \sr_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \sr_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \sr_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__write_cr0$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__write_cr0$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 27 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 52 \xer_ca$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 28 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 53 \xer_ca_ok$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ca_ok$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ca_ok$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ca_ok$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 25 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 26 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$46 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$issuer_ls180.v:153694$8529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$48 - connect \B \p_ready_o - connect \Y $and$issuer_ls180.v:153694$8529_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:153743.11-153746.4" - cell \n$114 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:153747.16-153793.4" - cell \output$115 \output - connect \cr_a \output_cr_a - connect \cr_a$20 \output_cr_a$43 - connect \cr_a_ok \output_cr_a_ok - connect \muxid \output_muxid - connect \muxid$1 \output_muxid$24 - connect \o \output_o - connect \o$18 \output_o$41 - connect \o_ok \output_o_ok - connect \o_ok$19 \output_o_ok$42 - connect \sr_op__fn_unit \output_sr_op__fn_unit - connect \sr_op__fn_unit$3 \output_sr_op__fn_unit$26 - connect \sr_op__imm_data__data \output_sr_op__imm_data__data - connect \sr_op__imm_data__data$4 \output_sr_op__imm_data__data$27 - connect \sr_op__imm_data__ok \output_sr_op__imm_data__ok - connect \sr_op__imm_data__ok$5 \output_sr_op__imm_data__ok$28 - connect \sr_op__input_carry \output_sr_op__input_carry - connect \sr_op__input_carry$11 \output_sr_op__input_carry$34 - connect \sr_op__input_cr \output_sr_op__input_cr - connect \sr_op__input_cr$13 \output_sr_op__input_cr$36 - connect \sr_op__insn \output_sr_op__insn - connect \sr_op__insn$17 \output_sr_op__insn$40 - connect \sr_op__insn_type \output_sr_op__insn_type - connect \sr_op__insn_type$2 \output_sr_op__insn_type$25 - connect \sr_op__is_32bit \output_sr_op__is_32bit - connect \sr_op__is_32bit$15 \output_sr_op__is_32bit$38 - connect \sr_op__is_signed \output_sr_op__is_signed - connect \sr_op__is_signed$16 \output_sr_op__is_signed$39 - connect \sr_op__oe__oe \output_sr_op__oe__oe - connect \sr_op__oe__oe$8 \output_sr_op__oe__oe$31 - connect \sr_op__oe__ok \output_sr_op__oe__ok - connect \sr_op__oe__ok$9 \output_sr_op__oe__ok$32 - connect \sr_op__output_carry \output_sr_op__output_carry - connect \sr_op__output_carry$12 \output_sr_op__output_carry$35 - connect \sr_op__output_cr \output_sr_op__output_cr - connect \sr_op__output_cr$14 \output_sr_op__output_cr$37 - connect \sr_op__rc__ok \output_sr_op__rc__ok - connect \sr_op__rc__ok$7 \output_sr_op__rc__ok$30 - connect \sr_op__rc__rc \output_sr_op__rc__rc - connect \sr_op__rc__rc$6 \output_sr_op__rc__rc$29 - connect \sr_op__write_cr0 \output_sr_op__write_cr0 - connect \sr_op__write_cr0$10 \output_sr_op__write_cr0$33 - connect \xer_ca \output_xer_ca - connect \xer_ca$21 \output_xer_ca$44 - connect \xer_ca_ok \output_xer_ca_ok - connect \xer_so \output_xer_so - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:153794.11-153797.4" - cell \p$113 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "issuer_ls180.v:152907.7-152907.20" - process $proc$issuer_ls180.v:152907$8641 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:152918.13-152918.29" - process $proc$issuer_ls180.v:152918$8642 - assign { } { } - assign $0\cr_a$20[3:0]$8643 4'0000 - sync always - sync init - update \cr_a$20 $0\cr_a$20[3:0]$8643 - end - attribute \src "issuer_ls180.v:152927.7-152927.26" - process $proc$issuer_ls180.v:152927$8644 - assign { } { } - assign $0\cr_a_ok$21[0:0]$8645 1'0 - sync always - sync init - update \cr_a_ok$21 $0\cr_a_ok$21[0:0]$8645 - end - attribute \src "issuer_ls180.v:152938.13-152938.29" - process $proc$issuer_ls180.v:152938$8646 - assign { } { } - assign $0\muxid$1[1:0]$8647 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$8647 - end - attribute \src "issuer_ls180.v:152953.14-152953.43" - process $proc$issuer_ls180.v:152953$8648 - assign { } { } - assign $0\o$18[63:0]$8649 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o$18 $0\o$18[63:0]$8649 - end - attribute \src "issuer_ls180.v:152962.7-152962.23" - process $proc$issuer_ls180.v:152962$8650 - assign { } { } - assign $0\o_ok$19[0:0]$8651 1'0 - sync always - sync init - update \o_ok$19 $0\o_ok$19[0:0]$8651 - end - attribute \src "issuer_ls180.v:153248.7-153248.20" - process $proc$issuer_ls180.v:153248$8652 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "issuer_ls180.v:153281.14-153281.42" - process $proc$issuer_ls180.v:153281$8653 - assign { } { } - assign $0\sr_op__fn_unit$3[11:0]$8654 12'000000000000 - sync always - sync init - update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[11:0]$8654 - end - attribute \src "issuer_ls180.v:153303.14-153303.62" - process $proc$issuer_ls180.v:153303$8655 - assign { } { } - assign $0\sr_op__imm_data__data$4[63:0]$8656 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$8656 - end - attribute \src "issuer_ls180.v:153312.7-153312.37" - process $proc$issuer_ls180.v:153312$8657 - assign { } { } - assign $0\sr_op__imm_data__ok$5[0:0]$8658 1'0 - sync always - sync init - update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$8658 - end - attribute \src "issuer_ls180.v:153329.13-153329.43" - process $proc$issuer_ls180.v:153329$8659 - assign { } { } - assign $0\sr_op__input_carry$11[1:0]$8660 2'00 - sync always - sync init - update \sr_op__input_carry$11 $0\sr_op__input_carry$11[1:0]$8660 - end - attribute \src "issuer_ls180.v:153342.7-153342.34" - process $proc$issuer_ls180.v:153342$8661 - assign { } { } - assign $0\sr_op__input_cr$13[0:0]$8662 1'0 - sync always - sync init - update \sr_op__input_cr$13 $0\sr_op__input_cr$13[0:0]$8662 - end - attribute \src "issuer_ls180.v:153351.14-153351.38" - process $proc$issuer_ls180.v:153351$8663 - assign { } { } - assign $0\sr_op__insn$17[31:0]$8664 0 - sync always - sync init - update \sr_op__insn$17 $0\sr_op__insn$17[31:0]$8664 - end - attribute \src "issuer_ls180.v:153508.13-153508.41" - process $proc$issuer_ls180.v:153508$8665 - assign { } { } - assign $0\sr_op__insn_type$2[6:0]$8666 7'0000000 - sync always - sync init - update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$8666 - end - attribute \src "issuer_ls180.v:153591.7-153591.34" - process $proc$issuer_ls180.v:153591$8667 - assign { } { } - assign $0\sr_op__is_32bit$15[0:0]$8668 1'0 - sync always - sync init - update \sr_op__is_32bit$15 $0\sr_op__is_32bit$15[0:0]$8668 - end - attribute \src "issuer_ls180.v:153600.7-153600.35" - process $proc$issuer_ls180.v:153600$8669 - assign { } { } - assign $0\sr_op__is_signed$16[0:0]$8670 1'0 - sync always - sync init - update \sr_op__is_signed$16 $0\sr_op__is_signed$16[0:0]$8670 - end - attribute \src "issuer_ls180.v:153611.7-153611.31" - process $proc$issuer_ls180.v:153611$8671 - assign { } { } - assign $0\sr_op__oe__oe$8[0:0]$8672 1'0 - sync always - sync init - update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$8672 - end - attribute \src "issuer_ls180.v:153620.7-153620.31" - process $proc$issuer_ls180.v:153620$8673 - assign { } { } - assign $0\sr_op__oe__ok$9[0:0]$8674 1'0 - sync always - sync init - update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$8674 - end - attribute \src "issuer_ls180.v:153627.7-153627.38" - process $proc$issuer_ls180.v:153627$8675 - assign { } { } - assign $0\sr_op__output_carry$12[0:0]$8676 1'0 - sync always - sync init - update \sr_op__output_carry$12 $0\sr_op__output_carry$12[0:0]$8676 - end - attribute \src "issuer_ls180.v:153636.7-153636.35" - process $proc$issuer_ls180.v:153636$8677 - assign { } { } - assign $0\sr_op__output_cr$14[0:0]$8678 1'0 - sync always - sync init - update \sr_op__output_cr$14 $0\sr_op__output_cr$14[0:0]$8678 - end - attribute \src "issuer_ls180.v:153647.7-153647.31" - process $proc$issuer_ls180.v:153647$8679 - assign { } { } - assign $0\sr_op__rc__ok$7[0:0]$8680 1'0 - sync always - sync init - update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$8680 - end - attribute \src "issuer_ls180.v:153656.7-153656.31" - process $proc$issuer_ls180.v:153656$8681 - assign { } { } - assign $0\sr_op__rc__rc$6[0:0]$8682 1'0 - sync always - sync init - update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$8682 - end - attribute \src "issuer_ls180.v:153663.7-153663.35" - process $proc$issuer_ls180.v:153663$8683 - assign { } { } - assign $0\sr_op__write_cr0$10[0:0]$8684 1'0 - sync always - sync init - update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$8684 - end - attribute \src "issuer_ls180.v:153672.13-153672.31" - process $proc$issuer_ls180.v:153672$8685 - assign { } { } - assign $0\xer_ca$22[1:0]$8686 2'00 - sync always - sync init - update \xer_ca$22 $0\xer_ca$22[1:0]$8686 - end - attribute \src "issuer_ls180.v:153681.7-153681.28" - process $proc$issuer_ls180.v:153681$8687 - assign { } { } - assign $0\xer_ca_ok$23[0:0]$8688 1'0 - sync always - sync init - update \xer_ca_ok$23 $0\xer_ca_ok$23[0:0]$8688 - end - attribute \src "issuer_ls180.v:153695.3-153696.37" - process $proc$issuer_ls180.v:153695$8530 - assign { } { } - assign $0\xer_ca$22[1:0]$8531 \xer_ca$22$next - sync posedge \coresync_clk - update \xer_ca$22 $0\xer_ca$22[1:0]$8531 - end - attribute \src "issuer_ls180.v:153697.3-153698.43" - process $proc$issuer_ls180.v:153697$8532 - assign { } { } - assign $0\xer_ca_ok$23[0:0]$8533 \xer_ca_ok$23$next - sync posedge \coresync_clk - update \xer_ca_ok$23 $0\xer_ca_ok$23[0:0]$8533 - end - attribute \src "issuer_ls180.v:153699.3-153700.33" - process $proc$issuer_ls180.v:153699$8534 - assign { } { } - assign $0\cr_a$20[3:0]$8535 \cr_a$20$next - sync posedge \coresync_clk - update \cr_a$20 $0\cr_a$20[3:0]$8535 - end - attribute \src "issuer_ls180.v:153701.3-153702.39" - process $proc$issuer_ls180.v:153701$8536 - assign { } { } - assign $0\cr_a_ok$21[0:0]$8537 \cr_a_ok$21$next - sync posedge \coresync_clk - update \cr_a_ok$21 $0\cr_a_ok$21[0:0]$8537 - end - attribute \src "issuer_ls180.v:153703.3-153704.27" - process $proc$issuer_ls180.v:153703$8538 - assign { } { } - assign $0\o$18[63:0]$8539 \o$18$next - sync posedge \coresync_clk - update \o$18 $0\o$18[63:0]$8539 - end - attribute \src "issuer_ls180.v:153705.3-153706.33" - process $proc$issuer_ls180.v:153705$8540 - assign { } { } - assign $0\o_ok$19[0:0]$8541 \o_ok$19$next - sync posedge \coresync_clk - update \o_ok$19 $0\o_ok$19[0:0]$8541 - end - attribute \src "issuer_ls180.v:153707.3-153708.55" - process $proc$issuer_ls180.v:153707$8542 - assign { } { } - assign $0\sr_op__insn_type$2[6:0]$8543 \sr_op__insn_type$2$next - sync posedge \coresync_clk - update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$8543 - end - attribute \src "issuer_ls180.v:153709.3-153710.51" - process $proc$issuer_ls180.v:153709$8544 - assign { } { } - assign $0\sr_op__fn_unit$3[11:0]$8545 \sr_op__fn_unit$3$next - sync posedge \coresync_clk - update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[11:0]$8545 - end - attribute \src "issuer_ls180.v:153711.3-153712.65" - process $proc$issuer_ls180.v:153711$8546 - assign { } { } - assign $0\sr_op__imm_data__data$4[63:0]$8547 \sr_op__imm_data__data$4$next - sync posedge \coresync_clk - update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$8547 - end - attribute \src "issuer_ls180.v:153713.3-153714.61" - process $proc$issuer_ls180.v:153713$8548 - assign { } { } - assign $0\sr_op__imm_data__ok$5[0:0]$8549 \sr_op__imm_data__ok$5$next - sync posedge \coresync_clk - update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$8549 - end - attribute \src "issuer_ls180.v:153715.3-153716.49" - process $proc$issuer_ls180.v:153715$8550 - assign { } { } - assign $0\sr_op__rc__rc$6[0:0]$8551 \sr_op__rc__rc$6$next - sync posedge \coresync_clk - update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$8551 - end - attribute \src "issuer_ls180.v:153717.3-153718.49" - process $proc$issuer_ls180.v:153717$8552 - assign { } { } - assign $0\sr_op__rc__ok$7[0:0]$8553 \sr_op__rc__ok$7$next - sync posedge \coresync_clk - update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$8553 - end - attribute \src "issuer_ls180.v:153719.3-153720.49" - process $proc$issuer_ls180.v:153719$8554 - assign { } { } - assign $0\sr_op__oe__oe$8[0:0]$8555 \sr_op__oe__oe$8$next - sync posedge \coresync_clk - update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$8555 - end - attribute \src "issuer_ls180.v:153721.3-153722.49" - process $proc$issuer_ls180.v:153721$8556 - assign { } { } - assign $0\sr_op__oe__ok$9[0:0]$8557 \sr_op__oe__ok$9$next - sync posedge \coresync_clk - update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$8557 - end - attribute \src "issuer_ls180.v:153723.3-153724.57" - process $proc$issuer_ls180.v:153723$8558 - assign { } { } - assign $0\sr_op__write_cr0$10[0:0]$8559 \sr_op__write_cr0$10$next - sync posedge \coresync_clk - update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$8559 - end - attribute \src "issuer_ls180.v:153725.3-153726.61" - process $proc$issuer_ls180.v:153725$8560 - assign { } { } - assign $0\sr_op__input_carry$11[1:0]$8561 \sr_op__input_carry$11$next - sync posedge \coresync_clk - update \sr_op__input_carry$11 $0\sr_op__input_carry$11[1:0]$8561 - end - attribute \src "issuer_ls180.v:153727.3-153728.63" - process $proc$issuer_ls180.v:153727$8562 - assign { } { } - assign $0\sr_op__output_carry$12[0:0]$8563 \sr_op__output_carry$12$next - sync posedge \coresync_clk - update \sr_op__output_carry$12 $0\sr_op__output_carry$12[0:0]$8563 - end - attribute \src "issuer_ls180.v:153729.3-153730.55" - process $proc$issuer_ls180.v:153729$8564 - assign { } { } - assign $0\sr_op__input_cr$13[0:0]$8565 \sr_op__input_cr$13$next - sync posedge \coresync_clk - update \sr_op__input_cr$13 $0\sr_op__input_cr$13[0:0]$8565 - end - attribute \src "issuer_ls180.v:153731.3-153732.57" - process $proc$issuer_ls180.v:153731$8566 - assign { } { } - assign $0\sr_op__output_cr$14[0:0]$8567 \sr_op__output_cr$14$next - sync posedge \coresync_clk - update \sr_op__output_cr$14 $0\sr_op__output_cr$14[0:0]$8567 - end - attribute \src "issuer_ls180.v:153733.3-153734.55" - process $proc$issuer_ls180.v:153733$8568 - assign { } { } - assign $0\sr_op__is_32bit$15[0:0]$8569 \sr_op__is_32bit$15$next - sync posedge \coresync_clk - update \sr_op__is_32bit$15 $0\sr_op__is_32bit$15[0:0]$8569 - end - attribute \src "issuer_ls180.v:153735.3-153736.57" - process $proc$issuer_ls180.v:153735$8570 - assign { } { } - assign $0\sr_op__is_signed$16[0:0]$8571 \sr_op__is_signed$16$next - sync posedge \coresync_clk - update \sr_op__is_signed$16 $0\sr_op__is_signed$16[0:0]$8571 - end - attribute \src "issuer_ls180.v:153737.3-153738.47" - process $proc$issuer_ls180.v:153737$8572 - assign { } { } - assign $0\sr_op__insn$17[31:0]$8573 \sr_op__insn$17$next - sync posedge \coresync_clk - update \sr_op__insn$17 $0\sr_op__insn$17[31:0]$8573 - end - attribute \src "issuer_ls180.v:153739.3-153740.33" - process $proc$issuer_ls180.v:153739$8574 - assign { } { } - assign $0\muxid$1[1:0]$8575 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8575 - end - attribute \src "issuer_ls180.v:153741.3-153742.29" - process $proc$issuer_ls180.v:153741$8576 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "issuer_ls180.v:153798.3-153815.6" - process $proc$issuer_ls180.v:153798$8577 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$8578 $2\r_busy$next[0:0]$8580 - attribute \src "issuer_ls180.v:153799.5-153799.29" - switch \initial - attribute \src "issuer_ls180.v:153799.9-153799.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$8579 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\r_busy$next[0:0]$8579 1'0 - case - assign $1\r_busy$next[0:0]$8579 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$8580 1'0 - case - assign $2\r_busy$next[0:0]$8580 $1\r_busy$next[0:0]$8579 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$8578 - end - attribute \src "issuer_ls180.v:153816.3-153828.6" - process $proc$issuer_ls180.v:153816$8581 - assign { } { } - assign { } { } - assign $0\muxid$1$next[1:0]$8582 $1\muxid$1$next[1:0]$8583 - attribute \src "issuer_ls180.v:153817.5-153817.29" - switch \initial - attribute \src "issuer_ls180.v:153817.9-153817.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$1$next[1:0]$8583 \muxid$51 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$1$next[1:0]$8583 \muxid$51 - case - assign $1\muxid$1$next[1:0]$8583 \muxid$1 - end - sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8582 - end - attribute \src "issuer_ls180.v:153829.3-153868.6" - process $proc$issuer_ls180.v:153829$8584 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\sr_op__fn_unit$3$next[11:0]$8585 $1\sr_op__fn_unit$3$next[11:0]$8601 - assign { } { } - assign { } { } - assign $0\sr_op__input_carry$11$next[1:0]$8588 $1\sr_op__input_carry$11$next[1:0]$8604 - assign $0\sr_op__input_cr$13$next[0:0]$8589 $1\sr_op__input_cr$13$next[0:0]$8605 - assign $0\sr_op__insn$17$next[31:0]$8590 $1\sr_op__insn$17$next[31:0]$8606 - assign $0\sr_op__insn_type$2$next[6:0]$8591 $1\sr_op__insn_type$2$next[6:0]$8607 - assign $0\sr_op__is_32bit$15$next[0:0]$8592 $1\sr_op__is_32bit$15$next[0:0]$8608 - assign $0\sr_op__is_signed$16$next[0:0]$8593 $1\sr_op__is_signed$16$next[0:0]$8609 - assign { } { } - assign { } { } - assign $0\sr_op__output_carry$12$next[0:0]$8596 $1\sr_op__output_carry$12$next[0:0]$8612 - assign $0\sr_op__output_cr$14$next[0:0]$8597 $1\sr_op__output_cr$14$next[0:0]$8613 - assign { } { } - assign { } { } - assign $0\sr_op__write_cr0$10$next[0:0]$8600 $1\sr_op__write_cr0$10$next[0:0]$8616 - assign $0\sr_op__imm_data__data$4$next[63:0]$8586 $2\sr_op__imm_data__data$4$next[63:0]$8617 - assign $0\sr_op__imm_data__ok$5$next[0:0]$8587 $2\sr_op__imm_data__ok$5$next[0:0]$8618 - assign $0\sr_op__oe__oe$8$next[0:0]$8594 $2\sr_op__oe__oe$8$next[0:0]$8619 - assign $0\sr_op__oe__ok$9$next[0:0]$8595 $2\sr_op__oe__ok$9$next[0:0]$8620 - assign $0\sr_op__rc__ok$7$next[0:0]$8598 $2\sr_op__rc__ok$7$next[0:0]$8621 - assign $0\sr_op__rc__rc$6$next[0:0]$8599 $2\sr_op__rc__rc$6$next[0:0]$8622 - attribute \src "issuer_ls180.v:153830.5-153830.29" - switch \initial - attribute \src "issuer_ls180.v:153830.9-153830.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\sr_op__insn$17$next[31:0]$8606 $1\sr_op__is_signed$16$next[0:0]$8609 $1\sr_op__is_32bit$15$next[0:0]$8608 $1\sr_op__output_cr$14$next[0:0]$8613 $1\sr_op__input_cr$13$next[0:0]$8605 $1\sr_op__output_carry$12$next[0:0]$8612 $1\sr_op__input_carry$11$next[1:0]$8604 $1\sr_op__write_cr0$10$next[0:0]$8616 $1\sr_op__oe__ok$9$next[0:0]$8611 $1\sr_op__oe__oe$8$next[0:0]$8610 $1\sr_op__rc__ok$7$next[0:0]$8614 $1\sr_op__rc__rc$6$next[0:0]$8615 $1\sr_op__imm_data__ok$5$next[0:0]$8603 $1\sr_op__imm_data__data$4$next[63:0]$8602 $1\sr_op__fn_unit$3$next[11:0]$8601 $1\sr_op__insn_type$2$next[6:0]$8607 } { \sr_op__insn$67 \sr_op__is_signed$66 \sr_op__is_32bit$65 \sr_op__output_cr$64 \sr_op__input_cr$63 \sr_op__output_carry$62 \sr_op__input_carry$61 \sr_op__write_cr0$60 \sr_op__oe__ok$59 \sr_op__oe__oe$58 \sr_op__rc__ok$57 \sr_op__rc__rc$56 \sr_op__imm_data__ok$55 \sr_op__imm_data__data$54 \sr_op__fn_unit$53 \sr_op__insn_type$52 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\sr_op__insn$17$next[31:0]$8606 $1\sr_op__is_signed$16$next[0:0]$8609 $1\sr_op__is_32bit$15$next[0:0]$8608 $1\sr_op__output_cr$14$next[0:0]$8613 $1\sr_op__input_cr$13$next[0:0]$8605 $1\sr_op__output_carry$12$next[0:0]$8612 $1\sr_op__input_carry$11$next[1:0]$8604 $1\sr_op__write_cr0$10$next[0:0]$8616 $1\sr_op__oe__ok$9$next[0:0]$8611 $1\sr_op__oe__oe$8$next[0:0]$8610 $1\sr_op__rc__ok$7$next[0:0]$8614 $1\sr_op__rc__rc$6$next[0:0]$8615 $1\sr_op__imm_data__ok$5$next[0:0]$8603 $1\sr_op__imm_data__data$4$next[63:0]$8602 $1\sr_op__fn_unit$3$next[11:0]$8601 $1\sr_op__insn_type$2$next[6:0]$8607 } { \sr_op__insn$67 \sr_op__is_signed$66 \sr_op__is_32bit$65 \sr_op__output_cr$64 \sr_op__input_cr$63 \sr_op__output_carry$62 \sr_op__input_carry$61 \sr_op__write_cr0$60 \sr_op__oe__ok$59 \sr_op__oe__oe$58 \sr_op__rc__ok$57 \sr_op__rc__rc$56 \sr_op__imm_data__ok$55 \sr_op__imm_data__data$54 \sr_op__fn_unit$53 \sr_op__insn_type$52 } - case - assign $1\sr_op__fn_unit$3$next[11:0]$8601 \sr_op__fn_unit$3 - assign $1\sr_op__imm_data__data$4$next[63:0]$8602 \sr_op__imm_data__data$4 - assign $1\sr_op__imm_data__ok$5$next[0:0]$8603 \sr_op__imm_data__ok$5 - assign $1\sr_op__input_carry$11$next[1:0]$8604 \sr_op__input_carry$11 - assign $1\sr_op__input_cr$13$next[0:0]$8605 \sr_op__input_cr$13 - assign $1\sr_op__insn$17$next[31:0]$8606 \sr_op__insn$17 - assign $1\sr_op__insn_type$2$next[6:0]$8607 \sr_op__insn_type$2 - assign $1\sr_op__is_32bit$15$next[0:0]$8608 \sr_op__is_32bit$15 - assign $1\sr_op__is_signed$16$next[0:0]$8609 \sr_op__is_signed$16 - assign $1\sr_op__oe__oe$8$next[0:0]$8610 \sr_op__oe__oe$8 - assign $1\sr_op__oe__ok$9$next[0:0]$8611 \sr_op__oe__ok$9 - assign $1\sr_op__output_carry$12$next[0:0]$8612 \sr_op__output_carry$12 - assign $1\sr_op__output_cr$14$next[0:0]$8613 \sr_op__output_cr$14 - assign $1\sr_op__rc__ok$7$next[0:0]$8614 \sr_op__rc__ok$7 - assign $1\sr_op__rc__rc$6$next[0:0]$8615 \sr_op__rc__rc$6 - assign $1\sr_op__write_cr0$10$next[0:0]$8616 \sr_op__write_cr0$10 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\sr_op__imm_data__data$4$next[63:0]$8617 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\sr_op__imm_data__ok$5$next[0:0]$8618 1'0 - assign $2\sr_op__rc__rc$6$next[0:0]$8622 1'0 - assign $2\sr_op__rc__ok$7$next[0:0]$8621 1'0 - assign $2\sr_op__oe__oe$8$next[0:0]$8619 1'0 - assign $2\sr_op__oe__ok$9$next[0:0]$8620 1'0 - case - assign $2\sr_op__imm_data__data$4$next[63:0]$8617 $1\sr_op__imm_data__data$4$next[63:0]$8602 - assign $2\sr_op__imm_data__ok$5$next[0:0]$8618 $1\sr_op__imm_data__ok$5$next[0:0]$8603 - assign $2\sr_op__oe__oe$8$next[0:0]$8619 $1\sr_op__oe__oe$8$next[0:0]$8610 - assign $2\sr_op__oe__ok$9$next[0:0]$8620 $1\sr_op__oe__ok$9$next[0:0]$8611 - assign $2\sr_op__rc__ok$7$next[0:0]$8621 $1\sr_op__rc__ok$7$next[0:0]$8614 - assign $2\sr_op__rc__rc$6$next[0:0]$8622 $1\sr_op__rc__rc$6$next[0:0]$8615 - end - sync always - update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[11:0]$8585 - update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$8586 - update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$8587 - update \sr_op__input_carry$11$next $0\sr_op__input_carry$11$next[1:0]$8588 - update \sr_op__input_cr$13$next $0\sr_op__input_cr$13$next[0:0]$8589 - update \sr_op__insn$17$next $0\sr_op__insn$17$next[31:0]$8590 - update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$8591 - update \sr_op__is_32bit$15$next $0\sr_op__is_32bit$15$next[0:0]$8592 - update \sr_op__is_signed$16$next $0\sr_op__is_signed$16$next[0:0]$8593 - update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$8594 - update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$8595 - update \sr_op__output_carry$12$next $0\sr_op__output_carry$12$next[0:0]$8596 - update \sr_op__output_cr$14$next $0\sr_op__output_cr$14$next[0:0]$8597 - update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$8598 - update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$8599 - update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$8600 - end - attribute \src "issuer_ls180.v:153869.3-153887.6" - process $proc$issuer_ls180.v:153869$8623 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$18$next[63:0]$8624 $1\o$18$next[63:0]$8626 - assign { } { } - assign $0\o_ok$19$next[0:0]$8625 $2\o_ok$19$next[0:0]$8628 - attribute \src "issuer_ls180.v:153870.5-153870.29" - switch \initial - attribute \src "issuer_ls180.v:153870.9-153870.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$19$next[0:0]$8627 $1\o$18$next[63:0]$8626 } { \o_ok$69 \o$68 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\o_ok$19$next[0:0]$8627 $1\o$18$next[63:0]$8626 } { \o_ok$69 \o$68 } - case - assign $1\o$18$next[63:0]$8626 \o$18 - assign $1\o_ok$19$next[0:0]$8627 \o_ok$19 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o_ok$19$next[0:0]$8628 1'0 - case - assign $2\o_ok$19$next[0:0]$8628 $1\o_ok$19$next[0:0]$8627 - end - sync always - update \o$18$next $0\o$18$next[63:0]$8624 - update \o_ok$19$next $0\o_ok$19$next[0:0]$8625 - end - attribute \src "issuer_ls180.v:153888.3-153906.6" - process $proc$issuer_ls180.v:153888$8629 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$20$next[3:0]$8630 $1\cr_a$20$next[3:0]$8632 - assign { } { } - assign $0\cr_a_ok$21$next[0:0]$8631 $2\cr_a_ok$21$next[0:0]$8634 - attribute \src "issuer_ls180.v:153889.5-153889.29" - switch \initial - attribute \src "issuer_ls180.v:153889.9-153889.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\cr_a_ok$21$next[0:0]$8633 $1\cr_a$20$next[3:0]$8632 } { \cr_a_ok$71 \cr_a$70 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\cr_a_ok$21$next[0:0]$8633 $1\cr_a$20$next[3:0]$8632 } { \cr_a_ok$71 \cr_a$70 } - case - assign $1\cr_a$20$next[3:0]$8632 \cr_a$20 - assign $1\cr_a_ok$21$next[0:0]$8633 \cr_a_ok$21 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_a_ok$21$next[0:0]$8634 1'0 - case - assign $2\cr_a_ok$21$next[0:0]$8634 $1\cr_a_ok$21$next[0:0]$8633 - end - sync always - update \cr_a$20$next $0\cr_a$20$next[3:0]$8630 - update \cr_a_ok$21$next $0\cr_a_ok$21$next[0:0]$8631 - end - attribute \src "issuer_ls180.v:153907.3-153925.6" - process $proc$issuer_ls180.v:153907$8635 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_ca$22$next[1:0]$8636 $1\xer_ca$22$next[1:0]$8638 - assign { } { } - assign $0\xer_ca_ok$23$next[0:0]$8637 $2\xer_ca_ok$23$next[0:0]$8640 - attribute \src "issuer_ls180.v:153908.5-153908.29" - switch \initial - attribute \src "issuer_ls180.v:153908.9-153908.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_ca_ok$23$next[0:0]$8639 $1\xer_ca$22$next[1:0]$8638 } { \xer_ca_ok$73 \xer_ca$72 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_ca_ok$23$next[0:0]$8639 $1\xer_ca$22$next[1:0]$8638 } { \xer_ca_ok$73 \xer_ca$72 } - case - assign $1\xer_ca$22$next[1:0]$8638 \xer_ca$22 - assign $1\xer_ca_ok$23$next[0:0]$8639 \xer_ca_ok$23 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_ca_ok$23$next[0:0]$8640 1'0 - case - assign $2\xer_ca_ok$23$next[0:0]$8640 $1\xer_ca_ok$23$next[0:0]$8639 - end - sync always - update \xer_ca$22$next $0\xer_ca$22$next[1:0]$8636 - update \xer_ca_ok$23$next $0\xer_ca_ok$23$next[0:0]$8637 - end - connect \$49 $and$issuer_ls180.v:153694$8529_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \xer_ca_ok$73 \xer_ca$72 } { \output_xer_ca_ok \output_xer_ca$44 } - connect { \cr_a_ok$71 \cr_a$70 } { \output_cr_a_ok \output_cr_a$43 } - connect { \o_ok$69 \o$68 } { \output_o_ok$42 \output_o$41 } - connect { \sr_op__insn$67 \sr_op__is_signed$66 \sr_op__is_32bit$65 \sr_op__output_cr$64 \sr_op__input_cr$63 \sr_op__output_carry$62 \sr_op__input_carry$61 \sr_op__write_cr0$60 \sr_op__oe__ok$59 \sr_op__oe__oe$58 \sr_op__rc__ok$57 \sr_op__rc__rc$56 \sr_op__imm_data__ok$55 \sr_op__imm_data__data$54 \sr_op__fn_unit$53 \sr_op__insn_type$52 } { \output_sr_op__insn$40 \output_sr_op__is_signed$39 \output_sr_op__is_32bit$38 \output_sr_op__output_cr$37 \output_sr_op__input_cr$36 \output_sr_op__output_carry$35 \output_sr_op__input_carry$34 \output_sr_op__write_cr0$33 \output_sr_op__oe__ok$32 \output_sr_op__oe__oe$31 \output_sr_op__rc__ok$30 \output_sr_op__rc__rc$29 \output_sr_op__imm_data__ok$28 \output_sr_op__imm_data__data$27 \output_sr_op__fn_unit$26 \output_sr_op__insn_type$25 } - connect \muxid$51 \output_muxid$24 - connect \p_valid_i_p_ready_o \$49 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$48 \p_valid_i - connect { \xer_ca_ok$47 \output_xer_ca } { \xer_ca_ok \xer_ca } - connect { \xer_so_ok$46 \output_xer_so } { \xer_so_ok \xer_so } - connect { \cr_a_ok$45 \output_cr_a } { \cr_a_ok \cr_a } - connect { \output_o_ok \output_o } { \o_ok \o } - connect { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry \output_sr_op__write_cr0 \output_sr_op__oe__ok \output_sr_op__oe__oe \output_sr_op__rc__ok \output_sr_op__rc__rc \output_sr_op__imm_data__ok \output_sr_op__imm_data__data \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } - connect \output_muxid \muxid -end -attribute \src "issuer_ls180.v:153946.1-155428.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end" -attribute \generator "nMigen" -module \pipe_end - attribute \src "issuer_ls180.v:155266.3-155284.6" - wire width 4 $0\cr_a$next[3:0]$8745 - attribute \src "issuer_ls180.v:155085.3-155086.25" - wire width 4 $0\cr_a[3:0] - attribute \src "issuer_ls180.v:155266.3-155284.6" - wire $0\cr_a_ok$next[0:0]$8746 - attribute \src "issuer_ls180.v:155087.3-155088.31" - wire $0\cr_a_ok[0:0] - attribute \src "issuer_ls180.v:153947.7-153947.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire width 4 $0\logical_op__data_len$18$next[3:0]$8770 - attribute \src "issuer_ls180.v:155125.3-155126.65" - wire width 4 $0\logical_op__data_len$18[3:0]$8732 - attribute \src "issuer_ls180.v:153988.13-153988.45" - wire width 4 $0\logical_op__data_len$18[3:0]$8816 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire width 12 $0\logical_op__fn_unit$3$next[11:0]$8771 - attribute \src "issuer_ls180.v:155095.3-155096.61" - wire width 12 $0\logical_op__fn_unit$3[11:0]$8702 - attribute \src "issuer_ls180.v:154023.14-154023.47" - wire width 12 $0\logical_op__fn_unit$3[11:0]$8818 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$8772 - attribute \src "issuer_ls180.v:155097.3-155098.75" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$8704 - attribute \src "issuer_ls180.v:154045.14-154045.67" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$8820 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $0\logical_op__imm_data__ok$5$next[0:0]$8773 - attribute \src "issuer_ls180.v:155099.3-155100.71" - wire $0\logical_op__imm_data__ok$5[0:0]$8706 - attribute \src "issuer_ls180.v:154054.7-154054.42" - wire $0\logical_op__imm_data__ok$5[0:0]$8822 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire width 2 $0\logical_op__input_carry$12$next[1:0]$8774 - attribute \src "issuer_ls180.v:155113.3-155114.71" - wire width 2 $0\logical_op__input_carry$12[1:0]$8720 - attribute \src "issuer_ls180.v:154071.13-154071.48" - wire width 2 $0\logical_op__input_carry$12[1:0]$8824 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire width 32 $0\logical_op__insn$19$next[31:0]$8775 - attribute \src "issuer_ls180.v:155127.3-155128.57" - wire width 32 $0\logical_op__insn$19[31:0]$8734 - attribute \src "issuer_ls180.v:154084.14-154084.43" - wire width 32 $0\logical_op__insn$19[31:0]$8826 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire width 7 $0\logical_op__insn_type$2$next[6:0]$8776 - attribute \src "issuer_ls180.v:155093.3-155094.65" - wire width 7 $0\logical_op__insn_type$2[6:0]$8700 - attribute \src "issuer_ls180.v:154241.13-154241.46" - wire width 7 $0\logical_op__insn_type$2[6:0]$8828 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $0\logical_op__invert_in$10$next[0:0]$8777 - attribute \src "issuer_ls180.v:155109.3-155110.67" - wire $0\logical_op__invert_in$10[0:0]$8716 - attribute \src "issuer_ls180.v:154324.7-154324.40" - wire $0\logical_op__invert_in$10[0:0]$8830 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $0\logical_op__invert_out$13$next[0:0]$8778 - attribute \src "issuer_ls180.v:155115.3-155116.69" - wire $0\logical_op__invert_out$13[0:0]$8722 - attribute \src "issuer_ls180.v:154333.7-154333.41" - wire $0\logical_op__invert_out$13[0:0]$8832 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $0\logical_op__is_32bit$16$next[0:0]$8779 - attribute \src "issuer_ls180.v:155121.3-155122.65" - wire $0\logical_op__is_32bit$16[0:0]$8728 - attribute \src "issuer_ls180.v:154342.7-154342.39" - wire $0\logical_op__is_32bit$16[0:0]$8834 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $0\logical_op__is_signed$17$next[0:0]$8780 - attribute \src "issuer_ls180.v:155123.3-155124.67" - wire $0\logical_op__is_signed$17[0:0]$8730 - attribute \src "issuer_ls180.v:154351.7-154351.40" - wire $0\logical_op__is_signed$17[0:0]$8836 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $0\logical_op__oe__oe$8$next[0:0]$8781 - attribute \src "issuer_ls180.v:155105.3-155106.59" - wire $0\logical_op__oe__oe$8[0:0]$8712 - attribute \src "issuer_ls180.v:154360.7-154360.36" - wire $0\logical_op__oe__oe$8[0:0]$8838 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $0\logical_op__oe__ok$9$next[0:0]$8782 - attribute \src "issuer_ls180.v:155107.3-155108.59" - wire $0\logical_op__oe__ok$9[0:0]$8714 - attribute \src "issuer_ls180.v:154371.7-154371.36" - wire $0\logical_op__oe__ok$9[0:0]$8840 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $0\logical_op__output_carry$15$next[0:0]$8783 - attribute \src "issuer_ls180.v:155119.3-155120.73" - wire $0\logical_op__output_carry$15[0:0]$8726 - attribute \src "issuer_ls180.v:154378.7-154378.43" - wire $0\logical_op__output_carry$15[0:0]$8842 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $0\logical_op__rc__ok$7$next[0:0]$8784 - attribute \src "issuer_ls180.v:155103.3-155104.59" - wire $0\logical_op__rc__ok$7[0:0]$8710 - attribute \src "issuer_ls180.v:154387.7-154387.36" - wire $0\logical_op__rc__ok$7[0:0]$8844 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $0\logical_op__rc__rc$6$next[0:0]$8785 - attribute \src "issuer_ls180.v:155101.3-155102.59" - wire $0\logical_op__rc__rc$6[0:0]$8708 - attribute \src "issuer_ls180.v:154396.7-154396.36" - wire $0\logical_op__rc__rc$6[0:0]$8846 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $0\logical_op__write_cr0$14$next[0:0]$8786 - attribute \src "issuer_ls180.v:155117.3-155118.67" - wire $0\logical_op__write_cr0$14[0:0]$8724 - attribute \src "issuer_ls180.v:154405.7-154405.40" - wire $0\logical_op__write_cr0$14[0:0]$8848 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $0\logical_op__zero_a$11$next[0:0]$8787 - attribute \src "issuer_ls180.v:155111.3-155112.61" - wire $0\logical_op__zero_a$11[0:0]$8718 - attribute \src "issuer_ls180.v:154414.7-154414.37" - wire $0\logical_op__zero_a$11[0:0]$8850 - attribute \src "issuer_ls180.v:155341.3-155353.6" - wire width 2 $0\muxid$1$next[1:0]$8767 - attribute \src "issuer_ls180.v:155129.3-155130.33" - wire width 2 $0\muxid$1[1:0]$8736 - attribute \src "issuer_ls180.v:154423.13-154423.29" - wire width 2 $0\muxid$1[1:0]$8852 - attribute \src "issuer_ls180.v:155247.3-155265.6" - wire width 64 $0\o$next[63:0]$8739 - attribute \src "issuer_ls180.v:155089.3-155090.19" - wire width 64 $0\o[63:0] - attribute \src "issuer_ls180.v:155247.3-155265.6" - wire $0\o_ok$next[0:0]$8740 - attribute \src "issuer_ls180.v:155091.3-155092.25" - wire $0\o_ok[0:0] - attribute \src "issuer_ls180.v:155323.3-155340.6" - wire $0\r_busy$next[0:0]$8763 - attribute \src "issuer_ls180.v:155131.3-155132.29" - wire $0\r_busy[0:0] - attribute \src "issuer_ls180.v:155285.3-155303.6" - wire width 2 $0\xer_ov$next[1:0]$8751 - attribute \src "issuer_ls180.v:155081.3-155082.29" - wire width 2 $0\xer_ov[1:0] - attribute \src "issuer_ls180.v:155285.3-155303.6" - wire $0\xer_ov_ok$next[0:0]$8752 - attribute \src "issuer_ls180.v:155083.3-155084.35" - wire $0\xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:155304.3-155322.6" - wire $0\xer_so$20$next[0:0]$8758 - attribute \src "issuer_ls180.v:155077.3-155078.37" - wire $0\xer_so$20[0:0]$8691 - attribute \src "issuer_ls180.v:155062.7-155062.25" - wire $0\xer_so$20[0:0]$8859 - attribute \src "issuer_ls180.v:155304.3-155322.6" - wire $0\xer_so_ok$next[0:0]$8757 - attribute \src "issuer_ls180.v:155079.3-155080.35" - wire $0\xer_so_ok[0:0] - attribute \src "issuer_ls180.v:155266.3-155284.6" - wire width 4 $1\cr_a$next[3:0]$8747 - attribute \src "issuer_ls180.v:153956.13-153956.24" - wire width 4 $1\cr_a[3:0] - attribute \src "issuer_ls180.v:155266.3-155284.6" - wire $1\cr_a_ok$next[0:0]$8748 - attribute \src "issuer_ls180.v:153965.7-153965.21" - wire $1\cr_a_ok[0:0] - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire width 4 $1\logical_op__data_len$18$next[3:0]$8788 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire width 12 $1\logical_op__fn_unit$3$next[11:0]$8789 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$8790 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $1\logical_op__imm_data__ok$5$next[0:0]$8791 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire width 2 $1\logical_op__input_carry$12$next[1:0]$8792 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire width 32 $1\logical_op__insn$19$next[31:0]$8793 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire width 7 $1\logical_op__insn_type$2$next[6:0]$8794 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $1\logical_op__invert_in$10$next[0:0]$8795 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $1\logical_op__invert_out$13$next[0:0]$8796 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $1\logical_op__is_32bit$16$next[0:0]$8797 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $1\logical_op__is_signed$17$next[0:0]$8798 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $1\logical_op__oe__oe$8$next[0:0]$8799 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $1\logical_op__oe__ok$9$next[0:0]$8800 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $1\logical_op__output_carry$15$next[0:0]$8801 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $1\logical_op__rc__ok$7$next[0:0]$8802 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $1\logical_op__rc__rc$6$next[0:0]$8803 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $1\logical_op__write_cr0$14$next[0:0]$8804 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $1\logical_op__zero_a$11$next[0:0]$8805 - attribute \src "issuer_ls180.v:155341.3-155353.6" - wire width 2 $1\muxid$1$next[1:0]$8768 - attribute \src "issuer_ls180.v:155247.3-155265.6" - wire width 64 $1\o$next[63:0]$8741 - attribute \src "issuer_ls180.v:154436.14-154436.38" - wire width 64 $1\o[63:0] - attribute \src "issuer_ls180.v:155247.3-155265.6" - wire $1\o_ok$next[0:0]$8742 - attribute \src "issuer_ls180.v:154443.7-154443.18" - wire $1\o_ok[0:0] - attribute \src "issuer_ls180.v:155323.3-155340.6" - wire $1\r_busy$next[0:0]$8764 - attribute \src "issuer_ls180.v:155027.7-155027.20" - wire $1\r_busy[0:0] - attribute \src "issuer_ls180.v:155285.3-155303.6" - wire width 2 $1\xer_ov$next[1:0]$8753 - attribute \src "issuer_ls180.v:155042.13-155042.26" - wire width 2 $1\xer_ov[1:0] - attribute \src "issuer_ls180.v:155285.3-155303.6" - wire $1\xer_ov_ok$next[0:0]$8754 - attribute \src "issuer_ls180.v:155049.7-155049.23" - wire $1\xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:155304.3-155322.6" - wire $1\xer_so$20$next[0:0]$8760 - attribute \src "issuer_ls180.v:155304.3-155322.6" - wire $1\xer_so_ok$next[0:0]$8759 - attribute \src "issuer_ls180.v:155067.7-155067.23" - wire $1\xer_so_ok[0:0] - attribute \src "issuer_ls180.v:155266.3-155284.6" - wire $2\cr_a_ok$next[0:0]$8749 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$8806 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $2\logical_op__imm_data__ok$5$next[0:0]$8807 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $2\logical_op__oe__oe$8$next[0:0]$8808 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $2\logical_op__oe__ok$9$next[0:0]$8809 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $2\logical_op__rc__ok$7$next[0:0]$8810 - attribute \src "issuer_ls180.v:155354.3-155395.6" - wire $2\logical_op__rc__rc$6$next[0:0]$8811 - attribute \src "issuer_ls180.v:155247.3-155265.6" - wire $2\o_ok$next[0:0]$8743 - attribute \src "issuer_ls180.v:155323.3-155340.6" - wire $2\r_busy$next[0:0]$8765 - attribute \src "issuer_ls180.v:155285.3-155303.6" - wire $2\xer_ov_ok$next[0:0]$8755 - attribute \src "issuer_ls180.v:155304.3-155322.6" - wire $2\xer_so_ok$next[0:0]$8761 - attribute \src "issuer_ls180.v:155076.18-155076.118" - wire $and$issuer_ls180.v:155076$8689_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 62 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 56 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 57 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire input 30 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire input 28 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire input 29 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire input 27 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire input 26 \divisor_neg - attribute \src "issuer_ls180.v:153947.7-153947.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 52 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$93 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 37 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$3$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 38 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \logical_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$80 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 46 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$12$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 53 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$94 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 36 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$2$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 44 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 47 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 50 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 51 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 42 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 43 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 49 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 41 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 48 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 45 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$86 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 35 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$76 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 34 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 33 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 54 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 55 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_logical_op__data_len$58 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_logical_op__fn_unit$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_logical_op__imm_data__data$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__imm_data__ok$45 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_logical_op__input_carry$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_logical_op__insn$59 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_logical_op__insn_type$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__invert_in$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__invert_out$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__is_32bit$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__is_signed$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__oe__oe$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__oe__ok$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__output_carry$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__ok$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__rc$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__write_cr0$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__zero_a$51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_o$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_o_ok$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire \output_stage_div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire \output_stage_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire \output_stage_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \output_stage_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \output_stage_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_stage_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_stage_logical_op__data_len$38 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_stage_logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_stage_logical_op__fn_unit$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_stage_logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_stage_logical_op__imm_data__data$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__imm_data__ok$25 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_stage_logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_stage_logical_op__input_carry$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_stage_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_stage_logical_op__insn$39 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_stage_logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_stage_logical_op__insn_type$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__invert_in$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__invert_out$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__is_32bit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__is_signed$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__oe__oe$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__oe__ok$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__output_carry$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__rc__ok$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__rc__rc$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__write_cr0$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__zero_a$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_stage_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_stage_muxid$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_stage_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_stage_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 64 \output_stage_quotient_root - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" - wire width 192 \output_stage_remainder - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_stage_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_stage_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \output_stage_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_stage_xer_so$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ov$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_xer_so$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$73 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 64 input 31 \quotient_root - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 23 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 25 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 60 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 61 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$next - attribute \src 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\logical_op__is_32bit$16 \output_logical_op__is_32bit$56 - connect \logical_op__is_signed \output_logical_op__is_signed - connect \logical_op__is_signed$17 \output_logical_op__is_signed$57 - connect \logical_op__oe__oe \output_logical_op__oe__oe - connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$48 - connect \logical_op__oe__ok \output_logical_op__oe__ok - connect \logical_op__oe__ok$9 \output_logical_op__oe__ok$49 - connect \logical_op__output_carry \output_logical_op__output_carry - connect \logical_op__output_carry$15 \output_logical_op__output_carry$55 - connect \logical_op__rc__ok \output_logical_op__rc__ok - connect \logical_op__rc__ok$7 \output_logical_op__rc__ok$47 - connect \logical_op__rc__rc \output_logical_op__rc__rc - connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$46 - connect \logical_op__write_cr0 \output_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$54 - connect \logical_op__zero_a \output_logical_op__zero_a - connect \logical_op__zero_a$11 \output_logical_op__zero_a$51 - connect \muxid \output_muxid - connect \muxid$1 \output_muxid$41 - connect \o \output_o - connect \o$20 \output_o$60 - connect \o_ok \output_o_ok - connect \o_ok$21 \output_o_ok$61 - connect \xer_ov \output_xer_ov - connect \xer_ov$23 \output_xer_ov$63 - connect \xer_ov_ok \output_xer_ov_ok - connect \xer_so \output_xer_so - connect \xer_so$24 \output_xer_so$64 - connect \xer_so_ok \output_xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:155190.16-155242.4" - cell \output_stage \output_stage - connect \div_by_zero \output_stage_div_by_zero - connect \dive_abs_ov32 \output_stage_dive_abs_ov32 - connect \dive_abs_ov64 \output_stage_dive_abs_ov64 - connect \dividend_neg \output_stage_dividend_neg - connect \divisor_neg \output_stage_divisor_neg - connect \logical_op__data_len \output_stage_logical_op__data_len - connect \logical_op__data_len$18 \output_stage_logical_op__data_len$38 - connect \logical_op__fn_unit \output_stage_logical_op__fn_unit - connect \logical_op__fn_unit$3 \output_stage_logical_op__fn_unit$23 - connect \logical_op__imm_data__data \output_stage_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \output_stage_logical_op__imm_data__data$24 - connect \logical_op__imm_data__ok \output_stage_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \output_stage_logical_op__imm_data__ok$25 - connect \logical_op__input_carry \output_stage_logical_op__input_carry - connect \logical_op__input_carry$12 \output_stage_logical_op__input_carry$32 - connect \logical_op__insn \output_stage_logical_op__insn - connect \logical_op__insn$19 \output_stage_logical_op__insn$39 - connect \logical_op__insn_type \output_stage_logical_op__insn_type - connect \logical_op__insn_type$2 \output_stage_logical_op__insn_type$22 - connect \logical_op__invert_in \output_stage_logical_op__invert_in - connect \logical_op__invert_in$10 \output_stage_logical_op__invert_in$30 - connect \logical_op__invert_out \output_stage_logical_op__invert_out - connect \logical_op__invert_out$13 \output_stage_logical_op__invert_out$33 - connect \logical_op__is_32bit \output_stage_logical_op__is_32bit - connect \logical_op__is_32bit$16 \output_stage_logical_op__is_32bit$36 - connect \logical_op__is_signed \output_stage_logical_op__is_signed - connect \logical_op__is_signed$17 \output_stage_logical_op__is_signed$37 - connect \logical_op__oe__oe \output_stage_logical_op__oe__oe - connect \logical_op__oe__oe$8 \output_stage_logical_op__oe__oe$28 - connect \logical_op__oe__ok \output_stage_logical_op__oe__ok - connect \logical_op__oe__ok$9 \output_stage_logical_op__oe__ok$29 - connect \logical_op__output_carry \output_stage_logical_op__output_carry - connect \logical_op__output_carry$15 \output_stage_logical_op__output_carry$35 - connect \logical_op__rc__ok \output_stage_logical_op__rc__ok - connect \logical_op__rc__ok$7 \output_stage_logical_op__rc__ok$27 - connect \logical_op__rc__rc \output_stage_logical_op__rc__rc - connect \logical_op__rc__rc$6 \output_stage_logical_op__rc__rc$26 - connect \logical_op__write_cr0 \output_stage_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \output_stage_logical_op__write_cr0$34 - connect \logical_op__zero_a \output_stage_logical_op__zero_a - connect \logical_op__zero_a$11 \output_stage_logical_op__zero_a$31 - connect \muxid \output_stage_muxid - connect \muxid$1 \output_stage_muxid$21 - connect \o \output_stage_o - connect \o_ok \output_stage_o_ok - connect \quotient_root \output_stage_quotient_root - connect \remainder \output_stage_remainder - connect \xer_ov \output_stage_xer_ov - connect \xer_ov_ok \output_stage_xer_ov_ok - connect \xer_so \output_stage_xer_so - connect \xer_so$20 \output_stage_xer_so$40 - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:155243.10-155246.4" - cell \p$78 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "issuer_ls180.v:153947.7-153947.20" - process $proc$issuer_ls180.v:153947$8812 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:153956.13-153956.24" - process $proc$issuer_ls180.v:153956$8813 - assign { } { } - assign $1\cr_a[3:0] 4'0000 - sync always - sync init - update \cr_a $1\cr_a[3:0] - end - attribute \src "issuer_ls180.v:153965.7-153965.21" - process $proc$issuer_ls180.v:153965$8814 - assign { } { } - assign $1\cr_a_ok[0:0] 1'0 - sync always - sync init - update \cr_a_ok $1\cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:153988.13-153988.45" - process $proc$issuer_ls180.v:153988$8815 - assign { } { } - assign $0\logical_op__data_len$18[3:0]$8816 4'0000 - sync always - sync init - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$8816 - end - attribute \src "issuer_ls180.v:154023.14-154023.47" - process $proc$issuer_ls180.v:154023$8817 - assign { } { } - assign $0\logical_op__fn_unit$3[11:0]$8818 12'000000000000 - sync always - sync init - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$8818 - end - attribute \src "issuer_ls180.v:154045.14-154045.67" - process $proc$issuer_ls180.v:154045$8819 - assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$8820 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$8820 - end - attribute \src "issuer_ls180.v:154054.7-154054.42" - process $proc$issuer_ls180.v:154054$8821 - assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$8822 1'0 - sync always - sync init - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$8822 - end - attribute \src "issuer_ls180.v:154071.13-154071.48" - process $proc$issuer_ls180.v:154071$8823 - assign { } { } - assign $0\logical_op__input_carry$12[1:0]$8824 2'00 - sync always - sync init - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$8824 - end - attribute \src "issuer_ls180.v:154084.14-154084.43" - process $proc$issuer_ls180.v:154084$8825 - assign { } { } - assign $0\logical_op__insn$19[31:0]$8826 0 - sync always - sync init - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$8826 - end - attribute \src "issuer_ls180.v:154241.13-154241.46" - process $proc$issuer_ls180.v:154241$8827 - assign { } { } - assign $0\logical_op__insn_type$2[6:0]$8828 7'0000000 - sync always - sync init - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$8828 - end - attribute \src "issuer_ls180.v:154324.7-154324.40" - process $proc$issuer_ls180.v:154324$8829 - assign { } { } - assign $0\logical_op__invert_in$10[0:0]$8830 1'0 - sync always - sync init - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$8830 - end - attribute \src "issuer_ls180.v:154333.7-154333.41" - process $proc$issuer_ls180.v:154333$8831 - assign { } { } - assign $0\logical_op__invert_out$13[0:0]$8832 1'0 - sync always - sync init - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$8832 - end - attribute \src "issuer_ls180.v:154342.7-154342.39" - process $proc$issuer_ls180.v:154342$8833 - assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$8834 1'0 - sync always - sync init - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$8834 - end - attribute \src "issuer_ls180.v:154351.7-154351.40" - process $proc$issuer_ls180.v:154351$8835 - assign { } { } - assign $0\logical_op__is_signed$17[0:0]$8836 1'0 - sync always - sync init - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$8836 - end - attribute \src "issuer_ls180.v:154360.7-154360.36" - process $proc$issuer_ls180.v:154360$8837 - assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$8838 1'0 - sync always - sync init - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$8838 - end - attribute \src "issuer_ls180.v:154371.7-154371.36" - process $proc$issuer_ls180.v:154371$8839 - assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$8840 1'0 - sync always - sync init - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$8840 - end - attribute \src "issuer_ls180.v:154378.7-154378.43" - process $proc$issuer_ls180.v:154378$8841 - assign { } { } - assign $0\logical_op__output_carry$15[0:0]$8842 1'0 - sync always - sync init - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$8842 - end - attribute \src "issuer_ls180.v:154387.7-154387.36" - process $proc$issuer_ls180.v:154387$8843 - assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$8844 1'0 - sync always - sync init - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$8844 - end - attribute \src "issuer_ls180.v:154396.7-154396.36" - process $proc$issuer_ls180.v:154396$8845 - assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$8846 1'0 - sync always - sync init - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$8846 - end - attribute \src "issuer_ls180.v:154405.7-154405.40" - process $proc$issuer_ls180.v:154405$8847 - assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$8848 1'0 - sync always - sync init - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$8848 - end - attribute \src "issuer_ls180.v:154414.7-154414.37" - process $proc$issuer_ls180.v:154414$8849 - assign { } { } - assign $0\logical_op__zero_a$11[0:0]$8850 1'0 - sync always - sync init - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$8850 - end - attribute \src "issuer_ls180.v:154423.13-154423.29" - process $proc$issuer_ls180.v:154423$8851 - assign { } { } - assign $0\muxid$1[1:0]$8852 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$8852 - end - attribute \src "issuer_ls180.v:154436.14-154436.38" - process $proc$issuer_ls180.v:154436$8853 - assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o $1\o[63:0] - end - attribute \src "issuer_ls180.v:154443.7-154443.18" - process $proc$issuer_ls180.v:154443$8854 - assign { } { } - assign $1\o_ok[0:0] 1'0 - sync always - sync init - update \o_ok $1\o_ok[0:0] - end - attribute \src "issuer_ls180.v:155027.7-155027.20" - process $proc$issuer_ls180.v:155027$8855 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "issuer_ls180.v:155042.13-155042.26" - process $proc$issuer_ls180.v:155042$8856 - assign { } { } - assign $1\xer_ov[1:0] 2'00 - sync always - sync init - update \xer_ov $1\xer_ov[1:0] - end - attribute \src "issuer_ls180.v:155049.7-155049.23" - process $proc$issuer_ls180.v:155049$8857 - assign { } { } - assign $1\xer_ov_ok[0:0] 1'0 - sync always - sync init - update \xer_ov_ok $1\xer_ov_ok[0:0] - end - attribute \src "issuer_ls180.v:155062.7-155062.25" - process $proc$issuer_ls180.v:155062$8858 - assign { } { } - assign $0\xer_so$20[0:0]$8859 1'0 - sync always - sync init - update \xer_so$20 $0\xer_so$20[0:0]$8859 - end - attribute \src "issuer_ls180.v:155067.7-155067.23" - process $proc$issuer_ls180.v:155067$8860 - assign { } { } - assign $1\xer_so_ok[0:0] 1'0 - sync always - sync init - update \xer_so_ok $1\xer_so_ok[0:0] - end - attribute \src "issuer_ls180.v:155077.3-155078.37" - process $proc$issuer_ls180.v:155077$8690 - assign { } { } - assign $0\xer_so$20[0:0]$8691 \xer_so$20$next - sync posedge \coresync_clk - update \xer_so$20 $0\xer_so$20[0:0]$8691 - end - attribute \src "issuer_ls180.v:155079.3-155080.35" - process $proc$issuer_ls180.v:155079$8692 - assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next - sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] - end - attribute \src "issuer_ls180.v:155081.3-155082.29" - process $proc$issuer_ls180.v:155081$8693 - assign { } { } - assign $0\xer_ov[1:0] \xer_ov$next - sync posedge \coresync_clk - update \xer_ov $0\xer_ov[1:0] - end - attribute \src "issuer_ls180.v:155083.3-155084.35" - process $proc$issuer_ls180.v:155083$8694 - assign { } { } - assign $0\xer_ov_ok[0:0] \xer_ov_ok$next - sync posedge \coresync_clk - update \xer_ov_ok $0\xer_ov_ok[0:0] - end - attribute \src "issuer_ls180.v:155085.3-155086.25" - process $proc$issuer_ls180.v:155085$8695 - assign { } { } - assign $0\cr_a[3:0] \cr_a$next - sync posedge \coresync_clk - update \cr_a $0\cr_a[3:0] - end - attribute \src "issuer_ls180.v:155087.3-155088.31" - process $proc$issuer_ls180.v:155087$8696 - assign { } { } - assign $0\cr_a_ok[0:0] \cr_a_ok$next - sync posedge \coresync_clk - update \cr_a_ok $0\cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:155089.3-155090.19" - process $proc$issuer_ls180.v:155089$8697 - assign { } { } - assign $0\o[63:0] \o$next - sync posedge \coresync_clk - update \o $0\o[63:0] - end - attribute \src "issuer_ls180.v:155091.3-155092.25" - process $proc$issuer_ls180.v:155091$8698 - assign { } { } - assign $0\o_ok[0:0] \o_ok$next - sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] - end - attribute \src "issuer_ls180.v:155093.3-155094.65" - process $proc$issuer_ls180.v:155093$8699 - assign { } { } - assign $0\logical_op__insn_type$2[6:0]$8700 \logical_op__insn_type$2$next - sync posedge \coresync_clk - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$8700 - end - attribute \src "issuer_ls180.v:155095.3-155096.61" - process $proc$issuer_ls180.v:155095$8701 - assign { } { } - assign $0\logical_op__fn_unit$3[11:0]$8702 \logical_op__fn_unit$3$next - sync posedge \coresync_clk - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$8702 - end - attribute \src "issuer_ls180.v:155097.3-155098.75" - process $proc$issuer_ls180.v:155097$8703 - assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$8704 \logical_op__imm_data__data$4$next - sync posedge \coresync_clk - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$8704 - end - attribute \src "issuer_ls180.v:155099.3-155100.71" - process $proc$issuer_ls180.v:155099$8705 - assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$8706 \logical_op__imm_data__ok$5$next - sync posedge \coresync_clk - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$8706 - end - attribute \src "issuer_ls180.v:155101.3-155102.59" - process $proc$issuer_ls180.v:155101$8707 - assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$8708 \logical_op__rc__rc$6$next - sync posedge \coresync_clk - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$8708 - end - attribute \src "issuer_ls180.v:155103.3-155104.59" - process $proc$issuer_ls180.v:155103$8709 - assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$8710 \logical_op__rc__ok$7$next - sync posedge \coresync_clk - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$8710 - end - attribute \src "issuer_ls180.v:155105.3-155106.59" - process $proc$issuer_ls180.v:155105$8711 - assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$8712 \logical_op__oe__oe$8$next - sync posedge \coresync_clk - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$8712 - end - attribute \src "issuer_ls180.v:155107.3-155108.59" - process $proc$issuer_ls180.v:155107$8713 - assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$8714 \logical_op__oe__ok$9$next - sync posedge \coresync_clk - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$8714 - end - attribute \src "issuer_ls180.v:155109.3-155110.67" - process $proc$issuer_ls180.v:155109$8715 - assign { } { } - assign $0\logical_op__invert_in$10[0:0]$8716 \logical_op__invert_in$10$next - sync posedge \coresync_clk - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$8716 - end - attribute \src "issuer_ls180.v:155111.3-155112.61" - process $proc$issuer_ls180.v:155111$8717 - assign { } { } - assign $0\logical_op__zero_a$11[0:0]$8718 \logical_op__zero_a$11$next - sync posedge \coresync_clk - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$8718 - end - attribute \src "issuer_ls180.v:155113.3-155114.71" - process $proc$issuer_ls180.v:155113$8719 - assign { } { } - assign $0\logical_op__input_carry$12[1:0]$8720 \logical_op__input_carry$12$next - sync posedge \coresync_clk - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$8720 - end - attribute \src "issuer_ls180.v:155115.3-155116.69" - process $proc$issuer_ls180.v:155115$8721 - assign { } { } - assign $0\logical_op__invert_out$13[0:0]$8722 \logical_op__invert_out$13$next - sync posedge \coresync_clk - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$8722 - end - attribute \src "issuer_ls180.v:155117.3-155118.67" - process $proc$issuer_ls180.v:155117$8723 - assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$8724 \logical_op__write_cr0$14$next - sync posedge \coresync_clk - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$8724 - end - attribute \src "issuer_ls180.v:155119.3-155120.73" - process $proc$issuer_ls180.v:155119$8725 - assign { } { } - assign $0\logical_op__output_carry$15[0:0]$8726 \logical_op__output_carry$15$next - sync posedge \coresync_clk - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$8726 - end - attribute \src "issuer_ls180.v:155121.3-155122.65" - process $proc$issuer_ls180.v:155121$8727 - assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$8728 \logical_op__is_32bit$16$next - sync posedge \coresync_clk - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$8728 - end - attribute \src "issuer_ls180.v:155123.3-155124.67" - process $proc$issuer_ls180.v:155123$8729 - assign { } { } - assign $0\logical_op__is_signed$17[0:0]$8730 \logical_op__is_signed$17$next - sync posedge \coresync_clk - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$8730 - end - attribute \src "issuer_ls180.v:155125.3-155126.65" - process $proc$issuer_ls180.v:155125$8731 - assign { } { } - assign $0\logical_op__data_len$18[3:0]$8732 \logical_op__data_len$18$next - sync posedge \coresync_clk - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$8732 - end - attribute \src "issuer_ls180.v:155127.3-155128.57" - process $proc$issuer_ls180.v:155127$8733 - assign { } { } - assign $0\logical_op__insn$19[31:0]$8734 \logical_op__insn$19$next - sync posedge \coresync_clk - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$8734 - end - attribute \src "issuer_ls180.v:155129.3-155130.33" - process $proc$issuer_ls180.v:155129$8735 - assign { } { } - assign $0\muxid$1[1:0]$8736 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8736 - end - attribute \src "issuer_ls180.v:155131.3-155132.29" - process $proc$issuer_ls180.v:155131$8737 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "issuer_ls180.v:155247.3-155265.6" - process $proc$issuer_ls180.v:155247$8738 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$next[63:0]$8739 $1\o$next[63:0]$8741 - assign { } { } - assign $0\o_ok$next[0:0]$8740 $2\o_ok$next[0:0]$8743 - attribute \src "issuer_ls180.v:155248.5-155248.29" - switch \initial - attribute \src "issuer_ls180.v:155248.9-155248.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$8742 $1\o$next[63:0]$8741 } { \o_ok$96 \o$95 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$8742 $1\o$next[63:0]$8741 } { \o_ok$96 \o$95 } - case - assign $1\o$next[63:0]$8741 \o - assign $1\o_ok$next[0:0]$8742 \o_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o_ok$next[0:0]$8743 1'0 - case - assign $2\o_ok$next[0:0]$8743 $1\o_ok$next[0:0]$8742 - end - sync always - update \o$next $0\o$next[63:0]$8739 - update \o_ok$next $0\o_ok$next[0:0]$8740 - end - attribute \src "issuer_ls180.v:155266.3-155284.6" - process $proc$issuer_ls180.v:155266$8744 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$next[3:0]$8745 $1\cr_a$next[3:0]$8747 - assign { } { } - assign $0\cr_a_ok$next[0:0]$8746 $2\cr_a_ok$next[0:0]$8749 - attribute \src "issuer_ls180.v:155267.5-155267.29" - switch \initial - attribute \src "issuer_ls180.v:155267.9-155267.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$8748 $1\cr_a$next[3:0]$8747 } { \cr_a_ok$98 \cr_a$97 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$8748 $1\cr_a$next[3:0]$8747 } { \cr_a_ok$98 \cr_a$97 } - case - assign $1\cr_a$next[3:0]$8747 \cr_a - assign $1\cr_a_ok$next[0:0]$8748 \cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_a_ok$next[0:0]$8749 1'0 - case - assign $2\cr_a_ok$next[0:0]$8749 $1\cr_a_ok$next[0:0]$8748 - end - sync always - update \cr_a$next $0\cr_a$next[3:0]$8745 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8746 - end - attribute \src "issuer_ls180.v:155285.3-155303.6" - process $proc$issuer_ls180.v:155285$8750 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_ov$next[1:0]$8751 $1\xer_ov$next[1:0]$8753 - assign { } { } - assign $0\xer_ov_ok$next[0:0]$8752 $2\xer_ov_ok$next[0:0]$8755 - attribute \src "issuer_ls180.v:155286.5-155286.29" - switch \initial - attribute \src "issuer_ls180.v:155286.9-155286.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8754 $1\xer_ov$next[1:0]$8753 } { \xer_ov_ok$100 \xer_ov$99 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8754 $1\xer_ov$next[1:0]$8753 } { \xer_ov_ok$100 \xer_ov$99 } - case - assign $1\xer_ov$next[1:0]$8753 \xer_ov - assign $1\xer_ov_ok$next[0:0]$8754 \xer_ov_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_ov_ok$next[0:0]$8755 1'0 - case - assign $2\xer_ov_ok$next[0:0]$8755 $1\xer_ov_ok$next[0:0]$8754 - end - sync always - update \xer_ov$next $0\xer_ov$next[1:0]$8751 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8752 - end - attribute \src "issuer_ls180.v:155304.3-155322.6" - process $proc$issuer_ls180.v:155304$8756 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_so$20$next[0:0]$8758 $1\xer_so$20$next[0:0]$8760 - assign $0\xer_so_ok$next[0:0]$8757 $2\xer_so_ok$next[0:0]$8761 - attribute \src "issuer_ls180.v:155305.5-155305.29" - switch \initial - attribute \src "issuer_ls180.v:155305.9-155305.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_so_ok$next[0:0]$8759 $1\xer_so$20$next[0:0]$8760 } { \xer_so_ok$102 \xer_so$101 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_so_ok$next[0:0]$8759 $1\xer_so$20$next[0:0]$8760 } { \xer_so_ok$102 \xer_so$101 } - case - assign $1\xer_so_ok$next[0:0]$8759 \xer_so_ok - assign $1\xer_so$20$next[0:0]$8760 \xer_so$20 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_so_ok$next[0:0]$8761 1'0 - case - assign $2\xer_so_ok$next[0:0]$8761 $1\xer_so_ok$next[0:0]$8759 - end - sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8757 - update \xer_so$20$next $0\xer_so$20$next[0:0]$8758 - end - attribute \src "issuer_ls180.v:155323.3-155340.6" - process $proc$issuer_ls180.v:155323$8762 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$8763 $2\r_busy$next[0:0]$8765 - attribute \src "issuer_ls180.v:155324.5-155324.29" - switch \initial - attribute \src "issuer_ls180.v:155324.9-155324.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$8764 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\r_busy$next[0:0]$8764 1'0 - case - assign $1\r_busy$next[0:0]$8764 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$8765 1'0 - case - assign $2\r_busy$next[0:0]$8765 $1\r_busy$next[0:0]$8764 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$8763 - end - attribute \src "issuer_ls180.v:155341.3-155353.6" - process $proc$issuer_ls180.v:155341$8766 - assign { } { } - assign { } { } - assign $0\muxid$1$next[1:0]$8767 $1\muxid$1$next[1:0]$8768 - attribute \src "issuer_ls180.v:155342.5-155342.29" - switch \initial - attribute \src "issuer_ls180.v:155342.9-155342.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$1$next[1:0]$8768 \muxid$76 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$1$next[1:0]$8768 \muxid$76 - case - assign $1\muxid$1$next[1:0]$8768 \muxid$1 - end - sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8767 - end - attribute \src "issuer_ls180.v:155354.3-155395.6" - process $proc$issuer_ls180.v:155354$8769 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\logical_op__data_len$18$next[3:0]$8770 $1\logical_op__data_len$18$next[3:0]$8788 - assign $0\logical_op__fn_unit$3$next[11:0]$8771 $1\logical_op__fn_unit$3$next[11:0]$8789 - assign { } { } - assign { } { } - assign $0\logical_op__input_carry$12$next[1:0]$8774 $1\logical_op__input_carry$12$next[1:0]$8792 - assign $0\logical_op__insn$19$next[31:0]$8775 $1\logical_op__insn$19$next[31:0]$8793 - assign $0\logical_op__insn_type$2$next[6:0]$8776 $1\logical_op__insn_type$2$next[6:0]$8794 - assign $0\logical_op__invert_in$10$next[0:0]$8777 $1\logical_op__invert_in$10$next[0:0]$8795 - assign $0\logical_op__invert_out$13$next[0:0]$8778 $1\logical_op__invert_out$13$next[0:0]$8796 - assign $0\logical_op__is_32bit$16$next[0:0]$8779 $1\logical_op__is_32bit$16$next[0:0]$8797 - assign $0\logical_op__is_signed$17$next[0:0]$8780 $1\logical_op__is_signed$17$next[0:0]$8798 - assign { } { } - assign { } { } - assign $0\logical_op__output_carry$15$next[0:0]$8783 $1\logical_op__output_carry$15$next[0:0]$8801 - assign { } { } - assign { } { } - assign $0\logical_op__write_cr0$14$next[0:0]$8786 $1\logical_op__write_cr0$14$next[0:0]$8804 - assign $0\logical_op__zero_a$11$next[0:0]$8787 $1\logical_op__zero_a$11$next[0:0]$8805 - assign $0\logical_op__imm_data__data$4$next[63:0]$8772 $2\logical_op__imm_data__data$4$next[63:0]$8806 - assign $0\logical_op__imm_data__ok$5$next[0:0]$8773 $2\logical_op__imm_data__ok$5$next[0:0]$8807 - assign $0\logical_op__oe__oe$8$next[0:0]$8781 $2\logical_op__oe__oe$8$next[0:0]$8808 - assign $0\logical_op__oe__ok$9$next[0:0]$8782 $2\logical_op__oe__ok$9$next[0:0]$8809 - assign $0\logical_op__rc__ok$7$next[0:0]$8784 $2\logical_op__rc__ok$7$next[0:0]$8810 - assign $0\logical_op__rc__rc$6$next[0:0]$8785 $2\logical_op__rc__rc$6$next[0:0]$8811 - attribute \src "issuer_ls180.v:155355.5-155355.29" - switch \initial - attribute \src "issuer_ls180.v:155355.9-155355.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$8793 $1\logical_op__data_len$18$next[3:0]$8788 $1\logical_op__is_signed$17$next[0:0]$8798 $1\logical_op__is_32bit$16$next[0:0]$8797 $1\logical_op__output_carry$15$next[0:0]$8801 $1\logical_op__write_cr0$14$next[0:0]$8804 $1\logical_op__invert_out$13$next[0:0]$8796 $1\logical_op__input_carry$12$next[1:0]$8792 $1\logical_op__zero_a$11$next[0:0]$8805 $1\logical_op__invert_in$10$next[0:0]$8795 $1\logical_op__oe__ok$9$next[0:0]$8800 $1\logical_op__oe__oe$8$next[0:0]$8799 $1\logical_op__rc__ok$7$next[0:0]$8802 $1\logical_op__rc__rc$6$next[0:0]$8803 $1\logical_op__imm_data__ok$5$next[0:0]$8791 $1\logical_op__imm_data__data$4$next[63:0]$8790 $1\logical_op__fn_unit$3$next[11:0]$8789 $1\logical_op__insn_type$2$next[6:0]$8794 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$8793 $1\logical_op__data_len$18$next[3:0]$8788 $1\logical_op__is_signed$17$next[0:0]$8798 $1\logical_op__is_32bit$16$next[0:0]$8797 $1\logical_op__output_carry$15$next[0:0]$8801 $1\logical_op__write_cr0$14$next[0:0]$8804 $1\logical_op__invert_out$13$next[0:0]$8796 $1\logical_op__input_carry$12$next[1:0]$8792 $1\logical_op__zero_a$11$next[0:0]$8805 $1\logical_op__invert_in$10$next[0:0]$8795 $1\logical_op__oe__ok$9$next[0:0]$8800 $1\logical_op__oe__oe$8$next[0:0]$8799 $1\logical_op__rc__ok$7$next[0:0]$8802 $1\logical_op__rc__rc$6$next[0:0]$8803 $1\logical_op__imm_data__ok$5$next[0:0]$8791 $1\logical_op__imm_data__data$4$next[63:0]$8790 $1\logical_op__fn_unit$3$next[11:0]$8789 $1\logical_op__insn_type$2$next[6:0]$8794 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } - case - assign $1\logical_op__data_len$18$next[3:0]$8788 \logical_op__data_len$18 - assign $1\logical_op__fn_unit$3$next[11:0]$8789 \logical_op__fn_unit$3 - assign $1\logical_op__imm_data__data$4$next[63:0]$8790 \logical_op__imm_data__data$4 - assign $1\logical_op__imm_data__ok$5$next[0:0]$8791 \logical_op__imm_data__ok$5 - assign $1\logical_op__input_carry$12$next[1:0]$8792 \logical_op__input_carry$12 - assign $1\logical_op__insn$19$next[31:0]$8793 \logical_op__insn$19 - assign $1\logical_op__insn_type$2$next[6:0]$8794 \logical_op__insn_type$2 - assign $1\logical_op__invert_in$10$next[0:0]$8795 \logical_op__invert_in$10 - assign $1\logical_op__invert_out$13$next[0:0]$8796 \logical_op__invert_out$13 - assign $1\logical_op__is_32bit$16$next[0:0]$8797 \logical_op__is_32bit$16 - assign $1\logical_op__is_signed$17$next[0:0]$8798 \logical_op__is_signed$17 - assign $1\logical_op__oe__oe$8$next[0:0]$8799 \logical_op__oe__oe$8 - assign $1\logical_op__oe__ok$9$next[0:0]$8800 \logical_op__oe__ok$9 - assign $1\logical_op__output_carry$15$next[0:0]$8801 \logical_op__output_carry$15 - assign $1\logical_op__rc__ok$7$next[0:0]$8802 \logical_op__rc__ok$7 - assign $1\logical_op__rc__rc$6$next[0:0]$8803 \logical_op__rc__rc$6 - assign $1\logical_op__write_cr0$14$next[0:0]$8804 \logical_op__write_cr0$14 - assign $1\logical_op__zero_a$11$next[0:0]$8805 \logical_op__zero_a$11 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\logical_op__imm_data__data$4$next[63:0]$8806 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$5$next[0:0]$8807 1'0 - assign $2\logical_op__rc__rc$6$next[0:0]$8811 1'0 - assign $2\logical_op__rc__ok$7$next[0:0]$8810 1'0 - assign $2\logical_op__oe__oe$8$next[0:0]$8808 1'0 - assign $2\logical_op__oe__ok$9$next[0:0]$8809 1'0 - case - assign $2\logical_op__imm_data__data$4$next[63:0]$8806 $1\logical_op__imm_data__data$4$next[63:0]$8790 - assign $2\logical_op__imm_data__ok$5$next[0:0]$8807 $1\logical_op__imm_data__ok$5$next[0:0]$8791 - assign $2\logical_op__oe__oe$8$next[0:0]$8808 $1\logical_op__oe__oe$8$next[0:0]$8799 - assign $2\logical_op__oe__ok$9$next[0:0]$8809 $1\logical_op__oe__ok$9$next[0:0]$8800 - assign $2\logical_op__rc__ok$7$next[0:0]$8810 $1\logical_op__rc__ok$7$next[0:0]$8802 - assign $2\logical_op__rc__rc$6$next[0:0]$8811 $1\logical_op__rc__rc$6$next[0:0]$8803 - end - sync always - update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$8770 - update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[11:0]$8771 - update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$8772 - update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$8773 - update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$8774 - update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$8775 - update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$8776 - update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$8777 - update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$8778 - update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$8779 - update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$8780 - update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$8781 - update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$8782 - update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$8783 - update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$8784 - update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$8785 - update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$8786 - update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$8787 - end - connect \$74 $and$issuer_ls180.v:155076$8689_Y - connect \cr_a$68 4'0000 - connect \cr_a_ok$69 1'0 - connect \xer_so_ok$72 1'0 - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \xer_so_ok$102 \xer_so$101 } { \output_xer_so_ok \output_xer_so$64 } - connect { \xer_ov_ok$100 \xer_ov$99 } { \output_xer_ov_ok \output_xer_ov$63 } - connect { \cr_a_ok$98 \cr_a$97 } { \output_cr_a_ok \output_cr_a$62 } - connect { \o_ok$96 \o$95 } { \output_o_ok$61 \output_o$60 } - connect { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } { \output_logical_op__insn$59 \output_logical_op__data_len$58 \output_logical_op__is_signed$57 \output_logical_op__is_32bit$56 \output_logical_op__output_carry$55 \output_logical_op__write_cr0$54 \output_logical_op__invert_out$53 \output_logical_op__input_carry$52 \output_logical_op__zero_a$51 \output_logical_op__invert_in$50 \output_logical_op__oe__ok$49 \output_logical_op__oe__oe$48 \output_logical_op__rc__ok$47 \output_logical_op__rc__rc$46 \output_logical_op__imm_data__ok$45 \output_logical_op__imm_data__data$44 \output_logical_op__fn_unit$43 \output_logical_op__insn_type$42 } - connect \muxid$76 \output_muxid$41 - connect \p_valid_i_p_ready_o \$74 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$73 \p_valid_i - connect { \xer_so_ok$71 \output_xer_so } { 1'0 \output_stage_xer_so$40 } - connect { \xer_ov_ok$70 \output_xer_ov } { \output_stage_xer_ov_ok \output_stage_xer_ov } - connect { \cr_a_ok$67 \output_cr_a } 5'00000 - connect { \output_o_ok \output_o } { \output_stage_o_ok \output_stage_o } - connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \output_stage_logical_op__insn$39 \output_stage_logical_op__data_len$38 \output_stage_logical_op__is_signed$37 \output_stage_logical_op__is_32bit$36 \output_stage_logical_op__output_carry$35 \output_stage_logical_op__write_cr0$34 \output_stage_logical_op__invert_out$33 \output_stage_logical_op__input_carry$32 \output_stage_logical_op__zero_a$31 \output_stage_logical_op__invert_in$30 \output_stage_logical_op__oe__ok$29 \output_stage_logical_op__oe__oe$28 \output_stage_logical_op__rc__ok$27 \output_stage_logical_op__rc__rc$26 \output_stage_logical_op__imm_data__ok$25 \output_stage_logical_op__imm_data__data$24 \output_stage_logical_op__fn_unit$23 \output_stage_logical_op__insn_type$22 } - connect \output_muxid \output_stage_muxid$21 - connect \output_stage_remainder \remainder - connect \output_stage_quotient_root \quotient_root - connect \output_stage_div_by_zero \div_by_zero - connect \output_stage_dive_abs_ov64 \dive_abs_ov64 - connect \output_stage_dive_abs_ov32 \dive_abs_ov32 - connect \output_stage_dividend_neg \dividend_neg - connect \output_stage_divisor_neg \divisor_neg - connect \output_stage_xer_so \xer_so - connect \rb$66 \rb - connect \ra$65 \ra - connect { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in \output_stage_logical_op__oe__ok \output_stage_logical_op__oe__oe \output_stage_logical_op__rc__ok \output_stage_logical_op__rc__rc \output_stage_logical_op__imm_data__ok \output_stage_logical_op__imm_data__data \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - connect \output_stage_muxid \muxid -end -attribute \src "issuer_ls180.v:155432.1-156410.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0" -attribute \generator "nMigen" -module \pipe_middle_0 - attribute \src "issuer_ls180.v:156335.3-156349.6" - wire $0\div_by_zero$54$next[0:0]$9040 - attribute \src "issuer_ls180.v:156009.3-156010.47" - wire $0\div_by_zero$54[0:0]$8875 - attribute \src "issuer_ls180.v:155455.7-155455.30" - wire $0\div_by_zero$54[0:0]$9057 - attribute \src "issuer_ls180.v:156131.3-156142.6" - wire width 64 $0\div_state_next_divisor[63:0] - attribute \src "issuer_ls180.v:156119.3-156130.6" - wire width 128 $0\div_state_next_i_dividend_quotient[127:0] - attribute \src "issuer_ls180.v:156107.3-156118.6" - wire width 7 $0\div_state_next_i_q_bits_known[6:0] - attribute \src "issuer_ls180.v:156305.3-156319.6" - wire $0\dive_abs_ov32$52$next[0:0]$9032 - attribute \src "issuer_ls180.v:156013.3-156014.51" - wire $0\dive_abs_ov32$52[0:0]$8879 - attribute \src "issuer_ls180.v:155479.7-155479.32" - wire $0\dive_abs_ov32$52[0:0]$9059 - attribute \src "issuer_ls180.v:156320.3-156334.6" - wire $0\dive_abs_ov64$53$next[0:0]$9036 - attribute \src "issuer_ls180.v:156011.3-156012.51" - wire $0\dive_abs_ov64$53[0:0]$8877 - attribute \src "issuer_ls180.v:155487.7-155487.32" - wire $0\dive_abs_ov64$53[0:0]$9061 - attribute \src "issuer_ls180.v:156350.3-156364.6" - wire width 128 $0\dividend$68$next[127:0]$9044 - attribute \src "issuer_ls180.v:156007.3-156008.41" - wire width 128 $0\dividend$68[127:0]$8873 - attribute \src "issuer_ls180.v:155493.15-155493.68" - wire width 128 $0\dividend$68[127:0]$9063 - attribute \src "issuer_ls180.v:156290.3-156304.6" - wire $0\dividend_neg$51$next[0:0]$9028 - attribute \src "issuer_ls180.v:156015.3-156016.49" - wire $0\dividend_neg$51[0:0]$8881 - attribute \src "issuer_ls180.v:155501.7-155501.31" - wire $0\dividend_neg$51[0:0]$9065 - attribute \src "issuer_ls180.v:156275.3-156289.6" - wire $0\divisor_neg$50$next[0:0]$9024 - attribute \src "issuer_ls180.v:156017.3-156018.47" - wire $0\divisor_neg$50[0:0]$8883 - attribute \src "issuer_ls180.v:155509.7-155509.30" - wire $0\divisor_neg$50[0:0]$9067 - attribute \src "issuer_ls180.v:156365.3-156379.6" - wire width 64 $0\divisor_radicand$65$next[63:0]$9048 - attribute \src "issuer_ls180.v:156005.3-156006.57" - wire width 64 $0\divisor_radicand$65[63:0]$8871 - attribute \src "issuer_ls180.v:155515.14-155515.58" - wire width 64 $0\divisor_radicand$65[63:0]$9069 - attribute \src "issuer_ls180.v:156143.3-156170.6" - wire $0\empty$next[0:0]$8941 - attribute \src "issuer_ls180.v:156063.3-156064.27" - wire $0\empty[0:0] - attribute \src "issuer_ls180.v:155433.7-155433.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire width 4 $0\logical_op__data_len$45$next[3:0]$8951 - attribute \src "issuer_ls180.v:156057.3-156058.65" - wire width 4 $0\logical_op__data_len$45[3:0]$8923 - attribute \src "issuer_ls180.v:155527.13-155527.45" - wire width 4 $0\logical_op__data_len$45[3:0]$9072 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire width 12 $0\logical_op__fn_unit$30$next[11:0]$8952 - attribute \src "issuer_ls180.v:156027.3-156028.63" - wire width 12 $0\logical_op__fn_unit$30[11:0]$8893 - attribute \src "issuer_ls180.v:155574.14-155574.48" - wire width 12 $0\logical_op__fn_unit$30[11:0]$9074 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$8953 - attribute \src "issuer_ls180.v:156029.3-156030.77" - wire width 64 $0\logical_op__imm_data__data$31[63:0]$8895 - attribute \src "issuer_ls180.v:155580.14-155580.68" - wire width 64 $0\logical_op__imm_data__data$31[63:0]$9076 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $0\logical_op__imm_data__ok$32$next[0:0]$8954 - attribute \src "issuer_ls180.v:156031.3-156032.73" - wire $0\logical_op__imm_data__ok$32[0:0]$8897 - attribute \src "issuer_ls180.v:155588.7-155588.43" - wire $0\logical_op__imm_data__ok$32[0:0]$9078 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire width 2 $0\logical_op__input_carry$39$next[1:0]$8955 - attribute \src "issuer_ls180.v:156045.3-156046.71" - wire width 2 $0\logical_op__input_carry$39[1:0]$8911 - attribute \src "issuer_ls180.v:155610.13-155610.48" - wire width 2 $0\logical_op__input_carry$39[1:0]$9080 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire width 32 $0\logical_op__insn$46$next[31:0]$8956 - attribute \src "issuer_ls180.v:156059.3-156060.57" - wire width 32 $0\logical_op__insn$46[31:0]$8925 - attribute \src "issuer_ls180.v:155618.14-155618.43" - wire width 32 $0\logical_op__insn$46[31:0]$9082 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire width 7 $0\logical_op__insn_type$29$next[6:0]$8957 - attribute \src "issuer_ls180.v:156025.3-156026.67" - wire width 7 $0\logical_op__insn_type$29[6:0]$8891 - attribute \src "issuer_ls180.v:155848.13-155848.47" - wire width 7 $0\logical_op__insn_type$29[6:0]$9084 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $0\logical_op__invert_in$37$next[0:0]$8958 - attribute \src "issuer_ls180.v:156041.3-156042.67" - wire $0\logical_op__invert_in$37[0:0]$8907 - attribute \src "issuer_ls180.v:155856.7-155856.40" - wire $0\logical_op__invert_in$37[0:0]$9086 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $0\logical_op__invert_out$40$next[0:0]$8959 - attribute \src "issuer_ls180.v:156047.3-156048.69" - wire $0\logical_op__invert_out$40[0:0]$8913 - attribute \src "issuer_ls180.v:155864.7-155864.41" - wire $0\logical_op__invert_out$40[0:0]$9088 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $0\logical_op__is_32bit$43$next[0:0]$8960 - attribute \src "issuer_ls180.v:156053.3-156054.65" - wire $0\logical_op__is_32bit$43[0:0]$8919 - attribute \src "issuer_ls180.v:155872.7-155872.39" - wire $0\logical_op__is_32bit$43[0:0]$9090 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $0\logical_op__is_signed$44$next[0:0]$8961 - attribute \src "issuer_ls180.v:156055.3-156056.67" - wire $0\logical_op__is_signed$44[0:0]$8921 - attribute \src "issuer_ls180.v:155880.7-155880.40" - wire $0\logical_op__is_signed$44[0:0]$9092 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $0\logical_op__oe__oe$35$next[0:0]$8962 - attribute \src "issuer_ls180.v:156037.3-156038.61" - wire $0\logical_op__oe__oe$35[0:0]$8903 - attribute \src "issuer_ls180.v:155886.7-155886.37" - wire $0\logical_op__oe__oe$35[0:0]$9094 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $0\logical_op__oe__ok$36$next[0:0]$8963 - attribute \src "issuer_ls180.v:156039.3-156040.61" - wire $0\logical_op__oe__ok$36[0:0]$8905 - attribute \src "issuer_ls180.v:155894.7-155894.37" - wire $0\logical_op__oe__ok$36[0:0]$9096 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $0\logical_op__output_carry$42$next[0:0]$8964 - attribute \src "issuer_ls180.v:156051.3-156052.73" - wire $0\logical_op__output_carry$42[0:0]$8917 - attribute \src "issuer_ls180.v:155904.7-155904.43" - wire $0\logical_op__output_carry$42[0:0]$9098 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $0\logical_op__rc__ok$34$next[0:0]$8965 - attribute \src "issuer_ls180.v:156035.3-156036.61" - wire $0\logical_op__rc__ok$34[0:0]$8901 - attribute \src "issuer_ls180.v:155910.7-155910.37" - wire $0\logical_op__rc__ok$34[0:0]$9100 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $0\logical_op__rc__rc$33$next[0:0]$8966 - attribute \src "issuer_ls180.v:156033.3-156034.61" - wire $0\logical_op__rc__rc$33[0:0]$8899 - attribute \src "issuer_ls180.v:155918.7-155918.37" - wire $0\logical_op__rc__rc$33[0:0]$9102 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $0\logical_op__write_cr0$41$next[0:0]$8967 - attribute \src "issuer_ls180.v:156049.3-156050.67" - wire $0\logical_op__write_cr0$41[0:0]$8915 - attribute \src "issuer_ls180.v:155928.7-155928.40" - wire $0\logical_op__write_cr0$41[0:0]$9104 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $0\logical_op__zero_a$38$next[0:0]$8968 - attribute \src "issuer_ls180.v:156043.3-156044.61" - wire $0\logical_op__zero_a$38[0:0]$8909 - attribute \src "issuer_ls180.v:155936.7-155936.37" - wire $0\logical_op__zero_a$38[0:0]$9106 - attribute \src "issuer_ls180.v:156171.3-156185.6" - wire width 2 $0\muxid$28$next[1:0]$8947 - attribute \src "issuer_ls180.v:156061.3-156062.35" - wire width 2 $0\muxid$28[1:0]$8927 - attribute \src "issuer_ls180.v:155944.13-155944.30" - wire width 2 $0\muxid$28[1:0]$9108 - attribute \src "issuer_ls180.v:156380.3-156394.6" - wire width 2 $0\operation$69$next[1:0]$9052 - attribute \src "issuer_ls180.v:156003.3-156004.43" - wire width 2 $0\operation$69[1:0]$8869 - attribute \src "issuer_ls180.v:155954.13-155954.34" - wire width 2 $0\operation$69[1:0]$9110 - attribute \src "issuer_ls180.v:156230.3-156244.6" - wire width 64 $0\ra$47$next[63:0]$9012 - attribute \src "issuer_ls180.v:156023.3-156024.29" - wire width 64 $0\ra$47[63:0]$8889 - attribute \src "issuer_ls180.v:155968.14-155968.44" - wire width 64 $0\ra$47[63:0]$9112 - attribute \src "issuer_ls180.v:156245.3-156259.6" - wire width 64 $0\rb$48$next[63:0]$9016 - attribute \src "issuer_ls180.v:156021.3-156022.29" - wire width 64 $0\rb$48[63:0]$8887 - attribute \src "issuer_ls180.v:155976.14-155976.44" - wire width 64 $0\rb$48[63:0]$9114 - attribute \src "issuer_ls180.v:156098.3-156106.6" - wire width 128 $0\saved_state_dividend_quotient$next[127:0]$8935 - attribute \src "issuer_ls180.v:156065.3-156066.75" - wire width 128 $0\saved_state_dividend_quotient[127:0] - attribute \src "issuer_ls180.v:156089.3-156097.6" - wire width 7 $0\saved_state_q_bits_known$next[6:0]$8932 - attribute \src "issuer_ls180.v:156067.3-156068.65" - wire width 7 $0\saved_state_q_bits_known[6:0] - attribute \src "issuer_ls180.v:156260.3-156274.6" - wire $0\xer_so$49$next[0:0]$9020 - attribute \src "issuer_ls180.v:156019.3-156020.37" - wire $0\xer_so$49[0:0]$8885 - attribute \src "issuer_ls180.v:155994.7-155994.25" - wire $0\xer_so$49[0:0]$9118 - attribute \src "issuer_ls180.v:156335.3-156349.6" - wire $1\div_by_zero$54$next[0:0]$9041 - attribute \src "issuer_ls180.v:156131.3-156142.6" - wire width 64 $1\div_state_next_divisor[63:0] - attribute \src "issuer_ls180.v:156119.3-156130.6" - wire width 128 $1\div_state_next_i_dividend_quotient[127:0] - attribute \src "issuer_ls180.v:156107.3-156118.6" - wire width 7 $1\div_state_next_i_q_bits_known[6:0] - attribute \src "issuer_ls180.v:156305.3-156319.6" - wire $1\dive_abs_ov32$52$next[0:0]$9033 - attribute \src "issuer_ls180.v:156320.3-156334.6" - wire $1\dive_abs_ov64$53$next[0:0]$9037 - attribute \src "issuer_ls180.v:156350.3-156364.6" - wire width 128 $1\dividend$68$next[127:0]$9045 - attribute \src "issuer_ls180.v:156290.3-156304.6" - wire $1\dividend_neg$51$next[0:0]$9029 - attribute \src "issuer_ls180.v:156275.3-156289.6" - wire $1\divisor_neg$50$next[0:0]$9025 - attribute \src "issuer_ls180.v:156365.3-156379.6" - wire width 64 $1\divisor_radicand$65$next[63:0]$9049 - attribute \src "issuer_ls180.v:156143.3-156170.6" - wire $1\empty$next[0:0]$8942 - attribute \src "issuer_ls180.v:155519.7-155519.19" - wire $1\empty[0:0] - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire width 4 $1\logical_op__data_len$45$next[3:0]$8969 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire width 12 $1\logical_op__fn_unit$30$next[11:0]$8970 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$8971 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $1\logical_op__imm_data__ok$32$next[0:0]$8972 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire width 2 $1\logical_op__input_carry$39$next[1:0]$8973 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire width 32 $1\logical_op__insn$46$next[31:0]$8974 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire width 7 $1\logical_op__insn_type$29$next[6:0]$8975 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $1\logical_op__invert_in$37$next[0:0]$8976 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $1\logical_op__invert_out$40$next[0:0]$8977 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $1\logical_op__is_32bit$43$next[0:0]$8978 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $1\logical_op__is_signed$44$next[0:0]$8979 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $1\logical_op__oe__oe$35$next[0:0]$8980 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $1\logical_op__oe__ok$36$next[0:0]$8981 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $1\logical_op__output_carry$42$next[0:0]$8982 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $1\logical_op__rc__ok$34$next[0:0]$8983 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $1\logical_op__rc__rc$33$next[0:0]$8984 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $1\logical_op__write_cr0$41$next[0:0]$8985 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $1\logical_op__zero_a$38$next[0:0]$8986 - attribute \src "issuer_ls180.v:156171.3-156185.6" - wire width 2 $1\muxid$28$next[1:0]$8948 - attribute \src "issuer_ls180.v:156380.3-156394.6" - wire width 2 $1\operation$69$next[1:0]$9053 - attribute \src "issuer_ls180.v:156230.3-156244.6" - wire width 64 $1\ra$47$next[63:0]$9013 - attribute \src "issuer_ls180.v:156245.3-156259.6" - wire width 64 $1\rb$48$next[63:0]$9017 - attribute \src "issuer_ls180.v:156098.3-156106.6" - wire width 128 $1\saved_state_dividend_quotient$next[127:0]$8936 - attribute \src "issuer_ls180.v:155982.15-155982.84" - wire width 128 $1\saved_state_dividend_quotient[127:0] - attribute \src "issuer_ls180.v:156089.3-156097.6" - wire width 7 $1\saved_state_q_bits_known$next[6:0]$8933 - attribute \src "issuer_ls180.v:155986.13-155986.45" - wire width 7 $1\saved_state_q_bits_known[6:0] - attribute \src "issuer_ls180.v:156260.3-156274.6" - wire $1\xer_so$49$next[0:0]$9021 - attribute \src "issuer_ls180.v:156335.3-156349.6" - wire $2\div_by_zero$54$next[0:0]$9042 - attribute \src "issuer_ls180.v:156305.3-156319.6" - wire $2\dive_abs_ov32$52$next[0:0]$9034 - attribute \src "issuer_ls180.v:156320.3-156334.6" - wire $2\dive_abs_ov64$53$next[0:0]$9038 - attribute \src "issuer_ls180.v:156350.3-156364.6" - wire width 128 $2\dividend$68$next[127:0]$9046 - attribute \src "issuer_ls180.v:156290.3-156304.6" - wire $2\dividend_neg$51$next[0:0]$9030 - attribute \src "issuer_ls180.v:156275.3-156289.6" - wire $2\divisor_neg$50$next[0:0]$9026 - attribute \src "issuer_ls180.v:156365.3-156379.6" - wire width 64 $2\divisor_radicand$65$next[63:0]$9050 - attribute \src "issuer_ls180.v:156143.3-156170.6" - wire $2\empty$next[0:0]$8943 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire width 4 $2\logical_op__data_len$45$next[3:0]$8987 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire width 12 $2\logical_op__fn_unit$30$next[11:0]$8988 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$8989 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $2\logical_op__imm_data__ok$32$next[0:0]$8990 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire width 2 $2\logical_op__input_carry$39$next[1:0]$8991 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire width 32 $2\logical_op__insn$46$next[31:0]$8992 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire width 7 $2\logical_op__insn_type$29$next[6:0]$8993 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $2\logical_op__invert_in$37$next[0:0]$8994 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $2\logical_op__invert_out$40$next[0:0]$8995 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $2\logical_op__is_32bit$43$next[0:0]$8996 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $2\logical_op__is_signed$44$next[0:0]$8997 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $2\logical_op__oe__oe$35$next[0:0]$8998 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $2\logical_op__oe__ok$36$next[0:0]$8999 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $2\logical_op__output_carry$42$next[0:0]$9000 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $2\logical_op__rc__ok$34$next[0:0]$9001 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $2\logical_op__rc__rc$33$next[0:0]$9002 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $2\logical_op__write_cr0$41$next[0:0]$9003 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $2\logical_op__zero_a$38$next[0:0]$9004 - attribute \src "issuer_ls180.v:156171.3-156185.6" - wire width 2 $2\muxid$28$next[1:0]$8949 - attribute \src "issuer_ls180.v:156380.3-156394.6" - wire width 2 $2\operation$69$next[1:0]$9054 - attribute \src "issuer_ls180.v:156230.3-156244.6" - wire width 64 $2\ra$47$next[63:0]$9014 - attribute \src "issuer_ls180.v:156245.3-156259.6" - wire width 64 $2\rb$48$next[63:0]$9018 - attribute \src "issuer_ls180.v:156260.3-156274.6" - wire $2\xer_so$49$next[0:0]$9022 - attribute \src "issuer_ls180.v:156143.3-156170.6" - wire $3\empty$next[0:0]$8944 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$9005 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $3\logical_op__imm_data__ok$32$next[0:0]$9006 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $3\logical_op__oe__oe$35$next[0:0]$9007 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $3\logical_op__oe__ok$36$next[0:0]$9008 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $3\logical_op__rc__ok$34$next[0:0]$9009 - attribute \src "issuer_ls180.v:156186.3-156229.6" - wire $3\logical_op__rc__rc$33$next[0:0]$9010 - attribute \src "issuer_ls180.v:156143.3-156170.6" - wire $4\empty$next[0:0]$8945 - attribute \src "issuer_ls180.v:156001.18-156001.98" - wire $and$issuer_ls180.v:156001$8866_Y - attribute \src "issuer_ls180.v:156002.18-156002.107" - wire $and$issuer_ls180.v:156002$8867_Y - attribute \src "issuer_ls180.v:156000.18-156000.124" - wire $eq$issuer_ls180.v:156000$8865_Y - attribute \src "issuer_ls180.v:155998.18-155998.92" - wire width 192 $extend$issuer_ls180.v:155998$8862_Y - attribute \src "issuer_ls180.v:155999.18-155999.93" - wire $not$issuer_ls180.v:155999$8864_Y - attribute \src "issuer_ls180.v:155998.18-155998.92" - wire width 192 $pos$issuer_ls180.v:155998$8863_Y - attribute \src "issuer_ls180.v:155997.18-155997.138" - wire width 191 $sshl$issuer_ls180.v:155997$8861_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:162" - wire width 192 \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:162" - wire width 191 \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:163" - wire \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:109" - wire \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:163" - wire \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:177" - wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 65 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire input 30 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire output 62 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire \div_by_zero$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire \div_by_zero$54$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" - wire width 128 \div_state_init_dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" - wire width 128 \div_state_init_o_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" - wire width 7 \div_state_init_o_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:59" - wire width 64 \div_state_next_divisor - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" - wire width 128 \div_state_next_i_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" - wire width 7 \div_state_next_i_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" - wire width 128 \div_state_next_o_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" - wire width 7 \div_state_next_o_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire input 28 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire output 60 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire \dive_abs_ov32$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire \dive_abs_ov32$52$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire input 29 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire output 61 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire \dive_abs_ov64$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire \dive_abs_ov64$53$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 input 31 \dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \dividend$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \dividend$68$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire input 27 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire output 59 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \dividend_neg$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \dividend_neg$51$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire input 26 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire output 58 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \divisor_neg$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \divisor_neg$50$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 input 32 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$65$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:133" - wire \empty - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:133" - wire \empty$next - attribute \src "issuer_ls180.v:155433.7-155433.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 53 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$45$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 38 \logical_op__fn_unit$3 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$30$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$31$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 39 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$32$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \logical_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 47 \logical_op__input_carry$12 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$39$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 54 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$46$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 37 \logical_op__insn_type$2 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$29$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 45 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$37$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 48 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$40$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 51 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$43$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 52 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$44$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$35$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 43 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$36$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 44 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 50 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$42$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$34$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 42 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$33$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 41 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 49 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$41$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 46 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$38$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 36 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$28$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 35 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 34 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 input 33 \operation - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$69$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 64 output 63 \quotient_root - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 23 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 55 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$47$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 24 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 56 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$48$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" - wire width 192 output 64 \remainder - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" - wire width 128 \saved_state_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" - wire width 128 \saved_state_dividend_quotient$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" - wire width 7 \saved_state_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" - wire width 7 \saved_state_q_bits_known$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 25 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 57 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \xer_so$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \xer_so$49$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:163" - cell $and $and$issuer_ls180.v:156001$8866 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$59 - connect \B \$61 - connect \Y $and$issuer_ls180.v:156001$8866_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:177" - cell $and $and$issuer_ls180.v:156002$8867 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$issuer_ls180.v:156002$8867_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:109" - cell $eq $eq$issuer_ls180.v:156000$8865 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \div_state_next_o_q_bits_known - connect \B 7'1000000 - connect \Y $eq$issuer_ls180.v:156000$8865_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:162" - cell $pos $extend$issuer_ls180.v:155998$8862 - parameter \A_SIGNED 0 - parameter \A_WIDTH 191 - parameter \Y_WIDTH 192 - connect \A \$56 - connect \Y $extend$issuer_ls180.v:155998$8862_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:163" - cell $not $not$issuer_ls180.v:155999$8864 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \empty - connect \Y $not$issuer_ls180.v:155999$8864_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:162" - cell $pos $pos$issuer_ls180.v:155998$8863 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A $extend$issuer_ls180.v:155998$8862_Y - connect \Y $pos$issuer_ls180.v:155998$8863_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:162" - cell $sshl $sshl$issuer_ls180.v:155997$8861 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 191 - connect \A \div_state_next_o_dividend_quotient [127:64] - connect \B 7'1000000 - connect \Y $sshl$issuer_ls180.v:155997$8861_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:156069.18-156073.4" - cell \div_state_init \div_state_init - connect \dividend \div_state_init_dividend - connect \o_dividend_quotient \div_state_init_o_dividend_quotient - connect \o_q_bits_known \div_state_init_o_q_bits_known - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:156074.18-156080.4" - cell \div_state_next \div_state_next - connect \divisor \div_state_next_divisor - connect \i_dividend_quotient \div_state_next_i_dividend_quotient - connect \i_q_bits_known \div_state_next_i_q_bits_known - connect \o_dividend_quotient \div_state_next_o_dividend_quotient - connect \o_q_bits_known \div_state_next_o_q_bits_known - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:156081.10-156084.4" - cell \n$77 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:156085.10-156088.4" - cell \p$76 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "issuer_ls180.v:155433.7-155433.20" - process $proc$issuer_ls180.v:155433$9055 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:155455.7-155455.30" - process $proc$issuer_ls180.v:155455$9056 - assign { } { } - assign $0\div_by_zero$54[0:0]$9057 1'0 - sync always - sync init - update \div_by_zero$54 $0\div_by_zero$54[0:0]$9057 - end - attribute \src "issuer_ls180.v:155479.7-155479.32" - process $proc$issuer_ls180.v:155479$9058 - assign { } { } - assign $0\dive_abs_ov32$52[0:0]$9059 1'0 - sync always - sync init - update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$9059 - end - attribute \src "issuer_ls180.v:155487.7-155487.32" - process $proc$issuer_ls180.v:155487$9060 - assign { } { } - assign $0\dive_abs_ov64$53[0:0]$9061 1'0 - sync always - sync init - update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$9061 - end - attribute \src "issuer_ls180.v:155493.15-155493.68" - process $proc$issuer_ls180.v:155493$9062 - assign { } { } - assign $0\dividend$68[127:0]$9063 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dividend$68 $0\dividend$68[127:0]$9063 - end - attribute \src "issuer_ls180.v:155501.7-155501.31" - process $proc$issuer_ls180.v:155501$9064 - assign { } { } - assign $0\dividend_neg$51[0:0]$9065 1'0 - sync always - sync init - update \dividend_neg$51 $0\dividend_neg$51[0:0]$9065 - end - attribute \src "issuer_ls180.v:155509.7-155509.30" - process $proc$issuer_ls180.v:155509$9066 - assign { } { } - assign $0\divisor_neg$50[0:0]$9067 1'0 - sync always - sync init - update \divisor_neg$50 $0\divisor_neg$50[0:0]$9067 - end - attribute \src "issuer_ls180.v:155515.14-155515.58" - process $proc$issuer_ls180.v:155515$9068 - assign { } { } - assign $0\divisor_radicand$65[63:0]$9069 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$9069 - end - attribute \src "issuer_ls180.v:155519.7-155519.19" - process $proc$issuer_ls180.v:155519$9070 - assign { } { } - assign $1\empty[0:0] 1'1 - sync always - sync init - update \empty $1\empty[0:0] - end - attribute \src "issuer_ls180.v:155527.13-155527.45" - process $proc$issuer_ls180.v:155527$9071 - assign { } { } - assign $0\logical_op__data_len$45[3:0]$9072 4'0000 - sync always - sync init - update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$9072 - end - attribute \src "issuer_ls180.v:155574.14-155574.48" - process $proc$issuer_ls180.v:155574$9073 - assign { } { } - assign $0\logical_op__fn_unit$30[11:0]$9074 12'000000000000 - sync always - sync init - update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[11:0]$9074 - end - attribute \src "issuer_ls180.v:155580.14-155580.68" - process $proc$issuer_ls180.v:155580$9075 - assign { } { } - assign $0\logical_op__imm_data__data$31[63:0]$9076 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$9076 - end - attribute \src "issuer_ls180.v:155588.7-155588.43" - process $proc$issuer_ls180.v:155588$9077 - assign { } { } - assign $0\logical_op__imm_data__ok$32[0:0]$9078 1'0 - sync always - sync init - update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$9078 - end - attribute \src "issuer_ls180.v:155610.13-155610.48" - process $proc$issuer_ls180.v:155610$9079 - assign { } { } - assign $0\logical_op__input_carry$39[1:0]$9080 2'00 - sync always - sync init - update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$9080 - end - attribute \src "issuer_ls180.v:155618.14-155618.43" - process $proc$issuer_ls180.v:155618$9081 - assign { } { } - assign $0\logical_op__insn$46[31:0]$9082 0 - sync always - sync init - update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$9082 - end - attribute \src "issuer_ls180.v:155848.13-155848.47" - process $proc$issuer_ls180.v:155848$9083 - assign { } { } - assign $0\logical_op__insn_type$29[6:0]$9084 7'0000000 - sync always - sync init - update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$9084 - end - attribute \src "issuer_ls180.v:155856.7-155856.40" - process $proc$issuer_ls180.v:155856$9085 - assign { } { } - assign $0\logical_op__invert_in$37[0:0]$9086 1'0 - sync always - sync init - update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$9086 - end - attribute \src "issuer_ls180.v:155864.7-155864.41" - process $proc$issuer_ls180.v:155864$9087 - assign { } { } - assign $0\logical_op__invert_out$40[0:0]$9088 1'0 - sync always - sync init - update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$9088 - end - attribute \src "issuer_ls180.v:155872.7-155872.39" - process $proc$issuer_ls180.v:155872$9089 - assign { } { } - assign $0\logical_op__is_32bit$43[0:0]$9090 1'0 - sync always - sync init - update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$9090 - end - attribute \src "issuer_ls180.v:155880.7-155880.40" - process $proc$issuer_ls180.v:155880$9091 - assign { } { } - assign $0\logical_op__is_signed$44[0:0]$9092 1'0 - sync always - sync init - update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$9092 - end - attribute \src "issuer_ls180.v:155886.7-155886.37" - process $proc$issuer_ls180.v:155886$9093 - assign { } { } - assign $0\logical_op__oe__oe$35[0:0]$9094 1'0 - sync always - sync init - update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$9094 - end - attribute \src "issuer_ls180.v:155894.7-155894.37" - process $proc$issuer_ls180.v:155894$9095 - assign { } { } - assign $0\logical_op__oe__ok$36[0:0]$9096 1'0 - sync always - sync init - update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$9096 - end - attribute \src "issuer_ls180.v:155904.7-155904.43" - process $proc$issuer_ls180.v:155904$9097 - assign { } { } - assign $0\logical_op__output_carry$42[0:0]$9098 1'0 - sync always - sync init - update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$9098 - end - attribute \src "issuer_ls180.v:155910.7-155910.37" - process $proc$issuer_ls180.v:155910$9099 - assign { } { } - assign $0\logical_op__rc__ok$34[0:0]$9100 1'0 - sync always - sync init - update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$9100 - end - attribute \src "issuer_ls180.v:155918.7-155918.37" - process $proc$issuer_ls180.v:155918$9101 - assign { } { } - assign $0\logical_op__rc__rc$33[0:0]$9102 1'0 - sync always - sync init - update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$9102 - end - attribute \src "issuer_ls180.v:155928.7-155928.40" - process $proc$issuer_ls180.v:155928$9103 - assign { } { } - assign $0\logical_op__write_cr0$41[0:0]$9104 1'0 - sync always - sync init - update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$9104 - end - attribute \src "issuer_ls180.v:155936.7-155936.37" - process $proc$issuer_ls180.v:155936$9105 - assign { } { } - assign $0\logical_op__zero_a$38[0:0]$9106 1'0 - sync always - sync init - update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$9106 - end - attribute \src "issuer_ls180.v:155944.13-155944.30" - process $proc$issuer_ls180.v:155944$9107 - assign { } { } - assign $0\muxid$28[1:0]$9108 2'00 - sync always - sync init - update \muxid$28 $0\muxid$28[1:0]$9108 - end - attribute \src "issuer_ls180.v:155954.13-155954.34" - process $proc$issuer_ls180.v:155954$9109 - assign { } { } - assign $0\operation$69[1:0]$9110 2'00 - sync always - sync init - update \operation$69 $0\operation$69[1:0]$9110 - end - attribute \src "issuer_ls180.v:155968.14-155968.44" - process $proc$issuer_ls180.v:155968$9111 - assign { } { } - assign $0\ra$47[63:0]$9112 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \ra$47 $0\ra$47[63:0]$9112 - end - attribute \src "issuer_ls180.v:155976.14-155976.44" - process $proc$issuer_ls180.v:155976$9113 - assign { } { } - assign $0\rb$48[63:0]$9114 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \rb$48 $0\rb$48[63:0]$9114 - end - attribute \src "issuer_ls180.v:155982.15-155982.84" - process $proc$issuer_ls180.v:155982$9115 - assign { } { } - assign $1\saved_state_dividend_quotient[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \saved_state_dividend_quotient $1\saved_state_dividend_quotient[127:0] - end - attribute \src "issuer_ls180.v:155986.13-155986.45" - process $proc$issuer_ls180.v:155986$9116 - assign { } { } - assign $1\saved_state_q_bits_known[6:0] 7'0000000 - sync always - sync init - update \saved_state_q_bits_known $1\saved_state_q_bits_known[6:0] - end - attribute \src "issuer_ls180.v:155994.7-155994.25" - process $proc$issuer_ls180.v:155994$9117 - assign { } { } - assign $0\xer_so$49[0:0]$9118 1'0 - sync always - sync init - update \xer_so$49 $0\xer_so$49[0:0]$9118 - end - attribute \src "issuer_ls180.v:156003.3-156004.43" - process $proc$issuer_ls180.v:156003$8868 - assign { } { } - assign $0\operation$69[1:0]$8869 \operation$69$next - sync posedge \coresync_clk - update \operation$69 $0\operation$69[1:0]$8869 - end - attribute \src "issuer_ls180.v:156005.3-156006.57" - process $proc$issuer_ls180.v:156005$8870 - assign { } { } - assign $0\divisor_radicand$65[63:0]$8871 \divisor_radicand$65$next - sync posedge \coresync_clk - update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$8871 - end - attribute \src "issuer_ls180.v:156007.3-156008.41" - process $proc$issuer_ls180.v:156007$8872 - assign { } { } - assign $0\dividend$68[127:0]$8873 \dividend$68$next - sync posedge \coresync_clk - update \dividend$68 $0\dividend$68[127:0]$8873 - end - attribute \src "issuer_ls180.v:156009.3-156010.47" - process $proc$issuer_ls180.v:156009$8874 - assign { } { } - assign $0\div_by_zero$54[0:0]$8875 \div_by_zero$54$next - sync posedge \coresync_clk - update \div_by_zero$54 $0\div_by_zero$54[0:0]$8875 - end - attribute \src "issuer_ls180.v:156011.3-156012.51" - process $proc$issuer_ls180.v:156011$8876 - assign { } { } - assign $0\dive_abs_ov64$53[0:0]$8877 \dive_abs_ov64$53$next - sync posedge \coresync_clk - update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$8877 - end - attribute \src "issuer_ls180.v:156013.3-156014.51" - process $proc$issuer_ls180.v:156013$8878 - assign { } { } - assign $0\dive_abs_ov32$52[0:0]$8879 \dive_abs_ov32$52$next - sync posedge \coresync_clk - update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$8879 - end - attribute \src "issuer_ls180.v:156015.3-156016.49" - process $proc$issuer_ls180.v:156015$8880 - assign { } { } - assign $0\dividend_neg$51[0:0]$8881 \dividend_neg$51$next - sync posedge \coresync_clk - update \dividend_neg$51 $0\dividend_neg$51[0:0]$8881 - end - attribute \src "issuer_ls180.v:156017.3-156018.47" - process $proc$issuer_ls180.v:156017$8882 - assign { } { } - assign $0\divisor_neg$50[0:0]$8883 \divisor_neg$50$next - sync posedge \coresync_clk - update \divisor_neg$50 $0\divisor_neg$50[0:0]$8883 - end - attribute \src "issuer_ls180.v:156019.3-156020.37" - process $proc$issuer_ls180.v:156019$8884 - assign { } { } - assign $0\xer_so$49[0:0]$8885 \xer_so$49$next - sync posedge \coresync_clk - update \xer_so$49 $0\xer_so$49[0:0]$8885 - end - attribute \src "issuer_ls180.v:156021.3-156022.29" - process $proc$issuer_ls180.v:156021$8886 - assign { } { } - assign $0\rb$48[63:0]$8887 \rb$48$next - sync posedge \coresync_clk - update \rb$48 $0\rb$48[63:0]$8887 - end - attribute \src "issuer_ls180.v:156023.3-156024.29" - process $proc$issuer_ls180.v:156023$8888 - assign { } { } - assign $0\ra$47[63:0]$8889 \ra$47$next - sync posedge \coresync_clk - update \ra$47 $0\ra$47[63:0]$8889 - end - attribute \src "issuer_ls180.v:156025.3-156026.67" - process $proc$issuer_ls180.v:156025$8890 - assign { } { } - assign $0\logical_op__insn_type$29[6:0]$8891 \logical_op__insn_type$29$next - sync posedge \coresync_clk - update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$8891 - end - attribute \src "issuer_ls180.v:156027.3-156028.63" - process $proc$issuer_ls180.v:156027$8892 - assign { } { } - assign $0\logical_op__fn_unit$30[11:0]$8893 \logical_op__fn_unit$30$next - sync posedge \coresync_clk - update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[11:0]$8893 - end - attribute \src "issuer_ls180.v:156029.3-156030.77" - process $proc$issuer_ls180.v:156029$8894 - assign { } { } - assign $0\logical_op__imm_data__data$31[63:0]$8895 \logical_op__imm_data__data$31$next - sync posedge \coresync_clk - update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$8895 - end - attribute \src "issuer_ls180.v:156031.3-156032.73" - process $proc$issuer_ls180.v:156031$8896 - assign { } { } - assign $0\logical_op__imm_data__ok$32[0:0]$8897 \logical_op__imm_data__ok$32$next - sync posedge \coresync_clk - update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$8897 - end - attribute \src "issuer_ls180.v:156033.3-156034.61" - process $proc$issuer_ls180.v:156033$8898 - assign { } { } - assign $0\logical_op__rc__rc$33[0:0]$8899 \logical_op__rc__rc$33$next - sync posedge \coresync_clk - update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$8899 - end - attribute \src "issuer_ls180.v:156035.3-156036.61" - process $proc$issuer_ls180.v:156035$8900 - assign { } { } - assign $0\logical_op__rc__ok$34[0:0]$8901 \logical_op__rc__ok$34$next - sync posedge \coresync_clk - update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$8901 - end - attribute \src "issuer_ls180.v:156037.3-156038.61" - process $proc$issuer_ls180.v:156037$8902 - assign { } { } - assign $0\logical_op__oe__oe$35[0:0]$8903 \logical_op__oe__oe$35$next - sync posedge \coresync_clk - update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$8903 - end - attribute \src "issuer_ls180.v:156039.3-156040.61" - process $proc$issuer_ls180.v:156039$8904 - assign { } { } - assign $0\logical_op__oe__ok$36[0:0]$8905 \logical_op__oe__ok$36$next - sync posedge \coresync_clk - update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$8905 - end - attribute \src "issuer_ls180.v:156041.3-156042.67" - process $proc$issuer_ls180.v:156041$8906 - assign { } { } - assign $0\logical_op__invert_in$37[0:0]$8907 \logical_op__invert_in$37$next - sync posedge \coresync_clk - update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$8907 - end - attribute \src "issuer_ls180.v:156043.3-156044.61" - process $proc$issuer_ls180.v:156043$8908 - assign { } { } - assign $0\logical_op__zero_a$38[0:0]$8909 \logical_op__zero_a$38$next - sync posedge \coresync_clk - update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$8909 - end - attribute \src "issuer_ls180.v:156045.3-156046.71" - process $proc$issuer_ls180.v:156045$8910 - assign { } { } - assign $0\logical_op__input_carry$39[1:0]$8911 \logical_op__input_carry$39$next - sync posedge \coresync_clk - update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$8911 - end - attribute \src "issuer_ls180.v:156047.3-156048.69" - process $proc$issuer_ls180.v:156047$8912 - assign { } { } - assign $0\logical_op__invert_out$40[0:0]$8913 \logical_op__invert_out$40$next - sync posedge \coresync_clk - update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$8913 - end - attribute \src "issuer_ls180.v:156049.3-156050.67" - process $proc$issuer_ls180.v:156049$8914 - assign { } { } - assign $0\logical_op__write_cr0$41[0:0]$8915 \logical_op__write_cr0$41$next - sync posedge \coresync_clk - update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$8915 - end - attribute \src "issuer_ls180.v:156051.3-156052.73" - process $proc$issuer_ls180.v:156051$8916 - assign { } { } - assign $0\logical_op__output_carry$42[0:0]$8917 \logical_op__output_carry$42$next - sync posedge \coresync_clk - update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$8917 - end - attribute \src "issuer_ls180.v:156053.3-156054.65" - process $proc$issuer_ls180.v:156053$8918 - assign { } { } - assign $0\logical_op__is_32bit$43[0:0]$8919 \logical_op__is_32bit$43$next - sync posedge \coresync_clk - update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$8919 - end - attribute \src "issuer_ls180.v:156055.3-156056.67" - process $proc$issuer_ls180.v:156055$8920 - assign { } { } - assign $0\logical_op__is_signed$44[0:0]$8921 \logical_op__is_signed$44$next - sync posedge \coresync_clk - update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$8921 - end - attribute \src "issuer_ls180.v:156057.3-156058.65" - process $proc$issuer_ls180.v:156057$8922 - assign { } { } - assign $0\logical_op__data_len$45[3:0]$8923 \logical_op__data_len$45$next - sync posedge \coresync_clk - update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$8923 - end - attribute \src "issuer_ls180.v:156059.3-156060.57" - process $proc$issuer_ls180.v:156059$8924 - assign { } { } - assign $0\logical_op__insn$46[31:0]$8925 \logical_op__insn$46$next - sync posedge \coresync_clk - update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$8925 - end - attribute \src "issuer_ls180.v:156061.3-156062.35" - process $proc$issuer_ls180.v:156061$8926 - assign { } { } - assign $0\muxid$28[1:0]$8927 \muxid$28$next - sync posedge \coresync_clk - update \muxid$28 $0\muxid$28[1:0]$8927 - end - attribute \src "issuer_ls180.v:156063.3-156064.27" - process $proc$issuer_ls180.v:156063$8928 - assign { } { } - assign $0\empty[0:0] \empty$next - sync posedge \coresync_clk - update \empty $0\empty[0:0] - end - attribute \src "issuer_ls180.v:156065.3-156066.75" - process $proc$issuer_ls180.v:156065$8929 - assign { } { } - assign $0\saved_state_dividend_quotient[127:0] \saved_state_dividend_quotient$next - sync posedge \coresync_clk - update \saved_state_dividend_quotient $0\saved_state_dividend_quotient[127:0] - end - attribute \src "issuer_ls180.v:156067.3-156068.65" - process $proc$issuer_ls180.v:156067$8930 - assign { } { } - assign $0\saved_state_q_bits_known[6:0] \saved_state_q_bits_known$next - sync posedge \coresync_clk - update \saved_state_q_bits_known $0\saved_state_q_bits_known[6:0] - end - attribute \src "issuer_ls180.v:156089.3-156097.6" - process $proc$issuer_ls180.v:156089$8931 - assign { } { } - assign { } { } - assign $0\saved_state_q_bits_known$next[6:0]$8932 $1\saved_state_q_bits_known$next[6:0]$8933 - attribute \src "issuer_ls180.v:156090.5-156090.29" - switch \initial - attribute \src "issuer_ls180.v:156090.9-156090.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\saved_state_q_bits_known$next[6:0]$8933 7'0000000 - case - assign $1\saved_state_q_bits_known$next[6:0]$8933 \div_state_next_o_q_bits_known - end - sync always - update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$8932 - end - attribute \src "issuer_ls180.v:156098.3-156106.6" - process $proc$issuer_ls180.v:156098$8934 - assign { } { } - assign { } { } - assign $0\saved_state_dividend_quotient$next[127:0]$8935 $1\saved_state_dividend_quotient$next[127:0]$8936 - attribute \src "issuer_ls180.v:156099.5-156099.29" - switch \initial - attribute \src "issuer_ls180.v:156099.9-156099.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\saved_state_dividend_quotient$next[127:0]$8936 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - case - assign $1\saved_state_dividend_quotient$next[127:0]$8936 \div_state_next_o_dividend_quotient - end - sync always - update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$8935 - end - attribute \src "issuer_ls180.v:156107.3-156118.6" - process $proc$issuer_ls180.v:156107$8937 - assign { } { } - assign $0\div_state_next_i_q_bits_known[6:0] $1\div_state_next_i_q_bits_known[6:0] - attribute \src "issuer_ls180.v:156108.5-156108.29" - switch \initial - attribute \src "issuer_ls180.v:156108.9-156108.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" - switch \empty - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\div_state_next_i_q_bits_known[6:0] \div_state_init_o_q_bits_known - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\div_state_next_i_q_bits_known[6:0] \saved_state_q_bits_known - end - sync always - update \div_state_next_i_q_bits_known $0\div_state_next_i_q_bits_known[6:0] - end - attribute \src "issuer_ls180.v:156119.3-156130.6" - process $proc$issuer_ls180.v:156119$8938 - assign { } { } - assign $0\div_state_next_i_dividend_quotient[127:0] $1\div_state_next_i_dividend_quotient[127:0] - attribute \src "issuer_ls180.v:156120.5-156120.29" - switch \initial - attribute \src "issuer_ls180.v:156120.9-156120.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" - switch \empty - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\div_state_next_i_dividend_quotient[127:0] \div_state_init_o_dividend_quotient - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\div_state_next_i_dividend_quotient[127:0] \saved_state_dividend_quotient - end - sync always - update \div_state_next_i_dividend_quotient $0\div_state_next_i_dividend_quotient[127:0] - end - attribute \src "issuer_ls180.v:156131.3-156142.6" - process $proc$issuer_ls180.v:156131$8939 - assign { } { } - assign $0\div_state_next_divisor[63:0] $1\div_state_next_divisor[63:0] - attribute \src "issuer_ls180.v:156132.5-156132.29" - switch \initial - attribute \src "issuer_ls180.v:156132.9-156132.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" - switch \empty - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\div_state_next_divisor[63:0] \divisor_radicand - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\div_state_next_divisor[63:0] \divisor_radicand$65 - end - sync always - update \div_state_next_divisor $0\div_state_next_divisor[63:0] - end - attribute \src "issuer_ls180.v:156143.3-156170.6" - process $proc$issuer_ls180.v:156143$8940 - assign { } { } - assign { } { } - assign { } { } - assign $0\empty$next[0:0]$8941 $4\empty$next[0:0]$8945 - attribute \src "issuer_ls180.v:156144.5-156144.29" - switch \initial - attribute \src "issuer_ls180.v:156144.9-156144.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" - switch \empty - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\empty$next[0:0]$8942 $2\empty$next[0:0]$8943 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" - switch \p_valid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\empty$next[0:0]$8943 1'0 - case - assign $2\empty$next[0:0]$8943 \empty - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\empty$next[0:0]$8942 $3\empty$next[0:0]$8944 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:177" - switch \$66 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\empty$next[0:0]$8944 1'1 - case - assign $3\empty$next[0:0]$8944 \empty - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\empty$next[0:0]$8945 1'1 - case - assign $4\empty$next[0:0]$8945 $1\empty$next[0:0]$8942 - end - sync always - update \empty$next $0\empty$next[0:0]$8941 - end - attribute \src "issuer_ls180.v:156171.3-156185.6" - process $proc$issuer_ls180.v:156171$8946 - assign { } { } - assign { } { } - assign $0\muxid$28$next[1:0]$8947 $1\muxid$28$next[1:0]$8948 - attribute \src "issuer_ls180.v:156172.5-156172.29" - switch \initial - attribute \src "issuer_ls180.v:156172.9-156172.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" - switch \empty - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\muxid$28$next[1:0]$8948 $2\muxid$28$next[1:0]$8949 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" - switch \p_valid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\muxid$28$next[1:0]$8949 \muxid - case - assign $2\muxid$28$next[1:0]$8949 \muxid$28 - end - case - assign $1\muxid$28$next[1:0]$8948 \muxid$28 - end - sync always - update \muxid$28$next $0\muxid$28$next[1:0]$8947 - end - attribute \src "issuer_ls180.v:156186.3-156229.6" - process $proc$issuer_ls180.v:156186$8950 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\logical_op__data_len$45$next[3:0]$8951 $1\logical_op__data_len$45$next[3:0]$8969 - assign $0\logical_op__fn_unit$30$next[11:0]$8952 $1\logical_op__fn_unit$30$next[11:0]$8970 - assign { } { } - assign { } { } - assign $0\logical_op__input_carry$39$next[1:0]$8955 $1\logical_op__input_carry$39$next[1:0]$8973 - assign $0\logical_op__insn$46$next[31:0]$8956 $1\logical_op__insn$46$next[31:0]$8974 - assign $0\logical_op__insn_type$29$next[6:0]$8957 $1\logical_op__insn_type$29$next[6:0]$8975 - assign $0\logical_op__invert_in$37$next[0:0]$8958 $1\logical_op__invert_in$37$next[0:0]$8976 - assign $0\logical_op__invert_out$40$next[0:0]$8959 $1\logical_op__invert_out$40$next[0:0]$8977 - assign $0\logical_op__is_32bit$43$next[0:0]$8960 $1\logical_op__is_32bit$43$next[0:0]$8978 - assign $0\logical_op__is_signed$44$next[0:0]$8961 $1\logical_op__is_signed$44$next[0:0]$8979 - assign { } { } - assign { } { } - assign $0\logical_op__output_carry$42$next[0:0]$8964 $1\logical_op__output_carry$42$next[0:0]$8982 - assign { } { } - assign { } { } - assign $0\logical_op__write_cr0$41$next[0:0]$8967 $1\logical_op__write_cr0$41$next[0:0]$8985 - assign $0\logical_op__zero_a$38$next[0:0]$8968 $1\logical_op__zero_a$38$next[0:0]$8986 - assign $0\logical_op__imm_data__data$31$next[63:0]$8953 $3\logical_op__imm_data__data$31$next[63:0]$9005 - assign $0\logical_op__imm_data__ok$32$next[0:0]$8954 $3\logical_op__imm_data__ok$32$next[0:0]$9006 - assign $0\logical_op__oe__oe$35$next[0:0]$8962 $3\logical_op__oe__oe$35$next[0:0]$9007 - assign $0\logical_op__oe__ok$36$next[0:0]$8963 $3\logical_op__oe__ok$36$next[0:0]$9008 - assign $0\logical_op__rc__ok$34$next[0:0]$8965 $3\logical_op__rc__ok$34$next[0:0]$9009 - assign $0\logical_op__rc__rc$33$next[0:0]$8966 $3\logical_op__rc__rc$33$next[0:0]$9010 - attribute \src "issuer_ls180.v:156187.5-156187.29" - switch \initial - attribute \src "issuer_ls180.v:156187.9-156187.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" - switch \empty - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\logical_op__data_len$45$next[3:0]$8969 $2\logical_op__data_len$45$next[3:0]$8987 - assign $1\logical_op__fn_unit$30$next[11:0]$8970 $2\logical_op__fn_unit$30$next[11:0]$8988 - assign $1\logical_op__imm_data__data$31$next[63:0]$8971 $2\logical_op__imm_data__data$31$next[63:0]$8989 - assign $1\logical_op__imm_data__ok$32$next[0:0]$8972 $2\logical_op__imm_data__ok$32$next[0:0]$8990 - assign $1\logical_op__input_carry$39$next[1:0]$8973 $2\logical_op__input_carry$39$next[1:0]$8991 - assign $1\logical_op__insn$46$next[31:0]$8974 $2\logical_op__insn$46$next[31:0]$8992 - assign $1\logical_op__insn_type$29$next[6:0]$8975 $2\logical_op__insn_type$29$next[6:0]$8993 - assign $1\logical_op__invert_in$37$next[0:0]$8976 $2\logical_op__invert_in$37$next[0:0]$8994 - assign $1\logical_op__invert_out$40$next[0:0]$8977 $2\logical_op__invert_out$40$next[0:0]$8995 - assign $1\logical_op__is_32bit$43$next[0:0]$8978 $2\logical_op__is_32bit$43$next[0:0]$8996 - assign $1\logical_op__is_signed$44$next[0:0]$8979 $2\logical_op__is_signed$44$next[0:0]$8997 - assign $1\logical_op__oe__oe$35$next[0:0]$8980 $2\logical_op__oe__oe$35$next[0:0]$8998 - assign $1\logical_op__oe__ok$36$next[0:0]$8981 $2\logical_op__oe__ok$36$next[0:0]$8999 - assign $1\logical_op__output_carry$42$next[0:0]$8982 $2\logical_op__output_carry$42$next[0:0]$9000 - assign $1\logical_op__rc__ok$34$next[0:0]$8983 $2\logical_op__rc__ok$34$next[0:0]$9001 - assign $1\logical_op__rc__rc$33$next[0:0]$8984 $2\logical_op__rc__rc$33$next[0:0]$9002 - assign $1\logical_op__write_cr0$41$next[0:0]$8985 $2\logical_op__write_cr0$41$next[0:0]$9003 - assign $1\logical_op__zero_a$38$next[0:0]$8986 $2\logical_op__zero_a$38$next[0:0]$9004 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" - switch \p_valid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $2\logical_op__insn$46$next[31:0]$8992 $2\logical_op__data_len$45$next[3:0]$8987 $2\logical_op__is_signed$44$next[0:0]$8997 $2\logical_op__is_32bit$43$next[0:0]$8996 $2\logical_op__output_carry$42$next[0:0]$9000 $2\logical_op__write_cr0$41$next[0:0]$9003 $2\logical_op__invert_out$40$next[0:0]$8995 $2\logical_op__input_carry$39$next[1:0]$8991 $2\logical_op__zero_a$38$next[0:0]$9004 $2\logical_op__invert_in$37$next[0:0]$8994 $2\logical_op__oe__ok$36$next[0:0]$8999 $2\logical_op__oe__oe$35$next[0:0]$8998 $2\logical_op__rc__ok$34$next[0:0]$9001 $2\logical_op__rc__rc$33$next[0:0]$9002 $2\logical_op__imm_data__ok$32$next[0:0]$8990 $2\logical_op__imm_data__data$31$next[63:0]$8989 $2\logical_op__fn_unit$30$next[11:0]$8988 $2\logical_op__insn_type$29$next[6:0]$8993 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - case - assign $2\logical_op__data_len$45$next[3:0]$8987 \logical_op__data_len$45 - assign $2\logical_op__fn_unit$30$next[11:0]$8988 \logical_op__fn_unit$30 - assign $2\logical_op__imm_data__data$31$next[63:0]$8989 \logical_op__imm_data__data$31 - assign $2\logical_op__imm_data__ok$32$next[0:0]$8990 \logical_op__imm_data__ok$32 - assign $2\logical_op__input_carry$39$next[1:0]$8991 \logical_op__input_carry$39 - assign $2\logical_op__insn$46$next[31:0]$8992 \logical_op__insn$46 - assign $2\logical_op__insn_type$29$next[6:0]$8993 \logical_op__insn_type$29 - assign $2\logical_op__invert_in$37$next[0:0]$8994 \logical_op__invert_in$37 - assign $2\logical_op__invert_out$40$next[0:0]$8995 \logical_op__invert_out$40 - assign $2\logical_op__is_32bit$43$next[0:0]$8996 \logical_op__is_32bit$43 - assign $2\logical_op__is_signed$44$next[0:0]$8997 \logical_op__is_signed$44 - assign $2\logical_op__oe__oe$35$next[0:0]$8998 \logical_op__oe__oe$35 - assign $2\logical_op__oe__ok$36$next[0:0]$8999 \logical_op__oe__ok$36 - assign $2\logical_op__output_carry$42$next[0:0]$9000 \logical_op__output_carry$42 - assign $2\logical_op__rc__ok$34$next[0:0]$9001 \logical_op__rc__ok$34 - assign $2\logical_op__rc__rc$33$next[0:0]$9002 \logical_op__rc__rc$33 - assign $2\logical_op__write_cr0$41$next[0:0]$9003 \logical_op__write_cr0$41 - assign $2\logical_op__zero_a$38$next[0:0]$9004 \logical_op__zero_a$38 - end - case - assign $1\logical_op__data_len$45$next[3:0]$8969 \logical_op__data_len$45 - assign $1\logical_op__fn_unit$30$next[11:0]$8970 \logical_op__fn_unit$30 - assign $1\logical_op__imm_data__data$31$next[63:0]$8971 \logical_op__imm_data__data$31 - assign $1\logical_op__imm_data__ok$32$next[0:0]$8972 \logical_op__imm_data__ok$32 - assign $1\logical_op__input_carry$39$next[1:0]$8973 \logical_op__input_carry$39 - assign $1\logical_op__insn$46$next[31:0]$8974 \logical_op__insn$46 - assign $1\logical_op__insn_type$29$next[6:0]$8975 \logical_op__insn_type$29 - assign $1\logical_op__invert_in$37$next[0:0]$8976 \logical_op__invert_in$37 - assign $1\logical_op__invert_out$40$next[0:0]$8977 \logical_op__invert_out$40 - assign $1\logical_op__is_32bit$43$next[0:0]$8978 \logical_op__is_32bit$43 - assign $1\logical_op__is_signed$44$next[0:0]$8979 \logical_op__is_signed$44 - assign $1\logical_op__oe__oe$35$next[0:0]$8980 \logical_op__oe__oe$35 - assign $1\logical_op__oe__ok$36$next[0:0]$8981 \logical_op__oe__ok$36 - assign $1\logical_op__output_carry$42$next[0:0]$8982 \logical_op__output_carry$42 - assign $1\logical_op__rc__ok$34$next[0:0]$8983 \logical_op__rc__ok$34 - assign $1\logical_op__rc__rc$33$next[0:0]$8984 \logical_op__rc__rc$33 - assign $1\logical_op__write_cr0$41$next[0:0]$8985 \logical_op__write_cr0$41 - assign $1\logical_op__zero_a$38$next[0:0]$8986 \logical_op__zero_a$38 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $3\logical_op__imm_data__data$31$next[63:0]$9005 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\logical_op__imm_data__ok$32$next[0:0]$9006 1'0 - assign $3\logical_op__rc__rc$33$next[0:0]$9010 1'0 - assign $3\logical_op__rc__ok$34$next[0:0]$9009 1'0 - assign $3\logical_op__oe__oe$35$next[0:0]$9007 1'0 - assign $3\logical_op__oe__ok$36$next[0:0]$9008 1'0 - case - assign $3\logical_op__imm_data__data$31$next[63:0]$9005 $1\logical_op__imm_data__data$31$next[63:0]$8971 - assign $3\logical_op__imm_data__ok$32$next[0:0]$9006 $1\logical_op__imm_data__ok$32$next[0:0]$8972 - assign $3\logical_op__oe__oe$35$next[0:0]$9007 $1\logical_op__oe__oe$35$next[0:0]$8980 - assign $3\logical_op__oe__ok$36$next[0:0]$9008 $1\logical_op__oe__ok$36$next[0:0]$8981 - assign $3\logical_op__rc__ok$34$next[0:0]$9009 $1\logical_op__rc__ok$34$next[0:0]$8983 - assign $3\logical_op__rc__rc$33$next[0:0]$9010 $1\logical_op__rc__rc$33$next[0:0]$8984 - end - sync always - update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$8951 - update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[11:0]$8952 - update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$8953 - update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$8954 - update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$8955 - update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$8956 - update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$8957 - update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$8958 - update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$8959 - update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$8960 - update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$8961 - update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$8962 - update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$8963 - update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$8964 - update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$8965 - update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$8966 - update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$8967 - update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$8968 - end - attribute \src "issuer_ls180.v:156230.3-156244.6" - process $proc$issuer_ls180.v:156230$9011 - assign { } { } - assign { } { } - assign $0\ra$47$next[63:0]$9012 $1\ra$47$next[63:0]$9013 - attribute \src "issuer_ls180.v:156231.5-156231.29" - switch \initial - attribute \src "issuer_ls180.v:156231.9-156231.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" - switch \empty - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ra$47$next[63:0]$9013 $2\ra$47$next[63:0]$9014 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" - switch \p_valid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ra$47$next[63:0]$9014 \ra - case - assign $2\ra$47$next[63:0]$9014 \ra$47 - end - case - assign $1\ra$47$next[63:0]$9013 \ra$47 - end - sync always - update \ra$47$next $0\ra$47$next[63:0]$9012 - end - attribute \src "issuer_ls180.v:156245.3-156259.6" - process $proc$issuer_ls180.v:156245$9015 - assign { } { } - assign { } { } - assign $0\rb$48$next[63:0]$9016 $1\rb$48$next[63:0]$9017 - attribute \src "issuer_ls180.v:156246.5-156246.29" - switch \initial - attribute \src "issuer_ls180.v:156246.9-156246.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" - switch \empty - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rb$48$next[63:0]$9017 $2\rb$48$next[63:0]$9018 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" - switch \p_valid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\rb$48$next[63:0]$9018 \rb - case - assign $2\rb$48$next[63:0]$9018 \rb$48 - end - case - assign $1\rb$48$next[63:0]$9017 \rb$48 - end - sync always - update \rb$48$next $0\rb$48$next[63:0]$9016 - end - attribute \src "issuer_ls180.v:156260.3-156274.6" - process $proc$issuer_ls180.v:156260$9019 - assign { } { } - assign { } { } - assign $0\xer_so$49$next[0:0]$9020 $1\xer_so$49$next[0:0]$9021 - attribute \src "issuer_ls180.v:156261.5-156261.29" - switch \initial - attribute \src "issuer_ls180.v:156261.9-156261.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" - switch \empty - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\xer_so$49$next[0:0]$9021 $2\xer_so$49$next[0:0]$9022 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" - switch \p_valid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_so$49$next[0:0]$9022 \xer_so - case - assign $2\xer_so$49$next[0:0]$9022 \xer_so$49 - end - case - assign $1\xer_so$49$next[0:0]$9021 \xer_so$49 - end - sync always - update \xer_so$49$next $0\xer_so$49$next[0:0]$9020 - end - attribute \src "issuer_ls180.v:156275.3-156289.6" - process $proc$issuer_ls180.v:156275$9023 - assign { } { } - assign { } { } - assign $0\divisor_neg$50$next[0:0]$9024 $1\divisor_neg$50$next[0:0]$9025 - attribute \src "issuer_ls180.v:156276.5-156276.29" - switch \initial - attribute \src "issuer_ls180.v:156276.9-156276.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" - switch \empty - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\divisor_neg$50$next[0:0]$9025 $2\divisor_neg$50$next[0:0]$9026 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" - switch \p_valid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\divisor_neg$50$next[0:0]$9026 \divisor_neg - case - assign $2\divisor_neg$50$next[0:0]$9026 \divisor_neg$50 - end - case - assign $1\divisor_neg$50$next[0:0]$9025 \divisor_neg$50 - end - sync always - update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$9024 - end - attribute \src "issuer_ls180.v:156290.3-156304.6" - process $proc$issuer_ls180.v:156290$9027 - assign { } { } - assign { } { } - assign $0\dividend_neg$51$next[0:0]$9028 $1\dividend_neg$51$next[0:0]$9029 - attribute \src "issuer_ls180.v:156291.5-156291.29" - switch \initial - attribute \src "issuer_ls180.v:156291.9-156291.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" - switch \empty - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dividend_neg$51$next[0:0]$9029 $2\dividend_neg$51$next[0:0]$9030 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" - switch \p_valid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dividend_neg$51$next[0:0]$9030 \dividend_neg - case - assign $2\dividend_neg$51$next[0:0]$9030 \dividend_neg$51 - end - case - assign $1\dividend_neg$51$next[0:0]$9029 \dividend_neg$51 - end - sync always - update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$9028 - end - attribute \src "issuer_ls180.v:156305.3-156319.6" - process $proc$issuer_ls180.v:156305$9031 - assign { } { } - assign { } { } - assign $0\dive_abs_ov32$52$next[0:0]$9032 $1\dive_abs_ov32$52$next[0:0]$9033 - attribute \src "issuer_ls180.v:156306.5-156306.29" - switch \initial - attribute \src "issuer_ls180.v:156306.9-156306.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" - switch \empty - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dive_abs_ov32$52$next[0:0]$9033 $2\dive_abs_ov32$52$next[0:0]$9034 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" - switch \p_valid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dive_abs_ov32$52$next[0:0]$9034 \dive_abs_ov32 - case - assign $2\dive_abs_ov32$52$next[0:0]$9034 \dive_abs_ov32$52 - end - case - assign $1\dive_abs_ov32$52$next[0:0]$9033 \dive_abs_ov32$52 - end - sync always - update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$9032 - end - attribute \src "issuer_ls180.v:156320.3-156334.6" - process $proc$issuer_ls180.v:156320$9035 - assign { } { } - assign { } { } - assign $0\dive_abs_ov64$53$next[0:0]$9036 $1\dive_abs_ov64$53$next[0:0]$9037 - attribute \src "issuer_ls180.v:156321.5-156321.29" - switch \initial - attribute \src "issuer_ls180.v:156321.9-156321.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" - switch \empty - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dive_abs_ov64$53$next[0:0]$9037 $2\dive_abs_ov64$53$next[0:0]$9038 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" - switch \p_valid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dive_abs_ov64$53$next[0:0]$9038 \dive_abs_ov64 - case - assign $2\dive_abs_ov64$53$next[0:0]$9038 \dive_abs_ov64$53 - end - case - assign $1\dive_abs_ov64$53$next[0:0]$9037 \dive_abs_ov64$53 - end - sync always - update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$9036 - end - attribute \src "issuer_ls180.v:156335.3-156349.6" - process $proc$issuer_ls180.v:156335$9039 - assign { } { } - assign { } { } - assign $0\div_by_zero$54$next[0:0]$9040 $1\div_by_zero$54$next[0:0]$9041 - attribute \src "issuer_ls180.v:156336.5-156336.29" - switch \initial - attribute \src "issuer_ls180.v:156336.9-156336.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" - switch \empty - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\div_by_zero$54$next[0:0]$9041 $2\div_by_zero$54$next[0:0]$9042 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" - switch \p_valid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\div_by_zero$54$next[0:0]$9042 \div_by_zero - case - assign $2\div_by_zero$54$next[0:0]$9042 \div_by_zero$54 - end - case - assign $1\div_by_zero$54$next[0:0]$9041 \div_by_zero$54 - end - sync always - update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$9040 - end - attribute \src "issuer_ls180.v:156350.3-156364.6" - process $proc$issuer_ls180.v:156350$9043 - assign { } { } - assign { } { } - assign $0\dividend$68$next[127:0]$9044 $1\dividend$68$next[127:0]$9045 - attribute \src "issuer_ls180.v:156351.5-156351.29" - switch \initial - attribute \src "issuer_ls180.v:156351.9-156351.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" - switch \empty - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dividend$68$next[127:0]$9045 $2\dividend$68$next[127:0]$9046 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" - switch \p_valid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dividend$68$next[127:0]$9046 \dividend - case - assign $2\dividend$68$next[127:0]$9046 \dividend$68 - end - case - assign $1\dividend$68$next[127:0]$9045 \dividend$68 - end - sync always - update \dividend$68$next $0\dividend$68$next[127:0]$9044 - end - attribute \src "issuer_ls180.v:156365.3-156379.6" - process $proc$issuer_ls180.v:156365$9047 - assign { } { } - assign { } { } - assign $0\divisor_radicand$65$next[63:0]$9048 $1\divisor_radicand$65$next[63:0]$9049 - attribute \src "issuer_ls180.v:156366.5-156366.29" - switch \initial - attribute \src "issuer_ls180.v:156366.9-156366.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" - switch \empty - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\divisor_radicand$65$next[63:0]$9049 $2\divisor_radicand$65$next[63:0]$9050 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" - switch \p_valid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\divisor_radicand$65$next[63:0]$9050 \divisor_radicand - case - assign $2\divisor_radicand$65$next[63:0]$9050 \divisor_radicand$65 - end - case - assign $1\divisor_radicand$65$next[63:0]$9049 \divisor_radicand$65 - end - sync always - update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$9048 - end - attribute \src "issuer_ls180.v:156380.3-156394.6" - process $proc$issuer_ls180.v:156380$9051 - assign { } { } - assign { } { } - assign $0\operation$69$next[1:0]$9052 $1\operation$69$next[1:0]$9053 - attribute \src "issuer_ls180.v:156381.5-156381.29" - switch \initial - attribute \src "issuer_ls180.v:156381.9-156381.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" - switch \empty - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\operation$69$next[1:0]$9053 $2\operation$69$next[1:0]$9054 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" - switch \p_valid_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\operation$69$next[1:0]$9054 \operation - case - assign $2\operation$69$next[1:0]$9054 \operation$69 - end - case - assign $1\operation$69$next[1:0]$9053 \operation$69 - end - sync always - update \operation$69$next $0\operation$69$next[1:0]$9052 - end - connect \$56 $sshl$issuer_ls180.v:155997$8861_Y - connect \$55 $pos$issuer_ls180.v:155998$8863_Y - connect \$59 $not$issuer_ls180.v:155999$8864_Y - connect \$61 $eq$issuer_ls180.v:156000$8865_Y - connect \$63 $and$issuer_ls180.v:156001$8866_Y - connect \$66 $and$issuer_ls180.v:156002$8867_Y - connect \p_ready_o \empty - connect \n_valid_o \$63 - connect \remainder \$55 - connect \quotient_root \div_state_next_o_dividend_quotient [63:0] - connect \div_by_zero$27 \div_by_zero$54 - connect \dive_abs_ov64$26 \dive_abs_ov64$53 - connect \dive_abs_ov32$25 \dive_abs_ov32$52 - connect \dividend_neg$24 \dividend_neg$51 - connect \divisor_neg$23 \divisor_neg$50 - connect \xer_so$22 \xer_so$49 - connect \rb$21 \rb$48 - connect \ra$20 \ra$47 - connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn$46 \logical_op__data_len$45 \logical_op__is_signed$44 \logical_op__is_32bit$43 \logical_op__output_carry$42 \logical_op__write_cr0$41 \logical_op__invert_out$40 \logical_op__input_carry$39 \logical_op__zero_a$38 \logical_op__invert_in$37 \logical_op__oe__ok$36 \logical_op__oe__oe$35 \logical_op__rc__ok$34 \logical_op__rc__rc$33 \logical_op__imm_data__ok$32 \logical_op__imm_data__data$31 \logical_op__fn_unit$30 \logical_op__insn_type$29 } - connect \muxid$1 \muxid$28 - connect \div_state_init_dividend \dividend -end -attribute \src "issuer_ls180.v:156414.1-157938.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start" -attribute \generator "nMigen" -module \pipe_start - attribute \src "issuer_ls180.v:157744.3-157756.6" - wire $0\div_by_zero$next[0:0]$9164 - attribute \src "issuer_ls180.v:157530.3-157531.39" - wire $0\div_by_zero[0:0] - attribute \src "issuer_ls180.v:157718.3-157730.6" - wire $0\dive_abs_ov32$next[0:0]$9158 - attribute \src "issuer_ls180.v:157534.3-157535.43" - wire $0\dive_abs_ov32[0:0] - attribute \src "issuer_ls180.v:157731.3-157743.6" - wire $0\dive_abs_ov64$next[0:0]$9161 - attribute \src "issuer_ls180.v:157532.3-157533.43" - wire $0\dive_abs_ov64[0:0] - attribute \src "issuer_ls180.v:157757.3-157769.6" - wire width 128 $0\dividend$next[127:0]$9167 - attribute \src "issuer_ls180.v:157528.3-157529.33" - wire width 128 $0\dividend[127:0] - attribute \src "issuer_ls180.v:157705.3-157717.6" - wire $0\dividend_neg$next[0:0]$9155 - attribute \src "issuer_ls180.v:157536.3-157537.41" - wire $0\dividend_neg[0:0] - attribute \src "issuer_ls180.v:157692.3-157704.6" - wire $0\divisor_neg$next[0:0]$9152 - attribute \src "issuer_ls180.v:157538.3-157539.39" - wire $0\divisor_neg[0:0] - attribute \src "issuer_ls180.v:157770.3-157782.6" - wire width 64 $0\divisor_radicand$next[63:0]$9170 - attribute \src "issuer_ls180.v:157526.3-157527.49" - wire width 64 $0\divisor_radicand[63:0] - attribute \src "issuer_ls180.v:156415.7-156415.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire width 4 $0\logical_op__data_len$next[3:0]$9183 - attribute \src "issuer_ls180.v:157578.3-157579.57" - wire width 4 $0\logical_op__data_len[3:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire width 12 $0\logical_op__fn_unit$next[11:0]$9184 - attribute \src "issuer_ls180.v:157548.3-157549.55" - wire width 12 $0\logical_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire width 64 $0\logical_op__imm_data__data$next[63:0]$9185 - attribute \src "issuer_ls180.v:157550.3-157551.69" - wire width 64 $0\logical_op__imm_data__data[63:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $0\logical_op__imm_data__ok$next[0:0]$9186 - attribute \src "issuer_ls180.v:157552.3-157553.65" - wire $0\logical_op__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire width 2 $0\logical_op__input_carry$next[1:0]$9187 - attribute \src "issuer_ls180.v:157566.3-157567.63" - wire width 2 $0\logical_op__input_carry[1:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire width 32 $0\logical_op__insn$next[31:0]$9188 - attribute \src "issuer_ls180.v:157580.3-157581.49" - wire width 32 $0\logical_op__insn[31:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire width 7 $0\logical_op__insn_type$next[6:0]$9189 - attribute \src "issuer_ls180.v:157546.3-157547.59" - wire width 7 $0\logical_op__insn_type[6:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $0\logical_op__invert_in$next[0:0]$9190 - attribute \src "issuer_ls180.v:157562.3-157563.59" - wire $0\logical_op__invert_in[0:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $0\logical_op__invert_out$next[0:0]$9191 - attribute \src "issuer_ls180.v:157568.3-157569.61" - wire $0\logical_op__invert_out[0:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $0\logical_op__is_32bit$next[0:0]$9192 - attribute \src "issuer_ls180.v:157574.3-157575.57" - wire $0\logical_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $0\logical_op__is_signed$next[0:0]$9193 - attribute \src "issuer_ls180.v:157576.3-157577.59" - wire $0\logical_op__is_signed[0:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $0\logical_op__oe__oe$next[0:0]$9194 - attribute \src "issuer_ls180.v:157558.3-157559.53" - wire $0\logical_op__oe__oe[0:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $0\logical_op__oe__ok$next[0:0]$9195 - attribute \src "issuer_ls180.v:157560.3-157561.53" - wire $0\logical_op__oe__ok[0:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $0\logical_op__output_carry$next[0:0]$9196 - attribute \src "issuer_ls180.v:157572.3-157573.65" - wire $0\logical_op__output_carry[0:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $0\logical_op__rc__ok$next[0:0]$9197 - attribute \src "issuer_ls180.v:157556.3-157557.53" - wire $0\logical_op__rc__ok[0:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $0\logical_op__rc__rc$next[0:0]$9198 - attribute \src "issuer_ls180.v:157554.3-157555.53" - wire $0\logical_op__rc__rc[0:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $0\logical_op__write_cr0$next[0:0]$9199 - attribute \src "issuer_ls180.v:157570.3-157571.59" - wire $0\logical_op__write_cr0[0:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $0\logical_op__zero_a$next[0:0]$9200 - attribute \src "issuer_ls180.v:157564.3-157565.53" - wire $0\logical_op__zero_a[0:0] - attribute \src "issuer_ls180.v:157814.3-157826.6" - wire width 2 $0\muxid$next[1:0]$9180 - attribute \src "issuer_ls180.v:157582.3-157583.27" - wire width 2 $0\muxid[1:0] - attribute \src "issuer_ls180.v:157783.3-157795.6" - wire width 2 $0\operation$next[1:0]$9173 - attribute \src "issuer_ls180.v:157524.3-157525.35" - wire width 2 $0\operation[1:0] - attribute \src "issuer_ls180.v:157796.3-157813.6" - wire $0\r_busy$next[0:0]$9176 - attribute \src "issuer_ls180.v:157584.3-157585.29" - wire $0\r_busy[0:0] - attribute \src "issuer_ls180.v:157869.3-157881.6" - wire width 64 $0\ra$next[63:0]$9226 - attribute \src "issuer_ls180.v:157544.3-157545.21" - wire width 64 $0\ra[63:0] - attribute \src "issuer_ls180.v:157882.3-157894.6" - wire width 64 $0\rb$next[63:0]$9229 - attribute \src "issuer_ls180.v:157542.3-157543.21" - wire width 64 $0\rb[63:0] - attribute \src "issuer_ls180.v:157895.3-157907.6" - wire $0\xer_so$next[0:0]$9232 - attribute \src "issuer_ls180.v:157540.3-157541.29" - wire $0\xer_so[0:0] - attribute \src "issuer_ls180.v:157744.3-157756.6" - wire $1\div_by_zero$next[0:0]$9165 - attribute \src "issuer_ls180.v:156424.7-156424.25" - wire $1\div_by_zero[0:0] - attribute \src "issuer_ls180.v:157718.3-157730.6" - wire $1\dive_abs_ov32$next[0:0]$9159 - attribute \src "issuer_ls180.v:156431.7-156431.27" - wire $1\dive_abs_ov32[0:0] - attribute \src "issuer_ls180.v:157731.3-157743.6" - wire $1\dive_abs_ov64$next[0:0]$9162 - attribute \src "issuer_ls180.v:156438.7-156438.27" - wire $1\dive_abs_ov64[0:0] - attribute \src "issuer_ls180.v:157757.3-157769.6" - wire width 128 $1\dividend$next[127:0]$9168 - attribute \src "issuer_ls180.v:156445.15-156445.63" - wire width 128 $1\dividend[127:0] - attribute \src "issuer_ls180.v:157705.3-157717.6" - wire $1\dividend_neg$next[0:0]$9156 - attribute \src "issuer_ls180.v:156452.7-156452.26" - wire $1\dividend_neg[0:0] - attribute \src "issuer_ls180.v:157692.3-157704.6" - wire $1\divisor_neg$next[0:0]$9153 - attribute \src "issuer_ls180.v:156459.7-156459.25" - wire $1\divisor_neg[0:0] - attribute \src "issuer_ls180.v:157770.3-157782.6" - wire width 64 $1\divisor_radicand$next[63:0]$9171 - attribute \src "issuer_ls180.v:156466.14-156466.53" - wire width 64 $1\divisor_radicand[63:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire width 4 $1\logical_op__data_len$next[3:0]$9201 - attribute \src "issuer_ls180.v:156743.13-156743.40" - wire width 4 $1\logical_op__data_len[3:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire width 12 $1\logical_op__fn_unit$next[11:0]$9202 - attribute \src "issuer_ls180.v:156765.14-156765.43" - wire width 12 $1\logical_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire width 64 $1\logical_op__imm_data__data$next[63:0]$9203 - attribute \src "issuer_ls180.v:156800.14-156800.63" - wire width 64 $1\logical_op__imm_data__data[63:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $1\logical_op__imm_data__ok$next[0:0]$9204 - attribute \src "issuer_ls180.v:156809.7-156809.38" - wire $1\logical_op__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire width 2 $1\logical_op__input_carry$next[1:0]$9205 - attribute \src "issuer_ls180.v:156822.13-156822.43" - wire width 2 $1\logical_op__input_carry[1:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire width 32 $1\logical_op__insn$next[31:0]$9206 - attribute \src "issuer_ls180.v:156839.14-156839.38" - wire width 32 $1\logical_op__insn[31:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire width 7 $1\logical_op__insn_type$next[6:0]$9207 - attribute \src "issuer_ls180.v:156922.13-156922.42" - wire width 7 $1\logical_op__insn_type[6:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $1\logical_op__invert_in$next[0:0]$9208 - attribute \src "issuer_ls180.v:157079.7-157079.35" - wire $1\logical_op__invert_in[0:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $1\logical_op__invert_out$next[0:0]$9209 - attribute \src "issuer_ls180.v:157088.7-157088.36" - wire $1\logical_op__invert_out[0:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $1\logical_op__is_32bit$next[0:0]$9210 - attribute \src "issuer_ls180.v:157097.7-157097.34" - wire $1\logical_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $1\logical_op__is_signed$next[0:0]$9211 - attribute \src "issuer_ls180.v:157106.7-157106.35" - wire $1\logical_op__is_signed[0:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $1\logical_op__oe__oe$next[0:0]$9212 - attribute \src "issuer_ls180.v:157115.7-157115.32" - wire $1\logical_op__oe__oe[0:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $1\logical_op__oe__ok$next[0:0]$9213 - attribute \src "issuer_ls180.v:157124.7-157124.32" - wire $1\logical_op__oe__ok[0:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $1\logical_op__output_carry$next[0:0]$9214 - attribute \src "issuer_ls180.v:157133.7-157133.38" - wire $1\logical_op__output_carry[0:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $1\logical_op__rc__ok$next[0:0]$9215 - attribute \src "issuer_ls180.v:157142.7-157142.32" - wire $1\logical_op__rc__ok[0:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $1\logical_op__rc__rc$next[0:0]$9216 - attribute \src "issuer_ls180.v:157151.7-157151.32" - wire $1\logical_op__rc__rc[0:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $1\logical_op__write_cr0$next[0:0]$9217 - attribute \src "issuer_ls180.v:157160.7-157160.35" - wire $1\logical_op__write_cr0[0:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $1\logical_op__zero_a$next[0:0]$9218 - attribute \src "issuer_ls180.v:157169.7-157169.32" - wire $1\logical_op__zero_a[0:0] - attribute \src "issuer_ls180.v:157814.3-157826.6" - wire width 2 $1\muxid$next[1:0]$9181 - attribute \src "issuer_ls180.v:157178.13-157178.25" - wire width 2 $1\muxid[1:0] - attribute \src "issuer_ls180.v:157783.3-157795.6" - wire width 2 $1\operation$next[1:0]$9174 - attribute \src "issuer_ls180.v:157193.13-157193.29" - wire width 2 $1\operation[1:0] - attribute \src "issuer_ls180.v:157796.3-157813.6" - wire $1\r_busy$next[0:0]$9177 - attribute \src "issuer_ls180.v:157207.7-157207.20" - wire $1\r_busy[0:0] - attribute \src "issuer_ls180.v:157869.3-157881.6" - wire width 64 $1\ra$next[63:0]$9227 - attribute \src "issuer_ls180.v:157212.14-157212.39" - wire width 64 $1\ra[63:0] - attribute \src "issuer_ls180.v:157882.3-157894.6" - wire width 64 $1\rb$next[63:0]$9230 - attribute \src "issuer_ls180.v:157223.14-157223.39" - wire width 64 $1\rb[63:0] - attribute \src "issuer_ls180.v:157895.3-157907.6" - wire $1\xer_so$next[0:0]$9233 - attribute \src "issuer_ls180.v:157516.7-157516.20" - wire $1\xer_so[0:0] - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire width 64 $2\logical_op__imm_data__data$next[63:0]$9219 - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $2\logical_op__imm_data__ok$next[0:0]$9220 - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $2\logical_op__oe__oe$next[0:0]$9221 - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $2\logical_op__oe__ok$next[0:0]$9222 - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $2\logical_op__rc__ok$next[0:0]$9223 - attribute \src "issuer_ls180.v:157827.3-157868.6" - wire $2\logical_op__rc__rc$next[0:0]$9224 - attribute \src "issuer_ls180.v:157796.3-157813.6" - wire $2\r_busy$next[0:0]$9178 - attribute \src "issuer_ls180.v:157523.18-157523.118" - wire $and$issuer_ls180.v:157523$9119_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 58 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire output 30 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire \div_by_zero$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire \div_by_zero$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire output 28 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire \dive_abs_ov32$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire \dive_abs_ov32$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire output 29 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire \dive_abs_ov64$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire \dive_abs_ov64$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 output 31 \dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \dividend$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \dividend$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire output 27 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \dividend_neg$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \dividend_neg$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire output 26 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \divisor_neg$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \divisor_neg$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 output 32 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$next - attribute \src "issuer_ls180.v:156415.7-156415.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_logical_op__data_len$40 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - 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"OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 5 \logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 37 \logical_op__insn_type$2 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 45 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 48 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 51 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 52 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 43 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 44 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 18 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 50 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 42 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 41 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 49 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 46 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 36 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$68 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 3 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 output 33 \operation - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 35 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 34 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$65 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 23 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 55 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 24 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 56 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire \setup_stage_div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire \setup_stage_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire \setup_stage_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \setup_stage_dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \setup_stage_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \setup_stage_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \setup_stage_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \setup_stage_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \setup_stage_logical_op__data_len$62 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \setup_stage_logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute 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$proc$issuer_ls180.v:156415$9234 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:156424.7-156424.25" - process $proc$issuer_ls180.v:156424$9235 - assign { } { } - assign $1\div_by_zero[0:0] 1'0 - sync always - sync init - update \div_by_zero $1\div_by_zero[0:0] - end - attribute \src "issuer_ls180.v:156431.7-156431.27" - process $proc$issuer_ls180.v:156431$9236 - assign { } { } - assign $1\dive_abs_ov32[0:0] 1'0 - sync always - sync init - update \dive_abs_ov32 $1\dive_abs_ov32[0:0] - end - attribute \src "issuer_ls180.v:156438.7-156438.27" - process $proc$issuer_ls180.v:156438$9237 - assign { } { } - assign $1\dive_abs_ov64[0:0] 1'0 - sync always - sync init - update \dive_abs_ov64 $1\dive_abs_ov64[0:0] - end - attribute \src "issuer_ls180.v:156445.15-156445.63" - process $proc$issuer_ls180.v:156445$9238 - assign { } { } - assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dividend $1\dividend[127:0] - end - attribute \src "issuer_ls180.v:156452.7-156452.26" - process $proc$issuer_ls180.v:156452$9239 - assign { } { } - assign $1\dividend_neg[0:0] 1'0 - sync always - sync init - update \dividend_neg $1\dividend_neg[0:0] - end - attribute \src "issuer_ls180.v:156459.7-156459.25" - process $proc$issuer_ls180.v:156459$9240 - assign { } { } - assign $1\divisor_neg[0:0] 1'0 - sync always - sync init - update \divisor_neg $1\divisor_neg[0:0] - end - attribute \src "issuer_ls180.v:156466.14-156466.53" - process $proc$issuer_ls180.v:156466$9241 - assign { } { } - assign $1\divisor_radicand[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \divisor_radicand $1\divisor_radicand[63:0] - end - attribute \src "issuer_ls180.v:156743.13-156743.40" - process $proc$issuer_ls180.v:156743$9242 - assign { } { } - assign $1\logical_op__data_len[3:0] 4'0000 - sync always - sync init - update \logical_op__data_len $1\logical_op__data_len[3:0] - end - attribute \src "issuer_ls180.v:156765.14-156765.43" - process $proc$issuer_ls180.v:156765$9243 - assign { } { } - assign $1\logical_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \logical_op__fn_unit $1\logical_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:156800.14-156800.63" - process $proc$issuer_ls180.v:156800$9244 - assign { } { } - assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] - end - attribute \src "issuer_ls180.v:156809.7-156809.38" - process $proc$issuer_ls180.v:156809$9245 - assign { } { } - assign $1\logical_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:156822.13-156822.43" - process $proc$issuer_ls180.v:156822$9246 - assign { } { } - assign $1\logical_op__input_carry[1:0] 2'00 - sync always - sync init - update \logical_op__input_carry $1\logical_op__input_carry[1:0] - end - attribute \src "issuer_ls180.v:156839.14-156839.38" - process $proc$issuer_ls180.v:156839$9247 - assign { } { } - assign $1\logical_op__insn[31:0] 0 - sync always - sync init - update \logical_op__insn $1\logical_op__insn[31:0] - end - attribute \src "issuer_ls180.v:156922.13-156922.42" - process $proc$issuer_ls180.v:156922$9248 - assign { } { } - assign $1\logical_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \logical_op__insn_type $1\logical_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:157079.7-157079.35" - process $proc$issuer_ls180.v:157079$9249 - assign { } { } - assign $1\logical_op__invert_in[0:0] 1'0 - sync always - sync init - update \logical_op__invert_in $1\logical_op__invert_in[0:0] - end - attribute \src "issuer_ls180.v:157088.7-157088.36" - process $proc$issuer_ls180.v:157088$9250 - assign { } { } - assign $1\logical_op__invert_out[0:0] 1'0 - sync always - sync init - update \logical_op__invert_out $1\logical_op__invert_out[0:0] - end - attribute \src "issuer_ls180.v:157097.7-157097.34" - process $proc$issuer_ls180.v:157097$9251 - assign { } { } - assign $1\logical_op__is_32bit[0:0] 1'0 - sync always - sync init - update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:157106.7-157106.35" - process $proc$issuer_ls180.v:157106$9252 - assign { } { } - assign $1\logical_op__is_signed[0:0] 1'0 - sync always - sync init - update \logical_op__is_signed $1\logical_op__is_signed[0:0] - end - attribute \src "issuer_ls180.v:157115.7-157115.32" - process $proc$issuer_ls180.v:157115$9253 - assign { } { } - assign $1\logical_op__oe__oe[0:0] 1'0 - sync always - sync init - update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] - end - attribute \src "issuer_ls180.v:157124.7-157124.32" - process $proc$issuer_ls180.v:157124$9254 - assign { } { } - assign $1\logical_op__oe__ok[0:0] 1'0 - sync always - sync init - update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:157133.7-157133.38" - process $proc$issuer_ls180.v:157133$9255 - assign { } { } - assign $1\logical_op__output_carry[0:0] 1'0 - sync always - sync init - update \logical_op__output_carry $1\logical_op__output_carry[0:0] - end - attribute \src "issuer_ls180.v:157142.7-157142.32" - process $proc$issuer_ls180.v:157142$9256 - assign { } { } - assign $1\logical_op__rc__ok[0:0] 1'0 - sync always - sync init - update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] - end - attribute \src "issuer_ls180.v:157151.7-157151.32" - process $proc$issuer_ls180.v:157151$9257 - assign { } { } - assign $1\logical_op__rc__rc[0:0] 1'0 - sync always - sync init - update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:157160.7-157160.35" - process $proc$issuer_ls180.v:157160$9258 - assign { } { } - assign $1\logical_op__write_cr0[0:0] 1'0 - sync always - sync init - update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:157169.7-157169.32" - process $proc$issuer_ls180.v:157169$9259 - assign { } { } - assign $1\logical_op__zero_a[0:0] 1'0 - sync always - sync init - update \logical_op__zero_a $1\logical_op__zero_a[0:0] - end - attribute \src "issuer_ls180.v:157178.13-157178.25" - process $proc$issuer_ls180.v:157178$9260 - assign { } { } - assign $1\muxid[1:0] 2'00 - sync always - sync init - update \muxid $1\muxid[1:0] - end - attribute \src "issuer_ls180.v:157193.13-157193.29" - process $proc$issuer_ls180.v:157193$9261 - assign { } { } - assign $1\operation[1:0] 2'00 - sync always - sync init - update \operation $1\operation[1:0] - end - attribute \src "issuer_ls180.v:157207.7-157207.20" - process $proc$issuer_ls180.v:157207$9262 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "issuer_ls180.v:157212.14-157212.39" - process $proc$issuer_ls180.v:157212$9263 - assign { } { } - assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \ra $1\ra[63:0] - end - attribute \src "issuer_ls180.v:157223.14-157223.39" - process $proc$issuer_ls180.v:157223$9264 - assign { } { } - assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \rb $1\rb[63:0] - end - attribute \src "issuer_ls180.v:157516.7-157516.20" - process $proc$issuer_ls180.v:157516$9265 - assign { } { } - assign $1\xer_so[0:0] 1'0 - sync always - sync init - update \xer_so $1\xer_so[0:0] - end - attribute \src "issuer_ls180.v:157524.3-157525.35" - process $proc$issuer_ls180.v:157524$9120 - assign { } { } - assign $0\operation[1:0] \operation$next - sync posedge \coresync_clk - update \operation $0\operation[1:0] - end - attribute \src "issuer_ls180.v:157526.3-157527.49" - process $proc$issuer_ls180.v:157526$9121 - assign { } { } - assign $0\divisor_radicand[63:0] \divisor_radicand$next - sync posedge \coresync_clk - update \divisor_radicand $0\divisor_radicand[63:0] - end - attribute \src "issuer_ls180.v:157528.3-157529.33" - process $proc$issuer_ls180.v:157528$9122 - assign { } { } - assign $0\dividend[127:0] \dividend$next - sync posedge \coresync_clk - update \dividend $0\dividend[127:0] - end - attribute \src "issuer_ls180.v:157530.3-157531.39" - process $proc$issuer_ls180.v:157530$9123 - assign { } { } - assign $0\div_by_zero[0:0] \div_by_zero$next - sync posedge \coresync_clk - update \div_by_zero $0\div_by_zero[0:0] - end - attribute \src "issuer_ls180.v:157532.3-157533.43" - process $proc$issuer_ls180.v:157532$9124 - assign { } { } - assign $0\dive_abs_ov64[0:0] \dive_abs_ov64$next - sync posedge \coresync_clk - update \dive_abs_ov64 $0\dive_abs_ov64[0:0] - end - attribute \src "issuer_ls180.v:157534.3-157535.43" - process $proc$issuer_ls180.v:157534$9125 - assign { } { } - assign $0\dive_abs_ov32[0:0] \dive_abs_ov32$next - sync posedge \coresync_clk - update \dive_abs_ov32 $0\dive_abs_ov32[0:0] - end - attribute \src "issuer_ls180.v:157536.3-157537.41" - process $proc$issuer_ls180.v:157536$9126 - assign { } { } - assign $0\dividend_neg[0:0] \dividend_neg$next - sync posedge \coresync_clk - update \dividend_neg $0\dividend_neg[0:0] - end - attribute \src "issuer_ls180.v:157538.3-157539.39" - process $proc$issuer_ls180.v:157538$9127 - assign { } { } - assign $0\divisor_neg[0:0] \divisor_neg$next - sync posedge \coresync_clk - update \divisor_neg $0\divisor_neg[0:0] - end - attribute \src "issuer_ls180.v:157540.3-157541.29" - process $proc$issuer_ls180.v:157540$9128 - assign { } { } - assign $0\xer_so[0:0] \xer_so$next - sync posedge \coresync_clk - update \xer_so $0\xer_so[0:0] - end - attribute \src "issuer_ls180.v:157542.3-157543.21" - process $proc$issuer_ls180.v:157542$9129 - assign { } { } - assign $0\rb[63:0] \rb$next - sync posedge \coresync_clk - update \rb $0\rb[63:0] - end - attribute \src "issuer_ls180.v:157544.3-157545.21" - process $proc$issuer_ls180.v:157544$9130 - assign { } { } - assign $0\ra[63:0] \ra$next - sync posedge \coresync_clk - update \ra $0\ra[63:0] - end - attribute \src "issuer_ls180.v:157546.3-157547.59" - process $proc$issuer_ls180.v:157546$9131 - assign { } { } - assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next - sync posedge \coresync_clk - update \logical_op__insn_type $0\logical_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:157548.3-157549.55" - process $proc$issuer_ls180.v:157548$9132 - assign { } { } - assign $0\logical_op__fn_unit[11:0] \logical_op__fn_unit$next - sync posedge \coresync_clk - update \logical_op__fn_unit $0\logical_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:157550.3-157551.69" - process $proc$issuer_ls180.v:157550$9133 - assign { } { } - assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next - sync posedge \coresync_clk - update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] - end - attribute \src "issuer_ls180.v:157552.3-157553.65" - process $proc$issuer_ls180.v:157552$9134 - assign { } { } - assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next - sync posedge \coresync_clk - update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:157554.3-157555.53" - process $proc$issuer_ls180.v:157554$9135 - assign { } { } - assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next - sync posedge \coresync_clk - update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:157556.3-157557.53" - process $proc$issuer_ls180.v:157556$9136 - assign { } { } - assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next - sync posedge \coresync_clk - update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] - end - attribute \src "issuer_ls180.v:157558.3-157559.53" - process $proc$issuer_ls180.v:157558$9137 - assign { } { } - assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next - sync posedge \coresync_clk - update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] - end - attribute \src "issuer_ls180.v:157560.3-157561.53" - process $proc$issuer_ls180.v:157560$9138 - assign { } { } - assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next - sync posedge \coresync_clk - update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:157562.3-157563.59" - process $proc$issuer_ls180.v:157562$9139 - assign { } { } - assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next - sync posedge \coresync_clk - update \logical_op__invert_in $0\logical_op__invert_in[0:0] - end - attribute \src "issuer_ls180.v:157564.3-157565.53" - process $proc$issuer_ls180.v:157564$9140 - assign { } { } - assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next - sync posedge \coresync_clk - update \logical_op__zero_a $0\logical_op__zero_a[0:0] - end - attribute \src "issuer_ls180.v:157566.3-157567.63" - process $proc$issuer_ls180.v:157566$9141 - assign { } { } - assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next - sync posedge \coresync_clk - update \logical_op__input_carry $0\logical_op__input_carry[1:0] - end - attribute \src "issuer_ls180.v:157568.3-157569.61" - process $proc$issuer_ls180.v:157568$9142 - assign { } { } - assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next - sync posedge \coresync_clk - update \logical_op__invert_out $0\logical_op__invert_out[0:0] - end - attribute \src "issuer_ls180.v:157570.3-157571.59" - process $proc$issuer_ls180.v:157570$9143 - assign { } { } - assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next - sync posedge \coresync_clk - update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:157572.3-157573.65" - process $proc$issuer_ls180.v:157572$9144 - assign { } { } - assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next - sync posedge \coresync_clk - update \logical_op__output_carry $0\logical_op__output_carry[0:0] - end - attribute \src "issuer_ls180.v:157574.3-157575.57" - process $proc$issuer_ls180.v:157574$9145 - assign { } { } - assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next - sync posedge \coresync_clk - update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:157576.3-157577.59" - process $proc$issuer_ls180.v:157576$9146 - assign { } { } - assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next - sync posedge \coresync_clk - update \logical_op__is_signed $0\logical_op__is_signed[0:0] - end - attribute \src "issuer_ls180.v:157578.3-157579.57" - process $proc$issuer_ls180.v:157578$9147 - assign { } { } - assign $0\logical_op__data_len[3:0] \logical_op__data_len$next - sync posedge \coresync_clk - update \logical_op__data_len $0\logical_op__data_len[3:0] - end - attribute \src "issuer_ls180.v:157580.3-157581.49" - process $proc$issuer_ls180.v:157580$9148 - assign { } { } - assign $0\logical_op__insn[31:0] \logical_op__insn$next - sync posedge \coresync_clk - update \logical_op__insn $0\logical_op__insn[31:0] - end - attribute \src "issuer_ls180.v:157582.3-157583.27" - process $proc$issuer_ls180.v:157582$9149 - assign { } { } - assign $0\muxid[1:0] \muxid$next - sync posedge \coresync_clk - update \muxid $0\muxid[1:0] - end - attribute \src "issuer_ls180.v:157584.3-157585.29" - process $proc$issuer_ls180.v:157584$9150 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "issuer_ls180.v:157692.3-157704.6" - process $proc$issuer_ls180.v:157692$9151 - assign { } { } - assign { } { } - assign $0\divisor_neg$next[0:0]$9152 $1\divisor_neg$next[0:0]$9153 - attribute \src "issuer_ls180.v:157693.5-157693.29" - switch \initial - attribute \src "issuer_ls180.v:157693.9-157693.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\divisor_neg$next[0:0]$9153 \divisor_neg$92 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\divisor_neg$next[0:0]$9153 \divisor_neg$92 - case - assign $1\divisor_neg$next[0:0]$9153 \divisor_neg - end - sync always - update \divisor_neg$next $0\divisor_neg$next[0:0]$9152 - end - attribute \src "issuer_ls180.v:157705.3-157717.6" - process $proc$issuer_ls180.v:157705$9154 - assign { } { } - assign { } { } - assign $0\dividend_neg$next[0:0]$9155 $1\dividend_neg$next[0:0]$9156 - attribute \src "issuer_ls180.v:157706.5-157706.29" - switch \initial - attribute \src "issuer_ls180.v:157706.9-157706.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\dividend_neg$next[0:0]$9156 \dividend_neg$93 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\dividend_neg$next[0:0]$9156 \dividend_neg$93 - case - assign $1\dividend_neg$next[0:0]$9156 \dividend_neg - end - sync always - update \dividend_neg$next $0\dividend_neg$next[0:0]$9155 - end - attribute \src "issuer_ls180.v:157718.3-157730.6" - process $proc$issuer_ls180.v:157718$9157 - assign { } { } - assign { } { } - assign $0\dive_abs_ov32$next[0:0]$9158 $1\dive_abs_ov32$next[0:0]$9159 - attribute \src "issuer_ls180.v:157719.5-157719.29" - switch \initial - attribute \src "issuer_ls180.v:157719.9-157719.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\dive_abs_ov32$next[0:0]$9159 \dive_abs_ov32$94 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\dive_abs_ov32$next[0:0]$9159 \dive_abs_ov32$94 - case - assign $1\dive_abs_ov32$next[0:0]$9159 \dive_abs_ov32 - end - sync always - update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$9158 - end - attribute \src "issuer_ls180.v:157731.3-157743.6" - process $proc$issuer_ls180.v:157731$9160 - assign { } { } - assign { } { } - assign $0\dive_abs_ov64$next[0:0]$9161 $1\dive_abs_ov64$next[0:0]$9162 - attribute \src "issuer_ls180.v:157732.5-157732.29" - switch \initial - attribute \src "issuer_ls180.v:157732.9-157732.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\dive_abs_ov64$next[0:0]$9162 \dive_abs_ov64$95 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\dive_abs_ov64$next[0:0]$9162 \dive_abs_ov64$95 - case - assign $1\dive_abs_ov64$next[0:0]$9162 \dive_abs_ov64 - end - sync always - update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$9161 - end - attribute \src "issuer_ls180.v:157744.3-157756.6" - process $proc$issuer_ls180.v:157744$9163 - assign { } { } - assign { } { } - assign $0\div_by_zero$next[0:0]$9164 $1\div_by_zero$next[0:0]$9165 - attribute \src "issuer_ls180.v:157745.5-157745.29" - switch \initial - attribute \src "issuer_ls180.v:157745.9-157745.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\div_by_zero$next[0:0]$9165 \div_by_zero$96 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\div_by_zero$next[0:0]$9165 \div_by_zero$96 - case - assign $1\div_by_zero$next[0:0]$9165 \div_by_zero - end - sync always - update \div_by_zero$next $0\div_by_zero$next[0:0]$9164 - end - attribute \src "issuer_ls180.v:157757.3-157769.6" - process $proc$issuer_ls180.v:157757$9166 - assign { } { } - assign { } { } - assign $0\dividend$next[127:0]$9167 $1\dividend$next[127:0]$9168 - attribute \src "issuer_ls180.v:157758.5-157758.29" - switch \initial - attribute \src "issuer_ls180.v:157758.9-157758.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\dividend$next[127:0]$9168 \dividend$97 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\dividend$next[127:0]$9168 \dividend$97 - case - assign $1\dividend$next[127:0]$9168 \dividend - end - sync always - update \dividend$next $0\dividend$next[127:0]$9167 - end - attribute \src "issuer_ls180.v:157770.3-157782.6" - process $proc$issuer_ls180.v:157770$9169 - assign { } { } - assign { } { } - assign $0\divisor_radicand$next[63:0]$9170 $1\divisor_radicand$next[63:0]$9171 - attribute \src "issuer_ls180.v:157771.5-157771.29" - switch \initial - attribute \src "issuer_ls180.v:157771.9-157771.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\divisor_radicand$next[63:0]$9171 \divisor_radicand$98 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\divisor_radicand$next[63:0]$9171 \divisor_radicand$98 - case - assign $1\divisor_radicand$next[63:0]$9171 \divisor_radicand - end - sync always - update \divisor_radicand$next $0\divisor_radicand$next[63:0]$9170 - end - attribute \src "issuer_ls180.v:157783.3-157795.6" - process $proc$issuer_ls180.v:157783$9172 - assign { } { } - assign { } { } - assign $0\operation$next[1:0]$9173 $1\operation$next[1:0]$9174 - attribute \src "issuer_ls180.v:157784.5-157784.29" - switch \initial - attribute \src "issuer_ls180.v:157784.9-157784.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\operation$next[1:0]$9174 \operation$99 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\operation$next[1:0]$9174 \operation$99 - case - assign $1\operation$next[1:0]$9174 \operation - end - sync always - update \operation$next $0\operation$next[1:0]$9173 - end - attribute \src "issuer_ls180.v:157796.3-157813.6" - process $proc$issuer_ls180.v:157796$9175 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$9176 $2\r_busy$next[0:0]$9178 - attribute \src "issuer_ls180.v:157797.5-157797.29" - switch \initial - attribute \src "issuer_ls180.v:157797.9-157797.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$9177 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\r_busy$next[0:0]$9177 1'0 - case - assign $1\r_busy$next[0:0]$9177 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$9178 1'0 - case - assign $2\r_busy$next[0:0]$9178 $1\r_busy$next[0:0]$9177 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$9176 - end - attribute \src "issuer_ls180.v:157814.3-157826.6" - process $proc$issuer_ls180.v:157814$9179 - assign { } { } - assign { } { } - assign $0\muxid$next[1:0]$9180 $1\muxid$next[1:0]$9181 - attribute \src "issuer_ls180.v:157815.5-157815.29" - switch \initial - attribute \src "issuer_ls180.v:157815.9-157815.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$next[1:0]$9181 \muxid$68 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$next[1:0]$9181 \muxid$68 - case - assign $1\muxid$next[1:0]$9181 \muxid - end - sync always - update \muxid$next $0\muxid$next[1:0]$9180 - end - attribute \src "issuer_ls180.v:157827.3-157868.6" - process $proc$issuer_ls180.v:157827$9182 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\logical_op__data_len$next[3:0]$9183 $1\logical_op__data_len$next[3:0]$9201 - assign $0\logical_op__fn_unit$next[11:0]$9184 $1\logical_op__fn_unit$next[11:0]$9202 - assign { } { } - assign { } { } - assign $0\logical_op__input_carry$next[1:0]$9187 $1\logical_op__input_carry$next[1:0]$9205 - assign $0\logical_op__insn$next[31:0]$9188 $1\logical_op__insn$next[31:0]$9206 - assign $0\logical_op__insn_type$next[6:0]$9189 $1\logical_op__insn_type$next[6:0]$9207 - assign $0\logical_op__invert_in$next[0:0]$9190 $1\logical_op__invert_in$next[0:0]$9208 - assign $0\logical_op__invert_out$next[0:0]$9191 $1\logical_op__invert_out$next[0:0]$9209 - assign $0\logical_op__is_32bit$next[0:0]$9192 $1\logical_op__is_32bit$next[0:0]$9210 - assign $0\logical_op__is_signed$next[0:0]$9193 $1\logical_op__is_signed$next[0:0]$9211 - assign { } { } - assign { } { } - assign $0\logical_op__output_carry$next[0:0]$9196 $1\logical_op__output_carry$next[0:0]$9214 - assign { } { } - assign { } { } - assign $0\logical_op__write_cr0$next[0:0]$9199 $1\logical_op__write_cr0$next[0:0]$9217 - assign $0\logical_op__zero_a$next[0:0]$9200 $1\logical_op__zero_a$next[0:0]$9218 - assign $0\logical_op__imm_data__data$next[63:0]$9185 $2\logical_op__imm_data__data$next[63:0]$9219 - assign $0\logical_op__imm_data__ok$next[0:0]$9186 $2\logical_op__imm_data__ok$next[0:0]$9220 - assign $0\logical_op__oe__oe$next[0:0]$9194 $2\logical_op__oe__oe$next[0:0]$9221 - assign $0\logical_op__oe__ok$next[0:0]$9195 $2\logical_op__oe__ok$next[0:0]$9222 - assign $0\logical_op__rc__ok$next[0:0]$9197 $2\logical_op__rc__ok$next[0:0]$9223 - assign $0\logical_op__rc__rc$next[0:0]$9198 $2\logical_op__rc__rc$next[0:0]$9224 - attribute \src "issuer_ls180.v:157828.5-157828.29" - switch \initial - attribute \src "issuer_ls180.v:157828.9-157828.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\logical_op__insn$next[31:0]$9206 $1\logical_op__data_len$next[3:0]$9201 $1\logical_op__is_signed$next[0:0]$9211 $1\logical_op__is_32bit$next[0:0]$9210 $1\logical_op__output_carry$next[0:0]$9214 $1\logical_op__write_cr0$next[0:0]$9217 $1\logical_op__invert_out$next[0:0]$9209 $1\logical_op__input_carry$next[1:0]$9205 $1\logical_op__zero_a$next[0:0]$9218 $1\logical_op__invert_in$next[0:0]$9208 $1\logical_op__oe__ok$next[0:0]$9213 $1\logical_op__oe__oe$next[0:0]$9212 $1\logical_op__rc__ok$next[0:0]$9215 $1\logical_op__rc__rc$next[0:0]$9216 $1\logical_op__imm_data__ok$next[0:0]$9204 $1\logical_op__imm_data__data$next[63:0]$9203 $1\logical_op__fn_unit$next[11:0]$9202 $1\logical_op__insn_type$next[6:0]$9207 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\logical_op__insn$next[31:0]$9206 $1\logical_op__data_len$next[3:0]$9201 $1\logical_op__is_signed$next[0:0]$9211 $1\logical_op__is_32bit$next[0:0]$9210 $1\logical_op__output_carry$next[0:0]$9214 $1\logical_op__write_cr0$next[0:0]$9217 $1\logical_op__invert_out$next[0:0]$9209 $1\logical_op__input_carry$next[1:0]$9205 $1\logical_op__zero_a$next[0:0]$9218 $1\logical_op__invert_in$next[0:0]$9208 $1\logical_op__oe__ok$next[0:0]$9213 $1\logical_op__oe__oe$next[0:0]$9212 $1\logical_op__rc__ok$next[0:0]$9215 $1\logical_op__rc__rc$next[0:0]$9216 $1\logical_op__imm_data__ok$next[0:0]$9204 $1\logical_op__imm_data__data$next[63:0]$9203 $1\logical_op__fn_unit$next[11:0]$9202 $1\logical_op__insn_type$next[6:0]$9207 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } - case - assign $1\logical_op__data_len$next[3:0]$9201 \logical_op__data_len - assign $1\logical_op__fn_unit$next[11:0]$9202 \logical_op__fn_unit - assign $1\logical_op__imm_data__data$next[63:0]$9203 \logical_op__imm_data__data - assign $1\logical_op__imm_data__ok$next[0:0]$9204 \logical_op__imm_data__ok - assign $1\logical_op__input_carry$next[1:0]$9205 \logical_op__input_carry - assign $1\logical_op__insn$next[31:0]$9206 \logical_op__insn - assign $1\logical_op__insn_type$next[6:0]$9207 \logical_op__insn_type - assign $1\logical_op__invert_in$next[0:0]$9208 \logical_op__invert_in - assign $1\logical_op__invert_out$next[0:0]$9209 \logical_op__invert_out - assign $1\logical_op__is_32bit$next[0:0]$9210 \logical_op__is_32bit - assign $1\logical_op__is_signed$next[0:0]$9211 \logical_op__is_signed - assign $1\logical_op__oe__oe$next[0:0]$9212 \logical_op__oe__oe - assign $1\logical_op__oe__ok$next[0:0]$9213 \logical_op__oe__ok - assign $1\logical_op__output_carry$next[0:0]$9214 \logical_op__output_carry - assign $1\logical_op__rc__ok$next[0:0]$9215 \logical_op__rc__ok - assign $1\logical_op__rc__rc$next[0:0]$9216 \logical_op__rc__rc - assign $1\logical_op__write_cr0$next[0:0]$9217 \logical_op__write_cr0 - assign $1\logical_op__zero_a$next[0:0]$9218 \logical_op__zero_a - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\logical_op__imm_data__data$next[63:0]$9219 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$next[0:0]$9220 1'0 - assign $2\logical_op__rc__rc$next[0:0]$9224 1'0 - assign $2\logical_op__rc__ok$next[0:0]$9223 1'0 - assign $2\logical_op__oe__oe$next[0:0]$9221 1'0 - assign $2\logical_op__oe__ok$next[0:0]$9222 1'0 - case - assign $2\logical_op__imm_data__data$next[63:0]$9219 $1\logical_op__imm_data__data$next[63:0]$9203 - assign $2\logical_op__imm_data__ok$next[0:0]$9220 $1\logical_op__imm_data__ok$next[0:0]$9204 - assign $2\logical_op__oe__oe$next[0:0]$9221 $1\logical_op__oe__oe$next[0:0]$9212 - assign $2\logical_op__oe__ok$next[0:0]$9222 $1\logical_op__oe__ok$next[0:0]$9213 - assign $2\logical_op__rc__ok$next[0:0]$9223 $1\logical_op__rc__ok$next[0:0]$9215 - assign $2\logical_op__rc__rc$next[0:0]$9224 $1\logical_op__rc__rc$next[0:0]$9216 - end - sync always - update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$9183 - update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[11:0]$9184 - update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$9185 - update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$9186 - update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$9187 - update \logical_op__insn$next $0\logical_op__insn$next[31:0]$9188 - update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$9189 - update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$9190 - update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$9191 - update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$9192 - update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$9193 - update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$9194 - update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$9195 - update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$9196 - update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$9197 - update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$9198 - update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$9199 - update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$9200 - end - attribute \src "issuer_ls180.v:157869.3-157881.6" - process $proc$issuer_ls180.v:157869$9225 - assign { } { } - assign { } { } - assign $0\ra$next[63:0]$9226 $1\ra$next[63:0]$9227 - attribute \src "issuer_ls180.v:157870.5-157870.29" - switch \initial - attribute \src "issuer_ls180.v:157870.9-157870.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\ra$next[63:0]$9227 \ra$87 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\ra$next[63:0]$9227 \ra$87 - case - assign $1\ra$next[63:0]$9227 \ra - end - sync always - update \ra$next $0\ra$next[63:0]$9226 - end - attribute \src "issuer_ls180.v:157882.3-157894.6" - process $proc$issuer_ls180.v:157882$9228 - assign { } { } - assign { } { } - assign $0\rb$next[63:0]$9229 $1\rb$next[63:0]$9230 - attribute \src "issuer_ls180.v:157883.5-157883.29" - switch \initial - attribute \src "issuer_ls180.v:157883.9-157883.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\rb$next[63:0]$9230 \rb$89 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\rb$next[63:0]$9230 \rb$89 - case - assign $1\rb$next[63:0]$9230 \rb - end - sync always - update \rb$next $0\rb$next[63:0]$9229 - end - attribute \src "issuer_ls180.v:157895.3-157907.6" - process $proc$issuer_ls180.v:157895$9231 - assign { } { } - assign { } { } - assign $0\xer_so$next[0:0]$9232 $1\xer_so$next[0:0]$9233 - attribute \src "issuer_ls180.v:157896.5-157896.29" - switch \initial - attribute \src "issuer_ls180.v:157896.9-157896.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\xer_so$next[0:0]$9233 \xer_so$91 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\xer_so$next[0:0]$9233 \xer_so$91 - case - assign $1\xer_so$next[0:0]$9233 \xer_so - end - sync always - update \xer_so$next $0\xer_so$next[0:0]$9232 - end - connect \$66 $and$issuer_ls180.v:157523$9119_Y - connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect \operation$99 \setup_stage_operation - connect \divisor_radicand$98 \setup_stage_divisor_radicand - connect \dividend$97 \setup_stage_dividend - connect \div_by_zero$96 \setup_stage_div_by_zero - connect \dive_abs_ov64$95 \setup_stage_dive_abs_ov64 - connect \dive_abs_ov32$94 \setup_stage_dive_abs_ov32 - connect \dividend_neg$93 \setup_stage_dividend_neg - connect \divisor_neg$92 \setup_stage_divisor_neg - connect \xer_so$91 \setup_stage_xer_so$64 - connect \rb$89 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \ra$87 64'0000000000000000000000000000000000000000000000000000000000000000 - connect { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } { \setup_stage_logical_op__insn$63 \setup_stage_logical_op__data_len$62 \setup_stage_logical_op__is_signed$61 \setup_stage_logical_op__is_32bit$60 \setup_stage_logical_op__output_carry$59 \setup_stage_logical_op__write_cr0$58 \setup_stage_logical_op__invert_out$57 \setup_stage_logical_op__input_carry$56 \setup_stage_logical_op__zero_a$55 \setup_stage_logical_op__invert_in$54 \setup_stage_logical_op__oe__ok$53 \setup_stage_logical_op__oe__oe$52 \setup_stage_logical_op__rc__ok$51 \setup_stage_logical_op__rc__rc$50 \setup_stage_logical_op__imm_data__ok$49 \setup_stage_logical_op__imm_data__data$48 \setup_stage_logical_op__fn_unit$47 \setup_stage_logical_op__insn_type$46 } - connect \muxid$68 \setup_stage_muxid$45 - connect \p_valid_i_p_ready_o \$66 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$65 \p_valid_i - connect \setup_stage_xer_so \input_xer_so$44 - connect \setup_stage_rb \input_rb$43 - connect \setup_stage_ra \input_ra$42 - connect { \setup_stage_logical_op__insn \setup_stage_logical_op__data_len \setup_stage_logical_op__is_signed \setup_stage_logical_op__is_32bit \setup_stage_logical_op__output_carry \setup_stage_logical_op__write_cr0 \setup_stage_logical_op__invert_out \setup_stage_logical_op__input_carry \setup_stage_logical_op__zero_a \setup_stage_logical_op__invert_in \setup_stage_logical_op__oe__ok \setup_stage_logical_op__oe__oe \setup_stage_logical_op__rc__ok \setup_stage_logical_op__rc__rc \setup_stage_logical_op__imm_data__ok \setup_stage_logical_op__imm_data__data \setup_stage_logical_op__fn_unit \setup_stage_logical_op__insn_type } { \input_logical_op__insn$41 \input_logical_op__data_len$40 \input_logical_op__is_signed$39 \input_logical_op__is_32bit$38 \input_logical_op__output_carry$37 \input_logical_op__write_cr0$36 \input_logical_op__invert_out$35 \input_logical_op__input_carry$34 \input_logical_op__zero_a$33 \input_logical_op__invert_in$32 \input_logical_op__oe__ok$31 \input_logical_op__oe__oe$30 \input_logical_op__rc__ok$29 \input_logical_op__rc__rc$28 \input_logical_op__imm_data__ok$27 \input_logical_op__imm_data__data$26 \input_logical_op__fn_unit$25 \input_logical_op__insn_type$24 } - connect \setup_stage_muxid \input_muxid$23 - connect \input_xer_so \xer_so$22 - connect \input_rb \rb$21 - connect \input_ra \ra$20 - connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } - connect \input_muxid \muxid$1 -end -attribute \src "issuer_ls180.v:157942.1-158584.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" -attribute \generator "nMigen" -module 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parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_20 } - connect \B { 2'00 \pop_2_21 } - connect \Y $add$issuer_ls180.v:158365$9276_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$issuer_ls180.v:158366$9277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_22 } - connect \B { 2'00 \pop_2_23 } - connect \Y $add$issuer_ls180.v:158366$9277_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$issuer_ls180.v:158367$9278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_24 } - connect \B { 2'00 \pop_2_25 } - connect \Y $add$issuer_ls180.v:158367$9278_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$issuer_ls180.v:158368$9279 - parameter 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connect \Y $add$issuer_ls180.v:158373$9284_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$issuer_ls180.v:158374$9285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'00 \pop_3_4 } - connect \B { 2'00 \pop_3_5 } - connect \Y $add$issuer_ls180.v:158374$9285_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$issuer_ls180.v:158375$9286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'00 \pop_3_6 } - connect \B { 2'00 \pop_3_7 } - connect \Y $add$issuer_ls180.v:158375$9286_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$issuer_ls180.v:158376$9287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter 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parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'00 \pop_3_14 } - connect \B { 2'00 \pop_3_15 } - connect \Y $add$issuer_ls180.v:158379$9290_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$issuer_ls180.v:158380$9291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A { 2'00 \pop_4_0 } - connect \B { 2'00 \pop_4_1 } - connect \Y $add$issuer_ls180.v:158380$9291_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$issuer_ls180.v:158381$9292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A { 2'00 \pop_4_2 } - connect \B { 2'00 \pop_4_3 } - connect \Y $add$issuer_ls180.v:158381$9292_Y - end - attribute \src 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connect \Y $add$issuer_ls180.v:158384$9295_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$issuer_ls180.v:158385$9296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 7 - connect \A { 2'00 \pop_5_0 } - connect \B { 2'00 \pop_5_1 } - connect \Y $add$issuer_ls180.v:158385$9296_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$issuer_ls180.v:158386$9297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 7 - connect \A { 2'00 \pop_5_2 } - connect \B { 2'00 \pop_5_3 } - connect \Y $add$issuer_ls180.v:158386$9297_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$issuer_ls180.v:158387$9298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { 2'00 \pop_6_0 } - connect \B { 2'00 \pop_6_1 } - connect \Y $add$issuer_ls180.v:158387$9298_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$issuer_ls180.v:158398$9317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [12] } - connect \B { 2'00 \a [13] } - connect \Y $add$issuer_ls180.v:158398$9317_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$issuer_ls180.v:158402$9324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [14] } - connect \B { 2'00 \a [15] } - connect \Y $add$issuer_ls180.v:158402$9324_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$issuer_ls180.v:158403$9325 - parameter \A_SIGNED 0 - parameter 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3 - connect \A { 2'00 \a [36] } - connect \B { 2'00 \a [37] } - connect \Y $add$issuer_ls180.v:158414$9336_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$issuer_ls180.v:158415$9337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [2] } - connect \B { 2'00 \a [3] } - connect \Y $add$issuer_ls180.v:158415$9337_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$issuer_ls180.v:158416$9338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [38] } - connect \B { 2'00 \a [39] } - connect \Y $add$issuer_ls180.v:158416$9338_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$issuer_ls180.v:158417$9339 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [40] } - connect \B { 2'00 \a [41] } - connect \Y $add$issuer_ls180.v:158417$9339_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$issuer_ls180.v:158418$9340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [42] } - connect \B { 2'00 \a [43] } - connect \Y $add$issuer_ls180.v:158418$9340_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$issuer_ls180.v:158419$9341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [44] } - connect \B { 2'00 \a [45] } - connect \Y $add$issuer_ls180.v:158419$9341_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add 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$add$issuer_ls180.v:158372$9283_Y - connect \$149 $add$issuer_ls180.v:158373$9284_Y - connect \$152 $add$issuer_ls180.v:158374$9285_Y - connect \$155 $add$issuer_ls180.v:158375$9286_Y - connect \$158 $add$issuer_ls180.v:158376$9287_Y - connect \$161 $add$issuer_ls180.v:158377$9288_Y - connect \$164 $add$issuer_ls180.v:158378$9289_Y - connect \$167 $add$issuer_ls180.v:158379$9290_Y - connect \$170 $add$issuer_ls180.v:158380$9291_Y - connect \$173 $add$issuer_ls180.v:158381$9292_Y - connect \$176 $add$issuer_ls180.v:158382$9293_Y - connect \$17 $add$issuer_ls180.v:158383$9294_Y - connect \$179 $add$issuer_ls180.v:158384$9295_Y - connect \$182 $add$issuer_ls180.v:158385$9296_Y - connect \$185 $add$issuer_ls180.v:158386$9297_Y - connect \$188 $add$issuer_ls180.v:158387$9298_Y - connect \$190 $eq$issuer_ls180.v:158388$9299_Y - connect \$192 $eq$issuer_ls180.v:158389$9300_Y - connect \$194 $pos$issuer_ls180.v:158390$9302_Y - connect \$196 $pos$issuer_ls180.v:158391$9304_Y - connect \$198 $pos$issuer_ls180.v:158392$9306_Y - connect \$200 $pos$issuer_ls180.v:158393$9308_Y - connect \$202 $pos$issuer_ls180.v:158394$9310_Y - connect \$204 $pos$issuer_ls180.v:158395$9312_Y - connect \$206 $pos$issuer_ls180.v:158396$9314_Y - connect \$208 $pos$issuer_ls180.v:158397$9316_Y - connect \$20 $add$issuer_ls180.v:158398$9317_Y - connect \$210 $pos$issuer_ls180.v:158399$9319_Y - connect \$212 $pos$issuer_ls180.v:158400$9321_Y - connect \$214 $pos$issuer_ls180.v:158401$9323_Y - connect \$23 $add$issuer_ls180.v:158402$9324_Y - connect \$26 $add$issuer_ls180.v:158403$9325_Y - connect \$2 $add$issuer_ls180.v:158404$9326_Y - connect \$29 $add$issuer_ls180.v:158405$9327_Y - connect \$32 $add$issuer_ls180.v:158406$9328_Y - connect \$35 $add$issuer_ls180.v:158407$9329_Y - connect \$38 $add$issuer_ls180.v:158408$9330_Y - connect \$41 $add$issuer_ls180.v:158409$9331_Y - connect \$44 $add$issuer_ls180.v:158410$9332_Y - connect \$47 $add$issuer_ls180.v:158411$9333_Y - connect \$50 $add$issuer_ls180.v:158412$9334_Y - connect \$53 $add$issuer_ls180.v:158413$9335_Y - connect \$56 $add$issuer_ls180.v:158414$9336_Y - connect \$5 $add$issuer_ls180.v:158415$9337_Y - connect \$59 $add$issuer_ls180.v:158416$9338_Y - connect \$62 $add$issuer_ls180.v:158417$9339_Y - connect \$65 $add$issuer_ls180.v:158418$9340_Y - connect \$68 $add$issuer_ls180.v:158419$9341_Y - connect \$71 $add$issuer_ls180.v:158420$9342_Y - connect \$74 $add$issuer_ls180.v:158421$9343_Y - connect \$77 $add$issuer_ls180.v:158422$9344_Y - connect \$80 $add$issuer_ls180.v:158423$9345_Y - connect \$83 $add$issuer_ls180.v:158424$9346_Y - connect \$86 $add$issuer_ls180.v:158425$9347_Y - connect \$8 $add$issuer_ls180.v:158426$9348_Y - connect \$89 $add$issuer_ls180.v:158427$9349_Y - connect \$92 $add$issuer_ls180.v:158428$9350_Y - connect \$95 $add$issuer_ls180.v:158429$9351_Y - connect \$98 $add$issuer_ls180.v:158430$9352_Y - connect \$1 \$2 - connect \$4 \$5 - connect \$7 \$8 - connect \$10 \$11 - connect \$13 \$14 - connect \$16 \$17 - connect \$19 \$20 - connect \$22 \$23 - connect \$25 \$26 - connect \$28 \$29 - connect \$31 \$32 - connect \$34 \$35 - connect \$37 \$38 - connect \$40 \$41 - connect \$43 \$44 - connect \$46 \$47 - connect \$49 \$50 - connect \$52 \$53 - connect \$55 \$56 - connect \$58 \$59 - connect \$61 \$62 - connect \$64 \$65 - connect \$67 \$68 - connect \$70 \$71 - connect \$73 \$74 - connect \$76 \$77 - connect \$79 \$80 - connect \$82 \$83 - connect \$85 \$86 - connect \$88 \$89 - connect \$91 \$92 - connect \$94 \$95 - connect \$97 \$98 - connect \$100 \$101 - connect \$103 \$104 - connect \$106 \$107 - connect \$109 \$110 - connect \$112 \$113 - connect \$115 \$116 - connect \$118 \$119 - connect \$121 \$122 - connect \$124 \$125 - connect \$127 \$128 - connect \$130 \$131 - connect \$133 \$134 - connect \$136 \$137 - connect \$139 \$140 - connect \$142 \$143 - connect \$145 \$146 - connect \$148 \$149 - connect \$151 \$152 - connect \$154 \$155 - connect \$157 \$158 - connect \$160 \$161 - connect \$163 \$164 - connect \$166 \$167 - connect \$169 \$170 - connect \$172 \$173 - connect \$175 \$176 - connect \$178 \$179 - connect \$181 \$182 - connect \$184 \$185 - connect \$187 \$188 - connect \pop_7_0 \$188 [6:0] - connect \pop_6_1 \$185 [5:0] - connect \pop_6_0 \$182 [5:0] - connect \pop_5_3 \$179 [4:0] - connect \pop_5_2 \$176 [4:0] - connect \pop_5_1 \$173 [4:0] - connect \pop_5_0 \$170 [4:0] - connect \pop_4_7 \$167 [3:0] - connect \pop_4_6 \$164 [3:0] - connect \pop_4_5 \$161 [3:0] - connect \pop_4_4 \$158 [3:0] - connect \pop_4_3 \$155 [3:0] - connect \pop_4_2 \$152 [3:0] - connect \pop_4_1 \$149 [3:0] - connect \pop_4_0 \$146 [3:0] - connect \pop_3_15 \$143 [2:0] - connect \pop_3_14 \$140 [2:0] - connect \pop_3_13 \$137 [2:0] - connect \pop_3_12 \$134 [2:0] - connect \pop_3_11 \$131 [2:0] - connect \pop_3_10 \$128 [2:0] - connect \pop_3_9 \$125 [2:0] - connect \pop_3_8 \$122 [2:0] - connect \pop_3_7 \$119 [2:0] - connect \pop_3_6 \$116 [2:0] - connect \pop_3_5 \$113 [2:0] - connect \pop_3_4 \$110 [2:0] - connect \pop_3_3 \$107 [2:0] - connect \pop_3_2 \$104 [2:0] - connect \pop_3_1 \$101 [2:0] - connect \pop_3_0 \$98 [2:0] - connect \pop_2_31 \$95 [1:0] - connect \pop_2_30 \$92 [1:0] - connect \pop_2_29 \$89 [1:0] - connect \pop_2_28 \$86 [1:0] - connect \pop_2_27 \$83 [1:0] - connect \pop_2_26 \$80 [1:0] - connect \pop_2_25 \$77 [1:0] - connect \pop_2_24 \$74 [1:0] - connect \pop_2_23 \$71 [1:0] - connect \pop_2_22 \$68 [1:0] - connect \pop_2_21 \$65 [1:0] - connect \pop_2_20 \$62 [1:0] - connect \pop_2_19 \$59 [1:0] - connect \pop_2_18 \$56 [1:0] - connect \pop_2_17 \$53 [1:0] - connect \pop_2_16 \$50 [1:0] - connect \pop_2_15 \$47 [1:0] - connect \pop_2_14 \$44 [1:0] - connect \pop_2_13 \$41 [1:0] - connect \pop_2_12 \$38 [1:0] - connect \pop_2_11 \$35 [1:0] - connect \pop_2_10 \$32 [1:0] - connect \pop_2_9 \$29 [1:0] - connect \pop_2_8 \$26 [1:0] - connect \pop_2_7 \$23 [1:0] - connect \pop_2_6 \$20 [1:0] - connect \pop_2_5 \$17 [1:0] - connect \pop_2_4 \$14 [1:0] - connect \pop_2_3 \$11 [1:0] - connect \pop_2_2 \$8 [1:0] - connect \pop_2_1 \$5 [1:0] - connect \pop_2_0 \$2 [1:0] -end -attribute \src "issuer_ls180.v:158588.1-158672.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick - attribute \src "issuer_ls180.v:158645.17-158645.91" - wire $not$issuer_ls180.v:158645$9355_Y - attribute \src "issuer_ls180.v:158647.18-158647.93" - wire $not$issuer_ls180.v:158647$9357_Y - attribute \src "issuer_ls180.v:158649.18-158649.93" - wire $not$issuer_ls180.v:158649$9359_Y - attribute \src "issuer_ls180.v:158650.17-158650.138" - wire width 8 $not$issuer_ls180.v:158650$9360_Y - attribute \src "issuer_ls180.v:158652.18-158652.93" - wire $not$issuer_ls180.v:158652$9362_Y - attribute \src "issuer_ls180.v:158654.18-158654.93" - wire $not$issuer_ls180.v:158654$9364_Y - attribute \src "issuer_ls180.v:158656.18-158656.93" - wire $not$issuer_ls180.v:158656$9366_Y - attribute \src "issuer_ls180.v:158659.17-158659.91" - wire $not$issuer_ls180.v:158659$9369_Y - attribute \src "issuer_ls180.v:158646.18-158646.116" - wire $reduce_or$issuer_ls180.v:158646$9356_Y - attribute \src "issuer_ls180.v:158648.18-158648.122" - wire $reduce_or$issuer_ls180.v:158648$9358_Y - attribute \src "issuer_ls180.v:158651.18-158651.128" - wire $reduce_or$issuer_ls180.v:158651$9361_Y - attribute \src "issuer_ls180.v:158653.18-158653.134" - wire $reduce_or$issuer_ls180.v:158653$9363_Y - attribute \src "issuer_ls180.v:158655.18-158655.140" - wire $reduce_or$issuer_ls180.v:158655$9365_Y - attribute \src "issuer_ls180.v:158657.18-158657.90" - wire $reduce_or$issuer_ls180.v:158657$9367_Y - attribute \src "issuer_ls180.v:158658.17-158658.103" - wire $reduce_or$issuer_ls180.v:158658$9368_Y - attribute \src "issuer_ls180.v:158660.17-158660.109" - wire $reduce_or$issuer_ls180.v:158660$9370_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158645$9355 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:158645$9355_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158647$9357 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:158647$9357_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158649$9359 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:158649$9359_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:158650$9360 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$issuer_ls180.v:158650$9360_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158652$9362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$issuer_ls180.v:158652$9362_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158654$9364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:158654$9364_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158656$9366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$issuer_ls180.v:158656$9366_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158659$9369 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:158659$9369_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158646$9356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:158646$9356_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158648$9358 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:158648$9358_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158651$9361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$issuer_ls180.v:158651$9361_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158653$9363 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$issuer_ls180.v:158653$9363_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158655$9365 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$issuer_ls180.v:158655$9365_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:158657$9367 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:158657$9367_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158658$9368 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:158658$9368_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158660$9370 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:158660$9370_Y - end - connect \$7 $not$issuer_ls180.v:158645$9355_Y - connect \$12 $reduce_or$issuer_ls180.v:158646$9356_Y - connect \$11 $not$issuer_ls180.v:158647$9357_Y - connect \$16 $reduce_or$issuer_ls180.v:158648$9358_Y - connect \$15 $not$issuer_ls180.v:158649$9359_Y - connect \$1 $not$issuer_ls180.v:158650$9360_Y - connect \$20 $reduce_or$issuer_ls180.v:158651$9361_Y - connect \$19 $not$issuer_ls180.v:158652$9362_Y - connect \$24 $reduce_or$issuer_ls180.v:158653$9363_Y - connect \$23 $not$issuer_ls180.v:158654$9364_Y - connect \$28 $reduce_or$issuer_ls180.v:158655$9365_Y - connect \$27 $not$issuer_ls180.v:158656$9366_Y - connect \$31 $reduce_or$issuer_ls180.v:158657$9367_Y - connect \$4 $reduce_or$issuer_ls180.v:158658$9368_Y - connect \$3 $not$issuer_ls180.v:158659$9369_Y - connect \$8 $reduce_or$issuer_ls180.v:158660$9370_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:158676.1-158760.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$136 - attribute \src "issuer_ls180.v:158733.17-158733.91" - wire $not$issuer_ls180.v:158733$9371_Y - attribute \src "issuer_ls180.v:158735.18-158735.93" - wire $not$issuer_ls180.v:158735$9373_Y - attribute \src "issuer_ls180.v:158737.18-158737.93" - wire $not$issuer_ls180.v:158737$9375_Y - attribute \src "issuer_ls180.v:158738.17-158738.138" - wire width 8 $not$issuer_ls180.v:158738$9376_Y - attribute \src "issuer_ls180.v:158740.18-158740.93" - wire $not$issuer_ls180.v:158740$9378_Y - attribute \src "issuer_ls180.v:158742.18-158742.93" - wire $not$issuer_ls180.v:158742$9380_Y - attribute \src "issuer_ls180.v:158744.18-158744.93" - wire $not$issuer_ls180.v:158744$9382_Y - attribute \src "issuer_ls180.v:158747.17-158747.91" - wire $not$issuer_ls180.v:158747$9385_Y - attribute \src "issuer_ls180.v:158734.18-158734.116" - wire $reduce_or$issuer_ls180.v:158734$9372_Y - attribute \src "issuer_ls180.v:158736.18-158736.122" - wire $reduce_or$issuer_ls180.v:158736$9374_Y - attribute \src "issuer_ls180.v:158739.18-158739.128" - wire $reduce_or$issuer_ls180.v:158739$9377_Y - attribute \src "issuer_ls180.v:158741.18-158741.134" - wire $reduce_or$issuer_ls180.v:158741$9379_Y - attribute \src "issuer_ls180.v:158743.18-158743.140" - wire $reduce_or$issuer_ls180.v:158743$9381_Y - attribute \src "issuer_ls180.v:158745.18-158745.90" - wire $reduce_or$issuer_ls180.v:158745$9383_Y - attribute \src "issuer_ls180.v:158746.17-158746.103" - wire $reduce_or$issuer_ls180.v:158746$9384_Y - attribute \src "issuer_ls180.v:158748.17-158748.109" - wire $reduce_or$issuer_ls180.v:158748$9386_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158733$9371 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:158733$9371_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158735$9373 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:158735$9373_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158737$9375 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:158737$9375_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:158738$9376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$issuer_ls180.v:158738$9376_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158740$9378 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$issuer_ls180.v:158740$9378_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158742$9380 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:158742$9380_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158744$9382 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$issuer_ls180.v:158744$9382_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158747$9385 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:158747$9385_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158734$9372 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:158734$9372_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158736$9374 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:158736$9374_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158739$9377 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$issuer_ls180.v:158739$9377_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158741$9379 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$issuer_ls180.v:158741$9379_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158743$9381 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$issuer_ls180.v:158743$9381_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:158745$9383 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:158745$9383_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158746$9384 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:158746$9384_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158748$9386 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:158748$9386_Y - end - connect \$7 $not$issuer_ls180.v:158733$9371_Y - connect \$12 $reduce_or$issuer_ls180.v:158734$9372_Y - connect \$11 $not$issuer_ls180.v:158735$9373_Y - connect \$16 $reduce_or$issuer_ls180.v:158736$9374_Y - connect \$15 $not$issuer_ls180.v:158737$9375_Y - connect \$1 $not$issuer_ls180.v:158738$9376_Y - connect \$20 $reduce_or$issuer_ls180.v:158739$9377_Y - connect \$19 $not$issuer_ls180.v:158740$9378_Y - connect \$24 $reduce_or$issuer_ls180.v:158741$9379_Y - connect \$23 $not$issuer_ls180.v:158742$9380_Y - connect \$28 $reduce_or$issuer_ls180.v:158743$9381_Y - connect \$27 $not$issuer_ls180.v:158744$9382_Y - connect \$31 $reduce_or$issuer_ls180.v:158745$9383_Y - connect \$4 $reduce_or$issuer_ls180.v:158746$9384_Y - connect \$3 $not$issuer_ls180.v:158747$9385_Y - connect \$8 $reduce_or$issuer_ls180.v:158748$9386_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:158764.1-158848.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$141 - attribute \src "issuer_ls180.v:158821.17-158821.91" - wire $not$issuer_ls180.v:158821$9387_Y - attribute \src "issuer_ls180.v:158823.18-158823.93" - wire $not$issuer_ls180.v:158823$9389_Y - attribute \src "issuer_ls180.v:158825.18-158825.93" - wire $not$issuer_ls180.v:158825$9391_Y - attribute \src "issuer_ls180.v:158826.17-158826.138" - wire width 8 $not$issuer_ls180.v:158826$9392_Y - attribute \src "issuer_ls180.v:158828.18-158828.93" - wire $not$issuer_ls180.v:158828$9394_Y - attribute \src "issuer_ls180.v:158830.18-158830.93" - wire $not$issuer_ls180.v:158830$9396_Y - attribute \src "issuer_ls180.v:158832.18-158832.93" - wire $not$issuer_ls180.v:158832$9398_Y - attribute \src "issuer_ls180.v:158835.17-158835.91" - wire $not$issuer_ls180.v:158835$9401_Y - attribute \src "issuer_ls180.v:158822.18-158822.116" - wire $reduce_or$issuer_ls180.v:158822$9388_Y - attribute \src "issuer_ls180.v:158824.18-158824.122" - wire $reduce_or$issuer_ls180.v:158824$9390_Y - attribute \src "issuer_ls180.v:158827.18-158827.128" - wire $reduce_or$issuer_ls180.v:158827$9393_Y - attribute \src "issuer_ls180.v:158829.18-158829.134" - wire $reduce_or$issuer_ls180.v:158829$9395_Y - attribute \src "issuer_ls180.v:158831.18-158831.140" - wire $reduce_or$issuer_ls180.v:158831$9397_Y - attribute \src "issuer_ls180.v:158833.18-158833.90" - wire $reduce_or$issuer_ls180.v:158833$9399_Y - attribute \src "issuer_ls180.v:158834.17-158834.103" - wire $reduce_or$issuer_ls180.v:158834$9400_Y - attribute \src "issuer_ls180.v:158836.17-158836.109" - wire $reduce_or$issuer_ls180.v:158836$9402_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158821$9387 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:158821$9387_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158823$9389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:158823$9389_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158825$9391 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:158825$9391_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:158826$9392 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$issuer_ls180.v:158826$9392_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158828$9394 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$issuer_ls180.v:158828$9394_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158830$9396 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:158830$9396_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158832$9398 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$issuer_ls180.v:158832$9398_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158835$9401 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:158835$9401_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158822$9388 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:158822$9388_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158824$9390 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:158824$9390_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158827$9393 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$issuer_ls180.v:158827$9393_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158829$9395 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$issuer_ls180.v:158829$9395_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158831$9397 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$issuer_ls180.v:158831$9397_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:158833$9399 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:158833$9399_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158834$9400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:158834$9400_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158836$9402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:158836$9402_Y - end - connect \$7 $not$issuer_ls180.v:158821$9387_Y - connect \$12 $reduce_or$issuer_ls180.v:158822$9388_Y - connect \$11 $not$issuer_ls180.v:158823$9389_Y - connect \$16 $reduce_or$issuer_ls180.v:158824$9390_Y - connect \$15 $not$issuer_ls180.v:158825$9391_Y - connect \$1 $not$issuer_ls180.v:158826$9392_Y - connect \$20 $reduce_or$issuer_ls180.v:158827$9393_Y - connect \$19 $not$issuer_ls180.v:158828$9394_Y - connect \$24 $reduce_or$issuer_ls180.v:158829$9395_Y - connect \$23 $not$issuer_ls180.v:158830$9396_Y - connect \$28 $reduce_or$issuer_ls180.v:158831$9397_Y - connect \$27 $not$issuer_ls180.v:158832$9398_Y - connect \$31 $reduce_or$issuer_ls180.v:158833$9399_Y - connect \$4 $reduce_or$issuer_ls180.v:158834$9400_Y - connect \$3 $not$issuer_ls180.v:158835$9401_Y - connect \$8 $reduce_or$issuer_ls180.v:158836$9402_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:158852.1-158936.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$143 - attribute \src "issuer_ls180.v:158909.17-158909.91" - wire $not$issuer_ls180.v:158909$9403_Y - attribute \src "issuer_ls180.v:158911.18-158911.93" - wire $not$issuer_ls180.v:158911$9405_Y - attribute \src "issuer_ls180.v:158913.18-158913.93" - wire $not$issuer_ls180.v:158913$9407_Y - attribute \src "issuer_ls180.v:158914.17-158914.138" - wire width 8 $not$issuer_ls180.v:158914$9408_Y - attribute \src "issuer_ls180.v:158916.18-158916.93" - wire $not$issuer_ls180.v:158916$9410_Y - attribute \src "issuer_ls180.v:158918.18-158918.93" - wire $not$issuer_ls180.v:158918$9412_Y - attribute \src "issuer_ls180.v:158920.18-158920.93" - wire $not$issuer_ls180.v:158920$9414_Y - attribute \src "issuer_ls180.v:158923.17-158923.91" - wire $not$issuer_ls180.v:158923$9417_Y - attribute \src "issuer_ls180.v:158910.18-158910.116" - wire $reduce_or$issuer_ls180.v:158910$9404_Y - attribute \src "issuer_ls180.v:158912.18-158912.122" - wire $reduce_or$issuer_ls180.v:158912$9406_Y - attribute \src "issuer_ls180.v:158915.18-158915.128" - wire $reduce_or$issuer_ls180.v:158915$9409_Y - attribute \src "issuer_ls180.v:158917.18-158917.134" - wire $reduce_or$issuer_ls180.v:158917$9411_Y - attribute \src "issuer_ls180.v:158919.18-158919.140" - wire $reduce_or$issuer_ls180.v:158919$9413_Y - attribute \src "issuer_ls180.v:158921.18-158921.90" - wire $reduce_or$issuer_ls180.v:158921$9415_Y - attribute \src "issuer_ls180.v:158922.17-158922.103" - wire $reduce_or$issuer_ls180.v:158922$9416_Y - attribute \src "issuer_ls180.v:158924.17-158924.109" - wire $reduce_or$issuer_ls180.v:158924$9418_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158909$9403 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:158909$9403_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158911$9405 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:158911$9405_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158913$9407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:158913$9407_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:158914$9408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$issuer_ls180.v:158914$9408_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158916$9410 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$issuer_ls180.v:158916$9410_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158918$9412 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:158918$9412_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158920$9414 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$issuer_ls180.v:158920$9414_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158923$9417 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:158923$9417_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158910$9404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:158910$9404_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158912$9406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:158912$9406_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158915$9409 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$issuer_ls180.v:158915$9409_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158917$9411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$issuer_ls180.v:158917$9411_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158919$9413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$issuer_ls180.v:158919$9413_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:158921$9415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:158921$9415_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158922$9416 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:158922$9416_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158924$9418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:158924$9418_Y - end - connect \$7 $not$issuer_ls180.v:158909$9403_Y - connect \$12 $reduce_or$issuer_ls180.v:158910$9404_Y - connect \$11 $not$issuer_ls180.v:158911$9405_Y - connect \$16 $reduce_or$issuer_ls180.v:158912$9406_Y - connect \$15 $not$issuer_ls180.v:158913$9407_Y - connect \$1 $not$issuer_ls180.v:158914$9408_Y - connect \$20 $reduce_or$issuer_ls180.v:158915$9409_Y - connect \$19 $not$issuer_ls180.v:158916$9410_Y - connect \$24 $reduce_or$issuer_ls180.v:158917$9411_Y - connect \$23 $not$issuer_ls180.v:158918$9412_Y - connect \$28 $reduce_or$issuer_ls180.v:158919$9413_Y - connect \$27 $not$issuer_ls180.v:158920$9414_Y - connect \$31 $reduce_or$issuer_ls180.v:158921$9415_Y - connect \$4 $reduce_or$issuer_ls180.v:158922$9416_Y - connect \$3 $not$issuer_ls180.v:158923$9417_Y - connect \$8 $reduce_or$issuer_ls180.v:158924$9418_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:158940.1-159024.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$148 - attribute \src "issuer_ls180.v:158997.17-158997.91" - wire $not$issuer_ls180.v:158997$9419_Y - attribute \src "issuer_ls180.v:158999.18-158999.93" - wire $not$issuer_ls180.v:158999$9421_Y - attribute \src "issuer_ls180.v:159001.18-159001.93" - wire $not$issuer_ls180.v:159001$9423_Y - attribute \src "issuer_ls180.v:159002.17-159002.138" - wire width 8 $not$issuer_ls180.v:159002$9424_Y - attribute \src "issuer_ls180.v:159004.18-159004.93" - wire $not$issuer_ls180.v:159004$9426_Y - attribute \src "issuer_ls180.v:159006.18-159006.93" - wire $not$issuer_ls180.v:159006$9428_Y - attribute \src "issuer_ls180.v:159008.18-159008.93" - wire $not$issuer_ls180.v:159008$9430_Y - attribute \src "issuer_ls180.v:159011.17-159011.91" - wire $not$issuer_ls180.v:159011$9433_Y - attribute \src "issuer_ls180.v:158998.18-158998.116" - wire $reduce_or$issuer_ls180.v:158998$9420_Y - attribute \src "issuer_ls180.v:159000.18-159000.122" - wire $reduce_or$issuer_ls180.v:159000$9422_Y - attribute \src "issuer_ls180.v:159003.18-159003.128" - wire $reduce_or$issuer_ls180.v:159003$9425_Y - attribute \src "issuer_ls180.v:159005.18-159005.134" - wire $reduce_or$issuer_ls180.v:159005$9427_Y - attribute \src "issuer_ls180.v:159007.18-159007.140" - wire $reduce_or$issuer_ls180.v:159007$9429_Y - attribute \src "issuer_ls180.v:159009.18-159009.90" - wire $reduce_or$issuer_ls180.v:159009$9431_Y - attribute \src "issuer_ls180.v:159010.17-159010.103" - wire $reduce_or$issuer_ls180.v:159010$9432_Y - attribute \src "issuer_ls180.v:159012.17-159012.109" - wire $reduce_or$issuer_ls180.v:159012$9434_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158997$9419 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:158997$9419_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:158999$9421 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:158999$9421_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159001$9423 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:159001$9423_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:159002$9424 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$issuer_ls180.v:159002$9424_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159004$9426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$issuer_ls180.v:159004$9426_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159006$9428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:159006$9428_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159008$9430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$issuer_ls180.v:159008$9430_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159011$9433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:159011$9433_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:158998$9420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:158998$9420_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159000$9422 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:159000$9422_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159003$9425 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$issuer_ls180.v:159003$9425_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159005$9427 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$issuer_ls180.v:159005$9427_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159007$9429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$issuer_ls180.v:159007$9429_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:159009$9431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:159009$9431_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159010$9432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:159010$9432_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159012$9434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:159012$9434_Y - end - connect \$7 $not$issuer_ls180.v:158997$9419_Y - connect \$12 $reduce_or$issuer_ls180.v:158998$9420_Y - connect \$11 $not$issuer_ls180.v:158999$9421_Y - connect \$16 $reduce_or$issuer_ls180.v:159000$9422_Y - connect \$15 $not$issuer_ls180.v:159001$9423_Y - connect \$1 $not$issuer_ls180.v:159002$9424_Y - connect \$20 $reduce_or$issuer_ls180.v:159003$9425_Y - connect \$19 $not$issuer_ls180.v:159004$9426_Y - connect \$24 $reduce_or$issuer_ls180.v:159005$9427_Y - connect \$23 $not$issuer_ls180.v:159006$9428_Y - connect \$28 $reduce_or$issuer_ls180.v:159007$9429_Y - connect \$27 $not$issuer_ls180.v:159008$9430_Y - connect \$31 $reduce_or$issuer_ls180.v:159009$9431_Y - connect \$4 $reduce_or$issuer_ls180.v:159010$9432_Y - connect \$3 $not$issuer_ls180.v:159011$9433_Y - connect \$8 $reduce_or$issuer_ls180.v:159012$9434_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:159028.1-159112.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$150 - attribute \src "issuer_ls180.v:159085.17-159085.91" - wire $not$issuer_ls180.v:159085$9435_Y - attribute \src "issuer_ls180.v:159087.18-159087.93" - wire $not$issuer_ls180.v:159087$9437_Y - attribute \src "issuer_ls180.v:159089.18-159089.93" - wire $not$issuer_ls180.v:159089$9439_Y - attribute \src "issuer_ls180.v:159090.17-159090.138" - wire width 8 $not$issuer_ls180.v:159090$9440_Y - attribute \src "issuer_ls180.v:159092.18-159092.93" - wire $not$issuer_ls180.v:159092$9442_Y - attribute \src "issuer_ls180.v:159094.18-159094.93" - wire $not$issuer_ls180.v:159094$9444_Y - attribute \src "issuer_ls180.v:159096.18-159096.93" - wire $not$issuer_ls180.v:159096$9446_Y - attribute \src "issuer_ls180.v:159099.17-159099.91" - wire $not$issuer_ls180.v:159099$9449_Y - attribute \src "issuer_ls180.v:159086.18-159086.116" - wire $reduce_or$issuer_ls180.v:159086$9436_Y - attribute \src "issuer_ls180.v:159088.18-159088.122" - wire $reduce_or$issuer_ls180.v:159088$9438_Y - attribute \src "issuer_ls180.v:159091.18-159091.128" - wire $reduce_or$issuer_ls180.v:159091$9441_Y - attribute \src "issuer_ls180.v:159093.18-159093.134" - wire $reduce_or$issuer_ls180.v:159093$9443_Y - attribute \src "issuer_ls180.v:159095.18-159095.140" - wire $reduce_or$issuer_ls180.v:159095$9445_Y - attribute \src "issuer_ls180.v:159097.18-159097.90" - wire $reduce_or$issuer_ls180.v:159097$9447_Y - attribute \src "issuer_ls180.v:159098.17-159098.103" - wire $reduce_or$issuer_ls180.v:159098$9448_Y - attribute \src "issuer_ls180.v:159100.17-159100.109" - wire $reduce_or$issuer_ls180.v:159100$9450_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159085$9435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:159085$9435_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159087$9437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:159087$9437_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159089$9439 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:159089$9439_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:159090$9440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$issuer_ls180.v:159090$9440_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159092$9442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$issuer_ls180.v:159092$9442_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159094$9444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:159094$9444_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159096$9446 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$issuer_ls180.v:159096$9446_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159099$9449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:159099$9449_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159086$9436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:159086$9436_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159088$9438 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:159088$9438_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159091$9441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$issuer_ls180.v:159091$9441_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159093$9443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$issuer_ls180.v:159093$9443_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159095$9445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$issuer_ls180.v:159095$9445_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:159097$9447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:159097$9447_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159098$9448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:159098$9448_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159100$9450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:159100$9450_Y - end - connect \$7 $not$issuer_ls180.v:159085$9435_Y - connect \$12 $reduce_or$issuer_ls180.v:159086$9436_Y - connect \$11 $not$issuer_ls180.v:159087$9437_Y - connect \$16 $reduce_or$issuer_ls180.v:159088$9438_Y - connect \$15 $not$issuer_ls180.v:159089$9439_Y - connect \$1 $not$issuer_ls180.v:159090$9440_Y - connect \$20 $reduce_or$issuer_ls180.v:159091$9441_Y - connect \$19 $not$issuer_ls180.v:159092$9442_Y - connect \$24 $reduce_or$issuer_ls180.v:159093$9443_Y - connect \$23 $not$issuer_ls180.v:159094$9444_Y - connect \$28 $reduce_or$issuer_ls180.v:159095$9445_Y - connect \$27 $not$issuer_ls180.v:159096$9446_Y - connect \$31 $reduce_or$issuer_ls180.v:159097$9447_Y - connect \$4 $reduce_or$issuer_ls180.v:159098$9448_Y - connect \$3 $not$issuer_ls180.v:159099$9449_Y - connect \$8 $reduce_or$issuer_ls180.v:159100$9450_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:159116.1-159200.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$156 - attribute \src "issuer_ls180.v:159173.17-159173.91" - wire $not$issuer_ls180.v:159173$9451_Y - attribute \src "issuer_ls180.v:159175.18-159175.93" - wire $not$issuer_ls180.v:159175$9453_Y - attribute \src "issuer_ls180.v:159177.18-159177.93" - wire $not$issuer_ls180.v:159177$9455_Y - attribute \src "issuer_ls180.v:159178.17-159178.138" - wire width 8 $not$issuer_ls180.v:159178$9456_Y - attribute \src "issuer_ls180.v:159180.18-159180.93" - wire $not$issuer_ls180.v:159180$9458_Y - attribute \src "issuer_ls180.v:159182.18-159182.93" - wire $not$issuer_ls180.v:159182$9460_Y - attribute \src "issuer_ls180.v:159184.18-159184.93" - wire $not$issuer_ls180.v:159184$9462_Y - attribute \src "issuer_ls180.v:159187.17-159187.91" - wire $not$issuer_ls180.v:159187$9465_Y - attribute \src "issuer_ls180.v:159174.18-159174.116" - wire $reduce_or$issuer_ls180.v:159174$9452_Y - attribute \src "issuer_ls180.v:159176.18-159176.122" - wire $reduce_or$issuer_ls180.v:159176$9454_Y - attribute \src "issuer_ls180.v:159179.18-159179.128" - wire $reduce_or$issuer_ls180.v:159179$9457_Y - attribute \src "issuer_ls180.v:159181.18-159181.134" - wire $reduce_or$issuer_ls180.v:159181$9459_Y - attribute \src "issuer_ls180.v:159183.18-159183.140" - wire $reduce_or$issuer_ls180.v:159183$9461_Y - attribute \src "issuer_ls180.v:159185.18-159185.90" - wire $reduce_or$issuer_ls180.v:159185$9463_Y - attribute \src "issuer_ls180.v:159186.17-159186.103" - wire $reduce_or$issuer_ls180.v:159186$9464_Y - attribute \src "issuer_ls180.v:159188.17-159188.109" - wire $reduce_or$issuer_ls180.v:159188$9466_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159173$9451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:159173$9451_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159175$9453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:159175$9453_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159177$9455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:159177$9455_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:159178$9456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$issuer_ls180.v:159178$9456_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159180$9458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$issuer_ls180.v:159180$9458_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159182$9460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:159182$9460_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159184$9462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$issuer_ls180.v:159184$9462_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159187$9465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:159187$9465_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159174$9452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:159174$9452_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159176$9454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:159176$9454_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159179$9457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$issuer_ls180.v:159179$9457_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159181$9459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$issuer_ls180.v:159181$9459_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159183$9461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$issuer_ls180.v:159183$9461_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:159185$9463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:159185$9463_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159186$9464 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:159186$9464_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159188$9466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:159188$9466_Y - end - connect \$7 $not$issuer_ls180.v:159173$9451_Y - connect \$12 $reduce_or$issuer_ls180.v:159174$9452_Y - connect \$11 $not$issuer_ls180.v:159175$9453_Y - connect \$16 $reduce_or$issuer_ls180.v:159176$9454_Y - connect \$15 $not$issuer_ls180.v:159177$9455_Y - connect \$1 $not$issuer_ls180.v:159178$9456_Y - connect \$20 $reduce_or$issuer_ls180.v:159179$9457_Y - connect \$19 $not$issuer_ls180.v:159180$9458_Y - connect \$24 $reduce_or$issuer_ls180.v:159181$9459_Y - connect \$23 $not$issuer_ls180.v:159182$9460_Y - connect \$28 $reduce_or$issuer_ls180.v:159183$9461_Y - connect \$27 $not$issuer_ls180.v:159184$9462_Y - connect \$31 $reduce_or$issuer_ls180.v:159185$9463_Y - connect \$4 $reduce_or$issuer_ls180.v:159186$9464_Y - connect \$3 $not$issuer_ls180.v:159187$9465_Y - connect \$8 $reduce_or$issuer_ls180.v:159188$9466_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:159204.1-159288.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$158 - attribute \src "issuer_ls180.v:159261.17-159261.91" - wire $not$issuer_ls180.v:159261$9467_Y - attribute \src "issuer_ls180.v:159263.18-159263.93" - wire $not$issuer_ls180.v:159263$9469_Y - attribute \src "issuer_ls180.v:159265.18-159265.93" - wire $not$issuer_ls180.v:159265$9471_Y - attribute \src "issuer_ls180.v:159266.17-159266.138" - wire width 8 $not$issuer_ls180.v:159266$9472_Y - attribute \src "issuer_ls180.v:159268.18-159268.93" - wire $not$issuer_ls180.v:159268$9474_Y - attribute \src "issuer_ls180.v:159270.18-159270.93" - wire $not$issuer_ls180.v:159270$9476_Y - attribute \src "issuer_ls180.v:159272.18-159272.93" - wire $not$issuer_ls180.v:159272$9478_Y - attribute \src "issuer_ls180.v:159275.17-159275.91" - wire $not$issuer_ls180.v:159275$9481_Y - attribute \src "issuer_ls180.v:159262.18-159262.116" - wire $reduce_or$issuer_ls180.v:159262$9468_Y - attribute \src "issuer_ls180.v:159264.18-159264.122" - wire $reduce_or$issuer_ls180.v:159264$9470_Y - attribute \src "issuer_ls180.v:159267.18-159267.128" - wire $reduce_or$issuer_ls180.v:159267$9473_Y - attribute \src "issuer_ls180.v:159269.18-159269.134" - wire $reduce_or$issuer_ls180.v:159269$9475_Y - attribute \src "issuer_ls180.v:159271.18-159271.140" - wire $reduce_or$issuer_ls180.v:159271$9477_Y - attribute \src "issuer_ls180.v:159273.18-159273.90" - wire $reduce_or$issuer_ls180.v:159273$9479_Y - attribute \src "issuer_ls180.v:159274.17-159274.103" - wire $reduce_or$issuer_ls180.v:159274$9480_Y - attribute \src "issuer_ls180.v:159276.17-159276.109" - wire $reduce_or$issuer_ls180.v:159276$9482_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159261$9467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:159261$9467_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159263$9469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:159263$9469_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159265$9471 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:159265$9471_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:159266$9472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$issuer_ls180.v:159266$9472_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159268$9474 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$issuer_ls180.v:159268$9474_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159270$9476 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:159270$9476_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159272$9478 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$issuer_ls180.v:159272$9478_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159275$9481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:159275$9481_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159262$9468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:159262$9468_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159264$9470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:159264$9470_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159267$9473 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$issuer_ls180.v:159267$9473_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159269$9475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$issuer_ls180.v:159269$9475_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159271$9477 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$issuer_ls180.v:159271$9477_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:159273$9479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:159273$9479_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159274$9480 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:159274$9480_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159276$9482 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:159276$9482_Y - end - connect \$7 $not$issuer_ls180.v:159261$9467_Y - connect \$12 $reduce_or$issuer_ls180.v:159262$9468_Y - connect \$11 $not$issuer_ls180.v:159263$9469_Y - connect \$16 $reduce_or$issuer_ls180.v:159264$9470_Y - connect \$15 $not$issuer_ls180.v:159265$9471_Y - connect \$1 $not$issuer_ls180.v:159266$9472_Y - connect \$20 $reduce_or$issuer_ls180.v:159267$9473_Y - connect \$19 $not$issuer_ls180.v:159268$9474_Y - connect \$24 $reduce_or$issuer_ls180.v:159269$9475_Y - connect \$23 $not$issuer_ls180.v:159270$9476_Y - connect \$28 $reduce_or$issuer_ls180.v:159271$9477_Y - connect \$27 $not$issuer_ls180.v:159272$9478_Y - connect \$31 $reduce_or$issuer_ls180.v:159273$9479_Y - connect \$4 $reduce_or$issuer_ls180.v:159274$9480_Y - connect \$3 $not$issuer_ls180.v:159275$9481_Y - connect \$8 $reduce_or$issuer_ls180.v:159276$9482_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:159292.1-159376.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$165 - attribute \src "issuer_ls180.v:159349.17-159349.91" - wire $not$issuer_ls180.v:159349$9483_Y - attribute \src "issuer_ls180.v:159351.18-159351.93" - wire $not$issuer_ls180.v:159351$9485_Y - attribute \src "issuer_ls180.v:159353.18-159353.93" - wire $not$issuer_ls180.v:159353$9487_Y - attribute \src "issuer_ls180.v:159354.17-159354.138" - wire width 8 $not$issuer_ls180.v:159354$9488_Y - attribute \src "issuer_ls180.v:159356.18-159356.93" - wire $not$issuer_ls180.v:159356$9490_Y - attribute \src "issuer_ls180.v:159358.18-159358.93" - wire $not$issuer_ls180.v:159358$9492_Y - attribute \src "issuer_ls180.v:159360.18-159360.93" - wire $not$issuer_ls180.v:159360$9494_Y - attribute \src "issuer_ls180.v:159363.17-159363.91" - wire $not$issuer_ls180.v:159363$9497_Y - attribute \src "issuer_ls180.v:159350.18-159350.116" - wire $reduce_or$issuer_ls180.v:159350$9484_Y - attribute \src "issuer_ls180.v:159352.18-159352.122" - wire $reduce_or$issuer_ls180.v:159352$9486_Y - attribute \src "issuer_ls180.v:159355.18-159355.128" - wire $reduce_or$issuer_ls180.v:159355$9489_Y - attribute \src "issuer_ls180.v:159357.18-159357.134" - wire $reduce_or$issuer_ls180.v:159357$9491_Y - attribute \src "issuer_ls180.v:159359.18-159359.140" - wire $reduce_or$issuer_ls180.v:159359$9493_Y - attribute \src "issuer_ls180.v:159361.18-159361.90" - wire $reduce_or$issuer_ls180.v:159361$9495_Y - attribute \src "issuer_ls180.v:159362.17-159362.103" - wire $reduce_or$issuer_ls180.v:159362$9496_Y - attribute \src "issuer_ls180.v:159364.17-159364.109" - wire $reduce_or$issuer_ls180.v:159364$9498_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159349$9483 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:159349$9483_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159351$9485 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:159351$9485_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159353$9487 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:159353$9487_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:159354$9488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$issuer_ls180.v:159354$9488_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159356$9490 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$issuer_ls180.v:159356$9490_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159358$9492 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:159358$9492_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159360$9494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$issuer_ls180.v:159360$9494_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159363$9497 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:159363$9497_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159350$9484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:159350$9484_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159352$9486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:159352$9486_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159355$9489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$issuer_ls180.v:159355$9489_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159357$9491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$issuer_ls180.v:159357$9491_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159359$9493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$issuer_ls180.v:159359$9493_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:159361$9495 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:159361$9495_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159362$9496 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:159362$9496_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159364$9498 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:159364$9498_Y - end - connect \$7 $not$issuer_ls180.v:159349$9483_Y - connect \$12 $reduce_or$issuer_ls180.v:159350$9484_Y - connect \$11 $not$issuer_ls180.v:159351$9485_Y - connect \$16 $reduce_or$issuer_ls180.v:159352$9486_Y - connect \$15 $not$issuer_ls180.v:159353$9487_Y - connect \$1 $not$issuer_ls180.v:159354$9488_Y - connect \$20 $reduce_or$issuer_ls180.v:159355$9489_Y - connect \$19 $not$issuer_ls180.v:159356$9490_Y - connect \$24 $reduce_or$issuer_ls180.v:159357$9491_Y - connect \$23 $not$issuer_ls180.v:159358$9492_Y - connect \$28 $reduce_or$issuer_ls180.v:159359$9493_Y - connect \$27 $not$issuer_ls180.v:159360$9494_Y - connect \$31 $reduce_or$issuer_ls180.v:159361$9495_Y - connect \$4 $reduce_or$issuer_ls180.v:159362$9496_Y - connect \$3 $not$issuer_ls180.v:159363$9497_Y - connect \$8 $reduce_or$issuer_ls180.v:159364$9498_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:159380.1-159464.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$167 - attribute \src "issuer_ls180.v:159437.17-159437.91" - wire $not$issuer_ls180.v:159437$9499_Y - attribute \src "issuer_ls180.v:159439.18-159439.93" - wire $not$issuer_ls180.v:159439$9501_Y - attribute \src "issuer_ls180.v:159441.18-159441.93" - wire $not$issuer_ls180.v:159441$9503_Y - attribute \src "issuer_ls180.v:159442.17-159442.138" - wire width 8 $not$issuer_ls180.v:159442$9504_Y - attribute \src "issuer_ls180.v:159444.18-159444.93" - wire $not$issuer_ls180.v:159444$9506_Y - attribute \src "issuer_ls180.v:159446.18-159446.93" - wire $not$issuer_ls180.v:159446$9508_Y - attribute \src "issuer_ls180.v:159448.18-159448.93" - wire $not$issuer_ls180.v:159448$9510_Y - attribute \src "issuer_ls180.v:159451.17-159451.91" - wire $not$issuer_ls180.v:159451$9513_Y - attribute \src "issuer_ls180.v:159438.18-159438.116" - wire $reduce_or$issuer_ls180.v:159438$9500_Y - attribute \src "issuer_ls180.v:159440.18-159440.122" - wire $reduce_or$issuer_ls180.v:159440$9502_Y - attribute \src "issuer_ls180.v:159443.18-159443.128" - wire $reduce_or$issuer_ls180.v:159443$9505_Y - attribute \src "issuer_ls180.v:159445.18-159445.134" - wire $reduce_or$issuer_ls180.v:159445$9507_Y - attribute \src "issuer_ls180.v:159447.18-159447.140" - wire $reduce_or$issuer_ls180.v:159447$9509_Y - attribute \src "issuer_ls180.v:159449.18-159449.90" - wire $reduce_or$issuer_ls180.v:159449$9511_Y - attribute \src "issuer_ls180.v:159450.17-159450.103" - wire $reduce_or$issuer_ls180.v:159450$9512_Y - attribute \src "issuer_ls180.v:159452.17-159452.109" - wire $reduce_or$issuer_ls180.v:159452$9514_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159437$9499 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:159437$9499_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159439$9501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:159439$9501_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159441$9503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:159441$9503_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:159442$9504 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$issuer_ls180.v:159442$9504_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159444$9506 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$issuer_ls180.v:159444$9506_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159446$9508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:159446$9508_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159448$9510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$issuer_ls180.v:159448$9510_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159451$9513 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:159451$9513_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159438$9500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:159438$9500_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159440$9502 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:159440$9502_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159443$9505 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$issuer_ls180.v:159443$9505_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159445$9507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$issuer_ls180.v:159445$9507_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159447$9509 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$issuer_ls180.v:159447$9509_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:159449$9511 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:159449$9511_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159450$9512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:159450$9512_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159452$9514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:159452$9514_Y - end - connect \$7 $not$issuer_ls180.v:159437$9499_Y - connect \$12 $reduce_or$issuer_ls180.v:159438$9500_Y - connect \$11 $not$issuer_ls180.v:159439$9501_Y - connect \$16 $reduce_or$issuer_ls180.v:159440$9502_Y - connect \$15 $not$issuer_ls180.v:159441$9503_Y - connect \$1 $not$issuer_ls180.v:159442$9504_Y - connect \$20 $reduce_or$issuer_ls180.v:159443$9505_Y - connect \$19 $not$issuer_ls180.v:159444$9506_Y - connect \$24 $reduce_or$issuer_ls180.v:159445$9507_Y - connect \$23 $not$issuer_ls180.v:159446$9508_Y - connect \$28 $reduce_or$issuer_ls180.v:159447$9509_Y - connect \$27 $not$issuer_ls180.v:159448$9510_Y - connect \$31 $reduce_or$issuer_ls180.v:159449$9511_Y - connect \$4 $reduce_or$issuer_ls180.v:159450$9512_Y - connect \$3 $not$issuer_ls180.v:159451$9513_Y - connect \$8 $reduce_or$issuer_ls180.v:159452$9514_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:159468.1-159552.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$172 - attribute \src "issuer_ls180.v:159525.17-159525.91" - wire $not$issuer_ls180.v:159525$9515_Y - attribute \src "issuer_ls180.v:159527.18-159527.93" - wire $not$issuer_ls180.v:159527$9517_Y - attribute \src "issuer_ls180.v:159529.18-159529.93" - wire $not$issuer_ls180.v:159529$9519_Y - attribute \src "issuer_ls180.v:159530.17-159530.138" - wire width 8 $not$issuer_ls180.v:159530$9520_Y - attribute \src "issuer_ls180.v:159532.18-159532.93" - wire $not$issuer_ls180.v:159532$9522_Y - attribute \src "issuer_ls180.v:159534.18-159534.93" - wire $not$issuer_ls180.v:159534$9524_Y - attribute \src "issuer_ls180.v:159536.18-159536.93" - wire $not$issuer_ls180.v:159536$9526_Y - attribute \src "issuer_ls180.v:159539.17-159539.91" - wire $not$issuer_ls180.v:159539$9529_Y - attribute \src "issuer_ls180.v:159526.18-159526.116" - wire $reduce_or$issuer_ls180.v:159526$9516_Y - attribute \src "issuer_ls180.v:159528.18-159528.122" - wire $reduce_or$issuer_ls180.v:159528$9518_Y - attribute \src "issuer_ls180.v:159531.18-159531.128" - wire $reduce_or$issuer_ls180.v:159531$9521_Y - attribute \src "issuer_ls180.v:159533.18-159533.134" - wire $reduce_or$issuer_ls180.v:159533$9523_Y - attribute \src "issuer_ls180.v:159535.18-159535.140" - wire $reduce_or$issuer_ls180.v:159535$9525_Y - attribute \src "issuer_ls180.v:159537.18-159537.90" - wire $reduce_or$issuer_ls180.v:159537$9527_Y - attribute \src "issuer_ls180.v:159538.17-159538.103" - wire $reduce_or$issuer_ls180.v:159538$9528_Y - attribute \src "issuer_ls180.v:159540.17-159540.109" - wire $reduce_or$issuer_ls180.v:159540$9530_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159525$9515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:159525$9515_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159527$9517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:159527$9517_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159529$9519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:159529$9519_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:159530$9520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$issuer_ls180.v:159530$9520_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159532$9522 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$issuer_ls180.v:159532$9522_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159534$9524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:159534$9524_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159536$9526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$issuer_ls180.v:159536$9526_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159539$9529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:159539$9529_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159526$9516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:159526$9516_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159528$9518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:159528$9518_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159531$9521 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$issuer_ls180.v:159531$9521_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159533$9523 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$issuer_ls180.v:159533$9523_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159535$9525 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$issuer_ls180.v:159535$9525_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:159537$9527 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:159537$9527_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159538$9528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:159538$9528_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159540$9530 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:159540$9530_Y - end - connect \$7 $not$issuer_ls180.v:159525$9515_Y - connect \$12 $reduce_or$issuer_ls180.v:159526$9516_Y - connect \$11 $not$issuer_ls180.v:159527$9517_Y - connect \$16 $reduce_or$issuer_ls180.v:159528$9518_Y - connect \$15 $not$issuer_ls180.v:159529$9519_Y - connect \$1 $not$issuer_ls180.v:159530$9520_Y - connect \$20 $reduce_or$issuer_ls180.v:159531$9521_Y - connect \$19 $not$issuer_ls180.v:159532$9522_Y - connect \$24 $reduce_or$issuer_ls180.v:159533$9523_Y - connect \$23 $not$issuer_ls180.v:159534$9524_Y - connect \$28 $reduce_or$issuer_ls180.v:159535$9525_Y - connect \$27 $not$issuer_ls180.v:159536$9526_Y - connect \$31 $reduce_or$issuer_ls180.v:159537$9527_Y - connect \$4 $reduce_or$issuer_ls180.v:159538$9528_Y - connect \$3 $not$issuer_ls180.v:159539$9529_Y - connect \$8 $reduce_or$issuer_ls180.v:159540$9530_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:159556.1-159640.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$174 - attribute \src "issuer_ls180.v:159613.17-159613.91" - wire $not$issuer_ls180.v:159613$9531_Y - attribute \src "issuer_ls180.v:159615.18-159615.93" - wire $not$issuer_ls180.v:159615$9533_Y - attribute \src "issuer_ls180.v:159617.18-159617.93" - wire $not$issuer_ls180.v:159617$9535_Y - attribute \src "issuer_ls180.v:159618.17-159618.138" - wire width 8 $not$issuer_ls180.v:159618$9536_Y - attribute \src "issuer_ls180.v:159620.18-159620.93" - wire $not$issuer_ls180.v:159620$9538_Y - attribute \src "issuer_ls180.v:159622.18-159622.93" - wire $not$issuer_ls180.v:159622$9540_Y - attribute \src "issuer_ls180.v:159624.18-159624.93" - wire $not$issuer_ls180.v:159624$9542_Y - attribute \src "issuer_ls180.v:159627.17-159627.91" - wire $not$issuer_ls180.v:159627$9545_Y - attribute \src "issuer_ls180.v:159614.18-159614.116" - wire $reduce_or$issuer_ls180.v:159614$9532_Y - attribute \src "issuer_ls180.v:159616.18-159616.122" - wire $reduce_or$issuer_ls180.v:159616$9534_Y - attribute \src "issuer_ls180.v:159619.18-159619.128" - wire $reduce_or$issuer_ls180.v:159619$9537_Y - attribute \src "issuer_ls180.v:159621.18-159621.134" - wire $reduce_or$issuer_ls180.v:159621$9539_Y - attribute \src "issuer_ls180.v:159623.18-159623.140" - wire $reduce_or$issuer_ls180.v:159623$9541_Y - attribute \src "issuer_ls180.v:159625.18-159625.90" - wire $reduce_or$issuer_ls180.v:159625$9543_Y - attribute \src "issuer_ls180.v:159626.17-159626.103" - wire $reduce_or$issuer_ls180.v:159626$9544_Y - attribute \src "issuer_ls180.v:159628.17-159628.109" - wire $reduce_or$issuer_ls180.v:159628$9546_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159613$9531 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:159613$9531_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159615$9533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:159615$9533_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159617$9535 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:159617$9535_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:159618$9536 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$issuer_ls180.v:159618$9536_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159620$9538 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$issuer_ls180.v:159620$9538_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159622$9540 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:159622$9540_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159624$9542 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$issuer_ls180.v:159624$9542_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159627$9545 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:159627$9545_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159614$9532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:159614$9532_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159616$9534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:159616$9534_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159619$9537 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$issuer_ls180.v:159619$9537_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159621$9539 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$issuer_ls180.v:159621$9539_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159623$9541 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$issuer_ls180.v:159623$9541_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:159625$9543 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:159625$9543_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159626$9544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:159626$9544_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159628$9546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:159628$9546_Y - end - connect \$7 $not$issuer_ls180.v:159613$9531_Y - connect \$12 $reduce_or$issuer_ls180.v:159614$9532_Y - connect \$11 $not$issuer_ls180.v:159615$9533_Y - connect \$16 $reduce_or$issuer_ls180.v:159616$9534_Y - connect \$15 $not$issuer_ls180.v:159617$9535_Y - connect \$1 $not$issuer_ls180.v:159618$9536_Y - connect \$20 $reduce_or$issuer_ls180.v:159619$9537_Y - connect \$19 $not$issuer_ls180.v:159620$9538_Y - connect \$24 $reduce_or$issuer_ls180.v:159621$9539_Y - connect \$23 $not$issuer_ls180.v:159622$9540_Y - connect \$28 $reduce_or$issuer_ls180.v:159623$9541_Y - connect \$27 $not$issuer_ls180.v:159624$9542_Y - connect \$31 $reduce_or$issuer_ls180.v:159625$9543_Y - connect \$4 $reduce_or$issuer_ls180.v:159626$9544_Y - connect \$3 $not$issuer_ls180.v:159627$9545_Y - connect \$8 $reduce_or$issuer_ls180.v:159628$9546_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:159644.1-159728.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$181 - attribute \src "issuer_ls180.v:159701.17-159701.91" - wire $not$issuer_ls180.v:159701$9547_Y - attribute \src "issuer_ls180.v:159703.18-159703.93" - wire $not$issuer_ls180.v:159703$9549_Y - attribute \src "issuer_ls180.v:159705.18-159705.93" - wire $not$issuer_ls180.v:159705$9551_Y - attribute \src "issuer_ls180.v:159706.17-159706.138" - wire width 8 $not$issuer_ls180.v:159706$9552_Y - attribute \src "issuer_ls180.v:159708.18-159708.93" - wire $not$issuer_ls180.v:159708$9554_Y - attribute \src "issuer_ls180.v:159710.18-159710.93" - wire $not$issuer_ls180.v:159710$9556_Y - attribute \src "issuer_ls180.v:159712.18-159712.93" - wire $not$issuer_ls180.v:159712$9558_Y - attribute \src "issuer_ls180.v:159715.17-159715.91" - wire $not$issuer_ls180.v:159715$9561_Y - attribute \src "issuer_ls180.v:159702.18-159702.116" - wire $reduce_or$issuer_ls180.v:159702$9548_Y - attribute \src "issuer_ls180.v:159704.18-159704.122" - wire $reduce_or$issuer_ls180.v:159704$9550_Y - attribute \src "issuer_ls180.v:159707.18-159707.128" - wire $reduce_or$issuer_ls180.v:159707$9553_Y - attribute \src "issuer_ls180.v:159709.18-159709.134" - wire $reduce_or$issuer_ls180.v:159709$9555_Y - attribute \src "issuer_ls180.v:159711.18-159711.140" - wire $reduce_or$issuer_ls180.v:159711$9557_Y - attribute \src "issuer_ls180.v:159713.18-159713.90" - wire $reduce_or$issuer_ls180.v:159713$9559_Y - attribute \src "issuer_ls180.v:159714.17-159714.103" - wire $reduce_or$issuer_ls180.v:159714$9560_Y - attribute \src "issuer_ls180.v:159716.17-159716.109" - wire $reduce_or$issuer_ls180.v:159716$9562_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159701$9547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:159701$9547_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159703$9549 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:159703$9549_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159705$9551 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:159705$9551_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:159706$9552 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$issuer_ls180.v:159706$9552_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159708$9554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$issuer_ls180.v:159708$9554_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159710$9556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:159710$9556_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159712$9558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$issuer_ls180.v:159712$9558_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159715$9561 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:159715$9561_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159702$9548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:159702$9548_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159704$9550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:159704$9550_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159707$9553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$issuer_ls180.v:159707$9553_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159709$9555 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$issuer_ls180.v:159709$9555_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159711$9557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$issuer_ls180.v:159711$9557_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:159713$9559 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:159713$9559_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159714$9560 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:159714$9560_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159716$9562 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:159716$9562_Y - end - connect \$7 $not$issuer_ls180.v:159701$9547_Y - connect \$12 $reduce_or$issuer_ls180.v:159702$9548_Y - connect \$11 $not$issuer_ls180.v:159703$9549_Y - connect \$16 $reduce_or$issuer_ls180.v:159704$9550_Y - connect \$15 $not$issuer_ls180.v:159705$9551_Y - connect \$1 $not$issuer_ls180.v:159706$9552_Y - connect \$20 $reduce_or$issuer_ls180.v:159707$9553_Y - connect \$19 $not$issuer_ls180.v:159708$9554_Y - connect \$24 $reduce_or$issuer_ls180.v:159709$9555_Y - connect \$23 $not$issuer_ls180.v:159710$9556_Y - connect \$28 $reduce_or$issuer_ls180.v:159711$9557_Y - connect \$27 $not$issuer_ls180.v:159712$9558_Y - connect \$31 $reduce_or$issuer_ls180.v:159713$9559_Y - connect \$4 $reduce_or$issuer_ls180.v:159714$9560_Y - connect \$3 $not$issuer_ls180.v:159715$9561_Y - connect \$8 $reduce_or$issuer_ls180.v:159716$9562_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:159732.1-159816.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$183 - attribute \src "issuer_ls180.v:159789.17-159789.91" - wire $not$issuer_ls180.v:159789$9563_Y - attribute \src "issuer_ls180.v:159791.18-159791.93" - wire $not$issuer_ls180.v:159791$9565_Y - attribute \src "issuer_ls180.v:159793.18-159793.93" - wire $not$issuer_ls180.v:159793$9567_Y - attribute \src "issuer_ls180.v:159794.17-159794.138" - wire width 8 $not$issuer_ls180.v:159794$9568_Y - attribute \src "issuer_ls180.v:159796.18-159796.93" - wire $not$issuer_ls180.v:159796$9570_Y - attribute \src "issuer_ls180.v:159798.18-159798.93" - wire $not$issuer_ls180.v:159798$9572_Y - attribute \src "issuer_ls180.v:159800.18-159800.93" - wire $not$issuer_ls180.v:159800$9574_Y - attribute \src "issuer_ls180.v:159803.17-159803.91" - wire $not$issuer_ls180.v:159803$9577_Y - attribute \src "issuer_ls180.v:159790.18-159790.116" - wire $reduce_or$issuer_ls180.v:159790$9564_Y - attribute \src "issuer_ls180.v:159792.18-159792.122" - wire $reduce_or$issuer_ls180.v:159792$9566_Y - attribute \src "issuer_ls180.v:159795.18-159795.128" - wire $reduce_or$issuer_ls180.v:159795$9569_Y - attribute \src "issuer_ls180.v:159797.18-159797.134" - wire $reduce_or$issuer_ls180.v:159797$9571_Y - attribute \src "issuer_ls180.v:159799.18-159799.140" - wire $reduce_or$issuer_ls180.v:159799$9573_Y - attribute \src "issuer_ls180.v:159801.18-159801.90" - wire $reduce_or$issuer_ls180.v:159801$9575_Y - attribute \src "issuer_ls180.v:159802.17-159802.103" - wire $reduce_or$issuer_ls180.v:159802$9576_Y - attribute \src "issuer_ls180.v:159804.17-159804.109" - wire $reduce_or$issuer_ls180.v:159804$9578_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159789$9563 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:159789$9563_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159791$9565 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:159791$9565_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159793$9567 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:159793$9567_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:159794$9568 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$issuer_ls180.v:159794$9568_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159796$9570 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$issuer_ls180.v:159796$9570_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159798$9572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:159798$9572_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159800$9574 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$issuer_ls180.v:159800$9574_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159803$9577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:159803$9577_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159790$9564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:159790$9564_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159792$9566 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:159792$9566_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159795$9569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$issuer_ls180.v:159795$9569_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159797$9571 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$issuer_ls180.v:159797$9571_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159799$9573 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$issuer_ls180.v:159799$9573_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:159801$9575 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:159801$9575_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159802$9576 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:159802$9576_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159804$9578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:159804$9578_Y - end - connect \$7 $not$issuer_ls180.v:159789$9563_Y - connect \$12 $reduce_or$issuer_ls180.v:159790$9564_Y - connect \$11 $not$issuer_ls180.v:159791$9565_Y - connect \$16 $reduce_or$issuer_ls180.v:159792$9566_Y - connect \$15 $not$issuer_ls180.v:159793$9567_Y - connect \$1 $not$issuer_ls180.v:159794$9568_Y - connect \$20 $reduce_or$issuer_ls180.v:159795$9569_Y - connect \$19 $not$issuer_ls180.v:159796$9570_Y - connect \$24 $reduce_or$issuer_ls180.v:159797$9571_Y - connect \$23 $not$issuer_ls180.v:159798$9572_Y - connect \$28 $reduce_or$issuer_ls180.v:159799$9573_Y - connect \$27 $not$issuer_ls180.v:159800$9574_Y - connect \$31 $reduce_or$issuer_ls180.v:159801$9575_Y - connect \$4 $reduce_or$issuer_ls180.v:159802$9576_Y - connect \$3 $not$issuer_ls180.v:159803$9577_Y - connect \$8 $reduce_or$issuer_ls180.v:159804$9578_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:159820.1-159904.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$189 - attribute \src "issuer_ls180.v:159877.17-159877.91" - wire $not$issuer_ls180.v:159877$9579_Y - attribute \src "issuer_ls180.v:159879.18-159879.93" - wire $not$issuer_ls180.v:159879$9581_Y - attribute \src "issuer_ls180.v:159881.18-159881.93" - wire $not$issuer_ls180.v:159881$9583_Y - attribute \src "issuer_ls180.v:159882.17-159882.138" - wire width 8 $not$issuer_ls180.v:159882$9584_Y - attribute \src "issuer_ls180.v:159884.18-159884.93" - wire $not$issuer_ls180.v:159884$9586_Y - attribute \src "issuer_ls180.v:159886.18-159886.93" - wire $not$issuer_ls180.v:159886$9588_Y - attribute \src "issuer_ls180.v:159888.18-159888.93" - wire $not$issuer_ls180.v:159888$9590_Y - attribute \src "issuer_ls180.v:159891.17-159891.91" - wire $not$issuer_ls180.v:159891$9593_Y - attribute \src "issuer_ls180.v:159878.18-159878.116" - wire $reduce_or$issuer_ls180.v:159878$9580_Y - attribute \src "issuer_ls180.v:159880.18-159880.122" - wire $reduce_or$issuer_ls180.v:159880$9582_Y - attribute \src "issuer_ls180.v:159883.18-159883.128" - wire $reduce_or$issuer_ls180.v:159883$9585_Y - attribute \src "issuer_ls180.v:159885.18-159885.134" - wire $reduce_or$issuer_ls180.v:159885$9587_Y - attribute \src "issuer_ls180.v:159887.18-159887.140" - wire $reduce_or$issuer_ls180.v:159887$9589_Y - attribute \src "issuer_ls180.v:159889.18-159889.90" - wire $reduce_or$issuer_ls180.v:159889$9591_Y - attribute \src "issuer_ls180.v:159890.17-159890.103" - wire $reduce_or$issuer_ls180.v:159890$9592_Y - attribute \src "issuer_ls180.v:159892.17-159892.109" - wire $reduce_or$issuer_ls180.v:159892$9594_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159877$9579 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:159877$9579_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159879$9581 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:159879$9581_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159881$9583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:159881$9583_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:159882$9584 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$issuer_ls180.v:159882$9584_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159884$9586 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$issuer_ls180.v:159884$9586_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159886$9588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:159886$9588_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159888$9590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$issuer_ls180.v:159888$9590_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159891$9593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:159891$9593_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159878$9580 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:159878$9580_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159880$9582 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:159880$9582_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159883$9585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$issuer_ls180.v:159883$9585_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159885$9587 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$issuer_ls180.v:159885$9587_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159887$9589 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$issuer_ls180.v:159887$9589_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:159889$9591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:159889$9591_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159890$9592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:159890$9592_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159892$9594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:159892$9594_Y - end - connect \$7 $not$issuer_ls180.v:159877$9579_Y - connect \$12 $reduce_or$issuer_ls180.v:159878$9580_Y - connect \$11 $not$issuer_ls180.v:159879$9581_Y - connect \$16 $reduce_or$issuer_ls180.v:159880$9582_Y - connect \$15 $not$issuer_ls180.v:159881$9583_Y - connect \$1 $not$issuer_ls180.v:159882$9584_Y - connect \$20 $reduce_or$issuer_ls180.v:159883$9585_Y - connect \$19 $not$issuer_ls180.v:159884$9586_Y - connect \$24 $reduce_or$issuer_ls180.v:159885$9587_Y - connect \$23 $not$issuer_ls180.v:159886$9588_Y - connect \$28 $reduce_or$issuer_ls180.v:159887$9589_Y - connect \$27 $not$issuer_ls180.v:159888$9590_Y - connect \$31 $reduce_or$issuer_ls180.v:159889$9591_Y - connect \$4 $reduce_or$issuer_ls180.v:159890$9592_Y - connect \$3 $not$issuer_ls180.v:159891$9593_Y - connect \$8 $reduce_or$issuer_ls180.v:159892$9594_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:159908.1-159992.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$191 - attribute \src "issuer_ls180.v:159965.17-159965.91" - wire $not$issuer_ls180.v:159965$9595_Y - attribute \src "issuer_ls180.v:159967.18-159967.93" - wire $not$issuer_ls180.v:159967$9597_Y - attribute \src "issuer_ls180.v:159969.18-159969.93" - wire $not$issuer_ls180.v:159969$9599_Y - attribute \src "issuer_ls180.v:159970.17-159970.138" - wire width 8 $not$issuer_ls180.v:159970$9600_Y - attribute \src "issuer_ls180.v:159972.18-159972.93" - wire $not$issuer_ls180.v:159972$9602_Y - attribute \src "issuer_ls180.v:159974.18-159974.93" - wire $not$issuer_ls180.v:159974$9604_Y - attribute \src "issuer_ls180.v:159976.18-159976.93" - wire $not$issuer_ls180.v:159976$9606_Y - attribute \src "issuer_ls180.v:159979.17-159979.91" - wire $not$issuer_ls180.v:159979$9609_Y - attribute \src "issuer_ls180.v:159966.18-159966.116" - wire $reduce_or$issuer_ls180.v:159966$9596_Y - attribute \src "issuer_ls180.v:159968.18-159968.122" - wire $reduce_or$issuer_ls180.v:159968$9598_Y - attribute \src "issuer_ls180.v:159971.18-159971.128" - wire $reduce_or$issuer_ls180.v:159971$9601_Y - attribute \src "issuer_ls180.v:159973.18-159973.134" - wire $reduce_or$issuer_ls180.v:159973$9603_Y - attribute \src "issuer_ls180.v:159975.18-159975.140" - wire $reduce_or$issuer_ls180.v:159975$9605_Y - attribute \src "issuer_ls180.v:159977.18-159977.90" - wire $reduce_or$issuer_ls180.v:159977$9607_Y - attribute \src "issuer_ls180.v:159978.17-159978.103" - wire $reduce_or$issuer_ls180.v:159978$9608_Y - attribute \src "issuer_ls180.v:159980.17-159980.109" - wire $reduce_or$issuer_ls180.v:159980$9610_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159965$9595 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:159965$9595_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159967$9597 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:159967$9597_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159969$9599 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:159969$9599_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:159970$9600 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$issuer_ls180.v:159970$9600_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159972$9602 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$issuer_ls180.v:159972$9602_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159974$9604 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:159974$9604_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159976$9606 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$issuer_ls180.v:159976$9606_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:159979$9609 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:159979$9609_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159966$9596 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:159966$9596_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159968$9598 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:159968$9598_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159971$9601 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$issuer_ls180.v:159971$9601_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159973$9603 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$issuer_ls180.v:159973$9603_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159975$9605 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$issuer_ls180.v:159975$9605_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:159977$9607 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:159977$9607_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159978$9608 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:159978$9608_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:159980$9610 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:159980$9610_Y - end - connect \$7 $not$issuer_ls180.v:159965$9595_Y - connect \$12 $reduce_or$issuer_ls180.v:159966$9596_Y - connect \$11 $not$issuer_ls180.v:159967$9597_Y - connect \$16 $reduce_or$issuer_ls180.v:159968$9598_Y - connect \$15 $not$issuer_ls180.v:159969$9599_Y - connect \$1 $not$issuer_ls180.v:159970$9600_Y - connect \$20 $reduce_or$issuer_ls180.v:159971$9601_Y - connect \$19 $not$issuer_ls180.v:159972$9602_Y - connect \$24 $reduce_or$issuer_ls180.v:159973$9603_Y - connect \$23 $not$issuer_ls180.v:159974$9604_Y - connect \$28 $reduce_or$issuer_ls180.v:159975$9605_Y - connect \$27 $not$issuer_ls180.v:159976$9606_Y - connect \$31 $reduce_or$issuer_ls180.v:159977$9607_Y - connect \$4 $reduce_or$issuer_ls180.v:159978$9608_Y - connect \$3 $not$issuer_ls180.v:159979$9609_Y - connect \$8 $reduce_or$issuer_ls180.v:159980$9610_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:159996.1-160080.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$197 - attribute \src "issuer_ls180.v:160053.17-160053.91" - wire $not$issuer_ls180.v:160053$9611_Y - attribute \src "issuer_ls180.v:160055.18-160055.93" - wire $not$issuer_ls180.v:160055$9613_Y - attribute \src "issuer_ls180.v:160057.18-160057.93" - wire $not$issuer_ls180.v:160057$9615_Y - attribute \src "issuer_ls180.v:160058.17-160058.138" - wire width 8 $not$issuer_ls180.v:160058$9616_Y - attribute \src "issuer_ls180.v:160060.18-160060.93" - wire $not$issuer_ls180.v:160060$9618_Y - attribute \src "issuer_ls180.v:160062.18-160062.93" - wire $not$issuer_ls180.v:160062$9620_Y - attribute \src "issuer_ls180.v:160064.18-160064.93" - wire $not$issuer_ls180.v:160064$9622_Y - attribute \src "issuer_ls180.v:160067.17-160067.91" - wire $not$issuer_ls180.v:160067$9625_Y - attribute \src "issuer_ls180.v:160054.18-160054.116" - wire $reduce_or$issuer_ls180.v:160054$9612_Y - attribute \src "issuer_ls180.v:160056.18-160056.122" - wire $reduce_or$issuer_ls180.v:160056$9614_Y - attribute \src "issuer_ls180.v:160059.18-160059.128" - wire $reduce_or$issuer_ls180.v:160059$9617_Y - attribute \src "issuer_ls180.v:160061.18-160061.134" - wire $reduce_or$issuer_ls180.v:160061$9619_Y - attribute \src "issuer_ls180.v:160063.18-160063.140" - wire $reduce_or$issuer_ls180.v:160063$9621_Y - attribute \src "issuer_ls180.v:160065.18-160065.90" - wire $reduce_or$issuer_ls180.v:160065$9623_Y - attribute \src "issuer_ls180.v:160066.17-160066.103" - wire $reduce_or$issuer_ls180.v:160066$9624_Y - attribute \src "issuer_ls180.v:160068.17-160068.109" - wire $reduce_or$issuer_ls180.v:160068$9626_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160053$9611 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:160053$9611_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160055$9613 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:160055$9613_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160057$9615 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:160057$9615_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:160058$9616 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$issuer_ls180.v:160058$9616_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160060$9618 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$issuer_ls180.v:160060$9618_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160062$9620 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:160062$9620_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160064$9622 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$issuer_ls180.v:160064$9622_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160067$9625 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:160067$9625_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160054$9612 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:160054$9612_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160056$9614 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:160056$9614_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160059$9617 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$issuer_ls180.v:160059$9617_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160061$9619 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$issuer_ls180.v:160061$9619_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160063$9621 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$issuer_ls180.v:160063$9621_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:160065$9623 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:160065$9623_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160066$9624 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:160066$9624_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160068$9626 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:160068$9626_Y - end - connect \$7 $not$issuer_ls180.v:160053$9611_Y - connect \$12 $reduce_or$issuer_ls180.v:160054$9612_Y - connect \$11 $not$issuer_ls180.v:160055$9613_Y - connect \$16 $reduce_or$issuer_ls180.v:160056$9614_Y - connect \$15 $not$issuer_ls180.v:160057$9615_Y - connect \$1 $not$issuer_ls180.v:160058$9616_Y - connect \$20 $reduce_or$issuer_ls180.v:160059$9617_Y - connect \$19 $not$issuer_ls180.v:160060$9618_Y - connect \$24 $reduce_or$issuer_ls180.v:160061$9619_Y - connect \$23 $not$issuer_ls180.v:160062$9620_Y - connect \$28 $reduce_or$issuer_ls180.v:160063$9621_Y - connect \$27 $not$issuer_ls180.v:160064$9622_Y - connect \$31 $reduce_or$issuer_ls180.v:160065$9623_Y - connect \$4 $reduce_or$issuer_ls180.v:160066$9624_Y - connect \$3 $not$issuer_ls180.v:160067$9625_Y - connect \$8 $reduce_or$issuer_ls180.v:160068$9626_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:160084.1-160168.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$199 - attribute \src "issuer_ls180.v:160141.17-160141.91" - wire $not$issuer_ls180.v:160141$9627_Y - attribute \src "issuer_ls180.v:160143.18-160143.93" - wire $not$issuer_ls180.v:160143$9629_Y - attribute \src "issuer_ls180.v:160145.18-160145.93" - wire $not$issuer_ls180.v:160145$9631_Y - attribute \src "issuer_ls180.v:160146.17-160146.138" - wire width 8 $not$issuer_ls180.v:160146$9632_Y - attribute \src "issuer_ls180.v:160148.18-160148.93" - wire $not$issuer_ls180.v:160148$9634_Y - attribute \src "issuer_ls180.v:160150.18-160150.93" - wire $not$issuer_ls180.v:160150$9636_Y - attribute \src "issuer_ls180.v:160152.18-160152.93" - wire $not$issuer_ls180.v:160152$9638_Y - attribute \src "issuer_ls180.v:160155.17-160155.91" - wire $not$issuer_ls180.v:160155$9641_Y - attribute \src "issuer_ls180.v:160142.18-160142.116" - wire $reduce_or$issuer_ls180.v:160142$9628_Y - attribute \src "issuer_ls180.v:160144.18-160144.122" - wire $reduce_or$issuer_ls180.v:160144$9630_Y - attribute \src "issuer_ls180.v:160147.18-160147.128" - wire $reduce_or$issuer_ls180.v:160147$9633_Y - attribute \src "issuer_ls180.v:160149.18-160149.134" - wire $reduce_or$issuer_ls180.v:160149$9635_Y - attribute \src "issuer_ls180.v:160151.18-160151.140" - wire $reduce_or$issuer_ls180.v:160151$9637_Y - attribute \src "issuer_ls180.v:160153.18-160153.90" - wire $reduce_or$issuer_ls180.v:160153$9639_Y - attribute \src "issuer_ls180.v:160154.17-160154.103" - wire $reduce_or$issuer_ls180.v:160154$9640_Y - attribute \src "issuer_ls180.v:160156.17-160156.109" - wire $reduce_or$issuer_ls180.v:160156$9642_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160141$9627 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:160141$9627_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160143$9629 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:160143$9629_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160145$9631 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:160145$9631_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:160146$9632 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$issuer_ls180.v:160146$9632_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160148$9634 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$issuer_ls180.v:160148$9634_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160150$9636 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:160150$9636_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160152$9638 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$issuer_ls180.v:160152$9638_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160155$9641 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:160155$9641_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160142$9628 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:160142$9628_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160144$9630 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:160144$9630_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160147$9633 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$issuer_ls180.v:160147$9633_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160149$9635 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$issuer_ls180.v:160149$9635_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160151$9637 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$issuer_ls180.v:160151$9637_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:160153$9639 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:160153$9639_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160154$9640 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:160154$9640_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160156$9642 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:160156$9642_Y - end - connect \$7 $not$issuer_ls180.v:160141$9627_Y - connect \$12 $reduce_or$issuer_ls180.v:160142$9628_Y - connect \$11 $not$issuer_ls180.v:160143$9629_Y - connect \$16 $reduce_or$issuer_ls180.v:160144$9630_Y - connect \$15 $not$issuer_ls180.v:160145$9631_Y - connect \$1 $not$issuer_ls180.v:160146$9632_Y - connect \$20 $reduce_or$issuer_ls180.v:160147$9633_Y - connect \$19 $not$issuer_ls180.v:160148$9634_Y - connect \$24 $reduce_or$issuer_ls180.v:160149$9635_Y - connect \$23 $not$issuer_ls180.v:160150$9636_Y - connect \$28 $reduce_or$issuer_ls180.v:160151$9637_Y - connect \$27 $not$issuer_ls180.v:160152$9638_Y - connect \$31 $reduce_or$issuer_ls180.v:160153$9639_Y - connect \$4 $reduce_or$issuer_ls180.v:160154$9640_Y - connect \$3 $not$issuer_ls180.v:160155$9641_Y - connect \$8 $reduce_or$issuer_ls180.v:160156$9642_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:160172.1-160256.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$206 - attribute \src "issuer_ls180.v:160229.17-160229.91" - wire $not$issuer_ls180.v:160229$9643_Y - attribute \src "issuer_ls180.v:160231.18-160231.93" - wire $not$issuer_ls180.v:160231$9645_Y - attribute \src "issuer_ls180.v:160233.18-160233.93" - wire $not$issuer_ls180.v:160233$9647_Y - attribute \src "issuer_ls180.v:160234.17-160234.138" - wire width 8 $not$issuer_ls180.v:160234$9648_Y - attribute \src "issuer_ls180.v:160236.18-160236.93" - wire $not$issuer_ls180.v:160236$9650_Y - attribute \src "issuer_ls180.v:160238.18-160238.93" - wire $not$issuer_ls180.v:160238$9652_Y - attribute \src "issuer_ls180.v:160240.18-160240.93" - wire $not$issuer_ls180.v:160240$9654_Y - attribute \src "issuer_ls180.v:160243.17-160243.91" - wire $not$issuer_ls180.v:160243$9657_Y - attribute \src "issuer_ls180.v:160230.18-160230.116" - wire $reduce_or$issuer_ls180.v:160230$9644_Y - attribute \src "issuer_ls180.v:160232.18-160232.122" - wire $reduce_or$issuer_ls180.v:160232$9646_Y - attribute \src "issuer_ls180.v:160235.18-160235.128" - wire $reduce_or$issuer_ls180.v:160235$9649_Y - attribute \src "issuer_ls180.v:160237.18-160237.134" - wire $reduce_or$issuer_ls180.v:160237$9651_Y - attribute \src "issuer_ls180.v:160239.18-160239.140" - wire $reduce_or$issuer_ls180.v:160239$9653_Y - attribute \src "issuer_ls180.v:160241.18-160241.90" - wire $reduce_or$issuer_ls180.v:160241$9655_Y - attribute \src "issuer_ls180.v:160242.17-160242.103" - wire $reduce_or$issuer_ls180.v:160242$9656_Y - attribute \src "issuer_ls180.v:160244.17-160244.109" - wire $reduce_or$issuer_ls180.v:160244$9658_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160229$9643 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:160229$9643_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160231$9645 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:160231$9645_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160233$9647 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:160233$9647_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:160234$9648 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$issuer_ls180.v:160234$9648_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160236$9650 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$issuer_ls180.v:160236$9650_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160238$9652 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:160238$9652_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160240$9654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$issuer_ls180.v:160240$9654_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160243$9657 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:160243$9657_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160230$9644 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:160230$9644_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160232$9646 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:160232$9646_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160235$9649 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$issuer_ls180.v:160235$9649_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160237$9651 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$issuer_ls180.v:160237$9651_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160239$9653 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$issuer_ls180.v:160239$9653_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:160241$9655 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:160241$9655_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160242$9656 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:160242$9656_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160244$9658 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:160244$9658_Y - end - connect \$7 $not$issuer_ls180.v:160229$9643_Y - connect \$12 $reduce_or$issuer_ls180.v:160230$9644_Y - connect \$11 $not$issuer_ls180.v:160231$9645_Y - connect \$16 $reduce_or$issuer_ls180.v:160232$9646_Y - connect \$15 $not$issuer_ls180.v:160233$9647_Y - connect \$1 $not$issuer_ls180.v:160234$9648_Y - connect \$20 $reduce_or$issuer_ls180.v:160235$9649_Y - connect \$19 $not$issuer_ls180.v:160236$9650_Y - connect \$24 $reduce_or$issuer_ls180.v:160237$9651_Y - connect \$23 $not$issuer_ls180.v:160238$9652_Y - connect \$28 $reduce_or$issuer_ls180.v:160239$9653_Y - connect \$27 $not$issuer_ls180.v:160240$9654_Y - connect \$31 $reduce_or$issuer_ls180.v:160241$9655_Y - connect \$4 $reduce_or$issuer_ls180.v:160242$9656_Y - connect \$3 $not$issuer_ls180.v:160243$9657_Y - connect \$8 $reduce_or$issuer_ls180.v:160244$9658_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:160260.1-160344.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$208 - attribute \src "issuer_ls180.v:160317.17-160317.91" - wire $not$issuer_ls180.v:160317$9659_Y - attribute \src "issuer_ls180.v:160319.18-160319.93" - wire $not$issuer_ls180.v:160319$9661_Y - attribute \src "issuer_ls180.v:160321.18-160321.93" - wire $not$issuer_ls180.v:160321$9663_Y - attribute \src "issuer_ls180.v:160322.17-160322.138" - wire width 8 $not$issuer_ls180.v:160322$9664_Y - attribute \src "issuer_ls180.v:160324.18-160324.93" - wire $not$issuer_ls180.v:160324$9666_Y - attribute \src "issuer_ls180.v:160326.18-160326.93" - wire $not$issuer_ls180.v:160326$9668_Y - attribute \src "issuer_ls180.v:160328.18-160328.93" - wire $not$issuer_ls180.v:160328$9670_Y - attribute \src "issuer_ls180.v:160331.17-160331.91" - wire $not$issuer_ls180.v:160331$9673_Y - attribute \src "issuer_ls180.v:160318.18-160318.116" - wire $reduce_or$issuer_ls180.v:160318$9660_Y - attribute \src "issuer_ls180.v:160320.18-160320.122" - wire $reduce_or$issuer_ls180.v:160320$9662_Y - attribute \src "issuer_ls180.v:160323.18-160323.128" - wire $reduce_or$issuer_ls180.v:160323$9665_Y - attribute \src "issuer_ls180.v:160325.18-160325.134" - wire $reduce_or$issuer_ls180.v:160325$9667_Y - attribute \src "issuer_ls180.v:160327.18-160327.140" - wire $reduce_or$issuer_ls180.v:160327$9669_Y - attribute \src "issuer_ls180.v:160329.18-160329.90" - wire $reduce_or$issuer_ls180.v:160329$9671_Y - attribute \src "issuer_ls180.v:160330.17-160330.103" - wire $reduce_or$issuer_ls180.v:160330$9672_Y - attribute \src "issuer_ls180.v:160332.17-160332.109" - wire $reduce_or$issuer_ls180.v:160332$9674_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160317$9659 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:160317$9659_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160319$9661 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:160319$9661_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160321$9663 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:160321$9663_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:160322$9664 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$issuer_ls180.v:160322$9664_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160324$9666 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$issuer_ls180.v:160324$9666_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160326$9668 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:160326$9668_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160328$9670 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$issuer_ls180.v:160328$9670_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160331$9673 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:160331$9673_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160318$9660 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:160318$9660_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160320$9662 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:160320$9662_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160323$9665 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$issuer_ls180.v:160323$9665_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160325$9667 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$issuer_ls180.v:160325$9667_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160327$9669 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$issuer_ls180.v:160327$9669_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:160329$9671 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:160329$9671_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160330$9672 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:160330$9672_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160332$9674 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:160332$9674_Y - end - connect \$7 $not$issuer_ls180.v:160317$9659_Y - connect \$12 $reduce_or$issuer_ls180.v:160318$9660_Y - connect \$11 $not$issuer_ls180.v:160319$9661_Y - connect \$16 $reduce_or$issuer_ls180.v:160320$9662_Y - connect \$15 $not$issuer_ls180.v:160321$9663_Y - connect \$1 $not$issuer_ls180.v:160322$9664_Y - connect \$20 $reduce_or$issuer_ls180.v:160323$9665_Y - connect \$19 $not$issuer_ls180.v:160324$9666_Y - connect \$24 $reduce_or$issuer_ls180.v:160325$9667_Y - connect \$23 $not$issuer_ls180.v:160326$9668_Y - connect \$28 $reduce_or$issuer_ls180.v:160327$9669_Y - connect \$27 $not$issuer_ls180.v:160328$9670_Y - connect \$31 $reduce_or$issuer_ls180.v:160329$9671_Y - connect \$4 $reduce_or$issuer_ls180.v:160330$9672_Y - connect \$3 $not$issuer_ls180.v:160331$9673_Y - connect \$8 $reduce_or$issuer_ls180.v:160332$9674_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:160348.1-160378.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_a" -attribute \generator "nMigen" -module \rdpick_CR_cr_a - attribute \src "issuer_ls180.v:160369.17-160369.89" - wire width 2 $not$issuer_ls180.v:160369$9675_Y - attribute \src "issuer_ls180.v:160371.17-160371.91" - wire $not$issuer_ls180.v:160371$9677_Y - attribute \src "issuer_ls180.v:160370.17-160370.103" - wire $reduce_or$issuer_ls180.v:160370$9676_Y - attribute \src "issuer_ls180.v:160372.17-160372.89" - wire $reduce_or$issuer_ls180.v:160372$9678_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 2 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 2 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 2 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 2 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:160369$9675 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \i - connect \Y $not$issuer_ls180.v:160369$9675_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160371$9677 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:160371$9677_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160370$9676 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:160370$9676_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:160372$9678 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:160372$9678_Y - end - connect \$1 $not$issuer_ls180.v:160369$9675_Y - connect \$4 $reduce_or$issuer_ls180.v:160370$9676_Y - connect \$3 $not$issuer_ls180.v:160371$9677_Y - connect \$7 $reduce_or$issuer_ls180.v:160372$9678_Y - connect \en_o \$7 - connect \o { \t1 \t0 } - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:160382.1-160403.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_b" -attribute \generator "nMigen" -module \rdpick_CR_cr_b - attribute \src "issuer_ls180.v:160397.17-160397.89" - wire $not$issuer_ls180.v:160397$9679_Y - attribute \src "issuer_ls180.v:160398.17-160398.89" - wire $reduce_or$issuer_ls180.v:160398$9680_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:160397$9679 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \Y $not$issuer_ls180.v:160397$9679_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:160398$9680 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:160398$9680_Y - end - connect \$1 $not$issuer_ls180.v:160397$9679_Y - connect \$3 $reduce_or$issuer_ls180.v:160398$9680_Y - connect \en_o \$3 - connect \o \t0 - connect \t0 \i - connect \ni \$1 -end -attribute \src "issuer_ls180.v:160407.1-160428.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_c" -attribute \generator "nMigen" -module \rdpick_CR_cr_c - attribute \src "issuer_ls180.v:160422.17-160422.89" - wire $not$issuer_ls180.v:160422$9681_Y - attribute \src "issuer_ls180.v:160423.17-160423.89" - wire $reduce_or$issuer_ls180.v:160423$9682_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:160422$9681 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \Y $not$issuer_ls180.v:160422$9681_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:160423$9682 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:160423$9682_Y - end - connect \$1 $not$issuer_ls180.v:160422$9681_Y - connect \$3 $reduce_or$issuer_ls180.v:160423$9682_Y - connect \en_o \$3 - connect \o \t0 - connect \t0 \i - connect \ni \$1 -end -attribute \src "issuer_ls180.v:160432.1-160453.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_full_cr" -attribute \generator "nMigen" -module \rdpick_CR_full_cr - attribute \src "issuer_ls180.v:160447.17-160447.89" - wire $not$issuer_ls180.v:160447$9683_Y - attribute \src "issuer_ls180.v:160448.17-160448.89" - wire $reduce_or$issuer_ls180.v:160448$9684_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:160447$9683 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \Y $not$issuer_ls180.v:160447$9683_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:160448$9684 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:160448$9684_Y - end - connect \$1 $not$issuer_ls180.v:160447$9683_Y - connect \$3 $reduce_or$issuer_ls180.v:160448$9684_Y - connect \en_o \$3 - connect \o \t0 - connect \t0 \i - connect \ni \$1 -end -attribute \src "issuer_ls180.v:160457.1-160496.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_fast1" -attribute \generator "nMigen" -module \rdpick_FAST_fast1 - attribute \src "issuer_ls180.v:160484.17-160484.91" - wire $not$issuer_ls180.v:160484$9685_Y - attribute \src "issuer_ls180.v:160486.17-160486.89" - wire width 3 $not$issuer_ls180.v:160486$9687_Y - attribute \src "issuer_ls180.v:160488.17-160488.91" - wire $not$issuer_ls180.v:160488$9689_Y - attribute \src "issuer_ls180.v:160485.18-160485.90" - wire $reduce_or$issuer_ls180.v:160485$9686_Y - attribute \src "issuer_ls180.v:160487.17-160487.103" - wire $reduce_or$issuer_ls180.v:160487$9688_Y - attribute \src "issuer_ls180.v:160489.17-160489.105" - wire $reduce_or$issuer_ls180.v:160489$9690_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 3 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 3 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 3 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160484$9685 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:160484$9685_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:160486$9687 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \i - connect \Y $not$issuer_ls180.v:160486$9687_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160488$9689 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:160488$9689_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:160485$9686 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:160485$9686_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160487$9688 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:160487$9688_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160489$9690 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:160489$9690_Y - end - connect \$7 $not$issuer_ls180.v:160484$9685_Y - connect \$11 $reduce_or$issuer_ls180.v:160485$9686_Y - connect \$1 $not$issuer_ls180.v:160486$9687_Y - connect \$4 $reduce_or$issuer_ls180.v:160487$9688_Y - connect \$3 $not$issuer_ls180.v:160488$9689_Y - connect \$8 $reduce_or$issuer_ls180.v:160489$9690_Y - connect \en_o \$11 - connect \o { \t2 \t1 \t0 } - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:160500.1-160530.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_fast2" -attribute \generator "nMigen" -module \rdpick_FAST_fast2 - attribute \src "issuer_ls180.v:160521.17-160521.89" - wire width 2 $not$issuer_ls180.v:160521$9691_Y - attribute \src "issuer_ls180.v:160523.17-160523.91" - wire $not$issuer_ls180.v:160523$9693_Y - attribute \src "issuer_ls180.v:160522.17-160522.103" - wire $reduce_or$issuer_ls180.v:160522$9692_Y - attribute \src "issuer_ls180.v:160524.17-160524.89" - wire $reduce_or$issuer_ls180.v:160524$9694_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 2 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 2 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 2 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 2 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:160521$9691 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \i - connect \Y $not$issuer_ls180.v:160521$9691_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160523$9693 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:160523$9693_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160522$9692 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:160522$9692_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:160524$9694 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:160524$9694_Y - end - connect \$1 $not$issuer_ls180.v:160521$9691_Y - connect \$4 $reduce_or$issuer_ls180.v:160522$9692_Y - connect \$3 $not$issuer_ls180.v:160523$9693_Y - connect \$7 $reduce_or$issuer_ls180.v:160524$9694_Y - connect \en_o \$7 - connect \o { \t1 \t0 } - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:160534.1-160627.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_ra" -attribute \generator "nMigen" -module \rdpick_INT_ra - attribute \src "issuer_ls180.v:160597.17-160597.91" - wire $not$issuer_ls180.v:160597$9695_Y - attribute \src "issuer_ls180.v:160599.18-160599.93" - wire $not$issuer_ls180.v:160599$9697_Y - attribute \src "issuer_ls180.v:160601.18-160601.93" - wire $not$issuer_ls180.v:160601$9699_Y - attribute \src "issuer_ls180.v:160602.17-160602.89" - wire width 9 $not$issuer_ls180.v:160602$9700_Y - attribute \src "issuer_ls180.v:160604.18-160604.93" - wire $not$issuer_ls180.v:160604$9702_Y - attribute \src "issuer_ls180.v:160606.18-160606.93" - wire $not$issuer_ls180.v:160606$9704_Y - attribute \src "issuer_ls180.v:160608.18-160608.93" - wire $not$issuer_ls180.v:160608$9706_Y - attribute \src "issuer_ls180.v:160610.18-160610.93" - wire $not$issuer_ls180.v:160610$9708_Y - attribute \src "issuer_ls180.v:160613.17-160613.91" - wire $not$issuer_ls180.v:160613$9711_Y - attribute \src "issuer_ls180.v:160598.18-160598.106" - wire $reduce_or$issuer_ls180.v:160598$9696_Y - attribute \src "issuer_ls180.v:160600.18-160600.106" - wire $reduce_or$issuer_ls180.v:160600$9698_Y - attribute \src "issuer_ls180.v:160603.18-160603.106" - wire $reduce_or$issuer_ls180.v:160603$9701_Y - attribute \src "issuer_ls180.v:160605.18-160605.106" - wire $reduce_or$issuer_ls180.v:160605$9703_Y - attribute \src "issuer_ls180.v:160607.18-160607.106" - wire $reduce_or$issuer_ls180.v:160607$9705_Y - attribute \src "issuer_ls180.v:160609.18-160609.106" - wire $reduce_or$issuer_ls180.v:160609$9707_Y - attribute \src "issuer_ls180.v:160611.18-160611.90" - wire $reduce_or$issuer_ls180.v:160611$9709_Y - attribute \src "issuer_ls180.v:160612.17-160612.103" - wire $reduce_or$issuer_ls180.v:160612$9710_Y - attribute \src "issuer_ls180.v:160614.17-160614.105" - wire $reduce_or$issuer_ls180.v:160614$9712_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 9 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 9 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 9 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 9 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160597$9695 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:160597$9695_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160599$9697 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:160599$9697_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160601$9699 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:160601$9699_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:160602$9700 - parameter \A_SIGNED 0 - parameter \A_WIDTH 9 - parameter \Y_WIDTH 9 - connect \A \i - connect \Y $not$issuer_ls180.v:160602$9700_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160604$9702 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$issuer_ls180.v:160604$9702_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160606$9704 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:160606$9704_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160608$9706 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$issuer_ls180.v:160608$9706_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160610$9708 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$32 - connect \Y $not$issuer_ls180.v:160610$9708_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160613$9711 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:160613$9711_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160598$9696 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:160598$9696_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160600$9698 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:160600$9698_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160603$9701 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$issuer_ls180.v:160603$9701_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160605$9703 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$issuer_ls180.v:160605$9703_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160607$9705 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$issuer_ls180.v:160607$9705_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160609$9707 - parameter \A_SIGNED 0 - parameter \A_WIDTH 9 - parameter \Y_WIDTH 1 - connect \A { \i [7:0] \ni [8] } - connect \Y $reduce_or$issuer_ls180.v:160609$9707_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:160611$9709 - parameter \A_SIGNED 0 - parameter \A_WIDTH 9 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:160611$9709_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160612$9710 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:160612$9710_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160614$9712 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:160614$9712_Y - end - connect \$7 $not$issuer_ls180.v:160597$9695_Y - connect \$12 $reduce_or$issuer_ls180.v:160598$9696_Y - connect \$11 $not$issuer_ls180.v:160599$9697_Y - connect \$16 $reduce_or$issuer_ls180.v:160600$9698_Y - connect \$15 $not$issuer_ls180.v:160601$9699_Y - connect \$1 $not$issuer_ls180.v:160602$9700_Y - connect \$20 $reduce_or$issuer_ls180.v:160603$9701_Y - connect \$19 $not$issuer_ls180.v:160604$9702_Y - connect \$24 $reduce_or$issuer_ls180.v:160605$9703_Y - connect \$23 $not$issuer_ls180.v:160606$9704_Y - connect \$28 $reduce_or$issuer_ls180.v:160607$9705_Y - connect \$27 $not$issuer_ls180.v:160608$9706_Y - connect \$32 $reduce_or$issuer_ls180.v:160609$9707_Y - connect \$31 $not$issuer_ls180.v:160610$9708_Y - connect \$35 $reduce_or$issuer_ls180.v:160611$9709_Y - connect \$4 $reduce_or$issuer_ls180.v:160612$9710_Y - connect \$3 $not$issuer_ls180.v:160613$9711_Y - connect \$8 $reduce_or$issuer_ls180.v:160614$9712_Y - connect \en_o \$35 - connect \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } - connect \t8 \$31 - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:160631.1-160715.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_rb" -attribute \generator "nMigen" -module \rdpick_INT_rb - attribute \src "issuer_ls180.v:160688.17-160688.91" - wire $not$issuer_ls180.v:160688$9713_Y - attribute \src "issuer_ls180.v:160690.18-160690.93" - wire $not$issuer_ls180.v:160690$9715_Y - attribute \src "issuer_ls180.v:160692.18-160692.93" - wire $not$issuer_ls180.v:160692$9717_Y - attribute \src "issuer_ls180.v:160693.17-160693.89" - wire width 8 $not$issuer_ls180.v:160693$9718_Y - attribute \src "issuer_ls180.v:160695.18-160695.93" - wire $not$issuer_ls180.v:160695$9720_Y - attribute \src "issuer_ls180.v:160697.18-160697.93" - wire $not$issuer_ls180.v:160697$9722_Y - attribute \src "issuer_ls180.v:160699.18-160699.93" - wire $not$issuer_ls180.v:160699$9724_Y - attribute \src "issuer_ls180.v:160702.17-160702.91" - wire $not$issuer_ls180.v:160702$9727_Y - attribute \src "issuer_ls180.v:160689.18-160689.106" - wire $reduce_or$issuer_ls180.v:160689$9714_Y - attribute \src "issuer_ls180.v:160691.18-160691.106" - wire $reduce_or$issuer_ls180.v:160691$9716_Y - attribute \src "issuer_ls180.v:160694.18-160694.106" - wire $reduce_or$issuer_ls180.v:160694$9719_Y - attribute \src "issuer_ls180.v:160696.18-160696.106" - wire $reduce_or$issuer_ls180.v:160696$9721_Y - attribute \src "issuer_ls180.v:160698.18-160698.106" - wire $reduce_or$issuer_ls180.v:160698$9723_Y - attribute \src "issuer_ls180.v:160700.18-160700.90" - wire $reduce_or$issuer_ls180.v:160700$9725_Y - attribute \src "issuer_ls180.v:160701.17-160701.103" - wire $reduce_or$issuer_ls180.v:160701$9726_Y - attribute \src "issuer_ls180.v:160703.17-160703.105" - wire $reduce_or$issuer_ls180.v:160703$9728_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160688$9713 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:160688$9713_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160690$9715 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:160690$9715_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160692$9717 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:160692$9717_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:160693$9718 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A \i - connect \Y $not$issuer_ls180.v:160693$9718_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160695$9720 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$issuer_ls180.v:160695$9720_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160697$9722 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:160697$9722_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160699$9724 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$issuer_ls180.v:160699$9724_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160702$9727 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:160702$9727_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160689$9714 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:160689$9714_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160691$9716 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:160691$9716_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160694$9719 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$issuer_ls180.v:160694$9719_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160696$9721 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$issuer_ls180.v:160696$9721_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160698$9723 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$issuer_ls180.v:160698$9723_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:160700$9725 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:160700$9725_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160701$9726 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:160701$9726_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160703$9728 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:160703$9728_Y - end - connect \$7 $not$issuer_ls180.v:160688$9713_Y - connect \$12 $reduce_or$issuer_ls180.v:160689$9714_Y - connect \$11 $not$issuer_ls180.v:160690$9715_Y - connect \$16 $reduce_or$issuer_ls180.v:160691$9716_Y - connect \$15 $not$issuer_ls180.v:160692$9717_Y - connect \$1 $not$issuer_ls180.v:160693$9718_Y - connect \$20 $reduce_or$issuer_ls180.v:160694$9719_Y - connect \$19 $not$issuer_ls180.v:160695$9720_Y - connect \$24 $reduce_or$issuer_ls180.v:160696$9721_Y - connect \$23 $not$issuer_ls180.v:160697$9722_Y - connect \$28 $reduce_or$issuer_ls180.v:160698$9723_Y - connect \$27 $not$issuer_ls180.v:160699$9724_Y - connect \$31 $reduce_or$issuer_ls180.v:160700$9725_Y - connect \$4 $reduce_or$issuer_ls180.v:160701$9726_Y - connect \$3 $not$issuer_ls180.v:160702$9727_Y - connect \$8 $reduce_or$issuer_ls180.v:160703$9728_Y - connect \en_o \$31 - connect \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:160719.1-160749.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_rc" -attribute \generator "nMigen" -module \rdpick_INT_rc - attribute \src "issuer_ls180.v:160740.17-160740.89" - wire width 2 $not$issuer_ls180.v:160740$9729_Y - attribute \src "issuer_ls180.v:160742.17-160742.91" - wire $not$issuer_ls180.v:160742$9731_Y - attribute \src "issuer_ls180.v:160741.17-160741.103" - wire $reduce_or$issuer_ls180.v:160741$9730_Y - attribute \src "issuer_ls180.v:160743.17-160743.89" - wire $reduce_or$issuer_ls180.v:160743$9732_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 2 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 2 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 2 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 2 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:160740$9729 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \i - connect \Y $not$issuer_ls180.v:160740$9729_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160742$9731 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:160742$9731_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160741$9730 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:160741$9730_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:160743$9732 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:160743$9732_Y - end - connect \$1 $not$issuer_ls180.v:160740$9729_Y - connect \$4 $reduce_or$issuer_ls180.v:160741$9730_Y - connect \$3 $not$issuer_ls180.v:160742$9731_Y - connect \$7 $reduce_or$issuer_ls180.v:160743$9732_Y - connect \en_o \$7 - connect \o { \t1 \t0 } - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:160753.1-160774.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_SPR_spr1" -attribute \generator "nMigen" -module \rdpick_SPR_spr1 - attribute \src "issuer_ls180.v:160768.17-160768.89" - wire $not$issuer_ls180.v:160768$9733_Y - attribute \src "issuer_ls180.v:160769.17-160769.89" - wire $reduce_or$issuer_ls180.v:160769$9734_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:160768$9733 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \Y $not$issuer_ls180.v:160768$9733_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:160769$9734 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:160769$9734_Y - end - connect \$1 $not$issuer_ls180.v:160768$9733_Y - connect \$3 $reduce_or$issuer_ls180.v:160769$9734_Y - connect \en_o \$3 - connect \o \t0 - connect \t0 \i - connect \ni \$1 -end -attribute \src "issuer_ls180.v:160778.1-160817.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_ca" -attribute \generator "nMigen" -module \rdpick_XER_xer_ca - attribute \src "issuer_ls180.v:160805.17-160805.91" - wire $not$issuer_ls180.v:160805$9735_Y - attribute \src "issuer_ls180.v:160807.17-160807.89" - wire width 3 $not$issuer_ls180.v:160807$9737_Y - attribute \src "issuer_ls180.v:160809.17-160809.91" - wire $not$issuer_ls180.v:160809$9739_Y - attribute \src "issuer_ls180.v:160806.18-160806.90" - wire $reduce_or$issuer_ls180.v:160806$9736_Y - attribute \src "issuer_ls180.v:160808.17-160808.103" - wire $reduce_or$issuer_ls180.v:160808$9738_Y - attribute \src "issuer_ls180.v:160810.17-160810.105" - wire $reduce_or$issuer_ls180.v:160810$9740_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 3 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 3 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 3 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160805$9735 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:160805$9735_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:160807$9737 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \i - connect \Y $not$issuer_ls180.v:160807$9737_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:160809$9739 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:160809$9739_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:160806$9736 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:160806$9736_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160808$9738 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:160808$9738_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:160810$9740 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:160810$9740_Y - end - connect \$7 $not$issuer_ls180.v:160805$9735_Y - connect \$11 $reduce_or$issuer_ls180.v:160806$9736_Y - connect \$1 $not$issuer_ls180.v:160807$9737_Y - connect \$4 $reduce_or$issuer_ls180.v:160808$9738_Y - connect \$3 $not$issuer_ls180.v:160809$9739_Y - connect \$8 $reduce_or$issuer_ls180.v:160810$9740_Y - connect \en_o \$11 - connect \o { \t2 \t1 \t0 } - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:160821.1-160842.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_ov" -attribute \generator "nMigen" -module \rdpick_XER_xer_ov - attribute \src "issuer_ls180.v:160836.17-160836.89" - wire $not$issuer_ls180.v:160836$9741_Y - attribute \src "issuer_ls180.v:160837.17-160837.89" - wire $reduce_or$issuer_ls180.v:160837$9742_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:160836$9741 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \Y $not$issuer_ls180.v:160836$9741_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:160837$9742 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:160837$9742_Y - end - connect \$1 $not$issuer_ls180.v:160836$9741_Y - connect \$3 $reduce_or$issuer_ls180.v:160837$9742_Y - connect \en_o \$3 - connect \o \t0 - connect \t0 \i - connect \ni \$1 -end -attribute \src "issuer_ls180.v:160846.1-160912.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_so" -attribute \generator "nMigen" -module \rdpick_XER_xer_so - attribute \src "issuer_ls180.v:160891.17-160891.91" - wire $not$issuer_ls180.v:160891$9743_Y - attribute \src "issuer_ls180.v:160893.18-160893.93" - wire $not$issuer_ls180.v:160893$9745_Y - attribute \src "issuer_ls180.v:160895.18-160895.93" - wire $not$issuer_ls180.v:160895$9747_Y - attribute \src "issuer_ls180.v:160896.17-160896.89" - wire width 6 $not$issuer_ls180.v:160896$9748_Y - attribute \src "issuer_ls180.v:160898.18-160898.93" - wire $not$issuer_ls180.v:160898$9750_Y - attribute \src "issuer_ls180.v:160901.17-160901.91" - wire $not$issuer_ls180.v:160901$9753_Y - attribute \src "issuer_ls180.v:160892.18-160892.106" - wire $reduce_or$issuer_ls180.v:160892$9744_Y - attribute \src "issuer_ls180.v:160894.18-160894.106" - wire $reduce_or$issuer_ls180.v:160894$9746_Y - attribute \src "issuer_ls180.v:160897.18-160897.106" - wire $reduce_or$issuer_ls180.v:160897$9749_Y - attribute \src "issuer_ls180.v:160899.18-160899.90" - wire $reduce_or$issuer_ls180.v:160899$9751_Y - attribute \src "issuer_ls180.v:160900.17-160900.103" - wire $reduce_or$issuer_ls180.v:160900$9752_Y - attribute \src "issuer_ls180.v:160902.17-160902.105" - wire $reduce_or$issuer_ls180.v:160902$9754_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 6 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 6 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 6 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 6 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src30__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src30__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \src30__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 16 \w0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 17 \w0__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:160993$9755 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $not$issuer_ls180.v:160993$9755_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:160994$9756 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$13 - connect \Y $not$issuer_ls180.v:160994$9756_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:160995$9757 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$issuer_ls180.v:160995$9757_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:160996$9758 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$issuer_ls180.v:160996$9758_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:160997$9759 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $not$issuer_ls180.v:160997$9759_Y - end - attribute \src "issuer_ls180.v:160917.7-160917.20" - process $proc$issuer_ls180.v:160917$9837 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:160942.13-160942.30" - process $proc$issuer_ls180.v:160942$9838 - assign { } { } - assign $1\r0__data_o[3:0] 4'0000 - sync always - sync init - update \r0__data_o $1\r0__data_o[3:0] - end - attribute \src "issuer_ls180.v:160949.13-160949.31" - process $proc$issuer_ls180.v:160949$9839 - assign { } { } - assign $1\r20__data_o[3:0] 4'0000 - sync always - sync init - update \r20__data_o $1\r20__data_o[3:0] - end - attribute \src "issuer_ls180.v:160955.13-160955.25" - process $proc$issuer_ls180.v:160955$9840 - assign { } { } - assign $1\reg[3:0] 4'0000 - sync always - sync init - update \reg $1\reg[3:0] - end - attribute \src "issuer_ls180.v:160960.13-160960.33" - process $proc$issuer_ls180.v:160960$9841 - assign { } { } - assign $1\src10__data_o[3:0] 4'0000 - sync always - sync init - update \src10__data_o $1\src10__data_o[3:0] - end - attribute \src "issuer_ls180.v:160967.13-160967.33" - process $proc$issuer_ls180.v:160967$9842 - assign { } { } - assign $1\src20__data_o[3:0] 4'0000 - sync always - sync init - update \src20__data_o $1\src20__data_o[3:0] - end - attribute \src "issuer_ls180.v:160974.13-160974.33" - process $proc$issuer_ls180.v:160974$9843 - assign { } { } - assign $1\src30__data_o[3:0] 4'0000 - sync always - sync init - update \src30__data_o $1\src30__data_o[3:0] - end - attribute \src "issuer_ls180.v:160998.3-160999.25" - process $proc$issuer_ls180.v:160998$9760 - assign { } { } - assign $0\reg[3:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[3:0] - end - attribute \src "issuer_ls180.v:161000.3-161001.39" - process $proc$issuer_ls180.v:161000$9761 - assign { } { } - assign $0\r20__data_o[3:0] \r20__data_o$next - sync posedge \coresync_clk - update \r20__data_o $0\r20__data_o[3:0] - end - attribute \src "issuer_ls180.v:161002.3-161003.37" - process $proc$issuer_ls180.v:161002$9762 - assign { } { } - assign $0\r0__data_o[3:0] \r0__data_o$next - sync posedge \coresync_clk - update \r0__data_o $0\r0__data_o[3:0] - end - attribute \src "issuer_ls180.v:161004.3-161005.43" - process $proc$issuer_ls180.v:161004$9763 - assign { } { } - assign $0\src30__data_o[3:0] \src30__data_o$next - sync posedge \coresync_clk - update \src30__data_o $0\src30__data_o[3:0] - end - attribute \src "issuer_ls180.v:161006.3-161007.43" - process $proc$issuer_ls180.v:161006$9764 - assign { } { } - assign $0\src20__data_o[3:0] \src20__data_o$next - sync posedge \coresync_clk - update \src20__data_o $0\src20__data_o[3:0] - end - attribute \src "issuer_ls180.v:161008.3-161009.43" - process $proc$issuer_ls180.v:161008$9765 - assign { } { } - assign $0\src10__data_o[3:0] \src10__data_o$next - sync posedge \coresync_clk - update \src10__data_o $0\src10__data_o[3:0] - end - attribute \src "issuer_ls180.v:161010.3-161049.6" - process $proc$issuer_ls180.v:161010$9766 - assign { } { } - assign { } { } - assign { } { } - assign $0\src10__data_o$next[3:0]$9767 $6\src10__data_o$next[3:0]$9773 - attribute \src "issuer_ls180.v:161011.5-161011.29" - switch \initial - attribute \src "issuer_ls180.v:161011.9-161011.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src10__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src10__data_o$next[3:0]$9768 $5\src10__data_o$next[3:0]$9772 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src10__data_o$next[3:0]$9769 \dest10__data_i - case - assign $2\src10__data_o$next[3:0]$9769 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src10__data_o$next[3:0]$9770 \dest20__data_i - case - assign $3\src10__data_o$next[3:0]$9770 $2\src10__data_o$next[3:0]$9769 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src10__data_o$next[3:0]$9771 \w0__data_i - case - assign $4\src10__data_o$next[3:0]$9771 $3\src10__data_o$next[3:0]$9770 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src10__data_o$next[3:0]$9772 \reg - case - assign $5\src10__data_o$next[3:0]$9772 $4\src10__data_o$next[3:0]$9771 - end - case - assign $1\src10__data_o$next[3:0]$9768 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src10__data_o$next[3:0]$9773 4'0000 - case - assign $6\src10__data_o$next[3:0]$9773 $1\src10__data_o$next[3:0]$9768 - end - sync always - update \src10__data_o$next $0\src10__data_o$next[3:0]$9767 - end - attribute \src "issuer_ls180.v:161050.3-161079.6" - process $proc$issuer_ls180.v:161050$9774 - assign { } { } - assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:161051.5-161051.29" - switch \initial - attribute \src "issuer_ls180.v:161051.9-161051.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src10__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end - case - assign $1\wr_detect[0:0] 1'0 - end - sync always - update \wr_detect $0\wr_detect[0:0] - end - attribute \src "issuer_ls180.v:161080.3-161106.6" - process $proc$issuer_ls180.v:161080$9775 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[3:0]$9776 $4\reg$next[3:0]$9780 - attribute \src "issuer_ls180.v:161081.5-161081.29" - switch \initial - attribute \src "issuer_ls180.v:161081.9-161081.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg$next[3:0]$9777 \dest10__data_i - case - assign $1\reg$next[3:0]$9777 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest20__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reg$next[3:0]$9778 \dest20__data_i - case - assign $2\reg$next[3:0]$9778 $1\reg$next[3:0]$9777 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\reg$next[3:0]$9779 \w0__data_i - case - assign $3\reg$next[3:0]$9779 $2\reg$next[3:0]$9778 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\reg$next[3:0]$9780 4'0000 - case - assign $4\reg$next[3:0]$9780 $3\reg$next[3:0]$9779 - end - sync always - update \reg$next $0\reg$next[3:0]$9776 - end - attribute \src "issuer_ls180.v:161107.3-161146.6" - process $proc$issuer_ls180.v:161107$9781 - assign { } { } - assign { } { } - assign { } { } - assign $0\src20__data_o$next[3:0]$9782 $6\src20__data_o$next[3:0]$9788 - attribute \src "issuer_ls180.v:161108.5-161108.29" - switch \initial - attribute \src "issuer_ls180.v:161108.9-161108.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src20__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src20__data_o$next[3:0]$9783 $5\src20__data_o$next[3:0]$9787 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src20__data_o$next[3:0]$9784 \dest10__data_i - case - assign $2\src20__data_o$next[3:0]$9784 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src20__data_o$next[3:0]$9785 \dest20__data_i - case - assign $3\src20__data_o$next[3:0]$9785 $2\src20__data_o$next[3:0]$9784 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src20__data_o$next[3:0]$9786 \w0__data_i - case - assign $4\src20__data_o$next[3:0]$9786 $3\src20__data_o$next[3:0]$9785 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src20__data_o$next[3:0]$9787 \reg - case - assign $5\src20__data_o$next[3:0]$9787 $4\src20__data_o$next[3:0]$9786 - end - case - assign $1\src20__data_o$next[3:0]$9783 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src20__data_o$next[3:0]$9788 4'0000 - case - assign $6\src20__data_o$next[3:0]$9788 $1\src20__data_o$next[3:0]$9783 - end - sync always - update \src20__data_o$next $0\src20__data_o$next[3:0]$9782 - end - attribute \src "issuer_ls180.v:161147.3-161176.6" - process $proc$issuer_ls180.v:161147$9789 - assign { } { } - assign { } { } - assign $0\wr_detect$4[0:0]$9790 $1\wr_detect$4[0:0]$9791 - attribute \src "issuer_ls180.v:161148.5-161148.29" - switch \initial - attribute \src "issuer_ls180.v:161148.9-161148.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src20__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$4[0:0]$9791 $4\wr_detect$4[0:0]$9794 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$9792 1'1 - case - assign $2\wr_detect$4[0:0]$9792 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$9793 1'1 - case - assign $3\wr_detect$4[0:0]$9793 $2\wr_detect$4[0:0]$9792 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$9794 1'1 - case - assign $4\wr_detect$4[0:0]$9794 $3\wr_detect$4[0:0]$9793 - end - case - assign $1\wr_detect$4[0:0]$9791 1'0 - end - sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$9790 - end - attribute \src "issuer_ls180.v:161177.3-161216.6" - process $proc$issuer_ls180.v:161177$9795 - assign { } { } - assign { } { } - assign { } { } - assign $0\src30__data_o$next[3:0]$9796 $6\src30__data_o$next[3:0]$9802 - attribute \src "issuer_ls180.v:161178.5-161178.29" - switch \initial - attribute \src "issuer_ls180.v:161178.9-161178.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src30__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src30__data_o$next[3:0]$9797 $5\src30__data_o$next[3:0]$9801 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src30__data_o$next[3:0]$9798 \dest10__data_i - case - assign $2\src30__data_o$next[3:0]$9798 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src30__data_o$next[3:0]$9799 \dest20__data_i - case - assign $3\src30__data_o$next[3:0]$9799 $2\src30__data_o$next[3:0]$9798 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src30__data_o$next[3:0]$9800 \w0__data_i - case - assign $4\src30__data_o$next[3:0]$9800 $3\src30__data_o$next[3:0]$9799 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$6 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src30__data_o$next[3:0]$9801 \reg - case - assign $5\src30__data_o$next[3:0]$9801 $4\src30__data_o$next[3:0]$9800 - end - case - assign $1\src30__data_o$next[3:0]$9797 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src30__data_o$next[3:0]$9802 4'0000 - case - assign $6\src30__data_o$next[3:0]$9802 $1\src30__data_o$next[3:0]$9797 - end - sync always - update \src30__data_o$next $0\src30__data_o$next[3:0]$9796 - end - attribute \src "issuer_ls180.v:161217.3-161246.6" - process $proc$issuer_ls180.v:161217$9803 - assign { } { } - assign { } { } - assign $0\wr_detect$7[0:0]$9804 $1\wr_detect$7[0:0]$9805 - attribute \src "issuer_ls180.v:161218.5-161218.29" - switch \initial - attribute \src "issuer_ls180.v:161218.9-161218.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src30__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$7[0:0]$9805 $4\wr_detect$7[0:0]$9808 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$7[0:0]$9806 1'1 - case - assign $2\wr_detect$7[0:0]$9806 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$7[0:0]$9807 1'1 - case - assign $3\wr_detect$7[0:0]$9807 $2\wr_detect$7[0:0]$9806 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$7[0:0]$9808 1'1 - case - assign $4\wr_detect$7[0:0]$9808 $3\wr_detect$7[0:0]$9807 - end - case - assign $1\wr_detect$7[0:0]$9805 1'0 - end - sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$9804 - end - attribute \src "issuer_ls180.v:161247.3-161286.6" - process $proc$issuer_ls180.v:161247$9809 - assign { } { } - assign { } { } - assign { } { } - assign $0\r0__data_o$next[3:0]$9810 $6\r0__data_o$next[3:0]$9816 - attribute \src "issuer_ls180.v:161248.5-161248.29" - switch \initial - attribute \src "issuer_ls180.v:161248.9-161248.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r0__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r0__data_o$next[3:0]$9811 $5\r0__data_o$next[3:0]$9815 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r0__data_o$next[3:0]$9812 \dest10__data_i - case - assign $2\r0__data_o$next[3:0]$9812 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r0__data_o$next[3:0]$9813 \dest20__data_i - case - assign $3\r0__data_o$next[3:0]$9813 $2\r0__data_o$next[3:0]$9812 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r0__data_o$next[3:0]$9814 \w0__data_i - case - assign $4\r0__data_o$next[3:0]$9814 $3\r0__data_o$next[3:0]$9813 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r0__data_o$next[3:0]$9815 \reg - case - assign $5\r0__data_o$next[3:0]$9815 $4\r0__data_o$next[3:0]$9814 - end - case - assign $1\r0__data_o$next[3:0]$9811 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r0__data_o$next[3:0]$9816 4'0000 - case - assign $6\r0__data_o$next[3:0]$9816 $1\r0__data_o$next[3:0]$9811 - end - sync always - update \r0__data_o$next $0\r0__data_o$next[3:0]$9810 - end - attribute \src "issuer_ls180.v:161287.3-161316.6" - process $proc$issuer_ls180.v:161287$9817 - assign { } { } - assign { } { } - assign $0\wr_detect$10[0:0]$9818 $1\wr_detect$10[0:0]$9819 - attribute \src "issuer_ls180.v:161288.5-161288.29" - switch \initial - attribute \src "issuer_ls180.v:161288.9-161288.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r0__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$10[0:0]$9819 $4\wr_detect$10[0:0]$9822 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$10[0:0]$9820 1'1 - case - assign $2\wr_detect$10[0:0]$9820 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$10[0:0]$9821 1'1 - case - assign $3\wr_detect$10[0:0]$9821 $2\wr_detect$10[0:0]$9820 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$10[0:0]$9822 1'1 - case - assign $4\wr_detect$10[0:0]$9822 $3\wr_detect$10[0:0]$9821 - end - case - assign $1\wr_detect$10[0:0]$9819 1'0 - end - sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$9818 - end - attribute \src "issuer_ls180.v:161317.3-161356.6" - process $proc$issuer_ls180.v:161317$9823 - assign { } { } - assign { } { } - assign { } { } - assign $0\r20__data_o$next[3:0]$9824 $6\r20__data_o$next[3:0]$9830 - attribute \src "issuer_ls180.v:161318.5-161318.29" - switch \initial - attribute \src "issuer_ls180.v:161318.9-161318.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r20__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r20__data_o$next[3:0]$9825 $5\r20__data_o$next[3:0]$9829 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r20__data_o$next[3:0]$9826 \dest10__data_i - case - assign $2\r20__data_o$next[3:0]$9826 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r20__data_o$next[3:0]$9827 \dest20__data_i - case - assign $3\r20__data_o$next[3:0]$9827 $2\r20__data_o$next[3:0]$9826 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r20__data_o$next[3:0]$9828 \w0__data_i - case - assign $4\r20__data_o$next[3:0]$9828 $3\r20__data_o$next[3:0]$9827 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$12 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r20__data_o$next[3:0]$9829 \reg - case - assign $5\r20__data_o$next[3:0]$9829 $4\r20__data_o$next[3:0]$9828 - end - case - assign $1\r20__data_o$next[3:0]$9825 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r20__data_o$next[3:0]$9830 4'0000 - case - assign $6\r20__data_o$next[3:0]$9830 $1\r20__data_o$next[3:0]$9825 - end - sync always - update \r20__data_o$next $0\r20__data_o$next[3:0]$9824 - end - attribute \src "issuer_ls180.v:161357.3-161386.6" - process $proc$issuer_ls180.v:161357$9831 - assign { } { } - assign { } { } - assign $0\wr_detect$13[0:0]$9832 $1\wr_detect$13[0:0]$9833 - attribute \src "issuer_ls180.v:161358.5-161358.29" - switch \initial - attribute \src "issuer_ls180.v:161358.9-161358.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r20__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$13[0:0]$9833 $4\wr_detect$13[0:0]$9836 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$13[0:0]$9834 1'1 - case - assign $2\wr_detect$13[0:0]$9834 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$13[0:0]$9835 1'1 - case - assign $3\wr_detect$13[0:0]$9835 $2\wr_detect$13[0:0]$9834 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$13[0:0]$9836 1'1 - case - assign $4\wr_detect$13[0:0]$9836 $3\wr_detect$13[0:0]$9835 - end - case - assign $1\wr_detect$13[0:0]$9833 1'0 - end - sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$9832 - end - connect \$9 $not$issuer_ls180.v:160993$9755_Y - connect \$12 $not$issuer_ls180.v:160994$9756_Y - connect \$1 $not$issuer_ls180.v:160995$9757_Y - connect \$3 $not$issuer_ls180.v:160996$9758_Y - connect \$6 $not$issuer_ls180.v:160997$9759_Y -end -attribute \src "issuer_ls180.v:161391.1-161836.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.xer.reg_0" -attribute \generator "nMigen" -module \reg_0$129 - attribute \src "issuer_ls180.v:161392.7-161392.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:161721.3-161766.6" - wire width 2 $0\r0__data_o$next[1:0]$9896 - attribute \src "issuer_ls180.v:161467.3-161468.37" - wire width 2 $0\r0__data_o[1:0] - attribute \src "issuer_ls180.v:161803.3-161835.6" - wire width 2 $0\reg$next[1:0]$9912 - attribute \src "issuer_ls180.v:161465.3-161466.25" - wire width 2 $0\reg[1:0] - attribute \src "issuer_ls180.v:161475.3-161520.6" - wire width 2 $0\src10__data_o$next[1:0]$9854 - attribute \src "issuer_ls180.v:161473.3-161474.43" - wire width 2 $0\src10__data_o[1:0] - attribute \src "issuer_ls180.v:161557.3-161602.6" - wire width 2 $0\src20__data_o$next[1:0]$9864 - attribute \src "issuer_ls180.v:161471.3-161472.43" - wire width 2 $0\src20__data_o[1:0] - attribute \src "issuer_ls180.v:161639.3-161684.6" - wire width 2 $0\src30__data_o$next[1:0]$9880 - attribute \src "issuer_ls180.v:161469.3-161470.43" - wire width 2 $0\src30__data_o[1:0] - attribute \src "issuer_ls180.v:161767.3-161802.6" - wire $0\wr_detect$10[0:0]$9905 - attribute \src "issuer_ls180.v:161603.3-161638.6" - wire $0\wr_detect$4[0:0]$9873 - attribute \src "issuer_ls180.v:161685.3-161720.6" - wire $0\wr_detect$7[0:0]$9889 - attribute \src "issuer_ls180.v:161521.3-161556.6" - wire $0\wr_detect[0:0] - attribute \src "issuer_ls180.v:161721.3-161766.6" - wire width 2 $1\r0__data_o$next[1:0]$9897 - attribute \src "issuer_ls180.v:161419.13-161419.30" - wire width 2 $1\r0__data_o[1:0] - attribute \src "issuer_ls180.v:161803.3-161835.6" - wire width 2 $1\reg$next[1:0]$9913 - attribute \src "issuer_ls180.v:161425.13-161425.25" - wire width 2 $1\reg[1:0] - attribute \src "issuer_ls180.v:161475.3-161520.6" - wire width 2 $1\src10__data_o$next[1:0]$9855 - attribute \src "issuer_ls180.v:161430.13-161430.33" - wire width 2 $1\src10__data_o[1:0] - attribute \src "issuer_ls180.v:161557.3-161602.6" - wire width 2 $1\src20__data_o$next[1:0]$9865 - attribute \src "issuer_ls180.v:161437.13-161437.33" - wire width 2 $1\src20__data_o[1:0] - attribute \src "issuer_ls180.v:161639.3-161684.6" - wire width 2 $1\src30__data_o$next[1:0]$9881 - attribute \src "issuer_ls180.v:161444.13-161444.33" - wire width 2 $1\src30__data_o[1:0] - attribute \src "issuer_ls180.v:161767.3-161802.6" - wire $1\wr_detect$10[0:0]$9906 - attribute \src "issuer_ls180.v:161603.3-161638.6" - wire $1\wr_detect$4[0:0]$9874 - attribute \src "issuer_ls180.v:161685.3-161720.6" - wire $1\wr_detect$7[0:0]$9890 - attribute \src "issuer_ls180.v:161521.3-161556.6" - wire $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:161721.3-161766.6" - wire width 2 $2\r0__data_o$next[1:0]$9898 - attribute \src "issuer_ls180.v:161803.3-161835.6" - wire width 2 $2\reg$next[1:0]$9914 - attribute \src "issuer_ls180.v:161475.3-161520.6" - wire width 2 $2\src10__data_o$next[1:0]$9856 - attribute \src "issuer_ls180.v:161557.3-161602.6" - wire width 2 $2\src20__data_o$next[1:0]$9866 - attribute \src "issuer_ls180.v:161639.3-161684.6" - wire width 2 $2\src30__data_o$next[1:0]$9882 - attribute \src "issuer_ls180.v:161767.3-161802.6" - wire $2\wr_detect$10[0:0]$9907 - attribute \src "issuer_ls180.v:161603.3-161638.6" - wire $2\wr_detect$4[0:0]$9875 - attribute \src "issuer_ls180.v:161685.3-161720.6" - wire $2\wr_detect$7[0:0]$9891 - attribute \src "issuer_ls180.v:161521.3-161556.6" - wire $2\wr_detect[0:0] - attribute \src "issuer_ls180.v:161721.3-161766.6" - wire width 2 $3\r0__data_o$next[1:0]$9899 - attribute \src "issuer_ls180.v:161803.3-161835.6" - wire width 2 $3\reg$next[1:0]$9915 - attribute \src "issuer_ls180.v:161475.3-161520.6" - wire width 2 $3\src10__data_o$next[1:0]$9857 - attribute \src "issuer_ls180.v:161557.3-161602.6" - wire width 2 $3\src20__data_o$next[1:0]$9867 - attribute \src "issuer_ls180.v:161639.3-161684.6" - wire width 2 $3\src30__data_o$next[1:0]$9883 - attribute \src "issuer_ls180.v:161767.3-161802.6" - wire $3\wr_detect$10[0:0]$9908 - attribute \src "issuer_ls180.v:161603.3-161638.6" - wire $3\wr_detect$4[0:0]$9876 - attribute \src "issuer_ls180.v:161685.3-161720.6" - wire $3\wr_detect$7[0:0]$9892 - attribute \src "issuer_ls180.v:161521.3-161556.6" - wire $3\wr_detect[0:0] - attribute \src "issuer_ls180.v:161721.3-161766.6" - wire width 2 $4\r0__data_o$next[1:0]$9900 - attribute \src "issuer_ls180.v:161803.3-161835.6" - wire width 2 $4\reg$next[1:0]$9916 - attribute \src "issuer_ls180.v:161475.3-161520.6" - wire width 2 $4\src10__data_o$next[1:0]$9858 - attribute \src "issuer_ls180.v:161557.3-161602.6" - wire width 2 $4\src20__data_o$next[1:0]$9868 - attribute \src "issuer_ls180.v:161639.3-161684.6" - wire width 2 $4\src30__data_o$next[1:0]$9884 - attribute \src "issuer_ls180.v:161767.3-161802.6" - wire $4\wr_detect$10[0:0]$9909 - attribute \src "issuer_ls180.v:161603.3-161638.6" - wire $4\wr_detect$4[0:0]$9877 - attribute \src "issuer_ls180.v:161685.3-161720.6" - wire $4\wr_detect$7[0:0]$9893 - attribute \src "issuer_ls180.v:161521.3-161556.6" - wire $4\wr_detect[0:0] - attribute \src "issuer_ls180.v:161721.3-161766.6" - wire width 2 $5\r0__data_o$next[1:0]$9901 - attribute \src "issuer_ls180.v:161803.3-161835.6" - wire width 2 $5\reg$next[1:0]$9917 - attribute \src "issuer_ls180.v:161475.3-161520.6" - wire width 2 $5\src10__data_o$next[1:0]$9859 - attribute \src "issuer_ls180.v:161557.3-161602.6" - wire width 2 $5\src20__data_o$next[1:0]$9869 - attribute \src "issuer_ls180.v:161639.3-161684.6" - wire width 2 $5\src30__data_o$next[1:0]$9885 - attribute \src "issuer_ls180.v:161767.3-161802.6" - wire $5\wr_detect$10[0:0]$9910 - attribute \src "issuer_ls180.v:161603.3-161638.6" - wire $5\wr_detect$4[0:0]$9878 - attribute \src "issuer_ls180.v:161685.3-161720.6" - wire $5\wr_detect$7[0:0]$9894 - attribute \src "issuer_ls180.v:161521.3-161556.6" - wire $5\wr_detect[0:0] - attribute \src "issuer_ls180.v:161721.3-161766.6" - wire width 2 $6\r0__data_o$next[1:0]$9902 - attribute \src "issuer_ls180.v:161475.3-161520.6" - wire width 2 $6\src10__data_o$next[1:0]$9860 - attribute \src "issuer_ls180.v:161557.3-161602.6" - wire width 2 $6\src20__data_o$next[1:0]$9870 - attribute \src "issuer_ls180.v:161639.3-161684.6" - wire width 2 $6\src30__data_o$next[1:0]$9886 - attribute \src "issuer_ls180.v:161721.3-161766.6" - wire width 2 $7\r0__data_o$next[1:0]$9903 - attribute \src "issuer_ls180.v:161475.3-161520.6" - wire width 2 $7\src10__data_o$next[1:0]$9861 - attribute \src "issuer_ls180.v:161557.3-161602.6" - wire width 2 $7\src20__data_o$next[1:0]$9871 - attribute \src "issuer_ls180.v:161639.3-161684.6" - wire width 2 $7\src30__data_o$next[1:0]$9887 - attribute \src "issuer_ls180.v:161461.17-161461.104" - wire $not$issuer_ls180.v:161461$9844_Y - attribute \src "issuer_ls180.v:161462.17-161462.100" - wire $not$issuer_ls180.v:161462$9845_Y - attribute \src "issuer_ls180.v:161463.17-161463.103" - wire $not$issuer_ls180.v:161463$9846_Y - attribute \src "issuer_ls180.v:161464.17-161464.103" - wire $not$issuer_ls180.v:161464$9847_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 9 \dest10__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \dest10__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 11 \dest20__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \dest20__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 13 \dest30__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 12 \dest30__wen - attribute \src "issuer_ls180.v:161392.7-161392.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 14 \r0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \r0__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \r0__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 2 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 2 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 3 \src10__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src10__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \src10__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 5 \src20__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src20__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \src20__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 7 \src30__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src30__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \src30__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 16 \w0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 17 \w0__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:161461$9844 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $not$issuer_ls180.v:161461$9844_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:161462$9845 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$issuer_ls180.v:161462$9845_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:161463$9846 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$issuer_ls180.v:161463$9846_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:161464$9847 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $not$issuer_ls180.v:161464$9847_Y - end - attribute \src "issuer_ls180.v:161392.7-161392.20" - process $proc$issuer_ls180.v:161392$9918 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:161419.13-161419.30" - process $proc$issuer_ls180.v:161419$9919 - assign { } { } - assign $1\r0__data_o[1:0] 2'00 - sync always - sync init - update \r0__data_o $1\r0__data_o[1:0] - end - attribute \src "issuer_ls180.v:161425.13-161425.25" - process $proc$issuer_ls180.v:161425$9920 - assign { } { } - assign $1\reg[1:0] 2'00 - sync always - sync init - update \reg $1\reg[1:0] - end - attribute \src "issuer_ls180.v:161430.13-161430.33" - process $proc$issuer_ls180.v:161430$9921 - assign { } { } - assign $1\src10__data_o[1:0] 2'00 - sync always - sync init - update \src10__data_o $1\src10__data_o[1:0] - end - attribute \src "issuer_ls180.v:161437.13-161437.33" - process $proc$issuer_ls180.v:161437$9922 - assign { } { } - assign $1\src20__data_o[1:0] 2'00 - sync always - sync init - update \src20__data_o $1\src20__data_o[1:0] - end - attribute \src "issuer_ls180.v:161444.13-161444.33" - process $proc$issuer_ls180.v:161444$9923 - assign { } { } - assign $1\src30__data_o[1:0] 2'00 - sync always - sync init - update \src30__data_o $1\src30__data_o[1:0] - end - attribute \src "issuer_ls180.v:161465.3-161466.25" - process $proc$issuer_ls180.v:161465$9848 - assign { } { } - assign $0\reg[1:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[1:0] - end - attribute \src "issuer_ls180.v:161467.3-161468.37" - process $proc$issuer_ls180.v:161467$9849 - assign { } { } - assign $0\r0__data_o[1:0] \r0__data_o$next - sync posedge \coresync_clk - update \r0__data_o $0\r0__data_o[1:0] - end - attribute \src "issuer_ls180.v:161469.3-161470.43" - process $proc$issuer_ls180.v:161469$9850 - assign { } { } - assign $0\src30__data_o[1:0] \src30__data_o$next - sync posedge \coresync_clk - update \src30__data_o $0\src30__data_o[1:0] - end - attribute \src "issuer_ls180.v:161471.3-161472.43" - process $proc$issuer_ls180.v:161471$9851 - assign { } { } - assign $0\src20__data_o[1:0] \src20__data_o$next - sync posedge \coresync_clk - update \src20__data_o $0\src20__data_o[1:0] - end - attribute \src "issuer_ls180.v:161473.3-161474.43" - process $proc$issuer_ls180.v:161473$9852 - assign { } { } - assign $0\src10__data_o[1:0] \src10__data_o$next - sync posedge \coresync_clk - update \src10__data_o $0\src10__data_o[1:0] - end - attribute \src "issuer_ls180.v:161475.3-161520.6" - process $proc$issuer_ls180.v:161475$9853 - assign { } { } - assign { } { } - assign { } { } - assign $0\src10__data_o$next[1:0]$9854 $7\src10__data_o$next[1:0]$9861 - attribute \src "issuer_ls180.v:161476.5-161476.29" - switch \initial - attribute \src "issuer_ls180.v:161476.9-161476.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src10__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src10__data_o$next[1:0]$9855 $6\src10__data_o$next[1:0]$9860 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src10__data_o$next[1:0]$9856 \dest10__data_i - case - assign $2\src10__data_o$next[1:0]$9856 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src10__data_o$next[1:0]$9857 \dest20__data_i - case - assign $3\src10__data_o$next[1:0]$9857 $2\src10__data_o$next[1:0]$9856 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest30__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src10__data_o$next[1:0]$9858 \dest30__data_i - case - assign $4\src10__data_o$next[1:0]$9858 $3\src10__data_o$next[1:0]$9857 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src10__data_o$next[1:0]$9859 \w0__data_i - case - assign $5\src10__data_o$next[1:0]$9859 $4\src10__data_o$next[1:0]$9858 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src10__data_o$next[1:0]$9860 \reg - case - assign $6\src10__data_o$next[1:0]$9860 $5\src10__data_o$next[1:0]$9859 - end - case - assign $1\src10__data_o$next[1:0]$9855 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\src10__data_o$next[1:0]$9861 2'00 - case - assign $7\src10__data_o$next[1:0]$9861 $1\src10__data_o$next[1:0]$9855 - end - sync always - update \src10__data_o$next $0\src10__data_o$next[1:0]$9854 - end - attribute \src "issuer_ls180.v:161521.3-161556.6" - process $proc$issuer_ls180.v:161521$9862 - assign { } { } - assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:161522.5-161522.29" - switch \initial - attribute \src "issuer_ls180.v:161522.9-161522.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src10__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect[0:0] $5\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest30__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\wr_detect[0:0] 1'1 - case - assign $5\wr_detect[0:0] $4\wr_detect[0:0] - end - case - assign $1\wr_detect[0:0] 1'0 - end - sync always - update \wr_detect $0\wr_detect[0:0] - end - attribute \src "issuer_ls180.v:161557.3-161602.6" - process $proc$issuer_ls180.v:161557$9863 - assign { } { } - assign { } { } - assign { } { } - assign $0\src20__data_o$next[1:0]$9864 $7\src20__data_o$next[1:0]$9871 - attribute \src "issuer_ls180.v:161558.5-161558.29" - switch \initial - attribute \src "issuer_ls180.v:161558.9-161558.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src20__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src20__data_o$next[1:0]$9865 $6\src20__data_o$next[1:0]$9870 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src20__data_o$next[1:0]$9866 \dest10__data_i - case - assign $2\src20__data_o$next[1:0]$9866 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src20__data_o$next[1:0]$9867 \dest20__data_i - case - assign $3\src20__data_o$next[1:0]$9867 $2\src20__data_o$next[1:0]$9866 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest30__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src20__data_o$next[1:0]$9868 \dest30__data_i - case - assign $4\src20__data_o$next[1:0]$9868 $3\src20__data_o$next[1:0]$9867 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src20__data_o$next[1:0]$9869 \w0__data_i - case - assign $5\src20__data_o$next[1:0]$9869 $4\src20__data_o$next[1:0]$9868 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src20__data_o$next[1:0]$9870 \reg - case - assign $6\src20__data_o$next[1:0]$9870 $5\src20__data_o$next[1:0]$9869 - end - case - assign $1\src20__data_o$next[1:0]$9865 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\src20__data_o$next[1:0]$9871 2'00 - case - assign $7\src20__data_o$next[1:0]$9871 $1\src20__data_o$next[1:0]$9865 - end - sync always - update \src20__data_o$next $0\src20__data_o$next[1:0]$9864 - end - attribute \src "issuer_ls180.v:161603.3-161638.6" - process $proc$issuer_ls180.v:161603$9872 - assign { } { } - assign { } { } - assign $0\wr_detect$4[0:0]$9873 $1\wr_detect$4[0:0]$9874 - attribute \src "issuer_ls180.v:161604.5-161604.29" - switch \initial - attribute \src "issuer_ls180.v:161604.9-161604.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src20__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$4[0:0]$9874 $5\wr_detect$4[0:0]$9878 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$9875 1'1 - case - assign $2\wr_detect$4[0:0]$9875 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$9876 1'1 - case - assign $3\wr_detect$4[0:0]$9876 $2\wr_detect$4[0:0]$9875 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest30__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$9877 1'1 - case - assign $4\wr_detect$4[0:0]$9877 $3\wr_detect$4[0:0]$9876 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\wr_detect$4[0:0]$9878 1'1 - case - assign $5\wr_detect$4[0:0]$9878 $4\wr_detect$4[0:0]$9877 - end - case - assign $1\wr_detect$4[0:0]$9874 1'0 - end - sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$9873 - end - attribute \src "issuer_ls180.v:161639.3-161684.6" - process $proc$issuer_ls180.v:161639$9879 - assign { } { } - assign { } { } - assign { } { } - assign $0\src30__data_o$next[1:0]$9880 $7\src30__data_o$next[1:0]$9887 - attribute \src "issuer_ls180.v:161640.5-161640.29" - switch \initial - attribute \src "issuer_ls180.v:161640.9-161640.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src30__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src30__data_o$next[1:0]$9881 $6\src30__data_o$next[1:0]$9886 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src30__data_o$next[1:0]$9882 \dest10__data_i - case - assign $2\src30__data_o$next[1:0]$9882 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src30__data_o$next[1:0]$9883 \dest20__data_i - case - assign $3\src30__data_o$next[1:0]$9883 $2\src30__data_o$next[1:0]$9882 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest30__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src30__data_o$next[1:0]$9884 \dest30__data_i - case - assign $4\src30__data_o$next[1:0]$9884 $3\src30__data_o$next[1:0]$9883 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src30__data_o$next[1:0]$9885 \w0__data_i - case - assign $5\src30__data_o$next[1:0]$9885 $4\src30__data_o$next[1:0]$9884 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$6 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src30__data_o$next[1:0]$9886 \reg - case - assign $6\src30__data_o$next[1:0]$9886 $5\src30__data_o$next[1:0]$9885 - end - case - assign $1\src30__data_o$next[1:0]$9881 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\src30__data_o$next[1:0]$9887 2'00 - case - assign $7\src30__data_o$next[1:0]$9887 $1\src30__data_o$next[1:0]$9881 - end - sync always - update \src30__data_o$next $0\src30__data_o$next[1:0]$9880 - end - attribute \src "issuer_ls180.v:161685.3-161720.6" - process $proc$issuer_ls180.v:161685$9888 - assign { } { } - assign { } { } - assign $0\wr_detect$7[0:0]$9889 $1\wr_detect$7[0:0]$9890 - attribute \src "issuer_ls180.v:161686.5-161686.29" - switch \initial - attribute \src "issuer_ls180.v:161686.9-161686.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src30__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$7[0:0]$9890 $5\wr_detect$7[0:0]$9894 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$7[0:0]$9891 1'1 - case - assign $2\wr_detect$7[0:0]$9891 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$7[0:0]$9892 1'1 - case - assign $3\wr_detect$7[0:0]$9892 $2\wr_detect$7[0:0]$9891 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest30__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$7[0:0]$9893 1'1 - case - assign $4\wr_detect$7[0:0]$9893 $3\wr_detect$7[0:0]$9892 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\wr_detect$7[0:0]$9894 1'1 - case - assign $5\wr_detect$7[0:0]$9894 $4\wr_detect$7[0:0]$9893 - end - case - assign $1\wr_detect$7[0:0]$9890 1'0 - end - sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$9889 - end - attribute \src "issuer_ls180.v:161721.3-161766.6" - process $proc$issuer_ls180.v:161721$9895 - assign { } { } - assign { } { } - assign { } { } - assign $0\r0__data_o$next[1:0]$9896 $7\r0__data_o$next[1:0]$9903 - attribute \src "issuer_ls180.v:161722.5-161722.29" - switch \initial - attribute \src "issuer_ls180.v:161722.9-161722.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r0__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r0__data_o$next[1:0]$9897 $6\r0__data_o$next[1:0]$9902 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r0__data_o$next[1:0]$9898 \dest10__data_i - case - assign $2\r0__data_o$next[1:0]$9898 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r0__data_o$next[1:0]$9899 \dest20__data_i - case - assign $3\r0__data_o$next[1:0]$9899 $2\r0__data_o$next[1:0]$9898 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest30__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r0__data_o$next[1:0]$9900 \dest30__data_i - case - assign $4\r0__data_o$next[1:0]$9900 $3\r0__data_o$next[1:0]$9899 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r0__data_o$next[1:0]$9901 \w0__data_i - case - assign $5\r0__data_o$next[1:0]$9901 $4\r0__data_o$next[1:0]$9900 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r0__data_o$next[1:0]$9902 \reg - case - assign $6\r0__data_o$next[1:0]$9902 $5\r0__data_o$next[1:0]$9901 - end - case - assign $1\r0__data_o$next[1:0]$9897 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\r0__data_o$next[1:0]$9903 2'00 - case - assign $7\r0__data_o$next[1:0]$9903 $1\r0__data_o$next[1:0]$9897 - end - sync always - update \r0__data_o$next $0\r0__data_o$next[1:0]$9896 - end - attribute \src "issuer_ls180.v:161767.3-161802.6" - process $proc$issuer_ls180.v:161767$9904 - assign { } { } - assign { } { } - assign $0\wr_detect$10[0:0]$9905 $1\wr_detect$10[0:0]$9906 - attribute \src "issuer_ls180.v:161768.5-161768.29" - switch \initial - attribute \src "issuer_ls180.v:161768.9-161768.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r0__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$10[0:0]$9906 $5\wr_detect$10[0:0]$9910 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$10[0:0]$9907 1'1 - case - assign $2\wr_detect$10[0:0]$9907 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$10[0:0]$9908 1'1 - case - assign $3\wr_detect$10[0:0]$9908 $2\wr_detect$10[0:0]$9907 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest30__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$10[0:0]$9909 1'1 - case - assign $4\wr_detect$10[0:0]$9909 $3\wr_detect$10[0:0]$9908 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\wr_detect$10[0:0]$9910 1'1 - case - assign $5\wr_detect$10[0:0]$9910 $4\wr_detect$10[0:0]$9909 - end - case - assign $1\wr_detect$10[0:0]$9906 1'0 - end - sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$9905 - end - attribute \src "issuer_ls180.v:161803.3-161835.6" - process $proc$issuer_ls180.v:161803$9911 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[1:0]$9912 $5\reg$next[1:0]$9917 - attribute \src "issuer_ls180.v:161804.5-161804.29" - switch \initial - attribute \src "issuer_ls180.v:161804.9-161804.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg$next[1:0]$9913 \dest10__data_i - case - assign $1\reg$next[1:0]$9913 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest20__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reg$next[1:0]$9914 \dest20__data_i - case - assign $2\reg$next[1:0]$9914 $1\reg$next[1:0]$9913 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest30__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\reg$next[1:0]$9915 \dest30__data_i - case - assign $3\reg$next[1:0]$9915 $2\reg$next[1:0]$9914 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\reg$next[1:0]$9916 \w0__data_i - case - assign $4\reg$next[1:0]$9916 $3\reg$next[1:0]$9915 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\reg$next[1:0]$9917 2'00 - case - assign $5\reg$next[1:0]$9917 $4\reg$next[1:0]$9916 - end - sync always - update \reg$next $0\reg$next[1:0]$9912 - end - connect \$9 $not$issuer_ls180.v:161461$9844_Y - connect \$1 $not$issuer_ls180.v:161462$9845_Y - connect \$3 $not$issuer_ls180.v:161463$9846_Y - connect \$6 $not$issuer_ls180.v:161464$9847_Y -end -attribute \src "issuer_ls180.v:161840.1-162059.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.state.reg_0" -attribute \generator "nMigen" -module \reg_0$132 - attribute \src "issuer_ls180.v:161892.3-161931.6" - wire width 64 $0\cia0__data_o$next[63:0]$9930 - attribute \src "issuer_ls180.v:161890.3-161891.41" - wire width 64 $0\cia0__data_o[63:0] - attribute \src "issuer_ls180.v:161841.7-161841.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:161962.3-162001.6" - wire width 64 $0\msr0__data_o$next[63:0]$9939 - attribute \src "issuer_ls180.v:161888.3-161889.41" - wire width 64 $0\msr0__data_o[63:0] - attribute \src "issuer_ls180.v:162032.3-162058.6" - wire width 64 $0\reg$next[63:0]$9953 - attribute \src "issuer_ls180.v:161886.3-161887.25" - wire width 64 $0\reg[63:0] - attribute \src "issuer_ls180.v:162002.3-162031.6" - wire $0\wr_detect$4[0:0]$9947 - attribute \src "issuer_ls180.v:161932.3-161961.6" - wire $0\wr_detect[0:0] - attribute \src "issuer_ls180.v:161892.3-161931.6" - wire width 64 $1\cia0__data_o$next[63:0]$9931 - attribute \src "issuer_ls180.v:161848.14-161848.49" - wire width 64 $1\cia0__data_o[63:0] - attribute \src "issuer_ls180.v:161962.3-162001.6" - wire width 64 $1\msr0__data_o$next[63:0]$9940 - attribute \src "issuer_ls180.v:161865.14-161865.49" - wire width 64 $1\msr0__data_o[63:0] - attribute \src "issuer_ls180.v:162032.3-162058.6" - wire width 64 $1\reg$next[63:0]$9954 - attribute \src "issuer_ls180.v:161877.14-161877.42" - wire width 64 $1\reg[63:0] - attribute \src "issuer_ls180.v:162002.3-162031.6" - wire $1\wr_detect$4[0:0]$9948 - attribute \src "issuer_ls180.v:161932.3-161961.6" - wire $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:161892.3-161931.6" - wire width 64 $2\cia0__data_o$next[63:0]$9932 - attribute \src "issuer_ls180.v:161962.3-162001.6" - wire width 64 $2\msr0__data_o$next[63:0]$9941 - attribute \src "issuer_ls180.v:162032.3-162058.6" - wire width 64 $2\reg$next[63:0]$9955 - attribute \src "issuer_ls180.v:162002.3-162031.6" - wire $2\wr_detect$4[0:0]$9949 - attribute \src "issuer_ls180.v:161932.3-161961.6" - wire $2\wr_detect[0:0] - attribute \src "issuer_ls180.v:161892.3-161931.6" - wire width 64 $3\cia0__data_o$next[63:0]$9933 - attribute \src "issuer_ls180.v:161962.3-162001.6" - wire width 64 $3\msr0__data_o$next[63:0]$9942 - attribute \src "issuer_ls180.v:162032.3-162058.6" - wire width 64 $3\reg$next[63:0]$9956 - attribute \src "issuer_ls180.v:162002.3-162031.6" - wire $3\wr_detect$4[0:0]$9950 - attribute \src "issuer_ls180.v:161932.3-161961.6" - wire $3\wr_detect[0:0] - attribute \src "issuer_ls180.v:161892.3-161931.6" - wire width 64 $4\cia0__data_o$next[63:0]$9934 - attribute \src "issuer_ls180.v:161962.3-162001.6" - wire width 64 $4\msr0__data_o$next[63:0]$9943 - attribute \src "issuer_ls180.v:162032.3-162058.6" - wire width 64 $4\reg$next[63:0]$9957 - attribute \src "issuer_ls180.v:162002.3-162031.6" - wire $4\wr_detect$4[0:0]$9951 - attribute \src "issuer_ls180.v:161932.3-161961.6" - wire $4\wr_detect[0:0] - attribute \src "issuer_ls180.v:161892.3-161931.6" - wire width 64 $5\cia0__data_o$next[63:0]$9935 - attribute \src "issuer_ls180.v:161962.3-162001.6" - wire width 64 $5\msr0__data_o$next[63:0]$9944 - attribute \src "issuer_ls180.v:161892.3-161931.6" - wire width 64 $6\cia0__data_o$next[63:0]$9936 - attribute \src "issuer_ls180.v:161962.3-162001.6" - wire width 64 $6\msr0__data_o$next[63:0]$9945 - attribute \src "issuer_ls180.v:161884.17-161884.100" - wire $not$issuer_ls180.v:161884$9924_Y - attribute \src "issuer_ls180.v:161885.17-161885.103" - wire $not$issuer_ls180.v:161885$9925_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \cia0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \cia0__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \cia0__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 12 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 11 \d_wr10__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \d_wr10__wen - attribute \src "issuer_ls180.v:161841.7-161841.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 9 \msr0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 5 \msr0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \msr0__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \msr0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \msr0__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 7 \nia0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \nia0__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:161884$9924 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$issuer_ls180.v:161884$9924_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:161885$9925 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$issuer_ls180.v:161885$9925_Y - end - attribute \src "issuer_ls180.v:161841.7-161841.20" - process $proc$issuer_ls180.v:161841$9958 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:161848.14-161848.49" - process $proc$issuer_ls180.v:161848$9959 - assign { } { } - assign $1\cia0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \cia0__data_o $1\cia0__data_o[63:0] - end - attribute \src "issuer_ls180.v:161865.14-161865.49" - process $proc$issuer_ls180.v:161865$9960 - assign { } { } - assign $1\msr0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \msr0__data_o $1\msr0__data_o[63:0] - end - attribute \src "issuer_ls180.v:161877.14-161877.42" - process $proc$issuer_ls180.v:161877$9961 - assign { } { } - assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \reg $1\reg[63:0] - end - attribute \src "issuer_ls180.v:161886.3-161887.25" - process $proc$issuer_ls180.v:161886$9926 - assign { } { } - assign $0\reg[63:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[63:0] - end - attribute \src "issuer_ls180.v:161888.3-161889.41" - process $proc$issuer_ls180.v:161888$9927 - assign { } { } - assign $0\msr0__data_o[63:0] \msr0__data_o$next - sync posedge \coresync_clk - update \msr0__data_o $0\msr0__data_o[63:0] - end - attribute \src "issuer_ls180.v:161890.3-161891.41" - process $proc$issuer_ls180.v:161890$9928 - assign { } { } - assign $0\cia0__data_o[63:0] \cia0__data_o$next - sync posedge \coresync_clk - update \cia0__data_o $0\cia0__data_o[63:0] - end - attribute \src "issuer_ls180.v:161892.3-161931.6" - process $proc$issuer_ls180.v:161892$9929 - assign { } { } - assign { } { } - assign { } { } - assign $0\cia0__data_o$next[63:0]$9930 $6\cia0__data_o$next[63:0]$9936 - attribute \src "issuer_ls180.v:161893.5-161893.29" - switch \initial - attribute \src "issuer_ls180.v:161893.9-161893.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cia0__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\cia0__data_o$next[63:0]$9931 $5\cia0__data_o$next[63:0]$9935 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cia0__data_o$next[63:0]$9932 \nia0__data_i - case - assign $2\cia0__data_o$next[63:0]$9932 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cia0__data_o$next[63:0]$9933 \msr0__data_i - case - assign $3\cia0__data_o$next[63:0]$9933 $2\cia0__data_o$next[63:0]$9932 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cia0__data_o$next[63:0]$9934 \d_wr10__data_i - case - assign $4\cia0__data_o$next[63:0]$9934 $3\cia0__data_o$next[63:0]$9933 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\cia0__data_o$next[63:0]$9935 \reg - case - assign $5\cia0__data_o$next[63:0]$9935 $4\cia0__data_o$next[63:0]$9934 - end - case - assign $1\cia0__data_o$next[63:0]$9931 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\cia0__data_o$next[63:0]$9936 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $6\cia0__data_o$next[63:0]$9936 $1\cia0__data_o$next[63:0]$9931 - end - sync always - update \cia0__data_o$next $0\cia0__data_o$next[63:0]$9930 - end - attribute \src "issuer_ls180.v:161932.3-161961.6" - process $proc$issuer_ls180.v:161932$9937 - assign { } { } - assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:161933.5-161933.29" - switch \initial - attribute \src "issuer_ls180.v:161933.9-161933.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cia0__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end - case - assign $1\wr_detect[0:0] 1'0 - end - sync always - update \wr_detect $0\wr_detect[0:0] - end - attribute \src "issuer_ls180.v:161962.3-162001.6" - process $proc$issuer_ls180.v:161962$9938 - assign { } { } - assign { } { } - assign { } { } - assign $0\msr0__data_o$next[63:0]$9939 $6\msr0__data_o$next[63:0]$9945 - attribute \src "issuer_ls180.v:161963.5-161963.29" - switch \initial - attribute \src "issuer_ls180.v:161963.9-161963.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \msr0__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\msr0__data_o$next[63:0]$9940 $5\msr0__data_o$next[63:0]$9944 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\msr0__data_o$next[63:0]$9941 \nia0__data_i - case - assign $2\msr0__data_o$next[63:0]$9941 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\msr0__data_o$next[63:0]$9942 \msr0__data_i - case - assign $3\msr0__data_o$next[63:0]$9942 $2\msr0__data_o$next[63:0]$9941 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\msr0__data_o$next[63:0]$9943 \d_wr10__data_i - case - assign $4\msr0__data_o$next[63:0]$9943 $3\msr0__data_o$next[63:0]$9942 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\msr0__data_o$next[63:0]$9944 \reg - case - assign $5\msr0__data_o$next[63:0]$9944 $4\msr0__data_o$next[63:0]$9943 - end - case - assign $1\msr0__data_o$next[63:0]$9940 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\msr0__data_o$next[63:0]$9945 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $6\msr0__data_o$next[63:0]$9945 $1\msr0__data_o$next[63:0]$9940 - end - sync always - update \msr0__data_o$next $0\msr0__data_o$next[63:0]$9939 - end - attribute \src "issuer_ls180.v:162002.3-162031.6" - process $proc$issuer_ls180.v:162002$9946 - assign { } { } - assign { } { } - assign $0\wr_detect$4[0:0]$9947 $1\wr_detect$4[0:0]$9948 - attribute \src "issuer_ls180.v:162003.5-162003.29" - switch \initial - attribute \src "issuer_ls180.v:162003.9-162003.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \msr0__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$4[0:0]$9948 $4\wr_detect$4[0:0]$9951 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$9949 1'1 - case - assign $2\wr_detect$4[0:0]$9949 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$9950 1'1 - case - assign $3\wr_detect$4[0:0]$9950 $2\wr_detect$4[0:0]$9949 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$9951 1'1 - case - assign $4\wr_detect$4[0:0]$9951 $3\wr_detect$4[0:0]$9950 - end - case - assign $1\wr_detect$4[0:0]$9948 1'0 - end - sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$9947 - end - attribute \src "issuer_ls180.v:162032.3-162058.6" - process $proc$issuer_ls180.v:162032$9952 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[63:0]$9953 $4\reg$next[63:0]$9957 - attribute \src "issuer_ls180.v:162033.5-162033.29" - switch \initial - attribute \src "issuer_ls180.v:162033.9-162033.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \nia0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg$next[63:0]$9954 \nia0__data_i - case - assign $1\reg$next[63:0]$9954 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \msr0__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reg$next[63:0]$9955 \msr0__data_i - case - assign $2\reg$next[63:0]$9955 $1\reg$next[63:0]$9954 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \d_wr10__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\reg$next[63:0]$9956 \d_wr10__data_i - case - assign $3\reg$next[63:0]$9956 $2\reg$next[63:0]$9955 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\reg$next[63:0]$9957 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $4\reg$next[63:0]$9957 $3\reg$next[63:0]$9956 - end - sync always - update \reg$next $0\reg$next[63:0]$9953 - end - connect \$1 $not$issuer_ls180.v:161884$9924_Y - connect \$3 $not$issuer_ls180.v:161885$9925_Y -end -attribute \src "issuer_ls180.v:162063.1-162534.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_1" -attribute \generator "nMigen" -module \reg_1 - attribute \src "issuer_ls180.v:162064.7-162064.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:162394.3-162433.6" - wire width 4 $0\r1__data_o$next[3:0]$10017 - attribute \src "issuer_ls180.v:162149.3-162150.37" - wire width 4 $0\r1__data_o[3:0] - attribute \src "issuer_ls180.v:162464.3-162503.6" - wire width 4 $0\r21__data_o$next[3:0]$10031 - attribute \src "issuer_ls180.v:162147.3-162148.39" - wire width 4 $0\r21__data_o[3:0] - attribute \src "issuer_ls180.v:162227.3-162253.6" - wire width 4 $0\reg$next[3:0]$9983 - attribute \src "issuer_ls180.v:162145.3-162146.25" - wire width 4 $0\reg[3:0] - attribute \src "issuer_ls180.v:162157.3-162196.6" - wire width 4 $0\src11__data_o$next[3:0]$9974 - attribute \src "issuer_ls180.v:162155.3-162156.43" - wire width 4 $0\src11__data_o[3:0] - attribute \src "issuer_ls180.v:162254.3-162293.6" - wire width 4 $0\src21__data_o$next[3:0]$9989 - attribute \src "issuer_ls180.v:162153.3-162154.43" - wire width 4 $0\src21__data_o[3:0] - attribute \src "issuer_ls180.v:162324.3-162363.6" - wire width 4 $0\src31__data_o$next[3:0]$10003 - attribute \src "issuer_ls180.v:162151.3-162152.43" - wire width 4 $0\src31__data_o[3:0] - attribute \src "issuer_ls180.v:162434.3-162463.6" - wire $0\wr_detect$10[0:0]$10025 - attribute \src "issuer_ls180.v:162504.3-162533.6" - wire $0\wr_detect$13[0:0]$10039 - attribute \src "issuer_ls180.v:162294.3-162323.6" - wire $0\wr_detect$4[0:0]$9997 - attribute \src "issuer_ls180.v:162364.3-162393.6" - wire $0\wr_detect$7[0:0]$10011 - attribute \src "issuer_ls180.v:162197.3-162226.6" - wire $0\wr_detect[0:0] - attribute \src "issuer_ls180.v:162394.3-162433.6" - wire width 4 $1\r1__data_o$next[3:0]$10018 - attribute \src "issuer_ls180.v:162089.13-162089.30" - wire width 4 $1\r1__data_o[3:0] - attribute \src "issuer_ls180.v:162464.3-162503.6" - wire width 4 $1\r21__data_o$next[3:0]$10032 - attribute \src "issuer_ls180.v:162096.13-162096.31" - wire width 4 $1\r21__data_o[3:0] - attribute \src "issuer_ls180.v:162227.3-162253.6" - wire width 4 $1\reg$next[3:0]$9984 - attribute \src "issuer_ls180.v:162102.13-162102.25" - wire width 4 $1\reg[3:0] - attribute \src "issuer_ls180.v:162157.3-162196.6" - wire width 4 $1\src11__data_o$next[3:0]$9975 - attribute \src "issuer_ls180.v:162107.13-162107.33" - wire width 4 $1\src11__data_o[3:0] - attribute \src "issuer_ls180.v:162254.3-162293.6" - wire width 4 $1\src21__data_o$next[3:0]$9990 - attribute \src "issuer_ls180.v:162114.13-162114.33" - wire width 4 $1\src21__data_o[3:0] - attribute \src "issuer_ls180.v:162324.3-162363.6" - wire width 4 $1\src31__data_o$next[3:0]$10004 - attribute \src "issuer_ls180.v:162121.13-162121.33" - wire width 4 $1\src31__data_o[3:0] - attribute \src "issuer_ls180.v:162434.3-162463.6" - wire $1\wr_detect$10[0:0]$10026 - attribute \src "issuer_ls180.v:162504.3-162533.6" - wire $1\wr_detect$13[0:0]$10040 - attribute \src "issuer_ls180.v:162294.3-162323.6" - wire $1\wr_detect$4[0:0]$9998 - attribute \src "issuer_ls180.v:162364.3-162393.6" - wire $1\wr_detect$7[0:0]$10012 - attribute \src "issuer_ls180.v:162197.3-162226.6" - wire $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:162394.3-162433.6" - wire width 4 $2\r1__data_o$next[3:0]$10019 - attribute \src "issuer_ls180.v:162464.3-162503.6" - wire width 4 $2\r21__data_o$next[3:0]$10033 - attribute \src "issuer_ls180.v:162227.3-162253.6" - wire width 4 $2\reg$next[3:0]$9985 - attribute \src "issuer_ls180.v:162157.3-162196.6" - wire width 4 $2\src11__data_o$next[3:0]$9976 - attribute \src "issuer_ls180.v:162254.3-162293.6" - wire width 4 $2\src21__data_o$next[3:0]$9991 - attribute \src "issuer_ls180.v:162324.3-162363.6" - wire width 4 $2\src31__data_o$next[3:0]$10005 - attribute \src "issuer_ls180.v:162434.3-162463.6" - wire $2\wr_detect$10[0:0]$10027 - attribute \src "issuer_ls180.v:162504.3-162533.6" - wire $2\wr_detect$13[0:0]$10041 - attribute \src "issuer_ls180.v:162294.3-162323.6" - wire $2\wr_detect$4[0:0]$9999 - attribute \src "issuer_ls180.v:162364.3-162393.6" - wire $2\wr_detect$7[0:0]$10013 - attribute \src "issuer_ls180.v:162197.3-162226.6" - wire $2\wr_detect[0:0] - attribute \src "issuer_ls180.v:162394.3-162433.6" - wire width 4 $3\r1__data_o$next[3:0]$10020 - attribute \src "issuer_ls180.v:162464.3-162503.6" - wire width 4 $3\r21__data_o$next[3:0]$10034 - attribute \src "issuer_ls180.v:162227.3-162253.6" - wire width 4 $3\reg$next[3:0]$9986 - attribute \src "issuer_ls180.v:162157.3-162196.6" - wire width 4 $3\src11__data_o$next[3:0]$9977 - attribute \src "issuer_ls180.v:162254.3-162293.6" - wire width 4 $3\src21__data_o$next[3:0]$9992 - attribute \src "issuer_ls180.v:162324.3-162363.6" - wire width 4 $3\src31__data_o$next[3:0]$10006 - attribute \src "issuer_ls180.v:162434.3-162463.6" - wire $3\wr_detect$10[0:0]$10028 - attribute \src "issuer_ls180.v:162504.3-162533.6" - wire $3\wr_detect$13[0:0]$10042 - attribute \src "issuer_ls180.v:162294.3-162323.6" - wire $3\wr_detect$4[0:0]$10000 - attribute \src "issuer_ls180.v:162364.3-162393.6" - wire $3\wr_detect$7[0:0]$10014 - attribute \src "issuer_ls180.v:162197.3-162226.6" - wire $3\wr_detect[0:0] - attribute \src "issuer_ls180.v:162394.3-162433.6" - wire width 4 $4\r1__data_o$next[3:0]$10021 - attribute \src "issuer_ls180.v:162464.3-162503.6" - wire width 4 $4\r21__data_o$next[3:0]$10035 - attribute \src "issuer_ls180.v:162227.3-162253.6" - wire width 4 $4\reg$next[3:0]$9987 - attribute \src "issuer_ls180.v:162157.3-162196.6" - wire width 4 $4\src11__data_o$next[3:0]$9978 - attribute \src "issuer_ls180.v:162254.3-162293.6" - wire width 4 $4\src21__data_o$next[3:0]$9993 - attribute \src "issuer_ls180.v:162324.3-162363.6" - wire width 4 $4\src31__data_o$next[3:0]$10007 - attribute \src "issuer_ls180.v:162434.3-162463.6" - wire $4\wr_detect$10[0:0]$10029 - attribute \src "issuer_ls180.v:162504.3-162533.6" - wire $4\wr_detect$13[0:0]$10043 - attribute \src "issuer_ls180.v:162294.3-162323.6" - wire $4\wr_detect$4[0:0]$10001 - attribute \src "issuer_ls180.v:162364.3-162393.6" - wire $4\wr_detect$7[0:0]$10015 - attribute \src "issuer_ls180.v:162197.3-162226.6" - wire $4\wr_detect[0:0] - attribute \src "issuer_ls180.v:162394.3-162433.6" - wire width 4 $5\r1__data_o$next[3:0]$10022 - attribute \src "issuer_ls180.v:162464.3-162503.6" - wire width 4 $5\r21__data_o$next[3:0]$10036 - attribute \src "issuer_ls180.v:162157.3-162196.6" - wire width 4 $5\src11__data_o$next[3:0]$9979 - attribute \src "issuer_ls180.v:162254.3-162293.6" - wire width 4 $5\src21__data_o$next[3:0]$9994 - attribute \src "issuer_ls180.v:162324.3-162363.6" - wire width 4 $5\src31__data_o$next[3:0]$10008 - attribute \src "issuer_ls180.v:162394.3-162433.6" - wire width 4 $6\r1__data_o$next[3:0]$10023 - attribute \src "issuer_ls180.v:162464.3-162503.6" - wire width 4 $6\r21__data_o$next[3:0]$10037 - attribute \src "issuer_ls180.v:162157.3-162196.6" - wire width 4 $6\src11__data_o$next[3:0]$9980 - attribute \src "issuer_ls180.v:162254.3-162293.6" - wire width 4 $6\src21__data_o$next[3:0]$9995 - attribute \src "issuer_ls180.v:162324.3-162363.6" - wire width 4 $6\src31__data_o$next[3:0]$10009 - attribute \src "issuer_ls180.v:162140.17-162140.104" - wire $not$issuer_ls180.v:162140$9962_Y - attribute \src "issuer_ls180.v:162141.18-162141.105" - wire $not$issuer_ls180.v:162141$9963_Y - attribute \src "issuer_ls180.v:162142.17-162142.100" - wire $not$issuer_ls180.v:162142$9964_Y - attribute \src "issuer_ls180.v:162143.17-162143.103" - wire $not$issuer_ls180.v:162143$9965_Y - attribute \src "issuer_ls180.v:162144.17-162144.103" - wire $not$issuer_ls180.v:162144$9966_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest11__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \dest11__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest21__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \dest21__wen - attribute \src "issuer_ls180.v:162064.7-162064.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r1__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 13 \r1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 14 \r21__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r21__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \r21__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src11__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src11__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \src11__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src21__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src21__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \src21__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src31__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src31__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \src31__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 16 \w1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 17 \w1__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:162140$9962 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $not$issuer_ls180.v:162140$9962_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:162141$9963 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$13 - connect \Y $not$issuer_ls180.v:162141$9963_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:162142$9964 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$issuer_ls180.v:162142$9964_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:162143$9965 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$issuer_ls180.v:162143$9965_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:162144$9966 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $not$issuer_ls180.v:162144$9966_Y - end - attribute \src "issuer_ls180.v:162064.7-162064.20" - process $proc$issuer_ls180.v:162064$10044 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:162089.13-162089.30" - process $proc$issuer_ls180.v:162089$10045 - assign { } { } - assign $1\r1__data_o[3:0] 4'0000 - sync always - sync init - update \r1__data_o $1\r1__data_o[3:0] - end - attribute \src "issuer_ls180.v:162096.13-162096.31" - process $proc$issuer_ls180.v:162096$10046 - assign { } { } - assign $1\r21__data_o[3:0] 4'0000 - sync always - sync init - update \r21__data_o $1\r21__data_o[3:0] - end - attribute \src "issuer_ls180.v:162102.13-162102.25" - process $proc$issuer_ls180.v:162102$10047 - assign { } { } - assign $1\reg[3:0] 4'0000 - sync always - sync init - update \reg $1\reg[3:0] - end - attribute \src "issuer_ls180.v:162107.13-162107.33" - process $proc$issuer_ls180.v:162107$10048 - assign { } { } - assign $1\src11__data_o[3:0] 4'0000 - sync always - sync init - update \src11__data_o $1\src11__data_o[3:0] - end - attribute \src "issuer_ls180.v:162114.13-162114.33" - process $proc$issuer_ls180.v:162114$10049 - assign { } { } - assign $1\src21__data_o[3:0] 4'0000 - sync always - sync init - update \src21__data_o $1\src21__data_o[3:0] - end - attribute \src "issuer_ls180.v:162121.13-162121.33" - process $proc$issuer_ls180.v:162121$10050 - assign { } { } - assign $1\src31__data_o[3:0] 4'0000 - sync always - sync init - update \src31__data_o $1\src31__data_o[3:0] - end - attribute \src "issuer_ls180.v:162145.3-162146.25" - process $proc$issuer_ls180.v:162145$9967 - assign { } { } - assign $0\reg[3:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[3:0] - end - attribute \src "issuer_ls180.v:162147.3-162148.39" - process $proc$issuer_ls180.v:162147$9968 - assign { } { } - assign $0\r21__data_o[3:0] \r21__data_o$next - sync posedge \coresync_clk - update \r21__data_o $0\r21__data_o[3:0] - end - attribute \src "issuer_ls180.v:162149.3-162150.37" - process $proc$issuer_ls180.v:162149$9969 - assign { } { } - assign $0\r1__data_o[3:0] \r1__data_o$next - sync posedge \coresync_clk - update \r1__data_o $0\r1__data_o[3:0] - end - attribute \src "issuer_ls180.v:162151.3-162152.43" - process $proc$issuer_ls180.v:162151$9970 - assign { } { } - assign $0\src31__data_o[3:0] \src31__data_o$next - sync posedge \coresync_clk - update \src31__data_o $0\src31__data_o[3:0] - end - attribute \src "issuer_ls180.v:162153.3-162154.43" - process $proc$issuer_ls180.v:162153$9971 - assign { } { } - assign $0\src21__data_o[3:0] \src21__data_o$next - sync posedge \coresync_clk - update \src21__data_o $0\src21__data_o[3:0] - end - attribute \src "issuer_ls180.v:162155.3-162156.43" - process $proc$issuer_ls180.v:162155$9972 - assign { } { } - assign $0\src11__data_o[3:0] \src11__data_o$next - sync posedge \coresync_clk - update \src11__data_o $0\src11__data_o[3:0] - end - attribute \src "issuer_ls180.v:162157.3-162196.6" - process $proc$issuer_ls180.v:162157$9973 - assign { } { } - assign { } { } - assign { } { } - assign $0\src11__data_o$next[3:0]$9974 $6\src11__data_o$next[3:0]$9980 - attribute \src "issuer_ls180.v:162158.5-162158.29" - switch \initial - attribute \src "issuer_ls180.v:162158.9-162158.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src11__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src11__data_o$next[3:0]$9975 $5\src11__data_o$next[3:0]$9979 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src11__data_o$next[3:0]$9976 \dest11__data_i - case - assign $2\src11__data_o$next[3:0]$9976 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src11__data_o$next[3:0]$9977 \dest21__data_i - case - assign $3\src11__data_o$next[3:0]$9977 $2\src11__data_o$next[3:0]$9976 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src11__data_o$next[3:0]$9978 \w1__data_i - case - assign $4\src11__data_o$next[3:0]$9978 $3\src11__data_o$next[3:0]$9977 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src11__data_o$next[3:0]$9979 \reg - case - assign $5\src11__data_o$next[3:0]$9979 $4\src11__data_o$next[3:0]$9978 - end - case - assign $1\src11__data_o$next[3:0]$9975 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src11__data_o$next[3:0]$9980 4'0000 - case - assign $6\src11__data_o$next[3:0]$9980 $1\src11__data_o$next[3:0]$9975 - end - sync always - update \src11__data_o$next $0\src11__data_o$next[3:0]$9974 - end - attribute \src "issuer_ls180.v:162197.3-162226.6" - process $proc$issuer_ls180.v:162197$9981 - assign { } { } - assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:162198.5-162198.29" - switch \initial - attribute \src "issuer_ls180.v:162198.9-162198.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src11__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end - case - assign $1\wr_detect[0:0] 1'0 - end - sync always - update \wr_detect $0\wr_detect[0:0] - end - attribute \src "issuer_ls180.v:162227.3-162253.6" - process $proc$issuer_ls180.v:162227$9982 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[3:0]$9983 $4\reg$next[3:0]$9987 - attribute \src "issuer_ls180.v:162228.5-162228.29" - switch \initial - attribute \src "issuer_ls180.v:162228.9-162228.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg$next[3:0]$9984 \dest11__data_i - case - assign $1\reg$next[3:0]$9984 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest21__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reg$next[3:0]$9985 \dest21__data_i - case - assign $2\reg$next[3:0]$9985 $1\reg$next[3:0]$9984 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\reg$next[3:0]$9986 \w1__data_i - case - assign $3\reg$next[3:0]$9986 $2\reg$next[3:0]$9985 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\reg$next[3:0]$9987 4'0000 - case - assign $4\reg$next[3:0]$9987 $3\reg$next[3:0]$9986 - end - sync always - update \reg$next $0\reg$next[3:0]$9983 - end - attribute \src "issuer_ls180.v:162254.3-162293.6" - process $proc$issuer_ls180.v:162254$9988 - assign { } { } - assign { } { } - assign { } { } - assign $0\src21__data_o$next[3:0]$9989 $6\src21__data_o$next[3:0]$9995 - attribute \src "issuer_ls180.v:162255.5-162255.29" - switch \initial - attribute \src "issuer_ls180.v:162255.9-162255.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src21__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src21__data_o$next[3:0]$9990 $5\src21__data_o$next[3:0]$9994 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src21__data_o$next[3:0]$9991 \dest11__data_i - case - assign $2\src21__data_o$next[3:0]$9991 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src21__data_o$next[3:0]$9992 \dest21__data_i - case - assign $3\src21__data_o$next[3:0]$9992 $2\src21__data_o$next[3:0]$9991 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src21__data_o$next[3:0]$9993 \w1__data_i - case - assign $4\src21__data_o$next[3:0]$9993 $3\src21__data_o$next[3:0]$9992 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src21__data_o$next[3:0]$9994 \reg - case - assign $5\src21__data_o$next[3:0]$9994 $4\src21__data_o$next[3:0]$9993 - end - case - assign $1\src21__data_o$next[3:0]$9990 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src21__data_o$next[3:0]$9995 4'0000 - case - assign $6\src21__data_o$next[3:0]$9995 $1\src21__data_o$next[3:0]$9990 - end - sync always - update \src21__data_o$next $0\src21__data_o$next[3:0]$9989 - end - attribute \src "issuer_ls180.v:162294.3-162323.6" - process $proc$issuer_ls180.v:162294$9996 - assign { } { } - assign { } { } - assign $0\wr_detect$4[0:0]$9997 $1\wr_detect$4[0:0]$9998 - attribute \src "issuer_ls180.v:162295.5-162295.29" - switch \initial - attribute \src "issuer_ls180.v:162295.9-162295.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src21__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$4[0:0]$9998 $4\wr_detect$4[0:0]$10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$9999 1'1 - case - assign $2\wr_detect$4[0:0]$9999 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$10000 1'1 - case - assign $3\wr_detect$4[0:0]$10000 $2\wr_detect$4[0:0]$9999 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$10001 1'1 - case - assign $4\wr_detect$4[0:0]$10001 $3\wr_detect$4[0:0]$10000 - end - case - assign $1\wr_detect$4[0:0]$9998 1'0 - end - sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$9997 - end - attribute \src "issuer_ls180.v:162324.3-162363.6" - process $proc$issuer_ls180.v:162324$10002 - assign { } { } - assign { } { } - assign { } { } - assign $0\src31__data_o$next[3:0]$10003 $6\src31__data_o$next[3:0]$10009 - attribute \src "issuer_ls180.v:162325.5-162325.29" - switch \initial - attribute \src "issuer_ls180.v:162325.9-162325.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src31__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src31__data_o$next[3:0]$10004 $5\src31__data_o$next[3:0]$10008 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src31__data_o$next[3:0]$10005 \dest11__data_i - case - assign $2\src31__data_o$next[3:0]$10005 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src31__data_o$next[3:0]$10006 \dest21__data_i - case - assign $3\src31__data_o$next[3:0]$10006 $2\src31__data_o$next[3:0]$10005 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src31__data_o$next[3:0]$10007 \w1__data_i - case - assign $4\src31__data_o$next[3:0]$10007 $3\src31__data_o$next[3:0]$10006 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$6 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src31__data_o$next[3:0]$10008 \reg - case - assign $5\src31__data_o$next[3:0]$10008 $4\src31__data_o$next[3:0]$10007 - end - case - assign $1\src31__data_o$next[3:0]$10004 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src31__data_o$next[3:0]$10009 4'0000 - case - assign $6\src31__data_o$next[3:0]$10009 $1\src31__data_o$next[3:0]$10004 - end - sync always - update \src31__data_o$next $0\src31__data_o$next[3:0]$10003 - end - attribute \src "issuer_ls180.v:162364.3-162393.6" - process $proc$issuer_ls180.v:162364$10010 - assign { } { } - assign { } { } - assign $0\wr_detect$7[0:0]$10011 $1\wr_detect$7[0:0]$10012 - attribute \src "issuer_ls180.v:162365.5-162365.29" - switch \initial - attribute \src "issuer_ls180.v:162365.9-162365.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src31__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$7[0:0]$10012 $4\wr_detect$7[0:0]$10015 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$7[0:0]$10013 1'1 - case - assign $2\wr_detect$7[0:0]$10013 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$7[0:0]$10014 1'1 - case - assign $3\wr_detect$7[0:0]$10014 $2\wr_detect$7[0:0]$10013 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$7[0:0]$10015 1'1 - case - assign $4\wr_detect$7[0:0]$10015 $3\wr_detect$7[0:0]$10014 - end - case - assign $1\wr_detect$7[0:0]$10012 1'0 - end - sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10011 - end - attribute \src "issuer_ls180.v:162394.3-162433.6" - process $proc$issuer_ls180.v:162394$10016 - assign { } { } - assign { } { } - assign { } { } - assign $0\r1__data_o$next[3:0]$10017 $6\r1__data_o$next[3:0]$10023 - attribute \src "issuer_ls180.v:162395.5-162395.29" - switch \initial - attribute \src "issuer_ls180.v:162395.9-162395.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r1__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r1__data_o$next[3:0]$10018 $5\r1__data_o$next[3:0]$10022 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r1__data_o$next[3:0]$10019 \dest11__data_i - case - assign $2\r1__data_o$next[3:0]$10019 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r1__data_o$next[3:0]$10020 \dest21__data_i - case - assign $3\r1__data_o$next[3:0]$10020 $2\r1__data_o$next[3:0]$10019 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r1__data_o$next[3:0]$10021 \w1__data_i - case - assign $4\r1__data_o$next[3:0]$10021 $3\r1__data_o$next[3:0]$10020 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r1__data_o$next[3:0]$10022 \reg - case - assign $5\r1__data_o$next[3:0]$10022 $4\r1__data_o$next[3:0]$10021 - end - case - assign $1\r1__data_o$next[3:0]$10018 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r1__data_o$next[3:0]$10023 4'0000 - case - assign $6\r1__data_o$next[3:0]$10023 $1\r1__data_o$next[3:0]$10018 - end - sync always - update \r1__data_o$next $0\r1__data_o$next[3:0]$10017 - end - attribute \src "issuer_ls180.v:162434.3-162463.6" - process $proc$issuer_ls180.v:162434$10024 - assign { } { } - assign { } { } - assign $0\wr_detect$10[0:0]$10025 $1\wr_detect$10[0:0]$10026 - attribute \src "issuer_ls180.v:162435.5-162435.29" - switch \initial - attribute \src "issuer_ls180.v:162435.9-162435.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r1__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$10[0:0]$10026 $4\wr_detect$10[0:0]$10029 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$10[0:0]$10027 1'1 - case - assign $2\wr_detect$10[0:0]$10027 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$10[0:0]$10028 1'1 - case - assign $3\wr_detect$10[0:0]$10028 $2\wr_detect$10[0:0]$10027 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$10[0:0]$10029 1'1 - case - assign $4\wr_detect$10[0:0]$10029 $3\wr_detect$10[0:0]$10028 - end - case - assign $1\wr_detect$10[0:0]$10026 1'0 - end - sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10025 - end - attribute \src "issuer_ls180.v:162464.3-162503.6" - process $proc$issuer_ls180.v:162464$10030 - assign { } { } - assign { } { } - assign { } { } - assign $0\r21__data_o$next[3:0]$10031 $6\r21__data_o$next[3:0]$10037 - attribute \src "issuer_ls180.v:162465.5-162465.29" - switch \initial - attribute \src "issuer_ls180.v:162465.9-162465.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r21__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r21__data_o$next[3:0]$10032 $5\r21__data_o$next[3:0]$10036 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r21__data_o$next[3:0]$10033 \dest11__data_i - case - assign $2\r21__data_o$next[3:0]$10033 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r21__data_o$next[3:0]$10034 \dest21__data_i - case - assign $3\r21__data_o$next[3:0]$10034 $2\r21__data_o$next[3:0]$10033 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r21__data_o$next[3:0]$10035 \w1__data_i - case - assign $4\r21__data_o$next[3:0]$10035 $3\r21__data_o$next[3:0]$10034 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$12 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r21__data_o$next[3:0]$10036 \reg - case - assign $5\r21__data_o$next[3:0]$10036 $4\r21__data_o$next[3:0]$10035 - end - case - assign $1\r21__data_o$next[3:0]$10032 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r21__data_o$next[3:0]$10037 4'0000 - case - assign $6\r21__data_o$next[3:0]$10037 $1\r21__data_o$next[3:0]$10032 - end - sync always - update \r21__data_o$next $0\r21__data_o$next[3:0]$10031 - end - attribute \src "issuer_ls180.v:162504.3-162533.6" - process $proc$issuer_ls180.v:162504$10038 - assign { } { } - assign { } { } - assign $0\wr_detect$13[0:0]$10039 $1\wr_detect$13[0:0]$10040 - attribute \src "issuer_ls180.v:162505.5-162505.29" - switch \initial - attribute \src "issuer_ls180.v:162505.9-162505.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r21__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$13[0:0]$10040 $4\wr_detect$13[0:0]$10043 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$13[0:0]$10041 1'1 - case - assign $2\wr_detect$13[0:0]$10041 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$13[0:0]$10042 1'1 - case - assign $3\wr_detect$13[0:0]$10042 $2\wr_detect$13[0:0]$10041 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$13[0:0]$10043 1'1 - case - assign $4\wr_detect$13[0:0]$10043 $3\wr_detect$13[0:0]$10042 - end - case - assign $1\wr_detect$13[0:0]$10040 1'0 - end - sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10039 - end - connect \$9 $not$issuer_ls180.v:162140$9962_Y - connect \$12 $not$issuer_ls180.v:162141$9963_Y - connect \$1 $not$issuer_ls180.v:162142$9964_Y - connect \$3 $not$issuer_ls180.v:162143$9965_Y - connect \$6 $not$issuer_ls180.v:162144$9966_Y -end -attribute \src "issuer_ls180.v:162538.1-162983.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.xer.reg_1" -attribute \generator "nMigen" -module \reg_1$130 - attribute \src "issuer_ls180.v:162539.7-162539.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:162868.3-162913.6" - wire width 2 $0\r1__data_o$next[1:0]$10103 - attribute \src "issuer_ls180.v:162614.3-162615.37" - wire width 2 $0\r1__data_o[1:0] - attribute \src "issuer_ls180.v:162950.3-162982.6" - wire width 2 $0\reg$next[1:0]$10119 - attribute \src "issuer_ls180.v:162612.3-162613.25" - wire width 2 $0\reg[1:0] - attribute \src "issuer_ls180.v:162622.3-162667.6" - wire width 2 $0\src11__data_o$next[1:0]$10061 - attribute \src "issuer_ls180.v:162620.3-162621.43" - wire width 2 $0\src11__data_o[1:0] - attribute \src "issuer_ls180.v:162704.3-162749.6" - wire width 2 $0\src21__data_o$next[1:0]$10071 - attribute \src "issuer_ls180.v:162618.3-162619.43" - wire width 2 $0\src21__data_o[1:0] - attribute \src "issuer_ls180.v:162786.3-162831.6" - wire width 2 $0\src31__data_o$next[1:0]$10087 - attribute \src "issuer_ls180.v:162616.3-162617.43" - wire width 2 $0\src31__data_o[1:0] - attribute \src "issuer_ls180.v:162914.3-162949.6" - wire $0\wr_detect$10[0:0]$10112 - attribute \src "issuer_ls180.v:162750.3-162785.6" - wire $0\wr_detect$4[0:0]$10080 - attribute \src "issuer_ls180.v:162832.3-162867.6" - wire $0\wr_detect$7[0:0]$10096 - attribute \src "issuer_ls180.v:162668.3-162703.6" - wire $0\wr_detect[0:0] - attribute \src "issuer_ls180.v:162868.3-162913.6" - wire width 2 $1\r1__data_o$next[1:0]$10104 - attribute \src "issuer_ls180.v:162566.13-162566.30" - wire width 2 $1\r1__data_o[1:0] - attribute \src "issuer_ls180.v:162950.3-162982.6" - wire width 2 $1\reg$next[1:0]$10120 - attribute \src "issuer_ls180.v:162572.13-162572.25" - wire width 2 $1\reg[1:0] - attribute \src "issuer_ls180.v:162622.3-162667.6" - wire width 2 $1\src11__data_o$next[1:0]$10062 - attribute \src "issuer_ls180.v:162577.13-162577.33" - wire width 2 $1\src11__data_o[1:0] - attribute \src "issuer_ls180.v:162704.3-162749.6" - wire width 2 $1\src21__data_o$next[1:0]$10072 - attribute \src "issuer_ls180.v:162584.13-162584.33" - wire width 2 $1\src21__data_o[1:0] - attribute \src "issuer_ls180.v:162786.3-162831.6" - wire width 2 $1\src31__data_o$next[1:0]$10088 - attribute \src "issuer_ls180.v:162591.13-162591.33" - wire width 2 $1\src31__data_o[1:0] - attribute \src "issuer_ls180.v:162914.3-162949.6" - wire $1\wr_detect$10[0:0]$10113 - attribute \src "issuer_ls180.v:162750.3-162785.6" - wire $1\wr_detect$4[0:0]$10081 - attribute \src "issuer_ls180.v:162832.3-162867.6" - wire $1\wr_detect$7[0:0]$10097 - attribute \src "issuer_ls180.v:162668.3-162703.6" - wire $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:162868.3-162913.6" - wire width 2 $2\r1__data_o$next[1:0]$10105 - attribute \src "issuer_ls180.v:162950.3-162982.6" - wire width 2 $2\reg$next[1:0]$10121 - attribute \src "issuer_ls180.v:162622.3-162667.6" - wire width 2 $2\src11__data_o$next[1:0]$10063 - attribute \src "issuer_ls180.v:162704.3-162749.6" - wire width 2 $2\src21__data_o$next[1:0]$10073 - attribute \src "issuer_ls180.v:162786.3-162831.6" - wire width 2 $2\src31__data_o$next[1:0]$10089 - attribute \src "issuer_ls180.v:162914.3-162949.6" - wire $2\wr_detect$10[0:0]$10114 - attribute \src "issuer_ls180.v:162750.3-162785.6" - wire $2\wr_detect$4[0:0]$10082 - attribute \src "issuer_ls180.v:162832.3-162867.6" - wire $2\wr_detect$7[0:0]$10098 - attribute \src "issuer_ls180.v:162668.3-162703.6" - wire $2\wr_detect[0:0] - attribute \src "issuer_ls180.v:162868.3-162913.6" - wire width 2 $3\r1__data_o$next[1:0]$10106 - attribute \src "issuer_ls180.v:162950.3-162982.6" - wire width 2 $3\reg$next[1:0]$10122 - attribute \src "issuer_ls180.v:162622.3-162667.6" - wire width 2 $3\src11__data_o$next[1:0]$10064 - attribute \src "issuer_ls180.v:162704.3-162749.6" - wire width 2 $3\src21__data_o$next[1:0]$10074 - attribute \src "issuer_ls180.v:162786.3-162831.6" - wire width 2 $3\src31__data_o$next[1:0]$10090 - attribute \src "issuer_ls180.v:162914.3-162949.6" - wire $3\wr_detect$10[0:0]$10115 - attribute \src "issuer_ls180.v:162750.3-162785.6" - wire $3\wr_detect$4[0:0]$10083 - attribute \src "issuer_ls180.v:162832.3-162867.6" - wire $3\wr_detect$7[0:0]$10099 - attribute \src "issuer_ls180.v:162668.3-162703.6" - wire $3\wr_detect[0:0] - attribute \src "issuer_ls180.v:162868.3-162913.6" - wire width 2 $4\r1__data_o$next[1:0]$10107 - attribute \src "issuer_ls180.v:162950.3-162982.6" - wire width 2 $4\reg$next[1:0]$10123 - attribute \src "issuer_ls180.v:162622.3-162667.6" - wire width 2 $4\src11__data_o$next[1:0]$10065 - attribute \src "issuer_ls180.v:162704.3-162749.6" - wire width 2 $4\src21__data_o$next[1:0]$10075 - attribute \src "issuer_ls180.v:162786.3-162831.6" - wire width 2 $4\src31__data_o$next[1:0]$10091 - attribute \src "issuer_ls180.v:162914.3-162949.6" - wire $4\wr_detect$10[0:0]$10116 - attribute \src "issuer_ls180.v:162750.3-162785.6" - wire $4\wr_detect$4[0:0]$10084 - attribute \src "issuer_ls180.v:162832.3-162867.6" - wire $4\wr_detect$7[0:0]$10100 - attribute \src "issuer_ls180.v:162668.3-162703.6" - wire $4\wr_detect[0:0] - attribute \src "issuer_ls180.v:162868.3-162913.6" - wire width 2 $5\r1__data_o$next[1:0]$10108 - attribute \src "issuer_ls180.v:162950.3-162982.6" - wire width 2 $5\reg$next[1:0]$10124 - attribute \src "issuer_ls180.v:162622.3-162667.6" - wire width 2 $5\src11__data_o$next[1:0]$10066 - attribute \src "issuer_ls180.v:162704.3-162749.6" - wire width 2 $5\src21__data_o$next[1:0]$10076 - attribute \src "issuer_ls180.v:162786.3-162831.6" - wire width 2 $5\src31__data_o$next[1:0]$10092 - attribute \src "issuer_ls180.v:162914.3-162949.6" - wire $5\wr_detect$10[0:0]$10117 - attribute \src "issuer_ls180.v:162750.3-162785.6" - wire $5\wr_detect$4[0:0]$10085 - attribute \src "issuer_ls180.v:162832.3-162867.6" - wire $5\wr_detect$7[0:0]$10101 - attribute \src "issuer_ls180.v:162668.3-162703.6" - wire $5\wr_detect[0:0] - attribute \src "issuer_ls180.v:162868.3-162913.6" - wire width 2 $6\r1__data_o$next[1:0]$10109 - attribute \src "issuer_ls180.v:162622.3-162667.6" - wire width 2 $6\src11__data_o$next[1:0]$10067 - attribute \src "issuer_ls180.v:162704.3-162749.6" - wire width 2 $6\src21__data_o$next[1:0]$10077 - attribute \src "issuer_ls180.v:162786.3-162831.6" - wire width 2 $6\src31__data_o$next[1:0]$10093 - attribute \src "issuer_ls180.v:162868.3-162913.6" - wire width 2 $7\r1__data_o$next[1:0]$10110 - attribute \src "issuer_ls180.v:162622.3-162667.6" - wire width 2 $7\src11__data_o$next[1:0]$10068 - attribute \src "issuer_ls180.v:162704.3-162749.6" - wire width 2 $7\src21__data_o$next[1:0]$10078 - attribute \src "issuer_ls180.v:162786.3-162831.6" - wire width 2 $7\src31__data_o$next[1:0]$10094 - attribute \src "issuer_ls180.v:162608.17-162608.104" - wire $not$issuer_ls180.v:162608$10051_Y - attribute \src "issuer_ls180.v:162609.17-162609.100" - wire $not$issuer_ls180.v:162609$10052_Y - attribute \src "issuer_ls180.v:162610.17-162610.103" - wire $not$issuer_ls180.v:162610$10053_Y - attribute \src "issuer_ls180.v:162611.17-162611.103" - wire $not$issuer_ls180.v:162611$10054_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 9 \dest11__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \dest11__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 11 \dest21__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \dest21__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 13 \dest31__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 12 \dest31__wen - attribute \src "issuer_ls180.v:162539.7-162539.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 14 \r1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \r1__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \r1__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 2 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 2 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 3 \src11__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src11__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \src11__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 5 \src21__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src21__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \src21__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 7 \src31__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src31__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \src31__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 16 \w1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 17 \w1__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:162608$10051 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $not$issuer_ls180.v:162608$10051_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:162609$10052 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$issuer_ls180.v:162609$10052_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:162610$10053 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$issuer_ls180.v:162610$10053_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:162611$10054 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $not$issuer_ls180.v:162611$10054_Y - end - attribute \src "issuer_ls180.v:162539.7-162539.20" - process $proc$issuer_ls180.v:162539$10125 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:162566.13-162566.30" - process $proc$issuer_ls180.v:162566$10126 - assign { } { } - assign $1\r1__data_o[1:0] 2'00 - sync always - sync init - update \r1__data_o $1\r1__data_o[1:0] - end - attribute \src "issuer_ls180.v:162572.13-162572.25" - process $proc$issuer_ls180.v:162572$10127 - assign { } { } - assign $1\reg[1:0] 2'00 - sync always - sync init - update \reg $1\reg[1:0] - end - attribute \src "issuer_ls180.v:162577.13-162577.33" - process $proc$issuer_ls180.v:162577$10128 - assign { } { } - assign $1\src11__data_o[1:0] 2'00 - sync always - sync init - update \src11__data_o $1\src11__data_o[1:0] - end - attribute \src "issuer_ls180.v:162584.13-162584.33" - process $proc$issuer_ls180.v:162584$10129 - assign { } { } - assign $1\src21__data_o[1:0] 2'00 - sync always - sync init - update \src21__data_o $1\src21__data_o[1:0] - end - attribute \src "issuer_ls180.v:162591.13-162591.33" - process $proc$issuer_ls180.v:162591$10130 - assign { } { } - assign $1\src31__data_o[1:0] 2'00 - sync always - sync init - update \src31__data_o $1\src31__data_o[1:0] - end - attribute \src "issuer_ls180.v:162612.3-162613.25" - process $proc$issuer_ls180.v:162612$10055 - assign { } { } - assign $0\reg[1:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[1:0] - end - attribute \src "issuer_ls180.v:162614.3-162615.37" - process $proc$issuer_ls180.v:162614$10056 - assign { } { } - assign $0\r1__data_o[1:0] \r1__data_o$next - sync posedge \coresync_clk - update \r1__data_o $0\r1__data_o[1:0] - end - attribute \src "issuer_ls180.v:162616.3-162617.43" - process $proc$issuer_ls180.v:162616$10057 - assign { } { } - assign $0\src31__data_o[1:0] \src31__data_o$next - sync posedge \coresync_clk - update \src31__data_o $0\src31__data_o[1:0] - end - attribute \src "issuer_ls180.v:162618.3-162619.43" - process $proc$issuer_ls180.v:162618$10058 - assign { } { } - assign $0\src21__data_o[1:0] \src21__data_o$next - sync posedge \coresync_clk - update \src21__data_o $0\src21__data_o[1:0] - end - attribute \src "issuer_ls180.v:162620.3-162621.43" - process $proc$issuer_ls180.v:162620$10059 - assign { } { } - assign $0\src11__data_o[1:0] \src11__data_o$next - sync posedge \coresync_clk - update \src11__data_o $0\src11__data_o[1:0] - end - attribute \src "issuer_ls180.v:162622.3-162667.6" - process $proc$issuer_ls180.v:162622$10060 - assign { } { } - assign { } { } - assign { } { } - assign $0\src11__data_o$next[1:0]$10061 $7\src11__data_o$next[1:0]$10068 - attribute \src "issuer_ls180.v:162623.5-162623.29" - switch \initial - attribute \src "issuer_ls180.v:162623.9-162623.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src11__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src11__data_o$next[1:0]$10062 $6\src11__data_o$next[1:0]$10067 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src11__data_o$next[1:0]$10063 \dest11__data_i - case - assign $2\src11__data_o$next[1:0]$10063 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src11__data_o$next[1:0]$10064 \dest21__data_i - case - assign $3\src11__data_o$next[1:0]$10064 $2\src11__data_o$next[1:0]$10063 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest31__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src11__data_o$next[1:0]$10065 \dest31__data_i - case - assign $4\src11__data_o$next[1:0]$10065 $3\src11__data_o$next[1:0]$10064 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src11__data_o$next[1:0]$10066 \w1__data_i - case - assign $5\src11__data_o$next[1:0]$10066 $4\src11__data_o$next[1:0]$10065 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src11__data_o$next[1:0]$10067 \reg - case - assign $6\src11__data_o$next[1:0]$10067 $5\src11__data_o$next[1:0]$10066 - end - case - assign $1\src11__data_o$next[1:0]$10062 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\src11__data_o$next[1:0]$10068 2'00 - case - assign $7\src11__data_o$next[1:0]$10068 $1\src11__data_o$next[1:0]$10062 - end - sync always - update \src11__data_o$next $0\src11__data_o$next[1:0]$10061 - end - attribute \src "issuer_ls180.v:162668.3-162703.6" - process $proc$issuer_ls180.v:162668$10069 - assign { } { } - assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:162669.5-162669.29" - switch \initial - attribute \src "issuer_ls180.v:162669.9-162669.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src11__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect[0:0] $5\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest31__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\wr_detect[0:0] 1'1 - case - assign $5\wr_detect[0:0] $4\wr_detect[0:0] - end - case - assign $1\wr_detect[0:0] 1'0 - end - sync always - update \wr_detect $0\wr_detect[0:0] - end - attribute \src "issuer_ls180.v:162704.3-162749.6" - process $proc$issuer_ls180.v:162704$10070 - assign { } { } - assign { } { } - assign { } { } - assign $0\src21__data_o$next[1:0]$10071 $7\src21__data_o$next[1:0]$10078 - attribute \src "issuer_ls180.v:162705.5-162705.29" - switch \initial - attribute \src "issuer_ls180.v:162705.9-162705.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src21__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src21__data_o$next[1:0]$10072 $6\src21__data_o$next[1:0]$10077 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src21__data_o$next[1:0]$10073 \dest11__data_i - case - assign $2\src21__data_o$next[1:0]$10073 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src21__data_o$next[1:0]$10074 \dest21__data_i - case - assign $3\src21__data_o$next[1:0]$10074 $2\src21__data_o$next[1:0]$10073 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest31__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src21__data_o$next[1:0]$10075 \dest31__data_i - case - assign $4\src21__data_o$next[1:0]$10075 $3\src21__data_o$next[1:0]$10074 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src21__data_o$next[1:0]$10076 \w1__data_i - case - assign $5\src21__data_o$next[1:0]$10076 $4\src21__data_o$next[1:0]$10075 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src21__data_o$next[1:0]$10077 \reg - case - assign $6\src21__data_o$next[1:0]$10077 $5\src21__data_o$next[1:0]$10076 - end - case - assign $1\src21__data_o$next[1:0]$10072 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\src21__data_o$next[1:0]$10078 2'00 - case - assign $7\src21__data_o$next[1:0]$10078 $1\src21__data_o$next[1:0]$10072 - end - sync always - update \src21__data_o$next $0\src21__data_o$next[1:0]$10071 - end - attribute \src "issuer_ls180.v:162750.3-162785.6" - process $proc$issuer_ls180.v:162750$10079 - assign { } { } - assign { } { } - assign $0\wr_detect$4[0:0]$10080 $1\wr_detect$4[0:0]$10081 - attribute \src "issuer_ls180.v:162751.5-162751.29" - switch \initial - attribute \src "issuer_ls180.v:162751.9-162751.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src21__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$4[0:0]$10081 $5\wr_detect$4[0:0]$10085 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$10082 1'1 - case - assign $2\wr_detect$4[0:0]$10082 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$10083 1'1 - case - assign $3\wr_detect$4[0:0]$10083 $2\wr_detect$4[0:0]$10082 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest31__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$10084 1'1 - case - assign $4\wr_detect$4[0:0]$10084 $3\wr_detect$4[0:0]$10083 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\wr_detect$4[0:0]$10085 1'1 - case - assign $5\wr_detect$4[0:0]$10085 $4\wr_detect$4[0:0]$10084 - end - case - assign $1\wr_detect$4[0:0]$10081 1'0 - end - sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10080 - end - attribute \src "issuer_ls180.v:162786.3-162831.6" - process $proc$issuer_ls180.v:162786$10086 - assign { } { } - assign { } { } - assign { } { } - assign $0\src31__data_o$next[1:0]$10087 $7\src31__data_o$next[1:0]$10094 - attribute \src "issuer_ls180.v:162787.5-162787.29" - switch \initial - attribute \src "issuer_ls180.v:162787.9-162787.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src31__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src31__data_o$next[1:0]$10088 $6\src31__data_o$next[1:0]$10093 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src31__data_o$next[1:0]$10089 \dest11__data_i - case - assign $2\src31__data_o$next[1:0]$10089 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src31__data_o$next[1:0]$10090 \dest21__data_i - case - assign $3\src31__data_o$next[1:0]$10090 $2\src31__data_o$next[1:0]$10089 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest31__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src31__data_o$next[1:0]$10091 \dest31__data_i - case - assign $4\src31__data_o$next[1:0]$10091 $3\src31__data_o$next[1:0]$10090 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src31__data_o$next[1:0]$10092 \w1__data_i - case - assign $5\src31__data_o$next[1:0]$10092 $4\src31__data_o$next[1:0]$10091 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$6 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src31__data_o$next[1:0]$10093 \reg - case - assign $6\src31__data_o$next[1:0]$10093 $5\src31__data_o$next[1:0]$10092 - end - case - assign $1\src31__data_o$next[1:0]$10088 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\src31__data_o$next[1:0]$10094 2'00 - case - assign $7\src31__data_o$next[1:0]$10094 $1\src31__data_o$next[1:0]$10088 - end - sync always - update \src31__data_o$next $0\src31__data_o$next[1:0]$10087 - end - attribute \src "issuer_ls180.v:162832.3-162867.6" - process $proc$issuer_ls180.v:162832$10095 - assign { } { } - assign { } { } - assign $0\wr_detect$7[0:0]$10096 $1\wr_detect$7[0:0]$10097 - attribute \src "issuer_ls180.v:162833.5-162833.29" - switch \initial - attribute \src "issuer_ls180.v:162833.9-162833.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src31__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$7[0:0]$10097 $5\wr_detect$7[0:0]$10101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$7[0:0]$10098 1'1 - case - assign $2\wr_detect$7[0:0]$10098 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$7[0:0]$10099 1'1 - case - assign $3\wr_detect$7[0:0]$10099 $2\wr_detect$7[0:0]$10098 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest31__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$7[0:0]$10100 1'1 - case - assign $4\wr_detect$7[0:0]$10100 $3\wr_detect$7[0:0]$10099 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\wr_detect$7[0:0]$10101 1'1 - case - assign $5\wr_detect$7[0:0]$10101 $4\wr_detect$7[0:0]$10100 - end - case - assign $1\wr_detect$7[0:0]$10097 1'0 - end - sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10096 - end - attribute \src "issuer_ls180.v:162868.3-162913.6" - process $proc$issuer_ls180.v:162868$10102 - assign { } { } - assign { } { } - assign { } { } - assign $0\r1__data_o$next[1:0]$10103 $7\r1__data_o$next[1:0]$10110 - attribute \src "issuer_ls180.v:162869.5-162869.29" - switch \initial - attribute \src "issuer_ls180.v:162869.9-162869.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r1__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r1__data_o$next[1:0]$10104 $6\r1__data_o$next[1:0]$10109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r1__data_o$next[1:0]$10105 \dest11__data_i - case - assign $2\r1__data_o$next[1:0]$10105 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r1__data_o$next[1:0]$10106 \dest21__data_i - case - assign $3\r1__data_o$next[1:0]$10106 $2\r1__data_o$next[1:0]$10105 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest31__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r1__data_o$next[1:0]$10107 \dest31__data_i - case - assign $4\r1__data_o$next[1:0]$10107 $3\r1__data_o$next[1:0]$10106 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r1__data_o$next[1:0]$10108 \w1__data_i - case - assign $5\r1__data_o$next[1:0]$10108 $4\r1__data_o$next[1:0]$10107 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r1__data_o$next[1:0]$10109 \reg - case - assign $6\r1__data_o$next[1:0]$10109 $5\r1__data_o$next[1:0]$10108 - end - case - assign $1\r1__data_o$next[1:0]$10104 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\r1__data_o$next[1:0]$10110 2'00 - case - assign $7\r1__data_o$next[1:0]$10110 $1\r1__data_o$next[1:0]$10104 - end - sync always - update \r1__data_o$next $0\r1__data_o$next[1:0]$10103 - end - attribute \src "issuer_ls180.v:162914.3-162949.6" - process $proc$issuer_ls180.v:162914$10111 - assign { } { } - assign { } { } - assign $0\wr_detect$10[0:0]$10112 $1\wr_detect$10[0:0]$10113 - attribute \src "issuer_ls180.v:162915.5-162915.29" - switch \initial - attribute \src "issuer_ls180.v:162915.9-162915.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r1__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$10[0:0]$10113 $5\wr_detect$10[0:0]$10117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$10[0:0]$10114 1'1 - case - assign $2\wr_detect$10[0:0]$10114 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$10[0:0]$10115 1'1 - case - assign $3\wr_detect$10[0:0]$10115 $2\wr_detect$10[0:0]$10114 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest31__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$10[0:0]$10116 1'1 - case - assign $4\wr_detect$10[0:0]$10116 $3\wr_detect$10[0:0]$10115 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\wr_detect$10[0:0]$10117 1'1 - case - assign $5\wr_detect$10[0:0]$10117 $4\wr_detect$10[0:0]$10116 - end - case - assign $1\wr_detect$10[0:0]$10113 1'0 - end - sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10112 - end - attribute \src "issuer_ls180.v:162950.3-162982.6" - process $proc$issuer_ls180.v:162950$10118 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[1:0]$10119 $5\reg$next[1:0]$10124 - attribute \src "issuer_ls180.v:162951.5-162951.29" - switch \initial - attribute \src "issuer_ls180.v:162951.9-162951.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg$next[1:0]$10120 \dest11__data_i - case - assign $1\reg$next[1:0]$10120 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest21__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reg$next[1:0]$10121 \dest21__data_i - case - assign $2\reg$next[1:0]$10121 $1\reg$next[1:0]$10120 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest31__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\reg$next[1:0]$10122 \dest31__data_i - case - assign $3\reg$next[1:0]$10122 $2\reg$next[1:0]$10121 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\reg$next[1:0]$10123 \w1__data_i - case - assign $4\reg$next[1:0]$10123 $3\reg$next[1:0]$10122 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\reg$next[1:0]$10124 2'00 - case - assign $5\reg$next[1:0]$10124 $4\reg$next[1:0]$10123 - end - sync always - update \reg$next $0\reg$next[1:0]$10119 - end - connect \$9 $not$issuer_ls180.v:162608$10051_Y - connect \$1 $not$issuer_ls180.v:162609$10052_Y - connect \$3 $not$issuer_ls180.v:162610$10053_Y - connect \$6 $not$issuer_ls180.v:162611$10054_Y -end -attribute \src "issuer_ls180.v:162987.1-163206.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.state.reg_1" -attribute \generator "nMigen" -module \reg_1$133 - attribute \src "issuer_ls180.v:163039.3-163078.6" - wire width 64 $0\cia1__data_o$next[63:0]$10137 - attribute \src "issuer_ls180.v:163037.3-163038.41" - wire width 64 $0\cia1__data_o[63:0] - attribute \src "issuer_ls180.v:162988.7-162988.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:163109.3-163148.6" - wire width 64 $0\msr1__data_o$next[63:0]$10146 - attribute \src "issuer_ls180.v:163035.3-163036.41" - wire width 64 $0\msr1__data_o[63:0] - attribute \src "issuer_ls180.v:163179.3-163205.6" - wire width 64 $0\reg$next[63:0]$10160 - attribute \src "issuer_ls180.v:163033.3-163034.25" - wire width 64 $0\reg[63:0] - attribute \src "issuer_ls180.v:163149.3-163178.6" - wire $0\wr_detect$4[0:0]$10154 - attribute \src "issuer_ls180.v:163079.3-163108.6" - wire $0\wr_detect[0:0] - attribute \src "issuer_ls180.v:163039.3-163078.6" - wire width 64 $1\cia1__data_o$next[63:0]$10138 - attribute \src "issuer_ls180.v:162995.14-162995.49" - wire width 64 $1\cia1__data_o[63:0] - attribute \src "issuer_ls180.v:163109.3-163148.6" - wire width 64 $1\msr1__data_o$next[63:0]$10147 - attribute \src "issuer_ls180.v:163012.14-163012.49" - wire width 64 $1\msr1__data_o[63:0] - attribute \src "issuer_ls180.v:163179.3-163205.6" - wire width 64 $1\reg$next[63:0]$10161 - attribute \src "issuer_ls180.v:163024.14-163024.42" - wire width 64 $1\reg[63:0] - attribute \src "issuer_ls180.v:163149.3-163178.6" - wire $1\wr_detect$4[0:0]$10155 - attribute \src "issuer_ls180.v:163079.3-163108.6" - wire $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:163039.3-163078.6" - wire width 64 $2\cia1__data_o$next[63:0]$10139 - attribute \src "issuer_ls180.v:163109.3-163148.6" - wire width 64 $2\msr1__data_o$next[63:0]$10148 - attribute \src "issuer_ls180.v:163179.3-163205.6" - wire width 64 $2\reg$next[63:0]$10162 - attribute \src "issuer_ls180.v:163149.3-163178.6" - wire $2\wr_detect$4[0:0]$10156 - attribute \src "issuer_ls180.v:163079.3-163108.6" - wire $2\wr_detect[0:0] - attribute \src "issuer_ls180.v:163039.3-163078.6" - wire width 64 $3\cia1__data_o$next[63:0]$10140 - attribute \src "issuer_ls180.v:163109.3-163148.6" - wire width 64 $3\msr1__data_o$next[63:0]$10149 - attribute \src "issuer_ls180.v:163179.3-163205.6" - wire width 64 $3\reg$next[63:0]$10163 - attribute \src "issuer_ls180.v:163149.3-163178.6" - wire $3\wr_detect$4[0:0]$10157 - attribute \src "issuer_ls180.v:163079.3-163108.6" - wire $3\wr_detect[0:0] - attribute \src "issuer_ls180.v:163039.3-163078.6" - wire width 64 $4\cia1__data_o$next[63:0]$10141 - attribute \src "issuer_ls180.v:163109.3-163148.6" - wire width 64 $4\msr1__data_o$next[63:0]$10150 - attribute \src "issuer_ls180.v:163179.3-163205.6" - wire width 64 $4\reg$next[63:0]$10164 - attribute \src "issuer_ls180.v:163149.3-163178.6" - wire $4\wr_detect$4[0:0]$10158 - attribute \src "issuer_ls180.v:163079.3-163108.6" - wire $4\wr_detect[0:0] - attribute \src "issuer_ls180.v:163039.3-163078.6" - wire width 64 $5\cia1__data_o$next[63:0]$10142 - attribute \src "issuer_ls180.v:163109.3-163148.6" - wire width 64 $5\msr1__data_o$next[63:0]$10151 - attribute \src "issuer_ls180.v:163039.3-163078.6" - wire width 64 $6\cia1__data_o$next[63:0]$10143 - attribute \src "issuer_ls180.v:163109.3-163148.6" - wire width 64 $6\msr1__data_o$next[63:0]$10152 - attribute \src "issuer_ls180.v:163031.17-163031.100" - wire $not$issuer_ls180.v:163031$10131_Y - attribute \src "issuer_ls180.v:163032.17-163032.103" - wire $not$issuer_ls180.v:163032$10132_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \cia1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \cia1__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \cia1__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 12 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 11 \d_wr11__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \d_wr11__wen - attribute \src "issuer_ls180.v:162988.7-162988.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 9 \msr1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 5 \msr1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \msr1__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \msr1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \msr1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 7 \nia1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \nia1__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:163031$10131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$issuer_ls180.v:163031$10131_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:163032$10132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$issuer_ls180.v:163032$10132_Y - end - attribute \src "issuer_ls180.v:162988.7-162988.20" - process $proc$issuer_ls180.v:162988$10165 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:162995.14-162995.49" - process $proc$issuer_ls180.v:162995$10166 - assign { } { } - assign $1\cia1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \cia1__data_o $1\cia1__data_o[63:0] - end - attribute \src "issuer_ls180.v:163012.14-163012.49" - process $proc$issuer_ls180.v:163012$10167 - assign { } { } - assign $1\msr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \msr1__data_o $1\msr1__data_o[63:0] - end - attribute \src "issuer_ls180.v:163024.14-163024.42" - process $proc$issuer_ls180.v:163024$10168 - assign { } { } - assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \reg $1\reg[63:0] - end - attribute \src "issuer_ls180.v:163033.3-163034.25" - process $proc$issuer_ls180.v:163033$10133 - assign { } { } - assign $0\reg[63:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[63:0] - end - attribute \src "issuer_ls180.v:163035.3-163036.41" - process $proc$issuer_ls180.v:163035$10134 - assign { } { } - assign $0\msr1__data_o[63:0] \msr1__data_o$next - sync posedge \coresync_clk - update \msr1__data_o $0\msr1__data_o[63:0] - end - attribute \src "issuer_ls180.v:163037.3-163038.41" - process $proc$issuer_ls180.v:163037$10135 - assign { } { } - assign $0\cia1__data_o[63:0] \cia1__data_o$next - sync posedge \coresync_clk - update \cia1__data_o $0\cia1__data_o[63:0] - end - attribute \src "issuer_ls180.v:163039.3-163078.6" - process $proc$issuer_ls180.v:163039$10136 - assign { } { } - assign { } { } - assign { } { } - assign $0\cia1__data_o$next[63:0]$10137 $6\cia1__data_o$next[63:0]$10143 - attribute \src "issuer_ls180.v:163040.5-163040.29" - switch \initial - attribute \src "issuer_ls180.v:163040.9-163040.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cia1__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\cia1__data_o$next[63:0]$10138 $5\cia1__data_o$next[63:0]$10142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cia1__data_o$next[63:0]$10139 \nia1__data_i - case - assign $2\cia1__data_o$next[63:0]$10139 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cia1__data_o$next[63:0]$10140 \msr1__data_i - case - assign $3\cia1__data_o$next[63:0]$10140 $2\cia1__data_o$next[63:0]$10139 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cia1__data_o$next[63:0]$10141 \d_wr11__data_i - case - assign $4\cia1__data_o$next[63:0]$10141 $3\cia1__data_o$next[63:0]$10140 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\cia1__data_o$next[63:0]$10142 \reg - case - assign $5\cia1__data_o$next[63:0]$10142 $4\cia1__data_o$next[63:0]$10141 - end - case - assign $1\cia1__data_o$next[63:0]$10138 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\cia1__data_o$next[63:0]$10143 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $6\cia1__data_o$next[63:0]$10143 $1\cia1__data_o$next[63:0]$10138 - end - sync always - update \cia1__data_o$next $0\cia1__data_o$next[63:0]$10137 - end - attribute \src "issuer_ls180.v:163079.3-163108.6" - process $proc$issuer_ls180.v:163079$10144 - assign { } { } - assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:163080.5-163080.29" - switch \initial - attribute \src "issuer_ls180.v:163080.9-163080.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cia1__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end - case - assign $1\wr_detect[0:0] 1'0 - end - sync always - update \wr_detect $0\wr_detect[0:0] - end - attribute \src "issuer_ls180.v:163109.3-163148.6" - process $proc$issuer_ls180.v:163109$10145 - assign { } { } - assign { } { } - assign { } { } - assign $0\msr1__data_o$next[63:0]$10146 $6\msr1__data_o$next[63:0]$10152 - attribute \src "issuer_ls180.v:163110.5-163110.29" - switch \initial - attribute \src "issuer_ls180.v:163110.9-163110.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \msr1__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\msr1__data_o$next[63:0]$10147 $5\msr1__data_o$next[63:0]$10151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\msr1__data_o$next[63:0]$10148 \nia1__data_i - case - assign $2\msr1__data_o$next[63:0]$10148 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\msr1__data_o$next[63:0]$10149 \msr1__data_i - case - assign $3\msr1__data_o$next[63:0]$10149 $2\msr1__data_o$next[63:0]$10148 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\msr1__data_o$next[63:0]$10150 \d_wr11__data_i - case - assign $4\msr1__data_o$next[63:0]$10150 $3\msr1__data_o$next[63:0]$10149 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\msr1__data_o$next[63:0]$10151 \reg - case - assign $5\msr1__data_o$next[63:0]$10151 $4\msr1__data_o$next[63:0]$10150 - end - case - assign $1\msr1__data_o$next[63:0]$10147 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\msr1__data_o$next[63:0]$10152 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $6\msr1__data_o$next[63:0]$10152 $1\msr1__data_o$next[63:0]$10147 - end - sync always - update \msr1__data_o$next $0\msr1__data_o$next[63:0]$10146 - end - attribute \src "issuer_ls180.v:163149.3-163178.6" - process $proc$issuer_ls180.v:163149$10153 - assign { } { } - assign { } { } - assign $0\wr_detect$4[0:0]$10154 $1\wr_detect$4[0:0]$10155 - attribute \src "issuer_ls180.v:163150.5-163150.29" - switch \initial - attribute \src "issuer_ls180.v:163150.9-163150.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \msr1__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$4[0:0]$10155 $4\wr_detect$4[0:0]$10158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$10156 1'1 - case - assign $2\wr_detect$4[0:0]$10156 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$10157 1'1 - case - assign $3\wr_detect$4[0:0]$10157 $2\wr_detect$4[0:0]$10156 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$10158 1'1 - case - assign $4\wr_detect$4[0:0]$10158 $3\wr_detect$4[0:0]$10157 - end - case - assign $1\wr_detect$4[0:0]$10155 1'0 - end - sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10154 - end - attribute \src "issuer_ls180.v:163179.3-163205.6" - process $proc$issuer_ls180.v:163179$10159 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[63:0]$10160 $4\reg$next[63:0]$10164 - attribute \src "issuer_ls180.v:163180.5-163180.29" - switch \initial - attribute \src "issuer_ls180.v:163180.9-163180.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \nia1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg$next[63:0]$10161 \nia1__data_i - case - assign $1\reg$next[63:0]$10161 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \msr1__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reg$next[63:0]$10162 \msr1__data_i - case - assign $2\reg$next[63:0]$10162 $1\reg$next[63:0]$10161 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \d_wr11__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\reg$next[63:0]$10163 \d_wr11__data_i - case - assign $3\reg$next[63:0]$10163 $2\reg$next[63:0]$10162 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\reg$next[63:0]$10164 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $4\reg$next[63:0]$10164 $3\reg$next[63:0]$10163 - end - sync always - update \reg$next $0\reg$next[63:0]$10160 - end - connect \$1 $not$issuer_ls180.v:163031$10131_Y - connect \$3 $not$issuer_ls180.v:163032$10132_Y -end -attribute \src "issuer_ls180.v:163210.1-163681.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_2" -attribute \generator "nMigen" -module \reg_2 - attribute \src "issuer_ls180.v:163211.7-163211.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:163611.3-163650.6" - wire width 4 $0\r22__data_o$next[3:0]$10238 - attribute \src "issuer_ls180.v:163294.3-163295.39" - wire width 4 $0\r22__data_o[3:0] - attribute \src "issuer_ls180.v:163541.3-163580.6" - wire width 4 $0\r2__data_o$next[3:0]$10224 - attribute \src "issuer_ls180.v:163296.3-163297.37" - wire width 4 $0\r2__data_o[3:0] - attribute \src "issuer_ls180.v:163374.3-163400.6" - wire width 4 $0\reg$next[3:0]$10190 - attribute \src "issuer_ls180.v:163292.3-163293.25" - wire width 4 $0\reg[3:0] - attribute \src "issuer_ls180.v:163304.3-163343.6" - wire width 4 $0\src12__data_o$next[3:0]$10181 - attribute \src "issuer_ls180.v:163302.3-163303.43" - wire width 4 $0\src12__data_o[3:0] - attribute \src "issuer_ls180.v:163401.3-163440.6" - wire width 4 $0\src22__data_o$next[3:0]$10196 - attribute \src "issuer_ls180.v:163300.3-163301.43" - wire width 4 $0\src22__data_o[3:0] - attribute \src "issuer_ls180.v:163471.3-163510.6" - wire width 4 $0\src32__data_o$next[3:0]$10210 - attribute \src "issuer_ls180.v:163298.3-163299.43" - wire width 4 $0\src32__data_o[3:0] - attribute \src "issuer_ls180.v:163581.3-163610.6" - wire $0\wr_detect$10[0:0]$10232 - attribute \src "issuer_ls180.v:163651.3-163680.6" - wire $0\wr_detect$13[0:0]$10246 - attribute \src "issuer_ls180.v:163441.3-163470.6" - wire $0\wr_detect$4[0:0]$10204 - attribute \src "issuer_ls180.v:163511.3-163540.6" - wire $0\wr_detect$7[0:0]$10218 - attribute \src "issuer_ls180.v:163344.3-163373.6" - wire $0\wr_detect[0:0] - attribute \src "issuer_ls180.v:163611.3-163650.6" - wire width 4 $1\r22__data_o$next[3:0]$10239 - attribute \src "issuer_ls180.v:163236.13-163236.31" - wire width 4 $1\r22__data_o[3:0] - attribute \src "issuer_ls180.v:163541.3-163580.6" - wire width 4 $1\r2__data_o$next[3:0]$10225 - attribute \src "issuer_ls180.v:163243.13-163243.30" - wire width 4 $1\r2__data_o[3:0] - attribute \src "issuer_ls180.v:163374.3-163400.6" - wire width 4 $1\reg$next[3:0]$10191 - attribute \src "issuer_ls180.v:163249.13-163249.25" - wire width 4 $1\reg[3:0] - attribute \src "issuer_ls180.v:163304.3-163343.6" - wire width 4 $1\src12__data_o$next[3:0]$10182 - attribute \src "issuer_ls180.v:163254.13-163254.33" - wire width 4 $1\src12__data_o[3:0] - attribute \src "issuer_ls180.v:163401.3-163440.6" - wire width 4 $1\src22__data_o$next[3:0]$10197 - attribute \src "issuer_ls180.v:163261.13-163261.33" - wire width 4 $1\src22__data_o[3:0] - attribute \src "issuer_ls180.v:163471.3-163510.6" - wire width 4 $1\src32__data_o$next[3:0]$10211 - attribute \src "issuer_ls180.v:163268.13-163268.33" - wire width 4 $1\src32__data_o[3:0] - attribute \src "issuer_ls180.v:163581.3-163610.6" - wire $1\wr_detect$10[0:0]$10233 - attribute \src "issuer_ls180.v:163651.3-163680.6" - wire $1\wr_detect$13[0:0]$10247 - attribute \src "issuer_ls180.v:163441.3-163470.6" - wire $1\wr_detect$4[0:0]$10205 - attribute \src "issuer_ls180.v:163511.3-163540.6" - wire $1\wr_detect$7[0:0]$10219 - attribute \src "issuer_ls180.v:163344.3-163373.6" - wire $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:163611.3-163650.6" - wire width 4 $2\r22__data_o$next[3:0]$10240 - attribute \src "issuer_ls180.v:163541.3-163580.6" - wire width 4 $2\r2__data_o$next[3:0]$10226 - attribute \src "issuer_ls180.v:163374.3-163400.6" - wire width 4 $2\reg$next[3:0]$10192 - attribute \src "issuer_ls180.v:163304.3-163343.6" - wire width 4 $2\src12__data_o$next[3:0]$10183 - attribute \src "issuer_ls180.v:163401.3-163440.6" - wire width 4 $2\src22__data_o$next[3:0]$10198 - attribute \src "issuer_ls180.v:163471.3-163510.6" - wire width 4 $2\src32__data_o$next[3:0]$10212 - attribute \src "issuer_ls180.v:163581.3-163610.6" - wire $2\wr_detect$10[0:0]$10234 - attribute \src "issuer_ls180.v:163651.3-163680.6" - wire $2\wr_detect$13[0:0]$10248 - attribute \src "issuer_ls180.v:163441.3-163470.6" - wire $2\wr_detect$4[0:0]$10206 - attribute \src "issuer_ls180.v:163511.3-163540.6" - wire $2\wr_detect$7[0:0]$10220 - attribute \src "issuer_ls180.v:163344.3-163373.6" - wire $2\wr_detect[0:0] - attribute \src "issuer_ls180.v:163611.3-163650.6" - wire width 4 $3\r22__data_o$next[3:0]$10241 - attribute \src "issuer_ls180.v:163541.3-163580.6" - wire width 4 $3\r2__data_o$next[3:0]$10227 - attribute \src "issuer_ls180.v:163374.3-163400.6" - wire width 4 $3\reg$next[3:0]$10193 - attribute \src "issuer_ls180.v:163304.3-163343.6" - wire width 4 $3\src12__data_o$next[3:0]$10184 - attribute \src "issuer_ls180.v:163401.3-163440.6" - wire width 4 $3\src22__data_o$next[3:0]$10199 - attribute \src "issuer_ls180.v:163471.3-163510.6" - wire width 4 $3\src32__data_o$next[3:0]$10213 - attribute \src "issuer_ls180.v:163581.3-163610.6" - wire $3\wr_detect$10[0:0]$10235 - attribute \src "issuer_ls180.v:163651.3-163680.6" - wire $3\wr_detect$13[0:0]$10249 - attribute \src "issuer_ls180.v:163441.3-163470.6" - wire $3\wr_detect$4[0:0]$10207 - attribute \src "issuer_ls180.v:163511.3-163540.6" - wire $3\wr_detect$7[0:0]$10221 - attribute \src "issuer_ls180.v:163344.3-163373.6" - wire $3\wr_detect[0:0] - attribute \src "issuer_ls180.v:163611.3-163650.6" - wire width 4 $4\r22__data_o$next[3:0]$10242 - attribute \src "issuer_ls180.v:163541.3-163580.6" - wire width 4 $4\r2__data_o$next[3:0]$10228 - attribute \src "issuer_ls180.v:163374.3-163400.6" - wire width 4 $4\reg$next[3:0]$10194 - attribute \src "issuer_ls180.v:163304.3-163343.6" - wire width 4 $4\src12__data_o$next[3:0]$10185 - attribute \src "issuer_ls180.v:163401.3-163440.6" - wire width 4 $4\src22__data_o$next[3:0]$10200 - attribute \src "issuer_ls180.v:163471.3-163510.6" - wire width 4 $4\src32__data_o$next[3:0]$10214 - attribute \src "issuer_ls180.v:163581.3-163610.6" - wire $4\wr_detect$10[0:0]$10236 - attribute \src "issuer_ls180.v:163651.3-163680.6" - wire $4\wr_detect$13[0:0]$10250 - attribute \src "issuer_ls180.v:163441.3-163470.6" - wire $4\wr_detect$4[0:0]$10208 - attribute \src "issuer_ls180.v:163511.3-163540.6" - wire $4\wr_detect$7[0:0]$10222 - attribute \src "issuer_ls180.v:163344.3-163373.6" - wire $4\wr_detect[0:0] - attribute \src "issuer_ls180.v:163611.3-163650.6" - wire width 4 $5\r22__data_o$next[3:0]$10243 - attribute \src "issuer_ls180.v:163541.3-163580.6" - wire width 4 $5\r2__data_o$next[3:0]$10229 - attribute \src "issuer_ls180.v:163304.3-163343.6" - wire width 4 $5\src12__data_o$next[3:0]$10186 - attribute \src "issuer_ls180.v:163401.3-163440.6" - wire width 4 $5\src22__data_o$next[3:0]$10201 - attribute \src "issuer_ls180.v:163471.3-163510.6" - wire width 4 $5\src32__data_o$next[3:0]$10215 - attribute \src "issuer_ls180.v:163611.3-163650.6" - wire width 4 $6\r22__data_o$next[3:0]$10244 - attribute \src "issuer_ls180.v:163541.3-163580.6" - wire width 4 $6\r2__data_o$next[3:0]$10230 - attribute \src "issuer_ls180.v:163304.3-163343.6" - wire width 4 $6\src12__data_o$next[3:0]$10187 - attribute \src "issuer_ls180.v:163401.3-163440.6" - wire width 4 $6\src22__data_o$next[3:0]$10202 - attribute \src "issuer_ls180.v:163471.3-163510.6" - wire width 4 $6\src32__data_o$next[3:0]$10216 - attribute \src "issuer_ls180.v:163287.17-163287.104" - wire $not$issuer_ls180.v:163287$10169_Y - attribute \src "issuer_ls180.v:163288.18-163288.105" - wire $not$issuer_ls180.v:163288$10170_Y - attribute \src "issuer_ls180.v:163289.17-163289.100" - wire $not$issuer_ls180.v:163289$10171_Y - attribute \src "issuer_ls180.v:163290.17-163290.103" - wire $not$issuer_ls180.v:163290$10172_Y - attribute \src "issuer_ls180.v:163291.17-163291.103" - wire $not$issuer_ls180.v:163291$10173_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest12__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \dest12__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest22__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \dest22__wen - attribute \src "issuer_ls180.v:163211.7-163211.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 14 \r22__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r22__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \r22__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r2__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 13 \r2__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src12__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src12__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \src12__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src22__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src22__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \src22__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src32__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src32__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \src32__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 16 \w2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 17 \w2__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:163287$10169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $not$issuer_ls180.v:163287$10169_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:163288$10170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$13 - connect \Y $not$issuer_ls180.v:163288$10170_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:163289$10171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$issuer_ls180.v:163289$10171_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:163290$10172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$issuer_ls180.v:163290$10172_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:163291$10173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $not$issuer_ls180.v:163291$10173_Y - end - attribute \src "issuer_ls180.v:163211.7-163211.20" - process $proc$issuer_ls180.v:163211$10251 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:163236.13-163236.31" - process $proc$issuer_ls180.v:163236$10252 - assign { } { } - assign $1\r22__data_o[3:0] 4'0000 - sync always - sync init - update \r22__data_o $1\r22__data_o[3:0] - end - attribute \src "issuer_ls180.v:163243.13-163243.30" - process $proc$issuer_ls180.v:163243$10253 - assign { } { } - assign $1\r2__data_o[3:0] 4'0000 - sync always - sync init - update \r2__data_o $1\r2__data_o[3:0] - end - attribute \src "issuer_ls180.v:163249.13-163249.25" - process $proc$issuer_ls180.v:163249$10254 - assign { } { } - assign $1\reg[3:0] 4'0000 - sync always - sync init - update \reg $1\reg[3:0] - end - attribute \src "issuer_ls180.v:163254.13-163254.33" - process $proc$issuer_ls180.v:163254$10255 - assign { } { } - assign $1\src12__data_o[3:0] 4'0000 - sync always - sync init - update \src12__data_o $1\src12__data_o[3:0] - end - attribute \src "issuer_ls180.v:163261.13-163261.33" - process $proc$issuer_ls180.v:163261$10256 - assign { } { } - assign $1\src22__data_o[3:0] 4'0000 - sync always - sync init - update \src22__data_o $1\src22__data_o[3:0] - end - attribute \src "issuer_ls180.v:163268.13-163268.33" - process $proc$issuer_ls180.v:163268$10257 - assign { } { } - assign $1\src32__data_o[3:0] 4'0000 - sync always - sync init - update \src32__data_o $1\src32__data_o[3:0] - end - attribute \src "issuer_ls180.v:163292.3-163293.25" - process $proc$issuer_ls180.v:163292$10174 - assign { } { } - assign $0\reg[3:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[3:0] - end - attribute \src "issuer_ls180.v:163294.3-163295.39" - process $proc$issuer_ls180.v:163294$10175 - assign { } { } - assign $0\r22__data_o[3:0] \r22__data_o$next - sync posedge \coresync_clk - update \r22__data_o $0\r22__data_o[3:0] - end - attribute \src "issuer_ls180.v:163296.3-163297.37" - process $proc$issuer_ls180.v:163296$10176 - assign { } { } - assign $0\r2__data_o[3:0] \r2__data_o$next - sync posedge \coresync_clk - update \r2__data_o $0\r2__data_o[3:0] - end - attribute \src "issuer_ls180.v:163298.3-163299.43" - process $proc$issuer_ls180.v:163298$10177 - assign { } { } - assign $0\src32__data_o[3:0] \src32__data_o$next - sync posedge \coresync_clk - update \src32__data_o $0\src32__data_o[3:0] - end - attribute \src "issuer_ls180.v:163300.3-163301.43" - process $proc$issuer_ls180.v:163300$10178 - assign { } { } - assign $0\src22__data_o[3:0] \src22__data_o$next - sync posedge \coresync_clk - update \src22__data_o $0\src22__data_o[3:0] - end - attribute \src "issuer_ls180.v:163302.3-163303.43" - process $proc$issuer_ls180.v:163302$10179 - assign { } { } - assign $0\src12__data_o[3:0] \src12__data_o$next - sync posedge \coresync_clk - update \src12__data_o $0\src12__data_o[3:0] - end - attribute \src "issuer_ls180.v:163304.3-163343.6" - process $proc$issuer_ls180.v:163304$10180 - assign { } { } - assign { } { } - assign { } { } - assign $0\src12__data_o$next[3:0]$10181 $6\src12__data_o$next[3:0]$10187 - attribute \src "issuer_ls180.v:163305.5-163305.29" - switch \initial - attribute \src "issuer_ls180.v:163305.9-163305.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src12__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src12__data_o$next[3:0]$10182 $5\src12__data_o$next[3:0]$10186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src12__data_o$next[3:0]$10183 \dest12__data_i - case - assign $2\src12__data_o$next[3:0]$10183 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src12__data_o$next[3:0]$10184 \dest22__data_i - case - assign $3\src12__data_o$next[3:0]$10184 $2\src12__data_o$next[3:0]$10183 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src12__data_o$next[3:0]$10185 \w2__data_i - case - assign $4\src12__data_o$next[3:0]$10185 $3\src12__data_o$next[3:0]$10184 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src12__data_o$next[3:0]$10186 \reg - case - assign $5\src12__data_o$next[3:0]$10186 $4\src12__data_o$next[3:0]$10185 - end - case - assign $1\src12__data_o$next[3:0]$10182 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src12__data_o$next[3:0]$10187 4'0000 - case - assign $6\src12__data_o$next[3:0]$10187 $1\src12__data_o$next[3:0]$10182 - end - sync always - update \src12__data_o$next $0\src12__data_o$next[3:0]$10181 - end - attribute \src "issuer_ls180.v:163344.3-163373.6" - process $proc$issuer_ls180.v:163344$10188 - assign { } { } - assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:163345.5-163345.29" - switch \initial - attribute \src "issuer_ls180.v:163345.9-163345.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src12__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end - case - assign $1\wr_detect[0:0] 1'0 - end - sync always - update \wr_detect $0\wr_detect[0:0] - end - attribute \src "issuer_ls180.v:163374.3-163400.6" - process $proc$issuer_ls180.v:163374$10189 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[3:0]$10190 $4\reg$next[3:0]$10194 - attribute \src "issuer_ls180.v:163375.5-163375.29" - switch \initial - attribute \src "issuer_ls180.v:163375.9-163375.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg$next[3:0]$10191 \dest12__data_i - case - assign $1\reg$next[3:0]$10191 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest22__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reg$next[3:0]$10192 \dest22__data_i - case - assign $2\reg$next[3:0]$10192 $1\reg$next[3:0]$10191 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\reg$next[3:0]$10193 \w2__data_i - case - assign $3\reg$next[3:0]$10193 $2\reg$next[3:0]$10192 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\reg$next[3:0]$10194 4'0000 - case - assign $4\reg$next[3:0]$10194 $3\reg$next[3:0]$10193 - end - sync always - update \reg$next $0\reg$next[3:0]$10190 - end - attribute \src "issuer_ls180.v:163401.3-163440.6" - process $proc$issuer_ls180.v:163401$10195 - assign { } { } - assign { } { } - assign { } { } - assign $0\src22__data_o$next[3:0]$10196 $6\src22__data_o$next[3:0]$10202 - attribute \src "issuer_ls180.v:163402.5-163402.29" - switch \initial - attribute \src "issuer_ls180.v:163402.9-163402.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src22__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src22__data_o$next[3:0]$10197 $5\src22__data_o$next[3:0]$10201 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src22__data_o$next[3:0]$10198 \dest12__data_i - case - assign $2\src22__data_o$next[3:0]$10198 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src22__data_o$next[3:0]$10199 \dest22__data_i - case - assign $3\src22__data_o$next[3:0]$10199 $2\src22__data_o$next[3:0]$10198 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src22__data_o$next[3:0]$10200 \w2__data_i - case - assign $4\src22__data_o$next[3:0]$10200 $3\src22__data_o$next[3:0]$10199 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src22__data_o$next[3:0]$10201 \reg - case - assign $5\src22__data_o$next[3:0]$10201 $4\src22__data_o$next[3:0]$10200 - end - case - assign $1\src22__data_o$next[3:0]$10197 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src22__data_o$next[3:0]$10202 4'0000 - case - assign $6\src22__data_o$next[3:0]$10202 $1\src22__data_o$next[3:0]$10197 - end - sync always - update \src22__data_o$next $0\src22__data_o$next[3:0]$10196 - end - attribute \src "issuer_ls180.v:163441.3-163470.6" - process $proc$issuer_ls180.v:163441$10203 - assign { } { } - assign { } { } - assign $0\wr_detect$4[0:0]$10204 $1\wr_detect$4[0:0]$10205 - attribute \src "issuer_ls180.v:163442.5-163442.29" - switch \initial - attribute \src "issuer_ls180.v:163442.9-163442.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src22__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$4[0:0]$10205 $4\wr_detect$4[0:0]$10208 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$10206 1'1 - case - assign $2\wr_detect$4[0:0]$10206 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$10207 1'1 - case - assign $3\wr_detect$4[0:0]$10207 $2\wr_detect$4[0:0]$10206 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$10208 1'1 - case - assign $4\wr_detect$4[0:0]$10208 $3\wr_detect$4[0:0]$10207 - end - case - assign $1\wr_detect$4[0:0]$10205 1'0 - end - sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10204 - end - attribute \src "issuer_ls180.v:163471.3-163510.6" - process $proc$issuer_ls180.v:163471$10209 - assign { } { } - assign { } { } - assign { } { } - assign $0\src32__data_o$next[3:0]$10210 $6\src32__data_o$next[3:0]$10216 - attribute \src "issuer_ls180.v:163472.5-163472.29" - switch \initial - attribute \src "issuer_ls180.v:163472.9-163472.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src32__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src32__data_o$next[3:0]$10211 $5\src32__data_o$next[3:0]$10215 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src32__data_o$next[3:0]$10212 \dest12__data_i - case - assign $2\src32__data_o$next[3:0]$10212 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src32__data_o$next[3:0]$10213 \dest22__data_i - case - assign $3\src32__data_o$next[3:0]$10213 $2\src32__data_o$next[3:0]$10212 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src32__data_o$next[3:0]$10214 \w2__data_i - case - assign $4\src32__data_o$next[3:0]$10214 $3\src32__data_o$next[3:0]$10213 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$6 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src32__data_o$next[3:0]$10215 \reg - case - assign $5\src32__data_o$next[3:0]$10215 $4\src32__data_o$next[3:0]$10214 - end - case - assign $1\src32__data_o$next[3:0]$10211 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src32__data_o$next[3:0]$10216 4'0000 - case - assign $6\src32__data_o$next[3:0]$10216 $1\src32__data_o$next[3:0]$10211 - end - sync always - update \src32__data_o$next $0\src32__data_o$next[3:0]$10210 - end - attribute \src "issuer_ls180.v:163511.3-163540.6" - process $proc$issuer_ls180.v:163511$10217 - assign { } { } - assign { } { } - assign $0\wr_detect$7[0:0]$10218 $1\wr_detect$7[0:0]$10219 - attribute \src "issuer_ls180.v:163512.5-163512.29" - switch \initial - attribute \src "issuer_ls180.v:163512.9-163512.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src32__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$7[0:0]$10219 $4\wr_detect$7[0:0]$10222 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$7[0:0]$10220 1'1 - case - assign $2\wr_detect$7[0:0]$10220 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$7[0:0]$10221 1'1 - case - assign $3\wr_detect$7[0:0]$10221 $2\wr_detect$7[0:0]$10220 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$7[0:0]$10222 1'1 - case - assign $4\wr_detect$7[0:0]$10222 $3\wr_detect$7[0:0]$10221 - end - case - assign $1\wr_detect$7[0:0]$10219 1'0 - end - sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10218 - end - attribute \src "issuer_ls180.v:163541.3-163580.6" - process $proc$issuer_ls180.v:163541$10223 - assign { } { } - assign { } { } - assign { } { } - assign $0\r2__data_o$next[3:0]$10224 $6\r2__data_o$next[3:0]$10230 - attribute \src "issuer_ls180.v:163542.5-163542.29" - switch \initial - attribute \src "issuer_ls180.v:163542.9-163542.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r2__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r2__data_o$next[3:0]$10225 $5\r2__data_o$next[3:0]$10229 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r2__data_o$next[3:0]$10226 \dest12__data_i - case - assign $2\r2__data_o$next[3:0]$10226 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r2__data_o$next[3:0]$10227 \dest22__data_i - case - assign $3\r2__data_o$next[3:0]$10227 $2\r2__data_o$next[3:0]$10226 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r2__data_o$next[3:0]$10228 \w2__data_i - case - assign $4\r2__data_o$next[3:0]$10228 $3\r2__data_o$next[3:0]$10227 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r2__data_o$next[3:0]$10229 \reg - case - assign $5\r2__data_o$next[3:0]$10229 $4\r2__data_o$next[3:0]$10228 - end - case - assign $1\r2__data_o$next[3:0]$10225 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r2__data_o$next[3:0]$10230 4'0000 - case - assign $6\r2__data_o$next[3:0]$10230 $1\r2__data_o$next[3:0]$10225 - end - sync always - update \r2__data_o$next $0\r2__data_o$next[3:0]$10224 - end - attribute \src "issuer_ls180.v:163581.3-163610.6" - process $proc$issuer_ls180.v:163581$10231 - assign { } { } - assign { } { } - assign $0\wr_detect$10[0:0]$10232 $1\wr_detect$10[0:0]$10233 - attribute \src "issuer_ls180.v:163582.5-163582.29" - switch \initial - attribute \src "issuer_ls180.v:163582.9-163582.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r2__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$10[0:0]$10233 $4\wr_detect$10[0:0]$10236 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$10[0:0]$10234 1'1 - case - assign $2\wr_detect$10[0:0]$10234 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$10[0:0]$10235 1'1 - case - assign $3\wr_detect$10[0:0]$10235 $2\wr_detect$10[0:0]$10234 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$10[0:0]$10236 1'1 - case - assign $4\wr_detect$10[0:0]$10236 $3\wr_detect$10[0:0]$10235 - end - case - assign $1\wr_detect$10[0:0]$10233 1'0 - end - sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10232 - end - attribute \src "issuer_ls180.v:163611.3-163650.6" - process $proc$issuer_ls180.v:163611$10237 - assign { } { } - assign { } { } - assign { } { } - assign $0\r22__data_o$next[3:0]$10238 $6\r22__data_o$next[3:0]$10244 - attribute \src "issuer_ls180.v:163612.5-163612.29" - switch \initial - attribute \src "issuer_ls180.v:163612.9-163612.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r22__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r22__data_o$next[3:0]$10239 $5\r22__data_o$next[3:0]$10243 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r22__data_o$next[3:0]$10240 \dest12__data_i - case - assign $2\r22__data_o$next[3:0]$10240 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r22__data_o$next[3:0]$10241 \dest22__data_i - case - assign $3\r22__data_o$next[3:0]$10241 $2\r22__data_o$next[3:0]$10240 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r22__data_o$next[3:0]$10242 \w2__data_i - case - assign $4\r22__data_o$next[3:0]$10242 $3\r22__data_o$next[3:0]$10241 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$12 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r22__data_o$next[3:0]$10243 \reg - case - assign $5\r22__data_o$next[3:0]$10243 $4\r22__data_o$next[3:0]$10242 - end - case - assign $1\r22__data_o$next[3:0]$10239 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r22__data_o$next[3:0]$10244 4'0000 - case - assign $6\r22__data_o$next[3:0]$10244 $1\r22__data_o$next[3:0]$10239 - end - sync always - update \r22__data_o$next $0\r22__data_o$next[3:0]$10238 - end - attribute \src "issuer_ls180.v:163651.3-163680.6" - process $proc$issuer_ls180.v:163651$10245 - assign { } { } - assign { } { } - assign $0\wr_detect$13[0:0]$10246 $1\wr_detect$13[0:0]$10247 - attribute \src "issuer_ls180.v:163652.5-163652.29" - switch \initial - attribute \src "issuer_ls180.v:163652.9-163652.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r22__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$13[0:0]$10247 $4\wr_detect$13[0:0]$10250 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$13[0:0]$10248 1'1 - case - assign $2\wr_detect$13[0:0]$10248 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$13[0:0]$10249 1'1 - case - assign $3\wr_detect$13[0:0]$10249 $2\wr_detect$13[0:0]$10248 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$13[0:0]$10250 1'1 - case - assign $4\wr_detect$13[0:0]$10250 $3\wr_detect$13[0:0]$10249 - end - case - assign $1\wr_detect$13[0:0]$10247 1'0 - end - sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10246 - end - connect \$9 $not$issuer_ls180.v:163287$10169_Y - connect \$12 $not$issuer_ls180.v:163288$10170_Y - connect \$1 $not$issuer_ls180.v:163289$10171_Y - connect \$3 $not$issuer_ls180.v:163290$10172_Y - connect \$6 $not$issuer_ls180.v:163291$10173_Y -end -attribute \src "issuer_ls180.v:163685.1-164130.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.xer.reg_2" -attribute \generator "nMigen" -module \reg_2$131 - attribute \src "issuer_ls180.v:163686.7-163686.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:164015.3-164060.6" - wire width 2 $0\r2__data_o$next[1:0]$10310 - attribute \src "issuer_ls180.v:163761.3-163762.37" - wire width 2 $0\r2__data_o[1:0] - attribute \src "issuer_ls180.v:164097.3-164129.6" - wire width 2 $0\reg$next[1:0]$10326 - attribute \src "issuer_ls180.v:163759.3-163760.25" - wire width 2 $0\reg[1:0] - attribute \src "issuer_ls180.v:163769.3-163814.6" - wire width 2 $0\src12__data_o$next[1:0]$10268 - attribute \src "issuer_ls180.v:163767.3-163768.43" - wire width 2 $0\src12__data_o[1:0] - attribute \src "issuer_ls180.v:163851.3-163896.6" - wire width 2 $0\src22__data_o$next[1:0]$10278 - attribute \src "issuer_ls180.v:163765.3-163766.43" - wire width 2 $0\src22__data_o[1:0] - attribute \src "issuer_ls180.v:163933.3-163978.6" - wire width 2 $0\src32__data_o$next[1:0]$10294 - attribute \src "issuer_ls180.v:163763.3-163764.43" - wire width 2 $0\src32__data_o[1:0] - attribute \src "issuer_ls180.v:164061.3-164096.6" - wire $0\wr_detect$10[0:0]$10319 - attribute \src "issuer_ls180.v:163897.3-163932.6" - wire $0\wr_detect$4[0:0]$10287 - attribute \src "issuer_ls180.v:163979.3-164014.6" - wire $0\wr_detect$7[0:0]$10303 - attribute \src "issuer_ls180.v:163815.3-163850.6" - wire $0\wr_detect[0:0] - attribute \src "issuer_ls180.v:164015.3-164060.6" - wire width 2 $1\r2__data_o$next[1:0]$10311 - attribute \src "issuer_ls180.v:163713.13-163713.30" - wire width 2 $1\r2__data_o[1:0] - attribute \src "issuer_ls180.v:164097.3-164129.6" - wire width 2 $1\reg$next[1:0]$10327 - attribute \src "issuer_ls180.v:163719.13-163719.25" - wire width 2 $1\reg[1:0] - attribute \src "issuer_ls180.v:163769.3-163814.6" - wire width 2 $1\src12__data_o$next[1:0]$10269 - attribute \src "issuer_ls180.v:163724.13-163724.33" - wire width 2 $1\src12__data_o[1:0] - attribute \src "issuer_ls180.v:163851.3-163896.6" - wire width 2 $1\src22__data_o$next[1:0]$10279 - attribute \src "issuer_ls180.v:163731.13-163731.33" - wire width 2 $1\src22__data_o[1:0] - attribute \src "issuer_ls180.v:163933.3-163978.6" - wire width 2 $1\src32__data_o$next[1:0]$10295 - attribute \src "issuer_ls180.v:163738.13-163738.33" - wire width 2 $1\src32__data_o[1:0] - attribute \src "issuer_ls180.v:164061.3-164096.6" - wire $1\wr_detect$10[0:0]$10320 - attribute \src "issuer_ls180.v:163897.3-163932.6" - wire $1\wr_detect$4[0:0]$10288 - attribute \src "issuer_ls180.v:163979.3-164014.6" - wire $1\wr_detect$7[0:0]$10304 - attribute \src "issuer_ls180.v:163815.3-163850.6" - wire $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:164015.3-164060.6" - wire width 2 $2\r2__data_o$next[1:0]$10312 - attribute \src "issuer_ls180.v:164097.3-164129.6" - wire width 2 $2\reg$next[1:0]$10328 - attribute \src "issuer_ls180.v:163769.3-163814.6" - wire width 2 $2\src12__data_o$next[1:0]$10270 - attribute \src "issuer_ls180.v:163851.3-163896.6" - wire width 2 $2\src22__data_o$next[1:0]$10280 - attribute \src "issuer_ls180.v:163933.3-163978.6" - wire width 2 $2\src32__data_o$next[1:0]$10296 - attribute \src "issuer_ls180.v:164061.3-164096.6" - wire $2\wr_detect$10[0:0]$10321 - attribute \src "issuer_ls180.v:163897.3-163932.6" - wire $2\wr_detect$4[0:0]$10289 - attribute \src "issuer_ls180.v:163979.3-164014.6" - wire $2\wr_detect$7[0:0]$10305 - attribute \src "issuer_ls180.v:163815.3-163850.6" - wire $2\wr_detect[0:0] - attribute \src "issuer_ls180.v:164015.3-164060.6" - wire width 2 $3\r2__data_o$next[1:0]$10313 - attribute \src "issuer_ls180.v:164097.3-164129.6" - wire width 2 $3\reg$next[1:0]$10329 - attribute \src "issuer_ls180.v:163769.3-163814.6" - wire width 2 $3\src12__data_o$next[1:0]$10271 - attribute \src "issuer_ls180.v:163851.3-163896.6" - wire width 2 $3\src22__data_o$next[1:0]$10281 - attribute \src "issuer_ls180.v:163933.3-163978.6" - wire width 2 $3\src32__data_o$next[1:0]$10297 - attribute \src "issuer_ls180.v:164061.3-164096.6" - wire $3\wr_detect$10[0:0]$10322 - attribute \src "issuer_ls180.v:163897.3-163932.6" - wire $3\wr_detect$4[0:0]$10290 - attribute \src "issuer_ls180.v:163979.3-164014.6" - wire $3\wr_detect$7[0:0]$10306 - attribute \src "issuer_ls180.v:163815.3-163850.6" - wire $3\wr_detect[0:0] - attribute \src "issuer_ls180.v:164015.3-164060.6" - wire width 2 $4\r2__data_o$next[1:0]$10314 - attribute \src "issuer_ls180.v:164097.3-164129.6" - wire width 2 $4\reg$next[1:0]$10330 - attribute \src "issuer_ls180.v:163769.3-163814.6" - wire width 2 $4\src12__data_o$next[1:0]$10272 - attribute \src "issuer_ls180.v:163851.3-163896.6" - wire width 2 $4\src22__data_o$next[1:0]$10282 - attribute \src "issuer_ls180.v:163933.3-163978.6" - wire width 2 $4\src32__data_o$next[1:0]$10298 - attribute \src "issuer_ls180.v:164061.3-164096.6" - wire $4\wr_detect$10[0:0]$10323 - attribute \src "issuer_ls180.v:163897.3-163932.6" - wire $4\wr_detect$4[0:0]$10291 - attribute \src "issuer_ls180.v:163979.3-164014.6" - wire $4\wr_detect$7[0:0]$10307 - attribute \src "issuer_ls180.v:163815.3-163850.6" - wire $4\wr_detect[0:0] - attribute \src "issuer_ls180.v:164015.3-164060.6" - wire width 2 $5\r2__data_o$next[1:0]$10315 - attribute \src "issuer_ls180.v:164097.3-164129.6" - wire width 2 $5\reg$next[1:0]$10331 - attribute \src "issuer_ls180.v:163769.3-163814.6" - wire width 2 $5\src12__data_o$next[1:0]$10273 - attribute \src "issuer_ls180.v:163851.3-163896.6" - wire width 2 $5\src22__data_o$next[1:0]$10283 - attribute \src "issuer_ls180.v:163933.3-163978.6" - wire width 2 $5\src32__data_o$next[1:0]$10299 - attribute \src "issuer_ls180.v:164061.3-164096.6" - wire $5\wr_detect$10[0:0]$10324 - attribute \src "issuer_ls180.v:163897.3-163932.6" - wire $5\wr_detect$4[0:0]$10292 - attribute \src "issuer_ls180.v:163979.3-164014.6" - wire $5\wr_detect$7[0:0]$10308 - attribute \src "issuer_ls180.v:163815.3-163850.6" - wire $5\wr_detect[0:0] - attribute \src "issuer_ls180.v:164015.3-164060.6" - wire width 2 $6\r2__data_o$next[1:0]$10316 - attribute \src "issuer_ls180.v:163769.3-163814.6" - wire width 2 $6\src12__data_o$next[1:0]$10274 - attribute \src "issuer_ls180.v:163851.3-163896.6" - wire width 2 $6\src22__data_o$next[1:0]$10284 - attribute \src "issuer_ls180.v:163933.3-163978.6" - wire width 2 $6\src32__data_o$next[1:0]$10300 - attribute \src "issuer_ls180.v:164015.3-164060.6" - wire width 2 $7\r2__data_o$next[1:0]$10317 - attribute \src "issuer_ls180.v:163769.3-163814.6" - wire width 2 $7\src12__data_o$next[1:0]$10275 - attribute \src "issuer_ls180.v:163851.3-163896.6" - wire width 2 $7\src22__data_o$next[1:0]$10285 - attribute \src "issuer_ls180.v:163933.3-163978.6" - wire width 2 $7\src32__data_o$next[1:0]$10301 - attribute \src "issuer_ls180.v:163755.17-163755.104" - wire $not$issuer_ls180.v:163755$10258_Y - attribute \src "issuer_ls180.v:163756.17-163756.100" - wire $not$issuer_ls180.v:163756$10259_Y - attribute \src "issuer_ls180.v:163757.17-163757.103" - wire $not$issuer_ls180.v:163757$10260_Y - attribute \src "issuer_ls180.v:163758.17-163758.103" - wire $not$issuer_ls180.v:163758$10261_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 9 \dest12__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \dest12__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 11 \dest22__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \dest22__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 13 \dest32__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 12 \dest32__wen - attribute \src "issuer_ls180.v:163686.7-163686.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 14 \r2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \r2__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \r2__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 2 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 2 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 3 \src12__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src12__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \src12__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 5 \src22__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src22__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \src22__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 7 \src32__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src32__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \src32__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 16 \w2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 17 \w2__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:163755$10258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $not$issuer_ls180.v:163755$10258_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:163756$10259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$issuer_ls180.v:163756$10259_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:163757$10260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$issuer_ls180.v:163757$10260_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:163758$10261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $not$issuer_ls180.v:163758$10261_Y - end - attribute \src "issuer_ls180.v:163686.7-163686.20" - process $proc$issuer_ls180.v:163686$10332 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:163713.13-163713.30" - process $proc$issuer_ls180.v:163713$10333 - assign { } { } - assign $1\r2__data_o[1:0] 2'00 - sync always - sync init - update \r2__data_o $1\r2__data_o[1:0] - end - attribute \src "issuer_ls180.v:163719.13-163719.25" - process $proc$issuer_ls180.v:163719$10334 - assign { } { } - assign $1\reg[1:0] 2'00 - sync always - sync init - update \reg $1\reg[1:0] - end - attribute \src "issuer_ls180.v:163724.13-163724.33" - process $proc$issuer_ls180.v:163724$10335 - assign { } { } - assign $1\src12__data_o[1:0] 2'00 - sync always - sync init - update \src12__data_o $1\src12__data_o[1:0] - end - attribute \src "issuer_ls180.v:163731.13-163731.33" - process $proc$issuer_ls180.v:163731$10336 - assign { } { } - assign $1\src22__data_o[1:0] 2'00 - sync always - sync init - update \src22__data_o $1\src22__data_o[1:0] - end - attribute \src "issuer_ls180.v:163738.13-163738.33" - process $proc$issuer_ls180.v:163738$10337 - assign { } { } - assign $1\src32__data_o[1:0] 2'00 - sync always - sync init - update \src32__data_o $1\src32__data_o[1:0] - end - attribute \src "issuer_ls180.v:163759.3-163760.25" - process $proc$issuer_ls180.v:163759$10262 - assign { } { } - assign $0\reg[1:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[1:0] - end - attribute \src "issuer_ls180.v:163761.3-163762.37" - process $proc$issuer_ls180.v:163761$10263 - assign { } { } - assign $0\r2__data_o[1:0] \r2__data_o$next - sync posedge \coresync_clk - update \r2__data_o $0\r2__data_o[1:0] - end - attribute \src "issuer_ls180.v:163763.3-163764.43" - process $proc$issuer_ls180.v:163763$10264 - assign { } { } - assign $0\src32__data_o[1:0] \src32__data_o$next - sync posedge \coresync_clk - update \src32__data_o $0\src32__data_o[1:0] - end - attribute \src "issuer_ls180.v:163765.3-163766.43" - process $proc$issuer_ls180.v:163765$10265 - assign { } { } - assign $0\src22__data_o[1:0] \src22__data_o$next - sync posedge \coresync_clk - update \src22__data_o $0\src22__data_o[1:0] - end - attribute \src "issuer_ls180.v:163767.3-163768.43" - process $proc$issuer_ls180.v:163767$10266 - assign { } { } - assign $0\src12__data_o[1:0] \src12__data_o$next - sync posedge \coresync_clk - update \src12__data_o $0\src12__data_o[1:0] - end - attribute \src "issuer_ls180.v:163769.3-163814.6" - process $proc$issuer_ls180.v:163769$10267 - assign { } { } - assign { } { } - assign { } { } - assign $0\src12__data_o$next[1:0]$10268 $7\src12__data_o$next[1:0]$10275 - attribute \src "issuer_ls180.v:163770.5-163770.29" - switch \initial - attribute \src "issuer_ls180.v:163770.9-163770.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src12__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src12__data_o$next[1:0]$10269 $6\src12__data_o$next[1:0]$10274 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src12__data_o$next[1:0]$10270 \dest12__data_i - case - assign $2\src12__data_o$next[1:0]$10270 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src12__data_o$next[1:0]$10271 \dest22__data_i - case - assign $3\src12__data_o$next[1:0]$10271 $2\src12__data_o$next[1:0]$10270 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest32__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src12__data_o$next[1:0]$10272 \dest32__data_i - case - assign $4\src12__data_o$next[1:0]$10272 $3\src12__data_o$next[1:0]$10271 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src12__data_o$next[1:0]$10273 \w2__data_i - case - assign $5\src12__data_o$next[1:0]$10273 $4\src12__data_o$next[1:0]$10272 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src12__data_o$next[1:0]$10274 \reg - case - assign $6\src12__data_o$next[1:0]$10274 $5\src12__data_o$next[1:0]$10273 - end - case - assign $1\src12__data_o$next[1:0]$10269 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\src12__data_o$next[1:0]$10275 2'00 - case - assign $7\src12__data_o$next[1:0]$10275 $1\src12__data_o$next[1:0]$10269 - end - sync always - update \src12__data_o$next $0\src12__data_o$next[1:0]$10268 - end - attribute \src "issuer_ls180.v:163815.3-163850.6" - process $proc$issuer_ls180.v:163815$10276 - assign { } { } - assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:163816.5-163816.29" - switch \initial - attribute \src "issuer_ls180.v:163816.9-163816.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src12__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect[0:0] $5\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest32__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\wr_detect[0:0] 1'1 - case - assign $5\wr_detect[0:0] $4\wr_detect[0:0] - end - case - assign $1\wr_detect[0:0] 1'0 - end - sync always - update \wr_detect $0\wr_detect[0:0] - end - attribute \src "issuer_ls180.v:163851.3-163896.6" - process $proc$issuer_ls180.v:163851$10277 - assign { } { } - assign { } { } - assign { } { } - assign $0\src22__data_o$next[1:0]$10278 $7\src22__data_o$next[1:0]$10285 - attribute \src "issuer_ls180.v:163852.5-163852.29" - switch \initial - attribute \src "issuer_ls180.v:163852.9-163852.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src22__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src22__data_o$next[1:0]$10279 $6\src22__data_o$next[1:0]$10284 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src22__data_o$next[1:0]$10280 \dest12__data_i - case - assign $2\src22__data_o$next[1:0]$10280 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src22__data_o$next[1:0]$10281 \dest22__data_i - case - assign $3\src22__data_o$next[1:0]$10281 $2\src22__data_o$next[1:0]$10280 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest32__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src22__data_o$next[1:0]$10282 \dest32__data_i - case - assign $4\src22__data_o$next[1:0]$10282 $3\src22__data_o$next[1:0]$10281 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src22__data_o$next[1:0]$10283 \w2__data_i - case - assign $5\src22__data_o$next[1:0]$10283 $4\src22__data_o$next[1:0]$10282 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src22__data_o$next[1:0]$10284 \reg - case - assign $6\src22__data_o$next[1:0]$10284 $5\src22__data_o$next[1:0]$10283 - end - case - assign $1\src22__data_o$next[1:0]$10279 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\src22__data_o$next[1:0]$10285 2'00 - case - assign $7\src22__data_o$next[1:0]$10285 $1\src22__data_o$next[1:0]$10279 - end - sync always - update \src22__data_o$next $0\src22__data_o$next[1:0]$10278 - end - attribute \src "issuer_ls180.v:163897.3-163932.6" - process $proc$issuer_ls180.v:163897$10286 - assign { } { } - assign { } { } - assign $0\wr_detect$4[0:0]$10287 $1\wr_detect$4[0:0]$10288 - attribute \src "issuer_ls180.v:163898.5-163898.29" - switch \initial - attribute \src "issuer_ls180.v:163898.9-163898.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src22__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$4[0:0]$10288 $5\wr_detect$4[0:0]$10292 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$10289 1'1 - case - assign $2\wr_detect$4[0:0]$10289 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$10290 1'1 - case - assign $3\wr_detect$4[0:0]$10290 $2\wr_detect$4[0:0]$10289 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest32__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$10291 1'1 - case - assign $4\wr_detect$4[0:0]$10291 $3\wr_detect$4[0:0]$10290 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\wr_detect$4[0:0]$10292 1'1 - case - assign $5\wr_detect$4[0:0]$10292 $4\wr_detect$4[0:0]$10291 - end - case - assign $1\wr_detect$4[0:0]$10288 1'0 - end - sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10287 - end - attribute \src "issuer_ls180.v:163933.3-163978.6" - process $proc$issuer_ls180.v:163933$10293 - assign { } { } - assign { } { } - assign { } { } - assign $0\src32__data_o$next[1:0]$10294 $7\src32__data_o$next[1:0]$10301 - attribute \src "issuer_ls180.v:163934.5-163934.29" - switch \initial - attribute \src "issuer_ls180.v:163934.9-163934.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src32__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src32__data_o$next[1:0]$10295 $6\src32__data_o$next[1:0]$10300 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src32__data_o$next[1:0]$10296 \dest12__data_i - case - assign $2\src32__data_o$next[1:0]$10296 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src32__data_o$next[1:0]$10297 \dest22__data_i - case - assign $3\src32__data_o$next[1:0]$10297 $2\src32__data_o$next[1:0]$10296 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest32__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src32__data_o$next[1:0]$10298 \dest32__data_i - case - assign $4\src32__data_o$next[1:0]$10298 $3\src32__data_o$next[1:0]$10297 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src32__data_o$next[1:0]$10299 \w2__data_i - case - assign $5\src32__data_o$next[1:0]$10299 $4\src32__data_o$next[1:0]$10298 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$6 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src32__data_o$next[1:0]$10300 \reg - case - assign $6\src32__data_o$next[1:0]$10300 $5\src32__data_o$next[1:0]$10299 - end - case - assign $1\src32__data_o$next[1:0]$10295 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\src32__data_o$next[1:0]$10301 2'00 - case - assign $7\src32__data_o$next[1:0]$10301 $1\src32__data_o$next[1:0]$10295 - end - sync always - update \src32__data_o$next $0\src32__data_o$next[1:0]$10294 - end - attribute \src "issuer_ls180.v:163979.3-164014.6" - process $proc$issuer_ls180.v:163979$10302 - assign { } { } - assign { } { } - assign $0\wr_detect$7[0:0]$10303 $1\wr_detect$7[0:0]$10304 - attribute \src "issuer_ls180.v:163980.5-163980.29" - switch \initial - attribute \src "issuer_ls180.v:163980.9-163980.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src32__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$7[0:0]$10304 $5\wr_detect$7[0:0]$10308 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$7[0:0]$10305 1'1 - case - assign $2\wr_detect$7[0:0]$10305 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$7[0:0]$10306 1'1 - case - assign $3\wr_detect$7[0:0]$10306 $2\wr_detect$7[0:0]$10305 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest32__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$7[0:0]$10307 1'1 - case - assign $4\wr_detect$7[0:0]$10307 $3\wr_detect$7[0:0]$10306 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\wr_detect$7[0:0]$10308 1'1 - case - assign $5\wr_detect$7[0:0]$10308 $4\wr_detect$7[0:0]$10307 - end - case - assign $1\wr_detect$7[0:0]$10304 1'0 - end - sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10303 - end - attribute \src "issuer_ls180.v:164015.3-164060.6" - process $proc$issuer_ls180.v:164015$10309 - assign { } { } - assign { } { } - assign { } { } - assign $0\r2__data_o$next[1:0]$10310 $7\r2__data_o$next[1:0]$10317 - attribute \src "issuer_ls180.v:164016.5-164016.29" - switch \initial - attribute \src "issuer_ls180.v:164016.9-164016.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r2__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r2__data_o$next[1:0]$10311 $6\r2__data_o$next[1:0]$10316 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r2__data_o$next[1:0]$10312 \dest12__data_i - case - assign $2\r2__data_o$next[1:0]$10312 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r2__data_o$next[1:0]$10313 \dest22__data_i - case - assign $3\r2__data_o$next[1:0]$10313 $2\r2__data_o$next[1:0]$10312 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest32__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r2__data_o$next[1:0]$10314 \dest32__data_i - case - assign $4\r2__data_o$next[1:0]$10314 $3\r2__data_o$next[1:0]$10313 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r2__data_o$next[1:0]$10315 \w2__data_i - case - assign $5\r2__data_o$next[1:0]$10315 $4\r2__data_o$next[1:0]$10314 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r2__data_o$next[1:0]$10316 \reg - case - assign $6\r2__data_o$next[1:0]$10316 $5\r2__data_o$next[1:0]$10315 - end - case - assign $1\r2__data_o$next[1:0]$10311 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\r2__data_o$next[1:0]$10317 2'00 - case - assign $7\r2__data_o$next[1:0]$10317 $1\r2__data_o$next[1:0]$10311 - end - sync always - update \r2__data_o$next $0\r2__data_o$next[1:0]$10310 - end - attribute \src "issuer_ls180.v:164061.3-164096.6" - process $proc$issuer_ls180.v:164061$10318 - assign { } { } - assign { } { } - assign $0\wr_detect$10[0:0]$10319 $1\wr_detect$10[0:0]$10320 - attribute \src "issuer_ls180.v:164062.5-164062.29" - switch \initial - attribute \src "issuer_ls180.v:164062.9-164062.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r2__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$10[0:0]$10320 $5\wr_detect$10[0:0]$10324 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$10[0:0]$10321 1'1 - case - assign $2\wr_detect$10[0:0]$10321 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$10[0:0]$10322 1'1 - case - assign $3\wr_detect$10[0:0]$10322 $2\wr_detect$10[0:0]$10321 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest32__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$10[0:0]$10323 1'1 - case - assign $4\wr_detect$10[0:0]$10323 $3\wr_detect$10[0:0]$10322 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\wr_detect$10[0:0]$10324 1'1 - case - assign $5\wr_detect$10[0:0]$10324 $4\wr_detect$10[0:0]$10323 - end - case - assign $1\wr_detect$10[0:0]$10320 1'0 - end - sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10319 - end - attribute \src "issuer_ls180.v:164097.3-164129.6" - process $proc$issuer_ls180.v:164097$10325 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[1:0]$10326 $5\reg$next[1:0]$10331 - attribute \src "issuer_ls180.v:164098.5-164098.29" - switch \initial - attribute \src "issuer_ls180.v:164098.9-164098.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg$next[1:0]$10327 \dest12__data_i - case - assign $1\reg$next[1:0]$10327 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest22__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reg$next[1:0]$10328 \dest22__data_i - case - assign $2\reg$next[1:0]$10328 $1\reg$next[1:0]$10327 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest32__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\reg$next[1:0]$10329 \dest32__data_i - case - assign $3\reg$next[1:0]$10329 $2\reg$next[1:0]$10328 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\reg$next[1:0]$10330 \w2__data_i - case - assign $4\reg$next[1:0]$10330 $3\reg$next[1:0]$10329 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\reg$next[1:0]$10331 2'00 - case - assign $5\reg$next[1:0]$10331 $4\reg$next[1:0]$10330 - end - sync always - update \reg$next $0\reg$next[1:0]$10326 - end - connect \$9 $not$issuer_ls180.v:163755$10258_Y - connect \$1 $not$issuer_ls180.v:163756$10259_Y - connect \$3 $not$issuer_ls180.v:163757$10260_Y - connect \$6 $not$issuer_ls180.v:163758$10261_Y -end -attribute \src "issuer_ls180.v:164134.1-164353.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.state.reg_2" -attribute \generator "nMigen" -module \reg_2$134 - attribute \src "issuer_ls180.v:164186.3-164225.6" - wire width 64 $0\cia2__data_o$next[63:0]$10344 - attribute \src "issuer_ls180.v:164184.3-164185.41" - wire width 64 $0\cia2__data_o[63:0] - attribute \src "issuer_ls180.v:164135.7-164135.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:164256.3-164295.6" - wire width 64 $0\msr2__data_o$next[63:0]$10353 - attribute \src "issuer_ls180.v:164182.3-164183.41" - wire width 64 $0\msr2__data_o[63:0] - attribute \src "issuer_ls180.v:164326.3-164352.6" - wire width 64 $0\reg$next[63:0]$10367 - attribute \src "issuer_ls180.v:164180.3-164181.25" - wire width 64 $0\reg[63:0] - attribute \src "issuer_ls180.v:164296.3-164325.6" - wire $0\wr_detect$4[0:0]$10361 - attribute \src "issuer_ls180.v:164226.3-164255.6" - wire $0\wr_detect[0:0] - attribute \src "issuer_ls180.v:164186.3-164225.6" - wire width 64 $1\cia2__data_o$next[63:0]$10345 - attribute \src "issuer_ls180.v:164142.14-164142.49" - wire width 64 $1\cia2__data_o[63:0] - attribute \src "issuer_ls180.v:164256.3-164295.6" - wire width 64 $1\msr2__data_o$next[63:0]$10354 - attribute \src "issuer_ls180.v:164159.14-164159.49" - wire width 64 $1\msr2__data_o[63:0] - attribute \src "issuer_ls180.v:164326.3-164352.6" - wire width 64 $1\reg$next[63:0]$10368 - attribute \src "issuer_ls180.v:164171.14-164171.42" - wire width 64 $1\reg[63:0] - attribute \src "issuer_ls180.v:164296.3-164325.6" - wire $1\wr_detect$4[0:0]$10362 - attribute \src "issuer_ls180.v:164226.3-164255.6" - wire $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:164186.3-164225.6" - wire width 64 $2\cia2__data_o$next[63:0]$10346 - attribute \src "issuer_ls180.v:164256.3-164295.6" - wire width 64 $2\msr2__data_o$next[63:0]$10355 - attribute \src "issuer_ls180.v:164326.3-164352.6" - wire width 64 $2\reg$next[63:0]$10369 - attribute \src "issuer_ls180.v:164296.3-164325.6" - wire $2\wr_detect$4[0:0]$10363 - attribute \src "issuer_ls180.v:164226.3-164255.6" - wire $2\wr_detect[0:0] - attribute \src "issuer_ls180.v:164186.3-164225.6" - wire width 64 $3\cia2__data_o$next[63:0]$10347 - attribute \src "issuer_ls180.v:164256.3-164295.6" - wire width 64 $3\msr2__data_o$next[63:0]$10356 - attribute \src "issuer_ls180.v:164326.3-164352.6" - wire width 64 $3\reg$next[63:0]$10370 - attribute \src "issuer_ls180.v:164296.3-164325.6" - wire $3\wr_detect$4[0:0]$10364 - attribute \src "issuer_ls180.v:164226.3-164255.6" - wire $3\wr_detect[0:0] - attribute \src "issuer_ls180.v:164186.3-164225.6" - wire width 64 $4\cia2__data_o$next[63:0]$10348 - attribute \src "issuer_ls180.v:164256.3-164295.6" - wire width 64 $4\msr2__data_o$next[63:0]$10357 - attribute \src "issuer_ls180.v:164326.3-164352.6" - wire width 64 $4\reg$next[63:0]$10371 - attribute \src "issuer_ls180.v:164296.3-164325.6" - wire $4\wr_detect$4[0:0]$10365 - attribute \src "issuer_ls180.v:164226.3-164255.6" - wire $4\wr_detect[0:0] - attribute \src "issuer_ls180.v:164186.3-164225.6" - wire width 64 $5\cia2__data_o$next[63:0]$10349 - attribute \src "issuer_ls180.v:164256.3-164295.6" - wire width 64 $5\msr2__data_o$next[63:0]$10358 - attribute \src "issuer_ls180.v:164186.3-164225.6" - wire width 64 $6\cia2__data_o$next[63:0]$10350 - attribute \src "issuer_ls180.v:164256.3-164295.6" - wire width 64 $6\msr2__data_o$next[63:0]$10359 - attribute \src "issuer_ls180.v:164178.17-164178.100" - wire $not$issuer_ls180.v:164178$10338_Y - attribute \src "issuer_ls180.v:164179.17-164179.103" - wire $not$issuer_ls180.v:164179$10339_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \cia2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \cia2__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \cia2__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 12 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 11 \d_wr12__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \d_wr12__wen - attribute \src "issuer_ls180.v:164135.7-164135.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 9 \msr2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 5 \msr2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \msr2__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \msr2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \msr2__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 7 \nia2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \nia2__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:164178$10338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$issuer_ls180.v:164178$10338_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:164179$10339 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$issuer_ls180.v:164179$10339_Y - end - attribute \src "issuer_ls180.v:164135.7-164135.20" - process $proc$issuer_ls180.v:164135$10372 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:164142.14-164142.49" - process $proc$issuer_ls180.v:164142$10373 - assign { } { } - assign $1\cia2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \cia2__data_o $1\cia2__data_o[63:0] - end - attribute \src "issuer_ls180.v:164159.14-164159.49" - process $proc$issuer_ls180.v:164159$10374 - assign { } { } - assign $1\msr2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \msr2__data_o $1\msr2__data_o[63:0] - end - attribute \src "issuer_ls180.v:164171.14-164171.42" - process $proc$issuer_ls180.v:164171$10375 - assign { } { } - assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \reg $1\reg[63:0] - end - attribute \src "issuer_ls180.v:164180.3-164181.25" - process $proc$issuer_ls180.v:164180$10340 - assign { } { } - assign $0\reg[63:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[63:0] - end - attribute \src "issuer_ls180.v:164182.3-164183.41" - process $proc$issuer_ls180.v:164182$10341 - assign { } { } - assign $0\msr2__data_o[63:0] \msr2__data_o$next - sync posedge \coresync_clk - update \msr2__data_o $0\msr2__data_o[63:0] - end - attribute \src "issuer_ls180.v:164184.3-164185.41" - process $proc$issuer_ls180.v:164184$10342 - assign { } { } - assign $0\cia2__data_o[63:0] \cia2__data_o$next - sync posedge \coresync_clk - update \cia2__data_o $0\cia2__data_o[63:0] - end - attribute \src "issuer_ls180.v:164186.3-164225.6" - process $proc$issuer_ls180.v:164186$10343 - assign { } { } - assign { } { } - assign { } { } - assign $0\cia2__data_o$next[63:0]$10344 $6\cia2__data_o$next[63:0]$10350 - attribute \src "issuer_ls180.v:164187.5-164187.29" - switch \initial - attribute \src "issuer_ls180.v:164187.9-164187.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cia2__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\cia2__data_o$next[63:0]$10345 $5\cia2__data_o$next[63:0]$10349 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cia2__data_o$next[63:0]$10346 \nia2__data_i - case - assign $2\cia2__data_o$next[63:0]$10346 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cia2__data_o$next[63:0]$10347 \msr2__data_i - case - assign $3\cia2__data_o$next[63:0]$10347 $2\cia2__data_o$next[63:0]$10346 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cia2__data_o$next[63:0]$10348 \d_wr12__data_i - case - assign $4\cia2__data_o$next[63:0]$10348 $3\cia2__data_o$next[63:0]$10347 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\cia2__data_o$next[63:0]$10349 \reg - case - assign $5\cia2__data_o$next[63:0]$10349 $4\cia2__data_o$next[63:0]$10348 - end - case - assign $1\cia2__data_o$next[63:0]$10345 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\cia2__data_o$next[63:0]$10350 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $6\cia2__data_o$next[63:0]$10350 $1\cia2__data_o$next[63:0]$10345 - end - sync always - update \cia2__data_o$next $0\cia2__data_o$next[63:0]$10344 - end - attribute \src "issuer_ls180.v:164226.3-164255.6" - process $proc$issuer_ls180.v:164226$10351 - assign { } { } - assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:164227.5-164227.29" - switch \initial - attribute \src "issuer_ls180.v:164227.9-164227.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cia2__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end - case - assign $1\wr_detect[0:0] 1'0 - end - sync always - update \wr_detect $0\wr_detect[0:0] - end - attribute \src "issuer_ls180.v:164256.3-164295.6" - process $proc$issuer_ls180.v:164256$10352 - assign { } { } - assign { } { } - assign { } { } - assign $0\msr2__data_o$next[63:0]$10353 $6\msr2__data_o$next[63:0]$10359 - attribute \src "issuer_ls180.v:164257.5-164257.29" - switch \initial - attribute \src "issuer_ls180.v:164257.9-164257.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \msr2__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\msr2__data_o$next[63:0]$10354 $5\msr2__data_o$next[63:0]$10358 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\msr2__data_o$next[63:0]$10355 \nia2__data_i - case - assign $2\msr2__data_o$next[63:0]$10355 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\msr2__data_o$next[63:0]$10356 \msr2__data_i - case - assign $3\msr2__data_o$next[63:0]$10356 $2\msr2__data_o$next[63:0]$10355 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\msr2__data_o$next[63:0]$10357 \d_wr12__data_i - case - assign $4\msr2__data_o$next[63:0]$10357 $3\msr2__data_o$next[63:0]$10356 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\msr2__data_o$next[63:0]$10358 \reg - case - assign $5\msr2__data_o$next[63:0]$10358 $4\msr2__data_o$next[63:0]$10357 - end - case - assign $1\msr2__data_o$next[63:0]$10354 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\msr2__data_o$next[63:0]$10359 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $6\msr2__data_o$next[63:0]$10359 $1\msr2__data_o$next[63:0]$10354 - end - sync always - update \msr2__data_o$next $0\msr2__data_o$next[63:0]$10353 - end - attribute \src "issuer_ls180.v:164296.3-164325.6" - process $proc$issuer_ls180.v:164296$10360 - assign { } { } - assign { } { } - assign $0\wr_detect$4[0:0]$10361 $1\wr_detect$4[0:0]$10362 - attribute \src "issuer_ls180.v:164297.5-164297.29" - switch \initial - attribute \src "issuer_ls180.v:164297.9-164297.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \msr2__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$4[0:0]$10362 $4\wr_detect$4[0:0]$10365 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$10363 1'1 - case - assign $2\wr_detect$4[0:0]$10363 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$10364 1'1 - case - assign $3\wr_detect$4[0:0]$10364 $2\wr_detect$4[0:0]$10363 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$10365 1'1 - case - assign $4\wr_detect$4[0:0]$10365 $3\wr_detect$4[0:0]$10364 - end - case - assign $1\wr_detect$4[0:0]$10362 1'0 - end - sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10361 - end - attribute \src "issuer_ls180.v:164326.3-164352.6" - process $proc$issuer_ls180.v:164326$10366 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[63:0]$10367 $4\reg$next[63:0]$10371 - attribute \src "issuer_ls180.v:164327.5-164327.29" - switch \initial - attribute \src "issuer_ls180.v:164327.9-164327.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \nia2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg$next[63:0]$10368 \nia2__data_i - case - assign $1\reg$next[63:0]$10368 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \msr2__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reg$next[63:0]$10369 \msr2__data_i - case - assign $2\reg$next[63:0]$10369 $1\reg$next[63:0]$10368 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \d_wr12__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\reg$next[63:0]$10370 \d_wr12__data_i - case - assign $3\reg$next[63:0]$10370 $2\reg$next[63:0]$10369 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\reg$next[63:0]$10371 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $4\reg$next[63:0]$10371 $3\reg$next[63:0]$10370 - end - sync always - update \reg$next $0\reg$next[63:0]$10367 - end - connect \$1 $not$issuer_ls180.v:164178$10338_Y - connect \$3 $not$issuer_ls180.v:164179$10339_Y -end -attribute \src "issuer_ls180.v:164357.1-164828.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_3" -attribute \generator "nMigen" -module \reg_3 - attribute \src "issuer_ls180.v:164358.7-164358.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:164758.3-164797.6" - wire width 4 $0\r23__data_o$next[3:0]$10445 - attribute \src "issuer_ls180.v:164441.3-164442.39" - wire width 4 $0\r23__data_o[3:0] - attribute \src "issuer_ls180.v:164688.3-164727.6" - wire width 4 $0\r3__data_o$next[3:0]$10431 - attribute \src "issuer_ls180.v:164443.3-164444.37" - wire width 4 $0\r3__data_o[3:0] - attribute \src "issuer_ls180.v:164521.3-164547.6" - wire width 4 $0\reg$next[3:0]$10397 - attribute \src "issuer_ls180.v:164439.3-164440.25" - wire width 4 $0\reg[3:0] - attribute \src "issuer_ls180.v:164451.3-164490.6" - wire width 4 $0\src13__data_o$next[3:0]$10388 - attribute \src "issuer_ls180.v:164449.3-164450.43" - wire width 4 $0\src13__data_o[3:0] - attribute \src "issuer_ls180.v:164548.3-164587.6" - wire width 4 $0\src23__data_o$next[3:0]$10403 - attribute \src "issuer_ls180.v:164447.3-164448.43" - wire width 4 $0\src23__data_o[3:0] - attribute \src "issuer_ls180.v:164618.3-164657.6" - wire width 4 $0\src33__data_o$next[3:0]$10417 - attribute \src "issuer_ls180.v:164445.3-164446.43" - wire width 4 $0\src33__data_o[3:0] - attribute \src "issuer_ls180.v:164728.3-164757.6" - wire $0\wr_detect$10[0:0]$10439 - attribute \src "issuer_ls180.v:164798.3-164827.6" - wire $0\wr_detect$13[0:0]$10453 - attribute \src "issuer_ls180.v:164588.3-164617.6" - wire $0\wr_detect$4[0:0]$10411 - attribute \src "issuer_ls180.v:164658.3-164687.6" - wire $0\wr_detect$7[0:0]$10425 - attribute \src "issuer_ls180.v:164491.3-164520.6" - wire $0\wr_detect[0:0] - attribute \src "issuer_ls180.v:164758.3-164797.6" - wire width 4 $1\r23__data_o$next[3:0]$10446 - attribute \src "issuer_ls180.v:164383.13-164383.31" - wire width 4 $1\r23__data_o[3:0] - attribute \src "issuer_ls180.v:164688.3-164727.6" - wire width 4 $1\r3__data_o$next[3:0]$10432 - attribute \src "issuer_ls180.v:164390.13-164390.30" - wire width 4 $1\r3__data_o[3:0] - attribute \src "issuer_ls180.v:164521.3-164547.6" - wire width 4 $1\reg$next[3:0]$10398 - attribute \src "issuer_ls180.v:164396.13-164396.25" - wire width 4 $1\reg[3:0] - attribute \src "issuer_ls180.v:164451.3-164490.6" - wire width 4 $1\src13__data_o$next[3:0]$10389 - attribute \src "issuer_ls180.v:164401.13-164401.33" - wire width 4 $1\src13__data_o[3:0] - attribute \src "issuer_ls180.v:164548.3-164587.6" - wire width 4 $1\src23__data_o$next[3:0]$10404 - attribute \src "issuer_ls180.v:164408.13-164408.33" - wire width 4 $1\src23__data_o[3:0] - attribute \src "issuer_ls180.v:164618.3-164657.6" - wire width 4 $1\src33__data_o$next[3:0]$10418 - attribute \src "issuer_ls180.v:164415.13-164415.33" - wire width 4 $1\src33__data_o[3:0] - attribute \src "issuer_ls180.v:164728.3-164757.6" - wire $1\wr_detect$10[0:0]$10440 - attribute \src "issuer_ls180.v:164798.3-164827.6" - wire $1\wr_detect$13[0:0]$10454 - attribute \src "issuer_ls180.v:164588.3-164617.6" - wire $1\wr_detect$4[0:0]$10412 - attribute \src "issuer_ls180.v:164658.3-164687.6" - wire $1\wr_detect$7[0:0]$10426 - attribute \src "issuer_ls180.v:164491.3-164520.6" - wire $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:164758.3-164797.6" - wire width 4 $2\r23__data_o$next[3:0]$10447 - attribute \src "issuer_ls180.v:164688.3-164727.6" - wire width 4 $2\r3__data_o$next[3:0]$10433 - attribute \src "issuer_ls180.v:164521.3-164547.6" - wire width 4 $2\reg$next[3:0]$10399 - attribute \src "issuer_ls180.v:164451.3-164490.6" - wire width 4 $2\src13__data_o$next[3:0]$10390 - attribute \src "issuer_ls180.v:164548.3-164587.6" - wire width 4 $2\src23__data_o$next[3:0]$10405 - attribute \src "issuer_ls180.v:164618.3-164657.6" - wire width 4 $2\src33__data_o$next[3:0]$10419 - attribute \src "issuer_ls180.v:164728.3-164757.6" - wire $2\wr_detect$10[0:0]$10441 - attribute \src "issuer_ls180.v:164798.3-164827.6" - wire $2\wr_detect$13[0:0]$10455 - attribute \src "issuer_ls180.v:164588.3-164617.6" - wire $2\wr_detect$4[0:0]$10413 - attribute \src "issuer_ls180.v:164658.3-164687.6" - wire $2\wr_detect$7[0:0]$10427 - attribute \src "issuer_ls180.v:164491.3-164520.6" - wire $2\wr_detect[0:0] - attribute \src "issuer_ls180.v:164758.3-164797.6" - wire width 4 $3\r23__data_o$next[3:0]$10448 - attribute \src "issuer_ls180.v:164688.3-164727.6" - wire width 4 $3\r3__data_o$next[3:0]$10434 - attribute \src "issuer_ls180.v:164521.3-164547.6" - wire width 4 $3\reg$next[3:0]$10400 - attribute \src "issuer_ls180.v:164451.3-164490.6" - wire width 4 $3\src13__data_o$next[3:0]$10391 - attribute \src "issuer_ls180.v:164548.3-164587.6" - wire width 4 $3\src23__data_o$next[3:0]$10406 - attribute \src "issuer_ls180.v:164618.3-164657.6" - wire width 4 $3\src33__data_o$next[3:0]$10420 - attribute \src "issuer_ls180.v:164728.3-164757.6" - wire $3\wr_detect$10[0:0]$10442 - attribute \src "issuer_ls180.v:164798.3-164827.6" - wire $3\wr_detect$13[0:0]$10456 - attribute \src "issuer_ls180.v:164588.3-164617.6" - wire $3\wr_detect$4[0:0]$10414 - attribute \src "issuer_ls180.v:164658.3-164687.6" - wire $3\wr_detect$7[0:0]$10428 - attribute \src "issuer_ls180.v:164491.3-164520.6" - wire $3\wr_detect[0:0] - attribute \src "issuer_ls180.v:164758.3-164797.6" - wire width 4 $4\r23__data_o$next[3:0]$10449 - attribute \src "issuer_ls180.v:164688.3-164727.6" - wire width 4 $4\r3__data_o$next[3:0]$10435 - attribute \src "issuer_ls180.v:164521.3-164547.6" - wire width 4 $4\reg$next[3:0]$10401 - attribute \src "issuer_ls180.v:164451.3-164490.6" - wire width 4 $4\src13__data_o$next[3:0]$10392 - attribute \src "issuer_ls180.v:164548.3-164587.6" - wire width 4 $4\src23__data_o$next[3:0]$10407 - attribute \src "issuer_ls180.v:164618.3-164657.6" - wire width 4 $4\src33__data_o$next[3:0]$10421 - attribute \src "issuer_ls180.v:164728.3-164757.6" - wire $4\wr_detect$10[0:0]$10443 - attribute \src "issuer_ls180.v:164798.3-164827.6" - wire $4\wr_detect$13[0:0]$10457 - attribute \src "issuer_ls180.v:164588.3-164617.6" - wire $4\wr_detect$4[0:0]$10415 - attribute \src "issuer_ls180.v:164658.3-164687.6" - wire $4\wr_detect$7[0:0]$10429 - attribute \src "issuer_ls180.v:164491.3-164520.6" - wire $4\wr_detect[0:0] - attribute \src "issuer_ls180.v:164758.3-164797.6" - wire width 4 $5\r23__data_o$next[3:0]$10450 - attribute \src "issuer_ls180.v:164688.3-164727.6" - wire width 4 $5\r3__data_o$next[3:0]$10436 - attribute \src "issuer_ls180.v:164451.3-164490.6" - wire width 4 $5\src13__data_o$next[3:0]$10393 - attribute \src "issuer_ls180.v:164548.3-164587.6" - wire width 4 $5\src23__data_o$next[3:0]$10408 - attribute \src "issuer_ls180.v:164618.3-164657.6" - wire width 4 $5\src33__data_o$next[3:0]$10422 - attribute \src "issuer_ls180.v:164758.3-164797.6" - wire width 4 $6\r23__data_o$next[3:0]$10451 - attribute \src "issuer_ls180.v:164688.3-164727.6" - wire width 4 $6\r3__data_o$next[3:0]$10437 - attribute \src "issuer_ls180.v:164451.3-164490.6" - wire width 4 $6\src13__data_o$next[3:0]$10394 - attribute \src "issuer_ls180.v:164548.3-164587.6" - wire width 4 $6\src23__data_o$next[3:0]$10409 - attribute \src "issuer_ls180.v:164618.3-164657.6" - wire width 4 $6\src33__data_o$next[3:0]$10423 - attribute \src "issuer_ls180.v:164434.17-164434.104" - wire $not$issuer_ls180.v:164434$10376_Y - attribute \src "issuer_ls180.v:164435.18-164435.105" - wire $not$issuer_ls180.v:164435$10377_Y - attribute \src "issuer_ls180.v:164436.17-164436.100" - wire $not$issuer_ls180.v:164436$10378_Y - attribute \src "issuer_ls180.v:164437.17-164437.103" - wire $not$issuer_ls180.v:164437$10379_Y - attribute \src "issuer_ls180.v:164438.17-164438.103" - wire $not$issuer_ls180.v:164438$10380_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest13__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \dest13__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest23__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \dest23__wen - attribute \src "issuer_ls180.v:164358.7-164358.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 14 \r23__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r23__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \r23__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r3__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 13 \r3__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src13__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src13__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \src13__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src23__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src23__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \src23__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src33__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src33__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \src33__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 16 \w3__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 17 \w3__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:164434$10376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $not$issuer_ls180.v:164434$10376_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:164435$10377 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$13 - connect \Y $not$issuer_ls180.v:164435$10377_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:164436$10378 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$issuer_ls180.v:164436$10378_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:164437$10379 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$issuer_ls180.v:164437$10379_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:164438$10380 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $not$issuer_ls180.v:164438$10380_Y - end - attribute \src "issuer_ls180.v:164358.7-164358.20" - process $proc$issuer_ls180.v:164358$10458 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:164383.13-164383.31" - process $proc$issuer_ls180.v:164383$10459 - assign { } { } - assign $1\r23__data_o[3:0] 4'0000 - sync always - sync init - update \r23__data_o $1\r23__data_o[3:0] - end - attribute \src "issuer_ls180.v:164390.13-164390.30" - process $proc$issuer_ls180.v:164390$10460 - assign { } { } - assign $1\r3__data_o[3:0] 4'0000 - sync always - sync init - update \r3__data_o $1\r3__data_o[3:0] - end - attribute \src "issuer_ls180.v:164396.13-164396.25" - process $proc$issuer_ls180.v:164396$10461 - assign { } { } - assign $1\reg[3:0] 4'0000 - sync always - sync init - update \reg $1\reg[3:0] - end - attribute \src "issuer_ls180.v:164401.13-164401.33" - process $proc$issuer_ls180.v:164401$10462 - assign { } { } - assign $1\src13__data_o[3:0] 4'0000 - sync always - sync init - update \src13__data_o $1\src13__data_o[3:0] - end - attribute \src "issuer_ls180.v:164408.13-164408.33" - process $proc$issuer_ls180.v:164408$10463 - assign { } { } - assign $1\src23__data_o[3:0] 4'0000 - sync always - sync init - update \src23__data_o $1\src23__data_o[3:0] - end - attribute \src "issuer_ls180.v:164415.13-164415.33" - process $proc$issuer_ls180.v:164415$10464 - assign { } { } - assign $1\src33__data_o[3:0] 4'0000 - sync always - sync init - update \src33__data_o $1\src33__data_o[3:0] - end - attribute \src "issuer_ls180.v:164439.3-164440.25" - process $proc$issuer_ls180.v:164439$10381 - assign { } { } - assign $0\reg[3:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[3:0] - end - attribute \src "issuer_ls180.v:164441.3-164442.39" - process $proc$issuer_ls180.v:164441$10382 - assign { } { } - assign $0\r23__data_o[3:0] \r23__data_o$next - sync posedge \coresync_clk - update \r23__data_o $0\r23__data_o[3:0] - end - attribute \src "issuer_ls180.v:164443.3-164444.37" - process $proc$issuer_ls180.v:164443$10383 - assign { } { } - assign $0\r3__data_o[3:0] \r3__data_o$next - sync posedge \coresync_clk - update \r3__data_o $0\r3__data_o[3:0] - end - attribute \src "issuer_ls180.v:164445.3-164446.43" - process $proc$issuer_ls180.v:164445$10384 - assign { } { } - assign $0\src33__data_o[3:0] \src33__data_o$next - sync posedge \coresync_clk - update \src33__data_o $0\src33__data_o[3:0] - end - attribute \src "issuer_ls180.v:164447.3-164448.43" - process $proc$issuer_ls180.v:164447$10385 - assign { } { } - assign $0\src23__data_o[3:0] \src23__data_o$next - sync posedge \coresync_clk - update \src23__data_o $0\src23__data_o[3:0] - end - attribute \src "issuer_ls180.v:164449.3-164450.43" - process $proc$issuer_ls180.v:164449$10386 - assign { } { } - assign $0\src13__data_o[3:0] \src13__data_o$next - sync posedge \coresync_clk - update \src13__data_o $0\src13__data_o[3:0] - end - attribute \src "issuer_ls180.v:164451.3-164490.6" - process $proc$issuer_ls180.v:164451$10387 - assign { } { } - assign { } { } - assign { } { } - assign $0\src13__data_o$next[3:0]$10388 $6\src13__data_o$next[3:0]$10394 - attribute \src "issuer_ls180.v:164452.5-164452.29" - switch \initial - attribute \src "issuer_ls180.v:164452.9-164452.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src13__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src13__data_o$next[3:0]$10389 $5\src13__data_o$next[3:0]$10393 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest13__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src13__data_o$next[3:0]$10390 \dest13__data_i - case - assign $2\src13__data_o$next[3:0]$10390 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest23__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src13__data_o$next[3:0]$10391 \dest23__data_i - case - assign $3\src13__data_o$next[3:0]$10391 $2\src13__data_o$next[3:0]$10390 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w3__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src13__data_o$next[3:0]$10392 \w3__data_i - case - assign $4\src13__data_o$next[3:0]$10392 $3\src13__data_o$next[3:0]$10391 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src13__data_o$next[3:0]$10393 \reg - case - assign $5\src13__data_o$next[3:0]$10393 $4\src13__data_o$next[3:0]$10392 - end - case - assign $1\src13__data_o$next[3:0]$10389 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src13__data_o$next[3:0]$10394 4'0000 - case - assign $6\src13__data_o$next[3:0]$10394 $1\src13__data_o$next[3:0]$10389 - end - sync always - update \src13__data_o$next $0\src13__data_o$next[3:0]$10388 - end - attribute \src "issuer_ls180.v:164491.3-164520.6" - process $proc$issuer_ls180.v:164491$10395 - assign { } { } - assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:164492.5-164492.29" - switch \initial - attribute \src "issuer_ls180.v:164492.9-164492.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src13__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest13__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest23__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w3__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end - case - assign $1\wr_detect[0:0] 1'0 - end - sync always - update \wr_detect $0\wr_detect[0:0] - end - attribute \src "issuer_ls180.v:164521.3-164547.6" - process $proc$issuer_ls180.v:164521$10396 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[3:0]$10397 $4\reg$next[3:0]$10401 - attribute \src "issuer_ls180.v:164522.5-164522.29" - switch \initial - attribute \src "issuer_ls180.v:164522.9-164522.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest13__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg$next[3:0]$10398 \dest13__data_i - case - assign $1\reg$next[3:0]$10398 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest23__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reg$next[3:0]$10399 \dest23__data_i - case - assign $2\reg$next[3:0]$10399 $1\reg$next[3:0]$10398 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w3__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\reg$next[3:0]$10400 \w3__data_i - case - assign $3\reg$next[3:0]$10400 $2\reg$next[3:0]$10399 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\reg$next[3:0]$10401 4'0000 - case - assign $4\reg$next[3:0]$10401 $3\reg$next[3:0]$10400 - end - sync always - update \reg$next $0\reg$next[3:0]$10397 - end - attribute \src "issuer_ls180.v:164548.3-164587.6" - process $proc$issuer_ls180.v:164548$10402 - assign { } { } - assign { } { } - assign { } { } - assign $0\src23__data_o$next[3:0]$10403 $6\src23__data_o$next[3:0]$10409 - attribute \src "issuer_ls180.v:164549.5-164549.29" - switch \initial - attribute \src "issuer_ls180.v:164549.9-164549.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src23__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src23__data_o$next[3:0]$10404 $5\src23__data_o$next[3:0]$10408 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest13__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src23__data_o$next[3:0]$10405 \dest13__data_i - case - assign $2\src23__data_o$next[3:0]$10405 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest23__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src23__data_o$next[3:0]$10406 \dest23__data_i - case - assign $3\src23__data_o$next[3:0]$10406 $2\src23__data_o$next[3:0]$10405 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w3__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src23__data_o$next[3:0]$10407 \w3__data_i - case - assign $4\src23__data_o$next[3:0]$10407 $3\src23__data_o$next[3:0]$10406 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src23__data_o$next[3:0]$10408 \reg - case - assign $5\src23__data_o$next[3:0]$10408 $4\src23__data_o$next[3:0]$10407 - end - case - assign $1\src23__data_o$next[3:0]$10404 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src23__data_o$next[3:0]$10409 4'0000 - case - assign $6\src23__data_o$next[3:0]$10409 $1\src23__data_o$next[3:0]$10404 - end - sync always - update \src23__data_o$next $0\src23__data_o$next[3:0]$10403 - end - attribute \src "issuer_ls180.v:164588.3-164617.6" - process $proc$issuer_ls180.v:164588$10410 - assign { } { } - assign { } { } - assign $0\wr_detect$4[0:0]$10411 $1\wr_detect$4[0:0]$10412 - attribute \src "issuer_ls180.v:164589.5-164589.29" - switch \initial - attribute \src "issuer_ls180.v:164589.9-164589.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src23__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$4[0:0]$10412 $4\wr_detect$4[0:0]$10415 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest13__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$10413 1'1 - case - assign $2\wr_detect$4[0:0]$10413 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest23__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$10414 1'1 - case - assign $3\wr_detect$4[0:0]$10414 $2\wr_detect$4[0:0]$10413 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w3__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$10415 1'1 - case - assign $4\wr_detect$4[0:0]$10415 $3\wr_detect$4[0:0]$10414 - end - case - assign $1\wr_detect$4[0:0]$10412 1'0 - end - sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10411 - end - attribute \src "issuer_ls180.v:164618.3-164657.6" - process $proc$issuer_ls180.v:164618$10416 - assign { } { } - assign { } { } - assign { } { } - assign $0\src33__data_o$next[3:0]$10417 $6\src33__data_o$next[3:0]$10423 - attribute \src "issuer_ls180.v:164619.5-164619.29" - switch \initial - attribute \src "issuer_ls180.v:164619.9-164619.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src33__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src33__data_o$next[3:0]$10418 $5\src33__data_o$next[3:0]$10422 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest13__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src33__data_o$next[3:0]$10419 \dest13__data_i - case - assign $2\src33__data_o$next[3:0]$10419 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest23__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src33__data_o$next[3:0]$10420 \dest23__data_i - case - assign $3\src33__data_o$next[3:0]$10420 $2\src33__data_o$next[3:0]$10419 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w3__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src33__data_o$next[3:0]$10421 \w3__data_i - case - assign $4\src33__data_o$next[3:0]$10421 $3\src33__data_o$next[3:0]$10420 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$6 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src33__data_o$next[3:0]$10422 \reg - case - assign $5\src33__data_o$next[3:0]$10422 $4\src33__data_o$next[3:0]$10421 - end - case - assign $1\src33__data_o$next[3:0]$10418 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src33__data_o$next[3:0]$10423 4'0000 - case - assign $6\src33__data_o$next[3:0]$10423 $1\src33__data_o$next[3:0]$10418 - end - sync always - update \src33__data_o$next $0\src33__data_o$next[3:0]$10417 - end - attribute \src "issuer_ls180.v:164658.3-164687.6" - process $proc$issuer_ls180.v:164658$10424 - assign { } { } - assign { } { } - assign $0\wr_detect$7[0:0]$10425 $1\wr_detect$7[0:0]$10426 - attribute \src "issuer_ls180.v:164659.5-164659.29" - switch \initial - attribute \src "issuer_ls180.v:164659.9-164659.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src33__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$7[0:0]$10426 $4\wr_detect$7[0:0]$10429 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest13__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$7[0:0]$10427 1'1 - case - assign $2\wr_detect$7[0:0]$10427 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest23__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$7[0:0]$10428 1'1 - case - assign $3\wr_detect$7[0:0]$10428 $2\wr_detect$7[0:0]$10427 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w3__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$7[0:0]$10429 1'1 - case - assign $4\wr_detect$7[0:0]$10429 $3\wr_detect$7[0:0]$10428 - end - case - assign $1\wr_detect$7[0:0]$10426 1'0 - end - sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10425 - end - attribute \src "issuer_ls180.v:164688.3-164727.6" - process $proc$issuer_ls180.v:164688$10430 - assign { } { } - assign { } { } - assign { } { } - assign $0\r3__data_o$next[3:0]$10431 $6\r3__data_o$next[3:0]$10437 - attribute \src "issuer_ls180.v:164689.5-164689.29" - switch \initial - attribute \src "issuer_ls180.v:164689.9-164689.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r3__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r3__data_o$next[3:0]$10432 $5\r3__data_o$next[3:0]$10436 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest13__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r3__data_o$next[3:0]$10433 \dest13__data_i - case - assign $2\r3__data_o$next[3:0]$10433 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest23__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r3__data_o$next[3:0]$10434 \dest23__data_i - case - assign $3\r3__data_o$next[3:0]$10434 $2\r3__data_o$next[3:0]$10433 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w3__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r3__data_o$next[3:0]$10435 \w3__data_i - case - assign $4\r3__data_o$next[3:0]$10435 $3\r3__data_o$next[3:0]$10434 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r3__data_o$next[3:0]$10436 \reg - case - assign $5\r3__data_o$next[3:0]$10436 $4\r3__data_o$next[3:0]$10435 - end - case - assign $1\r3__data_o$next[3:0]$10432 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r3__data_o$next[3:0]$10437 4'0000 - case - assign $6\r3__data_o$next[3:0]$10437 $1\r3__data_o$next[3:0]$10432 - end - sync always - update \r3__data_o$next $0\r3__data_o$next[3:0]$10431 - end - attribute \src "issuer_ls180.v:164728.3-164757.6" - process $proc$issuer_ls180.v:164728$10438 - assign { } { } - assign { } { } - assign $0\wr_detect$10[0:0]$10439 $1\wr_detect$10[0:0]$10440 - attribute \src "issuer_ls180.v:164729.5-164729.29" - switch \initial - attribute \src "issuer_ls180.v:164729.9-164729.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r3__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$10[0:0]$10440 $4\wr_detect$10[0:0]$10443 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest13__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$10[0:0]$10441 1'1 - case - assign $2\wr_detect$10[0:0]$10441 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest23__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$10[0:0]$10442 1'1 - case - assign $3\wr_detect$10[0:0]$10442 $2\wr_detect$10[0:0]$10441 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w3__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$10[0:0]$10443 1'1 - case - assign $4\wr_detect$10[0:0]$10443 $3\wr_detect$10[0:0]$10442 - end - case - assign $1\wr_detect$10[0:0]$10440 1'0 - end - sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10439 - end - attribute \src "issuer_ls180.v:164758.3-164797.6" - process $proc$issuer_ls180.v:164758$10444 - assign { } { } - assign { } { } - assign { } { } - assign $0\r23__data_o$next[3:0]$10445 $6\r23__data_o$next[3:0]$10451 - attribute \src "issuer_ls180.v:164759.5-164759.29" - switch \initial - attribute \src "issuer_ls180.v:164759.9-164759.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r23__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r23__data_o$next[3:0]$10446 $5\r23__data_o$next[3:0]$10450 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest13__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r23__data_o$next[3:0]$10447 \dest13__data_i - case - assign $2\r23__data_o$next[3:0]$10447 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest23__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r23__data_o$next[3:0]$10448 \dest23__data_i - case - assign $3\r23__data_o$next[3:0]$10448 $2\r23__data_o$next[3:0]$10447 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w3__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r23__data_o$next[3:0]$10449 \w3__data_i - case - assign $4\r23__data_o$next[3:0]$10449 $3\r23__data_o$next[3:0]$10448 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$12 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r23__data_o$next[3:0]$10450 \reg - case - assign $5\r23__data_o$next[3:0]$10450 $4\r23__data_o$next[3:0]$10449 - end - case - assign $1\r23__data_o$next[3:0]$10446 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r23__data_o$next[3:0]$10451 4'0000 - case - assign $6\r23__data_o$next[3:0]$10451 $1\r23__data_o$next[3:0]$10446 - end - sync always - update \r23__data_o$next $0\r23__data_o$next[3:0]$10445 - end - attribute \src "issuer_ls180.v:164798.3-164827.6" - process $proc$issuer_ls180.v:164798$10452 - assign { } { } - assign { } { } - assign $0\wr_detect$13[0:0]$10453 $1\wr_detect$13[0:0]$10454 - attribute \src "issuer_ls180.v:164799.5-164799.29" - switch \initial - attribute \src "issuer_ls180.v:164799.9-164799.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r23__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$13[0:0]$10454 $4\wr_detect$13[0:0]$10457 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest13__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$13[0:0]$10455 1'1 - case - assign $2\wr_detect$13[0:0]$10455 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest23__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$13[0:0]$10456 1'1 - case - assign $3\wr_detect$13[0:0]$10456 $2\wr_detect$13[0:0]$10455 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w3__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$13[0:0]$10457 1'1 - case - assign $4\wr_detect$13[0:0]$10457 $3\wr_detect$13[0:0]$10456 - end - case - assign $1\wr_detect$13[0:0]$10454 1'0 - end - sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10453 - end - connect \$9 $not$issuer_ls180.v:164434$10376_Y - connect \$12 $not$issuer_ls180.v:164435$10377_Y - connect \$1 $not$issuer_ls180.v:164436$10378_Y - connect \$3 $not$issuer_ls180.v:164437$10379_Y - connect \$6 $not$issuer_ls180.v:164438$10380_Y -end -attribute \src "issuer_ls180.v:164832.1-165051.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.state.reg_3" -attribute \generator "nMigen" -module \reg_3$135 - attribute \src "issuer_ls180.v:164884.3-164923.6" - wire width 64 $0\cia3__data_o$next[63:0]$10471 - attribute \src "issuer_ls180.v:164882.3-164883.41" - wire width 64 $0\cia3__data_o[63:0] - attribute \src "issuer_ls180.v:164833.7-164833.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:164954.3-164993.6" - wire width 64 $0\msr3__data_o$next[63:0]$10480 - attribute \src "issuer_ls180.v:164880.3-164881.41" - wire width 64 $0\msr3__data_o[63:0] - attribute \src "issuer_ls180.v:165024.3-165050.6" - wire width 64 $0\reg$next[63:0]$10494 - attribute \src "issuer_ls180.v:164878.3-164879.25" - wire width 64 $0\reg[63:0] - attribute \src "issuer_ls180.v:164994.3-165023.6" - wire $0\wr_detect$4[0:0]$10488 - attribute \src "issuer_ls180.v:164924.3-164953.6" - wire $0\wr_detect[0:0] - attribute \src "issuer_ls180.v:164884.3-164923.6" - wire width 64 $1\cia3__data_o$next[63:0]$10472 - attribute \src "issuer_ls180.v:164840.14-164840.49" - wire width 64 $1\cia3__data_o[63:0] - attribute \src "issuer_ls180.v:164954.3-164993.6" - wire width 64 $1\msr3__data_o$next[63:0]$10481 - attribute \src "issuer_ls180.v:164857.14-164857.49" - wire width 64 $1\msr3__data_o[63:0] - attribute \src "issuer_ls180.v:165024.3-165050.6" - wire width 64 $1\reg$next[63:0]$10495 - attribute \src "issuer_ls180.v:164869.14-164869.42" - wire width 64 $1\reg[63:0] - attribute \src "issuer_ls180.v:164994.3-165023.6" - wire $1\wr_detect$4[0:0]$10489 - attribute \src "issuer_ls180.v:164924.3-164953.6" - wire $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:164884.3-164923.6" - wire width 64 $2\cia3__data_o$next[63:0]$10473 - attribute \src "issuer_ls180.v:164954.3-164993.6" - wire width 64 $2\msr3__data_o$next[63:0]$10482 - attribute \src "issuer_ls180.v:165024.3-165050.6" - wire width 64 $2\reg$next[63:0]$10496 - attribute \src "issuer_ls180.v:164994.3-165023.6" - wire $2\wr_detect$4[0:0]$10490 - attribute \src "issuer_ls180.v:164924.3-164953.6" - wire $2\wr_detect[0:0] - attribute \src "issuer_ls180.v:164884.3-164923.6" - wire width 64 $3\cia3__data_o$next[63:0]$10474 - attribute \src "issuer_ls180.v:164954.3-164993.6" - wire width 64 $3\msr3__data_o$next[63:0]$10483 - attribute \src "issuer_ls180.v:165024.3-165050.6" - wire width 64 $3\reg$next[63:0]$10497 - attribute \src "issuer_ls180.v:164994.3-165023.6" - wire $3\wr_detect$4[0:0]$10491 - attribute \src "issuer_ls180.v:164924.3-164953.6" - wire $3\wr_detect[0:0] - attribute \src "issuer_ls180.v:164884.3-164923.6" - wire width 64 $4\cia3__data_o$next[63:0]$10475 - attribute \src "issuer_ls180.v:164954.3-164993.6" - wire width 64 $4\msr3__data_o$next[63:0]$10484 - attribute \src "issuer_ls180.v:165024.3-165050.6" - wire width 64 $4\reg$next[63:0]$10498 - attribute \src "issuer_ls180.v:164994.3-165023.6" - wire $4\wr_detect$4[0:0]$10492 - attribute \src "issuer_ls180.v:164924.3-164953.6" - wire $4\wr_detect[0:0] - attribute \src "issuer_ls180.v:164884.3-164923.6" - wire width 64 $5\cia3__data_o$next[63:0]$10476 - attribute \src "issuer_ls180.v:164954.3-164993.6" - wire width 64 $5\msr3__data_o$next[63:0]$10485 - attribute \src "issuer_ls180.v:164884.3-164923.6" - wire width 64 $6\cia3__data_o$next[63:0]$10477 - attribute \src "issuer_ls180.v:164954.3-164993.6" - wire width 64 $6\msr3__data_o$next[63:0]$10486 - attribute \src "issuer_ls180.v:164876.17-164876.100" - wire $not$issuer_ls180.v:164876$10465_Y - attribute \src "issuer_ls180.v:164877.17-164877.103" - wire $not$issuer_ls180.v:164877$10466_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \cia3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \cia3__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \cia3__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 12 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 11 \d_wr13__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \d_wr13__wen - attribute \src "issuer_ls180.v:164833.7-164833.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 9 \msr3__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 5 \msr3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \msr3__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \msr3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \msr3__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 7 \nia3__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \nia3__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:164876$10465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$issuer_ls180.v:164876$10465_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:164877$10466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$issuer_ls180.v:164877$10466_Y - end - attribute \src "issuer_ls180.v:164833.7-164833.20" - process $proc$issuer_ls180.v:164833$10499 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:164840.14-164840.49" - process $proc$issuer_ls180.v:164840$10500 - assign { } { } - assign $1\cia3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \cia3__data_o $1\cia3__data_o[63:0] - end - attribute \src "issuer_ls180.v:164857.14-164857.49" - process $proc$issuer_ls180.v:164857$10501 - assign { } { } - assign $1\msr3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \msr3__data_o $1\msr3__data_o[63:0] - end - attribute \src "issuer_ls180.v:164869.14-164869.42" - process $proc$issuer_ls180.v:164869$10502 - assign { } { } - assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \reg $1\reg[63:0] - end - attribute \src "issuer_ls180.v:164878.3-164879.25" - process $proc$issuer_ls180.v:164878$10467 - assign { } { } - assign $0\reg[63:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[63:0] - end - attribute \src "issuer_ls180.v:164880.3-164881.41" - process $proc$issuer_ls180.v:164880$10468 - assign { } { } - assign $0\msr3__data_o[63:0] \msr3__data_o$next - sync posedge \coresync_clk - update \msr3__data_o $0\msr3__data_o[63:0] - end - attribute \src "issuer_ls180.v:164882.3-164883.41" - process $proc$issuer_ls180.v:164882$10469 - assign { } { } - assign $0\cia3__data_o[63:0] \cia3__data_o$next - sync posedge \coresync_clk - update \cia3__data_o $0\cia3__data_o[63:0] - end - attribute \src "issuer_ls180.v:164884.3-164923.6" - process $proc$issuer_ls180.v:164884$10470 - assign { } { } - assign { } { } - assign { } { } - assign $0\cia3__data_o$next[63:0]$10471 $6\cia3__data_o$next[63:0]$10477 - attribute \src "issuer_ls180.v:164885.5-164885.29" - switch \initial - attribute \src "issuer_ls180.v:164885.9-164885.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cia3__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\cia3__data_o$next[63:0]$10472 $5\cia3__data_o$next[63:0]$10476 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia3__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cia3__data_o$next[63:0]$10473 \nia3__data_i - case - assign $2\cia3__data_o$next[63:0]$10473 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr3__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cia3__data_o$next[63:0]$10474 \msr3__data_i - case - assign $3\cia3__data_o$next[63:0]$10474 $2\cia3__data_o$next[63:0]$10473 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr13__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cia3__data_o$next[63:0]$10475 \d_wr13__data_i - case - assign $4\cia3__data_o$next[63:0]$10475 $3\cia3__data_o$next[63:0]$10474 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\cia3__data_o$next[63:0]$10476 \reg - case - assign $5\cia3__data_o$next[63:0]$10476 $4\cia3__data_o$next[63:0]$10475 - end - case - assign $1\cia3__data_o$next[63:0]$10472 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\cia3__data_o$next[63:0]$10477 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $6\cia3__data_o$next[63:0]$10477 $1\cia3__data_o$next[63:0]$10472 - end - sync always - update \cia3__data_o$next $0\cia3__data_o$next[63:0]$10471 - end - attribute \src "issuer_ls180.v:164924.3-164953.6" - process $proc$issuer_ls180.v:164924$10478 - assign { } { } - assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:164925.5-164925.29" - switch \initial - attribute \src "issuer_ls180.v:164925.9-164925.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cia3__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia3__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr3__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr13__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end - case - assign $1\wr_detect[0:0] 1'0 - end - sync always - update \wr_detect $0\wr_detect[0:0] - end - attribute \src "issuer_ls180.v:164954.3-164993.6" - process $proc$issuer_ls180.v:164954$10479 - assign { } { } - assign { } { } - assign { } { } - assign $0\msr3__data_o$next[63:0]$10480 $6\msr3__data_o$next[63:0]$10486 - attribute \src "issuer_ls180.v:164955.5-164955.29" - switch \initial - attribute \src "issuer_ls180.v:164955.9-164955.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \msr3__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\msr3__data_o$next[63:0]$10481 $5\msr3__data_o$next[63:0]$10485 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia3__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\msr3__data_o$next[63:0]$10482 \nia3__data_i - case - assign $2\msr3__data_o$next[63:0]$10482 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr3__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\msr3__data_o$next[63:0]$10483 \msr3__data_i - case - assign $3\msr3__data_o$next[63:0]$10483 $2\msr3__data_o$next[63:0]$10482 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr13__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\msr3__data_o$next[63:0]$10484 \d_wr13__data_i - case - assign $4\msr3__data_o$next[63:0]$10484 $3\msr3__data_o$next[63:0]$10483 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\msr3__data_o$next[63:0]$10485 \reg - case - assign $5\msr3__data_o$next[63:0]$10485 $4\msr3__data_o$next[63:0]$10484 - end - case - assign $1\msr3__data_o$next[63:0]$10481 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\msr3__data_o$next[63:0]$10486 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $6\msr3__data_o$next[63:0]$10486 $1\msr3__data_o$next[63:0]$10481 - end - sync always - update \msr3__data_o$next $0\msr3__data_o$next[63:0]$10480 - end - attribute \src "issuer_ls180.v:164994.3-165023.6" - process $proc$issuer_ls180.v:164994$10487 - assign { } { } - assign { } { } - assign $0\wr_detect$4[0:0]$10488 $1\wr_detect$4[0:0]$10489 - attribute \src "issuer_ls180.v:164995.5-164995.29" - switch \initial - attribute \src "issuer_ls180.v:164995.9-164995.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \msr3__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$4[0:0]$10489 $4\wr_detect$4[0:0]$10492 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia3__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$10490 1'1 - case - assign $2\wr_detect$4[0:0]$10490 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr3__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$10491 1'1 - case - assign $3\wr_detect$4[0:0]$10491 $2\wr_detect$4[0:0]$10490 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr13__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$10492 1'1 - case - assign $4\wr_detect$4[0:0]$10492 $3\wr_detect$4[0:0]$10491 - end - case - assign $1\wr_detect$4[0:0]$10489 1'0 - end - sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10488 - end - attribute \src "issuer_ls180.v:165024.3-165050.6" - process $proc$issuer_ls180.v:165024$10493 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[63:0]$10494 $4\reg$next[63:0]$10498 - attribute \src "issuer_ls180.v:165025.5-165025.29" - switch \initial - attribute \src "issuer_ls180.v:165025.9-165025.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \nia3__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg$next[63:0]$10495 \nia3__data_i - case - assign $1\reg$next[63:0]$10495 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \msr3__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reg$next[63:0]$10496 \msr3__data_i - case - assign $2\reg$next[63:0]$10496 $1\reg$next[63:0]$10495 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \d_wr13__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\reg$next[63:0]$10497 \d_wr13__data_i - case - assign $3\reg$next[63:0]$10497 $2\reg$next[63:0]$10496 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\reg$next[63:0]$10498 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $4\reg$next[63:0]$10498 $3\reg$next[63:0]$10497 - end - sync always - update \reg$next $0\reg$next[63:0]$10494 - end - connect \$1 $not$issuer_ls180.v:164876$10465_Y - connect \$3 $not$issuer_ls180.v:164877$10466_Y -end -attribute \src "issuer_ls180.v:165055.1-165526.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_4" -attribute \generator "nMigen" -module \reg_4 - attribute \src "issuer_ls180.v:165056.7-165056.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:165456.3-165495.6" - wire width 4 $0\r24__data_o$next[3:0]$10572 - attribute \src "issuer_ls180.v:165139.3-165140.39" - wire width 4 $0\r24__data_o[3:0] - attribute \src "issuer_ls180.v:165386.3-165425.6" - wire width 4 $0\r4__data_o$next[3:0]$10558 - attribute \src "issuer_ls180.v:165141.3-165142.37" - wire width 4 $0\r4__data_o[3:0] - attribute \src "issuer_ls180.v:165219.3-165245.6" - wire width 4 $0\reg$next[3:0]$10524 - attribute \src "issuer_ls180.v:165137.3-165138.25" - wire width 4 $0\reg[3:0] - attribute \src "issuer_ls180.v:165149.3-165188.6" - wire width 4 $0\src14__data_o$next[3:0]$10515 - attribute \src "issuer_ls180.v:165147.3-165148.43" - wire width 4 $0\src14__data_o[3:0] - attribute \src "issuer_ls180.v:165246.3-165285.6" - wire width 4 $0\src24__data_o$next[3:0]$10530 - attribute \src "issuer_ls180.v:165145.3-165146.43" - wire width 4 $0\src24__data_o[3:0] - attribute \src "issuer_ls180.v:165316.3-165355.6" - wire width 4 $0\src34__data_o$next[3:0]$10544 - attribute \src "issuer_ls180.v:165143.3-165144.43" - wire width 4 $0\src34__data_o[3:0] - attribute \src "issuer_ls180.v:165426.3-165455.6" - wire $0\wr_detect$10[0:0]$10566 - attribute \src "issuer_ls180.v:165496.3-165525.6" - wire $0\wr_detect$13[0:0]$10580 - attribute \src "issuer_ls180.v:165286.3-165315.6" - wire $0\wr_detect$4[0:0]$10538 - attribute \src "issuer_ls180.v:165356.3-165385.6" - wire $0\wr_detect$7[0:0]$10552 - attribute \src "issuer_ls180.v:165189.3-165218.6" - wire $0\wr_detect[0:0] - attribute \src "issuer_ls180.v:165456.3-165495.6" - wire width 4 $1\r24__data_o$next[3:0]$10573 - attribute \src "issuer_ls180.v:165081.13-165081.31" - wire width 4 $1\r24__data_o[3:0] - attribute \src "issuer_ls180.v:165386.3-165425.6" - wire width 4 $1\r4__data_o$next[3:0]$10559 - attribute \src "issuer_ls180.v:165088.13-165088.30" - wire width 4 $1\r4__data_o[3:0] - attribute \src "issuer_ls180.v:165219.3-165245.6" - wire width 4 $1\reg$next[3:0]$10525 - attribute \src "issuer_ls180.v:165094.13-165094.25" - wire width 4 $1\reg[3:0] - attribute \src "issuer_ls180.v:165149.3-165188.6" - wire width 4 $1\src14__data_o$next[3:0]$10516 - attribute \src "issuer_ls180.v:165099.13-165099.33" - wire width 4 $1\src14__data_o[3:0] - attribute \src "issuer_ls180.v:165246.3-165285.6" - wire width 4 $1\src24__data_o$next[3:0]$10531 - attribute \src "issuer_ls180.v:165106.13-165106.33" - wire width 4 $1\src24__data_o[3:0] - attribute \src "issuer_ls180.v:165316.3-165355.6" - wire width 4 $1\src34__data_o$next[3:0]$10545 - attribute \src "issuer_ls180.v:165113.13-165113.33" - wire width 4 $1\src34__data_o[3:0] - attribute \src "issuer_ls180.v:165426.3-165455.6" - wire $1\wr_detect$10[0:0]$10567 - attribute \src "issuer_ls180.v:165496.3-165525.6" - wire $1\wr_detect$13[0:0]$10581 - attribute \src "issuer_ls180.v:165286.3-165315.6" - wire $1\wr_detect$4[0:0]$10539 - attribute \src "issuer_ls180.v:165356.3-165385.6" - wire $1\wr_detect$7[0:0]$10553 - attribute \src "issuer_ls180.v:165189.3-165218.6" - wire $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:165456.3-165495.6" - wire width 4 $2\r24__data_o$next[3:0]$10574 - attribute \src "issuer_ls180.v:165386.3-165425.6" - wire width 4 $2\r4__data_o$next[3:0]$10560 - attribute \src "issuer_ls180.v:165219.3-165245.6" - wire width 4 $2\reg$next[3:0]$10526 - attribute \src "issuer_ls180.v:165149.3-165188.6" - wire width 4 $2\src14__data_o$next[3:0]$10517 - attribute \src "issuer_ls180.v:165246.3-165285.6" - wire width 4 $2\src24__data_o$next[3:0]$10532 - attribute \src "issuer_ls180.v:165316.3-165355.6" - wire width 4 $2\src34__data_o$next[3:0]$10546 - attribute \src "issuer_ls180.v:165426.3-165455.6" - wire $2\wr_detect$10[0:0]$10568 - attribute \src "issuer_ls180.v:165496.3-165525.6" - wire $2\wr_detect$13[0:0]$10582 - attribute \src "issuer_ls180.v:165286.3-165315.6" - wire $2\wr_detect$4[0:0]$10540 - attribute \src "issuer_ls180.v:165356.3-165385.6" - wire $2\wr_detect$7[0:0]$10554 - attribute \src "issuer_ls180.v:165189.3-165218.6" - wire $2\wr_detect[0:0] - attribute \src "issuer_ls180.v:165456.3-165495.6" - wire width 4 $3\r24__data_o$next[3:0]$10575 - attribute \src "issuer_ls180.v:165386.3-165425.6" - wire width 4 $3\r4__data_o$next[3:0]$10561 - attribute \src "issuer_ls180.v:165219.3-165245.6" - wire width 4 $3\reg$next[3:0]$10527 - attribute \src "issuer_ls180.v:165149.3-165188.6" - wire width 4 $3\src14__data_o$next[3:0]$10518 - attribute \src "issuer_ls180.v:165246.3-165285.6" - wire width 4 $3\src24__data_o$next[3:0]$10533 - attribute \src "issuer_ls180.v:165316.3-165355.6" - wire width 4 $3\src34__data_o$next[3:0]$10547 - attribute \src "issuer_ls180.v:165426.3-165455.6" - wire $3\wr_detect$10[0:0]$10569 - attribute \src "issuer_ls180.v:165496.3-165525.6" - wire $3\wr_detect$13[0:0]$10583 - attribute \src "issuer_ls180.v:165286.3-165315.6" - wire $3\wr_detect$4[0:0]$10541 - attribute \src "issuer_ls180.v:165356.3-165385.6" - wire $3\wr_detect$7[0:0]$10555 - attribute \src "issuer_ls180.v:165189.3-165218.6" - wire $3\wr_detect[0:0] - attribute \src "issuer_ls180.v:165456.3-165495.6" - wire width 4 $4\r24__data_o$next[3:0]$10576 - attribute \src "issuer_ls180.v:165386.3-165425.6" - wire width 4 $4\r4__data_o$next[3:0]$10562 - attribute \src "issuer_ls180.v:165219.3-165245.6" - wire width 4 $4\reg$next[3:0]$10528 - attribute \src "issuer_ls180.v:165149.3-165188.6" - wire width 4 $4\src14__data_o$next[3:0]$10519 - attribute \src "issuer_ls180.v:165246.3-165285.6" - wire width 4 $4\src24__data_o$next[3:0]$10534 - attribute \src "issuer_ls180.v:165316.3-165355.6" - wire width 4 $4\src34__data_o$next[3:0]$10548 - attribute \src "issuer_ls180.v:165426.3-165455.6" - wire $4\wr_detect$10[0:0]$10570 - attribute \src "issuer_ls180.v:165496.3-165525.6" - wire $4\wr_detect$13[0:0]$10584 - attribute \src "issuer_ls180.v:165286.3-165315.6" - wire $4\wr_detect$4[0:0]$10542 - attribute \src "issuer_ls180.v:165356.3-165385.6" - wire $4\wr_detect$7[0:0]$10556 - attribute \src "issuer_ls180.v:165189.3-165218.6" - wire $4\wr_detect[0:0] - attribute \src "issuer_ls180.v:165456.3-165495.6" - wire width 4 $5\r24__data_o$next[3:0]$10577 - attribute \src "issuer_ls180.v:165386.3-165425.6" - wire width 4 $5\r4__data_o$next[3:0]$10563 - attribute \src "issuer_ls180.v:165149.3-165188.6" - wire width 4 $5\src14__data_o$next[3:0]$10520 - attribute \src "issuer_ls180.v:165246.3-165285.6" - wire width 4 $5\src24__data_o$next[3:0]$10535 - attribute \src "issuer_ls180.v:165316.3-165355.6" - wire width 4 $5\src34__data_o$next[3:0]$10549 - attribute \src "issuer_ls180.v:165456.3-165495.6" - wire width 4 $6\r24__data_o$next[3:0]$10578 - attribute \src "issuer_ls180.v:165386.3-165425.6" - wire width 4 $6\r4__data_o$next[3:0]$10564 - attribute \src "issuer_ls180.v:165149.3-165188.6" - wire width 4 $6\src14__data_o$next[3:0]$10521 - attribute \src "issuer_ls180.v:165246.3-165285.6" - wire width 4 $6\src24__data_o$next[3:0]$10536 - attribute \src "issuer_ls180.v:165316.3-165355.6" - wire width 4 $6\src34__data_o$next[3:0]$10550 - attribute \src "issuer_ls180.v:165132.17-165132.104" - wire $not$issuer_ls180.v:165132$10503_Y - attribute \src "issuer_ls180.v:165133.18-165133.105" - wire $not$issuer_ls180.v:165133$10504_Y - attribute \src "issuer_ls180.v:165134.17-165134.100" - wire $not$issuer_ls180.v:165134$10505_Y - attribute \src "issuer_ls180.v:165135.17-165135.103" - wire $not$issuer_ls180.v:165135$10506_Y - attribute \src "issuer_ls180.v:165136.17-165136.103" - wire $not$issuer_ls180.v:165136$10507_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest14__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \dest14__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest24__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \dest24__wen - attribute \src "issuer_ls180.v:165056.7-165056.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 14 \r24__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r24__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \r24__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r4__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r4__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 13 \r4__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src14__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src14__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \src14__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src24__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src24__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \src24__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src34__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src34__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \src34__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 16 \w4__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 17 \w4__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:165132$10503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $not$issuer_ls180.v:165132$10503_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:165133$10504 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$13 - connect \Y $not$issuer_ls180.v:165133$10504_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:165134$10505 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$issuer_ls180.v:165134$10505_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:165135$10506 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$issuer_ls180.v:165135$10506_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:165136$10507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $not$issuer_ls180.v:165136$10507_Y - end - attribute \src "issuer_ls180.v:165056.7-165056.20" - process $proc$issuer_ls180.v:165056$10585 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:165081.13-165081.31" - process $proc$issuer_ls180.v:165081$10586 - assign { } { } - assign $1\r24__data_o[3:0] 4'0000 - sync always - sync init - update \r24__data_o $1\r24__data_o[3:0] - end - attribute \src "issuer_ls180.v:165088.13-165088.30" - process $proc$issuer_ls180.v:165088$10587 - assign { } { } - assign $1\r4__data_o[3:0] 4'0000 - sync always - sync init - update \r4__data_o $1\r4__data_o[3:0] - end - attribute \src "issuer_ls180.v:165094.13-165094.25" - process $proc$issuer_ls180.v:165094$10588 - assign { } { } - assign $1\reg[3:0] 4'0000 - sync always - sync init - update \reg $1\reg[3:0] - end - attribute \src "issuer_ls180.v:165099.13-165099.33" - process $proc$issuer_ls180.v:165099$10589 - assign { } { } - assign $1\src14__data_o[3:0] 4'0000 - sync always - sync init - update \src14__data_o $1\src14__data_o[3:0] - end - attribute \src "issuer_ls180.v:165106.13-165106.33" - process $proc$issuer_ls180.v:165106$10590 - assign { } { } - assign $1\src24__data_o[3:0] 4'0000 - sync always - sync init - update \src24__data_o $1\src24__data_o[3:0] - end - attribute \src "issuer_ls180.v:165113.13-165113.33" - process $proc$issuer_ls180.v:165113$10591 - assign { } { } - assign $1\src34__data_o[3:0] 4'0000 - sync always - sync init - update \src34__data_o $1\src34__data_o[3:0] - end - attribute \src "issuer_ls180.v:165137.3-165138.25" - process $proc$issuer_ls180.v:165137$10508 - assign { } { } - assign $0\reg[3:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[3:0] - end - attribute \src "issuer_ls180.v:165139.3-165140.39" - process $proc$issuer_ls180.v:165139$10509 - assign { } { } - assign $0\r24__data_o[3:0] \r24__data_o$next - sync posedge \coresync_clk - update \r24__data_o $0\r24__data_o[3:0] - end - attribute \src "issuer_ls180.v:165141.3-165142.37" - process $proc$issuer_ls180.v:165141$10510 - assign { } { } - assign $0\r4__data_o[3:0] \r4__data_o$next - sync posedge \coresync_clk - update \r4__data_o $0\r4__data_o[3:0] - end - attribute \src "issuer_ls180.v:165143.3-165144.43" - process $proc$issuer_ls180.v:165143$10511 - assign { } { } - assign $0\src34__data_o[3:0] \src34__data_o$next - sync posedge \coresync_clk - update \src34__data_o $0\src34__data_o[3:0] - end - attribute \src "issuer_ls180.v:165145.3-165146.43" - process $proc$issuer_ls180.v:165145$10512 - assign { } { } - assign $0\src24__data_o[3:0] \src24__data_o$next - sync posedge \coresync_clk - update \src24__data_o $0\src24__data_o[3:0] - end - attribute \src "issuer_ls180.v:165147.3-165148.43" - process $proc$issuer_ls180.v:165147$10513 - assign { } { } - assign $0\src14__data_o[3:0] \src14__data_o$next - sync posedge \coresync_clk - update \src14__data_o $0\src14__data_o[3:0] - end - attribute \src "issuer_ls180.v:165149.3-165188.6" - process $proc$issuer_ls180.v:165149$10514 - assign { } { } - assign { } { } - assign { } { } - assign $0\src14__data_o$next[3:0]$10515 $6\src14__data_o$next[3:0]$10521 - attribute \src "issuer_ls180.v:165150.5-165150.29" - switch \initial - attribute \src "issuer_ls180.v:165150.9-165150.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src14__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src14__data_o$next[3:0]$10516 $5\src14__data_o$next[3:0]$10520 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest14__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src14__data_o$next[3:0]$10517 \dest14__data_i - case - assign $2\src14__data_o$next[3:0]$10517 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest24__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src14__data_o$next[3:0]$10518 \dest24__data_i - case - assign $3\src14__data_o$next[3:0]$10518 $2\src14__data_o$next[3:0]$10517 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w4__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src14__data_o$next[3:0]$10519 \w4__data_i - case - assign $4\src14__data_o$next[3:0]$10519 $3\src14__data_o$next[3:0]$10518 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src14__data_o$next[3:0]$10520 \reg - case - assign $5\src14__data_o$next[3:0]$10520 $4\src14__data_o$next[3:0]$10519 - end - case - assign $1\src14__data_o$next[3:0]$10516 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src14__data_o$next[3:0]$10521 4'0000 - case - assign $6\src14__data_o$next[3:0]$10521 $1\src14__data_o$next[3:0]$10516 - end - sync always - update \src14__data_o$next $0\src14__data_o$next[3:0]$10515 - end - attribute \src "issuer_ls180.v:165189.3-165218.6" - process $proc$issuer_ls180.v:165189$10522 - assign { } { } - assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:165190.5-165190.29" - switch \initial - attribute \src "issuer_ls180.v:165190.9-165190.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src14__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest14__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest24__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w4__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end - case - assign $1\wr_detect[0:0] 1'0 - end - sync always - update \wr_detect $0\wr_detect[0:0] - end - attribute \src "issuer_ls180.v:165219.3-165245.6" - process $proc$issuer_ls180.v:165219$10523 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[3:0]$10524 $4\reg$next[3:0]$10528 - attribute \src "issuer_ls180.v:165220.5-165220.29" - switch \initial - attribute \src "issuer_ls180.v:165220.9-165220.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest14__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg$next[3:0]$10525 \dest14__data_i - case - assign $1\reg$next[3:0]$10525 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest24__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reg$next[3:0]$10526 \dest24__data_i - case - assign $2\reg$next[3:0]$10526 $1\reg$next[3:0]$10525 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w4__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\reg$next[3:0]$10527 \w4__data_i - case - assign $3\reg$next[3:0]$10527 $2\reg$next[3:0]$10526 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\reg$next[3:0]$10528 4'0000 - case - assign $4\reg$next[3:0]$10528 $3\reg$next[3:0]$10527 - end - sync always - update \reg$next $0\reg$next[3:0]$10524 - end - attribute \src "issuer_ls180.v:165246.3-165285.6" - process $proc$issuer_ls180.v:165246$10529 - assign { } { } - assign { } { } - assign { } { } - assign $0\src24__data_o$next[3:0]$10530 $6\src24__data_o$next[3:0]$10536 - attribute \src "issuer_ls180.v:165247.5-165247.29" - switch \initial - attribute \src "issuer_ls180.v:165247.9-165247.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src24__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src24__data_o$next[3:0]$10531 $5\src24__data_o$next[3:0]$10535 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest14__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src24__data_o$next[3:0]$10532 \dest14__data_i - case - assign $2\src24__data_o$next[3:0]$10532 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest24__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src24__data_o$next[3:0]$10533 \dest24__data_i - case - assign $3\src24__data_o$next[3:0]$10533 $2\src24__data_o$next[3:0]$10532 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w4__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src24__data_o$next[3:0]$10534 \w4__data_i - case - assign $4\src24__data_o$next[3:0]$10534 $3\src24__data_o$next[3:0]$10533 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src24__data_o$next[3:0]$10535 \reg - case - assign $5\src24__data_o$next[3:0]$10535 $4\src24__data_o$next[3:0]$10534 - end - case - assign $1\src24__data_o$next[3:0]$10531 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src24__data_o$next[3:0]$10536 4'0000 - case - assign $6\src24__data_o$next[3:0]$10536 $1\src24__data_o$next[3:0]$10531 - end - sync always - update \src24__data_o$next $0\src24__data_o$next[3:0]$10530 - end - attribute \src "issuer_ls180.v:165286.3-165315.6" - process $proc$issuer_ls180.v:165286$10537 - assign { } { } - assign { } { } - assign $0\wr_detect$4[0:0]$10538 $1\wr_detect$4[0:0]$10539 - attribute \src "issuer_ls180.v:165287.5-165287.29" - switch \initial - attribute \src "issuer_ls180.v:165287.9-165287.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src24__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$4[0:0]$10539 $4\wr_detect$4[0:0]$10542 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest14__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$10540 1'1 - case - assign $2\wr_detect$4[0:0]$10540 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest24__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$10541 1'1 - case - assign $3\wr_detect$4[0:0]$10541 $2\wr_detect$4[0:0]$10540 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w4__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$10542 1'1 - case - assign $4\wr_detect$4[0:0]$10542 $3\wr_detect$4[0:0]$10541 - end - case - assign $1\wr_detect$4[0:0]$10539 1'0 - end - sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10538 - end - attribute \src "issuer_ls180.v:165316.3-165355.6" - process $proc$issuer_ls180.v:165316$10543 - assign { } { } - assign { } { } - assign { } { } - assign $0\src34__data_o$next[3:0]$10544 $6\src34__data_o$next[3:0]$10550 - attribute \src "issuer_ls180.v:165317.5-165317.29" - switch \initial - attribute \src "issuer_ls180.v:165317.9-165317.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src34__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src34__data_o$next[3:0]$10545 $5\src34__data_o$next[3:0]$10549 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest14__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src34__data_o$next[3:0]$10546 \dest14__data_i - case - assign $2\src34__data_o$next[3:0]$10546 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest24__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src34__data_o$next[3:0]$10547 \dest24__data_i - case - assign $3\src34__data_o$next[3:0]$10547 $2\src34__data_o$next[3:0]$10546 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w4__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src34__data_o$next[3:0]$10548 \w4__data_i - case - assign $4\src34__data_o$next[3:0]$10548 $3\src34__data_o$next[3:0]$10547 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$6 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src34__data_o$next[3:0]$10549 \reg - case - assign $5\src34__data_o$next[3:0]$10549 $4\src34__data_o$next[3:0]$10548 - end - case - assign $1\src34__data_o$next[3:0]$10545 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src34__data_o$next[3:0]$10550 4'0000 - case - assign $6\src34__data_o$next[3:0]$10550 $1\src34__data_o$next[3:0]$10545 - end - sync always - update \src34__data_o$next $0\src34__data_o$next[3:0]$10544 - end - attribute \src "issuer_ls180.v:165356.3-165385.6" - process $proc$issuer_ls180.v:165356$10551 - assign { } { } - assign { } { } - assign $0\wr_detect$7[0:0]$10552 $1\wr_detect$7[0:0]$10553 - attribute \src "issuer_ls180.v:165357.5-165357.29" - switch \initial - attribute \src "issuer_ls180.v:165357.9-165357.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src34__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$7[0:0]$10553 $4\wr_detect$7[0:0]$10556 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest14__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$7[0:0]$10554 1'1 - case - assign $2\wr_detect$7[0:0]$10554 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest24__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$7[0:0]$10555 1'1 - case - assign $3\wr_detect$7[0:0]$10555 $2\wr_detect$7[0:0]$10554 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w4__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$7[0:0]$10556 1'1 - case - assign $4\wr_detect$7[0:0]$10556 $3\wr_detect$7[0:0]$10555 - end - case - assign $1\wr_detect$7[0:0]$10553 1'0 - end - sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10552 - end - attribute \src "issuer_ls180.v:165386.3-165425.6" - process $proc$issuer_ls180.v:165386$10557 - assign { } { } - assign { } { } - assign { } { } - assign $0\r4__data_o$next[3:0]$10558 $6\r4__data_o$next[3:0]$10564 - attribute \src "issuer_ls180.v:165387.5-165387.29" - switch \initial - attribute \src "issuer_ls180.v:165387.9-165387.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r4__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r4__data_o$next[3:0]$10559 $5\r4__data_o$next[3:0]$10563 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest14__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r4__data_o$next[3:0]$10560 \dest14__data_i - case - assign $2\r4__data_o$next[3:0]$10560 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest24__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r4__data_o$next[3:0]$10561 \dest24__data_i - case - assign $3\r4__data_o$next[3:0]$10561 $2\r4__data_o$next[3:0]$10560 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w4__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r4__data_o$next[3:0]$10562 \w4__data_i - case - assign $4\r4__data_o$next[3:0]$10562 $3\r4__data_o$next[3:0]$10561 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r4__data_o$next[3:0]$10563 \reg - case - assign $5\r4__data_o$next[3:0]$10563 $4\r4__data_o$next[3:0]$10562 - end - case - assign $1\r4__data_o$next[3:0]$10559 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r4__data_o$next[3:0]$10564 4'0000 - case - assign $6\r4__data_o$next[3:0]$10564 $1\r4__data_o$next[3:0]$10559 - end - sync always - update \r4__data_o$next $0\r4__data_o$next[3:0]$10558 - end - attribute \src "issuer_ls180.v:165426.3-165455.6" - process $proc$issuer_ls180.v:165426$10565 - assign { } { } - assign { } { } - assign $0\wr_detect$10[0:0]$10566 $1\wr_detect$10[0:0]$10567 - attribute \src "issuer_ls180.v:165427.5-165427.29" - switch \initial - attribute \src "issuer_ls180.v:165427.9-165427.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r4__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$10[0:0]$10567 $4\wr_detect$10[0:0]$10570 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest14__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$10[0:0]$10568 1'1 - case - assign $2\wr_detect$10[0:0]$10568 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest24__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$10[0:0]$10569 1'1 - case - assign $3\wr_detect$10[0:0]$10569 $2\wr_detect$10[0:0]$10568 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w4__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$10[0:0]$10570 1'1 - case - assign $4\wr_detect$10[0:0]$10570 $3\wr_detect$10[0:0]$10569 - end - case - assign $1\wr_detect$10[0:0]$10567 1'0 - end - sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10566 - end - attribute \src "issuer_ls180.v:165456.3-165495.6" - process $proc$issuer_ls180.v:165456$10571 - assign { } { } - assign { } { } - assign { } { } - assign $0\r24__data_o$next[3:0]$10572 $6\r24__data_o$next[3:0]$10578 - attribute \src "issuer_ls180.v:165457.5-165457.29" - switch \initial - attribute \src "issuer_ls180.v:165457.9-165457.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r24__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r24__data_o$next[3:0]$10573 $5\r24__data_o$next[3:0]$10577 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest14__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r24__data_o$next[3:0]$10574 \dest14__data_i - case - assign $2\r24__data_o$next[3:0]$10574 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest24__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r24__data_o$next[3:0]$10575 \dest24__data_i - case - assign $3\r24__data_o$next[3:0]$10575 $2\r24__data_o$next[3:0]$10574 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w4__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r24__data_o$next[3:0]$10576 \w4__data_i - case - assign $4\r24__data_o$next[3:0]$10576 $3\r24__data_o$next[3:0]$10575 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$12 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r24__data_o$next[3:0]$10577 \reg - case - assign $5\r24__data_o$next[3:0]$10577 $4\r24__data_o$next[3:0]$10576 - end - case - assign $1\r24__data_o$next[3:0]$10573 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r24__data_o$next[3:0]$10578 4'0000 - case - assign $6\r24__data_o$next[3:0]$10578 $1\r24__data_o$next[3:0]$10573 - end - sync always - update \r24__data_o$next $0\r24__data_o$next[3:0]$10572 - end - attribute \src "issuer_ls180.v:165496.3-165525.6" - process $proc$issuer_ls180.v:165496$10579 - assign { } { } - assign { } { } - assign $0\wr_detect$13[0:0]$10580 $1\wr_detect$13[0:0]$10581 - attribute \src "issuer_ls180.v:165497.5-165497.29" - switch \initial - attribute \src "issuer_ls180.v:165497.9-165497.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r24__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$13[0:0]$10581 $4\wr_detect$13[0:0]$10584 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest14__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$13[0:0]$10582 1'1 - case - assign $2\wr_detect$13[0:0]$10582 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest24__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$13[0:0]$10583 1'1 - case - assign $3\wr_detect$13[0:0]$10583 $2\wr_detect$13[0:0]$10582 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w4__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$13[0:0]$10584 1'1 - case - assign $4\wr_detect$13[0:0]$10584 $3\wr_detect$13[0:0]$10583 - end - case - assign $1\wr_detect$13[0:0]$10581 1'0 - end - sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10580 - end - connect \$9 $not$issuer_ls180.v:165132$10503_Y - connect \$12 $not$issuer_ls180.v:165133$10504_Y - connect \$1 $not$issuer_ls180.v:165134$10505_Y - connect \$3 $not$issuer_ls180.v:165135$10506_Y - connect \$6 $not$issuer_ls180.v:165136$10507_Y -end -attribute \src "issuer_ls180.v:165530.1-166001.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_5" -attribute \generator "nMigen" -module \reg_5 - attribute \src "issuer_ls180.v:165531.7-165531.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:165931.3-165970.6" - wire width 4 $0\r25__data_o$next[3:0]$10661 - attribute \src "issuer_ls180.v:165614.3-165615.39" - wire width 4 $0\r25__data_o[3:0] - attribute \src "issuer_ls180.v:165861.3-165900.6" - wire width 4 $0\r5__data_o$next[3:0]$10647 - attribute \src "issuer_ls180.v:165616.3-165617.37" - wire width 4 $0\r5__data_o[3:0] - attribute \src "issuer_ls180.v:165694.3-165720.6" - wire width 4 $0\reg$next[3:0]$10613 - attribute \src "issuer_ls180.v:165612.3-165613.25" - wire width 4 $0\reg[3:0] - attribute \src "issuer_ls180.v:165624.3-165663.6" - wire width 4 $0\src15__data_o$next[3:0]$10604 - attribute \src "issuer_ls180.v:165622.3-165623.43" - wire width 4 $0\src15__data_o[3:0] - attribute \src "issuer_ls180.v:165721.3-165760.6" - wire width 4 $0\src25__data_o$next[3:0]$10619 - attribute \src "issuer_ls180.v:165620.3-165621.43" - wire width 4 $0\src25__data_o[3:0] - attribute \src "issuer_ls180.v:165791.3-165830.6" - wire width 4 $0\src35__data_o$next[3:0]$10633 - attribute \src "issuer_ls180.v:165618.3-165619.43" - wire width 4 $0\src35__data_o[3:0] - attribute \src "issuer_ls180.v:165901.3-165930.6" - wire $0\wr_detect$10[0:0]$10655 - attribute \src "issuer_ls180.v:165971.3-166000.6" - wire $0\wr_detect$13[0:0]$10669 - attribute \src "issuer_ls180.v:165761.3-165790.6" - wire $0\wr_detect$4[0:0]$10627 - attribute \src "issuer_ls180.v:165831.3-165860.6" - wire $0\wr_detect$7[0:0]$10641 - attribute \src "issuer_ls180.v:165664.3-165693.6" - wire $0\wr_detect[0:0] - attribute \src "issuer_ls180.v:165931.3-165970.6" - wire width 4 $1\r25__data_o$next[3:0]$10662 - attribute \src "issuer_ls180.v:165556.13-165556.31" - wire width 4 $1\r25__data_o[3:0] - attribute \src "issuer_ls180.v:165861.3-165900.6" - wire width 4 $1\r5__data_o$next[3:0]$10648 - attribute \src "issuer_ls180.v:165563.13-165563.30" - wire width 4 $1\r5__data_o[3:0] - attribute \src "issuer_ls180.v:165694.3-165720.6" - wire width 4 $1\reg$next[3:0]$10614 - attribute \src "issuer_ls180.v:165569.13-165569.25" - wire width 4 $1\reg[3:0] - attribute \src "issuer_ls180.v:165624.3-165663.6" - wire width 4 $1\src15__data_o$next[3:0]$10605 - attribute \src "issuer_ls180.v:165574.13-165574.33" - wire width 4 $1\src15__data_o[3:0] - attribute \src "issuer_ls180.v:165721.3-165760.6" - wire width 4 $1\src25__data_o$next[3:0]$10620 - attribute \src "issuer_ls180.v:165581.13-165581.33" - wire width 4 $1\src25__data_o[3:0] - attribute \src "issuer_ls180.v:165791.3-165830.6" - wire width 4 $1\src35__data_o$next[3:0]$10634 - attribute \src "issuer_ls180.v:165588.13-165588.33" - wire width 4 $1\src35__data_o[3:0] - attribute \src "issuer_ls180.v:165901.3-165930.6" - wire $1\wr_detect$10[0:0]$10656 - attribute \src "issuer_ls180.v:165971.3-166000.6" - wire $1\wr_detect$13[0:0]$10670 - attribute \src "issuer_ls180.v:165761.3-165790.6" - wire $1\wr_detect$4[0:0]$10628 - attribute \src "issuer_ls180.v:165831.3-165860.6" - wire $1\wr_detect$7[0:0]$10642 - attribute \src "issuer_ls180.v:165664.3-165693.6" - wire $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:165931.3-165970.6" - wire width 4 $2\r25__data_o$next[3:0]$10663 - attribute \src "issuer_ls180.v:165861.3-165900.6" - wire width 4 $2\r5__data_o$next[3:0]$10649 - attribute \src "issuer_ls180.v:165694.3-165720.6" - wire width 4 $2\reg$next[3:0]$10615 - attribute \src "issuer_ls180.v:165624.3-165663.6" - wire width 4 $2\src15__data_o$next[3:0]$10606 - attribute \src "issuer_ls180.v:165721.3-165760.6" - wire width 4 $2\src25__data_o$next[3:0]$10621 - attribute \src "issuer_ls180.v:165791.3-165830.6" - wire width 4 $2\src35__data_o$next[3:0]$10635 - attribute \src "issuer_ls180.v:165901.3-165930.6" - wire $2\wr_detect$10[0:0]$10657 - attribute \src "issuer_ls180.v:165971.3-166000.6" - wire $2\wr_detect$13[0:0]$10671 - attribute \src "issuer_ls180.v:165761.3-165790.6" - wire $2\wr_detect$4[0:0]$10629 - attribute \src "issuer_ls180.v:165831.3-165860.6" - wire $2\wr_detect$7[0:0]$10643 - attribute \src "issuer_ls180.v:165664.3-165693.6" - wire $2\wr_detect[0:0] - attribute \src "issuer_ls180.v:165931.3-165970.6" - wire width 4 $3\r25__data_o$next[3:0]$10664 - attribute \src "issuer_ls180.v:165861.3-165900.6" - wire width 4 $3\r5__data_o$next[3:0]$10650 - attribute \src "issuer_ls180.v:165694.3-165720.6" - wire width 4 $3\reg$next[3:0]$10616 - attribute \src "issuer_ls180.v:165624.3-165663.6" - wire width 4 $3\src15__data_o$next[3:0]$10607 - attribute \src "issuer_ls180.v:165721.3-165760.6" - wire width 4 $3\src25__data_o$next[3:0]$10622 - attribute \src "issuer_ls180.v:165791.3-165830.6" - wire width 4 $3\src35__data_o$next[3:0]$10636 - attribute \src "issuer_ls180.v:165901.3-165930.6" - wire $3\wr_detect$10[0:0]$10658 - attribute \src "issuer_ls180.v:165971.3-166000.6" - wire $3\wr_detect$13[0:0]$10672 - attribute \src "issuer_ls180.v:165761.3-165790.6" - wire $3\wr_detect$4[0:0]$10630 - attribute \src "issuer_ls180.v:165831.3-165860.6" - wire $3\wr_detect$7[0:0]$10644 - attribute \src "issuer_ls180.v:165664.3-165693.6" - wire $3\wr_detect[0:0] - attribute \src "issuer_ls180.v:165931.3-165970.6" - wire width 4 $4\r25__data_o$next[3:0]$10665 - attribute \src "issuer_ls180.v:165861.3-165900.6" - wire width 4 $4\r5__data_o$next[3:0]$10651 - attribute \src "issuer_ls180.v:165694.3-165720.6" - wire width 4 $4\reg$next[3:0]$10617 - attribute \src "issuer_ls180.v:165624.3-165663.6" - wire width 4 $4\src15__data_o$next[3:0]$10608 - attribute \src "issuer_ls180.v:165721.3-165760.6" - wire width 4 $4\src25__data_o$next[3:0]$10623 - attribute \src "issuer_ls180.v:165791.3-165830.6" - wire width 4 $4\src35__data_o$next[3:0]$10637 - attribute \src "issuer_ls180.v:165901.3-165930.6" - wire $4\wr_detect$10[0:0]$10659 - attribute \src "issuer_ls180.v:165971.3-166000.6" - wire $4\wr_detect$13[0:0]$10673 - attribute \src "issuer_ls180.v:165761.3-165790.6" - wire $4\wr_detect$4[0:0]$10631 - attribute \src "issuer_ls180.v:165831.3-165860.6" - wire $4\wr_detect$7[0:0]$10645 - attribute \src "issuer_ls180.v:165664.3-165693.6" - wire $4\wr_detect[0:0] - attribute \src "issuer_ls180.v:165931.3-165970.6" - wire width 4 $5\r25__data_o$next[3:0]$10666 - attribute \src "issuer_ls180.v:165861.3-165900.6" - wire width 4 $5\r5__data_o$next[3:0]$10652 - attribute \src "issuer_ls180.v:165624.3-165663.6" - wire width 4 $5\src15__data_o$next[3:0]$10609 - attribute \src "issuer_ls180.v:165721.3-165760.6" - wire width 4 $5\src25__data_o$next[3:0]$10624 - attribute \src "issuer_ls180.v:165791.3-165830.6" - wire width 4 $5\src35__data_o$next[3:0]$10638 - attribute \src "issuer_ls180.v:165931.3-165970.6" - wire width 4 $6\r25__data_o$next[3:0]$10667 - attribute \src "issuer_ls180.v:165861.3-165900.6" - wire width 4 $6\r5__data_o$next[3:0]$10653 - attribute \src "issuer_ls180.v:165624.3-165663.6" - wire width 4 $6\src15__data_o$next[3:0]$10610 - attribute \src "issuer_ls180.v:165721.3-165760.6" - wire width 4 $6\src25__data_o$next[3:0]$10625 - attribute \src "issuer_ls180.v:165791.3-165830.6" - wire width 4 $6\src35__data_o$next[3:0]$10639 - attribute \src "issuer_ls180.v:165607.17-165607.104" - wire $not$issuer_ls180.v:165607$10592_Y - attribute \src "issuer_ls180.v:165608.18-165608.105" - wire $not$issuer_ls180.v:165608$10593_Y - attribute \src "issuer_ls180.v:165609.17-165609.100" - wire $not$issuer_ls180.v:165609$10594_Y - attribute \src "issuer_ls180.v:165610.17-165610.103" - wire $not$issuer_ls180.v:165610$10595_Y - attribute \src "issuer_ls180.v:165611.17-165611.103" - wire $not$issuer_ls180.v:165611$10596_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest15__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \dest15__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest25__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \dest25__wen - attribute \src "issuer_ls180.v:165531.7-165531.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 14 \r25__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r25__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \r25__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r5__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r5__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 13 \r5__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src15__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src15__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \src15__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src25__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src25__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \src25__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src35__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src35__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \src35__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 16 \w5__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 17 \w5__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:165607$10592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $not$issuer_ls180.v:165607$10592_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:165608$10593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$13 - connect \Y $not$issuer_ls180.v:165608$10593_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:165609$10594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$issuer_ls180.v:165609$10594_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:165610$10595 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$issuer_ls180.v:165610$10595_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:165611$10596 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $not$issuer_ls180.v:165611$10596_Y - end - attribute \src "issuer_ls180.v:165531.7-165531.20" - process $proc$issuer_ls180.v:165531$10674 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:165556.13-165556.31" - process $proc$issuer_ls180.v:165556$10675 - assign { } { } - assign $1\r25__data_o[3:0] 4'0000 - sync always - sync init - update \r25__data_o $1\r25__data_o[3:0] - end - attribute \src "issuer_ls180.v:165563.13-165563.30" - process $proc$issuer_ls180.v:165563$10676 - assign { } { } - assign $1\r5__data_o[3:0] 4'0000 - sync always - sync init - update \r5__data_o $1\r5__data_o[3:0] - end - attribute \src "issuer_ls180.v:165569.13-165569.25" - process $proc$issuer_ls180.v:165569$10677 - assign { } { } - assign $1\reg[3:0] 4'0000 - sync always - sync init - update \reg $1\reg[3:0] - end - attribute \src "issuer_ls180.v:165574.13-165574.33" - process $proc$issuer_ls180.v:165574$10678 - assign { } { } - assign $1\src15__data_o[3:0] 4'0000 - sync always - sync init - update \src15__data_o $1\src15__data_o[3:0] - end - attribute \src "issuer_ls180.v:165581.13-165581.33" - process $proc$issuer_ls180.v:165581$10679 - assign { } { } - assign $1\src25__data_o[3:0] 4'0000 - sync always - sync init - update \src25__data_o $1\src25__data_o[3:0] - end - attribute \src "issuer_ls180.v:165588.13-165588.33" - process $proc$issuer_ls180.v:165588$10680 - assign { } { } - assign $1\src35__data_o[3:0] 4'0000 - sync always - sync init - update \src35__data_o $1\src35__data_o[3:0] - end - attribute \src "issuer_ls180.v:165612.3-165613.25" - process $proc$issuer_ls180.v:165612$10597 - assign { } { } - assign $0\reg[3:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[3:0] - end - attribute \src "issuer_ls180.v:165614.3-165615.39" - process $proc$issuer_ls180.v:165614$10598 - assign { } { } - assign $0\r25__data_o[3:0] \r25__data_o$next - sync posedge \coresync_clk - update \r25__data_o $0\r25__data_o[3:0] - end - attribute \src "issuer_ls180.v:165616.3-165617.37" - process $proc$issuer_ls180.v:165616$10599 - assign { } { } - assign $0\r5__data_o[3:0] \r5__data_o$next - sync posedge \coresync_clk - update \r5__data_o $0\r5__data_o[3:0] - end - attribute \src "issuer_ls180.v:165618.3-165619.43" - process $proc$issuer_ls180.v:165618$10600 - assign { } { } - assign $0\src35__data_o[3:0] \src35__data_o$next - sync posedge \coresync_clk - update \src35__data_o $0\src35__data_o[3:0] - end - attribute \src "issuer_ls180.v:165620.3-165621.43" - process $proc$issuer_ls180.v:165620$10601 - assign { } { } - assign $0\src25__data_o[3:0] \src25__data_o$next - sync posedge \coresync_clk - update \src25__data_o $0\src25__data_o[3:0] - end - attribute \src "issuer_ls180.v:165622.3-165623.43" - process $proc$issuer_ls180.v:165622$10602 - assign { } { } - assign $0\src15__data_o[3:0] \src15__data_o$next - sync posedge \coresync_clk - update \src15__data_o $0\src15__data_o[3:0] - end - attribute \src "issuer_ls180.v:165624.3-165663.6" - process $proc$issuer_ls180.v:165624$10603 - assign { } { } - assign { } { } - assign { } { } - assign $0\src15__data_o$next[3:0]$10604 $6\src15__data_o$next[3:0]$10610 - attribute \src "issuer_ls180.v:165625.5-165625.29" - switch \initial - attribute \src "issuer_ls180.v:165625.9-165625.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src15__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src15__data_o$next[3:0]$10605 $5\src15__data_o$next[3:0]$10609 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest15__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src15__data_o$next[3:0]$10606 \dest15__data_i - case - assign $2\src15__data_o$next[3:0]$10606 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest25__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src15__data_o$next[3:0]$10607 \dest25__data_i - case - assign $3\src15__data_o$next[3:0]$10607 $2\src15__data_o$next[3:0]$10606 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w5__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src15__data_o$next[3:0]$10608 \w5__data_i - case - assign $4\src15__data_o$next[3:0]$10608 $3\src15__data_o$next[3:0]$10607 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src15__data_o$next[3:0]$10609 \reg - case - assign $5\src15__data_o$next[3:0]$10609 $4\src15__data_o$next[3:0]$10608 - end - case - assign $1\src15__data_o$next[3:0]$10605 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src15__data_o$next[3:0]$10610 4'0000 - case - assign $6\src15__data_o$next[3:0]$10610 $1\src15__data_o$next[3:0]$10605 - end - sync always - update \src15__data_o$next $0\src15__data_o$next[3:0]$10604 - end - attribute \src "issuer_ls180.v:165664.3-165693.6" - process $proc$issuer_ls180.v:165664$10611 - assign { } { } - assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:165665.5-165665.29" - switch \initial - attribute \src "issuer_ls180.v:165665.9-165665.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src15__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest15__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest25__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w5__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end - case - assign $1\wr_detect[0:0] 1'0 - end - sync always - update \wr_detect $0\wr_detect[0:0] - end - attribute \src "issuer_ls180.v:165694.3-165720.6" - process $proc$issuer_ls180.v:165694$10612 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[3:0]$10613 $4\reg$next[3:0]$10617 - attribute \src "issuer_ls180.v:165695.5-165695.29" - switch \initial - attribute \src "issuer_ls180.v:165695.9-165695.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest15__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg$next[3:0]$10614 \dest15__data_i - case - assign $1\reg$next[3:0]$10614 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest25__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reg$next[3:0]$10615 \dest25__data_i - case - assign $2\reg$next[3:0]$10615 $1\reg$next[3:0]$10614 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w5__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\reg$next[3:0]$10616 \w5__data_i - case - assign $3\reg$next[3:0]$10616 $2\reg$next[3:0]$10615 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\reg$next[3:0]$10617 4'0000 - case - assign $4\reg$next[3:0]$10617 $3\reg$next[3:0]$10616 - end - sync always - update \reg$next $0\reg$next[3:0]$10613 - end - attribute \src "issuer_ls180.v:165721.3-165760.6" - process $proc$issuer_ls180.v:165721$10618 - assign { } { } - assign { } { } - assign { } { } - assign $0\src25__data_o$next[3:0]$10619 $6\src25__data_o$next[3:0]$10625 - attribute \src "issuer_ls180.v:165722.5-165722.29" - switch \initial - attribute \src "issuer_ls180.v:165722.9-165722.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src25__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src25__data_o$next[3:0]$10620 $5\src25__data_o$next[3:0]$10624 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest15__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src25__data_o$next[3:0]$10621 \dest15__data_i - case - assign $2\src25__data_o$next[3:0]$10621 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest25__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src25__data_o$next[3:0]$10622 \dest25__data_i - case - assign $3\src25__data_o$next[3:0]$10622 $2\src25__data_o$next[3:0]$10621 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w5__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src25__data_o$next[3:0]$10623 \w5__data_i - case - assign $4\src25__data_o$next[3:0]$10623 $3\src25__data_o$next[3:0]$10622 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src25__data_o$next[3:0]$10624 \reg - case - assign $5\src25__data_o$next[3:0]$10624 $4\src25__data_o$next[3:0]$10623 - end - case - assign $1\src25__data_o$next[3:0]$10620 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src25__data_o$next[3:0]$10625 4'0000 - case - assign $6\src25__data_o$next[3:0]$10625 $1\src25__data_o$next[3:0]$10620 - end - sync always - update \src25__data_o$next $0\src25__data_o$next[3:0]$10619 - end - attribute \src "issuer_ls180.v:165761.3-165790.6" - process $proc$issuer_ls180.v:165761$10626 - assign { } { } - assign { } { } - assign $0\wr_detect$4[0:0]$10627 $1\wr_detect$4[0:0]$10628 - attribute \src "issuer_ls180.v:165762.5-165762.29" - switch \initial - attribute \src "issuer_ls180.v:165762.9-165762.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src25__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$4[0:0]$10628 $4\wr_detect$4[0:0]$10631 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest15__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$10629 1'1 - case - assign $2\wr_detect$4[0:0]$10629 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest25__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$10630 1'1 - case - assign $3\wr_detect$4[0:0]$10630 $2\wr_detect$4[0:0]$10629 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w5__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$10631 1'1 - case - assign $4\wr_detect$4[0:0]$10631 $3\wr_detect$4[0:0]$10630 - end - case - assign $1\wr_detect$4[0:0]$10628 1'0 - end - sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10627 - end - attribute \src "issuer_ls180.v:165791.3-165830.6" - process $proc$issuer_ls180.v:165791$10632 - assign { } { } - assign { } { } - assign { } { } - assign $0\src35__data_o$next[3:0]$10633 $6\src35__data_o$next[3:0]$10639 - attribute \src "issuer_ls180.v:165792.5-165792.29" - switch \initial - attribute \src "issuer_ls180.v:165792.9-165792.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src35__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src35__data_o$next[3:0]$10634 $5\src35__data_o$next[3:0]$10638 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest15__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src35__data_o$next[3:0]$10635 \dest15__data_i - case - assign $2\src35__data_o$next[3:0]$10635 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest25__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src35__data_o$next[3:0]$10636 \dest25__data_i - case - assign $3\src35__data_o$next[3:0]$10636 $2\src35__data_o$next[3:0]$10635 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w5__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src35__data_o$next[3:0]$10637 \w5__data_i - case - assign $4\src35__data_o$next[3:0]$10637 $3\src35__data_o$next[3:0]$10636 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$6 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src35__data_o$next[3:0]$10638 \reg - case - assign $5\src35__data_o$next[3:0]$10638 $4\src35__data_o$next[3:0]$10637 - end - case - assign $1\src35__data_o$next[3:0]$10634 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src35__data_o$next[3:0]$10639 4'0000 - case - assign $6\src35__data_o$next[3:0]$10639 $1\src35__data_o$next[3:0]$10634 - end - sync always - update \src35__data_o$next $0\src35__data_o$next[3:0]$10633 - end - attribute \src "issuer_ls180.v:165831.3-165860.6" - process $proc$issuer_ls180.v:165831$10640 - assign { } { } - assign { } { } - assign $0\wr_detect$7[0:0]$10641 $1\wr_detect$7[0:0]$10642 - attribute \src "issuer_ls180.v:165832.5-165832.29" - switch \initial - attribute \src "issuer_ls180.v:165832.9-165832.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src35__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$7[0:0]$10642 $4\wr_detect$7[0:0]$10645 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest15__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$7[0:0]$10643 1'1 - case - assign $2\wr_detect$7[0:0]$10643 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest25__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$7[0:0]$10644 1'1 - case - assign $3\wr_detect$7[0:0]$10644 $2\wr_detect$7[0:0]$10643 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w5__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$7[0:0]$10645 1'1 - case - assign $4\wr_detect$7[0:0]$10645 $3\wr_detect$7[0:0]$10644 - end - case - assign $1\wr_detect$7[0:0]$10642 1'0 - end - sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10641 - end - attribute \src "issuer_ls180.v:165861.3-165900.6" - process $proc$issuer_ls180.v:165861$10646 - assign { } { } - assign { } { } - assign { } { } - assign $0\r5__data_o$next[3:0]$10647 $6\r5__data_o$next[3:0]$10653 - attribute \src "issuer_ls180.v:165862.5-165862.29" - switch \initial - attribute \src "issuer_ls180.v:165862.9-165862.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r5__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r5__data_o$next[3:0]$10648 $5\r5__data_o$next[3:0]$10652 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest15__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r5__data_o$next[3:0]$10649 \dest15__data_i - case - assign $2\r5__data_o$next[3:0]$10649 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest25__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r5__data_o$next[3:0]$10650 \dest25__data_i - case - assign $3\r5__data_o$next[3:0]$10650 $2\r5__data_o$next[3:0]$10649 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w5__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r5__data_o$next[3:0]$10651 \w5__data_i - case - assign $4\r5__data_o$next[3:0]$10651 $3\r5__data_o$next[3:0]$10650 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r5__data_o$next[3:0]$10652 \reg - case - assign $5\r5__data_o$next[3:0]$10652 $4\r5__data_o$next[3:0]$10651 - end - case - assign $1\r5__data_o$next[3:0]$10648 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r5__data_o$next[3:0]$10653 4'0000 - case - assign $6\r5__data_o$next[3:0]$10653 $1\r5__data_o$next[3:0]$10648 - end - sync always - update \r5__data_o$next $0\r5__data_o$next[3:0]$10647 - end - attribute \src "issuer_ls180.v:165901.3-165930.6" - process $proc$issuer_ls180.v:165901$10654 - assign { } { } - assign { } { } - assign $0\wr_detect$10[0:0]$10655 $1\wr_detect$10[0:0]$10656 - attribute \src "issuer_ls180.v:165902.5-165902.29" - switch \initial - attribute \src "issuer_ls180.v:165902.9-165902.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r5__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$10[0:0]$10656 $4\wr_detect$10[0:0]$10659 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest15__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$10[0:0]$10657 1'1 - case - assign $2\wr_detect$10[0:0]$10657 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest25__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$10[0:0]$10658 1'1 - case - assign $3\wr_detect$10[0:0]$10658 $2\wr_detect$10[0:0]$10657 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w5__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$10[0:0]$10659 1'1 - case - assign $4\wr_detect$10[0:0]$10659 $3\wr_detect$10[0:0]$10658 - end - case - assign $1\wr_detect$10[0:0]$10656 1'0 - end - sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10655 - end - attribute \src "issuer_ls180.v:165931.3-165970.6" - process $proc$issuer_ls180.v:165931$10660 - assign { } { } - assign { } { } - assign { } { } - assign $0\r25__data_o$next[3:0]$10661 $6\r25__data_o$next[3:0]$10667 - attribute \src "issuer_ls180.v:165932.5-165932.29" - switch \initial - attribute \src "issuer_ls180.v:165932.9-165932.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r25__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r25__data_o$next[3:0]$10662 $5\r25__data_o$next[3:0]$10666 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest15__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r25__data_o$next[3:0]$10663 \dest15__data_i - case - assign $2\r25__data_o$next[3:0]$10663 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest25__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r25__data_o$next[3:0]$10664 \dest25__data_i - case - assign $3\r25__data_o$next[3:0]$10664 $2\r25__data_o$next[3:0]$10663 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w5__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r25__data_o$next[3:0]$10665 \w5__data_i - case - assign $4\r25__data_o$next[3:0]$10665 $3\r25__data_o$next[3:0]$10664 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$12 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r25__data_o$next[3:0]$10666 \reg - case - assign $5\r25__data_o$next[3:0]$10666 $4\r25__data_o$next[3:0]$10665 - end - case - assign $1\r25__data_o$next[3:0]$10662 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r25__data_o$next[3:0]$10667 4'0000 - case - assign $6\r25__data_o$next[3:0]$10667 $1\r25__data_o$next[3:0]$10662 - end - sync always - update \r25__data_o$next $0\r25__data_o$next[3:0]$10661 - end - attribute \src "issuer_ls180.v:165971.3-166000.6" - process $proc$issuer_ls180.v:165971$10668 - assign { } { } - assign { } { } - assign $0\wr_detect$13[0:0]$10669 $1\wr_detect$13[0:0]$10670 - attribute \src "issuer_ls180.v:165972.5-165972.29" - switch \initial - attribute \src "issuer_ls180.v:165972.9-165972.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r25__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$13[0:0]$10670 $4\wr_detect$13[0:0]$10673 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest15__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$13[0:0]$10671 1'1 - case - assign $2\wr_detect$13[0:0]$10671 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest25__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$13[0:0]$10672 1'1 - case - assign $3\wr_detect$13[0:0]$10672 $2\wr_detect$13[0:0]$10671 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w5__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$13[0:0]$10673 1'1 - case - assign $4\wr_detect$13[0:0]$10673 $3\wr_detect$13[0:0]$10672 - end - case - assign $1\wr_detect$13[0:0]$10670 1'0 - end - sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10669 - end - connect \$9 $not$issuer_ls180.v:165607$10592_Y - connect \$12 $not$issuer_ls180.v:165608$10593_Y - connect \$1 $not$issuer_ls180.v:165609$10594_Y - connect \$3 $not$issuer_ls180.v:165610$10595_Y - connect \$6 $not$issuer_ls180.v:165611$10596_Y -end -attribute \src "issuer_ls180.v:166005.1-166476.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_6" -attribute \generator "nMigen" -module \reg_6 - attribute \src "issuer_ls180.v:166006.7-166006.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:166406.3-166445.6" - wire width 4 $0\r26__data_o$next[3:0]$10750 - attribute \src "issuer_ls180.v:166089.3-166090.39" - wire width 4 $0\r26__data_o[3:0] - attribute \src "issuer_ls180.v:166336.3-166375.6" - wire width 4 $0\r6__data_o$next[3:0]$10736 - attribute \src "issuer_ls180.v:166091.3-166092.37" - wire width 4 $0\r6__data_o[3:0] - attribute \src "issuer_ls180.v:166169.3-166195.6" - wire width 4 $0\reg$next[3:0]$10702 - attribute \src "issuer_ls180.v:166087.3-166088.25" - wire width 4 $0\reg[3:0] - attribute \src "issuer_ls180.v:166099.3-166138.6" - wire width 4 $0\src16__data_o$next[3:0]$10693 - attribute \src "issuer_ls180.v:166097.3-166098.43" - wire width 4 $0\src16__data_o[3:0] - attribute \src "issuer_ls180.v:166196.3-166235.6" - wire width 4 $0\src26__data_o$next[3:0]$10708 - attribute \src "issuer_ls180.v:166095.3-166096.43" - wire width 4 $0\src26__data_o[3:0] - attribute \src "issuer_ls180.v:166266.3-166305.6" - wire width 4 $0\src36__data_o$next[3:0]$10722 - attribute \src "issuer_ls180.v:166093.3-166094.43" - wire width 4 $0\src36__data_o[3:0] - attribute \src "issuer_ls180.v:166376.3-166405.6" - wire $0\wr_detect$10[0:0]$10744 - attribute \src "issuer_ls180.v:166446.3-166475.6" - wire $0\wr_detect$13[0:0]$10758 - attribute \src "issuer_ls180.v:166236.3-166265.6" - wire $0\wr_detect$4[0:0]$10716 - attribute \src "issuer_ls180.v:166306.3-166335.6" - wire $0\wr_detect$7[0:0]$10730 - attribute \src "issuer_ls180.v:166139.3-166168.6" - wire $0\wr_detect[0:0] - attribute \src "issuer_ls180.v:166406.3-166445.6" - wire width 4 $1\r26__data_o$next[3:0]$10751 - attribute \src "issuer_ls180.v:166031.13-166031.31" - wire width 4 $1\r26__data_o[3:0] - attribute \src "issuer_ls180.v:166336.3-166375.6" - wire width 4 $1\r6__data_o$next[3:0]$10737 - attribute \src "issuer_ls180.v:166038.13-166038.30" - wire width 4 $1\r6__data_o[3:0] - attribute \src "issuer_ls180.v:166169.3-166195.6" - wire width 4 $1\reg$next[3:0]$10703 - attribute \src "issuer_ls180.v:166044.13-166044.25" - wire width 4 $1\reg[3:0] - attribute \src "issuer_ls180.v:166099.3-166138.6" - wire width 4 $1\src16__data_o$next[3:0]$10694 - attribute \src "issuer_ls180.v:166049.13-166049.33" - wire width 4 $1\src16__data_o[3:0] - attribute \src "issuer_ls180.v:166196.3-166235.6" - wire width 4 $1\src26__data_o$next[3:0]$10709 - attribute \src "issuer_ls180.v:166056.13-166056.33" - wire width 4 $1\src26__data_o[3:0] - attribute \src "issuer_ls180.v:166266.3-166305.6" - wire width 4 $1\src36__data_o$next[3:0]$10723 - attribute \src "issuer_ls180.v:166063.13-166063.33" - wire width 4 $1\src36__data_o[3:0] - attribute \src "issuer_ls180.v:166376.3-166405.6" - wire $1\wr_detect$10[0:0]$10745 - attribute \src "issuer_ls180.v:166446.3-166475.6" - wire $1\wr_detect$13[0:0]$10759 - attribute \src "issuer_ls180.v:166236.3-166265.6" - wire $1\wr_detect$4[0:0]$10717 - attribute \src "issuer_ls180.v:166306.3-166335.6" - wire $1\wr_detect$7[0:0]$10731 - attribute \src "issuer_ls180.v:166139.3-166168.6" - wire $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:166406.3-166445.6" - wire width 4 $2\r26__data_o$next[3:0]$10752 - attribute \src "issuer_ls180.v:166336.3-166375.6" - wire width 4 $2\r6__data_o$next[3:0]$10738 - attribute \src "issuer_ls180.v:166169.3-166195.6" - wire width 4 $2\reg$next[3:0]$10704 - attribute \src "issuer_ls180.v:166099.3-166138.6" - wire width 4 $2\src16__data_o$next[3:0]$10695 - attribute \src "issuer_ls180.v:166196.3-166235.6" - wire width 4 $2\src26__data_o$next[3:0]$10710 - attribute \src "issuer_ls180.v:166266.3-166305.6" - wire width 4 $2\src36__data_o$next[3:0]$10724 - attribute \src "issuer_ls180.v:166376.3-166405.6" - wire $2\wr_detect$10[0:0]$10746 - attribute \src "issuer_ls180.v:166446.3-166475.6" - wire $2\wr_detect$13[0:0]$10760 - attribute \src "issuer_ls180.v:166236.3-166265.6" - wire $2\wr_detect$4[0:0]$10718 - attribute \src "issuer_ls180.v:166306.3-166335.6" - wire $2\wr_detect$7[0:0]$10732 - attribute \src "issuer_ls180.v:166139.3-166168.6" - wire $2\wr_detect[0:0] - attribute \src "issuer_ls180.v:166406.3-166445.6" - wire width 4 $3\r26__data_o$next[3:0]$10753 - attribute \src "issuer_ls180.v:166336.3-166375.6" - wire width 4 $3\r6__data_o$next[3:0]$10739 - attribute \src "issuer_ls180.v:166169.3-166195.6" - wire width 4 $3\reg$next[3:0]$10705 - attribute \src "issuer_ls180.v:166099.3-166138.6" - wire width 4 $3\src16__data_o$next[3:0]$10696 - attribute \src "issuer_ls180.v:166196.3-166235.6" - wire width 4 $3\src26__data_o$next[3:0]$10711 - attribute \src "issuer_ls180.v:166266.3-166305.6" - wire width 4 $3\src36__data_o$next[3:0]$10725 - attribute \src "issuer_ls180.v:166376.3-166405.6" - wire $3\wr_detect$10[0:0]$10747 - attribute \src "issuer_ls180.v:166446.3-166475.6" - wire $3\wr_detect$13[0:0]$10761 - attribute \src "issuer_ls180.v:166236.3-166265.6" - wire $3\wr_detect$4[0:0]$10719 - attribute \src "issuer_ls180.v:166306.3-166335.6" - wire $3\wr_detect$7[0:0]$10733 - attribute \src "issuer_ls180.v:166139.3-166168.6" - wire $3\wr_detect[0:0] - attribute \src "issuer_ls180.v:166406.3-166445.6" - wire width 4 $4\r26__data_o$next[3:0]$10754 - attribute \src "issuer_ls180.v:166336.3-166375.6" - wire width 4 $4\r6__data_o$next[3:0]$10740 - attribute \src "issuer_ls180.v:166169.3-166195.6" - wire width 4 $4\reg$next[3:0]$10706 - attribute \src "issuer_ls180.v:166099.3-166138.6" - wire width 4 $4\src16__data_o$next[3:0]$10697 - attribute \src "issuer_ls180.v:166196.3-166235.6" - wire width 4 $4\src26__data_o$next[3:0]$10712 - attribute \src "issuer_ls180.v:166266.3-166305.6" - wire width 4 $4\src36__data_o$next[3:0]$10726 - attribute \src "issuer_ls180.v:166376.3-166405.6" - wire $4\wr_detect$10[0:0]$10748 - attribute \src "issuer_ls180.v:166446.3-166475.6" - wire $4\wr_detect$13[0:0]$10762 - attribute \src "issuer_ls180.v:166236.3-166265.6" - wire $4\wr_detect$4[0:0]$10720 - attribute \src "issuer_ls180.v:166306.3-166335.6" - wire $4\wr_detect$7[0:0]$10734 - attribute \src "issuer_ls180.v:166139.3-166168.6" - wire $4\wr_detect[0:0] - attribute \src "issuer_ls180.v:166406.3-166445.6" - wire width 4 $5\r26__data_o$next[3:0]$10755 - attribute \src "issuer_ls180.v:166336.3-166375.6" - wire width 4 $5\r6__data_o$next[3:0]$10741 - attribute \src "issuer_ls180.v:166099.3-166138.6" - wire width 4 $5\src16__data_o$next[3:0]$10698 - attribute \src "issuer_ls180.v:166196.3-166235.6" - wire width 4 $5\src26__data_o$next[3:0]$10713 - attribute \src "issuer_ls180.v:166266.3-166305.6" - wire width 4 $5\src36__data_o$next[3:0]$10727 - attribute \src "issuer_ls180.v:166406.3-166445.6" - wire width 4 $6\r26__data_o$next[3:0]$10756 - attribute \src "issuer_ls180.v:166336.3-166375.6" - wire width 4 $6\r6__data_o$next[3:0]$10742 - attribute \src "issuer_ls180.v:166099.3-166138.6" - wire width 4 $6\src16__data_o$next[3:0]$10699 - attribute \src "issuer_ls180.v:166196.3-166235.6" - wire width 4 $6\src26__data_o$next[3:0]$10714 - attribute \src "issuer_ls180.v:166266.3-166305.6" - wire width 4 $6\src36__data_o$next[3:0]$10728 - attribute \src "issuer_ls180.v:166082.17-166082.104" - wire $not$issuer_ls180.v:166082$10681_Y - attribute \src "issuer_ls180.v:166083.18-166083.105" - wire $not$issuer_ls180.v:166083$10682_Y - attribute \src "issuer_ls180.v:166084.17-166084.100" - wire $not$issuer_ls180.v:166084$10683_Y - attribute \src "issuer_ls180.v:166085.17-166085.103" - wire $not$issuer_ls180.v:166085$10684_Y - attribute \src "issuer_ls180.v:166086.17-166086.103" - wire $not$issuer_ls180.v:166086$10685_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest16__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \dest16__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest26__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \dest26__wen - attribute \src "issuer_ls180.v:166006.7-166006.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 14 \r26__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r26__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \r26__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r6__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r6__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 13 \r6__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src16__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src16__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \src16__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src26__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src26__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \src26__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src36__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src36__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \src36__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 16 \w6__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 17 \w6__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:166082$10681 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $not$issuer_ls180.v:166082$10681_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:166083$10682 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$13 - connect \Y $not$issuer_ls180.v:166083$10682_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:166084$10683 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$issuer_ls180.v:166084$10683_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:166085$10684 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$issuer_ls180.v:166085$10684_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:166086$10685 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $not$issuer_ls180.v:166086$10685_Y - end - attribute \src "issuer_ls180.v:166006.7-166006.20" - process $proc$issuer_ls180.v:166006$10763 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:166031.13-166031.31" - process $proc$issuer_ls180.v:166031$10764 - assign { } { } - assign $1\r26__data_o[3:0] 4'0000 - sync always - sync init - update \r26__data_o $1\r26__data_o[3:0] - end - attribute \src "issuer_ls180.v:166038.13-166038.30" - process $proc$issuer_ls180.v:166038$10765 - assign { } { } - assign $1\r6__data_o[3:0] 4'0000 - sync always - sync init - update \r6__data_o $1\r6__data_o[3:0] - end - attribute \src "issuer_ls180.v:166044.13-166044.25" - process $proc$issuer_ls180.v:166044$10766 - assign { } { } - assign $1\reg[3:0] 4'0000 - sync always - sync init - update \reg $1\reg[3:0] - end - attribute \src "issuer_ls180.v:166049.13-166049.33" - process $proc$issuer_ls180.v:166049$10767 - assign { } { } - assign $1\src16__data_o[3:0] 4'0000 - sync always - sync init - update \src16__data_o $1\src16__data_o[3:0] - end - attribute \src "issuer_ls180.v:166056.13-166056.33" - process $proc$issuer_ls180.v:166056$10768 - assign { } { } - assign $1\src26__data_o[3:0] 4'0000 - sync always - sync init - update \src26__data_o $1\src26__data_o[3:0] - end - attribute \src "issuer_ls180.v:166063.13-166063.33" - process $proc$issuer_ls180.v:166063$10769 - assign { } { } - assign $1\src36__data_o[3:0] 4'0000 - sync always - sync init - update \src36__data_o $1\src36__data_o[3:0] - end - attribute \src "issuer_ls180.v:166087.3-166088.25" - process $proc$issuer_ls180.v:166087$10686 - assign { } { } - assign $0\reg[3:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[3:0] - end - attribute \src "issuer_ls180.v:166089.3-166090.39" - process $proc$issuer_ls180.v:166089$10687 - assign { } { } - assign $0\r26__data_o[3:0] \r26__data_o$next - sync posedge \coresync_clk - update \r26__data_o $0\r26__data_o[3:0] - end - attribute \src "issuer_ls180.v:166091.3-166092.37" - process $proc$issuer_ls180.v:166091$10688 - assign { } { } - assign $0\r6__data_o[3:0] \r6__data_o$next - sync posedge \coresync_clk - update \r6__data_o $0\r6__data_o[3:0] - end - attribute \src "issuer_ls180.v:166093.3-166094.43" - process $proc$issuer_ls180.v:166093$10689 - assign { } { } - assign $0\src36__data_o[3:0] \src36__data_o$next - sync posedge \coresync_clk - update \src36__data_o $0\src36__data_o[3:0] - end - attribute \src "issuer_ls180.v:166095.3-166096.43" - process $proc$issuer_ls180.v:166095$10690 - assign { } { } - assign $0\src26__data_o[3:0] \src26__data_o$next - sync posedge \coresync_clk - update \src26__data_o $0\src26__data_o[3:0] - end - attribute \src "issuer_ls180.v:166097.3-166098.43" - process $proc$issuer_ls180.v:166097$10691 - assign { } { } - assign $0\src16__data_o[3:0] \src16__data_o$next - sync posedge \coresync_clk - update \src16__data_o $0\src16__data_o[3:0] - end - attribute \src "issuer_ls180.v:166099.3-166138.6" - process $proc$issuer_ls180.v:166099$10692 - assign { } { } - assign { } { } - assign { } { } - assign $0\src16__data_o$next[3:0]$10693 $6\src16__data_o$next[3:0]$10699 - attribute \src "issuer_ls180.v:166100.5-166100.29" - switch \initial - attribute \src "issuer_ls180.v:166100.9-166100.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src16__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src16__data_o$next[3:0]$10694 $5\src16__data_o$next[3:0]$10698 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest16__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src16__data_o$next[3:0]$10695 \dest16__data_i - case - assign $2\src16__data_o$next[3:0]$10695 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest26__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src16__data_o$next[3:0]$10696 \dest26__data_i - case - assign $3\src16__data_o$next[3:0]$10696 $2\src16__data_o$next[3:0]$10695 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w6__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src16__data_o$next[3:0]$10697 \w6__data_i - case - assign $4\src16__data_o$next[3:0]$10697 $3\src16__data_o$next[3:0]$10696 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src16__data_o$next[3:0]$10698 \reg - case - assign $5\src16__data_o$next[3:0]$10698 $4\src16__data_o$next[3:0]$10697 - end - case - assign $1\src16__data_o$next[3:0]$10694 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src16__data_o$next[3:0]$10699 4'0000 - case - assign $6\src16__data_o$next[3:0]$10699 $1\src16__data_o$next[3:0]$10694 - end - sync always - update \src16__data_o$next $0\src16__data_o$next[3:0]$10693 - end - attribute \src "issuer_ls180.v:166139.3-166168.6" - process $proc$issuer_ls180.v:166139$10700 - assign { } { } - assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:166140.5-166140.29" - switch \initial - attribute \src "issuer_ls180.v:166140.9-166140.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src16__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest16__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest26__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w6__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end - case - assign $1\wr_detect[0:0] 1'0 - end - sync always - update \wr_detect $0\wr_detect[0:0] - end - attribute \src "issuer_ls180.v:166169.3-166195.6" - process $proc$issuer_ls180.v:166169$10701 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[3:0]$10702 $4\reg$next[3:0]$10706 - attribute \src "issuer_ls180.v:166170.5-166170.29" - switch \initial - attribute \src "issuer_ls180.v:166170.9-166170.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest16__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg$next[3:0]$10703 \dest16__data_i - case - assign $1\reg$next[3:0]$10703 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest26__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reg$next[3:0]$10704 \dest26__data_i - case - assign $2\reg$next[3:0]$10704 $1\reg$next[3:0]$10703 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w6__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\reg$next[3:0]$10705 \w6__data_i - case - assign $3\reg$next[3:0]$10705 $2\reg$next[3:0]$10704 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\reg$next[3:0]$10706 4'0000 - case - assign $4\reg$next[3:0]$10706 $3\reg$next[3:0]$10705 - end - sync always - update \reg$next $0\reg$next[3:0]$10702 - end - attribute \src "issuer_ls180.v:166196.3-166235.6" - process $proc$issuer_ls180.v:166196$10707 - assign { } { } - assign { } { } - assign { } { } - assign $0\src26__data_o$next[3:0]$10708 $6\src26__data_o$next[3:0]$10714 - attribute \src "issuer_ls180.v:166197.5-166197.29" - switch \initial - attribute \src "issuer_ls180.v:166197.9-166197.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src26__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src26__data_o$next[3:0]$10709 $5\src26__data_o$next[3:0]$10713 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest16__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src26__data_o$next[3:0]$10710 \dest16__data_i - case - assign $2\src26__data_o$next[3:0]$10710 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest26__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src26__data_o$next[3:0]$10711 \dest26__data_i - case - assign $3\src26__data_o$next[3:0]$10711 $2\src26__data_o$next[3:0]$10710 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w6__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src26__data_o$next[3:0]$10712 \w6__data_i - case - assign $4\src26__data_o$next[3:0]$10712 $3\src26__data_o$next[3:0]$10711 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src26__data_o$next[3:0]$10713 \reg - case - assign $5\src26__data_o$next[3:0]$10713 $4\src26__data_o$next[3:0]$10712 - end - case - assign $1\src26__data_o$next[3:0]$10709 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src26__data_o$next[3:0]$10714 4'0000 - case - assign $6\src26__data_o$next[3:0]$10714 $1\src26__data_o$next[3:0]$10709 - end - sync always - update \src26__data_o$next $0\src26__data_o$next[3:0]$10708 - end - attribute \src "issuer_ls180.v:166236.3-166265.6" - process $proc$issuer_ls180.v:166236$10715 - assign { } { } - assign { } { } - assign $0\wr_detect$4[0:0]$10716 $1\wr_detect$4[0:0]$10717 - attribute \src "issuer_ls180.v:166237.5-166237.29" - switch \initial - attribute \src "issuer_ls180.v:166237.9-166237.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src26__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$4[0:0]$10717 $4\wr_detect$4[0:0]$10720 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest16__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$10718 1'1 - case - assign $2\wr_detect$4[0:0]$10718 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest26__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$10719 1'1 - case - assign $3\wr_detect$4[0:0]$10719 $2\wr_detect$4[0:0]$10718 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w6__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$10720 1'1 - case - assign $4\wr_detect$4[0:0]$10720 $3\wr_detect$4[0:0]$10719 - end - case - assign $1\wr_detect$4[0:0]$10717 1'0 - end - sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10716 - end - attribute \src "issuer_ls180.v:166266.3-166305.6" - process $proc$issuer_ls180.v:166266$10721 - assign { } { } - assign { } { } - assign { } { } - assign $0\src36__data_o$next[3:0]$10722 $6\src36__data_o$next[3:0]$10728 - attribute \src "issuer_ls180.v:166267.5-166267.29" - switch \initial - attribute \src "issuer_ls180.v:166267.9-166267.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src36__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src36__data_o$next[3:0]$10723 $5\src36__data_o$next[3:0]$10727 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest16__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src36__data_o$next[3:0]$10724 \dest16__data_i - case - assign $2\src36__data_o$next[3:0]$10724 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest26__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src36__data_o$next[3:0]$10725 \dest26__data_i - case - assign $3\src36__data_o$next[3:0]$10725 $2\src36__data_o$next[3:0]$10724 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w6__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src36__data_o$next[3:0]$10726 \w6__data_i - case - assign $4\src36__data_o$next[3:0]$10726 $3\src36__data_o$next[3:0]$10725 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$6 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src36__data_o$next[3:0]$10727 \reg - case - assign $5\src36__data_o$next[3:0]$10727 $4\src36__data_o$next[3:0]$10726 - end - case - assign $1\src36__data_o$next[3:0]$10723 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src36__data_o$next[3:0]$10728 4'0000 - case - assign $6\src36__data_o$next[3:0]$10728 $1\src36__data_o$next[3:0]$10723 - end - sync always - update \src36__data_o$next $0\src36__data_o$next[3:0]$10722 - end - attribute \src "issuer_ls180.v:166306.3-166335.6" - process $proc$issuer_ls180.v:166306$10729 - assign { } { } - assign { } { } - assign $0\wr_detect$7[0:0]$10730 $1\wr_detect$7[0:0]$10731 - attribute \src "issuer_ls180.v:166307.5-166307.29" - switch \initial - attribute \src "issuer_ls180.v:166307.9-166307.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src36__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$7[0:0]$10731 $4\wr_detect$7[0:0]$10734 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest16__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$7[0:0]$10732 1'1 - case - assign $2\wr_detect$7[0:0]$10732 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest26__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$7[0:0]$10733 1'1 - case - assign $3\wr_detect$7[0:0]$10733 $2\wr_detect$7[0:0]$10732 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w6__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$7[0:0]$10734 1'1 - case - assign $4\wr_detect$7[0:0]$10734 $3\wr_detect$7[0:0]$10733 - end - case - assign $1\wr_detect$7[0:0]$10731 1'0 - end - sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10730 - end - attribute \src "issuer_ls180.v:166336.3-166375.6" - process $proc$issuer_ls180.v:166336$10735 - assign { } { } - assign { } { } - assign { } { } - assign $0\r6__data_o$next[3:0]$10736 $6\r6__data_o$next[3:0]$10742 - attribute \src "issuer_ls180.v:166337.5-166337.29" - switch \initial - attribute \src "issuer_ls180.v:166337.9-166337.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r6__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r6__data_o$next[3:0]$10737 $5\r6__data_o$next[3:0]$10741 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest16__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r6__data_o$next[3:0]$10738 \dest16__data_i - case - assign $2\r6__data_o$next[3:0]$10738 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest26__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r6__data_o$next[3:0]$10739 \dest26__data_i - case - assign $3\r6__data_o$next[3:0]$10739 $2\r6__data_o$next[3:0]$10738 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w6__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r6__data_o$next[3:0]$10740 \w6__data_i - case - assign $4\r6__data_o$next[3:0]$10740 $3\r6__data_o$next[3:0]$10739 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r6__data_o$next[3:0]$10741 \reg - case - assign $5\r6__data_o$next[3:0]$10741 $4\r6__data_o$next[3:0]$10740 - end - case - assign $1\r6__data_o$next[3:0]$10737 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r6__data_o$next[3:0]$10742 4'0000 - case - assign $6\r6__data_o$next[3:0]$10742 $1\r6__data_o$next[3:0]$10737 - end - sync always - update \r6__data_o$next $0\r6__data_o$next[3:0]$10736 - end - attribute \src "issuer_ls180.v:166376.3-166405.6" - process $proc$issuer_ls180.v:166376$10743 - assign { } { } - assign { } { } - assign $0\wr_detect$10[0:0]$10744 $1\wr_detect$10[0:0]$10745 - attribute \src "issuer_ls180.v:166377.5-166377.29" - switch \initial - attribute \src "issuer_ls180.v:166377.9-166377.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r6__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$10[0:0]$10745 $4\wr_detect$10[0:0]$10748 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest16__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$10[0:0]$10746 1'1 - case - assign $2\wr_detect$10[0:0]$10746 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest26__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$10[0:0]$10747 1'1 - case - assign $3\wr_detect$10[0:0]$10747 $2\wr_detect$10[0:0]$10746 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w6__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$10[0:0]$10748 1'1 - case - assign $4\wr_detect$10[0:0]$10748 $3\wr_detect$10[0:0]$10747 - end - case - assign $1\wr_detect$10[0:0]$10745 1'0 - end - sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10744 - end - attribute \src "issuer_ls180.v:166406.3-166445.6" - process $proc$issuer_ls180.v:166406$10749 - assign { } { } - assign { } { } - assign { } { } - assign $0\r26__data_o$next[3:0]$10750 $6\r26__data_o$next[3:0]$10756 - attribute \src "issuer_ls180.v:166407.5-166407.29" - switch \initial - attribute \src "issuer_ls180.v:166407.9-166407.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r26__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r26__data_o$next[3:0]$10751 $5\r26__data_o$next[3:0]$10755 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest16__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r26__data_o$next[3:0]$10752 \dest16__data_i - case - assign $2\r26__data_o$next[3:0]$10752 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest26__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r26__data_o$next[3:0]$10753 \dest26__data_i - case - assign $3\r26__data_o$next[3:0]$10753 $2\r26__data_o$next[3:0]$10752 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w6__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r26__data_o$next[3:0]$10754 \w6__data_i - case - assign $4\r26__data_o$next[3:0]$10754 $3\r26__data_o$next[3:0]$10753 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$12 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r26__data_o$next[3:0]$10755 \reg - case - assign $5\r26__data_o$next[3:0]$10755 $4\r26__data_o$next[3:0]$10754 - end - case - assign $1\r26__data_o$next[3:0]$10751 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r26__data_o$next[3:0]$10756 4'0000 - case - assign $6\r26__data_o$next[3:0]$10756 $1\r26__data_o$next[3:0]$10751 - end - sync always - update \r26__data_o$next $0\r26__data_o$next[3:0]$10750 - end - attribute \src "issuer_ls180.v:166446.3-166475.6" - process $proc$issuer_ls180.v:166446$10757 - assign { } { } - assign { } { } - assign $0\wr_detect$13[0:0]$10758 $1\wr_detect$13[0:0]$10759 - attribute \src "issuer_ls180.v:166447.5-166447.29" - switch \initial - attribute \src "issuer_ls180.v:166447.9-166447.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r26__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$13[0:0]$10759 $4\wr_detect$13[0:0]$10762 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest16__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$13[0:0]$10760 1'1 - case - assign $2\wr_detect$13[0:0]$10760 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest26__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$13[0:0]$10761 1'1 - case - assign $3\wr_detect$13[0:0]$10761 $2\wr_detect$13[0:0]$10760 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w6__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$13[0:0]$10762 1'1 - case - assign $4\wr_detect$13[0:0]$10762 $3\wr_detect$13[0:0]$10761 - end - case - assign $1\wr_detect$13[0:0]$10759 1'0 - end - sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10758 - end - connect \$9 $not$issuer_ls180.v:166082$10681_Y - connect \$12 $not$issuer_ls180.v:166083$10682_Y - connect \$1 $not$issuer_ls180.v:166084$10683_Y - connect \$3 $not$issuer_ls180.v:166085$10684_Y - connect \$6 $not$issuer_ls180.v:166086$10685_Y -end -attribute \src "issuer_ls180.v:166480.1-166951.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_7" -attribute \generator "nMigen" -module \reg_7 - attribute \src "issuer_ls180.v:166481.7-166481.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:166881.3-166920.6" - wire width 4 $0\r27__data_o$next[3:0]$10839 - attribute \src "issuer_ls180.v:166564.3-166565.39" - wire width 4 $0\r27__data_o[3:0] - attribute \src "issuer_ls180.v:166811.3-166850.6" - wire width 4 $0\r7__data_o$next[3:0]$10825 - attribute \src "issuer_ls180.v:166566.3-166567.37" - wire width 4 $0\r7__data_o[3:0] - attribute \src "issuer_ls180.v:166644.3-166670.6" - wire width 4 $0\reg$next[3:0]$10791 - attribute \src "issuer_ls180.v:166562.3-166563.25" - wire width 4 $0\reg[3:0] - attribute \src "issuer_ls180.v:166574.3-166613.6" - wire width 4 $0\src17__data_o$next[3:0]$10782 - attribute \src "issuer_ls180.v:166572.3-166573.43" - wire width 4 $0\src17__data_o[3:0] - attribute \src "issuer_ls180.v:166671.3-166710.6" - wire width 4 $0\src27__data_o$next[3:0]$10797 - attribute \src "issuer_ls180.v:166570.3-166571.43" - wire width 4 $0\src27__data_o[3:0] - attribute \src "issuer_ls180.v:166741.3-166780.6" - wire width 4 $0\src37__data_o$next[3:0]$10811 - attribute \src "issuer_ls180.v:166568.3-166569.43" - wire width 4 $0\src37__data_o[3:0] - attribute \src "issuer_ls180.v:166851.3-166880.6" - wire $0\wr_detect$10[0:0]$10833 - attribute \src "issuer_ls180.v:166921.3-166950.6" - wire $0\wr_detect$13[0:0]$10847 - attribute \src "issuer_ls180.v:166711.3-166740.6" - wire $0\wr_detect$4[0:0]$10805 - attribute \src "issuer_ls180.v:166781.3-166810.6" - wire $0\wr_detect$7[0:0]$10819 - attribute \src "issuer_ls180.v:166614.3-166643.6" - wire $0\wr_detect[0:0] - attribute \src "issuer_ls180.v:166881.3-166920.6" - wire width 4 $1\r27__data_o$next[3:0]$10840 - attribute \src "issuer_ls180.v:166506.13-166506.31" - wire width 4 $1\r27__data_o[3:0] - attribute \src "issuer_ls180.v:166811.3-166850.6" - wire width 4 $1\r7__data_o$next[3:0]$10826 - attribute \src "issuer_ls180.v:166513.13-166513.30" - wire width 4 $1\r7__data_o[3:0] - attribute \src "issuer_ls180.v:166644.3-166670.6" - wire width 4 $1\reg$next[3:0]$10792 - attribute \src "issuer_ls180.v:166519.13-166519.25" - wire width 4 $1\reg[3:0] - attribute \src "issuer_ls180.v:166574.3-166613.6" - wire width 4 $1\src17__data_o$next[3:0]$10783 - attribute \src "issuer_ls180.v:166524.13-166524.33" - wire width 4 $1\src17__data_o[3:0] - attribute \src "issuer_ls180.v:166671.3-166710.6" - wire width 4 $1\src27__data_o$next[3:0]$10798 - attribute \src "issuer_ls180.v:166531.13-166531.33" - wire width 4 $1\src27__data_o[3:0] - attribute \src "issuer_ls180.v:166741.3-166780.6" - wire width 4 $1\src37__data_o$next[3:0]$10812 - attribute \src "issuer_ls180.v:166538.13-166538.33" - wire width 4 $1\src37__data_o[3:0] - attribute \src "issuer_ls180.v:166851.3-166880.6" - wire $1\wr_detect$10[0:0]$10834 - attribute \src "issuer_ls180.v:166921.3-166950.6" - wire $1\wr_detect$13[0:0]$10848 - attribute \src "issuer_ls180.v:166711.3-166740.6" - wire $1\wr_detect$4[0:0]$10806 - attribute \src "issuer_ls180.v:166781.3-166810.6" - wire $1\wr_detect$7[0:0]$10820 - attribute \src "issuer_ls180.v:166614.3-166643.6" - wire $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:166881.3-166920.6" - wire width 4 $2\r27__data_o$next[3:0]$10841 - attribute \src "issuer_ls180.v:166811.3-166850.6" - wire width 4 $2\r7__data_o$next[3:0]$10827 - attribute \src "issuer_ls180.v:166644.3-166670.6" - wire width 4 $2\reg$next[3:0]$10793 - attribute \src "issuer_ls180.v:166574.3-166613.6" - wire width 4 $2\src17__data_o$next[3:0]$10784 - attribute \src "issuer_ls180.v:166671.3-166710.6" - wire width 4 $2\src27__data_o$next[3:0]$10799 - attribute \src "issuer_ls180.v:166741.3-166780.6" - wire width 4 $2\src37__data_o$next[3:0]$10813 - attribute \src "issuer_ls180.v:166851.3-166880.6" - wire $2\wr_detect$10[0:0]$10835 - attribute \src "issuer_ls180.v:166921.3-166950.6" - wire $2\wr_detect$13[0:0]$10849 - attribute \src "issuer_ls180.v:166711.3-166740.6" - wire $2\wr_detect$4[0:0]$10807 - attribute \src "issuer_ls180.v:166781.3-166810.6" - wire $2\wr_detect$7[0:0]$10821 - attribute \src "issuer_ls180.v:166614.3-166643.6" - wire $2\wr_detect[0:0] - attribute \src "issuer_ls180.v:166881.3-166920.6" - wire width 4 $3\r27__data_o$next[3:0]$10842 - attribute \src "issuer_ls180.v:166811.3-166850.6" - wire width 4 $3\r7__data_o$next[3:0]$10828 - attribute \src "issuer_ls180.v:166644.3-166670.6" - wire width 4 $3\reg$next[3:0]$10794 - attribute \src "issuer_ls180.v:166574.3-166613.6" - wire width 4 $3\src17__data_o$next[3:0]$10785 - attribute \src "issuer_ls180.v:166671.3-166710.6" - wire width 4 $3\src27__data_o$next[3:0]$10800 - attribute \src "issuer_ls180.v:166741.3-166780.6" - wire width 4 $3\src37__data_o$next[3:0]$10814 - attribute \src "issuer_ls180.v:166851.3-166880.6" - wire $3\wr_detect$10[0:0]$10836 - attribute \src "issuer_ls180.v:166921.3-166950.6" - wire $3\wr_detect$13[0:0]$10850 - attribute \src "issuer_ls180.v:166711.3-166740.6" - wire $3\wr_detect$4[0:0]$10808 - attribute \src "issuer_ls180.v:166781.3-166810.6" - wire $3\wr_detect$7[0:0]$10822 - attribute \src "issuer_ls180.v:166614.3-166643.6" - wire $3\wr_detect[0:0] - attribute \src "issuer_ls180.v:166881.3-166920.6" - wire width 4 $4\r27__data_o$next[3:0]$10843 - attribute \src "issuer_ls180.v:166811.3-166850.6" - wire width 4 $4\r7__data_o$next[3:0]$10829 - attribute \src "issuer_ls180.v:166644.3-166670.6" - wire width 4 $4\reg$next[3:0]$10795 - attribute \src "issuer_ls180.v:166574.3-166613.6" - wire width 4 $4\src17__data_o$next[3:0]$10786 - attribute \src "issuer_ls180.v:166671.3-166710.6" - wire width 4 $4\src27__data_o$next[3:0]$10801 - attribute \src "issuer_ls180.v:166741.3-166780.6" - wire width 4 $4\src37__data_o$next[3:0]$10815 - attribute \src "issuer_ls180.v:166851.3-166880.6" - wire $4\wr_detect$10[0:0]$10837 - attribute \src "issuer_ls180.v:166921.3-166950.6" - wire $4\wr_detect$13[0:0]$10851 - attribute \src "issuer_ls180.v:166711.3-166740.6" - wire $4\wr_detect$4[0:0]$10809 - attribute \src "issuer_ls180.v:166781.3-166810.6" - wire $4\wr_detect$7[0:0]$10823 - attribute \src "issuer_ls180.v:166614.3-166643.6" - wire $4\wr_detect[0:0] - attribute \src "issuer_ls180.v:166881.3-166920.6" - wire width 4 $5\r27__data_o$next[3:0]$10844 - attribute \src "issuer_ls180.v:166811.3-166850.6" - wire width 4 $5\r7__data_o$next[3:0]$10830 - attribute \src "issuer_ls180.v:166574.3-166613.6" - wire width 4 $5\src17__data_o$next[3:0]$10787 - attribute \src "issuer_ls180.v:166671.3-166710.6" - wire width 4 $5\src27__data_o$next[3:0]$10802 - attribute \src "issuer_ls180.v:166741.3-166780.6" - wire width 4 $5\src37__data_o$next[3:0]$10816 - attribute \src "issuer_ls180.v:166881.3-166920.6" - wire width 4 $6\r27__data_o$next[3:0]$10845 - attribute \src "issuer_ls180.v:166811.3-166850.6" - wire width 4 $6\r7__data_o$next[3:0]$10831 - attribute \src "issuer_ls180.v:166574.3-166613.6" - wire width 4 $6\src17__data_o$next[3:0]$10788 - attribute \src "issuer_ls180.v:166671.3-166710.6" - wire width 4 $6\src27__data_o$next[3:0]$10803 - attribute \src "issuer_ls180.v:166741.3-166780.6" - wire width 4 $6\src37__data_o$next[3:0]$10817 - attribute \src "issuer_ls180.v:166557.17-166557.104" - wire $not$issuer_ls180.v:166557$10770_Y - attribute \src "issuer_ls180.v:166558.18-166558.105" - wire $not$issuer_ls180.v:166558$10771_Y - attribute \src "issuer_ls180.v:166559.17-166559.100" - wire $not$issuer_ls180.v:166559$10772_Y - attribute \src "issuer_ls180.v:166560.17-166560.103" - wire $not$issuer_ls180.v:166560$10773_Y - attribute \src "issuer_ls180.v:166561.17-166561.103" - wire $not$issuer_ls180.v:166561$10774_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest17__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \dest17__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest27__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \dest27__wen - attribute \src "issuer_ls180.v:166481.7-166481.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 14 \r27__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r27__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \r27__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r7__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r7__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 13 \r7__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src17__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src17__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \src17__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src27__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src27__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \src27__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src37__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src37__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \src37__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 16 \w7__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 17 \w7__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:166557$10770 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $not$issuer_ls180.v:166557$10770_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:166558$10771 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$13 - connect \Y $not$issuer_ls180.v:166558$10771_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:166559$10772 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$issuer_ls180.v:166559$10772_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:166560$10773 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$issuer_ls180.v:166560$10773_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$issuer_ls180.v:166561$10774 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $not$issuer_ls180.v:166561$10774_Y - end - attribute \src "issuer_ls180.v:166481.7-166481.20" - process $proc$issuer_ls180.v:166481$10852 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:166506.13-166506.31" - process $proc$issuer_ls180.v:166506$10853 - assign { } { } - assign $1\r27__data_o[3:0] 4'0000 - sync always - sync init - update \r27__data_o $1\r27__data_o[3:0] - end - attribute \src "issuer_ls180.v:166513.13-166513.30" - process $proc$issuer_ls180.v:166513$10854 - assign { } { } - assign $1\r7__data_o[3:0] 4'0000 - sync always - sync init - update \r7__data_o $1\r7__data_o[3:0] - end - attribute \src "issuer_ls180.v:166519.13-166519.25" - process $proc$issuer_ls180.v:166519$10855 - assign { } { } - assign $1\reg[3:0] 4'0000 - sync always - sync init - update \reg $1\reg[3:0] - end - attribute \src "issuer_ls180.v:166524.13-166524.33" - process $proc$issuer_ls180.v:166524$10856 - assign { } { } - assign $1\src17__data_o[3:0] 4'0000 - sync always - sync init - update \src17__data_o $1\src17__data_o[3:0] - end - attribute \src "issuer_ls180.v:166531.13-166531.33" - process $proc$issuer_ls180.v:166531$10857 - assign { } { } - assign $1\src27__data_o[3:0] 4'0000 - sync always - sync init - update \src27__data_o $1\src27__data_o[3:0] - end - attribute \src "issuer_ls180.v:166538.13-166538.33" - process $proc$issuer_ls180.v:166538$10858 - assign { } { } - assign $1\src37__data_o[3:0] 4'0000 - sync always - sync init - update \src37__data_o $1\src37__data_o[3:0] - end - attribute \src "issuer_ls180.v:166562.3-166563.25" - process $proc$issuer_ls180.v:166562$10775 - assign { } { } - assign $0\reg[3:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[3:0] - end - attribute \src "issuer_ls180.v:166564.3-166565.39" - process $proc$issuer_ls180.v:166564$10776 - assign { } { } - assign $0\r27__data_o[3:0] \r27__data_o$next - sync posedge \coresync_clk - update \r27__data_o $0\r27__data_o[3:0] - end - attribute \src "issuer_ls180.v:166566.3-166567.37" - process $proc$issuer_ls180.v:166566$10777 - assign { } { } - assign $0\r7__data_o[3:0] \r7__data_o$next - sync posedge \coresync_clk - update \r7__data_o $0\r7__data_o[3:0] - end - attribute \src "issuer_ls180.v:166568.3-166569.43" - process $proc$issuer_ls180.v:166568$10778 - assign { } { } - assign $0\src37__data_o[3:0] \src37__data_o$next - sync posedge \coresync_clk - update \src37__data_o $0\src37__data_o[3:0] - end - attribute \src "issuer_ls180.v:166570.3-166571.43" - process $proc$issuer_ls180.v:166570$10779 - assign { } { } - assign $0\src27__data_o[3:0] \src27__data_o$next - sync posedge \coresync_clk - update \src27__data_o $0\src27__data_o[3:0] - end - attribute \src "issuer_ls180.v:166572.3-166573.43" - process $proc$issuer_ls180.v:166572$10780 - assign { } { } - assign $0\src17__data_o[3:0] \src17__data_o$next - sync posedge \coresync_clk - update \src17__data_o $0\src17__data_o[3:0] - end - attribute \src "issuer_ls180.v:166574.3-166613.6" - process $proc$issuer_ls180.v:166574$10781 - assign { } { } - assign { } { } - assign { } { } - assign $0\src17__data_o$next[3:0]$10782 $6\src17__data_o$next[3:0]$10788 - attribute \src "issuer_ls180.v:166575.5-166575.29" - switch \initial - attribute \src "issuer_ls180.v:166575.9-166575.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src17__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src17__data_o$next[3:0]$10783 $5\src17__data_o$next[3:0]$10787 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest17__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src17__data_o$next[3:0]$10784 \dest17__data_i - case - assign $2\src17__data_o$next[3:0]$10784 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest27__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src17__data_o$next[3:0]$10785 \dest27__data_i - case - assign $3\src17__data_o$next[3:0]$10785 $2\src17__data_o$next[3:0]$10784 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w7__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src17__data_o$next[3:0]$10786 \w7__data_i - case - assign $4\src17__data_o$next[3:0]$10786 $3\src17__data_o$next[3:0]$10785 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src17__data_o$next[3:0]$10787 \reg - case - assign $5\src17__data_o$next[3:0]$10787 $4\src17__data_o$next[3:0]$10786 - end - case - assign $1\src17__data_o$next[3:0]$10783 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src17__data_o$next[3:0]$10788 4'0000 - case - assign $6\src17__data_o$next[3:0]$10788 $1\src17__data_o$next[3:0]$10783 - end - sync always - update \src17__data_o$next $0\src17__data_o$next[3:0]$10782 - end - attribute \src "issuer_ls180.v:166614.3-166643.6" - process $proc$issuer_ls180.v:166614$10789 - assign { } { } - assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "issuer_ls180.v:166615.5-166615.29" - switch \initial - attribute \src "issuer_ls180.v:166615.9-166615.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src17__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest17__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest27__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w7__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end - case - assign $1\wr_detect[0:0] 1'0 - end - sync always - update \wr_detect $0\wr_detect[0:0] - end - attribute \src "issuer_ls180.v:166644.3-166670.6" - process $proc$issuer_ls180.v:166644$10790 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[3:0]$10791 $4\reg$next[3:0]$10795 - attribute \src "issuer_ls180.v:166645.5-166645.29" - switch \initial - attribute \src "issuer_ls180.v:166645.9-166645.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest17__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg$next[3:0]$10792 \dest17__data_i - case - assign $1\reg$next[3:0]$10792 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest27__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reg$next[3:0]$10793 \dest27__data_i - case - assign $2\reg$next[3:0]$10793 $1\reg$next[3:0]$10792 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w7__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\reg$next[3:0]$10794 \w7__data_i - case - assign $3\reg$next[3:0]$10794 $2\reg$next[3:0]$10793 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\reg$next[3:0]$10795 4'0000 - case - assign $4\reg$next[3:0]$10795 $3\reg$next[3:0]$10794 - end - sync always - update \reg$next $0\reg$next[3:0]$10791 - end - attribute \src "issuer_ls180.v:166671.3-166710.6" - process $proc$issuer_ls180.v:166671$10796 - assign { } { } - assign { } { } - assign { } { } - assign $0\src27__data_o$next[3:0]$10797 $6\src27__data_o$next[3:0]$10803 - attribute \src "issuer_ls180.v:166672.5-166672.29" - switch \initial - attribute \src "issuer_ls180.v:166672.9-166672.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src27__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src27__data_o$next[3:0]$10798 $5\src27__data_o$next[3:0]$10802 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest17__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src27__data_o$next[3:0]$10799 \dest17__data_i - case - assign $2\src27__data_o$next[3:0]$10799 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest27__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src27__data_o$next[3:0]$10800 \dest27__data_i - case - assign $3\src27__data_o$next[3:0]$10800 $2\src27__data_o$next[3:0]$10799 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w7__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src27__data_o$next[3:0]$10801 \w7__data_i - case - assign $4\src27__data_o$next[3:0]$10801 $3\src27__data_o$next[3:0]$10800 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src27__data_o$next[3:0]$10802 \reg - case - assign $5\src27__data_o$next[3:0]$10802 $4\src27__data_o$next[3:0]$10801 - end - case - assign $1\src27__data_o$next[3:0]$10798 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src27__data_o$next[3:0]$10803 4'0000 - case - assign $6\src27__data_o$next[3:0]$10803 $1\src27__data_o$next[3:0]$10798 - end - sync always - update \src27__data_o$next $0\src27__data_o$next[3:0]$10797 - end - attribute \src "issuer_ls180.v:166711.3-166740.6" - process $proc$issuer_ls180.v:166711$10804 - assign { } { } - assign { } { } - assign $0\wr_detect$4[0:0]$10805 $1\wr_detect$4[0:0]$10806 - attribute \src "issuer_ls180.v:166712.5-166712.29" - switch \initial - attribute \src "issuer_ls180.v:166712.9-166712.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src27__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$4[0:0]$10806 $4\wr_detect$4[0:0]$10809 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest17__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$10807 1'1 - case - assign $2\wr_detect$4[0:0]$10807 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest27__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$10808 1'1 - case - assign $3\wr_detect$4[0:0]$10808 $2\wr_detect$4[0:0]$10807 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w7__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$10809 1'1 - case - assign $4\wr_detect$4[0:0]$10809 $3\wr_detect$4[0:0]$10808 - end - case - assign $1\wr_detect$4[0:0]$10806 1'0 - end - sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10805 - end - attribute \src "issuer_ls180.v:166741.3-166780.6" - process $proc$issuer_ls180.v:166741$10810 - assign { } { } - assign { } { } - assign { } { } - assign $0\src37__data_o$next[3:0]$10811 $6\src37__data_o$next[3:0]$10817 - attribute \src "issuer_ls180.v:166742.5-166742.29" - switch \initial - attribute \src "issuer_ls180.v:166742.9-166742.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src37__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\src37__data_o$next[3:0]$10812 $5\src37__data_o$next[3:0]$10816 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest17__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src37__data_o$next[3:0]$10813 \dest17__data_i - case - assign $2\src37__data_o$next[3:0]$10813 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest27__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src37__data_o$next[3:0]$10814 \dest27__data_i - case - assign $3\src37__data_o$next[3:0]$10814 $2\src37__data_o$next[3:0]$10813 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w7__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src37__data_o$next[3:0]$10815 \w7__data_i - case - assign $4\src37__data_o$next[3:0]$10815 $3\src37__data_o$next[3:0]$10814 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$6 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src37__data_o$next[3:0]$10816 \reg - case - assign $5\src37__data_o$next[3:0]$10816 $4\src37__data_o$next[3:0]$10815 - end - case - assign $1\src37__data_o$next[3:0]$10812 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src37__data_o$next[3:0]$10817 4'0000 - case - assign $6\src37__data_o$next[3:0]$10817 $1\src37__data_o$next[3:0]$10812 - end - sync always - update \src37__data_o$next $0\src37__data_o$next[3:0]$10811 - end - attribute \src "issuer_ls180.v:166781.3-166810.6" - process $proc$issuer_ls180.v:166781$10818 - assign { } { } - assign { } { } - assign $0\wr_detect$7[0:0]$10819 $1\wr_detect$7[0:0]$10820 - attribute \src "issuer_ls180.v:166782.5-166782.29" - switch \initial - attribute \src "issuer_ls180.v:166782.9-166782.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src37__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$7[0:0]$10820 $4\wr_detect$7[0:0]$10823 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest17__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$7[0:0]$10821 1'1 - case - assign $2\wr_detect$7[0:0]$10821 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest27__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$7[0:0]$10822 1'1 - case - assign $3\wr_detect$7[0:0]$10822 $2\wr_detect$7[0:0]$10821 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w7__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$7[0:0]$10823 1'1 - case - assign $4\wr_detect$7[0:0]$10823 $3\wr_detect$7[0:0]$10822 - end - case - assign $1\wr_detect$7[0:0]$10820 1'0 - end - sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10819 - end - attribute \src "issuer_ls180.v:166811.3-166850.6" - process $proc$issuer_ls180.v:166811$10824 - assign { } { } - assign { } { } - assign { } { } - assign $0\r7__data_o$next[3:0]$10825 $6\r7__data_o$next[3:0]$10831 - attribute \src "issuer_ls180.v:166812.5-166812.29" - switch \initial - attribute \src "issuer_ls180.v:166812.9-166812.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r7__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r7__data_o$next[3:0]$10826 $5\r7__data_o$next[3:0]$10830 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest17__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r7__data_o$next[3:0]$10827 \dest17__data_i - case - assign $2\r7__data_o$next[3:0]$10827 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest27__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r7__data_o$next[3:0]$10828 \dest27__data_i - case - assign $3\r7__data_o$next[3:0]$10828 $2\r7__data_o$next[3:0]$10827 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w7__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r7__data_o$next[3:0]$10829 \w7__data_i - case - assign $4\r7__data_o$next[3:0]$10829 $3\r7__data_o$next[3:0]$10828 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r7__data_o$next[3:0]$10830 \reg - case - assign $5\r7__data_o$next[3:0]$10830 $4\r7__data_o$next[3:0]$10829 - end - case - assign $1\r7__data_o$next[3:0]$10826 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r7__data_o$next[3:0]$10831 4'0000 - case - assign $6\r7__data_o$next[3:0]$10831 $1\r7__data_o$next[3:0]$10826 - end - sync always - update \r7__data_o$next $0\r7__data_o$next[3:0]$10825 - end - attribute \src "issuer_ls180.v:166851.3-166880.6" - process $proc$issuer_ls180.v:166851$10832 - assign { } { } - assign { } { } - assign $0\wr_detect$10[0:0]$10833 $1\wr_detect$10[0:0]$10834 - attribute \src "issuer_ls180.v:166852.5-166852.29" - switch \initial - attribute \src "issuer_ls180.v:166852.9-166852.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r7__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$10[0:0]$10834 $4\wr_detect$10[0:0]$10837 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest17__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$10[0:0]$10835 1'1 - case - assign $2\wr_detect$10[0:0]$10835 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest27__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$10[0:0]$10836 1'1 - case - assign $3\wr_detect$10[0:0]$10836 $2\wr_detect$10[0:0]$10835 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w7__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$10[0:0]$10837 1'1 - case - assign $4\wr_detect$10[0:0]$10837 $3\wr_detect$10[0:0]$10836 - end - case - assign $1\wr_detect$10[0:0]$10834 1'0 - end - sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10833 - end - attribute \src "issuer_ls180.v:166881.3-166920.6" - process $proc$issuer_ls180.v:166881$10838 - assign { } { } - assign { } { } - assign { } { } - assign $0\r27__data_o$next[3:0]$10839 $6\r27__data_o$next[3:0]$10845 - attribute \src "issuer_ls180.v:166882.5-166882.29" - switch \initial - attribute \src "issuer_ls180.v:166882.9-166882.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r27__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\r27__data_o$next[3:0]$10840 $5\r27__data_o$next[3:0]$10844 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest17__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r27__data_o$next[3:0]$10841 \dest17__data_i - case - assign $2\r27__data_o$next[3:0]$10841 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest27__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r27__data_o$next[3:0]$10842 \dest27__data_i - case - assign $3\r27__data_o$next[3:0]$10842 $2\r27__data_o$next[3:0]$10841 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w7__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r27__data_o$next[3:0]$10843 \w7__data_i - case - assign $4\r27__data_o$next[3:0]$10843 $3\r27__data_o$next[3:0]$10842 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$12 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r27__data_o$next[3:0]$10844 \reg - case - assign $5\r27__data_o$next[3:0]$10844 $4\r27__data_o$next[3:0]$10843 - end - case - assign $1\r27__data_o$next[3:0]$10840 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r27__data_o$next[3:0]$10845 4'0000 - case - assign $6\r27__data_o$next[3:0]$10845 $1\r27__data_o$next[3:0]$10840 - end - sync always - update \r27__data_o$next $0\r27__data_o$next[3:0]$10839 - end - attribute \src "issuer_ls180.v:166921.3-166950.6" - process $proc$issuer_ls180.v:166921$10846 - assign { } { } - assign { } { } - assign $0\wr_detect$13[0:0]$10847 $1\wr_detect$13[0:0]$10848 - attribute \src "issuer_ls180.v:166922.5-166922.29" - switch \initial - attribute \src "issuer_ls180.v:166922.9-166922.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r27__ren - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\wr_detect$13[0:0]$10848 $4\wr_detect$13[0:0]$10851 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest17__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$13[0:0]$10849 1'1 - case - assign $2\wr_detect$13[0:0]$10849 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest27__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$13[0:0]$10850 1'1 - case - assign $3\wr_detect$13[0:0]$10850 $2\wr_detect$13[0:0]$10849 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w7__wen - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$13[0:0]$10851 1'1 - case - assign $4\wr_detect$13[0:0]$10851 $3\wr_detect$13[0:0]$10850 - end - case - assign $1\wr_detect$13[0:0]$10848 1'0 - end - sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10847 - end - connect \$9 $not$issuer_ls180.v:166557$10770_Y - connect \$12 $not$issuer_ls180.v:166558$10771_Y - connect \$1 $not$issuer_ls180.v:166559$10772_Y - connect \$3 $not$issuer_ls180.v:166560$10773_Y - connect \$6 $not$issuer_ls180.v:166561$10774_Y -end -attribute \src "issuer_ls180.v:166955.1-167013.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.req_l" -attribute \generator "nMigen" -module \req_l - attribute \src "issuer_ls180.v:166956.7-166956.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:167001.3-167009.6" - wire width 5 $0\q_int$next[4:0]$10869 - attribute \src "issuer_ls180.v:166999.3-167000.27" - wire width 5 $0\q_int[4:0] - attribute \src "issuer_ls180.v:167001.3-167009.6" - wire width 5 $1\q_int$next[4:0]$10870 - attribute \src "issuer_ls180.v:166978.13-166978.26" - wire width 5 $1\q_int[4:0] - attribute \src "issuer_ls180.v:166991.17-166991.96" - wire width 5 $and$issuer_ls180.v:166991$10859_Y - attribute \src "issuer_ls180.v:166996.17-166996.96" - wire width 5 $and$issuer_ls180.v:166996$10864_Y - attribute \src "issuer_ls180.v:166993.18-166993.93" - wire width 5 $not$issuer_ls180.v:166993$10861_Y - attribute \src "issuer_ls180.v:166995.17-166995.92" - wire width 5 $not$issuer_ls180.v:166995$10863_Y - attribute \src "issuer_ls180.v:166998.17-166998.92" - wire width 5 $not$issuer_ls180.v:166998$10866_Y - attribute \src "issuer_ls180.v:166992.18-166992.98" - wire width 5 $or$issuer_ls180.v:166992$10860_Y - attribute \src "issuer_ls180.v:166994.18-166994.99" - wire width 5 $or$issuer_ls180.v:166994$10862_Y - attribute \src "issuer_ls180.v:166997.17-166997.97" - wire width 5 $or$issuer_ls180.v:166997$10865_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 5 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 5 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:166956.7-166956.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 5 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 5 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 5 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 5 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 5 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:166991$10859 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:166991$10859_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:166996$10864 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:166996$10864_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:166993$10861 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_req - connect \Y $not$issuer_ls180.v:166993$10861_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:166995$10863 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \r_req - connect \Y $not$issuer_ls180.v:166995$10863_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:166998$10866 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \r_req - connect \Y $not$issuer_ls180.v:166998$10866_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:166992$10860 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$9 - connect \B \s_req - connect \Y $or$issuer_ls180.v:166992$10860_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:166994$10862 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_req - connect \B \q_int - connect \Y $or$issuer_ls180.v:166994$10862_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:166997$10865 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$3 - connect \B \s_req - connect \Y $or$issuer_ls180.v:166997$10865_Y - end - attribute \src "issuer_ls180.v:166956.7-166956.20" - process $proc$issuer_ls180.v:166956$10871 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:166978.13-166978.26" - process $proc$issuer_ls180.v:166978$10872 - assign { } { } - assign $1\q_int[4:0] 5'00000 - sync always - sync init - update \q_int $1\q_int[4:0] - end - attribute \src "issuer_ls180.v:166999.3-167000.27" - process $proc$issuer_ls180.v:166999$10867 - assign { } { } - assign $0\q_int[4:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[4:0] - end - attribute \src "issuer_ls180.v:167001.3-167009.6" - process $proc$issuer_ls180.v:167001$10868 - assign { } { } - assign { } { } - assign $0\q_int$next[4:0]$10869 $1\q_int$next[4:0]$10870 - attribute \src "issuer_ls180.v:167002.5-167002.29" - switch \initial - attribute \src "issuer_ls180.v:167002.9-167002.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[4:0]$10870 5'00000 - case - assign $1\q_int$next[4:0]$10870 \$5 - end - sync always - update \q_int$next $0\q_int$next[4:0]$10869 - end - connect \$9 $and$issuer_ls180.v:166991$10859_Y - connect \$11 $or$issuer_ls180.v:166992$10860_Y - connect \$13 $not$issuer_ls180.v:166993$10861_Y - connect \$15 $or$issuer_ls180.v:166994$10862_Y - connect \$1 $not$issuer_ls180.v:166995$10863_Y - connect \$3 $and$issuer_ls180.v:166996$10864_Y - connect \$5 $or$issuer_ls180.v:166997$10865_Y - connect \$7 $not$issuer_ls180.v:166998$10866_Y - connect \qlq_req \$15 - connect \qn_req \$13 - connect \q_req \$11 -end -attribute \src "issuer_ls180.v:167017.1-167075.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.req_l" -attribute \generator "nMigen" -module \req_l$100 - attribute \src "issuer_ls180.v:167018.7-167018.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:167063.3-167071.6" - wire width 4 $0\q_int$next[3:0]$10883 - attribute \src "issuer_ls180.v:167061.3-167062.27" - wire width 4 $0\q_int[3:0] - attribute \src "issuer_ls180.v:167063.3-167071.6" - wire width 4 $1\q_int$next[3:0]$10884 - attribute \src "issuer_ls180.v:167040.13-167040.25" - wire width 4 $1\q_int[3:0] - attribute \src "issuer_ls180.v:167053.17-167053.96" - wire width 4 $and$issuer_ls180.v:167053$10873_Y - attribute \src "issuer_ls180.v:167058.17-167058.96" - wire width 4 $and$issuer_ls180.v:167058$10878_Y - attribute \src "issuer_ls180.v:167055.18-167055.93" - wire width 4 $not$issuer_ls180.v:167055$10875_Y - attribute \src "issuer_ls180.v:167057.17-167057.92" - wire width 4 $not$issuer_ls180.v:167057$10877_Y - attribute \src "issuer_ls180.v:167060.17-167060.92" - wire width 4 $not$issuer_ls180.v:167060$10880_Y - attribute \src "issuer_ls180.v:167054.18-167054.98" - wire width 4 $or$issuer_ls180.v:167054$10874_Y - attribute \src "issuer_ls180.v:167056.18-167056.99" - wire width 4 $or$issuer_ls180.v:167056$10876_Y - attribute \src "issuer_ls180.v:167059.17-167059.97" - wire width 4 $or$issuer_ls180.v:167059$10879_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 4 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 4 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:167018.7-167018.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 4 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 4 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:167053$10873 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:167053$10873_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:167058$10878 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:167058$10878_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:167055$10875 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_req - connect \Y $not$issuer_ls180.v:167055$10875_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:167057$10877 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_req - connect \Y $not$issuer_ls180.v:167057$10877_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:167060$10880 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_req - connect \Y $not$issuer_ls180.v:167060$10880_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:167054$10874 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$9 - connect \B \s_req - connect \Y $or$issuer_ls180.v:167054$10874_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:167056$10876 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_req - connect \B \q_int - connect \Y $or$issuer_ls180.v:167056$10876_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:167059$10879 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$3 - connect \B \s_req - connect \Y $or$issuer_ls180.v:167059$10879_Y - end - attribute \src "issuer_ls180.v:167018.7-167018.20" - process $proc$issuer_ls180.v:167018$10885 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:167040.13-167040.25" - process $proc$issuer_ls180.v:167040$10886 - assign { } { } - assign $1\q_int[3:0] 4'0000 - sync always - sync init - update \q_int $1\q_int[3:0] - end - attribute \src "issuer_ls180.v:167061.3-167062.27" - process $proc$issuer_ls180.v:167061$10881 - assign { } { } - assign $0\q_int[3:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[3:0] - end - attribute \src "issuer_ls180.v:167063.3-167071.6" - process $proc$issuer_ls180.v:167063$10882 - assign { } { } - assign { } { } - assign $0\q_int$next[3:0]$10883 $1\q_int$next[3:0]$10884 - attribute \src "issuer_ls180.v:167064.5-167064.29" - switch \initial - attribute \src "issuer_ls180.v:167064.9-167064.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[3:0]$10884 4'0000 - case - assign $1\q_int$next[3:0]$10884 \$5 - end - sync always - update \q_int$next $0\q_int$next[3:0]$10883 - end - connect \$9 $and$issuer_ls180.v:167053$10873_Y - connect \$11 $or$issuer_ls180.v:167054$10874_Y - connect \$13 $not$issuer_ls180.v:167055$10875_Y - connect \$15 $or$issuer_ls180.v:167056$10876_Y - connect \$1 $not$issuer_ls180.v:167057$10877_Y - connect \$3 $and$issuer_ls180.v:167058$10878_Y - connect \$5 $or$issuer_ls180.v:167059$10879_Y - connect \$7 $not$issuer_ls180.v:167060$10880_Y - connect \qlq_req \$15 - connect \qn_req \$13 - connect \q_req \$11 -end -attribute \src "issuer_ls180.v:167079.1-167137.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.req_l" -attribute \generator "nMigen" -module \req_l$118 - attribute \src "issuer_ls180.v:167080.7-167080.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:167125.3-167133.6" - wire width 3 $0\q_int$next[2:0]$10897 - attribute \src "issuer_ls180.v:167123.3-167124.27" - wire width 3 $0\q_int[2:0] - attribute \src "issuer_ls180.v:167125.3-167133.6" - wire width 3 $1\q_int$next[2:0]$10898 - attribute \src "issuer_ls180.v:167102.13-167102.25" - wire width 3 $1\q_int[2:0] - attribute \src "issuer_ls180.v:167115.17-167115.96" - wire width 3 $and$issuer_ls180.v:167115$10887_Y - attribute \src "issuer_ls180.v:167120.17-167120.96" - wire width 3 $and$issuer_ls180.v:167120$10892_Y - attribute \src "issuer_ls180.v:167117.18-167117.93" - wire width 3 $not$issuer_ls180.v:167117$10889_Y - attribute \src "issuer_ls180.v:167119.17-167119.92" - wire width 3 $not$issuer_ls180.v:167119$10891_Y - attribute \src "issuer_ls180.v:167122.17-167122.92" - wire width 3 $not$issuer_ls180.v:167122$10894_Y - attribute \src "issuer_ls180.v:167116.18-167116.98" - wire width 3 $or$issuer_ls180.v:167116$10888_Y - attribute \src "issuer_ls180.v:167118.18-167118.99" - wire width 3 $or$issuer_ls180.v:167118$10890_Y - attribute \src "issuer_ls180.v:167121.17-167121.97" - wire width 3 $or$issuer_ls180.v:167121$10893_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:167080.7-167080.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:167115$10887 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:167115$10887_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:167120$10892 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:167120$10892_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:167117$10889 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_req - connect \Y $not$issuer_ls180.v:167117$10889_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:167119$10891 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_req - connect \Y $not$issuer_ls180.v:167119$10891_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:167122$10894 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_req - connect \Y $not$issuer_ls180.v:167122$10894_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:167116$10888 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$9 - connect \B \s_req - connect \Y $or$issuer_ls180.v:167116$10888_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:167118$10890 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_req - connect \B \q_int - connect \Y $or$issuer_ls180.v:167118$10890_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:167121$10893 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$3 - connect \B \s_req - connect \Y $or$issuer_ls180.v:167121$10893_Y - end - attribute \src "issuer_ls180.v:167080.7-167080.20" - process $proc$issuer_ls180.v:167080$10899 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:167102.13-167102.25" - process $proc$issuer_ls180.v:167102$10900 - assign { } { } - assign $1\q_int[2:0] 3'000 - sync always - sync init - update \q_int $1\q_int[2:0] - end - attribute \src "issuer_ls180.v:167123.3-167124.27" - process $proc$issuer_ls180.v:167123$10895 - assign { } { } - assign $0\q_int[2:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[2:0] - end - attribute \src "issuer_ls180.v:167125.3-167133.6" - process $proc$issuer_ls180.v:167125$10896 - assign { } { } - assign { } { } - assign $0\q_int$next[2:0]$10897 $1\q_int$next[2:0]$10898 - attribute \src "issuer_ls180.v:167126.5-167126.29" - switch \initial - attribute \src "issuer_ls180.v:167126.9-167126.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[2:0]$10898 3'000 - case - assign $1\q_int$next[2:0]$10898 \$5 - end - sync always - update \q_int$next $0\q_int$next[2:0]$10897 - end - connect \$9 $and$issuer_ls180.v:167115$10887_Y - connect \$11 $or$issuer_ls180.v:167116$10888_Y - connect \$13 $not$issuer_ls180.v:167117$10889_Y - connect \$15 $or$issuer_ls180.v:167118$10890_Y - connect \$1 $not$issuer_ls180.v:167119$10891_Y - connect \$3 $and$issuer_ls180.v:167120$10892_Y - connect \$5 $or$issuer_ls180.v:167121$10893_Y - connect \$7 $not$issuer_ls180.v:167122$10894_Y - connect \qlq_req \$15 - connect \qn_req \$13 - connect \q_req \$11 -end -attribute \src "issuer_ls180.v:167141.1-167199.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.req_l" -attribute \generator "nMigen" -module \req_l$12 - attribute \src "issuer_ls180.v:167142.7-167142.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:167187.3-167195.6" - wire width 3 $0\q_int$next[2:0]$10911 - attribute \src "issuer_ls180.v:167185.3-167186.27" - wire width 3 $0\q_int[2:0] - attribute \src "issuer_ls180.v:167187.3-167195.6" - wire width 3 $1\q_int$next[2:0]$10912 - attribute \src "issuer_ls180.v:167164.13-167164.25" - wire width 3 $1\q_int[2:0] - attribute \src "issuer_ls180.v:167177.17-167177.96" - wire width 3 $and$issuer_ls180.v:167177$10901_Y - attribute \src "issuer_ls180.v:167182.17-167182.96" - wire width 3 $and$issuer_ls180.v:167182$10906_Y - attribute \src "issuer_ls180.v:167179.18-167179.93" - wire width 3 $not$issuer_ls180.v:167179$10903_Y - attribute \src "issuer_ls180.v:167181.17-167181.92" - wire width 3 $not$issuer_ls180.v:167181$10905_Y - attribute \src "issuer_ls180.v:167184.17-167184.92" - wire width 3 $not$issuer_ls180.v:167184$10908_Y - attribute \src "issuer_ls180.v:167178.18-167178.98" - wire width 3 $or$issuer_ls180.v:167178$10902_Y - attribute \src "issuer_ls180.v:167180.18-167180.99" - wire width 3 $or$issuer_ls180.v:167180$10904_Y - attribute \src "issuer_ls180.v:167183.17-167183.97" - wire width 3 $or$issuer_ls180.v:167183$10907_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:167142.7-167142.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:167177$10901 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:167177$10901_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:167182$10906 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:167182$10906_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:167179$10903 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_req - connect \Y $not$issuer_ls180.v:167179$10903_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:167181$10905 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_req - connect \Y $not$issuer_ls180.v:167181$10905_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:167184$10908 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_req - connect \Y $not$issuer_ls180.v:167184$10908_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:167178$10902 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$9 - connect \B \s_req - connect \Y $or$issuer_ls180.v:167178$10902_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:167180$10904 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_req - connect \B \q_int - connect \Y $or$issuer_ls180.v:167180$10904_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:167183$10907 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$3 - connect \B \s_req - connect \Y $or$issuer_ls180.v:167183$10907_Y - end - attribute \src "issuer_ls180.v:167142.7-167142.20" - process $proc$issuer_ls180.v:167142$10913 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:167164.13-167164.25" - process $proc$issuer_ls180.v:167164$10914 - assign { } { } - assign $1\q_int[2:0] 3'000 - sync always - sync init - update \q_int $1\q_int[2:0] - end - attribute \src "issuer_ls180.v:167185.3-167186.27" - process $proc$issuer_ls180.v:167185$10909 - assign { } { } - assign $0\q_int[2:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[2:0] - end - attribute \src "issuer_ls180.v:167187.3-167195.6" - process $proc$issuer_ls180.v:167187$10910 - assign { } { } - assign { } { } - assign $0\q_int$next[2:0]$10911 $1\q_int$next[2:0]$10912 - attribute \src "issuer_ls180.v:167188.5-167188.29" - switch \initial - attribute \src "issuer_ls180.v:167188.9-167188.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[2:0]$10912 3'000 - case - assign $1\q_int$next[2:0]$10912 \$5 - end - sync always - update \q_int$next $0\q_int$next[2:0]$10911 - end - connect \$9 $and$issuer_ls180.v:167177$10901_Y - connect \$11 $or$issuer_ls180.v:167178$10902_Y - connect \$13 $not$issuer_ls180.v:167179$10903_Y - connect \$15 $or$issuer_ls180.v:167180$10904_Y - connect \$1 $not$issuer_ls180.v:167181$10905_Y - connect \$3 $and$issuer_ls180.v:167182$10906_Y - connect \$5 $or$issuer_ls180.v:167183$10907_Y - connect \$7 $not$issuer_ls180.v:167184$10908_Y - connect \qlq_req \$15 - connect \qn_req \$13 - connect \q_req \$11 -end -attribute \src "issuer_ls180.v:167203.1-167261.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.req_l" -attribute \generator "nMigen" -module \req_l$25 - attribute \src "issuer_ls180.v:167204.7-167204.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:167249.3-167257.6" - wire width 3 $0\q_int$next[2:0]$10925 - attribute \src "issuer_ls180.v:167247.3-167248.27" - wire width 3 $0\q_int[2:0] - attribute \src "issuer_ls180.v:167249.3-167257.6" - wire width 3 $1\q_int$next[2:0]$10926 - attribute \src "issuer_ls180.v:167226.13-167226.25" - wire width 3 $1\q_int[2:0] - attribute \src "issuer_ls180.v:167239.17-167239.96" - wire width 3 $and$issuer_ls180.v:167239$10915_Y - attribute \src "issuer_ls180.v:167244.17-167244.96" - wire width 3 $and$issuer_ls180.v:167244$10920_Y - attribute \src "issuer_ls180.v:167241.18-167241.93" - wire width 3 $not$issuer_ls180.v:167241$10917_Y - attribute \src "issuer_ls180.v:167243.17-167243.92" - wire width 3 $not$issuer_ls180.v:167243$10919_Y - attribute \src "issuer_ls180.v:167246.17-167246.92" - wire width 3 $not$issuer_ls180.v:167246$10922_Y - attribute \src "issuer_ls180.v:167240.18-167240.98" - wire width 3 $or$issuer_ls180.v:167240$10916_Y - attribute \src "issuer_ls180.v:167242.18-167242.99" - wire width 3 $or$issuer_ls180.v:167242$10918_Y - attribute \src "issuer_ls180.v:167245.17-167245.97" - wire width 3 $or$issuer_ls180.v:167245$10921_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:167204.7-167204.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:167239$10915 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:167239$10915_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:167244$10920 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:167244$10920_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:167241$10917 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_req - connect \Y $not$issuer_ls180.v:167241$10917_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:167243$10919 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_req - connect \Y $not$issuer_ls180.v:167243$10919_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:167246$10922 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_req - connect \Y $not$issuer_ls180.v:167246$10922_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:167240$10916 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$9 - connect \B \s_req - connect \Y $or$issuer_ls180.v:167240$10916_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:167242$10918 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_req - connect \B \q_int - connect \Y $or$issuer_ls180.v:167242$10918_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:167245$10921 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$3 - connect \B \s_req - connect \Y $or$issuer_ls180.v:167245$10921_Y - end - attribute \src "issuer_ls180.v:167204.7-167204.20" - process $proc$issuer_ls180.v:167204$10927 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:167226.13-167226.25" - process $proc$issuer_ls180.v:167226$10928 - assign { } { } - assign $1\q_int[2:0] 3'000 - sync always - sync init - update \q_int $1\q_int[2:0] - end - attribute \src "issuer_ls180.v:167247.3-167248.27" - process $proc$issuer_ls180.v:167247$10923 - assign { } { } - assign $0\q_int[2:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[2:0] - end - attribute \src "issuer_ls180.v:167249.3-167257.6" - process $proc$issuer_ls180.v:167249$10924 - assign { } { } - assign { } { } - assign $0\q_int$next[2:0]$10925 $1\q_int$next[2:0]$10926 - attribute \src "issuer_ls180.v:167250.5-167250.29" - switch \initial - attribute \src "issuer_ls180.v:167250.9-167250.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[2:0]$10926 3'000 - case - assign $1\q_int$next[2:0]$10926 \$5 - end - sync always - update \q_int$next $0\q_int$next[2:0]$10925 - end - connect \$9 $and$issuer_ls180.v:167239$10915_Y - connect \$11 $or$issuer_ls180.v:167240$10916_Y - connect \$13 $not$issuer_ls180.v:167241$10917_Y - connect \$15 $or$issuer_ls180.v:167242$10918_Y - connect \$1 $not$issuer_ls180.v:167243$10919_Y - connect \$3 $and$issuer_ls180.v:167244$10920_Y - connect \$5 $or$issuer_ls180.v:167245$10921_Y - connect \$7 $not$issuer_ls180.v:167246$10922_Y - connect \qlq_req \$15 - connect \qn_req \$13 - connect \q_req \$11 -end -attribute \src "issuer_ls180.v:167265.1-167323.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.req_l" -attribute \generator "nMigen" -module \req_l$38 - attribute \src "issuer_ls180.v:167266.7-167266.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:167311.3-167319.6" - wire width 5 $0\q_int$next[4:0]$10939 - attribute \src "issuer_ls180.v:167309.3-167310.27" - wire width 5 $0\q_int[4:0] - attribute \src "issuer_ls180.v:167311.3-167319.6" - wire width 5 $1\q_int$next[4:0]$10940 - attribute \src "issuer_ls180.v:167288.13-167288.26" - wire width 5 $1\q_int[4:0] - attribute \src "issuer_ls180.v:167301.17-167301.96" - wire width 5 $and$issuer_ls180.v:167301$10929_Y - attribute \src "issuer_ls180.v:167306.17-167306.96" - wire width 5 $and$issuer_ls180.v:167306$10934_Y - attribute \src "issuer_ls180.v:167303.18-167303.93" - wire width 5 $not$issuer_ls180.v:167303$10931_Y - attribute \src "issuer_ls180.v:167305.17-167305.92" - wire width 5 $not$issuer_ls180.v:167305$10933_Y - attribute \src "issuer_ls180.v:167308.17-167308.92" - wire width 5 $not$issuer_ls180.v:167308$10936_Y - attribute \src "issuer_ls180.v:167302.18-167302.98" - wire width 5 $or$issuer_ls180.v:167302$10930_Y - attribute \src "issuer_ls180.v:167304.18-167304.99" - wire width 5 $or$issuer_ls180.v:167304$10932_Y - attribute \src "issuer_ls180.v:167307.17-167307.97" - wire width 5 $or$issuer_ls180.v:167307$10935_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 5 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 5 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:167266.7-167266.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 5 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 5 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 5 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 5 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 5 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:167301$10929 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:167301$10929_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:167306$10934 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:167306$10934_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:167303$10931 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_req - connect \Y $not$issuer_ls180.v:167303$10931_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:167305$10933 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \r_req - connect \Y $not$issuer_ls180.v:167305$10933_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:167308$10936 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \r_req - connect \Y $not$issuer_ls180.v:167308$10936_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:167302$10930 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$9 - connect \B \s_req - connect \Y $or$issuer_ls180.v:167302$10930_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:167304$10932 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_req - connect \B \q_int - connect \Y $or$issuer_ls180.v:167304$10932_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:167307$10935 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$3 - connect \B \s_req - connect \Y $or$issuer_ls180.v:167307$10935_Y - end - attribute \src "issuer_ls180.v:167266.7-167266.20" - process $proc$issuer_ls180.v:167266$10941 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:167288.13-167288.26" - process $proc$issuer_ls180.v:167288$10942 - assign { } { } - assign $1\q_int[4:0] 5'00000 - sync always - sync init - update \q_int $1\q_int[4:0] - end - attribute \src "issuer_ls180.v:167309.3-167310.27" - process $proc$issuer_ls180.v:167309$10937 - assign { } { } - assign $0\q_int[4:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[4:0] - end - attribute \src "issuer_ls180.v:167311.3-167319.6" - process $proc$issuer_ls180.v:167311$10938 - assign { } { } - assign { } { } - assign $0\q_int$next[4:0]$10939 $1\q_int$next[4:0]$10940 - attribute \src "issuer_ls180.v:167312.5-167312.29" - switch \initial - attribute \src "issuer_ls180.v:167312.9-167312.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[4:0]$10940 5'00000 - case - assign $1\q_int$next[4:0]$10940 \$5 - end - sync always - update \q_int$next $0\q_int$next[4:0]$10939 - end - connect \$9 $and$issuer_ls180.v:167301$10929_Y - connect \$11 $or$issuer_ls180.v:167302$10930_Y - connect \$13 $not$issuer_ls180.v:167303$10931_Y - connect \$15 $or$issuer_ls180.v:167304$10932_Y - connect \$1 $not$issuer_ls180.v:167305$10933_Y - connect \$3 $and$issuer_ls180.v:167306$10934_Y - connect \$5 $or$issuer_ls180.v:167307$10935_Y - connect \$7 $not$issuer_ls180.v:167308$10936_Y - connect \qlq_req \$15 - connect \qn_req \$13 - connect \q_req \$11 -end -attribute \src "issuer_ls180.v:167327.1-167385.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.req_l" -attribute \generator "nMigen" -module \req_l$54 - attribute \src "issuer_ls180.v:167328.7-167328.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:167373.3-167381.6" - wire width 2 $0\q_int$next[1:0]$10953 - attribute \src "issuer_ls180.v:167371.3-167372.27" - wire width 2 $0\q_int[1:0] - attribute \src "issuer_ls180.v:167373.3-167381.6" - wire width 2 $1\q_int$next[1:0]$10954 - attribute \src "issuer_ls180.v:167350.13-167350.25" - wire width 2 $1\q_int[1:0] - attribute \src "issuer_ls180.v:167363.17-167363.96" - wire width 2 $and$issuer_ls180.v:167363$10943_Y - attribute \src "issuer_ls180.v:167368.17-167368.96" - wire width 2 $and$issuer_ls180.v:167368$10948_Y - attribute \src "issuer_ls180.v:167365.18-167365.93" - wire width 2 $not$issuer_ls180.v:167365$10945_Y - attribute \src "issuer_ls180.v:167367.17-167367.92" - wire width 2 $not$issuer_ls180.v:167367$10947_Y - attribute \src "issuer_ls180.v:167370.17-167370.92" - wire width 2 $not$issuer_ls180.v:167370$10950_Y - attribute \src "issuer_ls180.v:167364.18-167364.98" - wire width 2 $or$issuer_ls180.v:167364$10944_Y - attribute \src "issuer_ls180.v:167366.18-167366.99" - wire width 2 $or$issuer_ls180.v:167366$10946_Y - attribute \src "issuer_ls180.v:167369.17-167369.97" - wire width 2 $or$issuer_ls180.v:167369$10949_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 2 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 2 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 2 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 2 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 2 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 2 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 2 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 2 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:167328.7-167328.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 2 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 2 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 2 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 2 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 2 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 2 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 2 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:167363$10943 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:167363$10943_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:167368$10948 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:167368$10948_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:167365$10945 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \q_req - connect \Y $not$issuer_ls180.v:167365$10945_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:167367$10947 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \r_req - connect \Y $not$issuer_ls180.v:167367$10947_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:167370$10950 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \r_req - connect \Y $not$issuer_ls180.v:167370$10950_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:167364$10944 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \$9 - connect \B \s_req - connect \Y $or$issuer_ls180.v:167364$10944_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:167366$10946 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \q_req - connect \B \q_int - connect \Y $or$issuer_ls180.v:167366$10946_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:167369$10949 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \$3 - connect \B \s_req - connect \Y $or$issuer_ls180.v:167369$10949_Y - end - attribute \src "issuer_ls180.v:167328.7-167328.20" - process $proc$issuer_ls180.v:167328$10955 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:167350.13-167350.25" - process $proc$issuer_ls180.v:167350$10956 - assign { } { } - assign $1\q_int[1:0] 2'00 - sync always - sync init - update \q_int $1\q_int[1:0] - end - attribute \src "issuer_ls180.v:167371.3-167372.27" - process $proc$issuer_ls180.v:167371$10951 - assign { } { } - assign $0\q_int[1:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[1:0] - end - attribute \src "issuer_ls180.v:167373.3-167381.6" - process $proc$issuer_ls180.v:167373$10952 - assign { } { } - assign { } { } - assign $0\q_int$next[1:0]$10953 $1\q_int$next[1:0]$10954 - attribute \src "issuer_ls180.v:167374.5-167374.29" - switch \initial - attribute \src "issuer_ls180.v:167374.9-167374.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[1:0]$10954 2'00 - case - assign $1\q_int$next[1:0]$10954 \$5 - end - sync always - update \q_int$next $0\q_int$next[1:0]$10953 - end - connect \$9 $and$issuer_ls180.v:167363$10943_Y - connect \$11 $or$issuer_ls180.v:167364$10944_Y - connect \$13 $not$issuer_ls180.v:167365$10945_Y - connect \$15 $or$issuer_ls180.v:167366$10946_Y - connect \$1 $not$issuer_ls180.v:167367$10947_Y - connect \$3 $and$issuer_ls180.v:167368$10948_Y - connect \$5 $or$issuer_ls180.v:167369$10949_Y - connect \$7 $not$issuer_ls180.v:167370$10950_Y - connect \qlq_req \$15 - connect \qn_req \$13 - connect \q_req \$11 -end -attribute \src "issuer_ls180.v:167389.1-167447.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.req_l" -attribute \generator "nMigen" -module \req_l$66 - attribute \src "issuer_ls180.v:167390.7-167390.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:167435.3-167443.6" - wire width 6 $0\q_int$next[5:0]$10967 - attribute \src "issuer_ls180.v:167433.3-167434.27" - wire width 6 $0\q_int[5:0] - attribute \src "issuer_ls180.v:167435.3-167443.6" - wire width 6 $1\q_int$next[5:0]$10968 - attribute \src "issuer_ls180.v:167412.13-167412.26" - wire width 6 $1\q_int[5:0] - attribute \src "issuer_ls180.v:167425.17-167425.96" - wire width 6 $and$issuer_ls180.v:167425$10957_Y - attribute \src "issuer_ls180.v:167430.17-167430.96" - wire width 6 $and$issuer_ls180.v:167430$10962_Y - attribute \src "issuer_ls180.v:167427.18-167427.93" - wire width 6 $not$issuer_ls180.v:167427$10959_Y - attribute \src "issuer_ls180.v:167429.17-167429.92" - wire width 6 $not$issuer_ls180.v:167429$10961_Y - attribute \src "issuer_ls180.v:167432.17-167432.92" - wire width 6 $not$issuer_ls180.v:167432$10964_Y - attribute \src "issuer_ls180.v:167426.18-167426.98" - wire width 6 $or$issuer_ls180.v:167426$10958_Y - attribute \src "issuer_ls180.v:167428.18-167428.99" - wire width 6 $or$issuer_ls180.v:167428$10960_Y - attribute \src "issuer_ls180.v:167431.17-167431.97" - wire width 6 $or$issuer_ls180.v:167431$10963_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 6 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 6 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:167390.7-167390.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 6 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 6 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 6 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 6 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:167425$10957 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:167425$10957_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:167430$10962 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:167430$10962_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:167427$10959 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_req - connect \Y $not$issuer_ls180.v:167427$10959_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:167429$10961 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \r_req - connect \Y $not$issuer_ls180.v:167429$10961_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:167432$10964 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \r_req - connect \Y $not$issuer_ls180.v:167432$10964_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:167426$10958 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \$9 - connect \B \s_req - connect \Y $or$issuer_ls180.v:167426$10958_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:167428$10960 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_req - connect \B \q_int - connect \Y $or$issuer_ls180.v:167428$10960_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:167431$10963 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \$3 - connect \B \s_req - connect \Y $or$issuer_ls180.v:167431$10963_Y - end - attribute \src "issuer_ls180.v:167390.7-167390.20" - process $proc$issuer_ls180.v:167390$10969 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:167412.13-167412.26" - process $proc$issuer_ls180.v:167412$10970 - assign { } { } - assign $1\q_int[5:0] 6'000000 - sync always - sync init - update \q_int $1\q_int[5:0] - end - attribute \src "issuer_ls180.v:167433.3-167434.27" - process $proc$issuer_ls180.v:167433$10965 - assign { } { } - assign $0\q_int[5:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[5:0] - end - attribute \src "issuer_ls180.v:167435.3-167443.6" - process $proc$issuer_ls180.v:167435$10966 - assign { } { } - assign { } { } - assign $0\q_int$next[5:0]$10967 $1\q_int$next[5:0]$10968 - attribute \src "issuer_ls180.v:167436.5-167436.29" - switch \initial - attribute \src "issuer_ls180.v:167436.9-167436.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[5:0]$10968 6'000000 - case - assign $1\q_int$next[5:0]$10968 \$5 - end - sync always - update \q_int$next $0\q_int$next[5:0]$10967 - end - connect \$9 $and$issuer_ls180.v:167425$10957_Y - connect \$11 $or$issuer_ls180.v:167426$10958_Y - connect \$13 $not$issuer_ls180.v:167427$10959_Y - connect \$15 $or$issuer_ls180.v:167428$10960_Y - connect \$1 $not$issuer_ls180.v:167429$10961_Y - connect \$3 $and$issuer_ls180.v:167430$10962_Y - connect \$5 $or$issuer_ls180.v:167431$10963_Y - connect \$7 $not$issuer_ls180.v:167432$10964_Y - connect \qlq_req \$15 - connect \qn_req \$13 - connect \q_req \$11 -end -attribute \src "issuer_ls180.v:167451.1-167509.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.req_l" -attribute \generator "nMigen" -module \req_l$83 - attribute \src "issuer_ls180.v:167452.7-167452.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:167497.3-167505.6" - wire width 4 $0\q_int$next[3:0]$10981 - attribute \src "issuer_ls180.v:167495.3-167496.27" - wire width 4 $0\q_int[3:0] - attribute \src "issuer_ls180.v:167497.3-167505.6" - wire width 4 $1\q_int$next[3:0]$10982 - attribute \src "issuer_ls180.v:167474.13-167474.25" - wire width 4 $1\q_int[3:0] - attribute \src "issuer_ls180.v:167487.17-167487.96" - wire width 4 $and$issuer_ls180.v:167487$10971_Y - attribute \src "issuer_ls180.v:167492.17-167492.96" - wire width 4 $and$issuer_ls180.v:167492$10976_Y - attribute \src "issuer_ls180.v:167489.18-167489.93" - wire width 4 $not$issuer_ls180.v:167489$10973_Y - attribute \src "issuer_ls180.v:167491.17-167491.92" - wire width 4 $not$issuer_ls180.v:167491$10975_Y - attribute \src "issuer_ls180.v:167494.17-167494.92" - wire width 4 $not$issuer_ls180.v:167494$10978_Y - attribute \src "issuer_ls180.v:167488.18-167488.98" - wire width 4 $or$issuer_ls180.v:167488$10972_Y - attribute \src "issuer_ls180.v:167490.18-167490.99" - wire width 4 $or$issuer_ls180.v:167490$10974_Y - attribute \src "issuer_ls180.v:167493.17-167493.97" - wire width 4 $or$issuer_ls180.v:167493$10977_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 4 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 4 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:167452.7-167452.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 4 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 4 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:167487$10971 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:167487$10971_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:167492$10976 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:167492$10976_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:167489$10973 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_req - connect \Y $not$issuer_ls180.v:167489$10973_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:167491$10975 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_req - connect \Y $not$issuer_ls180.v:167491$10975_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:167494$10978 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_req - connect \Y $not$issuer_ls180.v:167494$10978_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:167488$10972 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$9 - connect \B \s_req - connect \Y $or$issuer_ls180.v:167488$10972_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:167490$10974 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_req - connect \B \q_int - connect \Y $or$issuer_ls180.v:167490$10974_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:167493$10977 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$3 - connect \B \s_req - connect \Y $or$issuer_ls180.v:167493$10977_Y - end - attribute \src "issuer_ls180.v:167452.7-167452.20" - process $proc$issuer_ls180.v:167452$10983 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:167474.13-167474.25" - process $proc$issuer_ls180.v:167474$10984 - assign { } { } - assign $1\q_int[3:0] 4'0000 - sync always - sync init - update \q_int $1\q_int[3:0] - end - attribute \src "issuer_ls180.v:167495.3-167496.27" - process $proc$issuer_ls180.v:167495$10979 - assign { } { } - assign $0\q_int[3:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[3:0] - end - attribute \src "issuer_ls180.v:167497.3-167505.6" - process $proc$issuer_ls180.v:167497$10980 - assign { } { } - assign { } { } - assign $0\q_int$next[3:0]$10981 $1\q_int$next[3:0]$10982 - attribute \src "issuer_ls180.v:167498.5-167498.29" - switch \initial - attribute \src "issuer_ls180.v:167498.9-167498.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[3:0]$10982 4'0000 - case - assign $1\q_int$next[3:0]$10982 \$5 - end - sync always - update \q_int$next $0\q_int$next[3:0]$10981 - end - connect \$9 $and$issuer_ls180.v:167487$10971_Y - connect \$11 $or$issuer_ls180.v:167488$10972_Y - connect \$13 $not$issuer_ls180.v:167489$10973_Y - connect \$15 $or$issuer_ls180.v:167490$10974_Y - connect \$1 $not$issuer_ls180.v:167491$10975_Y - connect \$3 $and$issuer_ls180.v:167492$10976_Y - connect \$5 $or$issuer_ls180.v:167493$10977_Y - connect \$7 $not$issuer_ls180.v:167494$10978_Y - connect \qlq_req \$15 - connect \qn_req \$13 - connect \q_req \$11 -end -attribute \src "issuer_ls180.v:167513.1-167562.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.reset_l" -attribute \generator "nMigen" -module \reset_l - attribute \src "issuer_ls180.v:167514.7-167514.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:167550.3-167558.6" - wire $0\q_int$next[0:0]$10992 - attribute \src "issuer_ls180.v:167548.3-167549.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:167550.3-167558.6" - wire $1\q_int$next[0:0]$10993 - attribute \src "issuer_ls180.v:167530.7-167530.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:167545.17-167545.96" - wire $and$issuer_ls180.v:167545$10987_Y - attribute \src "issuer_ls180.v:167544.17-167544.94" - wire $not$issuer_ls180.v:167544$10986_Y - attribute \src "issuer_ls180.v:167547.17-167547.94" - wire $not$issuer_ls180.v:167547$10989_Y - attribute \src "issuer_ls180.v:167543.17-167543.100" - wire $or$issuer_ls180.v:167543$10985_Y - attribute \src "issuer_ls180.v:167546.17-167546.99" - wire $or$issuer_ls180.v:167546$10988_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:167514.7-167514.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:167545$10987 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:167545$10987_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:167544$10986 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_reset - connect \Y $not$issuer_ls180.v:167544$10986_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:167547$10989 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_reset - connect \Y $not$issuer_ls180.v:167547$10989_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:167543$10985 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_reset - connect \B \q_int - connect \Y $or$issuer_ls180.v:167543$10985_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:167546$10988 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_reset - connect \Y $or$issuer_ls180.v:167546$10988_Y - end - attribute \src "issuer_ls180.v:167514.7-167514.20" - process $proc$issuer_ls180.v:167514$10994 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:167530.7-167530.19" - process $proc$issuer_ls180.v:167530$10995 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:167548.3-167549.27" - process $proc$issuer_ls180.v:167548$10990 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:167550.3-167558.6" - process $proc$issuer_ls180.v:167550$10991 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$10992 $1\q_int$next[0:0]$10993 - attribute \src "issuer_ls180.v:167551.5-167551.29" - switch \initial - attribute \src "issuer_ls180.v:167551.9-167551.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$10993 1'0 - case - assign $1\q_int$next[0:0]$10993 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$10992 - end - connect \$9 $or$issuer_ls180.v:167543$10985_Y - connect \$1 $not$issuer_ls180.v:167544$10986_Y - connect \$3 $and$issuer_ls180.v:167545$10987_Y - connect \$5 $or$issuer_ls180.v:167546$10988_Y - connect \$7 $not$issuer_ls180.v:167547$10989_Y - connect \qlq_reset \$9 - connect \qn_reset \$7 - connect \q_reset \q_int -end -attribute \src "issuer_ls180.v:167566.1-167615.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.l0.reset_l" -attribute \generator "nMigen" -module \reset_l$128 - attribute \src "issuer_ls180.v:167567.7-167567.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:167603.3-167611.6" - wire $0\q_int$next[0:0]$11003 - attribute \src "issuer_ls180.v:167601.3-167602.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:167603.3-167611.6" - wire $1\q_int$next[0:0]$11004 - attribute \src "issuer_ls180.v:167583.7-167583.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:167598.17-167598.96" - wire $and$issuer_ls180.v:167598$10998_Y - attribute \src "issuer_ls180.v:167597.17-167597.94" - wire $not$issuer_ls180.v:167597$10997_Y - attribute \src "issuer_ls180.v:167600.17-167600.94" - wire $not$issuer_ls180.v:167600$11000_Y - attribute \src "issuer_ls180.v:167596.17-167596.100" - wire $or$issuer_ls180.v:167596$10996_Y - attribute \src "issuer_ls180.v:167599.17-167599.99" - wire $or$issuer_ls180.v:167599$10999_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:167567.7-167567.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:167598$10998 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:167598$10998_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:167597$10997 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_reset - connect \Y $not$issuer_ls180.v:167597$10997_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:167600$11000 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_reset - connect \Y $not$issuer_ls180.v:167600$11000_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:167596$10996 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_reset - connect \B \q_int - connect \Y $or$issuer_ls180.v:167596$10996_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:167599$10999 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_reset - connect \Y $or$issuer_ls180.v:167599$10999_Y - end - attribute \src "issuer_ls180.v:167567.7-167567.20" - process $proc$issuer_ls180.v:167567$11005 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:167583.7-167583.19" - process $proc$issuer_ls180.v:167583$11006 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:167601.3-167602.27" - process $proc$issuer_ls180.v:167601$11001 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:167603.3-167611.6" - process $proc$issuer_ls180.v:167603$11002 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$11003 $1\q_int$next[0:0]$11004 - attribute \src "issuer_ls180.v:167604.5-167604.29" - switch \initial - attribute \src "issuer_ls180.v:167604.9-167604.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$11004 1'0 - case - assign $1\q_int$next[0:0]$11004 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$11003 - end - connect \$9 $or$issuer_ls180.v:167596$10996_Y - connect \$1 $not$issuer_ls180.v:167597$10997_Y - connect \$3 $and$issuer_ls180.v:167598$10998_Y - connect \$5 $or$issuer_ls180.v:167599$10999_Y - connect \$7 $not$issuer_ls180.v:167600$11000_Y - connect \qlq_reset \$9 - connect \qn_reset \$7 - connect \q_reset \q_int -end -attribute \src "issuer_ls180.v:167619.1-168206.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask" -attribute \generator "nMigen" -module \right_mask - attribute \src "issuer_ls180.v:167620.7-167620.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire width 64 $0\mask[63:0] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $10\mask[9:9] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $11\mask[10:10] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $12\mask[11:11] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $13\mask[12:12] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $14\mask[13:13] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $15\mask[14:14] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $16\mask[15:15] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $17\mask[16:16] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $18\mask[17:17] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $19\mask[18:18] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $1\mask[0:0] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $20\mask[19:19] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $21\mask[20:20] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $22\mask[21:21] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $23\mask[22:22] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $24\mask[23:23] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $25\mask[24:24] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $26\mask[25:25] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $27\mask[26:26] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $28\mask[27:27] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $29\mask[28:28] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $2\mask[1:1] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $30\mask[29:29] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $31\mask[30:30] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $32\mask[31:31] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $33\mask[32:32] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $34\mask[33:33] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $35\mask[34:34] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $36\mask[35:35] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $37\mask[36:36] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $38\mask[37:37] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $39\mask[38:38] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $3\mask[2:2] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $40\mask[39:39] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $41\mask[40:40] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $42\mask[41:41] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $43\mask[42:42] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $44\mask[43:43] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $45\mask[44:44] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $46\mask[45:45] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $47\mask[46:46] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $48\mask[47:47] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $49\mask[48:48] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $4\mask[3:3] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $50\mask[49:49] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $51\mask[50:50] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $52\mask[51:51] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $53\mask[52:52] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $54\mask[53:53] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $55\mask[54:54] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $56\mask[55:55] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $57\mask[56:56] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $58\mask[57:57] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $59\mask[58:58] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $5\mask[4:4] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $60\mask[59:59] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $61\mask[60:60] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $62\mask[61:61] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $63\mask[62:62] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $64\mask[63:63] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $6\mask[5:5] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $7\mask[6:6] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $8\mask[7:7] - attribute \src "issuer_ls180.v:167818.3-168205.6" - wire $9\mask[8:8] - attribute \src "issuer_ls180.v:167754.17-167754.96" - wire $gt$issuer_ls180.v:167754$11007_Y - attribute \src "issuer_ls180.v:167755.18-167755.98" - wire $gt$issuer_ls180.v:167755$11008_Y - attribute \src "issuer_ls180.v:167756.19-167756.99" - wire $gt$issuer_ls180.v:167756$11009_Y - attribute \src "issuer_ls180.v:167757.19-167757.99" - wire $gt$issuer_ls180.v:167757$11010_Y - attribute \src "issuer_ls180.v:167758.19-167758.99" - wire $gt$issuer_ls180.v:167758$11011_Y - attribute \src "issuer_ls180.v:167759.19-167759.99" - wire $gt$issuer_ls180.v:167759$11012_Y - attribute \src "issuer_ls180.v:167760.19-167760.99" - wire $gt$issuer_ls180.v:167760$11013_Y - attribute \src "issuer_ls180.v:167761.19-167761.99" - wire $gt$issuer_ls180.v:167761$11014_Y - attribute \src "issuer_ls180.v:167762.19-167762.99" - wire $gt$issuer_ls180.v:167762$11015_Y - attribute \src "issuer_ls180.v:167763.19-167763.99" - wire $gt$issuer_ls180.v:167763$11016_Y - attribute \src "issuer_ls180.v:167764.19-167764.99" - wire $gt$issuer_ls180.v:167764$11017_Y - attribute \src "issuer_ls180.v:167765.18-167765.97" - wire $gt$issuer_ls180.v:167765$11018_Y - attribute \src "issuer_ls180.v:167766.19-167766.99" - wire $gt$issuer_ls180.v:167766$11019_Y - attribute \src "issuer_ls180.v:167767.19-167767.99" - wire $gt$issuer_ls180.v:167767$11020_Y - attribute \src "issuer_ls180.v:167768.19-167768.99" - wire $gt$issuer_ls180.v:167768$11021_Y - attribute \src "issuer_ls180.v:167769.19-167769.99" - wire $gt$issuer_ls180.v:167769$11022_Y - attribute \src "issuer_ls180.v:167770.19-167770.99" - wire $gt$issuer_ls180.v:167770$11023_Y - attribute \src "issuer_ls180.v:167771.18-167771.97" - wire $gt$issuer_ls180.v:167771$11024_Y - attribute \src "issuer_ls180.v:167772.18-167772.97" - wire $gt$issuer_ls180.v:167772$11025_Y - attribute \src "issuer_ls180.v:167773.18-167773.97" - wire $gt$issuer_ls180.v:167773$11026_Y - attribute \src "issuer_ls180.v:167774.17-167774.96" - wire $gt$issuer_ls180.v:167774$11027_Y - attribute \src "issuer_ls180.v:167775.18-167775.97" - wire $gt$issuer_ls180.v:167775$11028_Y - attribute \src "issuer_ls180.v:167776.18-167776.97" - wire $gt$issuer_ls180.v:167776$11029_Y - attribute \src "issuer_ls180.v:167777.18-167777.97" - wire $gt$issuer_ls180.v:167777$11030_Y - attribute \src "issuer_ls180.v:167778.18-167778.97" - wire $gt$issuer_ls180.v:167778$11031_Y - attribute \src "issuer_ls180.v:167779.18-167779.97" - wire $gt$issuer_ls180.v:167779$11032_Y - attribute \src "issuer_ls180.v:167780.18-167780.97" - wire $gt$issuer_ls180.v:167780$11033_Y - attribute \src "issuer_ls180.v:167781.18-167781.97" - wire $gt$issuer_ls180.v:167781$11034_Y - attribute \src "issuer_ls180.v:167782.18-167782.98" - wire $gt$issuer_ls180.v:167782$11035_Y - attribute \src "issuer_ls180.v:167783.18-167783.98" - wire $gt$issuer_ls180.v:167783$11036_Y - attribute \src "issuer_ls180.v:167784.18-167784.98" - wire $gt$issuer_ls180.v:167784$11037_Y - attribute \src "issuer_ls180.v:167785.17-167785.96" - wire $gt$issuer_ls180.v:167785$11038_Y - attribute \src "issuer_ls180.v:167786.18-167786.98" - wire $gt$issuer_ls180.v:167786$11039_Y - attribute \src "issuer_ls180.v:167787.18-167787.98" - wire $gt$issuer_ls180.v:167787$11040_Y - attribute \src "issuer_ls180.v:167788.18-167788.98" - wire $gt$issuer_ls180.v:167788$11041_Y - attribute \src "issuer_ls180.v:167789.18-167789.98" - wire $gt$issuer_ls180.v:167789$11042_Y - attribute \src "issuer_ls180.v:167790.18-167790.98" - wire $gt$issuer_ls180.v:167790$11043_Y - attribute \src "issuer_ls180.v:167791.18-167791.98" - wire $gt$issuer_ls180.v:167791$11044_Y - attribute \src "issuer_ls180.v:167792.18-167792.98" - wire $gt$issuer_ls180.v:167792$11045_Y - attribute \src "issuer_ls180.v:167793.18-167793.98" - wire $gt$issuer_ls180.v:167793$11046_Y - attribute \src "issuer_ls180.v:167794.18-167794.98" - wire $gt$issuer_ls180.v:167794$11047_Y - attribute \src "issuer_ls180.v:167795.18-167795.98" - wire $gt$issuer_ls180.v:167795$11048_Y - attribute \src "issuer_ls180.v:167796.17-167796.96" - wire $gt$issuer_ls180.v:167796$11049_Y - attribute \src "issuer_ls180.v:167797.18-167797.98" - wire $gt$issuer_ls180.v:167797$11050_Y - attribute \src "issuer_ls180.v:167798.18-167798.98" - wire $gt$issuer_ls180.v:167798$11051_Y - attribute \src "issuer_ls180.v:167799.18-167799.98" - wire $gt$issuer_ls180.v:167799$11052_Y - attribute \src "issuer_ls180.v:167800.18-167800.98" - wire $gt$issuer_ls180.v:167800$11053_Y - attribute \src "issuer_ls180.v:167801.18-167801.98" - wire $gt$issuer_ls180.v:167801$11054_Y - attribute \src "issuer_ls180.v:167802.18-167802.98" - wire $gt$issuer_ls180.v:167802$11055_Y - attribute \src "issuer_ls180.v:167803.18-167803.98" - wire $gt$issuer_ls180.v:167803$11056_Y - attribute \src "issuer_ls180.v:167804.18-167804.98" - wire $gt$issuer_ls180.v:167804$11057_Y - attribute \src "issuer_ls180.v:167805.18-167805.98" - wire $gt$issuer_ls180.v:167805$11058_Y - attribute \src "issuer_ls180.v:167806.18-167806.98" - wire $gt$issuer_ls180.v:167806$11059_Y - attribute \src "issuer_ls180.v:167807.17-167807.96" - wire $gt$issuer_ls180.v:167807$11060_Y - attribute \src "issuer_ls180.v:167808.18-167808.98" - wire $gt$issuer_ls180.v:167808$11061_Y - attribute \src "issuer_ls180.v:167809.18-167809.98" - wire $gt$issuer_ls180.v:167809$11062_Y - attribute \src "issuer_ls180.v:167810.18-167810.98" - wire $gt$issuer_ls180.v:167810$11063_Y - attribute \src "issuer_ls180.v:167811.18-167811.98" - wire $gt$issuer_ls180.v:167811$11064_Y - attribute \src "issuer_ls180.v:167812.18-167812.98" - wire $gt$issuer_ls180.v:167812$11065_Y - attribute \src "issuer_ls180.v:167813.18-167813.98" - wire $gt$issuer_ls180.v:167813$11066_Y - attribute \src "issuer_ls180.v:167814.18-167814.98" - wire $gt$issuer_ls180.v:167814$11067_Y - attribute \src "issuer_ls180.v:167815.18-167815.98" - wire $gt$issuer_ls180.v:167815$11068_Y - attribute \src "issuer_ls180.v:167816.18-167816.98" - wire $gt$issuer_ls180.v:167816$11069_Y - attribute \src "issuer_ls180.v:167817.18-167817.98" - wire $gt$issuer_ls180.v:167817$11070_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$101 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$103 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$105 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$107 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$109 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$111 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$113 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$115 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$117 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$119 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$121 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$123 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$125 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$127 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$37 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$39 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$41 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$43 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$45 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$47 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$53 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$55 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$57 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$59 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$61 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$63 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$65 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$67 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$69 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$71 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$73 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$75 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$77 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$79 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$83 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$85 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$87 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$89 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$91 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$93 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$95 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$97 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$99 - attribute \src "issuer_ls180.v:167620.7-167620.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:12" - wire width 64 output 1 \mask - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:11" - wire width 7 input 2 \shift - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167754$11007 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 3'100 - connect \Y $gt$issuer_ls180.v:167754$11007_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167755$11008 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110001 - connect \Y $gt$issuer_ls180.v:167755$11008_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167756$11009 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110010 - connect \Y $gt$issuer_ls180.v:167756$11009_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167757$11010 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110011 - connect \Y $gt$issuer_ls180.v:167757$11010_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167758$11011 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110100 - connect \Y $gt$issuer_ls180.v:167758$11011_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167759$11012 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110101 - connect \Y $gt$issuer_ls180.v:167759$11012_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167760$11013 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110110 - connect \Y $gt$issuer_ls180.v:167760$11013_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167761$11014 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110111 - connect \Y $gt$issuer_ls180.v:167761$11014_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167762$11015 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111000 - connect \Y $gt$issuer_ls180.v:167762$11015_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167763$11016 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111001 - connect \Y $gt$issuer_ls180.v:167763$11016_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167764$11017 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111010 - connect \Y $gt$issuer_ls180.v:167764$11017_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167765$11018 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 3'101 - connect \Y $gt$issuer_ls180.v:167765$11018_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167766$11019 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111011 - connect \Y $gt$issuer_ls180.v:167766$11019_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167767$11020 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111100 - connect \Y $gt$issuer_ls180.v:167767$11020_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167768$11021 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111101 - connect \Y $gt$issuer_ls180.v:167768$11021_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167769$11022 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111110 - connect \Y $gt$issuer_ls180.v:167769$11022_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167770$11023 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111111 - connect \Y $gt$issuer_ls180.v:167770$11023_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167771$11024 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 3'110 - connect \Y $gt$issuer_ls180.v:167771$11024_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167772$11025 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 3'111 - connect \Y $gt$issuer_ls180.v:167772$11025_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167773$11026 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1000 - connect \Y $gt$issuer_ls180.v:167773$11026_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167774$11027 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 1'0 - connect \Y $gt$issuer_ls180.v:167774$11027_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167775$11028 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1001 - connect \Y $gt$issuer_ls180.v:167775$11028_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167776$11029 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1010 - connect \Y $gt$issuer_ls180.v:167776$11029_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167777$11030 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1011 - connect \Y $gt$issuer_ls180.v:167777$11030_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167778$11031 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1100 - connect \Y $gt$issuer_ls180.v:167778$11031_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167779$11032 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1101 - connect \Y $gt$issuer_ls180.v:167779$11032_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167780$11033 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1110 - connect \Y $gt$issuer_ls180.v:167780$11033_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167781$11034 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1111 - connect \Y $gt$issuer_ls180.v:167781$11034_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167782$11035 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10000 - connect \Y $gt$issuer_ls180.v:167782$11035_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167783$11036 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10001 - connect \Y $gt$issuer_ls180.v:167783$11036_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167784$11037 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10010 - connect \Y $gt$issuer_ls180.v:167784$11037_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167785$11038 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 1'1 - connect \Y $gt$issuer_ls180.v:167785$11038_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167786$11039 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10011 - connect \Y $gt$issuer_ls180.v:167786$11039_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167787$11040 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10100 - connect \Y $gt$issuer_ls180.v:167787$11040_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167788$11041 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10101 - connect \Y $gt$issuer_ls180.v:167788$11041_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167789$11042 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10110 - connect \Y $gt$issuer_ls180.v:167789$11042_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167790$11043 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10111 - connect \Y $gt$issuer_ls180.v:167790$11043_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167791$11044 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11000 - connect \Y $gt$issuer_ls180.v:167791$11044_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167792$11045 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11001 - connect \Y $gt$issuer_ls180.v:167792$11045_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167793$11046 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11010 - connect \Y $gt$issuer_ls180.v:167793$11046_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167794$11047 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11011 - connect \Y $gt$issuer_ls180.v:167794$11047_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167795$11048 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11100 - connect \Y $gt$issuer_ls180.v:167795$11048_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167796$11049 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 2'10 - connect \Y $gt$issuer_ls180.v:167796$11049_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167797$11050 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11101 - connect \Y $gt$issuer_ls180.v:167797$11050_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167798$11051 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11110 - connect \Y $gt$issuer_ls180.v:167798$11051_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167799$11052 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11111 - connect \Y $gt$issuer_ls180.v:167799$11052_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167800$11053 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100000 - connect \Y $gt$issuer_ls180.v:167800$11053_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167801$11054 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100001 - connect \Y $gt$issuer_ls180.v:167801$11054_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167802$11055 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100010 - connect \Y $gt$issuer_ls180.v:167802$11055_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167803$11056 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100011 - connect \Y $gt$issuer_ls180.v:167803$11056_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167804$11057 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100100 - connect \Y $gt$issuer_ls180.v:167804$11057_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167805$11058 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100101 - connect \Y $gt$issuer_ls180.v:167805$11058_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167806$11059 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100110 - connect \Y $gt$issuer_ls180.v:167806$11059_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167807$11060 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 2'11 - connect \Y $gt$issuer_ls180.v:167807$11060_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167808$11061 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100111 - connect \Y $gt$issuer_ls180.v:167808$11061_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167809$11062 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101000 - connect \Y $gt$issuer_ls180.v:167809$11062_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167810$11063 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101001 - connect \Y $gt$issuer_ls180.v:167810$11063_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167811$11064 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101010 - connect \Y $gt$issuer_ls180.v:167811$11064_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167812$11065 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101011 - connect \Y $gt$issuer_ls180.v:167812$11065_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167813$11066 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101100 - connect \Y $gt$issuer_ls180.v:167813$11066_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167814$11067 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101101 - connect \Y $gt$issuer_ls180.v:167814$11067_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167815$11068 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101110 - connect \Y $gt$issuer_ls180.v:167815$11068_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167816$11069 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101111 - connect \Y $gt$issuer_ls180.v:167816$11069_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$issuer_ls180.v:167817$11070 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110000 - connect \Y $gt$issuer_ls180.v:167817$11070_Y - end - attribute \src "issuer_ls180.v:167620.7-167620.20" - process $proc$issuer_ls180.v:167620$11072 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:167818.3-168205.6" - process $proc$issuer_ls180.v:167818$11071 - assign { } { } - assign { } { } - assign $0\mask[63:0] [0] $1\mask[0:0] - assign $0\mask[63:0] [1] $2\mask[1:1] - assign $0\mask[63:0] [2] $3\mask[2:2] - assign $0\mask[63:0] [3] $4\mask[3:3] - assign $0\mask[63:0] [4] $5\mask[4:4] - assign $0\mask[63:0] [5] $6\mask[5:5] - assign $0\mask[63:0] [6] $7\mask[6:6] - assign $0\mask[63:0] [7] $8\mask[7:7] - assign $0\mask[63:0] [8] $9\mask[8:8] - assign $0\mask[63:0] [9] $10\mask[9:9] - assign $0\mask[63:0] [10] $11\mask[10:10] - assign $0\mask[63:0] [11] $12\mask[11:11] - assign $0\mask[63:0] [12] $13\mask[12:12] - assign $0\mask[63:0] [13] $14\mask[13:13] - assign $0\mask[63:0] [14] $15\mask[14:14] - assign $0\mask[63:0] [15] $16\mask[15:15] - assign $0\mask[63:0] [16] $17\mask[16:16] - assign $0\mask[63:0] [17] $18\mask[17:17] - assign $0\mask[63:0] [18] $19\mask[18:18] - assign $0\mask[63:0] [19] $20\mask[19:19] - assign $0\mask[63:0] [20] $21\mask[20:20] - assign $0\mask[63:0] [21] $22\mask[21:21] - assign $0\mask[63:0] [22] $23\mask[22:22] - assign $0\mask[63:0] [23] $24\mask[23:23] - assign $0\mask[63:0] [24] $25\mask[24:24] - assign $0\mask[63:0] [25] $26\mask[25:25] - assign $0\mask[63:0] [26] $27\mask[26:26] - assign $0\mask[63:0] [27] $28\mask[27:27] - assign $0\mask[63:0] [28] $29\mask[28:28] - assign $0\mask[63:0] [29] $30\mask[29:29] - assign $0\mask[63:0] [30] $31\mask[30:30] - assign $0\mask[63:0] [31] $32\mask[31:31] - assign $0\mask[63:0] [32] $33\mask[32:32] - assign $0\mask[63:0] [33] $34\mask[33:33] - assign $0\mask[63:0] [34] $35\mask[34:34] - assign $0\mask[63:0] [35] $36\mask[35:35] - assign $0\mask[63:0] [36] $37\mask[36:36] - assign $0\mask[63:0] [37] $38\mask[37:37] - assign $0\mask[63:0] [38] $39\mask[38:38] - assign $0\mask[63:0] [39] $40\mask[39:39] - assign $0\mask[63:0] [40] $41\mask[40:40] - assign $0\mask[63:0] [41] $42\mask[41:41] - assign $0\mask[63:0] [42] $43\mask[42:42] - assign $0\mask[63:0] [43] $44\mask[43:43] - assign $0\mask[63:0] [44] $45\mask[44:44] - assign $0\mask[63:0] [45] $46\mask[45:45] - assign $0\mask[63:0] [46] $47\mask[46:46] - assign $0\mask[63:0] [47] $48\mask[47:47] - assign $0\mask[63:0] [48] $49\mask[48:48] - assign $0\mask[63:0] [49] $50\mask[49:49] - assign $0\mask[63:0] [50] $51\mask[50:50] - assign $0\mask[63:0] [51] $52\mask[51:51] - assign $0\mask[63:0] [52] $53\mask[52:52] - assign $0\mask[63:0] [53] $54\mask[53:53] - assign $0\mask[63:0] [54] $55\mask[54:54] - assign $0\mask[63:0] [55] $56\mask[55:55] - assign $0\mask[63:0] [56] $57\mask[56:56] - assign $0\mask[63:0] [57] $58\mask[57:57] - assign $0\mask[63:0] [58] $59\mask[58:58] - assign $0\mask[63:0] [59] $60\mask[59:59] - assign $0\mask[63:0] [60] $61\mask[60:60] - assign $0\mask[63:0] [61] $62\mask[61:61] - assign $0\mask[63:0] [62] $63\mask[62:62] - assign $0\mask[63:0] [63] $64\mask[63:63] - attribute \src "issuer_ls180.v:167819.5-167819.29" - switch \initial - attribute \src "issuer_ls180.v:167819.9-167819.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\mask[0:0] 1'1 - case - assign $1\mask[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\mask[1:1] 1'1 - case - assign $2\mask[1:1] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$5 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\mask[2:2] 1'1 - case - assign $3\mask[2:2] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\mask[3:3] 1'1 - case - assign $4\mask[3:3] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$9 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\mask[4:4] 1'1 - case - assign $5\mask[4:4] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$11 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\mask[5:5] 1'1 - case - assign $6\mask[5:5] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$13 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\mask[6:6] 1'1 - case - assign $7\mask[6:6] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$15 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $8\mask[7:7] 1'1 - case - assign $8\mask[7:7] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$17 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $9\mask[8:8] 1'1 - case - assign $9\mask[8:8] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$19 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $10\mask[9:9] 1'1 - case - assign $10\mask[9:9] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$21 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $11\mask[10:10] 1'1 - case - assign $11\mask[10:10] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$23 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $12\mask[11:11] 1'1 - case - assign $12\mask[11:11] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$25 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $13\mask[12:12] 1'1 - case - assign $13\mask[12:12] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$27 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $14\mask[13:13] 1'1 - case - assign $14\mask[13:13] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$29 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $15\mask[14:14] 1'1 - case - assign $15\mask[14:14] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$31 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $16\mask[15:15] 1'1 - case - assign $16\mask[15:15] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$33 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $17\mask[16:16] 1'1 - case - assign $17\mask[16:16] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$35 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $18\mask[17:17] 1'1 - case - assign $18\mask[17:17] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$37 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $19\mask[18:18] 1'1 - case - assign $19\mask[18:18] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$39 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $20\mask[19:19] 1'1 - case - assign $20\mask[19:19] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$41 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $21\mask[20:20] 1'1 - case - assign $21\mask[20:20] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$43 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $22\mask[21:21] 1'1 - case - assign $22\mask[21:21] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$45 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $23\mask[22:22] 1'1 - case - assign $23\mask[22:22] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$47 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $24\mask[23:23] 1'1 - case - assign $24\mask[23:23] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$49 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $25\mask[24:24] 1'1 - case - assign $25\mask[24:24] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$51 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $26\mask[25:25] 1'1 - case - assign $26\mask[25:25] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$53 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $27\mask[26:26] 1'1 - case - assign $27\mask[26:26] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$55 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $28\mask[27:27] 1'1 - case - assign $28\mask[27:27] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$57 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $29\mask[28:28] 1'1 - case - assign $29\mask[28:28] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$59 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $30\mask[29:29] 1'1 - case - assign $30\mask[29:29] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$61 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $31\mask[30:30] 1'1 - case - assign $31\mask[30:30] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$63 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $32\mask[31:31] 1'1 - case - assign $32\mask[31:31] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$65 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $33\mask[32:32] 1'1 - case - assign $33\mask[32:32] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$67 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $34\mask[33:33] 1'1 - case - assign $34\mask[33:33] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$69 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $35\mask[34:34] 1'1 - case - assign $35\mask[34:34] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$71 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $36\mask[35:35] 1'1 - case - assign $36\mask[35:35] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$73 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $37\mask[36:36] 1'1 - case - assign $37\mask[36:36] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$75 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $38\mask[37:37] 1'1 - case - assign $38\mask[37:37] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$77 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $39\mask[38:38] 1'1 - case - assign $39\mask[38:38] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$79 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $40\mask[39:39] 1'1 - case - assign $40\mask[39:39] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$81 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $41\mask[40:40] 1'1 - case - assign $41\mask[40:40] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$83 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $42\mask[41:41] 1'1 - case - assign $42\mask[41:41] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$85 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $43\mask[42:42] 1'1 - case - assign $43\mask[42:42] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$87 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $44\mask[43:43] 1'1 - case - assign $44\mask[43:43] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$89 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $45\mask[44:44] 1'1 - case - assign $45\mask[44:44] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$91 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $46\mask[45:45] 1'1 - case - assign $46\mask[45:45] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$93 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $47\mask[46:46] 1'1 - case - assign $47\mask[46:46] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$95 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $48\mask[47:47] 1'1 - case - assign $48\mask[47:47] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$97 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $49\mask[48:48] 1'1 - case - assign $49\mask[48:48] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$99 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $50\mask[49:49] 1'1 - case - assign $50\mask[49:49] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $51\mask[50:50] 1'1 - case - assign $51\mask[50:50] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$103 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $52\mask[51:51] 1'1 - case - assign $52\mask[51:51] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$105 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $53\mask[52:52] 1'1 - case - assign $53\mask[52:52] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$107 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $54\mask[53:53] 1'1 - case - assign $54\mask[53:53] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$109 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $55\mask[54:54] 1'1 - case - assign $55\mask[54:54] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $56\mask[55:55] 1'1 - case - assign $56\mask[55:55] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$113 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $57\mask[56:56] 1'1 - case - assign $57\mask[56:56] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$115 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $58\mask[57:57] 1'1 - case - assign $58\mask[57:57] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$117 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $59\mask[58:58] 1'1 - case - assign $59\mask[58:58] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$119 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $60\mask[59:59] 1'1 - case - assign $60\mask[59:59] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$121 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $61\mask[60:60] 1'1 - case - assign $61\mask[60:60] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$123 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $62\mask[61:61] 1'1 - case - assign $62\mask[61:61] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$125 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $63\mask[62:62] 1'1 - case - assign $63\mask[62:62] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$127 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $64\mask[63:63] 1'1 - case - assign $64\mask[63:63] 1'0 - end - sync always - update \mask $0\mask[63:0] - end - connect \$9 $gt$issuer_ls180.v:167754$11007_Y - connect \$99 $gt$issuer_ls180.v:167755$11008_Y - connect \$101 $gt$issuer_ls180.v:167756$11009_Y - connect \$103 $gt$issuer_ls180.v:167757$11010_Y - connect \$105 $gt$issuer_ls180.v:167758$11011_Y - connect \$107 $gt$issuer_ls180.v:167759$11012_Y - connect \$109 $gt$issuer_ls180.v:167760$11013_Y - connect \$111 $gt$issuer_ls180.v:167761$11014_Y - connect \$113 $gt$issuer_ls180.v:167762$11015_Y - connect \$115 $gt$issuer_ls180.v:167763$11016_Y - connect \$117 $gt$issuer_ls180.v:167764$11017_Y - connect \$11 $gt$issuer_ls180.v:167765$11018_Y - connect \$119 $gt$issuer_ls180.v:167766$11019_Y - connect \$121 $gt$issuer_ls180.v:167767$11020_Y - connect \$123 $gt$issuer_ls180.v:167768$11021_Y - connect \$125 $gt$issuer_ls180.v:167769$11022_Y - connect \$127 $gt$issuer_ls180.v:167770$11023_Y - connect \$13 $gt$issuer_ls180.v:167771$11024_Y - connect \$15 $gt$issuer_ls180.v:167772$11025_Y - connect \$17 $gt$issuer_ls180.v:167773$11026_Y - connect \$1 $gt$issuer_ls180.v:167774$11027_Y - connect \$19 $gt$issuer_ls180.v:167775$11028_Y - connect \$21 $gt$issuer_ls180.v:167776$11029_Y - connect \$23 $gt$issuer_ls180.v:167777$11030_Y - connect \$25 $gt$issuer_ls180.v:167778$11031_Y - connect \$27 $gt$issuer_ls180.v:167779$11032_Y - connect \$29 $gt$issuer_ls180.v:167780$11033_Y - connect \$31 $gt$issuer_ls180.v:167781$11034_Y - connect \$33 $gt$issuer_ls180.v:167782$11035_Y - connect \$35 $gt$issuer_ls180.v:167783$11036_Y - connect \$37 $gt$issuer_ls180.v:167784$11037_Y - connect \$3 $gt$issuer_ls180.v:167785$11038_Y - connect \$39 $gt$issuer_ls180.v:167786$11039_Y - connect \$41 $gt$issuer_ls180.v:167787$11040_Y - connect \$43 $gt$issuer_ls180.v:167788$11041_Y - connect \$45 $gt$issuer_ls180.v:167789$11042_Y - connect \$47 $gt$issuer_ls180.v:167790$11043_Y - connect \$49 $gt$issuer_ls180.v:167791$11044_Y - connect \$51 $gt$issuer_ls180.v:167792$11045_Y - connect \$53 $gt$issuer_ls180.v:167793$11046_Y - connect \$55 $gt$issuer_ls180.v:167794$11047_Y - connect \$57 $gt$issuer_ls180.v:167795$11048_Y - connect \$5 $gt$issuer_ls180.v:167796$11049_Y - connect \$59 $gt$issuer_ls180.v:167797$11050_Y - connect \$61 $gt$issuer_ls180.v:167798$11051_Y - connect \$63 $gt$issuer_ls180.v:167799$11052_Y - connect \$65 $gt$issuer_ls180.v:167800$11053_Y - connect \$67 $gt$issuer_ls180.v:167801$11054_Y - connect \$69 $gt$issuer_ls180.v:167802$11055_Y - connect \$71 $gt$issuer_ls180.v:167803$11056_Y - connect \$73 $gt$issuer_ls180.v:167804$11057_Y - connect \$75 $gt$issuer_ls180.v:167805$11058_Y - connect \$77 $gt$issuer_ls180.v:167806$11059_Y - connect \$7 $gt$issuer_ls180.v:167807$11060_Y - connect \$79 $gt$issuer_ls180.v:167808$11061_Y - connect \$81 $gt$issuer_ls180.v:167809$11062_Y - connect \$83 $gt$issuer_ls180.v:167810$11063_Y - connect \$85 $gt$issuer_ls180.v:167811$11064_Y - connect \$87 $gt$issuer_ls180.v:167812$11065_Y - connect \$89 $gt$issuer_ls180.v:167813$11066_Y - connect \$91 $gt$issuer_ls180.v:167814$11067_Y - connect \$93 $gt$issuer_ls180.v:167815$11068_Y - connect \$95 $gt$issuer_ls180.v:167816$11069_Y - connect \$97 $gt$issuer_ls180.v:167817$11070_Y -end -attribute \src "issuer_ls180.v:168210.1-168268.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.rok_l" -attribute \generator "nMigen" -module \rok_l - attribute \src "issuer_ls180.v:168211.7-168211.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:168256.3-168264.6" - wire $0\q_int$next[0:0]$11083 - attribute \src "issuer_ls180.v:168254.3-168255.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:168256.3-168264.6" - wire $1\q_int$next[0:0]$11084 - attribute \src "issuer_ls180.v:168233.7-168233.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:168246.17-168246.96" - wire $and$issuer_ls180.v:168246$11073_Y - attribute \src "issuer_ls180.v:168251.17-168251.96" - wire $and$issuer_ls180.v:168251$11078_Y - attribute \src "issuer_ls180.v:168248.18-168248.94" - wire $not$issuer_ls180.v:168248$11075_Y - attribute \src "issuer_ls180.v:168250.17-168250.93" - wire $not$issuer_ls180.v:168250$11077_Y - attribute \src "issuer_ls180.v:168253.17-168253.93" - wire $not$issuer_ls180.v:168253$11080_Y - attribute \src "issuer_ls180.v:168247.18-168247.99" - wire $or$issuer_ls180.v:168247$11074_Y - attribute \src "issuer_ls180.v:168249.18-168249.100" - wire $or$issuer_ls180.v:168249$11076_Y - attribute \src "issuer_ls180.v:168252.17-168252.98" - wire $or$issuer_ls180.v:168252$11079_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:168211.7-168211.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:168246$11073 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:168246$11073_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:168251$11078 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:168251$11078_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:168248$11075 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $not$issuer_ls180.v:168248$11075_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:168250$11077 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$issuer_ls180.v:168250$11077_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:168253$11080 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$issuer_ls180.v:168253$11080_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:168247$11074 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rdok - connect \Y $or$issuer_ls180.v:168247$11074_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:168249$11076 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $or$issuer_ls180.v:168249$11076_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:168252$11079 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rdok - connect \Y $or$issuer_ls180.v:168252$11079_Y - end - attribute \src "issuer_ls180.v:168211.7-168211.20" - process $proc$issuer_ls180.v:168211$11085 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:168233.7-168233.19" - process $proc$issuer_ls180.v:168233$11086 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:168254.3-168255.27" - process $proc$issuer_ls180.v:168254$11081 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:168256.3-168264.6" - process $proc$issuer_ls180.v:168256$11082 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$11083 $1\q_int$next[0:0]$11084 - attribute \src "issuer_ls180.v:168257.5-168257.29" - switch \initial - attribute \src "issuer_ls180.v:168257.9-168257.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$11084 1'0 - case - assign $1\q_int$next[0:0]$11084 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$11083 - end - connect \$9 $and$issuer_ls180.v:168246$11073_Y - connect \$11 $or$issuer_ls180.v:168247$11074_Y - connect \$13 $not$issuer_ls180.v:168248$11075_Y - connect \$15 $or$issuer_ls180.v:168249$11076_Y - connect \$1 $not$issuer_ls180.v:168250$11077_Y - connect \$3 $and$issuer_ls180.v:168251$11078_Y - connect \$5 $or$issuer_ls180.v:168252$11079_Y - connect \$7 $not$issuer_ls180.v:168253$11080_Y - connect \qlq_rdok \$15 - connect \qn_rdok \$13 - connect \q_rdok \$11 -end -attribute \src "issuer_ls180.v:168272.1-168330.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rok_l" -attribute \generator "nMigen" -module \rok_l$102 - attribute \src "issuer_ls180.v:168273.7-168273.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:168318.3-168326.6" - wire $0\q_int$next[0:0]$11097 - attribute \src "issuer_ls180.v:168316.3-168317.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:168318.3-168326.6" - wire $1\q_int$next[0:0]$11098 - attribute \src "issuer_ls180.v:168295.7-168295.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:168308.17-168308.96" - wire $and$issuer_ls180.v:168308$11087_Y - attribute \src "issuer_ls180.v:168313.17-168313.96" - wire $and$issuer_ls180.v:168313$11092_Y - attribute \src "issuer_ls180.v:168310.18-168310.94" - wire $not$issuer_ls180.v:168310$11089_Y - attribute \src "issuer_ls180.v:168312.17-168312.93" - wire $not$issuer_ls180.v:168312$11091_Y - attribute \src "issuer_ls180.v:168315.17-168315.93" - wire $not$issuer_ls180.v:168315$11094_Y - attribute \src "issuer_ls180.v:168309.18-168309.99" - wire $or$issuer_ls180.v:168309$11088_Y - attribute \src "issuer_ls180.v:168311.18-168311.100" - wire $or$issuer_ls180.v:168311$11090_Y - attribute \src "issuer_ls180.v:168314.17-168314.98" - wire $or$issuer_ls180.v:168314$11093_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:168273.7-168273.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:168308$11087 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:168308$11087_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:168313$11092 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:168313$11092_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:168310$11089 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $not$issuer_ls180.v:168310$11089_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:168312$11091 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$issuer_ls180.v:168312$11091_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:168315$11094 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$issuer_ls180.v:168315$11094_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:168309$11088 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rdok - connect \Y $or$issuer_ls180.v:168309$11088_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:168311$11090 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $or$issuer_ls180.v:168311$11090_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:168314$11093 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rdok - connect \Y $or$issuer_ls180.v:168314$11093_Y - end - attribute \src "issuer_ls180.v:168273.7-168273.20" - process $proc$issuer_ls180.v:168273$11099 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:168295.7-168295.19" - process $proc$issuer_ls180.v:168295$11100 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:168316.3-168317.27" - process $proc$issuer_ls180.v:168316$11095 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:168318.3-168326.6" - process $proc$issuer_ls180.v:168318$11096 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$11097 $1\q_int$next[0:0]$11098 - attribute \src "issuer_ls180.v:168319.5-168319.29" - switch \initial - attribute \src "issuer_ls180.v:168319.9-168319.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$11098 1'0 - case - assign $1\q_int$next[0:0]$11098 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$11097 - end - connect \$9 $and$issuer_ls180.v:168308$11087_Y - connect \$11 $or$issuer_ls180.v:168309$11088_Y - connect \$13 $not$issuer_ls180.v:168310$11089_Y - connect \$15 $or$issuer_ls180.v:168311$11090_Y - connect \$1 $not$issuer_ls180.v:168312$11091_Y - connect \$3 $and$issuer_ls180.v:168313$11092_Y - connect \$5 $or$issuer_ls180.v:168314$11093_Y - connect \$7 $not$issuer_ls180.v:168315$11094_Y - connect \qlq_rdok \$15 - connect \qn_rdok \$13 - connect \q_rdok \$11 -end -attribute \src "issuer_ls180.v:168334.1-168392.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rok_l" -attribute \generator "nMigen" -module \rok_l$120 - attribute \src "issuer_ls180.v:168335.7-168335.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:168380.3-168388.6" - wire $0\q_int$next[0:0]$11111 - attribute \src "issuer_ls180.v:168378.3-168379.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:168380.3-168388.6" - wire $1\q_int$next[0:0]$11112 - attribute \src "issuer_ls180.v:168357.7-168357.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:168370.17-168370.96" - wire $and$issuer_ls180.v:168370$11101_Y - attribute \src "issuer_ls180.v:168375.17-168375.96" - wire $and$issuer_ls180.v:168375$11106_Y - attribute \src "issuer_ls180.v:168372.18-168372.94" - wire $not$issuer_ls180.v:168372$11103_Y - attribute \src "issuer_ls180.v:168374.17-168374.93" - wire $not$issuer_ls180.v:168374$11105_Y - attribute \src "issuer_ls180.v:168377.17-168377.93" - wire $not$issuer_ls180.v:168377$11108_Y - attribute \src "issuer_ls180.v:168371.18-168371.99" - wire $or$issuer_ls180.v:168371$11102_Y - attribute \src "issuer_ls180.v:168373.18-168373.100" - wire $or$issuer_ls180.v:168373$11104_Y - attribute \src "issuer_ls180.v:168376.17-168376.98" - wire $or$issuer_ls180.v:168376$11107_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:168335.7-168335.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:168370$11101 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:168370$11101_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:168375$11106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:168375$11106_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:168372$11103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $not$issuer_ls180.v:168372$11103_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:168374$11105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$issuer_ls180.v:168374$11105_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:168377$11108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$issuer_ls180.v:168377$11108_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:168371$11102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rdok - connect \Y $or$issuer_ls180.v:168371$11102_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:168373$11104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $or$issuer_ls180.v:168373$11104_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:168376$11107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rdok - connect \Y $or$issuer_ls180.v:168376$11107_Y - end - attribute \src "issuer_ls180.v:168335.7-168335.20" - process $proc$issuer_ls180.v:168335$11113 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:168357.7-168357.19" - process $proc$issuer_ls180.v:168357$11114 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:168378.3-168379.27" - process $proc$issuer_ls180.v:168378$11109 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:168380.3-168388.6" - process $proc$issuer_ls180.v:168380$11110 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$11111 $1\q_int$next[0:0]$11112 - attribute \src "issuer_ls180.v:168381.5-168381.29" - switch \initial - attribute \src "issuer_ls180.v:168381.9-168381.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$11112 1'0 - case - assign $1\q_int$next[0:0]$11112 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$11111 - end - connect \$9 $and$issuer_ls180.v:168370$11101_Y - connect \$11 $or$issuer_ls180.v:168371$11102_Y - connect \$13 $not$issuer_ls180.v:168372$11103_Y - connect \$15 $or$issuer_ls180.v:168373$11104_Y - connect \$1 $not$issuer_ls180.v:168374$11105_Y - connect \$3 $and$issuer_ls180.v:168375$11106_Y - connect \$5 $or$issuer_ls180.v:168376$11107_Y - connect \$7 $not$issuer_ls180.v:168377$11108_Y - connect \qlq_rdok \$15 - connect \qn_rdok \$13 - connect \q_rdok \$11 -end -attribute \src "issuer_ls180.v:168396.1-168454.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rok_l" -attribute \generator "nMigen" -module \rok_l$14 - attribute \src "issuer_ls180.v:168397.7-168397.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:168442.3-168450.6" - wire $0\q_int$next[0:0]$11125 - attribute \src "issuer_ls180.v:168440.3-168441.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:168442.3-168450.6" - wire $1\q_int$next[0:0]$11126 - attribute \src "issuer_ls180.v:168419.7-168419.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:168432.17-168432.96" - wire $and$issuer_ls180.v:168432$11115_Y - attribute \src "issuer_ls180.v:168437.17-168437.96" - wire $and$issuer_ls180.v:168437$11120_Y - attribute \src "issuer_ls180.v:168434.18-168434.94" - wire $not$issuer_ls180.v:168434$11117_Y - attribute \src "issuer_ls180.v:168436.17-168436.93" - wire $not$issuer_ls180.v:168436$11119_Y - attribute \src "issuer_ls180.v:168439.17-168439.93" - wire $not$issuer_ls180.v:168439$11122_Y - attribute \src "issuer_ls180.v:168433.18-168433.99" - wire $or$issuer_ls180.v:168433$11116_Y - attribute \src "issuer_ls180.v:168435.18-168435.100" - wire $or$issuer_ls180.v:168435$11118_Y - attribute \src "issuer_ls180.v:168438.17-168438.98" - wire $or$issuer_ls180.v:168438$11121_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:168397.7-168397.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:168432$11115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:168432$11115_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:168437$11120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:168437$11120_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:168434$11117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $not$issuer_ls180.v:168434$11117_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:168436$11119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$issuer_ls180.v:168436$11119_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:168439$11122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$issuer_ls180.v:168439$11122_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:168433$11116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rdok - connect \Y $or$issuer_ls180.v:168433$11116_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:168435$11118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $or$issuer_ls180.v:168435$11118_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:168438$11121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rdok - connect \Y $or$issuer_ls180.v:168438$11121_Y - end - attribute \src "issuer_ls180.v:168397.7-168397.20" - process $proc$issuer_ls180.v:168397$11127 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:168419.7-168419.19" - process $proc$issuer_ls180.v:168419$11128 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:168440.3-168441.27" - process $proc$issuer_ls180.v:168440$11123 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:168442.3-168450.6" - process $proc$issuer_ls180.v:168442$11124 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$11125 $1\q_int$next[0:0]$11126 - attribute \src "issuer_ls180.v:168443.5-168443.29" - switch \initial - attribute \src "issuer_ls180.v:168443.9-168443.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$11126 1'0 - case - assign $1\q_int$next[0:0]$11126 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$11125 - end - connect \$9 $and$issuer_ls180.v:168432$11115_Y - connect \$11 $or$issuer_ls180.v:168433$11116_Y - connect \$13 $not$issuer_ls180.v:168434$11117_Y - connect \$15 $or$issuer_ls180.v:168435$11118_Y - connect \$1 $not$issuer_ls180.v:168436$11119_Y - connect \$3 $and$issuer_ls180.v:168437$11120_Y - connect \$5 $or$issuer_ls180.v:168438$11121_Y - connect \$7 $not$issuer_ls180.v:168439$11122_Y - connect \qlq_rdok \$15 - connect \qn_rdok \$13 - connect \q_rdok \$11 -end -attribute \src "issuer_ls180.v:168458.1-168516.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rok_l" -attribute \generator "nMigen" -module \rok_l$27 - attribute \src "issuer_ls180.v:168459.7-168459.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:168504.3-168512.6" - wire $0\q_int$next[0:0]$11139 - attribute \src "issuer_ls180.v:168502.3-168503.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:168504.3-168512.6" - wire $1\q_int$next[0:0]$11140 - attribute \src "issuer_ls180.v:168481.7-168481.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:168494.17-168494.96" - wire $and$issuer_ls180.v:168494$11129_Y - attribute \src "issuer_ls180.v:168499.17-168499.96" - wire $and$issuer_ls180.v:168499$11134_Y - attribute \src "issuer_ls180.v:168496.18-168496.94" - wire $not$issuer_ls180.v:168496$11131_Y - attribute \src "issuer_ls180.v:168498.17-168498.93" - wire $not$issuer_ls180.v:168498$11133_Y - attribute \src "issuer_ls180.v:168501.17-168501.93" - wire $not$issuer_ls180.v:168501$11136_Y - attribute \src "issuer_ls180.v:168495.18-168495.99" - wire $or$issuer_ls180.v:168495$11130_Y - attribute \src "issuer_ls180.v:168497.18-168497.100" - wire $or$issuer_ls180.v:168497$11132_Y - attribute \src "issuer_ls180.v:168500.17-168500.98" - wire $or$issuer_ls180.v:168500$11135_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:168459.7-168459.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:168494$11129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:168494$11129_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:168499$11134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:168499$11134_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:168496$11131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $not$issuer_ls180.v:168496$11131_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:168498$11133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$issuer_ls180.v:168498$11133_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:168501$11136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$issuer_ls180.v:168501$11136_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:168495$11130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rdok - connect \Y $or$issuer_ls180.v:168495$11130_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:168497$11132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $or$issuer_ls180.v:168497$11132_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:168500$11135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rdok - connect \Y $or$issuer_ls180.v:168500$11135_Y - end - attribute \src "issuer_ls180.v:168459.7-168459.20" - process $proc$issuer_ls180.v:168459$11141 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:168481.7-168481.19" - process $proc$issuer_ls180.v:168481$11142 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:168502.3-168503.27" - process $proc$issuer_ls180.v:168502$11137 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:168504.3-168512.6" - process $proc$issuer_ls180.v:168504$11138 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$11139 $1\q_int$next[0:0]$11140 - attribute \src "issuer_ls180.v:168505.5-168505.29" - switch \initial - attribute \src "issuer_ls180.v:168505.9-168505.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$11140 1'0 - case - assign $1\q_int$next[0:0]$11140 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$11139 - end - connect \$9 $and$issuer_ls180.v:168494$11129_Y - connect \$11 $or$issuer_ls180.v:168495$11130_Y - connect \$13 $not$issuer_ls180.v:168496$11131_Y - connect \$15 $or$issuer_ls180.v:168497$11132_Y - connect \$1 $not$issuer_ls180.v:168498$11133_Y - connect \$3 $and$issuer_ls180.v:168499$11134_Y - connect \$5 $or$issuer_ls180.v:168500$11135_Y - connect \$7 $not$issuer_ls180.v:168501$11136_Y - connect \qlq_rdok \$15 - connect \qn_rdok \$13 - connect \q_rdok \$11 -end -attribute \src "issuer_ls180.v:168520.1-168578.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rok_l" -attribute \generator "nMigen" -module \rok_l$40 - attribute \src "issuer_ls180.v:168521.7-168521.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:168566.3-168574.6" - wire $0\q_int$next[0:0]$11153 - attribute \src "issuer_ls180.v:168564.3-168565.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:168566.3-168574.6" - wire $1\q_int$next[0:0]$11154 - attribute \src "issuer_ls180.v:168543.7-168543.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:168556.17-168556.96" - wire $and$issuer_ls180.v:168556$11143_Y - attribute \src "issuer_ls180.v:168561.17-168561.96" - wire $and$issuer_ls180.v:168561$11148_Y - attribute \src "issuer_ls180.v:168558.18-168558.94" - wire $not$issuer_ls180.v:168558$11145_Y - attribute \src "issuer_ls180.v:168560.17-168560.93" - wire $not$issuer_ls180.v:168560$11147_Y - attribute \src "issuer_ls180.v:168563.17-168563.93" - wire $not$issuer_ls180.v:168563$11150_Y - attribute \src "issuer_ls180.v:168557.18-168557.99" - wire $or$issuer_ls180.v:168557$11144_Y - attribute \src "issuer_ls180.v:168559.18-168559.100" - wire $or$issuer_ls180.v:168559$11146_Y - attribute \src "issuer_ls180.v:168562.17-168562.98" - wire $or$issuer_ls180.v:168562$11149_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:168521.7-168521.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:168556$11143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:168556$11143_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:168561$11148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:168561$11148_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:168558$11145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $not$issuer_ls180.v:168558$11145_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:168560$11147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$issuer_ls180.v:168560$11147_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:168563$11150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$issuer_ls180.v:168563$11150_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:168557$11144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rdok - connect \Y $or$issuer_ls180.v:168557$11144_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:168559$11146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $or$issuer_ls180.v:168559$11146_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:168562$11149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rdok - connect \Y $or$issuer_ls180.v:168562$11149_Y - end - attribute \src "issuer_ls180.v:168521.7-168521.20" - process $proc$issuer_ls180.v:168521$11155 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:168543.7-168543.19" - process $proc$issuer_ls180.v:168543$11156 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:168564.3-168565.27" - process $proc$issuer_ls180.v:168564$11151 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:168566.3-168574.6" - process $proc$issuer_ls180.v:168566$11152 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$11153 $1\q_int$next[0:0]$11154 - attribute \src "issuer_ls180.v:168567.5-168567.29" - switch \initial - attribute \src "issuer_ls180.v:168567.9-168567.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$11154 1'0 - case - assign $1\q_int$next[0:0]$11154 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$11153 - end - connect \$9 $and$issuer_ls180.v:168556$11143_Y - connect \$11 $or$issuer_ls180.v:168557$11144_Y - connect \$13 $not$issuer_ls180.v:168558$11145_Y - connect \$15 $or$issuer_ls180.v:168559$11146_Y - connect \$1 $not$issuer_ls180.v:168560$11147_Y - connect \$3 $and$issuer_ls180.v:168561$11148_Y - connect \$5 $or$issuer_ls180.v:168562$11149_Y - connect \$7 $not$issuer_ls180.v:168563$11150_Y - connect \qlq_rdok \$15 - connect \qn_rdok \$13 - connect \q_rdok \$11 -end -attribute \src "issuer_ls180.v:168582.1-168640.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rok_l" -attribute \generator "nMigen" -module \rok_l$56 - attribute \src "issuer_ls180.v:168583.7-168583.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:168628.3-168636.6" - wire $0\q_int$next[0:0]$11167 - attribute \src "issuer_ls180.v:168626.3-168627.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:168628.3-168636.6" - wire $1\q_int$next[0:0]$11168 - attribute \src "issuer_ls180.v:168605.7-168605.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:168618.17-168618.96" - wire $and$issuer_ls180.v:168618$11157_Y - attribute \src "issuer_ls180.v:168623.17-168623.96" - wire $and$issuer_ls180.v:168623$11162_Y - attribute \src "issuer_ls180.v:168620.18-168620.94" - wire $not$issuer_ls180.v:168620$11159_Y - attribute \src "issuer_ls180.v:168622.17-168622.93" - wire $not$issuer_ls180.v:168622$11161_Y - attribute \src "issuer_ls180.v:168625.17-168625.93" - wire $not$issuer_ls180.v:168625$11164_Y - attribute \src "issuer_ls180.v:168619.18-168619.99" - wire $or$issuer_ls180.v:168619$11158_Y - attribute \src "issuer_ls180.v:168621.18-168621.100" - wire $or$issuer_ls180.v:168621$11160_Y - attribute \src "issuer_ls180.v:168624.17-168624.98" - wire $or$issuer_ls180.v:168624$11163_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:168583.7-168583.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:168618$11157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:168618$11157_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:168623$11162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:168623$11162_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:168620$11159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $not$issuer_ls180.v:168620$11159_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:168622$11161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$issuer_ls180.v:168622$11161_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:168625$11164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$issuer_ls180.v:168625$11164_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:168619$11158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rdok - connect \Y $or$issuer_ls180.v:168619$11158_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:168621$11160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $or$issuer_ls180.v:168621$11160_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:168624$11163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rdok - connect \Y $or$issuer_ls180.v:168624$11163_Y - end - attribute \src "issuer_ls180.v:168583.7-168583.20" - process $proc$issuer_ls180.v:168583$11169 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:168605.7-168605.19" - process $proc$issuer_ls180.v:168605$11170 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:168626.3-168627.27" - process $proc$issuer_ls180.v:168626$11165 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:168628.3-168636.6" - process $proc$issuer_ls180.v:168628$11166 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$11167 $1\q_int$next[0:0]$11168 - attribute \src "issuer_ls180.v:168629.5-168629.29" - switch \initial - attribute \src "issuer_ls180.v:168629.9-168629.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$11168 1'0 - case - assign $1\q_int$next[0:0]$11168 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$11167 - end - connect \$9 $and$issuer_ls180.v:168618$11157_Y - connect \$11 $or$issuer_ls180.v:168619$11158_Y - connect \$13 $not$issuer_ls180.v:168620$11159_Y - connect \$15 $or$issuer_ls180.v:168621$11160_Y - connect \$1 $not$issuer_ls180.v:168622$11161_Y - connect \$3 $and$issuer_ls180.v:168623$11162_Y - connect \$5 $or$issuer_ls180.v:168624$11163_Y - connect \$7 $not$issuer_ls180.v:168625$11164_Y - connect \qlq_rdok \$15 - connect \qn_rdok \$13 - connect \q_rdok \$11 -end -attribute \src "issuer_ls180.v:168644.1-168702.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.rok_l" -attribute \generator "nMigen" -module \rok_l$68 - attribute \src "issuer_ls180.v:168645.7-168645.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:168690.3-168698.6" - wire $0\q_int$next[0:0]$11181 - attribute \src "issuer_ls180.v:168688.3-168689.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:168690.3-168698.6" - wire $1\q_int$next[0:0]$11182 - attribute \src "issuer_ls180.v:168667.7-168667.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:168680.17-168680.96" - wire $and$issuer_ls180.v:168680$11171_Y - attribute \src "issuer_ls180.v:168685.17-168685.96" - wire $and$issuer_ls180.v:168685$11176_Y - attribute \src "issuer_ls180.v:168682.18-168682.94" - wire $not$issuer_ls180.v:168682$11173_Y - attribute \src "issuer_ls180.v:168684.17-168684.93" - wire $not$issuer_ls180.v:168684$11175_Y - attribute \src "issuer_ls180.v:168687.17-168687.93" - wire $not$issuer_ls180.v:168687$11178_Y - attribute \src "issuer_ls180.v:168681.18-168681.99" - wire $or$issuer_ls180.v:168681$11172_Y - attribute \src "issuer_ls180.v:168683.18-168683.100" - wire $or$issuer_ls180.v:168683$11174_Y - attribute \src "issuer_ls180.v:168686.17-168686.98" - wire $or$issuer_ls180.v:168686$11177_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:168645.7-168645.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:168680$11171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:168680$11171_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:168685$11176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:168685$11176_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:168682$11173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $not$issuer_ls180.v:168682$11173_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:168684$11175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$issuer_ls180.v:168684$11175_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:168687$11178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$issuer_ls180.v:168687$11178_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:168681$11172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rdok - connect \Y $or$issuer_ls180.v:168681$11172_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:168683$11174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $or$issuer_ls180.v:168683$11174_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:168686$11177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rdok - connect \Y $or$issuer_ls180.v:168686$11177_Y - end - attribute \src "issuer_ls180.v:168645.7-168645.20" - process $proc$issuer_ls180.v:168645$11183 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:168667.7-168667.19" - process $proc$issuer_ls180.v:168667$11184 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:168688.3-168689.27" - process $proc$issuer_ls180.v:168688$11179 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:168690.3-168698.6" - process $proc$issuer_ls180.v:168690$11180 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$11181 $1\q_int$next[0:0]$11182 - attribute \src "issuer_ls180.v:168691.5-168691.29" - switch \initial - attribute \src "issuer_ls180.v:168691.9-168691.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$11182 1'0 - case - assign $1\q_int$next[0:0]$11182 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$11181 - end - connect \$9 $and$issuer_ls180.v:168680$11171_Y - connect \$11 $or$issuer_ls180.v:168681$11172_Y - connect \$13 $not$issuer_ls180.v:168682$11173_Y - connect \$15 $or$issuer_ls180.v:168683$11174_Y - connect \$1 $not$issuer_ls180.v:168684$11175_Y - connect \$3 $and$issuer_ls180.v:168685$11176_Y - connect \$5 $or$issuer_ls180.v:168686$11177_Y - connect \$7 $not$issuer_ls180.v:168687$11178_Y - connect \qlq_rdok \$15 - connect \qn_rdok \$13 - connect \q_rdok \$11 -end -attribute \src "issuer_ls180.v:168706.1-168764.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.rok_l" -attribute \generator "nMigen" -module \rok_l$85 - attribute \src "issuer_ls180.v:168707.7-168707.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:168752.3-168760.6" - wire $0\q_int$next[0:0]$11195 - attribute \src "issuer_ls180.v:168750.3-168751.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:168752.3-168760.6" - wire $1\q_int$next[0:0]$11196 - attribute \src "issuer_ls180.v:168729.7-168729.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:168742.17-168742.96" - wire $and$issuer_ls180.v:168742$11185_Y - attribute \src "issuer_ls180.v:168747.17-168747.96" - wire $and$issuer_ls180.v:168747$11190_Y - attribute \src "issuer_ls180.v:168744.18-168744.94" - wire $not$issuer_ls180.v:168744$11187_Y - attribute \src "issuer_ls180.v:168746.17-168746.93" - wire $not$issuer_ls180.v:168746$11189_Y - attribute \src "issuer_ls180.v:168749.17-168749.93" - wire $not$issuer_ls180.v:168749$11192_Y - attribute \src "issuer_ls180.v:168743.18-168743.99" - wire $or$issuer_ls180.v:168743$11186_Y - attribute \src "issuer_ls180.v:168745.18-168745.100" - wire $or$issuer_ls180.v:168745$11188_Y - attribute \src "issuer_ls180.v:168748.17-168748.98" - wire $or$issuer_ls180.v:168748$11191_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:168707.7-168707.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:168742$11185 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:168742$11185_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:168747$11190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:168747$11190_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:168744$11187 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $not$issuer_ls180.v:168744$11187_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:168746$11189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y 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$and$issuer_ls180.v:168931$11213_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" - cell $and $and$issuer_ls180.v:168933$11215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \arith - connect \B \repl32 [63] - connect \Y $and$issuer_ls180.v:168933$11215_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $and $and$issuer_ls180.v:168935$11217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \clear_right - connect \B \$42 - connect \Y $and$issuer_ls180.v:168935$11217_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$issuer_ls180.v:168936$11218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \mr - connect \B \ml - connect \Y $and$issuer_ls180.v:168936$11218_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$issuer_ls180.v:168937$11219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \rot - connect \B \$46 - connect \Y $and$issuer_ls180.v:168937$11219_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$issuer_ls180.v:168939$11221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \mr - connect \B \ml - connect \Y $and$issuer_ls180.v:168939$11221_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$issuer_ls180.v:168941$11223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \B \$50 - connect \Y $and$issuer_ls180.v:168941$11223_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $and $and$issuer_ls180.v:168944$11226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \rot - connect \B \$58 - connect \Y $and$issuer_ls180.v:168944$11226_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $and $and$issuer_ls180.v:168947$11229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \B \$62 - connect \Y $and$issuer_ls180.v:168947$11229_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - cell $and $and$issuer_ls180.v:168949$11231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \shift [6] - connect \B \$4 - connect \Y $and$issuer_ls180.v:168949$11231_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:174" - cell $and $and$issuer_ls180.v:168950$11232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \rot - connect \B \mr - connect \Y $and$issuer_ls180.v:168950$11232_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $and $and$issuer_ls180.v:168954$11236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \rs - connect \B \$77 - connect \Y $and$issuer_ls180.v:168954$11236_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $extend$issuer_ls180.v:168918$11199 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 7 - connect \A \mb - connect \Y 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\B 7'1000000 - connect \Y $le$issuer_ls180.v:168926$11208_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" - cell $neg $neg$issuer_ls180.v:168927$11209 - parameter \A_SIGNED 1 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 7 - connect \A { \shift_signed [5] \shift_signed } - connect \Y $neg$issuer_ls180.v:168927$11209_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" - cell $not $not$issuer_ls180.v:168919$11201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sh [5] - connect \Y $not$issuer_ls180.v:168919$11201_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - cell $not $not$issuer_ls180.v:168921$11203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \clear_left - connect \Y $not$issuer_ls180.v:168921$11203_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139" - cell $not $not$issuer_ls180.v:168923$11205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \sh [5:0] - connect \Y $not$issuer_ls180.v:168923$11205_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" - cell $not $not$issuer_ls180.v:168929$11211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \left_mask_mask - connect \Y $not$issuer_ls180.v:168929$11211_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $not $not$issuer_ls180.v:168930$11212 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \clear_right - connect \Y $not$issuer_ls180.v:168930$11212_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - cell $not $not$issuer_ls180.v:168938$11220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_32bit - connect \Y $not$issuer_ls180.v:168938$11220_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $not $not$issuer_ls180.v:168940$11222 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \$51 - connect \Y $not$issuer_ls180.v:168940$11222_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $not $not$issuer_ls180.v:168946$11228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \$63 - connect \Y $not$issuer_ls180.v:168946$11228_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" - cell $not $not$issuer_ls180.v:168951$11233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \mr - connect \Y $not$issuer_ls180.v:168951$11233_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $not $not$issuer_ls180.v:168953$11235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ml - connect \Y $not$issuer_ls180.v:168953$11235_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $or $or$issuer_ls180.v:168932$11214 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$36 - connect \B \right_shift - connect \Y $or$issuer_ls180.v:168932$11214_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $or $or$issuer_ls180.v:168942$11224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \$48 - connect \B \$54 - connect \Y $or$issuer_ls180.v:168942$11224_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$issuer_ls180.v:168943$11225 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \mr - connect \B \ml - connect \Y $or$issuer_ls180.v:168943$11225_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$issuer_ls180.v:168945$11227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \mr - connect \B \ml - connect \Y $or$issuer_ls180.v:168945$11227_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$issuer_ls180.v:168948$11230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \$60 - connect \B \$66 - connect \Y $or$issuer_ls180.v:168948$11230_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" - cell $or $or$issuer_ls180.v:168952$11234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \rot - connect \B \$72 - connect \Y $or$issuer_ls180.v:168952$11234_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $pos$issuer_ls180.v:168918$11200 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 7 - connect \A $extend$issuer_ls180.v:168918$11199_Y - connect \Y $pos$issuer_ls180.v:168918$11200_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $reduce_or $reduce_or$issuer_ls180.v:168955$11237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \$79 - connect \Y $reduce_or$issuer_ls180.v:168955$11237_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" - cell $sub $sub$issuer_ls180.v:168925$11207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 8 - connect \A 7'1000000 - connect \B \mb$8 - connect \Y $sub$issuer_ls180.v:168925$11207_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" - cell $sub $sub$issuer_ls180.v:168928$11210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 8 - connect \A 6'111111 - connect \B \me$13 - connect \Y $sub$issuer_ls180.v:168928$11210_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:168956.13-168959.4" - cell \left_mask \left_mask - connect \mask \left_mask_mask - connect \shift \left_mask_shift - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:168960.14-168963.4" - cell \right_mask \right_mask - connect \mask \right_mask_mask - connect \shift \right_mask_shift - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:168964.8-168968.4" - cell \rotl \rotl - connect \a \rotl_a - connect \b \rotl_b - connect \o \rotl_o - end - attribute \src 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\rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] } - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\hi32[31:0] \rs [63:32] - end - sync always - update \hi32 $0\hi32[31:0] - end - attribute \src "issuer_ls180.v:168984.3-168993.6" - process $proc$issuer_ls180.v:168984$11239 - assign { } { } - assign { } { } - assign $0\right_mask_shift[6:0] $1\right_mask_shift[6:0] - attribute \src "issuer_ls180.v:168985.5-168985.29" - switch \initial - attribute \src "issuer_ls180.v:168985.9-168985.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - switch \$22 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\right_mask_shift[6:0] \$24 [6:0] - case - assign $1\right_mask_shift[6:0] 7'0000000 - end - sync always - update \right_mask_shift $0\right_mask_shift[6:0] - end - attribute \src "issuer_ls180.v:168994.3-169005.6" - process $proc$issuer_ls180.v:168994$11240 - assign { } { } - assign $0\mr[63:0] $1\mr[63:0] - attribute \src "issuer_ls180.v:168995.5-168995.29" - switch \initial - attribute \src "issuer_ls180.v:168995.9-168995.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - switch \$27 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\mr[63:0] \right_mask_mask - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\mr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \mr $0\mr[63:0] - end - attribute \src "issuer_ls180.v:169006.3-169017.6" - process $proc$issuer_ls180.v:169006$11241 - assign { } { } - assign $0\output_mode[1:0] $1\output_mode[1:0] - attribute \src "issuer_ls180.v:169007.5-169007.29" - switch \initial - attribute \src "issuer_ls180.v:169007.9-169007.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - switch \$38 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\output_mode[1:0] { 1'1 \$40 } - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\output_mode[1:0] { 1'0 \$44 } - end - sync always - update \output_mode $0\output_mode[1:0] - end - attribute \src "issuer_ls180.v:169018.3-169036.6" - process $proc$issuer_ls180.v:169018$11242 - assign { } { } - assign { } { } - assign $0\result_o[63:0] $1\result_o[63:0] - attribute \src "issuer_ls180.v:169019.5-169019.29" - switch \initial - attribute \src "issuer_ls180.v:169019.9-169019.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:168" - switch \output_mode - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\result_o[63:0] \$56 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\result_o[63:0] \$68 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\result_o[63:0] \$70 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\result_o[63:0] \$74 - case - assign $1\result_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \result_o $0\result_o[63:0] - end - attribute \src "issuer_ls180.v:169037.3-169046.6" - process $proc$issuer_ls180.v:169037$11243 - assign { } { } - assign { } { } - assign $0\carry_out_o[0:0] $1\carry_out_o[0:0] - attribute \src "issuer_ls180.v:169038.5-169038.29" - switch \initial - attribute \src "issuer_ls180.v:169038.9-169038.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:168" - switch \output_mode - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\carry_out_o[0:0] \$76 - case - assign $1\carry_out_o[0:0] 1'0 - end - sync always - update \carry_out_o $0\carry_out_o[0:0] - end - attribute \src "issuer_ls180.v:169047.3-169058.6" - process $proc$issuer_ls180.v:169047$11244 - assign { } { } - assign $0\rot_count[5:0] $1\rot_count[5:0] - attribute \src "issuer_ls180.v:169048.5-169048.29" - switch \initial - attribute \src "issuer_ls180.v:169048.9-169048.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:98" - switch \right_shift - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rot_count[5:0] \$1 [5:0] - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\rot_count[5:0] \shift [5:0] - end - sync always - update \rot_count $0\rot_count[5:0] - end - attribute \src "issuer_ls180.v:169059.3-169092.6" - process $proc$issuer_ls180.v:169059$11245 - assign { } { } - assign $0\mb$8[6:0]$11246 $1\mb$8[6:0]$11247 - attribute \src "issuer_ls180.v:169060.5-169060.29" - switch \initial - attribute \src "issuer_ls180.v:169060.9-169060.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:116" - switch { \right_shift \clear_left } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\mb$8[6:0]$11247 [4:0] \$9 [4:0] - assign $1\mb$8[6:0]$11247 [6:5] $2\mb$8[6:5]$11248 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118" - switch \is_32bit - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\mb$8[6:5]$11248 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\mb$8[6:5]$11248 { 1'0 \mb_extra } - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\mb$8[6:0]$11247 [4:0] \sh [4:0] - assign $1\mb$8[6:0]$11247 [6:5] $3\mb$8[6:5]$11249 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125" - switch \is_32bit - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\mb$8[6:5]$11249 { \sh [5] \$11 } - case - assign $3\mb$8[6:5]$11249 \sh [6:5] - end - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\mb$8[6:0]$11247 { 1'0 \is_32bit 5'00000 } - end - sync always - update \mb$8 $0\mb$8[6:0]$11246 - end - attribute \src "issuer_ls180.v:169093.3-169107.6" - process $proc$issuer_ls180.v:169093$11250 - assign { } { } - assign $0\me$13[6:0]$11251 $1\me$13[6:0]$11252 - attribute \src "issuer_ls180.v:169094.5-169094.29" - switch \initial - attribute \src "issuer_ls180.v:169094.9-169094.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" - switch { \$18 \$14 } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\me$13[6:0]$11252 { 2'01 \me } - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\me$13[6:0]$11252 { 1'0 \mb_extra \mb } - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $1\me$13[6:0]$11252 { \sh [6] \$20 } - end - sync always - update \me$13 $0\me$13[6:0]$11251 - end - connect \$9 $pos$issuer_ls180.v:168918$11200_Y - connect \$11 $not$issuer_ls180.v:168919$11201_Y - connect \$14 $and$issuer_ls180.v:168920$11202_Y - connect \$16 $not$issuer_ls180.v:168921$11203_Y - connect \$18 $and$issuer_ls180.v:168922$11204_Y - connect \$20 $not$issuer_ls180.v:168923$11205_Y - connect \$22 $le$issuer_ls180.v:168924$11206_Y - connect \$25 $sub$issuer_ls180.v:168925$11207_Y - connect \$27 $le$issuer_ls180.v:168926$11208_Y - connect \$2 $neg$issuer_ls180.v:168927$11209_Y - connect \$30 $sub$issuer_ls180.v:168928$11210_Y - connect \$32 $not$issuer_ls180.v:168929$11211_Y - connect \$34 $not$issuer_ls180.v:168930$11212_Y - connect \$36 $and$issuer_ls180.v:168931$11213_Y - connect \$38 $or$issuer_ls180.v:168932$11214_Y - connect \$40 $and$issuer_ls180.v:168933$11215_Y - connect \$42 $gt$issuer_ls180.v:168934$11216_Y - connect \$44 $and$issuer_ls180.v:168935$11217_Y - connect \$46 $and$issuer_ls180.v:168936$11218_Y - connect \$48 $and$issuer_ls180.v:168937$11219_Y - connect \$4 $not$issuer_ls180.v:168938$11220_Y - connect \$51 $and$issuer_ls180.v:168939$11221_Y - connect \$50 $not$issuer_ls180.v:168940$11222_Y - connect \$54 $and$issuer_ls180.v:168941$11223_Y - connect \$56 $or$issuer_ls180.v:168942$11224_Y - connect \$58 $or$issuer_ls180.v:168943$11225_Y - connect \$60 $and$issuer_ls180.v:168944$11226_Y - connect \$63 $or$issuer_ls180.v:168945$11227_Y - connect \$62 $not$issuer_ls180.v:168946$11228_Y - connect \$66 $and$issuer_ls180.v:168947$11229_Y - connect \$68 $or$issuer_ls180.v:168948$11230_Y - connect \$6 $and$issuer_ls180.v:168949$11231_Y - connect \$70 $and$issuer_ls180.v:168950$11232_Y - connect \$72 $not$issuer_ls180.v:168951$11233_Y - connect \$74 $or$issuer_ls180.v:168952$11234_Y - connect \$77 $not$issuer_ls180.v:168953$11235_Y - connect \$79 $and$issuer_ls180.v:168954$11236_Y - connect \$76 $reduce_or$issuer_ls180.v:168955$11237_Y - connect \$1 \$2 - connect \$24 \$25 - connect \$29 \$30 - connect \ml \$32 - connect \left_mask_shift \$30 [6:0] - connect \sh { \$6 \shift [5:0] } - connect \rot \rotl_o - connect \rotl_b \rot_count - connect \rotl_a \repl32 - connect \shift_signed \shift [5:0] - connect \repl32 { \hi32 \rs [31:0] } -end -attribute \src "issuer_ls180.v:169123.1-169137.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.rotl" -attribute \generator "nMigen" -module \rotl - attribute \src "issuer_ls180.v:169135.17-169135.32" - wire width 128 $shr$issuer_ls180.v:169135$11255_Y - attribute \src "issuer_ls180.v:169134.17-169134.100" - wire width 8 $sub$issuer_ls180.v:169134$11254_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19" - wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" - wire width 8 \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8" - wire width 64 input 3 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9" - wire width 6 input 1 \b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" - wire width 64 output 2 \o - attribute \src "issuer_ls180.v:169135.17-169135.32" - cell $shr $shr$issuer_ls180.v:169135$11255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 128 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 128 - connect \A { \a \a } - connect \B \$2 - connect \Y $shr$issuer_ls180.v:169135$11255_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" - cell $sub $sub$issuer_ls180.v:169134$11254 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 8 - connect \A 7'1000000 - connect \B \b - connect \Y $sub$issuer_ls180.v:169134$11254_Y - end - connect \$2 $sub$issuer_ls180.v:169134$11254_Y - connect \$1 $shr$issuer_ls180.v:169135$11255_Y [63:0] - connect \o \$1 -end -attribute \src "issuer_ls180.v:169141.1-169199.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.rst_l" -attribute \generator "nMigen" -module \rst_l - attribute \src "issuer_ls180.v:169142.7-169142.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:169187.3-169195.6" - wire $0\q_int$next[0:0]$11266 - attribute \src "issuer_ls180.v:169185.3-169186.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:169187.3-169195.6" - wire $1\q_int$next[0:0]$11267 - attribute \src "issuer_ls180.v:169164.7-169164.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:169177.17-169177.96" - wire $and$issuer_ls180.v:169177$11256_Y - attribute \src "issuer_ls180.v:169182.17-169182.96" - wire $and$issuer_ls180.v:169182$11261_Y - attribute \src "issuer_ls180.v:169179.18-169179.93" - wire $not$issuer_ls180.v:169179$11258_Y - attribute \src "issuer_ls180.v:169181.17-169181.92" - wire $not$issuer_ls180.v:169181$11260_Y - attribute \src "issuer_ls180.v:169184.17-169184.92" - wire $not$issuer_ls180.v:169184$11263_Y - attribute \src "issuer_ls180.v:169178.18-169178.98" - wire $or$issuer_ls180.v:169178$11257_Y - attribute \src "issuer_ls180.v:169180.18-169180.99" - wire $or$issuer_ls180.v:169180$11259_Y - attribute \src "issuer_ls180.v:169183.17-169183.97" - wire $or$issuer_ls180.v:169183$11262_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:169142.7-169142.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:169177$11256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:169177$11256_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:169182$11261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:169182$11261_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:169179$11258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $not$issuer_ls180.v:169179$11258_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:169181$11260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$issuer_ls180.v:169181$11260_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:169184$11263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$issuer_ls180.v:169184$11263_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:169178$11257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rst - connect \Y $or$issuer_ls180.v:169178$11257_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:169180$11259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $or$issuer_ls180.v:169180$11259_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:169183$11262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rst - connect \Y $or$issuer_ls180.v:169183$11262_Y - end - attribute \src "issuer_ls180.v:169142.7-169142.20" - process $proc$issuer_ls180.v:169142$11268 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:169164.7-169164.19" - process $proc$issuer_ls180.v:169164$11269 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:169185.3-169186.27" - process $proc$issuer_ls180.v:169185$11264 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:169187.3-169195.6" - process $proc$issuer_ls180.v:169187$11265 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$11266 $1\q_int$next[0:0]$11267 - attribute \src "issuer_ls180.v:169188.5-169188.29" - switch \initial - attribute \src "issuer_ls180.v:169188.9-169188.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$11267 1'0 - case - assign $1\q_int$next[0:0]$11267 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$11266 - end - connect \$9 $and$issuer_ls180.v:169177$11256_Y - connect \$11 $or$issuer_ls180.v:169178$11257_Y - connect \$13 $not$issuer_ls180.v:169179$11258_Y - connect \$15 $or$issuer_ls180.v:169180$11259_Y - connect \$1 $not$issuer_ls180.v:169181$11260_Y - connect \$3 $and$issuer_ls180.v:169182$11261_Y - connect \$5 $or$issuer_ls180.v:169183$11262_Y - connect \$7 $not$issuer_ls180.v:169184$11263_Y - connect \qlq_rst \$15 - connect \qn_rst \$13 - connect \q_rst \$11 -end -attribute \src "issuer_ls180.v:169203.1-169261.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rst_l" -attribute \generator "nMigen" -module \rst_l$101 - attribute \src "issuer_ls180.v:169204.7-169204.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:169249.3-169257.6" - wire $0\q_int$next[0:0]$11280 - attribute \src "issuer_ls180.v:169247.3-169248.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:169249.3-169257.6" - wire $1\q_int$next[0:0]$11281 - attribute \src "issuer_ls180.v:169226.7-169226.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:169239.17-169239.96" - wire $and$issuer_ls180.v:169239$11270_Y - attribute \src "issuer_ls180.v:169244.17-169244.96" - wire $and$issuer_ls180.v:169244$11275_Y - attribute \src "issuer_ls180.v:169241.18-169241.93" - wire $not$issuer_ls180.v:169241$11272_Y - attribute \src "issuer_ls180.v:169243.17-169243.92" - wire $not$issuer_ls180.v:169243$11274_Y - attribute \src "issuer_ls180.v:169246.17-169246.92" - wire $not$issuer_ls180.v:169246$11277_Y - attribute \src "issuer_ls180.v:169240.18-169240.98" - wire $or$issuer_ls180.v:169240$11271_Y - attribute \src "issuer_ls180.v:169242.18-169242.99" - wire $or$issuer_ls180.v:169242$11273_Y - attribute \src "issuer_ls180.v:169245.17-169245.97" - wire $or$issuer_ls180.v:169245$11276_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:169204.7-169204.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:169239$11270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:169239$11270_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:169244$11275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:169244$11275_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:169241$11272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $not$issuer_ls180.v:169241$11272_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:169243$11274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$issuer_ls180.v:169243$11274_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:169246$11277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$issuer_ls180.v:169246$11277_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:169240$11271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rst - connect \Y $or$issuer_ls180.v:169240$11271_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:169242$11273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $or$issuer_ls180.v:169242$11273_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:169245$11276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rst - connect \Y $or$issuer_ls180.v:169245$11276_Y - end - attribute \src "issuer_ls180.v:169204.7-169204.20" - process $proc$issuer_ls180.v:169204$11282 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:169226.7-169226.19" - process $proc$issuer_ls180.v:169226$11283 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:169247.3-169248.27" - process $proc$issuer_ls180.v:169247$11278 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:169249.3-169257.6" - process $proc$issuer_ls180.v:169249$11279 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$11280 $1\q_int$next[0:0]$11281 - attribute \src "issuer_ls180.v:169250.5-169250.29" - switch \initial - attribute \src "issuer_ls180.v:169250.9-169250.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$11281 1'0 - case - assign $1\q_int$next[0:0]$11281 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$11280 - end - connect \$9 $and$issuer_ls180.v:169239$11270_Y - connect \$11 $or$issuer_ls180.v:169240$11271_Y - connect \$13 $not$issuer_ls180.v:169241$11272_Y - connect \$15 $or$issuer_ls180.v:169242$11273_Y - connect \$1 $not$issuer_ls180.v:169243$11274_Y - connect \$3 $and$issuer_ls180.v:169244$11275_Y - connect \$5 $or$issuer_ls180.v:169245$11276_Y - connect \$7 $not$issuer_ls180.v:169246$11277_Y - connect \qlq_rst \$15 - connect \qn_rst \$13 - connect \q_rst \$11 -end -attribute \src "issuer_ls180.v:169265.1-169323.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rst_l" -attribute \generator "nMigen" -module \rst_l$119 - attribute \src "issuer_ls180.v:169266.7-169266.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:169311.3-169319.6" - wire $0\q_int$next[0:0]$11294 - attribute \src "issuer_ls180.v:169309.3-169310.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:169311.3-169319.6" - wire $1\q_int$next[0:0]$11295 - attribute \src "issuer_ls180.v:169288.7-169288.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:169301.17-169301.96" - wire $and$issuer_ls180.v:169301$11284_Y - attribute \src "issuer_ls180.v:169306.17-169306.96" - wire $and$issuer_ls180.v:169306$11289_Y - attribute \src "issuer_ls180.v:169303.18-169303.93" - wire $not$issuer_ls180.v:169303$11286_Y - attribute \src "issuer_ls180.v:169305.17-169305.92" - wire $not$issuer_ls180.v:169305$11288_Y - attribute \src "issuer_ls180.v:169308.17-169308.92" - wire $not$issuer_ls180.v:169308$11291_Y - attribute \src "issuer_ls180.v:169302.18-169302.98" - wire $or$issuer_ls180.v:169302$11285_Y - attribute \src "issuer_ls180.v:169304.18-169304.99" - wire $or$issuer_ls180.v:169304$11287_Y - attribute \src "issuer_ls180.v:169307.17-169307.97" - wire $or$issuer_ls180.v:169307$11290_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:169266.7-169266.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:169301$11284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:169301$11284_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:169306$11289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:169306$11289_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:169303$11286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $not$issuer_ls180.v:169303$11286_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:169305$11288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$issuer_ls180.v:169305$11288_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:169308$11291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$issuer_ls180.v:169308$11291_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:169302$11285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rst - connect \Y $or$issuer_ls180.v:169302$11285_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:169304$11287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $or$issuer_ls180.v:169304$11287_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:169307$11290 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rst - connect \Y $or$issuer_ls180.v:169307$11290_Y - end - attribute \src "issuer_ls180.v:169266.7-169266.20" - process $proc$issuer_ls180.v:169266$11296 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:169288.7-169288.19" - process $proc$issuer_ls180.v:169288$11297 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:169309.3-169310.27" - process $proc$issuer_ls180.v:169309$11292 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:169311.3-169319.6" - process $proc$issuer_ls180.v:169311$11293 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$11294 $1\q_int$next[0:0]$11295 - attribute \src "issuer_ls180.v:169312.5-169312.29" - switch \initial - attribute \src "issuer_ls180.v:169312.9-169312.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$11295 1'0 - case - assign $1\q_int$next[0:0]$11295 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$11294 - end - connect \$9 $and$issuer_ls180.v:169301$11284_Y - connect \$11 $or$issuer_ls180.v:169302$11285_Y - connect \$13 $not$issuer_ls180.v:169303$11286_Y - connect \$15 $or$issuer_ls180.v:169304$11287_Y - connect \$1 $not$issuer_ls180.v:169305$11288_Y - connect \$3 $and$issuer_ls180.v:169306$11289_Y - connect \$5 $or$issuer_ls180.v:169307$11290_Y - connect \$7 $not$issuer_ls180.v:169308$11291_Y - connect \qlq_rst \$15 - connect \qn_rst \$13 - connect \q_rst \$11 -end -attribute \src "issuer_ls180.v:169327.1-169385.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.rst_l" -attribute \generator "nMigen" -module \rst_l$126 - attribute \src "issuer_ls180.v:169328.7-169328.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:169373.3-169381.6" - wire $0\q_int$next[0:0]$11308 - attribute \src "issuer_ls180.v:169371.3-169372.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:169373.3-169381.6" - wire $1\q_int$next[0:0]$11309 - attribute \src "issuer_ls180.v:169350.7-169350.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:169363.17-169363.96" - wire $and$issuer_ls180.v:169363$11298_Y - attribute \src "issuer_ls180.v:169368.17-169368.96" - wire $and$issuer_ls180.v:169368$11303_Y - attribute \src "issuer_ls180.v:169365.18-169365.93" - wire $not$issuer_ls180.v:169365$11300_Y - attribute \src "issuer_ls180.v:169367.17-169367.92" - wire $not$issuer_ls180.v:169367$11302_Y - attribute \src "issuer_ls180.v:169370.17-169370.92" - wire $not$issuer_ls180.v:169370$11305_Y - attribute \src "issuer_ls180.v:169364.18-169364.98" - wire $or$issuer_ls180.v:169364$11299_Y - attribute \src "issuer_ls180.v:169366.18-169366.99" - wire $or$issuer_ls180.v:169366$11301_Y - attribute \src "issuer_ls180.v:169369.17-169369.97" - wire $or$issuer_ls180.v:169369$11304_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:169328.7-169328.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:169363$11298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:169363$11298_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:169368$11303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:169368$11303_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:169365$11300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $not$issuer_ls180.v:169365$11300_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:169367$11302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$issuer_ls180.v:169367$11302_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:169370$11305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$issuer_ls180.v:169370$11305_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:169364$11299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rst - connect \Y $or$issuer_ls180.v:169364$11299_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:169366$11301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $or$issuer_ls180.v:169366$11301_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:169369$11304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rst - connect \Y $or$issuer_ls180.v:169369$11304_Y - end - attribute \src "issuer_ls180.v:169328.7-169328.20" - process $proc$issuer_ls180.v:169328$11310 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:169350.7-169350.19" - process $proc$issuer_ls180.v:169350$11311 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:169371.3-169372.27" - process $proc$issuer_ls180.v:169371$11306 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:169373.3-169381.6" - process $proc$issuer_ls180.v:169373$11307 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$11308 $1\q_int$next[0:0]$11309 - attribute \src "issuer_ls180.v:169374.5-169374.29" - switch \initial - attribute \src "issuer_ls180.v:169374.9-169374.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$11309 1'0 - case - assign $1\q_int$next[0:0]$11309 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$11308 - end - connect \$9 $and$issuer_ls180.v:169363$11298_Y - connect \$11 $or$issuer_ls180.v:169364$11299_Y - connect \$13 $not$issuer_ls180.v:169365$11300_Y - connect \$15 $or$issuer_ls180.v:169366$11301_Y - connect \$1 $not$issuer_ls180.v:169367$11302_Y - connect \$3 $and$issuer_ls180.v:169368$11303_Y - connect \$5 $or$issuer_ls180.v:169369$11304_Y - connect \$7 $not$issuer_ls180.v:169370$11305_Y - connect \qlq_rst \$15 - connect \qn_rst \$13 - connect \q_rst \$11 -end -attribute \src "issuer_ls180.v:169389.1-169447.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rst_l" -attribute \generator "nMigen" -module \rst_l$13 - attribute \src "issuer_ls180.v:169390.7-169390.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:169435.3-169443.6" - wire $0\q_int$next[0:0]$11322 - attribute \src "issuer_ls180.v:169433.3-169434.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:169435.3-169443.6" - wire $1\q_int$next[0:0]$11323 - attribute \src "issuer_ls180.v:169412.7-169412.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:169425.17-169425.96" - wire $and$issuer_ls180.v:169425$11312_Y - attribute \src "issuer_ls180.v:169430.17-169430.96" - wire $and$issuer_ls180.v:169430$11317_Y - attribute \src "issuer_ls180.v:169427.18-169427.93" - wire $not$issuer_ls180.v:169427$11314_Y - attribute \src "issuer_ls180.v:169429.17-169429.92" - wire $not$issuer_ls180.v:169429$11316_Y - attribute \src "issuer_ls180.v:169432.17-169432.92" - wire $not$issuer_ls180.v:169432$11319_Y - attribute \src "issuer_ls180.v:169426.18-169426.98" - wire $or$issuer_ls180.v:169426$11313_Y - attribute \src "issuer_ls180.v:169428.18-169428.99" - wire $or$issuer_ls180.v:169428$11315_Y - attribute \src "issuer_ls180.v:169431.17-169431.97" - wire $or$issuer_ls180.v:169431$11318_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:169390.7-169390.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:169425$11312 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:169425$11312_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:169430$11317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:169430$11317_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:169427$11314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $not$issuer_ls180.v:169427$11314_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:169429$11316 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$issuer_ls180.v:169429$11316_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:169432$11319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$issuer_ls180.v:169432$11319_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:169426$11313 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rst - connect \Y $or$issuer_ls180.v:169426$11313_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:169428$11315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $or$issuer_ls180.v:169428$11315_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:169431$11318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rst - connect \Y $or$issuer_ls180.v:169431$11318_Y - end - attribute \src "issuer_ls180.v:169390.7-169390.20" - process $proc$issuer_ls180.v:169390$11324 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:169412.7-169412.19" - process $proc$issuer_ls180.v:169412$11325 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:169433.3-169434.27" - process $proc$issuer_ls180.v:169433$11320 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:169435.3-169443.6" - process $proc$issuer_ls180.v:169435$11321 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$11322 $1\q_int$next[0:0]$11323 - attribute \src "issuer_ls180.v:169436.5-169436.29" - switch \initial - attribute \src "issuer_ls180.v:169436.9-169436.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$11323 1'0 - case - assign $1\q_int$next[0:0]$11323 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$11322 - end - connect \$9 $and$issuer_ls180.v:169425$11312_Y - connect \$11 $or$issuer_ls180.v:169426$11313_Y - connect \$13 $not$issuer_ls180.v:169427$11314_Y - connect \$15 $or$issuer_ls180.v:169428$11315_Y - connect \$1 $not$issuer_ls180.v:169429$11316_Y - connect \$3 $and$issuer_ls180.v:169430$11317_Y - connect \$5 $or$issuer_ls180.v:169431$11318_Y - connect \$7 $not$issuer_ls180.v:169432$11319_Y - connect \qlq_rst \$15 - connect \qn_rst \$13 - connect \q_rst \$11 -end -attribute \src "issuer_ls180.v:169451.1-169509.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rst_l" -attribute \generator "nMigen" -module \rst_l$26 - attribute \src "issuer_ls180.v:169452.7-169452.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:169497.3-169505.6" - wire $0\q_int$next[0:0]$11336 - attribute \src "issuer_ls180.v:169495.3-169496.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:169497.3-169505.6" - wire $1\q_int$next[0:0]$11337 - attribute \src "issuer_ls180.v:169474.7-169474.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:169487.17-169487.96" - wire $and$issuer_ls180.v:169487$11326_Y - attribute \src "issuer_ls180.v:169492.17-169492.96" - wire $and$issuer_ls180.v:169492$11331_Y - attribute \src "issuer_ls180.v:169489.18-169489.93" - wire $not$issuer_ls180.v:169489$11328_Y - attribute \src "issuer_ls180.v:169491.17-169491.92" - wire $not$issuer_ls180.v:169491$11330_Y - attribute \src "issuer_ls180.v:169494.17-169494.92" - wire $not$issuer_ls180.v:169494$11333_Y - attribute \src "issuer_ls180.v:169488.18-169488.98" - wire $or$issuer_ls180.v:169488$11327_Y - attribute \src "issuer_ls180.v:169490.18-169490.99" - wire $or$issuer_ls180.v:169490$11329_Y - attribute \src "issuer_ls180.v:169493.17-169493.97" - wire $or$issuer_ls180.v:169493$11332_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:169452.7-169452.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:169487$11326 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:169487$11326_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:169492$11331 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:169492$11331_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:169489$11328 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $not$issuer_ls180.v:169489$11328_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:169491$11330 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$issuer_ls180.v:169491$11330_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:169494$11333 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$issuer_ls180.v:169494$11333_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:169488$11327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rst - connect \Y $or$issuer_ls180.v:169488$11327_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:169490$11329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $or$issuer_ls180.v:169490$11329_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:169493$11332 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rst - connect \Y $or$issuer_ls180.v:169493$11332_Y - end - attribute \src "issuer_ls180.v:169452.7-169452.20" - process $proc$issuer_ls180.v:169452$11338 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:169474.7-169474.19" - process $proc$issuer_ls180.v:169474$11339 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:169495.3-169496.27" - process $proc$issuer_ls180.v:169495$11334 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:169497.3-169505.6" - process $proc$issuer_ls180.v:169497$11335 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$11336 $1\q_int$next[0:0]$11337 - attribute \src "issuer_ls180.v:169498.5-169498.29" - switch \initial - attribute \src "issuer_ls180.v:169498.9-169498.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$11337 1'0 - case - assign $1\q_int$next[0:0]$11337 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$11336 - end - connect \$9 $and$issuer_ls180.v:169487$11326_Y - connect \$11 $or$issuer_ls180.v:169488$11327_Y - connect \$13 $not$issuer_ls180.v:169489$11328_Y - connect \$15 $or$issuer_ls180.v:169490$11329_Y - connect \$1 $not$issuer_ls180.v:169491$11330_Y - connect \$3 $and$issuer_ls180.v:169492$11331_Y - connect \$5 $or$issuer_ls180.v:169493$11332_Y - connect \$7 $not$issuer_ls180.v:169494$11333_Y - connect \qlq_rst \$15 - connect \qn_rst \$13 - connect \q_rst \$11 -end -attribute \src "issuer_ls180.v:169513.1-169571.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rst_l" -attribute \generator "nMigen" -module \rst_l$39 - attribute \src "issuer_ls180.v:169514.7-169514.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:169559.3-169567.6" - wire $0\q_int$next[0:0]$11350 - attribute \src "issuer_ls180.v:169557.3-169558.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:169559.3-169567.6" - wire $1\q_int$next[0:0]$11351 - attribute \src "issuer_ls180.v:169536.7-169536.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:169549.17-169549.96" - wire $and$issuer_ls180.v:169549$11340_Y - attribute \src "issuer_ls180.v:169554.17-169554.96" - wire $and$issuer_ls180.v:169554$11345_Y - attribute \src "issuer_ls180.v:169551.18-169551.93" - wire $not$issuer_ls180.v:169551$11342_Y - attribute \src "issuer_ls180.v:169553.17-169553.92" - wire $not$issuer_ls180.v:169553$11344_Y - attribute \src "issuer_ls180.v:169556.17-169556.92" - wire $not$issuer_ls180.v:169556$11347_Y - attribute \src "issuer_ls180.v:169550.18-169550.98" - wire $or$issuer_ls180.v:169550$11341_Y - attribute \src "issuer_ls180.v:169552.18-169552.99" - wire $or$issuer_ls180.v:169552$11343_Y - attribute \src "issuer_ls180.v:169555.17-169555.97" - wire $or$issuer_ls180.v:169555$11346_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:169514.7-169514.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:169549$11340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:169549$11340_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:169554$11345 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:169554$11345_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:169551$11342 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $not$issuer_ls180.v:169551$11342_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:169553$11344 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$issuer_ls180.v:169553$11344_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:169556$11347 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$issuer_ls180.v:169556$11347_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:169550$11341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rst - connect \Y $or$issuer_ls180.v:169550$11341_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:169552$11343 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $or$issuer_ls180.v:169552$11343_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:169555$11346 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rst - connect \Y $or$issuer_ls180.v:169555$11346_Y - end - attribute \src "issuer_ls180.v:169514.7-169514.20" - process $proc$issuer_ls180.v:169514$11352 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:169536.7-169536.19" - process $proc$issuer_ls180.v:169536$11353 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:169557.3-169558.27" - process $proc$issuer_ls180.v:169557$11348 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:169559.3-169567.6" - process $proc$issuer_ls180.v:169559$11349 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$11350 $1\q_int$next[0:0]$11351 - attribute \src "issuer_ls180.v:169560.5-169560.29" - switch \initial - attribute \src "issuer_ls180.v:169560.9-169560.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$11351 1'0 - case - assign $1\q_int$next[0:0]$11351 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$11350 - end - connect \$9 $and$issuer_ls180.v:169549$11340_Y - connect \$11 $or$issuer_ls180.v:169550$11341_Y - connect \$13 $not$issuer_ls180.v:169551$11342_Y - connect \$15 $or$issuer_ls180.v:169552$11343_Y - connect \$1 $not$issuer_ls180.v:169553$11344_Y - connect \$3 $and$issuer_ls180.v:169554$11345_Y - connect \$5 $or$issuer_ls180.v:169555$11346_Y - connect \$7 $not$issuer_ls180.v:169556$11347_Y - connect \qlq_rst \$15 - connect \qn_rst \$13 - connect \q_rst \$11 -end -attribute \src "issuer_ls180.v:169575.1-169633.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rst_l" -attribute \generator "nMigen" -module \rst_l$55 - attribute \src "issuer_ls180.v:169576.7-169576.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:169621.3-169629.6" - wire $0\q_int$next[0:0]$11364 - attribute \src "issuer_ls180.v:169619.3-169620.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:169621.3-169629.6" - wire $1\q_int$next[0:0]$11365 - attribute \src "issuer_ls180.v:169598.7-169598.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:169611.17-169611.96" - wire $and$issuer_ls180.v:169611$11354_Y - attribute \src "issuer_ls180.v:169616.17-169616.96" - wire $and$issuer_ls180.v:169616$11359_Y - attribute \src "issuer_ls180.v:169613.18-169613.93" - wire $not$issuer_ls180.v:169613$11356_Y - attribute \src "issuer_ls180.v:169615.17-169615.92" - wire $not$issuer_ls180.v:169615$11358_Y - attribute \src "issuer_ls180.v:169618.17-169618.92" - wire $not$issuer_ls180.v:169618$11361_Y - attribute \src "issuer_ls180.v:169612.18-169612.98" - wire $or$issuer_ls180.v:169612$11355_Y - attribute \src "issuer_ls180.v:169614.18-169614.99" - wire $or$issuer_ls180.v:169614$11357_Y - attribute \src "issuer_ls180.v:169617.17-169617.97" - wire $or$issuer_ls180.v:169617$11360_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:169576.7-169576.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:169611$11354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:169611$11354_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:169616$11359 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:169616$11359_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:169613$11356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $not$issuer_ls180.v:169613$11356_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:169615$11358 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$issuer_ls180.v:169615$11358_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:169618$11361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$issuer_ls180.v:169618$11361_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:169612$11355 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rst - connect \Y $or$issuer_ls180.v:169612$11355_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:169614$11357 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $or$issuer_ls180.v:169614$11357_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:169617$11360 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rst - connect \Y $or$issuer_ls180.v:169617$11360_Y - end - attribute \src "issuer_ls180.v:169576.7-169576.20" - process $proc$issuer_ls180.v:169576$11366 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:169598.7-169598.19" - process $proc$issuer_ls180.v:169598$11367 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:169619.3-169620.27" - process $proc$issuer_ls180.v:169619$11362 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:169621.3-169629.6" - process $proc$issuer_ls180.v:169621$11363 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$11364 $1\q_int$next[0:0]$11365 - attribute \src "issuer_ls180.v:169622.5-169622.29" - switch \initial - attribute \src "issuer_ls180.v:169622.9-169622.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$11365 1'0 - case - assign $1\q_int$next[0:0]$11365 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$11364 - end - connect \$9 $and$issuer_ls180.v:169611$11354_Y - connect \$11 $or$issuer_ls180.v:169612$11355_Y - connect \$13 $not$issuer_ls180.v:169613$11356_Y - connect \$15 $or$issuer_ls180.v:169614$11357_Y - connect \$1 $not$issuer_ls180.v:169615$11358_Y - connect \$3 $and$issuer_ls180.v:169616$11359_Y - connect \$5 $or$issuer_ls180.v:169617$11360_Y - connect \$7 $not$issuer_ls180.v:169618$11361_Y - connect \qlq_rst \$15 - connect \qn_rst \$13 - connect \q_rst \$11 -end -attribute \src "issuer_ls180.v:169637.1-169695.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.rst_l" -attribute \generator "nMigen" -module \rst_l$67 - attribute \src "issuer_ls180.v:169638.7-169638.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:169683.3-169691.6" - wire $0\q_int$next[0:0]$11378 - attribute \src "issuer_ls180.v:169681.3-169682.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:169683.3-169691.6" - wire $1\q_int$next[0:0]$11379 - attribute \src "issuer_ls180.v:169660.7-169660.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:169673.17-169673.96" - wire $and$issuer_ls180.v:169673$11368_Y - attribute \src "issuer_ls180.v:169678.17-169678.96" - wire $and$issuer_ls180.v:169678$11373_Y - attribute \src "issuer_ls180.v:169675.18-169675.93" - wire $not$issuer_ls180.v:169675$11370_Y - attribute \src "issuer_ls180.v:169677.17-169677.92" - wire $not$issuer_ls180.v:169677$11372_Y - attribute \src "issuer_ls180.v:169680.17-169680.92" - wire $not$issuer_ls180.v:169680$11375_Y - attribute \src "issuer_ls180.v:169674.18-169674.98" - wire $or$issuer_ls180.v:169674$11369_Y - attribute \src "issuer_ls180.v:169676.18-169676.99" - wire $or$issuer_ls180.v:169676$11371_Y - attribute \src "issuer_ls180.v:169679.17-169679.97" - wire $or$issuer_ls180.v:169679$11374_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:169638.7-169638.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:169673$11368 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:169673$11368_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:169678$11373 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:169678$11373_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:169675$11370 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $not$issuer_ls180.v:169675$11370_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:169677$11372 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$issuer_ls180.v:169677$11372_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:169680$11375 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$issuer_ls180.v:169680$11375_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:169674$11369 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rst - connect \Y $or$issuer_ls180.v:169674$11369_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:169676$11371 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $or$issuer_ls180.v:169676$11371_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:169679$11374 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rst - connect \Y $or$issuer_ls180.v:169679$11374_Y - end - attribute \src "issuer_ls180.v:169638.7-169638.20" - process $proc$issuer_ls180.v:169638$11380 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:169660.7-169660.19" - process $proc$issuer_ls180.v:169660$11381 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:169681.3-169682.27" - process $proc$issuer_ls180.v:169681$11376 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:169683.3-169691.6" - process $proc$issuer_ls180.v:169683$11377 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$11378 $1\q_int$next[0:0]$11379 - attribute \src "issuer_ls180.v:169684.5-169684.29" - switch \initial - attribute \src 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\coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:169700.7-169700.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:169735$11382 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:169735$11382_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:169740$11387 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:169740$11387_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:169737$11384 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $not$issuer_ls180.v:169737$11384_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:169739$11386 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$issuer_ls180.v:169739$11386_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:169742$11389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$issuer_ls180.v:169742$11389_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:169736$11383 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rst - connect \Y $or$issuer_ls180.v:169736$11383_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:169738$11385 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $or$issuer_ls180.v:169738$11385_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:169741$11388 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rst - connect \Y $or$issuer_ls180.v:169741$11388_Y - end - attribute \src "issuer_ls180.v:169700.7-169700.20" - process $proc$issuer_ls180.v:169700$11394 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:169722.7-169722.19" - process $proc$issuer_ls180.v:169722$11395 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:169743.3-169744.27" - process $proc$issuer_ls180.v:169743$11390 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:169745.3-169753.6" - process $proc$issuer_ls180.v:169745$11391 - assign { } { } - assign { } { } - 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 65 \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - wire width 65 \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - wire width 65 \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - wire width 65 \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 65 \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - wire width 65 \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" - wire \$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - wire \$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - wire \$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - wire \$53 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - wire width 32 \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" - wire \$57 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - wire width 32 \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - wire width 128 \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - wire width 95 \$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" - wire width 191 \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" - wire width 191 \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:52" - wire width 64 \abs_dend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:51" - wire width 64 \abs_dor - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire output 46 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire output 44 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire output 45 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 output 47 \dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire output 43 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire output 42 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 output 48 \divisor_radicand - attribute \src "issuer_ls180.v:169762.7-169762.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 39 \logical_op__data_len$18 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 24 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 25 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \logical_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 33 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 40 \logical_op__insn$19 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 23 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 50 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 22 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 output 49 \operation - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 41 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $and $and$issuer_ls180.v:170101$11397 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$21 - connect \B \logical_op__is_signed - connect \Y $and$issuer_ls180.v:170101$11397_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $and $and$issuer_ls180.v:170103$11399 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$25 - connect \B \logical_op__is_signed - connect \Y $and$issuer_ls180.v:170103$11399_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $and $and$issuer_ls180.v:170112$11412 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$43 - connect \B \$45 - connect \Y $and$issuer_ls180.v:170112$11412_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $and $and$issuer_ls180.v:170115$11415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$49 - connect \B \$51 - connect \Y $and$issuer_ls180.v:170115$11415_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $eq $eq$issuer_ls180.v:170111$11411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0011110 - connect \Y $eq$issuer_ls180.v:170111$11411_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $eq $eq$issuer_ls180.v:170114$11414 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0011110 - connect \Y $eq$issuer_ls180.v:170114$11414_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" - cell $eq $eq$issuer_ls180.v:170117$11417 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $eq$issuer_ls180.v:170117$11417_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $pos $extend$issuer_ls180.v:170104$11400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \rb - connect \Y $extend$issuer_ls180.v:170104$11400_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$issuer_ls180.v:170105$11402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \rb - connect \Y $extend$issuer_ls180.v:170105$11402_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $pos $extend$issuer_ls180.v:170107$11405 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \ra - connect \Y $extend$issuer_ls180.v:170107$11405_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$issuer_ls180.v:170108$11407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \ra - connect \Y $extend$issuer_ls180.v:170108$11407_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $extend$issuer_ls180.v:170120$11420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 95 - parameter \Y_WIDTH 128 - connect \A \$62 - connect \Y $extend$issuer_ls180.v:170120$11420_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" - cell $ge $ge$issuer_ls180.v:170110$11410 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \abs_dend - connect \B \abs_dor - connect \Y $ge$issuer_ls180.v:170110$11410_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" - cell $ge $ge$issuer_ls180.v:170113$11413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \abs_dend [31:0] - connect \B \abs_dor [31:0] - connect \Y $ge$issuer_ls180.v:170113$11413_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $neg $neg$issuer_ls180.v:170104$11401 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$issuer_ls180.v:170104$11400_Y - connect \Y $neg$issuer_ls180.v:170104$11401_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $neg $neg$issuer_ls180.v:170107$11406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$issuer_ls180.v:170107$11405_Y - connect \Y $neg$issuer_ls180.v:170107$11406_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$issuer_ls180.v:170105$11403 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$issuer_ls180.v:170105$11402_Y - connect \Y $pos$issuer_ls180.v:170105$11403_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$issuer_ls180.v:170108$11408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$issuer_ls180.v:170108$11407_Y - connect \Y $pos$issuer_ls180.v:170108$11408_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $pos$issuer_ls180.v:170120$11421 - parameter \A_SIGNED 0 - parameter \A_WIDTH 128 - parameter \Y_WIDTH 128 - connect \A $extend$issuer_ls180.v:170120$11420_Y - connect \Y $pos$issuer_ls180.v:170120$11421_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $sshl $sshl$issuer_ls180.v:170119$11419 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 95 - connect \A \abs_dend [31:0] - connect \B 6'100000 - connect \Y $sshl$issuer_ls180.v:170119$11419_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" - cell $sshl $sshl$issuer_ls180.v:170121$11422 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 191 - connect \A \abs_dend - connect \B 7'1000000 - connect \Y $sshl$issuer_ls180.v:170121$11422_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $mux $ternary$issuer_ls180.v:170100$11396 - parameter \WIDTH 1 - connect \A \ra [63] - connect \B \ra [31] - connect \S \logical_op__is_32bit - connect \Y $ternary$issuer_ls180.v:170100$11396_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $mux $ternary$issuer_ls180.v:170102$11398 - parameter \WIDTH 1 - connect \A \rb [63] - connect \B \rb [31] - connect \S \logical_op__is_32bit - connect \Y $ternary$issuer_ls180.v:170102$11398_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $mux $ternary$issuer_ls180.v:170106$11404 - parameter \WIDTH 65 - connect \A \$32 - connect \B \$30 - connect \S \divisor_neg - connect \Y $ternary$issuer_ls180.v:170106$11404_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $mux $ternary$issuer_ls180.v:170109$11409 - parameter \WIDTH 65 - connect \A \$39 - connect \B \$37 - connect \S \dividend_neg - connect \Y $ternary$issuer_ls180.v:170109$11409_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - cell $mux $ternary$issuer_ls180.v:170116$11416 - parameter \WIDTH 32 - connect \A \abs_dor [63:32] - connect \B 0 - connect \S \logical_op__is_32bit - connect \Y $ternary$issuer_ls180.v:170116$11416_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - cell $mux $ternary$issuer_ls180.v:170118$11418 - parameter \WIDTH 32 - connect \A \abs_dend [63:32] - connect \B 0 - connect \S \logical_op__is_32bit - connect \Y $ternary$issuer_ls180.v:170118$11418_Y - end - attribute \src "issuer_ls180.v:169762.7-169762.20" - process $proc$issuer_ls180.v:169762$11424 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:170122.3-170147.6" - process $proc$issuer_ls180.v:170122$11423 - assign { } { } - assign { } { } - assign $0\dividend[127:0] $1\dividend[127:0] - attribute \src "issuer_ls180.v:170123.5-170123.29" - switch \initial - attribute \src "issuer_ls180.v:170123.9-170123.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:72" - switch \logical_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0011101 , 7'0101111 - assign $1\dividend[127:0] [127:64] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\dividend[127:0] [31:0] \abs_dend [31:0] - assign $1\dividend[127:0] [63:32] \$59 - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0011110 - assign { } { } - assign $1\dividend[127:0] $2\dividend[127:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:78" - switch \logical_op__is_32bit - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dividend[127:0] \$61 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\dividend[127:0] \$65 [127:0] - end - case - assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dividend $0\dividend[127:0] - end - connect \$21 $ternary$issuer_ls180.v:170100$11396_Y - connect \$23 $and$issuer_ls180.v:170101$11397_Y - connect \$25 $ternary$issuer_ls180.v:170102$11398_Y - connect \$27 $and$issuer_ls180.v:170103$11399_Y - connect \$30 $neg$issuer_ls180.v:170104$11401_Y - connect \$32 $pos$issuer_ls180.v:170105$11403_Y - connect \$34 $ternary$issuer_ls180.v:170106$11404_Y - connect \$37 $neg$issuer_ls180.v:170107$11406_Y - connect \$39 $pos$issuer_ls180.v:170108$11408_Y - connect \$41 $ternary$issuer_ls180.v:170109$11409_Y - connect \$43 $ge$issuer_ls180.v:170110$11410_Y - connect \$45 $eq$issuer_ls180.v:170111$11411_Y - connect \$47 $and$issuer_ls180.v:170112$11412_Y - connect \$49 $ge$issuer_ls180.v:170113$11413_Y - connect \$51 $eq$issuer_ls180.v:170114$11414_Y - connect \$53 $and$issuer_ls180.v:170115$11415_Y - connect \$55 $ternary$issuer_ls180.v:170116$11416_Y - connect \$57 $eq$issuer_ls180.v:170117$11417_Y - connect \$59 $ternary$issuer_ls180.v:170118$11418_Y - connect \$62 $sshl$issuer_ls180.v:170119$11419_Y - connect \$61 $pos$issuer_ls180.v:170120$11421_Y - connect \$66 $sshl$issuer_ls180.v:170121$11422_Y - connect \$29 \$34 - connect \$36 \$41 - connect \$65 \$66 - connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - connect \muxid$1 \muxid - connect \xer_so$20 \xer_so - connect \div_by_zero \$57 - connect \divisor_radicand [63:32] \$55 - connect \divisor_radicand [31:0] \abs_dor [31:0] - connect \dive_abs_ov32 \$53 - connect \dive_abs_ov64 \$47 - connect \abs_dend \$41 [63:0] - connect \abs_dor \$34 [63:0] - connect \divisor_neg \$27 - connect \dividend_neg \$23 - connect \operation 2'01 -end -attribute \src "issuer_ls180.v:170168.1-171359.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0" -attribute \generator "nMigen" -module \shiftrot0 - attribute \src "issuer_ls180.v:170932.3-170933.25" - wire $0\all_rd_dly[0:0] - attribute \src "issuer_ls180.v:170930.3-170931.46" - wire $0\alu_done_dly[0:0] - attribute \src "issuer_ls180.v:171279.3-171287.6" - wire $0\alu_l_r_alu$next[0:0]$11639 - attribute \src "issuer_ls180.v:170850.3-170851.39" - wire $0\alu_l_r_alu[0:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire width 12 $0\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11558 - attribute \src "issuer_ls180.v:170878.3-170879.75" - wire width 12 $0\alu_shift_rot0_sr_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11559 - attribute \src "issuer_ls180.v:170880.3-170881.89" - wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data[63:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11560 - attribute \src "issuer_ls180.v:170882.3-170883.85" - wire $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$11561 - attribute \src "issuer_ls180.v:170894.3-170895.83" - wire width 2 $0\alu_shift_rot0_sr_op__input_carry[1:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$11562 - attribute \src "issuer_ls180.v:170898.3-170899.77" - wire $0\alu_shift_rot0_sr_op__input_cr[0:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$11563 - attribute \src "issuer_ls180.v:170906.3-170907.69" - wire width 32 $0\alu_shift_rot0_sr_op__insn[31:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$11564 - attribute \src "issuer_ls180.v:170876.3-170877.79" - wire width 7 $0\alu_shift_rot0_sr_op__insn_type[6:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$11565 - attribute \src "issuer_ls180.v:170902.3-170903.77" - wire $0\alu_shift_rot0_sr_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$11566 - attribute \src "issuer_ls180.v:170904.3-170905.79" - wire $0\alu_shift_rot0_sr_op__is_signed[0:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11567 - attribute \src "issuer_ls180.v:170888.3-170889.73" - wire $0\alu_shift_rot0_sr_op__oe__oe[0:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11568 - attribute \src "issuer_ls180.v:170890.3-170891.73" - wire $0\alu_shift_rot0_sr_op__oe__ok[0:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$11569 - attribute \src "issuer_ls180.v:170896.3-170897.85" - wire $0\alu_shift_rot0_sr_op__output_carry[0:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$11570 - attribute \src "issuer_ls180.v:170900.3-170901.79" - wire $0\alu_shift_rot0_sr_op__output_cr[0:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11571 - attribute \src "issuer_ls180.v:170886.3-170887.73" - wire $0\alu_shift_rot0_sr_op__rc__ok[0:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11572 - attribute \src "issuer_ls180.v:170884.3-170885.73" - wire $0\alu_shift_rot0_sr_op__rc__rc[0:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$11573 - attribute \src "issuer_ls180.v:170892.3-170893.79" - wire $0\alu_shift_rot0_sr_op__write_cr0[0:0] - attribute \src "issuer_ls180.v:171270.3-171278.6" - wire $0\alui_l_r_alui$next[0:0]$11636 - attribute \src "issuer_ls180.v:170852.3-170853.43" - wire $0\alui_l_r_alui[0:0] - attribute \src "issuer_ls180.v:171154.3-171175.6" - wire width 64 $0\data_r0__o$next[63:0]$11597 - attribute \src "issuer_ls180.v:170872.3-170873.37" - wire width 64 $0\data_r0__o[63:0] - attribute \src "issuer_ls180.v:171154.3-171175.6" - wire $0\data_r0__o_ok$next[0:0]$11598 - attribute \src "issuer_ls180.v:170874.3-170875.43" - wire $0\data_r0__o_ok[0:0] - attribute \src "issuer_ls180.v:171176.3-171197.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$11605 - attribute \src "issuer_ls180.v:170868.3-170869.43" - wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "issuer_ls180.v:171176.3-171197.6" - wire $0\data_r1__cr_a_ok$next[0:0]$11606 - attribute \src "issuer_ls180.v:170870.3-170871.49" - wire $0\data_r1__cr_a_ok[0:0] - attribute \src "issuer_ls180.v:171198.3-171219.6" - wire width 2 $0\data_r2__xer_ca$next[1:0]$11613 - attribute \src "issuer_ls180.v:170864.3-170865.47" - wire width 2 $0\data_r2__xer_ca[1:0] - attribute \src "issuer_ls180.v:171198.3-171219.6" - wire $0\data_r2__xer_ca_ok$next[0:0]$11614 - attribute \src "issuer_ls180.v:170866.3-170867.53" - wire $0\data_r2__xer_ca_ok[0:0] - attribute \src "issuer_ls180.v:171288.3-171297.6" - wire width 64 $0\dest1_o[63:0] - attribute \src "issuer_ls180.v:171298.3-171307.6" - wire width 4 $0\dest2_o[3:0] - attribute \src "issuer_ls180.v:171308.3-171317.6" - wire width 2 $0\dest3_o[1:0] - attribute \src "issuer_ls180.v:170169.7-170169.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:171072.3-171080.6" - wire $0\opc_l_r_opc$next[0:0]$11543 - attribute \src "issuer_ls180.v:170916.3-170917.39" - wire $0\opc_l_r_opc[0:0] - attribute \src "issuer_ls180.v:171063.3-171071.6" - wire $0\opc_l_s_opc$next[0:0]$11540 - attribute \src "issuer_ls180.v:170918.3-170919.39" - wire $0\opc_l_s_opc[0:0] - attribute \src "issuer_ls180.v:171318.3-171326.6" - wire width 3 $0\prev_wr_go$next[2:0]$11645 - attribute \src "issuer_ls180.v:170928.3-170929.37" - wire width 3 $0\prev_wr_go[2:0] - attribute \src "issuer_ls180.v:171017.3-171026.6" - wire $0\req_done[0:0] - attribute \src "issuer_ls180.v:171108.3-171116.6" - wire width 3 $0\req_l_r_req$next[2:0]$11555 - attribute \src "issuer_ls180.v:170908.3-170909.39" - wire width 3 $0\req_l_r_req[2:0] - attribute \src "issuer_ls180.v:171099.3-171107.6" - wire width 3 $0\req_l_s_req$next[2:0]$11552 - attribute \src "issuer_ls180.v:170910.3-170911.39" - wire width 3 $0\req_l_s_req[2:0] - attribute \src "issuer_ls180.v:171036.3-171044.6" - wire $0\rok_l_r_rdok$next[0:0]$11531 - attribute \src "issuer_ls180.v:170924.3-170925.41" - wire $0\rok_l_r_rdok[0:0] - attribute \src "issuer_ls180.v:171027.3-171035.6" - wire $0\rok_l_s_rdok$next[0:0]$11528 - attribute \src "issuer_ls180.v:170926.3-170927.41" - wire $0\rok_l_s_rdok[0:0] - attribute \src "issuer_ls180.v:171054.3-171062.6" - wire $0\rst_l_r_rst$next[0:0]$11537 - attribute \src "issuer_ls180.v:170920.3-170921.39" - wire $0\rst_l_r_rst[0:0] - attribute \src "issuer_ls180.v:171045.3-171053.6" - wire $0\rst_l_s_rst$next[0:0]$11534 - attribute \src "issuer_ls180.v:170922.3-170923.39" - wire $0\rst_l_s_rst[0:0] - attribute \src "issuer_ls180.v:171090.3-171098.6" - wire width 5 $0\src_l_r_src$next[4:0]$11549 - attribute \src "issuer_ls180.v:170912.3-170913.39" - wire width 5 $0\src_l_r_src[4:0] - attribute \src "issuer_ls180.v:171081.3-171089.6" - wire width 5 $0\src_l_s_src$next[4:0]$11546 - attribute \src "issuer_ls180.v:170914.3-170915.39" - wire width 5 $0\src_l_s_src[4:0] - attribute \src "issuer_ls180.v:171220.3-171229.6" - wire width 64 $0\src_r0$next[63:0]$11621 - attribute \src "issuer_ls180.v:170862.3-170863.29" - wire width 64 $0\src_r0[63:0] - attribute \src "issuer_ls180.v:171230.3-171239.6" - wire width 64 $0\src_r1$next[63:0]$11624 - attribute \src "issuer_ls180.v:170860.3-170861.29" - wire width 64 $0\src_r1[63:0] - attribute \src "issuer_ls180.v:171240.3-171249.6" - wire width 64 $0\src_r2$next[63:0]$11627 - attribute \src "issuer_ls180.v:170858.3-170859.29" - wire width 64 $0\src_r2[63:0] - attribute \src "issuer_ls180.v:171250.3-171259.6" - wire $0\src_r3$next[0:0]$11630 - attribute \src "issuer_ls180.v:170856.3-170857.29" - wire $0\src_r3[0:0] - attribute \src "issuer_ls180.v:171260.3-171269.6" - wire width 2 $0\src_r4$next[1:0]$11633 - attribute \src "issuer_ls180.v:170854.3-170855.29" - wire width 2 $0\src_r4[1:0] - attribute \src "issuer_ls180.v:170291.7-170291.24" - wire $1\all_rd_dly[0:0] - attribute \src "issuer_ls180.v:170301.7-170301.26" - wire $1\alu_done_dly[0:0] - attribute \src "issuer_ls180.v:171279.3-171287.6" - wire $1\alu_l_r_alu$next[0:0]$11640 - attribute \src "issuer_ls180.v:170309.7-170309.25" - wire $1\alu_l_r_alu[0:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire width 12 $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11574 - attribute \src "issuer_ls180.v:170350.14-170350.53" - wire width 12 $1\alu_shift_rot0_sr_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11575 - attribute \src "issuer_ls180.v:170354.14-170354.73" - wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data[63:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11576 - attribute \src "issuer_ls180.v:170358.7-170358.48" - wire $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$11577 - attribute \src "issuer_ls180.v:170366.13-170366.53" - wire width 2 $1\alu_shift_rot0_sr_op__input_carry[1:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$11578 - attribute \src "issuer_ls180.v:170370.7-170370.44" - wire $1\alu_shift_rot0_sr_op__input_cr[0:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$11579 - attribute \src "issuer_ls180.v:170374.14-170374.48" - wire width 32 $1\alu_shift_rot0_sr_op__insn[31:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$11580 - attribute \src "issuer_ls180.v:170452.13-170452.52" - wire width 7 $1\alu_shift_rot0_sr_op__insn_type[6:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$11581 - attribute \src "issuer_ls180.v:170456.7-170456.44" - wire $1\alu_shift_rot0_sr_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$11582 - attribute \src "issuer_ls180.v:170460.7-170460.45" - wire $1\alu_shift_rot0_sr_op__is_signed[0:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11583 - attribute \src "issuer_ls180.v:170464.7-170464.42" - wire $1\alu_shift_rot0_sr_op__oe__oe[0:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11584 - attribute \src "issuer_ls180.v:170468.7-170468.42" - wire $1\alu_shift_rot0_sr_op__oe__ok[0:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$11585 - attribute \src "issuer_ls180.v:170472.7-170472.48" - wire $1\alu_shift_rot0_sr_op__output_carry[0:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$11586 - attribute \src "issuer_ls180.v:170476.7-170476.45" - wire $1\alu_shift_rot0_sr_op__output_cr[0:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11587 - attribute \src "issuer_ls180.v:170480.7-170480.42" - wire $1\alu_shift_rot0_sr_op__rc__ok[0:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11588 - attribute \src "issuer_ls180.v:170484.7-170484.42" - wire $1\alu_shift_rot0_sr_op__rc__rc[0:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$11589 - attribute \src "issuer_ls180.v:170488.7-170488.45" - wire $1\alu_shift_rot0_sr_op__write_cr0[0:0] - attribute \src "issuer_ls180.v:171270.3-171278.6" - wire $1\alui_l_r_alui$next[0:0]$11637 - attribute \src "issuer_ls180.v:170500.7-170500.27" - wire $1\alui_l_r_alui[0:0] - attribute \src "issuer_ls180.v:171154.3-171175.6" - wire width 64 $1\data_r0__o$next[63:0]$11599 - attribute \src "issuer_ls180.v:170534.14-170534.47" - wire width 64 $1\data_r0__o[63:0] - attribute \src "issuer_ls180.v:171154.3-171175.6" - wire $1\data_r0__o_ok$next[0:0]$11600 - attribute \src "issuer_ls180.v:170538.7-170538.27" - wire $1\data_r0__o_ok[0:0] - attribute \src "issuer_ls180.v:171176.3-171197.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$11607 - attribute \src "issuer_ls180.v:170542.13-170542.33" - wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "issuer_ls180.v:171176.3-171197.6" - wire $1\data_r1__cr_a_ok$next[0:0]$11608 - attribute \src "issuer_ls180.v:170546.7-170546.30" - wire $1\data_r1__cr_a_ok[0:0] - attribute \src "issuer_ls180.v:171198.3-171219.6" - wire width 2 $1\data_r2__xer_ca$next[1:0]$11615 - attribute \src "issuer_ls180.v:170550.13-170550.35" - wire width 2 $1\data_r2__xer_ca[1:0] - attribute \src "issuer_ls180.v:171198.3-171219.6" - wire $1\data_r2__xer_ca_ok$next[0:0]$11616 - attribute \src "issuer_ls180.v:170554.7-170554.32" - wire $1\data_r2__xer_ca_ok[0:0] - attribute \src "issuer_ls180.v:171288.3-171297.6" - wire width 64 $1\dest1_o[63:0] - attribute \src "issuer_ls180.v:171298.3-171307.6" - wire width 4 $1\dest2_o[3:0] - attribute \src "issuer_ls180.v:171308.3-171317.6" - wire width 2 $1\dest3_o[1:0] - attribute \src "issuer_ls180.v:171072.3-171080.6" - wire $1\opc_l_r_opc$next[0:0]$11544 - attribute \src "issuer_ls180.v:170571.7-170571.25" - wire $1\opc_l_r_opc[0:0] - attribute \src "issuer_ls180.v:171063.3-171071.6" - wire $1\opc_l_s_opc$next[0:0]$11541 - attribute \src "issuer_ls180.v:170575.7-170575.25" - wire $1\opc_l_s_opc[0:0] - attribute \src "issuer_ls180.v:171318.3-171326.6" - wire width 3 $1\prev_wr_go$next[2:0]$11646 - attribute \src "issuer_ls180.v:170702.13-170702.30" - wire width 3 $1\prev_wr_go[2:0] - attribute \src "issuer_ls180.v:171017.3-171026.6" - wire $1\req_done[0:0] - attribute \src "issuer_ls180.v:171108.3-171116.6" - wire width 3 $1\req_l_r_req$next[2:0]$11556 - attribute \src "issuer_ls180.v:170710.13-170710.31" - wire width 3 $1\req_l_r_req[2:0] - attribute \src "issuer_ls180.v:171099.3-171107.6" - wire width 3 $1\req_l_s_req$next[2:0]$11553 - attribute \src "issuer_ls180.v:170714.13-170714.31" - wire width 3 $1\req_l_s_req[2:0] - attribute \src "issuer_ls180.v:171036.3-171044.6" - wire $1\rok_l_r_rdok$next[0:0]$11532 - attribute \src "issuer_ls180.v:170726.7-170726.26" - wire $1\rok_l_r_rdok[0:0] - attribute \src "issuer_ls180.v:171027.3-171035.6" - wire $1\rok_l_s_rdok$next[0:0]$11529 - attribute \src "issuer_ls180.v:170730.7-170730.26" - wire $1\rok_l_s_rdok[0:0] - attribute \src "issuer_ls180.v:171054.3-171062.6" - wire $1\rst_l_r_rst$next[0:0]$11538 - attribute \src "issuer_ls180.v:170734.7-170734.25" - wire $1\rst_l_r_rst[0:0] - attribute \src "issuer_ls180.v:171045.3-171053.6" - wire $1\rst_l_s_rst$next[0:0]$11535 - attribute \src "issuer_ls180.v:170738.7-170738.25" - wire $1\rst_l_s_rst[0:0] - attribute \src "issuer_ls180.v:171090.3-171098.6" - wire width 5 $1\src_l_r_src$next[4:0]$11550 - attribute \src "issuer_ls180.v:170756.13-170756.32" - wire width 5 $1\src_l_r_src[4:0] - attribute \src "issuer_ls180.v:171081.3-171089.6" - wire width 5 $1\src_l_s_src$next[4:0]$11547 - attribute \src "issuer_ls180.v:170760.13-170760.32" - wire width 5 $1\src_l_s_src[4:0] - attribute \src "issuer_ls180.v:171220.3-171229.6" - wire width 64 $1\src_r0$next[63:0]$11622 - attribute \src "issuer_ls180.v:170766.14-170766.43" - wire width 64 $1\src_r0[63:0] - attribute \src "issuer_ls180.v:171230.3-171239.6" - wire width 64 $1\src_r1$next[63:0]$11625 - attribute \src "issuer_ls180.v:170770.14-170770.43" - wire width 64 $1\src_r1[63:0] - attribute \src "issuer_ls180.v:171240.3-171249.6" - wire width 64 $1\src_r2$next[63:0]$11628 - attribute \src "issuer_ls180.v:170774.14-170774.43" - wire width 64 $1\src_r2[63:0] - attribute \src "issuer_ls180.v:171250.3-171259.6" - wire $1\src_r3$next[0:0]$11631 - attribute \src "issuer_ls180.v:170778.7-170778.20" - wire $1\src_r3[0:0] - attribute \src "issuer_ls180.v:171260.3-171269.6" - wire width 2 $1\src_r4$next[1:0]$11634 - attribute \src "issuer_ls180.v:170782.13-170782.26" - wire width 2 $1\src_r4[1:0] - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11590 - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11591 - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11592 - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11593 - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11594 - attribute \src "issuer_ls180.v:171117.3-171153.6" - wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11595 - attribute \src "issuer_ls180.v:171154.3-171175.6" - wire width 64 $2\data_r0__o$next[63:0]$11601 - attribute \src "issuer_ls180.v:171154.3-171175.6" - wire $2\data_r0__o_ok$next[0:0]$11602 - attribute \src "issuer_ls180.v:171176.3-171197.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$11609 - attribute \src "issuer_ls180.v:171176.3-171197.6" - wire $2\data_r1__cr_a_ok$next[0:0]$11610 - attribute \src "issuer_ls180.v:171198.3-171219.6" - wire width 2 $2\data_r2__xer_ca$next[1:0]$11617 - attribute \src "issuer_ls180.v:171198.3-171219.6" - wire $2\data_r2__xer_ca_ok$next[0:0]$11618 - attribute \src "issuer_ls180.v:171154.3-171175.6" - wire $3\data_r0__o_ok$next[0:0]$11603 - attribute \src "issuer_ls180.v:171176.3-171197.6" - wire $3\data_r1__cr_a_ok$next[0:0]$11611 - attribute \src "issuer_ls180.v:171198.3-171219.6" - wire $3\data_r2__xer_ca_ok$next[0:0]$11619 - attribute \src "issuer_ls180.v:170792.19-170792.114" - wire width 5 $and$issuer_ls180.v:170792$11426_Y - attribute \src "issuer_ls180.v:170793.19-170793.125" - wire $and$issuer_ls180.v:170793$11427_Y - attribute \src "issuer_ls180.v:170794.19-170794.125" - wire $and$issuer_ls180.v:170794$11428_Y - attribute \src "issuer_ls180.v:170795.19-170795.125" - wire $and$issuer_ls180.v:170795$11429_Y - attribute \src "issuer_ls180.v:170796.18-170796.110" - wire $and$issuer_ls180.v:170796$11430_Y - attribute \src "issuer_ls180.v:170797.19-170797.141" - wire width 3 $and$issuer_ls180.v:170797$11431_Y - attribute \src "issuer_ls180.v:170798.19-170798.121" - wire width 3 $and$issuer_ls180.v:170798$11432_Y - attribute \src "issuer_ls180.v:170799.19-170799.127" - wire $and$issuer_ls180.v:170799$11433_Y - attribute \src "issuer_ls180.v:170800.19-170800.127" - wire $and$issuer_ls180.v:170800$11434_Y - attribute \src "issuer_ls180.v:170801.19-170801.127" - wire $and$issuer_ls180.v:170801$11435_Y - attribute \src "issuer_ls180.v:170803.18-170803.98" - wire $and$issuer_ls180.v:170803$11437_Y - attribute \src "issuer_ls180.v:170805.18-170805.100" - wire $and$issuer_ls180.v:170805$11439_Y - attribute \src "issuer_ls180.v:170806.18-170806.149" - wire width 3 $and$issuer_ls180.v:170806$11440_Y - attribute \src "issuer_ls180.v:170808.18-170808.119" - wire width 3 $and$issuer_ls180.v:170808$11442_Y - attribute \src "issuer_ls180.v:170811.17-170811.123" - wire $and$issuer_ls180.v:170811$11445_Y - attribute \src "issuer_ls180.v:170812.18-170812.116" - wire $and$issuer_ls180.v:170812$11446_Y - attribute \src "issuer_ls180.v:170817.18-170817.113" - wire $and$issuer_ls180.v:170817$11451_Y - attribute \src "issuer_ls180.v:170818.18-170818.125" - wire width 3 $and$issuer_ls180.v:170818$11452_Y - attribute \src "issuer_ls180.v:170820.18-170820.112" - wire $and$issuer_ls180.v:170820$11454_Y - attribute \src "issuer_ls180.v:170822.18-170822.132" - wire $and$issuer_ls180.v:170822$11456_Y - attribute \src "issuer_ls180.v:170823.18-170823.132" - wire $and$issuer_ls180.v:170823$11457_Y - attribute \src "issuer_ls180.v:170824.18-170824.117" - wire $and$issuer_ls180.v:170824$11458_Y - attribute \src "issuer_ls180.v:170830.18-170830.136" - wire $and$issuer_ls180.v:170830$11464_Y - attribute \src "issuer_ls180.v:170831.18-170831.124" - wire width 3 $and$issuer_ls180.v:170831$11465_Y - attribute \src "issuer_ls180.v:170833.18-170833.116" - wire $and$issuer_ls180.v:170833$11467_Y - attribute \src "issuer_ls180.v:170834.18-170834.119" - wire $and$issuer_ls180.v:170834$11468_Y - attribute \src "issuer_ls180.v:170835.18-170835.121" - wire $and$issuer_ls180.v:170835$11469_Y - attribute \src "issuer_ls180.v:170845.18-170845.140" - wire $and$issuer_ls180.v:170845$11479_Y - attribute \src "issuer_ls180.v:170846.18-170846.138" - wire $and$issuer_ls180.v:170846$11480_Y - attribute \src "issuer_ls180.v:170847.18-170847.171" - wire width 5 $and$issuer_ls180.v:170847$11481_Y - attribute \src "issuer_ls180.v:170849.18-170849.129" - wire width 5 $and$issuer_ls180.v:170849$11483_Y - attribute \src "issuer_ls180.v:170819.18-170819.113" - wire $eq$issuer_ls180.v:170819$11453_Y - attribute \src "issuer_ls180.v:170821.18-170821.119" - wire $eq$issuer_ls180.v:170821$11455_Y - attribute \src "issuer_ls180.v:170791.19-170791.115" - wire width 5 $not$issuer_ls180.v:170791$11425_Y - attribute \src "issuer_ls180.v:170802.18-170802.97" - wire $not$issuer_ls180.v:170802$11436_Y - attribute \src "issuer_ls180.v:170804.18-170804.99" - wire $not$issuer_ls180.v:170804$11438_Y - attribute \src "issuer_ls180.v:170807.18-170807.113" - wire width 3 $not$issuer_ls180.v:170807$11441_Y - attribute \src "issuer_ls180.v:170810.18-170810.106" - wire $not$issuer_ls180.v:170810$11444_Y - attribute \src "issuer_ls180.v:170816.18-170816.126" - wire $not$issuer_ls180.v:170816$11450_Y - attribute \src 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\alu_shift_rot0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_shift_rot0_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \alu_shift_rot0_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \alu_shift_rot0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_shift_rot0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_shift_rot0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_shift_rot0_rc - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__imm_data__ok$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_shift_rot0_sr_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_shift_rot0_sr_op__input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__input_cr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_shift_rot0_sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 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attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_shift_rot0_sr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_shift_rot0_sr_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__output_cr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \alu_shift_rot0_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \alu_shift_rot0_xer_ca$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \alu_shift_rot0_xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 36 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 35 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 31 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 18 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 17 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 input 21 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 output 20 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 5 input 19 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" - wire \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 29 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 28 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 3 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r0__o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r1__cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r2__xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r2__xer_ca$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r2__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r2__xer_ca_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 30 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 32 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 34 \dest3_o - attribute \src "issuer_ls180.v:170169.7-170169.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 27 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \opc_l_s_opc$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \oper_i_alu_shift_rot0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \oper_i_alu_shift_rot0__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \oper_i_alu_shift_rot0__imm_data__ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 10 \oper_i_alu_shift_rot0__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \oper_i_alu_shift_rot0__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 16 \oper_i_alu_shift_rot0__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \oper_i_alu_shift_rot0__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \oper_i_alu_shift_rot0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \oper_i_alu_shift_rot0__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \oper_i_alu_shift_rot0__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \oper_i_alu_shift_rot0__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \oper_i_alu_shift_rot0__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \oper_i_alu_shift_rot0__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \oper_i_alu_shift_rot0__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \oper_i_alu_shift_rot0__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \oper_i_alu_shift_rot0__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 3 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 3 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" - wire \req_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \req_l_r_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \req_l_s_req$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" - wire \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 5 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" - wire width 3 \reset_w - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \rok_l_r_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \rok_l_s_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \rst_l_r_rst$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \rst_l_s_rst$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" - wire \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 22 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 23 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 24 \src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 25 \src4_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 26 \src5_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 5 \src_l_q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire \src_r3$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - wire \src_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" - wire \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 33 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$issuer_ls180.v:170792$11426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$98 - connect \B \$100 - connect \Y $and$issuer_ls180.v:170792$11426_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$issuer_ls180.v:170793$11427 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $and$issuer_ls180.v:170793$11427_Y - end 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\Y $and$issuer_ls180.v:170796$11430_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$issuer_ls180.v:170797$11431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \req_l_q_req - connect \B { \$104 \$106 \$108 } - connect \Y $and$issuer_ls180.v:170797$11431_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$issuer_ls180.v:170798$11432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$110 - connect \B \cu_wrmask_o - connect \Y $and$issuer_ls180.v:170798$11432_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$issuer_ls180.v:170799$11433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:170799$11433_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$issuer_ls180.v:170800$11434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:170800$11434_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$issuer_ls180.v:170801$11435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [2] - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:170801$11435_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:170803$11437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd - connect \B \$12 - connect \Y $and$issuer_ls180.v:170803$11437_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:170805$11439 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done - connect \B \$16 - connect \Y $and$issuer_ls180.v:170805$11439_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$issuer_ls180.v:170806$11440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$issuer_ls180.v:170806$11440_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$issuer_ls180.v:170808$11442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__rel_o - connect \B \$24 - connect \Y $and$issuer_ls180.v:170808$11442_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$issuer_ls180.v:170811$11445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \rok_l_q_rdok - connect \Y $and$issuer_ls180.v:170811$11445_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$issuer_ls180.v:170812$11446 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \$22 - connect \Y $and$issuer_ls180.v:170812$11446_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$issuer_ls180.v:170817$11451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_any - connect \B \$38 - connect \Y $and$issuer_ls180.v:170817$11451_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$issuer_ls180.v:170818$11452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \req_l_q_req - connect \B \cu_wrmask_o - connect \Y $and$issuer_ls180.v:170818$11452_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$issuer_ls180.v:170820$11454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$40 - connect \B \$44 - connect \Y $and$issuer_ls180.v:170820$11454_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$issuer_ls180.v:170822$11456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$48 - connect \B \alu_shift_rot0_n_ready_i - connect \Y $and$issuer_ls180.v:170822$11456_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$issuer_ls180.v:170823$11457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$50 - connect \B \alu_shift_rot0_n_valid_o - connect \Y $and$issuer_ls180.v:170823$11457_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$issuer_ls180.v:170824$11458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$52 - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:170824$11458_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$issuer_ls180.v:170830$11464 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_shift_rot0_n_valid_o - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:170830$11464_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$issuer_ls180.v:170831$11465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $and$issuer_ls180.v:170831$11465_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$issuer_ls180.v:170833$11467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o_ok - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:170833$11467_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$issuer_ls180.v:170834$11468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cr_a_ok - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:170834$11468_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$issuer_ls180.v:170835$11469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_ca_ok - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:170835$11469_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$issuer_ls180.v:170845$11479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_shift_rot0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $and$issuer_ls180.v:170845$11479_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$issuer_ls180.v:170846$11480 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_shift_rot0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $and$issuer_ls180.v:170846$11480_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$issuer_ls180.v:170847$11481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$issuer_ls180.v:170847$11481_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$issuer_ls180.v:170849$11483 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$94 - connect \B { 3'111 \$96 1'1 } - connect \Y $and$issuer_ls180.v:170849$11483_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$issuer_ls180.v:170819$11453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$42 - connect \B 1'0 - connect \Y $eq$issuer_ls180.v:170819$11453_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$issuer_ls180.v:170821$11455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o - connect \B 1'0 - connect \Y $eq$issuer_ls180.v:170821$11455_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$issuer_ls180.v:170791$11425 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_rdmaskn_i - connect \Y $not$issuer_ls180.v:170791$11425_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:170802$11436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $not$issuer_ls180.v:170802$11436_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:170804$11438 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $not$issuer_ls180.v:170804$11438_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$issuer_ls180.v:170807$11441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wrmask_o - connect \Y $not$issuer_ls180.v:170807$11441_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$issuer_ls180.v:170810$11444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$23 - connect \Y $not$issuer_ls180.v:170810$11444_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$issuer_ls180.v:170816$11450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_shift_rot0_n_ready_i - connect \Y $not$issuer_ls180.v:170816$11450_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$issuer_ls180.v:170827$11461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_rd__rel_o - connect \Y $not$issuer_ls180.v:170827$11461_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$issuer_ls180.v:170848$11482 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $not$issuer_ls180.v:170848$11482_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$issuer_ls180.v:170815$11449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$32 - connect \B \$34 - connect \Y $or$issuer_ls180.v:170815$11449_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$issuer_ls180.v:170825$11459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $or$issuer_ls180.v:170825$11459_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$issuer_ls180.v:170826$11460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $or$issuer_ls180.v:170826$11460_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$issuer_ls180.v:170828$11462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$issuer_ls180.v:170828$11462_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$issuer_ls180.v:170829$11463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$issuer_ls180.v:170829$11463_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$issuer_ls180.v:170832$11466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $or$issuer_ls180.v:170832$11466_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$issuer_ls180.v:170838$11472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$5 - connect \B \cu_rd__go_i - connect \Y $or$issuer_ls180.v:170838$11472_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$issuer_ls180.v:170844$11478 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \$7 - connect \Y $reduce_and$issuer_ls180.v:170844$11478_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$issuer_ls180.v:170809$11443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \$26 - connect \Y $reduce_or$issuer_ls180.v:170809$11443_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$issuer_ls180.v:170813$11447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $reduce_or$issuer_ls180.v:170813$11447_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$issuer_ls180.v:170814$11448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $reduce_or$issuer_ls180.v:170814$11448_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$issuer_ls180.v:170836$11470 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $ternary$issuer_ls180.v:170836$11470_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$issuer_ls180.v:170837$11471 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \alu_shift_rot0_sr_op__imm_data__data - connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $ternary$issuer_ls180.v:170837$11471_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:170839$11473 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src1_i - connect \S \src_l_q_src [0] - connect \Y $ternary$issuer_ls180.v:170839$11473_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:170840$11474 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $ternary$issuer_ls180.v:170840$11474_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:170841$11475 - parameter \WIDTH 64 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $ternary$issuer_ls180.v:170841$11475_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:170842$11476 - parameter \WIDTH 1 - connect \A \src_r3 - connect \B \src4_i - connect \S \src_l_q_src [3] - connect \Y $ternary$issuer_ls180.v:170842$11476_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:170843$11477 - parameter \WIDTH 2 - connect \A \src_r4 - connect \B \src5_i - connect \S \src_l_q_src [4] - connect \Y $ternary$issuer_ls180.v:170843$11477_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:170934.15-170940.4" - cell \alu_l$122 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:170941.18-170975.4" - cell \alu_shift_rot0 \alu_shift_rot0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \alu_shift_rot0_cr_a - connect \cr_a_ok \cr_a_ok - connect \n_ready_i \alu_shift_rot0_n_ready_i - connect \n_valid_o \alu_shift_rot0_n_valid_o - connect \o \alu_shift_rot0_o - connect \o_ok \o_ok - connect \p_ready_o \alu_shift_rot0_p_ready_o - connect \p_valid_i \alu_shift_rot0_p_valid_i - connect \ra \alu_shift_rot0_ra - connect \rb \alu_shift_rot0_rb - connect \rc \alu_shift_rot0_rc - connect \sr_op__fn_unit \alu_shift_rot0_sr_op__fn_unit - connect \sr_op__imm_data__data \alu_shift_rot0_sr_op__imm_data__data - connect \sr_op__imm_data__ok \alu_shift_rot0_sr_op__imm_data__ok - connect \sr_op__input_carry \alu_shift_rot0_sr_op__input_carry - connect \sr_op__input_cr \alu_shift_rot0_sr_op__input_cr - connect \sr_op__insn \alu_shift_rot0_sr_op__insn - connect \sr_op__insn_type \alu_shift_rot0_sr_op__insn_type - connect \sr_op__is_32bit \alu_shift_rot0_sr_op__is_32bit - connect \sr_op__is_signed \alu_shift_rot0_sr_op__is_signed - connect \sr_op__oe__oe \alu_shift_rot0_sr_op__oe__oe - connect \sr_op__oe__ok \alu_shift_rot0_sr_op__oe__ok - connect \sr_op__output_carry \alu_shift_rot0_sr_op__output_carry - connect \sr_op__output_cr \alu_shift_rot0_sr_op__output_cr - connect \sr_op__rc__ok \alu_shift_rot0_sr_op__rc__ok - connect \sr_op__rc__rc \alu_shift_rot0_sr_op__rc__rc - connect \sr_op__write_cr0 \alu_shift_rot0_sr_op__write_cr0 - connect \xer_ca \alu_shift_rot0_xer_ca - connect \xer_ca$1 \alu_shift_rot0_xer_ca$1 - connect \xer_ca_ok \xer_ca_ok - connect \xer_so \alu_shift_rot0_xer_so - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:170976.16-170982.4" - cell \alui_l$121 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:170983.15-170989.4" - cell \opc_l$117 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_opc \opc_l_q_opc - connect \r_opc \opc_l_r_opc - connect \s_opc \opc_l_s_opc - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:170990.15-170996.4" - cell \req_l$118 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \r_req \req_l_r_req - connect \s_req \req_l_s_req - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:170997.15-171003.4" - cell \rok_l$120 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \r_rdok \rok_l_r_rdok - connect \s_rdok \rok_l_s_rdok - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:171004.15-171009.4" - cell \rst_l$119 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_rst \rst_l_r_rst - connect \s_rst \rst_l_s_rst - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:171010.15-171016.4" - cell \src_l$116 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_src \src_l_q_src - connect \r_src \src_l_r_src - connect \s_src \src_l_s_src - end - attribute \src "issuer_ls180.v:170169.7-170169.20" - process $proc$issuer_ls180.v:170169$11647 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:170291.7-170291.24" - process $proc$issuer_ls180.v:170291$11648 - assign { } { } - assign $1\all_rd_dly[0:0] 1'0 - sync always - sync init - update \all_rd_dly $1\all_rd_dly[0:0] - end - attribute \src "issuer_ls180.v:170301.7-170301.26" - process $proc$issuer_ls180.v:170301$11649 - assign { } { } - assign $1\alu_done_dly[0:0] 1'0 - sync always - sync init - update \alu_done_dly $1\alu_done_dly[0:0] - end - attribute \src "issuer_ls180.v:170309.7-170309.25" - process $proc$issuer_ls180.v:170309$11650 - assign { } { } - assign $1\alu_l_r_alu[0:0] 1'1 - sync always - sync init - update \alu_l_r_alu $1\alu_l_r_alu[0:0] - end - attribute \src "issuer_ls180.v:170350.14-170350.53" - process $proc$issuer_ls180.v:170350$11651 - assign { } { } - assign $1\alu_shift_rot0_sr_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \alu_shift_rot0_sr_op__fn_unit $1\alu_shift_rot0_sr_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:170354.14-170354.73" - process $proc$issuer_ls180.v:170354$11652 - assign { } { } - assign $1\alu_shift_rot0_sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_shift_rot0_sr_op__imm_data__data $1\alu_shift_rot0_sr_op__imm_data__data[63:0] - end - attribute \src "issuer_ls180.v:170358.7-170358.48" - process $proc$issuer_ls180.v:170358$11653 - assign { } { } - assign $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \alu_shift_rot0_sr_op__imm_data__ok $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:170366.13-170366.53" - process $proc$issuer_ls180.v:170366$11654 - assign { } { } - assign $1\alu_shift_rot0_sr_op__input_carry[1:0] 2'00 - sync always - sync init - update \alu_shift_rot0_sr_op__input_carry $1\alu_shift_rot0_sr_op__input_carry[1:0] - end - attribute \src "issuer_ls180.v:170370.7-170370.44" - process $proc$issuer_ls180.v:170370$11655 - assign { } { } - assign $1\alu_shift_rot0_sr_op__input_cr[0:0] 1'0 - sync always - sync init - update \alu_shift_rot0_sr_op__input_cr $1\alu_shift_rot0_sr_op__input_cr[0:0] - end - attribute \src "issuer_ls180.v:170374.14-170374.48" - process $proc$issuer_ls180.v:170374$11656 - assign { } { } - assign $1\alu_shift_rot0_sr_op__insn[31:0] 0 - sync always - sync init - update \alu_shift_rot0_sr_op__insn $1\alu_shift_rot0_sr_op__insn[31:0] - end - attribute \src "issuer_ls180.v:170452.13-170452.52" - process $proc$issuer_ls180.v:170452$11657 - assign { } { } - assign $1\alu_shift_rot0_sr_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \alu_shift_rot0_sr_op__insn_type $1\alu_shift_rot0_sr_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:170456.7-170456.44" - process $proc$issuer_ls180.v:170456$11658 - assign { } { } - assign $1\alu_shift_rot0_sr_op__is_32bit[0:0] 1'0 - sync always - sync init - update \alu_shift_rot0_sr_op__is_32bit $1\alu_shift_rot0_sr_op__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:170460.7-170460.45" - process $proc$issuer_ls180.v:170460$11659 - assign { } { } - assign $1\alu_shift_rot0_sr_op__is_signed[0:0] 1'0 - sync always - sync init - update \alu_shift_rot0_sr_op__is_signed $1\alu_shift_rot0_sr_op__is_signed[0:0] - end - attribute \src "issuer_ls180.v:170464.7-170464.42" - process $proc$issuer_ls180.v:170464$11660 - assign { } { } - assign $1\alu_shift_rot0_sr_op__oe__oe[0:0] 1'0 - sync always - sync init - update \alu_shift_rot0_sr_op__oe__oe $1\alu_shift_rot0_sr_op__oe__oe[0:0] - end - attribute \src "issuer_ls180.v:170468.7-170468.42" - process $proc$issuer_ls180.v:170468$11661 - assign { } { } - assign $1\alu_shift_rot0_sr_op__oe__ok[0:0] 1'0 - sync always - sync init - update \alu_shift_rot0_sr_op__oe__ok $1\alu_shift_rot0_sr_op__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:170472.7-170472.48" - process $proc$issuer_ls180.v:170472$11662 - assign { } { } - assign $1\alu_shift_rot0_sr_op__output_carry[0:0] 1'0 - sync always - sync init - update \alu_shift_rot0_sr_op__output_carry $1\alu_shift_rot0_sr_op__output_carry[0:0] - end - attribute \src "issuer_ls180.v:170476.7-170476.45" - process $proc$issuer_ls180.v:170476$11663 - assign { } { } - assign $1\alu_shift_rot0_sr_op__output_cr[0:0] 1'0 - sync always - sync init - update \alu_shift_rot0_sr_op__output_cr $1\alu_shift_rot0_sr_op__output_cr[0:0] - end - attribute \src "issuer_ls180.v:170480.7-170480.42" - process $proc$issuer_ls180.v:170480$11664 - assign { } { } - assign $1\alu_shift_rot0_sr_op__rc__ok[0:0] 1'0 - sync always - sync init - update \alu_shift_rot0_sr_op__rc__ok $1\alu_shift_rot0_sr_op__rc__ok[0:0] - end - attribute \src "issuer_ls180.v:170484.7-170484.42" - process $proc$issuer_ls180.v:170484$11665 - assign { } { } - assign $1\alu_shift_rot0_sr_op__rc__rc[0:0] 1'0 - sync always - sync init - update \alu_shift_rot0_sr_op__rc__rc $1\alu_shift_rot0_sr_op__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:170488.7-170488.45" - process $proc$issuer_ls180.v:170488$11666 - assign { } { } - assign $1\alu_shift_rot0_sr_op__write_cr0[0:0] 1'0 - sync always - sync init - update \alu_shift_rot0_sr_op__write_cr0 $1\alu_shift_rot0_sr_op__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:170500.7-170500.27" - process $proc$issuer_ls180.v:170500$11667 - assign { } { } - assign $1\alui_l_r_alui[0:0] 1'1 - sync always - sync init - update \alui_l_r_alui $1\alui_l_r_alui[0:0] - end - attribute \src "issuer_ls180.v:170534.14-170534.47" - process $proc$issuer_ls180.v:170534$11668 - assign { } { } - assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r0__o $1\data_r0__o[63:0] - end - attribute \src "issuer_ls180.v:170538.7-170538.27" - process $proc$issuer_ls180.v:170538$11669 - assign { } { } - assign $1\data_r0__o_ok[0:0] 1'0 - sync always - sync init - update \data_r0__o_ok $1\data_r0__o_ok[0:0] - end - attribute \src "issuer_ls180.v:170542.13-170542.33" - process $proc$issuer_ls180.v:170542$11670 - assign { } { } - assign $1\data_r1__cr_a[3:0] 4'0000 - sync always - sync init - update \data_r1__cr_a $1\data_r1__cr_a[3:0] - end - attribute \src "issuer_ls180.v:170546.7-170546.30" - process $proc$issuer_ls180.v:170546$11671 - assign { } { } - assign $1\data_r1__cr_a_ok[0:0] 1'0 - sync always - sync init - update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:170550.13-170550.35" - process $proc$issuer_ls180.v:170550$11672 - assign { } { } - assign $1\data_r2__xer_ca[1:0] 2'00 - sync always - sync init - update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] - end - attribute \src "issuer_ls180.v:170554.7-170554.32" - process $proc$issuer_ls180.v:170554$11673 - assign { } { } - assign $1\data_r2__xer_ca_ok[0:0] 1'0 - sync always - sync init - update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] - end - attribute \src "issuer_ls180.v:170571.7-170571.25" - process $proc$issuer_ls180.v:170571$11674 - assign { } { } - assign $1\opc_l_r_opc[0:0] 1'1 - sync always - sync init - update \opc_l_r_opc $1\opc_l_r_opc[0:0] - end - attribute \src "issuer_ls180.v:170575.7-170575.25" - process $proc$issuer_ls180.v:170575$11675 - assign { } { } - assign $1\opc_l_s_opc[0:0] 1'0 - sync always - sync init - update \opc_l_s_opc $1\opc_l_s_opc[0:0] - end - attribute \src "issuer_ls180.v:170702.13-170702.30" - process $proc$issuer_ls180.v:170702$11676 - assign { } { } - assign $1\prev_wr_go[2:0] 3'000 - sync always - sync init - update \prev_wr_go $1\prev_wr_go[2:0] - end - attribute \src "issuer_ls180.v:170710.13-170710.31" - process $proc$issuer_ls180.v:170710$11677 - assign { } { } - assign $1\req_l_r_req[2:0] 3'111 - sync always - sync init - update \req_l_r_req $1\req_l_r_req[2:0] - end - attribute \src "issuer_ls180.v:170714.13-170714.31" - process $proc$issuer_ls180.v:170714$11678 - assign { } { } - assign $1\req_l_s_req[2:0] 3'000 - sync always - sync init - update \req_l_s_req $1\req_l_s_req[2:0] - end - attribute \src "issuer_ls180.v:170726.7-170726.26" - process $proc$issuer_ls180.v:170726$11679 - assign { } { } - assign $1\rok_l_r_rdok[0:0] 1'1 - sync always - sync init - update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] - end - attribute \src "issuer_ls180.v:170730.7-170730.26" - process $proc$issuer_ls180.v:170730$11680 - assign { } { } - assign $1\rok_l_s_rdok[0:0] 1'0 - sync always - sync init - update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] - end - attribute \src "issuer_ls180.v:170734.7-170734.25" - process $proc$issuer_ls180.v:170734$11681 - assign { } { } - assign $1\rst_l_r_rst[0:0] 1'1 - sync always - sync init - update \rst_l_r_rst $1\rst_l_r_rst[0:0] - end - attribute \src "issuer_ls180.v:170738.7-170738.25" - process $proc$issuer_ls180.v:170738$11682 - assign { } { } - assign $1\rst_l_s_rst[0:0] 1'0 - sync always - sync init - update \rst_l_s_rst $1\rst_l_s_rst[0:0] - end - attribute \src "issuer_ls180.v:170756.13-170756.32" - process $proc$issuer_ls180.v:170756$11683 - assign { } { } - assign $1\src_l_r_src[4:0] 5'11111 - sync always - sync init - update \src_l_r_src $1\src_l_r_src[4:0] - end - attribute \src "issuer_ls180.v:170760.13-170760.32" - process $proc$issuer_ls180.v:170760$11684 - assign { } { } - assign $1\src_l_s_src[4:0] 5'00000 - sync always - sync init - update \src_l_s_src $1\src_l_s_src[4:0] - end - attribute \src "issuer_ls180.v:170766.14-170766.43" - process $proc$issuer_ls180.v:170766$11685 - assign { } { } - assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r0 $1\src_r0[63:0] - end - attribute \src "issuer_ls180.v:170770.14-170770.43" - process $proc$issuer_ls180.v:170770$11686 - assign { } { } - assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r1 $1\src_r1[63:0] - end - attribute \src "issuer_ls180.v:170774.14-170774.43" - process $proc$issuer_ls180.v:170774$11687 - assign { } { } - assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r2 $1\src_r2[63:0] - end - attribute \src "issuer_ls180.v:170778.7-170778.20" - process $proc$issuer_ls180.v:170778$11688 - assign { } { } - assign $1\src_r3[0:0] 1'0 - sync always - sync init - update \src_r3 $1\src_r3[0:0] - end - attribute \src "issuer_ls180.v:170782.13-170782.26" - process $proc$issuer_ls180.v:170782$11689 - assign { } { } - assign $1\src_r4[1:0] 2'00 - sync always - sync init - update \src_r4 $1\src_r4[1:0] - end - attribute \src "issuer_ls180.v:170850.3-170851.39" - process $proc$issuer_ls180.v:170850$11484 - assign { } { } - assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next - sync posedge \coresync_clk - update \alu_l_r_alu $0\alu_l_r_alu[0:0] - end - attribute \src "issuer_ls180.v:170852.3-170853.43" - process $proc$issuer_ls180.v:170852$11485 - assign { } { } - assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next - sync posedge \coresync_clk - update \alui_l_r_alui $0\alui_l_r_alui[0:0] - end - attribute \src "issuer_ls180.v:170854.3-170855.29" - process $proc$issuer_ls180.v:170854$11486 - assign { } { } - assign $0\src_r4[1:0] \src_r4$next - sync posedge \coresync_clk - update \src_r4 $0\src_r4[1:0] - end - attribute \src "issuer_ls180.v:170856.3-170857.29" - process $proc$issuer_ls180.v:170856$11487 - assign { } { } - assign $0\src_r3[0:0] \src_r3$next - sync posedge \coresync_clk - update \src_r3 $0\src_r3[0:0] - end - attribute \src "issuer_ls180.v:170858.3-170859.29" - process $proc$issuer_ls180.v:170858$11488 - assign { } { } - assign $0\src_r2[63:0] \src_r2$next - sync posedge \coresync_clk - update \src_r2 $0\src_r2[63:0] - end - attribute \src "issuer_ls180.v:170860.3-170861.29" - process $proc$issuer_ls180.v:170860$11489 - assign { } { } - assign $0\src_r1[63:0] \src_r1$next - sync posedge \coresync_clk - update \src_r1 $0\src_r1[63:0] - end - attribute \src "issuer_ls180.v:170862.3-170863.29" - process $proc$issuer_ls180.v:170862$11490 - assign { } { } - assign $0\src_r0[63:0] \src_r0$next - sync posedge \coresync_clk - update \src_r0 $0\src_r0[63:0] - end - attribute \src "issuer_ls180.v:170864.3-170865.47" - process $proc$issuer_ls180.v:170864$11491 - assign { } { } - assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next - sync posedge \coresync_clk - update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] - end - attribute \src "issuer_ls180.v:170866.3-170867.53" - process $proc$issuer_ls180.v:170866$11492 - assign { } { } - assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next - sync posedge \coresync_clk - update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] - end - attribute \src "issuer_ls180.v:170868.3-170869.43" - process $proc$issuer_ls180.v:170868$11493 - assign { } { } - assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next - sync posedge \coresync_clk - update \data_r1__cr_a $0\data_r1__cr_a[3:0] - end - attribute \src "issuer_ls180.v:170870.3-170871.49" - process $proc$issuer_ls180.v:170870$11494 - assign { } { } - assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next - sync posedge \coresync_clk - update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] - end - attribute \src "issuer_ls180.v:170872.3-170873.37" - process $proc$issuer_ls180.v:170872$11495 - assign { } { } - assign $0\data_r0__o[63:0] \data_r0__o$next - sync posedge \coresync_clk - update \data_r0__o $0\data_r0__o[63:0] - end - attribute \src "issuer_ls180.v:170874.3-170875.43" - process $proc$issuer_ls180.v:170874$11496 - assign { } { } - assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next - sync posedge \coresync_clk - update \data_r0__o_ok $0\data_r0__o_ok[0:0] - end - attribute \src "issuer_ls180.v:170876.3-170877.79" - process $proc$issuer_ls180.v:170876$11497 - assign { } { } - assign $0\alu_shift_rot0_sr_op__insn_type[6:0] \alu_shift_rot0_sr_op__insn_type$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__insn_type $0\alu_shift_rot0_sr_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:170878.3-170879.75" - process $proc$issuer_ls180.v:170878$11498 - assign { } { } - assign $0\alu_shift_rot0_sr_op__fn_unit[11:0] \alu_shift_rot0_sr_op__fn_unit$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__fn_unit $0\alu_shift_rot0_sr_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:170880.3-170881.89" - process $proc$issuer_ls180.v:170880$11499 - assign { } { } - assign $0\alu_shift_rot0_sr_op__imm_data__data[63:0] \alu_shift_rot0_sr_op__imm_data__data$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__imm_data__data $0\alu_shift_rot0_sr_op__imm_data__data[63:0] - end - attribute \src "issuer_ls180.v:170882.3-170883.85" - process $proc$issuer_ls180.v:170882$11500 - assign { } { } - assign $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] \alu_shift_rot0_sr_op__imm_data__ok$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__imm_data__ok $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] - end - attribute \src "issuer_ls180.v:170884.3-170885.73" - process $proc$issuer_ls180.v:170884$11501 - assign { } { } - assign $0\alu_shift_rot0_sr_op__rc__rc[0:0] \alu_shift_rot0_sr_op__rc__rc$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__rc__rc $0\alu_shift_rot0_sr_op__rc__rc[0:0] - end - attribute \src "issuer_ls180.v:170886.3-170887.73" - process $proc$issuer_ls180.v:170886$11502 - assign { } { } - assign $0\alu_shift_rot0_sr_op__rc__ok[0:0] \alu_shift_rot0_sr_op__rc__ok$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__rc__ok $0\alu_shift_rot0_sr_op__rc__ok[0:0] - end - attribute \src "issuer_ls180.v:170888.3-170889.73" - process $proc$issuer_ls180.v:170888$11503 - assign { } { } - assign $0\alu_shift_rot0_sr_op__oe__oe[0:0] \alu_shift_rot0_sr_op__oe__oe$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__oe__oe $0\alu_shift_rot0_sr_op__oe__oe[0:0] - end - attribute \src "issuer_ls180.v:170890.3-170891.73" - process $proc$issuer_ls180.v:170890$11504 - assign { } { } - assign $0\alu_shift_rot0_sr_op__oe__ok[0:0] \alu_shift_rot0_sr_op__oe__ok$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__oe__ok $0\alu_shift_rot0_sr_op__oe__ok[0:0] - end - attribute \src "issuer_ls180.v:170892.3-170893.79" - process $proc$issuer_ls180.v:170892$11505 - assign { } { } - assign $0\alu_shift_rot0_sr_op__write_cr0[0:0] \alu_shift_rot0_sr_op__write_cr0$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__write_cr0 $0\alu_shift_rot0_sr_op__write_cr0[0:0] - end - attribute \src "issuer_ls180.v:170894.3-170895.83" - process $proc$issuer_ls180.v:170894$11506 - assign { } { } - assign $0\alu_shift_rot0_sr_op__input_carry[1:0] \alu_shift_rot0_sr_op__input_carry$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__input_carry $0\alu_shift_rot0_sr_op__input_carry[1:0] - end - attribute \src "issuer_ls180.v:170896.3-170897.85" - process $proc$issuer_ls180.v:170896$11507 - assign { } { } - assign $0\alu_shift_rot0_sr_op__output_carry[0:0] \alu_shift_rot0_sr_op__output_carry$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__output_carry $0\alu_shift_rot0_sr_op__output_carry[0:0] - end - attribute \src "issuer_ls180.v:170898.3-170899.77" - process $proc$issuer_ls180.v:170898$11508 - assign { } { } - assign $0\alu_shift_rot0_sr_op__input_cr[0:0] \alu_shift_rot0_sr_op__input_cr$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__input_cr $0\alu_shift_rot0_sr_op__input_cr[0:0] - end - attribute \src "issuer_ls180.v:170900.3-170901.79" - process $proc$issuer_ls180.v:170900$11509 - assign { } { } - assign $0\alu_shift_rot0_sr_op__output_cr[0:0] \alu_shift_rot0_sr_op__output_cr$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__output_cr $0\alu_shift_rot0_sr_op__output_cr[0:0] - end - attribute \src "issuer_ls180.v:170902.3-170903.77" - process $proc$issuer_ls180.v:170902$11510 - assign { } { } - assign $0\alu_shift_rot0_sr_op__is_32bit[0:0] \alu_shift_rot0_sr_op__is_32bit$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__is_32bit $0\alu_shift_rot0_sr_op__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:170904.3-170905.79" - process $proc$issuer_ls180.v:170904$11511 - assign { } { } - assign $0\alu_shift_rot0_sr_op__is_signed[0:0] \alu_shift_rot0_sr_op__is_signed$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__is_signed $0\alu_shift_rot0_sr_op__is_signed[0:0] - end - attribute \src "issuer_ls180.v:170906.3-170907.69" - process $proc$issuer_ls180.v:170906$11512 - assign { } { } - assign $0\alu_shift_rot0_sr_op__insn[31:0] \alu_shift_rot0_sr_op__insn$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__insn $0\alu_shift_rot0_sr_op__insn[31:0] - end - attribute \src "issuer_ls180.v:170908.3-170909.39" - process $proc$issuer_ls180.v:170908$11513 - assign { } { } - assign $0\req_l_r_req[2:0] \req_l_r_req$next - sync posedge \coresync_clk - update \req_l_r_req $0\req_l_r_req[2:0] - end - attribute \src "issuer_ls180.v:170910.3-170911.39" - process $proc$issuer_ls180.v:170910$11514 - assign { } { } - assign $0\req_l_s_req[2:0] \req_l_s_req$next - sync posedge \coresync_clk - update \req_l_s_req $0\req_l_s_req[2:0] - end - attribute \src "issuer_ls180.v:170912.3-170913.39" - process $proc$issuer_ls180.v:170912$11515 - assign { } { } - assign $0\src_l_r_src[4:0] \src_l_r_src$next - sync posedge \coresync_clk - update \src_l_r_src $0\src_l_r_src[4:0] - end - attribute \src "issuer_ls180.v:170914.3-170915.39" - process $proc$issuer_ls180.v:170914$11516 - assign { } { } - assign $0\src_l_s_src[4:0] \src_l_s_src$next - sync posedge \coresync_clk - update \src_l_s_src $0\src_l_s_src[4:0] - end - attribute \src "issuer_ls180.v:170916.3-170917.39" - process $proc$issuer_ls180.v:170916$11517 - assign { } { } - assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next - sync posedge \coresync_clk - update \opc_l_r_opc $0\opc_l_r_opc[0:0] - end - attribute \src "issuer_ls180.v:170918.3-170919.39" - process $proc$issuer_ls180.v:170918$11518 - assign { } { } - assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next - sync posedge \coresync_clk - update \opc_l_s_opc $0\opc_l_s_opc[0:0] - end - attribute \src "issuer_ls180.v:170920.3-170921.39" - process $proc$issuer_ls180.v:170920$11519 - assign { } { } - assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next - sync posedge \coresync_clk - update \rst_l_r_rst $0\rst_l_r_rst[0:0] - end - attribute \src "issuer_ls180.v:170922.3-170923.39" - process $proc$issuer_ls180.v:170922$11520 - assign { } { } - assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next - sync posedge \coresync_clk - update \rst_l_s_rst $0\rst_l_s_rst[0:0] - end - attribute \src "issuer_ls180.v:170924.3-170925.41" - process $proc$issuer_ls180.v:170924$11521 - assign { } { } - assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next - sync posedge \coresync_clk - update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] - end - attribute \src "issuer_ls180.v:170926.3-170927.41" - process $proc$issuer_ls180.v:170926$11522 - assign { } { } - assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next - sync posedge \coresync_clk - update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] - end - attribute \src "issuer_ls180.v:170928.3-170929.37" - process $proc$issuer_ls180.v:170928$11523 - assign { } { } - assign $0\prev_wr_go[2:0] \prev_wr_go$next - sync posedge \coresync_clk - update \prev_wr_go $0\prev_wr_go[2:0] - end - attribute \src "issuer_ls180.v:170930.3-170931.46" - process $proc$issuer_ls180.v:170930$11524 - assign { } { } - assign $0\alu_done_dly[0:0] \alu_shift_rot0_n_valid_o - sync posedge \coresync_clk - update \alu_done_dly $0\alu_done_dly[0:0] - end - attribute \src "issuer_ls180.v:170932.3-170933.25" - process $proc$issuer_ls180.v:170932$11525 - assign { } { } - assign $0\all_rd_dly[0:0] \$10 - sync posedge \coresync_clk - update \all_rd_dly $0\all_rd_dly[0:0] - end - attribute \src "issuer_ls180.v:171017.3-171026.6" - process $proc$issuer_ls180.v:171017$11526 - assign { } { } - assign { } { } - assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "issuer_ls180.v:171018.5-171018.29" - switch \initial - attribute \src "issuer_ls180.v:171018.9-171018.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch \$54 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_done[0:0] 1'1 - case - assign $1\req_done[0:0] \$46 - end - sync always - update \req_done $0\req_done[0:0] - end - attribute \src "issuer_ls180.v:171027.3-171035.6" - process $proc$issuer_ls180.v:171027$11527 - assign { } { } - assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$11528 $1\rok_l_s_rdok$next[0:0]$11529 - attribute \src "issuer_ls180.v:171028.5-171028.29" - switch \initial - attribute \src "issuer_ls180.v:171028.9-171028.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$11529 1'0 - case - assign $1\rok_l_s_rdok$next[0:0]$11529 \cu_issue_i - end - sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$11528 - end - attribute \src "issuer_ls180.v:171036.3-171044.6" - process $proc$issuer_ls180.v:171036$11530 - assign { } { } - assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$11531 $1\rok_l_r_rdok$next[0:0]$11532 - attribute \src "issuer_ls180.v:171037.5-171037.29" - switch \initial - attribute \src "issuer_ls180.v:171037.9-171037.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$11532 1'1 - case - assign $1\rok_l_r_rdok$next[0:0]$11532 \$64 - end - sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$11531 - end - attribute \src "issuer_ls180.v:171045.3-171053.6" - process $proc$issuer_ls180.v:171045$11533 - assign { } { } - assign { } { } - assign $0\rst_l_s_rst$next[0:0]$11534 $1\rst_l_s_rst$next[0:0]$11535 - attribute \src "issuer_ls180.v:171046.5-171046.29" - switch \initial - attribute \src "issuer_ls180.v:171046.9-171046.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_s_rst$next[0:0]$11535 1'0 - case - assign $1\rst_l_s_rst$next[0:0]$11535 \all_rd - end - sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$11534 - end - attribute \src "issuer_ls180.v:171054.3-171062.6" - process $proc$issuer_ls180.v:171054$11536 - assign { } { } - assign { } { } - assign $0\rst_l_r_rst$next[0:0]$11537 $1\rst_l_r_rst$next[0:0]$11538 - attribute \src "issuer_ls180.v:171055.5-171055.29" - switch \initial - attribute \src "issuer_ls180.v:171055.9-171055.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_r_rst$next[0:0]$11538 1'1 - case - assign $1\rst_l_r_rst$next[0:0]$11538 \rst_r - end - sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$11537 - end - attribute \src "issuer_ls180.v:171063.3-171071.6" - process $proc$issuer_ls180.v:171063$11539 - assign { } { } - assign { } { } - assign $0\opc_l_s_opc$next[0:0]$11540 $1\opc_l_s_opc$next[0:0]$11541 - attribute \src "issuer_ls180.v:171064.5-171064.29" - switch \initial - attribute \src "issuer_ls180.v:171064.9-171064.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_s_opc$next[0:0]$11541 1'0 - case - assign $1\opc_l_s_opc$next[0:0]$11541 \cu_issue_i - end - sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$11540 - end - attribute \src "issuer_ls180.v:171072.3-171080.6" - process $proc$issuer_ls180.v:171072$11542 - assign { } { } - assign { } { } - assign $0\opc_l_r_opc$next[0:0]$11543 $1\opc_l_r_opc$next[0:0]$11544 - attribute \src "issuer_ls180.v:171073.5-171073.29" - switch \initial - attribute \src "issuer_ls180.v:171073.9-171073.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_r_opc$next[0:0]$11544 1'1 - case - assign $1\opc_l_r_opc$next[0:0]$11544 \req_done - end - sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$11543 - end - attribute \src "issuer_ls180.v:171081.3-171089.6" - process $proc$issuer_ls180.v:171081$11545 - assign { } { } - assign { } { } - assign $0\src_l_s_src$next[4:0]$11546 $1\src_l_s_src$next[4:0]$11547 - attribute \src "issuer_ls180.v:171082.5-171082.29" - switch \initial - attribute \src "issuer_ls180.v:171082.9-171082.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_s_src$next[4:0]$11547 5'00000 - case - assign $1\src_l_s_src$next[4:0]$11547 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } - end - sync always - update \src_l_s_src$next $0\src_l_s_src$next[4:0]$11546 - end - attribute \src "issuer_ls180.v:171090.3-171098.6" - process $proc$issuer_ls180.v:171090$11548 - assign { } { } - assign { } { } - assign $0\src_l_r_src$next[4:0]$11549 $1\src_l_r_src$next[4:0]$11550 - attribute \src "issuer_ls180.v:171091.5-171091.29" - switch \initial - attribute \src "issuer_ls180.v:171091.9-171091.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_r_src$next[4:0]$11550 5'11111 - case - assign $1\src_l_r_src$next[4:0]$11550 \reset_r - end - sync always - update \src_l_r_src$next $0\src_l_r_src$next[4:0]$11549 - end - attribute \src "issuer_ls180.v:171099.3-171107.6" - process $proc$issuer_ls180.v:171099$11551 - assign { } { } - assign { } { } - assign $0\req_l_s_req$next[2:0]$11552 $1\req_l_s_req$next[2:0]$11553 - attribute \src "issuer_ls180.v:171100.5-171100.29" - switch \initial - attribute \src "issuer_ls180.v:171100.9-171100.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_s_req$next[2:0]$11553 3'000 - case - assign $1\req_l_s_req$next[2:0]$11553 \$66 - end - sync always - update \req_l_s_req$next $0\req_l_s_req$next[2:0]$11552 - end - attribute \src "issuer_ls180.v:171108.3-171116.6" - process $proc$issuer_ls180.v:171108$11554 - assign { } { } - assign { } { } - assign $0\req_l_r_req$next[2:0]$11555 $1\req_l_r_req$next[2:0]$11556 - attribute \src "issuer_ls180.v:171109.5-171109.29" - switch \initial - attribute \src "issuer_ls180.v:171109.9-171109.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_r_req$next[2:0]$11556 3'111 - case - assign $1\req_l_r_req$next[2:0]$11556 \$68 - end - sync always - update \req_l_r_req$next $0\req_l_r_req$next[2:0]$11555 - end - attribute \src "issuer_ls180.v:171117.3-171153.6" - process $proc$issuer_ls180.v:171117$11557 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11558 $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11574 - assign { } { } - assign { } { } - assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$11561 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$11577 - assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$11562 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$11578 - assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$11563 $1\alu_shift_rot0_sr_op__insn$next[31:0]$11579 - assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$11564 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$11580 - assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$11565 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$11581 - assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$11566 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$11582 - assign { } { } - assign { } { } - assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$11569 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$11585 - assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$11570 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$11586 - assign { } { } - assign { } { } - assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$11573 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$11589 - assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11559 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11590 - assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11560 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11591 - assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11567 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11592 - assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11568 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11593 - assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11571 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11594 - assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11572 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11595 - attribute \src "issuer_ls180.v:171118.5-171118.29" - switch \initial - attribute \src "issuer_ls180.v:171118.9-171118.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$11579 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$11582 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$11581 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$11586 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$11578 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$11585 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$11577 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$11589 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11584 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11583 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11587 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11588 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11576 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11575 $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11574 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$11580 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } - case - assign $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11574 \alu_shift_rot0_sr_op__fn_unit - assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11575 \alu_shift_rot0_sr_op__imm_data__data - assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11576 \alu_shift_rot0_sr_op__imm_data__ok - assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$11577 \alu_shift_rot0_sr_op__input_carry - assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$11578 \alu_shift_rot0_sr_op__input_cr - assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$11579 \alu_shift_rot0_sr_op__insn - assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$11580 \alu_shift_rot0_sr_op__insn_type - assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$11581 \alu_shift_rot0_sr_op__is_32bit - assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$11582 \alu_shift_rot0_sr_op__is_signed - assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11583 \alu_shift_rot0_sr_op__oe__oe - assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11584 \alu_shift_rot0_sr_op__oe__ok - assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$11585 \alu_shift_rot0_sr_op__output_carry - assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$11586 \alu_shift_rot0_sr_op__output_cr - assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11587 \alu_shift_rot0_sr_op__rc__ok - assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11588 \alu_shift_rot0_sr_op__rc__rc - assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$11589 \alu_shift_rot0_sr_op__write_cr0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11590 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11591 1'0 - assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11595 1'0 - assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11594 1'0 - assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11592 1'0 - assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11593 1'0 - case - assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11590 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11575 - assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11591 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11576 - assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11592 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11583 - assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11593 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11584 - assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11594 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11587 - assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11595 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11588 - end - sync always - update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11558 - update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11559 - update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11560 - update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$11561 - update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$11562 - update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$11563 - update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$11564 - update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$11565 - update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$11566 - update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11567 - update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11568 - update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$11569 - update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$11570 - update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11571 - update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11572 - update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$11573 - end - attribute \src "issuer_ls180.v:171154.3-171175.6" - process $proc$issuer_ls180.v:171154$11596 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r0__o$next[63:0]$11597 $2\data_r0__o$next[63:0]$11601 - assign { } { } - assign $0\data_r0__o_ok$next[0:0]$11598 $3\data_r0__o_ok$next[0:0]$11603 - attribute \src "issuer_ls180.v:171155.5-171155.29" - switch \initial - attribute \src "issuer_ls180.v:171155.9-171155.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$11600 $1\data_r0__o$next[63:0]$11599 } { \o_ok \alu_shift_rot0_o } - case - assign $1\data_r0__o$next[63:0]$11599 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$11600 \data_r0__o_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$11602 $2\data_r0__o$next[63:0]$11601 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r0__o$next[63:0]$11601 $1\data_r0__o$next[63:0]$11599 - assign $2\data_r0__o_ok$next[0:0]$11602 $1\data_r0__o_ok$next[0:0]$11600 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r0__o_ok$next[0:0]$11603 1'0 - case - assign $3\data_r0__o_ok$next[0:0]$11603 $2\data_r0__o_ok$next[0:0]$11602 - end - sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$11597 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$11598 - end - attribute \src "issuer_ls180.v:171176.3-171197.6" - process $proc$issuer_ls180.v:171176$11604 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r1__cr_a$next[3:0]$11605 $2\data_r1__cr_a$next[3:0]$11609 - assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$11606 $3\data_r1__cr_a_ok$next[0:0]$11611 - attribute \src "issuer_ls180.v:171177.5-171177.29" - switch \initial - attribute \src "issuer_ls180.v:171177.9-171177.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$11608 $1\data_r1__cr_a$next[3:0]$11607 } { \cr_a_ok \alu_shift_rot0_cr_a } - case - assign $1\data_r1__cr_a$next[3:0]$11607 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$11608 \data_r1__cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$11610 $2\data_r1__cr_a$next[3:0]$11609 } 5'00000 - case - assign $2\data_r1__cr_a$next[3:0]$11609 $1\data_r1__cr_a$next[3:0]$11607 - assign $2\data_r1__cr_a_ok$next[0:0]$11610 $1\data_r1__cr_a_ok$next[0:0]$11608 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$11611 1'0 - case - assign $3\data_r1__cr_a_ok$next[0:0]$11611 $2\data_r1__cr_a_ok$next[0:0]$11610 - end - sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$11605 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$11606 - end - attribute \src "issuer_ls180.v:171198.3-171219.6" - process $proc$issuer_ls180.v:171198$11612 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r2__xer_ca$next[1:0]$11613 $2\data_r2__xer_ca$next[1:0]$11617 - assign { } { } - assign $0\data_r2__xer_ca_ok$next[0:0]$11614 $3\data_r2__xer_ca_ok$next[0:0]$11619 - attribute \src "issuer_ls180.v:171199.5-171199.29" - switch \initial - attribute \src "issuer_ls180.v:171199.9-171199.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r2__xer_ca_ok$next[0:0]$11616 $1\data_r2__xer_ca$next[1:0]$11615 } { \xer_ca_ok \alu_shift_rot0_xer_ca } - case - assign $1\data_r2__xer_ca$next[1:0]$11615 \data_r2__xer_ca - assign $1\data_r2__xer_ca_ok$next[0:0]$11616 \data_r2__xer_ca_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r2__xer_ca_ok$next[0:0]$11618 $2\data_r2__xer_ca$next[1:0]$11617 } 3'000 - case - assign $2\data_r2__xer_ca$next[1:0]$11617 $1\data_r2__xer_ca$next[1:0]$11615 - assign $2\data_r2__xer_ca_ok$next[0:0]$11618 $1\data_r2__xer_ca_ok$next[0:0]$11616 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r2__xer_ca_ok$next[0:0]$11619 1'0 - case - assign $3\data_r2__xer_ca_ok$next[0:0]$11619 $2\data_r2__xer_ca_ok$next[0:0]$11618 - end - sync always - update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$11613 - update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$11614 - end - attribute \src "issuer_ls180.v:171220.3-171229.6" - process $proc$issuer_ls180.v:171220$11620 - assign { } { } - assign { } { } - assign $0\src_r0$next[63:0]$11621 $1\src_r0$next[63:0]$11622 - attribute \src "issuer_ls180.v:171221.5-171221.29" - switch \initial - attribute \src "issuer_ls180.v:171221.9-171221.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r0$next[63:0]$11622 \src1_i - case - assign $1\src_r0$next[63:0]$11622 \src_r0 - end - sync always - update \src_r0$next $0\src_r0$next[63:0]$11621 - end - attribute \src "issuer_ls180.v:171230.3-171239.6" - process $proc$issuer_ls180.v:171230$11623 - assign { } { } - assign { } { } - assign $0\src_r1$next[63:0]$11624 $1\src_r1$next[63:0]$11625 - attribute \src "issuer_ls180.v:171231.5-171231.29" - switch \initial - attribute \src "issuer_ls180.v:171231.9-171231.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_sel - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r1$next[63:0]$11625 \src_or_imm - case - assign $1\src_r1$next[63:0]$11625 \src_r1 - end - sync always - update \src_r1$next $0\src_r1$next[63:0]$11624 - end - attribute \src "issuer_ls180.v:171240.3-171249.6" - process $proc$issuer_ls180.v:171240$11626 - assign { } { } - assign { } { } - assign $0\src_r2$next[63:0]$11627 $1\src_r2$next[63:0]$11628 - attribute \src "issuer_ls180.v:171241.5-171241.29" - switch \initial - attribute \src "issuer_ls180.v:171241.9-171241.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r2$next[63:0]$11628 \src3_i - case - assign $1\src_r2$next[63:0]$11628 \src_r2 - end - sync always - update \src_r2$next $0\src_r2$next[63:0]$11627 - end - attribute \src "issuer_ls180.v:171250.3-171259.6" - process $proc$issuer_ls180.v:171250$11629 - assign { } { } - assign { } { } - assign $0\src_r3$next[0:0]$11630 $1\src_r3$next[0:0]$11631 - attribute \src "issuer_ls180.v:171251.5-171251.29" - switch \initial - attribute \src "issuer_ls180.v:171251.9-171251.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [3] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r3$next[0:0]$11631 \src4_i - case - assign $1\src_r3$next[0:0]$11631 \src_r3 - end - sync always - update \src_r3$next $0\src_r3$next[0:0]$11630 - end - attribute \src "issuer_ls180.v:171260.3-171269.6" - process $proc$issuer_ls180.v:171260$11632 - assign { } { } - assign { } { } - assign $0\src_r4$next[1:0]$11633 $1\src_r4$next[1:0]$11634 - attribute \src "issuer_ls180.v:171261.5-171261.29" - switch \initial - attribute \src "issuer_ls180.v:171261.9-171261.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [4] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r4$next[1:0]$11634 \src5_i - case - assign $1\src_r4$next[1:0]$11634 \src_r4 - end - sync always - update \src_r4$next $0\src_r4$next[1:0]$11633 - end - attribute \src "issuer_ls180.v:171270.3-171278.6" - process $proc$issuer_ls180.v:171270$11635 - assign { } { } - assign { } { } - assign $0\alui_l_r_alui$next[0:0]$11636 $1\alui_l_r_alui$next[0:0]$11637 - attribute \src "issuer_ls180.v:171271.5-171271.29" - switch \initial - attribute \src "issuer_ls180.v:171271.9-171271.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alui_l_r_alui$next[0:0]$11637 1'1 - case - assign $1\alui_l_r_alui$next[0:0]$11637 \$90 - end - sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$11636 - end - attribute \src "issuer_ls180.v:171279.3-171287.6" - process $proc$issuer_ls180.v:171279$11638 - assign { } { } - assign { } { } - assign $0\alu_l_r_alu$next[0:0]$11639 $1\alu_l_r_alu$next[0:0]$11640 - attribute \src "issuer_ls180.v:171280.5-171280.29" - switch \initial - attribute \src "issuer_ls180.v:171280.9-171280.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alu_l_r_alu$next[0:0]$11640 1'1 - case - assign $1\alu_l_r_alu$next[0:0]$11640 \$92 - end - sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$11639 - end - attribute \src "issuer_ls180.v:171288.3-171297.6" - process $proc$issuer_ls180.v:171288$11641 - assign { } { } - assign { } { } - assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "issuer_ls180.v:171289.5-171289.29" - switch \initial - attribute \src "issuer_ls180.v:171289.9-171289.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$114 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest1_o[63:0] \data_r0__o - case - assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest1_o $0\dest1_o[63:0] - end - attribute \src "issuer_ls180.v:171298.3-171307.6" - process $proc$issuer_ls180.v:171298$11642 - assign { } { } - assign { } { } - assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "issuer_ls180.v:171299.5-171299.29" - switch \initial - attribute \src "issuer_ls180.v:171299.9-171299.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$116 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest2_o[3:0] \data_r1__cr_a - case - assign $1\dest2_o[3:0] 4'0000 - end - sync always - update \dest2_o $0\dest2_o[3:0] - end - attribute \src "issuer_ls180.v:171308.3-171317.6" - process $proc$issuer_ls180.v:171308$11643 - assign { } { } - assign { } { } - assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "issuer_ls180.v:171309.5-171309.29" - switch \initial - attribute \src "issuer_ls180.v:171309.9-171309.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$118 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest3_o[1:0] \data_r2__xer_ca - case - assign $1\dest3_o[1:0] 2'00 - end - sync always - update \dest3_o $0\dest3_o[1:0] - end - attribute \src "issuer_ls180.v:171318.3-171326.6" - process $proc$issuer_ls180.v:171318$11644 - assign { } { } - assign { } { } - assign $0\prev_wr_go$next[2:0]$11645 $1\prev_wr_go$next[2:0]$11646 - attribute \src "issuer_ls180.v:171319.5-171319.29" - switch \initial - attribute \src "issuer_ls180.v:171319.9-171319.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\prev_wr_go$next[2:0]$11646 3'000 - case - assign $1\prev_wr_go$next[2:0]$11646 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[2:0]$11645 - end - connect \$100 $not$issuer_ls180.v:170791$11425_Y - connect \$102 $and$issuer_ls180.v:170792$11426_Y - connect \$104 $and$issuer_ls180.v:170793$11427_Y - connect \$106 $and$issuer_ls180.v:170794$11428_Y - connect \$108 $and$issuer_ls180.v:170795$11429_Y - connect \$10 $and$issuer_ls180.v:170796$11430_Y - connect \$110 $and$issuer_ls180.v:170797$11431_Y - connect \$112 $and$issuer_ls180.v:170798$11432_Y - connect \$114 $and$issuer_ls180.v:170799$11433_Y - connect \$116 $and$issuer_ls180.v:170800$11434_Y - connect \$118 $and$issuer_ls180.v:170801$11435_Y - connect \$12 $not$issuer_ls180.v:170802$11436_Y - connect \$14 $and$issuer_ls180.v:170803$11437_Y - connect \$16 $not$issuer_ls180.v:170804$11438_Y - connect \$18 $and$issuer_ls180.v:170805$11439_Y - connect \$20 $and$issuer_ls180.v:170806$11440_Y - connect \$24 $not$issuer_ls180.v:170807$11441_Y - connect \$26 $and$issuer_ls180.v:170808$11442_Y - connect \$23 $reduce_or$issuer_ls180.v:170809$11443_Y - connect \$22 $not$issuer_ls180.v:170810$11444_Y - connect \$2 $and$issuer_ls180.v:170811$11445_Y - connect \$30 $and$issuer_ls180.v:170812$11446_Y - connect \$32 $reduce_or$issuer_ls180.v:170813$11447_Y - connect \$34 $reduce_or$issuer_ls180.v:170814$11448_Y - connect \$36 $or$issuer_ls180.v:170815$11449_Y - connect \$38 $not$issuer_ls180.v:170816$11450_Y - connect \$40 $and$issuer_ls180.v:170817$11451_Y - connect \$42 $and$issuer_ls180.v:170818$11452_Y - connect \$44 $eq$issuer_ls180.v:170819$11453_Y - connect \$46 $and$issuer_ls180.v:170820$11454_Y - connect \$48 $eq$issuer_ls180.v:170821$11455_Y - connect \$50 $and$issuer_ls180.v:170822$11456_Y - connect \$52 $and$issuer_ls180.v:170823$11457_Y - connect \$54 $and$issuer_ls180.v:170824$11458_Y - connect \$56 $or$issuer_ls180.v:170825$11459_Y - connect \$58 $or$issuer_ls180.v:170826$11460_Y - connect \$5 $not$issuer_ls180.v:170827$11461_Y - connect \$60 $or$issuer_ls180.v:170828$11462_Y - connect \$62 $or$issuer_ls180.v:170829$11463_Y - connect \$64 $and$issuer_ls180.v:170830$11464_Y - connect \$66 $and$issuer_ls180.v:170831$11465_Y - connect \$68 $or$issuer_ls180.v:170832$11466_Y - connect \$70 $and$issuer_ls180.v:170833$11467_Y - connect \$72 $and$issuer_ls180.v:170834$11468_Y - connect \$74 $and$issuer_ls180.v:170835$11469_Y - connect \$76 $ternary$issuer_ls180.v:170836$11470_Y - connect \$78 $ternary$issuer_ls180.v:170837$11471_Y - connect \$7 $or$issuer_ls180.v:170838$11472_Y - connect \$80 $ternary$issuer_ls180.v:170839$11473_Y - connect \$82 $ternary$issuer_ls180.v:170840$11474_Y - connect \$84 $ternary$issuer_ls180.v:170841$11475_Y - connect \$86 $ternary$issuer_ls180.v:170842$11476_Y - connect \$88 $ternary$issuer_ls180.v:170843$11477_Y - connect \$4 $reduce_and$issuer_ls180.v:170844$11478_Y - connect \$90 $and$issuer_ls180.v:170845$11479_Y - connect \$92 $and$issuer_ls180.v:170846$11480_Y - connect \$94 $and$issuer_ls180.v:170847$11481_Y - connect \$96 $not$issuer_ls180.v:170848$11482_Y - connect \$98 $and$issuer_ls180.v:170849$11483_Y - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 - connect \cu_wr__rel_o \$112 - connect \cu_rd__rel_o \$102 - connect \cu_busy_o \opc_l_q_opc - connect \alu_l_s_alu \all_rd_pulse - connect \alu_shift_rot0_n_ready_i \alu_l_q_alu - connect \alui_l_s_alui \all_rd_pulse - connect \alu_shift_rot0_p_valid_i \alui_l_q_alui - connect \alu_shift_rot0_xer_ca$1 \$88 - connect \alu_shift_rot0_xer_so \$86 - connect \alu_shift_rot0_rc \$84 - connect \alu_shift_rot0_rb \$82 - connect \alu_shift_rot0_ra \$80 - connect \src_or_imm \$78 - connect \src_sel \$76 - connect \cu_wrmask_o { \$74 \$72 \$70 } - connect \reset_r \$62 - connect \reset_w \$60 - connect \rst_r \$58 - connect \reset \$56 - connect \wr_any \$36 - connect \cu_done_o \$30 - connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } - connect \alu_pulse \alu_done_rise - connect \alu_done_rise \$18 - connect \alu_done_dly$next \alu_done - connect \alu_done \alu_shift_rot0_n_valid_o - connect \all_rd_pulse \all_rd_rise - connect \all_rd_rise \$14 - connect \all_rd_dly$next \all_rd - connect \all_rd \$10 -end -attribute \src "issuer_ls180.v:171363.1-171540.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.spr" -attribute \generator "nMigen" -module \spr - attribute \src "issuer_ls180.v:171512.3-171515.6" - wire width 7 $0$memwr$\memory$issuer_ls180.v:171514$11800_ADDR[6:0]$11803 - attribute \src "issuer_ls180.v:171512.3-171515.6" - wire width 64 $0$memwr$\memory$issuer_ls180.v:171514$11800_DATA[63:0]$11804 - attribute \src "issuer_ls180.v:171512.3-171515.6" - wire width 64 $0$memwr$\memory$issuer_ls180.v:171514$11800_EN[63:0]$11805 - attribute \src "issuer_ls180.v:171512.3-171515.6" - wire width 7 $0\_0_[6:0] - attribute \src "issuer_ls180.v:171364.7-171364.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:171517.3-171525.6" - wire $0\ren_delay$next[0:0]$11808 - attribute \src "issuer_ls180.v:171396.3-171397.35" - wire $0\ren_delay[0:0] - attribute \src "issuer_ls180.v:171526.3-171535.6" - wire width 64 $0\spr1__data_o[63:0] - attribute \src "issuer_ls180.v:171517.3-171525.6" - wire $1\ren_delay$next[0:0]$11809 - attribute \src "issuer_ls180.v:171380.7-171380.23" - wire $1\ren_delay[0:0] - attribute \src "issuer_ls180.v:171526.3-171535.6" - wire width 64 $1\spr1__data_o[63:0] - attribute \src "issuer_ls180.v:171516.26-171516.32" - wire width 64 $memrd$\memory$issuer_ls180.v:171516$11806_DATA - attribute \src "issuer_ls180.v:0.0-0.0" - wire width 7 $memwr$\memory$issuer_ls180.v:171514$11800_ADDR - attribute \src "issuer_ls180.v:0.0-0.0" - wire width 64 $memwr$\memory$issuer_ls180.v:171514$11800_DATA - attribute \src "issuer_ls180.v:0.0-0.0" - wire width 64 $memwr$\memory$issuer_ls180.v:171514$11800_EN - attribute \src "issuer_ls180.v:171511.13-171511.16" - wire width 7 \_0_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 8 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 7 \coresync_rst - attribute \src "issuer_ls180.v:171364.7-171364.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 7 \memory_r_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 7 \memory_w_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 64 \memory_w_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire \memory_w_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 7 input 2 \spr1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 7 input 5 \spr1__addr$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 4 \spr1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 1 \spr1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 3 \spr1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \spr1__wen - attribute \src "issuer_ls180.v:171398.14-171398.20" - memory width 64 size 110 \memory - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11811 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11811 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 0 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11812 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11812 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 1 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11813 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11813 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 2 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11814 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11814 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 3 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11815 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11815 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 4 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11816 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11816 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 5 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11817 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11817 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 6 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11818 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11818 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 7 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11819 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11819 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 8 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11820 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11820 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 9 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11821 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11821 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 10 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11822 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11822 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 11 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11823 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11823 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 12 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11824 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11824 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 13 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11825 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11825 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 14 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11826 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11826 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 15 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11827 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11827 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 16 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11828 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11828 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 17 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11829 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11829 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 18 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11830 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11830 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 19 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11831 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11831 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 20 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11832 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11832 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 21 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11833 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11833 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 22 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11834 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11834 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 23 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11835 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11835 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 24 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11836 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11836 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 25 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11837 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11837 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 26 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11838 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11838 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 27 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11839 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11839 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 28 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11840 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11840 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 29 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11841 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11841 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 30 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11842 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11842 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 31 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11843 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11843 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 32 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11844 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11844 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 33 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11845 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11845 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 34 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11846 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11846 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 35 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11847 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11847 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 36 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11848 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11848 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 37 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11849 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11849 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 38 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11850 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11850 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 39 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11851 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11851 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 40 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11852 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11852 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 41 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11853 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11853 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 42 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11854 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11854 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 43 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11855 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11855 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 44 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11856 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11856 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 45 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11857 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11857 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 46 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11858 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11858 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 47 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11859 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11859 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 48 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11860 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11860 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 49 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11861 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11861 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 50 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11862 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11862 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 51 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11863 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11863 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 52 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11864 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11864 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 53 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11865 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11865 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 54 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11866 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11866 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 55 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11867 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11867 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 56 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11868 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11868 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 57 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11869 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11869 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 58 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11870 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11870 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 59 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11871 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11871 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 60 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11872 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11872 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 61 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11873 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11873 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 62 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11874 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11874 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 63 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11875 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11875 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 64 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11876 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11876 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 65 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11877 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11877 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 66 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11878 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11878 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 67 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11879 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11879 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 68 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11880 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11880 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 69 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11881 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11881 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 70 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11882 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11882 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 71 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11883 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11883 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 72 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11884 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11884 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 73 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11885 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11885 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 74 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11886 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11886 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 75 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11887 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11887 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 76 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11888 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11888 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 77 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11889 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11889 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 78 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11890 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11890 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 79 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11891 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11891 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 80 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11892 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11892 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 81 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11893 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11893 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 82 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11894 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11894 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 83 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11895 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11895 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 84 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11896 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11896 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 85 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11897 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11897 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 86 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11898 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11898 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 87 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11899 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11899 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 88 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11900 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11900 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 89 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11901 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11901 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 90 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11902 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11902 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 91 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11903 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11903 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 92 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11904 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11904 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 93 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11905 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11905 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 94 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11906 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11906 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 95 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11907 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11907 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 96 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11908 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11908 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 97 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11909 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11909 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 98 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11910 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11910 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 99 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11911 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11911 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 100 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11912 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11912 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 101 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11913 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11913 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 102 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11914 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11914 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 103 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11915 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11915 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 104 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11916 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11916 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 105 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11917 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11917 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 106 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11918 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11918 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 107 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11919 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11919 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 108 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $meminit $meminit$\memory$issuer_ls180.v:0$11920 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 11920 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 109 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "issuer_ls180.v:171516.26-171516.32" - cell $memrd $memrd$\memory$issuer_ls180.v:171516$11806 - parameter \ABITS 7 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_0_ - connect \CLK 1'x - connect \DATA $memrd$\memory$issuer_ls180.v:171516$11806_DATA - connect \EN 1'x - end - attribute \src "issuer_ls180.v:0.0-0.0" - cell $memwr $memwr$\memory$issuer_ls180.v:0$11921 - parameter \ABITS 7 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \PRIORITY 11921 - parameter \WIDTH 64 - connect \ADDR $memwr$\memory$issuer_ls180.v:171514$11800_ADDR - connect \CLK 1'x - connect \DATA $memwr$\memory$issuer_ls180.v:171514$11800_DATA - connect \EN $memwr$\memory$issuer_ls180.v:171514$11800_EN - end - attribute \src "issuer_ls180.v:0.0-0.0" - process $proc$issuer_ls180.v:0$11924 - sync always - sync init - end - attribute \src "issuer_ls180.v:171364.7-171364.20" - process $proc$issuer_ls180.v:171364$11922 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:171380.7-171380.23" - process $proc$issuer_ls180.v:171380$11923 - assign { } { } - assign $1\ren_delay[0:0] 1'0 - sync always - sync init - update \ren_delay $1\ren_delay[0:0] - end - attribute \src "issuer_ls180.v:171396.3-171397.35" - process $proc$issuer_ls180.v:171396$11801 - assign { } { } - assign $0\ren_delay[0:0] \ren_delay$next - sync posedge \coresync_clk - update \ren_delay $0\ren_delay[0:0] - end - attribute \src "issuer_ls180.v:171512.3-171515.6" - process $proc$issuer_ls180.v:171512$11802 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\memory$issuer_ls180.v:171514$11800_ADDR[6:0]$11803 7'xxxxxxx - assign $0$memwr$\memory$issuer_ls180.v:171514$11800_DATA[63:0]$11804 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$issuer_ls180.v:171514$11800_EN[63:0]$11805 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\_0_[6:0] \spr1__addr - attribute \src "issuer_ls180.v:171514.5-171514.59" - switch \spr1__wen - attribute \src "issuer_ls180.v:171514.9-171514.18" - case 1'1 - assign $0$memwr$\memory$issuer_ls180.v:171514$11800_ADDR[6:0]$11803 \spr1__addr$1 - assign $0$memwr$\memory$issuer_ls180.v:171514$11800_DATA[63:0]$11804 \spr1__data_i - assign $0$memwr$\memory$issuer_ls180.v:171514$11800_EN[63:0]$11805 64'1111111111111111111111111111111111111111111111111111111111111111 - case - end - sync posedge \coresync_clk - update \_0_ $0\_0_[6:0] - update $memwr$\memory$issuer_ls180.v:171514$11800_ADDR $0$memwr$\memory$issuer_ls180.v:171514$11800_ADDR[6:0]$11803 - update $memwr$\memory$issuer_ls180.v:171514$11800_DATA $0$memwr$\memory$issuer_ls180.v:171514$11800_DATA[63:0]$11804 - update $memwr$\memory$issuer_ls180.v:171514$11800_EN $0$memwr$\memory$issuer_ls180.v:171514$11800_EN[63:0]$11805 - end - attribute \src "issuer_ls180.v:171517.3-171525.6" - process $proc$issuer_ls180.v:171517$11807 - assign { } { } - assign { } { } - assign $0\ren_delay$next[0:0]$11808 $1\ren_delay$next[0:0]$11809 - attribute \src "issuer_ls180.v:171518.5-171518.29" - switch \initial - attribute \src "issuer_ls180.v:171518.9-171518.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$next[0:0]$11809 1'0 - case - assign $1\ren_delay$next[0:0]$11809 \spr1__ren - end - sync always - update \ren_delay$next $0\ren_delay$next[0:0]$11808 - end - attribute \src "issuer_ls180.v:171526.3-171535.6" - process $proc$issuer_ls180.v:171526$11810 - assign { } { } - assign { } { } - assign $0\spr1__data_o[63:0] $1\spr1__data_o[63:0] - attribute \src "issuer_ls180.v:171527.5-171527.29" - switch \initial - attribute \src "issuer_ls180.v:171527.9-171527.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\spr1__data_o[63:0] \memory_r_data - case - assign $1\spr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \spr1__data_o $0\spr1__data_o[63:0] - end - connect \memory_r_data $memrd$\memory$issuer_ls180.v:171516$11806_DATA - connect \memory_w_data \spr1__data_i - connect \memory_w_en \spr1__wen - connect \memory_w_addr \spr1__addr$1 - connect \memory_r_addr \spr1__addr -end -attribute \src "issuer_ls180.v:171544.1-172791.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0" -attribute \generator "nMigen" -module \spr0 - attribute \src "issuer_ls180.v:172288.3-172289.25" - wire $0\all_rd_dly[0:0] - attribute \src "issuer_ls180.v:172286.3-172287.40" - wire $0\alu_done_dly[0:0] - attribute \src "issuer_ls180.v:172682.3-172690.6" - wire $0\alu_l_r_alu$next[0:0]$12138 - attribute \src "issuer_ls180.v:172216.3-172217.39" - wire $0\alu_l_r_alu[0:0] - attribute \src "issuer_ls180.v:172468.3-172480.6" - wire width 12 $0\alu_spr0_spr_op__fn_unit$next[11:0]$12060 - attribute \src "issuer_ls180.v:172258.3-172259.65" - wire width 12 $0\alu_spr0_spr_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:172468.3-172480.6" - wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$12061 - attribute \src "issuer_ls180.v:172260.3-172261.59" - wire width 32 $0\alu_spr0_spr_op__insn[31:0] - attribute \src "issuer_ls180.v:172468.3-172480.6" - wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$12062 - attribute \src "issuer_ls180.v:172256.3-172257.69" - wire width 7 $0\alu_spr0_spr_op__insn_type[6:0] - attribute \src "issuer_ls180.v:172468.3-172480.6" - wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$12063 - attribute \src "issuer_ls180.v:172262.3-172263.67" - wire $0\alu_spr0_spr_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:172673.3-172681.6" - wire $0\alui_l_r_alui$next[0:0]$12135 - attribute \src "issuer_ls180.v:172218.3-172219.43" - wire $0\alui_l_r_alui[0:0] - attribute \src "issuer_ls180.v:172481.3-172502.6" - wire width 64 $0\data_r0__o$next[63:0]$12069 - attribute \src "issuer_ls180.v:172252.3-172253.37" - wire width 64 $0\data_r0__o[63:0] - attribute \src "issuer_ls180.v:172481.3-172502.6" - wire $0\data_r0__o_ok$next[0:0]$12070 - attribute \src "issuer_ls180.v:172254.3-172255.43" - wire $0\data_r0__o_ok[0:0] - attribute \src "issuer_ls180.v:172503.3-172524.6" - wire width 64 $0\data_r1__spr1$next[63:0]$12077 - attribute \src "issuer_ls180.v:172248.3-172249.43" - wire width 64 $0\data_r1__spr1[63:0] - attribute \src "issuer_ls180.v:172503.3-172524.6" - wire $0\data_r1__spr1_ok$next[0:0]$12078 - attribute \src "issuer_ls180.v:172250.3-172251.49" - wire $0\data_r1__spr1_ok[0:0] - attribute \src "issuer_ls180.v:172525.3-172546.6" - wire width 64 $0\data_r2__fast1$next[63:0]$12085 - attribute \src "issuer_ls180.v:172244.3-172245.45" - wire width 64 $0\data_r2__fast1[63:0] - attribute \src "issuer_ls180.v:172525.3-172546.6" - wire $0\data_r2__fast1_ok$next[0:0]$12086 - attribute \src "issuer_ls180.v:172246.3-172247.51" - wire $0\data_r2__fast1_ok[0:0] - attribute \src "issuer_ls180.v:172547.3-172568.6" - wire $0\data_r3__xer_so$next[0:0]$12093 - attribute \src "issuer_ls180.v:172240.3-172241.47" - wire $0\data_r3__xer_so[0:0] - attribute \src "issuer_ls180.v:172547.3-172568.6" - wire $0\data_r3__xer_so_ok$next[0:0]$12094 - attribute \src "issuer_ls180.v:172242.3-172243.53" - wire $0\data_r3__xer_so_ok[0:0] - attribute \src "issuer_ls180.v:172569.3-172590.6" - wire width 2 $0\data_r4__xer_ov$next[1:0]$12101 - attribute \src "issuer_ls180.v:172236.3-172237.47" - wire width 2 $0\data_r4__xer_ov[1:0] - attribute \src "issuer_ls180.v:172569.3-172590.6" - wire $0\data_r4__xer_ov_ok$next[0:0]$12102 - attribute \src "issuer_ls180.v:172238.3-172239.53" - wire $0\data_r4__xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:172591.3-172612.6" - wire width 2 $0\data_r5__xer_ca$next[1:0]$12109 - attribute \src "issuer_ls180.v:172232.3-172233.47" - wire width 2 $0\data_r5__xer_ca[1:0] - attribute \src "issuer_ls180.v:172591.3-172612.6" - wire $0\data_r5__xer_ca_ok$next[0:0]$12110 - attribute \src "issuer_ls180.v:172234.3-172235.53" - wire $0\data_r5__xer_ca_ok[0:0] - attribute \src "issuer_ls180.v:172691.3-172700.6" - wire width 64 $0\dest1_o[63:0] - attribute \src "issuer_ls180.v:172701.3-172710.6" - wire width 64 $0\dest2_o[63:0] - attribute \src "issuer_ls180.v:172711.3-172720.6" - wire width 64 $0\dest3_o[63:0] - attribute \src "issuer_ls180.v:172721.3-172730.6" - wire $0\dest4_o[0:0] - attribute \src "issuer_ls180.v:172731.3-172740.6" - wire width 2 $0\dest5_o[1:0] - attribute \src "issuer_ls180.v:172741.3-172750.6" - wire width 2 $0\dest6_o[1:0] - attribute \src "issuer_ls180.v:171545.7-171545.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:172423.3-172431.6" - wire $0\opc_l_r_opc$next[0:0]$12045 - attribute \src "issuer_ls180.v:172272.3-172273.39" - wire $0\opc_l_r_opc[0:0] - attribute \src "issuer_ls180.v:172414.3-172422.6" - wire $0\opc_l_s_opc$next[0:0]$12042 - attribute \src "issuer_ls180.v:172274.3-172275.39" - wire $0\opc_l_s_opc[0:0] - attribute \src "issuer_ls180.v:172751.3-172759.6" - wire width 6 $0\prev_wr_go$next[5:0]$12147 - attribute \src "issuer_ls180.v:172284.3-172285.37" - wire width 6 $0\prev_wr_go[5:0] - attribute \src "issuer_ls180.v:172368.3-172377.6" - wire $0\req_done[0:0] - attribute \src "issuer_ls180.v:172459.3-172467.6" - wire width 6 $0\req_l_r_req$next[5:0]$12057 - attribute \src "issuer_ls180.v:172264.3-172265.39" - wire width 6 $0\req_l_r_req[5:0] - attribute \src "issuer_ls180.v:172450.3-172458.6" - wire width 6 $0\req_l_s_req$next[5:0]$12054 - attribute \src "issuer_ls180.v:172266.3-172267.39" - wire width 6 $0\req_l_s_req[5:0] - attribute \src "issuer_ls180.v:172387.3-172395.6" - wire $0\rok_l_r_rdok$next[0:0]$12033 - attribute \src "issuer_ls180.v:172280.3-172281.41" - wire $0\rok_l_r_rdok[0:0] - attribute \src "issuer_ls180.v:172378.3-172386.6" - wire $0\rok_l_s_rdok$next[0:0]$12030 - attribute \src "issuer_ls180.v:172282.3-172283.41" - wire $0\rok_l_s_rdok[0:0] - attribute \src "issuer_ls180.v:172405.3-172413.6" - wire $0\rst_l_r_rst$next[0:0]$12039 - attribute \src "issuer_ls180.v:172276.3-172277.39" - wire $0\rst_l_r_rst[0:0] - attribute \src "issuer_ls180.v:172396.3-172404.6" - wire $0\rst_l_s_rst$next[0:0]$12036 - attribute \src "issuer_ls180.v:172278.3-172279.39" - wire $0\rst_l_s_rst[0:0] - attribute \src "issuer_ls180.v:172441.3-172449.6" - wire width 6 $0\src_l_r_src$next[5:0]$12051 - attribute \src "issuer_ls180.v:172268.3-172269.39" - wire width 6 $0\src_l_r_src[5:0] - attribute \src "issuer_ls180.v:172432.3-172440.6" - wire width 6 $0\src_l_s_src$next[5:0]$12048 - attribute \src "issuer_ls180.v:172270.3-172271.39" - wire width 6 $0\src_l_s_src[5:0] - attribute \src "issuer_ls180.v:172613.3-172622.6" - wire width 64 $0\src_r0$next[63:0]$12117 - attribute \src "issuer_ls180.v:172230.3-172231.29" - wire width 64 $0\src_r0[63:0] - attribute \src "issuer_ls180.v:172623.3-172632.6" - wire width 64 $0\src_r1$next[63:0]$12120 - attribute \src "issuer_ls180.v:172228.3-172229.29" - wire width 64 $0\src_r1[63:0] - attribute \src "issuer_ls180.v:172633.3-172642.6" - wire width 64 $0\src_r2$next[63:0]$12123 - attribute \src "issuer_ls180.v:172226.3-172227.29" - wire width 64 $0\src_r2[63:0] - attribute \src "issuer_ls180.v:172643.3-172652.6" - wire $0\src_r3$next[0:0]$12126 - attribute \src "issuer_ls180.v:172224.3-172225.29" - wire $0\src_r3[0:0] - attribute \src "issuer_ls180.v:172653.3-172662.6" - wire width 2 $0\src_r4$next[1:0]$12129 - attribute \src "issuer_ls180.v:172222.3-172223.29" - wire width 2 $0\src_r4[1:0] - attribute \src "issuer_ls180.v:172663.3-172672.6" - wire width 2 $0\src_r5$next[1:0]$12132 - attribute \src "issuer_ls180.v:172220.3-172221.29" - wire width 2 $0\src_r5[1:0] - attribute \src "issuer_ls180.v:171681.7-171681.24" - wire $1\all_rd_dly[0:0] - attribute \src "issuer_ls180.v:171691.7-171691.26" - wire $1\alu_done_dly[0:0] - attribute \src "issuer_ls180.v:172682.3-172690.6" - wire $1\alu_l_r_alu$next[0:0]$12139 - attribute \src "issuer_ls180.v:171699.7-171699.25" - wire $1\alu_l_r_alu[0:0] - attribute \src "issuer_ls180.v:172468.3-172480.6" - wire width 12 $1\alu_spr0_spr_op__fn_unit$next[11:0]$12064 - attribute \src "issuer_ls180.v:171742.14-171742.48" - wire width 12 $1\alu_spr0_spr_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:172468.3-172480.6" - wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$12065 - attribute \src "issuer_ls180.v:171746.14-171746.43" - wire width 32 $1\alu_spr0_spr_op__insn[31:0] - attribute \src "issuer_ls180.v:172468.3-172480.6" - wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$12066 - attribute \src "issuer_ls180.v:171824.13-171824.47" - wire width 7 $1\alu_spr0_spr_op__insn_type[6:0] - attribute \src "issuer_ls180.v:172468.3-172480.6" - wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$12067 - attribute \src "issuer_ls180.v:171828.7-171828.39" - wire $1\alu_spr0_spr_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:172673.3-172681.6" - wire $1\alui_l_r_alui$next[0:0]$12136 - attribute \src "issuer_ls180.v:171846.7-171846.27" - wire $1\alui_l_r_alui[0:0] - attribute \src "issuer_ls180.v:172481.3-172502.6" - wire width 64 $1\data_r0__o$next[63:0]$12071 - attribute \src "issuer_ls180.v:171878.14-171878.47" - wire width 64 $1\data_r0__o[63:0] - attribute \src "issuer_ls180.v:172481.3-172502.6" - wire $1\data_r0__o_ok$next[0:0]$12072 - attribute \src "issuer_ls180.v:171882.7-171882.27" - wire $1\data_r0__o_ok[0:0] - attribute \src "issuer_ls180.v:172503.3-172524.6" - wire width 64 $1\data_r1__spr1$next[63:0]$12079 - attribute \src "issuer_ls180.v:171886.14-171886.50" - wire width 64 $1\data_r1__spr1[63:0] - attribute \src "issuer_ls180.v:172503.3-172524.6" - wire $1\data_r1__spr1_ok$next[0:0]$12080 - attribute \src "issuer_ls180.v:171890.7-171890.30" - wire $1\data_r1__spr1_ok[0:0] - attribute \src "issuer_ls180.v:172525.3-172546.6" - wire width 64 $1\data_r2__fast1$next[63:0]$12087 - attribute \src "issuer_ls180.v:171894.14-171894.51" - wire width 64 $1\data_r2__fast1[63:0] - attribute \src "issuer_ls180.v:172525.3-172546.6" - wire $1\data_r2__fast1_ok$next[0:0]$12088 - attribute \src "issuer_ls180.v:171898.7-171898.31" - wire $1\data_r2__fast1_ok[0:0] - attribute \src "issuer_ls180.v:172547.3-172568.6" - wire $1\data_r3__xer_so$next[0:0]$12095 - attribute \src "issuer_ls180.v:171902.7-171902.29" - wire $1\data_r3__xer_so[0:0] - attribute \src "issuer_ls180.v:172547.3-172568.6" - wire $1\data_r3__xer_so_ok$next[0:0]$12096 - attribute \src "issuer_ls180.v:171906.7-171906.32" - wire $1\data_r3__xer_so_ok[0:0] - attribute \src "issuer_ls180.v:172569.3-172590.6" - wire width 2 $1\data_r4__xer_ov$next[1:0]$12103 - attribute \src "issuer_ls180.v:171910.13-171910.35" - wire width 2 $1\data_r4__xer_ov[1:0] - attribute \src "issuer_ls180.v:172569.3-172590.6" - wire $1\data_r4__xer_ov_ok$next[0:0]$12104 - attribute \src "issuer_ls180.v:171914.7-171914.32" - wire $1\data_r4__xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:172591.3-172612.6" - wire width 2 $1\data_r5__xer_ca$next[1:0]$12111 - attribute \src "issuer_ls180.v:171918.13-171918.35" - wire width 2 $1\data_r5__xer_ca[1:0] - attribute \src "issuer_ls180.v:172591.3-172612.6" - wire $1\data_r5__xer_ca_ok$next[0:0]$12112 - attribute \src "issuer_ls180.v:171922.7-171922.32" - wire $1\data_r5__xer_ca_ok[0:0] - attribute \src "issuer_ls180.v:172691.3-172700.6" - wire width 64 $1\dest1_o[63:0] - attribute \src "issuer_ls180.v:172701.3-172710.6" - wire width 64 $1\dest2_o[63:0] - attribute \src "issuer_ls180.v:172711.3-172720.6" - wire width 64 $1\dest3_o[63:0] - attribute \src "issuer_ls180.v:172721.3-172730.6" - wire $1\dest4_o[0:0] - attribute \src "issuer_ls180.v:172731.3-172740.6" - wire width 2 $1\dest5_o[1:0] - attribute \src "issuer_ls180.v:172741.3-172750.6" - wire width 2 $1\dest6_o[1:0] - attribute \src "issuer_ls180.v:172423.3-172431.6" - wire $1\opc_l_r_opc$next[0:0]$12046 - attribute \src "issuer_ls180.v:171950.7-171950.25" - wire $1\opc_l_r_opc[0:0] - attribute \src "issuer_ls180.v:172414.3-172422.6" - wire $1\opc_l_s_opc$next[0:0]$12043 - attribute \src "issuer_ls180.v:171954.7-171954.25" - wire $1\opc_l_s_opc[0:0] - attribute \src "issuer_ls180.v:172751.3-172759.6" - wire width 6 $1\prev_wr_go$next[5:0]$12148 - attribute \src "issuer_ls180.v:172053.13-172053.31" - wire width 6 $1\prev_wr_go[5:0] - attribute \src "issuer_ls180.v:172368.3-172377.6" - wire $1\req_done[0:0] - attribute \src "issuer_ls180.v:172459.3-172467.6" - wire width 6 $1\req_l_r_req$next[5:0]$12058 - attribute \src "issuer_ls180.v:172061.13-172061.32" - wire width 6 $1\req_l_r_req[5:0] - attribute \src "issuer_ls180.v:172450.3-172458.6" - wire width 6 $1\req_l_s_req$next[5:0]$12055 - attribute \src "issuer_ls180.v:172065.13-172065.32" - wire width 6 $1\req_l_s_req[5:0] - attribute \src "issuer_ls180.v:172387.3-172395.6" - wire $1\rok_l_r_rdok$next[0:0]$12034 - attribute \src "issuer_ls180.v:172077.7-172077.26" - wire $1\rok_l_r_rdok[0:0] - attribute \src "issuer_ls180.v:172378.3-172386.6" - wire $1\rok_l_s_rdok$next[0:0]$12031 - attribute \src "issuer_ls180.v:172081.7-172081.26" - wire $1\rok_l_s_rdok[0:0] - attribute \src "issuer_ls180.v:172405.3-172413.6" - wire $1\rst_l_r_rst$next[0:0]$12040 - attribute \src "issuer_ls180.v:172085.7-172085.25" - wire $1\rst_l_r_rst[0:0] - attribute \src "issuer_ls180.v:172396.3-172404.6" - wire $1\rst_l_s_rst$next[0:0]$12037 - attribute \src "issuer_ls180.v:172089.7-172089.25" - wire $1\rst_l_s_rst[0:0] - attribute \src "issuer_ls180.v:172441.3-172449.6" - wire width 6 $1\src_l_r_src$next[5:0]$12052 - attribute \src "issuer_ls180.v:172111.13-172111.32" - wire width 6 $1\src_l_r_src[5:0] - attribute \src "issuer_ls180.v:172432.3-172440.6" - wire width 6 $1\src_l_s_src$next[5:0]$12049 - attribute \src "issuer_ls180.v:172115.13-172115.32" - wire width 6 $1\src_l_s_src[5:0] - attribute \src "issuer_ls180.v:172613.3-172622.6" - wire width 64 $1\src_r0$next[63:0]$12118 - attribute \src "issuer_ls180.v:172119.14-172119.43" - wire width 64 $1\src_r0[63:0] - attribute \src "issuer_ls180.v:172623.3-172632.6" - wire width 64 $1\src_r1$next[63:0]$12121 - attribute \src "issuer_ls180.v:172123.14-172123.43" - wire width 64 $1\src_r1[63:0] - attribute \src "issuer_ls180.v:172633.3-172642.6" - wire width 64 $1\src_r2$next[63:0]$12124 - attribute \src "issuer_ls180.v:172127.14-172127.43" - wire width 64 $1\src_r2[63:0] - attribute \src "issuer_ls180.v:172643.3-172652.6" - wire $1\src_r3$next[0:0]$12127 - attribute \src "issuer_ls180.v:172131.7-172131.20" - wire $1\src_r3[0:0] - attribute \src "issuer_ls180.v:172653.3-172662.6" - wire width 2 $1\src_r4$next[1:0]$12130 - attribute \src "issuer_ls180.v:172135.13-172135.26" - wire width 2 $1\src_r4[1:0] - attribute \src "issuer_ls180.v:172663.3-172672.6" - wire width 2 $1\src_r5$next[1:0]$12133 - attribute \src "issuer_ls180.v:172139.13-172139.26" - wire width 2 $1\src_r5[1:0] - attribute \src "issuer_ls180.v:172481.3-172502.6" - wire width 64 $2\data_r0__o$next[63:0]$12073 - attribute \src "issuer_ls180.v:172481.3-172502.6" - wire $2\data_r0__o_ok$next[0:0]$12074 - attribute \src "issuer_ls180.v:172503.3-172524.6" - wire width 64 $2\data_r1__spr1$next[63:0]$12081 - attribute \src "issuer_ls180.v:172503.3-172524.6" - wire $2\data_r1__spr1_ok$next[0:0]$12082 - attribute \src "issuer_ls180.v:172525.3-172546.6" - wire width 64 $2\data_r2__fast1$next[63:0]$12089 - attribute \src "issuer_ls180.v:172525.3-172546.6" - wire $2\data_r2__fast1_ok$next[0:0]$12090 - attribute \src "issuer_ls180.v:172547.3-172568.6" - wire $2\data_r3__xer_so$next[0:0]$12097 - attribute \src "issuer_ls180.v:172547.3-172568.6" - wire $2\data_r3__xer_so_ok$next[0:0]$12098 - attribute \src "issuer_ls180.v:172569.3-172590.6" - wire width 2 $2\data_r4__xer_ov$next[1:0]$12105 - attribute \src "issuer_ls180.v:172569.3-172590.6" - wire $2\data_r4__xer_ov_ok$next[0:0]$12106 - attribute \src "issuer_ls180.v:172591.3-172612.6" - wire width 2 $2\data_r5__xer_ca$next[1:0]$12113 - attribute \src "issuer_ls180.v:172591.3-172612.6" - wire $2\data_r5__xer_ca_ok$next[0:0]$12114 - attribute \src "issuer_ls180.v:172481.3-172502.6" - wire $3\data_r0__o_ok$next[0:0]$12075 - attribute \src "issuer_ls180.v:172503.3-172524.6" - wire $3\data_r1__spr1_ok$next[0:0]$12083 - attribute \src "issuer_ls180.v:172525.3-172546.6" - wire $3\data_r2__fast1_ok$next[0:0]$12091 - attribute \src "issuer_ls180.v:172547.3-172568.6" - wire $3\data_r3__xer_so_ok$next[0:0]$12099 - attribute \src "issuer_ls180.v:172569.3-172590.6" - wire $3\data_r4__xer_ov_ok$next[0:0]$12107 - attribute \src "issuer_ls180.v:172591.3-172612.6" - wire $3\data_r5__xer_ca_ok$next[0:0]$12115 - attribute \src "issuer_ls180.v:172151.19-172151.133" - wire $and$issuer_ls180.v:172151$11926_Y - attribute \src "issuer_ls180.v:172152.19-172152.183" - wire width 6 $and$issuer_ls180.v:172152$11927_Y - attribute \src "issuer_ls180.v:172153.19-172153.115" - wire width 6 $and$issuer_ls180.v:172153$11928_Y - attribute \src "issuer_ls180.v:172155.19-172155.115" - wire width 6 $and$issuer_ls180.v:172155$11930_Y - attribute \src "issuer_ls180.v:172156.19-172156.125" - wire $and$issuer_ls180.v:172156$11931_Y - attribute \src "issuer_ls180.v:172157.19-172157.125" - wire $and$issuer_ls180.v:172157$11932_Y - attribute \src "issuer_ls180.v:172158.19-172158.125" - wire $and$issuer_ls180.v:172158$11933_Y - attribute \src "issuer_ls180.v:172159.19-172159.125" - wire $and$issuer_ls180.v:172159$11934_Y - attribute \src "issuer_ls180.v:172160.19-172160.125" - wire $and$issuer_ls180.v:172160$11935_Y - attribute \src "issuer_ls180.v:172162.19-172162.125" - wire $and$issuer_ls180.v:172162$11937_Y - attribute \src "issuer_ls180.v:172163.19-172163.165" - wire width 6 $and$issuer_ls180.v:172163$11938_Y - attribute \src "issuer_ls180.v:172164.19-172164.121" - wire width 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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire \src_r3$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r4$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" - wire \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 20 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 22 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 24 \xer_so_ok - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$issuer_ls180.v:172150$11925 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_rd__rel_o - connect \Y $not$issuer_ls180.v:172150$11925_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$issuer_ls180.v:172154$11929 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_rdmaskn_i - connect \Y $not$issuer_ls180.v:172154$11929_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:172173$11948 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $not$issuer_ls180.v:172173$11948_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:172175$11950 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $not$issuer_ls180.v:172175$11950_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$issuer_ls180.v:172178$11953 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_wrmask_o - connect \Y $not$issuer_ls180.v:172178$11953_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$issuer_ls180.v:172181$11956 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$27 - connect \Y $not$issuer_ls180.v:172181$11956_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$issuer_ls180.v:172186$11961 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_spr0_n_ready_i - connect \Y $not$issuer_ls180.v:172186$11961_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$issuer_ls180.v:172161$11936 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \$9 - connect \B \cu_rd__go_i - connect \Y $or$issuer_ls180.v:172161$11936_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$issuer_ls180.v:172185$11960 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$36 - connect \B \$38 - connect \Y $or$issuer_ls180.v:172185$11960_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$issuer_ls180.v:172195$11970 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $or$issuer_ls180.v:172195$11970_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$issuer_ls180.v:172196$11971 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $or$issuer_ls180.v:172196$11971_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$issuer_ls180.v:172197$11972 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$issuer_ls180.v:172197$11972_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$issuer_ls180.v:172198$11973 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$issuer_ls180.v:172198$11973_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$issuer_ls180.v:172202$11977 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $or$issuer_ls180.v:172202$11977_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$issuer_ls180.v:172167$11942 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \$11 - connect \Y $reduce_and$issuer_ls180.v:172167$11942_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$issuer_ls180.v:172180$11955 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \$30 - connect \Y $reduce_or$issuer_ls180.v:172180$11955_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$issuer_ls180.v:172183$11958 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $reduce_or$issuer_ls180.v:172183$11958_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$issuer_ls180.v:172184$11959 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $reduce_or$issuer_ls180.v:172184$11959_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:172209$11984 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src1_i - connect \S \src_l_q_src [0] - connect \Y $ternary$issuer_ls180.v:172209$11984_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:172210$11985 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src2_i - connect \S \src_l_q_src [1] - connect \Y $ternary$issuer_ls180.v:172210$11985_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:172211$11986 - parameter \WIDTH 64 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $ternary$issuer_ls180.v:172211$11986_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:172212$11987 - parameter \WIDTH 1 - connect \A \src_r3 - connect \B \src4_i - connect \S \src_l_q_src [3] - connect \Y $ternary$issuer_ls180.v:172212$11987_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:172213$11988 - parameter \WIDTH 2 - connect \A \src_r4 - connect \B \src5_i - connect \S \src_l_q_src [4] - connect \Y $ternary$issuer_ls180.v:172213$11988_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:172214$11989 - parameter \WIDTH 2 - connect \A \src_r5 - connect \B \src6_i - connect \S \src_l_q_src [5] - connect \Y $ternary$issuer_ls180.v:172214$11989_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:172290.14-172296.4" - cell \alu_l$70 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:172297.12-172326.4" - cell \alu_spr0 \alu_spr0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \fast1 \alu_spr0_fast1 - connect \fast1$2 \alu_spr0_fast1$2 - connect \fast1_ok \fast1_ok - connect \n_ready_i \alu_spr0_n_ready_i - connect \n_valid_o \alu_spr0_n_valid_o - connect \o \alu_spr0_o - connect \o_ok \o_ok - connect \p_ready_o \alu_spr0_p_ready_o - connect \p_valid_i \alu_spr0_p_valid_i - connect \ra \alu_spr0_ra - connect \spr1 \alu_spr0_spr1 - connect \spr1$1 \alu_spr0_spr1$1 - connect \spr1_ok \spr1_ok - connect \spr_op__fn_unit \alu_spr0_spr_op__fn_unit - connect \spr_op__insn \alu_spr0_spr_op__insn - connect \spr_op__insn_type \alu_spr0_spr_op__insn_type - connect \spr_op__is_32bit \alu_spr0_spr_op__is_32bit - connect \xer_ca \alu_spr0_xer_ca - connect \xer_ca$5 \alu_spr0_xer_ca$5 - connect \xer_ca_ok \xer_ca_ok - connect \xer_ov \alu_spr0_xer_ov - connect \xer_ov$4 \alu_spr0_xer_ov$4 - connect \xer_ov_ok \xer_ov_ok - connect \xer_so \alu_spr0_xer_so - connect \xer_so$3 \alu_spr0_xer_so$3 - connect \xer_so_ok \xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:172327.15-172333.4" - cell \alui_l$69 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:172334.14-172340.4" - cell \opc_l$65 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_opc \opc_l_q_opc - connect \r_opc \opc_l_r_opc - connect \s_opc \opc_l_s_opc - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:172341.14-172347.4" - cell \req_l$66 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \r_req \req_l_r_req - connect \s_req \req_l_s_req - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:172348.14-172354.4" - cell \rok_l$68 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \r_rdok \rok_l_r_rdok - connect \s_rdok \rok_l_s_rdok - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:172355.14-172360.4" - cell \rst_l$67 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_rst \rst_l_r_rst - connect \s_rst \rst_l_s_rst - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:172361.14-172367.4" - cell \src_l$64 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_src \src_l_q_src - connect \r_src \src_l_r_src - connect \s_src \src_l_s_src - end - attribute \src "issuer_ls180.v:171545.7-171545.20" - process $proc$issuer_ls180.v:171545$12149 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:171681.7-171681.24" - process $proc$issuer_ls180.v:171681$12150 - assign { } { } - assign $1\all_rd_dly[0:0] 1'0 - sync always - sync init - update \all_rd_dly $1\all_rd_dly[0:0] - end - attribute \src "issuer_ls180.v:171691.7-171691.26" - process $proc$issuer_ls180.v:171691$12151 - assign { } { } - assign $1\alu_done_dly[0:0] 1'0 - sync always - sync init - update \alu_done_dly $1\alu_done_dly[0:0] - end - attribute \src "issuer_ls180.v:171699.7-171699.25" - process $proc$issuer_ls180.v:171699$12152 - assign { } { } - assign $1\alu_l_r_alu[0:0] 1'1 - sync always - sync init - update \alu_l_r_alu $1\alu_l_r_alu[0:0] - end - attribute \src "issuer_ls180.v:171742.14-171742.48" - process $proc$issuer_ls180.v:171742$12153 - assign { } { } - assign $1\alu_spr0_spr_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \alu_spr0_spr_op__fn_unit $1\alu_spr0_spr_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:171746.14-171746.43" - process $proc$issuer_ls180.v:171746$12154 - assign { } { } - assign $1\alu_spr0_spr_op__insn[31:0] 0 - sync always - sync init - update \alu_spr0_spr_op__insn $1\alu_spr0_spr_op__insn[31:0] - end - attribute \src "issuer_ls180.v:171824.13-171824.47" - process $proc$issuer_ls180.v:171824$12155 - assign { } { } - assign $1\alu_spr0_spr_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \alu_spr0_spr_op__insn_type $1\alu_spr0_spr_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:171828.7-171828.39" - process $proc$issuer_ls180.v:171828$12156 - assign { } { } - assign $1\alu_spr0_spr_op__is_32bit[0:0] 1'0 - sync always - sync init - update \alu_spr0_spr_op__is_32bit $1\alu_spr0_spr_op__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:171846.7-171846.27" - process $proc$issuer_ls180.v:171846$12157 - assign { } { } - assign $1\alui_l_r_alui[0:0] 1'1 - sync always - sync init - update \alui_l_r_alui $1\alui_l_r_alui[0:0] - end - attribute \src "issuer_ls180.v:171878.14-171878.47" - process $proc$issuer_ls180.v:171878$12158 - assign { } { } - assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r0__o $1\data_r0__o[63:0] - end - attribute \src "issuer_ls180.v:171882.7-171882.27" - process $proc$issuer_ls180.v:171882$12159 - assign { } { } - assign $1\data_r0__o_ok[0:0] 1'0 - sync always - sync init - update \data_r0__o_ok $1\data_r0__o_ok[0:0] - end - attribute \src "issuer_ls180.v:171886.14-171886.50" - process $proc$issuer_ls180.v:171886$12160 - assign { } { } - assign $1\data_r1__spr1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r1__spr1 $1\data_r1__spr1[63:0] - end - attribute \src "issuer_ls180.v:171890.7-171890.30" - process $proc$issuer_ls180.v:171890$12161 - assign { } { } - assign $1\data_r1__spr1_ok[0:0] 1'0 - sync always - sync init - update \data_r1__spr1_ok $1\data_r1__spr1_ok[0:0] - end - attribute \src "issuer_ls180.v:171894.14-171894.51" - process $proc$issuer_ls180.v:171894$12162 - assign { } { } - assign $1\data_r2__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r2__fast1 $1\data_r2__fast1[63:0] - end - attribute \src "issuer_ls180.v:171898.7-171898.31" - process $proc$issuer_ls180.v:171898$12163 - assign { } { } - assign $1\data_r2__fast1_ok[0:0] 1'0 - sync always - sync init - update \data_r2__fast1_ok $1\data_r2__fast1_ok[0:0] - end - attribute \src "issuer_ls180.v:171902.7-171902.29" - process $proc$issuer_ls180.v:171902$12164 - assign { } { } - assign $1\data_r3__xer_so[0:0] 1'0 - sync always - sync init - update \data_r3__xer_so $1\data_r3__xer_so[0:0] - end - attribute \src "issuer_ls180.v:171906.7-171906.32" - process $proc$issuer_ls180.v:171906$12165 - assign { } { } - assign $1\data_r3__xer_so_ok[0:0] 1'0 - sync always - sync init - update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] - end - attribute \src "issuer_ls180.v:171910.13-171910.35" - process $proc$issuer_ls180.v:171910$12166 - assign { } { } - assign $1\data_r4__xer_ov[1:0] 2'00 - sync always - sync init - update \data_r4__xer_ov $1\data_r4__xer_ov[1:0] - end - attribute \src "issuer_ls180.v:171914.7-171914.32" - process $proc$issuer_ls180.v:171914$12167 - assign { } { } - assign $1\data_r4__xer_ov_ok[0:0] 1'0 - sync always - sync init - update \data_r4__xer_ov_ok $1\data_r4__xer_ov_ok[0:0] - end - attribute \src "issuer_ls180.v:171918.13-171918.35" - process $proc$issuer_ls180.v:171918$12168 - assign { } { } - assign $1\data_r5__xer_ca[1:0] 2'00 - sync always - sync init - update \data_r5__xer_ca $1\data_r5__xer_ca[1:0] - end - attribute \src "issuer_ls180.v:171922.7-171922.32" - process $proc$issuer_ls180.v:171922$12169 - assign { } { } - assign $1\data_r5__xer_ca_ok[0:0] 1'0 - sync always - sync init - update \data_r5__xer_ca_ok $1\data_r5__xer_ca_ok[0:0] - end - attribute \src "issuer_ls180.v:171950.7-171950.25" - process $proc$issuer_ls180.v:171950$12170 - assign { } { } - assign $1\opc_l_r_opc[0:0] 1'1 - sync always - sync init - update \opc_l_r_opc $1\opc_l_r_opc[0:0] - end - attribute \src "issuer_ls180.v:171954.7-171954.25" - process $proc$issuer_ls180.v:171954$12171 - assign { } { } - assign $1\opc_l_s_opc[0:0] 1'0 - sync always - sync init - update \opc_l_s_opc $1\opc_l_s_opc[0:0] - end - attribute \src "issuer_ls180.v:172053.13-172053.31" - process $proc$issuer_ls180.v:172053$12172 - assign { } { } - assign $1\prev_wr_go[5:0] 6'000000 - sync always - sync init - update \prev_wr_go $1\prev_wr_go[5:0] - end - attribute \src "issuer_ls180.v:172061.13-172061.32" - process $proc$issuer_ls180.v:172061$12173 - assign { } { } - assign $1\req_l_r_req[5:0] 6'111111 - sync always - sync init - update \req_l_r_req $1\req_l_r_req[5:0] - end - attribute \src "issuer_ls180.v:172065.13-172065.32" - process $proc$issuer_ls180.v:172065$12174 - assign { } { } - assign $1\req_l_s_req[5:0] 6'000000 - sync always - sync init - update \req_l_s_req $1\req_l_s_req[5:0] - end - attribute \src "issuer_ls180.v:172077.7-172077.26" - process $proc$issuer_ls180.v:172077$12175 - assign { } { } - assign $1\rok_l_r_rdok[0:0] 1'1 - sync always - sync init - update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] - end - attribute \src "issuer_ls180.v:172081.7-172081.26" - process $proc$issuer_ls180.v:172081$12176 - assign { } { } - assign $1\rok_l_s_rdok[0:0] 1'0 - sync always - sync init - update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] - end - attribute \src "issuer_ls180.v:172085.7-172085.25" - process $proc$issuer_ls180.v:172085$12177 - assign { } { } - assign $1\rst_l_r_rst[0:0] 1'1 - sync always - sync init - update \rst_l_r_rst $1\rst_l_r_rst[0:0] - end - attribute \src "issuer_ls180.v:172089.7-172089.25" - process $proc$issuer_ls180.v:172089$12178 - assign { } { } - assign $1\rst_l_s_rst[0:0] 1'0 - sync always - sync init - update \rst_l_s_rst $1\rst_l_s_rst[0:0] - end - attribute \src "issuer_ls180.v:172111.13-172111.32" - process $proc$issuer_ls180.v:172111$12179 - assign { } { } - assign $1\src_l_r_src[5:0] 6'111111 - sync always - sync init - update \src_l_r_src $1\src_l_r_src[5:0] - end - attribute \src "issuer_ls180.v:172115.13-172115.32" - process $proc$issuer_ls180.v:172115$12180 - assign { } { } - assign $1\src_l_s_src[5:0] 6'000000 - sync always - sync init - update \src_l_s_src $1\src_l_s_src[5:0] - end - attribute \src "issuer_ls180.v:172119.14-172119.43" - process $proc$issuer_ls180.v:172119$12181 - assign { } { } - assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r0 $1\src_r0[63:0] - end - attribute \src "issuer_ls180.v:172123.14-172123.43" - process $proc$issuer_ls180.v:172123$12182 - assign { } { } - assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r1 $1\src_r1[63:0] - end - attribute \src "issuer_ls180.v:172127.14-172127.43" - process $proc$issuer_ls180.v:172127$12183 - assign { } { } - assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r2 $1\src_r2[63:0] - end - attribute \src "issuer_ls180.v:172131.7-172131.20" - process $proc$issuer_ls180.v:172131$12184 - assign { } { } - assign $1\src_r3[0:0] 1'0 - sync always - sync init - update \src_r3 $1\src_r3[0:0] - end - attribute \src "issuer_ls180.v:172135.13-172135.26" - process $proc$issuer_ls180.v:172135$12185 - assign { } { } - assign $1\src_r4[1:0] 2'00 - sync always - sync init - update \src_r4 $1\src_r4[1:0] - end - attribute \src "issuer_ls180.v:172139.13-172139.26" - process $proc$issuer_ls180.v:172139$12186 - assign { } { } - assign $1\src_r5[1:0] 2'00 - sync always - sync init - update \src_r5 $1\src_r5[1:0] - end - attribute \src "issuer_ls180.v:172216.3-172217.39" - process $proc$issuer_ls180.v:172216$11991 - assign { } { } - assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next - sync posedge \coresync_clk - update \alu_l_r_alu $0\alu_l_r_alu[0:0] - end - attribute \src "issuer_ls180.v:172218.3-172219.43" - process $proc$issuer_ls180.v:172218$11992 - assign { } { } - assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next - sync posedge \coresync_clk - update \alui_l_r_alui $0\alui_l_r_alui[0:0] - end - attribute \src "issuer_ls180.v:172220.3-172221.29" - process $proc$issuer_ls180.v:172220$11993 - assign { } { } - assign $0\src_r5[1:0] \src_r5$next - sync posedge \coresync_clk - update \src_r5 $0\src_r5[1:0] - end - attribute \src "issuer_ls180.v:172222.3-172223.29" - process $proc$issuer_ls180.v:172222$11994 - assign { } { } - assign $0\src_r4[1:0] \src_r4$next - sync posedge \coresync_clk - update \src_r4 $0\src_r4[1:0] - end - attribute \src "issuer_ls180.v:172224.3-172225.29" - process $proc$issuer_ls180.v:172224$11995 - assign { } { } - assign $0\src_r3[0:0] \src_r3$next - sync posedge \coresync_clk - update \src_r3 $0\src_r3[0:0] - end - attribute \src "issuer_ls180.v:172226.3-172227.29" - process $proc$issuer_ls180.v:172226$11996 - assign { } { } - assign $0\src_r2[63:0] \src_r2$next - sync posedge \coresync_clk - update \src_r2 $0\src_r2[63:0] - end - attribute \src "issuer_ls180.v:172228.3-172229.29" - process $proc$issuer_ls180.v:172228$11997 - assign { } { } - assign $0\src_r1[63:0] \src_r1$next - sync posedge \coresync_clk - update \src_r1 $0\src_r1[63:0] - end - attribute \src "issuer_ls180.v:172230.3-172231.29" - process $proc$issuer_ls180.v:172230$11998 - assign { } { } - assign $0\src_r0[63:0] \src_r0$next - sync posedge \coresync_clk - update \src_r0 $0\src_r0[63:0] - end - attribute \src "issuer_ls180.v:172232.3-172233.47" - process $proc$issuer_ls180.v:172232$11999 - assign { } { } - assign $0\data_r5__xer_ca[1:0] \data_r5__xer_ca$next - sync posedge \coresync_clk - update \data_r5__xer_ca $0\data_r5__xer_ca[1:0] - end - attribute \src "issuer_ls180.v:172234.3-172235.53" - process $proc$issuer_ls180.v:172234$12000 - assign { } { } - assign $0\data_r5__xer_ca_ok[0:0] \data_r5__xer_ca_ok$next - sync posedge \coresync_clk - update \data_r5__xer_ca_ok $0\data_r5__xer_ca_ok[0:0] - end - attribute \src "issuer_ls180.v:172236.3-172237.47" - process $proc$issuer_ls180.v:172236$12001 - assign { } { } - assign $0\data_r4__xer_ov[1:0] \data_r4__xer_ov$next - sync posedge \coresync_clk - update \data_r4__xer_ov $0\data_r4__xer_ov[1:0] - end - attribute \src "issuer_ls180.v:172238.3-172239.53" - process $proc$issuer_ls180.v:172238$12002 - assign { } { } - assign $0\data_r4__xer_ov_ok[0:0] \data_r4__xer_ov_ok$next - sync posedge \coresync_clk - update \data_r4__xer_ov_ok $0\data_r4__xer_ov_ok[0:0] - end - attribute \src "issuer_ls180.v:172240.3-172241.47" - process $proc$issuer_ls180.v:172240$12003 - assign { } { } - assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next - sync posedge \coresync_clk - update \data_r3__xer_so $0\data_r3__xer_so[0:0] - end - attribute \src "issuer_ls180.v:172242.3-172243.53" - process $proc$issuer_ls180.v:172242$12004 - assign { } { } - assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next - sync posedge \coresync_clk - update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] - end - attribute \src "issuer_ls180.v:172244.3-172245.45" - process $proc$issuer_ls180.v:172244$12005 - assign { } { } - assign $0\data_r2__fast1[63:0] \data_r2__fast1$next - sync posedge \coresync_clk - update \data_r2__fast1 $0\data_r2__fast1[63:0] - end - attribute \src "issuer_ls180.v:172246.3-172247.51" - process $proc$issuer_ls180.v:172246$12006 - assign { } { } - assign $0\data_r2__fast1_ok[0:0] \data_r2__fast1_ok$next - sync posedge \coresync_clk - update \data_r2__fast1_ok $0\data_r2__fast1_ok[0:0] - end - attribute \src "issuer_ls180.v:172248.3-172249.43" - process $proc$issuer_ls180.v:172248$12007 - assign { } { } - assign $0\data_r1__spr1[63:0] \data_r1__spr1$next - sync posedge \coresync_clk - update \data_r1__spr1 $0\data_r1__spr1[63:0] - end - attribute \src "issuer_ls180.v:172250.3-172251.49" - process $proc$issuer_ls180.v:172250$12008 - assign { } { } - assign $0\data_r1__spr1_ok[0:0] \data_r1__spr1_ok$next - sync posedge \coresync_clk - update \data_r1__spr1_ok $0\data_r1__spr1_ok[0:0] - end - attribute \src "issuer_ls180.v:172252.3-172253.37" - process $proc$issuer_ls180.v:172252$12009 - assign { } { } - assign $0\data_r0__o[63:0] \data_r0__o$next - sync posedge \coresync_clk - update \data_r0__o $0\data_r0__o[63:0] - end - attribute \src "issuer_ls180.v:172254.3-172255.43" - process $proc$issuer_ls180.v:172254$12010 - assign { } { } - assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next - sync posedge \coresync_clk - update \data_r0__o_ok $0\data_r0__o_ok[0:0] - end - attribute \src "issuer_ls180.v:172256.3-172257.69" - process $proc$issuer_ls180.v:172256$12011 - assign { } { } - assign $0\alu_spr0_spr_op__insn_type[6:0] \alu_spr0_spr_op__insn_type$next - sync posedge \coresync_clk - update \alu_spr0_spr_op__insn_type $0\alu_spr0_spr_op__insn_type[6:0] - end - attribute \src "issuer_ls180.v:172258.3-172259.65" - process $proc$issuer_ls180.v:172258$12012 - assign { } { } - assign $0\alu_spr0_spr_op__fn_unit[11:0] \alu_spr0_spr_op__fn_unit$next - sync posedge \coresync_clk - update \alu_spr0_spr_op__fn_unit $0\alu_spr0_spr_op__fn_unit[11:0] - end - attribute \src "issuer_ls180.v:172260.3-172261.59" - process $proc$issuer_ls180.v:172260$12013 - assign { } { } - assign $0\alu_spr0_spr_op__insn[31:0] \alu_spr0_spr_op__insn$next - sync posedge \coresync_clk - update \alu_spr0_spr_op__insn $0\alu_spr0_spr_op__insn[31:0] - end - attribute \src "issuer_ls180.v:172262.3-172263.67" - process $proc$issuer_ls180.v:172262$12014 - assign { } { } - assign $0\alu_spr0_spr_op__is_32bit[0:0] \alu_spr0_spr_op__is_32bit$next - sync posedge \coresync_clk - update \alu_spr0_spr_op__is_32bit $0\alu_spr0_spr_op__is_32bit[0:0] - end - attribute \src "issuer_ls180.v:172264.3-172265.39" - process $proc$issuer_ls180.v:172264$12015 - assign { } { } - assign $0\req_l_r_req[5:0] \req_l_r_req$next - sync posedge \coresync_clk - update \req_l_r_req $0\req_l_r_req[5:0] - end - attribute \src "issuer_ls180.v:172266.3-172267.39" - process $proc$issuer_ls180.v:172266$12016 - assign { } { } - assign $0\req_l_s_req[5:0] \req_l_s_req$next - sync posedge \coresync_clk - update \req_l_s_req $0\req_l_s_req[5:0] - end - attribute \src "issuer_ls180.v:172268.3-172269.39" - process $proc$issuer_ls180.v:172268$12017 - assign { } { } - assign $0\src_l_r_src[5:0] \src_l_r_src$next - sync posedge \coresync_clk - update \src_l_r_src $0\src_l_r_src[5:0] - end - attribute \src "issuer_ls180.v:172270.3-172271.39" - process $proc$issuer_ls180.v:172270$12018 - assign { } { } - assign $0\src_l_s_src[5:0] \src_l_s_src$next - sync posedge \coresync_clk - update \src_l_s_src $0\src_l_s_src[5:0] - end - attribute \src "issuer_ls180.v:172272.3-172273.39" - process $proc$issuer_ls180.v:172272$12019 - assign { } { } - assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next - sync posedge \coresync_clk - update \opc_l_r_opc $0\opc_l_r_opc[0:0] - end - attribute \src "issuer_ls180.v:172274.3-172275.39" - process $proc$issuer_ls180.v:172274$12020 - assign { } { } - assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next - sync posedge \coresync_clk - update \opc_l_s_opc $0\opc_l_s_opc[0:0] - end - attribute \src "issuer_ls180.v:172276.3-172277.39" - process $proc$issuer_ls180.v:172276$12021 - assign { } { } - assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next - sync posedge \coresync_clk - update \rst_l_r_rst $0\rst_l_r_rst[0:0] - end - attribute \src "issuer_ls180.v:172278.3-172279.39" - process $proc$issuer_ls180.v:172278$12022 - assign { } { } - assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next - sync posedge \coresync_clk - update \rst_l_s_rst $0\rst_l_s_rst[0:0] - end - attribute \src "issuer_ls180.v:172280.3-172281.41" - process $proc$issuer_ls180.v:172280$12023 - assign { } { } - assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next - sync posedge \coresync_clk - update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] - end - attribute \src "issuer_ls180.v:172282.3-172283.41" - process $proc$issuer_ls180.v:172282$12024 - assign { } { } - assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next - sync posedge \coresync_clk - update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] - end - attribute \src "issuer_ls180.v:172284.3-172285.37" - process $proc$issuer_ls180.v:172284$12025 - assign { } { } - assign $0\prev_wr_go[5:0] \prev_wr_go$next - sync posedge \coresync_clk - update \prev_wr_go $0\prev_wr_go[5:0] - end - attribute \src "issuer_ls180.v:172286.3-172287.40" - process $proc$issuer_ls180.v:172286$12026 - assign { } { } - assign $0\alu_done_dly[0:0] \alu_spr0_n_valid_o - sync posedge \coresync_clk - update \alu_done_dly $0\alu_done_dly[0:0] - end - attribute \src "issuer_ls180.v:172288.3-172289.25" - process $proc$issuer_ls180.v:172288$12027 - assign { } { } - assign $0\all_rd_dly[0:0] \$14 - sync posedge \coresync_clk - update \all_rd_dly $0\all_rd_dly[0:0] - end - attribute \src "issuer_ls180.v:172368.3-172377.6" - process $proc$issuer_ls180.v:172368$12028 - assign { } { } - assign { } { } - assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "issuer_ls180.v:172369.5-172369.29" - switch \initial - attribute \src "issuer_ls180.v:172369.9-172369.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch \$58 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_done[0:0] 1'1 - case - assign $1\req_done[0:0] \$50 - end - sync always - update \req_done $0\req_done[0:0] - end - attribute \src "issuer_ls180.v:172378.3-172386.6" - process $proc$issuer_ls180.v:172378$12029 - assign { } { } - assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$12030 $1\rok_l_s_rdok$next[0:0]$12031 - attribute \src "issuer_ls180.v:172379.5-172379.29" - switch \initial - attribute \src "issuer_ls180.v:172379.9-172379.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$12031 1'0 - case - assign $1\rok_l_s_rdok$next[0:0]$12031 \cu_issue_i - end - sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12030 - end - attribute \src "issuer_ls180.v:172387.3-172395.6" - process $proc$issuer_ls180.v:172387$12032 - assign { } { } - assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$12033 $1\rok_l_r_rdok$next[0:0]$12034 - attribute \src "issuer_ls180.v:172388.5-172388.29" - switch \initial - attribute \src "issuer_ls180.v:172388.9-172388.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$12034 1'1 - case - assign $1\rok_l_r_rdok$next[0:0]$12034 \$68 - end - sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12033 - end - attribute \src "issuer_ls180.v:172396.3-172404.6" - process $proc$issuer_ls180.v:172396$12035 - assign { } { } - assign { } { } - assign $0\rst_l_s_rst$next[0:0]$12036 $1\rst_l_s_rst$next[0:0]$12037 - attribute \src "issuer_ls180.v:172397.5-172397.29" - switch \initial - attribute \src "issuer_ls180.v:172397.9-172397.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_s_rst$next[0:0]$12037 1'0 - case - assign $1\rst_l_s_rst$next[0:0]$12037 \all_rd - end - sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12036 - end - attribute \src "issuer_ls180.v:172405.3-172413.6" - process $proc$issuer_ls180.v:172405$12038 - assign { } { } - assign { } { } - assign $0\rst_l_r_rst$next[0:0]$12039 $1\rst_l_r_rst$next[0:0]$12040 - attribute \src "issuer_ls180.v:172406.5-172406.29" - switch \initial - attribute \src "issuer_ls180.v:172406.9-172406.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_r_rst$next[0:0]$12040 1'1 - case - assign $1\rst_l_r_rst$next[0:0]$12040 \rst_r - end - sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12039 - end - attribute \src "issuer_ls180.v:172414.3-172422.6" - process $proc$issuer_ls180.v:172414$12041 - assign { } { } - assign { } { } - assign $0\opc_l_s_opc$next[0:0]$12042 $1\opc_l_s_opc$next[0:0]$12043 - attribute \src "issuer_ls180.v:172415.5-172415.29" - switch \initial - attribute \src "issuer_ls180.v:172415.9-172415.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_s_opc$next[0:0]$12043 1'0 - case - assign $1\opc_l_s_opc$next[0:0]$12043 \cu_issue_i - end - sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12042 - end - attribute \src "issuer_ls180.v:172423.3-172431.6" - process $proc$issuer_ls180.v:172423$12044 - assign { } { } - assign { } { } - assign $0\opc_l_r_opc$next[0:0]$12045 $1\opc_l_r_opc$next[0:0]$12046 - attribute \src "issuer_ls180.v:172424.5-172424.29" - switch \initial - attribute \src "issuer_ls180.v:172424.9-172424.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_r_opc$next[0:0]$12046 1'1 - case - assign $1\opc_l_r_opc$next[0:0]$12046 \req_done - end - sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12045 - end - attribute \src "issuer_ls180.v:172432.3-172440.6" - process $proc$issuer_ls180.v:172432$12047 - assign { } { } - assign { } { } - assign $0\src_l_s_src$next[5:0]$12048 $1\src_l_s_src$next[5:0]$12049 - attribute \src "issuer_ls180.v:172433.5-172433.29" - switch \initial - attribute \src "issuer_ls180.v:172433.9-172433.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_s_src$next[5:0]$12049 6'000000 - case - assign $1\src_l_s_src$next[5:0]$12049 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } - end - sync always - update \src_l_s_src$next $0\src_l_s_src$next[5:0]$12048 - end - attribute \src "issuer_ls180.v:172441.3-172449.6" - process $proc$issuer_ls180.v:172441$12050 - assign { } { } - assign { } { } - assign $0\src_l_r_src$next[5:0]$12051 $1\src_l_r_src$next[5:0]$12052 - attribute \src "issuer_ls180.v:172442.5-172442.29" - switch \initial - attribute \src "issuer_ls180.v:172442.9-172442.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_r_src$next[5:0]$12052 6'111111 - case - assign $1\src_l_r_src$next[5:0]$12052 \reset_r - end - sync always - update \src_l_r_src$next $0\src_l_r_src$next[5:0]$12051 - end - attribute \src "issuer_ls180.v:172450.3-172458.6" - process $proc$issuer_ls180.v:172450$12053 - assign { } { } - assign { } { } - assign $0\req_l_s_req$next[5:0]$12054 $1\req_l_s_req$next[5:0]$12055 - attribute \src "issuer_ls180.v:172451.5-172451.29" - switch \initial - attribute \src "issuer_ls180.v:172451.9-172451.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_s_req$next[5:0]$12055 6'000000 - case - assign $1\req_l_s_req$next[5:0]$12055 \$70 - end - sync always - update \req_l_s_req$next $0\req_l_s_req$next[5:0]$12054 - end - attribute \src "issuer_ls180.v:172459.3-172467.6" - process $proc$issuer_ls180.v:172459$12056 - assign { } { } - assign { } { } - assign $0\req_l_r_req$next[5:0]$12057 $1\req_l_r_req$next[5:0]$12058 - attribute \src "issuer_ls180.v:172460.5-172460.29" - switch \initial - attribute \src "issuer_ls180.v:172460.9-172460.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_r_req$next[5:0]$12058 6'111111 - case - assign $1\req_l_r_req$next[5:0]$12058 \$72 - end - sync always - update \req_l_r_req$next $0\req_l_r_req$next[5:0]$12057 - end - attribute \src "issuer_ls180.v:172468.3-172480.6" - process $proc$issuer_ls180.v:172468$12059 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_spr0_spr_op__fn_unit$next[11:0]$12060 $1\alu_spr0_spr_op__fn_unit$next[11:0]$12064 - assign $0\alu_spr0_spr_op__insn$next[31:0]$12061 $1\alu_spr0_spr_op__insn$next[31:0]$12065 - assign $0\alu_spr0_spr_op__insn_type$next[6:0]$12062 $1\alu_spr0_spr_op__insn_type$next[6:0]$12066 - assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$12063 $1\alu_spr0_spr_op__is_32bit$next[0:0]$12067 - attribute \src "issuer_ls180.v:172469.5-172469.29" - switch \initial - attribute \src "issuer_ls180.v:172469.9-172469.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$12067 $1\alu_spr0_spr_op__insn$next[31:0]$12065 $1\alu_spr0_spr_op__fn_unit$next[11:0]$12064 $1\alu_spr0_spr_op__insn_type$next[6:0]$12066 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } - case - assign $1\alu_spr0_spr_op__fn_unit$next[11:0]$12064 \alu_spr0_spr_op__fn_unit - assign $1\alu_spr0_spr_op__insn$next[31:0]$12065 \alu_spr0_spr_op__insn - assign $1\alu_spr0_spr_op__insn_type$next[6:0]$12066 \alu_spr0_spr_op__insn_type - assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$12067 \alu_spr0_spr_op__is_32bit - end - sync always - update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[11:0]$12060 - update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$12061 - update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$12062 - update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$12063 - end - attribute \src "issuer_ls180.v:172481.3-172502.6" - process $proc$issuer_ls180.v:172481$12068 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r0__o$next[63:0]$12069 $2\data_r0__o$next[63:0]$12073 - assign { } { } - assign $0\data_r0__o_ok$next[0:0]$12070 $3\data_r0__o_ok$next[0:0]$12075 - attribute \src "issuer_ls180.v:172482.5-172482.29" - switch \initial - attribute \src "issuer_ls180.v:172482.9-172482.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$12072 $1\data_r0__o$next[63:0]$12071 } { \o_ok \alu_spr0_o } - case - assign $1\data_r0__o$next[63:0]$12071 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$12072 \data_r0__o_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$12074 $2\data_r0__o$next[63:0]$12073 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r0__o$next[63:0]$12073 $1\data_r0__o$next[63:0]$12071 - assign $2\data_r0__o_ok$next[0:0]$12074 $1\data_r0__o_ok$next[0:0]$12072 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r0__o_ok$next[0:0]$12075 1'0 - case - assign $3\data_r0__o_ok$next[0:0]$12075 $2\data_r0__o_ok$next[0:0]$12074 - end - sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$12069 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12070 - end - attribute \src "issuer_ls180.v:172503.3-172524.6" - process $proc$issuer_ls180.v:172503$12076 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r1__spr1$next[63:0]$12077 $2\data_r1__spr1$next[63:0]$12081 - assign { } { } - assign $0\data_r1__spr1_ok$next[0:0]$12078 $3\data_r1__spr1_ok$next[0:0]$12083 - attribute \src "issuer_ls180.v:172504.5-172504.29" - switch \initial - attribute \src "issuer_ls180.v:172504.9-172504.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r1__spr1_ok$next[0:0]$12080 $1\data_r1__spr1$next[63:0]$12079 } { \spr1_ok \alu_spr0_spr1 } - case - assign $1\data_r1__spr1$next[63:0]$12079 \data_r1__spr1 - assign $1\data_r1__spr1_ok$next[0:0]$12080 \data_r1__spr1_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r1__spr1_ok$next[0:0]$12082 $2\data_r1__spr1$next[63:0]$12081 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r1__spr1$next[63:0]$12081 $1\data_r1__spr1$next[63:0]$12079 - assign $2\data_r1__spr1_ok$next[0:0]$12082 $1\data_r1__spr1_ok$next[0:0]$12080 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r1__spr1_ok$next[0:0]$12083 1'0 - case - assign $3\data_r1__spr1_ok$next[0:0]$12083 $2\data_r1__spr1_ok$next[0:0]$12082 - end - sync always - update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$12077 - update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$12078 - end - attribute \src "issuer_ls180.v:172525.3-172546.6" - process $proc$issuer_ls180.v:172525$12084 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r2__fast1$next[63:0]$12085 $2\data_r2__fast1$next[63:0]$12089 - assign { } { } - assign $0\data_r2__fast1_ok$next[0:0]$12086 $3\data_r2__fast1_ok$next[0:0]$12091 - attribute \src "issuer_ls180.v:172526.5-172526.29" - switch \initial - attribute \src "issuer_ls180.v:172526.9-172526.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r2__fast1_ok$next[0:0]$12088 $1\data_r2__fast1$next[63:0]$12087 } { \fast1_ok \alu_spr0_fast1 } - case - assign $1\data_r2__fast1$next[63:0]$12087 \data_r2__fast1 - assign $1\data_r2__fast1_ok$next[0:0]$12088 \data_r2__fast1_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r2__fast1_ok$next[0:0]$12090 $2\data_r2__fast1$next[63:0]$12089 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r2__fast1$next[63:0]$12089 $1\data_r2__fast1$next[63:0]$12087 - assign $2\data_r2__fast1_ok$next[0:0]$12090 $1\data_r2__fast1_ok$next[0:0]$12088 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r2__fast1_ok$next[0:0]$12091 1'0 - case - assign $3\data_r2__fast1_ok$next[0:0]$12091 $2\data_r2__fast1_ok$next[0:0]$12090 - end - sync always - update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$12085 - update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$12086 - end - attribute \src "issuer_ls180.v:172547.3-172568.6" - process $proc$issuer_ls180.v:172547$12092 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r3__xer_so$next[0:0]$12093 $2\data_r3__xer_so$next[0:0]$12097 - assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$12094 $3\data_r3__xer_so_ok$next[0:0]$12099 - attribute \src "issuer_ls180.v:172548.5-172548.29" - switch \initial - attribute \src "issuer_ls180.v:172548.9-172548.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$12096 $1\data_r3__xer_so$next[0:0]$12095 } { \xer_so_ok \alu_spr0_xer_so } - case - assign $1\data_r3__xer_so$next[0:0]$12095 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$12096 \data_r3__xer_so_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$12098 $2\data_r3__xer_so$next[0:0]$12097 } 2'00 - case - assign $2\data_r3__xer_so$next[0:0]$12097 $1\data_r3__xer_so$next[0:0]$12095 - assign $2\data_r3__xer_so_ok$next[0:0]$12098 $1\data_r3__xer_so_ok$next[0:0]$12096 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$12099 1'0 - case - assign $3\data_r3__xer_so_ok$next[0:0]$12099 $2\data_r3__xer_so_ok$next[0:0]$12098 - end - sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$12093 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$12094 - end - attribute \src "issuer_ls180.v:172569.3-172590.6" - process $proc$issuer_ls180.v:172569$12100 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r4__xer_ov$next[1:0]$12101 $2\data_r4__xer_ov$next[1:0]$12105 - assign { } { } - assign $0\data_r4__xer_ov_ok$next[0:0]$12102 $3\data_r4__xer_ov_ok$next[0:0]$12107 - attribute \src "issuer_ls180.v:172570.5-172570.29" - switch \initial - attribute \src "issuer_ls180.v:172570.9-172570.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r4__xer_ov_ok$next[0:0]$12104 $1\data_r4__xer_ov$next[1:0]$12103 } { \xer_ov_ok \alu_spr0_xer_ov } - case - assign $1\data_r4__xer_ov$next[1:0]$12103 \data_r4__xer_ov - assign $1\data_r4__xer_ov_ok$next[0:0]$12104 \data_r4__xer_ov_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r4__xer_ov_ok$next[0:0]$12106 $2\data_r4__xer_ov$next[1:0]$12105 } 3'000 - case - assign $2\data_r4__xer_ov$next[1:0]$12105 $1\data_r4__xer_ov$next[1:0]$12103 - assign $2\data_r4__xer_ov_ok$next[0:0]$12106 $1\data_r4__xer_ov_ok$next[0:0]$12104 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r4__xer_ov_ok$next[0:0]$12107 1'0 - case - assign $3\data_r4__xer_ov_ok$next[0:0]$12107 $2\data_r4__xer_ov_ok$next[0:0]$12106 - end - sync always - update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$12101 - update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$12102 - end - attribute \src "issuer_ls180.v:172591.3-172612.6" - process $proc$issuer_ls180.v:172591$12108 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r5__xer_ca$next[1:0]$12109 $2\data_r5__xer_ca$next[1:0]$12113 - assign { } { } - assign $0\data_r5__xer_ca_ok$next[0:0]$12110 $3\data_r5__xer_ca_ok$next[0:0]$12115 - attribute \src "issuer_ls180.v:172592.5-172592.29" - switch \initial - attribute \src "issuer_ls180.v:172592.9-172592.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r5__xer_ca_ok$next[0:0]$12112 $1\data_r5__xer_ca$next[1:0]$12111 } { \xer_ca_ok \alu_spr0_xer_ca } - case - assign $1\data_r5__xer_ca$next[1:0]$12111 \data_r5__xer_ca - assign $1\data_r5__xer_ca_ok$next[0:0]$12112 \data_r5__xer_ca_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r5__xer_ca_ok$next[0:0]$12114 $2\data_r5__xer_ca$next[1:0]$12113 } 3'000 - case - assign $2\data_r5__xer_ca$next[1:0]$12113 $1\data_r5__xer_ca$next[1:0]$12111 - assign $2\data_r5__xer_ca_ok$next[0:0]$12114 $1\data_r5__xer_ca_ok$next[0:0]$12112 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r5__xer_ca_ok$next[0:0]$12115 1'0 - case - assign $3\data_r5__xer_ca_ok$next[0:0]$12115 $2\data_r5__xer_ca_ok$next[0:0]$12114 - end - sync always - update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$12109 - update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$12110 - end - attribute \src "issuer_ls180.v:172613.3-172622.6" - process $proc$issuer_ls180.v:172613$12116 - assign { } { } - assign { } { } - assign $0\src_r0$next[63:0]$12117 $1\src_r0$next[63:0]$12118 - attribute \src "issuer_ls180.v:172614.5-172614.29" - switch \initial - attribute \src "issuer_ls180.v:172614.9-172614.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [0] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r0$next[63:0]$12118 \src1_i - case - assign $1\src_r0$next[63:0]$12118 \src_r0 - end - sync always - update \src_r0$next $0\src_r0$next[63:0]$12117 - end - attribute \src "issuer_ls180.v:172623.3-172632.6" - process $proc$issuer_ls180.v:172623$12119 - assign { } { } - assign { } { } - assign $0\src_r1$next[63:0]$12120 $1\src_r1$next[63:0]$12121 - attribute \src "issuer_ls180.v:172624.5-172624.29" - switch \initial - attribute \src "issuer_ls180.v:172624.9-172624.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [1] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r1$next[63:0]$12121 \src2_i - case - assign $1\src_r1$next[63:0]$12121 \src_r1 - end - sync always - update \src_r1$next $0\src_r1$next[63:0]$12120 - end - attribute \src "issuer_ls180.v:172633.3-172642.6" - process $proc$issuer_ls180.v:172633$12122 - assign { } { } - assign { } { } - assign $0\src_r2$next[63:0]$12123 $1\src_r2$next[63:0]$12124 - attribute \src "issuer_ls180.v:172634.5-172634.29" - switch \initial - attribute \src "issuer_ls180.v:172634.9-172634.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [2] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r2$next[63:0]$12124 \src3_i - case - assign $1\src_r2$next[63:0]$12124 \src_r2 - end - sync always - update \src_r2$next $0\src_r2$next[63:0]$12123 - end - attribute \src "issuer_ls180.v:172643.3-172652.6" - process $proc$issuer_ls180.v:172643$12125 - assign { } { } - assign { } { } - assign $0\src_r3$next[0:0]$12126 $1\src_r3$next[0:0]$12127 - attribute \src "issuer_ls180.v:172644.5-172644.29" - switch \initial - attribute \src "issuer_ls180.v:172644.9-172644.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [3] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r3$next[0:0]$12127 \src4_i - case - assign $1\src_r3$next[0:0]$12127 \src_r3 - end - sync always - update \src_r3$next $0\src_r3$next[0:0]$12126 - end - attribute \src "issuer_ls180.v:172653.3-172662.6" - process $proc$issuer_ls180.v:172653$12128 - assign { } { } - assign { } { } - assign $0\src_r4$next[1:0]$12129 $1\src_r4$next[1:0]$12130 - attribute \src "issuer_ls180.v:172654.5-172654.29" - switch \initial - attribute \src "issuer_ls180.v:172654.9-172654.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [4] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r4$next[1:0]$12130 \src5_i - case - assign $1\src_r4$next[1:0]$12130 \src_r4 - end - sync always - update \src_r4$next $0\src_r4$next[1:0]$12129 - end - attribute \src "issuer_ls180.v:172663.3-172672.6" - process $proc$issuer_ls180.v:172663$12131 - assign { } { } - assign { } { } - assign $0\src_r5$next[1:0]$12132 $1\src_r5$next[1:0]$12133 - attribute \src "issuer_ls180.v:172664.5-172664.29" - switch \initial - attribute \src "issuer_ls180.v:172664.9-172664.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [5] - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r5$next[1:0]$12133 \src6_i - case - assign $1\src_r5$next[1:0]$12133 \src_r5 - end - sync always - update \src_r5$next $0\src_r5$next[1:0]$12132 - end - attribute \src "issuer_ls180.v:172673.3-172681.6" - process $proc$issuer_ls180.v:172673$12134 - assign { } { } - assign { } { } - assign $0\alui_l_r_alui$next[0:0]$12135 $1\alui_l_r_alui$next[0:0]$12136 - attribute \src "issuer_ls180.v:172674.5-172674.29" - switch \initial - attribute \src "issuer_ls180.v:172674.9-172674.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alui_l_r_alui$next[0:0]$12136 1'1 - case - assign $1\alui_l_r_alui$next[0:0]$12136 \$98 - end - sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12135 - end - attribute \src "issuer_ls180.v:172682.3-172690.6" - process $proc$issuer_ls180.v:172682$12137 - assign { } { } - assign { } { } - assign $0\alu_l_r_alu$next[0:0]$12138 $1\alu_l_r_alu$next[0:0]$12139 - attribute \src "issuer_ls180.v:172683.5-172683.29" - switch \initial - attribute \src "issuer_ls180.v:172683.9-172683.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alu_l_r_alu$next[0:0]$12139 1'1 - case - assign $1\alu_l_r_alu$next[0:0]$12139 \$100 - end - sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12138 - end - attribute \src "issuer_ls180.v:172691.3-172700.6" - process $proc$issuer_ls180.v:172691$12140 - assign { } { } - assign { } { } - assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "issuer_ls180.v:172692.5-172692.29" - switch \initial - attribute \src "issuer_ls180.v:172692.9-172692.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$126 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest1_o[63:0] \data_r0__o - case - assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest1_o $0\dest1_o[63:0] - end - attribute \src "issuer_ls180.v:172701.3-172710.6" - process $proc$issuer_ls180.v:172701$12141 - assign { } { } - assign { } { } - assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "issuer_ls180.v:172702.5-172702.29" - switch \initial - attribute \src "issuer_ls180.v:172702.9-172702.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$128 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest2_o[63:0] \data_r1__spr1 - case - assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest2_o $0\dest2_o[63:0] - end - attribute \src "issuer_ls180.v:172711.3-172720.6" - process $proc$issuer_ls180.v:172711$12142 - assign { } { } - assign { } { } - assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "issuer_ls180.v:172712.5-172712.29" - switch \initial - attribute \src "issuer_ls180.v:172712.9-172712.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$130 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest3_o[63:0] \data_r2__fast1 - case - assign $1\dest3_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest3_o $0\dest3_o[63:0] - end - attribute \src "issuer_ls180.v:172721.3-172730.6" - process $proc$issuer_ls180.v:172721$12143 - assign { } { } - assign { } { } - assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "issuer_ls180.v:172722.5-172722.29" - switch \initial - attribute \src "issuer_ls180.v:172722.9-172722.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$132 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest4_o[0:0] \data_r3__xer_so - case - assign $1\dest4_o[0:0] 1'0 - end - sync always - update \dest4_o $0\dest4_o[0:0] - end - attribute \src "issuer_ls180.v:172731.3-172740.6" - process $proc$issuer_ls180.v:172731$12144 - assign { } { } - assign { } { } - assign $0\dest5_o[1:0] $1\dest5_o[1:0] - attribute \src "issuer_ls180.v:172732.5-172732.29" - switch \initial - attribute \src "issuer_ls180.v:172732.9-172732.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$134 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest5_o[1:0] \data_r4__xer_ov - case - assign $1\dest5_o[1:0] 2'00 - end - sync always - update \dest5_o $0\dest5_o[1:0] - end - attribute \src "issuer_ls180.v:172741.3-172750.6" - process $proc$issuer_ls180.v:172741$12145 - assign { } { } - assign { } { } - assign $0\dest6_o[1:0] $1\dest6_o[1:0] - attribute \src "issuer_ls180.v:172742.5-172742.29" - switch \initial - attribute \src "issuer_ls180.v:172742.9-172742.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$136 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest6_o[1:0] \data_r5__xer_ca - case - assign $1\dest6_o[1:0] 2'00 - end - sync always - update \dest6_o $0\dest6_o[1:0] - end - attribute \src "issuer_ls180.v:172751.3-172759.6" - process $proc$issuer_ls180.v:172751$12146 - assign { } { } - assign { } { } - assign $0\prev_wr_go$next[5:0]$12147 $1\prev_wr_go$next[5:0]$12148 - attribute \src "issuer_ls180.v:172752.5-172752.29" - switch \initial - attribute \src "issuer_ls180.v:172752.9-172752.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\prev_wr_go$next[5:0]$12148 6'000000 - case - assign $1\prev_wr_go$next[5:0]$12148 \$24 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[5:0]$12147 - end - connect \$9 $not$issuer_ls180.v:172150$11925_Y - connect \$100 $and$issuer_ls180.v:172151$11926_Y - connect \$102 $and$issuer_ls180.v:172152$11927_Y - connect \$104 $and$issuer_ls180.v:172153$11928_Y - connect \$106 $not$issuer_ls180.v:172154$11929_Y - connect \$108 $and$issuer_ls180.v:172155$11930_Y - connect \$110 $and$issuer_ls180.v:172156$11931_Y - connect \$112 $and$issuer_ls180.v:172157$11932_Y - connect \$114 $and$issuer_ls180.v:172158$11933_Y - connect \$116 $and$issuer_ls180.v:172159$11934_Y - connect \$118 $and$issuer_ls180.v:172160$11935_Y - connect \$11 $or$issuer_ls180.v:172161$11936_Y - connect \$120 $and$issuer_ls180.v:172162$11937_Y - connect \$122 $and$issuer_ls180.v:172163$11938_Y - connect \$124 $and$issuer_ls180.v:172164$11939_Y - connect \$126 $and$issuer_ls180.v:172165$11940_Y - connect \$128 $and$issuer_ls180.v:172166$11941_Y - connect \$8 $reduce_and$issuer_ls180.v:172167$11942_Y - connect \$130 $and$issuer_ls180.v:172168$11943_Y - connect \$132 $and$issuer_ls180.v:172169$11944_Y - connect \$134 $and$issuer_ls180.v:172170$11945_Y - connect \$136 $and$issuer_ls180.v:172171$11946_Y - connect \$14 $and$issuer_ls180.v:172172$11947_Y - connect \$16 $not$issuer_ls180.v:172173$11948_Y - connect \$18 $and$issuer_ls180.v:172174$11949_Y - connect \$20 $not$issuer_ls180.v:172175$11950_Y - connect \$22 $and$issuer_ls180.v:172176$11951_Y - connect \$24 $and$issuer_ls180.v:172177$11952_Y - connect \$28 $not$issuer_ls180.v:172178$11953_Y - connect \$30 $and$issuer_ls180.v:172179$11954_Y - connect \$27 $reduce_or$issuer_ls180.v:172180$11955_Y - connect \$26 $not$issuer_ls180.v:172181$11956_Y - connect \$34 $and$issuer_ls180.v:172182$11957_Y - connect \$36 $reduce_or$issuer_ls180.v:172183$11958_Y - connect \$38 $reduce_or$issuer_ls180.v:172184$11959_Y - connect \$40 $or$issuer_ls180.v:172185$11960_Y - connect \$42 $not$issuer_ls180.v:172186$11961_Y - connect \$44 $and$issuer_ls180.v:172187$11962_Y - connect \$46 $and$issuer_ls180.v:172188$11963_Y - connect \$48 $eq$issuer_ls180.v:172189$11964_Y - connect \$50 $and$issuer_ls180.v:172190$11965_Y - connect \$52 $eq$issuer_ls180.v:172191$11966_Y - connect \$54 $and$issuer_ls180.v:172192$11967_Y - connect \$56 $and$issuer_ls180.v:172193$11968_Y - connect \$58 $and$issuer_ls180.v:172194$11969_Y - connect \$60 $or$issuer_ls180.v:172195$11970_Y - connect \$62 $or$issuer_ls180.v:172196$11971_Y - connect \$64 $or$issuer_ls180.v:172197$11972_Y - connect \$66 $or$issuer_ls180.v:172198$11973_Y - connect \$68 $and$issuer_ls180.v:172199$11974_Y - connect \$6 $and$issuer_ls180.v:172200$11975_Y - connect \$70 $and$issuer_ls180.v:172201$11976_Y - connect \$72 $or$issuer_ls180.v:172202$11977_Y - connect \$74 $and$issuer_ls180.v:172203$11978_Y - connect \$76 $and$issuer_ls180.v:172204$11979_Y - connect \$78 $and$issuer_ls180.v:172205$11980_Y - connect \$80 $and$issuer_ls180.v:172206$11981_Y - connect \$82 $and$issuer_ls180.v:172207$11982_Y - connect \$84 $and$issuer_ls180.v:172208$11983_Y - connect \$86 $ternary$issuer_ls180.v:172209$11984_Y - connect \$88 $ternary$issuer_ls180.v:172210$11985_Y - connect \$90 $ternary$issuer_ls180.v:172211$11986_Y - connect \$92 $ternary$issuer_ls180.v:172212$11987_Y - connect \$94 $ternary$issuer_ls180.v:172213$11988_Y - connect \$96 $ternary$issuer_ls180.v:172214$11989_Y - connect \$98 $and$issuer_ls180.v:172215$11990_Y - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 - connect \cu_wr__rel_o \$124 - connect \cu_rd__rel_o \$108 - connect \cu_busy_o \opc_l_q_opc - connect \alu_l_s_alu \all_rd_pulse - connect \alu_spr0_n_ready_i \alu_l_q_alu - connect \alui_l_s_alui \all_rd_pulse - connect \alu_spr0_p_valid_i \alui_l_q_alui - connect \alu_spr0_xer_ca$5 \$96 - connect \alu_spr0_xer_ov$4 \$94 - connect \alu_spr0_xer_so$3 \$92 - connect \alu_spr0_fast1$2 \$90 - connect \alu_spr0_spr1$1 \$88 - connect \alu_spr0_ra \$86 - connect \cu_wrmask_o { \$84 \$82 \$80 \$78 \$76 \$74 } - connect \reset_r \$66 - connect \reset_w \$64 - connect \rst_r \$62 - connect \reset \$60 - connect \wr_any \$40 - connect \cu_done_o \$34 - connect \alu_pulsem { \alu_pulse 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"/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 7 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 20 \fast1$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 21 \fast1_ok - attribute \src "issuer_ls180.v:172796.7-172796.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 28 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 11 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 16 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 17 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 5 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:42" - wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 6 \spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 18 \spr1$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 19 \spr1_ok - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute 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attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 13 \spr_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 3 \spr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 14 \spr_op__insn$4 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - 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attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 12 \spr_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \spr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \spr_op__is_32bit$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 10 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 26 \xer_ca$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 27 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 9 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 24 \xer_ov$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 25 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 8 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 22 \xer_so$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 23 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$issuer_ls180.v:173055$12187 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000000001 - connect \Y $eq$issuer_ls180.v:173055$12187_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$issuer_ls180.v:173056$12188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000000001 - connect \Y $eq$issuer_ls180.v:173056$12188_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$issuer_ls180.v:173057$12189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000000001 - connect \Y $eq$issuer_ls180.v:173057$12189_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$issuer_ls180.v:173058$12190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000000001 - connect \Y $eq$issuer_ls180.v:173058$12190_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$issuer_ls180.v:173059$12191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000000001 - connect \Y $eq$issuer_ls180.v:173059$12191_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$issuer_ls180.v:173060$12192 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000000001 - connect \Y $eq$issuer_ls180.v:173060$12192_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" - cell $eq $eq$issuer_ls180.v:173061$12193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000000001 - connect \Y $eq$issuer_ls180.v:173061$12193_Y - end - attribute \src "issuer_ls180.v:172796.7-172796.20" - process $proc$issuer_ls180.v:172796$12223 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:173062.3-173077.6" - process $proc$issuer_ls180.v:173062$12194 - assign { } { } - assign { } { } - assign $0\fast1$7[63:0]$12195 $1\fast1$7[63:0]$12196 - attribute \src "issuer_ls180.v:173063.5-173063.29" - switch \initial - attribute \src "issuer_ls180.v:173063.9-173063.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110001 - assign { } { } - assign $1\fast1$7[63:0]$12196 $2\fast1$7[63:0]$12197 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign { } { } - assign $2\fast1$7[63:0]$12197 \ra - case - assign $2\fast1$7[63:0]$12197 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\fast1$7[63:0]$12196 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fast1$7 $0\fast1$7[63:0]$12195 - end - attribute \src "issuer_ls180.v:173078.3-173096.6" - process $proc$issuer_ls180.v:173078$12198 - assign { } { } - assign { } { } - assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] - attribute \src "issuer_ls180.v:173079.5-173079.29" - switch \initial - attribute \src "issuer_ls180.v:173079.9-173079.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110001 - assign { } { } - assign $1\spr1_ok[0:0] $2\spr1_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign $2\spr1_ok[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\spr1_ok[0:0] 1'1 - end - case - assign $1\spr1_ok[0:0] 1'0 - end - sync always - update \spr1_ok $0\spr1_ok[0:0] - end - attribute \src "issuer_ls180.v:173097.3-173138.6" - process $proc$issuer_ls180.v:173097$12199 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o_ok[0:0] $1\o_ok[0:0] - assign $0\o[63:0] $1\o[63:0] - attribute \src "issuer_ls180.v:173098.5-173098.29" - switch \initial - attribute \src "issuer_ls180.v:173098.9-173098.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0101110 - assign { } { } - assign { } { } - assign $1\o_ok[0:0] 1'1 - assign $1\o[63:0] $2\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:77" - switch \spr - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 , 10'0100001100 - assign { } { } - assign $2\o[63:0] [17:0] \fast1 [17:0] - assign $2\o[63:0] [63:18] $3\o[63:18] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" - switch \$23 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\o[63:18] [45:14] 0 - assign $3\o[63:18] [10:2] 9'000000000 - assign $3\o[63:18] [13] \xer_so - assign $3\o[63:18] [12] \xer_ov [0] - assign $3\o[63:18] [1] \xer_ov [1] - assign $3\o[63:18] [11] \xer_ca [0] - assign $3\o[63:18] [0] \xer_ca [1] - case - assign $3\o[63:18] \fast1 [63:18] - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100001101 - assign $2\o[63:0] [63:32] 0 - assign $2\o[63:0] [31:0] \fast1 [63:32] - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\o[63:0] \spr1 - end - case - assign $1\o_ok[0:0] 1'0 - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \o_ok $0\o_ok[0:0] - update \o $0\o[63:0] - end - attribute \src "issuer_ls180.v:173139.3-173154.6" - process $proc$issuer_ls180.v:173139$12200 - assign { } { } - assign { } { } - assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "issuer_ls180.v:173140.5-173140.29" - switch \initial - attribute \src "issuer_ls180.v:173140.9-173140.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110001 - assign { } { } - assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign { } { } - assign $2\fast1_ok[0:0] 1'1 - case - assign $2\fast1_ok[0:0] 1'0 - end - case - assign $1\fast1_ok[0:0] 1'0 - end - sync always - update \fast1_ok $0\fast1_ok[0:0] - end - attribute \src "issuer_ls180.v:173155.3-173175.6" - process $proc$issuer_ls180.v:173155$12201 - assign { } { } - assign { } { } - assign $0\xer_so$8[0:0]$12202 $1\xer_so$8[0:0]$12203 - attribute \src "issuer_ls180.v:173156.5-173156.29" - switch \initial - attribute \src "issuer_ls180.v:173156.9-173156.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110001 - assign { } { } - assign $1\xer_so$8[0:0]$12203 $2\xer_so$8[0:0]$12204 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign { } { } - assign $2\xer_so$8[0:0]$12204 $3\xer_so$8[0:0]$12205 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - switch \$11 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\xer_so$8[0:0]$12205 \ra [31] - case - assign $3\xer_so$8[0:0]$12205 1'0 - end - case - assign $2\xer_so$8[0:0]$12204 1'0 - end - case - assign $1\xer_so$8[0:0]$12203 1'0 - end - sync always - update \xer_so$8 $0\xer_so$8[0:0]$12202 - end - attribute \src "issuer_ls180.v:173176.3-173196.6" - process $proc$issuer_ls180.v:173176$12206 - assign { } { } - assign { } { } - assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "issuer_ls180.v:173177.5-173177.29" - switch \initial - attribute \src "issuer_ls180.v:173177.9-173177.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110001 - assign { } { } - assign $1\xer_so_ok[0:0] $2\xer_so_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign { } { } - assign $2\xer_so_ok[0:0] $3\xer_so_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - switch \$13 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\xer_so_ok[0:0] 1'1 - case - assign $3\xer_so_ok[0:0] 1'0 - end - case - assign $2\xer_so_ok[0:0] 1'0 - end - case - assign $1\xer_so_ok[0:0] 1'0 - end - sync always - update \xer_so_ok $0\xer_so_ok[0:0] - end - attribute \src "issuer_ls180.v:173197.3-173220.6" - process $proc$issuer_ls180.v:173197$12207 - assign { } { } - assign { } { } - assign $0\xer_ov$9[1:0]$12208 $1\xer_ov$9[1:0]$12209 - attribute \src "issuer_ls180.v:173198.5-173198.29" - switch \initial - attribute \src "issuer_ls180.v:173198.9-173198.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110001 - assign { } { } - assign $1\xer_ov$9[1:0]$12209 $2\xer_ov$9[1:0]$12210 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign { } { } - assign $2\xer_ov$9[1:0]$12210 $3\xer_ov$9[1:0]$12211 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - switch \$15 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\xer_ov$9[1:0]$12211 [0] \ra [30] - assign $3\xer_ov$9[1:0]$12211 [1] \ra [19] - case - assign $3\xer_ov$9[1:0]$12211 2'00 - end - case - assign $2\xer_ov$9[1:0]$12210 2'00 - end - case - assign $1\xer_ov$9[1:0]$12209 2'00 - end - sync always - update \xer_ov$9 $0\xer_ov$9[1:0]$12208 - end - attribute \src "issuer_ls180.v:173221.3-173241.6" - process $proc$issuer_ls180.v:173221$12212 - assign { } { } - assign { } { } - assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "issuer_ls180.v:173222.5-173222.29" - switch \initial - attribute \src "issuer_ls180.v:173222.9-173222.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110001 - assign { } { } - assign $1\xer_ov_ok[0:0] $2\xer_ov_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign { } { } - assign $2\xer_ov_ok[0:0] $3\xer_ov_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - switch \$17 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\xer_ov_ok[0:0] 1'1 - case - assign $3\xer_ov_ok[0:0] 1'0 - end - case - assign $2\xer_ov_ok[0:0] 1'0 - end - case - assign $1\xer_ov_ok[0:0] 1'0 - end - sync always - update \xer_ov_ok $0\xer_ov_ok[0:0] - end - attribute \src "issuer_ls180.v:173242.3-173265.6" - process $proc$issuer_ls180.v:173242$12213 - assign { } { } - assign { } { } - assign $0\xer_ca$10[1:0]$12214 $1\xer_ca$10[1:0]$12215 - attribute \src "issuer_ls180.v:173243.5-173243.29" - switch \initial - attribute \src "issuer_ls180.v:173243.9-173243.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110001 - assign { } { } - assign $1\xer_ca$10[1:0]$12215 $2\xer_ca$10[1:0]$12216 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign { } { } - assign $2\xer_ca$10[1:0]$12216 $3\xer_ca$10[1:0]$12217 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - switch \$19 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\xer_ca$10[1:0]$12217 [0] \ra [29] - assign $3\xer_ca$10[1:0]$12217 [1] \ra [18] - case - assign $3\xer_ca$10[1:0]$12217 2'00 - end - case - assign $2\xer_ca$10[1:0]$12216 2'00 - end - case - assign $1\xer_ca$10[1:0]$12215 2'00 - end - sync always - update \xer_ca$10 $0\xer_ca$10[1:0]$12214 - end - attribute \src "issuer_ls180.v:173266.3-173286.6" - process $proc$issuer_ls180.v:173266$12218 - assign { } { } - assign { } { } - assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] - attribute \src "issuer_ls180.v:173267.5-173267.29" - switch \initial - attribute \src "issuer_ls180.v:173267.9-173267.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110001 - assign { } { } - assign $1\xer_ca_ok[0:0] $2\xer_ca_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign { } { } - assign $2\xer_ca_ok[0:0] $3\xer_ca_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - switch \$21 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\xer_ca_ok[0:0] 1'1 - case - assign $3\xer_ca_ok[0:0] 1'0 - end - case - assign $2\xer_ca_ok[0:0] 1'0 - end - case - assign $1\xer_ca_ok[0:0] 1'0 - end - sync always - update \xer_ca_ok $0\xer_ca_ok[0:0] - end - attribute \src "issuer_ls180.v:173287.3-173305.6" - process $proc$issuer_ls180.v:173287$12219 - assign { } { } - assign { } { } - assign $0\spr1$6[63:0]$12220 $1\spr1$6[63:0]$12221 - attribute \src "issuer_ls180.v:173288.5-173288.29" - switch \initial - attribute \src "issuer_ls180.v:173288.9-173288.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "issuer_ls180.v:0.0-0.0" - case 7'0110001 - assign { } { } - assign $1\spr1$6[63:0]$12221 $2\spr1$6[63:0]$12222 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign $2\spr1$6[63:0]$12222 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\spr1$6[63:0]$12222 \ra - end - case - assign $1\spr1$6[63:0]$12221 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \spr1$6 $0\spr1$6[63:0]$12220 - end - connect \$11 $eq$issuer_ls180.v:173055$12187_Y - connect \$13 $eq$issuer_ls180.v:173056$12188_Y - connect \$15 $eq$issuer_ls180.v:173057$12189_Y - connect \$17 $eq$issuer_ls180.v:173058$12190_Y - connect \$19 $eq$issuer_ls180.v:173059$12191_Y - connect \$21 $eq$issuer_ls180.v:173060$12192_Y - connect \$23 $eq$issuer_ls180.v:173061$12193_Y - connect { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } - connect \muxid$1 \muxid - connect \spr { \spr_op__insn [15:11] \spr_op__insn [20:16] } -end -attribute \src "issuer_ls180.v:173313.1-174128.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec_a.sprmap" -attribute \generator "nMigen" -module \sprmap - attribute \src "issuer_ls180.v:173440.3-173470.6" - wire width 3 $0\fast_o[2:0] - attribute \src "issuer_ls180.v:173471.3-173501.6" - wire $0\fast_o_ok[0:0] - attribute \src "issuer_ls180.v:173314.7-173314.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:173502.3-173814.6" - wire width 10 $0\spr_o[9:0] - attribute \src "issuer_ls180.v:173815.3-174127.6" - wire $0\spr_o_ok[0:0] - attribute \src "issuer_ls180.v:173440.3-173470.6" - wire width 3 $1\fast_o[2:0] - attribute \src "issuer_ls180.v:173471.3-173501.6" - wire $1\fast_o_ok[0:0] - attribute \src "issuer_ls180.v:173502.3-173814.6" - wire width 10 $1\spr_o[9:0] - attribute \src "issuer_ls180.v:173815.3-174127.6" - wire $1\spr_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 3 \fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 4 \fast_o_ok - attribute \src "issuer_ls180.v:173314.7-173314.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" - wire width 10 input 5 \spr_i - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 output 1 \spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \spr_o_ok - attribute \src "issuer_ls180.v:173314.7-173314.20" - process $proc$issuer_ls180.v:173314$12228 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:173440.3-173470.6" - process $proc$issuer_ls180.v:173440$12224 - assign { } { } - assign { } { } - assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "issuer_ls180.v:173441.5-173441.29" - switch \initial - attribute \src "issuer_ls180.v:173441.9-173441.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" - switch \spr_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000001 - assign { } { } - assign $1\fast_o[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000001000 - assign { } { } - assign $1\fast_o[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000001001 - assign { } { } - assign $1\fast_o[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010110 - assign { } { } - assign $1\fast_o[2:0] 3'110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000011010 - assign { } { } - assign $1\fast_o[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000011011 - assign { } { } - assign $1\fast_o[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100001100 - assign { } { } - assign $1\fast_o[2:0] 3'111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100101111 - assign { } { } - assign $1\fast_o[2:0] 3'010 - case - assign $1\fast_o[2:0] 3'000 - end - sync always - update \fast_o $0\fast_o[2:0] - end - attribute \src "issuer_ls180.v:173471.3-173501.6" - process $proc$issuer_ls180.v:173471$12225 - assign { } { } - assign { } { } - assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "issuer_ls180.v:173472.5-173472.29" - switch \initial - attribute \src "issuer_ls180.v:173472.9-173472.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" - switch \spr_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000001 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000001000 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000001001 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010110 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000011010 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000011011 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100001100 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100101111 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - case - assign $1\fast_o_ok[0:0] 1'0 - end - sync always - update \fast_o_ok $0\fast_o_ok[0:0] - end - attribute \src "issuer_ls180.v:173502.3-173814.6" - process $proc$issuer_ls180.v:173502$12226 - assign { } { } - assign { } { } - assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "issuer_ls180.v:173503.5-173503.29" - switch \initial - attribute \src "issuer_ls180.v:173503.9-173503.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" - switch \spr_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000011 - assign { } { } - assign $1\spr_o[9:0] 10'0000000001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000001101 - assign { } { } - assign $1\spr_o[9:0] 10'0000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010001 - assign { } { } - assign $1\spr_o[9:0] 10'0000000101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\spr_o[9:0] 10'0000000110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010011 - assign { } { } - assign $1\spr_o[9:0] 10'0000000111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000011100 - assign { } { } - assign $1\spr_o[9:0] 10'0000001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000001100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000110000 - assign { } { } - assign $1\spr_o[9:0] 10'0000001101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000111101 - assign { } { } - assign $1\spr_o[9:0] 10'0000001110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000000 - assign { } { } - assign $1\spr_o[9:0] 10'0000001111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\spr_o[9:0] 10'0000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000010 - assign { } { } - assign $1\spr_o[9:0] 10'0000010001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000011 - assign { } { } - assign $1\spr_o[9:0] 10'0000010010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010001000 - assign { } { } - assign $1\spr_o[9:0] 10'0000010011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000010100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010011000 - assign { } { } - assign $1\spr_o[9:0] 10'0000010101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010011001 - assign { } { } - assign $1\spr_o[9:0] 10'0000010110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000010111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010011110 - assign { } { } - assign $1\spr_o[9:0] 10'0000011000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010011111 - assign { } { } - assign $1\spr_o[9:0] 10'0000011001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010110000 - assign { } { } - assign $1\spr_o[9:0] 10'0000011010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010110100 - assign { } { } - assign $1\spr_o[9:0] 10'0000011011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010111010 - assign { } { } - assign $1\spr_o[9:0] 10'0000011100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010111011 - assign { } { } - assign $1\spr_o[9:0] 10'0000011101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010111100 - assign { } { } - assign $1\spr_o[9:0] 10'0000011110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010111110 - assign { } { } - assign $1\spr_o[9:0] 10'0000011111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000000 - assign { } { } - assign $1\spr_o[9:0] 10'0000100000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000011 - assign { } { } - assign $1\spr_o[9:0] 10'0000100001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100001101 - assign { } { } - assign $1\spr_o[9:0] 10'0000100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000100100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010001 - assign { } { } - assign $1\spr_o[9:0] 10'0000100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\spr_o[9:0] 10'0000100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010011 - assign { } { } - assign $1\spr_o[9:0] 10'0000100111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100011011 - assign { } { } - assign $1\spr_o[9:0] 10'0000101000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100011100 - assign { } { } - assign $1\spr_o[9:0] 10'0000101001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000101010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100011110 - assign { } { } - assign $1\spr_o[9:0] 10'0000101011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100011111 - assign { } { } - assign $1\spr_o[9:0] 10'0000101100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110000 - assign { } { } - assign $1\spr_o[9:0] 10'0000101101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110001 - assign { } { } - assign $1\spr_o[9:0] 10'0000101110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110010 - assign { } { } - assign $1\spr_o[9:0] 10'0000101111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110011 - assign { } { } - assign $1\spr_o[9:0] 10'0000110000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110100 - assign { } { } - assign $1\spr_o[9:0] 10'0000110001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110101 - assign { } { } - assign $1\spr_o[9:0] 10'0000110010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110110 - assign { } { } - assign $1\spr_o[9:0] 10'0000110011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100111001 - assign { } { } - assign $1\spr_o[9:0] 10'0000110100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100111010 - assign { } { } - assign $1\spr_o[9:0] 10'0000110101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100111011 - assign { } { } - assign $1\spr_o[9:0] 10'0000110110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100111110 - assign { } { } - assign $1\spr_o[9:0] 10'0000110111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100111111 - assign { } { } - assign $1\spr_o[9:0] 10'0000111000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0101010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000111001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0101010001 - assign { } { } - assign $1\spr_o[9:0] 10'0000111010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0101010010 - assign { } { } - assign $1\spr_o[9:0] 10'0000111011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0101010011 - assign { } { } - assign $1\spr_o[9:0] 10'0000111100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0101011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000111101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110111110 - assign { } { } - assign $1\spr_o[9:0] 10'0000111110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000111111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000000 - assign { } { } - assign $1\spr_o[9:0] 10'0001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000001 - assign { } { } - assign $1\spr_o[9:0] 10'0001000001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000010 - assign { } { } - assign $1\spr_o[9:0] 10'0001000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000011 - assign { } { } - assign $1\spr_o[9:0] 10'0001000011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000100 - assign { } { } - assign $1\spr_o[9:0] 10'0001000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000101 - assign { } { } - assign $1\spr_o[9:0] 10'0001000101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000110 - assign { } { } - assign $1\spr_o[9:0] 10'0001000110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000111 - assign { } { } - assign $1\spr_o[9:0] 10'0001000111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100001000 - assign { } { } - assign $1\spr_o[9:0] 10'0001001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100001011 - assign { } { } - assign $1\spr_o[9:0] 10'0001001001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100001100 - assign { } { } - assign $1\spr_o[9:0] 10'0001001010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100001101 - assign { } { } - assign $1\spr_o[9:0] 10'0001001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100001110 - assign { } { } - assign $1\spr_o[9:0] 10'0001001100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010000 - assign { } { } - assign $1\spr_o[9:0] 10'0001001101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010001 - assign { } { } - assign $1\spr_o[9:0] 10'0001001110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010010 - assign { } { } - assign $1\spr_o[9:0] 10'0001001111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010011 - assign { } { } - assign $1\spr_o[9:0] 10'0001010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010100 - assign { } { } - assign $1\spr_o[9:0] 10'0001010001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010101 - assign { } { } - assign $1\spr_o[9:0] 10'0001010010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010110 - assign { } { } - assign $1\spr_o[9:0] 10'0001010011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010111 - assign { } { } - assign $1\spr_o[9:0] 10'0001010100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100011000 - assign { } { } - assign $1\spr_o[9:0] 10'0001010101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100011011 - assign { } { } - assign $1\spr_o[9:0] 10'0001010110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100011100 - assign { } { } - assign $1\spr_o[9:0] 10'0001010111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100011101 - assign { } { } - assign $1\spr_o[9:0] 10'0001011000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100011110 - assign { } { } - assign $1\spr_o[9:0] 10'0001011001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100000 - assign { } { } - assign $1\spr_o[9:0] 10'0001011010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100001 - assign { } { } - assign $1\spr_o[9:0] 10'0001011011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100010 - assign { } { } - assign $1\spr_o[9:0] 10'0001011100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100011 - assign { } { } - assign $1\spr_o[9:0] 10'0001011101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100100 - assign { } { } - assign $1\spr_o[9:0] 10'0001011110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100101 - assign { } { } - assign $1\spr_o[9:0] 10'0001011111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100110 - assign { } { } - assign $1\spr_o[9:0] 10'0001100000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100101000 - assign { } { } - assign $1\spr_o[9:0] 10'0001100001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100101001 - assign { } { } - assign $1\spr_o[9:0] 10'0001100010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100101010 - assign { } { } - assign $1\spr_o[9:0] 10'0001100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100101011 - assign { } { } - assign $1\spr_o[9:0] 10'0001100100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100110000 - assign { } { } - assign $1\spr_o[9:0] 10'0001100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100110111 - assign { } { } - assign $1\spr_o[9:0] 10'0001100111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1101010000 - assign { } { } - assign $1\spr_o[9:0] 10'0001101000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1101010001 - assign { } { } - assign $1\spr_o[9:0] 10'0001101001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1101010111 - assign { } { } - assign $1\spr_o[9:0] 10'0001101010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1110000000 - assign { } { } - assign $1\spr_o[9:0] 10'0001101011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1110000010 - assign { } { } - assign $1\spr_o[9:0] 10'0001101100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1111111111 - assign { } { } - assign $1\spr_o[9:0] 10'0001101101 - case - assign $1\spr_o[9:0] 10'0000000000 - end - sync always - update \spr_o $0\spr_o[9:0] - end - attribute \src "issuer_ls180.v:173815.3-174127.6" - process $proc$issuer_ls180.v:173815$12227 - assign { } { } - assign { } { } - assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "issuer_ls180.v:173816.5-173816.29" - switch \initial - attribute \src "issuer_ls180.v:173816.9-173816.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" - switch \spr_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000001101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000011100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000111101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010001000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010011000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010011001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010011110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010011111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010110100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010111010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010111011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010111100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010111110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100001101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100011011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100011100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100011110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100011111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100111001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100111010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100111011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100111110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100111111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0101010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0101010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0101010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0101010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0101011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110111110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100001000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100001011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100001100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100001101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100001110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100011000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100011011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100011100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100011110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100101000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100101001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100101010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100101011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100110111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1101010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1101010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1101010111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1110000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1110000010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1111111111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - case - assign $1\spr_o_ok[0:0] 1'0 - end - sync always - update \spr_o_ok $0\spr_o_ok[0:0] - end -end -attribute \src "issuer_ls180.v:174132.1-174947.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec_o.sprmap" -attribute \generator "nMigen" -module \sprmap$209 - attribute \src "issuer_ls180.v:174259.3-174289.6" - wire width 3 $0\fast_o[2:0] - attribute \src "issuer_ls180.v:174290.3-174320.6" - wire $0\fast_o_ok[0:0] - attribute \src "issuer_ls180.v:174133.7-174133.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:174321.3-174633.6" - wire width 10 $0\spr_o[9:0] - attribute \src "issuer_ls180.v:174634.3-174946.6" - wire $0\spr_o_ok[0:0] - attribute \src "issuer_ls180.v:174259.3-174289.6" - wire width 3 $1\fast_o[2:0] - attribute \src "issuer_ls180.v:174290.3-174320.6" - wire $1\fast_o_ok[0:0] - attribute \src "issuer_ls180.v:174321.3-174633.6" - wire width 10 $1\spr_o[9:0] - attribute \src "issuer_ls180.v:174634.3-174946.6" - wire $1\spr_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 3 \fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 4 \fast_o_ok - attribute \src "issuer_ls180.v:174133.7-174133.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" - wire width 10 input 5 \spr_i - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 output 1 \spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \spr_o_ok - attribute \src "issuer_ls180.v:174133.7-174133.20" - process $proc$issuer_ls180.v:174133$12233 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:174259.3-174289.6" - process $proc$issuer_ls180.v:174259$12229 - assign { } { } - assign { } { } - assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "issuer_ls180.v:174260.5-174260.29" - switch \initial - attribute \src "issuer_ls180.v:174260.9-174260.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" - switch \spr_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000001 - assign { } { } - assign $1\fast_o[2:0] 3'101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000001000 - assign { } { } - assign $1\fast_o[2:0] 3'001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000001001 - assign { } { } - assign $1\fast_o[2:0] 3'000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010110 - assign { } { } - assign $1\fast_o[2:0] 3'110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000011010 - assign { } { } - assign $1\fast_o[2:0] 3'011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000011011 - assign { } { } - assign $1\fast_o[2:0] 3'100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100001100 - assign { } { } - assign $1\fast_o[2:0] 3'111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100101111 - assign { } { } - assign $1\fast_o[2:0] 3'010 - case - assign $1\fast_o[2:0] 3'000 - end - sync always - update \fast_o $0\fast_o[2:0] - end - attribute \src "issuer_ls180.v:174290.3-174320.6" - process $proc$issuer_ls180.v:174290$12230 - assign { } { } - assign { } { } - assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "issuer_ls180.v:174291.5-174291.29" - switch \initial - attribute \src "issuer_ls180.v:174291.9-174291.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" - switch \spr_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000001 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000001000 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000001001 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010110 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000011010 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000011011 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100001100 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100101111 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - case - assign $1\fast_o_ok[0:0] 1'0 - end - sync always - update \fast_o_ok $0\fast_o_ok[0:0] - end - attribute \src "issuer_ls180.v:174321.3-174633.6" - process $proc$issuer_ls180.v:174321$12231 - assign { } { } - assign { } { } - assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "issuer_ls180.v:174322.5-174322.29" - switch \initial - attribute \src "issuer_ls180.v:174322.9-174322.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" - switch \spr_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000011 - assign { } { } - assign $1\spr_o[9:0] 10'0000000001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000001101 - assign { } { } - assign $1\spr_o[9:0] 10'0000000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010001 - assign { } { } - assign $1\spr_o[9:0] 10'0000000101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\spr_o[9:0] 10'0000000110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010011 - assign { } { } - assign $1\spr_o[9:0] 10'0000000111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000011100 - assign { } { } - assign $1\spr_o[9:0] 10'0000001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000001100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000110000 - assign { } { } - assign $1\spr_o[9:0] 10'0000001101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000111101 - assign { } { } - assign $1\spr_o[9:0] 10'0000001110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000000 - assign { } { } - assign $1\spr_o[9:0] 10'0000001111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\spr_o[9:0] 10'0000010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000010 - assign { } { } - assign $1\spr_o[9:0] 10'0000010001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000011 - assign { } { } - assign $1\spr_o[9:0] 10'0000010010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010001000 - assign { } { } - assign $1\spr_o[9:0] 10'0000010011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000010100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010011000 - assign { } { } - assign $1\spr_o[9:0] 10'0000010101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010011001 - assign { } { } - assign $1\spr_o[9:0] 10'0000010110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000010111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010011110 - assign { } { } - assign $1\spr_o[9:0] 10'0000011000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010011111 - assign { } { } - assign $1\spr_o[9:0] 10'0000011001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010110000 - assign { } { } - assign $1\spr_o[9:0] 10'0000011010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010110100 - assign { } { } - assign $1\spr_o[9:0] 10'0000011011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010111010 - assign { } { } - assign $1\spr_o[9:0] 10'0000011100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010111011 - assign { } { } - assign $1\spr_o[9:0] 10'0000011101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010111100 - assign { } { } - assign $1\spr_o[9:0] 10'0000011110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010111110 - assign { } { } - assign $1\spr_o[9:0] 10'0000011111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000000 - assign { } { } - assign $1\spr_o[9:0] 10'0000100000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000011 - assign { } { } - assign $1\spr_o[9:0] 10'0000100001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100001101 - assign { } { } - assign $1\spr_o[9:0] 10'0000100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000100100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010001 - assign { } { } - assign $1\spr_o[9:0] 10'0000100101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\spr_o[9:0] 10'0000100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010011 - assign { } { } - assign $1\spr_o[9:0] 10'0000100111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100011011 - assign { } { } - assign $1\spr_o[9:0] 10'0000101000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100011100 - assign { } { } - assign $1\spr_o[9:0] 10'0000101001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000101010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100011110 - assign { } { } - assign $1\spr_o[9:0] 10'0000101011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100011111 - assign { } { } - assign $1\spr_o[9:0] 10'0000101100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110000 - assign { } { } - assign $1\spr_o[9:0] 10'0000101101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110001 - assign { } { } - assign $1\spr_o[9:0] 10'0000101110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110010 - assign { } { } - assign $1\spr_o[9:0] 10'0000101111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110011 - assign { } { } - assign $1\spr_o[9:0] 10'0000110000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110100 - assign { } { } - assign $1\spr_o[9:0] 10'0000110001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110101 - assign { } { } - assign $1\spr_o[9:0] 10'0000110010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110110 - assign { } { } - assign $1\spr_o[9:0] 10'0000110011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100111001 - assign { } { } - assign $1\spr_o[9:0] 10'0000110100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100111010 - assign { } { } - assign $1\spr_o[9:0] 10'0000110101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100111011 - assign { } { } - assign $1\spr_o[9:0] 10'0000110110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100111110 - assign { } { } - assign $1\spr_o[9:0] 10'0000110111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100111111 - assign { } { } - assign $1\spr_o[9:0] 10'0000111000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0101010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000111001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0101010001 - assign { } { } - assign $1\spr_o[9:0] 10'0000111010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0101010010 - assign { } { } - assign $1\spr_o[9:0] 10'0000111011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0101010011 - assign { } { } - assign $1\spr_o[9:0] 10'0000111100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0101011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000111101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110111110 - assign { } { } - assign $1\spr_o[9:0] 10'0000111110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000111111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000000 - assign { } { } - assign $1\spr_o[9:0] 10'0001000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000001 - assign { } { } - assign $1\spr_o[9:0] 10'0001000001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000010 - assign { } { } - assign $1\spr_o[9:0] 10'0001000010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000011 - assign { } { } - assign $1\spr_o[9:0] 10'0001000011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000100 - assign { } { } - assign $1\spr_o[9:0] 10'0001000100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000101 - assign { } { } - assign $1\spr_o[9:0] 10'0001000101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000110 - assign { } { } - assign $1\spr_o[9:0] 10'0001000110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000111 - assign { } { } - assign $1\spr_o[9:0] 10'0001000111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100001000 - assign { } { } - assign $1\spr_o[9:0] 10'0001001000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100001011 - assign { } { } - assign $1\spr_o[9:0] 10'0001001001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100001100 - assign { } { } - assign $1\spr_o[9:0] 10'0001001010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100001101 - assign { } { } - assign $1\spr_o[9:0] 10'0001001011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100001110 - assign { } { } - assign $1\spr_o[9:0] 10'0001001100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010000 - assign { } { } - assign $1\spr_o[9:0] 10'0001001101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010001 - assign { } { } - assign $1\spr_o[9:0] 10'0001001110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010010 - assign { } { } - assign $1\spr_o[9:0] 10'0001001111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010011 - assign { } { } - assign $1\spr_o[9:0] 10'0001010000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010100 - assign { } { } - assign $1\spr_o[9:0] 10'0001010001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010101 - assign { } { } - assign $1\spr_o[9:0] 10'0001010010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010110 - assign { } { } - assign $1\spr_o[9:0] 10'0001010011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010111 - assign { } { } - assign $1\spr_o[9:0] 10'0001010100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100011000 - assign { } { } - assign $1\spr_o[9:0] 10'0001010101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100011011 - assign { } { } - assign $1\spr_o[9:0] 10'0001010110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100011100 - assign { } { } - assign $1\spr_o[9:0] 10'0001010111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100011101 - assign { } { } - assign $1\spr_o[9:0] 10'0001011000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100011110 - assign { } { } - assign $1\spr_o[9:0] 10'0001011001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100000 - assign { } { } - assign $1\spr_o[9:0] 10'0001011010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100001 - assign { } { } - assign $1\spr_o[9:0] 10'0001011011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100010 - assign { } { } - assign $1\spr_o[9:0] 10'0001011100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100011 - assign { } { } - assign $1\spr_o[9:0] 10'0001011101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100100 - assign { } { } - assign $1\spr_o[9:0] 10'0001011110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100101 - assign { } { } - assign $1\spr_o[9:0] 10'0001011111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100110 - assign { } { } - assign $1\spr_o[9:0] 10'0001100000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100101000 - assign { } { } - assign $1\spr_o[9:0] 10'0001100001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100101001 - assign { } { } - assign $1\spr_o[9:0] 10'0001100010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100101010 - assign { } { } - assign $1\spr_o[9:0] 10'0001100011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100101011 - assign { } { } - assign $1\spr_o[9:0] 10'0001100100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100110000 - assign { } { } - assign $1\spr_o[9:0] 10'0001100110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100110111 - assign { } { } - assign $1\spr_o[9:0] 10'0001100111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1101010000 - assign { } { } - assign $1\spr_o[9:0] 10'0001101000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1101010001 - assign { } { } - assign $1\spr_o[9:0] 10'0001101001 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1101010111 - assign { } { } - assign $1\spr_o[9:0] 10'0001101010 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1110000000 - assign { } { } - assign $1\spr_o[9:0] 10'0001101011 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1110000010 - assign { } { } - assign $1\spr_o[9:0] 10'0001101100 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1111111111 - assign { } { } - assign $1\spr_o[9:0] 10'0001101101 - case - assign $1\spr_o[9:0] 10'0000000000 - end - sync always - update \spr_o $0\spr_o[9:0] - end - attribute \src "issuer_ls180.v:174634.3-174946.6" - process $proc$issuer_ls180.v:174634$12232 - assign { } { } - assign { } { } - assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "issuer_ls180.v:174635.5-174635.29" - switch \initial - attribute \src "issuer_ls180.v:174635.9-174635.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" - switch \spr_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000001101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000011100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0000111101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010001000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010011000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010011001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010011110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010011111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010110100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010111010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010111011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010111100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0010111110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100001101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100011011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100011100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100011110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100011111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100110110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100111001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100111010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100111011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100111110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0100111111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0101010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0101010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0101010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0101010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0101011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0110111110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'0111010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100000111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100001000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100001011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100001100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100001101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100001110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100010111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100011000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100011011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100011100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100011110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100100110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100101000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100101001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100101010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100101011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1100110111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1101010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1101010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1101010111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1110000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1110000010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 10'1111111111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - case - assign $1\spr_o_ok[0:0] 1'0 - end - sync always - update \spr_o_ok $0\spr_o_ok[0:0] - end -end -attribute \src "issuer_ls180.v:174951.1-175009.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.src_l" -attribute \generator "nMigen" -module \src_l - attribute \src "issuer_ls180.v:174952.7-174952.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:174997.3-175005.6" - wire width 4 $0\q_int$next[3:0]$12244 - attribute \src "issuer_ls180.v:174995.3-174996.27" - wire width 4 $0\q_int[3:0] - attribute \src "issuer_ls180.v:174997.3-175005.6" - wire width 4 $1\q_int$next[3:0]$12245 - attribute \src "issuer_ls180.v:174974.13-174974.25" - wire width 4 $1\q_int[3:0] - attribute \src "issuer_ls180.v:174987.17-174987.96" - wire width 4 $and$issuer_ls180.v:174987$12234_Y - attribute \src "issuer_ls180.v:174992.17-174992.96" - wire width 4 $and$issuer_ls180.v:174992$12239_Y - attribute \src "issuer_ls180.v:174989.18-174989.93" - wire width 4 $not$issuer_ls180.v:174989$12236_Y - attribute \src "issuer_ls180.v:174991.17-174991.92" - wire width 4 $not$issuer_ls180.v:174991$12238_Y - attribute \src "issuer_ls180.v:174994.17-174994.92" - wire width 4 $not$issuer_ls180.v:174994$12241_Y - attribute \src "issuer_ls180.v:174988.18-174988.98" - wire width 4 $or$issuer_ls180.v:174988$12235_Y - attribute \src "issuer_ls180.v:174990.18-174990.99" - wire width 4 $or$issuer_ls180.v:174990$12237_Y - attribute \src "issuer_ls180.v:174993.17-174993.97" - wire width 4 $or$issuer_ls180.v:174993$12240_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 4 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 4 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:174952.7-174952.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 4 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 4 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:174987$12234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:174987$12234_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:174992$12239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:174992$12239_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:174989$12236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_src - connect \Y $not$issuer_ls180.v:174989$12236_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:174991$12238 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_src - connect \Y $not$issuer_ls180.v:174991$12238_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:174994$12241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_src - connect \Y $not$issuer_ls180.v:174994$12241_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:174988$12235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$9 - connect \B \s_src - connect \Y $or$issuer_ls180.v:174988$12235_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:174990$12237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_src - connect \B \q_int - connect \Y $or$issuer_ls180.v:174990$12237_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:174993$12240 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$3 - connect \B \s_src - connect \Y $or$issuer_ls180.v:174993$12240_Y - end - attribute \src "issuer_ls180.v:174952.7-174952.20" - process $proc$issuer_ls180.v:174952$12246 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:174974.13-174974.25" - process $proc$issuer_ls180.v:174974$12247 - assign { } { } - assign $1\q_int[3:0] 4'0000 - sync always - sync init - update \q_int $1\q_int[3:0] - end - attribute \src "issuer_ls180.v:174995.3-174996.27" - process $proc$issuer_ls180.v:174995$12242 - assign { } { } - assign $0\q_int[3:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[3:0] - end - attribute \src "issuer_ls180.v:174997.3-175005.6" - process $proc$issuer_ls180.v:174997$12243 - assign { } { } - assign { } { } - assign $0\q_int$next[3:0]$12244 $1\q_int$next[3:0]$12245 - attribute \src "issuer_ls180.v:174998.5-174998.29" - switch \initial - attribute \src "issuer_ls180.v:174998.9-174998.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[3:0]$12245 4'0000 - case - assign $1\q_int$next[3:0]$12245 \$5 - end - sync always - update \q_int$next $0\q_int$next[3:0]$12244 - end - connect \$9 $and$issuer_ls180.v:174987$12234_Y - connect \$11 $or$issuer_ls180.v:174988$12235_Y - connect \$13 $not$issuer_ls180.v:174989$12236_Y - connect \$15 $or$issuer_ls180.v:174990$12237_Y - connect \$1 $not$issuer_ls180.v:174991$12238_Y - connect \$3 $and$issuer_ls180.v:174992$12239_Y - connect \$5 $or$issuer_ls180.v:174993$12240_Y - connect \$7 $not$issuer_ls180.v:174994$12241_Y - connect \qlq_src \$15 - connect \qn_src \$13 - connect \q_src \$11 -end -attribute \src "issuer_ls180.v:175013.1-175071.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.src_l" -attribute \generator "nMigen" -module \src_l$10 - attribute \src "issuer_ls180.v:175014.7-175014.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:175059.3-175067.6" - wire width 6 $0\q_int$next[5:0]$12258 - attribute \src "issuer_ls180.v:175057.3-175058.27" - wire width 6 $0\q_int[5:0] - attribute \src "issuer_ls180.v:175059.3-175067.6" - wire width 6 $1\q_int$next[5:0]$12259 - attribute \src "issuer_ls180.v:175036.13-175036.26" - wire width 6 $1\q_int[5:0] - attribute \src "issuer_ls180.v:175049.17-175049.96" - wire width 6 $and$issuer_ls180.v:175049$12248_Y - attribute \src "issuer_ls180.v:175054.17-175054.96" - wire width 6 $and$issuer_ls180.v:175054$12253_Y - attribute \src "issuer_ls180.v:175051.18-175051.93" - wire width 6 $not$issuer_ls180.v:175051$12250_Y - attribute \src "issuer_ls180.v:175053.17-175053.92" - wire width 6 $not$issuer_ls180.v:175053$12252_Y - attribute \src "issuer_ls180.v:175056.17-175056.92" - wire width 6 $not$issuer_ls180.v:175056$12255_Y - attribute \src "issuer_ls180.v:175050.18-175050.98" - wire width 6 $or$issuer_ls180.v:175050$12249_Y - attribute \src "issuer_ls180.v:175052.18-175052.99" - wire width 6 $or$issuer_ls180.v:175052$12251_Y - attribute \src "issuer_ls180.v:175055.17-175055.97" - wire width 6 $or$issuer_ls180.v:175055$12254_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 6 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 6 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:175014.7-175014.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 6 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 6 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 6 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 6 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:175049$12248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:175049$12248_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:175054$12253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:175054$12253_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:175051$12250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_src - connect \Y $not$issuer_ls180.v:175051$12250_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:175053$12252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \r_src - connect \Y $not$issuer_ls180.v:175053$12252_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:175056$12255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \r_src - connect \Y $not$issuer_ls180.v:175056$12255_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:175050$12249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \$9 - connect \B \s_src - connect \Y $or$issuer_ls180.v:175050$12249_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:175052$12251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_src - connect \B \q_int - connect \Y $or$issuer_ls180.v:175052$12251_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:175055$12254 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \$3 - connect \B \s_src - connect \Y $or$issuer_ls180.v:175055$12254_Y - end - attribute \src "issuer_ls180.v:175014.7-175014.20" - process $proc$issuer_ls180.v:175014$12260 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:175036.13-175036.26" - process $proc$issuer_ls180.v:175036$12261 - assign { } { } - assign $1\q_int[5:0] 6'000000 - sync always - sync init - update \q_int $1\q_int[5:0] - end - attribute \src "issuer_ls180.v:175057.3-175058.27" - process $proc$issuer_ls180.v:175057$12256 - assign { } { } - assign $0\q_int[5:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[5:0] - end - attribute \src "issuer_ls180.v:175059.3-175067.6" - process $proc$issuer_ls180.v:175059$12257 - assign { } { } - assign { } { } - assign $0\q_int$next[5:0]$12258 $1\q_int$next[5:0]$12259 - attribute \src "issuer_ls180.v:175060.5-175060.29" - switch \initial - attribute \src "issuer_ls180.v:175060.9-175060.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[5:0]$12259 6'000000 - case - assign $1\q_int$next[5:0]$12259 \$5 - end - sync always - update \q_int$next $0\q_int$next[5:0]$12258 - end - connect \$9 $and$issuer_ls180.v:175049$12248_Y - connect \$11 $or$issuer_ls180.v:175050$12249_Y - connect \$13 $not$issuer_ls180.v:175051$12250_Y - connect \$15 $or$issuer_ls180.v:175052$12251_Y - connect \$1 $not$issuer_ls180.v:175053$12252_Y - connect \$3 $and$issuer_ls180.v:175054$12253_Y - connect \$5 $or$issuer_ls180.v:175055$12254_Y - connect \$7 $not$issuer_ls180.v:175056$12255_Y - connect \qlq_src \$15 - connect \qn_src \$13 - connect \q_src \$11 -end -attribute \src "issuer_ls180.v:175075.1-175133.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.src_l" -attribute \generator "nMigen" -module \src_l$116 - attribute \src "issuer_ls180.v:175076.7-175076.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:175121.3-175129.6" - wire width 5 $0\q_int$next[4:0]$12272 - attribute \src "issuer_ls180.v:175119.3-175120.27" - wire width 5 $0\q_int[4:0] - attribute \src "issuer_ls180.v:175121.3-175129.6" - wire width 5 $1\q_int$next[4:0]$12273 - attribute \src "issuer_ls180.v:175098.13-175098.26" - wire width 5 $1\q_int[4:0] - attribute \src "issuer_ls180.v:175111.17-175111.96" - wire width 5 $and$issuer_ls180.v:175111$12262_Y - attribute \src "issuer_ls180.v:175116.17-175116.96" - wire width 5 $and$issuer_ls180.v:175116$12267_Y - attribute \src "issuer_ls180.v:175113.18-175113.93" - wire width 5 $not$issuer_ls180.v:175113$12264_Y - attribute \src "issuer_ls180.v:175115.17-175115.92" - wire width 5 $not$issuer_ls180.v:175115$12266_Y - attribute \src "issuer_ls180.v:175118.17-175118.92" - wire width 5 $not$issuer_ls180.v:175118$12269_Y - attribute \src "issuer_ls180.v:175112.18-175112.98" - wire width 5 $or$issuer_ls180.v:175112$12263_Y - attribute \src "issuer_ls180.v:175114.18-175114.99" - wire width 5 $or$issuer_ls180.v:175114$12265_Y - attribute \src "issuer_ls180.v:175117.17-175117.97" - wire width 5 $or$issuer_ls180.v:175117$12268_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 5 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 5 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:175076.7-175076.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 5 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 5 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 5 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 5 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 5 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:175111$12262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:175111$12262_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:175116$12267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:175116$12267_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:175113$12264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_src - connect \Y $not$issuer_ls180.v:175113$12264_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:175115$12266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \r_src - connect \Y $not$issuer_ls180.v:175115$12266_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:175118$12269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \r_src - connect \Y $not$issuer_ls180.v:175118$12269_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:175112$12263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$9 - connect \B \s_src - connect \Y $or$issuer_ls180.v:175112$12263_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:175114$12265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_src - connect \B \q_int - connect \Y $or$issuer_ls180.v:175114$12265_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:175117$12268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$3 - connect \B \s_src - connect \Y $or$issuer_ls180.v:175117$12268_Y - end - attribute \src "issuer_ls180.v:175076.7-175076.20" - process $proc$issuer_ls180.v:175076$12274 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:175098.13-175098.26" - process $proc$issuer_ls180.v:175098$12275 - assign { } { } - assign $1\q_int[4:0] 5'00000 - sync always - sync init - update \q_int $1\q_int[4:0] - end - attribute \src "issuer_ls180.v:175119.3-175120.27" - process $proc$issuer_ls180.v:175119$12270 - assign { } { } - assign $0\q_int[4:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[4:0] - end - attribute \src "issuer_ls180.v:175121.3-175129.6" - process $proc$issuer_ls180.v:175121$12271 - assign { } { } - assign { } { } - assign $0\q_int$next[4:0]$12272 $1\q_int$next[4:0]$12273 - attribute \src "issuer_ls180.v:175122.5-175122.29" - switch \initial - attribute \src "issuer_ls180.v:175122.9-175122.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[4:0]$12273 5'00000 - case - assign $1\q_int$next[4:0]$12273 \$5 - end - sync always - update \q_int$next $0\q_int$next[4:0]$12272 - end - connect \$9 $and$issuer_ls180.v:175111$12262_Y - connect \$11 $or$issuer_ls180.v:175112$12263_Y - connect \$13 $not$issuer_ls180.v:175113$12264_Y - connect \$15 $or$issuer_ls180.v:175114$12265_Y - connect \$1 $not$issuer_ls180.v:175115$12266_Y - connect \$3 $and$issuer_ls180.v:175116$12267_Y - connect \$5 $or$issuer_ls180.v:175117$12268_Y - connect \$7 $not$issuer_ls180.v:175118$12269_Y - connect \qlq_src \$15 - connect \qn_src \$13 - connect \q_src \$11 -end -attribute \src "issuer_ls180.v:175137.1-175195.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.src_l" -attribute \generator "nMigen" -module \src_l$124 - attribute \src "issuer_ls180.v:175138.7-175138.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:175183.3-175191.6" - wire width 3 $0\q_int$next[2:0]$12286 - attribute \src "issuer_ls180.v:175181.3-175182.27" - wire width 3 $0\q_int[2:0] - attribute \src "issuer_ls180.v:175183.3-175191.6" - wire width 3 $1\q_int$next[2:0]$12287 - attribute \src "issuer_ls180.v:175160.13-175160.25" - wire width 3 $1\q_int[2:0] - attribute \src "issuer_ls180.v:175173.17-175173.96" - wire width 3 $and$issuer_ls180.v:175173$12276_Y - attribute \src "issuer_ls180.v:175178.17-175178.96" - wire width 3 $and$issuer_ls180.v:175178$12281_Y - attribute \src "issuer_ls180.v:175175.18-175175.93" - wire width 3 $not$issuer_ls180.v:175175$12278_Y - attribute \src "issuer_ls180.v:175177.17-175177.92" - wire width 3 $not$issuer_ls180.v:175177$12280_Y - attribute \src "issuer_ls180.v:175180.17-175180.92" - wire width 3 $not$issuer_ls180.v:175180$12283_Y - attribute \src "issuer_ls180.v:175174.18-175174.98" - wire width 3 $or$issuer_ls180.v:175174$12277_Y - attribute \src "issuer_ls180.v:175176.18-175176.99" - wire width 3 $or$issuer_ls180.v:175176$12279_Y - attribute \src "issuer_ls180.v:175179.17-175179.97" - wire width 3 $or$issuer_ls180.v:175179$12282_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:175138.7-175138.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:175173$12276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:175173$12276_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:175178$12281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:175178$12281_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:175175$12278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \Y $not$issuer_ls180.v:175175$12278_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:175177$12280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $not$issuer_ls180.v:175177$12280_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:175180$12283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $not$issuer_ls180.v:175180$12283_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:175174$12277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$9 - connect \B \s_src - connect \Y $or$issuer_ls180.v:175174$12277_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:175176$12279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \B \q_int - connect \Y $or$issuer_ls180.v:175176$12279_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:175179$12282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$3 - connect \B \s_src - connect \Y $or$issuer_ls180.v:175179$12282_Y - end - attribute \src "issuer_ls180.v:175138.7-175138.20" - process $proc$issuer_ls180.v:175138$12288 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:175160.13-175160.25" - process $proc$issuer_ls180.v:175160$12289 - assign { } { } - assign $1\q_int[2:0] 3'000 - sync always - sync init - update \q_int $1\q_int[2:0] - end - attribute \src "issuer_ls180.v:175181.3-175182.27" - process $proc$issuer_ls180.v:175181$12284 - assign { } { } - assign $0\q_int[2:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[2:0] - end - attribute \src "issuer_ls180.v:175183.3-175191.6" - process $proc$issuer_ls180.v:175183$12285 - assign { } { } - assign { } { } - assign $0\q_int$next[2:0]$12286 $1\q_int$next[2:0]$12287 - attribute \src "issuer_ls180.v:175184.5-175184.29" - switch \initial - attribute \src "issuer_ls180.v:175184.9-175184.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[2:0]$12287 3'000 - case - assign $1\q_int$next[2:0]$12287 \$5 - end - sync always - update \q_int$next $0\q_int$next[2:0]$12286 - end - connect \$9 $and$issuer_ls180.v:175173$12276_Y - connect \$11 $or$issuer_ls180.v:175174$12277_Y - connect \$13 $not$issuer_ls180.v:175175$12278_Y - connect \$15 $or$issuer_ls180.v:175176$12279_Y - connect \$1 $not$issuer_ls180.v:175177$12280_Y - connect \$3 $and$issuer_ls180.v:175178$12281_Y - connect \$5 $or$issuer_ls180.v:175179$12282_Y - connect \$7 $not$issuer_ls180.v:175180$12283_Y - connect \qlq_src \$15 - connect \qn_src \$13 - connect \q_src \$11 -end -attribute \src "issuer_ls180.v:175199.1-175257.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.src_l" -attribute \generator "nMigen" -module \src_l$23 - attribute \src "issuer_ls180.v:175200.7-175200.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:175245.3-175253.6" - wire width 3 $0\q_int$next[2:0]$12300 - attribute \src "issuer_ls180.v:175243.3-175244.27" - wire width 3 $0\q_int[2:0] - attribute \src "issuer_ls180.v:175245.3-175253.6" - wire width 3 $1\q_int$next[2:0]$12301 - attribute \src "issuer_ls180.v:175222.13-175222.25" - wire width 3 $1\q_int[2:0] - attribute \src "issuer_ls180.v:175235.17-175235.96" - wire width 3 $and$issuer_ls180.v:175235$12290_Y - attribute \src "issuer_ls180.v:175240.17-175240.96" - wire width 3 $and$issuer_ls180.v:175240$12295_Y - attribute \src "issuer_ls180.v:175237.18-175237.93" - wire width 3 $not$issuer_ls180.v:175237$12292_Y - attribute \src "issuer_ls180.v:175239.17-175239.92" - wire width 3 $not$issuer_ls180.v:175239$12294_Y - attribute \src "issuer_ls180.v:175242.17-175242.92" - wire width 3 $not$issuer_ls180.v:175242$12297_Y - attribute \src "issuer_ls180.v:175236.18-175236.98" - wire width 3 $or$issuer_ls180.v:175236$12291_Y - attribute \src "issuer_ls180.v:175238.18-175238.99" - wire width 3 $or$issuer_ls180.v:175238$12293_Y - attribute \src "issuer_ls180.v:175241.17-175241.97" - wire width 3 $or$issuer_ls180.v:175241$12296_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:175200.7-175200.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:175235$12290 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:175235$12290_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:175240$12295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:175240$12295_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:175237$12292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \Y $not$issuer_ls180.v:175237$12292_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:175239$12294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $not$issuer_ls180.v:175239$12294_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:175242$12297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $not$issuer_ls180.v:175242$12297_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:175236$12291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$9 - connect \B \s_src - connect \Y $or$issuer_ls180.v:175236$12291_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:175238$12293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \B \q_int - connect \Y $or$issuer_ls180.v:175238$12293_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:175241$12296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$3 - connect \B \s_src - connect \Y $or$issuer_ls180.v:175241$12296_Y - end - attribute \src "issuer_ls180.v:175200.7-175200.20" - process $proc$issuer_ls180.v:175200$12302 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:175222.13-175222.25" - process $proc$issuer_ls180.v:175222$12303 - assign { } { } - assign $1\q_int[2:0] 3'000 - sync always - sync init - update \q_int $1\q_int[2:0] - end - attribute \src "issuer_ls180.v:175243.3-175244.27" - process $proc$issuer_ls180.v:175243$12298 - assign { } { } - assign $0\q_int[2:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[2:0] - end - attribute \src "issuer_ls180.v:175245.3-175253.6" - process $proc$issuer_ls180.v:175245$12299 - assign { } { } - assign { } { } - assign $0\q_int$next[2:0]$12300 $1\q_int$next[2:0]$12301 - attribute \src "issuer_ls180.v:175246.5-175246.29" - switch \initial - attribute \src "issuer_ls180.v:175246.9-175246.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[2:0]$12301 3'000 - case - assign $1\q_int$next[2:0]$12301 \$5 - end - sync always - update \q_int$next $0\q_int$next[2:0]$12300 - end - connect \$9 $and$issuer_ls180.v:175235$12290_Y - connect \$11 $or$issuer_ls180.v:175236$12291_Y - connect \$13 $not$issuer_ls180.v:175237$12292_Y - connect \$15 $or$issuer_ls180.v:175238$12293_Y - connect \$1 $not$issuer_ls180.v:175239$12294_Y - connect \$3 $and$issuer_ls180.v:175240$12295_Y - connect \$5 $or$issuer_ls180.v:175241$12296_Y - connect \$7 $not$issuer_ls180.v:175242$12297_Y - connect \qlq_src \$15 - connect \qn_src \$13 - connect \q_src \$11 -end -attribute \src "issuer_ls180.v:175261.1-175319.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.src_l" -attribute \generator "nMigen" -module \src_l$36 - attribute \src "issuer_ls180.v:175262.7-175262.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:175307.3-175315.6" - wire width 4 $0\q_int$next[3:0]$12314 - attribute \src "issuer_ls180.v:175305.3-175306.27" - wire width 4 $0\q_int[3:0] - attribute \src "issuer_ls180.v:175307.3-175315.6" - wire width 4 $1\q_int$next[3:0]$12315 - attribute \src "issuer_ls180.v:175284.13-175284.25" - wire width 4 $1\q_int[3:0] - attribute \src "issuer_ls180.v:175297.17-175297.96" - wire width 4 $and$issuer_ls180.v:175297$12304_Y - attribute \src "issuer_ls180.v:175302.17-175302.96" - wire width 4 $and$issuer_ls180.v:175302$12309_Y - attribute \src "issuer_ls180.v:175299.18-175299.93" - wire width 4 $not$issuer_ls180.v:175299$12306_Y - attribute \src "issuer_ls180.v:175301.17-175301.92" - wire width 4 $not$issuer_ls180.v:175301$12308_Y - attribute \src "issuer_ls180.v:175304.17-175304.92" - wire width 4 $not$issuer_ls180.v:175304$12311_Y - attribute \src "issuer_ls180.v:175298.18-175298.98" - wire width 4 $or$issuer_ls180.v:175298$12305_Y - attribute \src "issuer_ls180.v:175300.18-175300.99" - wire width 4 $or$issuer_ls180.v:175300$12307_Y - attribute \src "issuer_ls180.v:175303.17-175303.97" - wire width 4 $or$issuer_ls180.v:175303$12310_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 4 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 4 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:175262.7-175262.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 4 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 4 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:175297$12304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:175297$12304_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:175302$12309 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:175302$12309_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:175299$12306 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_src - connect \Y $not$issuer_ls180.v:175299$12306_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:175301$12308 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_src - connect \Y $not$issuer_ls180.v:175301$12308_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:175304$12311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_src - connect \Y $not$issuer_ls180.v:175304$12311_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:175298$12305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$9 - connect \B \s_src - connect \Y $or$issuer_ls180.v:175298$12305_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:175300$12307 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_src - connect \B \q_int - connect \Y $or$issuer_ls180.v:175300$12307_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:175303$12310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$3 - connect \B \s_src - connect \Y $or$issuer_ls180.v:175303$12310_Y - end - attribute \src "issuer_ls180.v:175262.7-175262.20" - process $proc$issuer_ls180.v:175262$12316 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:175284.13-175284.25" - process $proc$issuer_ls180.v:175284$12317 - assign { } { } - assign $1\q_int[3:0] 4'0000 - sync always - sync init - update \q_int $1\q_int[3:0] - end - attribute \src "issuer_ls180.v:175305.3-175306.27" - process $proc$issuer_ls180.v:175305$12312 - assign { } { } - assign $0\q_int[3:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[3:0] - end - attribute \src "issuer_ls180.v:175307.3-175315.6" - process $proc$issuer_ls180.v:175307$12313 - assign { } { } - assign { } { } - assign $0\q_int$next[3:0]$12314 $1\q_int$next[3:0]$12315 - attribute \src "issuer_ls180.v:175308.5-175308.29" - switch \initial - attribute \src "issuer_ls180.v:175308.9-175308.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[3:0]$12315 4'0000 - case - assign $1\q_int$next[3:0]$12315 \$5 - end - sync always - update \q_int$next $0\q_int$next[3:0]$12314 - end - connect \$9 $and$issuer_ls180.v:175297$12304_Y - connect \$11 $or$issuer_ls180.v:175298$12305_Y - connect \$13 $not$issuer_ls180.v:175299$12306_Y - connect \$15 $or$issuer_ls180.v:175300$12307_Y - connect \$1 $not$issuer_ls180.v:175301$12308_Y - connect \$3 $and$issuer_ls180.v:175302$12309_Y - connect \$5 $or$issuer_ls180.v:175303$12310_Y - connect \$7 $not$issuer_ls180.v:175304$12311_Y - connect \qlq_src \$15 - connect \qn_src \$13 - connect \q_src \$11 -end -attribute \src "issuer_ls180.v:175323.1-175381.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.src_l" -attribute \generator "nMigen" -module \src_l$52 - attribute \src "issuer_ls180.v:175324.7-175324.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:175369.3-175377.6" - wire width 3 $0\q_int$next[2:0]$12328 - attribute \src "issuer_ls180.v:175367.3-175368.27" - wire width 3 $0\q_int[2:0] - attribute \src "issuer_ls180.v:175369.3-175377.6" - wire width 3 $1\q_int$next[2:0]$12329 - attribute \src "issuer_ls180.v:175346.13-175346.25" - wire width 3 $1\q_int[2:0] - attribute \src "issuer_ls180.v:175359.17-175359.96" - wire width 3 $and$issuer_ls180.v:175359$12318_Y - attribute \src "issuer_ls180.v:175364.17-175364.96" - wire width 3 $and$issuer_ls180.v:175364$12323_Y - attribute \src "issuer_ls180.v:175361.18-175361.93" - wire width 3 $not$issuer_ls180.v:175361$12320_Y - attribute \src "issuer_ls180.v:175363.17-175363.92" - wire width 3 $not$issuer_ls180.v:175363$12322_Y - attribute \src "issuer_ls180.v:175366.17-175366.92" - wire width 3 $not$issuer_ls180.v:175366$12325_Y - attribute \src "issuer_ls180.v:175360.18-175360.98" - wire width 3 $or$issuer_ls180.v:175360$12319_Y - attribute \src "issuer_ls180.v:175362.18-175362.99" - wire width 3 $or$issuer_ls180.v:175362$12321_Y - attribute \src "issuer_ls180.v:175365.17-175365.97" - wire width 3 $or$issuer_ls180.v:175365$12324_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:175324.7-175324.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:175359$12318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:175359$12318_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:175364$12323 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:175364$12323_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:175361$12320 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \Y $not$issuer_ls180.v:175361$12320_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:175363$12322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $not$issuer_ls180.v:175363$12322_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:175366$12325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $not$issuer_ls180.v:175366$12325_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:175360$12319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$9 - connect \B \s_src - connect \Y $or$issuer_ls180.v:175360$12319_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:175362$12321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \B \q_int - connect \Y $or$issuer_ls180.v:175362$12321_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:175365$12324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$3 - connect \B \s_src - connect \Y $or$issuer_ls180.v:175365$12324_Y - end - attribute \src "issuer_ls180.v:175324.7-175324.20" - process $proc$issuer_ls180.v:175324$12330 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:175346.13-175346.25" - process $proc$issuer_ls180.v:175346$12331 - assign { } { } - assign $1\q_int[2:0] 3'000 - sync always - sync init - update \q_int $1\q_int[2:0] - end - attribute \src "issuer_ls180.v:175367.3-175368.27" - process $proc$issuer_ls180.v:175367$12326 - assign { } { } - assign $0\q_int[2:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[2:0] - end - attribute \src "issuer_ls180.v:175369.3-175377.6" - process $proc$issuer_ls180.v:175369$12327 - assign { } { } - assign { } { } - assign $0\q_int$next[2:0]$12328 $1\q_int$next[2:0]$12329 - attribute \src "issuer_ls180.v:175370.5-175370.29" - switch \initial - attribute \src "issuer_ls180.v:175370.9-175370.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[2:0]$12329 3'000 - case - assign $1\q_int$next[2:0]$12329 \$5 - end - sync always - update \q_int$next $0\q_int$next[2:0]$12328 - end - connect \$9 $and$issuer_ls180.v:175359$12318_Y - connect \$11 $or$issuer_ls180.v:175360$12319_Y - connect \$13 $not$issuer_ls180.v:175361$12320_Y - connect \$15 $or$issuer_ls180.v:175362$12321_Y - connect \$1 $not$issuer_ls180.v:175363$12322_Y - connect \$3 $and$issuer_ls180.v:175364$12323_Y - connect \$5 $or$issuer_ls180.v:175365$12324_Y - connect \$7 $not$issuer_ls180.v:175366$12325_Y - connect \qlq_src \$15 - connect \qn_src \$13 - connect \q_src \$11 -end -attribute \src "issuer_ls180.v:175385.1-175443.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.src_l" -attribute \generator "nMigen" -module \src_l$64 - attribute \src "issuer_ls180.v:175386.7-175386.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:175431.3-175439.6" - wire width 6 $0\q_int$next[5:0]$12342 - attribute \src "issuer_ls180.v:175429.3-175430.27" - wire width 6 $0\q_int[5:0] - attribute \src "issuer_ls180.v:175431.3-175439.6" - wire width 6 $1\q_int$next[5:0]$12343 - attribute \src "issuer_ls180.v:175408.13-175408.26" - wire width 6 $1\q_int[5:0] - attribute \src "issuer_ls180.v:175421.17-175421.96" - wire width 6 $and$issuer_ls180.v:175421$12332_Y - attribute \src "issuer_ls180.v:175426.17-175426.96" - wire width 6 $and$issuer_ls180.v:175426$12337_Y - attribute \src "issuer_ls180.v:175423.18-175423.93" - wire width 6 $not$issuer_ls180.v:175423$12334_Y - attribute \src "issuer_ls180.v:175425.17-175425.92" - wire width 6 $not$issuer_ls180.v:175425$12336_Y - attribute \src "issuer_ls180.v:175428.17-175428.92" - wire width 6 $not$issuer_ls180.v:175428$12339_Y - attribute \src "issuer_ls180.v:175422.18-175422.98" - wire width 6 $or$issuer_ls180.v:175422$12333_Y - attribute \src "issuer_ls180.v:175424.18-175424.99" - wire width 6 $or$issuer_ls180.v:175424$12335_Y - attribute \src "issuer_ls180.v:175427.17-175427.97" - wire width 6 $or$issuer_ls180.v:175427$12338_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 6 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 6 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:175386.7-175386.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 6 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 6 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 6 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 6 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:175421$12332 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:175421$12332_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:175426$12337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:175426$12337_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:175423$12334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_src - connect \Y $not$issuer_ls180.v:175423$12334_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:175425$12336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \r_src - connect \Y $not$issuer_ls180.v:175425$12336_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:175428$12339 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \r_src - connect \Y $not$issuer_ls180.v:175428$12339_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:175422$12333 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \$9 - connect \B \s_src - connect \Y $or$issuer_ls180.v:175422$12333_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:175424$12335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_src - connect \B \q_int - connect \Y $or$issuer_ls180.v:175424$12335_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:175427$12338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \$3 - connect \B \s_src - connect \Y $or$issuer_ls180.v:175427$12338_Y - end - attribute \src "issuer_ls180.v:175386.7-175386.20" - process $proc$issuer_ls180.v:175386$12344 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:175408.13-175408.26" - process $proc$issuer_ls180.v:175408$12345 - assign { } { } - assign $1\q_int[5:0] 6'000000 - sync always - sync init - update \q_int $1\q_int[5:0] - end - attribute \src "issuer_ls180.v:175429.3-175430.27" - process $proc$issuer_ls180.v:175429$12340 - assign { } { } - assign $0\q_int[5:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[5:0] - end - attribute \src "issuer_ls180.v:175431.3-175439.6" - process $proc$issuer_ls180.v:175431$12341 - assign { } { } - assign { } { } - assign $0\q_int$next[5:0]$12342 $1\q_int$next[5:0]$12343 - attribute \src "issuer_ls180.v:175432.5-175432.29" - switch \initial - attribute \src "issuer_ls180.v:175432.9-175432.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[5:0]$12343 6'000000 - case - assign $1\q_int$next[5:0]$12343 \$5 - end - sync always - update \q_int$next $0\q_int$next[5:0]$12342 - end - connect \$9 $and$issuer_ls180.v:175421$12332_Y - connect \$11 $or$issuer_ls180.v:175422$12333_Y - connect \$13 $not$issuer_ls180.v:175423$12334_Y - connect \$15 $or$issuer_ls180.v:175424$12335_Y - connect \$1 $not$issuer_ls180.v:175425$12336_Y - connect \$3 $and$issuer_ls180.v:175426$12337_Y - connect \$5 $or$issuer_ls180.v:175427$12338_Y - connect \$7 $not$issuer_ls180.v:175428$12339_Y - connect \qlq_src \$15 - connect \qn_src \$13 - connect \q_src \$11 -end -attribute \src "issuer_ls180.v:175447.1-175505.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.src_l" -attribute \generator "nMigen" -module \src_l$81 - attribute \src "issuer_ls180.v:175448.7-175448.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:175493.3-175501.6" - wire width 3 $0\q_int$next[2:0]$12356 - attribute \src "issuer_ls180.v:175491.3-175492.27" - wire width 3 $0\q_int[2:0] - attribute \src "issuer_ls180.v:175493.3-175501.6" - wire width 3 $1\q_int$next[2:0]$12357 - attribute \src "issuer_ls180.v:175470.13-175470.25" - wire width 3 $1\q_int[2:0] - attribute \src "issuer_ls180.v:175483.17-175483.96" - wire width 3 $and$issuer_ls180.v:175483$12346_Y - attribute \src "issuer_ls180.v:175488.17-175488.96" - wire width 3 $and$issuer_ls180.v:175488$12351_Y - attribute \src "issuer_ls180.v:175485.18-175485.93" - wire width 3 $not$issuer_ls180.v:175485$12348_Y - attribute \src "issuer_ls180.v:175487.17-175487.92" - wire width 3 $not$issuer_ls180.v:175487$12350_Y - attribute \src "issuer_ls180.v:175490.17-175490.92" - wire width 3 $not$issuer_ls180.v:175490$12353_Y - attribute \src "issuer_ls180.v:175484.18-175484.98" - wire width 3 $or$issuer_ls180.v:175484$12347_Y - attribute \src "issuer_ls180.v:175486.18-175486.99" - wire width 3 $or$issuer_ls180.v:175486$12349_Y - attribute \src "issuer_ls180.v:175489.17-175489.97" - wire width 3 $or$issuer_ls180.v:175489$12352_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:175448.7-175448.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:175483$12346 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:175483$12346_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:175488$12351 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:175488$12351_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:175485$12348 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \Y $not$issuer_ls180.v:175485$12348_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:175487$12350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $not$issuer_ls180.v:175487$12350_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:175490$12353 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $not$issuer_ls180.v:175490$12353_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:175484$12347 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$9 - connect \B \s_src - connect \Y $or$issuer_ls180.v:175484$12347_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:175486$12349 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \B \q_int - connect \Y $or$issuer_ls180.v:175486$12349_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:175489$12352 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$3 - connect \B \s_src - connect \Y $or$issuer_ls180.v:175489$12352_Y - end - attribute \src "issuer_ls180.v:175448.7-175448.20" - process $proc$issuer_ls180.v:175448$12358 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:175470.13-175470.25" - process $proc$issuer_ls180.v:175470$12359 - assign { } { } - assign $1\q_int[2:0] 3'000 - sync always - sync init - update \q_int $1\q_int[2:0] - end - attribute \src "issuer_ls180.v:175491.3-175492.27" - process $proc$issuer_ls180.v:175491$12354 - assign { } { } - assign $0\q_int[2:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[2:0] - end - attribute \src "issuer_ls180.v:175493.3-175501.6" - process $proc$issuer_ls180.v:175493$12355 - assign { } { } - assign { } { } - assign $0\q_int$next[2:0]$12356 $1\q_int$next[2:0]$12357 - attribute \src "issuer_ls180.v:175494.5-175494.29" - switch \initial - attribute \src "issuer_ls180.v:175494.9-175494.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[2:0]$12357 3'000 - case - assign $1\q_int$next[2:0]$12357 \$5 - end - sync always - update \q_int$next $0\q_int$next[2:0]$12356 - end - connect \$9 $and$issuer_ls180.v:175483$12346_Y - connect \$11 $or$issuer_ls180.v:175484$12347_Y - connect \$13 $not$issuer_ls180.v:175485$12348_Y - connect \$15 $or$issuer_ls180.v:175486$12349_Y - connect \$1 $not$issuer_ls180.v:175487$12350_Y - connect \$3 $and$issuer_ls180.v:175488$12351_Y - connect \$5 $or$issuer_ls180.v:175489$12352_Y - connect \$7 $not$issuer_ls180.v:175490$12353_Y - connect \qlq_src \$15 - connect \qn_src \$13 - connect \q_src \$11 -end -attribute \src "issuer_ls180.v:175509.1-175567.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.src_l" -attribute \generator "nMigen" -module \src_l$98 - attribute \src "issuer_ls180.v:175510.7-175510.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:175555.3-175563.6" - wire width 3 $0\q_int$next[2:0]$12370 - attribute \src "issuer_ls180.v:175553.3-175554.27" - wire width 3 $0\q_int[2:0] - attribute \src "issuer_ls180.v:175555.3-175563.6" - wire width 3 $1\q_int$next[2:0]$12371 - attribute \src "issuer_ls180.v:175532.13-175532.25" - wire width 3 $1\q_int[2:0] - attribute \src "issuer_ls180.v:175545.17-175545.96" - wire width 3 $and$issuer_ls180.v:175545$12360_Y - attribute \src "issuer_ls180.v:175550.17-175550.96" - wire width 3 $and$issuer_ls180.v:175550$12365_Y - attribute \src "issuer_ls180.v:175547.18-175547.93" - wire width 3 $not$issuer_ls180.v:175547$12362_Y - attribute \src "issuer_ls180.v:175549.17-175549.92" - wire width 3 $not$issuer_ls180.v:175549$12364_Y - attribute \src "issuer_ls180.v:175552.17-175552.92" - wire width 3 $not$issuer_ls180.v:175552$12367_Y - attribute \src "issuer_ls180.v:175546.18-175546.98" - wire width 3 $or$issuer_ls180.v:175546$12361_Y - attribute \src "issuer_ls180.v:175548.18-175548.99" - wire width 3 $or$issuer_ls180.v:175548$12363_Y - attribute \src "issuer_ls180.v:175551.17-175551.97" - wire width 3 $or$issuer_ls180.v:175551$12366_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:175510.7-175510.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:175545$12360 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:175545$12360_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:175550$12365 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:175550$12365_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:175547$12362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \Y $not$issuer_ls180.v:175547$12362_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:175549$12364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $not$issuer_ls180.v:175549$12364_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:175552$12367 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $not$issuer_ls180.v:175552$12367_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:175546$12361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$9 - connect \B \s_src - connect \Y $or$issuer_ls180.v:175546$12361_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:175548$12363 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \B \q_int - connect \Y $or$issuer_ls180.v:175548$12363_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:175551$12366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$3 - connect \B \s_src - connect \Y $or$issuer_ls180.v:175551$12366_Y - end - attribute \src "issuer_ls180.v:175510.7-175510.20" - process $proc$issuer_ls180.v:175510$12372 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:175532.13-175532.25" - process $proc$issuer_ls180.v:175532$12373 - assign { } { } - assign $1\q_int[2:0] 3'000 - sync always - sync init - update \q_int $1\q_int[2:0] - end - attribute \src "issuer_ls180.v:175553.3-175554.27" - process $proc$issuer_ls180.v:175553$12368 - assign { } { } - assign $0\q_int[2:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[2:0] - end - attribute \src "issuer_ls180.v:175555.3-175563.6" - process $proc$issuer_ls180.v:175555$12369 - assign { } { } - assign { } { } - assign $0\q_int$next[2:0]$12370 $1\q_int$next[2:0]$12371 - attribute \src "issuer_ls180.v:175556.5-175556.29" - switch \initial - attribute \src "issuer_ls180.v:175556.9-175556.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[2:0]$12371 3'000 - case - assign $1\q_int$next[2:0]$12371 \$5 - end - sync always - update \q_int$next $0\q_int$next[2:0]$12370 - end - connect \$9 $and$issuer_ls180.v:175545$12360_Y - connect \$11 $or$issuer_ls180.v:175546$12361_Y - connect \$13 $not$issuer_ls180.v:175547$12362_Y - connect \$15 $or$issuer_ls180.v:175548$12363_Y - connect \$1 $not$issuer_ls180.v:175549$12364_Y - connect \$3 $and$issuer_ls180.v:175550$12365_Y - connect \$5 $or$issuer_ls180.v:175551$12366_Y - connect \$7 $not$issuer_ls180.v:175552$12367_Y - connect \qlq_src \$15 - connect \qn_src \$13 - connect \q_src \$11 -end -attribute \src "issuer_ls180.v:175571.1-175629.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.st_active" -attribute \generator "nMigen" -module \st_active - attribute \src "issuer_ls180.v:175572.7-175572.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:175617.3-175625.6" - wire $0\q_int$next[0:0]$12384 - attribute \src "issuer_ls180.v:175615.3-175616.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:175617.3-175625.6" - wire $1\q_int$next[0:0]$12385 - attribute \src "issuer_ls180.v:175594.7-175594.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:175607.17-175607.96" - wire $and$issuer_ls180.v:175607$12374_Y - attribute \src "issuer_ls180.v:175612.17-175612.96" - wire $and$issuer_ls180.v:175612$12379_Y - attribute \src "issuer_ls180.v:175609.18-175609.99" - wire $not$issuer_ls180.v:175609$12376_Y - attribute \src "issuer_ls180.v:175611.17-175611.98" - wire $not$issuer_ls180.v:175611$12378_Y - attribute \src "issuer_ls180.v:175614.17-175614.98" - wire $not$issuer_ls180.v:175614$12381_Y - attribute \src "issuer_ls180.v:175608.18-175608.104" - wire $or$issuer_ls180.v:175608$12375_Y - attribute \src "issuer_ls180.v:175610.18-175610.105" - wire $or$issuer_ls180.v:175610$12377_Y - attribute \src "issuer_ls180.v:175613.17-175613.103" - wire $or$issuer_ls180.v:175613$12380_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:175572.7-175572.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 2 \r_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 3 \s_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:175607$12374 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:175607$12374_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:175612$12379 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:175612$12379_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:175609$12376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_st_active - connect \Y $not$issuer_ls180.v:175609$12376_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:175611$12378 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_st_active - connect \Y $not$issuer_ls180.v:175611$12378_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:175614$12381 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_st_active - connect \Y $not$issuer_ls180.v:175614$12381_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:175608$12375 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_st_active - connect \Y $or$issuer_ls180.v:175608$12375_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:175610$12377 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_st_active - connect \B \q_int - connect \Y $or$issuer_ls180.v:175610$12377_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:175613$12380 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_st_active - connect \Y $or$issuer_ls180.v:175613$12380_Y - end - attribute \src "issuer_ls180.v:175572.7-175572.20" - process $proc$issuer_ls180.v:175572$12386 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:175594.7-175594.19" - process $proc$issuer_ls180.v:175594$12387 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:175615.3-175616.27" - process $proc$issuer_ls180.v:175615$12382 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:175617.3-175625.6" - process $proc$issuer_ls180.v:175617$12383 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$12384 $1\q_int$next[0:0]$12385 - attribute \src "issuer_ls180.v:175618.5-175618.29" - switch \initial - attribute \src "issuer_ls180.v:175618.9-175618.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$12385 1'0 - case - assign $1\q_int$next[0:0]$12385 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$12384 - end - connect \$9 $and$issuer_ls180.v:175607$12374_Y - connect \$11 $or$issuer_ls180.v:175608$12375_Y - connect \$13 $not$issuer_ls180.v:175609$12376_Y - connect \$15 $or$issuer_ls180.v:175610$12377_Y - connect \$1 $not$issuer_ls180.v:175611$12378_Y - connect \$3 $and$issuer_ls180.v:175612$12379_Y - connect \$5 $or$issuer_ls180.v:175613$12380_Y - connect \$7 $not$issuer_ls180.v:175614$12381_Y - connect \qlq_st_active \$15 - connect \qn_st_active \$13 - connect \q_st_active \$11 -end -attribute \src "issuer_ls180.v:175633.1-175691.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.st_done" -attribute \generator "nMigen" -module \st_done - attribute \src "issuer_ls180.v:175634.7-175634.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:175679.3-175687.6" - wire $0\q_int$next[0:0]$12398 - attribute \src "issuer_ls180.v:175677.3-175678.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:175679.3-175687.6" - wire $1\q_int$next[0:0]$12399 - attribute \src "issuer_ls180.v:175656.7-175656.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:175669.17-175669.96" - wire $and$issuer_ls180.v:175669$12388_Y - attribute \src "issuer_ls180.v:175674.17-175674.96" - wire $and$issuer_ls180.v:175674$12393_Y - attribute \src "issuer_ls180.v:175671.18-175671.97" - wire $not$issuer_ls180.v:175671$12390_Y - attribute \src "issuer_ls180.v:175673.17-175673.96" - wire $not$issuer_ls180.v:175673$12392_Y - attribute \src "issuer_ls180.v:175676.17-175676.96" - wire $not$issuer_ls180.v:175676$12395_Y - attribute \src "issuer_ls180.v:175670.18-175670.102" - wire $or$issuer_ls180.v:175670$12389_Y - attribute \src "issuer_ls180.v:175672.18-175672.103" - wire $or$issuer_ls180.v:175672$12391_Y - attribute \src "issuer_ls180.v:175675.17-175675.101" - wire $or$issuer_ls180.v:175675$12394_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:175634.7-175634.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:175669$12388 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:175669$12388_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:175674$12393 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:175674$12393_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:175671$12390 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_st_done - connect \Y $not$issuer_ls180.v:175671$12390_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:175673$12392 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_st_done - connect \Y $not$issuer_ls180.v:175673$12392_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:175676$12395 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_st_done - connect \Y $not$issuer_ls180.v:175676$12395_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:175670$12389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_st_done - connect \Y $or$issuer_ls180.v:175670$12389_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:175672$12391 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_st_done - connect \B \q_int - connect \Y $or$issuer_ls180.v:175672$12391_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:175675$12394 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_st_done - connect \Y $or$issuer_ls180.v:175675$12394_Y - end - attribute \src "issuer_ls180.v:175634.7-175634.20" - process $proc$issuer_ls180.v:175634$12400 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:175656.7-175656.19" - process $proc$issuer_ls180.v:175656$12401 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:175677.3-175678.27" - process $proc$issuer_ls180.v:175677$12396 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:175679.3-175687.6" - process $proc$issuer_ls180.v:175679$12397 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$12398 $1\q_int$next[0:0]$12399 - attribute \src "issuer_ls180.v:175680.5-175680.29" - switch \initial - attribute \src "issuer_ls180.v:175680.9-175680.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$12399 1'0 - case - assign $1\q_int$next[0:0]$12399 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$12398 - end - connect \$9 $and$issuer_ls180.v:175669$12388_Y - connect \$11 $or$issuer_ls180.v:175670$12389_Y - connect \$13 $not$issuer_ls180.v:175671$12390_Y - connect \$15 $or$issuer_ls180.v:175672$12391_Y - connect \$1 $not$issuer_ls180.v:175673$12392_Y - connect \$3 $and$issuer_ls180.v:175674$12393_Y - connect \$5 $or$issuer_ls180.v:175675$12394_Y - connect \$7 $not$issuer_ls180.v:175676$12395_Y - connect \qlq_st_done \$15 - connect \qn_st_done \$13 - connect \q_st_done \$11 -end -attribute \src "issuer_ls180.v:175695.1-175950.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.state" -attribute \generator "nMigen" -module \state - attribute \src "issuer_ls180.v:175923.3-175932.6" - wire width 64 $0\cia__data_o[63:0] - attribute \src "issuer_ls180.v:175696.7-175696.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:175904.3-175913.6" - wire width 64 $0\msr__data_o[63:0] - attribute \src "issuer_ls180.v:175895.3-175903.6" - wire width 4 $0\ren_delay$12$next[3:0]$12414 - attribute \src "issuer_ls180.v:175835.3-175836.43" - wire width 4 $0\ren_delay$12[3:0]$12411 - attribute \src "issuer_ls180.v:175816.13-175816.34" - wire width 4 $0\ren_delay$12[3:0]$12424 - attribute \src "issuer_ls180.v:175914.3-175922.6" - wire width 4 $0\ren_delay$next[3:0]$12418 - attribute \src "issuer_ls180.v:175837.3-175838.35" - wire width 4 $0\ren_delay[3:0] - attribute \src "issuer_ls180.v:175923.3-175932.6" - wire width 64 $1\cia__data_o[63:0] - attribute \src "issuer_ls180.v:175904.3-175913.6" - wire width 64 $1\msr__data_o[63:0] - attribute \src "issuer_ls180.v:175895.3-175903.6" - wire width 4 $1\ren_delay$12$next[3:0]$12415 - attribute \src "issuer_ls180.v:175914.3-175922.6" - wire width 4 $1\ren_delay$next[3:0]$12419 - attribute \src "issuer_ls180.v:175814.13-175814.29" - wire width 4 $1\ren_delay[3:0] - attribute \src "issuer_ls180.v:175827.18-175827.95" - wire width 64 $or$issuer_ls180.v:175827$12402_Y - attribute \src "issuer_ls180.v:175829.18-175829.124" - wire width 64 $or$issuer_ls180.v:175829$12404_Y - attribute \src "issuer_ls180.v:175830.18-175830.124" - wire width 64 $or$issuer_ls180.v:175830$12405_Y - attribute \src "issuer_ls180.v:175831.18-175831.97" - wire width 64 $or$issuer_ls180.v:175831$12406_Y - attribute \src "issuer_ls180.v:175833.17-175833.123" - wire width 64 $or$issuer_ls180.v:175833$12408_Y - attribute \src "issuer_ls180.v:175834.17-175834.123" - wire width 64 $or$issuer_ls180.v:175834$12409_Y - attribute \src "issuer_ls180.v:175828.18-175828.100" - wire $reduce_or$issuer_ls180.v:175828$12403_Y - attribute \src "issuer_ls180.v:175832.17-175832.95" - wire $reduce_or$issuer_ls180.v:175832$12407_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 \$10 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 \$17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 \$19 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 \$6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 2 \cia__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 1 \cia__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 12 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 11 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 4 \data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 8 \data_i$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 9 \data_i$2 - attribute \src "issuer_ls180.v:175696.7-175696.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 6 \msr__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 5 \msr__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_0_cia0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_0_cia0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_0_d_wr10__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_0_d_wr10__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_0_msr0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_0_msr0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_0_msr0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_0_msr0__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_0_nia0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_0_nia0__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_1_cia1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_1_cia1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_1_d_wr11__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_1_d_wr11__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_1_msr1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_1_msr1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_1_msr1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_1_msr1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_1_nia1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_1_nia1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_2_cia2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_2_cia2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_2_d_wr12__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_2_d_wr12__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_2_msr2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_2_msr2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_2_msr2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_2_msr2__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_2_nia2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_2_nia2__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_3_cia3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_3_cia3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_3_d_wr13__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_3_d_wr13__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_3_msr3__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_3_msr3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_3_msr3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_3_msr3__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_3_nia3__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_3_nia3__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 4 \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 4 \ren_delay$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 4 \ren_delay$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 4 \ren_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 7 \state_nia_wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 3 \wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 10 \wen$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:175827$12402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \$6 - connect \B \$8 - connect \Y $or$issuer_ls180.v:175827$12402_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:175829$12404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \reg_0_msr0__data_o - connect \B \reg_1_msr1__data_o - connect \Y $or$issuer_ls180.v:175829$12404_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:175830$12405 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \reg_2_msr2__data_o - connect \B \reg_3_msr3__data_o - connect \Y $or$issuer_ls180.v:175830$12405_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:175831$12406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \$15 - connect \B \$17 - connect \Y $or$issuer_ls180.v:175831$12406_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:175833$12408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \reg_0_cia0__data_o - connect \B \reg_1_cia1__data_o - connect \Y $or$issuer_ls180.v:175833$12408_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:175834$12409 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \reg_2_cia2__data_o - connect \B \reg_3_cia3__data_o - connect \Y $or$issuer_ls180.v:175834$12409_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$issuer_ls180.v:175828$12403 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \ren_delay$12 - connect \Y $reduce_or$issuer_ls180.v:175828$12403_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$issuer_ls180.v:175832$12407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \ren_delay - connect \Y $reduce_or$issuer_ls180.v:175832$12407_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:175839.15-175852.4" - cell \reg_0$132 \reg_0 - connect \cia0__data_o \reg_0_cia0__data_o - connect \cia0__ren \reg_0_cia0__ren - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \d_wr10__data_i \reg_0_d_wr10__data_i - connect \d_wr10__wen \reg_0_d_wr10__wen - connect \msr0__data_i \reg_0_msr0__data_i - connect \msr0__data_o \reg_0_msr0__data_o - connect \msr0__ren \reg_0_msr0__ren - connect \msr0__wen \reg_0_msr0__wen - connect \nia0__data_i \reg_0_nia0__data_i - connect \nia0__wen \reg_0_nia0__wen - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:175853.15-175866.4" - cell \reg_1$133 \reg_1 - connect \cia1__data_o \reg_1_cia1__data_o - connect \cia1__ren \reg_1_cia1__ren - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \d_wr11__data_i \reg_1_d_wr11__data_i - connect \d_wr11__wen \reg_1_d_wr11__wen - connect \msr1__data_i \reg_1_msr1__data_i - connect \msr1__data_o \reg_1_msr1__data_o - connect \msr1__ren \reg_1_msr1__ren - connect \msr1__wen \reg_1_msr1__wen - connect \nia1__data_i \reg_1_nia1__data_i - connect \nia1__wen \reg_1_nia1__wen - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:175867.15-175880.4" - cell \reg_2$134 \reg_2 - connect \cia2__data_o \reg_2_cia2__data_o - connect \cia2__ren \reg_2_cia2__ren - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \d_wr12__data_i \reg_2_d_wr12__data_i - connect \d_wr12__wen \reg_2_d_wr12__wen - connect \msr2__data_i \reg_2_msr2__data_i - connect \msr2__data_o \reg_2_msr2__data_o - connect \msr2__ren \reg_2_msr2__ren - connect \msr2__wen \reg_2_msr2__wen - connect \nia2__data_i \reg_2_nia2__data_i - connect \nia2__wen \reg_2_nia2__wen - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:175881.15-175894.4" - cell \reg_3$135 \reg_3 - connect \cia3__data_o \reg_3_cia3__data_o - connect \cia3__ren \reg_3_cia3__ren - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \d_wr13__data_i \reg_3_d_wr13__data_i - connect \d_wr13__wen \reg_3_d_wr13__wen - connect \msr3__data_i \reg_3_msr3__data_i - connect \msr3__data_o \reg_3_msr3__data_o - connect \msr3__ren \reg_3_msr3__ren - connect \msr3__wen \reg_3_msr3__wen - connect \nia3__data_i \reg_3_nia3__data_i - connect \nia3__wen \reg_3_nia3__wen - end - attribute \src "issuer_ls180.v:175696.7-175696.20" - process $proc$issuer_ls180.v:175696$12421 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:175814.13-175814.29" - process $proc$issuer_ls180.v:175814$12422 - assign { } { } - assign $1\ren_delay[3:0] 4'0000 - sync always - sync init - update \ren_delay $1\ren_delay[3:0] - end - attribute \src "issuer_ls180.v:175816.13-175816.34" - process $proc$issuer_ls180.v:175816$12423 - assign { } { } - assign $0\ren_delay$12[3:0]$12424 4'0000 - sync always - sync init - update \ren_delay$12 $0\ren_delay$12[3:0]$12424 - end - attribute \src "issuer_ls180.v:175835.3-175836.43" - process $proc$issuer_ls180.v:175835$12410 - assign { } { } - assign $0\ren_delay$12[3:0]$12411 \ren_delay$12$next - sync posedge \coresync_clk - update \ren_delay$12 $0\ren_delay$12[3:0]$12411 - end - attribute \src "issuer_ls180.v:175837.3-175838.35" - process $proc$issuer_ls180.v:175837$12412 - assign { } { } - assign $0\ren_delay[3:0] \ren_delay$next - sync posedge \coresync_clk - update \ren_delay $0\ren_delay[3:0] - end - attribute \src "issuer_ls180.v:175895.3-175903.6" - process $proc$issuer_ls180.v:175895$12413 - assign { } { } - assign { } { } - assign $0\ren_delay$12$next[3:0]$12414 $1\ren_delay$12$next[3:0]$12415 - attribute \src "issuer_ls180.v:175896.5-175896.29" - switch \initial - attribute \src "issuer_ls180.v:175896.9-175896.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$12$next[3:0]$12415 4'0000 - case - assign $1\ren_delay$12$next[3:0]$12415 \msr__ren - end - sync always - update \ren_delay$12$next $0\ren_delay$12$next[3:0]$12414 - end - attribute \src "issuer_ls180.v:175904.3-175913.6" - process $proc$issuer_ls180.v:175904$12416 - assign { } { } - assign { } { } - assign $0\msr__data_o[63:0] $1\msr__data_o[63:0] - attribute \src "issuer_ls180.v:175905.5-175905.29" - switch \initial - attribute \src "issuer_ls180.v:175905.9-175905.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch \$13 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\msr__data_o[63:0] \$19 - case - assign $1\msr__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \msr__data_o $0\msr__data_o[63:0] - end - attribute \src "issuer_ls180.v:175914.3-175922.6" - process $proc$issuer_ls180.v:175914$12417 - assign { } { } - assign { } { } - assign $0\ren_delay$next[3:0]$12418 $1\ren_delay$next[3:0]$12419 - attribute \src "issuer_ls180.v:175915.5-175915.29" - switch \initial - attribute \src "issuer_ls180.v:175915.9-175915.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$next[3:0]$12419 4'0000 - case - assign $1\ren_delay$next[3:0]$12419 \cia__ren - end - sync always - update \ren_delay$next $0\ren_delay$next[3:0]$12418 - end - attribute \src "issuer_ls180.v:175923.3-175932.6" - process $proc$issuer_ls180.v:175923$12420 - assign { } { } - assign { } { } - assign $0\cia__data_o[63:0] $1\cia__data_o[63:0] - attribute \src "issuer_ls180.v:175924.5-175924.29" - switch \initial - attribute \src "issuer_ls180.v:175924.9-175924.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch \$4 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cia__data_o[63:0] \$10 - case - assign $1\cia__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \cia__data_o $0\cia__data_o[63:0] - end - connect \$10 $or$issuer_ls180.v:175827$12402_Y - connect \$13 $reduce_or$issuer_ls180.v:175828$12403_Y - connect \$15 $or$issuer_ls180.v:175829$12404_Y - connect \$17 $or$issuer_ls180.v:175830$12405_Y - connect \$19 $or$issuer_ls180.v:175831$12406_Y - connect \$4 $reduce_or$issuer_ls180.v:175832$12407_Y - connect \$6 $or$issuer_ls180.v:175833$12408_Y - connect \$8 $or$issuer_ls180.v:175834$12409_Y - connect \reg_3_d_wr13__data_i \data_i - connect \reg_2_d_wr12__data_i \data_i - connect \reg_1_d_wr11__data_i \data_i - connect \reg_0_d_wr10__data_i \data_i - connect { \reg_3_d_wr13__wen \reg_2_d_wr12__wen \reg_1_d_wr11__wen \reg_0_d_wr10__wen } \wen - connect \reg_3_msr3__data_i \data_i$2 - connect \reg_2_msr2__data_i \data_i$2 - connect \reg_1_msr1__data_i \data_i$2 - connect \reg_0_msr0__data_i \data_i$2 - connect { \reg_3_msr3__wen \reg_2_msr2__wen \reg_1_msr1__wen \reg_0_msr0__wen } \wen$3 - connect \reg_3_nia3__data_i \data_i$1 - connect \reg_2_nia2__data_i \data_i$1 - connect \reg_1_nia1__data_i \data_i$1 - connect \reg_0_nia0__data_i \data_i$1 - connect { \reg_3_nia3__wen \reg_2_nia2__wen \reg_1_nia1__wen \reg_0_nia0__wen } \state_nia_wen - connect { \reg_3_msr3__ren \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren - connect { \reg_3_cia3__ren \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren -end -attribute \src "issuer_ls180.v:175954.1-176012.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.sto_l" -attribute \generator "nMigen" -module \sto_l - attribute \src "issuer_ls180.v:175955.7-175955.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:176000.3-176008.6" - wire $0\q_int$next[0:0]$12435 - attribute \src "issuer_ls180.v:175998.3-175999.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:176000.3-176008.6" - wire $1\q_int$next[0:0]$12436 - attribute \src "issuer_ls180.v:175977.7-175977.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:175990.17-175990.96" - wire $and$issuer_ls180.v:175990$12425_Y - attribute \src "issuer_ls180.v:175995.17-175995.96" - wire $and$issuer_ls180.v:175995$12430_Y - attribute \src "issuer_ls180.v:175992.18-175992.93" - wire $not$issuer_ls180.v:175992$12427_Y - attribute \src "issuer_ls180.v:175994.17-175994.92" - wire $not$issuer_ls180.v:175994$12429_Y - attribute \src "issuer_ls180.v:175997.17-175997.92" - wire $not$issuer_ls180.v:175997$12432_Y - attribute \src "issuer_ls180.v:175991.18-175991.98" - wire $or$issuer_ls180.v:175991$12426_Y - attribute \src "issuer_ls180.v:175993.18-175993.99" - wire $or$issuer_ls180.v:175993$12428_Y - attribute \src "issuer_ls180.v:175996.17-175996.97" - wire $or$issuer_ls180.v:175996$12431_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:175955.7-175955.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:175990$12425 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:175990$12425_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:175995$12430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:175995$12430_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:175992$12427 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_sto - connect \Y $not$issuer_ls180.v:175992$12427_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:175994$12429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_sto - connect \Y $not$issuer_ls180.v:175994$12429_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:175997$12432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_sto - connect \Y $not$issuer_ls180.v:175997$12432_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:175991$12426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_sto - connect \Y $or$issuer_ls180.v:175991$12426_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:175993$12428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_sto - connect \B \q_int - connect \Y $or$issuer_ls180.v:175993$12428_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:175996$12431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_sto - connect \Y $or$issuer_ls180.v:175996$12431_Y - end - attribute \src "issuer_ls180.v:175955.7-175955.20" - process $proc$issuer_ls180.v:175955$12437 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:175977.7-175977.19" - process $proc$issuer_ls180.v:175977$12438 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:175998.3-175999.27" - process $proc$issuer_ls180.v:175998$12433 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:176000.3-176008.6" - process $proc$issuer_ls180.v:176000$12434 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$12435 $1\q_int$next[0:0]$12436 - attribute \src "issuer_ls180.v:176001.5-176001.29" - switch \initial - attribute \src "issuer_ls180.v:176001.9-176001.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$12436 1'0 - case - assign $1\q_int$next[0:0]$12436 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$12435 - end - connect \$9 $and$issuer_ls180.v:175990$12425_Y - connect \$11 $or$issuer_ls180.v:175991$12426_Y - connect \$13 $not$issuer_ls180.v:175992$12427_Y - connect \$15 $or$issuer_ls180.v:175993$12428_Y - connect \$1 $not$issuer_ls180.v:175994$12429_Y - connect \$3 $and$issuer_ls180.v:175995$12430_Y - connect \$5 $or$issuer_ls180.v:175996$12431_Y - connect \$7 $not$issuer_ls180.v:175997$12432_Y - connect \qlq_sto \$15 - connect \qn_sto \$13 - connect \q_sto \$11 -end -attribute \src "issuer_ls180.v:176017.1-178754.10" -attribute \cells_not_processed 1 -attribute \top 1 -attribute \nmigen.hierarchy "test_issuer" -attribute \generator "nMigen" -module \test_issuer - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 8 $0\core_asmcode$next[7:0]$12619 - attribute \src "issuer_ls180.v:177475.3-177476.41" - wire width 8 $0\core_asmcode[7:0] - attribute \src "issuer_ls180.v:178321.3-178357.6" - wire $0\core_bigendian_i$3$next[0:0]$12852 - attribute \src "issuer_ls180.v:177471.3-177472.55" - wire $0\core_bigendian_i$3[0:0]$12504 - attribute \src "issuer_ls180.v:176150.7-176150.34" - wire $0\core_bigendian_i$3[0:0]$12920 - attribute \src "issuer_ls180.v:178062.3-178074.6" - wire width 4 $0\core_cia__ren[3:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 64 $0\core_core_core_cia$next[63:0]$12620 - attribute \src "issuer_ls180.v:177551.3-177552.53" - wire width 64 $0\core_core_core_cia[63:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 8 $0\core_core_core_cr_rd$next[7:0]$12621 - attribute \src "issuer_ls180.v:177577.3-177578.57" - wire width 8 $0\core_core_core_cr_rd[7:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $0\core_core_core_cr_rd_ok$next[0:0]$12622 - attribute \src "issuer_ls180.v:177579.3-177580.63" - wire $0\core_core_core_cr_rd_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 8 $0\core_core_core_cr_wr$next[7:0]$12623 - attribute \src "issuer_ls180.v:177581.3-177582.57" - wire width 8 $0\core_core_core_cr_wr[7:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 12 $0\core_core_core_fn_unit$next[11:0]$12624 - attribute \src "issuer_ls180.v:177557.3-177558.61" - wire width 12 $0\core_core_core_fn_unit[11:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 2 $0\core_core_core_input_carry$next[1:0]$12625 - attribute \src "issuer_ls180.v:177571.3-177572.69" - wire width 2 $0\core_core_core_input_carry[1:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 32 $0\core_core_core_insn$next[31:0]$12626 - attribute \src "issuer_ls180.v:177553.3-177554.55" - wire width 32 $0\core_core_core_insn[31:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 7 $0\core_core_core_insn_type$next[6:0]$12627 - attribute \src "issuer_ls180.v:177555.3-177556.65" - wire width 7 $0\core_core_core_insn_type[6:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $0\core_core_core_is_32bit$next[0:0]$12628 - attribute \src "issuer_ls180.v:177585.3-177586.63" - wire $0\core_core_core_is_32bit[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 64 $0\core_core_core_msr$next[63:0]$12629 - attribute \src "issuer_ls180.v:177549.3-177550.53" - wire width 64 $0\core_core_core_msr[63:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $0\core_core_core_oe$next[0:0]$12630 - attribute \src "issuer_ls180.v:177565.3-177566.51" - wire $0\core_core_core_oe[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $0\core_core_core_oe_ok$next[0:0]$12631 - attribute \src "issuer_ls180.v:177567.3-177568.57" - wire $0\core_core_core_oe_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $0\core_core_core_rc$next[0:0]$12632 - attribute \src "issuer_ls180.v:177561.3-177562.51" - wire $0\core_core_core_rc[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $0\core_core_core_rc_ok$next[0:0]$12633 - attribute \src "issuer_ls180.v:177563.3-177564.57" - wire $0\core_core_core_rc_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 13 $0\core_core_core_trapaddr$next[12:0]$12634 - attribute \src "issuer_ls180.v:177575.3-177576.63" - wire width 13 $0\core_core_core_trapaddr[12:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 7 $0\core_core_core_traptype$next[6:0]$12635 - attribute \src "issuer_ls180.v:177573.3-177574.63" - wire width 7 $0\core_core_core_traptype[6:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $0\core_core_cr_in1$next[2:0]$12636 - attribute \src "issuer_ls180.v:177531.3-177532.49" - wire width 3 $0\core_core_cr_in1[2:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $0\core_core_cr_in1_ok$next[0:0]$12637 - attribute \src "issuer_ls180.v:177533.3-177534.55" - wire $0\core_core_cr_in1_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $0\core_core_cr_in2$1$next[2:0]$12638 - attribute \src "issuer_ls180.v:177539.3-177540.55" - wire width 3 $0\core_core_cr_in2$1[2:0]$12540 - attribute \src "issuer_ls180.v:176323.13-176323.40" - wire width 3 $0\core_core_cr_in2$1[2:0]$12941 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $0\core_core_cr_in2$next[2:0]$12639 - attribute \src "issuer_ls180.v:177535.3-177536.49" - wire width 3 $0\core_core_cr_in2[2:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $0\core_core_cr_in2_ok$2$next[0:0]$12640 - attribute \src "issuer_ls180.v:177541.3-177542.61" - wire $0\core_core_cr_in2_ok$2[0:0]$12542 - attribute \src "issuer_ls180.v:176331.7-176331.37" - wire $0\core_core_cr_in2_ok$2[0:0]$12944 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $0\core_core_cr_in2_ok$next[0:0]$12641 - attribute \src "issuer_ls180.v:177537.3-177538.55" - wire $0\core_core_cr_in2_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $0\core_core_cr_out$next[2:0]$12642 - attribute \src "issuer_ls180.v:177543.3-177544.49" - wire width 3 $0\core_core_cr_out[2:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $0\core_core_cr_wr_ok$next[0:0]$12643 - attribute \src "issuer_ls180.v:177583.3-177584.53" - wire $0\core_core_cr_wr_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 5 $0\core_core_ea$next[4:0]$12644 - attribute \src "issuer_ls180.v:177483.3-177484.41" - wire width 5 $0\core_core_ea[4:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $0\core_core_fast1$next[2:0]$12645 - attribute \src "issuer_ls180.v:177513.3-177514.47" - wire width 3 $0\core_core_fast1[2:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $0\core_core_fast1_ok$next[0:0]$12646 - attribute \src "issuer_ls180.v:177515.3-177516.53" - wire $0\core_core_fast1_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $0\core_core_fast2$next[2:0]$12647 - attribute \src "issuer_ls180.v:177517.3-177518.47" - wire width 3 $0\core_core_fast2[2:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $0\core_core_fast2_ok$next[0:0]$12648 - attribute \src "issuer_ls180.v:177519.3-177520.53" - wire $0\core_core_fast2_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $0\core_core_fasto1$next[2:0]$12649 - attribute \src "issuer_ls180.v:177521.3-177522.49" - wire width 3 $0\core_core_fasto1[2:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $0\core_core_fasto2$next[2:0]$12650 - attribute \src "issuer_ls180.v:177527.3-177528.49" - wire width 3 $0\core_core_fasto2[2:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $0\core_core_lk$next[0:0]$12651 - attribute \src "issuer_ls180.v:177559.3-177560.41" - wire $0\core_core_lk[0:0] - attribute \src "issuer_ls180.v:178599.3-178630.6" - wire width 64 $0\core_core_pc$next[63:0]$12887 - attribute \src "issuer_ls180.v:177591.3-177592.41" - wire width 64 $0\core_core_pc[63:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 5 $0\core_core_reg1$next[4:0]$12652 - attribute \src "issuer_ls180.v:177487.3-177488.45" - wire width 5 $0\core_core_reg1[4:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $0\core_core_reg1_ok$next[0:0]$12653 - attribute \src "issuer_ls180.v:177489.3-177490.51" - wire $0\core_core_reg1_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 5 $0\core_core_reg2$next[4:0]$12654 - attribute \src "issuer_ls180.v:177491.3-177492.45" - wire width 5 $0\core_core_reg2[4:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $0\core_core_reg2_ok$next[0:0]$12655 - attribute \src "issuer_ls180.v:177493.3-177494.51" - wire $0\core_core_reg2_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 5 $0\core_core_reg3$next[4:0]$12656 - attribute \src "issuer_ls180.v:177495.3-177496.45" - wire width 5 $0\core_core_reg3[4:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $0\core_core_reg3_ok$next[0:0]$12657 - attribute \src "issuer_ls180.v:177497.3-177498.51" - wire $0\core_core_reg3_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 5 $0\core_core_rego$next[4:0]$12658 - attribute \src "issuer_ls180.v:177477.3-177478.45" - wire width 5 $0\core_core_rego[4:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 10 $0\core_core_spr1$next[9:0]$12659 - attribute \src "issuer_ls180.v:177505.3-177506.45" - wire width 10 $0\core_core_spr1[9:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $0\core_core_spr1_ok$next[0:0]$12660 - attribute \src "issuer_ls180.v:177507.3-177508.51" - wire $0\core_core_spr1_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 10 $0\core_core_spro$next[9:0]$12661 - attribute \src "issuer_ls180.v:177499.3-177500.45" - wire width 10 $0\core_core_spro[9:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $0\core_core_xer_in$next[2:0]$12662 - attribute \src "issuer_ls180.v:177509.3-177510.49" - wire width 3 $0\core_core_xer_in[2:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $0\core_cr_out_ok$next[0:0]$12663 - attribute \src "issuer_ls180.v:177545.3-177546.45" - wire $0\core_cr_out_ok[0:0] - attribute \src "issuer_ls180.v:178096.3-178116.6" - wire width 64 $0\core_data_i[63:0] - attribute \src "issuer_ls180.v:178599.3-178630.6" - wire width 64 $0\core_dec$next[63:0]$12888 - attribute \src "issuer_ls180.v:177461.3-177462.33" - wire width 64 $0\core_dec[63:0] - attribute \src "issuer_ls180.v:178686.3-178695.6" - wire width 5 $0\core_dmi__addr[4:0] - attribute \src "issuer_ls180.v:178696.3-178705.6" - wire $0\core_dmi__ren[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $0\core_ea_ok$next[0:0]$12664 - attribute \src "issuer_ls180.v:177485.3-177486.37" - wire $0\core_ea_ok[0:0] - attribute \src "issuer_ls180.v:178599.3-178630.6" - wire $0\core_eint$next[0:0]$12889 - attribute \src "issuer_ls180.v:177601.3-177602.35" - wire $0\core_eint[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $0\core_fasto1_ok$next[0:0]$12665 - attribute \src "issuer_ls180.v:177523.3-177524.45" - wire $0\core_fasto1_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $0\core_fasto2_ok$next[0:0]$12666 - attribute \src "issuer_ls180.v:177529.3-177530.45" - wire $0\core_fasto2_ok[0:0] - attribute \src "issuer_ls180.v:177818.3-177827.6" - wire width 8 $0\core_full_rd2__ren[7:0] - attribute \src "issuer_ls180.v:177857.3-177866.6" - wire width 3 $0\core_full_rd__ren[2:0] - attribute \src "issuer_ls180.v:177965.3-177979.6" - wire width 3 $0\core_issue__addr$4[2:0]$12593 - attribute \src "issuer_ls180.v:177896.3-177910.6" - wire width 3 $0\core_issue__addr[2:0] - attribute \src "issuer_ls180.v:177995.3-178009.6" - wire width 64 $0\core_issue__data_i[63:0] - attribute \src "issuer_ls180.v:177911.3-177925.6" - wire $0\core_issue__ren[0:0] - attribute \src "issuer_ls180.v:177980.3-177994.6" - wire $0\core_issue__wen[0:0] - attribute \src "issuer_ls180.v:178675.3-178685.6" - wire $0\core_issue_i[0:0] - attribute \src "issuer_ls180.v:178655.3-178674.6" - wire $0\core_ivalid_i[0:0] - attribute \src "issuer_ls180.v:178599.3-178630.6" - wire width 64 $0\core_msr$next[63:0]$12890 - attribute \src "issuer_ls180.v:177599.3-177600.33" - wire width 64 $0\core_msr[63:0] - attribute \src "issuer_ls180.v:178126.3-178141.6" - wire width 4 $0\core_msr__ren[3:0] - attribute \src "issuer_ls180.v:178284.3-178320.6" - wire width 32 $0\core_raw_insn_i$next[31:0]$12846 - attribute \src "issuer_ls180.v:177473.3-177474.47" - wire width 32 $0\core_raw_insn_i[31:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $0\core_rego_ok$next[0:0]$12667 - attribute \src "issuer_ls180.v:177479.3-177480.41" - wire $0\core_rego_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $0\core_spro_ok$next[0:0]$12668 - attribute \src "issuer_ls180.v:177501.3-177502.41" - wire $0\core_spro_ok[0:0] - attribute \src "issuer_ls180.v:178521.3-178539.6" - wire $0\core_stopped_i[0:0] - attribute \src "issuer_ls180.v:178075.3-178095.6" - wire width 4 $0\core_wen[3:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $0\core_xer_out$next[0:0]$12669 - attribute \src "issuer_ls180.v:177511.3-177512.41" - wire $0\core_xer_out[0:0] - attribute \src "issuer_ls180.v:177593.3-177594.43" - wire $0\cu_st__rel_o_dly[0:0] - attribute \src "issuer_ls180.v:177828.3-177836.6" - wire $0\d_cr_delay$next[0:0]$12575 - attribute \src "issuer_ls180.v:177525.3-177526.37" - wire $0\d_cr_delay[0:0] - attribute \src "issuer_ls180.v:178706.3-178714.6" - wire $0\d_reg_delay$next[0:0]$12913 - attribute \src "issuer_ls180.v:177547.3-177548.39" - wire $0\d_reg_delay[0:0] - attribute \src "issuer_ls180.v:177867.3-177875.6" - wire $0\d_xer_delay$next[0:0]$12581 - attribute \src "issuer_ls180.v:177503.3-177504.39" - wire $0\d_xer_delay[0:0] - attribute \src "issuer_ls180.v:178540.3-178558.6" - wire $0\dbg_core_stopped_i[0:0] - attribute \src "issuer_ls180.v:177847.3-177856.6" - wire $0\dbg_d_cr_ack[0:0] - attribute \src "issuer_ls180.v:177837.3-177846.6" - wire width 64 $0\dbg_d_cr_data[63:0] - attribute \src "issuer_ls180.v:178725.3-178734.6" - wire $0\dbg_d_gpr_ack[0:0] - attribute \src "issuer_ls180.v:178715.3-178724.6" - wire width 64 $0\dbg_d_gpr_data[63:0] - attribute \src "issuer_ls180.v:177886.3-177895.6" - wire $0\dbg_d_xer_ack[0:0] - attribute \src "issuer_ls180.v:177876.3-177885.6" - wire width 64 $0\dbg_d_xer_data[63:0] - attribute \src "issuer_ls180.v:178010.3-178025.6" - wire width 64 $0\dec2_cur_dec$next[63:0]$12598 - attribute \src "issuer_ls180.v:177459.3-177460.41" - wire width 64 $0\dec2_cur_dec[63:0] - attribute \src "issuer_ls180.v:178117.3-178125.6" - wire $0\dec2_cur_eint$next[0:0]$12610 - attribute \src "issuer_ls180.v:177597.3-177598.43" - wire $0\dec2_cur_eint[0:0] - attribute \src "issuer_ls180.v:178559.3-178579.6" - wire width 64 $0\dec2_cur_msr$next[63:0]$12881 - attribute \src "issuer_ls180.v:177463.3-177464.41" - wire width 64 $0\dec2_cur_msr[63:0] - attribute \src "issuer_ls180.v:178424.3-178444.6" - wire width 64 $0\dec2_cur_pc$next[63:0]$12861 - attribute \src "issuer_ls180.v:177469.3-177470.39" - wire width 64 $0\dec2_cur_pc[63:0] - attribute \src "issuer_ls180.v:178580.3-178598.6" - wire width 32 $0\dec2_raw_opcode_in[31:0] - attribute \src "issuer_ls180.v:178274.3-178283.6" - wire width 2 $0\delay$next[1:0]$12843 - attribute \src "issuer_ls180.v:177595.3-177596.27" - wire width 2 $0\delay[1:0] - attribute \src "issuer_ls180.v:177926.3-177953.6" - wire width 2 $0\fsm_state$117$next[1:0]$12588 - attribute \src "issuer_ls180.v:177481.3-177482.45" - wire width 2 $0\fsm_state$117[1:0]$12510 - attribute \src "issuer_ls180.v:177274.13-177274.35" - wire width 2 $0\fsm_state$117[1:0]$12989 - attribute \src "issuer_ls180.v:178475.3-178520.6" - wire width 2 $0\fsm_state$next[1:0]$12872 - attribute \src "issuer_ls180.v:177465.3-177466.35" - wire width 2 $0\fsm_state[1:0] - attribute \src "issuer_ls180.v:178631.3-178654.6" - wire width 32 $0\ilatch$next[31:0]$12904 - attribute \src "issuer_ls180.v:177569.3-177570.29" - wire width 32 $0\ilatch[31:0] - attribute \src "issuer_ls180.v:178358.3-178373.6" - wire width 48 $0\imem_a_pc_i[47:0] - attribute \src "issuer_ls180.v:178374.3-178398.6" - wire $0\imem_a_valid_i[0:0] - attribute \src "issuer_ls180.v:178399.3-178423.6" - wire $0\imem_f_valid_i[0:0] - attribute \src "issuer_ls180.v:176018.7-176018.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:178445.3-178474.6" - wire $0\msr_read$next[0:0]$12866 - attribute \src "issuer_ls180.v:177467.3-177468.33" - wire $0\msr_read[0:0] - attribute \src "issuer_ls180.v:177954.3-177964.6" - wire width 64 $0\new_dec[63:0] - attribute \src "issuer_ls180.v:178026.3-178036.6" - wire width 64 $0\new_tb[63:0] - attribute \src "issuer_ls180.v:178046.3-178061.6" - wire width 64 $0\pc[63:0] - attribute \src "issuer_ls180.v:178142.3-178166.6" - wire $0\pc_changed$next[0:0]$12614 - attribute \src "issuer_ls180.v:177587.3-177588.37" - wire $0\pc_changed[0:0] - attribute \src "issuer_ls180.v:178037.3-178045.6" - wire $0\pc_ok_delay$next[0:0]$12603 - attribute \src "issuer_ls180.v:177589.3-177590.39" - wire $0\pc_ok_delay[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 8 $1\core_asmcode$next[7:0]$12670 - attribute \src "issuer_ls180.v:176144.13-176144.33" - wire width 8 $1\core_asmcode[7:0] - attribute \src "issuer_ls180.v:178321.3-178357.6" - wire $1\core_bigendian_i$3$next[0:0]$12853 - attribute \src "issuer_ls180.v:178062.3-178074.6" - wire width 4 $1\core_cia__ren[3:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 64 $1\core_core_core_cia$next[63:0]$12671 - attribute \src "issuer_ls180.v:176158.14-176158.55" - wire width 64 $1\core_core_core_cia[63:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 8 $1\core_core_core_cr_rd$next[7:0]$12672 - attribute \src "issuer_ls180.v:176162.13-176162.41" - wire width 8 $1\core_core_core_cr_rd[7:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $1\core_core_core_cr_rd_ok$next[0:0]$12673 - attribute \src "issuer_ls180.v:176166.7-176166.37" - wire $1\core_core_core_cr_rd_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 8 $1\core_core_core_cr_wr$next[7:0]$12674 - attribute \src "issuer_ls180.v:176170.13-176170.41" - wire width 8 $1\core_core_core_cr_wr[7:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 12 $1\core_core_core_fn_unit$next[11:0]$12675 - attribute \src "issuer_ls180.v:176187.14-176187.46" - wire width 12 $1\core_core_core_fn_unit[11:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 2 $1\core_core_core_input_carry$next[1:0]$12676 - attribute \src "issuer_ls180.v:176195.13-176195.46" - wire width 2 $1\core_core_core_input_carry[1:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 32 $1\core_core_core_insn$next[31:0]$12677 - attribute \src "issuer_ls180.v:176199.14-176199.41" - wire width 32 $1\core_core_core_insn[31:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 7 $1\core_core_core_insn_type$next[6:0]$12678 - attribute \src "issuer_ls180.v:176277.13-176277.45" - wire width 7 $1\core_core_core_insn_type[6:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $1\core_core_core_is_32bit$next[0:0]$12679 - attribute \src "issuer_ls180.v:176281.7-176281.37" - wire $1\core_core_core_is_32bit[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 64 $1\core_core_core_msr$next[63:0]$12680 - attribute \src "issuer_ls180.v:176285.14-176285.55" - wire width 64 $1\core_core_core_msr[63:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $1\core_core_core_oe$next[0:0]$12681 - attribute \src "issuer_ls180.v:176289.7-176289.31" - wire $1\core_core_core_oe[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $1\core_core_core_oe_ok$next[0:0]$12682 - attribute \src "issuer_ls180.v:176293.7-176293.34" - wire $1\core_core_core_oe_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $1\core_core_core_rc$next[0:0]$12683 - attribute \src "issuer_ls180.v:176297.7-176297.31" - wire $1\core_core_core_rc[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $1\core_core_core_rc_ok$next[0:0]$12684 - attribute \src "issuer_ls180.v:176301.7-176301.34" - wire $1\core_core_core_rc_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 13 $1\core_core_core_trapaddr$next[12:0]$12685 - attribute \src "issuer_ls180.v:176305.14-176305.48" - wire width 13 $1\core_core_core_trapaddr[12:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 7 $1\core_core_core_traptype$next[6:0]$12686 - attribute \src "issuer_ls180.v:176309.13-176309.44" - wire width 7 $1\core_core_core_traptype[6:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $1\core_core_cr_in1$next[2:0]$12687 - attribute \src "issuer_ls180.v:176313.13-176313.36" - wire width 3 $1\core_core_cr_in1[2:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $1\core_core_cr_in1_ok$next[0:0]$12688 - attribute \src "issuer_ls180.v:176317.7-176317.33" - wire $1\core_core_cr_in1_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $1\core_core_cr_in2$1$next[2:0]$12689 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $1\core_core_cr_in2$next[2:0]$12690 - attribute \src "issuer_ls180.v:176321.13-176321.36" - wire width 3 $1\core_core_cr_in2[2:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $1\core_core_cr_in2_ok$2$next[0:0]$12691 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $1\core_core_cr_in2_ok$next[0:0]$12692 - attribute \src "issuer_ls180.v:176329.7-176329.33" - wire $1\core_core_cr_in2_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $1\core_core_cr_out$next[2:0]$12693 - attribute \src "issuer_ls180.v:176337.13-176337.36" - wire width 3 $1\core_core_cr_out[2:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $1\core_core_cr_wr_ok$next[0:0]$12694 - attribute \src "issuer_ls180.v:176341.7-176341.32" - wire $1\core_core_cr_wr_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 5 $1\core_core_ea$next[4:0]$12695 - attribute \src "issuer_ls180.v:176345.13-176345.33" - wire width 5 $1\core_core_ea[4:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $1\core_core_fast1$next[2:0]$12696 - attribute \src "issuer_ls180.v:176349.13-176349.35" - wire width 3 $1\core_core_fast1[2:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $1\core_core_fast1_ok$next[0:0]$12697 - attribute \src "issuer_ls180.v:176353.7-176353.32" - wire $1\core_core_fast1_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $1\core_core_fast2$next[2:0]$12698 - attribute \src "issuer_ls180.v:176357.13-176357.35" - wire width 3 $1\core_core_fast2[2:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $1\core_core_fast2_ok$next[0:0]$12699 - attribute \src "issuer_ls180.v:176361.7-176361.32" - wire $1\core_core_fast2_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $1\core_core_fasto1$next[2:0]$12700 - attribute \src "issuer_ls180.v:176365.13-176365.36" - wire width 3 $1\core_core_fasto1[2:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $1\core_core_fasto2$next[2:0]$12701 - attribute \src "issuer_ls180.v:176369.13-176369.36" - wire width 3 $1\core_core_fasto2[2:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $1\core_core_lk$next[0:0]$12702 - attribute \src "issuer_ls180.v:176373.7-176373.26" - wire $1\core_core_lk[0:0] - attribute \src "issuer_ls180.v:178599.3-178630.6" - wire width 64 $1\core_core_pc$next[63:0]$12891 - attribute \src "issuer_ls180.v:176377.14-176377.49" - wire width 64 $1\core_core_pc[63:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 5 $1\core_core_reg1$next[4:0]$12703 - attribute \src "issuer_ls180.v:176381.13-176381.35" - wire width 5 $1\core_core_reg1[4:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $1\core_core_reg1_ok$next[0:0]$12704 - attribute \src "issuer_ls180.v:176385.7-176385.31" - wire $1\core_core_reg1_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 5 $1\core_core_reg2$next[4:0]$12705 - attribute \src "issuer_ls180.v:176389.13-176389.35" - wire width 5 $1\core_core_reg2[4:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $1\core_core_reg2_ok$next[0:0]$12706 - attribute \src "issuer_ls180.v:176393.7-176393.31" - wire $1\core_core_reg2_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 5 $1\core_core_reg3$next[4:0]$12707 - attribute \src "issuer_ls180.v:176397.13-176397.35" - wire width 5 $1\core_core_reg3[4:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $1\core_core_reg3_ok$next[0:0]$12708 - attribute \src "issuer_ls180.v:176401.7-176401.31" - wire $1\core_core_reg3_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 5 $1\core_core_rego$next[4:0]$12709 - attribute \src "issuer_ls180.v:176405.13-176405.35" - wire width 5 $1\core_core_rego[4:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 10 $1\core_core_spr1$next[9:0]$12710 - attribute \src "issuer_ls180.v:176522.13-176522.37" - wire width 10 $1\core_core_spr1[9:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $1\core_core_spr1_ok$next[0:0]$12711 - attribute \src "issuer_ls180.v:176526.7-176526.31" - wire $1\core_core_spr1_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 10 $1\core_core_spro$next[9:0]$12712 - attribute \src "issuer_ls180.v:176641.13-176641.37" - wire width 10 $1\core_core_spro[9:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $1\core_core_xer_in$next[2:0]$12713 - attribute \src "issuer_ls180.v:176647.13-176647.36" - wire width 3 $1\core_core_xer_in[2:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $1\core_cr_out_ok$next[0:0]$12714 - attribute \src "issuer_ls180.v:176655.7-176655.28" - wire $1\core_cr_out_ok[0:0] - attribute \src "issuer_ls180.v:178096.3-178116.6" - wire width 64 $1\core_data_i[63:0] - attribute \src "issuer_ls180.v:178599.3-178630.6" - wire width 64 $1\core_dec$next[63:0]$12892 - attribute \src "issuer_ls180.v:176669.14-176669.45" - wire width 64 $1\core_dec[63:0] - attribute \src "issuer_ls180.v:178686.3-178695.6" - wire width 5 $1\core_dmi__addr[4:0] - attribute \src "issuer_ls180.v:178696.3-178705.6" - wire $1\core_dmi__ren[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $1\core_ea_ok$next[0:0]$12715 - attribute \src "issuer_ls180.v:176679.7-176679.24" - wire $1\core_ea_ok[0:0] - attribute \src "issuer_ls180.v:178599.3-178630.6" - wire $1\core_eint$next[0:0]$12893 - attribute \src "issuer_ls180.v:176683.7-176683.23" - wire $1\core_eint[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $1\core_fasto1_ok$next[0:0]$12716 - attribute \src "issuer_ls180.v:176687.7-176687.28" - wire $1\core_fasto1_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $1\core_fasto2_ok$next[0:0]$12717 - attribute \src "issuer_ls180.v:176691.7-176691.28" - wire $1\core_fasto2_ok[0:0] - attribute \src "issuer_ls180.v:177818.3-177827.6" - wire width 8 $1\core_full_rd2__ren[7:0] - attribute \src "issuer_ls180.v:177857.3-177866.6" - wire width 3 $1\core_full_rd__ren[2:0] - attribute \src "issuer_ls180.v:177965.3-177979.6" - wire width 3 $1\core_issue__addr$4[2:0]$12594 - attribute \src "issuer_ls180.v:177896.3-177910.6" - wire width 3 $1\core_issue__addr[2:0] - attribute \src "issuer_ls180.v:177995.3-178009.6" - wire width 64 $1\core_issue__data_i[63:0] - attribute \src "issuer_ls180.v:177911.3-177925.6" - wire $1\core_issue__ren[0:0] - attribute \src "issuer_ls180.v:177980.3-177994.6" - wire $1\core_issue__wen[0:0] - attribute \src "issuer_ls180.v:178675.3-178685.6" - wire $1\core_issue_i[0:0] - attribute \src "issuer_ls180.v:178655.3-178674.6" - wire $1\core_ivalid_i[0:0] - attribute \src "issuer_ls180.v:178599.3-178630.6" - wire width 64 $1\core_msr$next[63:0]$12894 - attribute \src "issuer_ls180.v:176719.14-176719.45" - wire width 64 $1\core_msr[63:0] - attribute \src "issuer_ls180.v:178126.3-178141.6" - wire width 4 $1\core_msr__ren[3:0] - attribute \src "issuer_ls180.v:178284.3-178320.6" - wire width 32 $1\core_raw_insn_i$next[31:0]$12847 - attribute \src "issuer_ls180.v:176727.14-176727.37" - wire width 32 $1\core_raw_insn_i[31:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $1\core_rego_ok$next[0:0]$12718 - attribute \src "issuer_ls180.v:176731.7-176731.26" - wire $1\core_rego_ok[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $1\core_spro_ok$next[0:0]$12719 - attribute \src "issuer_ls180.v:176735.7-176735.26" - wire $1\core_spro_ok[0:0] - attribute \src "issuer_ls180.v:178521.3-178539.6" - wire $1\core_stopped_i[0:0] - attribute \src "issuer_ls180.v:178075.3-178095.6" - wire width 4 $1\core_wen[3:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $1\core_xer_out$next[0:0]$12720 - attribute \src "issuer_ls180.v:176745.7-176745.26" - wire $1\core_xer_out[0:0] - attribute \src "issuer_ls180.v:176749.7-176749.30" - wire $1\cu_st__rel_o_dly[0:0] - attribute \src "issuer_ls180.v:177828.3-177836.6" - wire $1\d_cr_delay$next[0:0]$12576 - attribute \src "issuer_ls180.v:176755.7-176755.24" - wire $1\d_cr_delay[0:0] - attribute \src "issuer_ls180.v:178706.3-178714.6" - wire $1\d_reg_delay$next[0:0]$12914 - attribute \src "issuer_ls180.v:176759.7-176759.25" - wire $1\d_reg_delay[0:0] - attribute \src "issuer_ls180.v:177867.3-177875.6" - wire $1\d_xer_delay$next[0:0]$12582 - attribute \src "issuer_ls180.v:176763.7-176763.25" - wire $1\d_xer_delay[0:0] - attribute \src "issuer_ls180.v:178540.3-178558.6" - wire $1\dbg_core_stopped_i[0:0] - attribute \src "issuer_ls180.v:177847.3-177856.6" - wire $1\dbg_d_cr_ack[0:0] - attribute \src "issuer_ls180.v:177837.3-177846.6" - wire width 64 $1\dbg_d_cr_data[63:0] - attribute \src "issuer_ls180.v:178725.3-178734.6" - wire $1\dbg_d_gpr_ack[0:0] - attribute \src "issuer_ls180.v:178715.3-178724.6" - wire width 64 $1\dbg_d_gpr_data[63:0] - attribute \src "issuer_ls180.v:177886.3-177895.6" - wire $1\dbg_d_xer_ack[0:0] - attribute \src "issuer_ls180.v:177876.3-177885.6" - wire width 64 $1\dbg_d_xer_data[63:0] - attribute \src "issuer_ls180.v:178010.3-178025.6" - wire width 64 $1\dec2_cur_dec$next[63:0]$12599 - attribute \src "issuer_ls180.v:176851.14-176851.49" - wire width 64 $1\dec2_cur_dec[63:0] - attribute \src "issuer_ls180.v:178117.3-178125.6" - wire $1\dec2_cur_eint$next[0:0]$12611 - attribute \src "issuer_ls180.v:176855.7-176855.27" - wire $1\dec2_cur_eint[0:0] - attribute \src "issuer_ls180.v:178559.3-178579.6" - wire width 64 $1\dec2_cur_msr$next[63:0]$12882 - attribute \src "issuer_ls180.v:176859.14-176859.49" - wire width 64 $1\dec2_cur_msr[63:0] - attribute \src "issuer_ls180.v:178424.3-178444.6" - wire width 64 $1\dec2_cur_pc$next[63:0]$12862 - attribute \src "issuer_ls180.v:176863.14-176863.48" - wire width 64 $1\dec2_cur_pc[63:0] - attribute \src "issuer_ls180.v:178580.3-178598.6" - wire width 32 $1\dec2_raw_opcode_in[31:0] - attribute \src "issuer_ls180.v:178274.3-178283.6" - wire width 2 $1\delay$next[1:0]$12844 - attribute \src "issuer_ls180.v:177256.13-177256.25" - wire width 2 $1\delay[1:0] - attribute \src "issuer_ls180.v:177926.3-177953.6" - wire width 2 $1\fsm_state$117$next[1:0]$12589 - attribute \src "issuer_ls180.v:178475.3-178520.6" - wire width 2 $1\fsm_state$next[1:0]$12873 - attribute \src "issuer_ls180.v:177272.13-177272.29" - wire width 2 $1\fsm_state[1:0] - attribute \src "issuer_ls180.v:178631.3-178654.6" - wire width 32 $1\ilatch$next[31:0]$12905 - attribute \src "issuer_ls180.v:177346.14-177346.28" - wire width 32 $1\ilatch[31:0] - attribute \src "issuer_ls180.v:178358.3-178373.6" - wire width 48 $1\imem_a_pc_i[47:0] - attribute \src "issuer_ls180.v:178374.3-178398.6" - wire $1\imem_a_valid_i[0:0] - attribute \src "issuer_ls180.v:178399.3-178423.6" - wire $1\imem_f_valid_i[0:0] - attribute \src "issuer_ls180.v:178445.3-178474.6" - wire $1\msr_read$next[0:0]$12867 - attribute \src "issuer_ls180.v:177364.7-177364.22" - wire $1\msr_read[0:0] - attribute \src "issuer_ls180.v:177954.3-177964.6" - wire width 64 $1\new_dec[63:0] - attribute \src "issuer_ls180.v:178026.3-178036.6" - wire width 64 $1\new_tb[63:0] - attribute \src "issuer_ls180.v:178046.3-178061.6" - wire width 64 $1\pc[63:0] - attribute \src "issuer_ls180.v:178142.3-178166.6" - wire $1\pc_changed$next[0:0]$12615 - attribute \src "issuer_ls180.v:177376.7-177376.24" - wire $1\pc_changed[0:0] - attribute \src "issuer_ls180.v:178037.3-178045.6" - wire $1\pc_ok_delay$next[0:0]$12604 - attribute \src "issuer_ls180.v:177386.7-177386.25" - wire $1\pc_ok_delay[0:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 8 $2\core_asmcode$next[7:0]$12721 - attribute \src "issuer_ls180.v:178321.3-178357.6" - wire $2\core_bigendian_i$3$next[0:0]$12854 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 64 $2\core_core_core_cia$next[63:0]$12722 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 8 $2\core_core_core_cr_rd$next[7:0]$12723 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $2\core_core_core_cr_rd_ok$next[0:0]$12724 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 8 $2\core_core_core_cr_wr$next[7:0]$12725 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 12 $2\core_core_core_fn_unit$next[11:0]$12726 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 2 $2\core_core_core_input_carry$next[1:0]$12727 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 32 $2\core_core_core_insn$next[31:0]$12728 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 7 $2\core_core_core_insn_type$next[6:0]$12729 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $2\core_core_core_is_32bit$next[0:0]$12730 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 64 $2\core_core_core_msr$next[63:0]$12731 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $2\core_core_core_oe$next[0:0]$12732 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $2\core_core_core_oe_ok$next[0:0]$12733 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $2\core_core_core_rc$next[0:0]$12734 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $2\core_core_core_rc_ok$next[0:0]$12735 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 13 $2\core_core_core_trapaddr$next[12:0]$12736 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 7 $2\core_core_core_traptype$next[6:0]$12737 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $2\core_core_cr_in1$next[2:0]$12738 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $2\core_core_cr_in1_ok$next[0:0]$12739 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $2\core_core_cr_in2$1$next[2:0]$12740 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $2\core_core_cr_in2$next[2:0]$12741 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $2\core_core_cr_in2_ok$2$next[0:0]$12742 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $2\core_core_cr_in2_ok$next[0:0]$12743 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $2\core_core_cr_out$next[2:0]$12744 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $2\core_core_cr_wr_ok$next[0:0]$12745 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 5 $2\core_core_ea$next[4:0]$12746 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $2\core_core_fast1$next[2:0]$12747 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $2\core_core_fast1_ok$next[0:0]$12748 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $2\core_core_fast2$next[2:0]$12749 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $2\core_core_fast2_ok$next[0:0]$12750 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $2\core_core_fasto1$next[2:0]$12751 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $2\core_core_fasto2$next[2:0]$12752 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $2\core_core_lk$next[0:0]$12753 - attribute \src "issuer_ls180.v:178599.3-178630.6" - wire width 64 $2\core_core_pc$next[63:0]$12895 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 5 $2\core_core_reg1$next[4:0]$12754 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $2\core_core_reg1_ok$next[0:0]$12755 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 5 $2\core_core_reg2$next[4:0]$12756 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $2\core_core_reg2_ok$next[0:0]$12757 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 5 $2\core_core_reg3$next[4:0]$12758 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $2\core_core_reg3_ok$next[0:0]$12759 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 5 $2\core_core_rego$next[4:0]$12760 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 10 $2\core_core_spr1$next[9:0]$12761 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $2\core_core_spr1_ok$next[0:0]$12762 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 10 $2\core_core_spro$next[9:0]$12763 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $2\core_core_xer_in$next[2:0]$12764 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $2\core_cr_out_ok$next[0:0]$12765 - attribute \src "issuer_ls180.v:178096.3-178116.6" - wire width 64 $2\core_data_i[63:0] - attribute \src "issuer_ls180.v:178599.3-178630.6" - wire width 64 $2\core_dec$next[63:0]$12896 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $2\core_ea_ok$next[0:0]$12766 - attribute \src "issuer_ls180.v:178599.3-178630.6" - wire $2\core_eint$next[0:0]$12897 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $2\core_fasto1_ok$next[0:0]$12767 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $2\core_fasto2_ok$next[0:0]$12768 - attribute \src "issuer_ls180.v:178655.3-178674.6" - wire $2\core_ivalid_i[0:0] - attribute \src "issuer_ls180.v:178599.3-178630.6" - wire width 64 $2\core_msr$next[63:0]$12898 - attribute \src "issuer_ls180.v:178126.3-178141.6" - wire width 4 $2\core_msr__ren[3:0] - attribute \src "issuer_ls180.v:178284.3-178320.6" - wire width 32 $2\core_raw_insn_i$next[31:0]$12848 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $2\core_rego_ok$next[0:0]$12769 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $2\core_spro_ok$next[0:0]$12770 - attribute \src "issuer_ls180.v:178521.3-178539.6" - wire $2\core_stopped_i[0:0] - attribute \src "issuer_ls180.v:178075.3-178095.6" - wire width 4 $2\core_wen[3:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $2\core_xer_out$next[0:0]$12771 - attribute \src "issuer_ls180.v:178540.3-178558.6" - wire $2\dbg_core_stopped_i[0:0] - attribute \src "issuer_ls180.v:178010.3-178025.6" - wire width 64 $2\dec2_cur_dec$next[63:0]$12600 - attribute \src "issuer_ls180.v:178559.3-178579.6" - wire width 64 $2\dec2_cur_msr$next[63:0]$12883 - attribute \src "issuer_ls180.v:178424.3-178444.6" - wire width 64 $2\dec2_cur_pc$next[63:0]$12863 - attribute \src "issuer_ls180.v:178580.3-178598.6" - wire width 32 $2\dec2_raw_opcode_in[31:0] - attribute \src "issuer_ls180.v:177926.3-177953.6" - wire width 2 $2\fsm_state$117$next[1:0]$12590 - attribute \src "issuer_ls180.v:178475.3-178520.6" - wire width 2 $2\fsm_state$next[1:0]$12874 - attribute \src "issuer_ls180.v:178631.3-178654.6" - wire width 32 $2\ilatch$next[31:0]$12906 - attribute \src "issuer_ls180.v:178358.3-178373.6" - wire width 48 $2\imem_a_pc_i[47:0] - attribute \src "issuer_ls180.v:178374.3-178398.6" - wire $2\imem_a_valid_i[0:0] - attribute \src "issuer_ls180.v:178399.3-178423.6" - wire $2\imem_f_valid_i[0:0] - attribute \src "issuer_ls180.v:178445.3-178474.6" - wire $2\msr_read$next[0:0]$12868 - attribute \src "issuer_ls180.v:178046.3-178061.6" - wire width 64 $2\pc[63:0] - attribute \src "issuer_ls180.v:178142.3-178166.6" - wire $2\pc_changed$next[0:0]$12616 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 8 $3\core_asmcode$next[7:0]$12772 - attribute \src "issuer_ls180.v:178321.3-178357.6" - wire $3\core_bigendian_i$3$next[0:0]$12855 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 64 $3\core_core_core_cia$next[63:0]$12773 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 8 $3\core_core_core_cr_rd$next[7:0]$12774 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $3\core_core_core_cr_rd_ok$next[0:0]$12775 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 8 $3\core_core_core_cr_wr$next[7:0]$12776 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 12 $3\core_core_core_fn_unit$next[11:0]$12777 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 2 $3\core_core_core_input_carry$next[1:0]$12778 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 32 $3\core_core_core_insn$next[31:0]$12779 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 7 $3\core_core_core_insn_type$next[6:0]$12780 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $3\core_core_core_is_32bit$next[0:0]$12781 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 64 $3\core_core_core_msr$next[63:0]$12782 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $3\core_core_core_oe$next[0:0]$12783 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $3\core_core_core_oe_ok$next[0:0]$12784 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $3\core_core_core_rc$next[0:0]$12785 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $3\core_core_core_rc_ok$next[0:0]$12786 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 13 $3\core_core_core_trapaddr$next[12:0]$12787 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 7 $3\core_core_core_traptype$next[6:0]$12788 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $3\core_core_cr_in1$next[2:0]$12789 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $3\core_core_cr_in1_ok$next[0:0]$12790 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $3\core_core_cr_in2$1$next[2:0]$12791 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $3\core_core_cr_in2$next[2:0]$12792 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $3\core_core_cr_in2_ok$2$next[0:0]$12793 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $3\core_core_cr_in2_ok$next[0:0]$12794 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $3\core_core_cr_out$next[2:0]$12795 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $3\core_core_cr_wr_ok$next[0:0]$12796 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 5 $3\core_core_ea$next[4:0]$12797 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $3\core_core_fast1$next[2:0]$12798 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $3\core_core_fast1_ok$next[0:0]$12799 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $3\core_core_fast2$next[2:0]$12800 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $3\core_core_fast2_ok$next[0:0]$12801 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $3\core_core_fasto1$next[2:0]$12802 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $3\core_core_fasto2$next[2:0]$12803 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $3\core_core_lk$next[0:0]$12804 - attribute \src "issuer_ls180.v:178599.3-178630.6" - wire width 64 $3\core_core_pc$next[63:0]$12899 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 5 $3\core_core_reg1$next[4:0]$12805 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $3\core_core_reg1_ok$next[0:0]$12806 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 5 $3\core_core_reg2$next[4:0]$12807 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $3\core_core_reg2_ok$next[0:0]$12808 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 5 $3\core_core_reg3$next[4:0]$12809 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $3\core_core_reg3_ok$next[0:0]$12810 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 5 $3\core_core_rego$next[4:0]$12811 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 10 $3\core_core_spr1$next[9:0]$12812 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $3\core_core_spr1_ok$next[0:0]$12813 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 10 $3\core_core_spro$next[9:0]$12814 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire width 3 $3\core_core_xer_in$next[2:0]$12815 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $3\core_cr_out_ok$next[0:0]$12816 - attribute \src "issuer_ls180.v:178096.3-178116.6" - wire width 64 $3\core_data_i[63:0] - attribute \src "issuer_ls180.v:178599.3-178630.6" - wire width 64 $3\core_dec$next[63:0]$12900 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $3\core_ea_ok$next[0:0]$12817 - attribute \src "issuer_ls180.v:178599.3-178630.6" - wire $3\core_eint$next[0:0]$12901 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $3\core_fasto1_ok$next[0:0]$12818 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $3\core_fasto2_ok$next[0:0]$12819 - attribute \src "issuer_ls180.v:178599.3-178630.6" - wire width 64 $3\core_msr$next[63:0]$12902 - attribute \src "issuer_ls180.v:178284.3-178320.6" - wire width 32 $3\core_raw_insn_i$next[31:0]$12849 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $3\core_rego_ok$next[0:0]$12820 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $3\core_spro_ok$next[0:0]$12821 - attribute \src "issuer_ls180.v:178075.3-178095.6" - wire width 4 $3\core_wen[3:0] - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $3\core_xer_out$next[0:0]$12822 - attribute \src "issuer_ls180.v:178559.3-178579.6" - wire width 64 $3\dec2_cur_msr$next[63:0]$12884 - attribute \src "issuer_ls180.v:178424.3-178444.6" - wire width 64 $3\dec2_cur_pc$next[63:0]$12864 - attribute \src "issuer_ls180.v:178475.3-178520.6" - wire width 2 $3\fsm_state$next[1:0]$12875 - attribute \src "issuer_ls180.v:178631.3-178654.6" - wire width 32 $3\ilatch$next[31:0]$12907 - attribute \src "issuer_ls180.v:178374.3-178398.6" - wire $3\imem_a_valid_i[0:0] - attribute \src "issuer_ls180.v:178399.3-178423.6" - wire $3\imem_f_valid_i[0:0] - attribute \src "issuer_ls180.v:178445.3-178474.6" - wire $3\msr_read$next[0:0]$12869 - attribute \src "issuer_ls180.v:178142.3-178166.6" - wire $3\pc_changed$next[0:0]$12617 - attribute \src "issuer_ls180.v:178321.3-178357.6" - wire $4\core_bigendian_i$3$next[0:0]$12856 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $4\core_core_core_cr_rd_ok$next[0:0]$12823 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $4\core_core_core_oe_ok$next[0:0]$12824 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $4\core_core_core_rc_ok$next[0:0]$12825 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $4\core_core_cr_in1_ok$next[0:0]$12826 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $4\core_core_cr_in2_ok$2$next[0:0]$12827 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $4\core_core_cr_in2_ok$next[0:0]$12828 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $4\core_core_cr_wr_ok$next[0:0]$12829 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $4\core_core_fast1_ok$next[0:0]$12830 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $4\core_core_fast2_ok$next[0:0]$12831 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $4\core_core_reg1_ok$next[0:0]$12832 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $4\core_core_reg2_ok$next[0:0]$12833 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $4\core_core_reg3_ok$next[0:0]$12834 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $4\core_core_spr1_ok$next[0:0]$12835 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $4\core_cr_out_ok$next[0:0]$12836 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $4\core_ea_ok$next[0:0]$12837 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $4\core_fasto1_ok$next[0:0]$12838 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $4\core_fasto2_ok$next[0:0]$12839 - attribute \src "issuer_ls180.v:178284.3-178320.6" - wire width 32 $4\core_raw_insn_i$next[31:0]$12850 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $4\core_rego_ok$next[0:0]$12840 - attribute \src "issuer_ls180.v:178167.3-178273.6" - wire $4\core_spro_ok$next[0:0]$12841 - attribute \src "issuer_ls180.v:178475.3-178520.6" - wire width 2 $4\fsm_state$next[1:0]$12876 - attribute \src "issuer_ls180.v:178445.3-178474.6" - wire $4\msr_read$next[0:0]$12870 - attribute \src "issuer_ls180.v:178475.3-178520.6" - wire width 2 $5\fsm_state$next[1:0]$12877 - attribute \src "issuer_ls180.v:177414.19-177414.115" - wire width 65 $add$issuer_ls180.v:177414$12452_Y - attribute \src "issuer_ls180.v:177419.18-177419.107" - wire width 65 $add$issuer_ls180.v:177419$12457_Y - attribute \src "issuer_ls180.v:177403.18-177403.101" - wire $and$issuer_ls180.v:177403$12439_Y - attribute \src "issuer_ls180.v:177418.18-177418.109" - wire $and$issuer_ls180.v:177418$12456_Y - attribute \src "issuer_ls180.v:177427.18-177427.101" - wire $and$issuer_ls180.v:177427$12465_Y - attribute \src "issuer_ls180.v:177428.18-177428.114" - wire width 4 $and$issuer_ls180.v:177428$12466_Y - attribute \src "issuer_ls180.v:177435.18-177435.101" - wire $and$issuer_ls180.v:177435$12473_Y - attribute \src "issuer_ls180.v:177438.18-177438.101" - wire $and$issuer_ls180.v:177438$12476_Y - attribute \src "issuer_ls180.v:177441.18-177441.101" - wire $and$issuer_ls180.v:177441$12479_Y - attribute \src "issuer_ls180.v:177444.18-177444.101" - wire $and$issuer_ls180.v:177444$12482_Y - attribute \src "issuer_ls180.v:177447.18-177447.101" - wire $and$issuer_ls180.v:177447$12485_Y - attribute \src "issuer_ls180.v:177452.18-177452.101" - wire $and$issuer_ls180.v:177452$12490_Y - attribute \src "issuer_ls180.v:177456.18-177456.101" - wire $and$issuer_ls180.v:177456$12494_Y - attribute \src "issuer_ls180.v:177411.19-177411.114" - wire width 64 $extend$issuer_ls180.v:177411$12447_Y - attribute \src "issuer_ls180.v:177412.19-177412.113" - wire width 64 $extend$issuer_ls180.v:177412$12449_Y - attribute \src "issuer_ls180.v:177405.19-177405.111" - wire width 7 $mul$issuer_ls180.v:177405$12441_Y - attribute \src "issuer_ls180.v:177407.19-177407.111" - wire width 7 $mul$issuer_ls180.v:177407$12443_Y - attribute \src "issuer_ls180.v:177410.19-177410.123" - wire $ne$issuer_ls180.v:177410$12446_Y - attribute \src "issuer_ls180.v:177416.18-177416.102" - wire $ne$issuer_ls180.v:177416$12454_Y - attribute \src "issuer_ls180.v:177448.17-177448.101" - wire $ne$issuer_ls180.v:177448$12486_Y - attribute \src "issuer_ls180.v:177404.19-177404.100" - wire $not$issuer_ls180.v:177404$12440_Y - attribute \src "issuer_ls180.v:177417.18-177417.103" - wire $not$issuer_ls180.v:177417$12455_Y - attribute \src "issuer_ls180.v:177420.18-177420.98" - wire $not$issuer_ls180.v:177420$12458_Y - attribute \src "issuer_ls180.v:177421.18-177421.106" - wire $not$issuer_ls180.v:177421$12459_Y - attribute \src "issuer_ls180.v:177422.18-177422.101" - wire $not$issuer_ls180.v:177422$12460_Y - attribute \src "issuer_ls180.v:177423.18-177423.106" - wire $not$issuer_ls180.v:177423$12461_Y - attribute \src "issuer_ls180.v:177424.18-177424.101" - wire $not$issuer_ls180.v:177424$12462_Y - attribute \src "issuer_ls180.v:177425.18-177425.106" - wire $not$issuer_ls180.v:177425$12463_Y - attribute \src "issuer_ls180.v:177426.18-177426.108" - wire $not$issuer_ls180.v:177426$12464_Y - attribute \src "issuer_ls180.v:177430.18-177430.106" - wire $not$issuer_ls180.v:177430$12468_Y - attribute \src "issuer_ls180.v:177431.18-177431.106" - wire $not$issuer_ls180.v:177431$12469_Y - attribute \src "issuer_ls180.v:177432.18-177432.106" - wire $not$issuer_ls180.v:177432$12470_Y - attribute \src "issuer_ls180.v:177433.18-177433.106" - wire $not$issuer_ls180.v:177433$12471_Y - attribute \src "issuer_ls180.v:177434.18-177434.108" - wire $not$issuer_ls180.v:177434$12472_Y - attribute \src "issuer_ls180.v:177436.18-177436.106" - wire $not$issuer_ls180.v:177436$12474_Y - attribute \src "issuer_ls180.v:177437.18-177437.108" - wire $not$issuer_ls180.v:177437$12475_Y - attribute \src "issuer_ls180.v:177439.18-177439.106" - wire $not$issuer_ls180.v:177439$12477_Y - attribute \src "issuer_ls180.v:177440.18-177440.108" - wire $not$issuer_ls180.v:177440$12478_Y - attribute \src "issuer_ls180.v:177442.18-177442.106" - wire $not$issuer_ls180.v:177442$12480_Y - attribute \src "issuer_ls180.v:177443.18-177443.108" - wire $not$issuer_ls180.v:177443$12481_Y - attribute \src "issuer_ls180.v:177445.18-177445.106" - wire $not$issuer_ls180.v:177445$12483_Y - attribute \src "issuer_ls180.v:177446.18-177446.108" - wire $not$issuer_ls180.v:177446$12484_Y - attribute \src "issuer_ls180.v:177449.18-177449.99" - wire $not$issuer_ls180.v:177449$12487_Y - attribute \src "issuer_ls180.v:177450.18-177450.106" - wire $not$issuer_ls180.v:177450$12488_Y - attribute \src "issuer_ls180.v:177451.18-177451.108" - wire $not$issuer_ls180.v:177451$12489_Y - attribute \src "issuer_ls180.v:177453.18-177453.106" - wire $not$issuer_ls180.v:177453$12491_Y - attribute \src "issuer_ls180.v:177454.18-177454.106" - wire $not$issuer_ls180.v:177454$12492_Y - attribute \src "issuer_ls180.v:177455.18-177455.108" - wire $not$issuer_ls180.v:177455$12493_Y - attribute \src "issuer_ls180.v:177457.18-177457.106" - wire $not$issuer_ls180.v:177457$12495_Y - attribute \src "issuer_ls180.v:177458.18-177458.108" - wire $not$issuer_ls180.v:177458$12496_Y - attribute \src "issuer_ls180.v:177415.18-177415.110" - wire $or$issuer_ls180.v:177415$12453_Y - attribute \src "issuer_ls180.v:177411.19-177411.114" - wire width 64 $pos$issuer_ls180.v:177411$12448_Y - attribute \src "issuer_ls180.v:177412.19-177412.113" - wire width 64 $pos$issuer_ls180.v:177412$12450_Y - attribute \src "issuer_ls180.v:177429.18-177429.91" - wire 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"/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - wire \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - wire \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - wire \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - wire \$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - wire \$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:145" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - wire \$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - wire \$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - wire \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - wire \$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - wire \$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - wire \$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - wire \$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" - wire \$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - wire \$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:146" - wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - wire \$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - wire \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - wire \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - wire \$97 - attribute \src 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\initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" - wire width 16 input 58 \int_level_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:85" - wire input 3 \memerr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:192" - wire \msr_read - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:192" - wire \msr_read$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" - wire width 64 \new_dec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:377" - wire width 64 \new_tb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" - wire width 64 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" - wire width 64 \pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:164" - wire \pc_changed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:164" - wire \pc_changed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 59 \pc_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 1 \pc_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:81" - wire width 64 output 2 \pc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174" - wire \pc_ok_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174" - wire \pc_ok_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:139" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr_update_core$next[0:0]$1328 1'0 + case + assign $1\dmi0_datasr_update_core$next[0:0]$1328 \dmi0_datasr_update + end + sync always + update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$1327 + end + connect \$9 $eq$libresoc.v:43573$1024_Y + connect \$99 $ternary$libresoc.v:43574$1025_Y + connect \$101 $ternary$libresoc.v:43575$1026_Y + connect \$103 $ternary$libresoc.v:43576$1027_Y + connect \$105 $ternary$libresoc.v:43577$1028_Y + connect \$107 $ternary$libresoc.v:43578$1029_Y + connect \$109 $ternary$libresoc.v:43579$1030_Y + connect \$111 $ternary$libresoc.v:43580$1031_Y + connect \$113 $ternary$libresoc.v:43581$1032_Y + connect \$115 $ternary$libresoc.v:43582$1033_Y + connect \$117 $ternary$libresoc.v:43583$1034_Y + connect \$11 $eq$libresoc.v:43584$1035_Y + connect \$119 $ternary$libresoc.v:43585$1036_Y + connect \$121 $ternary$libresoc.v:43586$1037_Y + connect \$123 $ternary$libresoc.v:43587$1038_Y + connect \$125 $ternary$libresoc.v:43588$1039_Y + connect \$127 $ternary$libresoc.v:43589$1040_Y + connect \$129 $ternary$libresoc.v:43590$1041_Y + connect \$131 $ternary$libresoc.v:43591$1042_Y + connect \$133 $ternary$libresoc.v:43592$1043_Y + connect \$135 $ternary$libresoc.v:43593$1044_Y + connect \$137 $ternary$libresoc.v:43594$1045_Y + connect \$13 $or$libresoc.v:43595$1046_Y + connect \$139 $ternary$libresoc.v:43596$1047_Y + connect \$141 $eq$libresoc.v:43597$1048_Y + connect \$143 $eq$libresoc.v:43598$1049_Y + connect \$145 $or$libresoc.v:43599$1050_Y + connect \$147 $and$libresoc.v:43600$1051_Y + connect \$149 $eq$libresoc.v:43601$1052_Y + connect \$151 $eq$libresoc.v:43602$1053_Y + connect \$153 $or$libresoc.v:43603$1054_Y + connect \$155 $eq$libresoc.v:43604$1055_Y + connect \$157 $or$libresoc.v:43605$1056_Y + connect \$15 $eq$libresoc.v:43606$1057_Y + connect \$159 $and$libresoc.v:43607$1058_Y + connect \$161 $eq$libresoc.v:43608$1059_Y + connect \$163 $ne$libresoc.v:43609$1060_Y + connect \$165 $and$libresoc.v:43610$1061_Y + connect \$167 $ne$libresoc.v:43611$1062_Y + connect \$169 $and$libresoc.v:43612$1063_Y + connect \$171 $ne$libresoc.v:43613$1064_Y + connect \$173 $and$libresoc.v:43614$1065_Y + connect \$175 $not$libresoc.v:43615$1066_Y + connect \$177 $and$libresoc.v:43616$1067_Y + connect \$17 $or$libresoc.v:43617$1068_Y + connect \$179 $eq$libresoc.v:43618$1069_Y + connect \$181 $ne$libresoc.v:43619$1070_Y + connect \$183 $and$libresoc.v:43620$1071_Y + connect \$185 $ne$libresoc.v:43621$1072_Y + connect \$187 $and$libresoc.v:43622$1073_Y + connect \$189 $ne$libresoc.v:43623$1074_Y + connect \$191 $and$libresoc.v:43624$1075_Y + connect \$193 $not$libresoc.v:43625$1076_Y + connect \$195 $and$libresoc.v:43626$1077_Y + connect \$197 $eq$libresoc.v:43627$1078_Y + connect \$1 $eq$libresoc.v:43628$1079_Y + connect \$19 $and$libresoc.v:43629$1080_Y + connect \$199 $eq$libresoc.v:43630$1081_Y + connect \$201 $ne$libresoc.v:43631$1082_Y + connect \$203 $and$libresoc.v:43632$1083_Y + connect \$205 $ne$libresoc.v:43633$1084_Y + connect \$207 $and$libresoc.v:43634$1085_Y + connect \$209 $ne$libresoc.v:43635$1086_Y + connect \$211 $and$libresoc.v:43636$1087_Y + connect \$213 $not$libresoc.v:43637$1088_Y + connect \$215 $and$libresoc.v:43638$1089_Y + connect \$217 $eq$libresoc.v:43639$1090_Y + connect \$21 $and$libresoc.v:43640$1091_Y + connect \$219 $ne$libresoc.v:43641$1092_Y + connect \$221 $and$libresoc.v:43642$1093_Y + connect \$223 $ne$libresoc.v:43643$1094_Y + connect \$225 $and$libresoc.v:43644$1095_Y + connect \$227 $ne$libresoc.v:43645$1096_Y + connect \$229 $and$libresoc.v:43646$1097_Y + connect \$231 $not$libresoc.v:43647$1098_Y + connect \$233 $and$libresoc.v:43648$1099_Y + connect \$235 $eq$libresoc.v:43649$1100_Y + connect \$237 $eq$libresoc.v:43650$1101_Y + connect \$23 $eq$libresoc.v:43651$1102_Y + connect \$239 $ne$libresoc.v:43652$1103_Y + connect \$241 $and$libresoc.v:43653$1104_Y + connect \$243 $ne$libresoc.v:43654$1105_Y + connect \$245 $and$libresoc.v:43655$1106_Y + connect \$247 $ne$libresoc.v:43656$1107_Y + connect \$249 $and$libresoc.v:43657$1108_Y + connect \$251 $not$libresoc.v:43658$1109_Y + connect \$253 $and$libresoc.v:43659$1110_Y + connect \$256 $eq$libresoc.v:43660$1111_Y + connect \$255 $not$libresoc.v:43661$1112_Y + connect \$25 $eq$libresoc.v:43662$1113_Y + connect \$259 $eq$libresoc.v:43663$1114_Y + connect \$261 $eq$libresoc.v:43664$1115_Y + connect \$263 $or$libresoc.v:43665$1116_Y + connect \$265 $eq$libresoc.v:43666$1117_Y + connect \$268 $add$libresoc.v:43667$1118_Y + connect \$271 $add$libresoc.v:43668$1119_Y + connect \$273 $pos$libresoc.v:43669$1121_Y + connect \$276 $eq$libresoc.v:43670$1122_Y + connect \$278 $eq$libresoc.v:43671$1123_Y + connect \$27 $or$libresoc.v:43672$1124_Y + connect \$280 $or$libresoc.v:43673$1125_Y + connect \$282 $eq$libresoc.v:43674$1126_Y + connect \$285 $add$libresoc.v:43675$1127_Y + connect \$288 $add$libresoc.v:43676$1128_Y + connect \$29 $eq$libresoc.v:43677$1129_Y + connect \$31 $or$libresoc.v:43678$1130_Y + connect \$33 $and$libresoc.v:43679$1131_Y + connect \$35 $and$libresoc.v:43680$1132_Y + connect \$37 $eq$libresoc.v:43681$1133_Y + connect \$3 $eq$libresoc.v:43682$1134_Y + connect \$39 $eq$libresoc.v:43683$1135_Y + connect \$41 $ternary$libresoc.v:43684$1136_Y + connect \$43 $ternary$libresoc.v:43685$1137_Y + connect \$45 $ternary$libresoc.v:43686$1138_Y + connect \$47 $ternary$libresoc.v:43687$1139_Y + connect \$49 $ternary$libresoc.v:43688$1140_Y + connect \$51 $ternary$libresoc.v:43689$1141_Y + connect \$53 $ternary$libresoc.v:43690$1142_Y + connect \$55 $ternary$libresoc.v:43691$1143_Y + connect \$57 $ternary$libresoc.v:43692$1144_Y + connect \$5 $or$libresoc.v:43693$1145_Y + connect \$59 $ternary$libresoc.v:43694$1146_Y + connect \$61 $ternary$libresoc.v:43695$1147_Y + connect \$63 $ternary$libresoc.v:43696$1148_Y + connect \$65 $ternary$libresoc.v:43697$1149_Y + connect \$67 $ternary$libresoc.v:43698$1150_Y + connect \$69 $ternary$libresoc.v:43699$1151_Y + connect \$71 $ternary$libresoc.v:43700$1152_Y + connect \$73 $ternary$libresoc.v:43701$1153_Y + connect \$75 $ternary$libresoc.v:43702$1154_Y + connect \$77 $ternary$libresoc.v:43703$1155_Y + connect \$7 $and$libresoc.v:43704$1156_Y + connect \$79 $ternary$libresoc.v:43705$1157_Y + connect \$81 $ternary$libresoc.v:43706$1158_Y + connect \$83 $ternary$libresoc.v:43707$1159_Y + connect \$85 $ternary$libresoc.v:43708$1160_Y + connect \$87 $ternary$libresoc.v:43709$1161_Y + connect \$89 $ternary$libresoc.v:43710$1162_Y + connect \$91 $ternary$libresoc.v:43711$1163_Y + connect \$93 $ternary$libresoc.v:43712$1164_Y + connect \$95 $ternary$libresoc.v:43713$1165_Y + connect \$97 $ternary$libresoc.v:43714$1166_Y + connect \$267 \$268 + connect \$270 \$271 + connect \$284 \$285 + connect \$287 \$288 + connect \sr0__i \sr0__o + connect \dmi0_we_i \$282 + connect \dmi0_req_i \$280 + connect \dmi0_addrsr__i \$273 + connect \jtag_wb__we \$265 + connect \jtag_wb__stb \$263 + connect \jtag_wb__cyc \$255 + connect \jtag_wb__sel 1'1 + connect \jtag_wb_addrsr__i \jtag_wb__adr + connect \dmi0_datasr_update \$249 + connect \dmi0_datasr_shift \$245 + connect \dmi0_datasr_capture \$241 + connect \dmi0_datasr_isir { \$237 \$235 } + connect \dmi0_datasr__o \dmi0_datasr_reg + connect \dmi0_addrsr_update \$229 + connect \dmi0_addrsr_shift \$225 + connect \dmi0_addrsr_capture \$221 + connect \dmi0_addrsr_isir \$217 + connect \dmi0_addrsr__o \dmi0_addrsr_reg + connect \jtag_wb_datasr_update \$211 + connect \jtag_wb_datasr_shift \$207 + connect \jtag_wb_datasr_capture \$203 + connect \jtag_wb_datasr_isir { \$199 \$197 } + connect \jtag_wb_datasr__o \jtag_wb_datasr_reg + connect \jtag_wb_addrsr_update \$191 + connect \jtag_wb_addrsr_shift \$187 + connect \jtag_wb_addrsr_capture \$183 + connect \jtag_wb_addrsr_isir \$179 + connect \jtag_wb_addrsr__o \jtag_wb_addrsr_reg + connect \sr0_update \$173 + connect \sr0_shift \$169 + connect \sr0_capture \$165 + connect \sr0_isir \$161 + connect \sr0__o \sr0_reg + connect \gpio_gpio15__pad__oe \$139 + connect \gpio_gpio15__pad__o \$137 + connect \gpio_gpio15__core__i \$135 + connect \gpio_gpio14__pad__oe \$133 + connect \gpio_gpio14__pad__o \$131 + connect \gpio_gpio14__core__i \$129 + connect \gpio_gpio13__pad__oe \$127 + connect \gpio_gpio13__pad__o \$125 + connect \gpio_gpio13__core__i \$123 + connect \gpio_gpio12__pad__oe \$121 + connect \gpio_gpio12__pad__o \$119 + connect \gpio_gpio12__core__i \$117 + connect \gpio_gpio11__pad__oe \$115 + connect \gpio_gpio11__pad__o \$113 + connect \gpio_gpio11__core__i \$111 + connect \gpio_gpio10__pad__oe \$109 + connect \gpio_gpio10__pad__o \$107 + connect \gpio_gpio10__core__i \$105 + connect \gpio_gpio9__pad__oe \$103 + connect \gpio_gpio9__pad__o \$101 + connect \gpio_gpio9__core__i \$99 + connect \gpio_gpio8__pad__oe \$97 + connect \gpio_gpio8__pad__o \$95 + connect \gpio_gpio8__core__i \$93 + connect \gpio_gpio7__pad__oe \$91 + connect \gpio_gpio7__pad__o \$89 + connect \gpio_gpio7__core__i \$87 + connect \gpio_gpio6__pad__oe \$85 + connect \gpio_gpio6__pad__o \$83 + connect \gpio_gpio6__core__i \$81 + connect \gpio_gpio5__pad__oe \$79 + connect \gpio_gpio5__pad__o \$77 + connect \gpio_gpio5__core__i \$75 + connect \gpio_gpio4__pad__oe \$73 + connect \gpio_gpio4__pad__o \$71 + connect \gpio_gpio4__core__i \$69 + connect \gpio_gpio3__pad__oe \$67 + connect \gpio_gpio3__pad__o \$65 + connect \gpio_gpio3__core__i \$63 + connect \gpio_gpio2__pad__oe \$61 + connect \gpio_gpio2__pad__o \$59 + connect \gpio_gpio2__core__i \$57 + connect \gpio_gpio1__pad__oe \$55 + connect \gpio_gpio1__pad__o \$53 + connect \gpio_gpio1__core__i \$51 + connect \gpio_gpio0__pad__oe \$49 + connect \gpio_gpio0__pad__o \$47 + connect \gpio_gpio0__core__i \$45 + connect \uart_rx__core__i \$43 + connect \uart_tx__pad__o \$41 + connect \io_bd2core \$39 + connect \io_bd2io \$37 + connect \io_update \$35 + connect \io_shift \$21 + connect \io_capture \$7 +end +attribute \src "ls180.v:4.1-10286.10" +attribute \cells_not_processed 1 +module \ls180 + attribute \src "ls180.v:9981.1-9991.4" + wire width 7 $0$memwr$\mem$ls180.v:9983$1_ADDR[6:0]$2685 + attribute \src "ls180.v:9981.1-9991.4" + wire width 32 $0$memwr$\mem$ls180.v:9983$1_DATA[31:0]$2686 + attribute \src "ls180.v:9981.1-9991.4" + wire width 32 $0$memwr$\mem$ls180.v:9983$1_EN[31:0]$2687 + attribute \src "ls180.v:9981.1-9991.4" + wire width 7 $0$memwr$\mem$ls180.v:9985$2_ADDR[6:0]$2688 + attribute \src "ls180.v:9981.1-9991.4" + wire width 32 $0$memwr$\mem$ls180.v:9985$2_DATA[31:0]$2689 + attribute \src "ls180.v:9981.1-9991.4" + wire width 32 $0$memwr$\mem$ls180.v:9985$2_EN[31:0]$2690 + attribute \src "ls180.v:9981.1-9991.4" + wire width 7 $0$memwr$\mem$ls180.v:9987$3_ADDR[6:0]$2691 + attribute \src "ls180.v:9981.1-9991.4" + wire width 32 $0$memwr$\mem$ls180.v:9987$3_DATA[31:0]$2692 + attribute \src "ls180.v:9981.1-9991.4" + wire width 32 $0$memwr$\mem$ls180.v:9987$3_EN[31:0]$2693 + attribute \src "ls180.v:9981.1-9991.4" + wire width 7 $0$memwr$\mem$ls180.v:9989$4_ADDR[6:0]$2694 + attribute \src "ls180.v:9981.1-9991.4" + wire width 32 $0$memwr$\mem$ls180.v:9989$4_DATA[31:0]$2695 + attribute \src "ls180.v:9981.1-9991.4" + wire width 32 $0$memwr$\mem$ls180.v:9989$4_EN[31:0]$2696 + attribute \src "ls180.v:10001.1-10005.4" + wire width 3 $0$memwr$\storage$ls180.v:10003$5_ADDR[2:0]$2699 + attribute \src "ls180.v:10001.1-10005.4" + wire width 25 $0$memwr$\storage$ls180.v:10003$5_DATA[24:0]$2700 + attribute \src "ls180.v:10001.1-10005.4" + wire width 25 $0$memwr$\storage$ls180.v:10003$5_EN[24:0]$2701 + attribute \src "ls180.v:10015.1-10019.4" + wire width 3 $0$memwr$\storage_1$ls180.v:10017$6_ADDR[2:0]$2706 + attribute \src "ls180.v:10015.1-10019.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10017$6_DATA[24:0]$2707 + attribute \src "ls180.v:10015.1-10019.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10017$6_EN[24:0]$2708 + attribute \src "ls180.v:10029.1-10033.4" + wire width 3 $0$memwr$\storage_2$ls180.v:10031$7_ADDR[2:0]$2713 + attribute \src "ls180.v:10029.1-10033.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10031$7_DATA[24:0]$2714 + attribute \src "ls180.v:10029.1-10033.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10031$7_EN[24:0]$2715 + attribute \src "ls180.v:10043.1-10047.4" + wire width 3 $0$memwr$\storage_3$ls180.v:10045$8_ADDR[2:0]$2720 + attribute \src "ls180.v:10043.1-10047.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10045$8_DATA[24:0]$2721 + attribute \src "ls180.v:10043.1-10047.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10045$8_EN[24:0]$2722 + attribute \src "ls180.v:10058.1-10062.4" + wire width 4 $0$memwr$\storage_4$ls180.v:10060$9_ADDR[3:0]$2727 + attribute \src "ls180.v:10058.1-10062.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10060$9_DATA[9:0]$2728 + attribute \src "ls180.v:10058.1-10062.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10060$9_EN[9:0]$2729 + attribute \src "ls180.v:10075.1-10079.4" + wire width 4 $0$memwr$\storage_5$ls180.v:10077$10_ADDR[3:0]$2734 + attribute \src "ls180.v:10075.1-10079.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10077$10_DATA[9:0]$2735 + attribute \src "ls180.v:10075.1-10079.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10077$10_EN[9:0]$2736 + attribute \src "ls180.v:10091.1-10095.4" + wire width 5 $0$memwr$\storage_6$ls180.v:10093$11_ADDR[4:0]$2741 + attribute \src "ls180.v:10091.1-10095.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10093$11_DATA[9:0]$2742 + attribute \src "ls180.v:10091.1-10095.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10093$11_EN[9:0]$2743 + attribute \src "ls180.v:10105.1-10109.4" + wire width 5 $0$memwr$\storage_7$ls180.v:10107$12_ADDR[4:0]$2748 + attribute \src "ls180.v:10105.1-10109.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10107$12_DATA[9:0]$2749 + attribute \src "ls180.v:10105.1-10109.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10107$12_EN[9:0]$2750 + attribute \src "ls180.v:3179.1-3272.4" + wire width 3 $0\builder_bankmachine0_next_state[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\builder_bankmachine0_state[2:0] + attribute \src "ls180.v:3336.1-3429.4" + wire width 3 $0\builder_bankmachine1_next_state[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\builder_bankmachine1_state[2:0] + attribute \src "ls180.v:3493.1-3586.4" + wire width 3 $0\builder_bankmachine2_next_state[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\builder_bankmachine2_state[2:0] + attribute \src "ls180.v:3650.1-3743.4" + wire width 3 $0\builder_bankmachine3_next_state[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\builder_bankmachine3_state[2:0] + attribute \src "ls180.v:6452.1-6468.4" + wire $0\builder_comb_rhs_array_muxed0[0:0] + attribute \src "ls180.v:6673.1-6689.4" + wire $0\builder_comb_rhs_array_muxed10[0:0] + attribute \src "ls180.v:6690.1-6706.4" + wire $0\builder_comb_rhs_array_muxed11[0:0] + attribute \src "ls180.v:6758.1-6765.4" + wire width 22 $0\builder_comb_rhs_array_muxed12[21:0] + attribute \src "ls180.v:6766.1-6773.4" + wire $0\builder_comb_rhs_array_muxed13[0:0] + attribute \src "ls180.v:6774.1-6781.4" + wire $0\builder_comb_rhs_array_muxed14[0:0] + attribute \src "ls180.v:6782.1-6789.4" + wire width 22 $0\builder_comb_rhs_array_muxed15[21:0] + attribute \src "ls180.v:6790.1-6797.4" + wire $0\builder_comb_rhs_array_muxed16[0:0] + attribute \src "ls180.v:6798.1-6805.4" + wire $0\builder_comb_rhs_array_muxed17[0:0] + attribute \src "ls180.v:6806.1-6813.4" + wire width 22 $0\builder_comb_rhs_array_muxed18[21:0] + attribute \src "ls180.v:6814.1-6821.4" + wire $0\builder_comb_rhs_array_muxed19[0:0] + attribute \src "ls180.v:6469.1-6485.4" + wire width 13 $0\builder_comb_rhs_array_muxed1[12:0] + attribute \src "ls180.v:6822.1-6829.4" + wire $0\builder_comb_rhs_array_muxed20[0:0] + attribute \src "ls180.v:6830.1-6837.4" + wire width 22 $0\builder_comb_rhs_array_muxed21[21:0] + attribute \src "ls180.v:6838.1-6845.4" + wire $0\builder_comb_rhs_array_muxed22[0:0] + attribute \src "ls180.v:6846.1-6853.4" + wire $0\builder_comb_rhs_array_muxed23[0:0] + attribute \src "ls180.v:6854.1-6873.4" + wire width 32 $0\builder_comb_rhs_array_muxed24[31:0] + attribute \src "ls180.v:6874.1-6893.4" + wire width 32 $0\builder_comb_rhs_array_muxed25[31:0] + attribute \src "ls180.v:6894.1-6913.4" + wire width 4 $0\builder_comb_rhs_array_muxed26[3:0] + attribute \src "ls180.v:6914.1-6933.4" + wire $0\builder_comb_rhs_array_muxed27[0:0] + attribute \src "ls180.v:6934.1-6953.4" + wire $0\builder_comb_rhs_array_muxed28[0:0] + attribute \src "ls180.v:6954.1-6973.4" + wire $0\builder_comb_rhs_array_muxed29[0:0] + attribute \src "ls180.v:6486.1-6502.4" + wire width 2 $0\builder_comb_rhs_array_muxed2[1:0] + attribute \src "ls180.v:6974.1-6993.4" + wire width 3 $0\builder_comb_rhs_array_muxed30[2:0] + attribute \src "ls180.v:6994.1-7013.4" + wire width 2 $0\builder_comb_rhs_array_muxed31[1:0] + attribute \src "ls180.v:6503.1-6519.4" + wire $0\builder_comb_rhs_array_muxed3[0:0] + attribute \src "ls180.v:6520.1-6536.4" + wire $0\builder_comb_rhs_array_muxed4[0:0] + attribute \src "ls180.v:6537.1-6553.4" + wire $0\builder_comb_rhs_array_muxed5[0:0] + attribute \src "ls180.v:6605.1-6621.4" + wire $0\builder_comb_rhs_array_muxed6[0:0] + attribute \src "ls180.v:6622.1-6638.4" + wire width 13 $0\builder_comb_rhs_array_muxed7[12:0] + attribute \src "ls180.v:6639.1-6655.4" + wire width 2 $0\builder_comb_rhs_array_muxed8[1:0] + attribute \src "ls180.v:6656.1-6672.4" + wire $0\builder_comb_rhs_array_muxed9[0:0] + attribute \src "ls180.v:6554.1-6570.4" + wire $0\builder_comb_t_array_muxed0[0:0] + attribute \src "ls180.v:6571.1-6587.4" + wire $0\builder_comb_t_array_muxed1[0:0] + attribute \src "ls180.v:6588.1-6604.4" + wire $0\builder_comb_t_array_muxed2[0:0] + attribute \src "ls180.v:6707.1-6723.4" + wire $0\builder_comb_t_array_muxed3[0:0] + attribute \src "ls180.v:6724.1-6740.4" + wire $0\builder_comb_t_array_muxed4[0:0] + attribute \src "ls180.v:6741.1-6757.4" + wire $0\builder_comb_t_array_muxed5[0:0] + attribute \src "ls180.v:2738.1-2784.4" + wire $0\builder_converter0_next_state[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_converter0_state[0:0] + attribute \src "ls180.v:2798.1-2844.4" + wire $0\builder_converter1_next_state[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_converter1_state[0:0] + attribute \src "ls180.v:2858.1-2904.4" + wire $0\builder_converter2_next_state[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_converter2_state[0:0] + attribute \src "ls180.v:3996.1-4042.4" + wire $0\builder_converter_next_state[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_converter_state[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 20 $0\builder_count[19:0] + attribute \src "ls180.v:5709.1-5720.4" + wire $0\builder_error[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\builder_grant[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 14 $0\builder_libresocsim_adr[13:0] + attribute \src "ls180.v:5598.1-5634.4" + wire width 14 $0\builder_libresocsim_adr_next_value1[13:0] + attribute \src "ls180.v:5598.1-5634.4" + wire $0\builder_libresocsim_adr_next_value_ce1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\builder_libresocsim_dat_w[7:0] + attribute \src "ls180.v:5598.1-5634.4" + wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0] + attribute \src "ls180.v:5598.1-5634.4" + wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_libresocsim_we[0:0] + attribute \src "ls180.v:5598.1-5634.4" + wire $0\builder_libresocsim_we_next_value2[0:0] + attribute \src "ls180.v:5598.1-5634.4" + wire $0\builder_libresocsim_we_next_value_ce2[0:0] + attribute \src "ls180.v:5598.1-5634.4" + wire $0\builder_libresocsim_wishbone_ack[0:0] + attribute \src "ls180.v:5598.1-5634.4" + wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0] + attribute \src "ls180.v:1842.5-1842.44" + wire $0\builder_libresocsim_wishbone_err[0:0] + attribute \src "ls180.v:1731.5-1731.27" + wire $0\builder_locked0[0:0] + attribute \src "ls180.v:1732.5-1732.27" + wire $0\builder_locked1[0:0] + attribute \src "ls180.v:1733.5-1733.27" + wire $0\builder_locked2[0:0] + attribute \src "ls180.v:1734.5-1734.27" + wire $0\builder_locked3[0:0] + attribute \src "ls180.v:3868.1-3940.4" + wire width 3 $0\builder_multiplexer_next_state[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\builder_multiplexer_state[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl0_regs0[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl0_regs1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl10_regs0[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl10_regs1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl11_regs0[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl11_regs1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl12_regs0[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl12_regs1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl13_regs0[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl13_regs1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl14_regs0[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl14_regs1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl15_regs0[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl15_regs1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl16_regs0[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl16_regs1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl1_regs0[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl1_regs1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl2_regs0[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl2_regs1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl3_regs0[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl3_regs1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl4_regs0[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl4_regs1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl5_regs0[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl5_regs1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl6_regs0[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl6_regs1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl7_regs0[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl7_regs1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl8_regs0[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl8_regs1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl9_regs0[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_multiregimpl9_regs1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_new_master_rdata_valid0[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_new_master_rdata_valid1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_new_master_rdata_valid2[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_new_master_rdata_valid3[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_new_master_wdata_ready[0:0] + attribute \src "ls180.v:5598.1-5634.4" + wire width 2 $0\builder_next_state[1:0] + attribute \src "ls180.v:3085.1-3115.4" + wire width 2 $0\builder_refresher_next_state[1:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 2 $0\builder_refresher_state[1:0] + attribute \src "ls180.v:5349.1-5388.4" + wire width 2 $0\builder_sdblock2memdma_next_state[1:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 2 $0\builder_sdblock2memdma_state[1:0] + attribute \src "ls180.v:4916.1-4995.4" + wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_sdcore_crcupstreaminserter_state[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire width 3 $0\builder_sdcore_fsm_next_state[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\builder_sdcore_fsm_state[2:0] + attribute \src "ls180.v:5408.1-5445.4" + wire $0\builder_sdmem2blockdma_fsm_next_state[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_sdmem2blockdma_fsm_state[0:0] + attribute \src "ls180.v:5446.1-5482.4" + wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0] + attribute \src "ls180.v:4591.1-4663.4" + wire width 3 $0\builder_sdphy_fsm_next_state[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\builder_sdphy_fsm_state[2:0] + attribute \src "ls180.v:4436.1-4529.4" + wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0] + attribute \src "ls180.v:4326.1-4402.4" + wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0] + attribute \src "ls180.v:4563.1-4590.4" + wire $0\builder_sdphy_sdphycrcr_next_state[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_sdphy_sdphycrcr_state[0:0] + attribute \src "ls180.v:4697.1-4798.4" + wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\builder_sdphy_sdphydatar_state[2:0] + attribute \src "ls180.v:4292.1-4325.4" + wire $0\builder_sdphy_sdphyinit_next_state[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\builder_sdphy_sdphyinit_state[0:0] + attribute \src "ls180.v:5709.1-5720.4" + wire $0\builder_shared_ack[0:0] + attribute \src "ls180.v:5709.1-5720.4" + wire width 32 $0\builder_shared_dat_r[31:0] + attribute \src "ls180.v:5659.1-5666.4" + wire width 5 $0\builder_slave_sel[4:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 5 $0\builder_slave_sel_r[4:0] + attribute \src "ls180.v:4186.1-4234.4" + wire width 2 $0\builder_spimaster0_next_state[1:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 2 $0\builder_spimaster0_state[1:0] + attribute \src "ls180.v:5549.1-5597.4" + wire width 2 $0\builder_spimaster1_next_state[1:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 2 $0\builder_spimaster1_state[1:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 2 $0\builder_state[1:0] + attribute \src "ls180.v:7133.1-7161.4" + wire $0\builder_sync_f_array_muxed0[0:0] + attribute \src "ls180.v:7162.1-7190.4" + wire $0\builder_sync_f_array_muxed1[0:0] + attribute \src "ls180.v:7014.1-7030.4" + wire width 2 $0\builder_sync_rhs_array_muxed0[1:0] + attribute \src "ls180.v:7031.1-7047.4" + wire width 13 $0\builder_sync_rhs_array_muxed1[12:0] + attribute \src "ls180.v:7048.1-7064.4" + wire $0\builder_sync_rhs_array_muxed2[0:0] + attribute \src "ls180.v:7065.1-7081.4" + wire $0\builder_sync_rhs_array_muxed3[0:0] + attribute \src "ls180.v:7082.1-7098.4" + wire $0\builder_sync_rhs_array_muxed4[0:0] + attribute \src "ls180.v:7099.1-7115.4" + wire $0\builder_sync_rhs_array_muxed5[0:0] + attribute \src "ls180.v:7116.1-7132.4" + wire $0\builder_sync_rhs_array_muxed6[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\libresocsim_clk_divider1[15:0] + attribute \src "ls180.v:5549.1-5597.4" + wire $0\libresocsim_clk_enable[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\libresocsim_control_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\libresocsim_control_storage[15:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\libresocsim_count[2:0] + attribute \src "ls180.v:5549.1-5597.4" + wire width 3 $0\libresocsim_count_spimaster1_next_value[2:0] + attribute \src "ls180.v:5549.1-5597.4" + wire $0\libresocsim_count_spimaster1_next_value_ce[0:0] + attribute \src "ls180.v:5549.1-5597.4" + wire $0\libresocsim_cs_enable[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\libresocsim_cs_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\libresocsim_cs_storage[0:0] + attribute \src "ls180.v:5549.1-5597.4" + wire $0\libresocsim_done0[0:0] + attribute \src "ls180.v:5549.1-5597.4" + wire $0\libresocsim_irq[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\libresocsim_loopback_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\libresocsim_loopback_storage[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\libresocsim_miso[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\libresocsim_miso_data[7:0] + attribute \src "ls180.v:5549.1-5597.4" + wire $0\libresocsim_miso_latch[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\libresocsim_mosi_data[7:0] + attribute \src "ls180.v:5549.1-5597.4" + wire $0\libresocsim_mosi_latch[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\libresocsim_mosi_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\libresocsim_mosi_sel[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\libresocsim_mosi_storage[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\libresocsim_re[0:0] + attribute \src "ls180.v:6266.1-6271.4" + wire $0\libresocsim_start1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\libresocsim_storage[15:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_cmd_consumed[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_converter_counter[0:0] + attribute \src "ls180.v:3996.1-4042.4" + wire $0\main_converter_counter_converter_next_value[0:0] + attribute \src "ls180.v:3996.1-4042.4" + wire $0\main_converter_counter_converter_next_value_ce[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_converter_dat_r[31:0] + attribute \src "ls180.v:3996.1-4042.4" + wire $0\main_converter_skip[0:0] + attribute \src "ls180.v:7289.1-7357.4" + wire width 16 $0\main_dfi_p0_rddata[15:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_dfi_p0_rddata_valid[0:0] + attribute \src "ls180.v:2931.1-2935.4" + wire width 2 $0\main_dm[1:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 43 $0\main_dummy[42:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_gpio_oe_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_gpio_oe_storage[15:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_gpio_out_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_gpio_out_storage[15:0] + attribute \src "ls180.v:7246.1-7264.4" + wire width 16 $0\main_gpio_status[15:0] + attribute \src "ls180.v:7285.1-7287.4" + wire $0\main_int_rst[0:0] + attribute \src "ls180.v:1481.11-1481.41" + wire width 2 $0\main_interface0_bus_bte[1:0] + attribute \src "ls180.v:1480.11-1480.41" + wire width 3 $0\main_interface0_bus_cti[2:0] + attribute \src "ls180.v:5408.1-5445.4" + wire width 32 $0\main_interface1_bus_adr[31:0] + attribute \src "ls180.v:1572.11-1572.41" + wire width 2 $0\main_interface1_bus_bte[1:0] + attribute \src "ls180.v:1571.11-1571.41" + wire width 3 $0\main_interface1_bus_cti[2:0] + attribute \src "ls180.v:5408.1-5445.4" + wire $0\main_interface1_bus_cyc[0:0] + attribute \src "ls180.v:1564.12-1564.45" + wire width 32 $0\main_interface1_bus_dat_w[31:0] + attribute \src "ls180.v:5408.1-5445.4" + wire width 4 $0\main_interface1_bus_sel[3:0] + attribute \src "ls180.v:5408.1-5445.4" + wire $0\main_interface1_bus_stb[0:0] + attribute \src "ls180.v:5408.1-5445.4" + wire $0\main_interface1_bus_we[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_libresocsim_bus_errors[31:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_libresocsim_converter0_counter[0:0] + attribute \src "ls180.v:2738.1-2784.4" + wire $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] + attribute \src "ls180.v:2738.1-2784.4" + wire $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 64 $0\main_libresocsim_converter0_dat_r[63:0] + attribute \src "ls180.v:2738.1-2784.4" + wire $0\main_libresocsim_converter0_skip[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_libresocsim_converter1_counter[0:0] + attribute \src "ls180.v:2798.1-2844.4" + wire $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] + attribute \src "ls180.v:2798.1-2844.4" + wire $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 64 $0\main_libresocsim_converter1_dat_r[63:0] + attribute \src "ls180.v:2798.1-2844.4" + wire $0\main_libresocsim_converter1_skip[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_libresocsim_converter2_counter[0:0] + attribute \src "ls180.v:2858.1-2904.4" + wire $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] + attribute \src "ls180.v:2858.1-2904.4" + wire $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 64 $0\main_libresocsim_converter2_dat_r[63:0] + attribute \src "ls180.v:2858.1-2904.4" + wire $0\main_libresocsim_converter2_skip[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_libresocsim_en_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_libresocsim_en_storage[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_libresocsim_eventmanager_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_libresocsim_eventmanager_storage[0:0] + attribute \src "ls180.v:2738.1-2784.4" + wire width 30 $0\main_libresocsim_interface0_converted_interface_adr[29:0] + attribute \src "ls180.v:139.11-139.69" + wire width 2 $0\main_libresocsim_interface0_converted_interface_bte[1:0] + attribute \src "ls180.v:138.11-138.69" + wire width 3 $0\main_libresocsim_interface0_converted_interface_cti[2:0] + attribute \src "ls180.v:2738.1-2784.4" + wire $0\main_libresocsim_interface0_converted_interface_cyc[0:0] + attribute \src "ls180.v:2726.1-2736.4" + wire width 32 $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] + attribute \src "ls180.v:2738.1-2784.4" + wire width 4 $0\main_libresocsim_interface0_converted_interface_sel[3:0] + attribute \src "ls180.v:2738.1-2784.4" + wire $0\main_libresocsim_interface0_converted_interface_stb[0:0] + attribute \src "ls180.v:2738.1-2784.4" + wire $0\main_libresocsim_interface0_converted_interface_we[0:0] + attribute \src "ls180.v:2798.1-2844.4" + wire width 30 $0\main_libresocsim_interface1_converted_interface_adr[29:0] + attribute \src "ls180.v:154.11-154.69" + wire width 2 $0\main_libresocsim_interface1_converted_interface_bte[1:0] + attribute \src "ls180.v:153.11-153.69" + wire width 3 $0\main_libresocsim_interface1_converted_interface_cti[2:0] + attribute \src "ls180.v:2798.1-2844.4" + wire $0\main_libresocsim_interface1_converted_interface_cyc[0:0] + attribute \src "ls180.v:2786.1-2796.4" + wire width 32 $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] + attribute \src "ls180.v:2798.1-2844.4" + wire width 4 $0\main_libresocsim_interface1_converted_interface_sel[3:0] + attribute \src "ls180.v:2798.1-2844.4" + wire $0\main_libresocsim_interface1_converted_interface_stb[0:0] + attribute \src "ls180.v:2798.1-2844.4" + wire $0\main_libresocsim_interface1_converted_interface_we[0:0] + attribute \src "ls180.v:2858.1-2904.4" + wire width 30 $0\main_libresocsim_interface2_converted_interface_adr[29:0] + attribute \src "ls180.v:169.11-169.69" + wire width 2 $0\main_libresocsim_interface2_converted_interface_bte[1:0] + attribute \src "ls180.v:168.11-168.69" + wire width 3 $0\main_libresocsim_interface2_converted_interface_cti[2:0] + attribute \src "ls180.v:2858.1-2904.4" + wire $0\main_libresocsim_interface2_converted_interface_cyc[0:0] + attribute \src "ls180.v:2846.1-2856.4" + wire width 32 $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] + attribute \src "ls180.v:2858.1-2904.4" + wire width 4 $0\main_libresocsim_interface2_converted_interface_sel[3:0] + attribute \src "ls180.v:2858.1-2904.4" + wire $0\main_libresocsim_interface2_converted_interface_stb[0:0] + attribute \src "ls180.v:2858.1-2904.4" + wire $0\main_libresocsim_interface2_converted_interface_we[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] + attribute \src "ls180.v:2798.1-2844.4" + wire $0\main_libresocsim_libresoc_dbus_ack[0:0] + attribute \src "ls180.v:70.5-70.46" + wire $0\main_libresocsim_libresoc_dbus_err[0:0] + attribute \src "ls180.v:2738.1-2784.4" + wire $0\main_libresocsim_libresoc_ibus_ack[0:0] + attribute \src "ls180.v:81.5-81.46" + wire $0\main_libresocsim_libresoc_ibus_err[0:0] + attribute \src "ls180.v:2719.1-2724.4" + wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0] + attribute \src "ls180.v:2858.1-2904.4" + wire $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] + attribute \src "ls180.v:112.5-112.49" + wire $0\main_libresocsim_libresoc_jtag_wb_err[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_libresocsim_load_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_libresocsim_load_storage[31:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_libresocsim_ram_bus_ack[0:0] + attribute \src "ls180.v:185.5-185.40" + wire $0\main_libresocsim_ram_bus_err[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_libresocsim_reload_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_libresocsim_reload_storage[31:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_libresocsim_reset_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_libresocsim_reset_storage[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_libresocsim_scratch_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_libresocsim_scratch_storage[31:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_libresocsim_update_value_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_libresocsim_update_value_storage[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_libresocsim_value[31:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_libresocsim_value_status[31:0] + attribute \src "ls180.v:2907.1-2913.4" + wire width 4 $0\main_libresocsim_we[3:0] + attribute \src "ls180.v:2919.1-2924.4" + wire $0\main_libresocsim_zero_clear[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_libresocsim_zero_old_trigger[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_libresocsim_zero_pending[0:0] + attribute \src "ls180.v:3996.1-4042.4" + wire width 30 $0\main_litedram_wb_adr[29:0] + attribute \src "ls180.v:3996.1-4042.4" + wire $0\main_litedram_wb_cyc[0:0] + attribute \src "ls180.v:3984.1-3994.4" + wire width 16 $0\main_litedram_wb_dat_w[15:0] + attribute \src "ls180.v:3996.1-4042.4" + wire width 2 $0\main_litedram_wb_sel[1:0] + attribute \src "ls180.v:3996.1-4042.4" + wire $0\main_litedram_wb_stb[0:0] + attribute \src "ls180.v:3996.1-4042.4" + wire $0\main_litedram_wb_we[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_phase_accumulator_rx[31:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_phase_accumulator_tx[31:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_pwm0_counter[31:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_pwm0_enable_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_pwm0_enable_storage[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_pwm0_period_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_pwm0_period_storage[31:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_pwm0_width_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_pwm0_width_storage[31:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_pwm1_counter[31:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_pwm1_enable_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_pwm1_enable_storage[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_pwm1_period_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_pwm1_period_storage[31:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_pwm1_width_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_pwm1_width_storage[31:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\main_rddata_en[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 4 $0\main_rx_bitcount[3:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_rx_busy[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_rx_r[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\main_rx_reg[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 2 $0\main_sdblock2mem_converter_demux[1:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdblock2mem_converter_source_first[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdblock2mem_converter_source_last[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_sdblock2mem_converter_source_payload_data[31:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdblock2mem_converter_strobe_all[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 5 $0\main_sdblock2mem_fifo_consume[4:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 6 $0\main_sdblock2mem_fifo_level[5:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 5 $0\main_sdblock2mem_fifo_produce[4:0] + attribute \src "ls180.v:1505.5-1505.41" + wire $0\main_sdblock2mem_fifo_replace[0:0] + attribute \src "ls180.v:5316.1-5323.4" + wire width 5 $0\main_sdblock2mem_fifo_wrport_adr[4:0] + attribute \src "ls180.v:5349.1-5388.4" + wire width 32 $0\main_sdblock2mem_sink_sink_payload_address[31:0] + attribute \src "ls180.v:5349.1-5388.4" + wire width 32 $0\main_sdblock2mem_sink_sink_payload_data1[31:0] + attribute \src "ls180.v:5349.1-5388.4" + wire $0\main_sdblock2mem_sink_sink_valid1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] + attribute \src "ls180.v:5349.1-5388.4" + wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + attribute \src "ls180.v:5349.1-5388.4" + wire $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + attribute \src "ls180.v:5349.1-5388.4" + wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + attribute \src "ls180.v:5349.1-5388.4" + wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdcore_block_count_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_sdcore_block_count_storage[31:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdcore_block_length_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 10 $0\main_sdcore_block_length_storage[9:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdcore_cmd_argument_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_sdcore_cmd_argument_storage[31:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdcore_cmd_command_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_sdcore_cmd_command_storage[31:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\main_sdcore_cmd_count[2:0] + attribute \src "ls180.v:5098.1-5288.4" + wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdcore_cmd_done[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdcore_cmd_error[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 128 $0\main_sdcore_cmd_response_status[127:0] + attribute \src "ls180.v:5098.1-5288.4" + wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + attribute \src "ls180.v:1314.5-1314.34" + wire $0\main_sdcore_cmd_send_w[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdcore_cmd_timeout[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0] + attribute \src "ls180.v:5004.1-5011.4" + wire $0\main_sdcore_crc16_checker_crc0_clr[0:0] + attribute \src "ls180.v:5060.1-5067.4" + wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + attribute \src "ls180.v:5014.1-5021.4" + wire $0\main_sdcore_crc16_checker_crc1_clr[0:0] + attribute \src "ls180.v:5070.1-5077.4" + wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + attribute \src "ls180.v:5024.1-5031.4" + wire $0\main_sdcore_crc16_checker_crc2_clr[0:0] + attribute \src "ls180.v:5080.1-5087.4" + wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + attribute \src "ls180.v:5034.1-5041.4" + wire $0\main_sdcore_crc16_checker_crc3_clr[0:0] + attribute \src "ls180.v:5090.1-5097.4" + wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdcore_crc16_checker_sink_first[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdcore_crc16_checker_sink_last[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire width 8 $0\main_sdcore_crc16_checker_sink_payload_data[7:0] + attribute \src "ls180.v:5049.1-5056.4" + wire $0\main_sdcore_crc16_checker_sink_ready[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdcore_crc16_checker_sink_valid[0:0] + attribute \src "ls180.v:1420.5-1420.50" + wire $0\main_sdcore_crc16_checker_source_first[0:0] + attribute \src "ls180.v:5043.1-5048.4" + wire $0\main_sdcore_crc16_checker_source_valid[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\main_sdcore_crc16_checker_val[7:0] + attribute \src "ls180.v:4996.1-5001.4" + wire $0\main_sdcore_crc16_checker_valid[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0] + attribute \src "ls180.v:4916.1-4995.4" + wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + attribute \src "ls180.v:4916.1-4995.4" + wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + attribute \src "ls180.v:4878.1-4885.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + attribute \src "ls180.v:4888.1-4895.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + attribute \src "ls180.v:4898.1-4905.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + attribute \src "ls180.v:4908.1-4915.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0] + attribute \src "ls180.v:4916.1-4995.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + attribute \src "ls180.v:4916.1-4995.4" + wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0] + attribute \src "ls180.v:4916.1-4995.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + attribute \src "ls180.v:4916.1-4995.4" + wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0] + attribute \src "ls180.v:4916.1-4995.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + attribute \src "ls180.v:4916.1-4995.4" + wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0] + attribute \src "ls180.v:4916.1-4995.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + attribute \src "ls180.v:4916.1-4995.4" + wire $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + attribute \src "ls180.v:4916.1-4995.4" + wire $0\main_sdcore_crc16_inserter_sink_ready[0:0] + attribute \src "ls180.v:1377.5-1377.51" + wire $0\main_sdcore_crc16_inserter_source_first[0:0] + attribute \src "ls180.v:4916.1-4995.4" + wire $0\main_sdcore_crc16_inserter_source_last[0:0] + attribute \src "ls180.v:4916.1-4995.4" + wire width 8 $0\main_sdcore_crc16_inserter_source_payload_data[7:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdcore_crc16_inserter_source_ready[0:0] + attribute \src "ls180.v:4916.1-4995.4" + wire $0\main_sdcore_crc16_inserter_source_valid[0:0] + attribute \src "ls180.v:4856.1-4863.4" + wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_sdcore_data_count[31:0] + attribute \src "ls180.v:5098.1-5288.4" + wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdcore_data_done[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdcore_data_error[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdcore_data_timeout[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 2 $0\main_sdmem2block_converter_mux[1:0] + attribute \src "ls180.v:5494.1-5510.4" + wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdmem2block_dma_base_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 64 $0\main_sdmem2block_dma_base_storage[63:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_sdmem2block_dma_data[31:0] + attribute \src "ls180.v:5408.1-5445.4" + wire width 32 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + attribute \src "ls180.v:5408.1-5445.4" + wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + attribute \src "ls180.v:5446.1-5482.4" + wire $0\main_sdmem2block_dma_done_status[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdmem2block_dma_enable_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdmem2block_dma_enable_storage[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdmem2block_dma_length_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_sdmem2block_dma_length_storage[31:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdmem2block_dma_loop_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdmem2block_dma_loop_storage[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_sdmem2block_dma_offset[31:0] + attribute \src "ls180.v:5446.1-5482.4" + wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + attribute \src "ls180.v:5446.1-5482.4" + wire $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + attribute \src "ls180.v:5446.1-5482.4" + wire $0\main_sdmem2block_dma_sink_last[0:0] + attribute \src "ls180.v:5446.1-5482.4" + wire width 32 $0\main_sdmem2block_dma_sink_payload_address[31:0] + attribute \src "ls180.v:5408.1-5445.4" + wire $0\main_sdmem2block_dma_sink_ready[0:0] + attribute \src "ls180.v:5446.1-5482.4" + wire $0\main_sdmem2block_dma_sink_valid[0:0] + attribute \src "ls180.v:1585.5-1585.45" + wire $0\main_sdmem2block_dma_source_first[0:0] + attribute \src "ls180.v:5408.1-5445.4" + wire $0\main_sdmem2block_dma_source_last[0:0] + attribute \src "ls180.v:5408.1-5445.4" + wire width 32 $0\main_sdmem2block_dma_source_payload_data[31:0] + attribute \src "ls180.v:5408.1-5445.4" + wire $0\main_sdmem2block_dma_source_valid[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 5 $0\main_sdmem2block_fifo_consume[4:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 6 $0\main_sdmem2block_fifo_level[5:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 5 $0\main_sdmem2block_fifo_produce[4:0] + attribute \src "ls180.v:1641.5-1641.41" + wire $0\main_sdmem2block_fifo_replace[0:0] + attribute \src "ls180.v:5524.1-5531.4" + wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_clocker_clk0[0:0] + attribute \src "ls180.v:4262.1-4290.4" + wire $0\main_sdphy_clocker_clk1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_clocker_clk_d[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 9 $0\main_sdphy_clocker_clks[8:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_clocker_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 9 $0\main_sdphy_clocker_storage[8:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] + attribute \src "ls180.v:1106.5-1106.53" + wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] + attribute \src "ls180.v:1107.5-1107.52" + wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + attribute \src "ls180.v:1087.5-1087.46" + wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_cmdr_cmdr_reset[0:0] + attribute \src "ls180.v:4436.1-4529.4" + wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + attribute \src "ls180.v:4436.1-4529.4" + wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_cmdr_cmdr_run[0:0] + attribute \src "ls180.v:4436.1-4529.4" + wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\main_sdphy_cmdr_count[7:0] + attribute \src "ls180.v:4436.1-4529.4" + wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + attribute \src "ls180.v:4436.1-4529.4" + wire $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + attribute \src "ls180.v:1060.5-1060.49" + wire $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] + attribute \src "ls180.v:1061.5-1061.48" + wire $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] + attribute \src "ls180.v:1062.5-1062.55" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] + attribute \src "ls180.v:1064.5-1064.57" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "ls180.v:1065.5-1065.58" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "ls180.v:1067.11-1067.64" + wire width 4 $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] + attribute \src "ls180.v:1068.5-1068.59" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "ls180.v:4436.1-4529.4" + wire $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] + attribute \src "ls180.v:4436.1-4529.4" + wire $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:4436.1-4529.4" + wire $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1073.11-1073.57" + wire width 4 $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1074.5-1074.52" + wire $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdphy_cmdr_sink_last[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire width 8 $0\main_sdphy_cmdr_sink_payload_length[7:0] + attribute \src "ls180.v:4436.1-4529.4" + wire $0\main_sdphy_cmdr_sink_ready[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdphy_cmdr_sink_valid[0:0] + attribute \src "ls180.v:4436.1-4529.4" + wire $0\main_sdphy_cmdr_source_last[0:0] + attribute \src "ls180.v:4436.1-4529.4" + wire width 8 $0\main_sdphy_cmdr_source_payload_data[7:0] + attribute \src "ls180.v:4436.1-4529.4" + wire width 3 $0\main_sdphy_cmdr_source_payload_status[2:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdphy_cmdr_source_ready[0:0] + attribute \src "ls180.v:4436.1-4529.4" + wire $0\main_sdphy_cmdr_source_valid[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_sdphy_cmdr_timeout[31:0] + attribute \src "ls180.v:4436.1-4529.4" + wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + attribute \src "ls180.v:4436.1-4529.4" + wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\main_sdphy_cmdw_count[7:0] + attribute \src "ls180.v:4326.1-4402.4" + wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + attribute \src "ls180.v:4326.1-4402.4" + wire $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + attribute \src "ls180.v:4326.1-4402.4" + wire $0\main_sdphy_cmdw_done[0:0] + attribute \src "ls180.v:4326.1-4402.4" + wire $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:4326.1-4402.4" + wire $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:4326.1-4402.4" + wire $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1050.11-1050.57" + wire width 4 $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1051.5-1051.52" + wire $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdphy_cmdw_sink_last[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire width 8 $0\main_sdphy_cmdw_sink_payload_data[7:0] + attribute \src "ls180.v:4326.1-4402.4" + wire $0\main_sdphy_cmdw_sink_ready[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdphy_cmdw_sink_valid[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 10 $0\main_sdphy_datar_count[9:0] + attribute \src "ls180.v:4697.1-4798.4" + wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + attribute \src "ls180.v:4697.1-4798.4" + wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_datar_datar_buf_source_first[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_datar_datar_buf_source_last[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_datar_datar_buf_source_valid[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_datar_datar_converter_demux[0:0] + attribute \src "ls180.v:1262.5-1262.55" + wire $0\main_sdphy_datar_datar_converter_sink_first[0:0] + attribute \src "ls180.v:1263.5-1263.54" + wire $0\main_sdphy_datar_datar_converter_sink_last[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_datar_datar_converter_source_first[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_datar_datar_converter_source_last[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0] + attribute \src "ls180.v:1243.5-1243.48" + wire $0\main_sdphy_datar_datar_pads_in_ready[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_datar_datar_reset[0:0] + attribute \src "ls180.v:4697.1-4798.4" + wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + attribute \src "ls180.v:4697.1-4798.4" + wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_datar_datar_run[0:0] + attribute \src "ls180.v:4697.1-4798.4" + wire $0\main_sdphy_datar_datar_source_source_ready0[0:0] + attribute \src "ls180.v:1214.5-1214.50" + wire $0\main_sdphy_datar_pads_in_pads_in_first[0:0] + attribute \src "ls180.v:1215.5-1215.49" + wire $0\main_sdphy_datar_pads_in_pads_in_last[0:0] + attribute \src "ls180.v:1216.5-1216.56" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] + attribute \src "ls180.v:1218.5-1218.58" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "ls180.v:1219.5-1219.59" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "ls180.v:1221.11-1221.65" + wire width 4 $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] + attribute \src "ls180.v:1222.5-1222.60" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "ls180.v:4697.1-4798.4" + wire $0\main_sdphy_datar_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1225.5-1225.51" + wire $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1226.5-1226.52" + wire $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1227.11-1227.58" + wire width 4 $0\main_sdphy_datar_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1228.5-1228.53" + wire $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdphy_datar_sink_last[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire width 10 $0\main_sdphy_datar_sink_payload_block_length[9:0] + attribute \src "ls180.v:4697.1-4798.4" + wire $0\main_sdphy_datar_sink_ready[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdphy_datar_sink_valid[0:0] + attribute \src "ls180.v:1235.5-1235.41" + wire $0\main_sdphy_datar_source_first[0:0] + attribute \src "ls180.v:4697.1-4798.4" + wire $0\main_sdphy_datar_source_last[0:0] + attribute \src "ls180.v:4697.1-4798.4" + wire width 8 $0\main_sdphy_datar_source_payload_data[7:0] + attribute \src "ls180.v:4697.1-4798.4" + wire width 3 $0\main_sdphy_datar_source_payload_status[2:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdphy_datar_source_ready[0:0] + attribute \src "ls180.v:4697.1-4798.4" + wire $0\main_sdphy_datar_source_valid[0:0] + attribute \src "ls180.v:4697.1-4798.4" + wire $0\main_sdphy_datar_stop[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_sdphy_datar_timeout[31:0] + attribute \src "ls180.v:4697.1-4798.4" + wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + attribute \src "ls180.v:4697.1-4798.4" + wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\main_sdphy_dataw_count[7:0] + attribute \src "ls180.v:4591.1-4663.4" + wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + attribute \src "ls180.v:4591.1-4663.4" + wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0] + attribute \src "ls180.v:1184.5-1184.54" + wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] + attribute \src "ls180.v:1185.5-1185.53" + wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + attribute \src "ls180.v:1165.5-1165.47" + wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_dataw_crcr_reset[0:0] + attribute \src "ls180.v:4563.1-4590.4" + wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + attribute \src "ls180.v:4563.1-4590.4" + wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdphy_dataw_crcr_run[0:0] + attribute \src "ls180.v:4563.1-4590.4" + wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] + attribute \src "ls180.v:4563.1-4590.4" + wire $0\main_sdphy_dataw_error[0:0] + attribute \src "ls180.v:1152.5-1152.50" + wire $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] + attribute \src "ls180.v:1153.5-1153.49" + wire $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] + attribute \src "ls180.v:1154.5-1154.56" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] + attribute \src "ls180.v:1155.5-1155.58" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] + attribute \src "ls180.v:1156.5-1156.58" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "ls180.v:1157.5-1157.59" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "ls180.v:1158.11-1158.65" + wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] + attribute \src "ls180.v:1159.11-1159.65" + wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] + attribute \src "ls180.v:1160.5-1160.60" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "ls180.v:1150.5-1150.50" + wire $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] + attribute \src "ls180.v:4591.1-4663.4" + wire $0\main_sdphy_dataw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1139.5-1139.51" + wire $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1140.5-1140.52" + wire $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:4591.1-4663.4" + wire width 4 $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:4591.1-4663.4" + wire $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdphy_dataw_sink_first[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdphy_dataw_sink_last[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire width 8 $0\main_sdphy_dataw_sink_payload_data[7:0] + attribute \src "ls180.v:4591.1-4663.4" + wire $0\main_sdphy_dataw_sink_ready[0:0] + attribute \src "ls180.v:5098.1-5288.4" + wire $0\main_sdphy_dataw_sink_valid[0:0] + attribute \src "ls180.v:4591.1-4663.4" + wire $0\main_sdphy_dataw_start[0:0] + attribute \src "ls180.v:4591.1-4663.4" + wire $0\main_sdphy_dataw_stop[0:0] + attribute \src "ls180.v:4563.1-4590.4" + wire $0\main_sdphy_dataw_valid[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\main_sdphy_init_count[7:0] + attribute \src "ls180.v:4292.1-4325.4" + wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + attribute \src "ls180.v:4292.1-4325.4" + wire $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + attribute \src "ls180.v:1032.5-1032.40" + wire $0\main_sdphy_init_initialize_w[0:0] + attribute \src "ls180.v:4292.1-4325.4" + wire $0\main_sdphy_init_pads_out_payload_clk[0:0] + attribute \src "ls180.v:4292.1-4325.4" + wire $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:4292.1-4325.4" + wire $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:4292.1-4325.4" + wire width 4 $0\main_sdphy_init_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:4292.1-4325.4" + wire $0\main_sdphy_init_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:7289.1-7357.4" + wire $0\main_sdphy_sdpads_cmd_i[0:0] + attribute \src "ls180.v:7289.1-7357.4" + wire width 4 $0\main_sdphy_sdpads_data_i[3:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_address_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 13 $0\main_sdram_address_storage[12:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_baddress_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 2 $0\main_sdram_baddress_storage[1:0] + attribute \src "ls180.v:3141.1-3148.4" + wire $0\main_sdram_bankmachine0_auto_precharge[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:418.5-418.64" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:401.5-401.67" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:402.5-402.66" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3163.1-3170.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3130.1-3137.4" + wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0] + attribute \src "ls180.v:3179.1-3272.4" + wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] + attribute \src "ls180.v:3179.1-3272.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3179.1-3272.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3179.1-3272.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3179.1-3272.4" + wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] + attribute \src "ls180.v:3179.1-3272.4" + wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0] + attribute \src "ls180.v:3828.1-3836.4" + wire $0\main_sdram_bankmachine0_cmd_ready[0:0] + attribute \src "ls180.v:3179.1-3272.4" + wire $0\main_sdram_bankmachine0_cmd_valid[0:0] + attribute \src "ls180.v:3179.1-3272.4" + wire $0\main_sdram_bankmachine0_refresh_gnt[0:0] + attribute \src "ls180.v:3179.1-3272.4" + wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0] + attribute \src "ls180.v:3179.1-3272.4" + wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 13 $0\main_sdram_bankmachine0_row[12:0] + attribute \src "ls180.v:3179.1-3272.4" + wire $0\main_sdram_bankmachine0_row_close[0:0] + attribute \src "ls180.v:3179.1-3272.4" + wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3179.1-3272.4" + wire $0\main_sdram_bankmachine0_row_open[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_bankmachine0_row_opened[0:0] + attribute \src "ls180.v:460.32-460.76" + wire $0\main_sdram_bankmachine0_trascon_ready[0:0] + attribute \src "ls180.v:458.32-458.75" + wire $0\main_sdram_bankmachine0_trccon_ready[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0] + attribute \src "ls180.v:3298.1-3305.4" + wire $0\main_sdram_bankmachine1_auto_precharge[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:500.5-500.64" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:483.5-483.67" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:484.5-484.66" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3320.1-3327.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3287.1-3294.4" + wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0] + attribute \src "ls180.v:3336.1-3429.4" + wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] + attribute \src "ls180.v:3336.1-3429.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3336.1-3429.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3336.1-3429.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3336.1-3429.4" + wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] + attribute \src "ls180.v:3336.1-3429.4" + wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0] + attribute \src "ls180.v:3837.1-3845.4" + wire $0\main_sdram_bankmachine1_cmd_ready[0:0] + attribute \src "ls180.v:3336.1-3429.4" + wire $0\main_sdram_bankmachine1_cmd_valid[0:0] + attribute \src "ls180.v:3336.1-3429.4" + wire $0\main_sdram_bankmachine1_refresh_gnt[0:0] + attribute \src "ls180.v:3336.1-3429.4" + wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0] + attribute \src "ls180.v:3336.1-3429.4" + wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 13 $0\main_sdram_bankmachine1_row[12:0] + attribute \src "ls180.v:3336.1-3429.4" + wire $0\main_sdram_bankmachine1_row_close[0:0] + attribute \src "ls180.v:3336.1-3429.4" + wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3336.1-3429.4" + wire $0\main_sdram_bankmachine1_row_open[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_bankmachine1_row_opened[0:0] + attribute \src "ls180.v:542.32-542.76" + wire $0\main_sdram_bankmachine1_trascon_ready[0:0] + attribute \src "ls180.v:540.32-540.75" + wire $0\main_sdram_bankmachine1_trccon_ready[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0] + attribute \src "ls180.v:3455.1-3462.4" + wire $0\main_sdram_bankmachine2_auto_precharge[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:582.5-582.64" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:565.5-565.67" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:566.5-566.66" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3477.1-3484.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3444.1-3451.4" + wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0] + attribute \src "ls180.v:3493.1-3586.4" + wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] + attribute \src "ls180.v:3493.1-3586.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3493.1-3586.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3493.1-3586.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3493.1-3586.4" + wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] + attribute \src "ls180.v:3493.1-3586.4" + wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0] + attribute \src "ls180.v:3846.1-3854.4" + wire $0\main_sdram_bankmachine2_cmd_ready[0:0] + attribute \src "ls180.v:3493.1-3586.4" + wire $0\main_sdram_bankmachine2_cmd_valid[0:0] + attribute \src "ls180.v:3493.1-3586.4" + wire $0\main_sdram_bankmachine2_refresh_gnt[0:0] + attribute \src "ls180.v:3493.1-3586.4" + wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0] + attribute \src "ls180.v:3493.1-3586.4" + wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 13 $0\main_sdram_bankmachine2_row[12:0] + attribute \src "ls180.v:3493.1-3586.4" + wire $0\main_sdram_bankmachine2_row_close[0:0] + attribute \src "ls180.v:3493.1-3586.4" + wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3493.1-3586.4" + wire $0\main_sdram_bankmachine2_row_open[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_bankmachine2_row_opened[0:0] + attribute \src "ls180.v:624.32-624.76" + wire $0\main_sdram_bankmachine2_trascon_ready[0:0] + attribute \src "ls180.v:622.32-622.75" + wire $0\main_sdram_bankmachine2_trccon_ready[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0] + attribute \src "ls180.v:3612.1-3619.4" + wire $0\main_sdram_bankmachine3_auto_precharge[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:664.5-664.64" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:647.5-647.67" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:648.5-648.66" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3634.1-3641.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3601.1-3608.4" + wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0] + attribute \src "ls180.v:3650.1-3743.4" + wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] + attribute \src "ls180.v:3650.1-3743.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3650.1-3743.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3650.1-3743.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3650.1-3743.4" + wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] + attribute \src "ls180.v:3650.1-3743.4" + wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0] + attribute \src "ls180.v:3855.1-3863.4" + wire $0\main_sdram_bankmachine3_cmd_ready[0:0] + attribute \src "ls180.v:3650.1-3743.4" + wire $0\main_sdram_bankmachine3_cmd_valid[0:0] + attribute \src "ls180.v:3650.1-3743.4" + wire $0\main_sdram_bankmachine3_refresh_gnt[0:0] + attribute \src "ls180.v:3650.1-3743.4" + wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0] + attribute \src "ls180.v:3650.1-3743.4" + wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 13 $0\main_sdram_bankmachine3_row[12:0] + attribute \src "ls180.v:3650.1-3743.4" + wire $0\main_sdram_bankmachine3_row_close[0:0] + attribute \src "ls180.v:3650.1-3743.4" + wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3650.1-3743.4" + wire $0\main_sdram_bankmachine3_row_open[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_bankmachine3_row_opened[0:0] + attribute \src "ls180.v:706.32-706.76" + wire $0\main_sdram_bankmachine3_trascon_ready[0:0] + attribute \src "ls180.v:704.32-704.75" + wire $0\main_sdram_bankmachine3_trccon_ready[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0] + attribute \src "ls180.v:3777.1-3782.4" + wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] + attribute \src "ls180.v:3783.1-3788.4" + wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] + attribute \src "ls180.v:3789.1-3794.4" + wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0] + attribute \src "ls180.v:714.5-714.43" + wire $0\main_sdram_choose_cmd_cmd_ready[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 2 $0\main_sdram_choose_cmd_grant[1:0] + attribute \src "ls180.v:3763.1-3769.4" + wire width 4 $0\main_sdram_choose_cmd_valids[3:0] + attribute \src "ls180.v:712.5-712.48" + wire $0\main_sdram_choose_cmd_want_activates[0:0] + attribute \src "ls180.v:711.5-711.43" + wire $0\main_sdram_choose_cmd_want_cmds[0:0] + attribute \src "ls180.v:709.5-709.44" + wire $0\main_sdram_choose_cmd_want_reads[0:0] + attribute \src "ls180.v:710.5-710.45" + wire $0\main_sdram_choose_cmd_want_writes[0:0] + attribute \src "ls180.v:3810.1-3815.4" + wire $0\main_sdram_choose_req_cmd_payload_cas[0:0] + attribute \src "ls180.v:3816.1-3821.4" + wire $0\main_sdram_choose_req_cmd_payload_ras[0:0] + attribute \src "ls180.v:3822.1-3827.4" + wire $0\main_sdram_choose_req_cmd_payload_we[0:0] + attribute \src "ls180.v:3868.1-3940.4" + wire $0\main_sdram_choose_req_cmd_ready[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 2 $0\main_sdram_choose_req_grant[1:0] + attribute \src "ls180.v:3796.1-3802.4" + wire width 4 $0\main_sdram_choose_req_valids[3:0] + attribute \src "ls180.v:3868.1-3940.4" + wire $0\main_sdram_choose_req_want_activates[0:0] + attribute \src "ls180.v:3868.1-3940.4" + wire $0\main_sdram_choose_req_want_reads[0:0] + attribute \src "ls180.v:3868.1-3940.4" + wire $0\main_sdram_choose_req_want_writes[0:0] + attribute \src "ls180.v:3085.1-3115.4" + wire $0\main_sdram_cmd_last[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 13 $0\main_sdram_cmd_payload_a[12:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 2 $0\main_sdram_cmd_payload_ba[1:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_cmd_payload_cas[0:0] + attribute \src "ls180.v:362.5-362.42" + wire $0\main_sdram_cmd_payload_is_read[0:0] + attribute \src "ls180.v:363.5-363.43" + wire $0\main_sdram_cmd_payload_is_write[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_cmd_payload_ras[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_cmd_payload_we[0:0] + attribute \src "ls180.v:3868.1-3940.4" + wire $0\main_sdram_cmd_ready[0:0] + attribute \src "ls180.v:3085.1-3115.4" + wire $0\main_sdram_cmd_valid[0:0] + attribute \src "ls180.v:298.5-298.38" + wire $0\main_sdram_command_issue_w[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_command_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 6 $0\main_sdram_command_storage[5:0] + attribute \src "ls180.v:347.5-347.35" + wire $0\main_sdram_dfi_p0_act_n[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 13 $0\main_sdram_dfi_p0_address[12:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 2 $0\main_sdram_dfi_p0_bank[1:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_dfi_p0_cas_n[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_dfi_p0_cs_n[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_dfi_p0_ras_n[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_dfi_p0_rddata_en[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_dfi_p0_we_n[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_dfi_p0_wrdata_en[0:0] + attribute \src "ls180.v:3868.1-3940.4" + wire $0\main_sdram_en0[0:0] + attribute \src "ls180.v:3868.1-3940.4" + wire $0\main_sdram_en1[0:0] + attribute \src "ls180.v:3964.1-3977.4" + wire width 16 $0\main_sdram_interface_wdata[15:0] + attribute \src "ls180.v:3964.1-3977.4" + wire width 2 $0\main_sdram_interface_wdata_we[1:0] + attribute \src "ls180.v:248.5-248.36" + wire $0\main_sdram_inti_p0_act_n[0:0] + attribute \src "ls180.v:3026.1-3042.4" + wire $0\main_sdram_inti_p0_cas_n[0:0] + attribute \src "ls180.v:3026.1-3042.4" + wire $0\main_sdram_inti_p0_cs_n[0:0] + attribute \src "ls180.v:3026.1-3042.4" + wire $0\main_sdram_inti_p0_ras_n[0:0] + attribute \src "ls180.v:2968.1-3022.4" + wire width 16 $0\main_sdram_inti_p0_rddata[15:0] + attribute \src "ls180.v:2968.1-3022.4" + wire $0\main_sdram_inti_p0_rddata_valid[0:0] + attribute \src "ls180.v:3026.1-3042.4" + wire $0\main_sdram_inti_p0_we_n[0:0] + attribute \src "ls180.v:2968.1-3022.4" + wire $0\main_sdram_master_p0_act_n[0:0] + attribute \src "ls180.v:2968.1-3022.4" + wire width 13 $0\main_sdram_master_p0_address[12:0] + attribute \src "ls180.v:2968.1-3022.4" + wire width 2 $0\main_sdram_master_p0_bank[1:0] + attribute \src "ls180.v:2968.1-3022.4" + wire $0\main_sdram_master_p0_cas_n[0:0] + attribute \src "ls180.v:2968.1-3022.4" + wire $0\main_sdram_master_p0_cke[0:0] + attribute \src "ls180.v:2968.1-3022.4" + wire $0\main_sdram_master_p0_cs_n[0:0] + attribute \src "ls180.v:2968.1-3022.4" + wire $0\main_sdram_master_p0_odt[0:0] + attribute \src "ls180.v:2968.1-3022.4" + wire $0\main_sdram_master_p0_ras_n[0:0] + attribute \src "ls180.v:2968.1-3022.4" + wire $0\main_sdram_master_p0_rddata_en[0:0] + attribute \src "ls180.v:2968.1-3022.4" + wire $0\main_sdram_master_p0_reset_n[0:0] + attribute \src "ls180.v:2968.1-3022.4" + wire $0\main_sdram_master_p0_we_n[0:0] + attribute \src "ls180.v:2968.1-3022.4" + wire width 16 $0\main_sdram_master_p0_wrdata[15:0] + attribute \src "ls180.v:2968.1-3022.4" + wire $0\main_sdram_master_p0_wrdata_en[0:0] + attribute \src "ls180.v:2968.1-3022.4" + wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0] + attribute \src "ls180.v:745.12-745.36" + wire width 13 $0\main_sdram_nop_a[12:0] + attribute \src "ls180.v:746.11-746.35" + wire width 2 $0\main_sdram_nop_ba[1:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_postponer_count[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_postponer_req_o[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_sequencer_count[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 4 $0\main_sdram_sequencer_counter[3:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_sequencer_done1[0:0] + attribute \src "ls180.v:3085.1-3115.4" + wire $0\main_sdram_sequencer_start0[0:0] + attribute \src "ls180.v:2968.1-3022.4" + wire width 16 $0\main_sdram_slave_p0_rddata[15:0] + attribute \src "ls180.v:2968.1-3022.4" + wire $0\main_sdram_slave_p0_rddata_valid[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_sdram_status[15:0] + attribute \src "ls180.v:748.5-748.31" + wire $0\main_sdram_steerer0[0:0] + attribute \src "ls180.v:749.5-749.31" + wire $0\main_sdram_steerer1[0:0] + attribute \src "ls180.v:3868.1-3940.4" + wire width 2 $0\main_sdram_steerer_sel[1:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 4 $0\main_sdram_storage[3:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_tccdcon_count[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_tccdcon_ready[0:0] + attribute \src "ls180.v:753.32-753.63" + wire $0\main_sdram_tfawcon_ready[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 5 $0\main_sdram_time0[4:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 4 $0\main_sdram_time1[3:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 10 $0\main_sdram_timer_count1[9:0] + attribute \src "ls180.v:751.32-751.63" + wire $0\main_sdram_trrdcon_ready[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\main_sdram_twtrcon_count[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_twtrcon_ready[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sdram_wrdata_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_sdram_wrdata_storage[15:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_sink_ready[0:0] + attribute \src "ls180.v:824.5-824.29" + wire $0\main_source_first[0:0] + attribute \src "ls180.v:825.5-825.28" + wire $0\main_source_last[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\main_source_payload_data[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_source_valid[0:0] + attribute \src "ls180.v:969.12-969.48" + wire width 16 $0\main_spi_master_clk_divider0[15:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_spi_master_clk_divider1[15:0] + attribute \src "ls180.v:4186.1-4234.4" + wire $0\main_spi_master_clk_enable[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_spi_master_control_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 16 $0\main_spi_master_control_storage[15:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\main_spi_master_count[2:0] + attribute \src "ls180.v:4186.1-4234.4" + wire width 3 $0\main_spi_master_count_spimaster0_next_value[2:0] + attribute \src "ls180.v:4186.1-4234.4" + wire $0\main_spi_master_count_spimaster0_next_value_ce[0:0] + attribute \src "ls180.v:4186.1-4234.4" + wire $0\main_spi_master_cs_enable[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_spi_master_cs_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_spi_master_cs_storage[0:0] + attribute \src "ls180.v:4186.1-4234.4" + wire $0\main_spi_master_done0[0:0] + attribute \src "ls180.v:4186.1-4234.4" + wire $0\main_spi_master_irq[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_spi_master_loopback_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_spi_master_loopback_storage[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\main_spi_master_miso[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\main_spi_master_miso_data[7:0] + attribute \src "ls180.v:4186.1-4234.4" + wire $0\main_spi_master_miso_latch[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\main_spi_master_mosi_data[7:0] + attribute \src "ls180.v:4186.1-4234.4" + wire $0\main_spi_master_mosi_latch[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_spi_master_mosi_re[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 3 $0\main_spi_master_mosi_sel[2:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\main_spi_master_mosi_storage[7:0] + attribute \src "ls180.v:6220.1-6225.4" + wire $0\main_spi_master_start1[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 32 $0\main_storage[31:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 4 $0\main_tx_bitcount[3:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_tx_busy[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 8 $0\main_tx_reg[7:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_uart_clk_rxen[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_uart_clk_txen[0:0] + attribute \src "ls180.v:4104.1-4108.4" + wire width 2 $0\main_uart_eventmanager_pending_w[1:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_uart_eventmanager_re[0:0] + attribute \src "ls180.v:4093.1-4097.4" + wire width 2 $0\main_uart_eventmanager_status_w[1:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 2 $0\main_uart_eventmanager_storage[1:0] + attribute \src "ls180.v:951.5-951.27" + wire $0\main_uart_reset[0:0] + attribute \src "ls180.v:4098.1-4103.4" + wire $0\main_uart_rx_clear[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 4 $0\main_uart_rx_fifo_consume[3:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 5 $0\main_uart_rx_fifo_level0[4:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 4 $0\main_uart_rx_fifo_produce[3:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_uart_rx_fifo_readable[0:0] + attribute \src "ls180.v:933.5-933.37" + wire $0\main_uart_rx_fifo_replace[0:0] + attribute \src "ls180.v:4156.1-4163.4" + wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_uart_rx_old_trigger[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_uart_rx_pending[0:0] + attribute \src "ls180.v:4087.1-4092.4" + wire $0\main_uart_tx_clear[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 4 $0\main_uart_tx_fifo_consume[3:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 5 $0\main_uart_tx_fifo_level0[4:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 4 $0\main_uart_tx_fifo_produce[3:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_uart_tx_fifo_readable[0:0] + attribute \src "ls180.v:896.5-896.37" + wire $0\main_uart_tx_fifo_replace[0:0] + attribute \src "ls180.v:879.5-879.40" + wire $0\main_uart_tx_fifo_sink_first[0:0] + attribute \src "ls180.v:880.5-880.39" + wire $0\main_uart_tx_fifo_sink_last[0:0] + attribute \src "ls180.v:4126.1-4133.4" + wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_uart_tx_old_trigger[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_uart_tx_pending[0:0] + attribute \src "ls180.v:3996.1-4042.4" + wire $0\main_wb_sdram_ack[0:0] + attribute \src "ls180.v:792.5-792.29" + wire $0\main_wb_sdram_err[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\main_wdata_consumed[0:0] + attribute \src "ls180.v:9981.1-9991.4" + wire width 7 $0\memadr[6:0] + attribute \src "ls180.v:10001.1-10005.4" + wire width 25 $0\memdat[24:0] + attribute \src "ls180.v:10015.1-10019.4" + wire width 25 $0\memdat_1[24:0] + attribute \src "ls180.v:10029.1-10033.4" + wire width 25 $0\memdat_2[24:0] + attribute \src "ls180.v:10043.1-10047.4" + wire width 25 $0\memdat_3[24:0] + attribute \src "ls180.v:10058.1-10062.4" + wire width 10 $0\memdat_4[9:0] + attribute \src "ls180.v:10064.1-10067.4" + wire width 10 $0\memdat_5[9:0] + attribute \src "ls180.v:10075.1-10079.4" + wire width 10 $0\memdat_6[9:0] + attribute \src "ls180.v:10081.1-10084.4" + wire width 10 $0\memdat_7[9:0] + attribute \src "ls180.v:10091.1-10095.4" + wire width 10 $0\memdat_8[9:0] + attribute \src "ls180.v:10105.1-10109.4" + wire width 10 $0\memdat_9[9:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\pwm0[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\pwm1[0:0] + attribute \src "ls180.v:7289.1-7357.4" + wire $0\sdcard_clk[0:0] + attribute \src "ls180.v:7289.1-7357.4" + wire $0\sdcard_cmd_o[0:0] + attribute \src "ls180.v:7289.1-7357.4" + wire $0\sdcard_cmd_oe[0:0] + attribute \src "ls180.v:7289.1-7357.4" + wire width 4 $0\sdcard_data_o[3:0] + attribute \src "ls180.v:7289.1-7357.4" + wire $0\sdcard_data_oe[0:0] + attribute \src "ls180.v:7289.1-7357.4" + wire width 13 $0\sdram_a[12:0] + attribute \src "ls180.v:7289.1-7357.4" + wire width 2 $0\sdram_ba[1:0] + attribute \src "ls180.v:7289.1-7357.4" + wire $0\sdram_cas_n[0:0] + attribute \src "ls180.v:7289.1-7357.4" + wire $0\sdram_cke[0:0] + attribute \src "ls180.v:7289.1-7357.4" + wire $0\sdram_clock[0:0] + attribute \src "ls180.v:7289.1-7357.4" + wire $0\sdram_cs_n[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire width 2 $0\sdram_dm[1:0] + attribute \src "ls180.v:7289.1-7357.4" + wire width 16 $0\sdram_dq_o[15:0] + attribute \src "ls180.v:7289.1-7357.4" + wire $0\sdram_dq_oe[0:0] + attribute \src "ls180.v:7289.1-7357.4" + wire $0\sdram_ras_n[0:0] + attribute \src "ls180.v:7289.1-7357.4" + wire $0\sdram_we_n[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\spi_master_clk[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\spi_master_cs_n[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\spi_master_mosi[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\spisdcard_clk[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\spisdcard_cs_n[0:0] + attribute \src "ls180.v:7359.1-9977.4" + wire $0\spisdcard_mosi[0:0] + attribute \src "ls180.v:1710.11-1710.49" + wire width 3 $1\builder_bankmachine0_next_state[2:0] + attribute \src "ls180.v:1709.11-1709.44" + wire width 3 $1\builder_bankmachine0_state[2:0] + attribute \src "ls180.v:1712.11-1712.49" + wire width 3 $1\builder_bankmachine1_next_state[2:0] + attribute \src "ls180.v:1711.11-1711.44" + wire width 3 $1\builder_bankmachine1_state[2:0] + attribute \src "ls180.v:1714.11-1714.49" + wire width 3 $1\builder_bankmachine2_next_state[2:0] + attribute \src "ls180.v:1713.11-1713.44" + wire width 3 $1\builder_bankmachine2_state[2:0] + attribute \src "ls180.v:1716.11-1716.49" + wire width 3 $1\builder_bankmachine3_next_state[2:0] + attribute \src "ls180.v:1715.11-1715.44" + wire width 3 $1\builder_bankmachine3_state[2:0] + attribute \src "ls180.v:2548.5-2548.41" + wire $1\builder_comb_rhs_array_muxed0[0:0] + attribute \src "ls180.v:2561.5-2561.42" + wire $1\builder_comb_rhs_array_muxed10[0:0] + attribute \src "ls180.v:2562.5-2562.42" + wire $1\builder_comb_rhs_array_muxed11[0:0] + attribute \src "ls180.v:2566.12-2566.50" + wire width 22 $1\builder_comb_rhs_array_muxed12[21:0] + attribute \src "ls180.v:2567.5-2567.42" + wire $1\builder_comb_rhs_array_muxed13[0:0] + attribute \src "ls180.v:2568.5-2568.42" + wire $1\builder_comb_rhs_array_muxed14[0:0] + attribute \src "ls180.v:2569.12-2569.50" + wire width 22 $1\builder_comb_rhs_array_muxed15[21:0] + attribute \src "ls180.v:2570.5-2570.42" + wire $1\builder_comb_rhs_array_muxed16[0:0] + attribute \src "ls180.v:2571.5-2571.42" + wire $1\builder_comb_rhs_array_muxed17[0:0] + attribute \src "ls180.v:2572.12-2572.50" + wire width 22 $1\builder_comb_rhs_array_muxed18[21:0] + attribute \src "ls180.v:2573.5-2573.42" + wire $1\builder_comb_rhs_array_muxed19[0:0] + attribute \src "ls180.v:2549.12-2549.49" + wire width 13 $1\builder_comb_rhs_array_muxed1[12:0] + attribute \src "ls180.v:2574.5-2574.42" + wire $1\builder_comb_rhs_array_muxed20[0:0] + attribute \src "ls180.v:2575.12-2575.50" + wire width 22 $1\builder_comb_rhs_array_muxed21[21:0] + attribute \src "ls180.v:2576.5-2576.42" + wire $1\builder_comb_rhs_array_muxed22[0:0] + attribute \src "ls180.v:2577.5-2577.42" + wire $1\builder_comb_rhs_array_muxed23[0:0] + attribute \src "ls180.v:2578.12-2578.50" + wire width 32 $1\builder_comb_rhs_array_muxed24[31:0] + attribute \src "ls180.v:2579.12-2579.50" + wire width 32 $1\builder_comb_rhs_array_muxed25[31:0] + attribute \src "ls180.v:2580.11-2580.48" + wire width 4 $1\builder_comb_rhs_array_muxed26[3:0] + attribute \src "ls180.v:2581.5-2581.42" + wire $1\builder_comb_rhs_array_muxed27[0:0] + attribute \src "ls180.v:2582.5-2582.42" + wire $1\builder_comb_rhs_array_muxed28[0:0] + attribute \src "ls180.v:2583.5-2583.42" + wire $1\builder_comb_rhs_array_muxed29[0:0] + attribute \src "ls180.v:2550.11-2550.47" + wire width 2 $1\builder_comb_rhs_array_muxed2[1:0] + attribute \src "ls180.v:2584.11-2584.48" + wire width 3 $1\builder_comb_rhs_array_muxed30[2:0] + attribute \src "ls180.v:2585.11-2585.48" + wire width 2 $1\builder_comb_rhs_array_muxed31[1:0] + attribute \src "ls180.v:2551.5-2551.41" + wire $1\builder_comb_rhs_array_muxed3[0:0] + attribute \src "ls180.v:2552.5-2552.41" + wire $1\builder_comb_rhs_array_muxed4[0:0] + attribute \src "ls180.v:2553.5-2553.41" + wire $1\builder_comb_rhs_array_muxed5[0:0] + attribute \src "ls180.v:2557.5-2557.41" + wire $1\builder_comb_rhs_array_muxed6[0:0] + attribute \src "ls180.v:2558.12-2558.49" + wire width 13 $1\builder_comb_rhs_array_muxed7[12:0] + attribute \src "ls180.v:2559.11-2559.47" + wire width 2 $1\builder_comb_rhs_array_muxed8[1:0] + attribute \src "ls180.v:2560.5-2560.41" + wire $1\builder_comb_rhs_array_muxed9[0:0] + attribute \src "ls180.v:2554.5-2554.39" + wire $1\builder_comb_t_array_muxed0[0:0] + attribute \src "ls180.v:2555.5-2555.39" + wire $1\builder_comb_t_array_muxed1[0:0] + attribute \src "ls180.v:2556.5-2556.39" + wire $1\builder_comb_t_array_muxed2[0:0] + attribute \src "ls180.v:2563.5-2563.39" + wire $1\builder_comb_t_array_muxed3[0:0] + attribute \src "ls180.v:2564.5-2564.39" + wire $1\builder_comb_t_array_muxed4[0:0] + attribute \src "ls180.v:2565.5-2565.39" + wire $1\builder_comb_t_array_muxed5[0:0] + attribute \src "ls180.v:1696.5-1696.41" + wire $1\builder_converter0_next_state[0:0] + attribute \src "ls180.v:1695.5-1695.36" + wire $1\builder_converter0_state[0:0] + attribute \src "ls180.v:1700.5-1700.41" + wire $1\builder_converter1_next_state[0:0] + attribute \src "ls180.v:1699.5-1699.36" + wire $1\builder_converter1_state[0:0] + attribute \src "ls180.v:1704.5-1704.41" + wire $1\builder_converter2_next_state[0:0] + attribute \src "ls180.v:1703.5-1703.36" + wire $1\builder_converter2_state[0:0] + attribute \src "ls180.v:1741.5-1741.40" + wire $1\builder_converter_next_state[0:0] + attribute \src "ls180.v:1740.5-1740.35" + wire $1\builder_converter_state[0:0] + attribute \src "ls180.v:1861.12-1861.39" + wire width 20 $1\builder_count[19:0] + attribute \src "ls180.v:1858.5-1858.25" + wire $1\builder_error[0:0] + attribute \src "ls180.v:1855.11-1855.31" + wire width 3 $1\builder_grant[2:0] + attribute \src "ls180.v:1865.11-1865.51" + wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2387.11-2387.52" + wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2428.11-2428.52" + wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2493.11-2493.52" + wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2518.11-2518.52" + wire width 8 $1\builder_interface13_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1906.11-1906.51" + wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1935.11-1935.51" + wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1976.11-1976.51" + wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2017.11-2017.51" + wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2082.11-2082.51" + wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2215.11-2215.51" + wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2296.11-2296.51" + wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2313.11-2313.51" + wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2354.11-2354.51" + wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1828.12-1828.43" + wire width 14 $1\builder_libresocsim_adr[13:0] + attribute \src "ls180.v:2544.12-2544.55" + wire width 14 $1\builder_libresocsim_adr_next_value1[13:0] + attribute \src "ls180.v:2545.5-2545.50" + wire $1\builder_libresocsim_adr_next_value_ce1[0:0] + attribute \src "ls180.v:1830.11-1830.43" + wire width 8 $1\builder_libresocsim_dat_w[7:0] + attribute \src "ls180.v:2542.11-2542.55" + wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0] + attribute \src "ls180.v:2543.5-2543.52" + wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0] + attribute \src "ls180.v:1829.5-1829.34" + wire $1\builder_libresocsim_we[0:0] + attribute \src "ls180.v:2546.5-2546.46" + wire $1\builder_libresocsim_we_next_value2[0:0] + attribute \src "ls180.v:2547.5-2547.49" + wire $1\builder_libresocsim_we_next_value_ce2[0:0] + attribute \src "ls180.v:1838.5-1838.44" + wire $1\builder_libresocsim_wishbone_ack[0:0] + attribute \src "ls180.v:1834.12-1834.54" + wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0] + attribute \src "ls180.v:1718.11-1718.48" + wire width 3 $1\builder_multiplexer_next_state[2:0] + attribute \src "ls180.v:1717.11-1717.43" + wire width 3 $1\builder_multiplexer_state[2:0] + attribute \src "ls180.v:2649.32-2649.66" + wire $1\builder_multiregimpl0_regs0[0:0] + attribute \src "ls180.v:2650.32-2650.66" + wire $1\builder_multiregimpl0_regs1[0:0] + attribute \src "ls180.v:2669.32-2669.67" + wire $1\builder_multiregimpl10_regs0[0:0] + attribute \src "ls180.v:2670.32-2670.67" + wire $1\builder_multiregimpl10_regs1[0:0] + attribute \src "ls180.v:2671.32-2671.67" + wire $1\builder_multiregimpl11_regs0[0:0] + attribute \src "ls180.v:2672.32-2672.67" + wire $1\builder_multiregimpl11_regs1[0:0] + attribute \src "ls180.v:2673.32-2673.67" + wire $1\builder_multiregimpl12_regs0[0:0] + attribute \src "ls180.v:2674.32-2674.67" + wire $1\builder_multiregimpl12_regs1[0:0] + attribute \src "ls180.v:2675.32-2675.67" + wire $1\builder_multiregimpl13_regs0[0:0] + attribute \src "ls180.v:2676.32-2676.67" + wire $1\builder_multiregimpl13_regs1[0:0] + attribute \src "ls180.v:2677.32-2677.67" + wire $1\builder_multiregimpl14_regs0[0:0] + attribute \src "ls180.v:2678.32-2678.67" + wire $1\builder_multiregimpl14_regs1[0:0] + attribute \src "ls180.v:2679.32-2679.67" + wire $1\builder_multiregimpl15_regs0[0:0] + attribute \src "ls180.v:2680.32-2680.67" + wire $1\builder_multiregimpl15_regs1[0:0] + attribute \src "ls180.v:2681.32-2681.67" + wire $1\builder_multiregimpl16_regs0[0:0] + attribute \src "ls180.v:2682.32-2682.67" + wire $1\builder_multiregimpl16_regs1[0:0] + attribute \src "ls180.v:2651.32-2651.66" + wire $1\builder_multiregimpl1_regs0[0:0] + attribute \src "ls180.v:2652.32-2652.66" + wire $1\builder_multiregimpl1_regs1[0:0] + attribute \src "ls180.v:2653.32-2653.66" + wire $1\builder_multiregimpl2_regs0[0:0] + attribute \src "ls180.v:2654.32-2654.66" + wire $1\builder_multiregimpl2_regs1[0:0] + attribute \src "ls180.v:2655.32-2655.66" + wire $1\builder_multiregimpl3_regs0[0:0] + attribute \src "ls180.v:2656.32-2656.66" + wire $1\builder_multiregimpl3_regs1[0:0] + attribute \src "ls180.v:2657.32-2657.66" + wire $1\builder_multiregimpl4_regs0[0:0] + attribute \src "ls180.v:2658.32-2658.66" + wire $1\builder_multiregimpl4_regs1[0:0] + attribute \src "ls180.v:2659.32-2659.66" + wire $1\builder_multiregimpl5_regs0[0:0] + attribute \src "ls180.v:2660.32-2660.66" + wire $1\builder_multiregimpl5_regs1[0:0] + attribute \src "ls180.v:2661.32-2661.66" + wire $1\builder_multiregimpl6_regs0[0:0] + attribute \src "ls180.v:2662.32-2662.66" + wire $1\builder_multiregimpl6_regs1[0:0] + attribute \src "ls180.v:2663.32-2663.66" + wire $1\builder_multiregimpl7_regs0[0:0] + attribute \src "ls180.v:2664.32-2664.66" + wire $1\builder_multiregimpl7_regs1[0:0] + attribute \src "ls180.v:2665.32-2665.66" + wire $1\builder_multiregimpl8_regs0[0:0] + attribute \src "ls180.v:2666.32-2666.66" + wire $1\builder_multiregimpl8_regs1[0:0] + attribute \src "ls180.v:2667.32-2667.66" + wire $1\builder_multiregimpl9_regs0[0:0] + attribute \src "ls180.v:2668.32-2668.66" + wire $1\builder_multiregimpl9_regs1[0:0] + attribute \src "ls180.v:1736.5-1736.43" + wire $1\builder_new_master_rdata_valid0[0:0] + attribute \src "ls180.v:1737.5-1737.43" + wire $1\builder_new_master_rdata_valid1[0:0] + attribute \src "ls180.v:1738.5-1738.43" + wire $1\builder_new_master_rdata_valid2[0:0] + attribute \src "ls180.v:1739.5-1739.43" + wire $1\builder_new_master_rdata_valid3[0:0] + attribute \src "ls180.v:1735.5-1735.42" + wire $1\builder_new_master_wdata_ready[0:0] + attribute \src "ls180.v:2541.11-2541.36" + wire width 2 $1\builder_next_state[1:0] + attribute \src "ls180.v:1708.11-1708.46" + wire width 2 $1\builder_refresher_next_state[1:0] + attribute \src "ls180.v:1707.11-1707.41" + wire width 2 $1\builder_refresher_state[1:0] + attribute \src "ls180.v:1813.11-1813.51" + wire width 2 $1\builder_sdblock2memdma_next_state[1:0] + attribute \src "ls180.v:1812.11-1812.46" + wire width 2 $1\builder_sdblock2memdma_state[1:0] + attribute \src "ls180.v:1781.5-1781.57" + wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0] + attribute \src "ls180.v:1780.5-1780.52" + wire $1\builder_sdcore_crcupstreaminserter_state[0:0] + attribute \src "ls180.v:1793.11-1793.47" + wire width 3 $1\builder_sdcore_fsm_next_state[2:0] + attribute \src "ls180.v:1792.11-1792.42" + wire width 3 $1\builder_sdcore_fsm_state[2:0] + attribute \src "ls180.v:1817.5-1817.49" + wire $1\builder_sdmem2blockdma_fsm_next_state[0:0] + attribute \src "ls180.v:1816.5-1816.44" + wire $1\builder_sdmem2blockdma_fsm_state[0:0] + attribute \src "ls180.v:1821.11-1821.65" + wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] + attribute \src "ls180.v:1820.11-1820.60" + wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0] + attribute \src "ls180.v:1769.11-1769.46" + wire width 3 $1\builder_sdphy_fsm_next_state[2:0] + attribute \src "ls180.v:1768.11-1768.41" + wire width 3 $1\builder_sdphy_fsm_state[2:0] + attribute \src "ls180.v:1757.11-1757.52" + wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0] + attribute \src "ls180.v:1756.11-1756.47" + wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0] + attribute \src "ls180.v:1753.11-1753.52" + wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0] + attribute \src "ls180.v:1752.11-1752.47" + wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0] + attribute \src "ls180.v:1765.5-1765.46" + wire $1\builder_sdphy_sdphycrcr_next_state[0:0] + attribute \src "ls180.v:1764.5-1764.41" + wire $1\builder_sdphy_sdphycrcr_state[0:0] + attribute \src "ls180.v:1773.11-1773.53" + wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0] + attribute \src "ls180.v:1772.11-1772.48" + wire width 3 $1\builder_sdphy_sdphydatar_state[2:0] + attribute \src "ls180.v:1749.5-1749.46" + wire $1\builder_sdphy_sdphyinit_next_state[0:0] + attribute \src "ls180.v:1748.5-1748.41" + wire $1\builder_sdphy_sdphyinit_state[0:0] + attribute \src "ls180.v:1849.5-1849.30" + wire $1\builder_shared_ack[0:0] + attribute \src "ls180.v:1845.12-1845.40" + wire width 32 $1\builder_shared_dat_r[31:0] + attribute \src "ls180.v:1856.11-1856.35" + wire width 5 $1\builder_slave_sel[4:0] + attribute \src "ls180.v:1857.11-1857.37" + wire width 5 $1\builder_slave_sel_r[4:0] + attribute \src "ls180.v:1745.11-1745.47" + wire width 2 $1\builder_spimaster0_next_state[1:0] + attribute \src "ls180.v:1744.11-1744.42" + wire width 2 $1\builder_spimaster0_state[1:0] + attribute \src "ls180.v:1825.11-1825.47" + wire width 2 $1\builder_spimaster1_next_state[1:0] + attribute \src "ls180.v:1824.11-1824.42" + wire width 2 $1\builder_spimaster1_state[1:0] + attribute \src "ls180.v:2540.11-2540.31" + wire width 2 $1\builder_state[1:0] + attribute \src "ls180.v:2593.5-2593.39" + wire $1\builder_sync_f_array_muxed0[0:0] + attribute \src "ls180.v:2594.5-2594.39" + wire $1\builder_sync_f_array_muxed1[0:0] + attribute \src "ls180.v:2586.11-2586.47" + wire width 2 $1\builder_sync_rhs_array_muxed0[1:0] + attribute \src "ls180.v:2587.12-2587.49" + wire width 13 $1\builder_sync_rhs_array_muxed1[12:0] + attribute \src "ls180.v:2588.5-2588.41" + wire $1\builder_sync_rhs_array_muxed2[0:0] + attribute \src "ls180.v:2589.5-2589.41" + wire $1\builder_sync_rhs_array_muxed3[0:0] + attribute \src "ls180.v:2590.5-2590.41" + wire $1\builder_sync_rhs_array_muxed4[0:0] + attribute \src "ls180.v:2591.5-2591.41" + wire $1\builder_sync_rhs_array_muxed5[0:0] + attribute \src "ls180.v:2592.5-2592.41" + wire $1\builder_sync_rhs_array_muxed6[0:0] + attribute \src "ls180.v:1687.12-1687.44" + wire width 16 $1\libresocsim_clk_divider1[15:0] + attribute \src "ls180.v:1682.5-1682.34" + wire $1\libresocsim_clk_enable[0:0] + attribute \src "ls180.v:1669.5-1669.34" + wire $1\libresocsim_control_re[0:0] + attribute \src "ls180.v:1668.12-1668.47" + wire width 16 $1\libresocsim_control_storage[15:0] + attribute \src "ls180.v:1684.11-1684.35" + wire width 3 $1\libresocsim_count[2:0] + attribute \src "ls180.v:1826.11-1826.57" + wire width 3 $1\libresocsim_count_spimaster1_next_value[2:0] + attribute \src "ls180.v:1827.5-1827.54" + wire $1\libresocsim_count_spimaster1_next_value_ce[0:0] + attribute \src "ls180.v:1683.5-1683.33" + wire $1\libresocsim_cs_enable[0:0] + attribute \src "ls180.v:1679.5-1679.29" + wire $1\libresocsim_cs_re[0:0] + attribute \src "ls180.v:1678.5-1678.34" + wire $1\libresocsim_cs_storage[0:0] + attribute \src "ls180.v:1659.5-1659.29" + wire $1\libresocsim_done0[0:0] + attribute \src "ls180.v:1660.5-1660.27" + wire $1\libresocsim_irq[0:0] + attribute \src "ls180.v:1681.5-1681.35" + wire $1\libresocsim_loopback_re[0:0] + attribute \src "ls180.v:1680.5-1680.40" + wire $1\libresocsim_loopback_storage[0:0] + attribute \src "ls180.v:1662.11-1662.34" + wire width 8 $1\libresocsim_miso[7:0] + attribute \src "ls180.v:1692.11-1692.39" + wire width 8 $1\libresocsim_miso_data[7:0] + attribute \src "ls180.v:1686.5-1686.34" + wire $1\libresocsim_miso_latch[0:0] + attribute \src "ls180.v:1690.11-1690.39" + wire width 8 $1\libresocsim_mosi_data[7:0] + attribute \src "ls180.v:1685.5-1685.34" + wire $1\libresocsim_mosi_latch[0:0] + attribute \src "ls180.v:1674.5-1674.31" + wire $1\libresocsim_mosi_re[0:0] + attribute \src "ls180.v:1691.11-1691.38" + wire width 3 $1\libresocsim_mosi_sel[2:0] + attribute \src "ls180.v:1673.11-1673.42" + wire width 8 $1\libresocsim_mosi_storage[7:0] + attribute \src "ls180.v:1694.5-1694.26" + wire $1\libresocsim_re[0:0] + attribute \src "ls180.v:1666.5-1666.30" + wire $1\libresocsim_start1[0:0] + attribute \src "ls180.v:1693.12-1693.41" + wire width 16 $1\libresocsim_storage[15:0] + attribute \src "ls180.v:805.5-805.29" + wire $1\main_cmd_consumed[0:0] + attribute \src "ls180.v:802.5-802.34" + wire $1\main_converter_counter[0:0] + attribute \src "ls180.v:1742.5-1742.55" + wire $1\main_converter_counter_converter_next_value[0:0] + attribute \src "ls180.v:1743.5-1743.58" + wire $1\main_converter_counter_converter_next_value_ce[0:0] + attribute \src "ls180.v:804.12-804.40" + wire width 32 $1\main_converter_dat_r[31:0] + attribute \src "ls180.v:801.5-801.31" + wire $1\main_converter_skip[0:0] + attribute \src "ls180.v:235.12-235.38" + wire width 16 $1\main_dfi_p0_rddata[15:0] + attribute \src "ls180.v:236.5-236.36" + wire $1\main_dfi_p0_rddata_valid[0:0] + attribute \src "ls180.v:237.11-237.25" + wire width 2 $1\main_dm[1:0] + attribute \src "ls180.v:998.12-998.30" + wire width 43 $1\main_dummy[42:0] + attribute \src "ls180.v:953.5-953.27" + wire $1\main_gpio_oe_re[0:0] + attribute \src "ls180.v:952.12-952.40" + wire width 16 $1\main_gpio_oe_storage[15:0] + attribute \src "ls180.v:957.5-957.28" + wire $1\main_gpio_out_re[0:0] + attribute \src "ls180.v:956.12-956.41" + wire width 16 $1\main_gpio_out_storage[15:0] + attribute \src "ls180.v:954.12-954.36" + wire width 16 $1\main_gpio_status[15:0] + attribute \src "ls180.v:220.5-220.24" + wire $1\main_int_rst[0:0] + attribute \src "ls180.v:1563.12-1563.43" + wire width 32 $1\main_interface1_bus_adr[31:0] + attribute \src "ls180.v:1567.5-1567.35" + wire $1\main_interface1_bus_cyc[0:0] + attribute \src "ls180.v:1566.11-1566.41" + wire width 4 $1\main_interface1_bus_sel[3:0] + attribute \src "ls180.v:1568.5-1568.35" + wire $1\main_interface1_bus_stb[0:0] + attribute \src "ls180.v:1570.5-1570.34" + wire $1\main_interface1_bus_we[0:0] + attribute \src "ls180.v:57.12-57.47" + wire width 32 $1\main_libresocsim_bus_errors[31:0] + attribute \src "ls180.v:142.5-142.47" + wire $1\main_libresocsim_converter0_counter[0:0] + attribute \src "ls180.v:1697.5-1697.69" + wire $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] + attribute \src "ls180.v:1698.5-1698.72" + wire $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + attribute \src "ls180.v:144.12-144.53" + wire width 64 $1\main_libresocsim_converter0_dat_r[63:0] + attribute \src "ls180.v:141.5-141.44" + wire $1\main_libresocsim_converter0_skip[0:0] + attribute \src "ls180.v:157.5-157.47" + wire $1\main_libresocsim_converter1_counter[0:0] + attribute \src "ls180.v:1701.5-1701.69" + wire $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] + attribute \src "ls180.v:1702.5-1702.72" + wire $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + attribute \src "ls180.v:159.12-159.53" + wire width 64 $1\main_libresocsim_converter1_dat_r[63:0] + attribute \src "ls180.v:156.5-156.44" + wire $1\main_libresocsim_converter1_skip[0:0] + attribute \src "ls180.v:172.5-172.47" + wire $1\main_libresocsim_converter2_counter[0:0] + attribute \src "ls180.v:1705.5-1705.69" + wire $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] + attribute \src "ls180.v:1706.5-1706.72" + wire $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + attribute \src "ls180.v:174.12-174.53" + wire width 64 $1\main_libresocsim_converter2_dat_r[63:0] + attribute \src "ls180.v:171.5-171.44" + wire $1\main_libresocsim_converter2_skip[0:0] + attribute \src "ls180.v:195.5-195.34" + wire $1\main_libresocsim_en_re[0:0] + attribute \src "ls180.v:194.5-194.39" + wire $1\main_libresocsim_en_storage[0:0] + attribute \src "ls180.v:215.5-215.44" + wire $1\main_libresocsim_eventmanager_re[0:0] + attribute \src "ls180.v:214.5-214.49" + wire $1\main_libresocsim_eventmanager_storage[0:0] + attribute \src "ls180.v:130.12-130.71" + wire width 30 $1\main_libresocsim_interface0_converted_interface_adr[29:0] + attribute \src "ls180.v:134.5-134.63" + wire $1\main_libresocsim_interface0_converted_interface_cyc[0:0] + attribute \src "ls180.v:131.12-131.73" + wire width 32 $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] + attribute \src "ls180.v:133.11-133.69" + wire width 4 $1\main_libresocsim_interface0_converted_interface_sel[3:0] + attribute \src "ls180.v:135.5-135.63" + wire $1\main_libresocsim_interface0_converted_interface_stb[0:0] + attribute \src "ls180.v:137.5-137.62" + wire $1\main_libresocsim_interface0_converted_interface_we[0:0] + attribute \src "ls180.v:145.12-145.71" + wire width 30 $1\main_libresocsim_interface1_converted_interface_adr[29:0] + attribute \src "ls180.v:149.5-149.63" + wire $1\main_libresocsim_interface1_converted_interface_cyc[0:0] + attribute \src "ls180.v:146.12-146.73" + wire width 32 $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] + attribute \src "ls180.v:148.11-148.69" + wire width 4 $1\main_libresocsim_interface1_converted_interface_sel[3:0] + attribute \src "ls180.v:150.5-150.63" + wire $1\main_libresocsim_interface1_converted_interface_stb[0:0] + attribute \src "ls180.v:152.5-152.62" + wire $1\main_libresocsim_interface1_converted_interface_we[0:0] + attribute \src "ls180.v:160.12-160.71" + wire width 30 $1\main_libresocsim_interface2_converted_interface_adr[29:0] + attribute \src "ls180.v:164.5-164.63" + wire $1\main_libresocsim_interface2_converted_interface_cyc[0:0] + attribute \src "ls180.v:161.12-161.73" + wire width 32 $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] + attribute \src "ls180.v:163.11-163.69" + wire width 4 $1\main_libresocsim_interface2_converted_interface_sel[3:0] + attribute \src "ls180.v:165.5-165.63" + wire $1\main_libresocsim_interface2_converted_interface_stb[0:0] + attribute \src "ls180.v:167.5-167.62" + wire $1\main_libresocsim_interface2_converted_interface_we[0:0] + attribute \src "ls180.v:120.5-120.65" + wire $1\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] + attribute \src "ls180.v:66.5-66.46" + wire $1\main_libresocsim_libresoc_dbus_ack[0:0] + attribute \src "ls180.v:77.5-77.46" + wire $1\main_libresocsim_libresoc_ibus_ack[0:0] + attribute \src "ls180.v:59.12-59.55" + wire width 16 $1\main_libresocsim_libresoc_interrupt[15:0] + attribute \src "ls180.v:110.5-110.49" + wire $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] + attribute \src "ls180.v:191.5-191.36" + wire $1\main_libresocsim_load_re[0:0] + attribute \src "ls180.v:190.12-190.49" + wire width 32 $1\main_libresocsim_load_storage[31:0] + attribute \src "ls180.v:181.5-181.40" + wire $1\main_libresocsim_ram_bus_ack[0:0] + attribute \src "ls180.v:193.5-193.38" + wire $1\main_libresocsim_reload_re[0:0] + attribute \src "ls180.v:192.12-192.51" + wire width 32 $1\main_libresocsim_reload_storage[31:0] + attribute \src "ls180.v:50.5-50.37" + wire $1\main_libresocsim_reset_re[0:0] + attribute \src "ls180.v:49.5-49.42" + wire $1\main_libresocsim_reset_storage[0:0] + attribute \src "ls180.v:52.5-52.39" + wire $1\main_libresocsim_scratch_re[0:0] + attribute \src "ls180.v:51.12-51.60" + wire width 32 $1\main_libresocsim_scratch_storage[31:0] + attribute \src "ls180.v:197.5-197.44" + wire $1\main_libresocsim_update_value_re[0:0] + attribute \src "ls180.v:196.5-196.49" + wire $1\main_libresocsim_update_value_storage[0:0] + attribute \src "ls180.v:216.12-216.42" + wire width 32 $1\main_libresocsim_value[31:0] + attribute \src "ls180.v:198.12-198.49" + wire width 32 $1\main_libresocsim_value_status[31:0] + attribute \src "ls180.v:188.11-188.37" + wire width 4 $1\main_libresocsim_we[3:0] + attribute \src "ls180.v:204.5-204.39" + wire $1\main_libresocsim_zero_clear[0:0] + attribute \src "ls180.v:205.5-205.45" + wire $1\main_libresocsim_zero_old_trigger[0:0] + attribute \src "ls180.v:202.5-202.41" + wire $1\main_libresocsim_zero_pending[0:0] + attribute \src "ls180.v:793.12-793.40" + wire width 30 $1\main_litedram_wb_adr[29:0] + attribute \src "ls180.v:797.5-797.32" + wire $1\main_litedram_wb_cyc[0:0] + attribute \src "ls180.v:794.12-794.42" + wire width 16 $1\main_litedram_wb_dat_w[15:0] + attribute \src "ls180.v:796.11-796.38" + wire width 2 $1\main_litedram_wb_sel[1:0] + attribute \src "ls180.v:798.5-798.32" + wire $1\main_litedram_wb_stb[0:0] + attribute \src "ls180.v:800.5-800.31" + wire $1\main_litedram_wb_we[0:0] + attribute \src "ls180.v:828.12-828.45" + wire width 32 $1\main_phase_accumulator_rx[31:0] + attribute \src "ls180.v:818.12-818.45" + wire width 32 $1\main_phase_accumulator_tx[31:0] + attribute \src "ls180.v:1002.12-1002.37" + wire width 32 $1\main_pwm0_counter[31:0] + attribute \src "ls180.v:1004.5-1004.31" + wire $1\main_pwm0_enable_re[0:0] + attribute \src "ls180.v:1003.5-1003.36" + wire $1\main_pwm0_enable_storage[0:0] + attribute \src "ls180.v:1008.5-1008.31" + wire $1\main_pwm0_period_re[0:0] + attribute \src "ls180.v:1007.12-1007.44" + wire width 32 $1\main_pwm0_period_storage[31:0] + attribute \src "ls180.v:1006.5-1006.30" + wire $1\main_pwm0_width_re[0:0] + attribute \src "ls180.v:1005.12-1005.43" + wire width 32 $1\main_pwm0_width_storage[31:0] + attribute \src "ls180.v:1012.12-1012.37" + wire width 32 $1\main_pwm1_counter[31:0] + attribute \src "ls180.v:1014.5-1014.31" + wire $1\main_pwm1_enable_re[0:0] + attribute \src "ls180.v:1013.5-1013.36" + wire $1\main_pwm1_enable_storage[0:0] + attribute \src "ls180.v:1018.5-1018.31" + wire $1\main_pwm1_period_re[0:0] + attribute \src "ls180.v:1017.12-1017.44" + wire width 32 $1\main_pwm1_period_storage[31:0] + attribute \src "ls180.v:1016.5-1016.30" + wire $1\main_pwm1_width_re[0:0] + attribute \src "ls180.v:1015.12-1015.43" + wire width 32 $1\main_pwm1_width_storage[31:0] + attribute \src "ls180.v:238.11-238.32" + wire width 3 $1\main_rddata_en[2:0] + attribute \src "ls180.v:811.5-811.19" + wire $1\main_re[0:0] + attribute \src "ls180.v:832.11-832.34" + wire width 4 $1\main_rx_bitcount[3:0] + attribute \src "ls180.v:833.5-833.24" + wire $1\main_rx_busy[0:0] + attribute \src "ls180.v:830.5-830.21" + wire $1\main_rx_r[0:0] + attribute \src "ls180.v:831.11-831.29" + wire width 8 $1\main_rx_reg[7:0] + attribute \src "ls180.v:1532.11-1532.50" + wire width 2 $1\main_sdblock2mem_converter_demux[1:0] + attribute \src "ls180.v:1528.5-1528.51" + wire $1\main_sdblock2mem_converter_source_first[0:0] + attribute \src "ls180.v:1529.5-1529.50" + wire $1\main_sdblock2mem_converter_source_last[0:0] + attribute \src "ls180.v:1530.12-1530.66" + wire width 32 $1\main_sdblock2mem_converter_source_payload_data[31:0] + attribute \src "ls180.v:1531.11-1531.77" + wire width 3 $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] + attribute \src "ls180.v:1534.5-1534.49" + wire $1\main_sdblock2mem_converter_strobe_all[0:0] + attribute \src "ls180.v:1507.11-1507.47" + wire width 5 $1\main_sdblock2mem_fifo_consume[4:0] + attribute \src "ls180.v:1504.11-1504.45" + wire width 6 $1\main_sdblock2mem_fifo_level[5:0] + attribute \src "ls180.v:1506.11-1506.47" + wire width 5 $1\main_sdblock2mem_fifo_produce[4:0] + attribute \src "ls180.v:1508.11-1508.50" + wire width 5 $1\main_sdblock2mem_fifo_wrport_adr[4:0] + attribute \src "ls180.v:1542.12-1542.62" + wire width 32 $1\main_sdblock2mem_sink_sink_payload_address[31:0] + attribute \src "ls180.v:1543.12-1543.60" + wire width 32 $1\main_sdblock2mem_sink_sink_payload_data1[31:0] + attribute \src "ls180.v:1540.5-1540.45" + wire $1\main_sdblock2mem_sink_sink_valid1[0:0] + attribute \src "ls180.v:1550.5-1550.54" + wire $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + attribute \src "ls180.v:1549.12-1549.67" + wire width 64 $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + attribute \src "ls180.v:1554.5-1554.56" + wire $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + attribute \src "ls180.v:1553.5-1553.61" + wire $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + attribute \src "ls180.v:1552.5-1552.56" + wire $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + attribute \src "ls180.v:1551.12-1551.69" + wire width 32 $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + attribute \src "ls180.v:1558.5-1558.54" + wire $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + attribute \src "ls180.v:1557.5-1557.59" + wire $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + attribute \src "ls180.v:1560.12-1560.61" + wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] + attribute \src "ls180.v:1814.12-1814.87" + wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + attribute \src "ls180.v:1815.5-1815.82" + wire $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + attribute \src "ls180.v:1545.5-1545.57" + wire $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + attribute \src "ls180.v:1555.5-1555.53" + wire $1\main_sdblock2mem_wishbonedmawriter_status[0:0] + attribute \src "ls180.v:1324.5-1324.38" + wire $1\main_sdcore_block_count_re[0:0] + attribute \src "ls180.v:1323.12-1323.51" + wire width 32 $1\main_sdcore_block_count_storage[31:0] + attribute \src "ls180.v:1322.5-1322.39" + wire $1\main_sdcore_block_length_re[0:0] + attribute \src "ls180.v:1321.11-1321.51" + wire width 10 $1\main_sdcore_block_length_storage[9:0] + attribute \src "ls180.v:1308.5-1308.39" + wire $1\main_sdcore_cmd_argument_re[0:0] + attribute \src "ls180.v:1307.12-1307.52" + wire width 32 $1\main_sdcore_cmd_argument_storage[31:0] + attribute \src "ls180.v:1310.5-1310.38" + wire $1\main_sdcore_cmd_command_re[0:0] + attribute \src "ls180.v:1309.12-1309.51" + wire width 32 $1\main_sdcore_cmd_command_storage[31:0] + attribute \src "ls180.v:1463.11-1463.39" + wire width 3 $1\main_sdcore_cmd_count[2:0] + attribute \src "ls180.v:1798.11-1798.62" + wire width 3 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + attribute \src "ls180.v:1799.5-1799.59" + wire $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + attribute \src "ls180.v:1464.5-1464.32" + wire $1\main_sdcore_cmd_done[0:0] + attribute \src "ls180.v:1794.5-1794.55" + wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + attribute \src "ls180.v:1795.5-1795.58" + wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + attribute \src "ls180.v:1465.5-1465.33" + wire $1\main_sdcore_cmd_error[0:0] + attribute \src "ls180.v:1802.5-1802.56" + wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + attribute \src "ls180.v:1803.5-1803.59" + wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + attribute \src "ls180.v:1315.13-1315.53" + wire width 128 $1\main_sdcore_cmd_response_status[127:0] + attribute \src "ls180.v:1810.13-1810.76" + wire width 128 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + attribute \src "ls180.v:1811.5-1811.69" + wire $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + attribute \src "ls180.v:1466.5-1466.35" + wire $1\main_sdcore_cmd_timeout[0:0] + attribute \src "ls180.v:1804.5-1804.58" + wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + attribute \src "ls180.v:1805.5-1805.61" + wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + attribute \src "ls180.v:1424.11-1424.47" + wire width 4 $1\main_sdcore_crc16_checker_cnt[3:0] + attribute \src "ls180.v:1430.5-1430.46" + wire $1\main_sdcore_crc16_checker_crc0_clr[0:0] + attribute \src "ls180.v:1429.12-1429.54" + wire width 16 $1\main_sdcore_crc16_checker_crc0_crc[15:0] + attribute \src "ls180.v:1425.12-1425.58" + wire width 16 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + attribute \src "ls180.v:1437.5-1437.46" + wire $1\main_sdcore_crc16_checker_crc1_clr[0:0] + attribute \src "ls180.v:1436.12-1436.54" + wire width 16 $1\main_sdcore_crc16_checker_crc1_crc[15:0] + attribute \src "ls180.v:1432.12-1432.58" + wire width 16 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + attribute \src "ls180.v:1444.5-1444.46" + wire $1\main_sdcore_crc16_checker_crc2_clr[0:0] + attribute \src "ls180.v:1443.12-1443.54" + wire width 16 $1\main_sdcore_crc16_checker_crc2_crc[15:0] + attribute \src "ls180.v:1439.12-1439.58" + wire width 16 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + attribute \src "ls180.v:1451.5-1451.46" + wire $1\main_sdcore_crc16_checker_crc3_clr[0:0] + attribute \src "ls180.v:1450.12-1450.54" + wire width 16 $1\main_sdcore_crc16_checker_crc3_crc[15:0] + attribute \src "ls180.v:1446.12-1446.58" + wire width 16 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + attribute \src "ls180.v:1453.12-1453.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp0[15:0] + attribute \src "ls180.v:1454.12-1454.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp1[15:0] + attribute \src "ls180.v:1455.12-1455.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp2[15:0] + attribute \src "ls180.v:1456.12-1456.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp3[15:0] + attribute \src "ls180.v:1458.12-1458.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo0[15:0] + attribute \src "ls180.v:1459.12-1459.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo1[15:0] + attribute \src "ls180.v:1460.12-1460.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo2[15:0] + attribute \src "ls180.v:1461.12-1461.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo3[15:0] + attribute \src "ls180.v:1415.5-1415.48" + wire $1\main_sdcore_crc16_checker_sink_first[0:0] + attribute \src "ls180.v:1416.5-1416.47" + wire $1\main_sdcore_crc16_checker_sink_last[0:0] + attribute \src "ls180.v:1417.11-1417.61" + wire width 8 $1\main_sdcore_crc16_checker_sink_payload_data[7:0] + attribute \src "ls180.v:1414.5-1414.48" + wire $1\main_sdcore_crc16_checker_sink_ready[0:0] + attribute \src "ls180.v:1413.5-1413.48" + wire $1\main_sdcore_crc16_checker_sink_valid[0:0] + attribute \src "ls180.v:1418.5-1418.50" + wire $1\main_sdcore_crc16_checker_source_valid[0:0] + attribute \src "ls180.v:1423.11-1423.47" + wire width 8 $1\main_sdcore_crc16_checker_val[7:0] + attribute \src "ls180.v:1457.5-1457.43" + wire $1\main_sdcore_crc16_checker_valid[0:0] + attribute \src "ls180.v:1380.11-1380.48" + wire width 3 $1\main_sdcore_crc16_inserter_cnt[2:0] + attribute \src "ls180.v:1790.11-1790.87" + wire width 3 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + attribute \src "ls180.v:1791.5-1791.84" + wire $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + attribute \src "ls180.v:1385.12-1385.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc0_crc[15:0] + attribute \src "ls180.v:1381.12-1381.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + attribute \src "ls180.v:1392.12-1392.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc1_crc[15:0] + attribute \src "ls180.v:1388.12-1388.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + attribute \src "ls180.v:1399.12-1399.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc2_crc[15:0] + attribute \src "ls180.v:1395.12-1395.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + attribute \src "ls180.v:1406.12-1406.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc3_crc[15:0] + attribute \src "ls180.v:1402.12-1402.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + attribute \src "ls180.v:1409.12-1409.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp0[15:0] + attribute \src "ls180.v:1782.12-1782.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + attribute \src "ls180.v:1783.5-1783.88" + wire $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + attribute \src "ls180.v:1410.12-1410.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp1[15:0] + attribute \src "ls180.v:1784.12-1784.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + attribute \src "ls180.v:1785.5-1785.88" + wire $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + attribute \src "ls180.v:1411.12-1411.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp2[15:0] + attribute \src "ls180.v:1786.12-1786.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + attribute \src "ls180.v:1787.5-1787.88" + wire $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + attribute \src "ls180.v:1412.12-1412.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp3[15:0] + attribute \src "ls180.v:1788.12-1788.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + attribute \src "ls180.v:1789.5-1789.88" + wire $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + attribute \src "ls180.v:1371.5-1371.49" + wire $1\main_sdcore_crc16_inserter_sink_ready[0:0] + attribute \src "ls180.v:1378.5-1378.50" + wire $1\main_sdcore_crc16_inserter_source_last[0:0] + attribute \src "ls180.v:1379.11-1379.64" + wire width 8 $1\main_sdcore_crc16_inserter_source_payload_data[7:0] + attribute \src "ls180.v:1376.5-1376.51" + wire $1\main_sdcore_crc16_inserter_source_ready[0:0] + attribute \src "ls180.v:1375.5-1375.51" + wire $1\main_sdcore_crc16_inserter_source_valid[0:0] + attribute \src "ls180.v:1367.11-1367.47" + wire width 7 $1\main_sdcore_crc7_inserter_crc[6:0] + attribute \src "ls180.v:1325.11-1325.51" + wire width 7 $1\main_sdcore_crc7_inserter_crcreg0[6:0] + attribute \src "ls180.v:1468.12-1468.42" + wire width 32 $1\main_sdcore_data_count[31:0] + attribute \src "ls180.v:1800.12-1800.65" + wire width 32 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + attribute \src "ls180.v:1801.5-1801.60" + wire $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + attribute \src "ls180.v:1469.5-1469.33" + wire $1\main_sdcore_data_done[0:0] + attribute \src "ls180.v:1796.5-1796.56" + wire $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + attribute \src "ls180.v:1797.5-1797.59" + wire $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + attribute \src "ls180.v:1470.5-1470.34" + wire $1\main_sdcore_data_error[0:0] + attribute \src "ls180.v:1806.5-1806.57" + wire $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + attribute \src "ls180.v:1807.5-1807.60" + wire $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + attribute \src "ls180.v:1471.5-1471.36" + wire $1\main_sdcore_data_timeout[0:0] + attribute \src "ls180.v:1808.5-1808.59" + wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + attribute \src "ls180.v:1809.5-1809.62" + wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + attribute \src "ls180.v:1616.11-1616.48" + wire width 2 $1\main_sdmem2block_converter_mux[1:0] + attribute \src "ls180.v:1614.11-1614.64" + wire width 8 $1\main_sdmem2block_converter_source_payload_data[7:0] + attribute \src "ls180.v:1590.5-1590.40" + wire $1\main_sdmem2block_dma_base_re[0:0] + attribute \src "ls180.v:1589.12-1589.53" + wire width 64 $1\main_sdmem2block_dma_base_storage[63:0] + attribute \src "ls180.v:1588.12-1588.45" + wire width 32 $1\main_sdmem2block_dma_data[31:0] + attribute \src "ls180.v:1818.12-1818.75" + wire width 32 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + attribute \src "ls180.v:1819.5-1819.70" + wire $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + attribute \src "ls180.v:1595.5-1595.44" + wire $1\main_sdmem2block_dma_done_status[0:0] + attribute \src "ls180.v:1594.5-1594.42" + wire $1\main_sdmem2block_dma_enable_re[0:0] + attribute \src "ls180.v:1593.5-1593.47" + wire $1\main_sdmem2block_dma_enable_storage[0:0] + attribute \src "ls180.v:1592.5-1592.42" + wire $1\main_sdmem2block_dma_length_re[0:0] + attribute \src "ls180.v:1591.12-1591.55" + wire width 32 $1\main_sdmem2block_dma_length_storage[31:0] + attribute \src "ls180.v:1598.5-1598.40" + wire $1\main_sdmem2block_dma_loop_re[0:0] + attribute \src "ls180.v:1597.5-1597.45" + wire $1\main_sdmem2block_dma_loop_storage[0:0] + attribute \src "ls180.v:1602.12-1602.47" + wire width 32 $1\main_sdmem2block_dma_offset[31:0] + attribute \src "ls180.v:1822.12-1822.87" + wire width 32 $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + attribute \src "ls180.v:1823.5-1823.82" + wire $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + attribute \src "ls180.v:1581.5-1581.42" + wire $1\main_sdmem2block_dma_sink_last[0:0] + attribute \src "ls180.v:1582.12-1582.61" + wire width 32 $1\main_sdmem2block_dma_sink_payload_address[31:0] + attribute \src "ls180.v:1580.5-1580.43" + wire $1\main_sdmem2block_dma_sink_ready[0:0] + attribute \src "ls180.v:1579.5-1579.43" + wire $1\main_sdmem2block_dma_sink_valid[0:0] + attribute \src "ls180.v:1586.5-1586.44" + wire $1\main_sdmem2block_dma_source_last[0:0] + attribute \src "ls180.v:1587.12-1587.60" + wire width 32 $1\main_sdmem2block_dma_source_payload_data[31:0] + attribute \src "ls180.v:1583.5-1583.45" + wire $1\main_sdmem2block_dma_source_valid[0:0] + attribute \src "ls180.v:1643.11-1643.47" + wire width 5 $1\main_sdmem2block_fifo_consume[4:0] + attribute \src "ls180.v:1640.11-1640.45" + wire width 6 $1\main_sdmem2block_fifo_level[5:0] + attribute \src "ls180.v:1642.11-1642.47" + wire width 5 $1\main_sdmem2block_fifo_produce[4:0] + attribute \src "ls180.v:1644.11-1644.50" + wire width 5 $1\main_sdmem2block_fifo_wrport_adr[4:0] + attribute \src "ls180.v:1024.5-1024.35" + wire $1\main_sdphy_clocker_clk0[0:0] + attribute \src "ls180.v:1027.5-1027.35" + wire $1\main_sdphy_clocker_clk1[0:0] + attribute \src "ls180.v:1028.5-1028.36" + wire $1\main_sdphy_clocker_clk_d[0:0] + attribute \src "ls180.v:1026.11-1026.41" + wire width 9 $1\main_sdphy_clocker_clks[8:0] + attribute \src "ls180.v:1022.5-1022.33" + wire $1\main_sdphy_clocker_re[0:0] + attribute \src "ls180.v:1021.11-1021.46" + wire width 9 $1\main_sdphy_clocker_storage[8:0] + attribute \src "ls180.v:1130.5-1130.49" + wire $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + attribute \src "ls180.v:1131.5-1131.48" + wire $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + attribute \src "ls180.v:1132.11-1132.62" + wire width 8 $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + attribute \src "ls180.v:1128.5-1128.49" + wire $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + attribute \src "ls180.v:1115.11-1115.54" + wire width 3 $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] + attribute \src "ls180.v:1111.5-1111.55" + wire $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + attribute \src "ls180.v:1112.5-1112.54" + wire $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + attribute \src "ls180.v:1113.11-1113.68" + wire width 8 $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + attribute \src "ls180.v:1114.11-1114.81" + wire width 4 $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:1117.5-1117.53" + wire $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + attribute \src "ls180.v:1133.5-1133.38" + wire $1\main_sdphy_cmdr_cmdr_reset[0:0] + attribute \src "ls180.v:1762.5-1762.66" + wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + attribute \src "ls180.v:1763.5-1763.69" + wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + attribute \src "ls180.v:1103.5-1103.36" + wire $1\main_sdphy_cmdr_cmdr_run[0:0] + attribute \src "ls180.v:1098.5-1098.53" + wire $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + attribute \src "ls180.v:1085.11-1085.39" + wire width 8 $1\main_sdphy_cmdr_count[7:0] + attribute \src "ls180.v:1758.11-1758.67" + wire width 8 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + attribute \src "ls180.v:1759.5-1759.64" + wire $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + attribute \src "ls180.v:1070.5-1070.48" + wire $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1071.5-1071.50" + wire $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1072.5-1072.51" + wire $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1077.5-1077.37" + wire $1\main_sdphy_cmdr_sink_last[0:0] + attribute \src "ls180.v:1078.11-1078.53" + wire width 8 $1\main_sdphy_cmdr_sink_payload_length[7:0] + attribute \src "ls180.v:1076.5-1076.38" + wire $1\main_sdphy_cmdr_sink_ready[0:0] + attribute \src "ls180.v:1075.5-1075.38" + wire $1\main_sdphy_cmdr_sink_valid[0:0] + attribute \src "ls180.v:1081.5-1081.39" + wire $1\main_sdphy_cmdr_source_last[0:0] + attribute \src "ls180.v:1082.11-1082.53" + wire width 8 $1\main_sdphy_cmdr_source_payload_data[7:0] + attribute \src "ls180.v:1083.11-1083.55" + wire width 3 $1\main_sdphy_cmdr_source_payload_status[2:0] + attribute \src "ls180.v:1080.5-1080.40" + wire $1\main_sdphy_cmdr_source_ready[0:0] + attribute \src "ls180.v:1079.5-1079.40" + wire $1\main_sdphy_cmdr_source_valid[0:0] + attribute \src "ls180.v:1084.12-1084.48" + wire width 32 $1\main_sdphy_cmdr_timeout[31:0] + attribute \src "ls180.v:1760.12-1760.71" + wire width 32 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + attribute \src "ls180.v:1761.5-1761.66" + wire $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + attribute \src "ls180.v:1057.11-1057.39" + wire width 8 $1\main_sdphy_cmdw_count[7:0] + attribute \src "ls180.v:1754.11-1754.66" + wire width 8 $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + attribute \src "ls180.v:1755.5-1755.63" + wire $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + attribute \src "ls180.v:1056.5-1056.32" + wire $1\main_sdphy_cmdw_done[0:0] + attribute \src "ls180.v:1047.5-1047.48" + wire $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1048.5-1048.50" + wire $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1049.5-1049.51" + wire $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1054.5-1054.37" + wire $1\main_sdphy_cmdw_sink_last[0:0] + attribute \src "ls180.v:1055.11-1055.51" + wire width 8 $1\main_sdphy_cmdw_sink_payload_data[7:0] + attribute \src "ls180.v:1053.5-1053.38" + wire $1\main_sdphy_cmdw_sink_ready[0:0] + attribute \src "ls180.v:1052.5-1052.38" + wire $1\main_sdphy_cmdw_sink_valid[0:0] + attribute \src "ls180.v:1241.11-1241.41" + wire width 10 $1\main_sdphy_datar_count[9:0] + attribute \src "ls180.v:1774.11-1774.70" + wire width 10 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + attribute \src "ls180.v:1775.5-1775.66" + wire $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + attribute \src "ls180.v:1286.5-1286.51" + wire $1\main_sdphy_datar_datar_buf_source_first[0:0] + attribute \src "ls180.v:1287.5-1287.50" + wire $1\main_sdphy_datar_datar_buf_source_last[0:0] + attribute \src "ls180.v:1288.11-1288.64" + wire width 8 $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] + attribute \src "ls180.v:1284.5-1284.51" + wire $1\main_sdphy_datar_datar_buf_source_valid[0:0] + attribute \src "ls180.v:1271.5-1271.50" + wire $1\main_sdphy_datar_datar_converter_demux[0:0] + attribute \src "ls180.v:1267.5-1267.57" + wire $1\main_sdphy_datar_datar_converter_source_first[0:0] + attribute \src "ls180.v:1268.5-1268.56" + wire $1\main_sdphy_datar_datar_converter_source_last[0:0] + attribute \src "ls180.v:1269.11-1269.70" + wire width 8 $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] + attribute \src "ls180.v:1270.11-1270.83" + wire width 2 $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + attribute \src "ls180.v:1273.5-1273.55" + wire $1\main_sdphy_datar_datar_converter_strobe_all[0:0] + attribute \src "ls180.v:1289.5-1289.40" + wire $1\main_sdphy_datar_datar_reset[0:0] + attribute \src "ls180.v:1778.5-1778.69" + wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + attribute \src "ls180.v:1779.5-1779.72" + wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + attribute \src "ls180.v:1259.5-1259.38" + wire $1\main_sdphy_datar_datar_run[0:0] + attribute \src "ls180.v:1254.5-1254.55" + wire $1\main_sdphy_datar_datar_source_source_ready0[0:0] + attribute \src "ls180.v:1224.5-1224.49" + wire $1\main_sdphy_datar_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1231.5-1231.38" + wire $1\main_sdphy_datar_sink_last[0:0] + attribute \src "ls180.v:1232.11-1232.61" + wire width 10 $1\main_sdphy_datar_sink_payload_block_length[9:0] + attribute \src "ls180.v:1230.5-1230.39" + wire $1\main_sdphy_datar_sink_ready[0:0] + attribute \src "ls180.v:1229.5-1229.39" + wire $1\main_sdphy_datar_sink_valid[0:0] + attribute \src "ls180.v:1236.5-1236.40" + wire $1\main_sdphy_datar_source_last[0:0] + attribute \src "ls180.v:1237.11-1237.54" + wire width 8 $1\main_sdphy_datar_source_payload_data[7:0] + attribute \src "ls180.v:1238.11-1238.56" + wire width 3 $1\main_sdphy_datar_source_payload_status[2:0] + attribute \src "ls180.v:1234.5-1234.41" + wire $1\main_sdphy_datar_source_ready[0:0] + attribute \src "ls180.v:1233.5-1233.41" + wire $1\main_sdphy_datar_source_valid[0:0] + attribute \src "ls180.v:1239.5-1239.33" + wire $1\main_sdphy_datar_stop[0:0] + attribute \src "ls180.v:1240.12-1240.49" + wire width 32 $1\main_sdphy_datar_timeout[31:0] + attribute \src "ls180.v:1776.12-1776.73" + wire width 32 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + attribute \src "ls180.v:1777.5-1777.68" + wire $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + attribute \src "ls180.v:1149.11-1149.40" + wire width 8 $1\main_sdphy_dataw_count[7:0] + attribute \src "ls180.v:1770.11-1770.61" + wire width 8 $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + attribute \src "ls180.v:1771.5-1771.58" + wire $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + attribute \src "ls180.v:1208.5-1208.50" + wire $1\main_sdphy_dataw_crcr_buf_source_first[0:0] + attribute \src "ls180.v:1209.5-1209.49" + wire $1\main_sdphy_dataw_crcr_buf_source_last[0:0] + attribute \src "ls180.v:1210.11-1210.63" + wire width 8 $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + attribute \src "ls180.v:1206.5-1206.50" + wire $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] + attribute \src "ls180.v:1193.11-1193.55" + wire width 3 $1\main_sdphy_dataw_crcr_converter_demux[2:0] + attribute \src "ls180.v:1189.5-1189.56" + wire $1\main_sdphy_dataw_crcr_converter_source_first[0:0] + attribute \src "ls180.v:1190.5-1190.55" + wire $1\main_sdphy_dataw_crcr_converter_source_last[0:0] + attribute \src "ls180.v:1191.11-1191.69" + wire width 8 $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + attribute \src "ls180.v:1192.11-1192.82" + wire width 4 $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:1195.5-1195.54" + wire $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + attribute \src "ls180.v:1211.5-1211.39" + wire $1\main_sdphy_dataw_crcr_reset[0:0] + attribute \src "ls180.v:1766.5-1766.66" + wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + attribute \src "ls180.v:1767.5-1767.69" + wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + attribute \src "ls180.v:1181.5-1181.37" + wire $1\main_sdphy_dataw_crcr_run[0:0] + attribute \src "ls180.v:1176.5-1176.54" + wire $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] + attribute \src "ls180.v:1163.5-1163.34" + wire $1\main_sdphy_dataw_error[0:0] + attribute \src "ls180.v:1138.5-1138.49" + wire $1\main_sdphy_dataw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1141.11-1141.58" + wire width 4 $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1142.5-1142.53" + wire $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:1145.5-1145.39" + wire $1\main_sdphy_dataw_sink_first[0:0] + attribute \src "ls180.v:1146.5-1146.38" + wire $1\main_sdphy_dataw_sink_last[0:0] + attribute \src "ls180.v:1147.11-1147.52" + wire width 8 $1\main_sdphy_dataw_sink_payload_data[7:0] + attribute \src "ls180.v:1144.5-1144.39" + wire $1\main_sdphy_dataw_sink_ready[0:0] + attribute \src "ls180.v:1143.5-1143.39" + wire $1\main_sdphy_dataw_sink_valid[0:0] + attribute \src "ls180.v:1161.5-1161.34" + wire $1\main_sdphy_dataw_start[0:0] + attribute \src "ls180.v:1148.5-1148.33" + wire $1\main_sdphy_dataw_stop[0:0] + attribute \src "ls180.v:1162.5-1162.34" + wire $1\main_sdphy_dataw_valid[0:0] + attribute \src "ls180.v:1042.11-1042.39" + wire width 8 $1\main_sdphy_init_count[7:0] + attribute \src "ls180.v:1750.11-1750.66" + wire width 8 $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + attribute \src "ls180.v:1751.5-1751.63" + wire $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + attribute \src "ls180.v:1037.5-1037.48" + wire $1\main_sdphy_init_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1038.5-1038.50" + wire $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1039.5-1039.51" + wire $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1040.11-1040.57" + wire width 4 $1\main_sdphy_init_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1041.5-1041.52" + wire $1\main_sdphy_init_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:1291.5-1291.35" + wire $1\main_sdphy_sdpads_cmd_i[0:0] + attribute \src "ls180.v:1294.11-1294.42" + wire width 4 $1\main_sdphy_sdpads_data_i[3:0] + attribute \src "ls180.v:300.5-300.33" + wire $1\main_sdram_address_re[0:0] + attribute \src "ls180.v:299.12-299.46" + wire width 13 $1\main_sdram_address_storage[12:0] + attribute \src "ls180.v:302.5-302.34" + wire $1\main_sdram_baddress_re[0:0] + attribute \src "ls180.v:301.11-301.45" + wire width 2 $1\main_sdram_baddress_storage[1:0] + attribute \src "ls180.v:398.5-398.50" + wire $1\main_sdram_bankmachine0_auto_precharge[0:0] + attribute \src "ls180.v:420.11-420.70" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:417.11-417.68" + wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:419.11-419.70" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:421.11-421.73" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:444.5-444.59" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:445.5-445.58" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:447.12-447.74" + wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:446.5-446.64" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:442.5-442.59" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:390.12-390.57" + wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + attribute \src "ls180.v:392.5-392.51" + wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] + attribute \src "ls180.v:395.5-395.54" + wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:396.5-396.55" + wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + attribute \src "ls180.v:397.5-397.56" + wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + attribute \src "ls180.v:393.5-393.51" + wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] + attribute \src "ls180.v:394.5-394.50" + wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0] + attribute \src "ls180.v:389.5-389.45" + wire $1\main_sdram_bankmachine0_cmd_ready[0:0] + attribute \src "ls180.v:388.5-388.45" + wire $1\main_sdram_bankmachine0_cmd_valid[0:0] + attribute \src "ls180.v:387.5-387.47" + wire $1\main_sdram_bankmachine0_refresh_gnt[0:0] + attribute \src "ls180.v:385.5-385.51" + wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0] + attribute \src "ls180.v:384.5-384.51" + wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + attribute \src "ls180.v:448.12-448.47" + wire width 13 $1\main_sdram_bankmachine0_row[12:0] + attribute \src "ls180.v:452.5-452.45" + wire $1\main_sdram_bankmachine0_row_close[0:0] + attribute \src "ls180.v:453.5-453.54" + wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:451.5-451.44" + wire $1\main_sdram_bankmachine0_row_open[0:0] + attribute \src "ls180.v:449.5-449.46" + wire $1\main_sdram_bankmachine0_row_opened[0:0] + attribute \src "ls180.v:456.11-456.55" + wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0] + attribute \src "ls180.v:455.32-455.76" + wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0] + attribute \src "ls180.v:480.5-480.50" + wire $1\main_sdram_bankmachine1_auto_precharge[0:0] + attribute \src "ls180.v:502.11-502.70" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:499.11-499.68" + wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:501.11-501.70" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:503.11-503.73" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:526.5-526.59" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:527.5-527.58" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:529.12-529.74" + wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:528.5-528.64" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:524.5-524.59" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:472.12-472.57" + wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0] + attribute \src "ls180.v:474.5-474.51" + wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] + attribute \src "ls180.v:477.5-477.54" + wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:478.5-478.55" + wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + attribute \src "ls180.v:479.5-479.56" + wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + attribute \src "ls180.v:475.5-475.51" + wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + attribute \src "ls180.v:476.5-476.50" + wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + attribute \src "ls180.v:471.5-471.45" + wire $1\main_sdram_bankmachine1_cmd_ready[0:0] + attribute \src "ls180.v:470.5-470.45" + wire $1\main_sdram_bankmachine1_cmd_valid[0:0] + attribute \src "ls180.v:469.5-469.47" + wire $1\main_sdram_bankmachine1_refresh_gnt[0:0] + attribute \src "ls180.v:467.5-467.51" + wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + attribute \src "ls180.v:466.5-466.51" + wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0] + attribute \src "ls180.v:530.12-530.47" + wire width 13 $1\main_sdram_bankmachine1_row[12:0] + attribute \src "ls180.v:534.5-534.45" + wire $1\main_sdram_bankmachine1_row_close[0:0] + attribute \src "ls180.v:535.5-535.54" + wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:533.5-533.44" + wire $1\main_sdram_bankmachine1_row_open[0:0] + attribute \src "ls180.v:531.5-531.46" + wire $1\main_sdram_bankmachine1_row_opened[0:0] + attribute \src "ls180.v:538.11-538.55" + wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0] + attribute \src "ls180.v:537.32-537.76" + wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0] + attribute \src "ls180.v:562.5-562.50" + wire $1\main_sdram_bankmachine2_auto_precharge[0:0] + attribute \src "ls180.v:584.11-584.70" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:581.11-581.68" + wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:583.11-583.70" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:585.11-585.73" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:608.5-608.59" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:609.5-609.58" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:611.12-611.74" + wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:610.5-610.64" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:606.5-606.59" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:554.12-554.57" + wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0] + attribute \src "ls180.v:556.5-556.51" + wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] + attribute \src "ls180.v:559.5-559.54" + wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:560.5-560.55" + wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + attribute \src "ls180.v:561.5-561.56" + wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + attribute \src "ls180.v:557.5-557.51" + wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] + attribute \src "ls180.v:558.5-558.50" + wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0] + attribute \src "ls180.v:553.5-553.45" + wire $1\main_sdram_bankmachine2_cmd_ready[0:0] + attribute \src "ls180.v:552.5-552.45" + wire $1\main_sdram_bankmachine2_cmd_valid[0:0] + attribute \src "ls180.v:551.5-551.47" + wire $1\main_sdram_bankmachine2_refresh_gnt[0:0] + attribute \src "ls180.v:549.5-549.51" + wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0] + attribute \src "ls180.v:548.5-548.51" + wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0] + attribute \src "ls180.v:612.12-612.47" + wire width 13 $1\main_sdram_bankmachine2_row[12:0] + attribute \src "ls180.v:616.5-616.45" + wire $1\main_sdram_bankmachine2_row_close[0:0] + attribute \src "ls180.v:617.5-617.54" + wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:615.5-615.44" + wire $1\main_sdram_bankmachine2_row_open[0:0] + attribute \src "ls180.v:613.5-613.46" + wire $1\main_sdram_bankmachine2_row_opened[0:0] + attribute \src "ls180.v:620.11-620.55" + wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0] + attribute \src "ls180.v:619.32-619.76" + wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0] + attribute \src "ls180.v:644.5-644.50" + wire $1\main_sdram_bankmachine3_auto_precharge[0:0] + attribute \src "ls180.v:666.11-666.70" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:663.11-663.68" + wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:665.11-665.70" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:667.11-667.73" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:690.5-690.59" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:691.5-691.58" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:693.12-693.74" + wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:692.5-692.64" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:688.5-688.59" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:636.12-636.57" + wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0] + attribute \src "ls180.v:638.5-638.51" + wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] + attribute \src "ls180.v:641.5-641.54" + wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:642.5-642.55" + wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + attribute \src "ls180.v:643.5-643.56" + wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + attribute \src "ls180.v:639.5-639.51" + wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] + attribute \src "ls180.v:640.5-640.50" + wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0] + attribute \src "ls180.v:635.5-635.45" + wire $1\main_sdram_bankmachine3_cmd_ready[0:0] + attribute \src "ls180.v:634.5-634.45" + wire $1\main_sdram_bankmachine3_cmd_valid[0:0] + attribute \src "ls180.v:633.5-633.47" + wire $1\main_sdram_bankmachine3_refresh_gnt[0:0] + attribute \src "ls180.v:631.5-631.51" + wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0] + attribute \src "ls180.v:630.5-630.51" + wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0] + attribute \src "ls180.v:694.12-694.47" + wire width 13 $1\main_sdram_bankmachine3_row[12:0] + attribute \src "ls180.v:698.5-698.45" + wire $1\main_sdram_bankmachine3_row_close[0:0] + attribute \src "ls180.v:699.5-699.54" + wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:697.5-697.44" + wire $1\main_sdram_bankmachine3_row_open[0:0] + attribute \src "ls180.v:695.5-695.46" + wire $1\main_sdram_bankmachine3_row_opened[0:0] + attribute \src "ls180.v:702.11-702.55" + wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0] + attribute \src "ls180.v:701.32-701.76" + wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0] + attribute \src "ls180.v:717.5-717.49" + wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] + attribute \src "ls180.v:718.5-718.49" + wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] + attribute \src "ls180.v:719.5-719.48" + wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0] + attribute \src "ls180.v:725.11-725.45" + wire width 2 $1\main_sdram_choose_cmd_grant[1:0] + attribute \src "ls180.v:723.11-723.46" + wire width 4 $1\main_sdram_choose_cmd_valids[3:0] + attribute \src "ls180.v:735.5-735.49" + wire $1\main_sdram_choose_req_cmd_payload_cas[0:0] + attribute \src "ls180.v:736.5-736.49" + wire $1\main_sdram_choose_req_cmd_payload_ras[0:0] + attribute \src "ls180.v:737.5-737.48" + wire $1\main_sdram_choose_req_cmd_payload_we[0:0] + attribute \src "ls180.v:732.5-732.43" + wire $1\main_sdram_choose_req_cmd_ready[0:0] + attribute \src "ls180.v:743.11-743.45" + wire width 2 $1\main_sdram_choose_req_grant[1:0] + attribute \src "ls180.v:741.11-741.46" + wire width 4 $1\main_sdram_choose_req_valids[3:0] + attribute \src "ls180.v:730.5-730.48" + wire $1\main_sdram_choose_req_want_activates[0:0] + attribute \src "ls180.v:727.5-727.44" + wire $1\main_sdram_choose_req_want_reads[0:0] + attribute \src "ls180.v:728.5-728.45" + wire $1\main_sdram_choose_req_want_writes[0:0] + attribute \src "ls180.v:356.5-356.31" + wire $1\main_sdram_cmd_last[0:0] + attribute \src "ls180.v:357.12-357.44" + wire width 13 $1\main_sdram_cmd_payload_a[12:0] + attribute \src "ls180.v:358.11-358.43" + wire width 2 $1\main_sdram_cmd_payload_ba[1:0] + attribute \src "ls180.v:359.5-359.38" + wire $1\main_sdram_cmd_payload_cas[0:0] + attribute \src "ls180.v:360.5-360.38" + wire $1\main_sdram_cmd_payload_ras[0:0] + attribute \src "ls180.v:361.5-361.37" + wire $1\main_sdram_cmd_payload_we[0:0] + attribute \src "ls180.v:355.5-355.32" + wire $1\main_sdram_cmd_ready[0:0] + attribute \src "ls180.v:354.5-354.32" + wire $1\main_sdram_cmd_valid[0:0] + attribute \src "ls180.v:294.5-294.33" + wire $1\main_sdram_command_re[0:0] + attribute \src "ls180.v:293.11-293.44" + wire width 6 $1\main_sdram_command_storage[5:0] + attribute \src "ls180.v:338.12-338.45" + wire width 13 $1\main_sdram_dfi_p0_address[12:0] + attribute \src "ls180.v:339.11-339.40" + wire width 2 $1\main_sdram_dfi_p0_bank[1:0] + attribute \src "ls180.v:340.5-340.35" + wire $1\main_sdram_dfi_p0_cas_n[0:0] + attribute \src "ls180.v:341.5-341.34" + wire $1\main_sdram_dfi_p0_cs_n[0:0] + attribute \src "ls180.v:342.5-342.35" + wire $1\main_sdram_dfi_p0_ras_n[0:0] + attribute \src "ls180.v:351.5-351.39" + wire $1\main_sdram_dfi_p0_rddata_en[0:0] + attribute \src "ls180.v:343.5-343.34" + wire $1\main_sdram_dfi_p0_we_n[0:0] + attribute \src "ls180.v:349.5-349.39" + wire $1\main_sdram_dfi_p0_wrdata_en[0:0] + attribute \src "ls180.v:762.5-762.26" + wire $1\main_sdram_en0[0:0] + attribute \src "ls180.v:765.5-765.26" + wire $1\main_sdram_en1[0:0] + attribute \src "ls180.v:335.12-335.46" + wire width 16 $1\main_sdram_interface_wdata[15:0] + attribute \src "ls180.v:336.11-336.47" + wire width 2 $1\main_sdram_interface_wdata_we[1:0] + attribute \src "ls180.v:241.5-241.36" + wire $1\main_sdram_inti_p0_cas_n[0:0] + attribute \src "ls180.v:242.5-242.35" + wire $1\main_sdram_inti_p0_cs_n[0:0] + attribute \src "ls180.v:243.5-243.36" + wire $1\main_sdram_inti_p0_ras_n[0:0] + attribute \src "ls180.v:253.12-253.45" + wire width 16 $1\main_sdram_inti_p0_rddata[15:0] + attribute \src "ls180.v:254.5-254.43" + wire $1\main_sdram_inti_p0_rddata_valid[0:0] + attribute \src "ls180.v:244.5-244.35" + wire $1\main_sdram_inti_p0_we_n[0:0] + attribute \src "ls180.v:280.5-280.38" + wire $1\main_sdram_master_p0_act_n[0:0] + attribute \src "ls180.v:271.12-271.48" + wire width 13 $1\main_sdram_master_p0_address[12:0] + attribute \src "ls180.v:272.11-272.43" + wire width 2 $1\main_sdram_master_p0_bank[1:0] + attribute \src "ls180.v:273.5-273.38" + wire $1\main_sdram_master_p0_cas_n[0:0] + attribute \src "ls180.v:277.5-277.36" + wire $1\main_sdram_master_p0_cke[0:0] + attribute \src "ls180.v:274.5-274.37" + wire $1\main_sdram_master_p0_cs_n[0:0] + attribute \src "ls180.v:278.5-278.36" + wire $1\main_sdram_master_p0_odt[0:0] + attribute \src "ls180.v:275.5-275.38" + wire $1\main_sdram_master_p0_ras_n[0:0] + attribute \src "ls180.v:284.5-284.42" + wire $1\main_sdram_master_p0_rddata_en[0:0] + attribute \src "ls180.v:279.5-279.40" + wire $1\main_sdram_master_p0_reset_n[0:0] + attribute \src "ls180.v:276.5-276.37" + wire $1\main_sdram_master_p0_we_n[0:0] + attribute \src "ls180.v:281.12-281.47" + wire width 16 $1\main_sdram_master_p0_wrdata[15:0] + attribute \src "ls180.v:282.5-282.42" + wire $1\main_sdram_master_p0_wrdata_en[0:0] + attribute \src "ls180.v:283.11-283.50" + wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0] + attribute \src "ls180.v:372.5-372.38" + wire $1\main_sdram_postponer_count[0:0] + attribute \src "ls180.v:371.5-371.38" + wire $1\main_sdram_postponer_req_o[0:0] + attribute \src "ls180.v:292.5-292.25" + wire $1\main_sdram_re[0:0] + attribute \src "ls180.v:378.5-378.38" + wire $1\main_sdram_sequencer_count[0:0] + attribute \src "ls180.v:377.11-377.46" + wire width 4 $1\main_sdram_sequencer_counter[3:0] + attribute \src "ls180.v:376.5-376.38" + wire $1\main_sdram_sequencer_done1[0:0] + attribute \src "ls180.v:373.5-373.39" + wire $1\main_sdram_sequencer_start0[0:0] + attribute \src "ls180.v:269.12-269.46" + wire width 16 $1\main_sdram_slave_p0_rddata[15:0] + attribute \src "ls180.v:270.5-270.44" + wire $1\main_sdram_slave_p0_rddata_valid[0:0] + attribute \src "ls180.v:305.12-305.37" + wire width 16 $1\main_sdram_status[15:0] + attribute \src "ls180.v:747.11-747.40" + wire width 2 $1\main_sdram_steerer_sel[1:0] + attribute \src "ls180.v:291.11-291.36" + wire width 4 $1\main_sdram_storage[3:0] + attribute \src "ls180.v:756.5-756.36" + wire $1\main_sdram_tccdcon_count[0:0] + attribute \src "ls180.v:755.32-755.63" + wire $1\main_sdram_tccdcon_ready[0:0] + attribute \src "ls180.v:764.11-764.34" + wire width 5 $1\main_sdram_time0[4:0] + attribute \src "ls180.v:767.11-767.34" + wire width 4 $1\main_sdram_time1[3:0] + attribute \src "ls180.v:369.11-369.44" + wire width 10 $1\main_sdram_timer_count1[9:0] + attribute \src "ls180.v:759.11-759.42" + wire width 3 $1\main_sdram_twtrcon_count[2:0] + attribute \src "ls180.v:758.32-758.63" + wire $1\main_sdram_twtrcon_ready[0:0] + attribute \src "ls180.v:304.5-304.32" + wire $1\main_sdram_wrdata_re[0:0] + attribute \src "ls180.v:303.12-303.45" + wire width 16 $1\main_sdram_wrdata_storage[15:0] + attribute \src "ls180.v:813.5-813.27" + wire $1\main_sink_ready[0:0] + attribute \src "ls180.v:826.11-826.42" + wire width 8 $1\main_source_payload_data[7:0] + attribute \src "ls180.v:822.5-822.29" + wire $1\main_source_valid[0:0] + attribute \src "ls180.v:991.12-991.48" + wire width 16 $1\main_spi_master_clk_divider1[15:0] + attribute \src "ls180.v:986.5-986.38" + wire $1\main_spi_master_clk_enable[0:0] + attribute \src "ls180.v:973.5-973.38" + wire $1\main_spi_master_control_re[0:0] + attribute \src "ls180.v:972.12-972.51" + wire width 16 $1\main_spi_master_control_storage[15:0] + attribute \src "ls180.v:988.11-988.39" + wire width 3 $1\main_spi_master_count[2:0] + attribute \src "ls180.v:1746.11-1746.61" + wire width 3 $1\main_spi_master_count_spimaster0_next_value[2:0] + attribute \src "ls180.v:1747.5-1747.58" + wire $1\main_spi_master_count_spimaster0_next_value_ce[0:0] + attribute \src "ls180.v:987.5-987.37" + wire $1\main_spi_master_cs_enable[0:0] + attribute \src "ls180.v:983.5-983.33" + wire $1\main_spi_master_cs_re[0:0] + attribute \src "ls180.v:982.5-982.38" + wire $1\main_spi_master_cs_storage[0:0] + attribute \src "ls180.v:963.5-963.33" + wire $1\main_spi_master_done0[0:0] + attribute \src "ls180.v:964.5-964.31" + wire $1\main_spi_master_irq[0:0] + attribute \src "ls180.v:985.5-985.39" + wire $1\main_spi_master_loopback_re[0:0] + attribute \src "ls180.v:984.5-984.44" + wire $1\main_spi_master_loopback_storage[0:0] + attribute \src "ls180.v:966.11-966.38" + wire width 8 $1\main_spi_master_miso[7:0] + attribute \src "ls180.v:996.11-996.43" + wire width 8 $1\main_spi_master_miso_data[7:0] + attribute \src "ls180.v:990.5-990.38" + wire $1\main_spi_master_miso_latch[0:0] + attribute \src "ls180.v:994.11-994.43" + wire width 8 $1\main_spi_master_mosi_data[7:0] + attribute \src "ls180.v:989.5-989.38" + wire $1\main_spi_master_mosi_latch[0:0] + attribute \src "ls180.v:978.5-978.35" + wire $1\main_spi_master_mosi_re[0:0] + attribute \src "ls180.v:995.11-995.42" + wire width 3 $1\main_spi_master_mosi_sel[2:0] + attribute \src "ls180.v:977.11-977.46" + wire width 8 $1\main_spi_master_mosi_storage[7:0] + attribute \src "ls180.v:970.5-970.34" + wire $1\main_spi_master_start1[0:0] + attribute \src "ls180.v:810.12-810.38" + wire width 32 $1\main_storage[31:0] + attribute \src "ls180.v:820.11-820.34" + wire width 4 $1\main_tx_bitcount[3:0] + attribute \src "ls180.v:821.5-821.24" + wire $1\main_tx_busy[0:0] + attribute \src "ls180.v:819.11-819.29" + wire width 8 $1\main_tx_reg[7:0] + attribute \src "ls180.v:827.5-827.30" + wire $1\main_uart_clk_rxen[0:0] + attribute \src "ls180.v:817.5-817.30" + wire $1\main_uart_clk_txen[0:0] + attribute \src "ls180.v:860.11-860.50" + wire width 2 $1\main_uart_eventmanager_pending_w[1:0] + attribute \src "ls180.v:862.5-862.37" + wire $1\main_uart_eventmanager_re[0:0] + attribute \src "ls180.v:856.11-856.49" + wire width 2 $1\main_uart_eventmanager_status_w[1:0] + attribute \src "ls180.v:861.11-861.48" + wire width 2 $1\main_uart_eventmanager_storage[1:0] + attribute \src "ls180.v:851.5-851.30" + wire $1\main_uart_rx_clear[0:0] + attribute \src "ls180.v:935.11-935.43" + wire width 4 $1\main_uart_rx_fifo_consume[3:0] + attribute \src "ls180.v:932.11-932.42" + wire width 5 $1\main_uart_rx_fifo_level0[4:0] + attribute \src "ls180.v:934.11-934.43" + wire width 4 $1\main_uart_rx_fifo_produce[3:0] + attribute \src "ls180.v:925.5-925.38" + wire $1\main_uart_rx_fifo_readable[0:0] + attribute \src "ls180.v:936.11-936.46" + wire width 4 $1\main_uart_rx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:852.5-852.36" + wire $1\main_uart_rx_old_trigger[0:0] + attribute \src "ls180.v:849.5-849.32" + wire $1\main_uart_rx_pending[0:0] + attribute \src "ls180.v:846.5-846.30" + wire $1\main_uart_tx_clear[0:0] + attribute \src "ls180.v:898.11-898.43" + wire width 4 $1\main_uart_tx_fifo_consume[3:0] + attribute \src "ls180.v:895.11-895.42" + wire width 5 $1\main_uart_tx_fifo_level0[4:0] + attribute \src "ls180.v:897.11-897.43" + wire width 4 $1\main_uart_tx_fifo_produce[3:0] + attribute \src "ls180.v:888.5-888.38" + wire $1\main_uart_tx_fifo_readable[0:0] + attribute \src "ls180.v:899.11-899.46" + wire width 4 $1\main_uart_tx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:847.5-847.36" + wire $1\main_uart_tx_old_trigger[0:0] + attribute \src "ls180.v:844.5-844.32" + wire $1\main_uart_tx_pending[0:0] + attribute \src "ls180.v:788.5-788.29" + wire $1\main_wb_sdram_ack[0:0] + attribute \src "ls180.v:806.5-806.31" + wire $1\main_wdata_consumed[0:0] + attribute \src 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"ls180.v:6084.105-6084.149" + wire $eq$ls180.v:6084$1718_Y + attribute \src "ls180.v:6086.102-6086.146" + wire $eq$ls180.v:6086$1721_Y + attribute \src "ls180.v:6087.105-6087.149" + wire $eq$ls180.v:6087$1725_Y + attribute \src "ls180.v:6089.102-6089.147" + wire $eq$ls180.v:6089$1728_Y + attribute \src "ls180.v:6090.105-6090.150" + wire $eq$ls180.v:6090$1732_Y + attribute \src "ls180.v:6092.102-6092.147" + wire $eq$ls180.v:6092$1735_Y + attribute \src "ls180.v:6093.105-6093.150" + wire $eq$ls180.v:6093$1739_Y + attribute \src "ls180.v:6095.102-6095.147" + wire $eq$ls180.v:6095$1742_Y + attribute \src "ls180.v:6096.105-6096.150" + wire $eq$ls180.v:6096$1746_Y + attribute \src "ls180.v:6098.99-6098.144" + wire $eq$ls180.v:6098$1749_Y + attribute \src "ls180.v:6099.102-6099.147" + wire $eq$ls180.v:6099$1753_Y + attribute \src "ls180.v:6101.100-6101.145" + wire $eq$ls180.v:6101$1756_Y + attribute \src "ls180.v:6102.103-6102.148" + wire $eq$ls180.v:6102$1760_Y + attribute \src "ls180.v:6104.102-6104.147" + wire $eq$ls180.v:6104$1763_Y + attribute \src "ls180.v:6105.105-6105.150" + wire $eq$ls180.v:6105$1767_Y + attribute \src "ls180.v:6107.102-6107.147" + wire $eq$ls180.v:6107$1770_Y + attribute \src "ls180.v:6108.105-6108.150" + wire $eq$ls180.v:6108$1774_Y + attribute \src "ls180.v:6110.102-6110.147" + wire $eq$ls180.v:6110$1777_Y + attribute \src "ls180.v:6111.105-6111.150" + wire $eq$ls180.v:6111$1781_Y + attribute \src "ls180.v:6113.102-6113.147" + wire $eq$ls180.v:6113$1784_Y + attribute \src "ls180.v:6114.105-6114.150" + wire $eq$ls180.v:6114$1788_Y + attribute \src "ls180.v:6136.32-6136.78" + wire $eq$ls180.v:6136$1790_Y + attribute \src "ls180.v:6138.102-6138.146" + wire $eq$ls180.v:6138$1792_Y + attribute \src "ls180.v:6139.105-6139.149" + wire $eq$ls180.v:6139$1796_Y + attribute \src "ls180.v:6141.107-6141.151" + wire $eq$ls180.v:6141$1799_Y + attribute \src "ls180.v:6142.110-6142.154" + wire $eq$ls180.v:6142$1803_Y + attribute \src "ls180.v:6144.107-6144.151" + wire $eq$ls180.v:6144$1806_Y + attribute \src "ls180.v:6145.110-6145.154" + wire $eq$ls180.v:6145$1810_Y + attribute \src "ls180.v:6147.100-6147.144" + wire $eq$ls180.v:6147$1813_Y + attribute \src "ls180.v:6148.103-6148.147" + wire $eq$ls180.v:6148$1817_Y + attribute \src "ls180.v:6153.32-6153.77" + wire $eq$ls180.v:6153$1819_Y + attribute \src "ls180.v:6155.104-6155.148" + wire $eq$ls180.v:6155$1821_Y + attribute \src "ls180.v:6156.107-6156.151" + wire $eq$ls180.v:6156$1825_Y + attribute \src "ls180.v:6158.108-6158.152" + wire $eq$ls180.v:6158$1828_Y + attribute \src "ls180.v:6159.111-6159.155" + wire $eq$ls180.v:6159$1832_Y + attribute \src "ls180.v:6161.98-6161.142" + wire $eq$ls180.v:6161$1835_Y + attribute \src "ls180.v:6162.101-6162.145" + wire $eq$ls180.v:6162$1839_Y + attribute \src "ls180.v:6164.108-6164.152" + wire $eq$ls180.v:6164$1842_Y + attribute \src "ls180.v:6165.111-6165.155" + wire $eq$ls180.v:6165$1846_Y + attribute \src "ls180.v:6167.108-6167.152" + wire $eq$ls180.v:6167$1849_Y + attribute \src "ls180.v:6168.111-6168.155" + wire $eq$ls180.v:6168$1853_Y + attribute \src "ls180.v:6170.109-6170.153" + wire $eq$ls180.v:6170$1856_Y + attribute \src "ls180.v:6171.112-6171.156" + wire $eq$ls180.v:6171$1860_Y + attribute \src "ls180.v:6173.107-6173.151" + wire $eq$ls180.v:6173$1863_Y + attribute \src "ls180.v:6174.110-6174.154" + wire $eq$ls180.v:6174$1867_Y + attribute \src "ls180.v:6176.107-6176.151" + wire $eq$ls180.v:6176$1870_Y + attribute \src "ls180.v:6177.110-6177.154" + wire $eq$ls180.v:6177$1874_Y + attribute \src "ls180.v:6179.107-6179.151" + wire $eq$ls180.v:6179$1877_Y + attribute \src "ls180.v:6180.110-6180.154" + wire $eq$ls180.v:6180$1881_Y + attribute \src "ls180.v:6182.107-6182.151" + wire $eq$ls180.v:6182$1884_Y + attribute \src "ls180.v:6183.110-6183.154" + wire $eq$ls180.v:6183$1888_Y + attribute \src "ls180.v:6198.32-6198.77" + wire $eq$ls180.v:6198$1890_Y + attribute \src "ls180.v:6200.99-6200.143" + wire $eq$ls180.v:6200$1892_Y + attribute \src "ls180.v:6201.102-6201.146" + wire $eq$ls180.v:6201$1896_Y + attribute \src "ls180.v:6203.99-6203.143" + wire $eq$ls180.v:6203$1899_Y + attribute \src "ls180.v:6204.102-6204.146" + wire $eq$ls180.v:6204$1903_Y + attribute \src "ls180.v:6206.97-6206.141" + wire $eq$ls180.v:6206$1906_Y + attribute \src "ls180.v:6207.100-6207.144" + wire $eq$ls180.v:6207$1910_Y + attribute \src "ls180.v:6209.96-6209.140" + wire $eq$ls180.v:6209$1913_Y + attribute \src "ls180.v:6210.99-6210.143" + wire $eq$ls180.v:6210$1917_Y + attribute \src "ls180.v:6212.95-6212.139" + wire $eq$ls180.v:6212$1920_Y + attribute \src "ls180.v:6213.98-6213.142" + wire $eq$ls180.v:6213$1924_Y + attribute \src "ls180.v:6215.94-6215.138" + wire $eq$ls180.v:6215$1927_Y + attribute \src "ls180.v:6216.97-6216.141" + wire $eq$ls180.v:6216$1931_Y + attribute \src "ls180.v:6218.100-6218.144" + wire $eq$ls180.v:6218$1934_Y + attribute \src "ls180.v:6219.103-6219.147" + wire $eq$ls180.v:6219$1938_Y + attribute \src "ls180.v:6238.33-6238.80" + wire $eq$ls180.v:6238$1941_Y + attribute \src "ls180.v:6240.102-6240.147" + wire $eq$ls180.v:6240$1943_Y + attribute \src "ls180.v:6241.105-6241.150" + wire $eq$ls180.v:6241$1947_Y + attribute \src "ls180.v:6243.102-6243.147" + wire $eq$ls180.v:6243$1950_Y + attribute \src "ls180.v:6244.105-6244.150" + wire $eq$ls180.v:6244$1954_Y + attribute \src "ls180.v:6246.100-6246.145" + wire $eq$ls180.v:6246$1957_Y + attribute \src "ls180.v:6247.103-6247.148" + wire $eq$ls180.v:6247$1961_Y + attribute \src "ls180.v:6249.99-6249.144" + wire $eq$ls180.v:6249$1964_Y + attribute \src "ls180.v:6250.102-6250.147" + wire $eq$ls180.v:6250$1968_Y + attribute \src "ls180.v:6252.98-6252.143" + wire $eq$ls180.v:6252$1971_Y + attribute \src "ls180.v:6253.101-6253.146" + wire $eq$ls180.v:6253$1975_Y + attribute \src "ls180.v:6255.97-6255.142" + wire $eq$ls180.v:6255$1978_Y + attribute \src "ls180.v:6256.100-6256.145" + wire $eq$ls180.v:6256$1982_Y + attribute \src "ls180.v:6258.103-6258.148" + wire $eq$ls180.v:6258$1985_Y + attribute \src "ls180.v:6259.106-6259.151" + wire $eq$ls180.v:6259$1989_Y + attribute \src "ls180.v:6261.106-6261.151" + wire $eq$ls180.v:6261$1992_Y + attribute \src "ls180.v:6262.109-6262.154" + wire $eq$ls180.v:6262$1996_Y + attribute \src "ls180.v:6264.106-6264.151" + wire $eq$ls180.v:6264$1999_Y + attribute \src "ls180.v:6265.109-6265.154" + wire $eq$ls180.v:6265$2003_Y + attribute \src "ls180.v:6286.33-6286.79" + wire $eq$ls180.v:6286$2006_Y + attribute \src "ls180.v:6288.99-6288.144" + wire $eq$ls180.v:6288$2008_Y + attribute \src "ls180.v:6289.102-6289.147" + wire $eq$ls180.v:6289$2012_Y + attribute \src "ls180.v:6291.99-6291.144" + wire $eq$ls180.v:6291$2015_Y + attribute \src "ls180.v:6292.102-6292.147" + wire $eq$ls180.v:6292$2019_Y + attribute \src "ls180.v:6294.99-6294.144" + wire $eq$ls180.v:6294$2022_Y + attribute \src "ls180.v:6295.102-6295.147" + wire $eq$ls180.v:6295$2026_Y + attribute \src "ls180.v:6297.99-6297.144" + wire $eq$ls180.v:6297$2029_Y + attribute \src "ls180.v:6298.102-6298.147" + wire $eq$ls180.v:6298$2033_Y + attribute \src "ls180.v:6300.101-6300.146" + wire $eq$ls180.v:6300$2036_Y + attribute \src "ls180.v:6301.104-6301.149" + wire $eq$ls180.v:6301$2040_Y + attribute \src "ls180.v:6303.101-6303.146" + wire $eq$ls180.v:6303$2043_Y + attribute \src "ls180.v:6304.104-6304.149" + wire $eq$ls180.v:6304$2047_Y + attribute \src "ls180.v:6306.101-6306.146" + wire $eq$ls180.v:6306$2050_Y + attribute \src "ls180.v:6307.104-6307.149" + wire $eq$ls180.v:6307$2054_Y + attribute \src "ls180.v:6309.101-6309.146" + wire $eq$ls180.v:6309$2057_Y + attribute \src "ls180.v:6310.104-6310.149" + wire $eq$ls180.v:6310$2061_Y + attribute \src "ls180.v:6312.97-6312.142" + wire $eq$ls180.v:6312$2064_Y + attribute \src "ls180.v:6313.100-6313.145" + wire $eq$ls180.v:6313$2068_Y + attribute \src "ls180.v:6315.107-6315.152" + wire $eq$ls180.v:6315$2071_Y + attribute \src "ls180.v:6316.110-6316.155" + wire $eq$ls180.v:6316$2075_Y + attribute \src "ls180.v:6318.100-6318.146" + wire $eq$ls180.v:6318$2078_Y + attribute \src "ls180.v:6319.103-6319.149" + wire $eq$ls180.v:6319$2082_Y + attribute \src "ls180.v:6321.100-6321.146" + wire $eq$ls180.v:6321$2085_Y + attribute \src "ls180.v:6322.103-6322.149" + wire $eq$ls180.v:6322$2089_Y + attribute \src "ls180.v:6324.100-6324.146" + wire $eq$ls180.v:6324$2092_Y + attribute \src "ls180.v:6325.103-6325.149" + wire $eq$ls180.v:6325$2096_Y + attribute \src "ls180.v:6327.100-6327.146" + wire $eq$ls180.v:6327$2099_Y + attribute \src "ls180.v:6328.103-6328.149" + wire $eq$ls180.v:6328$2103_Y + attribute \src "ls180.v:6330.112-6330.158" + wire $eq$ls180.v:6330$2106_Y + attribute \src "ls180.v:6331.115-6331.161" + wire $eq$ls180.v:6331$2110_Y + attribute \src "ls180.v:6333.113-6333.159" + wire $eq$ls180.v:6333$2113_Y + attribute \src "ls180.v:6334.116-6334.162" + wire $eq$ls180.v:6334$2117_Y + attribute \src "ls180.v:6336.104-6336.150" + wire $eq$ls180.v:6336$2120_Y + attribute \src "ls180.v:6337.107-6337.153" + wire $eq$ls180.v:6337$2124_Y + attribute \src "ls180.v:6354.33-6354.79" + wire $eq$ls180.v:6354$2126_Y + attribute \src "ls180.v:6356.90-6356.135" + wire $eq$ls180.v:6356$2128_Y + attribute \src "ls180.v:6357.93-6357.138" + wire $eq$ls180.v:6357$2132_Y + attribute \src "ls180.v:6359.100-6359.145" + wire $eq$ls180.v:6359$2135_Y + attribute \src "ls180.v:6360.103-6360.148" + wire $eq$ls180.v:6360$2139_Y + attribute \src "ls180.v:6362.101-6362.146" + wire $eq$ls180.v:6362$2142_Y + attribute \src "ls180.v:6363.104-6363.149" + wire $eq$ls180.v:6363$2146_Y + attribute \src "ls180.v:6365.105-6365.150" + wire $eq$ls180.v:6365$2149_Y + attribute \src "ls180.v:6366.108-6366.153" + wire $eq$ls180.v:6366$2153_Y + attribute \src "ls180.v:6368.106-6368.151" + wire $eq$ls180.v:6368$2156_Y + attribute \src "ls180.v:6369.109-6369.154" + wire $eq$ls180.v:6369$2160_Y + attribute \src "ls180.v:6371.104-6371.149" + wire $eq$ls180.v:6371$2163_Y + attribute \src "ls180.v:6372.107-6372.152" + wire $eq$ls180.v:6372$2167_Y + attribute \src "ls180.v:6374.101-6374.146" + wire $eq$ls180.v:6374$2170_Y + attribute \src "ls180.v:6375.104-6375.149" + wire $eq$ls180.v:6375$2174_Y + attribute \src "ls180.v:6377.100-6377.145" + wire $eq$ls180.v:6377$2177_Y + attribute \src "ls180.v:6378.103-6378.148" + wire $eq$ls180.v:6378$2181_Y + attribute \src "ls180.v:6388.33-6388.79" + wire $eq$ls180.v:6388$2183_Y + attribute \src "ls180.v:6390.106-6390.151" + wire $eq$ls180.v:6390$2185_Y + attribute \src "ls180.v:6391.109-6391.154" + wire $eq$ls180.v:6391$2189_Y + attribute \src "ls180.v:6393.106-6393.151" + wire $eq$ls180.v:6393$2192_Y + attribute \src "ls180.v:6394.109-6394.154" + wire $eq$ls180.v:6394$2196_Y + attribute \src "ls180.v:6396.106-6396.151" + wire $eq$ls180.v:6396$2199_Y + attribute \src "ls180.v:6397.109-6397.154" + wire $eq$ls180.v:6397$2203_Y + attribute \src "ls180.v:6399.106-6399.151" + wire $eq$ls180.v:6399$2206_Y + attribute \src "ls180.v:6400.109-6400.154" + wire $eq$ls180.v:6400$2210_Y + attribute \src "ls180.v:6778.41-6778.81" + wire $eq$ls180.v:6778$2246_Y + attribute \src "ls180.v:6778.144-6778.177" + wire $eq$ls180.v:6778$2247_Y + attribute \src "ls180.v:6778.219-6778.252" + wire $eq$ls180.v:6778$2250_Y + attribute \src "ls180.v:6778.294-6778.327" + wire $eq$ls180.v:6778$2253_Y + attribute \src "ls180.v:6802.41-6802.81" + wire $eq$ls180.v:6802$2262_Y + attribute \src "ls180.v:6802.144-6802.177" + wire $eq$ls180.v:6802$2263_Y + attribute \src "ls180.v:6802.219-6802.252" + wire $eq$ls180.v:6802$2266_Y + attribute \src "ls180.v:6802.294-6802.327" + wire $eq$ls180.v:6802$2269_Y + attribute \src "ls180.v:6826.41-6826.81" + wire $eq$ls180.v:6826$2278_Y + attribute \src "ls180.v:6826.144-6826.177" + wire $eq$ls180.v:6826$2279_Y + attribute \src "ls180.v:6826.219-6826.252" + wire $eq$ls180.v:6826$2282_Y + attribute \src "ls180.v:6826.294-6826.327" + wire $eq$ls180.v:6826$2285_Y + attribute \src "ls180.v:6850.41-6850.81" + wire $eq$ls180.v:6850$2294_Y + attribute \src "ls180.v:6850.144-6850.177" + wire $eq$ls180.v:6850$2295_Y + attribute \src "ls180.v:6850.219-6850.252" + wire $eq$ls180.v:6850$2298_Y + attribute \src "ls180.v:6850.294-6850.327" + wire $eq$ls180.v:6850$2301_Y + attribute \src "ls180.v:7446.8-7446.38" + wire $eq$ls180.v:7446$2411_Y + attribute \src "ls180.v:7479.8-7479.42" + wire $eq$ls180.v:7479$2419_Y + attribute \src "ls180.v:7499.38-7499.74" + wire $eq$ls180.v:7499$2422_Y + attribute \src "ls180.v:7506.7-7506.43" + wire $eq$ls180.v:7506$2424_Y + attribute \src "ls180.v:7513.7-7513.43" + wire $eq$ls180.v:7513$2425_Y + attribute \src "ls180.v:7521.7-7521.43" + wire $eq$ls180.v:7521$2426_Y + attribute \src "ls180.v:7573.9-7573.54" + wire $eq$ls180.v:7573$2444_Y + attribute \src "ls180.v:7619.9-7619.54" + wire $eq$ls180.v:7619$2460_Y + attribute \src "ls180.v:7665.9-7665.54" + wire $eq$ls180.v:7665$2476_Y + attribute \src "ls180.v:7711.9-7711.54" + wire $eq$ls180.v:7711$2492_Y + attribute \src "ls180.v:7861.9-7861.41" + wire $eq$ls180.v:7861$2504_Y + attribute \src "ls180.v:7876.9-7876.41" + wire $eq$ls180.v:7876$2507_Y + attribute \src "ls180.v:7882.49-7882.82" + wire $eq$ls180.v:7882$2508_Y + attribute \src "ls180.v:7882.131-7882.164" + wire $eq$ls180.v:7882$2511_Y + attribute \src "ls180.v:7882.213-7882.246" + wire $eq$ls180.v:7882$2514_Y + attribute \src "ls180.v:7882.295-7882.328" + wire $eq$ls180.v:7882$2517_Y + attribute \src "ls180.v:7883.50-7883.83" + wire $eq$ls180.v:7883$2520_Y + attribute \src "ls180.v:7883.132-7883.165" + wire $eq$ls180.v:7883$2523_Y + attribute \src "ls180.v:7883.214-7883.247" + wire $eq$ls180.v:7883$2526_Y + attribute \src "ls180.v:7883.296-7883.329" + wire $eq$ls180.v:7883$2529_Y + attribute \src "ls180.v:7918.9-7918.33" + wire $eq$ls180.v:7918$2541_Y + attribute \src "ls180.v:7921.10-7921.34" + wire $eq$ls180.v:7921$2542_Y + attribute \src "ls180.v:7947.9-7947.33" + wire $eq$ls180.v:7947$2548_Y + attribute \src "ls180.v:7952.10-7952.34" + wire $eq$ls180.v:7952$2549_Y + attribute \src "ls180.v:8124.9-8124.53" + wire $eq$ls180.v:8124$2593_Y + attribute \src "ls180.v:8205.9-8205.54" + wire $eq$ls180.v:8205$2605_Y + attribute \src "ls180.v:8284.9-8284.55" + wire $eq$ls180.v:8284$2617_Y + attribute \src "ls180.v:8507.9-8507.49" + wire $eq$ls180.v:8507$2650_Y + attribute \src "ls180.v:8083.8-8083.54" + wire $ge$ls180.v:8083$2585_Y + attribute \src "ls180.v:8097.8-8097.54" + wire $ge$ls180.v:8097$2589_Y + attribute \src "ls180.v:5045.47-5045.83" + wire $gt$ls180.v:5045$907_Y + attribute \src "ls180.v:5051.7-5051.43" + wire $lt$ls180.v:5051$910_Y + attribute \src "ls180.v:8078.8-8078.43" + wire $lt$ls180.v:8078$2583_Y + attribute \src "ls180.v:8092.8-8092.43" + wire $lt$ls180.v:8092$2587_Y + attribute \src "ls180.v:9993.33-9993.36" + wire width 32 $memrd$\mem$ls180.v:9993$2697_DATA + attribute \src "ls180.v:10004.12-10004.19" + wire width 25 $memrd$\storage$ls180.v:10004$2702_DATA + attribute \src "ls180.v:10011.68-10011.75" + wire width 25 $memrd$\storage$ls180.v:10011$2704_DATA + attribute \src "ls180.v:10018.14-10018.23" + wire width 25 $memrd$\storage_1$ls180.v:10018$2709_DATA + attribute \src "ls180.v:10025.68-10025.77" + wire width 25 $memrd$\storage_1$ls180.v:10025$2711_DATA + attribute \src "ls180.v:10032.14-10032.23" + wire width 25 $memrd$\storage_2$ls180.v:10032$2716_DATA + attribute \src "ls180.v:10039.68-10039.77" + wire width 25 $memrd$\storage_2$ls180.v:10039$2718_DATA + attribute \src "ls180.v:10046.14-10046.23" + wire width 25 $memrd$\storage_3$ls180.v:10046$2723_DATA + attribute \src "ls180.v:10053.68-10053.77" + wire width 25 $memrd$\storage_3$ls180.v:10053$2725_DATA + attribute \src "ls180.v:10061.14-10061.23" + wire width 10 $memrd$\storage_4$ls180.v:10061$2730_DATA + attribute \src "ls180.v:10066.15-10066.24" + wire width 10 $memrd$\storage_4$ls180.v:10066$2732_DATA + attribute \src "ls180.v:10078.14-10078.23" + wire width 10 $memrd$\storage_5$ls180.v:10078$2737_DATA + attribute \src "ls180.v:10083.15-10083.24" + wire width 10 $memrd$\storage_5$ls180.v:10083$2739_DATA + attribute \src "ls180.v:10094.14-10094.23" + wire width 10 $memrd$\storage_6$ls180.v:10094$2744_DATA + attribute \src "ls180.v:10101.45-10101.54" + wire width 10 $memrd$\storage_6$ls180.v:10101$2746_DATA + attribute \src "ls180.v:10108.14-10108.23" + wire width 10 $memrd$\storage_7$ls180.v:10108$2751_DATA + attribute \src "ls180.v:10115.45-10115.54" + wire width 10 $memrd$\storage_7$ls180.v:10115$2753_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 7 $memwr$\mem$ls180.v:9983$1_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:9983$1_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:9983$1_EN + attribute \src "ls180.v:0.0-0.0" + wire width 7 $memwr$\mem$ls180.v:9985$2_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:9985$2_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:9985$2_EN + attribute \src "ls180.v:0.0-0.0" + wire width 7 $memwr$\mem$ls180.v:9987$3_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:9987$3_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:9987$3_EN + attribute \src "ls180.v:0.0-0.0" + wire width 7 $memwr$\mem$ls180.v:9989$4_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:9989$4_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:9989$4_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage$ls180.v:10003$5_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage$ls180.v:10003$5_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage$ls180.v:10003$5_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_1$ls180.v:10017$6_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_1$ls180.v:10017$6_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_1$ls180.v:10017$6_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_2$ls180.v:10031$7_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_2$ls180.v:10031$7_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_2$ls180.v:10031$7_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_3$ls180.v:10045$8_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_3$ls180.v:10045$8_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_3$ls180.v:10045$8_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\storage_4$ls180.v:10060$9_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_4$ls180.v:10060$9_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_4$ls180.v:10060$9_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\storage_5$ls180.v:10077$10_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_5$ls180.v:10077$10_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_5$ls180.v:10077$10_EN + attribute \src "ls180.v:0.0-0.0" + wire width 5 $memwr$\storage_6$ls180.v:10093$11_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_6$ls180.v:10093$11_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_6$ls180.v:10093$11_EN + attribute \src "ls180.v:0.0-0.0" + wire width 5 $memwr$\storage_7$ls180.v:10107$12_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_7$ls180.v:10107$12_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_7$ls180.v:10107$12_EN + attribute \src "ls180.v:2917.41-2917.71" + wire $ne$ls180.v:2917$60_Y + attribute \src "ls180.v:3083.70-3083.104" + wire $ne$ls180.v:3083$75_Y + attribute \src "ls180.v:3144.8-3144.142" + wire $ne$ls180.v:3144$94_Y + attribute \src "ls180.v:3176.75-3176.133" + wire $ne$ls180.v:3176$101_Y + attribute \src "ls180.v:3177.75-3177.133" + wire $ne$ls180.v:3177$102_Y + attribute \src "ls180.v:3301.8-3301.142" + wire $ne$ls180.v:3301$124_Y + attribute \src "ls180.v:3333.75-3333.133" + wire $ne$ls180.v:3333$131_Y + attribute \src "ls180.v:3334.75-3334.133" + wire $ne$ls180.v:3334$132_Y + attribute \src "ls180.v:3458.8-3458.142" + wire $ne$ls180.v:3458$154_Y + attribute \src "ls180.v:3490.75-3490.133" + wire $ne$ls180.v:3490$161_Y + attribute \src "ls180.v:3491.75-3491.133" + wire $ne$ls180.v:3491$162_Y + attribute \src "ls180.v:3615.8-3615.142" + wire $ne$ls180.v:3615$184_Y + attribute \src "ls180.v:3647.75-3647.133" + wire $ne$ls180.v:3647$191_Y + attribute \src "ls180.v:3648.75-3648.133" + wire $ne$ls180.v:3648$192_Y + attribute \src "ls180.v:4140.47-4140.80" + wire $ne$ls180.v:4140$590_Y + attribute \src "ls180.v:4141.47-4141.79" + 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"ls180.v:2725.45-2725.80" + wire $not$ls180.v:2725$14_Y + attribute \src "ls180.v:2764.61-2764.94" + wire $not$ls180.v:2764$19_Y + attribute \src "ls180.v:2765.61-2765.94" + wire $not$ls180.v:2765$20_Y + attribute \src "ls180.v:2785.45-2785.80" + wire $not$ls180.v:2785$25_Y + attribute \src "ls180.v:2824.61-2824.94" + wire $not$ls180.v:2824$30_Y + attribute \src "ls180.v:2825.61-2825.94" + wire $not$ls180.v:2825$31_Y + attribute \src "ls180.v:2845.45-2845.83" + wire $not$ls180.v:2845$36_Y + attribute \src "ls180.v:2884.61-2884.94" + wire $not$ls180.v:2884$41_Y + attribute \src "ls180.v:2885.61-2885.94" + wire $not$ls180.v:2885$42_Y + attribute \src "ls180.v:3032.34-3032.64" + wire $not$ls180.v:3032$67_Y + attribute \src "ls180.v:3033.31-3033.61" + wire $not$ls180.v:3033$68_Y + attribute \src "ls180.v:3034.32-3034.62" + wire $not$ls180.v:3034$69_Y + attribute \src "ls180.v:3035.32-3035.62" + wire $not$ls180.v:3035$70_Y + attribute \src "ls180.v:3077.33-3077.56" + wire $not$ls180.v:3077$73_Y + attribute \src "ls180.v:3178.58-3178.106" + wire $not$ls180.v:3178$103_Y + attribute \src "ls180.v:3232.9-3232.45" + wire $not$ls180.v:3232$108_Y + attribute \src "ls180.v:3335.58-3335.106" + wire $not$ls180.v:3335$133_Y + attribute \src "ls180.v:3389.9-3389.45" + wire $not$ls180.v:3389$138_Y + attribute \src "ls180.v:3492.58-3492.106" + wire $not$ls180.v:3492$163_Y + attribute \src "ls180.v:3546.9-3546.45" + wire $not$ls180.v:3546$168_Y + attribute \src "ls180.v:3649.58-3649.106" + wire $not$ls180.v:3649$193_Y + attribute \src "ls180.v:3703.9-3703.45" + wire $not$ls180.v:3703$198_Y + attribute \src "ls180.v:3745.149-3745.187" + wire $not$ls180.v:3745$201_Y + attribute \src "ls180.v:3745.193-3745.230" + wire $not$ls180.v:3745$203_Y + attribute \src "ls180.v:3746.149-3746.187" + wire $not$ls180.v:3746$207_Y + attribute \src "ls180.v:3746.193-3746.230" + wire $not$ls180.v:3746$209_Y + attribute \src "ls180.v:3762.43-3762.73" + wire width 2 $not$ls180.v:3762$237_Y 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\src "ls180.v:3798.205-3798.245" + wire $not$ls180.v:3798$298_Y + attribute \src "ls180.v:3798.251-3798.290" + wire $not$ls180.v:3798$300_Y + attribute \src "ls180.v:3798.159-3798.292" + wire $not$ls180.v:3798$302_Y + attribute \src "ls180.v:3799.205-3799.245" + wire $not$ls180.v:3799$311_Y + attribute \src "ls180.v:3799.251-3799.290" + wire $not$ls180.v:3799$313_Y + attribute \src "ls180.v:3799.159-3799.292" + wire $not$ls180.v:3799$315_Y + attribute \src "ls180.v:3800.205-3800.245" + wire $not$ls180.v:3800$324_Y + attribute \src "ls180.v:3800.251-3800.290" + wire $not$ls180.v:3800$326_Y + attribute \src "ls180.v:3800.159-3800.292" + wire $not$ls180.v:3800$328_Y + attribute \src "ls180.v:3801.205-3801.245" + wire $not$ls180.v:3801$337_Y + attribute \src "ls180.v:3801.251-3801.290" + wire $not$ls180.v:3801$339_Y + attribute \src "ls180.v:3801.159-3801.292" + wire $not$ls180.v:3801$341_Y + attribute \src "ls180.v:3864.71-3864.103" + wire $not$ls180.v:3864$380_Y + attribute \src "ls180.v:3885.112-3885.150" + wire $not$ls180.v:3885$383_Y + attribute \src "ls180.v:3885.156-3885.193" + wire $not$ls180.v:3885$385_Y + attribute \src "ls180.v:3885.68-3885.195" + wire $not$ls180.v:3885$387_Y + attribute \src "ls180.v:3893.11-3893.38" + wire $not$ls180.v:3893$390_Y + attribute \src "ls180.v:3923.112-3923.150" + wire $not$ls180.v:3923$392_Y + attribute \src "ls180.v:3923.156-3923.193" + wire $not$ls180.v:3923$394_Y + attribute \src "ls180.v:3923.68-3923.195" + wire $not$ls180.v:3923$396_Y + attribute \src "ls180.v:3931.11-3931.37" + wire $not$ls180.v:3931$399_Y + attribute \src "ls180.v:3941.87-3941.331" + wire $not$ls180.v:3941$411_Y + attribute \src "ls180.v:3942.35-3942.68" + wire $not$ls180.v:3942$414_Y + attribute \src "ls180.v:3942.73-3942.105" + wire $not$ls180.v:3942$415_Y + attribute \src "ls180.v:3946.87-3946.331" + wire $not$ls180.v:3946$427_Y + attribute \src "ls180.v:3947.35-3947.68" + wire $not$ls180.v:3947$430_Y + attribute \src "ls180.v:3947.73-3947.105" + wire $not$ls180.v:3947$431_Y + attribute \src "ls180.v:3951.87-3951.331" + wire $not$ls180.v:3951$443_Y + attribute \src "ls180.v:3952.35-3952.68" + wire $not$ls180.v:3952$446_Y + attribute \src "ls180.v:3952.73-3952.105" + wire $not$ls180.v:3952$447_Y + attribute \src "ls180.v:3956.87-3956.331" + wire $not$ls180.v:3956$459_Y + attribute \src "ls180.v:3957.35-3957.68" + wire $not$ls180.v:3957$462_Y + attribute \src "ls180.v:3957.73-3957.105" + wire $not$ls180.v:3957$463_Y + attribute \src "ls180.v:3961.128-3961.372" + wire $not$ls180.v:3961$476_Y + attribute \src "ls180.v:3961.502-3961.746" + wire $not$ls180.v:3961$492_Y + attribute \src "ls180.v:3961.876-3961.1120" + wire $not$ls180.v:3961$508_Y + attribute \src "ls180.v:3961.1250-3961.1494" + wire $not$ls180.v:3961$524_Y + attribute \src "ls180.v:3983.32-3983.50" + wire $not$ls180.v:3983$530_Y + attribute \src "ls180.v:4022.30-4022.50" + wire $not$ls180.v:4022$535_Y + attribute \src "ls180.v:4023.30-4023.50" + wire $not$ls180.v:4023$536_Y + attribute \src "ls180.v:4048.27-4048.48" + wire $not$ls180.v:4048$542_Y + attribute \src "ls180.v:4049.30-4049.50" + wire $not$ls180.v:4049$543_Y + attribute \src "ls180.v:4050.80-4050.98" + wire $not$ls180.v:4050$545_Y + attribute \src "ls180.v:4051.107-4051.127" + wire $not$ls180.v:4051$549_Y + attribute \src "ls180.v:4052.78-4052.103" + wire $not$ls180.v:4052$552_Y + attribute \src "ls180.v:4053.91-4053.111" + wire $not$ls180.v:4053$555_Y + attribute \src "ls180.v:4069.35-4069.64" + wire $not$ls180.v:4069$564_Y + attribute \src "ls180.v:4070.36-4070.67" + wire $not$ls180.v:4070$565_Y + attribute \src "ls180.v:4076.32-4076.61" + wire $not$ls180.v:4076$566_Y + attribute \src "ls180.v:4082.36-4082.67" + wire $not$ls180.v:4082$567_Y + attribute \src "ls180.v:4083.35-4083.64" + wire $not$ls180.v:4083$568_Y + attribute \src "ls180.v:4086.32-4086.63" + wire $not$ls180.v:4086$571_Y + attribute \src "ls180.v:4124.81-4124.108" + wire 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\src "ls180.v:4823.200-4823.272" + wire $xor$ls180.v:4823$725_Y + attribute \src "ls180.v:4823.160-4823.273" + wire $xor$ls180.v:4823$726_Y + attribute \src "ls180.v:4824.353-4824.425" + wire $xor$ls180.v:4824$727_Y + attribute \src "ls180.v:4824.200-4824.272" + wire $xor$ls180.v:4824$728_Y + attribute \src "ls180.v:4824.160-4824.273" + wire $xor$ls180.v:4824$729_Y + attribute \src "ls180.v:4825.354-4825.426" + wire $xor$ls180.v:4825$730_Y + attribute \src "ls180.v:4825.201-4825.273" + wire $xor$ls180.v:4825$731_Y + attribute \src "ls180.v:4825.161-4825.274" + wire $xor$ls180.v:4825$732_Y + attribute \src "ls180.v:4826.361-4826.434" + wire $xor$ls180.v:4826$733_Y + attribute \src "ls180.v:4826.205-4826.278" + wire $xor$ls180.v:4826$734_Y + attribute \src "ls180.v:4826.164-4826.279" + wire $xor$ls180.v:4826$735_Y + attribute \src "ls180.v:4827.361-4827.434" + wire $xor$ls180.v:4827$736_Y + attribute \src "ls180.v:4827.205-4827.278" + wire $xor$ls180.v:4827$737_Y + attribute \src "ls180.v:4827.164-4827.279" + wire $xor$ls180.v:4827$738_Y + attribute \src "ls180.v:4828.361-4828.434" + wire $xor$ls180.v:4828$739_Y + attribute \src "ls180.v:4828.205-4828.278" + wire $xor$ls180.v:4828$740_Y + attribute \src "ls180.v:4828.164-4828.279" + wire $xor$ls180.v:4828$741_Y + attribute \src "ls180.v:4829.361-4829.434" + wire $xor$ls180.v:4829$742_Y + attribute \src "ls180.v:4829.205-4829.278" + wire $xor$ls180.v:4829$743_Y + attribute \src "ls180.v:4829.164-4829.279" + wire $xor$ls180.v:4829$744_Y + attribute \src "ls180.v:4830.361-4830.434" + wire $xor$ls180.v:4830$745_Y + attribute \src "ls180.v:4830.205-4830.278" + wire $xor$ls180.v:4830$746_Y + attribute \src "ls180.v:4830.164-4830.279" + wire $xor$ls180.v:4830$747_Y + attribute \src "ls180.v:4831.361-4831.434" + wire $xor$ls180.v:4831$748_Y + attribute \src "ls180.v:4831.205-4831.278" + wire $xor$ls180.v:4831$749_Y + attribute \src "ls180.v:4831.164-4831.279" + wire $xor$ls180.v:4831$750_Y + attribute \src "ls180.v:4832.361-4832.434" + wire $xor$ls180.v:4832$751_Y + attribute \src "ls180.v:4832.205-4832.278" + wire $xor$ls180.v:4832$752_Y + attribute \src "ls180.v:4832.164-4832.279" + wire $xor$ls180.v:4832$753_Y + attribute \src "ls180.v:4833.361-4833.434" + wire $xor$ls180.v:4833$754_Y + attribute \src "ls180.v:4833.205-4833.278" + wire $xor$ls180.v:4833$755_Y + attribute \src "ls180.v:4833.164-4833.279" + wire $xor$ls180.v:4833$756_Y + attribute \src "ls180.v:4834.361-4834.434" + wire $xor$ls180.v:4834$757_Y + attribute \src "ls180.v:4834.205-4834.278" + wire $xor$ls180.v:4834$758_Y + attribute \src "ls180.v:4834.164-4834.279" + wire $xor$ls180.v:4834$759_Y + attribute \src "ls180.v:4835.361-4835.434" + wire $xor$ls180.v:4835$760_Y + attribute \src "ls180.v:4835.205-4835.278" + wire $xor$ls180.v:4835$761_Y + attribute \src "ls180.v:4835.164-4835.279" + wire $xor$ls180.v:4835$762_Y + attribute \src "ls180.v:4836.361-4836.434" + wire $xor$ls180.v:4836$763_Y + attribute \src "ls180.v:4836.205-4836.278" + wire $xor$ls180.v:4836$764_Y + attribute \src "ls180.v:4836.164-4836.279" + wire $xor$ls180.v:4836$765_Y + attribute \src "ls180.v:4837.361-4837.434" + wire $xor$ls180.v:4837$766_Y + attribute \src "ls180.v:4837.205-4837.278" + wire $xor$ls180.v:4837$767_Y + attribute \src "ls180.v:4837.164-4837.279" + wire $xor$ls180.v:4837$768_Y + attribute \src "ls180.v:4838.361-4838.434" + wire $xor$ls180.v:4838$769_Y + attribute \src "ls180.v:4838.205-4838.278" + wire $xor$ls180.v:4838$770_Y + attribute \src "ls180.v:4838.164-4838.279" + wire $xor$ls180.v:4838$771_Y + attribute \src "ls180.v:4839.361-4839.434" + wire $xor$ls180.v:4839$772_Y + attribute \src "ls180.v:4839.205-4839.278" + wire $xor$ls180.v:4839$773_Y + attribute \src "ls180.v:4839.164-4839.279" + wire $xor$ls180.v:4839$774_Y + attribute \src "ls180.v:4840.361-4840.434" + wire $xor$ls180.v:4840$775_Y + attribute \src "ls180.v:4840.205-4840.278" + wire $xor$ls180.v:4840$776_Y + attribute \src "ls180.v:4840.164-4840.279" + wire $xor$ls180.v:4840$777_Y + attribute \src "ls180.v:4841.361-4841.434" + wire $xor$ls180.v:4841$778_Y + attribute \src "ls180.v:4841.205-4841.278" + wire $xor$ls180.v:4841$779_Y + attribute \src "ls180.v:4841.164-4841.279" + wire $xor$ls180.v:4841$780_Y + attribute \src "ls180.v:4842.361-4842.434" + wire $xor$ls180.v:4842$781_Y + attribute \src "ls180.v:4842.205-4842.278" + wire $xor$ls180.v:4842$782_Y + attribute \src "ls180.v:4842.164-4842.279" + wire $xor$ls180.v:4842$783_Y + attribute \src "ls180.v:4843.361-4843.434" + wire $xor$ls180.v:4843$784_Y + attribute \src "ls180.v:4843.205-4843.278" + wire $xor$ls180.v:4843$785_Y + attribute \src "ls180.v:4843.164-4843.279" + wire $xor$ls180.v:4843$786_Y + attribute \src "ls180.v:4844.361-4844.434" + wire $xor$ls180.v:4844$787_Y + attribute \src "ls180.v:4844.205-4844.278" + wire $xor$ls180.v:4844$788_Y + attribute \src "ls180.v:4844.164-4844.279" + wire $xor$ls180.v:4844$789_Y + attribute \src "ls180.v:4845.361-4845.434" + wire $xor$ls180.v:4845$790_Y + attribute \src "ls180.v:4845.205-4845.278" + wire $xor$ls180.v:4845$791_Y + attribute \src "ls180.v:4845.164-4845.279" + wire $xor$ls180.v:4845$792_Y + attribute \src "ls180.v:4846.360-4846.432" + wire $xor$ls180.v:4846$793_Y + attribute \src "ls180.v:4846.205-4846.277" + wire $xor$ls180.v:4846$794_Y + attribute \src "ls180.v:4846.164-4846.278" + wire $xor$ls180.v:4846$795_Y + attribute \src "ls180.v:4847.360-4847.432" + wire $xor$ls180.v:4847$796_Y + attribute \src "ls180.v:4847.205-4847.277" + wire $xor$ls180.v:4847$797_Y + attribute \src "ls180.v:4847.164-4847.278" + wire $xor$ls180.v:4847$798_Y + attribute \src "ls180.v:4848.360-4848.432" + wire $xor$ls180.v:4848$799_Y + attribute \src "ls180.v:4848.205-4848.277" + wire $xor$ls180.v:4848$800_Y + attribute \src "ls180.v:4848.164-4848.278" + wire $xor$ls180.v:4848$801_Y + attribute \src "ls180.v:4849.360-4849.432" + wire $xor$ls180.v:4849$802_Y + attribute \src "ls180.v:4849.205-4849.277" + wire $xor$ls180.v:4849$803_Y + attribute \src "ls180.v:4849.164-4849.278" + wire $xor$ls180.v:4849$804_Y + attribute \src "ls180.v:4850.360-4850.432" + wire $xor$ls180.v:4850$805_Y + attribute \src "ls180.v:4850.205-4850.277" + wire $xor$ls180.v:4850$806_Y + attribute \src "ls180.v:4850.164-4850.278" + wire $xor$ls180.v:4850$807_Y + attribute \src "ls180.v:4851.360-4851.432" + wire $xor$ls180.v:4851$808_Y + attribute \src "ls180.v:4851.205-4851.277" + wire $xor$ls180.v:4851$809_Y + attribute \src "ls180.v:4851.164-4851.278" + wire $xor$ls180.v:4851$810_Y + attribute \src "ls180.v:4852.360-4852.432" + wire $xor$ls180.v:4852$811_Y + attribute \src "ls180.v:4852.205-4852.277" + wire $xor$ls180.v:4852$812_Y + attribute \src "ls180.v:4852.164-4852.278" + wire $xor$ls180.v:4852$813_Y + attribute \src "ls180.v:4853.360-4853.432" + wire $xor$ls180.v:4853$814_Y + attribute \src "ls180.v:4853.205-4853.277" + wire $xor$ls180.v:4853$815_Y + attribute \src "ls180.v:4853.164-4853.278" + wire $xor$ls180.v:4853$816_Y + attribute \src "ls180.v:4854.360-4854.432" + wire $xor$ls180.v:4854$817_Y + attribute \src "ls180.v:4854.205-4854.277" + wire $xor$ls180.v:4854$818_Y + attribute \src "ls180.v:4854.164-4854.278" + wire $xor$ls180.v:4854$819_Y + attribute \src "ls180.v:4855.360-4855.432" + wire $xor$ls180.v:4855$820_Y + attribute \src "ls180.v:4855.205-4855.277" + wire $xor$ls180.v:4855$821_Y + attribute \src "ls180.v:4855.164-4855.278" + wire $xor$ls180.v:4855$822_Y + attribute \src "ls180.v:4876.899-4876.983" + wire $xor$ls180.v:4876$836_Y + attribute \src "ls180.v:4876.634-4876.718" + wire $xor$ls180.v:4876$837_Y + attribute \src "ls180.v:4876.588-4876.719" + wire $xor$ls180.v:4876$838_Y + attribute \src "ls180.v:4876.234-4876.318" + wire $xor$ls180.v:4876$839_Y + attribute \src "ls180.v:4876.187-4876.319" + wire $xor$ls180.v:4876$840_Y + attribute \src "ls180.v:4877.899-4877.983" + wire $xor$ls180.v:4877$841_Y + attribute \src "ls180.v:4877.634-4877.718" + wire $xor$ls180.v:4877$842_Y + attribute \src "ls180.v:4877.588-4877.719" + wire $xor$ls180.v:4877$843_Y + attribute \src "ls180.v:4877.234-4877.318" + wire $xor$ls180.v:4877$844_Y + attribute \src "ls180.v:4877.187-4877.319" + wire $xor$ls180.v:4877$845_Y + attribute \src "ls180.v:4886.899-4886.983" + wire $xor$ls180.v:4886$847_Y + attribute \src "ls180.v:4886.634-4886.718" + wire $xor$ls180.v:4886$848_Y + attribute \src "ls180.v:4886.588-4886.719" + wire $xor$ls180.v:4886$849_Y + attribute \src "ls180.v:4886.234-4886.318" + wire $xor$ls180.v:4886$850_Y + attribute \src "ls180.v:4886.187-4886.319" + wire $xor$ls180.v:4886$851_Y + attribute \src "ls180.v:4887.899-4887.983" + wire $xor$ls180.v:4887$852_Y + attribute \src "ls180.v:4887.634-4887.718" + wire $xor$ls180.v:4887$853_Y + attribute \src "ls180.v:4887.588-4887.719" + wire $xor$ls180.v:4887$854_Y + attribute \src "ls180.v:4887.234-4887.318" + wire $xor$ls180.v:4887$855_Y + attribute \src "ls180.v:4887.187-4887.319" + wire $xor$ls180.v:4887$856_Y + attribute \src "ls180.v:4896.899-4896.983" + wire $xor$ls180.v:4896$858_Y + attribute \src "ls180.v:4896.634-4896.718" + wire $xor$ls180.v:4896$859_Y + attribute \src "ls180.v:4896.588-4896.719" + wire $xor$ls180.v:4896$860_Y + attribute \src "ls180.v:4896.234-4896.318" + wire $xor$ls180.v:4896$861_Y + attribute \src "ls180.v:4896.187-4896.319" + wire $xor$ls180.v:4896$862_Y + attribute \src "ls180.v:4897.899-4897.983" + wire $xor$ls180.v:4897$863_Y + attribute \src "ls180.v:4897.634-4897.718" + wire $xor$ls180.v:4897$864_Y + attribute \src "ls180.v:4897.588-4897.719" + wire $xor$ls180.v:4897$865_Y + attribute \src "ls180.v:4897.234-4897.318" + wire $xor$ls180.v:4897$866_Y + attribute \src "ls180.v:4897.187-4897.319" + wire $xor$ls180.v:4897$867_Y + attribute \src "ls180.v:4906.899-4906.983" + wire $xor$ls180.v:4906$869_Y + attribute \src "ls180.v:4906.634-4906.718" + wire $xor$ls180.v:4906$870_Y + attribute \src "ls180.v:4906.588-4906.719" + wire $xor$ls180.v:4906$871_Y + attribute \src "ls180.v:4906.234-4906.318" + wire $xor$ls180.v:4906$872_Y + attribute \src "ls180.v:4906.187-4906.319" + wire $xor$ls180.v:4906$873_Y + attribute \src "ls180.v:4907.899-4907.983" + wire $xor$ls180.v:4907$874_Y + attribute \src "ls180.v:4907.634-4907.718" + wire $xor$ls180.v:4907$875_Y + attribute \src "ls180.v:4907.588-4907.719" + wire $xor$ls180.v:4907$876_Y + attribute \src "ls180.v:4907.234-4907.318" + wire $xor$ls180.v:4907$877_Y + attribute \src "ls180.v:4907.187-4907.319" + wire $xor$ls180.v:4907$878_Y + attribute \src "ls180.v:5058.879-5058.961" + wire $xor$ls180.v:5058$911_Y + attribute \src "ls180.v:5058.620-5058.702" + wire $xor$ls180.v:5058$912_Y + attribute \src "ls180.v:5058.575-5058.703" + wire $xor$ls180.v:5058$913_Y + attribute \src "ls180.v:5058.229-5058.311" + wire $xor$ls180.v:5058$914_Y + attribute \src "ls180.v:5058.183-5058.312" + wire $xor$ls180.v:5058$915_Y + attribute \src "ls180.v:5059.879-5059.961" + wire $xor$ls180.v:5059$916_Y + attribute \src "ls180.v:5059.620-5059.702" + wire $xor$ls180.v:5059$917_Y + attribute \src "ls180.v:5059.575-5059.703" + wire $xor$ls180.v:5059$918_Y + attribute \src "ls180.v:5059.229-5059.311" + wire $xor$ls180.v:5059$919_Y + attribute \src "ls180.v:5059.183-5059.312" + wire $xor$ls180.v:5059$920_Y + attribute \src "ls180.v:5068.879-5068.961" + wire $xor$ls180.v:5068$922_Y + attribute \src "ls180.v:5068.620-5068.702" + wire $xor$ls180.v:5068$923_Y + attribute \src "ls180.v:5068.575-5068.703" + wire $xor$ls180.v:5068$924_Y + attribute \src "ls180.v:5068.229-5068.311" + wire $xor$ls180.v:5068$925_Y + attribute \src "ls180.v:5068.183-5068.312" + wire $xor$ls180.v:5068$926_Y + attribute \src "ls180.v:5069.879-5069.961" + wire $xor$ls180.v:5069$927_Y + attribute \src "ls180.v:5069.620-5069.702" + wire $xor$ls180.v:5069$928_Y + attribute \src "ls180.v:5069.575-5069.703" + wire $xor$ls180.v:5069$929_Y + attribute \src "ls180.v:5069.229-5069.311" + wire $xor$ls180.v:5069$930_Y + attribute \src "ls180.v:5069.183-5069.312" + wire $xor$ls180.v:5069$931_Y + attribute \src "ls180.v:5078.879-5078.961" + wire $xor$ls180.v:5078$933_Y + attribute \src "ls180.v:5078.620-5078.702" + wire $xor$ls180.v:5078$934_Y + attribute \src "ls180.v:5078.575-5078.703" + wire $xor$ls180.v:5078$935_Y + attribute \src "ls180.v:5078.229-5078.311" + wire $xor$ls180.v:5078$936_Y + attribute \src "ls180.v:5078.183-5078.312" + wire $xor$ls180.v:5078$937_Y + attribute \src "ls180.v:5079.879-5079.961" + wire $xor$ls180.v:5079$938_Y + attribute \src "ls180.v:5079.620-5079.702" + wire $xor$ls180.v:5079$939_Y + attribute \src "ls180.v:5079.575-5079.703" + wire $xor$ls180.v:5079$940_Y + attribute \src "ls180.v:5079.229-5079.311" + wire $xor$ls180.v:5079$941_Y + attribute \src "ls180.v:5079.183-5079.312" + wire $xor$ls180.v:5079$942_Y + attribute \src "ls180.v:5088.879-5088.961" + wire $xor$ls180.v:5088$944_Y + attribute \src "ls180.v:5088.620-5088.702" + wire $xor$ls180.v:5088$945_Y + attribute \src "ls180.v:5088.575-5088.703" + wire $xor$ls180.v:5088$946_Y + attribute \src "ls180.v:5088.229-5088.311" + wire $xor$ls180.v:5088$947_Y + attribute \src "ls180.v:5088.183-5088.312" + wire $xor$ls180.v:5088$948_Y + attribute \src "ls180.v:5089.879-5089.961" + wire $xor$ls180.v:5089$949_Y + attribute \src "ls180.v:5089.620-5089.702" + wire $xor$ls180.v:5089$950_Y + attribute \src "ls180.v:5089.575-5089.703" + wire $xor$ls180.v:5089$951_Y + attribute \src "ls180.v:5089.229-5089.311" + wire $xor$ls180.v:5089$952_Y + attribute \src "ls180.v:5089.183-5089.312" + wire $xor$ls180.v:5089$953_Y + attribute \src "ls180.v:1710.11-1710.42" + wire width 3 \builder_bankmachine0_next_state + attribute \src "ls180.v:1709.11-1709.37" + wire width 3 \builder_bankmachine0_state + attribute \src "ls180.v:1712.11-1712.42" + wire width 3 \builder_bankmachine1_next_state + attribute \src "ls180.v:1711.11-1711.37" + wire width 3 \builder_bankmachine1_state + attribute \src "ls180.v:1714.11-1714.42" + wire width 3 \builder_bankmachine2_next_state + attribute \src "ls180.v:1713.11-1713.37" + wire width 3 \builder_bankmachine2_state + attribute \src "ls180.v:1716.11-1716.42" + wire width 3 \builder_bankmachine3_next_state + attribute \src "ls180.v:1715.11-1715.37" + wire width 3 \builder_bankmachine3_state + attribute \src "ls180.v:2548.5-2548.34" + wire \builder_comb_rhs_array_muxed0 + attribute \src "ls180.v:2549.12-2549.41" + wire width 13 \builder_comb_rhs_array_muxed1 + attribute \src "ls180.v:2561.5-2561.35" + wire \builder_comb_rhs_array_muxed10 + attribute \src "ls180.v:2562.5-2562.35" + wire \builder_comb_rhs_array_muxed11 + attribute \src "ls180.v:2566.12-2566.42" + wire width 22 \builder_comb_rhs_array_muxed12 + attribute \src "ls180.v:2567.5-2567.35" + wire \builder_comb_rhs_array_muxed13 + attribute \src "ls180.v:2568.5-2568.35" + wire \builder_comb_rhs_array_muxed14 + attribute \src "ls180.v:2569.12-2569.42" + wire width 22 \builder_comb_rhs_array_muxed15 + attribute \src "ls180.v:2570.5-2570.35" + wire \builder_comb_rhs_array_muxed16 + attribute \src "ls180.v:2571.5-2571.35" + wire \builder_comb_rhs_array_muxed17 + attribute \src "ls180.v:2572.12-2572.42" + wire width 22 \builder_comb_rhs_array_muxed18 + attribute \src "ls180.v:2573.5-2573.35" + wire \builder_comb_rhs_array_muxed19 + attribute \src "ls180.v:2550.11-2550.40" + wire width 2 \builder_comb_rhs_array_muxed2 + attribute \src "ls180.v:2574.5-2574.35" + wire \builder_comb_rhs_array_muxed20 + attribute \src "ls180.v:2575.12-2575.42" + wire width 22 \builder_comb_rhs_array_muxed21 + attribute \src "ls180.v:2576.5-2576.35" + wire \builder_comb_rhs_array_muxed22 + attribute \src "ls180.v:2577.5-2577.35" + wire \builder_comb_rhs_array_muxed23 + attribute \src "ls180.v:2578.12-2578.42" + wire width 32 \builder_comb_rhs_array_muxed24 + attribute \src "ls180.v:2579.12-2579.42" + wire width 32 \builder_comb_rhs_array_muxed25 + attribute \src "ls180.v:2580.11-2580.41" + wire width 4 \builder_comb_rhs_array_muxed26 + attribute \src "ls180.v:2581.5-2581.35" + wire \builder_comb_rhs_array_muxed27 + attribute \src "ls180.v:2582.5-2582.35" + wire \builder_comb_rhs_array_muxed28 + attribute \src "ls180.v:2583.5-2583.35" + wire \builder_comb_rhs_array_muxed29 + attribute \src "ls180.v:2551.5-2551.34" + wire \builder_comb_rhs_array_muxed3 + attribute \src "ls180.v:2584.11-2584.41" + wire width 3 \builder_comb_rhs_array_muxed30 + attribute \src "ls180.v:2585.11-2585.41" + wire width 2 \builder_comb_rhs_array_muxed31 + attribute \src "ls180.v:2552.5-2552.34" + wire \builder_comb_rhs_array_muxed4 + attribute \src "ls180.v:2553.5-2553.34" + wire \builder_comb_rhs_array_muxed5 + attribute \src "ls180.v:2557.5-2557.34" + wire \builder_comb_rhs_array_muxed6 + attribute \src "ls180.v:2558.12-2558.41" + wire width 13 \builder_comb_rhs_array_muxed7 + attribute \src "ls180.v:2559.11-2559.40" + wire width 2 \builder_comb_rhs_array_muxed8 + attribute \src "ls180.v:2560.5-2560.34" + wire \builder_comb_rhs_array_muxed9 + attribute \src "ls180.v:2554.5-2554.32" + wire \builder_comb_t_array_muxed0 + attribute \src "ls180.v:2555.5-2555.32" + wire \builder_comb_t_array_muxed1 + attribute \src "ls180.v:2556.5-2556.32" + wire \builder_comb_t_array_muxed2 + attribute \src "ls180.v:2563.5-2563.32" + wire \builder_comb_t_array_muxed3 + attribute \src "ls180.v:2564.5-2564.32" + wire \builder_comb_t_array_muxed4 + attribute \src "ls180.v:2565.5-2565.32" + wire \builder_comb_t_array_muxed5 + attribute \src "ls180.v:1696.5-1696.34" + wire \builder_converter0_next_state + attribute \src "ls180.v:1695.5-1695.29" + wire \builder_converter0_state + attribute \src "ls180.v:1700.5-1700.34" + wire \builder_converter1_next_state + attribute \src "ls180.v:1699.5-1699.29" + wire \builder_converter1_state + attribute \src "ls180.v:1704.5-1704.34" + wire \builder_converter2_next_state + attribute \src "ls180.v:1703.5-1703.29" + wire \builder_converter2_state + attribute \src "ls180.v:1741.5-1741.33" + wire \builder_converter_next_state + attribute \src "ls180.v:1740.5-1740.28" + wire \builder_converter_state + attribute \src "ls180.v:1861.12-1861.25" + wire width 20 \builder_count + attribute \src "ls180.v:2536.13-2536.41" + wire width 14 \builder_csr_interconnect_adr + attribute \src "ls180.v:2539.12-2539.42" + wire width 8 \builder_csr_interconnect_dat_r + attribute \src "ls180.v:2538.12-2538.42" + wire width 8 \builder_csr_interconnect_dat_w + attribute \src "ls180.v:2537.6-2537.33" + wire \builder_csr_interconnect_we + attribute \src "ls180.v:1899.12-1899.42" + wire width 8 \builder_csrbank0_bus_errors0_r + attribute \src "ls180.v:1898.6-1898.37" + wire \builder_csrbank0_bus_errors0_re + attribute \src "ls180.v:1901.12-1901.42" + wire width 8 \builder_csrbank0_bus_errors0_w + attribute \src "ls180.v:1900.6-1900.37" + wire \builder_csrbank0_bus_errors0_we + attribute \src "ls180.v:1895.12-1895.42" + wire width 8 \builder_csrbank0_bus_errors1_r + attribute \src "ls180.v:1894.6-1894.37" + wire \builder_csrbank0_bus_errors1_re + attribute \src "ls180.v:1897.12-1897.42" + wire width 8 \builder_csrbank0_bus_errors1_w + attribute \src "ls180.v:1896.6-1896.37" + wire \builder_csrbank0_bus_errors1_we + attribute \src "ls180.v:1891.12-1891.42" + wire width 8 \builder_csrbank0_bus_errors2_r + attribute \src "ls180.v:1890.6-1890.37" + wire \builder_csrbank0_bus_errors2_re + attribute \src "ls180.v:1893.12-1893.42" + wire width 8 \builder_csrbank0_bus_errors2_w + attribute \src "ls180.v:1892.6-1892.37" + wire \builder_csrbank0_bus_errors2_we + attribute \src "ls180.v:1887.12-1887.42" + wire width 8 \builder_csrbank0_bus_errors3_r + attribute \src "ls180.v:1886.6-1886.37" + wire \builder_csrbank0_bus_errors3_re + attribute \src "ls180.v:1889.12-1889.42" + wire width 8 \builder_csrbank0_bus_errors3_w + attribute \src "ls180.v:1888.6-1888.37" + wire \builder_csrbank0_bus_errors3_we + attribute \src "ls180.v:1867.6-1867.31" + wire \builder_csrbank0_reset0_r + attribute \src "ls180.v:1866.6-1866.32" + wire \builder_csrbank0_reset0_re + attribute \src "ls180.v:1869.6-1869.31" + wire \builder_csrbank0_reset0_w + attribute \src "ls180.v:1868.6-1868.32" + wire \builder_csrbank0_reset0_we + attribute \src "ls180.v:1883.12-1883.39" + wire width 8 \builder_csrbank0_scratch0_r + attribute \src "ls180.v:1882.6-1882.34" + wire \builder_csrbank0_scratch0_re + attribute \src "ls180.v:1885.12-1885.39" + wire width 8 \builder_csrbank0_scratch0_w + attribute \src "ls180.v:1884.6-1884.34" + wire \builder_csrbank0_scratch0_we + attribute \src "ls180.v:1879.12-1879.39" + wire width 8 \builder_csrbank0_scratch1_r + attribute \src "ls180.v:1878.6-1878.34" + wire \builder_csrbank0_scratch1_re + attribute \src "ls180.v:1881.12-1881.39" + wire width 8 \builder_csrbank0_scratch1_w + attribute \src "ls180.v:1880.6-1880.34" + wire \builder_csrbank0_scratch1_we + attribute \src "ls180.v:1875.12-1875.39" + wire width 8 \builder_csrbank0_scratch2_r + attribute \src "ls180.v:1874.6-1874.34" + wire \builder_csrbank0_scratch2_re + attribute \src "ls180.v:1877.12-1877.39" + wire width 8 \builder_csrbank0_scratch2_w + attribute \src "ls180.v:1876.6-1876.34" + wire \builder_csrbank0_scratch2_we + attribute \src "ls180.v:1871.12-1871.39" + wire width 8 \builder_csrbank0_scratch3_r + attribute \src "ls180.v:1870.6-1870.34" + wire \builder_csrbank0_scratch3_re + attribute \src "ls180.v:1873.12-1873.39" + wire width 8 \builder_csrbank0_scratch3_w + attribute \src "ls180.v:1872.6-1872.34" + wire \builder_csrbank0_scratch3_we + attribute \src "ls180.v:1902.6-1902.26" + wire \builder_csrbank0_sel + attribute \src "ls180.v:2421.12-2421.44" + wire width 8 \builder_csrbank10_clk_divider0_r + attribute \src "ls180.v:2420.6-2420.39" + wire \builder_csrbank10_clk_divider0_re + attribute \src "ls180.v:2423.12-2423.44" + wire width 8 \builder_csrbank10_clk_divider0_w + attribute \src "ls180.v:2422.6-2422.39" + wire \builder_csrbank10_clk_divider0_we + attribute \src "ls180.v:2417.12-2417.44" + wire width 8 \builder_csrbank10_clk_divider1_r + attribute \src "ls180.v:2416.6-2416.39" + wire \builder_csrbank10_clk_divider1_re + attribute \src "ls180.v:2419.12-2419.44" + wire width 8 \builder_csrbank10_clk_divider1_w + attribute \src "ls180.v:2418.6-2418.39" + wire \builder_csrbank10_clk_divider1_we + attribute \src "ls180.v:2393.12-2393.40" + wire width 8 \builder_csrbank10_control0_r + attribute \src "ls180.v:2392.6-2392.35" + wire \builder_csrbank10_control0_re + attribute \src "ls180.v:2395.12-2395.40" + wire width 8 \builder_csrbank10_control0_w + attribute \src "ls180.v:2394.6-2394.35" + wire \builder_csrbank10_control0_we + attribute \src "ls180.v:2389.12-2389.40" + wire width 8 \builder_csrbank10_control1_r + attribute \src "ls180.v:2388.6-2388.35" + wire \builder_csrbank10_control1_re + attribute \src "ls180.v:2391.12-2391.40" + wire width 8 \builder_csrbank10_control1_w + attribute \src "ls180.v:2390.6-2390.35" + wire \builder_csrbank10_control1_we + attribute \src "ls180.v:2409.6-2409.29" + wire \builder_csrbank10_cs0_r + attribute \src "ls180.v:2408.6-2408.30" + wire \builder_csrbank10_cs0_re + attribute \src "ls180.v:2411.6-2411.29" + wire \builder_csrbank10_cs0_w + attribute \src "ls180.v:2410.6-2410.30" + wire \builder_csrbank10_cs0_we + attribute \src "ls180.v:2413.6-2413.35" + wire \builder_csrbank10_loopback0_r + attribute \src "ls180.v:2412.6-2412.36" + wire \builder_csrbank10_loopback0_re + attribute \src "ls180.v:2415.6-2415.35" + wire \builder_csrbank10_loopback0_w + attribute \src "ls180.v:2414.6-2414.36" + wire \builder_csrbank10_loopback0_we + attribute \src "ls180.v:2405.12-2405.36" + wire width 8 \builder_csrbank10_miso_r + attribute \src "ls180.v:2404.6-2404.31" + wire \builder_csrbank10_miso_re + attribute \src "ls180.v:2407.12-2407.36" + wire width 8 \builder_csrbank10_miso_w + attribute \src "ls180.v:2406.6-2406.31" + wire \builder_csrbank10_miso_we + attribute \src "ls180.v:2401.12-2401.37" + wire width 8 \builder_csrbank10_mosi0_r + attribute \src "ls180.v:2400.6-2400.32" + wire \builder_csrbank10_mosi0_re + attribute \src "ls180.v:2403.12-2403.37" + wire width 8 \builder_csrbank10_mosi0_w + attribute \src "ls180.v:2402.6-2402.32" + wire \builder_csrbank10_mosi0_we + attribute \src "ls180.v:2424.6-2424.27" + wire \builder_csrbank10_sel + attribute \src "ls180.v:2397.6-2397.32" + wire \builder_csrbank10_status_r + attribute \src "ls180.v:2396.6-2396.33" + wire \builder_csrbank10_status_re + attribute \src "ls180.v:2399.6-2399.32" + wire \builder_csrbank10_status_w + attribute \src "ls180.v:2398.6-2398.33" + wire \builder_csrbank10_status_we + attribute \src "ls180.v:2462.6-2462.29" + wire \builder_csrbank11_en0_r + attribute \src "ls180.v:2461.6-2461.30" + wire \builder_csrbank11_en0_re + attribute \src "ls180.v:2464.6-2464.29" + wire \builder_csrbank11_en0_w + attribute \src "ls180.v:2463.6-2463.30" + wire \builder_csrbank11_en0_we + attribute \src "ls180.v:2486.6-2486.36" + wire \builder_csrbank11_ev_enable0_r + attribute \src "ls180.v:2485.6-2485.37" + wire \builder_csrbank11_ev_enable0_re + attribute \src "ls180.v:2488.6-2488.36" + wire \builder_csrbank11_ev_enable0_w + attribute \src "ls180.v:2487.6-2487.37" + wire \builder_csrbank11_ev_enable0_we + attribute \src "ls180.v:2442.12-2442.37" + wire width 8 \builder_csrbank11_load0_r + attribute \src "ls180.v:2441.6-2441.32" + wire \builder_csrbank11_load0_re + attribute \src "ls180.v:2444.12-2444.37" + wire width 8 \builder_csrbank11_load0_w + attribute \src "ls180.v:2443.6-2443.32" + wire \builder_csrbank11_load0_we + attribute \src "ls180.v:2438.12-2438.37" + wire width 8 \builder_csrbank11_load1_r + attribute \src "ls180.v:2437.6-2437.32" + wire \builder_csrbank11_load1_re + attribute \src "ls180.v:2440.12-2440.37" + wire width 8 \builder_csrbank11_load1_w + attribute \src "ls180.v:2439.6-2439.32" + wire \builder_csrbank11_load1_we + attribute \src "ls180.v:2434.12-2434.37" + wire width 8 \builder_csrbank11_load2_r + attribute \src "ls180.v:2433.6-2433.32" + wire \builder_csrbank11_load2_re + attribute \src "ls180.v:2436.12-2436.37" + wire width 8 \builder_csrbank11_load2_w + attribute \src "ls180.v:2435.6-2435.32" + wire \builder_csrbank11_load2_we + attribute \src "ls180.v:2430.12-2430.37" + wire width 8 \builder_csrbank11_load3_r + attribute \src "ls180.v:2429.6-2429.32" + wire \builder_csrbank11_load3_re + attribute \src "ls180.v:2432.12-2432.37" + wire width 8 \builder_csrbank11_load3_w + attribute \src "ls180.v:2431.6-2431.32" + wire \builder_csrbank11_load3_we + attribute \src "ls180.v:2458.12-2458.39" + wire width 8 \builder_csrbank11_reload0_r + attribute \src "ls180.v:2457.6-2457.34" + wire \builder_csrbank11_reload0_re + attribute \src "ls180.v:2460.12-2460.39" + wire width 8 \builder_csrbank11_reload0_w + attribute \src "ls180.v:2459.6-2459.34" + wire \builder_csrbank11_reload0_we + attribute \src "ls180.v:2454.12-2454.39" + wire width 8 \builder_csrbank11_reload1_r + attribute \src "ls180.v:2453.6-2453.34" + wire \builder_csrbank11_reload1_re + attribute \src "ls180.v:2456.12-2456.39" + wire width 8 \builder_csrbank11_reload1_w + attribute \src "ls180.v:2455.6-2455.34" + wire \builder_csrbank11_reload1_we + attribute \src "ls180.v:2450.12-2450.39" + wire width 8 \builder_csrbank11_reload2_r + attribute \src "ls180.v:2449.6-2449.34" + wire \builder_csrbank11_reload2_re + attribute \src "ls180.v:2452.12-2452.39" + wire width 8 \builder_csrbank11_reload2_w + attribute \src "ls180.v:2451.6-2451.34" + wire \builder_csrbank11_reload2_we + attribute \src "ls180.v:2446.12-2446.39" + wire width 8 \builder_csrbank11_reload3_r + attribute \src "ls180.v:2445.6-2445.34" + wire \builder_csrbank11_reload3_re + attribute \src "ls180.v:2448.12-2448.39" + wire width 8 \builder_csrbank11_reload3_w + attribute \src "ls180.v:2447.6-2447.34" + wire \builder_csrbank11_reload3_we + attribute \src "ls180.v:2489.6-2489.27" + wire \builder_csrbank11_sel + attribute \src "ls180.v:2466.6-2466.39" + wire \builder_csrbank11_update_value0_r + attribute \src "ls180.v:2465.6-2465.40" + wire \builder_csrbank11_update_value0_re + attribute \src "ls180.v:2468.6-2468.39" + wire \builder_csrbank11_update_value0_w + attribute \src "ls180.v:2467.6-2467.40" + wire \builder_csrbank11_update_value0_we + attribute \src "ls180.v:2482.12-2482.38" + wire width 8 \builder_csrbank11_value0_r + attribute \src "ls180.v:2481.6-2481.33" + wire \builder_csrbank11_value0_re + attribute \src "ls180.v:2484.12-2484.38" + wire width 8 \builder_csrbank11_value0_w + attribute \src "ls180.v:2483.6-2483.33" + wire \builder_csrbank11_value0_we + attribute \src "ls180.v:2478.12-2478.38" + wire width 8 \builder_csrbank11_value1_r + attribute \src "ls180.v:2477.6-2477.33" + wire \builder_csrbank11_value1_re + attribute \src "ls180.v:2480.12-2480.38" + wire width 8 \builder_csrbank11_value1_w + attribute \src "ls180.v:2479.6-2479.33" + wire \builder_csrbank11_value1_we + attribute \src "ls180.v:2474.12-2474.38" + wire width 8 \builder_csrbank11_value2_r + attribute \src "ls180.v:2473.6-2473.33" + wire \builder_csrbank11_value2_re + attribute \src "ls180.v:2476.12-2476.38" + wire width 8 \builder_csrbank11_value2_w + attribute \src "ls180.v:2475.6-2475.33" + wire \builder_csrbank11_value2_we + attribute \src "ls180.v:2470.12-2470.38" + wire width 8 \builder_csrbank11_value3_r + attribute \src "ls180.v:2469.6-2469.33" + wire \builder_csrbank11_value3_re + attribute \src "ls180.v:2472.12-2472.38" + wire width 8 \builder_csrbank11_value3_w + attribute \src "ls180.v:2471.6-2471.33" + wire \builder_csrbank11_value3_we + attribute \src "ls180.v:2503.12-2503.42" + wire width 2 \builder_csrbank12_ev_enable0_r + attribute \src "ls180.v:2502.6-2502.37" + wire \builder_csrbank12_ev_enable0_re + attribute \src "ls180.v:2505.12-2505.42" + wire width 2 \builder_csrbank12_ev_enable0_w + attribute \src "ls180.v:2504.6-2504.37" + wire \builder_csrbank12_ev_enable0_we + attribute \src "ls180.v:2499.6-2499.33" + wire \builder_csrbank12_rxempty_r + attribute \src "ls180.v:2498.6-2498.34" + wire \builder_csrbank12_rxempty_re + attribute \src "ls180.v:2501.6-2501.33" + wire \builder_csrbank12_rxempty_w + attribute \src "ls180.v:2500.6-2500.34" + wire \builder_csrbank12_rxempty_we + attribute \src "ls180.v:2511.6-2511.32" + wire \builder_csrbank12_rxfull_r + attribute \src "ls180.v:2510.6-2510.33" + wire \builder_csrbank12_rxfull_re + attribute \src "ls180.v:2513.6-2513.32" + wire \builder_csrbank12_rxfull_w + attribute \src "ls180.v:2512.6-2512.33" + wire \builder_csrbank12_rxfull_we + attribute \src "ls180.v:2514.6-2514.27" + wire \builder_csrbank12_sel + attribute \src "ls180.v:2507.6-2507.33" + wire \builder_csrbank12_txempty_r + attribute \src "ls180.v:2506.6-2506.34" + wire \builder_csrbank12_txempty_re + attribute \src "ls180.v:2509.6-2509.33" + wire \builder_csrbank12_txempty_w + attribute \src "ls180.v:2508.6-2508.34" + wire \builder_csrbank12_txempty_we + attribute \src "ls180.v:2495.6-2495.32" + wire \builder_csrbank12_txfull_r + attribute \src "ls180.v:2494.6-2494.33" + wire \builder_csrbank12_txfull_re + attribute \src "ls180.v:2497.6-2497.32" + wire \builder_csrbank12_txfull_w + attribute \src "ls180.v:2496.6-2496.33" + wire \builder_csrbank12_txfull_we + attribute \src "ls180.v:2535.6-2535.27" + wire \builder_csrbank13_sel + attribute \src "ls180.v:2532.12-2532.44" + wire width 8 \builder_csrbank13_tuning_word0_r + attribute \src "ls180.v:2531.6-2531.39" + wire \builder_csrbank13_tuning_word0_re + attribute \src "ls180.v:2534.12-2534.44" + wire width 8 \builder_csrbank13_tuning_word0_w + attribute \src "ls180.v:2533.6-2533.39" + wire \builder_csrbank13_tuning_word0_we + attribute \src "ls180.v:2528.12-2528.44" + wire width 8 \builder_csrbank13_tuning_word1_r + attribute \src "ls180.v:2527.6-2527.39" + wire \builder_csrbank13_tuning_word1_re + attribute \src "ls180.v:2530.12-2530.44" + wire width 8 \builder_csrbank13_tuning_word1_w + attribute \src "ls180.v:2529.6-2529.39" + wire \builder_csrbank13_tuning_word1_we + attribute \src "ls180.v:2524.12-2524.44" + wire width 8 \builder_csrbank13_tuning_word2_r + attribute \src "ls180.v:2523.6-2523.39" + wire \builder_csrbank13_tuning_word2_re + attribute \src "ls180.v:2526.12-2526.44" + wire width 8 \builder_csrbank13_tuning_word2_w + attribute \src "ls180.v:2525.6-2525.39" + wire \builder_csrbank13_tuning_word2_we + attribute \src "ls180.v:2520.12-2520.44" + wire width 8 \builder_csrbank13_tuning_word3_r + attribute \src "ls180.v:2519.6-2519.39" + wire \builder_csrbank13_tuning_word3_re + attribute \src "ls180.v:2522.12-2522.44" + wire width 8 \builder_csrbank13_tuning_word3_w + attribute \src "ls180.v:2521.6-2521.39" + wire \builder_csrbank13_tuning_word3_we + attribute \src "ls180.v:1920.12-1920.34" + wire width 8 \builder_csrbank1_in0_r + attribute \src "ls180.v:1919.6-1919.29" + wire \builder_csrbank1_in0_re + attribute \src "ls180.v:1922.12-1922.34" + wire width 8 \builder_csrbank1_in0_w + attribute \src "ls180.v:1921.6-1921.29" + wire \builder_csrbank1_in0_we + attribute \src "ls180.v:1916.12-1916.34" + wire width 8 \builder_csrbank1_in1_r + attribute \src "ls180.v:1915.6-1915.29" + wire \builder_csrbank1_in1_re + attribute \src "ls180.v:1918.12-1918.34" + wire width 8 \builder_csrbank1_in1_w + attribute \src "ls180.v:1917.6-1917.29" + wire \builder_csrbank1_in1_we + attribute \src "ls180.v:1912.12-1912.34" + wire width 8 \builder_csrbank1_oe0_r + attribute \src "ls180.v:1911.6-1911.29" + wire \builder_csrbank1_oe0_re + attribute \src "ls180.v:1914.12-1914.34" + wire width 8 \builder_csrbank1_oe0_w + attribute \src "ls180.v:1913.6-1913.29" + wire \builder_csrbank1_oe0_we + attribute \src "ls180.v:1908.12-1908.34" + wire width 8 \builder_csrbank1_oe1_r + attribute \src "ls180.v:1907.6-1907.29" + wire \builder_csrbank1_oe1_re + attribute \src "ls180.v:1910.12-1910.34" + wire width 8 \builder_csrbank1_oe1_w + attribute \src "ls180.v:1909.6-1909.29" + wire \builder_csrbank1_oe1_we + attribute \src "ls180.v:1928.12-1928.35" + wire width 8 \builder_csrbank1_out0_r + attribute \src "ls180.v:1927.6-1927.30" + wire \builder_csrbank1_out0_re + attribute \src "ls180.v:1930.12-1930.35" + wire width 8 \builder_csrbank1_out0_w + attribute \src "ls180.v:1929.6-1929.30" + wire \builder_csrbank1_out0_we + attribute \src "ls180.v:1924.12-1924.35" + wire width 8 \builder_csrbank1_out1_r + attribute \src "ls180.v:1923.6-1923.30" + wire \builder_csrbank1_out1_re + attribute \src "ls180.v:1926.12-1926.35" + wire width 8 \builder_csrbank1_out1_w + attribute \src "ls180.v:1925.6-1925.30" + wire \builder_csrbank1_out1_we + attribute \src "ls180.v:1931.6-1931.26" + wire \builder_csrbank1_sel + attribute \src "ls180.v:1937.6-1937.32" + wire \builder_csrbank2_enable0_r + attribute \src "ls180.v:1936.6-1936.33" + wire \builder_csrbank2_enable0_re + attribute \src "ls180.v:1939.6-1939.32" + wire \builder_csrbank2_enable0_w + attribute \src "ls180.v:1938.6-1938.33" + wire \builder_csrbank2_enable0_we + attribute \src "ls180.v:1969.12-1969.38" + wire width 8 \builder_csrbank2_period0_r + attribute \src "ls180.v:1968.6-1968.33" + wire \builder_csrbank2_period0_re + attribute \src "ls180.v:1971.12-1971.38" + wire width 8 \builder_csrbank2_period0_w + attribute \src "ls180.v:1970.6-1970.33" + wire \builder_csrbank2_period0_we + attribute \src "ls180.v:1965.12-1965.38" + wire width 8 \builder_csrbank2_period1_r + attribute \src "ls180.v:1964.6-1964.33" + wire \builder_csrbank2_period1_re + attribute \src "ls180.v:1967.12-1967.38" + wire width 8 \builder_csrbank2_period1_w + attribute \src "ls180.v:1966.6-1966.33" + wire \builder_csrbank2_period1_we + attribute \src "ls180.v:1961.12-1961.38" + wire width 8 \builder_csrbank2_period2_r + attribute \src "ls180.v:1960.6-1960.33" + wire \builder_csrbank2_period2_re + attribute \src "ls180.v:1963.12-1963.38" + wire width 8 \builder_csrbank2_period2_w + attribute \src "ls180.v:1962.6-1962.33" + wire \builder_csrbank2_period2_we + attribute \src "ls180.v:1957.12-1957.38" + wire width 8 \builder_csrbank2_period3_r + attribute \src "ls180.v:1956.6-1956.33" + wire \builder_csrbank2_period3_re + attribute \src "ls180.v:1959.12-1959.38" + wire width 8 \builder_csrbank2_period3_w + attribute \src "ls180.v:1958.6-1958.33" + wire \builder_csrbank2_period3_we + attribute \src "ls180.v:1972.6-1972.26" + wire \builder_csrbank2_sel + attribute \src "ls180.v:1953.12-1953.37" + wire width 8 \builder_csrbank2_width0_r + attribute \src "ls180.v:1952.6-1952.32" + wire \builder_csrbank2_width0_re + attribute \src "ls180.v:1955.12-1955.37" + wire width 8 \builder_csrbank2_width0_w + attribute \src "ls180.v:1954.6-1954.32" + wire \builder_csrbank2_width0_we + attribute \src "ls180.v:1949.12-1949.37" + wire width 8 \builder_csrbank2_width1_r + attribute \src "ls180.v:1948.6-1948.32" + wire \builder_csrbank2_width1_re + attribute \src "ls180.v:1951.12-1951.37" + wire width 8 \builder_csrbank2_width1_w + attribute \src "ls180.v:1950.6-1950.32" + wire \builder_csrbank2_width1_we + attribute \src "ls180.v:1945.12-1945.37" + wire width 8 \builder_csrbank2_width2_r + attribute \src "ls180.v:1944.6-1944.32" + wire \builder_csrbank2_width2_re + attribute \src "ls180.v:1947.12-1947.37" + wire width 8 \builder_csrbank2_width2_w + attribute \src "ls180.v:1946.6-1946.32" + wire \builder_csrbank2_width2_we + attribute \src "ls180.v:1941.12-1941.37" + wire width 8 \builder_csrbank2_width3_r + attribute \src "ls180.v:1940.6-1940.32" + wire \builder_csrbank2_width3_re + attribute \src "ls180.v:1943.12-1943.37" + wire width 8 \builder_csrbank2_width3_w + attribute \src "ls180.v:1942.6-1942.32" + wire \builder_csrbank2_width3_we + attribute \src "ls180.v:1978.6-1978.32" + wire \builder_csrbank3_enable0_r + attribute \src "ls180.v:1977.6-1977.33" + wire \builder_csrbank3_enable0_re + attribute \src "ls180.v:1980.6-1980.32" + wire \builder_csrbank3_enable0_w + attribute \src "ls180.v:1979.6-1979.33" + wire \builder_csrbank3_enable0_we + attribute \src "ls180.v:2010.12-2010.38" + wire width 8 \builder_csrbank3_period0_r + attribute \src "ls180.v:2009.6-2009.33" + wire \builder_csrbank3_period0_re + attribute \src "ls180.v:2012.12-2012.38" + wire width 8 \builder_csrbank3_period0_w + attribute \src "ls180.v:2011.6-2011.33" + wire \builder_csrbank3_period0_we + attribute \src "ls180.v:2006.12-2006.38" + wire width 8 \builder_csrbank3_period1_r + attribute \src "ls180.v:2005.6-2005.33" + wire \builder_csrbank3_period1_re + attribute \src "ls180.v:2008.12-2008.38" + wire width 8 \builder_csrbank3_period1_w + attribute \src "ls180.v:2007.6-2007.33" + wire \builder_csrbank3_period1_we + attribute \src "ls180.v:2002.12-2002.38" + wire width 8 \builder_csrbank3_period2_r + attribute \src "ls180.v:2001.6-2001.33" + wire \builder_csrbank3_period2_re + attribute \src "ls180.v:2004.12-2004.38" + wire width 8 \builder_csrbank3_period2_w + attribute \src "ls180.v:2003.6-2003.33" + wire \builder_csrbank3_period2_we + attribute \src "ls180.v:1998.12-1998.38" + wire width 8 \builder_csrbank3_period3_r + attribute \src "ls180.v:1997.6-1997.33" + wire \builder_csrbank3_period3_re + attribute \src "ls180.v:2000.12-2000.38" + wire width 8 \builder_csrbank3_period3_w + attribute \src "ls180.v:1999.6-1999.33" + wire \builder_csrbank3_period3_we + attribute \src "ls180.v:2013.6-2013.26" + wire \builder_csrbank3_sel + attribute \src "ls180.v:1994.12-1994.37" + wire width 8 \builder_csrbank3_width0_r + attribute \src "ls180.v:1993.6-1993.32" + wire \builder_csrbank3_width0_re + attribute \src "ls180.v:1996.12-1996.37" + wire width 8 \builder_csrbank3_width0_w + attribute \src "ls180.v:1995.6-1995.32" + wire \builder_csrbank3_width0_we + attribute \src "ls180.v:1990.12-1990.37" + wire width 8 \builder_csrbank3_width1_r + attribute \src "ls180.v:1989.6-1989.32" + wire \builder_csrbank3_width1_re + attribute \src "ls180.v:1992.12-1992.37" + wire width 8 \builder_csrbank3_width1_w + attribute \src "ls180.v:1991.6-1991.32" + wire \builder_csrbank3_width1_we + attribute \src "ls180.v:1986.12-1986.37" + wire width 8 \builder_csrbank3_width2_r + attribute \src "ls180.v:1985.6-1985.32" + wire \builder_csrbank3_width2_re + attribute \src "ls180.v:1988.12-1988.37" + wire width 8 \builder_csrbank3_width2_w + attribute \src "ls180.v:1987.6-1987.32" + wire \builder_csrbank3_width2_we + attribute \src "ls180.v:1982.12-1982.37" + wire width 8 \builder_csrbank3_width3_r + attribute \src "ls180.v:1981.6-1981.32" + wire \builder_csrbank3_width3_re + attribute \src "ls180.v:1984.12-1984.37" + wire width 8 \builder_csrbank3_width3_w + attribute \src "ls180.v:1983.6-1983.32" + wire \builder_csrbank3_width3_we + attribute \src "ls180.v:2047.12-2047.40" + wire width 8 \builder_csrbank4_dma_base0_r + attribute \src "ls180.v:2046.6-2046.35" + wire \builder_csrbank4_dma_base0_re + attribute \src "ls180.v:2049.12-2049.40" + wire width 8 \builder_csrbank4_dma_base0_w + attribute \src "ls180.v:2048.6-2048.35" + wire \builder_csrbank4_dma_base0_we + attribute \src "ls180.v:2043.12-2043.40" + wire width 8 \builder_csrbank4_dma_base1_r + attribute \src "ls180.v:2042.6-2042.35" + wire \builder_csrbank4_dma_base1_re + attribute \src "ls180.v:2045.12-2045.40" + wire width 8 \builder_csrbank4_dma_base1_w + attribute \src "ls180.v:2044.6-2044.35" + wire \builder_csrbank4_dma_base1_we + attribute \src "ls180.v:2039.12-2039.40" + wire width 8 \builder_csrbank4_dma_base2_r + attribute \src "ls180.v:2038.6-2038.35" + wire \builder_csrbank4_dma_base2_re + attribute \src "ls180.v:2041.12-2041.40" + wire width 8 \builder_csrbank4_dma_base2_w + attribute \src "ls180.v:2040.6-2040.35" + wire \builder_csrbank4_dma_base2_we + attribute \src "ls180.v:2035.12-2035.40" + wire width 8 \builder_csrbank4_dma_base3_r + attribute \src "ls180.v:2034.6-2034.35" + wire \builder_csrbank4_dma_base3_re + attribute \src "ls180.v:2037.12-2037.40" + wire width 8 \builder_csrbank4_dma_base3_w + attribute \src "ls180.v:2036.6-2036.35" + wire \builder_csrbank4_dma_base3_we + attribute \src "ls180.v:2031.12-2031.40" + wire width 8 \builder_csrbank4_dma_base4_r + attribute \src "ls180.v:2030.6-2030.35" + wire \builder_csrbank4_dma_base4_re + attribute \src "ls180.v:2033.12-2033.40" + wire width 8 \builder_csrbank4_dma_base4_w + attribute \src "ls180.v:2032.6-2032.35" + wire \builder_csrbank4_dma_base4_we + attribute \src "ls180.v:2027.12-2027.40" + wire width 8 \builder_csrbank4_dma_base5_r + attribute \src "ls180.v:2026.6-2026.35" + wire \builder_csrbank4_dma_base5_re + attribute \src "ls180.v:2029.12-2029.40" + wire width 8 \builder_csrbank4_dma_base5_w + attribute \src "ls180.v:2028.6-2028.35" + wire \builder_csrbank4_dma_base5_we + attribute \src "ls180.v:2023.12-2023.40" + wire width 8 \builder_csrbank4_dma_base6_r + attribute \src "ls180.v:2022.6-2022.35" + wire \builder_csrbank4_dma_base6_re + attribute \src "ls180.v:2025.12-2025.40" + wire width 8 \builder_csrbank4_dma_base6_w + attribute \src "ls180.v:2024.6-2024.35" + wire \builder_csrbank4_dma_base6_we + attribute \src "ls180.v:2019.12-2019.40" + wire width 8 \builder_csrbank4_dma_base7_r + attribute \src "ls180.v:2018.6-2018.35" + wire \builder_csrbank4_dma_base7_re + attribute \src "ls180.v:2021.12-2021.40" + wire width 8 \builder_csrbank4_dma_base7_w + attribute \src "ls180.v:2020.6-2020.35" + wire \builder_csrbank4_dma_base7_we + attribute \src "ls180.v:2071.6-2071.33" + wire \builder_csrbank4_dma_done_r + attribute \src "ls180.v:2070.6-2070.34" + wire \builder_csrbank4_dma_done_re + attribute \src "ls180.v:2073.6-2073.33" + wire \builder_csrbank4_dma_done_w + attribute \src "ls180.v:2072.6-2072.34" + wire \builder_csrbank4_dma_done_we + attribute \src "ls180.v:2067.6-2067.36" + wire \builder_csrbank4_dma_enable0_r + attribute \src "ls180.v:2066.6-2066.37" + wire \builder_csrbank4_dma_enable0_re + attribute \src "ls180.v:2069.6-2069.36" + wire \builder_csrbank4_dma_enable0_w + attribute \src "ls180.v:2068.6-2068.37" + wire \builder_csrbank4_dma_enable0_we + attribute \src "ls180.v:2063.12-2063.42" + wire width 8 \builder_csrbank4_dma_length0_r + attribute \src "ls180.v:2062.6-2062.37" + wire \builder_csrbank4_dma_length0_re + attribute \src "ls180.v:2065.12-2065.42" + wire width 8 \builder_csrbank4_dma_length0_w + attribute \src "ls180.v:2064.6-2064.37" + wire \builder_csrbank4_dma_length0_we + attribute \src "ls180.v:2059.12-2059.42" + wire width 8 \builder_csrbank4_dma_length1_r + attribute \src "ls180.v:2058.6-2058.37" + wire \builder_csrbank4_dma_length1_re + attribute \src "ls180.v:2061.12-2061.42" + wire width 8 \builder_csrbank4_dma_length1_w + attribute \src "ls180.v:2060.6-2060.37" + wire \builder_csrbank4_dma_length1_we + attribute \src "ls180.v:2055.12-2055.42" + wire width 8 \builder_csrbank4_dma_length2_r + attribute \src "ls180.v:2054.6-2054.37" + wire \builder_csrbank4_dma_length2_re + attribute \src "ls180.v:2057.12-2057.42" + wire width 8 \builder_csrbank4_dma_length2_w + attribute \src "ls180.v:2056.6-2056.37" + wire \builder_csrbank4_dma_length2_we + attribute \src "ls180.v:2051.12-2051.42" + wire width 8 \builder_csrbank4_dma_length3_r + attribute \src "ls180.v:2050.6-2050.37" + wire \builder_csrbank4_dma_length3_re + attribute \src "ls180.v:2053.12-2053.42" + wire width 8 \builder_csrbank4_dma_length3_w + attribute \src "ls180.v:2052.6-2052.37" + wire \builder_csrbank4_dma_length3_we + attribute \src "ls180.v:2075.6-2075.34" + wire \builder_csrbank4_dma_loop0_r + attribute \src "ls180.v:2074.6-2074.35" + wire \builder_csrbank4_dma_loop0_re + attribute \src "ls180.v:2077.6-2077.34" + wire \builder_csrbank4_dma_loop0_w + attribute \src "ls180.v:2076.6-2076.35" + wire \builder_csrbank4_dma_loop0_we + attribute \src "ls180.v:2078.6-2078.26" + wire \builder_csrbank4_sel + attribute \src "ls180.v:2208.12-2208.43" + wire width 8 \builder_csrbank5_block_count0_r + attribute \src "ls180.v:2207.6-2207.38" + wire \builder_csrbank5_block_count0_re + attribute \src "ls180.v:2210.12-2210.43" + wire width 8 \builder_csrbank5_block_count0_w + attribute \src "ls180.v:2209.6-2209.38" + wire \builder_csrbank5_block_count0_we + attribute \src "ls180.v:2204.12-2204.43" + wire width 8 \builder_csrbank5_block_count1_r + attribute \src "ls180.v:2203.6-2203.38" + wire \builder_csrbank5_block_count1_re + attribute \src "ls180.v:2206.12-2206.43" + wire width 8 \builder_csrbank5_block_count1_w + attribute \src "ls180.v:2205.6-2205.38" + wire \builder_csrbank5_block_count1_we + attribute \src "ls180.v:2200.12-2200.43" + wire width 8 \builder_csrbank5_block_count2_r + attribute \src "ls180.v:2199.6-2199.38" + wire \builder_csrbank5_block_count2_re + attribute \src "ls180.v:2202.12-2202.43" + wire width 8 \builder_csrbank5_block_count2_w + attribute \src "ls180.v:2201.6-2201.38" + wire \builder_csrbank5_block_count2_we + attribute \src "ls180.v:2196.12-2196.43" + wire width 8 \builder_csrbank5_block_count3_r + attribute \src "ls180.v:2195.6-2195.38" + wire \builder_csrbank5_block_count3_re + attribute \src "ls180.v:2198.12-2198.43" + wire width 8 \builder_csrbank5_block_count3_w + attribute \src "ls180.v:2197.6-2197.38" + wire \builder_csrbank5_block_count3_we + attribute \src "ls180.v:2192.12-2192.44" + wire width 8 \builder_csrbank5_block_length0_r + attribute \src "ls180.v:2191.6-2191.39" + wire \builder_csrbank5_block_length0_re + attribute \src "ls180.v:2194.12-2194.44" + wire width 8 \builder_csrbank5_block_length0_w + attribute \src "ls180.v:2193.6-2193.39" + wire \builder_csrbank5_block_length0_we + attribute \src "ls180.v:2188.12-2188.44" + wire width 2 \builder_csrbank5_block_length1_r + attribute \src "ls180.v:2187.6-2187.39" + wire \builder_csrbank5_block_length1_re + attribute \src "ls180.v:2190.12-2190.44" + wire width 2 \builder_csrbank5_block_length1_w + attribute \src "ls180.v:2189.6-2189.39" + wire \builder_csrbank5_block_length1_we + attribute \src "ls180.v:2096.12-2096.44" + wire width 8 \builder_csrbank5_cmd_argument0_r + attribute \src "ls180.v:2095.6-2095.39" + wire \builder_csrbank5_cmd_argument0_re + attribute \src "ls180.v:2098.12-2098.44" + wire width 8 \builder_csrbank5_cmd_argument0_w + attribute \src "ls180.v:2097.6-2097.39" + wire \builder_csrbank5_cmd_argument0_we + attribute \src "ls180.v:2092.12-2092.44" + wire width 8 \builder_csrbank5_cmd_argument1_r + attribute \src "ls180.v:2091.6-2091.39" + wire \builder_csrbank5_cmd_argument1_re + attribute \src "ls180.v:2094.12-2094.44" + wire width 8 \builder_csrbank5_cmd_argument1_w + attribute \src "ls180.v:2093.6-2093.39" + wire \builder_csrbank5_cmd_argument1_we + attribute \src "ls180.v:2088.12-2088.44" + wire width 8 \builder_csrbank5_cmd_argument2_r + attribute \src "ls180.v:2087.6-2087.39" + wire \builder_csrbank5_cmd_argument2_re + attribute \src "ls180.v:2090.12-2090.44" + wire width 8 \builder_csrbank5_cmd_argument2_w + attribute \src "ls180.v:2089.6-2089.39" + wire \builder_csrbank5_cmd_argument2_we + attribute \src "ls180.v:2084.12-2084.44" + wire width 8 \builder_csrbank5_cmd_argument3_r + attribute \src "ls180.v:2083.6-2083.39" + wire \builder_csrbank5_cmd_argument3_re + attribute \src "ls180.v:2086.12-2086.44" + wire width 8 \builder_csrbank5_cmd_argument3_w + attribute \src "ls180.v:2085.6-2085.39" + wire \builder_csrbank5_cmd_argument3_we + attribute \src "ls180.v:2112.12-2112.43" + wire width 8 \builder_csrbank5_cmd_command0_r + attribute \src "ls180.v:2111.6-2111.38" + wire \builder_csrbank5_cmd_command0_re + attribute \src "ls180.v:2114.12-2114.43" + wire width 8 \builder_csrbank5_cmd_command0_w + attribute \src "ls180.v:2113.6-2113.38" + wire \builder_csrbank5_cmd_command0_we + attribute \src "ls180.v:2108.12-2108.43" + wire width 8 \builder_csrbank5_cmd_command1_r + attribute \src "ls180.v:2107.6-2107.38" + wire \builder_csrbank5_cmd_command1_re + attribute \src "ls180.v:2110.12-2110.43" + wire width 8 \builder_csrbank5_cmd_command1_w + attribute \src "ls180.v:2109.6-2109.38" + wire \builder_csrbank5_cmd_command1_we + attribute \src "ls180.v:2104.12-2104.43" + wire width 8 \builder_csrbank5_cmd_command2_r + attribute \src "ls180.v:2103.6-2103.38" + wire \builder_csrbank5_cmd_command2_re + attribute \src "ls180.v:2106.12-2106.43" + wire width 8 \builder_csrbank5_cmd_command2_w + attribute \src "ls180.v:2105.6-2105.38" + wire \builder_csrbank5_cmd_command2_we + attribute \src "ls180.v:2100.12-2100.43" + wire width 8 \builder_csrbank5_cmd_command3_r + attribute \src "ls180.v:2099.6-2099.38" + wire \builder_csrbank5_cmd_command3_re + attribute \src "ls180.v:2102.12-2102.43" + wire width 8 \builder_csrbank5_cmd_command3_w + attribute \src "ls180.v:2101.6-2101.38" + wire \builder_csrbank5_cmd_command3_we + attribute \src "ls180.v:2180.12-2180.40" + wire width 4 \builder_csrbank5_cmd_event_r + attribute \src "ls180.v:2179.6-2179.35" + wire \builder_csrbank5_cmd_event_re + attribute \src "ls180.v:2182.12-2182.40" + wire width 4 \builder_csrbank5_cmd_event_w + attribute \src "ls180.v:2181.6-2181.35" + wire \builder_csrbank5_cmd_event_we + attribute \src "ls180.v:2176.12-2176.44" + wire width 8 \builder_csrbank5_cmd_response0_r + attribute \src "ls180.v:2175.6-2175.39" + wire \builder_csrbank5_cmd_response0_re + attribute \src "ls180.v:2178.12-2178.44" + wire width 8 \builder_csrbank5_cmd_response0_w + attribute \src "ls180.v:2177.6-2177.39" + wire \builder_csrbank5_cmd_response0_we + attribute \src "ls180.v:2136.12-2136.45" + wire width 8 \builder_csrbank5_cmd_response10_r + attribute \src "ls180.v:2135.6-2135.40" + wire \builder_csrbank5_cmd_response10_re + attribute \src "ls180.v:2138.12-2138.45" + wire width 8 \builder_csrbank5_cmd_response10_w + attribute \src "ls180.v:2137.6-2137.40" + wire \builder_csrbank5_cmd_response10_we + attribute \src "ls180.v:2132.12-2132.45" + wire width 8 \builder_csrbank5_cmd_response11_r + attribute \src "ls180.v:2131.6-2131.40" + wire \builder_csrbank5_cmd_response11_re + attribute \src "ls180.v:2134.12-2134.45" + wire width 8 \builder_csrbank5_cmd_response11_w + attribute \src "ls180.v:2133.6-2133.40" + wire \builder_csrbank5_cmd_response11_we + attribute \src "ls180.v:2128.12-2128.45" + wire width 8 \builder_csrbank5_cmd_response12_r + attribute \src "ls180.v:2127.6-2127.40" + wire \builder_csrbank5_cmd_response12_re + attribute \src "ls180.v:2130.12-2130.45" + wire width 8 \builder_csrbank5_cmd_response12_w + attribute \src "ls180.v:2129.6-2129.40" + wire \builder_csrbank5_cmd_response12_we + attribute \src "ls180.v:2124.12-2124.45" + wire width 8 \builder_csrbank5_cmd_response13_r + attribute \src "ls180.v:2123.6-2123.40" + wire \builder_csrbank5_cmd_response13_re + attribute \src "ls180.v:2126.12-2126.45" + wire width 8 \builder_csrbank5_cmd_response13_w + attribute \src "ls180.v:2125.6-2125.40" + wire \builder_csrbank5_cmd_response13_we + attribute \src "ls180.v:2120.12-2120.45" + wire width 8 \builder_csrbank5_cmd_response14_r + attribute \src "ls180.v:2119.6-2119.40" + wire \builder_csrbank5_cmd_response14_re + attribute \src "ls180.v:2122.12-2122.45" + wire width 8 \builder_csrbank5_cmd_response14_w + attribute \src "ls180.v:2121.6-2121.40" + wire \builder_csrbank5_cmd_response14_we + attribute \src "ls180.v:2116.12-2116.45" + wire width 8 \builder_csrbank5_cmd_response15_r + attribute \src "ls180.v:2115.6-2115.40" + wire \builder_csrbank5_cmd_response15_re + attribute \src "ls180.v:2118.12-2118.45" + wire width 8 \builder_csrbank5_cmd_response15_w + attribute \src "ls180.v:2117.6-2117.40" + wire \builder_csrbank5_cmd_response15_we + attribute \src "ls180.v:2172.12-2172.44" + wire width 8 \builder_csrbank5_cmd_response1_r + attribute \src "ls180.v:2171.6-2171.39" + wire \builder_csrbank5_cmd_response1_re + attribute \src "ls180.v:2174.12-2174.44" + wire width 8 \builder_csrbank5_cmd_response1_w + attribute \src "ls180.v:2173.6-2173.39" + wire \builder_csrbank5_cmd_response1_we + attribute \src "ls180.v:2168.12-2168.44" + wire width 8 \builder_csrbank5_cmd_response2_r + attribute \src "ls180.v:2167.6-2167.39" + wire \builder_csrbank5_cmd_response2_re + attribute \src "ls180.v:2170.12-2170.44" + wire width 8 \builder_csrbank5_cmd_response2_w + attribute \src "ls180.v:2169.6-2169.39" + wire \builder_csrbank5_cmd_response2_we + attribute \src "ls180.v:2164.12-2164.44" + wire width 8 \builder_csrbank5_cmd_response3_r + attribute \src "ls180.v:2163.6-2163.39" + wire \builder_csrbank5_cmd_response3_re + attribute \src "ls180.v:2166.12-2166.44" + wire width 8 \builder_csrbank5_cmd_response3_w + attribute \src "ls180.v:2165.6-2165.39" + wire \builder_csrbank5_cmd_response3_we + attribute \src "ls180.v:2160.12-2160.44" + wire width 8 \builder_csrbank5_cmd_response4_r + attribute \src "ls180.v:2159.6-2159.39" + wire \builder_csrbank5_cmd_response4_re + attribute \src "ls180.v:2162.12-2162.44" + wire width 8 \builder_csrbank5_cmd_response4_w + attribute \src "ls180.v:2161.6-2161.39" + wire \builder_csrbank5_cmd_response4_we + attribute \src "ls180.v:2156.12-2156.44" + wire width 8 \builder_csrbank5_cmd_response5_r + attribute \src "ls180.v:2155.6-2155.39" + wire \builder_csrbank5_cmd_response5_re + attribute \src "ls180.v:2158.12-2158.44" + wire width 8 \builder_csrbank5_cmd_response5_w + attribute \src "ls180.v:2157.6-2157.39" + wire \builder_csrbank5_cmd_response5_we + attribute \src "ls180.v:2152.12-2152.44" + wire width 8 \builder_csrbank5_cmd_response6_r + attribute \src "ls180.v:2151.6-2151.39" + wire \builder_csrbank5_cmd_response6_re + attribute \src "ls180.v:2154.12-2154.44" + wire width 8 \builder_csrbank5_cmd_response6_w + attribute \src "ls180.v:2153.6-2153.39" + wire \builder_csrbank5_cmd_response6_we + attribute \src "ls180.v:2148.12-2148.44" + wire width 8 \builder_csrbank5_cmd_response7_r + attribute \src "ls180.v:2147.6-2147.39" + wire \builder_csrbank5_cmd_response7_re + attribute \src "ls180.v:2150.12-2150.44" + wire width 8 \builder_csrbank5_cmd_response7_w + attribute \src "ls180.v:2149.6-2149.39" + wire \builder_csrbank5_cmd_response7_we + attribute \src "ls180.v:2144.12-2144.44" + wire width 8 \builder_csrbank5_cmd_response8_r + attribute \src "ls180.v:2143.6-2143.39" + wire \builder_csrbank5_cmd_response8_re + attribute \src "ls180.v:2146.12-2146.44" + wire width 8 \builder_csrbank5_cmd_response8_w + attribute \src "ls180.v:2145.6-2145.39" + wire \builder_csrbank5_cmd_response8_we + attribute \src "ls180.v:2140.12-2140.44" + wire width 8 \builder_csrbank5_cmd_response9_r + attribute \src "ls180.v:2139.6-2139.39" + wire \builder_csrbank5_cmd_response9_re + attribute \src "ls180.v:2142.12-2142.44" + wire width 8 \builder_csrbank5_cmd_response9_w + attribute \src "ls180.v:2141.6-2141.39" + wire \builder_csrbank5_cmd_response9_we + attribute \src "ls180.v:2184.12-2184.41" + wire width 4 \builder_csrbank5_data_event_r + attribute \src "ls180.v:2183.6-2183.36" + wire \builder_csrbank5_data_event_re + attribute \src "ls180.v:2186.12-2186.41" + wire width 4 \builder_csrbank5_data_event_w + attribute \src "ls180.v:2185.6-2185.36" + wire \builder_csrbank5_data_event_we + attribute \src "ls180.v:2211.6-2211.26" + wire \builder_csrbank5_sel + attribute \src "ls180.v:2245.12-2245.40" + wire width 8 \builder_csrbank6_dma_base0_r + attribute \src "ls180.v:2244.6-2244.35" + wire \builder_csrbank6_dma_base0_re + attribute \src "ls180.v:2247.12-2247.40" + wire width 8 \builder_csrbank6_dma_base0_w + attribute \src "ls180.v:2246.6-2246.35" + wire \builder_csrbank6_dma_base0_we + attribute \src "ls180.v:2241.12-2241.40" + wire width 8 \builder_csrbank6_dma_base1_r + attribute \src "ls180.v:2240.6-2240.35" + wire \builder_csrbank6_dma_base1_re + attribute \src "ls180.v:2243.12-2243.40" + wire width 8 \builder_csrbank6_dma_base1_w + attribute \src "ls180.v:2242.6-2242.35" + wire \builder_csrbank6_dma_base1_we + attribute \src "ls180.v:2237.12-2237.40" + wire width 8 \builder_csrbank6_dma_base2_r + attribute \src "ls180.v:2236.6-2236.35" + wire \builder_csrbank6_dma_base2_re + attribute \src "ls180.v:2239.12-2239.40" + wire width 8 \builder_csrbank6_dma_base2_w + attribute \src "ls180.v:2238.6-2238.35" + wire \builder_csrbank6_dma_base2_we + attribute \src "ls180.v:2233.12-2233.40" + wire width 8 \builder_csrbank6_dma_base3_r + attribute \src "ls180.v:2232.6-2232.35" + wire \builder_csrbank6_dma_base3_re + attribute \src "ls180.v:2235.12-2235.40" + wire width 8 \builder_csrbank6_dma_base3_w + attribute \src "ls180.v:2234.6-2234.35" + wire \builder_csrbank6_dma_base3_we + attribute \src "ls180.v:2229.12-2229.40" + wire width 8 \builder_csrbank6_dma_base4_r + attribute \src "ls180.v:2228.6-2228.35" + wire \builder_csrbank6_dma_base4_re + attribute \src "ls180.v:2231.12-2231.40" + wire width 8 \builder_csrbank6_dma_base4_w + attribute \src "ls180.v:2230.6-2230.35" + wire \builder_csrbank6_dma_base4_we + attribute \src "ls180.v:2225.12-2225.40" + wire width 8 \builder_csrbank6_dma_base5_r + attribute \src "ls180.v:2224.6-2224.35" + wire \builder_csrbank6_dma_base5_re + attribute \src "ls180.v:2227.12-2227.40" + wire width 8 \builder_csrbank6_dma_base5_w + attribute \src "ls180.v:2226.6-2226.35" + wire \builder_csrbank6_dma_base5_we + attribute \src "ls180.v:2221.12-2221.40" + wire width 8 \builder_csrbank6_dma_base6_r + attribute \src "ls180.v:2220.6-2220.35" + wire \builder_csrbank6_dma_base6_re + attribute \src "ls180.v:2223.12-2223.40" + wire width 8 \builder_csrbank6_dma_base6_w + attribute \src "ls180.v:2222.6-2222.35" + wire \builder_csrbank6_dma_base6_we + attribute \src "ls180.v:2217.12-2217.40" + wire width 8 \builder_csrbank6_dma_base7_r + attribute \src "ls180.v:2216.6-2216.35" + wire \builder_csrbank6_dma_base7_re + attribute \src "ls180.v:2219.12-2219.40" + wire width 8 \builder_csrbank6_dma_base7_w + attribute \src "ls180.v:2218.6-2218.35" + wire \builder_csrbank6_dma_base7_we + attribute \src "ls180.v:2269.6-2269.33" + wire \builder_csrbank6_dma_done_r + attribute \src "ls180.v:2268.6-2268.34" + wire \builder_csrbank6_dma_done_re + attribute \src "ls180.v:2271.6-2271.33" + wire \builder_csrbank6_dma_done_w + attribute \src "ls180.v:2270.6-2270.34" + wire \builder_csrbank6_dma_done_we + attribute \src "ls180.v:2265.6-2265.36" + wire \builder_csrbank6_dma_enable0_r + attribute \src "ls180.v:2264.6-2264.37" + wire \builder_csrbank6_dma_enable0_re + attribute \src "ls180.v:2267.6-2267.36" + wire \builder_csrbank6_dma_enable0_w + attribute \src "ls180.v:2266.6-2266.37" + wire \builder_csrbank6_dma_enable0_we + attribute \src "ls180.v:2261.12-2261.42" + wire width 8 \builder_csrbank6_dma_length0_r + attribute \src "ls180.v:2260.6-2260.37" + wire \builder_csrbank6_dma_length0_re + attribute \src "ls180.v:2263.12-2263.42" + wire width 8 \builder_csrbank6_dma_length0_w + attribute \src "ls180.v:2262.6-2262.37" + wire \builder_csrbank6_dma_length0_we + attribute \src "ls180.v:2257.12-2257.42" + wire width 8 \builder_csrbank6_dma_length1_r + attribute \src "ls180.v:2256.6-2256.37" + wire \builder_csrbank6_dma_length1_re + attribute \src "ls180.v:2259.12-2259.42" + wire width 8 \builder_csrbank6_dma_length1_w + attribute \src "ls180.v:2258.6-2258.37" + wire \builder_csrbank6_dma_length1_we + attribute \src "ls180.v:2253.12-2253.42" + wire width 8 \builder_csrbank6_dma_length2_r + attribute \src "ls180.v:2252.6-2252.37" + wire \builder_csrbank6_dma_length2_re + attribute \src "ls180.v:2255.12-2255.42" + wire width 8 \builder_csrbank6_dma_length2_w + attribute \src "ls180.v:2254.6-2254.37" + wire \builder_csrbank6_dma_length2_we + attribute \src "ls180.v:2249.12-2249.42" + wire width 8 \builder_csrbank6_dma_length3_r + attribute \src "ls180.v:2248.6-2248.37" + wire \builder_csrbank6_dma_length3_re + attribute \src "ls180.v:2251.12-2251.42" + wire width 8 \builder_csrbank6_dma_length3_w + attribute \src "ls180.v:2250.6-2250.37" + wire \builder_csrbank6_dma_length3_we + attribute \src "ls180.v:2273.6-2273.34" + wire \builder_csrbank6_dma_loop0_r + attribute \src "ls180.v:2272.6-2272.35" + wire \builder_csrbank6_dma_loop0_re + attribute \src "ls180.v:2275.6-2275.34" + wire \builder_csrbank6_dma_loop0_w + attribute \src "ls180.v:2274.6-2274.35" + wire \builder_csrbank6_dma_loop0_we + attribute \src "ls180.v:2289.12-2289.42" + wire width 8 \builder_csrbank6_dma_offset0_r + attribute \src "ls180.v:2288.6-2288.37" + wire \builder_csrbank6_dma_offset0_re + attribute \src "ls180.v:2291.12-2291.42" + wire width 8 \builder_csrbank6_dma_offset0_w + attribute \src "ls180.v:2290.6-2290.37" + wire \builder_csrbank6_dma_offset0_we + attribute \src "ls180.v:2285.12-2285.42" + wire width 8 \builder_csrbank6_dma_offset1_r + attribute \src "ls180.v:2284.6-2284.37" + wire \builder_csrbank6_dma_offset1_re + attribute \src "ls180.v:2287.12-2287.42" + wire width 8 \builder_csrbank6_dma_offset1_w + attribute \src "ls180.v:2286.6-2286.37" + wire \builder_csrbank6_dma_offset1_we + attribute \src "ls180.v:2281.12-2281.42" + wire width 8 \builder_csrbank6_dma_offset2_r + attribute \src "ls180.v:2280.6-2280.37" + wire \builder_csrbank6_dma_offset2_re + attribute \src "ls180.v:2283.12-2283.42" + wire width 8 \builder_csrbank6_dma_offset2_w + attribute \src "ls180.v:2282.6-2282.37" + wire \builder_csrbank6_dma_offset2_we + attribute \src "ls180.v:2277.12-2277.42" + wire width 8 \builder_csrbank6_dma_offset3_r + attribute \src "ls180.v:2276.6-2276.37" + wire \builder_csrbank6_dma_offset3_re + attribute \src "ls180.v:2279.12-2279.42" + wire width 8 \builder_csrbank6_dma_offset3_w + attribute \src "ls180.v:2278.6-2278.37" + wire \builder_csrbank6_dma_offset3_we + attribute \src "ls180.v:2292.6-2292.26" + wire \builder_csrbank6_sel + attribute \src "ls180.v:2298.6-2298.36" + wire \builder_csrbank7_card_detect_r + attribute \src "ls180.v:2297.6-2297.37" + wire \builder_csrbank7_card_detect_re + attribute \src "ls180.v:2300.6-2300.36" + wire \builder_csrbank7_card_detect_w + attribute \src "ls180.v:2299.6-2299.37" + wire \builder_csrbank7_card_detect_we + attribute \src "ls180.v:2306.12-2306.47" + wire width 8 \builder_csrbank7_clocker_divider0_r + attribute \src "ls180.v:2305.6-2305.42" + wire \builder_csrbank7_clocker_divider0_re + attribute \src "ls180.v:2308.12-2308.47" + wire width 8 \builder_csrbank7_clocker_divider0_w + attribute \src "ls180.v:2307.6-2307.42" + wire \builder_csrbank7_clocker_divider0_we + attribute \src "ls180.v:2302.6-2302.41" + wire \builder_csrbank7_clocker_divider1_r + attribute \src "ls180.v:2301.6-2301.42" + wire \builder_csrbank7_clocker_divider1_re + attribute \src "ls180.v:2304.6-2304.41" + wire \builder_csrbank7_clocker_divider1_w + attribute \src "ls180.v:2303.6-2303.42" + wire \builder_csrbank7_clocker_divider1_we + attribute \src "ls180.v:2309.6-2309.26" + wire \builder_csrbank7_sel + attribute \src "ls180.v:2315.12-2315.44" + wire width 4 \builder_csrbank8_dfii_control0_r + attribute \src "ls180.v:2314.6-2314.39" + wire \builder_csrbank8_dfii_control0_re + attribute \src "ls180.v:2317.12-2317.44" + wire width 4 \builder_csrbank8_dfii_control0_w + attribute \src "ls180.v:2316.6-2316.39" + wire \builder_csrbank8_dfii_control0_we + attribute \src "ls180.v:2327.12-2327.48" + wire width 8 \builder_csrbank8_dfii_pi0_address0_r + attribute \src "ls180.v:2326.6-2326.43" + wire \builder_csrbank8_dfii_pi0_address0_re + attribute \src "ls180.v:2329.12-2329.48" + wire width 8 \builder_csrbank8_dfii_pi0_address0_w + attribute \src "ls180.v:2328.6-2328.43" + wire \builder_csrbank8_dfii_pi0_address0_we + attribute \src "ls180.v:2323.12-2323.48" + wire width 5 \builder_csrbank8_dfii_pi0_address1_r + attribute \src "ls180.v:2322.6-2322.43" + wire \builder_csrbank8_dfii_pi0_address1_re + attribute \src "ls180.v:2325.12-2325.48" + wire width 5 \builder_csrbank8_dfii_pi0_address1_w + attribute \src "ls180.v:2324.6-2324.43" + wire \builder_csrbank8_dfii_pi0_address1_we + attribute \src "ls180.v:2331.12-2331.49" + wire width 2 \builder_csrbank8_dfii_pi0_baddress0_r + attribute \src "ls180.v:2330.6-2330.44" + wire \builder_csrbank8_dfii_pi0_baddress0_re + attribute \src "ls180.v:2333.12-2333.49" + wire width 2 \builder_csrbank8_dfii_pi0_baddress0_w + attribute \src "ls180.v:2332.6-2332.44" + wire \builder_csrbank8_dfii_pi0_baddress0_we + attribute \src "ls180.v:2319.12-2319.48" + wire width 6 \builder_csrbank8_dfii_pi0_command0_r + attribute \src "ls180.v:2318.6-2318.43" + wire \builder_csrbank8_dfii_pi0_command0_re + attribute \src "ls180.v:2321.12-2321.48" + wire width 6 \builder_csrbank8_dfii_pi0_command0_w + attribute \src "ls180.v:2320.6-2320.43" + wire \builder_csrbank8_dfii_pi0_command0_we + attribute \src "ls180.v:2347.12-2347.47" + wire width 8 \builder_csrbank8_dfii_pi0_rddata0_r + attribute \src "ls180.v:2346.6-2346.42" + wire \builder_csrbank8_dfii_pi0_rddata0_re + attribute \src "ls180.v:2349.12-2349.47" + wire width 8 \builder_csrbank8_dfii_pi0_rddata0_w + attribute \src "ls180.v:2348.6-2348.42" + wire \builder_csrbank8_dfii_pi0_rddata0_we + attribute \src "ls180.v:2343.12-2343.47" + wire width 8 \builder_csrbank8_dfii_pi0_rddata1_r + attribute \src "ls180.v:2342.6-2342.42" + wire \builder_csrbank8_dfii_pi0_rddata1_re + attribute \src "ls180.v:2345.12-2345.47" + wire width 8 \builder_csrbank8_dfii_pi0_rddata1_w + attribute \src "ls180.v:2344.6-2344.42" + wire \builder_csrbank8_dfii_pi0_rddata1_we + attribute \src "ls180.v:2339.12-2339.47" + wire width 8 \builder_csrbank8_dfii_pi0_wrdata0_r + attribute \src "ls180.v:2338.6-2338.42" + wire \builder_csrbank8_dfii_pi0_wrdata0_re + attribute \src "ls180.v:2341.12-2341.47" + wire width 8 \builder_csrbank8_dfii_pi0_wrdata0_w + attribute \src "ls180.v:2340.6-2340.42" + wire \builder_csrbank8_dfii_pi0_wrdata0_we + attribute \src "ls180.v:2335.12-2335.47" + wire width 8 \builder_csrbank8_dfii_pi0_wrdata1_r + attribute \src "ls180.v:2334.6-2334.42" + wire \builder_csrbank8_dfii_pi0_wrdata1_re + attribute \src "ls180.v:2337.12-2337.47" + wire width 8 \builder_csrbank8_dfii_pi0_wrdata1_w + attribute \src "ls180.v:2336.6-2336.42" + wire \builder_csrbank8_dfii_pi0_wrdata1_we + attribute \src "ls180.v:2350.6-2350.26" + wire \builder_csrbank8_sel + attribute \src "ls180.v:2360.12-2360.39" + wire width 8 \builder_csrbank9_control0_r + attribute \src "ls180.v:2359.6-2359.34" + wire \builder_csrbank9_control0_re + attribute \src "ls180.v:2362.12-2362.39" + wire width 8 \builder_csrbank9_control0_w + attribute \src "ls180.v:2361.6-2361.34" + wire \builder_csrbank9_control0_we + attribute \src "ls180.v:2356.12-2356.39" + wire width 8 \builder_csrbank9_control1_r + attribute \src "ls180.v:2355.6-2355.34" + wire \builder_csrbank9_control1_re + attribute \src "ls180.v:2358.12-2358.39" + wire width 8 \builder_csrbank9_control1_w + attribute \src "ls180.v:2357.6-2357.34" + wire \builder_csrbank9_control1_we + attribute \src "ls180.v:2376.6-2376.28" + wire \builder_csrbank9_cs0_r + attribute \src "ls180.v:2375.6-2375.29" + wire \builder_csrbank9_cs0_re + attribute \src "ls180.v:2378.6-2378.28" + wire \builder_csrbank9_cs0_w + attribute \src "ls180.v:2377.6-2377.29" + wire \builder_csrbank9_cs0_we + attribute \src "ls180.v:2380.6-2380.34" + wire \builder_csrbank9_loopback0_r + attribute \src "ls180.v:2379.6-2379.35" + wire \builder_csrbank9_loopback0_re + attribute \src "ls180.v:2382.6-2382.34" + wire \builder_csrbank9_loopback0_w + attribute \src "ls180.v:2381.6-2381.35" + wire \builder_csrbank9_loopback0_we + attribute \src "ls180.v:2372.12-2372.35" + wire width 8 \builder_csrbank9_miso_r + attribute \src "ls180.v:2371.6-2371.30" + wire \builder_csrbank9_miso_re + attribute \src "ls180.v:2374.12-2374.35" + wire width 8 \builder_csrbank9_miso_w + attribute \src "ls180.v:2373.6-2373.30" + wire \builder_csrbank9_miso_we + attribute \src "ls180.v:2368.12-2368.36" + wire width 8 \builder_csrbank9_mosi0_r + attribute \src "ls180.v:2367.6-2367.31" + wire \builder_csrbank9_mosi0_re + attribute \src "ls180.v:2370.12-2370.36" + wire width 8 \builder_csrbank9_mosi0_w + attribute \src "ls180.v:2369.6-2369.31" + wire \builder_csrbank9_mosi0_we + attribute \src "ls180.v:2383.6-2383.26" + wire \builder_csrbank9_sel + attribute \src "ls180.v:2364.6-2364.31" + wire \builder_csrbank9_status_r + attribute \src "ls180.v:2363.6-2363.32" + wire \builder_csrbank9_status_re + attribute \src "ls180.v:2366.6-2366.31" + wire \builder_csrbank9_status_w + attribute \src "ls180.v:2365.6-2365.32" + wire \builder_csrbank9_status_we + attribute \src "ls180.v:1860.6-1860.18" + wire \builder_done + attribute \src "ls180.v:1858.5-1858.18" + wire \builder_error + attribute \src "ls180.v:1855.11-1855.24" + wire width 3 \builder_grant + attribute \src "ls180.v:1862.13-1862.44" + wire width 14 \builder_interface0_bank_bus_adr + attribute \src "ls180.v:1865.11-1865.44" + wire width 8 \builder_interface0_bank_bus_dat_r + attribute \src "ls180.v:1864.12-1864.45" + wire width 8 \builder_interface0_bank_bus_dat_w + attribute \src "ls180.v:1863.6-1863.36" + wire \builder_interface0_bank_bus_we + attribute \src "ls180.v:2384.13-2384.45" + wire width 14 \builder_interface10_bank_bus_adr + attribute \src "ls180.v:2387.11-2387.45" + wire width 8 \builder_interface10_bank_bus_dat_r + attribute \src "ls180.v:2386.12-2386.46" + wire width 8 \builder_interface10_bank_bus_dat_w + attribute \src "ls180.v:2385.6-2385.37" + wire \builder_interface10_bank_bus_we + attribute \src "ls180.v:2425.13-2425.45" + wire width 14 \builder_interface11_bank_bus_adr + attribute \src "ls180.v:2428.11-2428.45" + wire width 8 \builder_interface11_bank_bus_dat_r + attribute \src "ls180.v:2427.12-2427.46" + wire width 8 \builder_interface11_bank_bus_dat_w + attribute \src "ls180.v:2426.6-2426.37" + wire \builder_interface11_bank_bus_we + attribute \src "ls180.v:2490.13-2490.45" + wire width 14 \builder_interface12_bank_bus_adr + attribute \src "ls180.v:2493.11-2493.45" + wire width 8 \builder_interface12_bank_bus_dat_r + attribute \src "ls180.v:2492.12-2492.46" + wire width 8 \builder_interface12_bank_bus_dat_w + attribute \src "ls180.v:2491.6-2491.37" + wire \builder_interface12_bank_bus_we + attribute \src "ls180.v:2515.13-2515.45" + wire width 14 \builder_interface13_bank_bus_adr + attribute \src "ls180.v:2518.11-2518.45" + wire width 8 \builder_interface13_bank_bus_dat_r + attribute \src "ls180.v:2517.12-2517.46" + wire width 8 \builder_interface13_bank_bus_dat_w + attribute \src "ls180.v:2516.6-2516.37" + wire \builder_interface13_bank_bus_we + attribute \src "ls180.v:1903.13-1903.44" + wire width 14 \builder_interface1_bank_bus_adr + attribute \src "ls180.v:1906.11-1906.44" + wire width 8 \builder_interface1_bank_bus_dat_r + attribute \src "ls180.v:1905.12-1905.45" + wire width 8 \builder_interface1_bank_bus_dat_w + attribute \src "ls180.v:1904.6-1904.36" + wire \builder_interface1_bank_bus_we + attribute \src "ls180.v:1932.13-1932.44" + wire width 14 \builder_interface2_bank_bus_adr + attribute \src "ls180.v:1935.11-1935.44" + wire width 8 \builder_interface2_bank_bus_dat_r + attribute \src "ls180.v:1934.12-1934.45" + wire width 8 \builder_interface2_bank_bus_dat_w + attribute \src "ls180.v:1933.6-1933.36" + wire \builder_interface2_bank_bus_we + attribute \src "ls180.v:1973.13-1973.44" + wire width 14 \builder_interface3_bank_bus_adr + attribute \src "ls180.v:1976.11-1976.44" + wire width 8 \builder_interface3_bank_bus_dat_r + attribute \src "ls180.v:1975.12-1975.45" + wire width 8 \builder_interface3_bank_bus_dat_w + attribute \src "ls180.v:1974.6-1974.36" + wire \builder_interface3_bank_bus_we + attribute \src "ls180.v:2014.13-2014.44" + wire width 14 \builder_interface4_bank_bus_adr + attribute \src "ls180.v:2017.11-2017.44" + wire width 8 \builder_interface4_bank_bus_dat_r + attribute \src "ls180.v:2016.12-2016.45" + wire width 8 \builder_interface4_bank_bus_dat_w + attribute \src "ls180.v:2015.6-2015.36" + wire \builder_interface4_bank_bus_we + attribute \src "ls180.v:2079.13-2079.44" + wire width 14 \builder_interface5_bank_bus_adr + attribute \src "ls180.v:2082.11-2082.44" + wire width 8 \builder_interface5_bank_bus_dat_r + attribute \src "ls180.v:2081.12-2081.45" + wire width 8 \builder_interface5_bank_bus_dat_w + attribute \src "ls180.v:2080.6-2080.36" + wire \builder_interface5_bank_bus_we + attribute \src "ls180.v:2212.13-2212.44" + wire width 14 \builder_interface6_bank_bus_adr + attribute \src "ls180.v:2215.11-2215.44" + wire width 8 \builder_interface6_bank_bus_dat_r + attribute \src "ls180.v:2214.12-2214.45" + wire width 8 \builder_interface6_bank_bus_dat_w + attribute \src "ls180.v:2213.6-2213.36" + wire \builder_interface6_bank_bus_we + attribute \src "ls180.v:2293.13-2293.44" + wire width 14 \builder_interface7_bank_bus_adr + attribute \src "ls180.v:2296.11-2296.44" + wire width 8 \builder_interface7_bank_bus_dat_r + attribute \src "ls180.v:2295.12-2295.45" + wire width 8 \builder_interface7_bank_bus_dat_w + attribute \src "ls180.v:2294.6-2294.36" + wire \builder_interface7_bank_bus_we + attribute \src "ls180.v:2310.13-2310.44" + wire width 14 \builder_interface8_bank_bus_adr + attribute \src "ls180.v:2313.11-2313.44" + wire width 8 \builder_interface8_bank_bus_dat_r + attribute \src "ls180.v:2312.12-2312.45" + wire width 8 \builder_interface8_bank_bus_dat_w + attribute \src "ls180.v:2311.6-2311.36" + wire \builder_interface8_bank_bus_we + attribute \src "ls180.v:2351.13-2351.44" + wire width 14 \builder_interface9_bank_bus_adr + attribute \src "ls180.v:2354.11-2354.44" + wire width 8 \builder_interface9_bank_bus_dat_r + attribute \src "ls180.v:2353.12-2353.45" + wire width 8 \builder_interface9_bank_bus_dat_w + attribute \src "ls180.v:2352.6-2352.36" + wire \builder_interface9_bank_bus_we + attribute \src "ls180.v:1828.12-1828.35" + wire width 14 \builder_libresocsim_adr + attribute \src "ls180.v:2544.12-2544.47" + wire width 14 \builder_libresocsim_adr_next_value1 + attribute \src "ls180.v:2545.5-2545.43" + wire \builder_libresocsim_adr_next_value_ce1 + attribute \src "ls180.v:1831.12-1831.37" + wire width 8 \builder_libresocsim_dat_r + attribute \src "ls180.v:1830.11-1830.36" + wire width 8 \builder_libresocsim_dat_w + attribute \src "ls180.v:2542.11-2542.48" + wire width 8 \builder_libresocsim_dat_w_next_value0 + attribute \src "ls180.v:2543.5-2543.45" + wire \builder_libresocsim_dat_w_next_value_ce0 + attribute \src "ls180.v:1829.5-1829.27" + wire \builder_libresocsim_we + attribute \src "ls180.v:2546.5-2546.39" + wire \builder_libresocsim_we_next_value2 + attribute \src "ls180.v:2547.5-2547.42" + wire \builder_libresocsim_we_next_value_ce2 + attribute \src "ls180.v:1838.5-1838.37" + wire \builder_libresocsim_wishbone_ack + attribute \src "ls180.v:1832.13-1832.45" + wire width 30 \builder_libresocsim_wishbone_adr + attribute \src "ls180.v:1841.12-1841.44" + wire width 2 \builder_libresocsim_wishbone_bte + attribute \src "ls180.v:1840.12-1840.44" + wire width 3 \builder_libresocsim_wishbone_cti + attribute \src "ls180.v:1836.6-1836.38" + wire \builder_libresocsim_wishbone_cyc + attribute \src "ls180.v:1834.12-1834.46" + wire width 32 \builder_libresocsim_wishbone_dat_r + attribute \src "ls180.v:1833.13-1833.47" + wire width 32 \builder_libresocsim_wishbone_dat_w + attribute \src "ls180.v:1842.5-1842.37" + wire \builder_libresocsim_wishbone_err + attribute \src "ls180.v:1835.12-1835.44" + wire width 4 \builder_libresocsim_wishbone_sel + attribute \src "ls180.v:1837.6-1837.38" + wire \builder_libresocsim_wishbone_stb + attribute \src "ls180.v:1839.6-1839.37" + wire \builder_libresocsim_wishbone_we + attribute \src "ls180.v:1731.5-1731.20" + wire \builder_locked0 + attribute \src "ls180.v:1732.5-1732.20" + wire \builder_locked1 + attribute \src "ls180.v:1733.5-1733.20" + wire \builder_locked2 + attribute \src "ls180.v:1734.5-1734.20" + wire \builder_locked3 + attribute \src "ls180.v:1718.11-1718.41" + wire width 3 \builder_multiplexer_next_state + attribute \src "ls180.v:1717.11-1717.36" + wire width 3 \builder_multiplexer_state + attribute \no_retiming "true" + attribute \src "ls180.v:2649.32-2649.59" + wire \builder_multiregimpl0_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2650.32-2650.59" + wire \builder_multiregimpl0_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2669.32-2669.60" + wire \builder_multiregimpl10_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2670.32-2670.60" + wire \builder_multiregimpl10_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2671.32-2671.60" + wire \builder_multiregimpl11_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2672.32-2672.60" + wire \builder_multiregimpl11_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2673.32-2673.60" + wire \builder_multiregimpl12_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2674.32-2674.60" + wire \builder_multiregimpl12_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2675.32-2675.60" + wire \builder_multiregimpl13_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2676.32-2676.60" + wire \builder_multiregimpl13_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2677.32-2677.60" + wire \builder_multiregimpl14_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2678.32-2678.60" + wire \builder_multiregimpl14_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2679.32-2679.60" + wire \builder_multiregimpl15_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2680.32-2680.60" + wire \builder_multiregimpl15_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2681.32-2681.60" + wire \builder_multiregimpl16_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2682.32-2682.60" + wire \builder_multiregimpl16_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2651.32-2651.59" + wire \builder_multiregimpl1_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2652.32-2652.59" + wire \builder_multiregimpl1_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2653.32-2653.59" + wire \builder_multiregimpl2_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2654.32-2654.59" + wire \builder_multiregimpl2_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2655.32-2655.59" + wire \builder_multiregimpl3_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2656.32-2656.59" + wire \builder_multiregimpl3_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2657.32-2657.59" + wire \builder_multiregimpl4_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2658.32-2658.59" + wire \builder_multiregimpl4_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2659.32-2659.59" + wire \builder_multiregimpl5_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2660.32-2660.59" + wire \builder_multiregimpl5_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2661.32-2661.59" + wire \builder_multiregimpl6_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2662.32-2662.59" + wire \builder_multiregimpl6_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2663.32-2663.59" + wire \builder_multiregimpl7_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2664.32-2664.59" + wire \builder_multiregimpl7_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2665.32-2665.59" + wire \builder_multiregimpl8_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2666.32-2666.59" + wire \builder_multiregimpl8_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2667.32-2667.59" + wire \builder_multiregimpl9_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2668.32-2668.59" + wire \builder_multiregimpl9_regs1 + attribute \src "ls180.v:1736.5-1736.36" + wire \builder_new_master_rdata_valid0 + attribute \src "ls180.v:1737.5-1737.36" + wire \builder_new_master_rdata_valid1 + attribute \src "ls180.v:1738.5-1738.36" + wire \builder_new_master_rdata_valid2 + attribute \src "ls180.v:1739.5-1739.36" + wire \builder_new_master_rdata_valid3 + attribute \src "ls180.v:1735.5-1735.35" + wire \builder_new_master_wdata_ready + attribute \src "ls180.v:2541.11-2541.29" + wire width 2 \builder_next_state + attribute \src "ls180.v:1708.11-1708.39" + wire width 2 \builder_refresher_next_state + attribute \src "ls180.v:1707.11-1707.34" + wire width 2 \builder_refresher_state + attribute \src "ls180.v:1854.12-1854.27" + wire width 5 \builder_request + attribute \src "ls180.v:1721.6-1721.28" + wire \builder_roundrobin0_ce + attribute \src "ls180.v:1720.6-1720.31" + wire \builder_roundrobin0_grant + attribute \src "ls180.v:1719.6-1719.33" + wire \builder_roundrobin0_request + attribute \src "ls180.v:1724.6-1724.28" + wire \builder_roundrobin1_ce + attribute \src "ls180.v:1723.6-1723.31" + wire \builder_roundrobin1_grant + attribute \src "ls180.v:1722.6-1722.33" + wire \builder_roundrobin1_request + attribute \src "ls180.v:1727.6-1727.28" + wire \builder_roundrobin2_ce + attribute \src "ls180.v:1726.6-1726.31" + wire \builder_roundrobin2_grant + attribute \src "ls180.v:1725.6-1725.33" + wire \builder_roundrobin2_request + attribute \src "ls180.v:1730.6-1730.28" + wire \builder_roundrobin3_ce + attribute \src "ls180.v:1729.6-1729.31" + wire \builder_roundrobin3_grant + attribute \src "ls180.v:1728.6-1728.33" + wire \builder_roundrobin3_request + attribute \src "ls180.v:1813.11-1813.44" + wire width 2 \builder_sdblock2memdma_next_state + attribute \src "ls180.v:1812.11-1812.39" + wire width 2 \builder_sdblock2memdma_state + attribute \src "ls180.v:1781.5-1781.50" + wire \builder_sdcore_crcupstreaminserter_next_state + attribute \src "ls180.v:1780.5-1780.45" + wire \builder_sdcore_crcupstreaminserter_state + attribute \src "ls180.v:1793.11-1793.40" + wire width 3 \builder_sdcore_fsm_next_state + attribute \src "ls180.v:1792.11-1792.35" + wire width 3 \builder_sdcore_fsm_state + attribute \src "ls180.v:1817.5-1817.42" + wire \builder_sdmem2blockdma_fsm_next_state + attribute \src "ls180.v:1816.5-1816.37" + wire \builder_sdmem2blockdma_fsm_state + attribute \src "ls180.v:1821.11-1821.58" + wire width 2 \builder_sdmem2blockdma_resetinserter_next_state + attribute \src "ls180.v:1820.11-1820.53" + wire width 2 \builder_sdmem2blockdma_resetinserter_state + attribute \src "ls180.v:1769.11-1769.39" + wire width 3 \builder_sdphy_fsm_next_state + attribute \src "ls180.v:1768.11-1768.34" + wire width 3 \builder_sdphy_fsm_state + attribute \src "ls180.v:1757.11-1757.45" + wire width 3 \builder_sdphy_sdphycmdr_next_state + attribute \src "ls180.v:1756.11-1756.40" + wire width 3 \builder_sdphy_sdphycmdr_state + attribute \src "ls180.v:1753.11-1753.45" + wire width 2 \builder_sdphy_sdphycmdw_next_state + attribute \src "ls180.v:1752.11-1752.40" + wire width 2 \builder_sdphy_sdphycmdw_state + attribute \src "ls180.v:1765.5-1765.39" + wire \builder_sdphy_sdphycrcr_next_state + attribute \src "ls180.v:1764.5-1764.34" + wire \builder_sdphy_sdphycrcr_state + attribute \src "ls180.v:1773.11-1773.46" + wire width 3 \builder_sdphy_sdphydatar_next_state + attribute \src "ls180.v:1772.11-1772.41" + wire width 3 \builder_sdphy_sdphydatar_state + attribute \src "ls180.v:1749.5-1749.39" + wire \builder_sdphy_sdphyinit_next_state + attribute \src "ls180.v:1748.5-1748.34" + wire \builder_sdphy_sdphyinit_state + attribute \src "ls180.v:1849.5-1849.23" + wire \builder_shared_ack + attribute \src "ls180.v:1843.13-1843.31" + wire width 30 \builder_shared_adr + attribute \src "ls180.v:1852.12-1852.30" + wire width 2 \builder_shared_bte + attribute \src "ls180.v:1851.12-1851.30" + wire width 3 \builder_shared_cti + attribute \src "ls180.v:1847.6-1847.24" + wire \builder_shared_cyc + attribute \src "ls180.v:1845.12-1845.32" + wire width 32 \builder_shared_dat_r + attribute \src "ls180.v:1844.13-1844.33" + wire width 32 \builder_shared_dat_w + attribute \src "ls180.v:1853.6-1853.24" + wire \builder_shared_err + attribute \src "ls180.v:1846.12-1846.30" + wire width 4 \builder_shared_sel + attribute \src "ls180.v:1848.6-1848.24" + wire \builder_shared_stb + attribute \src "ls180.v:1850.6-1850.23" + wire \builder_shared_we + attribute \src "ls180.v:1856.11-1856.28" + wire width 5 \builder_slave_sel + attribute \src "ls180.v:1857.11-1857.30" + wire width 5 \builder_slave_sel_r + attribute \src "ls180.v:1745.11-1745.40" + wire width 2 \builder_spimaster0_next_state + attribute \src "ls180.v:1744.11-1744.35" + wire width 2 \builder_spimaster0_state + attribute \src "ls180.v:1825.11-1825.40" + wire width 2 \builder_spimaster1_next_state + attribute \src "ls180.v:1824.11-1824.35" + wire width 2 \builder_spimaster1_state + attribute \src "ls180.v:2540.11-2540.24" + wire width 2 \builder_state + attribute \src "ls180.v:2593.5-2593.32" + wire \builder_sync_f_array_muxed0 + attribute \src "ls180.v:2594.5-2594.32" + wire \builder_sync_f_array_muxed1 + attribute \src "ls180.v:2586.11-2586.40" + wire width 2 \builder_sync_rhs_array_muxed0 + attribute \src "ls180.v:2587.12-2587.41" + wire width 13 \builder_sync_rhs_array_muxed1 + attribute \src "ls180.v:2588.5-2588.34" + wire \builder_sync_rhs_array_muxed2 + attribute \src "ls180.v:2589.5-2589.34" + wire \builder_sync_rhs_array_muxed3 + attribute \src "ls180.v:2590.5-2590.34" + wire \builder_sync_rhs_array_muxed4 + attribute \src "ls180.v:2591.5-2591.34" + wire \builder_sync_rhs_array_muxed5 + attribute \src "ls180.v:2592.5-2592.34" + wire \builder_sync_rhs_array_muxed6 + attribute \src "ls180.v:1859.6-1859.18" + wire \builder_wait + attribute \src "ls180.v:28.19-28.23" + wire width 3 input 24 \eint + attribute \src "ls180.v:21.20-21.26" + wire width 16 input 17 \gpio_i + attribute \src "ls180.v:22.21-22.27" + wire width 16 output 18 \gpio_o + attribute \src "ls180.v:23.21-23.28" + wire width 16 output 19 \gpio_oe + attribute \src "ls180.v:30.13-30.21" + wire input 26 \jtag_tck + attribute \src "ls180.v:31.13-31.21" + wire input 27 \jtag_tdi + attribute \src "ls180.v:32.14-32.22" + wire output 28 \jtag_tdo + attribute \src "ls180.v:29.13-29.21" + wire input 25 \jtag_tms + attribute \src "ls180.v:1665.13-1665.37" + wire width 16 \libresocsim_clk_divider0 + attribute \src "ls180.v:1687.12-1687.36" + wire width 16 \libresocsim_clk_divider1 + attribute \src "ls180.v:1682.5-1682.27" + wire \libresocsim_clk_enable + attribute \src "ls180.v:1689.6-1689.26" + wire \libresocsim_clk_fall + attribute \src "ls180.v:1688.6-1688.26" + wire \libresocsim_clk_rise + attribute \src "ls180.v:1669.5-1669.27" + wire \libresocsim_control_re + attribute \src "ls180.v:1668.12-1668.39" + wire width 16 \libresocsim_control_storage + attribute \src "ls180.v:1684.11-1684.28" + wire width 3 \libresocsim_count + attribute \src "ls180.v:1826.11-1826.50" + wire width 3 \libresocsim_count_spimaster1_next_value + attribute \src "ls180.v:1827.5-1827.47" + wire \libresocsim_count_spimaster1_next_value_ce + attribute \src "ls180.v:1663.6-1663.20" + wire \libresocsim_cs + attribute \src "ls180.v:1683.5-1683.26" + wire \libresocsim_cs_enable + attribute \src "ls180.v:1679.5-1679.22" + wire \libresocsim_cs_re + attribute \src "ls180.v:1678.5-1678.27" + wire \libresocsim_cs_storage + attribute \src "ls180.v:1659.5-1659.22" + wire \libresocsim_done0 + attribute \src "ls180.v:1670.6-1670.23" + wire \libresocsim_done1 + attribute \src "ls180.v:1660.5-1660.20" + wire \libresocsim_irq + attribute \src "ls180.v:1658.12-1658.31" + wire width 8 \libresocsim_length0 + attribute \src "ls180.v:1667.12-1667.31" + wire width 8 \libresocsim_length1 + attribute \src "ls180.v:1664.6-1664.26" + wire \libresocsim_loopback + attribute \src "ls180.v:1681.5-1681.28" + wire \libresocsim_loopback_re + attribute \src "ls180.v:1680.5-1680.33" + wire \libresocsim_loopback_storage + attribute \src "ls180.v:1662.11-1662.27" + wire width 8 \libresocsim_miso + attribute \src "ls180.v:1692.11-1692.32" + wire width 8 \libresocsim_miso_data + attribute \src "ls180.v:1686.5-1686.27" + wire \libresocsim_miso_latch + attribute \src "ls180.v:1675.12-1675.35" + wire width 8 \libresocsim_miso_status + attribute \src "ls180.v:1676.6-1676.25" + wire \libresocsim_miso_we + attribute \src "ls180.v:1661.12-1661.28" + wire width 8 \libresocsim_mosi + attribute \src "ls180.v:1690.11-1690.32" + wire width 8 \libresocsim_mosi_data + attribute \src "ls180.v:1685.5-1685.27" + wire \libresocsim_mosi_latch + attribute \src "ls180.v:1674.5-1674.24" + wire \libresocsim_mosi_re + attribute \src "ls180.v:1691.11-1691.31" + wire width 3 \libresocsim_mosi_sel + attribute \src "ls180.v:1673.11-1673.35" + wire width 8 \libresocsim_mosi_storage + attribute \src "ls180.v:1694.5-1694.19" + wire \libresocsim_re + attribute \src "ls180.v:1677.6-1677.21" + wire \libresocsim_sel + attribute \src "ls180.v:1657.6-1657.24" + wire \libresocsim_start0 + attribute \src "ls180.v:1666.5-1666.23" + wire \libresocsim_start1 + attribute \src "ls180.v:1671.6-1671.31" + wire \libresocsim_status_status + attribute \src "ls180.v:1672.6-1672.27" + wire \libresocsim_status_we + attribute \src "ls180.v:1693.12-1693.31" + wire width 16 \libresocsim_storage + attribute \src "ls180.v:807.6-807.18" + wire \main_ack_cmd + attribute \src "ls180.v:809.6-809.20" + wire \main_ack_rdata + attribute \src "ls180.v:808.6-808.20" + wire \main_ack_wdata + attribute \src "ls180.v:805.5-805.22" + wire \main_cmd_consumed + attribute \src "ls180.v:802.5-802.27" + wire \main_converter_counter + attribute \src "ls180.v:1742.5-1742.48" + wire \main_converter_counter_converter_next_value + attribute \src "ls180.v:1743.5-1743.51" + wire \main_converter_counter_converter_next_value_ce + attribute \src "ls180.v:804.12-804.32" + wire width 32 \main_converter_dat_r + attribute \src "ls180.v:803.6-803.26" + wire \main_converter_reset + attribute \src "ls180.v:801.5-801.24" + wire \main_converter_skip + attribute \src "ls180.v:230.6-230.23" + wire \main_dfi_p0_act_n + attribute \src "ls180.v:221.13-221.32" + wire width 13 \main_dfi_p0_address + attribute \src "ls180.v:222.12-222.28" + wire width 2 \main_dfi_p0_bank + attribute \src "ls180.v:223.6-223.23" + wire \main_dfi_p0_cas_n + attribute \src "ls180.v:227.6-227.21" + wire \main_dfi_p0_cke + attribute \src "ls180.v:224.6-224.22" + wire \main_dfi_p0_cs_n + attribute \src "ls180.v:228.6-228.21" + wire \main_dfi_p0_odt + attribute \src "ls180.v:225.6-225.23" + wire \main_dfi_p0_ras_n + attribute \src "ls180.v:235.12-235.30" + wire width 16 \main_dfi_p0_rddata + attribute \src "ls180.v:234.6-234.27" + wire \main_dfi_p0_rddata_en + attribute \src "ls180.v:236.5-236.29" + wire \main_dfi_p0_rddata_valid + attribute \src "ls180.v:229.6-229.25" + wire \main_dfi_p0_reset_n + attribute \src "ls180.v:226.6-226.22" + wire \main_dfi_p0_we_n + attribute \src "ls180.v:231.13-231.31" + wire width 16 \main_dfi_p0_wrdata + attribute \src "ls180.v:232.6-232.27" + wire \main_dfi_p0_wrdata_en + attribute \src "ls180.v:233.12-233.35" + wire width 2 \main_dfi_p0_wrdata_mask + attribute \src "ls180.v:237.11-237.18" + wire width 2 \main_dm + attribute \src "ls180.v:998.12-998.22" + wire width 43 \main_dummy + attribute \src "ls180.v:953.5-953.20" + wire \main_gpio_oe_re + attribute \src "ls180.v:952.12-952.32" + wire width 16 \main_gpio_oe_storage + attribute \src "ls180.v:957.5-957.21" + wire \main_gpio_out_re + attribute \src "ls180.v:956.12-956.33" + wire width 16 \main_gpio_out_storage + attribute \src "ls180.v:958.13-958.29" + wire width 16 \main_gpio_pads_i + attribute \src "ls180.v:959.13-959.29" + wire width 16 \main_gpio_pads_o + attribute \src "ls180.v:960.13-960.30" + wire width 16 \main_gpio_pads_oe + attribute \src "ls180.v:954.12-954.28" + wire width 16 \main_gpio_status + attribute \src "ls180.v:955.6-955.18" + wire \main_gpio_we + attribute \src "ls180.v:220.5-220.17" + wire \main_int_rst + attribute \src "ls180.v:1478.6-1478.29" + wire \main_interface0_bus_ack + attribute \src "ls180.v:1472.13-1472.36" + wire width 32 \main_interface0_bus_adr + attribute \src "ls180.v:1481.11-1481.34" + wire width 2 \main_interface0_bus_bte + attribute \src "ls180.v:1480.11-1480.34" + wire width 3 \main_interface0_bus_cti + attribute \src "ls180.v:1476.6-1476.29" + wire \main_interface0_bus_cyc + attribute \src "ls180.v:1474.13-1474.38" + wire width 32 \main_interface0_bus_dat_r + attribute \src "ls180.v:1473.13-1473.38" + wire width 32 \main_interface0_bus_dat_w + attribute \src "ls180.v:1482.6-1482.29" + wire \main_interface0_bus_err + attribute \src "ls180.v:1475.12-1475.35" + wire width 4 \main_interface0_bus_sel + attribute \src "ls180.v:1477.6-1477.29" + wire \main_interface0_bus_stb + attribute \src "ls180.v:1479.6-1479.28" + wire \main_interface0_bus_we + attribute \src "ls180.v:1569.6-1569.29" + wire \main_interface1_bus_ack + attribute \src "ls180.v:1563.12-1563.35" + wire width 32 \main_interface1_bus_adr + attribute \src "ls180.v:1572.11-1572.34" + wire width 2 \main_interface1_bus_bte + attribute \src "ls180.v:1571.11-1571.34" + wire width 3 \main_interface1_bus_cti + attribute \src "ls180.v:1567.5-1567.28" + wire \main_interface1_bus_cyc + attribute \src "ls180.v:1565.13-1565.38" + wire width 32 \main_interface1_bus_dat_r + attribute \src "ls180.v:1564.12-1564.37" + wire width 32 \main_interface1_bus_dat_w + attribute \src "ls180.v:1573.6-1573.29" + wire \main_interface1_bus_err + attribute \src "ls180.v:1566.11-1566.34" + wire width 4 \main_interface1_bus_sel + attribute \src "ls180.v:1568.5-1568.28" + wire \main_interface1_bus_stb + attribute \src "ls180.v:1570.5-1570.27" + wire \main_interface1_bus_we + attribute \src "ls180.v:186.12-186.32" + wire width 7 \main_libresocsim_adr + attribute \src "ls180.v:56.6-56.32" + wire \main_libresocsim_bus_error + attribute \src "ls180.v:57.12-57.39" + wire width 32 \main_libresocsim_bus_errors + attribute \src "ls180.v:53.13-53.47" + wire width 32 \main_libresocsim_bus_errors_status + attribute \src "ls180.v:54.6-54.36" + wire \main_libresocsim_bus_errors_we + attribute \src "ls180.v:142.5-142.40" + wire \main_libresocsim_converter0_counter + attribute \src "ls180.v:1697.5-1697.62" + wire \main_libresocsim_converter0_counter_converter0_next_value + attribute \src "ls180.v:1698.5-1698.65" + wire \main_libresocsim_converter0_counter_converter0_next_value_ce + attribute \src "ls180.v:144.12-144.45" + wire width 64 \main_libresocsim_converter0_dat_r + attribute \src "ls180.v:143.6-143.39" + wire \main_libresocsim_converter0_reset + attribute \src "ls180.v:141.5-141.37" + wire \main_libresocsim_converter0_skip + attribute \src "ls180.v:157.5-157.40" + wire \main_libresocsim_converter1_counter + attribute \src "ls180.v:1701.5-1701.62" + wire \main_libresocsim_converter1_counter_converter1_next_value + attribute \src "ls180.v:1702.5-1702.65" + wire \main_libresocsim_converter1_counter_converter1_next_value_ce + attribute \src "ls180.v:159.12-159.45" + wire width 64 \main_libresocsim_converter1_dat_r + attribute \src "ls180.v:158.6-158.39" + wire \main_libresocsim_converter1_reset + attribute \src "ls180.v:156.5-156.37" + wire \main_libresocsim_converter1_skip + attribute \src "ls180.v:172.5-172.40" + wire \main_libresocsim_converter2_counter + attribute \src "ls180.v:1705.5-1705.62" + wire \main_libresocsim_converter2_counter_converter2_next_value + attribute \src "ls180.v:1706.5-1706.65" + wire \main_libresocsim_converter2_counter_converter2_next_value_ce + attribute \src "ls180.v:174.12-174.45" + wire width 64 \main_libresocsim_converter2_dat_r + attribute \src "ls180.v:173.6-173.39" + wire \main_libresocsim_converter2_reset + attribute \src "ls180.v:171.5-171.37" + wire \main_libresocsim_converter2_skip + attribute \src "ls180.v:187.13-187.35" + wire width 32 \main_libresocsim_dat_r + attribute \src "ls180.v:189.13-189.35" + wire width 32 \main_libresocsim_dat_w + attribute \src "ls180.v:195.5-195.27" + wire \main_libresocsim_en_re + attribute \src "ls180.v:194.5-194.32" + wire \main_libresocsim_en_storage + attribute \src "ls180.v:211.6-211.45" + wire \main_libresocsim_eventmanager_pending_r + attribute \src "ls180.v:210.6-210.46" + wire \main_libresocsim_eventmanager_pending_re + attribute \src "ls180.v:213.6-213.45" + wire \main_libresocsim_eventmanager_pending_w + attribute \src "ls180.v:212.6-212.46" + wire \main_libresocsim_eventmanager_pending_we + attribute \src "ls180.v:215.5-215.37" + wire \main_libresocsim_eventmanager_re + attribute \src "ls180.v:207.6-207.44" + wire \main_libresocsim_eventmanager_status_r + attribute \src "ls180.v:206.6-206.45" + wire \main_libresocsim_eventmanager_status_re + attribute \src "ls180.v:209.6-209.44" + wire \main_libresocsim_eventmanager_status_w + attribute \src "ls180.v:208.6-208.45" + wire \main_libresocsim_eventmanager_status_we + attribute \src "ls180.v:214.5-214.42" + wire \main_libresocsim_eventmanager_storage + attribute \src "ls180.v:136.6-136.57" + wire \main_libresocsim_interface0_converted_interface_ack + attribute \src "ls180.v:130.12-130.63" + wire width 30 \main_libresocsim_interface0_converted_interface_adr + attribute \src "ls180.v:139.11-139.62" + wire width 2 \main_libresocsim_interface0_converted_interface_bte + attribute \src "ls180.v:138.11-138.62" + wire width 3 \main_libresocsim_interface0_converted_interface_cti + attribute \src "ls180.v:134.5-134.56" + wire \main_libresocsim_interface0_converted_interface_cyc + attribute \src "ls180.v:132.13-132.66" + wire width 32 \main_libresocsim_interface0_converted_interface_dat_r + attribute \src "ls180.v:131.12-131.65" + wire width 32 \main_libresocsim_interface0_converted_interface_dat_w + attribute \src "ls180.v:140.6-140.57" + wire \main_libresocsim_interface0_converted_interface_err + attribute \src "ls180.v:133.11-133.62" + wire width 4 \main_libresocsim_interface0_converted_interface_sel + attribute \src "ls180.v:135.5-135.56" + wire \main_libresocsim_interface0_converted_interface_stb + attribute \src "ls180.v:137.5-137.55" + wire \main_libresocsim_interface0_converted_interface_we + attribute \src "ls180.v:151.6-151.57" + wire \main_libresocsim_interface1_converted_interface_ack + attribute \src "ls180.v:145.12-145.63" + wire width 30 \main_libresocsim_interface1_converted_interface_adr + attribute \src "ls180.v:154.11-154.62" + wire width 2 \main_libresocsim_interface1_converted_interface_bte + attribute \src "ls180.v:153.11-153.62" + wire width 3 \main_libresocsim_interface1_converted_interface_cti + attribute \src "ls180.v:149.5-149.56" + wire \main_libresocsim_interface1_converted_interface_cyc + attribute \src "ls180.v:147.13-147.66" + wire width 32 \main_libresocsim_interface1_converted_interface_dat_r + attribute \src "ls180.v:146.12-146.65" + wire width 32 \main_libresocsim_interface1_converted_interface_dat_w + attribute \src "ls180.v:155.6-155.57" + wire \main_libresocsim_interface1_converted_interface_err + attribute \src "ls180.v:148.11-148.62" + wire width 4 \main_libresocsim_interface1_converted_interface_sel + attribute \src "ls180.v:150.5-150.56" + wire \main_libresocsim_interface1_converted_interface_stb + attribute \src "ls180.v:152.5-152.55" + wire \main_libresocsim_interface1_converted_interface_we + attribute \src "ls180.v:166.6-166.57" + wire \main_libresocsim_interface2_converted_interface_ack + attribute \src "ls180.v:160.12-160.63" + wire width 30 \main_libresocsim_interface2_converted_interface_adr + attribute \src "ls180.v:169.11-169.62" + wire width 2 \main_libresocsim_interface2_converted_interface_bte + attribute \src "ls180.v:168.11-168.62" + wire width 3 \main_libresocsim_interface2_converted_interface_cti + attribute \src "ls180.v:164.5-164.56" + wire \main_libresocsim_interface2_converted_interface_cyc + attribute \src "ls180.v:162.13-162.66" + wire width 32 \main_libresocsim_interface2_converted_interface_dat_r + attribute \src "ls180.v:161.12-161.65" + wire width 32 \main_libresocsim_interface2_converted_interface_dat_w + attribute \src "ls180.v:170.6-170.57" + wire \main_libresocsim_interface2_converted_interface_err + attribute \src "ls180.v:163.11-163.62" + wire width 4 \main_libresocsim_interface2_converted_interface_sel + attribute \src "ls180.v:165.5-165.56" + wire \main_libresocsim_interface2_converted_interface_stb + attribute \src "ls180.v:167.5-167.55" + wire \main_libresocsim_interface2_converted_interface_we + attribute \src "ls180.v:200.6-200.26" + wire \main_libresocsim_irq + attribute \src "ls180.v:117.6-117.32" + wire \main_libresocsim_libresoc0 + attribute \src "ls180.v:118.6-118.32" + wire \main_libresocsim_libresoc1 + attribute \src "ls180.v:119.13-119.39" + wire width 64 \main_libresocsim_libresoc2 + attribute \src "ls180.v:122.13-122.65" + wire width 16 \main_libresocsim_libresoc_constraintmanager0_gpio0_i + attribute \src "ls180.v:123.13-123.65" + wire width 16 \main_libresocsim_libresoc_constraintmanager0_gpio0_o + attribute \src "ls180.v:124.13-124.66" + wire width 16 \main_libresocsim_libresoc_constraintmanager0_gpio0_oe + attribute \src "ls180.v:121.6-121.59" + wire \main_libresocsim_libresoc_constraintmanager0_uart0_rx + attribute \src "ls180.v:120.5-120.58" + wire \main_libresocsim_libresoc_constraintmanager0_uart0_tx + attribute \src "ls180.v:127.13-127.65" + wire width 16 \main_libresocsim_libresoc_constraintmanager1_gpio0_i + attribute \src "ls180.v:128.13-128.65" + wire width 16 \main_libresocsim_libresoc_constraintmanager1_gpio0_o + attribute \src "ls180.v:129.13-129.66" + wire width 16 \main_libresocsim_libresoc_constraintmanager1_gpio0_oe + attribute \src "ls180.v:126.6-126.59" + wire \main_libresocsim_libresoc_constraintmanager1_uart0_rx + attribute \src "ls180.v:125.6-125.59" + wire \main_libresocsim_libresoc_constraintmanager1_uart0_tx + attribute \src "ls180.v:66.5-66.39" + wire \main_libresocsim_libresoc_dbus_ack + attribute \src "ls180.v:60.13-60.47" + wire width 29 \main_libresocsim_libresoc_dbus_adr + attribute \src "ls180.v:69.12-69.46" + wire width 2 \main_libresocsim_libresoc_dbus_bte + attribute \src "ls180.v:68.12-68.46" + wire width 3 \main_libresocsim_libresoc_dbus_cti + attribute \src "ls180.v:64.6-64.40" + wire \main_libresocsim_libresoc_dbus_cyc + attribute \src "ls180.v:62.13-62.49" + wire width 64 \main_libresocsim_libresoc_dbus_dat_r + attribute \src "ls180.v:61.13-61.49" + wire width 64 \main_libresocsim_libresoc_dbus_dat_w + attribute \src "ls180.v:70.5-70.39" + wire \main_libresocsim_libresoc_dbus_err + attribute \src "ls180.v:63.12-63.46" + wire width 8 \main_libresocsim_libresoc_dbus_sel + attribute \src "ls180.v:65.6-65.40" + wire \main_libresocsim_libresoc_dbus_stb + attribute \src "ls180.v:67.6-67.39" + wire \main_libresocsim_libresoc_dbus_we + attribute \src "ls180.v:77.5-77.39" + wire \main_libresocsim_libresoc_ibus_ack + attribute \src "ls180.v:71.13-71.47" + wire width 29 \main_libresocsim_libresoc_ibus_adr + attribute \src "ls180.v:80.12-80.46" + wire width 2 \main_libresocsim_libresoc_ibus_bte + attribute \src "ls180.v:79.12-79.46" + wire width 3 \main_libresocsim_libresoc_ibus_cti + attribute \src "ls180.v:75.6-75.40" + wire \main_libresocsim_libresoc_ibus_cyc + attribute \src "ls180.v:73.13-73.49" + wire width 64 \main_libresocsim_libresoc_ibus_dat_r + attribute \src "ls180.v:72.13-72.49" + wire width 64 \main_libresocsim_libresoc_ibus_dat_w + attribute \src "ls180.v:81.5-81.39" + wire \main_libresocsim_libresoc_ibus_err + attribute \src "ls180.v:74.12-74.46" + wire width 8 \main_libresocsim_libresoc_ibus_sel + attribute \src "ls180.v:76.6-76.40" + wire \main_libresocsim_libresoc_ibus_stb + attribute \src "ls180.v:78.6-78.39" + wire \main_libresocsim_libresoc_ibus_we + attribute \src "ls180.v:59.12-59.47" + wire width 16 \main_libresocsim_libresoc_interrupt + attribute \src "ls180.v:113.6-113.40" + wire \main_libresocsim_libresoc_jtag_tck + attribute \src "ls180.v:115.6-115.40" + wire \main_libresocsim_libresoc_jtag_tdi + attribute \src "ls180.v:116.6-116.40" + wire \main_libresocsim_libresoc_jtag_tdo + attribute \src "ls180.v:114.6-114.40" + wire \main_libresocsim_libresoc_jtag_tms + attribute \src "ls180.v:110.5-110.42" + wire \main_libresocsim_libresoc_jtag_wb_ack + attribute \src "ls180.v:104.13-104.50" + wire width 29 \main_libresocsim_libresoc_jtag_wb_adr + attribute \src "ls180.v:108.6-108.43" + wire \main_libresocsim_libresoc_jtag_wb_cyc + attribute \src "ls180.v:106.13-106.52" + wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_r + attribute \src "ls180.v:105.13-105.52" + wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_w + attribute \src "ls180.v:112.5-112.42" + wire \main_libresocsim_libresoc_jtag_wb_err + attribute \src "ls180.v:107.12-107.49" + wire width 8 \main_libresocsim_libresoc_jtag_wb_sel + attribute \src "ls180.v:109.6-109.43" + wire \main_libresocsim_libresoc_jtag_wb_stb + attribute \src "ls180.v:111.6-111.42" + wire \main_libresocsim_libresoc_jtag_wb_we + attribute \src "ls180.v:58.6-58.37" + wire \main_libresocsim_libresoc_reset + attribute \src "ls180.v:88.6-88.44" + wire \main_libresocsim_libresoc_xics_icp_ack + attribute \src "ls180.v:82.13-82.51" + wire width 30 \main_libresocsim_libresoc_xics_icp_adr + attribute \src "ls180.v:91.12-91.50" + wire width 2 \main_libresocsim_libresoc_xics_icp_bte + attribute \src "ls180.v:90.12-90.50" + wire width 3 \main_libresocsim_libresoc_xics_icp_cti + attribute \src "ls180.v:86.6-86.44" + wire \main_libresocsim_libresoc_xics_icp_cyc + attribute \src "ls180.v:84.13-84.53" + wire width 32 \main_libresocsim_libresoc_xics_icp_dat_r + attribute \src "ls180.v:83.13-83.53" + wire width 32 \main_libresocsim_libresoc_xics_icp_dat_w + attribute \src "ls180.v:92.6-92.44" + wire \main_libresocsim_libresoc_xics_icp_err + attribute \src "ls180.v:85.12-85.50" + wire width 4 \main_libresocsim_libresoc_xics_icp_sel + attribute \src "ls180.v:87.6-87.44" + wire \main_libresocsim_libresoc_xics_icp_stb + attribute \src "ls180.v:89.6-89.43" + wire \main_libresocsim_libresoc_xics_icp_we + attribute \src "ls180.v:99.6-99.44" + wire \main_libresocsim_libresoc_xics_ics_ack + attribute \src "ls180.v:93.13-93.51" + wire width 30 \main_libresocsim_libresoc_xics_ics_adr + attribute \src "ls180.v:102.12-102.50" + wire width 2 \main_libresocsim_libresoc_xics_ics_bte + attribute \src "ls180.v:101.12-101.50" + wire width 3 \main_libresocsim_libresoc_xics_ics_cti + attribute \src "ls180.v:97.6-97.44" + wire \main_libresocsim_libresoc_xics_ics_cyc + attribute \src "ls180.v:95.13-95.53" + wire width 32 \main_libresocsim_libresoc_xics_ics_dat_r + attribute \src "ls180.v:94.13-94.53" + wire width 32 \main_libresocsim_libresoc_xics_ics_dat_w + attribute \src "ls180.v:103.6-103.44" + wire \main_libresocsim_libresoc_xics_ics_err + attribute \src "ls180.v:96.12-96.50" + wire width 4 \main_libresocsim_libresoc_xics_ics_sel + attribute \src "ls180.v:98.6-98.44" + wire \main_libresocsim_libresoc_xics_ics_stb + attribute \src "ls180.v:100.6-100.43" + wire \main_libresocsim_libresoc_xics_ics_we + attribute \src "ls180.v:191.5-191.29" + wire \main_libresocsim_load_re + attribute \src "ls180.v:190.12-190.41" + wire width 32 \main_libresocsim_load_storage + attribute \src "ls180.v:181.5-181.33" + wire \main_libresocsim_ram_bus_ack + attribute \src "ls180.v:175.13-175.41" + wire width 30 \main_libresocsim_ram_bus_adr + attribute \src "ls180.v:184.12-184.40" + wire width 2 \main_libresocsim_ram_bus_bte + attribute \src "ls180.v:183.12-183.40" + wire width 3 \main_libresocsim_ram_bus_cti + attribute \src "ls180.v:179.6-179.34" + wire \main_libresocsim_ram_bus_cyc + attribute \src "ls180.v:177.13-177.43" + wire width 32 \main_libresocsim_ram_bus_dat_r + attribute \src "ls180.v:176.13-176.43" + wire width 32 \main_libresocsim_ram_bus_dat_w + attribute \src "ls180.v:185.5-185.33" + wire \main_libresocsim_ram_bus_err + attribute \src "ls180.v:178.12-178.40" + wire width 4 \main_libresocsim_ram_bus_sel + attribute \src "ls180.v:180.6-180.34" + wire \main_libresocsim_ram_bus_stb + attribute \src "ls180.v:182.6-182.33" + wire \main_libresocsim_ram_bus_we + attribute \src "ls180.v:193.5-193.31" + wire \main_libresocsim_reload_re + attribute \src "ls180.v:192.12-192.43" + wire width 32 \main_libresocsim_reload_storage + attribute \src "ls180.v:55.6-55.28" + wire \main_libresocsim_reset + attribute \src "ls180.v:50.5-50.30" + wire \main_libresocsim_reset_re + attribute \src "ls180.v:49.5-49.35" + wire \main_libresocsim_reset_storage + attribute \src "ls180.v:52.5-52.32" + wire \main_libresocsim_scratch_re + attribute \src "ls180.v:51.12-51.44" + wire width 32 \main_libresocsim_scratch_storage + attribute \src "ls180.v:197.5-197.37" + wire \main_libresocsim_update_value_re + attribute \src "ls180.v:196.5-196.42" + wire \main_libresocsim_update_value_storage + attribute \src "ls180.v:216.12-216.34" + wire width 32 \main_libresocsim_value + attribute \src "ls180.v:198.12-198.41" + wire width 32 \main_libresocsim_value_status + attribute \src "ls180.v:199.6-199.31" + wire \main_libresocsim_value_we + attribute \src "ls180.v:188.11-188.30" + wire width 4 \main_libresocsim_we + attribute \src "ls180.v:204.5-204.32" + wire \main_libresocsim_zero_clear + attribute \src "ls180.v:205.5-205.38" + wire \main_libresocsim_zero_old_trigger + attribute \src "ls180.v:202.5-202.34" + wire \main_libresocsim_zero_pending + attribute \src "ls180.v:201.6-201.34" + wire \main_libresocsim_zero_status + attribute \src "ls180.v:203.6-203.35" + wire \main_libresocsim_zero_trigger + attribute \src "ls180.v:799.6-799.26" + wire \main_litedram_wb_ack + attribute \src "ls180.v:793.12-793.32" + wire width 30 \main_litedram_wb_adr + attribute \src "ls180.v:797.5-797.25" + wire \main_litedram_wb_cyc + attribute \src "ls180.v:795.13-795.35" + wire width 16 \main_litedram_wb_dat_r + attribute \src "ls180.v:794.12-794.34" + wire width 16 \main_litedram_wb_dat_w + attribute \src "ls180.v:796.11-796.31" + wire width 2 \main_litedram_wb_sel + attribute \src "ls180.v:798.5-798.25" + wire \main_litedram_wb_stb + attribute \src "ls180.v:800.5-800.24" + wire \main_litedram_wb_we + attribute \src "ls180.v:997.13-997.20" + wire width 43 \main_nc + attribute \src "ls180.v:828.12-828.37" + wire width 32 \main_phase_accumulator_rx + attribute \src "ls180.v:818.12-818.37" + wire width 32 \main_phase_accumulator_tx + attribute \src "ls180.v:772.6-772.24" + wire \main_port_cmd_last + attribute \src "ls180.v:774.13-774.39" + wire width 24 \main_port_cmd_payload_addr + attribute \src "ls180.v:773.6-773.30" + wire \main_port_cmd_payload_we + attribute \src "ls180.v:771.6-771.25" + wire \main_port_cmd_ready + attribute \src "ls180.v:770.6-770.25" + wire \main_port_cmd_valid + attribute \src "ls180.v:769.6-769.21" + wire \main_port_flush + attribute \src "ls180.v:781.13-781.41" + wire width 16 \main_port_rdata_payload_data + attribute \src "ls180.v:780.6-780.27" + wire \main_port_rdata_ready + attribute \src "ls180.v:779.6-779.27" + wire \main_port_rdata_valid + attribute \src "ls180.v:777.13-777.41" + wire width 16 \main_port_wdata_payload_data + attribute \src "ls180.v:778.12-778.38" + wire width 2 \main_port_wdata_payload_we + attribute \src "ls180.v:776.6-776.27" + wire \main_port_wdata_ready + attribute \src "ls180.v:775.6-775.27" + wire \main_port_wdata_valid + attribute \src "ls180.v:1002.12-1002.29" + wire width 32 \main_pwm0_counter + attribute \src "ls180.v:999.6-999.22" + wire \main_pwm0_enable + attribute \src "ls180.v:1004.5-1004.24" + wire \main_pwm0_enable_re + attribute \src "ls180.v:1003.5-1003.29" + wire \main_pwm0_enable_storage + attribute \src "ls180.v:1001.13-1001.29" + wire width 32 \main_pwm0_period + attribute \src "ls180.v:1008.5-1008.24" + wire \main_pwm0_period_re + attribute \src "ls180.v:1007.12-1007.36" + wire width 32 \main_pwm0_period_storage + attribute \src "ls180.v:1000.13-1000.28" + wire width 32 \main_pwm0_width + attribute \src "ls180.v:1006.5-1006.23" + wire \main_pwm0_width_re + attribute \src "ls180.v:1005.12-1005.35" + wire width 32 \main_pwm0_width_storage + attribute \src "ls180.v:1012.12-1012.29" + wire width 32 \main_pwm1_counter + attribute \src "ls180.v:1009.6-1009.22" + wire \main_pwm1_enable + attribute \src "ls180.v:1014.5-1014.24" + wire \main_pwm1_enable_re + attribute \src "ls180.v:1013.5-1013.29" + wire \main_pwm1_enable_storage + attribute \src "ls180.v:1011.13-1011.29" + wire width 32 \main_pwm1_period + attribute \src "ls180.v:1018.5-1018.24" + wire \main_pwm1_period_re + attribute \src "ls180.v:1017.12-1017.36" + wire width 32 \main_pwm1_period_storage + attribute \src "ls180.v:1010.13-1010.28" + wire width 32 \main_pwm1_width + attribute \src "ls180.v:1016.5-1016.23" + wire \main_pwm1_width_re + attribute \src "ls180.v:1015.12-1015.35" + wire width 32 \main_pwm1_width_storage + attribute \src "ls180.v:238.11-238.25" + wire width 3 \main_rddata_en + attribute \src "ls180.v:811.5-811.12" + wire \main_re + attribute \src "ls180.v:829.6-829.13" + wire \main_rx + attribute \src "ls180.v:832.11-832.27" + wire width 4 \main_rx_bitcount + attribute \src "ls180.v:833.5-833.17" + wire \main_rx_busy + attribute \src "ls180.v:830.5-830.14" + wire \main_rx_r + attribute \src "ls180.v:831.11-831.22" + wire width 8 \main_rx_reg + attribute \src "ls180.v:1532.11-1532.43" + wire width 2 \main_sdblock2mem_converter_demux + attribute \src "ls180.v:1533.6-1533.42" + wire \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:1523.6-1523.43" + wire \main_sdblock2mem_converter_sink_first + attribute \src "ls180.v:1524.6-1524.42" + wire \main_sdblock2mem_converter_sink_last + attribute \src "ls180.v:1525.12-1525.56" + wire width 8 \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:1522.6-1522.43" + wire \main_sdblock2mem_converter_sink_ready + attribute \src "ls180.v:1521.6-1521.43" + wire \main_sdblock2mem_converter_sink_valid + attribute \src "ls180.v:1528.5-1528.44" + wire \main_sdblock2mem_converter_source_first + attribute \src "ls180.v:1529.5-1529.43" + wire \main_sdblock2mem_converter_source_last + attribute \src "ls180.v:1530.12-1530.58" + wire width 32 \main_sdblock2mem_converter_source_payload_data + attribute \src "ls180.v:1531.11-1531.70" + wire width 3 \main_sdblock2mem_converter_source_payload_valid_token_count + attribute \src "ls180.v:1527.6-1527.45" + wire \main_sdblock2mem_converter_source_ready + attribute \src "ls180.v:1526.6-1526.45" + wire \main_sdblock2mem_converter_source_valid + attribute \src "ls180.v:1534.5-1534.42" + wire \main_sdblock2mem_converter_strobe_all + attribute \src "ls180.v:1507.11-1507.40" + wire width 5 \main_sdblock2mem_fifo_consume + attribute \src "ls180.v:1512.6-1512.35" + wire \main_sdblock2mem_fifo_do_read + attribute \src "ls180.v:1516.6-1516.41" + wire \main_sdblock2mem_fifo_fifo_in_first + attribute \src "ls180.v:1517.6-1517.40" + wire \main_sdblock2mem_fifo_fifo_in_last + attribute \src "ls180.v:1515.12-1515.54" + wire width 8 \main_sdblock2mem_fifo_fifo_in_payload_data + attribute \src "ls180.v:1519.6-1519.42" + wire \main_sdblock2mem_fifo_fifo_out_first + attribute \src "ls180.v:1520.6-1520.41" + wire \main_sdblock2mem_fifo_fifo_out_last + attribute \src "ls180.v:1518.12-1518.55" + wire width 8 \main_sdblock2mem_fifo_fifo_out_payload_data + attribute \src "ls180.v:1504.11-1504.38" + wire width 6 \main_sdblock2mem_fifo_level + attribute \src "ls180.v:1506.11-1506.40" + wire width 5 \main_sdblock2mem_fifo_produce + attribute \src "ls180.v:1513.12-1513.44" + wire width 5 \main_sdblock2mem_fifo_rdport_adr + attribute \src "ls180.v:1514.12-1514.46" + wire width 10 \main_sdblock2mem_fifo_rdport_dat_r + attribute \src "ls180.v:1505.5-1505.34" + wire \main_sdblock2mem_fifo_replace + attribute \src "ls180.v:1490.6-1490.38" + wire \main_sdblock2mem_fifo_sink_first + attribute \src "ls180.v:1491.6-1491.37" + wire \main_sdblock2mem_fifo_sink_last + attribute \src "ls180.v:1492.12-1492.51" + wire width 8 \main_sdblock2mem_fifo_sink_payload_data + attribute \src "ls180.v:1489.6-1489.38" + wire \main_sdblock2mem_fifo_sink_ready + attribute \src "ls180.v:1488.6-1488.38" + wire \main_sdblock2mem_fifo_sink_valid + attribute \src "ls180.v:1495.6-1495.40" + wire \main_sdblock2mem_fifo_source_first + attribute \src "ls180.v:1496.6-1496.39" + wire \main_sdblock2mem_fifo_source_last + attribute \src "ls180.v:1497.12-1497.53" + wire width 8 \main_sdblock2mem_fifo_source_payload_data + attribute \src "ls180.v:1494.6-1494.40" + wire \main_sdblock2mem_fifo_source_ready + attribute \src "ls180.v:1493.6-1493.40" + wire \main_sdblock2mem_fifo_source_valid + attribute \src "ls180.v:1502.12-1502.46" + wire width 10 \main_sdblock2mem_fifo_syncfifo_din + attribute \src "ls180.v:1503.12-1503.47" + wire width 10 \main_sdblock2mem_fifo_syncfifo_dout + attribute \src "ls180.v:1500.6-1500.39" + wire \main_sdblock2mem_fifo_syncfifo_re + attribute \src "ls180.v:1501.6-1501.45" + wire \main_sdblock2mem_fifo_syncfifo_readable + attribute \src "ls180.v:1498.6-1498.39" + wire \main_sdblock2mem_fifo_syncfifo_we + attribute \src "ls180.v:1499.6-1499.45" + wire \main_sdblock2mem_fifo_syncfifo_writable + attribute \src "ls180.v:1508.11-1508.43" + wire width 5 \main_sdblock2mem_fifo_wrport_adr + attribute \src "ls180.v:1509.12-1509.46" + wire width 10 \main_sdblock2mem_fifo_wrport_dat_r + attribute \src "ls180.v:1511.12-1511.46" + wire width 10 \main_sdblock2mem_fifo_wrport_dat_w + attribute \src "ls180.v:1510.6-1510.37" + wire \main_sdblock2mem_fifo_wrport_we + attribute \src "ls180.v:1485.6-1485.38" + wire \main_sdblock2mem_sink_sink_first + attribute \src "ls180.v:1486.6-1486.37" + wire \main_sdblock2mem_sink_sink_last + attribute \src "ls180.v:1542.12-1542.54" + wire width 32 \main_sdblock2mem_sink_sink_payload_address + attribute \src "ls180.v:1487.12-1487.52" + wire width 8 \main_sdblock2mem_sink_sink_payload_data0 + attribute \src "ls180.v:1543.12-1543.52" + wire width 32 \main_sdblock2mem_sink_sink_payload_data1 + attribute \src "ls180.v:1484.6-1484.39" + wire \main_sdblock2mem_sink_sink_ready0 + attribute \src "ls180.v:1541.6-1541.39" + wire \main_sdblock2mem_sink_sink_ready1 + attribute \src "ls180.v:1483.6-1483.39" + wire \main_sdblock2mem_sink_sink_valid0 + attribute \src "ls180.v:1540.5-1540.38" + wire \main_sdblock2mem_sink_sink_valid1 + attribute \src "ls180.v:1537.6-1537.42" + wire \main_sdblock2mem_source_source_first + attribute \src "ls180.v:1538.6-1538.41" + wire \main_sdblock2mem_source_source_last + attribute \src "ls180.v:1539.13-1539.56" + wire width 32 \main_sdblock2mem_source_source_payload_data + attribute \src "ls180.v:1536.6-1536.42" + wire \main_sdblock2mem_source_source_ready + attribute \src "ls180.v:1535.6-1535.42" + wire \main_sdblock2mem_source_source_valid + attribute \src "ls180.v:1559.13-1559.52" + wire width 32 \main_sdblock2mem_wishbonedmawriter_base + attribute \src "ls180.v:1550.5-1550.47" + wire \main_sdblock2mem_wishbonedmawriter_base_re + attribute \src "ls180.v:1549.12-1549.59" + wire width 64 \main_sdblock2mem_wishbonedmawriter_base_storage + attribute \src "ls180.v:1554.5-1554.49" + wire \main_sdblock2mem_wishbonedmawriter_enable_re + attribute \src "ls180.v:1553.5-1553.54" + wire \main_sdblock2mem_wishbonedmawriter_enable_storage + attribute \src "ls180.v:1561.13-1561.54" + wire width 32 \main_sdblock2mem_wishbonedmawriter_length + attribute \src "ls180.v:1552.5-1552.49" + wire \main_sdblock2mem_wishbonedmawriter_length_re + attribute \src "ls180.v:1551.12-1551.61" + wire width 32 \main_sdblock2mem_wishbonedmawriter_length_storage + attribute \src "ls180.v:1558.5-1558.47" + wire \main_sdblock2mem_wishbonedmawriter_loop_re + attribute \src "ls180.v:1557.5-1557.52" + wire \main_sdblock2mem_wishbonedmawriter_loop_storage + attribute \src "ls180.v:1560.12-1560.53" + wire width 32 \main_sdblock2mem_wishbonedmawriter_offset + attribute \src "ls180.v:1814.12-1814.79" + wire width 32 \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value + attribute \src "ls180.v:1815.5-1815.75" + wire \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce + attribute \src "ls180.v:1562.6-1562.46" + wire \main_sdblock2mem_wishbonedmawriter_reset + attribute \src "ls180.v:1546.6-1546.51" + wire \main_sdblock2mem_wishbonedmawriter_sink_first + attribute \src "ls180.v:1547.6-1547.50" + wire \main_sdblock2mem_wishbonedmawriter_sink_last + attribute \src "ls180.v:1548.13-1548.65" + wire width 32 \main_sdblock2mem_wishbonedmawriter_sink_payload_data + attribute \src "ls180.v:1545.5-1545.50" + wire \main_sdblock2mem_wishbonedmawriter_sink_ready + attribute \src "ls180.v:1544.6-1544.51" + wire \main_sdblock2mem_wishbonedmawriter_sink_valid + attribute \src "ls180.v:1555.5-1555.46" + wire \main_sdblock2mem_wishbonedmawriter_status + attribute \src "ls180.v:1556.6-1556.43" + wire \main_sdblock2mem_wishbonedmawriter_we + attribute \src "ls180.v:1324.5-1324.31" + wire \main_sdcore_block_count_re + attribute \src "ls180.v:1323.12-1323.43" + wire width 32 \main_sdcore_block_count_storage + attribute \src "ls180.v:1322.5-1322.32" + wire \main_sdcore_block_length_re + attribute \src "ls180.v:1321.11-1321.43" + wire width 10 \main_sdcore_block_length_storage + attribute \src "ls180.v:1308.5-1308.32" + wire \main_sdcore_cmd_argument_re + attribute \src "ls180.v:1307.12-1307.44" + wire width 32 \main_sdcore_cmd_argument_storage + attribute \src "ls180.v:1310.5-1310.31" + wire \main_sdcore_cmd_command_re + attribute \src "ls180.v:1309.12-1309.43" + wire width 32 \main_sdcore_cmd_command_storage + attribute \src "ls180.v:1463.11-1463.32" + wire width 3 \main_sdcore_cmd_count + attribute \src "ls180.v:1798.11-1798.55" + wire width 3 \main_sdcore_cmd_count_sdcore_fsm_next_value2 + attribute \src "ls180.v:1799.5-1799.52" + wire \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 + attribute \src "ls180.v:1464.5-1464.25" + wire \main_sdcore_cmd_done + attribute \src "ls180.v:1794.5-1794.48" + wire \main_sdcore_cmd_done_sdcore_fsm_next_value0 + attribute \src "ls180.v:1795.5-1795.51" + wire \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 + attribute \src "ls180.v:1465.5-1465.26" + wire \main_sdcore_cmd_error + attribute \src "ls180.v:1802.5-1802.49" + wire \main_sdcore_cmd_error_sdcore_fsm_next_value4 + attribute \src "ls180.v:1803.5-1803.52" + wire \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 + attribute \src "ls180.v:1317.12-1317.40" + wire width 4 \main_sdcore_cmd_event_status + attribute \src "ls180.v:1318.6-1318.30" + wire \main_sdcore_cmd_event_we + attribute \src "ls180.v:1315.13-1315.44" + wire width 128 \main_sdcore_cmd_response_status + attribute \src "ls180.v:1810.13-1810.67" + wire width 128 \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 + attribute \src "ls180.v:1811.5-1811.62" + wire \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 + attribute \src "ls180.v:1316.6-1316.33" + wire \main_sdcore_cmd_response_we + attribute \src "ls180.v:1312.6-1312.28" + wire \main_sdcore_cmd_send_r + attribute \src "ls180.v:1311.6-1311.29" + wire \main_sdcore_cmd_send_re + attribute \src "ls180.v:1314.5-1314.27" + wire \main_sdcore_cmd_send_w + attribute \src "ls180.v:1313.6-1313.29" + wire \main_sdcore_cmd_send_we + attribute \src "ls180.v:1466.5-1466.28" + wire \main_sdcore_cmd_timeout + attribute \src "ls180.v:1804.5-1804.51" + wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 + attribute \src "ls180.v:1805.5-1805.54" + wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 + attribute \src "ls180.v:1462.12-1462.32" + wire width 2 \main_sdcore_cmd_type + attribute \src "ls180.v:1424.11-1424.40" + wire width 4 \main_sdcore_crc16_checker_cnt + attribute \src "ls180.v:1430.5-1430.39" + wire \main_sdcore_crc16_checker_crc0_clr + attribute \src "ls180.v:1429.12-1429.46" + wire width 16 \main_sdcore_crc16_checker_crc0_crc + attribute \src "ls180.v:1425.12-1425.50" + wire width 16 \main_sdcore_crc16_checker_crc0_crcreg0 + attribute \src "ls180.v:1426.13-1426.51" + wire width 16 \main_sdcore_crc16_checker_crc0_crcreg1 + attribute \src "ls180.v:1427.13-1427.51" + wire width 16 \main_sdcore_crc16_checker_crc0_crcreg2 + attribute \src "ls180.v:1431.6-1431.43" + wire \main_sdcore_crc16_checker_crc0_enable + attribute \src "ls180.v:1428.12-1428.46" + wire width 2 \main_sdcore_crc16_checker_crc0_val + attribute \src "ls180.v:1437.5-1437.39" + wire \main_sdcore_crc16_checker_crc1_clr + attribute \src "ls180.v:1436.12-1436.46" + wire width 16 \main_sdcore_crc16_checker_crc1_crc + attribute \src "ls180.v:1432.12-1432.50" + wire width 16 \main_sdcore_crc16_checker_crc1_crcreg0 + attribute \src "ls180.v:1433.13-1433.51" + wire width 16 \main_sdcore_crc16_checker_crc1_crcreg1 + attribute \src "ls180.v:1434.13-1434.51" + wire width 16 \main_sdcore_crc16_checker_crc1_crcreg2 + attribute \src "ls180.v:1438.6-1438.43" + wire \main_sdcore_crc16_checker_crc1_enable + attribute \src "ls180.v:1435.12-1435.46" + wire width 2 \main_sdcore_crc16_checker_crc1_val + attribute \src "ls180.v:1444.5-1444.39" + wire \main_sdcore_crc16_checker_crc2_clr + attribute \src "ls180.v:1443.12-1443.46" + wire width 16 \main_sdcore_crc16_checker_crc2_crc + attribute \src "ls180.v:1439.12-1439.50" + wire width 16 \main_sdcore_crc16_checker_crc2_crcreg0 + attribute \src "ls180.v:1440.13-1440.51" + wire width 16 \main_sdcore_crc16_checker_crc2_crcreg1 + attribute \src "ls180.v:1441.13-1441.51" + wire width 16 \main_sdcore_crc16_checker_crc2_crcreg2 + attribute \src "ls180.v:1445.6-1445.43" + wire \main_sdcore_crc16_checker_crc2_enable + attribute \src "ls180.v:1442.12-1442.46" + wire width 2 \main_sdcore_crc16_checker_crc2_val + attribute \src "ls180.v:1451.5-1451.39" + wire \main_sdcore_crc16_checker_crc3_clr + attribute \src "ls180.v:1450.12-1450.46" + wire width 16 \main_sdcore_crc16_checker_crc3_crc + attribute \src "ls180.v:1446.12-1446.50" + wire width 16 \main_sdcore_crc16_checker_crc3_crcreg0 + attribute \src "ls180.v:1447.13-1447.51" + wire width 16 \main_sdcore_crc16_checker_crc3_crcreg1 + attribute \src "ls180.v:1448.13-1448.51" + wire width 16 \main_sdcore_crc16_checker_crc3_crcreg2 + attribute \src "ls180.v:1452.6-1452.43" + wire \main_sdcore_crc16_checker_crc3_enable + attribute \src "ls180.v:1449.12-1449.46" + wire width 2 \main_sdcore_crc16_checker_crc3_val + attribute \src "ls180.v:1453.12-1453.45" + wire width 16 \main_sdcore_crc16_checker_crctmp0 + attribute \src "ls180.v:1454.12-1454.45" + wire width 16 \main_sdcore_crc16_checker_crctmp1 + attribute \src "ls180.v:1455.12-1455.45" + wire width 16 \main_sdcore_crc16_checker_crctmp2 + attribute \src "ls180.v:1456.12-1456.45" + wire width 16 \main_sdcore_crc16_checker_crctmp3 + attribute \src "ls180.v:1458.12-1458.43" + wire width 16 \main_sdcore_crc16_checker_fifo0 + attribute \src "ls180.v:1459.12-1459.43" + wire width 16 \main_sdcore_crc16_checker_fifo1 + attribute \src "ls180.v:1460.12-1460.43" + wire width 16 \main_sdcore_crc16_checker_fifo2 + attribute \src "ls180.v:1461.12-1461.43" + wire width 16 \main_sdcore_crc16_checker_fifo3 + attribute \src "ls180.v:1415.5-1415.41" + wire \main_sdcore_crc16_checker_sink_first + attribute \src "ls180.v:1416.5-1416.40" + wire \main_sdcore_crc16_checker_sink_last + attribute \src "ls180.v:1417.11-1417.54" + wire width 8 \main_sdcore_crc16_checker_sink_payload_data + attribute \src "ls180.v:1414.5-1414.41" + wire \main_sdcore_crc16_checker_sink_ready + attribute \src "ls180.v:1413.5-1413.41" + wire \main_sdcore_crc16_checker_sink_valid + attribute \src "ls180.v:1420.5-1420.43" + wire \main_sdcore_crc16_checker_source_first + attribute \src "ls180.v:1421.6-1421.43" + wire \main_sdcore_crc16_checker_source_last + attribute \src "ls180.v:1422.12-1422.57" + wire width 8 \main_sdcore_crc16_checker_source_payload_data + attribute \src "ls180.v:1419.6-1419.44" + wire \main_sdcore_crc16_checker_source_ready + attribute \src "ls180.v:1418.5-1418.43" + wire \main_sdcore_crc16_checker_source_valid + attribute \src "ls180.v:1423.11-1423.40" + wire width 8 \main_sdcore_crc16_checker_val + attribute \src "ls180.v:1457.5-1457.36" + wire \main_sdcore_crc16_checker_valid + attribute \src "ls180.v:1380.11-1380.41" + wire width 3 \main_sdcore_crc16_inserter_cnt + attribute \src "ls180.v:1790.11-1790.80" + wire width 3 \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 + attribute \src "ls180.v:1791.5-1791.77" + wire \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 + attribute \src "ls180.v:1386.6-1386.41" + wire \main_sdcore_crc16_inserter_crc0_clr + attribute \src "ls180.v:1385.12-1385.47" + wire width 16 \main_sdcore_crc16_inserter_crc0_crc + attribute \src "ls180.v:1381.12-1381.51" + wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg0 + attribute \src "ls180.v:1382.13-1382.52" + wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg1 + attribute \src "ls180.v:1383.13-1383.52" + wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg2 + attribute \src "ls180.v:1387.6-1387.44" + wire \main_sdcore_crc16_inserter_crc0_enable + attribute \src "ls180.v:1384.12-1384.47" + wire width 2 \main_sdcore_crc16_inserter_crc0_val + attribute \src "ls180.v:1393.6-1393.41" + wire \main_sdcore_crc16_inserter_crc1_clr + attribute \src "ls180.v:1392.12-1392.47" + wire width 16 \main_sdcore_crc16_inserter_crc1_crc + attribute \src "ls180.v:1388.12-1388.51" + wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg0 + attribute \src "ls180.v:1389.13-1389.52" + wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg1 + attribute \src "ls180.v:1390.13-1390.52" + wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg2 + attribute \src "ls180.v:1394.6-1394.44" + wire \main_sdcore_crc16_inserter_crc1_enable + attribute \src "ls180.v:1391.12-1391.47" + wire width 2 \main_sdcore_crc16_inserter_crc1_val + attribute \src "ls180.v:1400.6-1400.41" + wire \main_sdcore_crc16_inserter_crc2_clr + attribute \src "ls180.v:1399.12-1399.47" + wire width 16 \main_sdcore_crc16_inserter_crc2_crc + attribute \src "ls180.v:1395.12-1395.51" + wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg0 + attribute \src "ls180.v:1396.13-1396.52" + wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg1 + attribute \src "ls180.v:1397.13-1397.52" + wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg2 + attribute \src "ls180.v:1401.6-1401.44" + wire \main_sdcore_crc16_inserter_crc2_enable + attribute \src "ls180.v:1398.12-1398.47" + wire width 2 \main_sdcore_crc16_inserter_crc2_val + attribute \src "ls180.v:1407.6-1407.41" + wire \main_sdcore_crc16_inserter_crc3_clr + attribute \src "ls180.v:1406.12-1406.47" + wire width 16 \main_sdcore_crc16_inserter_crc3_crc + attribute \src "ls180.v:1402.12-1402.51" + wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg0 + attribute \src "ls180.v:1403.13-1403.52" + wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg1 + attribute \src "ls180.v:1404.13-1404.52" + wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg2 + attribute \src "ls180.v:1408.6-1408.44" + wire \main_sdcore_crc16_inserter_crc3_enable + attribute \src "ls180.v:1405.12-1405.47" + wire width 2 \main_sdcore_crc16_inserter_crc3_val + attribute \src "ls180.v:1409.12-1409.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp0 + attribute \src "ls180.v:1782.12-1782.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 + attribute \src "ls180.v:1783.5-1783.81" + wire \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 + attribute \src "ls180.v:1410.12-1410.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp1 + attribute \src "ls180.v:1784.12-1784.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 + attribute \src "ls180.v:1785.5-1785.81" + wire \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 + attribute \src "ls180.v:1411.12-1411.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp2 + attribute \src "ls180.v:1786.12-1786.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 + attribute \src "ls180.v:1787.5-1787.81" + wire \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 + attribute \src "ls180.v:1412.12-1412.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp3 + attribute \src "ls180.v:1788.12-1788.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 + attribute \src "ls180.v:1789.5-1789.81" + wire \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 + attribute \src "ls180.v:1372.6-1372.43" + wire \main_sdcore_crc16_inserter_sink_first + attribute \src "ls180.v:1373.6-1373.42" + wire \main_sdcore_crc16_inserter_sink_last + attribute \src "ls180.v:1374.12-1374.56" + wire width 8 \main_sdcore_crc16_inserter_sink_payload_data + attribute \src "ls180.v:1371.5-1371.42" + wire \main_sdcore_crc16_inserter_sink_ready + attribute \src "ls180.v:1370.6-1370.43" + wire \main_sdcore_crc16_inserter_sink_valid + attribute \src "ls180.v:1377.5-1377.44" + wire \main_sdcore_crc16_inserter_source_first + attribute \src "ls180.v:1378.5-1378.43" + wire \main_sdcore_crc16_inserter_source_last + attribute \src "ls180.v:1379.11-1379.57" + wire width 8 \main_sdcore_crc16_inserter_source_payload_data + attribute \src "ls180.v:1376.5-1376.44" + wire \main_sdcore_crc16_inserter_source_ready + attribute \src "ls180.v:1375.5-1375.44" + wire \main_sdcore_crc16_inserter_source_valid + attribute \src "ls180.v:1368.6-1368.35" + wire \main_sdcore_crc7_inserter_clr + attribute \src "ls180.v:1367.11-1367.40" + wire width 7 \main_sdcore_crc7_inserter_crc + attribute \src "ls180.v:1325.11-1325.44" + wire width 7 \main_sdcore_crc7_inserter_crcreg0 + attribute \src "ls180.v:1326.12-1326.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg1 + attribute \src "ls180.v:1335.12-1335.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg10 + attribute \src "ls180.v:1336.12-1336.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg11 + attribute \src "ls180.v:1337.12-1337.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg12 + attribute \src "ls180.v:1338.12-1338.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg13 + attribute \src "ls180.v:1339.12-1339.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg14 + attribute \src "ls180.v:1340.12-1340.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg15 + attribute \src "ls180.v:1341.12-1341.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg16 + attribute \src "ls180.v:1342.12-1342.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg17 + attribute \src "ls180.v:1343.12-1343.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg18 + attribute \src "ls180.v:1344.12-1344.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg19 + attribute \src "ls180.v:1327.12-1327.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg2 + attribute \src "ls180.v:1345.12-1345.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg20 + attribute \src "ls180.v:1346.12-1346.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg21 + attribute \src "ls180.v:1347.12-1347.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg22 + attribute \src "ls180.v:1348.12-1348.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg23 + attribute \src "ls180.v:1349.12-1349.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg24 + attribute \src "ls180.v:1350.12-1350.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg25 + attribute \src "ls180.v:1351.12-1351.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg26 + attribute \src "ls180.v:1352.12-1352.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg27 + attribute \src "ls180.v:1353.12-1353.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg28 + attribute \src "ls180.v:1354.12-1354.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg29 + attribute \src "ls180.v:1328.12-1328.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg3 + attribute \src "ls180.v:1355.12-1355.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg30 + attribute \src "ls180.v:1356.12-1356.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg31 + attribute \src "ls180.v:1357.12-1357.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg32 + attribute \src "ls180.v:1358.12-1358.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg33 + attribute \src "ls180.v:1359.12-1359.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg34 + attribute \src "ls180.v:1360.12-1360.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg35 + attribute \src "ls180.v:1361.12-1361.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg36 + attribute \src "ls180.v:1362.12-1362.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg37 + attribute \src "ls180.v:1363.12-1363.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg38 + attribute \src "ls180.v:1364.12-1364.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg39 + attribute \src "ls180.v:1329.12-1329.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg4 + attribute \src "ls180.v:1365.12-1365.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg40 + attribute \src "ls180.v:1330.12-1330.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg5 + attribute \src "ls180.v:1331.12-1331.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg6 + attribute \src "ls180.v:1332.12-1332.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg7 + attribute \src "ls180.v:1333.12-1333.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg8 + attribute \src "ls180.v:1334.12-1334.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg9 + attribute \src "ls180.v:1369.6-1369.38" + wire \main_sdcore_crc7_inserter_enable + attribute \src "ls180.v:1366.13-1366.42" + wire width 40 \main_sdcore_crc7_inserter_val + attribute \src "ls180.v:1468.12-1468.34" + wire width 32 \main_sdcore_data_count + attribute \src "ls180.v:1800.12-1800.57" + wire width 32 \main_sdcore_data_count_sdcore_fsm_next_value3 + attribute \src "ls180.v:1801.5-1801.53" + wire \main_sdcore_data_count_sdcore_fsm_next_value_ce3 + attribute \src "ls180.v:1469.5-1469.26" + wire \main_sdcore_data_done + attribute \src "ls180.v:1796.5-1796.49" + wire \main_sdcore_data_done_sdcore_fsm_next_value1 + attribute \src "ls180.v:1797.5-1797.52" + wire \main_sdcore_data_done_sdcore_fsm_next_value_ce1 + attribute \src "ls180.v:1470.5-1470.27" + wire \main_sdcore_data_error + attribute \src "ls180.v:1806.5-1806.50" + wire \main_sdcore_data_error_sdcore_fsm_next_value6 + attribute \src "ls180.v:1807.5-1807.53" + wire \main_sdcore_data_error_sdcore_fsm_next_value_ce6 + attribute \src "ls180.v:1319.12-1319.41" + wire width 4 \main_sdcore_data_event_status + attribute \src "ls180.v:1320.6-1320.31" + wire \main_sdcore_data_event_we + attribute \src "ls180.v:1471.5-1471.29" + wire \main_sdcore_data_timeout + attribute \src "ls180.v:1808.5-1808.52" + wire \main_sdcore_data_timeout_sdcore_fsm_next_value7 + attribute \src "ls180.v:1809.5-1809.55" + wire \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 + attribute \src "ls180.v:1467.12-1467.33" + wire width 2 \main_sdcore_data_type + attribute \src "ls180.v:1299.6-1299.33" + wire \main_sdcore_sink_sink_first + attribute \src "ls180.v:1300.6-1300.32" + wire \main_sdcore_sink_sink_last + attribute \src "ls180.v:1301.12-1301.46" + wire width 8 \main_sdcore_sink_sink_payload_data + attribute \src "ls180.v:1298.6-1298.33" + wire \main_sdcore_sink_sink_ready + attribute \src "ls180.v:1297.6-1297.33" + wire \main_sdcore_sink_sink_valid + attribute \src "ls180.v:1304.6-1304.37" + wire \main_sdcore_source_source_first + attribute \src "ls180.v:1305.6-1305.36" + wire \main_sdcore_source_source_last + attribute \src "ls180.v:1306.12-1306.50" + wire width 8 \main_sdcore_source_source_payload_data + attribute \src "ls180.v:1303.6-1303.37" + wire \main_sdcore_source_source_ready + attribute \src "ls180.v:1302.6-1302.37" + wire \main_sdcore_source_source_valid + attribute \src "ls180.v:1617.6-1617.38" + wire \main_sdmem2block_converter_first + attribute \src "ls180.v:1618.6-1618.37" + wire \main_sdmem2block_converter_last + attribute \src "ls180.v:1616.11-1616.41" + wire width 2 \main_sdmem2block_converter_mux + attribute \src "ls180.v:1607.6-1607.43" + wire \main_sdmem2block_converter_sink_first + attribute \src "ls180.v:1608.6-1608.42" + wire \main_sdmem2block_converter_sink_last + attribute \src "ls180.v:1609.13-1609.57" + wire width 32 \main_sdmem2block_converter_sink_payload_data + attribute \src "ls180.v:1606.6-1606.43" + wire \main_sdmem2block_converter_sink_ready + attribute \src "ls180.v:1605.6-1605.43" + wire \main_sdmem2block_converter_sink_valid + attribute \src "ls180.v:1612.6-1612.45" + wire \main_sdmem2block_converter_source_first + attribute \src "ls180.v:1613.6-1613.44" + wire \main_sdmem2block_converter_source_last + attribute \src "ls180.v:1614.11-1614.57" + wire width 8 \main_sdmem2block_converter_source_payload_data + attribute \src "ls180.v:1615.6-1615.65" + wire \main_sdmem2block_converter_source_payload_valid_token_count + attribute \src "ls180.v:1611.6-1611.45" + wire \main_sdmem2block_converter_source_ready + attribute \src "ls180.v:1610.6-1610.45" + wire \main_sdmem2block_converter_source_valid + attribute \src "ls180.v:1601.13-1601.38" + wire width 32 \main_sdmem2block_dma_base + attribute \src "ls180.v:1590.5-1590.33" + wire \main_sdmem2block_dma_base_re + attribute \src "ls180.v:1589.12-1589.45" + wire width 64 \main_sdmem2block_dma_base_storage + attribute \src "ls180.v:1588.12-1588.37" + wire width 32 \main_sdmem2block_dma_data + attribute \src "ls180.v:1818.12-1818.67" + wire width 32 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + attribute \src "ls180.v:1819.5-1819.63" + wire \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce + attribute \src "ls180.v:1595.5-1595.37" + wire \main_sdmem2block_dma_done_status + attribute \src "ls180.v:1596.6-1596.34" + wire \main_sdmem2block_dma_done_we + attribute \src "ls180.v:1594.5-1594.35" + wire \main_sdmem2block_dma_enable_re + attribute \src "ls180.v:1593.5-1593.40" + wire \main_sdmem2block_dma_enable_storage + attribute \src "ls180.v:1603.13-1603.40" + wire width 32 \main_sdmem2block_dma_length + attribute \src "ls180.v:1592.5-1592.35" + wire \main_sdmem2block_dma_length_re + attribute \src "ls180.v:1591.12-1591.47" + wire width 32 \main_sdmem2block_dma_length_storage + attribute \src "ls180.v:1598.5-1598.33" + wire \main_sdmem2block_dma_loop_re + attribute \src "ls180.v:1597.5-1597.38" + wire \main_sdmem2block_dma_loop_storage + attribute \src "ls180.v:1602.12-1602.39" + wire width 32 \main_sdmem2block_dma_offset + attribute \src "ls180.v:1822.12-1822.79" + wire width 32 \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value + attribute \src "ls180.v:1823.5-1823.75" + wire \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce + attribute \src "ls180.v:1599.13-1599.47" + wire width 32 \main_sdmem2block_dma_offset_status + attribute \src "ls180.v:1600.6-1600.36" + wire \main_sdmem2block_dma_offset_we + attribute \src "ls180.v:1604.6-1604.32" + wire \main_sdmem2block_dma_reset + attribute \src "ls180.v:1581.5-1581.35" + wire \main_sdmem2block_dma_sink_last + attribute \src "ls180.v:1582.12-1582.53" + wire width 32 \main_sdmem2block_dma_sink_payload_address + attribute \src "ls180.v:1580.5-1580.36" + wire \main_sdmem2block_dma_sink_ready + attribute \src "ls180.v:1579.5-1579.36" + wire \main_sdmem2block_dma_sink_valid + attribute \src "ls180.v:1585.5-1585.38" + wire \main_sdmem2block_dma_source_first + attribute \src "ls180.v:1586.5-1586.37" + wire \main_sdmem2block_dma_source_last + attribute \src "ls180.v:1587.12-1587.52" + wire width 32 \main_sdmem2block_dma_source_payload_data + attribute \src "ls180.v:1584.6-1584.39" + wire \main_sdmem2block_dma_source_ready + attribute \src "ls180.v:1583.5-1583.38" + wire \main_sdmem2block_dma_source_valid + attribute \src "ls180.v:1643.11-1643.40" + wire width 5 \main_sdmem2block_fifo_consume + attribute \src "ls180.v:1648.6-1648.35" + wire \main_sdmem2block_fifo_do_read + attribute \src "ls180.v:1652.6-1652.41" + wire \main_sdmem2block_fifo_fifo_in_first + attribute \src "ls180.v:1653.6-1653.40" + wire \main_sdmem2block_fifo_fifo_in_last + attribute \src "ls180.v:1651.12-1651.54" + wire width 8 \main_sdmem2block_fifo_fifo_in_payload_data + attribute \src "ls180.v:1655.6-1655.42" + wire \main_sdmem2block_fifo_fifo_out_first + attribute \src "ls180.v:1656.6-1656.41" + wire \main_sdmem2block_fifo_fifo_out_last + attribute \src "ls180.v:1654.12-1654.55" + wire width 8 \main_sdmem2block_fifo_fifo_out_payload_data + attribute \src "ls180.v:1640.11-1640.38" + wire width 6 \main_sdmem2block_fifo_level + attribute \src "ls180.v:1642.11-1642.40" + wire width 5 \main_sdmem2block_fifo_produce + attribute \src "ls180.v:1649.12-1649.44" + wire width 5 \main_sdmem2block_fifo_rdport_adr + attribute \src "ls180.v:1650.12-1650.46" + wire width 10 \main_sdmem2block_fifo_rdport_dat_r + attribute \src "ls180.v:1641.5-1641.34" + wire \main_sdmem2block_fifo_replace + attribute \src "ls180.v:1626.6-1626.38" + wire \main_sdmem2block_fifo_sink_first + attribute \src "ls180.v:1627.6-1627.37" + wire \main_sdmem2block_fifo_sink_last + attribute \src "ls180.v:1628.12-1628.51" + wire width 8 \main_sdmem2block_fifo_sink_payload_data + attribute \src "ls180.v:1625.6-1625.38" + wire \main_sdmem2block_fifo_sink_ready + attribute \src "ls180.v:1624.6-1624.38" + wire \main_sdmem2block_fifo_sink_valid + attribute \src "ls180.v:1631.6-1631.40" + wire \main_sdmem2block_fifo_source_first + attribute \src "ls180.v:1632.6-1632.39" + wire \main_sdmem2block_fifo_source_last + attribute \src "ls180.v:1633.12-1633.53" + wire width 8 \main_sdmem2block_fifo_source_payload_data + attribute \src "ls180.v:1630.6-1630.40" + wire \main_sdmem2block_fifo_source_ready + attribute \src "ls180.v:1629.6-1629.40" + wire \main_sdmem2block_fifo_source_valid + attribute \src "ls180.v:1638.12-1638.46" + wire width 10 \main_sdmem2block_fifo_syncfifo_din + attribute \src "ls180.v:1639.12-1639.47" + wire width 10 \main_sdmem2block_fifo_syncfifo_dout + attribute \src "ls180.v:1636.6-1636.39" + wire \main_sdmem2block_fifo_syncfifo_re + attribute \src "ls180.v:1637.6-1637.45" + wire \main_sdmem2block_fifo_syncfifo_readable + attribute \src "ls180.v:1634.6-1634.39" + wire \main_sdmem2block_fifo_syncfifo_we + attribute \src "ls180.v:1635.6-1635.45" + wire \main_sdmem2block_fifo_syncfifo_writable + attribute \src "ls180.v:1644.11-1644.43" + wire width 5 \main_sdmem2block_fifo_wrport_adr + attribute \src "ls180.v:1645.12-1645.46" + wire width 10 \main_sdmem2block_fifo_wrport_dat_r + attribute \src "ls180.v:1647.12-1647.46" + wire width 10 \main_sdmem2block_fifo_wrport_dat_w + attribute \src "ls180.v:1646.6-1646.37" + wire \main_sdmem2block_fifo_wrport_we + attribute \src "ls180.v:1576.6-1576.43" + wire \main_sdmem2block_source_source_first0 + attribute \src "ls180.v:1621.6-1621.43" + wire \main_sdmem2block_source_source_first1 + attribute \src "ls180.v:1577.6-1577.42" + wire \main_sdmem2block_source_source_last0 + attribute \src "ls180.v:1622.6-1622.42" + wire \main_sdmem2block_source_source_last1 + attribute \src "ls180.v:1578.12-1578.56" + wire width 8 \main_sdmem2block_source_source_payload_data0 + attribute \src "ls180.v:1623.12-1623.56" + wire width 8 \main_sdmem2block_source_source_payload_data1 + attribute \src "ls180.v:1575.6-1575.43" + wire \main_sdmem2block_source_source_ready0 + attribute \src "ls180.v:1620.6-1620.43" + wire \main_sdmem2block_source_source_ready1 + attribute \src "ls180.v:1574.6-1574.43" + wire \main_sdmem2block_source_source_valid0 + attribute \src "ls180.v:1619.6-1619.43" + wire \main_sdmem2block_source_source_valid1 + attribute \src "ls180.v:1025.6-1025.27" + wire \main_sdphy_clocker_ce + attribute \src "ls180.v:1024.5-1024.28" + wire \main_sdphy_clocker_clk0 + attribute \src "ls180.v:1027.5-1027.28" + wire \main_sdphy_clocker_clk1 + attribute \src "ls180.v:1028.5-1028.29" + wire \main_sdphy_clocker_clk_d + attribute \src "ls180.v:1026.11-1026.34" + wire width 9 \main_sdphy_clocker_clks + attribute \src "ls180.v:1022.5-1022.26" + wire \main_sdphy_clocker_re + attribute \src "ls180.v:1023.6-1023.29" + wire \main_sdphy_clocker_stop + attribute \src "ls180.v:1021.11-1021.37" + wire width 9 \main_sdphy_clocker_storage + attribute \src "ls180.v:1125.6-1125.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_first + attribute \src "ls180.v:1126.6-1126.40" + wire \main_sdphy_cmdr_cmdr_buf_sink_last + attribute \src "ls180.v:1127.12-1127.54" + wire width 8 \main_sdphy_cmdr_cmdr_buf_sink_payload_data + attribute \src "ls180.v:1124.6-1124.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_ready + attribute \src "ls180.v:1123.6-1123.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_valid + attribute \src "ls180.v:1130.5-1130.42" + wire \main_sdphy_cmdr_cmdr_buf_source_first + attribute \src "ls180.v:1131.5-1131.41" + wire \main_sdphy_cmdr_cmdr_buf_source_last + attribute \src "ls180.v:1132.11-1132.55" + wire width 8 \main_sdphy_cmdr_cmdr_buf_source_payload_data + attribute \src "ls180.v:1129.6-1129.43" + wire \main_sdphy_cmdr_cmdr_buf_source_ready + attribute \src "ls180.v:1128.5-1128.42" + wire \main_sdphy_cmdr_cmdr_buf_source_valid + attribute \src "ls180.v:1115.11-1115.47" + wire width 3 \main_sdphy_cmdr_cmdr_converter_demux + attribute \src "ls180.v:1116.6-1116.46" + wire \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:1106.5-1106.46" + wire \main_sdphy_cmdr_cmdr_converter_sink_first + attribute \src "ls180.v:1107.5-1107.45" + wire \main_sdphy_cmdr_cmdr_converter_sink_last + attribute \src "ls180.v:1108.6-1108.54" + wire \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:1105.6-1105.47" + wire \main_sdphy_cmdr_cmdr_converter_sink_ready + attribute \src "ls180.v:1104.6-1104.47" + wire \main_sdphy_cmdr_cmdr_converter_sink_valid + attribute \src "ls180.v:1111.5-1111.48" + wire \main_sdphy_cmdr_cmdr_converter_source_first + attribute \src "ls180.v:1112.5-1112.47" + wire \main_sdphy_cmdr_cmdr_converter_source_last + attribute \src "ls180.v:1113.11-1113.61" + wire width 8 \main_sdphy_cmdr_cmdr_converter_source_payload_data + attribute \src "ls180.v:1114.11-1114.74" + wire width 4 \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count + attribute \src "ls180.v:1110.6-1110.49" + wire \main_sdphy_cmdr_cmdr_converter_source_ready + attribute \src "ls180.v:1109.6-1109.49" + wire \main_sdphy_cmdr_cmdr_converter_source_valid + attribute \src "ls180.v:1117.5-1117.46" + wire \main_sdphy_cmdr_cmdr_converter_strobe_all + attribute \src "ls180.v:1088.6-1088.40" + wire \main_sdphy_cmdr_cmdr_pads_in_first + attribute \src "ls180.v:1089.6-1089.39" + wire \main_sdphy_cmdr_cmdr_pads_in_last + attribute \src "ls180.v:1090.6-1090.46" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_clk + attribute \src "ls180.v:1091.6-1091.48" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i + attribute \src "ls180.v:1092.6-1092.48" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o + attribute \src "ls180.v:1093.6-1093.49" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe + attribute \src "ls180.v:1094.12-1094.55" + wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_i + attribute \src "ls180.v:1095.12-1095.55" + wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_o + attribute \src "ls180.v:1096.6-1096.50" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe + attribute \src "ls180.v:1087.5-1087.39" + wire \main_sdphy_cmdr_cmdr_pads_in_ready + attribute \src "ls180.v:1086.6-1086.40" + wire \main_sdphy_cmdr_cmdr_pads_in_valid + attribute \src "ls180.v:1133.5-1133.31" + wire \main_sdphy_cmdr_cmdr_reset + attribute \src "ls180.v:1762.5-1762.59" + wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 + attribute \src "ls180.v:1763.5-1763.62" + wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 + attribute \src "ls180.v:1103.5-1103.29" + wire \main_sdphy_cmdr_cmdr_run + attribute \src "ls180.v:1099.6-1099.47" + wire \main_sdphy_cmdr_cmdr_source_source_first0 + attribute \src "ls180.v:1120.6-1120.47" + wire \main_sdphy_cmdr_cmdr_source_source_first1 + attribute \src "ls180.v:1100.6-1100.46" + wire \main_sdphy_cmdr_cmdr_source_source_last0 + attribute \src "ls180.v:1121.6-1121.46" + wire \main_sdphy_cmdr_cmdr_source_source_last1 + attribute \src "ls180.v:1101.12-1101.60" + wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data0 + attribute \src "ls180.v:1122.12-1122.60" + wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data1 + attribute \src "ls180.v:1098.5-1098.46" + wire \main_sdphy_cmdr_cmdr_source_source_ready0 + attribute \src "ls180.v:1119.6-1119.47" + wire \main_sdphy_cmdr_cmdr_source_source_ready1 + attribute \src "ls180.v:1097.6-1097.47" + wire \main_sdphy_cmdr_cmdr_source_source_valid0 + attribute \src "ls180.v:1118.6-1118.47" + wire \main_sdphy_cmdr_cmdr_source_source_valid1 + attribute \src "ls180.v:1102.6-1102.32" + wire \main_sdphy_cmdr_cmdr_start + attribute \src "ls180.v:1085.11-1085.32" + wire width 8 \main_sdphy_cmdr_count + attribute \src "ls180.v:1758.11-1758.60" + wire width 8 \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 + attribute \src "ls180.v:1759.5-1759.57" + wire \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 + attribute \src "ls180.v:1060.5-1060.42" + wire \main_sdphy_cmdr_pads_in_pads_in_first + attribute \src "ls180.v:1061.5-1061.41" + wire \main_sdphy_cmdr_pads_in_pads_in_last + attribute \src "ls180.v:1062.5-1062.48" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_clk + attribute \src "ls180.v:1063.6-1063.51" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i + attribute \src "ls180.v:1064.5-1064.50" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o + attribute \src "ls180.v:1065.5-1065.51" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe + attribute \src "ls180.v:1066.12-1066.58" + wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_i + attribute \src "ls180.v:1067.11-1067.57" + wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_o + attribute \src "ls180.v:1068.5-1068.52" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe + attribute \src "ls180.v:1059.6-1059.43" + wire \main_sdphy_cmdr_pads_in_pads_in_ready + attribute \src "ls180.v:1058.6-1058.43" + wire \main_sdphy_cmdr_pads_in_pads_in_valid + attribute \src "ls180.v:1070.5-1070.41" + wire \main_sdphy_cmdr_pads_out_payload_clk + attribute \src "ls180.v:1071.5-1071.43" + wire \main_sdphy_cmdr_pads_out_payload_cmd_o + attribute \src "ls180.v:1072.5-1072.44" + wire \main_sdphy_cmdr_pads_out_payload_cmd_oe + attribute \src "ls180.v:1073.11-1073.50" + wire width 4 \main_sdphy_cmdr_pads_out_payload_data_o + attribute \src "ls180.v:1074.5-1074.45" + wire \main_sdphy_cmdr_pads_out_payload_data_oe + attribute \src "ls180.v:1069.6-1069.36" + wire \main_sdphy_cmdr_pads_out_ready + attribute \src "ls180.v:1077.5-1077.30" + wire \main_sdphy_cmdr_sink_last + attribute \src "ls180.v:1078.11-1078.46" + wire width 8 \main_sdphy_cmdr_sink_payload_length + attribute \src "ls180.v:1076.5-1076.31" + wire \main_sdphy_cmdr_sink_ready + attribute \src "ls180.v:1075.5-1075.31" + wire \main_sdphy_cmdr_sink_valid + attribute \src "ls180.v:1081.5-1081.32" + wire \main_sdphy_cmdr_source_last + attribute \src "ls180.v:1082.11-1082.46" + wire width 8 \main_sdphy_cmdr_source_payload_data + attribute \src "ls180.v:1083.11-1083.48" + wire width 3 \main_sdphy_cmdr_source_payload_status + attribute \src "ls180.v:1080.5-1080.33" + wire \main_sdphy_cmdr_source_ready + attribute \src "ls180.v:1079.5-1079.33" + wire \main_sdphy_cmdr_source_valid + attribute \src "ls180.v:1084.12-1084.35" + wire width 32 \main_sdphy_cmdr_timeout + attribute \src "ls180.v:1760.12-1760.63" + wire width 32 \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 + attribute \src "ls180.v:1761.5-1761.59" + wire \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 + attribute \src "ls180.v:1057.11-1057.32" + wire width 8 \main_sdphy_cmdw_count + attribute \src "ls180.v:1754.11-1754.59" + wire width 8 \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value + attribute \src "ls180.v:1755.5-1755.56" + wire \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce + attribute \src "ls180.v:1056.5-1056.25" + wire \main_sdphy_cmdw_done + attribute \src "ls180.v:1044.6-1044.43" + wire \main_sdphy_cmdw_pads_in_payload_cmd_i + attribute \src "ls180.v:1045.12-1045.50" + wire width 4 \main_sdphy_cmdw_pads_in_payload_data_i + attribute \src "ls180.v:1043.6-1043.35" + wire \main_sdphy_cmdw_pads_in_valid + attribute \src "ls180.v:1047.5-1047.41" + wire \main_sdphy_cmdw_pads_out_payload_clk + attribute \src "ls180.v:1048.5-1048.43" + wire \main_sdphy_cmdw_pads_out_payload_cmd_o + attribute \src "ls180.v:1049.5-1049.44" + wire \main_sdphy_cmdw_pads_out_payload_cmd_oe + attribute \src "ls180.v:1050.11-1050.50" + wire width 4 \main_sdphy_cmdw_pads_out_payload_data_o + attribute \src "ls180.v:1051.5-1051.45" + wire \main_sdphy_cmdw_pads_out_payload_data_oe + attribute \src "ls180.v:1046.6-1046.36" + wire \main_sdphy_cmdw_pads_out_ready + attribute \src "ls180.v:1054.5-1054.30" + wire \main_sdphy_cmdw_sink_last + attribute \src "ls180.v:1055.11-1055.44" + wire width 8 \main_sdphy_cmdw_sink_payload_data + attribute \src "ls180.v:1053.5-1053.31" + wire \main_sdphy_cmdw_sink_ready + attribute \src "ls180.v:1052.5-1052.31" + wire \main_sdphy_cmdw_sink_valid + attribute \src "ls180.v:1241.11-1241.33" + wire width 10 \main_sdphy_datar_count + attribute \src "ls180.v:1774.11-1774.62" + wire width 10 \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 + attribute \src "ls180.v:1775.5-1775.59" + wire \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 + attribute \src "ls180.v:1281.6-1281.43" + wire \main_sdphy_datar_datar_buf_sink_first + attribute \src "ls180.v:1282.6-1282.42" + wire \main_sdphy_datar_datar_buf_sink_last + attribute \src "ls180.v:1283.12-1283.56" + wire width 8 \main_sdphy_datar_datar_buf_sink_payload_data + attribute \src "ls180.v:1280.6-1280.43" + wire \main_sdphy_datar_datar_buf_sink_ready + attribute \src "ls180.v:1279.6-1279.43" + wire \main_sdphy_datar_datar_buf_sink_valid + attribute \src "ls180.v:1286.5-1286.44" + wire \main_sdphy_datar_datar_buf_source_first + attribute \src "ls180.v:1287.5-1287.43" + wire \main_sdphy_datar_datar_buf_source_last + attribute \src "ls180.v:1288.11-1288.57" + wire width 8 \main_sdphy_datar_datar_buf_source_payload_data + attribute \src "ls180.v:1285.6-1285.45" + wire \main_sdphy_datar_datar_buf_source_ready + attribute \src "ls180.v:1284.5-1284.44" + wire \main_sdphy_datar_datar_buf_source_valid + attribute \src "ls180.v:1271.5-1271.43" + wire \main_sdphy_datar_datar_converter_demux + attribute \src "ls180.v:1272.6-1272.48" + wire \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:1262.5-1262.48" + wire \main_sdphy_datar_datar_converter_sink_first + attribute \src "ls180.v:1263.5-1263.47" + wire \main_sdphy_datar_datar_converter_sink_last + attribute \src "ls180.v:1264.12-1264.62" + wire width 4 \main_sdphy_datar_datar_converter_sink_payload_data + attribute \src "ls180.v:1261.6-1261.49" + wire \main_sdphy_datar_datar_converter_sink_ready + attribute \src "ls180.v:1260.6-1260.49" + wire \main_sdphy_datar_datar_converter_sink_valid + attribute \src "ls180.v:1267.5-1267.50" + wire \main_sdphy_datar_datar_converter_source_first + attribute \src "ls180.v:1268.5-1268.49" + wire \main_sdphy_datar_datar_converter_source_last + attribute \src "ls180.v:1269.11-1269.63" + wire width 8 \main_sdphy_datar_datar_converter_source_payload_data + attribute \src "ls180.v:1270.11-1270.76" + wire width 2 \main_sdphy_datar_datar_converter_source_payload_valid_token_count + attribute \src "ls180.v:1266.6-1266.51" + wire \main_sdphy_datar_datar_converter_source_ready + attribute \src "ls180.v:1265.6-1265.51" + wire \main_sdphy_datar_datar_converter_source_valid + attribute \src "ls180.v:1273.5-1273.48" + wire \main_sdphy_datar_datar_converter_strobe_all + attribute \src "ls180.v:1244.6-1244.42" + wire \main_sdphy_datar_datar_pads_in_first + attribute \src "ls180.v:1245.6-1245.41" + wire \main_sdphy_datar_datar_pads_in_last + attribute \src "ls180.v:1246.6-1246.48" + wire \main_sdphy_datar_datar_pads_in_payload_clk + attribute \src "ls180.v:1247.6-1247.50" + wire \main_sdphy_datar_datar_pads_in_payload_cmd_i + attribute \src "ls180.v:1248.6-1248.50" + wire \main_sdphy_datar_datar_pads_in_payload_cmd_o + attribute \src "ls180.v:1249.6-1249.51" + wire \main_sdphy_datar_datar_pads_in_payload_cmd_oe + attribute \src "ls180.v:1250.12-1250.57" + wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_i + attribute \src "ls180.v:1251.12-1251.57" + wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_o + attribute \src "ls180.v:1252.6-1252.52" + wire \main_sdphy_datar_datar_pads_in_payload_data_oe + attribute \src "ls180.v:1243.5-1243.41" + wire \main_sdphy_datar_datar_pads_in_ready + attribute \src "ls180.v:1242.6-1242.42" + wire \main_sdphy_datar_datar_pads_in_valid + attribute \src "ls180.v:1289.5-1289.33" + wire \main_sdphy_datar_datar_reset + attribute \src "ls180.v:1778.5-1778.62" + wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 + attribute \src "ls180.v:1779.5-1779.65" + wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 + attribute \src "ls180.v:1259.5-1259.31" + wire \main_sdphy_datar_datar_run + attribute \src "ls180.v:1255.6-1255.49" + wire \main_sdphy_datar_datar_source_source_first0 + attribute \src "ls180.v:1276.6-1276.49" + wire \main_sdphy_datar_datar_source_source_first1 + attribute \src "ls180.v:1256.6-1256.48" + wire \main_sdphy_datar_datar_source_source_last0 + attribute \src "ls180.v:1277.6-1277.48" + wire \main_sdphy_datar_datar_source_source_last1 + attribute \src "ls180.v:1257.12-1257.62" + wire width 8 \main_sdphy_datar_datar_source_source_payload_data0 + attribute \src "ls180.v:1278.12-1278.62" + wire width 8 \main_sdphy_datar_datar_source_source_payload_data1 + attribute \src "ls180.v:1254.5-1254.48" + wire \main_sdphy_datar_datar_source_source_ready0 + attribute \src "ls180.v:1275.6-1275.49" + wire \main_sdphy_datar_datar_source_source_ready1 + attribute \src "ls180.v:1253.6-1253.49" + wire \main_sdphy_datar_datar_source_source_valid0 + attribute \src "ls180.v:1274.6-1274.49" + wire \main_sdphy_datar_datar_source_source_valid1 + attribute \src "ls180.v:1258.6-1258.34" + wire \main_sdphy_datar_datar_start + attribute \src "ls180.v:1214.5-1214.43" + wire \main_sdphy_datar_pads_in_pads_in_first + attribute \src "ls180.v:1215.5-1215.42" + wire \main_sdphy_datar_pads_in_pads_in_last + attribute \src "ls180.v:1216.5-1216.49" + wire \main_sdphy_datar_pads_in_pads_in_payload_clk + attribute \src "ls180.v:1217.6-1217.52" + wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_i + attribute \src "ls180.v:1218.5-1218.51" + wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_o + attribute \src "ls180.v:1219.5-1219.52" + wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe + attribute \src "ls180.v:1220.12-1220.59" + wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_i + attribute \src "ls180.v:1221.11-1221.58" + wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_o + attribute \src "ls180.v:1222.5-1222.53" + wire \main_sdphy_datar_pads_in_pads_in_payload_data_oe + attribute \src "ls180.v:1213.6-1213.44" + wire \main_sdphy_datar_pads_in_pads_in_ready + attribute \src "ls180.v:1212.6-1212.44" + wire \main_sdphy_datar_pads_in_pads_in_valid + attribute \src "ls180.v:1224.5-1224.42" + wire \main_sdphy_datar_pads_out_payload_clk + attribute \src "ls180.v:1225.5-1225.44" + wire \main_sdphy_datar_pads_out_payload_cmd_o + attribute \src "ls180.v:1226.5-1226.45" + wire \main_sdphy_datar_pads_out_payload_cmd_oe + attribute \src "ls180.v:1227.11-1227.51" + wire width 4 \main_sdphy_datar_pads_out_payload_data_o + attribute \src "ls180.v:1228.5-1228.46" + wire \main_sdphy_datar_pads_out_payload_data_oe + attribute \src "ls180.v:1223.6-1223.37" + wire \main_sdphy_datar_pads_out_ready + attribute \src "ls180.v:1231.5-1231.31" + wire \main_sdphy_datar_sink_last + attribute \src "ls180.v:1232.11-1232.53" + wire width 10 \main_sdphy_datar_sink_payload_block_length + attribute \src "ls180.v:1230.5-1230.32" + wire \main_sdphy_datar_sink_ready + attribute \src "ls180.v:1229.5-1229.32" + wire \main_sdphy_datar_sink_valid + attribute \src "ls180.v:1235.5-1235.34" + wire \main_sdphy_datar_source_first + attribute \src "ls180.v:1236.5-1236.33" + wire \main_sdphy_datar_source_last + attribute \src "ls180.v:1237.11-1237.47" + wire width 8 \main_sdphy_datar_source_payload_data + attribute \src "ls180.v:1238.11-1238.49" + wire width 3 \main_sdphy_datar_source_payload_status + attribute \src "ls180.v:1234.5-1234.34" + wire \main_sdphy_datar_source_ready + attribute \src "ls180.v:1233.5-1233.34" + wire \main_sdphy_datar_source_valid + attribute \src "ls180.v:1239.5-1239.26" + wire \main_sdphy_datar_stop + attribute \src "ls180.v:1240.12-1240.36" + wire width 32 \main_sdphy_datar_timeout + attribute \src "ls180.v:1776.12-1776.65" + wire width 32 \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 + attribute \src "ls180.v:1777.5-1777.61" + wire \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 + attribute \src "ls180.v:1149.11-1149.33" + wire width 8 \main_sdphy_dataw_count + attribute \src "ls180.v:1770.11-1770.54" + wire width 8 \main_sdphy_dataw_count_sdphy_fsm_next_value + attribute \src "ls180.v:1771.5-1771.51" + wire \main_sdphy_dataw_count_sdphy_fsm_next_value_ce + attribute \src "ls180.v:1203.6-1203.42" + wire \main_sdphy_dataw_crcr_buf_sink_first + attribute \src "ls180.v:1204.6-1204.41" + wire \main_sdphy_dataw_crcr_buf_sink_last + attribute \src "ls180.v:1205.12-1205.55" + wire width 8 \main_sdphy_dataw_crcr_buf_sink_payload_data + attribute \src "ls180.v:1202.6-1202.42" + wire \main_sdphy_dataw_crcr_buf_sink_ready + attribute \src "ls180.v:1201.6-1201.42" + wire \main_sdphy_dataw_crcr_buf_sink_valid + attribute \src "ls180.v:1208.5-1208.43" + wire \main_sdphy_dataw_crcr_buf_source_first + attribute \src "ls180.v:1209.5-1209.42" + wire \main_sdphy_dataw_crcr_buf_source_last + attribute \src "ls180.v:1210.11-1210.56" + wire width 8 \main_sdphy_dataw_crcr_buf_source_payload_data + attribute \src "ls180.v:1207.6-1207.44" + wire \main_sdphy_dataw_crcr_buf_source_ready + attribute \src "ls180.v:1206.5-1206.43" + wire \main_sdphy_dataw_crcr_buf_source_valid + attribute \src "ls180.v:1193.11-1193.48" + wire width 3 \main_sdphy_dataw_crcr_converter_demux + attribute \src "ls180.v:1194.6-1194.47" + wire \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:1184.5-1184.47" + wire \main_sdphy_dataw_crcr_converter_sink_first + attribute \src "ls180.v:1185.5-1185.46" + wire \main_sdphy_dataw_crcr_converter_sink_last + attribute \src "ls180.v:1186.6-1186.55" + wire \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:1183.6-1183.48" + wire \main_sdphy_dataw_crcr_converter_sink_ready + attribute \src "ls180.v:1182.6-1182.48" + wire \main_sdphy_dataw_crcr_converter_sink_valid + attribute \src "ls180.v:1189.5-1189.49" + wire \main_sdphy_dataw_crcr_converter_source_first + attribute \src "ls180.v:1190.5-1190.48" + wire \main_sdphy_dataw_crcr_converter_source_last + attribute \src "ls180.v:1191.11-1191.62" + wire width 8 \main_sdphy_dataw_crcr_converter_source_payload_data + attribute \src "ls180.v:1192.11-1192.75" + wire width 4 \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count + attribute \src "ls180.v:1188.6-1188.50" + wire \main_sdphy_dataw_crcr_converter_source_ready + attribute \src "ls180.v:1187.6-1187.50" + wire \main_sdphy_dataw_crcr_converter_source_valid + attribute \src "ls180.v:1195.5-1195.47" + wire \main_sdphy_dataw_crcr_converter_strobe_all + attribute \src "ls180.v:1166.6-1166.41" + wire \main_sdphy_dataw_crcr_pads_in_first + attribute \src "ls180.v:1167.6-1167.40" + wire \main_sdphy_dataw_crcr_pads_in_last + attribute \src "ls180.v:1168.6-1168.47" + wire \main_sdphy_dataw_crcr_pads_in_payload_clk + attribute \src "ls180.v:1169.6-1169.49" + wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_i + attribute \src "ls180.v:1170.6-1170.49" + wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_o + attribute \src "ls180.v:1171.6-1171.50" + wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe + attribute \src "ls180.v:1172.12-1172.56" + wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_i + attribute \src "ls180.v:1173.12-1173.56" + wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_o + attribute \src "ls180.v:1174.6-1174.51" + wire \main_sdphy_dataw_crcr_pads_in_payload_data_oe + attribute \src "ls180.v:1165.5-1165.40" + wire \main_sdphy_dataw_crcr_pads_in_ready + attribute \src "ls180.v:1164.6-1164.41" + wire \main_sdphy_dataw_crcr_pads_in_valid + attribute \src "ls180.v:1211.5-1211.32" + wire \main_sdphy_dataw_crcr_reset + attribute \src "ls180.v:1766.5-1766.59" + wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value + attribute \src "ls180.v:1767.5-1767.62" + wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce + attribute \src "ls180.v:1181.5-1181.30" + wire \main_sdphy_dataw_crcr_run + attribute \src "ls180.v:1177.6-1177.48" + wire \main_sdphy_dataw_crcr_source_source_first0 + attribute \src "ls180.v:1198.6-1198.48" + wire \main_sdphy_dataw_crcr_source_source_first1 + attribute \src "ls180.v:1178.6-1178.47" + wire \main_sdphy_dataw_crcr_source_source_last0 + attribute \src "ls180.v:1199.6-1199.47" + wire \main_sdphy_dataw_crcr_source_source_last1 + attribute \src "ls180.v:1179.12-1179.61" + wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data0 + attribute \src "ls180.v:1200.12-1200.61" + wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data1 + attribute \src "ls180.v:1176.5-1176.47" + wire \main_sdphy_dataw_crcr_source_source_ready0 + attribute \src "ls180.v:1197.6-1197.48" + wire \main_sdphy_dataw_crcr_source_source_ready1 + attribute \src "ls180.v:1175.6-1175.48" + wire \main_sdphy_dataw_crcr_source_source_valid0 + attribute \src "ls180.v:1196.6-1196.48" + wire \main_sdphy_dataw_crcr_source_source_valid1 + attribute \src "ls180.v:1180.6-1180.33" + wire \main_sdphy_dataw_crcr_start + attribute \src "ls180.v:1163.5-1163.27" + wire \main_sdphy_dataw_error + attribute \src "ls180.v:1152.5-1152.43" + wire \main_sdphy_dataw_pads_in_pads_in_first + attribute \src "ls180.v:1153.5-1153.42" + wire \main_sdphy_dataw_pads_in_pads_in_last + attribute \src "ls180.v:1154.5-1154.49" + wire \main_sdphy_dataw_pads_in_pads_in_payload_clk + attribute \src "ls180.v:1155.5-1155.51" + wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i + attribute \src "ls180.v:1156.5-1156.51" + wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o + attribute \src "ls180.v:1157.5-1157.52" + wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe + attribute \src "ls180.v:1158.11-1158.58" + wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_i + attribute \src "ls180.v:1159.11-1159.58" + wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_o + attribute \src "ls180.v:1160.5-1160.53" + wire \main_sdphy_dataw_pads_in_pads_in_payload_data_oe + attribute \src "ls180.v:1151.6-1151.44" + wire \main_sdphy_dataw_pads_in_pads_in_ready + attribute \src "ls180.v:1150.5-1150.43" + wire \main_sdphy_dataw_pads_in_pads_in_valid + attribute \src "ls180.v:1135.6-1135.44" + wire \main_sdphy_dataw_pads_in_payload_cmd_i + attribute \src "ls180.v:1136.12-1136.51" + wire width 4 \main_sdphy_dataw_pads_in_payload_data_i + attribute \src "ls180.v:1134.6-1134.36" + wire \main_sdphy_dataw_pads_in_valid + attribute \src "ls180.v:1138.5-1138.42" + wire \main_sdphy_dataw_pads_out_payload_clk + attribute \src "ls180.v:1139.5-1139.44" + wire \main_sdphy_dataw_pads_out_payload_cmd_o + attribute \src "ls180.v:1140.5-1140.45" + wire \main_sdphy_dataw_pads_out_payload_cmd_oe + attribute \src "ls180.v:1141.11-1141.51" + wire width 4 \main_sdphy_dataw_pads_out_payload_data_o + attribute \src "ls180.v:1142.5-1142.46" + wire \main_sdphy_dataw_pads_out_payload_data_oe + attribute \src "ls180.v:1137.6-1137.37" + wire \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:1145.5-1145.32" + wire \main_sdphy_dataw_sink_first + attribute \src "ls180.v:1146.5-1146.31" + wire \main_sdphy_dataw_sink_last + attribute \src "ls180.v:1147.11-1147.45" + wire width 8 \main_sdphy_dataw_sink_payload_data + attribute \src "ls180.v:1144.5-1144.32" + wire \main_sdphy_dataw_sink_ready + attribute \src "ls180.v:1143.5-1143.32" + wire \main_sdphy_dataw_sink_valid + attribute \src "ls180.v:1161.5-1161.27" + wire \main_sdphy_dataw_start + attribute \src "ls180.v:1148.5-1148.26" + wire \main_sdphy_dataw_stop + attribute \src "ls180.v:1162.5-1162.27" + wire \main_sdphy_dataw_valid + attribute \src "ls180.v:1042.11-1042.32" + wire width 8 \main_sdphy_init_count + attribute \src "ls180.v:1750.11-1750.59" + wire width 8 \main_sdphy_init_count_sdphy_sdphyinit_next_value + attribute \src "ls180.v:1751.5-1751.56" + wire \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce + attribute \src "ls180.v:1030.6-1030.34" + wire \main_sdphy_init_initialize_r + attribute \src "ls180.v:1029.6-1029.35" + wire \main_sdphy_init_initialize_re + attribute \src "ls180.v:1032.5-1032.33" + wire \main_sdphy_init_initialize_w + attribute \src "ls180.v:1031.6-1031.35" + wire \main_sdphy_init_initialize_we + attribute \src "ls180.v:1034.6-1034.43" + wire \main_sdphy_init_pads_in_payload_cmd_i + attribute \src "ls180.v:1035.12-1035.50" + wire width 4 \main_sdphy_init_pads_in_payload_data_i + attribute \src "ls180.v:1033.6-1033.35" + wire \main_sdphy_init_pads_in_valid + attribute \src "ls180.v:1037.5-1037.41" + wire \main_sdphy_init_pads_out_payload_clk + attribute \src "ls180.v:1038.5-1038.43" + wire \main_sdphy_init_pads_out_payload_cmd_o + attribute \src "ls180.v:1039.5-1039.44" + wire \main_sdphy_init_pads_out_payload_cmd_oe + attribute \src "ls180.v:1040.11-1040.50" + wire width 4 \main_sdphy_init_pads_out_payload_data_o + attribute \src "ls180.v:1041.5-1041.45" + wire \main_sdphy_init_pads_out_payload_data_oe + attribute \src "ls180.v:1036.6-1036.36" + wire \main_sdphy_init_pads_out_ready + attribute \src "ls180.v:1290.6-1290.27" + wire \main_sdphy_sdpads_clk + attribute \src "ls180.v:1291.5-1291.28" + wire \main_sdphy_sdpads_cmd_i + attribute \src "ls180.v:1292.6-1292.29" + wire \main_sdphy_sdpads_cmd_o + attribute \src "ls180.v:1293.6-1293.30" + wire \main_sdphy_sdpads_cmd_oe + attribute \src "ls180.v:1294.11-1294.35" + wire width 4 \main_sdphy_sdpads_data_i + attribute \src "ls180.v:1295.12-1295.36" + wire width 4 \main_sdphy_sdpads_data_o + attribute \src "ls180.v:1296.6-1296.31" + wire \main_sdphy_sdpads_data_oe + attribute \src "ls180.v:1019.6-1019.23" + wire \main_sdphy_status + attribute \src "ls180.v:1020.6-1020.19" + wire \main_sdphy_we + attribute \src "ls180.v:300.5-300.26" + wire \main_sdram_address_re + attribute \src "ls180.v:299.12-299.38" + wire width 13 \main_sdram_address_storage + attribute \src "ls180.v:302.5-302.27" + wire \main_sdram_baddress_re + attribute \src "ls180.v:301.11-301.38" + wire width 2 \main_sdram_baddress_storage + attribute \src "ls180.v:398.5-398.43" + wire \main_sdram_bankmachine0_auto_precharge + attribute \src "ls180.v:420.11-420.63" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + attribute \src "ls180.v:425.6-425.58" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:430.6-430.64" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:431.6-431.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:429.13-429.78" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:428.6-428.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:434.6-434.65" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:435.6-435.64" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:433.13-433.79" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:432.6-432.70" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:417.11-417.61" + wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level + attribute \src "ls180.v:419.11-419.63" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + attribute \src "ls180.v:426.12-426.67" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:427.13-427.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:418.5-418.57" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + attribute \src "ls180.v:401.5-401.60" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:402.5-402.59" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:404.13-404.75" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:403.6-403.66" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:400.6-400.61" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:399.6-399.61" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:407.6-407.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:408.6-408.62" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:410.13-410.77" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:409.6-409.68" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:406.6-406.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:405.6-405.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:415.13-415.71" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din + attribute \src "ls180.v:416.13-416.72" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout + attribute \src "ls180.v:413.6-413.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re + attribute \src "ls180.v:414.6-414.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + attribute \src "ls180.v:411.6-411.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + attribute \src "ls180.v:412.6-412.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + attribute \src "ls180.v:421.11-421.66" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:422.13-422.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:424.13-424.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:423.6-423.60" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:438.6-438.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_first + attribute \src "ls180.v:439.6-439.50" + wire \main_sdram_bankmachine0_cmd_buffer_sink_last + attribute \src "ls180.v:441.13-441.65" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:440.6-440.56" + wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we + attribute \src "ls180.v:437.6-437.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_ready + attribute \src "ls180.v:436.6-436.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_valid + attribute \src "ls180.v:444.5-444.52" + wire \main_sdram_bankmachine0_cmd_buffer_source_first + attribute \src "ls180.v:445.5-445.51" + wire \main_sdram_bankmachine0_cmd_buffer_source_last + attribute \src "ls180.v:447.12-447.66" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr + attribute \src "ls180.v:446.5-446.57" + wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we + attribute \src "ls180.v:443.6-443.53" + wire \main_sdram_bankmachine0_cmd_buffer_source_ready + attribute \src "ls180.v:442.5-442.52" + wire \main_sdram_bankmachine0_cmd_buffer_source_valid + attribute \src "ls180.v:390.12-390.49" + wire width 13 \main_sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:391.12-391.50" + wire width 2 \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:392.5-392.44" + wire \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:395.5-395.47" + wire \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:396.5-396.48" + wire \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:397.5-397.49" + wire \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:393.5-393.44" + wire \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:394.5-394.43" + wire \main_sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:389.5-389.38" + wire \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:388.5-388.38" + wire \main_sdram_bankmachine0_cmd_valid + attribute \src "ls180.v:387.5-387.40" + wire \main_sdram_bankmachine0_refresh_gnt + attribute \src "ls180.v:386.6-386.41" + wire \main_sdram_bankmachine0_refresh_req + attribute \src "ls180.v:382.13-382.45" + wire width 22 \main_sdram_bankmachine0_req_addr + attribute \src "ls180.v:383.6-383.38" + wire \main_sdram_bankmachine0_req_lock + attribute \src "ls180.v:385.5-385.44" + wire \main_sdram_bankmachine0_req_rdata_valid + attribute \src "ls180.v:380.6-380.39" + wire \main_sdram_bankmachine0_req_ready + attribute \src "ls180.v:379.6-379.39" + wire \main_sdram_bankmachine0_req_valid + attribute \src "ls180.v:384.5-384.44" + wire \main_sdram_bankmachine0_req_wdata_ready + attribute \src "ls180.v:381.6-381.36" + wire \main_sdram_bankmachine0_req_we + attribute \src "ls180.v:448.12-448.39" + wire width 13 \main_sdram_bankmachine0_row + attribute \src "ls180.v:452.5-452.38" + wire \main_sdram_bankmachine0_row_close + attribute \src "ls180.v:453.5-453.47" + wire \main_sdram_bankmachine0_row_col_n_addr_sel + attribute \src "ls180.v:450.6-450.37" + wire \main_sdram_bankmachine0_row_hit + attribute \src "ls180.v:451.5-451.37" + wire \main_sdram_bankmachine0_row_open + attribute \src "ls180.v:449.5-449.39" + wire \main_sdram_bankmachine0_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:460.32-460.69" + wire \main_sdram_bankmachine0_trascon_ready + attribute \src "ls180.v:459.6-459.43" + wire \main_sdram_bankmachine0_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:458.32-458.68" + wire \main_sdram_bankmachine0_trccon_ready + attribute \src "ls180.v:457.6-457.42" + wire \main_sdram_bankmachine0_trccon_valid + attribute \src "ls180.v:456.11-456.48" + wire width 3 \main_sdram_bankmachine0_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:455.32-455.69" + wire \main_sdram_bankmachine0_twtpcon_ready + attribute \src "ls180.v:454.6-454.43" + wire \main_sdram_bankmachine0_twtpcon_valid + attribute \src "ls180.v:480.5-480.43" + wire \main_sdram_bankmachine1_auto_precharge + attribute \src "ls180.v:502.11-502.63" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + attribute \src "ls180.v:507.6-507.58" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:512.6-512.64" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:513.6-513.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:511.13-511.78" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:510.6-510.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:516.6-516.65" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:517.6-517.64" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:515.13-515.79" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:514.6-514.70" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:499.11-499.61" + wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level + attribute \src "ls180.v:501.11-501.63" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + attribute \src "ls180.v:508.12-508.67" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:509.13-509.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:500.5-500.57" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + attribute \src "ls180.v:483.5-483.60" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:484.5-484.59" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:486.13-486.75" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:485.6-485.66" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:482.6-482.61" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:481.6-481.61" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:489.6-489.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:490.6-490.62" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:492.13-492.77" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:491.6-491.68" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:488.6-488.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:487.6-487.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:497.13-497.71" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din + attribute \src "ls180.v:498.13-498.72" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout + attribute \src "ls180.v:495.6-495.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re + attribute \src "ls180.v:496.6-496.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + attribute \src "ls180.v:493.6-493.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + attribute \src "ls180.v:494.6-494.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + attribute \src "ls180.v:503.11-503.66" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:504.13-504.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:506.13-506.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:505.6-505.60" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:520.6-520.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_first + attribute \src "ls180.v:521.6-521.50" + wire \main_sdram_bankmachine1_cmd_buffer_sink_last + attribute \src "ls180.v:523.13-523.65" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:522.6-522.56" + wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we + attribute \src "ls180.v:519.6-519.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_ready + attribute \src "ls180.v:518.6-518.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_valid + attribute \src "ls180.v:526.5-526.52" + wire \main_sdram_bankmachine1_cmd_buffer_source_first + attribute \src "ls180.v:527.5-527.51" + wire \main_sdram_bankmachine1_cmd_buffer_source_last + attribute \src "ls180.v:529.12-529.66" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr + attribute \src "ls180.v:528.5-528.57" + wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we + attribute \src "ls180.v:525.6-525.53" + wire \main_sdram_bankmachine1_cmd_buffer_source_ready + attribute \src "ls180.v:524.5-524.52" + wire \main_sdram_bankmachine1_cmd_buffer_source_valid + attribute \src "ls180.v:472.12-472.49" + wire width 13 \main_sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:473.12-473.50" + wire width 2 \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:474.5-474.44" + wire \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:477.5-477.47" + wire \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:478.5-478.48" + wire \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:479.5-479.49" + wire \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:475.5-475.44" + wire \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:476.5-476.43" + wire \main_sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:471.5-471.38" + wire \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:470.5-470.38" + wire \main_sdram_bankmachine1_cmd_valid + attribute \src "ls180.v:469.5-469.40" + wire \main_sdram_bankmachine1_refresh_gnt + attribute \src "ls180.v:468.6-468.41" + wire \main_sdram_bankmachine1_refresh_req + attribute \src "ls180.v:464.13-464.45" + wire width 22 \main_sdram_bankmachine1_req_addr + attribute \src "ls180.v:465.6-465.38" + wire \main_sdram_bankmachine1_req_lock + attribute \src "ls180.v:467.5-467.44" + wire \main_sdram_bankmachine1_req_rdata_valid + attribute \src "ls180.v:462.6-462.39" + wire \main_sdram_bankmachine1_req_ready + attribute \src "ls180.v:461.6-461.39" + wire \main_sdram_bankmachine1_req_valid + attribute \src "ls180.v:466.5-466.44" + wire \main_sdram_bankmachine1_req_wdata_ready + attribute \src "ls180.v:463.6-463.36" + wire \main_sdram_bankmachine1_req_we + attribute \src "ls180.v:530.12-530.39" + wire width 13 \main_sdram_bankmachine1_row + attribute \src "ls180.v:534.5-534.38" + wire \main_sdram_bankmachine1_row_close + attribute \src "ls180.v:535.5-535.47" + wire \main_sdram_bankmachine1_row_col_n_addr_sel + attribute \src "ls180.v:532.6-532.37" + wire \main_sdram_bankmachine1_row_hit + attribute \src "ls180.v:533.5-533.37" + wire \main_sdram_bankmachine1_row_open + attribute \src "ls180.v:531.5-531.39" + wire \main_sdram_bankmachine1_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:542.32-542.69" + wire \main_sdram_bankmachine1_trascon_ready + attribute \src "ls180.v:541.6-541.43" + wire \main_sdram_bankmachine1_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:540.32-540.68" + wire \main_sdram_bankmachine1_trccon_ready + attribute \src "ls180.v:539.6-539.42" + wire \main_sdram_bankmachine1_trccon_valid + attribute \src "ls180.v:538.11-538.48" + wire width 3 \main_sdram_bankmachine1_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:537.32-537.69" + wire \main_sdram_bankmachine1_twtpcon_ready + attribute \src "ls180.v:536.6-536.43" + wire \main_sdram_bankmachine1_twtpcon_valid + attribute \src "ls180.v:562.5-562.43" + wire \main_sdram_bankmachine2_auto_precharge + attribute \src "ls180.v:584.11-584.63" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + attribute \src "ls180.v:589.6-589.58" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:594.6-594.64" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:595.6-595.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:593.13-593.78" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:592.6-592.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:598.6-598.65" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:599.6-599.64" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:597.13-597.79" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:596.6-596.70" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:581.11-581.61" + wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level + attribute \src "ls180.v:583.11-583.63" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + attribute \src "ls180.v:590.12-590.67" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:591.13-591.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:582.5-582.57" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + attribute \src "ls180.v:565.5-565.60" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:566.5-566.59" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:568.13-568.75" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:567.6-567.66" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:564.6-564.61" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:563.6-563.61" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:571.6-571.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:572.6-572.62" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:574.13-574.77" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:573.6-573.68" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:570.6-570.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:569.6-569.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:579.13-579.71" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din + attribute \src "ls180.v:580.13-580.72" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout + attribute \src "ls180.v:577.6-577.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re + attribute \src "ls180.v:578.6-578.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + attribute \src "ls180.v:575.6-575.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + attribute \src "ls180.v:576.6-576.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + attribute \src "ls180.v:585.11-585.66" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:586.13-586.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:588.13-588.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:587.6-587.60" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:602.6-602.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_first + attribute \src "ls180.v:603.6-603.50" + wire \main_sdram_bankmachine2_cmd_buffer_sink_last + attribute \src "ls180.v:605.13-605.65" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:604.6-604.56" + wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we + attribute \src "ls180.v:601.6-601.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_ready + attribute \src "ls180.v:600.6-600.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_valid + attribute \src "ls180.v:608.5-608.52" + wire \main_sdram_bankmachine2_cmd_buffer_source_first + attribute \src "ls180.v:609.5-609.51" + wire \main_sdram_bankmachine2_cmd_buffer_source_last + attribute \src "ls180.v:611.12-611.66" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr + attribute \src "ls180.v:610.5-610.57" + wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we + attribute \src "ls180.v:607.6-607.53" + wire \main_sdram_bankmachine2_cmd_buffer_source_ready + attribute \src "ls180.v:606.5-606.52" + wire \main_sdram_bankmachine2_cmd_buffer_source_valid + attribute \src "ls180.v:554.12-554.49" + wire width 13 \main_sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:555.12-555.50" + wire width 2 \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:556.5-556.44" + wire \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:559.5-559.47" + wire \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:560.5-560.48" + wire \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:561.5-561.49" + wire \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:557.5-557.44" + wire \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:558.5-558.43" + wire \main_sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:553.5-553.38" + wire \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:552.5-552.38" + wire \main_sdram_bankmachine2_cmd_valid + attribute \src "ls180.v:551.5-551.40" + wire \main_sdram_bankmachine2_refresh_gnt + attribute \src "ls180.v:550.6-550.41" + wire \main_sdram_bankmachine2_refresh_req + attribute \src "ls180.v:546.13-546.45" + wire width 22 \main_sdram_bankmachine2_req_addr + attribute \src "ls180.v:547.6-547.38" + wire \main_sdram_bankmachine2_req_lock + attribute \src "ls180.v:549.5-549.44" + wire \main_sdram_bankmachine2_req_rdata_valid + attribute \src "ls180.v:544.6-544.39" + wire \main_sdram_bankmachine2_req_ready + attribute \src "ls180.v:543.6-543.39" + wire \main_sdram_bankmachine2_req_valid + attribute \src "ls180.v:548.5-548.44" + wire \main_sdram_bankmachine2_req_wdata_ready + attribute \src "ls180.v:545.6-545.36" + wire \main_sdram_bankmachine2_req_we + attribute \src "ls180.v:612.12-612.39" + wire width 13 \main_sdram_bankmachine2_row + attribute \src "ls180.v:616.5-616.38" + wire \main_sdram_bankmachine2_row_close + attribute \src "ls180.v:617.5-617.47" + wire \main_sdram_bankmachine2_row_col_n_addr_sel + attribute \src "ls180.v:614.6-614.37" + wire \main_sdram_bankmachine2_row_hit + attribute \src "ls180.v:615.5-615.37" + wire \main_sdram_bankmachine2_row_open + attribute \src "ls180.v:613.5-613.39" + wire \main_sdram_bankmachine2_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:624.32-624.69" + wire \main_sdram_bankmachine2_trascon_ready + attribute \src "ls180.v:623.6-623.43" + wire \main_sdram_bankmachine2_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:622.32-622.68" + wire \main_sdram_bankmachine2_trccon_ready + attribute \src "ls180.v:621.6-621.42" + wire \main_sdram_bankmachine2_trccon_valid + attribute \src "ls180.v:620.11-620.48" + wire width 3 \main_sdram_bankmachine2_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:619.32-619.69" + wire \main_sdram_bankmachine2_twtpcon_ready + attribute \src "ls180.v:618.6-618.43" + wire \main_sdram_bankmachine2_twtpcon_valid + attribute \src "ls180.v:644.5-644.43" + wire \main_sdram_bankmachine3_auto_precharge + attribute \src "ls180.v:666.11-666.63" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + attribute \src "ls180.v:671.6-671.58" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:676.6-676.64" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:677.6-677.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:675.13-675.78" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:674.6-674.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:680.6-680.65" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:681.6-681.64" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:679.13-679.79" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:678.6-678.70" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:663.11-663.61" + wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level + attribute \src "ls180.v:665.11-665.63" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + attribute \src "ls180.v:672.12-672.67" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:673.13-673.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:664.5-664.57" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + attribute \src "ls180.v:647.5-647.60" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:648.5-648.59" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:650.13-650.75" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:649.6-649.66" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:646.6-646.61" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:645.6-645.61" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:653.6-653.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:654.6-654.62" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:656.13-656.77" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:655.6-655.68" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:652.6-652.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:651.6-651.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:661.13-661.71" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din + attribute \src "ls180.v:662.13-662.72" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout + attribute \src "ls180.v:659.6-659.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re + attribute \src "ls180.v:660.6-660.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + attribute \src "ls180.v:657.6-657.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + attribute \src "ls180.v:658.6-658.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + attribute \src "ls180.v:667.11-667.66" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:668.13-668.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:670.13-670.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:669.6-669.60" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:684.6-684.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_first + attribute \src "ls180.v:685.6-685.50" + wire \main_sdram_bankmachine3_cmd_buffer_sink_last + attribute \src "ls180.v:687.13-687.65" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:686.6-686.56" + wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we + attribute \src "ls180.v:683.6-683.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_ready + attribute \src "ls180.v:682.6-682.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_valid + attribute \src "ls180.v:690.5-690.52" + wire \main_sdram_bankmachine3_cmd_buffer_source_first + attribute \src "ls180.v:691.5-691.51" + wire \main_sdram_bankmachine3_cmd_buffer_source_last + attribute \src "ls180.v:693.12-693.66" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr + attribute \src "ls180.v:692.5-692.57" + wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we + attribute \src "ls180.v:689.6-689.53" + wire \main_sdram_bankmachine3_cmd_buffer_source_ready + attribute \src "ls180.v:688.5-688.52" + wire \main_sdram_bankmachine3_cmd_buffer_source_valid + attribute \src "ls180.v:636.12-636.49" + wire width 13 \main_sdram_bankmachine3_cmd_payload_a + attribute \src "ls180.v:637.12-637.50" + wire width 2 \main_sdram_bankmachine3_cmd_payload_ba + attribute \src "ls180.v:638.5-638.44" + wire \main_sdram_bankmachine3_cmd_payload_cas + attribute \src "ls180.v:641.5-641.47" + wire \main_sdram_bankmachine3_cmd_payload_is_cmd + attribute \src "ls180.v:642.5-642.48" + wire \main_sdram_bankmachine3_cmd_payload_is_read + attribute \src "ls180.v:643.5-643.49" + wire \main_sdram_bankmachine3_cmd_payload_is_write + attribute \src "ls180.v:639.5-639.44" + wire \main_sdram_bankmachine3_cmd_payload_ras + attribute \src "ls180.v:640.5-640.43" + wire \main_sdram_bankmachine3_cmd_payload_we + attribute \src "ls180.v:635.5-635.38" + wire \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:634.5-634.38" + wire \main_sdram_bankmachine3_cmd_valid + attribute \src "ls180.v:633.5-633.40" + wire \main_sdram_bankmachine3_refresh_gnt + attribute \src "ls180.v:632.6-632.41" + wire \main_sdram_bankmachine3_refresh_req + attribute \src "ls180.v:628.13-628.45" + wire width 22 \main_sdram_bankmachine3_req_addr + attribute \src "ls180.v:629.6-629.38" + wire \main_sdram_bankmachine3_req_lock + attribute \src "ls180.v:631.5-631.44" + wire \main_sdram_bankmachine3_req_rdata_valid + attribute \src "ls180.v:626.6-626.39" + wire \main_sdram_bankmachine3_req_ready + attribute \src "ls180.v:625.6-625.39" + wire \main_sdram_bankmachine3_req_valid + attribute \src "ls180.v:630.5-630.44" + wire \main_sdram_bankmachine3_req_wdata_ready + attribute \src "ls180.v:627.6-627.36" + wire \main_sdram_bankmachine3_req_we + attribute \src "ls180.v:694.12-694.39" + wire width 13 \main_sdram_bankmachine3_row + attribute \src "ls180.v:698.5-698.38" + wire \main_sdram_bankmachine3_row_close + attribute \src "ls180.v:699.5-699.47" + wire \main_sdram_bankmachine3_row_col_n_addr_sel + attribute \src "ls180.v:696.6-696.37" + wire \main_sdram_bankmachine3_row_hit + attribute \src "ls180.v:697.5-697.37" + wire \main_sdram_bankmachine3_row_open + attribute \src "ls180.v:695.5-695.39" + wire \main_sdram_bankmachine3_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:706.32-706.69" + wire \main_sdram_bankmachine3_trascon_ready + attribute \src "ls180.v:705.6-705.43" + wire \main_sdram_bankmachine3_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:704.32-704.68" + wire \main_sdram_bankmachine3_trccon_ready + attribute \src "ls180.v:703.6-703.42" + wire \main_sdram_bankmachine3_trccon_valid + attribute \src "ls180.v:702.11-702.48" + wire width 3 \main_sdram_bankmachine3_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:701.32-701.69" + wire \main_sdram_bankmachine3_twtpcon_ready + attribute \src "ls180.v:700.6-700.43" + wire \main_sdram_bankmachine3_twtpcon_valid + attribute \src "ls180.v:708.6-708.28" + wire \main_sdram_cas_allowed + attribute \src "ls180.v:726.6-726.30" + wire \main_sdram_choose_cmd_ce + attribute \src "ls180.v:715.13-715.48" + wire width 13 \main_sdram_choose_cmd_cmd_payload_a + attribute \src "ls180.v:716.12-716.48" + wire width 2 \main_sdram_choose_cmd_cmd_payload_ba + attribute \src "ls180.v:717.5-717.42" + wire \main_sdram_choose_cmd_cmd_payload_cas + attribute \src "ls180.v:720.6-720.46" + wire \main_sdram_choose_cmd_cmd_payload_is_cmd + attribute \src "ls180.v:721.6-721.47" + wire \main_sdram_choose_cmd_cmd_payload_is_read + attribute \src "ls180.v:722.6-722.48" + wire \main_sdram_choose_cmd_cmd_payload_is_write + attribute \src "ls180.v:718.5-718.42" + wire \main_sdram_choose_cmd_cmd_payload_ras + attribute \src "ls180.v:719.5-719.41" + wire \main_sdram_choose_cmd_cmd_payload_we + attribute \src "ls180.v:714.5-714.36" + wire \main_sdram_choose_cmd_cmd_ready + attribute \src "ls180.v:713.6-713.37" + wire \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:725.11-725.38" + wire width 2 \main_sdram_choose_cmd_grant + attribute \src "ls180.v:724.12-724.41" + wire width 4 \main_sdram_choose_cmd_request + attribute \src "ls180.v:723.11-723.39" + wire width 4 \main_sdram_choose_cmd_valids + attribute \src "ls180.v:712.5-712.41" + wire \main_sdram_choose_cmd_want_activates + attribute \src "ls180.v:711.5-711.36" + wire \main_sdram_choose_cmd_want_cmds + attribute \src "ls180.v:709.5-709.37" + wire \main_sdram_choose_cmd_want_reads + attribute \src "ls180.v:710.5-710.38" + wire \main_sdram_choose_cmd_want_writes + attribute \src "ls180.v:744.6-744.30" + wire \main_sdram_choose_req_ce + attribute \src "ls180.v:733.13-733.48" + wire width 13 \main_sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:734.12-734.48" + wire width 2 \main_sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:735.5-735.42" + wire \main_sdram_choose_req_cmd_payload_cas + attribute \src "ls180.v:738.6-738.46" + wire \main_sdram_choose_req_cmd_payload_is_cmd + attribute \src "ls180.v:739.6-739.47" + wire \main_sdram_choose_req_cmd_payload_is_read + attribute \src "ls180.v:740.6-740.48" + wire \main_sdram_choose_req_cmd_payload_is_write + attribute \src "ls180.v:736.5-736.42" + wire \main_sdram_choose_req_cmd_payload_ras + attribute \src "ls180.v:737.5-737.41" + wire \main_sdram_choose_req_cmd_payload_we + attribute \src "ls180.v:732.5-732.36" + wire \main_sdram_choose_req_cmd_ready + attribute \src "ls180.v:731.6-731.37" + wire \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:743.11-743.38" + wire width 2 \main_sdram_choose_req_grant + attribute \src "ls180.v:742.12-742.41" + wire width 4 \main_sdram_choose_req_request + attribute \src "ls180.v:741.11-741.39" + wire width 4 \main_sdram_choose_req_valids + attribute \src "ls180.v:730.5-730.41" + wire \main_sdram_choose_req_want_activates + attribute \src "ls180.v:729.6-729.37" + wire \main_sdram_choose_req_want_cmds + attribute \src "ls180.v:727.5-727.37" + wire \main_sdram_choose_req_want_reads + attribute \src "ls180.v:728.5-728.38" + wire \main_sdram_choose_req_want_writes + attribute \src "ls180.v:288.6-288.20" + wire \main_sdram_cke + attribute \src "ls180.v:356.5-356.24" + wire \main_sdram_cmd_last + attribute \src "ls180.v:357.12-357.36" + wire width 13 \main_sdram_cmd_payload_a + attribute \src "ls180.v:358.11-358.36" + wire width 2 \main_sdram_cmd_payload_ba + attribute \src "ls180.v:359.5-359.31" + wire \main_sdram_cmd_payload_cas + attribute \src "ls180.v:362.5-362.35" + wire \main_sdram_cmd_payload_is_read + attribute \src "ls180.v:363.5-363.36" + wire \main_sdram_cmd_payload_is_write + attribute \src "ls180.v:360.5-360.31" + wire \main_sdram_cmd_payload_ras + attribute \src "ls180.v:361.5-361.30" + wire \main_sdram_cmd_payload_we + attribute \src "ls180.v:355.5-355.25" + wire \main_sdram_cmd_ready + attribute \src "ls180.v:354.5-354.25" + wire \main_sdram_cmd_valid + attribute \src "ls180.v:296.6-296.32" + wire \main_sdram_command_issue_r + attribute \src "ls180.v:295.6-295.33" + wire \main_sdram_command_issue_re + attribute \src "ls180.v:298.5-298.31" + wire \main_sdram_command_issue_w + attribute \src "ls180.v:297.6-297.33" + wire \main_sdram_command_issue_we + attribute \src "ls180.v:294.5-294.26" + wire \main_sdram_command_re + attribute \src "ls180.v:293.11-293.37" + wire width 6 \main_sdram_command_storage + attribute \src "ls180.v:347.5-347.28" + wire \main_sdram_dfi_p0_act_n + attribute \src "ls180.v:338.12-338.37" + wire width 13 \main_sdram_dfi_p0_address + attribute \src "ls180.v:339.11-339.33" + wire width 2 \main_sdram_dfi_p0_bank + attribute \src "ls180.v:340.5-340.28" + wire \main_sdram_dfi_p0_cas_n + attribute \src "ls180.v:344.6-344.27" + wire \main_sdram_dfi_p0_cke + attribute \src "ls180.v:341.5-341.27" + wire \main_sdram_dfi_p0_cs_n + attribute \src "ls180.v:345.6-345.27" + wire \main_sdram_dfi_p0_odt + attribute \src "ls180.v:342.5-342.28" + wire \main_sdram_dfi_p0_ras_n + attribute \src "ls180.v:352.13-352.37" + wire width 16 \main_sdram_dfi_p0_rddata + attribute \src "ls180.v:351.5-351.32" + wire \main_sdram_dfi_p0_rddata_en + attribute \src "ls180.v:353.6-353.36" + wire \main_sdram_dfi_p0_rddata_valid + attribute \src "ls180.v:346.6-346.31" + wire \main_sdram_dfi_p0_reset_n + attribute \src "ls180.v:343.5-343.27" + wire \main_sdram_dfi_p0_we_n + attribute \src "ls180.v:348.13-348.37" + wire width 16 \main_sdram_dfi_p0_wrdata + attribute \src "ls180.v:349.5-349.32" + wire \main_sdram_dfi_p0_wrdata_en + attribute \src "ls180.v:350.12-350.41" + wire width 2 \main_sdram_dfi_p0_wrdata_mask + attribute \src "ls180.v:762.5-762.19" + wire \main_sdram_en0 + attribute \src "ls180.v:765.5-765.19" + wire \main_sdram_en1 + attribute \src "ls180.v:768.6-768.30" + wire \main_sdram_go_to_refresh + attribute \src "ls180.v:310.13-310.44" + wire width 22 \main_sdram_interface_bank0_addr + attribute \src "ls180.v:311.6-311.37" + wire \main_sdram_interface_bank0_lock + attribute \src "ls180.v:313.6-313.44" + wire \main_sdram_interface_bank0_rdata_valid + attribute \src "ls180.v:308.6-308.38" + wire \main_sdram_interface_bank0_ready + attribute \src "ls180.v:307.6-307.38" + wire \main_sdram_interface_bank0_valid + attribute \src "ls180.v:312.6-312.44" + wire \main_sdram_interface_bank0_wdata_ready + attribute \src "ls180.v:309.6-309.35" + wire \main_sdram_interface_bank0_we + attribute \src "ls180.v:317.13-317.44" + wire width 22 \main_sdram_interface_bank1_addr + attribute \src "ls180.v:318.6-318.37" + wire \main_sdram_interface_bank1_lock + attribute \src "ls180.v:320.6-320.44" + wire \main_sdram_interface_bank1_rdata_valid + attribute \src "ls180.v:315.6-315.38" + wire \main_sdram_interface_bank1_ready + attribute \src "ls180.v:314.6-314.38" + wire \main_sdram_interface_bank1_valid + attribute \src "ls180.v:319.6-319.44" + wire \main_sdram_interface_bank1_wdata_ready + attribute \src "ls180.v:316.6-316.35" + wire \main_sdram_interface_bank1_we + attribute \src "ls180.v:324.13-324.44" + wire width 22 \main_sdram_interface_bank2_addr + attribute \src "ls180.v:325.6-325.37" + wire \main_sdram_interface_bank2_lock + attribute \src "ls180.v:327.6-327.44" + wire \main_sdram_interface_bank2_rdata_valid + attribute \src "ls180.v:322.6-322.38" + wire \main_sdram_interface_bank2_ready + attribute \src "ls180.v:321.6-321.38" + wire \main_sdram_interface_bank2_valid + attribute \src "ls180.v:326.6-326.44" + wire \main_sdram_interface_bank2_wdata_ready + attribute \src "ls180.v:323.6-323.35" + wire \main_sdram_interface_bank2_we + attribute \src "ls180.v:331.13-331.44" + wire width 22 \main_sdram_interface_bank3_addr + attribute \src "ls180.v:332.6-332.37" + wire \main_sdram_interface_bank3_lock + attribute \src "ls180.v:334.6-334.44" + wire \main_sdram_interface_bank3_rdata_valid + attribute \src "ls180.v:329.6-329.38" + wire \main_sdram_interface_bank3_ready + attribute \src "ls180.v:328.6-328.38" + wire \main_sdram_interface_bank3_valid + attribute \src "ls180.v:333.6-333.44" + wire \main_sdram_interface_bank3_wdata_ready + attribute \src "ls180.v:330.6-330.35" + wire \main_sdram_interface_bank3_we + attribute \src "ls180.v:337.13-337.39" + wire width 16 \main_sdram_interface_rdata + attribute \src "ls180.v:335.12-335.38" + wire width 16 \main_sdram_interface_wdata + attribute \src "ls180.v:336.11-336.40" + wire width 2 \main_sdram_interface_wdata_we + attribute \src "ls180.v:248.5-248.29" + wire \main_sdram_inti_p0_act_n + attribute \src "ls180.v:239.13-239.39" + wire width 13 \main_sdram_inti_p0_address + attribute \src "ls180.v:240.12-240.35" + wire width 2 \main_sdram_inti_p0_bank + attribute \src "ls180.v:241.5-241.29" + wire \main_sdram_inti_p0_cas_n + attribute \src "ls180.v:245.6-245.28" + wire \main_sdram_inti_p0_cke + attribute \src "ls180.v:242.5-242.28" + wire \main_sdram_inti_p0_cs_n + attribute \src "ls180.v:246.6-246.28" + wire \main_sdram_inti_p0_odt + attribute \src "ls180.v:243.5-243.29" + wire \main_sdram_inti_p0_ras_n + attribute \src "ls180.v:253.12-253.37" + wire width 16 \main_sdram_inti_p0_rddata + attribute \src "ls180.v:252.6-252.34" + wire \main_sdram_inti_p0_rddata_en + attribute \src "ls180.v:254.5-254.36" + wire \main_sdram_inti_p0_rddata_valid + attribute \src "ls180.v:247.6-247.32" + wire \main_sdram_inti_p0_reset_n + attribute \src "ls180.v:244.5-244.28" + wire \main_sdram_inti_p0_we_n + attribute \src "ls180.v:249.13-249.38" + wire width 16 \main_sdram_inti_p0_wrdata + attribute \src "ls180.v:250.6-250.34" + wire \main_sdram_inti_p0_wrdata_en + attribute \src "ls180.v:251.12-251.42" + wire width 2 \main_sdram_inti_p0_wrdata_mask + attribute \src "ls180.v:280.5-280.31" + wire \main_sdram_master_p0_act_n + attribute \src "ls180.v:271.12-271.40" + wire width 13 \main_sdram_master_p0_address + attribute \src "ls180.v:272.11-272.36" + wire width 2 \main_sdram_master_p0_bank + attribute \src "ls180.v:273.5-273.31" + wire \main_sdram_master_p0_cas_n + attribute \src "ls180.v:277.5-277.29" + wire \main_sdram_master_p0_cke + attribute \src "ls180.v:274.5-274.30" + wire \main_sdram_master_p0_cs_n + attribute \src "ls180.v:278.5-278.29" + wire \main_sdram_master_p0_odt + attribute \src "ls180.v:275.5-275.31" + wire \main_sdram_master_p0_ras_n + attribute \src "ls180.v:285.13-285.40" + wire width 16 \main_sdram_master_p0_rddata + attribute \src "ls180.v:284.5-284.35" + wire \main_sdram_master_p0_rddata_en + attribute \src "ls180.v:286.6-286.39" + wire \main_sdram_master_p0_rddata_valid + attribute \src "ls180.v:279.5-279.33" + wire \main_sdram_master_p0_reset_n + attribute \src "ls180.v:276.5-276.30" + wire \main_sdram_master_p0_we_n + attribute \src "ls180.v:281.12-281.39" + wire width 16 \main_sdram_master_p0_wrdata + attribute \src "ls180.v:282.5-282.35" + wire \main_sdram_master_p0_wrdata_en + attribute \src "ls180.v:283.11-283.43" + wire width 2 \main_sdram_master_p0_wrdata_mask + attribute \src "ls180.v:763.6-763.26" + wire \main_sdram_max_time0 + attribute \src "ls180.v:766.6-766.26" + wire \main_sdram_max_time1 + attribute \src "ls180.v:745.12-745.28" + wire width 13 \main_sdram_nop_a + attribute \src "ls180.v:746.11-746.28" + wire width 2 \main_sdram_nop_ba + attribute \src "ls180.v:289.6-289.20" + wire \main_sdram_odt + attribute \src "ls180.v:372.5-372.31" + wire \main_sdram_postponer_count + attribute \src "ls180.v:370.6-370.32" + wire \main_sdram_postponer_req_i + attribute \src "ls180.v:371.5-371.31" + wire \main_sdram_postponer_req_o + attribute \src "ls180.v:707.6-707.28" + wire \main_sdram_ras_allowed + attribute \src "ls180.v:292.5-292.18" + wire \main_sdram_re + attribute \src "ls180.v:760.6-760.31" + wire \main_sdram_read_available + attribute \src "ls180.v:290.6-290.24" + wire \main_sdram_reset_n + attribute \src "ls180.v:287.6-287.20" + wire \main_sdram_sel + attribute \src "ls180.v:378.5-378.31" + wire \main_sdram_sequencer_count + attribute \src "ls180.v:377.11-377.39" + wire width 4 \main_sdram_sequencer_counter + attribute \src "ls180.v:374.6-374.32" + wire \main_sdram_sequencer_done0 + attribute \src "ls180.v:376.5-376.31" + wire \main_sdram_sequencer_done1 + attribute \src "ls180.v:373.5-373.32" + wire \main_sdram_sequencer_start0 + attribute \src "ls180.v:375.6-375.33" + wire \main_sdram_sequencer_start1 + attribute \src "ls180.v:264.6-264.31" + wire \main_sdram_slave_p0_act_n + attribute \src "ls180.v:255.13-255.40" + wire width 13 \main_sdram_slave_p0_address + attribute \src "ls180.v:256.12-256.36" + wire width 2 \main_sdram_slave_p0_bank + attribute \src "ls180.v:257.6-257.31" + wire \main_sdram_slave_p0_cas_n + attribute \src "ls180.v:261.6-261.29" + wire \main_sdram_slave_p0_cke + attribute \src "ls180.v:258.6-258.30" + wire \main_sdram_slave_p0_cs_n + attribute \src "ls180.v:262.6-262.29" + wire \main_sdram_slave_p0_odt + attribute \src "ls180.v:259.6-259.31" + wire \main_sdram_slave_p0_ras_n + attribute \src "ls180.v:269.12-269.38" + wire width 16 \main_sdram_slave_p0_rddata + attribute \src "ls180.v:268.6-268.35" + wire \main_sdram_slave_p0_rddata_en + attribute \src "ls180.v:270.5-270.37" + wire \main_sdram_slave_p0_rddata_valid + attribute \src "ls180.v:263.6-263.33" + wire \main_sdram_slave_p0_reset_n + attribute \src "ls180.v:260.6-260.30" + wire \main_sdram_slave_p0_we_n + attribute \src "ls180.v:265.13-265.39" + wire width 16 \main_sdram_slave_p0_wrdata + attribute \src "ls180.v:266.6-266.35" + wire \main_sdram_slave_p0_wrdata_en + attribute \src "ls180.v:267.12-267.43" + wire width 2 \main_sdram_slave_p0_wrdata_mask + attribute \src "ls180.v:305.12-305.29" + wire width 16 \main_sdram_status + attribute \src "ls180.v:748.5-748.24" + wire \main_sdram_steerer0 + attribute \src "ls180.v:749.5-749.24" + wire \main_sdram_steerer1 + attribute \src "ls180.v:747.11-747.33" + wire width 2 \main_sdram_steerer_sel + attribute \src "ls180.v:291.11-291.29" + wire width 4 \main_sdram_storage + attribute \src "ls180.v:756.5-756.29" + wire \main_sdram_tccdcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:755.32-755.56" + wire \main_sdram_tccdcon_ready + attribute \src "ls180.v:754.6-754.30" + wire \main_sdram_tccdcon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:753.32-753.56" + wire \main_sdram_tfawcon_ready + attribute \src "ls180.v:752.6-752.30" + wire \main_sdram_tfawcon_valid + attribute \src "ls180.v:764.11-764.27" + wire width 5 \main_sdram_time0 + attribute \src "ls180.v:767.11-767.27" + wire width 4 \main_sdram_time1 + attribute \src "ls180.v:367.12-367.35" + wire width 10 \main_sdram_timer_count0 + attribute \src "ls180.v:369.11-369.34" + wire width 10 \main_sdram_timer_count1 + attribute \src "ls180.v:366.6-366.28" + wire \main_sdram_timer_done0 + attribute \src "ls180.v:368.6-368.28" + wire \main_sdram_timer_done1 + attribute \src "ls180.v:365.6-365.27" + wire \main_sdram_timer_wait + attribute \no_retiming "true" + attribute \src "ls180.v:751.32-751.56" + wire \main_sdram_trrdcon_ready + attribute \src "ls180.v:750.6-750.30" + wire \main_sdram_trrdcon_valid + attribute \src "ls180.v:759.11-759.35" + wire width 3 \main_sdram_twtrcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:758.32-758.56" + wire \main_sdram_twtrcon_ready + attribute \src "ls180.v:757.6-757.30" + wire \main_sdram_twtrcon_valid + attribute \src "ls180.v:364.6-364.30" + wire \main_sdram_wants_refresh + attribute \src "ls180.v:306.6-306.19" + wire \main_sdram_we + attribute \src "ls180.v:304.5-304.25" + wire \main_sdram_wrdata_re + attribute \src "ls180.v:303.12-303.37" + wire width 16 \main_sdram_wrdata_storage + attribute \src "ls180.v:761.6-761.32" + wire \main_sdram_write_available + attribute \src "ls180.v:814.6-814.21" + wire \main_sink_first + attribute \src "ls180.v:815.6-815.20" + wire \main_sink_last + attribute \src "ls180.v:816.12-816.34" + wire width 8 \main_sink_payload_data + attribute \src "ls180.v:813.5-813.20" + wire \main_sink_ready + attribute \src "ls180.v:812.6-812.21" + wire \main_sink_valid + attribute \src "ls180.v:824.5-824.22" + wire \main_source_first + attribute \src "ls180.v:825.5-825.21" + wire \main_source_last + attribute \src "ls180.v:826.11-826.35" + wire width 8 \main_source_payload_data + attribute \src "ls180.v:823.6-823.23" + wire \main_source_ready + attribute \src "ls180.v:822.5-822.22" + wire \main_source_valid + attribute \src "ls180.v:969.12-969.40" + wire width 16 \main_spi_master_clk_divider0 + attribute \src "ls180.v:991.12-991.40" + wire width 16 \main_spi_master_clk_divider1 + attribute \src "ls180.v:986.5-986.31" + wire \main_spi_master_clk_enable + attribute \src "ls180.v:993.6-993.30" + wire \main_spi_master_clk_fall + attribute \src "ls180.v:992.6-992.30" + wire \main_spi_master_clk_rise + attribute \src "ls180.v:973.5-973.31" + wire \main_spi_master_control_re + attribute \src "ls180.v:972.12-972.43" + wire width 16 \main_spi_master_control_storage + attribute \src "ls180.v:988.11-988.32" + wire width 3 \main_spi_master_count + attribute \src "ls180.v:1746.11-1746.54" + wire width 3 \main_spi_master_count_spimaster0_next_value + attribute \src "ls180.v:1747.5-1747.51" + wire \main_spi_master_count_spimaster0_next_value_ce + attribute \src "ls180.v:967.6-967.24" + wire \main_spi_master_cs + attribute \src "ls180.v:987.5-987.30" + wire \main_spi_master_cs_enable + attribute \src "ls180.v:983.5-983.26" + wire \main_spi_master_cs_re + attribute \src "ls180.v:982.5-982.31" + wire \main_spi_master_cs_storage + attribute \src "ls180.v:963.5-963.26" + wire \main_spi_master_done0 + attribute \src "ls180.v:974.6-974.27" + wire \main_spi_master_done1 + attribute \src "ls180.v:964.5-964.24" + wire \main_spi_master_irq + attribute \src "ls180.v:962.12-962.35" + wire width 8 \main_spi_master_length0 + attribute \src "ls180.v:971.12-971.35" + wire width 8 \main_spi_master_length1 + attribute \src "ls180.v:968.6-968.30" + wire \main_spi_master_loopback + attribute \src "ls180.v:985.5-985.32" + wire \main_spi_master_loopback_re + attribute \src "ls180.v:984.5-984.37" + wire \main_spi_master_loopback_storage + attribute \src "ls180.v:966.11-966.31" + wire width 8 \main_spi_master_miso + attribute \src "ls180.v:996.11-996.36" + wire width 8 \main_spi_master_miso_data + attribute \src "ls180.v:990.5-990.31" + wire \main_spi_master_miso_latch + attribute \src "ls180.v:979.12-979.39" + wire width 8 \main_spi_master_miso_status + attribute \src "ls180.v:980.6-980.29" + wire \main_spi_master_miso_we + attribute \src "ls180.v:965.12-965.32" + wire width 8 \main_spi_master_mosi + attribute \src "ls180.v:994.11-994.36" + wire width 8 \main_spi_master_mosi_data + attribute \src "ls180.v:989.5-989.31" + wire \main_spi_master_mosi_latch + attribute \src "ls180.v:978.5-978.28" + wire \main_spi_master_mosi_re + attribute \src "ls180.v:995.11-995.35" + wire width 3 \main_spi_master_mosi_sel + attribute \src "ls180.v:977.11-977.39" + wire width 8 \main_spi_master_mosi_storage + attribute \src "ls180.v:981.6-981.25" + wire \main_spi_master_sel + attribute \src "ls180.v:961.6-961.28" + wire \main_spi_master_start0 + attribute \src "ls180.v:970.5-970.27" + wire \main_spi_master_start1 + attribute \src "ls180.v:975.6-975.35" + wire \main_spi_master_status_status + attribute \src "ls180.v:976.6-976.31" + wire \main_spi_master_status_we + attribute \src "ls180.v:810.12-810.24" + wire width 32 \main_storage + attribute \src "ls180.v:820.11-820.27" + wire width 4 \main_tx_bitcount + attribute \src "ls180.v:821.5-821.17" + wire \main_tx_busy + attribute \src "ls180.v:819.11-819.22" + wire width 8 \main_tx_reg + attribute \src "ls180.v:827.5-827.23" + wire \main_uart_clk_rxen + attribute \src "ls180.v:817.5-817.23" + wire \main_uart_clk_txen + attribute \src "ls180.v:858.12-858.44" + wire width 2 \main_uart_eventmanager_pending_r + attribute \src "ls180.v:857.6-857.39" + wire \main_uart_eventmanager_pending_re + attribute \src "ls180.v:860.11-860.43" + wire width 2 \main_uart_eventmanager_pending_w + attribute \src "ls180.v:859.6-859.39" + wire \main_uart_eventmanager_pending_we + attribute \src "ls180.v:862.5-862.30" + wire \main_uart_eventmanager_re + attribute \src "ls180.v:854.12-854.43" + wire width 2 \main_uart_eventmanager_status_r + attribute \src "ls180.v:853.6-853.38" + wire \main_uart_eventmanager_status_re + attribute \src "ls180.v:856.11-856.42" + wire width 2 \main_uart_eventmanager_status_w + attribute \src "ls180.v:855.6-855.38" + wire \main_uart_eventmanager_status_we + attribute \src "ls180.v:861.11-861.41" + wire width 2 \main_uart_eventmanager_storage + attribute \src "ls180.v:842.6-842.19" + wire \main_uart_irq + attribute \src "ls180.v:951.5-951.20" + wire \main_uart_reset + attribute \src "ls180.v:851.5-851.23" + wire \main_uart_rx_clear + attribute \src "ls180.v:935.11-935.36" + wire width 4 \main_uart_rx_fifo_consume + attribute \src "ls180.v:940.6-940.31" + wire \main_uart_rx_fifo_do_read + attribute \src "ls180.v:946.6-946.37" + wire \main_uart_rx_fifo_fifo_in_first + attribute \src "ls180.v:947.6-947.36" + wire \main_uart_rx_fifo_fifo_in_last + attribute \src "ls180.v:945.12-945.50" + wire width 8 \main_uart_rx_fifo_fifo_in_payload_data + attribute \src "ls180.v:949.6-949.38" + wire \main_uart_rx_fifo_fifo_out_first + attribute \src "ls180.v:950.6-950.37" + wire \main_uart_rx_fifo_fifo_out_last + attribute \src "ls180.v:948.12-948.51" + wire width 8 \main_uart_rx_fifo_fifo_out_payload_data + attribute \src "ls180.v:932.11-932.35" + wire width 5 \main_uart_rx_fifo_level0 + attribute \src "ls180.v:944.12-944.36" + wire width 5 \main_uart_rx_fifo_level1 + attribute \src "ls180.v:934.11-934.36" + wire width 4 \main_uart_rx_fifo_produce + attribute \src "ls180.v:941.12-941.40" + wire width 4 \main_uart_rx_fifo_rdport_adr + attribute \src "ls180.v:942.12-942.42" + wire width 10 \main_uart_rx_fifo_rdport_dat_r + attribute \src "ls180.v:943.6-943.33" + wire \main_uart_rx_fifo_rdport_re + attribute \src "ls180.v:924.6-924.26" + wire \main_uart_rx_fifo_re + attribute \src "ls180.v:925.5-925.31" + wire \main_uart_rx_fifo_readable + attribute \src "ls180.v:933.5-933.30" + wire \main_uart_rx_fifo_replace + attribute \src "ls180.v:916.6-916.34" + wire \main_uart_rx_fifo_sink_first + attribute \src "ls180.v:917.6-917.33" + wire \main_uart_rx_fifo_sink_last + attribute \src "ls180.v:918.12-918.47" + wire width 8 \main_uart_rx_fifo_sink_payload_data + attribute \src "ls180.v:915.6-915.34" + wire \main_uart_rx_fifo_sink_ready + attribute \src "ls180.v:914.6-914.34" + wire \main_uart_rx_fifo_sink_valid + attribute \src "ls180.v:921.6-921.36" + wire \main_uart_rx_fifo_source_first + attribute \src "ls180.v:922.6-922.35" + wire \main_uart_rx_fifo_source_last + attribute \src "ls180.v:923.12-923.49" + wire width 8 \main_uart_rx_fifo_source_payload_data + attribute \src "ls180.v:920.6-920.36" + wire \main_uart_rx_fifo_source_ready + attribute \src "ls180.v:919.6-919.36" + wire \main_uart_rx_fifo_source_valid + attribute \src "ls180.v:930.12-930.42" + wire width 10 \main_uart_rx_fifo_syncfifo_din + attribute \src "ls180.v:931.12-931.43" + wire width 10 \main_uart_rx_fifo_syncfifo_dout + attribute \src "ls180.v:928.6-928.35" + wire \main_uart_rx_fifo_syncfifo_re + attribute \src "ls180.v:929.6-929.41" + wire \main_uart_rx_fifo_syncfifo_readable + attribute \src "ls180.v:926.6-926.35" + wire \main_uart_rx_fifo_syncfifo_we + attribute \src "ls180.v:927.6-927.41" + wire \main_uart_rx_fifo_syncfifo_writable + attribute \src "ls180.v:936.11-936.39" + wire width 4 \main_uart_rx_fifo_wrport_adr + attribute \src "ls180.v:937.12-937.42" + wire width 10 \main_uart_rx_fifo_wrport_dat_r + attribute \src "ls180.v:939.12-939.42" + wire width 10 \main_uart_rx_fifo_wrport_dat_w + attribute \src "ls180.v:938.6-938.33" + wire \main_uart_rx_fifo_wrport_we + attribute \src "ls180.v:852.5-852.29" + wire \main_uart_rx_old_trigger + attribute \src "ls180.v:849.5-849.25" + wire \main_uart_rx_pending + attribute \src "ls180.v:848.6-848.25" + wire \main_uart_rx_status + attribute \src "ls180.v:850.6-850.26" + wire \main_uart_rx_trigger + attribute \src "ls180.v:840.6-840.30" + wire \main_uart_rxempty_status + attribute \src "ls180.v:841.6-841.26" + wire \main_uart_rxempty_we + attribute \src "ls180.v:865.6-865.29" + wire \main_uart_rxfull_status + attribute \src "ls180.v:866.6-866.25" + wire \main_uart_rxfull_we + attribute \src "ls180.v:835.12-835.28" + wire width 8 \main_uart_rxtx_r + attribute \src "ls180.v:834.6-834.23" + wire \main_uart_rxtx_re + attribute \src "ls180.v:837.12-837.28" + wire width 8 \main_uart_rxtx_w + attribute \src "ls180.v:836.6-836.23" + wire \main_uart_rxtx_we + attribute \src "ls180.v:846.5-846.23" + wire \main_uart_tx_clear + attribute \src "ls180.v:898.11-898.36" + wire width 4 \main_uart_tx_fifo_consume + attribute \src "ls180.v:903.6-903.31" + wire \main_uart_tx_fifo_do_read + attribute \src "ls180.v:909.6-909.37" + wire \main_uart_tx_fifo_fifo_in_first + attribute \src "ls180.v:910.6-910.36" + wire \main_uart_tx_fifo_fifo_in_last + attribute \src "ls180.v:908.12-908.50" + wire width 8 \main_uart_tx_fifo_fifo_in_payload_data + attribute \src "ls180.v:912.6-912.38" + wire \main_uart_tx_fifo_fifo_out_first + attribute \src "ls180.v:913.6-913.37" + wire \main_uart_tx_fifo_fifo_out_last + attribute \src "ls180.v:911.12-911.51" + wire width 8 \main_uart_tx_fifo_fifo_out_payload_data + attribute \src "ls180.v:895.11-895.35" + wire width 5 \main_uart_tx_fifo_level0 + attribute \src "ls180.v:907.12-907.36" + wire width 5 \main_uart_tx_fifo_level1 + attribute \src "ls180.v:897.11-897.36" + wire width 4 \main_uart_tx_fifo_produce + attribute \src "ls180.v:904.12-904.40" + wire width 4 \main_uart_tx_fifo_rdport_adr + attribute \src "ls180.v:905.12-905.42" + wire width 10 \main_uart_tx_fifo_rdport_dat_r + attribute \src "ls180.v:906.6-906.33" + wire \main_uart_tx_fifo_rdport_re + attribute \src "ls180.v:887.6-887.26" + wire \main_uart_tx_fifo_re + attribute \src "ls180.v:888.5-888.31" + wire \main_uart_tx_fifo_readable + attribute \src "ls180.v:896.5-896.30" + wire \main_uart_tx_fifo_replace + attribute \src "ls180.v:879.5-879.33" + wire \main_uart_tx_fifo_sink_first + attribute \src "ls180.v:880.5-880.32" + wire \main_uart_tx_fifo_sink_last + attribute \src "ls180.v:881.12-881.47" + wire width 8 \main_uart_tx_fifo_sink_payload_data + attribute \src "ls180.v:878.6-878.34" + wire \main_uart_tx_fifo_sink_ready + attribute \src "ls180.v:877.6-877.34" + wire \main_uart_tx_fifo_sink_valid + attribute \src "ls180.v:884.6-884.36" + wire \main_uart_tx_fifo_source_first + attribute \src "ls180.v:885.6-885.35" + wire \main_uart_tx_fifo_source_last + attribute \src "ls180.v:886.12-886.49" + wire width 8 \main_uart_tx_fifo_source_payload_data + attribute \src "ls180.v:883.6-883.36" + wire \main_uart_tx_fifo_source_ready + attribute \src "ls180.v:882.6-882.36" + wire \main_uart_tx_fifo_source_valid + attribute \src "ls180.v:893.12-893.42" + wire width 10 \main_uart_tx_fifo_syncfifo_din + attribute \src "ls180.v:894.12-894.43" + wire width 10 \main_uart_tx_fifo_syncfifo_dout + attribute \src "ls180.v:891.6-891.35" + wire \main_uart_tx_fifo_syncfifo_re + attribute \src "ls180.v:892.6-892.41" + wire \main_uart_tx_fifo_syncfifo_readable + attribute \src "ls180.v:889.6-889.35" + wire \main_uart_tx_fifo_syncfifo_we + attribute \src "ls180.v:890.6-890.41" + wire \main_uart_tx_fifo_syncfifo_writable + attribute \src "ls180.v:899.11-899.39" + wire width 4 \main_uart_tx_fifo_wrport_adr + attribute \src "ls180.v:900.12-900.42" + wire width 10 \main_uart_tx_fifo_wrport_dat_r + attribute \src "ls180.v:902.12-902.42" + wire width 10 \main_uart_tx_fifo_wrport_dat_w + attribute \src "ls180.v:901.6-901.33" + wire \main_uart_tx_fifo_wrport_we + attribute \src "ls180.v:847.5-847.29" + wire \main_uart_tx_old_trigger + attribute \src "ls180.v:844.5-844.25" + wire \main_uart_tx_pending + attribute \src "ls180.v:843.6-843.25" + wire \main_uart_tx_status + attribute \src "ls180.v:845.6-845.26" + wire \main_uart_tx_trigger + attribute \src "ls180.v:863.6-863.30" + wire \main_uart_txempty_status + attribute \src "ls180.v:864.6-864.26" + wire \main_uart_txempty_we + attribute \src "ls180.v:838.6-838.29" + wire \main_uart_txfull_status + attribute \src "ls180.v:839.6-839.25" + wire \main_uart_txfull_we + attribute \src "ls180.v:869.6-869.31" + wire \main_uart_uart_sink_first + attribute \src "ls180.v:870.6-870.30" + wire \main_uart_uart_sink_last + attribute \src "ls180.v:871.12-871.44" + wire width 8 \main_uart_uart_sink_payload_data + attribute \src "ls180.v:868.6-868.31" + wire \main_uart_uart_sink_ready + attribute \src "ls180.v:867.6-867.31" + wire \main_uart_uart_sink_valid + attribute \src "ls180.v:874.6-874.33" + wire \main_uart_uart_source_first + attribute \src "ls180.v:875.6-875.32" + wire \main_uart_uart_source_last + attribute \src "ls180.v:876.12-876.46" + wire width 8 \main_uart_uart_source_payload_data + attribute \src "ls180.v:873.6-873.33" + wire \main_uart_uart_source_ready + attribute \src "ls180.v:872.6-872.33" + wire \main_uart_uart_source_valid + attribute \src "ls180.v:788.5-788.22" + wire \main_wb_sdram_ack + attribute \src "ls180.v:782.13-782.30" + wire width 30 \main_wb_sdram_adr + attribute \src "ls180.v:791.12-791.29" + wire width 2 \main_wb_sdram_bte + attribute \src "ls180.v:790.12-790.29" + wire width 3 \main_wb_sdram_cti + attribute \src "ls180.v:786.6-786.23" + wire \main_wb_sdram_cyc + attribute \src "ls180.v:784.13-784.32" + wire width 32 \main_wb_sdram_dat_r + attribute \src "ls180.v:783.13-783.32" + wire width 32 \main_wb_sdram_dat_w + attribute \src "ls180.v:792.5-792.22" + wire \main_wb_sdram_err + attribute \src "ls180.v:785.12-785.29" + wire width 4 \main_wb_sdram_sel + attribute \src "ls180.v:787.6-787.23" + wire \main_wb_sdram_stb + attribute \src "ls180.v:789.6-789.22" + wire \main_wb_sdram_we + attribute \src "ls180.v:806.5-806.24" + wire \main_wdata_consumed + attribute \src "ls180.v:9980.11-9980.17" + wire width 7 \memadr + attribute \src "ls180.v:10000.12-10000.18" + wire width 25 \memdat + attribute \src "ls180.v:10014.12-10014.20" + wire width 25 \memdat_1 + attribute \src "ls180.v:10028.12-10028.20" + wire width 25 \memdat_2 + attribute \src "ls180.v:10042.12-10042.20" + wire width 25 \memdat_3 + attribute \src "ls180.v:10056.11-10056.19" + wire width 10 \memdat_4 + attribute \src "ls180.v:10057.11-10057.19" + wire width 10 \memdat_5 + attribute \src "ls180.v:10073.11-10073.19" + wire width 10 \memdat_6 + attribute \src "ls180.v:10074.11-10074.19" + wire width 10 \memdat_7 + attribute \src "ls180.v:10090.11-10090.19" + wire width 10 \memdat_8 + attribute \src "ls180.v:10104.11-10104.19" + wire width 10 \memdat_9 + attribute \src "ls180.v:33.20-33.22" + wire width 43 input 29 \nc + attribute \src "ls180.v:219.6-219.13" wire \por_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:140" - wire input 7 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" - wire \xics_icp_core_irq_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" - wire width 8 \xics_icp_ics_i_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" - wire width 4 \xics_icp_ics_i_src - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" - wire width 8 \xics_ics_icp_o_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" - wire width 4 \xics_ics_icp_o_src - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:378" - cell $add $add$issuer_ls180.v:177414$12452 + attribute \src "ls180.v:34.13-34.17" + wire output 30 \pwm0 + attribute \src "ls180.v:35.13-35.17" + wire output 31 \pwm1 + attribute \src "ls180.v:36.13-36.23" + wire output 32 \sdcard_clk + attribute \src "ls180.v:37.13-37.25" + wire input 33 \sdcard_cmd_i + attribute \src "ls180.v:38.13-38.25" + wire output 34 \sdcard_cmd_o + attribute \src "ls180.v:39.13-39.26" + wire output 35 \sdcard_cmd_oe + attribute \src "ls180.v:40.19-40.32" + wire width 4 input 36 \sdcard_data_i + attribute \src "ls180.v:41.19-41.32" + wire width 4 output 37 \sdcard_data_o + attribute \src "ls180.v:42.13-42.27" + wire output 38 \sdcard_data_oe + attribute \src "ls180.v:7.20-7.27" + wire width 13 output 3 \sdram_a + attribute \src "ls180.v:16.19-16.27" + wire width 2 output 12 \sdram_ba + attribute \src "ls180.v:13.13-13.24" + wire output 9 \sdram_cas_n + attribute \src "ls180.v:15.13-15.22" + wire output 11 \sdram_cke + attribute \src "ls180.v:18.13-18.24" + wire output 14 \sdram_clock + attribute \src "ls180.v:14.13-14.23" + wire output 10 \sdram_cs_n + attribute \src "ls180.v:17.19-17.27" + wire width 2 output 13 \sdram_dm + attribute \src "ls180.v:8.20-8.30" + wire width 16 input 4 \sdram_dq_i + attribute \src "ls180.v:9.20-9.30" + wire width 16 output 5 \sdram_dq_o + attribute \src "ls180.v:10.13-10.24" + wire output 6 \sdram_dq_oe + attribute \src "ls180.v:12.13-12.24" + wire output 8 \sdram_ras_n + attribute \src "ls180.v:11.13-11.23" + wire output 7 \sdram_we_n + attribute \src "ls180.v:2595.6-2595.15" + wire \sdrio_clk + attribute \src "ls180.v:2596.6-2596.17" + wire \sdrio_clk_1 + attribute \src "ls180.v:2605.6-2605.18" + wire \sdrio_clk_10 + attribute \src "ls180.v:2606.6-2606.18" + wire \sdrio_clk_11 + attribute \src "ls180.v:2607.6-2607.18" + wire \sdrio_clk_12 + attribute \src "ls180.v:2608.6-2608.18" + wire \sdrio_clk_13 + attribute \src "ls180.v:2609.6-2609.18" + wire \sdrio_clk_14 + attribute \src "ls180.v:2610.6-2610.18" + wire \sdrio_clk_15 + attribute \src "ls180.v:2611.6-2611.18" + wire \sdrio_clk_16 + attribute \src "ls180.v:2612.6-2612.18" + wire \sdrio_clk_17 + attribute \src "ls180.v:2613.6-2613.18" + wire \sdrio_clk_18 + attribute \src "ls180.v:2614.6-2614.18" + wire \sdrio_clk_19 + attribute \src "ls180.v:2597.6-2597.17" + wire \sdrio_clk_2 + attribute \src "ls180.v:2615.6-2615.18" + wire \sdrio_clk_20 + attribute \src "ls180.v:2616.6-2616.18" + wire \sdrio_clk_21 + attribute \src "ls180.v:2617.6-2617.18" + wire \sdrio_clk_22 + attribute \src "ls180.v:2618.6-2618.18" + wire \sdrio_clk_23 + attribute \src "ls180.v:2619.6-2619.18" + wire \sdrio_clk_24 + attribute \src "ls180.v:2620.6-2620.18" + wire \sdrio_clk_25 + attribute \src "ls180.v:2621.6-2621.18" + wire \sdrio_clk_26 + attribute \src "ls180.v:2622.6-2622.18" + wire \sdrio_clk_27 + attribute \src "ls180.v:2623.6-2623.18" + wire \sdrio_clk_28 + attribute \src "ls180.v:2624.6-2624.18" + wire \sdrio_clk_29 + attribute \src "ls180.v:2598.6-2598.17" + wire \sdrio_clk_3 + attribute \src "ls180.v:2625.6-2625.18" + wire \sdrio_clk_30 + attribute \src "ls180.v:2626.6-2626.18" + wire \sdrio_clk_31 + attribute \src "ls180.v:2627.6-2627.18" + wire \sdrio_clk_32 + attribute \src "ls180.v:2628.6-2628.18" + wire \sdrio_clk_33 + attribute \src "ls180.v:2629.6-2629.18" + wire \sdrio_clk_34 + attribute \src "ls180.v:2630.6-2630.18" + wire \sdrio_clk_35 + attribute \src "ls180.v:2631.6-2631.18" + wire \sdrio_clk_36 + attribute \src "ls180.v:2632.6-2632.18" + wire \sdrio_clk_37 + attribute \src "ls180.v:2633.6-2633.18" + wire \sdrio_clk_38 + attribute \src "ls180.v:2634.6-2634.18" + wire \sdrio_clk_39 + attribute \src "ls180.v:2599.6-2599.17" + wire \sdrio_clk_4 + attribute \src "ls180.v:2635.6-2635.18" + wire \sdrio_clk_40 + attribute \src "ls180.v:2636.6-2636.18" + wire \sdrio_clk_41 + attribute \src "ls180.v:2637.6-2637.18" + wire \sdrio_clk_42 + attribute \src "ls180.v:2638.6-2638.18" + wire \sdrio_clk_43 + attribute \src "ls180.v:2639.6-2639.18" + wire \sdrio_clk_44 + attribute \src "ls180.v:2640.6-2640.18" + wire \sdrio_clk_45 + attribute \src "ls180.v:2641.6-2641.18" + wire \sdrio_clk_46 + attribute \src "ls180.v:2642.6-2642.18" + wire \sdrio_clk_47 + attribute \src "ls180.v:2643.6-2643.18" + wire \sdrio_clk_48 + attribute \src "ls180.v:2644.6-2644.18" + wire \sdrio_clk_49 + attribute \src "ls180.v:2600.6-2600.17" + wire \sdrio_clk_5 + attribute \src "ls180.v:2645.6-2645.18" + wire \sdrio_clk_50 + attribute \src "ls180.v:2646.6-2646.18" + wire \sdrio_clk_51 + attribute \src "ls180.v:2647.6-2647.18" + wire \sdrio_clk_52 + attribute \src "ls180.v:2648.6-2648.18" + wire \sdrio_clk_53 + attribute \src "ls180.v:2683.6-2683.18" + wire \sdrio_clk_54 + attribute \src "ls180.v:2684.6-2684.18" + wire \sdrio_clk_55 + attribute \src "ls180.v:2685.6-2685.18" + wire \sdrio_clk_56 + attribute \src "ls180.v:2686.6-2686.18" + wire \sdrio_clk_57 + attribute \src "ls180.v:2687.6-2687.18" + wire \sdrio_clk_58 + attribute \src "ls180.v:2688.6-2688.18" + wire \sdrio_clk_59 + attribute \src "ls180.v:2601.6-2601.17" + wire \sdrio_clk_6 + attribute \src "ls180.v:2689.6-2689.18" + wire \sdrio_clk_60 + attribute \src "ls180.v:2690.6-2690.18" + wire \sdrio_clk_61 + attribute \src "ls180.v:2691.6-2691.18" + wire \sdrio_clk_62 + attribute \src "ls180.v:2692.6-2692.18" + wire \sdrio_clk_63 + attribute \src "ls180.v:2693.6-2693.18" + wire \sdrio_clk_64 + attribute \src "ls180.v:2694.6-2694.18" + wire \sdrio_clk_65 + attribute \src "ls180.v:2695.6-2695.18" + wire \sdrio_clk_66 + attribute \src "ls180.v:2602.6-2602.17" + wire \sdrio_clk_7 + attribute \src "ls180.v:2603.6-2603.17" + wire \sdrio_clk_8 + attribute \src "ls180.v:2604.6-2604.17" + wire \sdrio_clk_9 + attribute \src "ls180.v:24.13-24.27" + wire output 20 \spi_master_clk + attribute \src "ls180.v:26.13-26.28" + wire output 22 \spi_master_cs_n + attribute \src "ls180.v:27.13-27.28" + wire input 23 \spi_master_miso + attribute \src "ls180.v:25.13-25.28" + wire output 21 \spi_master_mosi + attribute \src "ls180.v:43.13-43.26" + wire output 39 \spisdcard_clk + attribute \src "ls180.v:45.13-45.27" + wire output 41 \spisdcard_cs_n + attribute \src "ls180.v:46.13-46.27" + wire input 42 \spisdcard_miso + attribute \src "ls180.v:44.13-44.27" + wire output 40 \spisdcard_mosi + attribute \src "ls180.v:5.13-5.20" + wire input 1 \sys_clk + attribute \src "ls180.v:217.6-217.15" + wire \sys_clk_1 + attribute \src "ls180.v:6.13-6.20" + wire input 2 \sys_rst + attribute \src "ls180.v:218.6-218.15" + wire \sys_rst_1 + attribute \src "ls180.v:20.13-20.20" + wire input 16 \uart_rx + attribute \src "ls180.v:19.14-19.21" + wire output 15 \uart_tx + attribute \src "ls180.v:9979.12-9979.15" + memory width 32 size 128 \mem + attribute \src "ls180.v:9999.12-9999.19" + memory width 25 size 8 \storage + attribute \src "ls180.v:10013.12-10013.21" + memory width 25 size 8 \storage_1 + attribute \src "ls180.v:10027.12-10027.21" + memory width 25 size 8 \storage_2 + attribute \src "ls180.v:10041.12-10041.21" + memory width 25 size 8 \storage_3 + attribute \src "ls180.v:10055.11-10055.20" + memory width 10 size 16 \storage_4 + attribute \src "ls180.v:10072.11-10072.20" + memory width 10 size 16 \storage_5 + attribute \src "ls180.v:10089.11-10089.20" + memory width 10 size 32 \storage_6 + attribute \src "ls180.v:10103.11-10103.20" + memory width 10 size 32 \storage_7 + attribute \src "ls180.v:2767.68-2767.110" + cell $add $add$ls180.v:2767$22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter0_counter + connect \B 1'1 + connect \Y $add$ls180.v:2767$22_Y + end + attribute \src "ls180.v:2827.68-2827.110" + cell $add $add$ls180.v:2827$33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter1_counter + connect \B 1'1 + connect \Y $add$ls180.v:2827$33_Y + end + attribute \src "ls180.v:2887.68-2887.110" + cell $add $add$ls180.v:2887$44 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter2_counter + connect \B 1'1 + connect \Y $add$ls180.v:2887$44_Y + end + attribute \src "ls180.v:4025.54-4025.83" + cell $add $add$ls180.v:4025$538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_counter + connect \B 1'1 + connect \Y $add$ls180.v:4025$538_Y + end + attribute \src "ls180.v:4125.36-4125.89" + cell $add $add$ls180.v:4125$584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_tx_fifo_level0 + connect \B \main_uart_tx_fifo_readable + connect \Y $add$ls180.v:4125$584_Y + end + attribute \src "ls180.v:4155.36-4155.89" + cell $add $add$ls180.v:4155$595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_rx_fifo_level0 + connect \B \main_uart_rx_fifo_readable + connect \Y $add$ls180.v:4155$595_Y + end + attribute \src "ls180.v:4210.53-4210.81" + cell $add $add$ls180.v:4210$608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spi_master_count + connect \B 1'1 + connect \Y $add$ls180.v:4210$608_Y + end + attribute \src "ls180.v:4310.58-4310.86" + cell $add $add$ls180.v:4310$636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_init_count + connect \B 1'1 + connect \Y $add$ls180.v:4310$636_Y + end + attribute \src "ls180.v:4367.58-4367.86" + cell $add $add$ls180.v:4367$639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdw_count + connect \B 1'1 + connect \Y $add$ls180.v:4367$639_Y + end + attribute \src "ls180.v:4384.58-4384.86" + cell $add $add$ls180.v:4384$641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdw_count + connect \B 1'1 + connect \Y $add$ls180.v:4384$641_Y + end + attribute \src "ls180.v:4477.59-4477.87" + cell $add $add$ls180.v:4477$658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdr_count + connect \B 1'1 + connect \Y $add$ls180.v:4477$658_Y + end + attribute \src "ls180.v:4502.59-4502.87" + cell $add $add$ls180.v:4502$661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdr_count + connect \B 1'1 + connect \Y $add$ls180.v:4502$661_Y + end + attribute \src "ls180.v:4624.53-4624.82" + cell $add $add$ls180.v:4624$678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_dataw_count + connect \B 1'1 + connect \Y $add$ls180.v:4624$678_Y + end + attribute \src "ls180.v:4735.65-4735.114" + cell $add $add$ls180.v:4735$692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 10 + connect \A \main_sdphy_datar_sink_payload_block_length + connect \B 4'1000 + connect \Y $add$ls180.v:4735$692_Y + end + attribute \src "ls180.v:4740.62-4740.91" + cell $add $add$ls180.v:4740$695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdphy_datar_count + connect \B 1'1 + connect \Y $add$ls180.v:4740$695_Y + end + attribute \src "ls180.v:4766.61-4766.90" + cell $add $add$ls180.v:4766$698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdphy_datar_count + connect \B 1'1 + connect \Y $add$ls180.v:4766$698_Y + end + attribute \src "ls180.v:4970.80-4970.117" + cell $add $add$ls180.v:4970$883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdcore_crc16_inserter_cnt + connect \B 1'1 + connect \Y $add$ls180.v:4970$883_Y + end + attribute \src "ls180.v:5164.54-5164.82" + cell $add $add$ls180.v:5164$958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdcore_cmd_count + connect \B 1'1 + connect \Y $add$ls180.v:5164$958_Y + end + attribute \src "ls180.v:5216.55-5216.84" + cell $add $add$ls180.v:5216$968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_data_count + connect \B 1'1 + connect \Y $add$ls180.v:5216$968_Y + end + attribute \src "ls180.v:5242.57-5242.86" + cell $add $add$ls180.v:5242$976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_data_count + connect \B 1'1 + connect \Y $add$ls180.v:5242$976_Y + end + attribute \src "ls180.v:5363.51-5363.134" + cell $add $add$ls180.v:5363$992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \main_sdblock2mem_wishbonedmawriter_base + connect \B \main_sdblock2mem_wishbonedmawriter_offset + connect \Y $add$ls180.v:5363$992_Y + end + attribute \src "ls180.v:5366.77-5366.125" + cell $add $add$ls180.v:5366$994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdblock2mem_wishbonedmawriter_offset + connect \B 1'1 + connect \Y $add$ls180.v:5366$994_Y + end + attribute \src "ls180.v:5459.50-5459.105" + cell $add $add$ls180.v:5459$1003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \main_sdmem2block_dma_base + connect \B \main_sdmem2block_dma_offset + connect \Y $add$ls180.v:5459$1003_Y + end + attribute \src "ls180.v:5461.77-5461.111" + cell $add $add$ls180.v:5461$1004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdmem2block_dma_offset + connect \B 1'1 + connect \Y $add$ls180.v:5461$1004_Y + end + attribute \src "ls180.v:5573.49-5573.73" + cell $add $add$ls180.v:5573$1023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \libresocsim_count + connect \B 1'1 + connect \Y $add$ls180.v:5573$1023_Y + end + attribute \src "ls180.v:7438.36-7438.70" + cell $add $add$ls180.v:7438$2407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_libresocsim_bus_errors + connect \B 1'1 + connect \Y $add$ls180.v:7438$2407_Y + end + attribute \src "ls180.v:7525.37-7525.72" + cell $add $add$ls180.v:7525$2428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_sequencer_counter + connect \B 1'1 + connect \Y $add$ls180.v:7525$2428_Y + end + attribute \src "ls180.v:7542.60-7542.119" + cell $add $add$ls180.v:7542$2432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7542$2432_Y + end + attribute \src "ls180.v:7545.60-7545.119" + cell $add $add$ls180.v:7545$2433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7545$2433_Y + end + attribute \src "ls180.v:7549.59-7549.116" + cell $add $add$ls180.v:7549$2438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7549$2438_Y + end + attribute \src "ls180.v:7588.60-7588.119" + cell $add $add$ls180.v:7588$2448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7588$2448_Y + end + attribute \src "ls180.v:7591.60-7591.119" + cell $add $add$ls180.v:7591$2449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7591$2449_Y + end + attribute \src "ls180.v:7595.59-7595.116" + cell $add $add$ls180.v:7595$2454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7595$2454_Y + end + attribute \src "ls180.v:7634.60-7634.119" + cell $add $add$ls180.v:7634$2464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7634$2464_Y + end + attribute \src "ls180.v:7637.60-7637.119" + cell $add $add$ls180.v:7637$2465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7637$2465_Y + end + attribute \src "ls180.v:7641.59-7641.116" + cell $add $add$ls180.v:7641$2470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7641$2470_Y + end + attribute \src "ls180.v:7680.60-7680.119" + cell $add $add$ls180.v:7680$2480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7680$2480_Y + end + attribute \src "ls180.v:7683.60-7683.119" + cell $add $add$ls180.v:7683$2481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7683$2481_Y + end + attribute \src "ls180.v:7687.59-7687.116" + cell $add $add$ls180.v:7687$2486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7687$2486_Y + end + attribute \src "ls180.v:7917.25-7917.48" + cell $add $add$ls180.v:7917$2540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_tx_bitcount + connect \B 1'1 + connect \Y $add$ls180.v:7917$2540_Y + end + attribute \src "ls180.v:7933.55-7933.95" + cell $add $add$ls180.v:7933$2543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 33 + connect \A \main_phase_accumulator_tx + connect \B \main_storage + connect \Y $add$ls180.v:7933$2543_Y + end + attribute \src "ls180.v:7946.25-7946.48" + cell $add $add$ls180.v:7946$2547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_rx_bitcount + connect \B 1'1 + connect \Y $add$ls180.v:7946$2547_Y + end + attribute \src "ls180.v:7965.55-7965.95" + cell $add $add$ls180.v:7965$2550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 33 + connect \A \main_phase_accumulator_rx + connect \B \main_storage + connect \Y $add$ls180.v:7965$2550_Y + end + attribute \src "ls180.v:7991.33-7991.65" + cell $add $add$ls180.v:7991$2558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_tx_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:7991$2558_Y + end + attribute \src "ls180.v:7994.33-7994.65" + cell $add $add$ls180.v:7994$2559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_tx_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:7994$2559_Y + end + attribute \src "ls180.v:7998.33-7998.64" + cell $add $add$ls180.v:7998$2564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_tx_fifo_level0 + connect \B 1'1 + connect \Y $add$ls180.v:7998$2564_Y + end + attribute \src "ls180.v:8013.33-8013.65" + cell $add $add$ls180.v:8013$2569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_rx_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8013$2569_Y + end + attribute \src "ls180.v:8016.33-8016.65" + cell $add $add$ls180.v:8016$2570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_rx_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8016$2570_Y + end + attribute \src "ls180.v:8020.33-8020.64" + cell $add $add$ls180.v:8020$2575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_rx_fifo_level0 + connect \B 1'1 + connect \Y $add$ls180.v:8020$2575_Y + end + attribute \src "ls180.v:8041.35-8041.70" + cell $add $add$ls180.v:8041$2577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spi_master_clk_divider1 + connect \B 1'1 + connect \Y $add$ls180.v:8041$2577_Y + end + attribute \src "ls180.v:8077.25-8077.49" + cell $add $add$ls180.v:8077$2582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm0_counter + connect \B 1'1 + connect \Y $add$ls180.v:8077$2582_Y + end + attribute \src "ls180.v:8091.25-8091.49" + cell $add $add$ls180.v:8091$2586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm1_counter + connect \B 1'1 + connect \Y $add$ls180.v:8091$2586_Y + end + attribute \src "ls180.v:8105.31-8105.61" + cell $add $add$ls180.v:8105$2591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 9 + connect \A \main_sdphy_clocker_clks + connect \B 1'1 + connect \Y $add$ls180.v:8105$2591_Y + end + attribute \src "ls180.v:8128.45-8128.88" + cell $add $add$ls180.v:8128$2595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdphy_cmdr_cmdr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8128$2595_Y + end + attribute \src "ls180.v:8174.71-8174.114" + cell $add $add$ls180.v:8174$2601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdphy_cmdr_cmdr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8174$2601_Y + end + attribute \src "ls180.v:8209.46-8209.90" + cell $add $add$ls180.v:8209$2607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdphy_dataw_crcr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8209$2607_Y + end + attribute \src "ls180.v:8255.72-8255.116" + cell $add $add$ls180.v:8255$2613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdphy_dataw_crcr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8255$2613_Y + end + attribute \src "ls180.v:8288.47-8288.92" + cell $add $add$ls180.v:8288$2619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8288$2619_Y + end + attribute \src "ls180.v:8316.73-8316.118" + cell $add $add$ls180.v:8316$2625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \main_sdphy_datar_datar_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8316$2625_Y + end + attribute \src "ls180.v:8428.39-8428.75" + cell $add $add$ls180.v:8428$2638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 1'1 + connect \Y $add$ls180.v:8428$2638_Y + end + attribute \src "ls180.v:8489.37-8489.73" + cell $add $add$ls180.v:8489$2642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdblock2mem_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8489$2642_Y + end + attribute \src "ls180.v:8492.37-8492.73" + cell $add $add$ls180.v:8492$2643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdblock2mem_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8492$2643_Y + end + attribute \src "ls180.v:8496.36-8496.70" + cell $add $add$ls180.v:8496$2648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdblock2mem_fifo_level + connect \B 1'1 + connect \Y $add$ls180.v:8496$2648_Y + end + attribute \src "ls180.v:8511.41-8511.80" + cell $add $add$ls180.v:8511$2652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \main_sdblock2mem_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8511$2652_Y + end + attribute \src "ls180.v:8545.67-8545.106" + cell $add $add$ls180.v:8545$2658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdblock2mem_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8545$2658_Y + end + attribute \src "ls180.v:8571.39-8571.76" + cell $add $add$ls180.v:8571$2660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \main_sdmem2block_converter_mux + connect \B 1'1 + connect \Y $add$ls180.v:8571$2660_Y + end + attribute \src "ls180.v:8575.37-8575.73" + cell $add $add$ls180.v:8575$2664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdmem2block_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8575$2664_Y + end + attribute \src "ls180.v:8578.37-8578.73" + cell $add $add$ls180.v:8578$2665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdmem2block_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8578$2665_Y + end + attribute \src "ls180.v:8582.36-8582.70" + cell $add $add$ls180.v:8582$2670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdmem2block_fifo_level + connect \B 1'1 + connect \Y $add$ls180.v:8582$2670_Y + end + attribute \src "ls180.v:8589.31-8589.62" + cell $add $add$ls180.v:8589$2672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \libresocsim_clk_divider1 + connect \B 1'1 + connect \Y $add$ls180.v:8589$2672_Y + end + attribute \src "ls180.v:2761.9-2761.80" + cell $and $and$ls180.v:2761$17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_ibus_stb + connect \B \main_libresocsim_libresoc_ibus_cyc + connect \Y $and$ls180.v:2761$17_Y + end + attribute \src "ls180.v:2779.9-2779.80" + cell $and $and$ls180.v:2779$24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_ibus_stb + connect \B \main_libresocsim_libresoc_ibus_cyc + connect \Y $and$ls180.v:2779$24_Y + end + attribute \src "ls180.v:2821.9-2821.80" + cell $and $and$ls180.v:2821$28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_dbus_stb + connect \B \main_libresocsim_libresoc_dbus_cyc + connect \Y $and$ls180.v:2821$28_Y + end + attribute \src "ls180.v:2839.9-2839.80" + cell $and $and$ls180.v:2839$35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_dbus_stb + connect \B \main_libresocsim_libresoc_dbus_cyc + connect \Y $and$ls180.v:2839$35_Y + end + attribute \src "ls180.v:2881.9-2881.86" + cell $and $and$ls180.v:2881$39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_jtag_wb_stb + connect \B \main_libresocsim_libresoc_jtag_wb_cyc + connect \Y $and$ls180.v:2881$39_Y + end + attribute \src "ls180.v:2899.9-2899.86" + cell $and $and$ls180.v:2899$46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_jtag_wb_stb + connect \B \main_libresocsim_libresoc_jtag_wb_cyc + connect \Y $and$ls180.v:2899$46_Y + end + attribute \src "ls180.v:2909.31-2909.90" + cell $and $and$ls180.v:2909$48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:2909$48_Y + end + attribute \src "ls180.v:2909.30-2909.121" + cell $and $and$ls180.v:2909$49 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2909$48_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:2909$49_Y + end + attribute \src "ls180.v:2909.29-2909.156" + cell $and $and$ls180.v:2909$50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2909$49_Y + connect \B \main_libresocsim_ram_bus_sel [0] + connect \Y $and$ls180.v:2909$50_Y + end + attribute \src "ls180.v:2910.31-2910.90" + cell $and $and$ls180.v:2910$51 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:2910$51_Y + end + attribute \src "ls180.v:2910.30-2910.121" + cell $and $and$ls180.v:2910$52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2910$51_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:2910$52_Y + end + attribute \src "ls180.v:2910.29-2910.156" + cell $and $and$ls180.v:2910$53 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2910$52_Y + connect \B \main_libresocsim_ram_bus_sel [1] + connect \Y $and$ls180.v:2910$53_Y + end + attribute \src "ls180.v:2911.31-2911.90" + cell $and $and$ls180.v:2911$54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:2911$54_Y + end + attribute \src "ls180.v:2911.30-2911.121" + cell $and $and$ls180.v:2911$55 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2911$54_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:2911$55_Y + end + attribute \src "ls180.v:2911.29-2911.156" + cell $and $and$ls180.v:2911$56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2911$55_Y + connect \B \main_libresocsim_ram_bus_sel [2] + connect \Y $and$ls180.v:2911$56_Y + end + attribute \src "ls180.v:2912.31-2912.90" + cell $and $and$ls180.v:2912$57 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:2912$57_Y + end + attribute \src "ls180.v:2912.30-2912.121" + cell $and $and$ls180.v:2912$58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2912$57_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:2912$58_Y + end + attribute \src "ls180.v:2912.29-2912.156" + cell $and $and$ls180.v:2912$59 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2912$58_Y + connect \B \main_libresocsim_ram_bus_sel [3] + connect \Y $and$ls180.v:2912$59_Y + end + attribute \src "ls180.v:2921.7-2921.89" + cell $and $and$ls180.v:2921$62 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_eventmanager_pending_re + connect \B \main_libresocsim_eventmanager_pending_r + connect \Y $and$ls180.v:2921$62_Y + end + attribute \src "ls180.v:2926.32-2926.111" + cell $and $and$ls180.v:2926$63 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_eventmanager_pending_w + connect \B \main_libresocsim_eventmanager_storage + connect \Y $and$ls180.v:2926$63_Y + end + attribute \src "ls180.v:3045.40-3045.99" + cell $and $and$ls180.v:3045$71 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_issue_re + connect \B \main_sdram_command_storage [4] + connect \Y $and$ls180.v:3045$71_Y + end + attribute \src "ls180.v:3046.40-3046.99" + cell $and $and$ls180.v:3046$72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_issue_re + connect \B \main_sdram_command_storage [5] + connect \Y $and$ls180.v:3046$72_Y + end + attribute \src "ls180.v:3084.38-3084.103" + cell $and $and$ls180.v:3084$78 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_done1 + connect \B $eq$ls180.v:3084$77_Y + connect \Y $and$ls180.v:3084$78_Y + end + attribute \src "ls180.v:3138.50-3138.119" + cell $and $and$ls180.v:3138$86 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3138$86_Y + end + attribute \src "ls180.v:3138.49-3138.167" + cell $and $and$ls180.v:3138$87 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3138$86_Y + connect \B \main_sdram_bankmachine0_cmd_payload_is_write + connect \Y $and$ls180.v:3138$87_Y + end + attribute \src "ls180.v:3139.49-3139.118" + cell $and $and$ls180.v:3139$88 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3139$88_Y + end + attribute \src "ls180.v:3139.48-3139.154" + cell $and $and$ls180.v:3139$89 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3139$88_Y + connect \B \main_sdram_bankmachine0_row_open + connect \Y $and$ls180.v:3139$89_Y + end + attribute \src "ls180.v:3140.50-3140.119" + cell $and $and$ls180.v:3140$90 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3140$90_Y + end + attribute \src "ls180.v:3140.49-3140.155" + cell $and $and$ls180.v:3140$91 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3140$90_Y + connect \B \main_sdram_bankmachine0_row_open + connect \Y $and$ls180.v:3140$91_Y + end + attribute \src "ls180.v:3143.7-3143.114" + cell $and $and$ls180.v:3143$93 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $and$ls180.v:3143$93_Y + end + attribute \src "ls180.v:3172.66-3172.246" + cell $and $and$ls180.v:3172$99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B $or$ls180.v:3172$98_Y + connect \Y $and$ls180.v:3172$99_Y + end + attribute \src "ls180.v:3173.64-3173.187" + cell $and $and$ls180.v:3173$100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re + connect \Y $and$ls180.v:3173$100_Y + end + attribute \src "ls180.v:3197.9-3197.86" + cell $and $and$ls180.v:3197$106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \B \main_sdram_bankmachine0_trascon_ready + connect \Y $and$ls180.v:3197$106_Y + end + attribute \src "ls180.v:3209.9-3209.86" + cell $and $and$ls180.v:3209$107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \B \main_sdram_bankmachine0_trascon_ready + connect \Y $and$ls180.v:3209$107_Y + end + attribute \src "ls180.v:3259.13-3259.87" + cell $and $and$ls180.v:3259$109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_ready + connect \B \main_sdram_bankmachine0_auto_precharge + connect \Y $and$ls180.v:3259$109_Y + end + attribute \src "ls180.v:3295.50-3295.119" + cell $and $and$ls180.v:3295$116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3295$116_Y + end + attribute \src "ls180.v:3295.49-3295.167" + cell $and $and$ls180.v:3295$117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3295$116_Y + connect \B \main_sdram_bankmachine1_cmd_payload_is_write + connect \Y $and$ls180.v:3295$117_Y + end + attribute \src "ls180.v:3296.49-3296.118" + cell $and $and$ls180.v:3296$118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3296$118_Y + end + attribute \src "ls180.v:3296.48-3296.154" + cell $and $and$ls180.v:3296$119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3296$118_Y + connect \B \main_sdram_bankmachine1_row_open + connect \Y $and$ls180.v:3296$119_Y + end + attribute \src "ls180.v:3297.50-3297.119" + cell $and $and$ls180.v:3297$120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3297$120_Y + end + attribute \src "ls180.v:3297.49-3297.155" + cell $and $and$ls180.v:3297$121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3297$120_Y + connect \B \main_sdram_bankmachine1_row_open + connect \Y $and$ls180.v:3297$121_Y + end + attribute \src "ls180.v:3300.7-3300.114" + cell $and $and$ls180.v:3300$123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $and$ls180.v:3300$123_Y + end + attribute \src "ls180.v:3329.66-3329.246" + cell $and $and$ls180.v:3329$129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B $or$ls180.v:3329$128_Y + connect \Y $and$ls180.v:3329$129_Y + end + attribute \src "ls180.v:3330.64-3330.187" + cell $and $and$ls180.v:3330$130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re + connect \Y $and$ls180.v:3330$130_Y + end + attribute \src "ls180.v:3354.9-3354.86" + cell $and $and$ls180.v:3354$136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \B \main_sdram_bankmachine1_trascon_ready + connect \Y $and$ls180.v:3354$136_Y + end + attribute \src "ls180.v:3366.9-3366.86" + cell $and $and$ls180.v:3366$137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \B \main_sdram_bankmachine1_trascon_ready + connect \Y $and$ls180.v:3366$137_Y + end + attribute \src "ls180.v:3416.13-3416.87" + cell $and $and$ls180.v:3416$139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_ready + connect \B \main_sdram_bankmachine1_auto_precharge + connect \Y $and$ls180.v:3416$139_Y + end + attribute \src "ls180.v:3452.50-3452.119" + cell $and $and$ls180.v:3452$146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3452$146_Y + end + attribute \src "ls180.v:3452.49-3452.167" + cell $and $and$ls180.v:3452$147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3452$146_Y + connect \B \main_sdram_bankmachine2_cmd_payload_is_write + connect \Y $and$ls180.v:3452$147_Y + end + attribute \src "ls180.v:3453.49-3453.118" + cell $and $and$ls180.v:3453$148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3453$148_Y + end + attribute \src "ls180.v:3453.48-3453.154" + cell $and $and$ls180.v:3453$149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3453$148_Y + connect \B \main_sdram_bankmachine2_row_open + connect \Y $and$ls180.v:3453$149_Y + end + attribute \src "ls180.v:3454.50-3454.119" + cell $and $and$ls180.v:3454$150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3454$150_Y + end + attribute \src "ls180.v:3454.49-3454.155" + cell $and $and$ls180.v:3454$151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3454$150_Y + connect \B \main_sdram_bankmachine2_row_open + connect \Y $and$ls180.v:3454$151_Y + end + attribute \src "ls180.v:3457.7-3457.114" + cell $and $and$ls180.v:3457$153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $and$ls180.v:3457$153_Y + end + attribute \src "ls180.v:3486.66-3486.246" + cell $and $and$ls180.v:3486$159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B $or$ls180.v:3486$158_Y + connect \Y $and$ls180.v:3486$159_Y + end + attribute \src "ls180.v:3487.64-3487.187" + cell $and $and$ls180.v:3487$160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re + connect \Y $and$ls180.v:3487$160_Y + end + attribute \src "ls180.v:3511.9-3511.86" + cell $and $and$ls180.v:3511$166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \B \main_sdram_bankmachine2_trascon_ready + connect \Y $and$ls180.v:3511$166_Y + end + attribute \src "ls180.v:3523.9-3523.86" + cell $and $and$ls180.v:3523$167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \B \main_sdram_bankmachine2_trascon_ready + connect \Y $and$ls180.v:3523$167_Y + end + attribute \src "ls180.v:3573.13-3573.87" + cell $and $and$ls180.v:3573$169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_ready + connect \B \main_sdram_bankmachine2_auto_precharge + connect \Y $and$ls180.v:3573$169_Y + end + attribute \src "ls180.v:3609.50-3609.119" + cell $and $and$ls180.v:3609$176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3609$176_Y + end + attribute \src "ls180.v:3609.49-3609.167" + cell $and $and$ls180.v:3609$177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3609$176_Y + connect \B \main_sdram_bankmachine3_cmd_payload_is_write + connect \Y $and$ls180.v:3609$177_Y + end + attribute \src "ls180.v:3610.49-3610.118" + cell $and $and$ls180.v:3610$178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3610$178_Y + end + attribute \src "ls180.v:3610.48-3610.154" + cell $and $and$ls180.v:3610$179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3610$178_Y + connect \B \main_sdram_bankmachine3_row_open + connect \Y $and$ls180.v:3610$179_Y + end + attribute \src "ls180.v:3611.50-3611.119" + cell $and $and$ls180.v:3611$180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3611$180_Y + end + attribute \src "ls180.v:3611.49-3611.155" + cell $and $and$ls180.v:3611$181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3611$180_Y + connect \B \main_sdram_bankmachine3_row_open + connect \Y $and$ls180.v:3611$181_Y + end + attribute \src "ls180.v:3614.7-3614.114" + cell $and $and$ls180.v:3614$183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $and$ls180.v:3614$183_Y + end + attribute \src "ls180.v:3643.66-3643.246" + cell $and $and$ls180.v:3643$189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B $or$ls180.v:3643$188_Y + connect \Y $and$ls180.v:3643$189_Y + end + attribute \src "ls180.v:3644.64-3644.187" + cell $and $and$ls180.v:3644$190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re + connect \Y $and$ls180.v:3644$190_Y + end + attribute \src "ls180.v:3668.9-3668.86" + cell $and $and$ls180.v:3668$196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \B \main_sdram_bankmachine3_trascon_ready + connect \Y $and$ls180.v:3668$196_Y + end + attribute \src "ls180.v:3680.9-3680.86" + cell $and $and$ls180.v:3680$197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \B \main_sdram_bankmachine3_trascon_ready + connect \Y $and$ls180.v:3680$197_Y + end + attribute \src "ls180.v:3730.13-3730.87" + cell $and $and$ls180.v:3730$199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_ready + connect \B \main_sdram_bankmachine3_auto_precharge + connect \Y $and$ls180.v:3730$199_Y + end + attribute \src "ls180.v:3745.37-3745.102" + cell $and $and$ls180.v:3745$200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3745$200_Y + end + attribute \src "ls180.v:3745.108-3745.188" + cell $and $and$ls180.v:3745$202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3745$201_Y + connect \Y $and$ls180.v:3745$202_Y + end + attribute \src "ls180.v:3745.107-3745.231" + cell $and $and$ls180.v:3745$204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3745$202_Y + connect \B $not$ls180.v:3745$203_Y + connect \Y $and$ls180.v:3745$204_Y + end + attribute \src "ls180.v:3745.36-3745.232" + cell $and $and$ls180.v:3745$205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3745$200_Y + connect \B $and$ls180.v:3745$204_Y + connect \Y $and$ls180.v:3745$205_Y + end + attribute \src "ls180.v:3746.37-3746.102" + cell $and $and$ls180.v:3746$206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3746$206_Y + end + attribute \src "ls180.v:3746.108-3746.188" + cell $and $and$ls180.v:3746$208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3746$207_Y + connect \Y $and$ls180.v:3746$208_Y + end + attribute \src "ls180.v:3746.107-3746.231" + cell $and $and$ls180.v:3746$210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3746$208_Y + connect \B $not$ls180.v:3746$209_Y + connect \Y $and$ls180.v:3746$210_Y + end + attribute \src "ls180.v:3746.36-3746.232" + cell $and $and$ls180.v:3746$211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3746$206_Y + connect \B $and$ls180.v:3746$210_Y + connect \Y $and$ls180.v:3746$211_Y + end + attribute \src "ls180.v:3747.34-3747.85" + cell $and $and$ls180.v:3747$212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_trrdcon_ready + connect \B \main_sdram_tfawcon_ready + connect \Y $and$ls180.v:3747$212_Y + end + attribute \src "ls180.v:3748.37-3748.102" + cell $and $and$ls180.v:3748$213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3748$213_Y + end + attribute \src "ls180.v:3748.36-3748.194" + cell $and $and$ls180.v:3748$215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3748$213_Y + connect \B $or$ls180.v:3748$214_Y + connect \Y $and$ls180.v:3748$215_Y + end + attribute \src "ls180.v:3750.37-3750.102" + cell $and $and$ls180.v:3750$216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3750$216_Y + end + attribute \src "ls180.v:3750.36-3750.148" + cell $and $and$ls180.v:3750$217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3750$216_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:3750$217_Y + end + attribute \src "ls180.v:3751.40-3751.119" + cell $and $and$ls180.v:3751$218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_payload_is_read + connect \Y $and$ls180.v:3751$218_Y + end + attribute \src "ls180.v:3751.124-3751.203" + cell $and $and$ls180.v:3751$219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_payload_is_read + connect \Y $and$ls180.v:3751$219_Y + end + attribute \src "ls180.v:3751.209-3751.288" + cell $and $and$ls180.v:3751$221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_payload_is_read + connect \Y $and$ls180.v:3751$221_Y + end + attribute \src "ls180.v:3751.294-3751.373" + cell $and $and$ls180.v:3751$223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_payload_is_read + connect \Y $and$ls180.v:3751$223_Y + end + attribute \src "ls180.v:3752.41-3752.121" + cell $and $and$ls180.v:3752$225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_payload_is_write + connect \Y $and$ls180.v:3752$225_Y + end + attribute \src "ls180.v:3752.126-3752.206" + cell $and $and$ls180.v:3752$226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_payload_is_write + connect \Y $and$ls180.v:3752$226_Y + end + attribute \src "ls180.v:3752.212-3752.292" + cell $and $and$ls180.v:3752$228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_payload_is_write + connect \Y $and$ls180.v:3752$228_Y + end + attribute \src "ls180.v:3752.298-3752.378" + cell $and $and$ls180.v:3752$230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_payload_is_write + connect \Y $and$ls180.v:3752$230_Y + end + attribute \src "ls180.v:3759.38-3759.111" + cell $and $and$ls180.v:3759$234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_refresh_gnt + connect \B \main_sdram_bankmachine1_refresh_gnt + connect \Y $and$ls180.v:3759$234_Y + end + attribute \src "ls180.v:3759.37-3759.150" + cell $and $and$ls180.v:3759$235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3759$234_Y + connect \B \main_sdram_bankmachine2_refresh_gnt + connect \Y $and$ls180.v:3759$235_Y + end + attribute \src "ls180.v:3759.36-3759.189" + cell $and $and$ls180.v:3759$236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3759$235_Y + connect \B \main_sdram_bankmachine3_refresh_gnt + connect \Y $and$ls180.v:3759$236_Y + end + attribute \src "ls180.v:3765.77-3765.153" + cell $and $and$ls180.v:3765$239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3765$239_Y + end + attribute \src "ls180.v:3765.162-3765.246" + cell $and $and$ls180.v:3765$241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_ras + connect \B $not$ls180.v:3765$240_Y + connect \Y $and$ls180.v:3765$241_Y + end + attribute \src "ls180.v:3765.161-3765.291" + cell $and $and$ls180.v:3765$243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3765$241_Y + connect \B $not$ls180.v:3765$242_Y + connect \Y $and$ls180.v:3765$243_Y + end + attribute \src "ls180.v:3765.76-3765.333" + cell $and $and$ls180.v:3765$246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3765$239_Y + connect \B $or$ls180.v:3765$245_Y + connect \Y $and$ls180.v:3765$246_Y + end + attribute \src "ls180.v:3765.338-3765.505" + cell $and $and$ls180.v:3765$249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3765$247_Y + connect \B $eq$ls180.v:3765$248_Y + connect \Y $and$ls180.v:3765$249_Y + end + attribute \src "ls180.v:3765.38-3765.507" + cell $and $and$ls180.v:3765$251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B $or$ls180.v:3765$250_Y + connect \Y $and$ls180.v:3765$251_Y + end + attribute \src "ls180.v:3766.77-3766.153" + cell $and $and$ls180.v:3766$252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3766$252_Y + end + attribute \src "ls180.v:3766.162-3766.246" + cell $and $and$ls180.v:3766$254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_ras + connect \B $not$ls180.v:3766$253_Y + connect \Y $and$ls180.v:3766$254_Y + end + attribute \src "ls180.v:3766.161-3766.291" + cell $and $and$ls180.v:3766$256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3766$254_Y + connect \B $not$ls180.v:3766$255_Y + connect \Y $and$ls180.v:3766$256_Y + end + attribute \src "ls180.v:3766.76-3766.333" + cell $and $and$ls180.v:3766$259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3766$252_Y + connect \B $or$ls180.v:3766$258_Y + connect \Y $and$ls180.v:3766$259_Y + end + attribute \src "ls180.v:3766.338-3766.505" + cell $and $and$ls180.v:3766$262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3766$260_Y + connect \B $eq$ls180.v:3766$261_Y + connect \Y $and$ls180.v:3766$262_Y + end + attribute \src "ls180.v:3766.38-3766.507" + cell $and $and$ls180.v:3766$264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B $or$ls180.v:3766$263_Y + connect \Y $and$ls180.v:3766$264_Y + end + attribute \src "ls180.v:3767.77-3767.153" + cell $and $and$ls180.v:3767$265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3767$265_Y + end + attribute \src "ls180.v:3767.162-3767.246" + cell $and $and$ls180.v:3767$267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_ras + connect \B $not$ls180.v:3767$266_Y + connect \Y $and$ls180.v:3767$267_Y + end + attribute \src "ls180.v:3767.161-3767.291" + cell $and $and$ls180.v:3767$269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3767$267_Y + connect \B $not$ls180.v:3767$268_Y + connect \Y $and$ls180.v:3767$269_Y + end + attribute \src "ls180.v:3767.76-3767.333" + cell $and $and$ls180.v:3767$272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3767$265_Y + connect \B $or$ls180.v:3767$271_Y + connect \Y $and$ls180.v:3767$272_Y + end + attribute \src "ls180.v:3767.338-3767.505" + cell $and $and$ls180.v:3767$275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3767$273_Y + connect \B $eq$ls180.v:3767$274_Y + connect \Y $and$ls180.v:3767$275_Y + end + attribute \src "ls180.v:3767.38-3767.507" + cell $and $and$ls180.v:3767$277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B $or$ls180.v:3767$276_Y + connect \Y $and$ls180.v:3767$277_Y + end + attribute \src "ls180.v:3768.77-3768.153" + cell $and $and$ls180.v:3768$278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3768$278_Y + end + attribute \src "ls180.v:3768.162-3768.246" + cell $and $and$ls180.v:3768$280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_ras + connect \B $not$ls180.v:3768$279_Y + connect \Y $and$ls180.v:3768$280_Y + end + attribute \src "ls180.v:3768.161-3768.291" + cell $and $and$ls180.v:3768$282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3768$280_Y + connect \B $not$ls180.v:3768$281_Y + connect \Y $and$ls180.v:3768$282_Y + end + attribute \src "ls180.v:3768.76-3768.333" + cell $and $and$ls180.v:3768$285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3768$278_Y + connect \B $or$ls180.v:3768$284_Y + connect \Y $and$ls180.v:3768$285_Y + end + attribute \src "ls180.v:3768.338-3768.505" + cell $and $and$ls180.v:3768$288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3768$286_Y + connect \B $eq$ls180.v:3768$287_Y + connect \Y $and$ls180.v:3768$288_Y + end + attribute \src "ls180.v:3768.38-3768.507" + cell $and $and$ls180.v:3768$290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B $or$ls180.v:3768$289_Y + connect \Y $and$ls180.v:3768$290_Y + end + attribute \src "ls180.v:3798.77-3798.153" + cell $and $and$ls180.v:3798$297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:3798$297_Y + end + attribute \src "ls180.v:3798.162-3798.246" + cell $and $and$ls180.v:3798$299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_ras + connect \B $not$ls180.v:3798$298_Y + connect \Y $and$ls180.v:3798$299_Y + end + attribute \src "ls180.v:3798.161-3798.291" + cell $and $and$ls180.v:3798$301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3798$299_Y + connect \B $not$ls180.v:3798$300_Y + connect \Y $and$ls180.v:3798$301_Y + end + attribute \src "ls180.v:3798.76-3798.333" + cell $and $and$ls180.v:3798$304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3798$297_Y + connect \B $or$ls180.v:3798$303_Y + connect \Y $and$ls180.v:3798$304_Y + end + attribute \src "ls180.v:3798.338-3798.505" + cell $and $and$ls180.v:3798$307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3798$305_Y + connect \B $eq$ls180.v:3798$306_Y + connect \Y $and$ls180.v:3798$307_Y + end + attribute \src "ls180.v:3798.38-3798.507" + cell $and $and$ls180.v:3798$309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B $or$ls180.v:3798$308_Y + connect \Y $and$ls180.v:3798$309_Y + end + attribute \src "ls180.v:3799.77-3799.153" + cell $and $and$ls180.v:3799$310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:3799$310_Y + end + attribute \src "ls180.v:3799.162-3799.246" + cell $and $and$ls180.v:3799$312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_ras + connect \B $not$ls180.v:3799$311_Y + connect \Y $and$ls180.v:3799$312_Y + end + attribute \src "ls180.v:3799.161-3799.291" + cell $and $and$ls180.v:3799$314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3799$312_Y + connect \B $not$ls180.v:3799$313_Y + connect \Y $and$ls180.v:3799$314_Y + end + attribute \src "ls180.v:3799.76-3799.333" + cell $and $and$ls180.v:3799$317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3799$310_Y + connect \B $or$ls180.v:3799$316_Y + connect \Y $and$ls180.v:3799$317_Y + end + attribute \src "ls180.v:3799.338-3799.505" + cell $and $and$ls180.v:3799$320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3799$318_Y + connect \B $eq$ls180.v:3799$319_Y + connect \Y $and$ls180.v:3799$320_Y + end + attribute \src "ls180.v:3799.38-3799.507" + cell $and $and$ls180.v:3799$322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B $or$ls180.v:3799$321_Y + connect \Y $and$ls180.v:3799$322_Y + end + attribute \src "ls180.v:3800.77-3800.153" + cell $and $and$ls180.v:3800$323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:3800$323_Y + end + attribute \src "ls180.v:3800.162-3800.246" + cell $and $and$ls180.v:3800$325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_ras + connect \B $not$ls180.v:3800$324_Y + connect \Y $and$ls180.v:3800$325_Y + end + attribute \src "ls180.v:3800.161-3800.291" + cell $and $and$ls180.v:3800$327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3800$325_Y + connect \B $not$ls180.v:3800$326_Y + connect \Y $and$ls180.v:3800$327_Y + end + attribute \src "ls180.v:3800.76-3800.333" + cell $and $and$ls180.v:3800$330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3800$323_Y + connect \B $or$ls180.v:3800$329_Y + connect \Y $and$ls180.v:3800$330_Y + end + attribute \src "ls180.v:3800.338-3800.505" + cell $and $and$ls180.v:3800$333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3800$331_Y + connect \B $eq$ls180.v:3800$332_Y + connect \Y $and$ls180.v:3800$333_Y + end + attribute \src "ls180.v:3800.38-3800.507" + cell $and $and$ls180.v:3800$335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B $or$ls180.v:3800$334_Y + connect \Y $and$ls180.v:3800$335_Y + end + attribute \src "ls180.v:3801.77-3801.153" + cell $and $and$ls180.v:3801$336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:3801$336_Y + end + attribute \src "ls180.v:3801.162-3801.246" + cell $and $and$ls180.v:3801$338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_ras + connect \B $not$ls180.v:3801$337_Y + connect \Y $and$ls180.v:3801$338_Y + end + attribute \src "ls180.v:3801.161-3801.291" + cell $and $and$ls180.v:3801$340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3801$338_Y + connect \B $not$ls180.v:3801$339_Y + connect \Y $and$ls180.v:3801$340_Y + end + attribute \src "ls180.v:3801.76-3801.333" + cell $and $and$ls180.v:3801$343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3801$336_Y + connect \B $or$ls180.v:3801$342_Y + connect \Y $and$ls180.v:3801$343_Y + end + attribute \src "ls180.v:3801.338-3801.505" + cell $and $and$ls180.v:3801$346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3801$344_Y + connect \B $eq$ls180.v:3801$345_Y + connect \Y $and$ls180.v:3801$346_Y + end + attribute \src "ls180.v:3801.38-3801.507" + cell $and $and$ls180.v:3801$348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B $or$ls180.v:3801$347_Y + connect \Y $and$ls180.v:3801$348_Y + end + attribute \src "ls180.v:3830.8-3830.73" + cell $and $and$ls180.v:3830$353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:3830$353_Y + end + attribute \src "ls180.v:3830.7-3830.114" + cell $and $and$ls180.v:3830$355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3830$353_Y + connect \B $eq$ls180.v:3830$354_Y + connect \Y $and$ls180.v:3830$355_Y + end + attribute \src "ls180.v:3833.8-3833.73" + cell $and $and$ls180.v:3833$356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3833$356_Y + end + attribute \src "ls180.v:3833.7-3833.114" + cell $and $and$ls180.v:3833$358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3833$356_Y + connect \B $eq$ls180.v:3833$357_Y + connect \Y $and$ls180.v:3833$358_Y + end + attribute \src "ls180.v:3839.8-3839.73" + cell $and $and$ls180.v:3839$360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:3839$360_Y + end + attribute \src "ls180.v:3839.7-3839.114" + cell $and $and$ls180.v:3839$362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3839$360_Y + connect \B $eq$ls180.v:3839$361_Y + connect \Y $and$ls180.v:3839$362_Y + end + attribute \src "ls180.v:3842.8-3842.73" + cell $and $and$ls180.v:3842$363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3842$363_Y + end + attribute \src "ls180.v:3842.7-3842.114" + cell $and $and$ls180.v:3842$365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3842$363_Y + connect \B $eq$ls180.v:3842$364_Y + connect \Y $and$ls180.v:3842$365_Y + end + attribute \src "ls180.v:3848.8-3848.73" + cell $and $and$ls180.v:3848$367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:3848$367_Y + end + attribute \src "ls180.v:3848.7-3848.114" + cell $and $and$ls180.v:3848$369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3848$367_Y + connect \B $eq$ls180.v:3848$368_Y + connect \Y $and$ls180.v:3848$369_Y + end + attribute \src "ls180.v:3851.8-3851.73" + cell $and $and$ls180.v:3851$370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3851$370_Y + end + attribute \src "ls180.v:3851.7-3851.114" + cell $and $and$ls180.v:3851$372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3851$370_Y + connect \B $eq$ls180.v:3851$371_Y + connect \Y $and$ls180.v:3851$372_Y + end + attribute \src "ls180.v:3857.8-3857.73" + cell $and $and$ls180.v:3857$374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:3857$374_Y + end + attribute \src "ls180.v:3857.7-3857.114" + cell $and $and$ls180.v:3857$376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3857$374_Y + connect \B $eq$ls180.v:3857$375_Y + connect \Y $and$ls180.v:3857$376_Y + end + attribute \src "ls180.v:3860.8-3860.73" + cell $and $and$ls180.v:3860$377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3860$377_Y + end + attribute \src "ls180.v:3860.7-3860.114" + cell $and $and$ls180.v:3860$379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3860$377_Y + connect \B $eq$ls180.v:3860$378_Y + connect \Y $and$ls180.v:3860$379_Y + end + attribute \src "ls180.v:3885.71-3885.151" + cell $and $and$ls180.v:3885$384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3885$383_Y + connect \Y $and$ls180.v:3885$384_Y + end + attribute \src "ls180.v:3885.70-3885.194" + cell $and $and$ls180.v:3885$386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3885$384_Y + connect \B $not$ls180.v:3885$385_Y + connect \Y $and$ls180.v:3885$386_Y + end + attribute \src "ls180.v:3885.41-3885.222" + cell $and $and$ls180.v:3885$389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cas_allowed + connect \B $or$ls180.v:3885$388_Y + connect \Y $and$ls180.v:3885$389_Y + end + attribute \src "ls180.v:3923.71-3923.151" + cell $and $and$ls180.v:3923$393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3923$392_Y + connect \Y $and$ls180.v:3923$393_Y + end + attribute \src "ls180.v:3923.70-3923.194" + cell $and $and$ls180.v:3923$395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3923$393_Y + connect \B $not$ls180.v:3923$394_Y + connect \Y $and$ls180.v:3923$395_Y + end + attribute \src "ls180.v:3923.41-3923.222" + cell $and $and$ls180.v:3923$398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cas_allowed + connect \B $or$ls180.v:3923$397_Y + connect \Y $and$ls180.v:3923$398_Y + end + attribute \src "ls180.v:3941.110-3941.179" + cell $and $and$ls180.v:3941$403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:3941$402_Y + connect \Y $and$ls180.v:3941$403_Y + end + attribute \src "ls180.v:3941.185-3941.254" + cell $and $and$ls180.v:3941$406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:3941$405_Y + connect \Y $and$ls180.v:3941$406_Y + end + attribute \src "ls180.v:3941.260-3941.329" + cell $and $and$ls180.v:3941$409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:3941$408_Y + connect \Y $and$ls180.v:3941$409_Y + end + attribute \src "ls180.v:3941.41-3941.332" + cell $and $and$ls180.v:3941$412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3941$401_Y + connect \B $not$ls180.v:3941$411_Y + connect \Y $and$ls180.v:3941$412_Y + end + attribute \src "ls180.v:3941.40-3941.355" + cell $and $and$ls180.v:3941$413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3941$412_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:3941$413_Y + end + attribute \src "ls180.v:3942.34-3942.106" + cell $and $and$ls180.v:3942$416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3942$414_Y + connect \B $not$ls180.v:3942$415_Y + connect \Y $and$ls180.v:3942$416_Y + end + attribute \src "ls180.v:3946.110-3946.179" + cell $and $and$ls180.v:3946$419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:3946$418_Y + connect \Y $and$ls180.v:3946$419_Y + end + attribute \src "ls180.v:3946.185-3946.254" + cell $and $and$ls180.v:3946$422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:3946$421_Y + connect \Y $and$ls180.v:3946$422_Y + end + attribute \src "ls180.v:3946.260-3946.329" + cell $and $and$ls180.v:3946$425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:3946$424_Y + connect \Y $and$ls180.v:3946$425_Y + end + attribute \src "ls180.v:3946.41-3946.332" + cell $and $and$ls180.v:3946$428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3946$417_Y + connect \B $not$ls180.v:3946$427_Y + connect \Y $and$ls180.v:3946$428_Y + end + attribute \src "ls180.v:3946.40-3946.355" + cell $and $and$ls180.v:3946$429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3946$428_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:3946$429_Y + end + attribute \src "ls180.v:3947.34-3947.106" + cell $and $and$ls180.v:3947$432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3947$430_Y + connect \B $not$ls180.v:3947$431_Y + connect \Y $and$ls180.v:3947$432_Y + end + attribute \src "ls180.v:3951.110-3951.179" + cell $and $and$ls180.v:3951$435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:3951$434_Y + connect \Y $and$ls180.v:3951$435_Y + end + attribute \src "ls180.v:3951.185-3951.254" + cell $and $and$ls180.v:3951$438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:3951$437_Y + connect \Y $and$ls180.v:3951$438_Y + end + attribute \src "ls180.v:3951.260-3951.329" + cell $and $and$ls180.v:3951$441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:3951$440_Y + connect \Y $and$ls180.v:3951$441_Y + end + attribute \src "ls180.v:3951.41-3951.332" + cell $and $and$ls180.v:3951$444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3951$433_Y + connect \B $not$ls180.v:3951$443_Y + connect \Y $and$ls180.v:3951$444_Y + end + attribute \src "ls180.v:3951.40-3951.355" + cell $and $and$ls180.v:3951$445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3951$444_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:3951$445_Y + end + attribute \src "ls180.v:3952.34-3952.106" + cell $and $and$ls180.v:3952$448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3952$446_Y + connect \B $not$ls180.v:3952$447_Y + connect \Y $and$ls180.v:3952$448_Y + end + attribute \src "ls180.v:3956.110-3956.179" + cell $and $and$ls180.v:3956$451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:3956$450_Y + connect \Y $and$ls180.v:3956$451_Y + end + attribute \src "ls180.v:3956.185-3956.254" + cell $and $and$ls180.v:3956$454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:3956$453_Y + connect \Y $and$ls180.v:3956$454_Y + end + attribute \src "ls180.v:3956.260-3956.329" + cell $and $and$ls180.v:3956$457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:3956$456_Y + connect \Y $and$ls180.v:3956$457_Y + end + attribute \src "ls180.v:3956.41-3956.332" + cell $and $and$ls180.v:3956$460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3956$449_Y + connect \B $not$ls180.v:3956$459_Y + connect \Y $and$ls180.v:3956$460_Y + end + attribute \src "ls180.v:3956.40-3956.355" + cell $and $and$ls180.v:3956$461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3956$460_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:3956$461_Y + end + attribute \src "ls180.v:3957.34-3957.106" + cell $and $and$ls180.v:3957$464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3957$462_Y + connect \B $not$ls180.v:3957$463_Y + connect \Y $and$ls180.v:3957$464_Y + end + attribute \src "ls180.v:3961.151-3961.220" + cell $and $and$ls180.v:3961$468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:3961$467_Y + connect \Y $and$ls180.v:3961$468_Y + end + attribute \src "ls180.v:3961.226-3961.295" + cell $and $and$ls180.v:3961$471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:3961$470_Y + connect \Y $and$ls180.v:3961$471_Y + end + attribute \src "ls180.v:3961.301-3961.370" + cell $and $and$ls180.v:3961$474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:3961$473_Y + connect \Y $and$ls180.v:3961$474_Y + end + attribute \src "ls180.v:3961.82-3961.373" + cell $and $and$ls180.v:3961$477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3961$466_Y + connect \B $not$ls180.v:3961$476_Y + connect \Y $and$ls180.v:3961$477_Y + end + attribute \src "ls180.v:3961.43-3961.374" + cell $and $and$ls180.v:3961$478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3961$465_Y + connect \B $and$ls180.v:3961$477_Y + connect \Y $and$ls180.v:3961$478_Y + end + attribute \src "ls180.v:3961.42-3961.410" + cell $and $and$ls180.v:3961$479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3961$478_Y + connect \B \main_sdram_interface_bank0_ready + connect \Y $and$ls180.v:3961$479_Y + end + attribute \src "ls180.v:3961.525-3961.594" + cell $and $and$ls180.v:3961$484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:3961$483_Y + connect \Y $and$ls180.v:3961$484_Y + end + attribute \src "ls180.v:3961.600-3961.669" + cell $and $and$ls180.v:3961$487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:3961$486_Y + connect \Y $and$ls180.v:3961$487_Y + end + attribute \src "ls180.v:3961.675-3961.744" + cell $and $and$ls180.v:3961$490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:3961$489_Y + connect \Y $and$ls180.v:3961$490_Y + end + attribute \src "ls180.v:3961.456-3961.747" + cell $and $and$ls180.v:3961$493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3961$482_Y + connect \B $not$ls180.v:3961$492_Y + connect \Y $and$ls180.v:3961$493_Y + end + attribute \src "ls180.v:3961.417-3961.748" + cell $and $and$ls180.v:3961$494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3961$481_Y + connect \B $and$ls180.v:3961$493_Y + connect \Y $and$ls180.v:3961$494_Y + end + attribute \src "ls180.v:3961.416-3961.784" + cell $and $and$ls180.v:3961$495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3961$494_Y + connect \B \main_sdram_interface_bank1_ready + connect \Y $and$ls180.v:3961$495_Y + end + attribute \src "ls180.v:3961.899-3961.968" + cell $and $and$ls180.v:3961$500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:3961$499_Y + connect \Y $and$ls180.v:3961$500_Y + end + attribute \src "ls180.v:3961.974-3961.1043" + cell $and $and$ls180.v:3961$503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:3961$502_Y + connect \Y $and$ls180.v:3961$503_Y + end + attribute \src "ls180.v:3961.1049-3961.1118" + cell $and $and$ls180.v:3961$506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:3961$505_Y + connect \Y $and$ls180.v:3961$506_Y + end + attribute \src "ls180.v:3961.830-3961.1121" + cell $and $and$ls180.v:3961$509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3961$498_Y + connect \B $not$ls180.v:3961$508_Y + connect \Y $and$ls180.v:3961$509_Y + end + attribute \src "ls180.v:3961.791-3961.1122" + cell $and $and$ls180.v:3961$510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3961$497_Y + connect \B $and$ls180.v:3961$509_Y + connect \Y $and$ls180.v:3961$510_Y + end + attribute \src "ls180.v:3961.790-3961.1158" + cell $and $and$ls180.v:3961$511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3961$510_Y + connect \B \main_sdram_interface_bank2_ready + connect \Y $and$ls180.v:3961$511_Y + end + attribute \src "ls180.v:3961.1273-3961.1342" + cell $and $and$ls180.v:3961$516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:3961$515_Y + connect \Y $and$ls180.v:3961$516_Y + end + attribute \src "ls180.v:3961.1348-3961.1417" + cell $and $and$ls180.v:3961$519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:3961$518_Y + connect \Y $and$ls180.v:3961$519_Y + end + attribute \src "ls180.v:3961.1423-3961.1492" + cell $and $and$ls180.v:3961$522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:3961$521_Y + connect \Y $and$ls180.v:3961$522_Y + end + attribute \src "ls180.v:3961.1204-3961.1495" + cell $and $and$ls180.v:3961$525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3961$514_Y + connect \B $not$ls180.v:3961$524_Y + connect \Y $and$ls180.v:3961$525_Y + end + attribute \src "ls180.v:3961.1165-3961.1496" + cell $and $and$ls180.v:3961$526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3961$513_Y + connect \B $and$ls180.v:3961$525_Y + connect \Y $and$ls180.v:3961$526_Y + end + attribute \src "ls180.v:3961.1164-3961.1532" + cell $and $and$ls180.v:3961$527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3961$526_Y + connect \B \main_sdram_interface_bank3_ready + connect \Y $and$ls180.v:3961$527_Y + end + attribute \src "ls180.v:4019.9-4019.46" + cell $and $and$ls180.v:4019$533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_stb + connect \B \main_wb_sdram_cyc + connect \Y $and$ls180.v:4019$533_Y + end + attribute \src "ls180.v:4037.9-4037.46" + cell $and $and$ls180.v:4037$540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_stb + connect \B \main_wb_sdram_cyc + connect \Y $and$ls180.v:4037$540_Y + end + attribute \src "ls180.v:4050.32-4050.75" + cell $and $and$ls180.v:4050$544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_cyc + connect \B \main_litedram_wb_stb + connect \Y $and$ls180.v:4050$544_Y + end + attribute \src "ls180.v:4050.31-4050.99" + cell $and $and$ls180.v:4050$546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4050$544_Y + connect \B $not$ls180.v:4050$545_Y + connect \Y $and$ls180.v:4050$546_Y + end + attribute \src "ls180.v:4051.34-4051.102" + cell $and $and$ls180.v:4051$548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4051$547_Y + connect \B \main_port_cmd_payload_we + connect \Y $and$ls180.v:4051$548_Y + end + attribute \src "ls180.v:4051.33-4051.128" + cell $and $and$ls180.v:4051$550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4051$548_Y + connect \B $not$ls180.v:4051$549_Y + connect \Y $and$ls180.v:4051$550_Y + end + attribute \src "ls180.v:4052.33-4052.104" + cell $and $and$ls180.v:4052$553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4052$551_Y + connect \B $not$ls180.v:4052$552_Y + connect \Y $and$ls180.v:4052$553_Y + end + attribute \src "ls180.v:4053.49-4053.85" + cell $and $and$ls180.v:4053$554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \B \main_ack_wdata + connect \Y $and$ls180.v:4053$554_Y + end + attribute \src "ls180.v:4053.90-4053.129" + cell $and $and$ls180.v:4053$556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4053$555_Y + connect \B \main_ack_rdata + connect \Y $and$ls180.v:4053$556_Y + end + attribute \src "ls180.v:4053.32-4053.131" + cell $and $and$ls180.v:4053$558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_ack_cmd + connect \B $or$ls180.v:4053$557_Y + connect \Y $and$ls180.v:4053$558_Y + end + attribute \src "ls180.v:4054.25-4054.66" + cell $and $and$ls180.v:4054$559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_port_cmd_ready + connect \Y $and$ls180.v:4054$559_Y + end + attribute \src "ls180.v:4055.27-4055.72" + cell $and $and$ls180.v:4055$561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_wdata_valid + connect \B \main_port_wdata_ready + connect \Y $and$ls180.v:4055$561_Y + end + attribute \src "ls180.v:4056.26-4056.71" + cell $and $and$ls180.v:4056$563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_rdata_valid + connect \B \main_port_rdata_ready + connect \Y $and$ls180.v:4056$563_Y + end + attribute \src "ls180.v:4085.64-4085.88" + cell $and $and$ls180.v:4085$569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B \main_uart_rxtx_we + connect \Y $and$ls180.v:4085$569_Y + end + attribute \src "ls180.v:4089.7-4089.78" + cell $and $and$ls180.v:4089$573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_re + connect \B \main_uart_eventmanager_pending_r [0] + connect \Y $and$ls180.v:4089$573_Y + end + attribute \src "ls180.v:4100.7-4100.78" + cell $and $and$ls180.v:4100$576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_re + connect \B \main_uart_eventmanager_pending_r [1] + connect \Y $and$ls180.v:4100$576_Y + end + attribute \src "ls180.v:4109.26-4109.97" + cell $and $and$ls180.v:4109$578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_w [0] + connect \B \main_uart_eventmanager_storage [0] + connect \Y $and$ls180.v:4109$578_Y + end + attribute \src "ls180.v:4109.102-4109.173" + cell $and $and$ls180.v:4109$579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_w [1] + connect \B \main_uart_eventmanager_storage [1] + connect \Y $and$ls180.v:4109$579_Y + end + attribute \src "ls180.v:4124.41-4124.133" + cell $and $and$ls180.v:4124$583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_readable + connect \B $or$ls180.v:4124$582_Y + connect \Y $and$ls180.v:4124$583_Y + end + attribute \src "ls180.v:4135.39-4135.136" + cell $and $and$ls180.v:4135$588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_we + connect \B $or$ls180.v:4135$587_Y + connect \Y $and$ls180.v:4135$588_Y + end + attribute \src "ls180.v:4136.37-4136.104" + cell $and $and$ls180.v:4136$589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_readable + connect \B \main_uart_tx_fifo_syncfifo_re + connect \Y $and$ls180.v:4136$589_Y + end + attribute \src "ls180.v:4154.41-4154.133" + cell $and $and$ls180.v:4154$594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_readable + connect \B $or$ls180.v:4154$593_Y + connect \Y $and$ls180.v:4154$594_Y + end + attribute \src "ls180.v:4165.39-4165.136" + cell $and $and$ls180.v:4165$599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_we + connect \B $or$ls180.v:4165$598_Y + connect \Y $and$ls180.v:4165$599_Y + end + attribute \src "ls180.v:4166.37-4166.104" + cell $and $and$ls180.v:4166$600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_readable + connect \B \main_uart_rx_fifo_syncfifo_re + connect \Y $and$ls180.v:4166$600_Y + end + attribute \src "ls180.v:4291.33-4291.86" + cell $and $and$ls180.v:4291$634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_clk1 + connect \B $not$ls180.v:4291$633_Y + connect \Y $and$ls180.v:4291$634_Y + end + attribute \src "ls180.v:4395.9-4395.68" + cell $and $and$ls180.v:4395$643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_sink_valid + connect \B \main_sdphy_cmdw_pads_out_ready + connect \Y $and$ls180.v:4395$643_Y + end + attribute \src "ls180.v:4415.53-4415.145" + cell $and $and$ls180.v:4415$646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_pads_in_valid + connect \B $or$ls180.v:4415$645_Y + connect \Y $and$ls180.v:4415$646_Y + end + attribute \src "ls180.v:4434.52-4434.137" + cell $and $and$ls180.v:4434$649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid + connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready + connect \Y $and$ls180.v:4434$649_Y + end + attribute \src "ls180.v:4475.9-4475.68" + cell $and $and$ls180.v:4475$657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_source_valid + connect \B \main_sdphy_cmdr_source_ready + connect \Y $and$ls180.v:4475$657_Y + end + attribute \src "ls180.v:4513.9-4513.68" + cell $and $and$ls180.v:4513$663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_source_valid + connect \B \main_sdphy_cmdr_source_ready + connect \Y $and$ls180.v:4513$663_Y + end + attribute \src "ls180.v:4522.10-4522.69" + cell $and $and$ls180.v:4522$664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_sink_valid + connect \B \main_sdphy_cmdr_pads_out_ready + connect \Y $and$ls180.v:4522$664_Y + end + attribute \src "ls180.v:4522.9-4522.93" + cell $and $and$ls180.v:4522$665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4522$664_Y + connect \B \main_sdphy_cmdw_done + connect \Y $and$ls180.v:4522$665_Y + end + attribute \src "ls180.v:4542.54-4542.117" + cell $and $and$ls180.v:4542$667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_pads_in_valid + connect \B \main_sdphy_dataw_crcr_run + connect \Y $and$ls180.v:4542$667_Y + end + attribute \src "ls180.v:4561.53-4561.140" + cell $and $and$ls180.v:4561$670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_valid + connect \B \main_sdphy_dataw_crcr_converter_sink_ready + connect \Y $and$ls180.v:4561$670_Y + end + attribute \src "ls180.v:4658.9-4658.70" + cell $and $and$ls180.v:4658$680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_sink_valid + connect \B \main_sdphy_dataw_pads_out_ready + connect \Y $and$ls180.v:4658$680_Y + end + attribute \src "ls180.v:4676.55-4676.120" + cell $and $and$ls180.v:4676$682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_pads_in_valid + connect \B \main_sdphy_datar_datar_run + connect \Y $and$ls180.v:4676$682_Y + end + attribute \src "ls180.v:4695.54-4695.143" + cell $and $and$ls180.v:4695$685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_valid + connect \B \main_sdphy_datar_datar_converter_sink_ready + connect \Y $and$ls180.v:4695$685_Y + end + attribute \src "ls180.v:4777.9-4777.70" + cell $and $and$ls180.v:4777$700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_valid + connect \B \main_sdphy_datar_source_ready + connect \Y $and$ls180.v:4777$700_Y + end + attribute \src "ls180.v:4784.9-4784.70" + cell $and $and$ls180.v:4784$701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_sink_valid + connect \B \main_sdphy_datar_pads_out_ready + connect \Y $and$ls180.v:4784$701_Y + end + attribute \src "ls180.v:4865.48-4865.124" + cell $and $and$ls180.v:4865$824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:4865$824_Y + end + attribute \src "ls180.v:4865.47-4865.165" + cell $and $and$ls180.v:4865$825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4865$824_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4865$825_Y + end + attribute \src "ls180.v:4866.50-4866.127" + cell $and $and$ls180.v:4866$826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4866$826_Y + end + attribute \src "ls180.v:4868.48-4868.124" + cell $and $and$ls180.v:4868$827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:4868$827_Y + end + attribute \src "ls180.v:4868.47-4868.165" + cell $and $and$ls180.v:4868$828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4868$827_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4868$828_Y + end + attribute \src "ls180.v:4869.50-4869.127" + cell $and $and$ls180.v:4869$829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4869$829_Y + end + attribute \src "ls180.v:4871.48-4871.124" + cell $and $and$ls180.v:4871$830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:4871$830_Y + end + attribute \src "ls180.v:4871.47-4871.165" + cell $and $and$ls180.v:4871$831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4871$830_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4871$831_Y + end + attribute \src "ls180.v:4872.50-4872.127" + cell $and $and$ls180.v:4872$832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4872$832_Y + end + attribute \src "ls180.v:4874.48-4874.124" + cell $and $and$ls180.v:4874$833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:4874$833_Y + end + attribute \src "ls180.v:4874.47-4874.165" + cell $and $and$ls180.v:4874$834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4874$833_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4874$834_Y + end + attribute \src "ls180.v:4875.50-4875.127" + cell $and $and$ls180.v:4875$835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4875$835_Y + end + attribute \src "ls180.v:4988.10-4988.86" + cell $and $and$ls180.v:4988$884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_last + connect \Y $and$ls180.v:4988$884_Y + end + attribute \src "ls180.v:4988.9-4988.127" + cell $and $and$ls180.v:4988$885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4988$884_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4988$885_Y + end + attribute \src "ls180.v:4998.9-4998.152" + cell $and $and$ls180.v:4998$889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4998$887_Y + connect \B $eq$ls180.v:4998$888_Y + connect \Y $and$ls180.v:4998$889_Y + end + attribute \src "ls180.v:4998.8-4998.226" + cell $and $and$ls180.v:4998$891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4998$889_Y + connect \B $eq$ls180.v:4998$890_Y + connect \Y $and$ls180.v:4998$891_Y + end + attribute \src "ls180.v:4998.7-4998.300" + cell $and $and$ls180.v:4998$893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4998$891_Y + connect \B $eq$ls180.v:4998$892_Y + connect \Y $and$ls180.v:4998$893_Y + end + attribute \src "ls180.v:5003.49-5003.124" + cell $and $and$ls180.v:5003$894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5003$894_Y + end + attribute \src "ls180.v:5013.49-5013.124" + cell $and $and$ls180.v:5013$897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5013$897_Y + end + attribute \src "ls180.v:5023.49-5023.124" + cell $and $and$ls180.v:5023$900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5023$900_Y + end + attribute \src "ls180.v:5033.49-5033.124" + cell $and $and$ls180.v:5033$903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5033$903_Y + end + attribute \src "ls180.v:5045.7-5045.84" + cell $and $and$ls180.v:5045$908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B $gt$ls180.v:5045$907_Y + connect \Y $and$ls180.v:5045$908_Y + end + attribute \src "ls180.v:5163.9-5163.64" + cell $and $and$ls180.v:5163$957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_sink_valid + connect \B \main_sdphy_cmdw_sink_ready + connect \Y $and$ls180.v:5163$957_Y + end + attribute \src "ls180.v:5215.10-5215.66" + cell $and $and$ls180.v:5215$966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_sink_valid + connect \B \main_sdphy_dataw_sink_last + connect \Y $and$ls180.v:5215$966_Y + end + attribute \src "ls180.v:5215.9-5215.97" + cell $and $and$ls180.v:5215$967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5215$966_Y + connect \B \main_sdphy_dataw_sink_ready + connect \Y $and$ls180.v:5215$967_Y + end + attribute \src "ls180.v:5241.11-5241.71" + cell $and $and$ls180.v:5241$975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_last + connect \B \main_sdphy_datar_source_ready + connect \Y $and$ls180.v:5241$975_Y + end + attribute \src "ls180.v:5325.43-5325.152" + cell $and $and$ls180.v:5325$983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_we + connect \B $or$ls180.v:5325$982_Y + connect \Y $and$ls180.v:5325$983_Y + end + attribute \src "ls180.v:5326.41-5326.116" + cell $and $and$ls180.v:5326$984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_readable + connect \B \main_sdblock2mem_fifo_syncfifo_re + connect \Y $and$ls180.v:5326$984_Y + end + attribute \src "ls180.v:5338.48-5338.125" + cell $and $and$ls180.v:5338$989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_valid + connect \B \main_sdblock2mem_converter_sink_ready + connect \Y $and$ls180.v:5338$989_Y + end + attribute \src "ls180.v:5365.9-5365.102" + cell $and $and$ls180.v:5365$993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_wishbonedmawriter_sink_valid + connect \B \main_sdblock2mem_wishbonedmawriter_sink_ready + connect \Y $and$ls180.v:5365$993_Y + end + attribute \src "ls180.v:5438.9-5438.58" + cell $and $and$ls180.v:5438$999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_bus_stb + connect \B \main_interface1_bus_ack + connect \Y $and$ls180.v:5438$999_Y + end + attribute \src "ls180.v:5491.51-5491.123" + cell $and $and$ls180.v:5491$1007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_sink_first + connect \B \main_sdmem2block_converter_first + connect \Y $and$ls180.v:5491$1007_Y + end + attribute \src "ls180.v:5492.50-5492.120" + cell $and $and$ls180.v:5492$1008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_sink_last + connect \B \main_sdmem2block_converter_last + connect \Y $and$ls180.v:5492$1008_Y + end + attribute \src "ls180.v:5493.49-5493.122" + cell $and $and$ls180.v:5493$1009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_last + connect \B \main_sdmem2block_converter_source_ready + connect \Y $and$ls180.v:5493$1009_Y + end + attribute \src "ls180.v:5533.43-5533.152" + cell $and $and$ls180.v:5533$1014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_we + connect \B $or$ls180.v:5533$1013_Y + connect \Y $and$ls180.v:5533$1014_Y + end + attribute \src "ls180.v:5534.41-5534.116" + cell $and $and$ls180.v:5534$1015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_readable + connect \B \main_sdmem2block_fifo_syncfifo_re + connect \Y $and$ls180.v:5534$1015_Y + end + attribute \src "ls180.v:5625.9-5625.76" + cell $and $and$ls180.v:5625$1027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_cyc + connect \B \builder_libresocsim_wishbone_stb + connect \Y $and$ls180.v:5625$1027_Y + end + attribute \src "ls180.v:5628.44-5628.120" + cell $and $and$ls180.v:5628$1029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_we + connect \B $ne$ls180.v:5628$1028_Y + connect \Y $and$ls180.v:5628$1029_Y + end + attribute \src "ls180.v:5648.63-5648.107" + cell $and $and$ls180.v:5648$1031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5648$1030_Y + connect \Y $and$ls180.v:5648$1031_Y + end + attribute \src "ls180.v:5649.63-5649.107" + cell $and $and$ls180.v:5649$1033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5649$1032_Y + connect \Y $and$ls180.v:5649$1033_Y + end + attribute \src "ls180.v:5650.63-5650.107" + cell $and $and$ls180.v:5650$1035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5650$1034_Y + connect \Y $and$ls180.v:5650$1035_Y + end + attribute \src "ls180.v:5651.35-5651.79" + cell $and $and$ls180.v:5651$1037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5651$1036_Y + connect \Y $and$ls180.v:5651$1037_Y + end + attribute \src "ls180.v:5652.35-5652.79" + cell $and $and$ls180.v:5652$1039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5652$1038_Y + connect \Y $and$ls180.v:5652$1039_Y + end + attribute \src "ls180.v:5653.63-5653.107" + cell $and $and$ls180.v:5653$1041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5653$1040_Y + connect \Y $and$ls180.v:5653$1041_Y + end + attribute \src "ls180.v:5654.63-5654.107" + cell $and $and$ls180.v:5654$1043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5654$1042_Y + connect \Y $and$ls180.v:5654$1043_Y + end + attribute \src "ls180.v:5655.63-5655.107" + cell $and $and$ls180.v:5655$1045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5655$1044_Y + connect \Y $and$ls180.v:5655$1045_Y + end + attribute \src "ls180.v:5656.35-5656.79" + cell $and $and$ls180.v:5656$1047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5656$1046_Y + connect \Y $and$ls180.v:5656$1047_Y + end + attribute \src "ls180.v:5657.35-5657.79" + cell $and $and$ls180.v:5657$1049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5657$1048_Y + connect \Y $and$ls180.v:5657$1049_Y + end + attribute \src "ls180.v:5702.40-5702.81" + cell $and $and$ls180.v:5702$1056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [0] + connect \Y $and$ls180.v:5702$1056_Y + end + attribute \src "ls180.v:5703.50-5703.91" + cell $and $and$ls180.v:5703$1057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [1] + connect \Y $and$ls180.v:5703$1057_Y + end + attribute \src "ls180.v:5704.50-5704.91" + cell $and $and$ls180.v:5704$1058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [2] + connect \Y $and$ls180.v:5704$1058_Y + end + attribute \src "ls180.v:5705.29-5705.70" + cell $and $and$ls180.v:5705$1059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [3] + connect \Y $and$ls180.v:5705$1059_Y + end + attribute \src "ls180.v:5706.44-5706.85" + cell $and $and$ls180.v:5706$1060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [4] + connect \Y $and$ls180.v:5706$1060_Y + end + attribute \src "ls180.v:5708.25-5708.64" + cell $and $and$ls180.v:5708$1065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_stb + connect \B \builder_shared_cyc + connect \Y $and$ls180.v:5708$1065_Y + end + attribute \src "ls180.v:5708.24-5708.89" + cell $and $and$ls180.v:5708$1067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5708$1065_Y + connect \B $not$ls180.v:5708$1066_Y + connect \Y $and$ls180.v:5708$1067_Y + end + attribute \src "ls180.v:5714.31-5714.92" + cell $and $and$ls180.v:5714$1073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } + connect \B \main_libresocsim_ram_bus_dat_r + connect \Y $and$ls180.v:5714$1073_Y + end + attribute \src "ls180.v:5714.97-5714.168" + cell $and $and$ls180.v:5714$1074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } + connect \B \main_libresocsim_libresoc_xics_icp_dat_r + connect \Y $and$ls180.v:5714$1074_Y + end + attribute \src "ls180.v:5714.174-5714.245" + cell $and $and$ls180.v:5714$1076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } + connect \B \main_libresocsim_libresoc_xics_ics_dat_r + connect \Y $and$ls180.v:5714$1076_Y + end + attribute \src "ls180.v:5714.251-5714.301" + cell $and $and$ls180.v:5714$1078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } + connect \B \main_wb_sdram_dat_r + connect \Y $and$ls180.v:5714$1078_Y + end + attribute \src "ls180.v:5714.307-5714.372" + cell $and $and$ls180.v:5714$1080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } + connect \B \builder_libresocsim_wishbone_dat_r + connect \Y $and$ls180.v:5714$1080_Y + end + attribute \src "ls180.v:5724.39-5724.92" + cell $and $and$ls180.v:5724$1084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5724$1084_Y + end + attribute \src "ls180.v:5724.38-5724.142" + cell $and $and$ls180.v:5724$1086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5724$1084_Y + connect \B $eq$ls180.v:5724$1085_Y + connect \Y $and$ls180.v:5724$1086_Y + end + attribute \src "ls180.v:5725.39-5725.95" + cell $and $and$ls180.v:5725$1088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5725$1087_Y + connect \Y $and$ls180.v:5725$1088_Y + end + attribute \src "ls180.v:5725.38-5725.145" + cell $and $and$ls180.v:5725$1090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5725$1088_Y + connect \B $eq$ls180.v:5725$1089_Y + connect \Y $and$ls180.v:5725$1090_Y + end + attribute \src "ls180.v:5727.41-5727.94" + cell $and $and$ls180.v:5727$1091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5727$1091_Y + end + attribute \src "ls180.v:5727.40-5727.144" + cell $and $and$ls180.v:5727$1093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5727$1091_Y + connect \B $eq$ls180.v:5727$1092_Y + connect \Y $and$ls180.v:5727$1093_Y + end + attribute \src "ls180.v:5728.41-5728.97" + cell $and $and$ls180.v:5728$1095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5728$1094_Y + connect \Y $and$ls180.v:5728$1095_Y + end + attribute \src "ls180.v:5728.40-5728.147" + cell $and $and$ls180.v:5728$1097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5728$1095_Y + connect \B $eq$ls180.v:5728$1096_Y + connect \Y $and$ls180.v:5728$1097_Y + end + attribute \src "ls180.v:5730.41-5730.94" + cell $and $and$ls180.v:5730$1098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5730$1098_Y + end + attribute \src "ls180.v:5730.40-5730.144" + cell $and $and$ls180.v:5730$1100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5730$1098_Y + connect \B $eq$ls180.v:5730$1099_Y + connect \Y $and$ls180.v:5730$1100_Y + end + attribute \src "ls180.v:5731.41-5731.97" + cell $and $and$ls180.v:5731$1102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5731$1101_Y + connect \Y $and$ls180.v:5731$1102_Y + end + attribute \src "ls180.v:5731.40-5731.147" + cell $and $and$ls180.v:5731$1104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5731$1102_Y + connect \B $eq$ls180.v:5731$1103_Y + connect \Y $and$ls180.v:5731$1104_Y + end + attribute \src "ls180.v:5733.41-5733.94" + cell $and $and$ls180.v:5733$1105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5733$1105_Y + end + attribute \src "ls180.v:5733.40-5733.144" + cell $and $and$ls180.v:5733$1107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5733$1105_Y + connect \B $eq$ls180.v:5733$1106_Y + connect \Y $and$ls180.v:5733$1107_Y + end + attribute \src "ls180.v:5734.41-5734.97" + cell $and $and$ls180.v:5734$1109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5734$1108_Y + connect \Y $and$ls180.v:5734$1109_Y + end + attribute \src "ls180.v:5734.40-5734.147" + cell $and $and$ls180.v:5734$1111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5734$1109_Y + connect \B $eq$ls180.v:5734$1110_Y + connect \Y $and$ls180.v:5734$1111_Y + end + attribute \src "ls180.v:5736.41-5736.94" + cell $and $and$ls180.v:5736$1112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5736$1112_Y + end + attribute \src "ls180.v:5736.40-5736.144" + cell $and $and$ls180.v:5736$1114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5736$1112_Y + connect \B $eq$ls180.v:5736$1113_Y + connect \Y $and$ls180.v:5736$1114_Y + end + attribute \src "ls180.v:5737.41-5737.97" + cell $and $and$ls180.v:5737$1116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5737$1115_Y + connect \Y $and$ls180.v:5737$1116_Y + end + attribute \src "ls180.v:5737.40-5737.147" + cell $and $and$ls180.v:5737$1118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5737$1116_Y + connect \B $eq$ls180.v:5737$1117_Y + connect \Y $and$ls180.v:5737$1118_Y + end + attribute \src "ls180.v:5739.44-5739.97" + cell $and $and$ls180.v:5739$1119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5739$1119_Y + end + attribute \src "ls180.v:5739.43-5739.147" + cell $and $and$ls180.v:5739$1121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5739$1119_Y + connect \B $eq$ls180.v:5739$1120_Y + connect \Y $and$ls180.v:5739$1121_Y + end + attribute \src "ls180.v:5740.44-5740.100" + cell $and $and$ls180.v:5740$1123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5740$1122_Y + connect \Y $and$ls180.v:5740$1123_Y + end + attribute \src "ls180.v:5740.43-5740.150" + cell $and $and$ls180.v:5740$1125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5740$1123_Y + connect \B $eq$ls180.v:5740$1124_Y + connect \Y $and$ls180.v:5740$1125_Y + end + attribute \src "ls180.v:5742.44-5742.97" + cell $and $and$ls180.v:5742$1126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5742$1126_Y + end + attribute \src "ls180.v:5742.43-5742.147" + cell $and $and$ls180.v:5742$1128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5742$1126_Y + connect \B $eq$ls180.v:5742$1127_Y + connect \Y $and$ls180.v:5742$1128_Y + end + attribute \src "ls180.v:5743.44-5743.100" + cell $and $and$ls180.v:5743$1130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5743$1129_Y + connect \Y $and$ls180.v:5743$1130_Y + end + attribute \src "ls180.v:5743.43-5743.150" + cell $and $and$ls180.v:5743$1132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5743$1130_Y + connect \B $eq$ls180.v:5743$1131_Y + connect \Y $and$ls180.v:5743$1132_Y + end + attribute \src "ls180.v:5745.44-5745.97" + cell $and $and$ls180.v:5745$1133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5745$1133_Y + end + attribute \src "ls180.v:5745.43-5745.147" + cell $and $and$ls180.v:5745$1135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5745$1133_Y + connect \B $eq$ls180.v:5745$1134_Y + connect \Y $and$ls180.v:5745$1135_Y + end + attribute \src "ls180.v:5746.44-5746.100" + cell $and $and$ls180.v:5746$1137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5746$1136_Y + connect \Y $and$ls180.v:5746$1137_Y + end + attribute \src "ls180.v:5746.43-5746.150" + cell $and $and$ls180.v:5746$1139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5746$1137_Y + connect \B $eq$ls180.v:5746$1138_Y + connect \Y $and$ls180.v:5746$1139_Y + end + attribute \src "ls180.v:5748.44-5748.97" + cell $and $and$ls180.v:5748$1140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5748$1140_Y + end + attribute \src "ls180.v:5748.43-5748.147" + cell $and $and$ls180.v:5748$1142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5748$1140_Y + connect \B $eq$ls180.v:5748$1141_Y + connect \Y $and$ls180.v:5748$1142_Y + end + attribute \src "ls180.v:5749.44-5749.100" + cell $and $and$ls180.v:5749$1144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5749$1143_Y + connect \Y $and$ls180.v:5749$1144_Y + end + attribute \src "ls180.v:5749.43-5749.150" + cell $and $and$ls180.v:5749$1146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5749$1144_Y + connect \B $eq$ls180.v:5749$1145_Y + connect \Y $and$ls180.v:5749$1146_Y + end + attribute \src "ls180.v:5762.36-5762.89" + cell $and $and$ls180.v:5762$1148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5762$1148_Y + end + attribute \src "ls180.v:5762.35-5762.139" + cell $and $and$ls180.v:5762$1150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5762$1148_Y + connect \B $eq$ls180.v:5762$1149_Y + connect \Y $and$ls180.v:5762$1150_Y + end + attribute \src "ls180.v:5763.36-5763.92" + cell $and $and$ls180.v:5763$1152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5763$1151_Y + connect \Y $and$ls180.v:5763$1152_Y + end + attribute \src "ls180.v:5763.35-5763.142" + cell $and $and$ls180.v:5763$1154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5763$1152_Y + connect \B $eq$ls180.v:5763$1153_Y + connect \Y $and$ls180.v:5763$1154_Y + end + attribute \src "ls180.v:5765.36-5765.89" + cell $and $and$ls180.v:5765$1155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5765$1155_Y + end + attribute \src "ls180.v:5765.35-5765.139" + cell $and $and$ls180.v:5765$1157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5765$1155_Y + connect \B $eq$ls180.v:5765$1156_Y + connect \Y $and$ls180.v:5765$1157_Y + end + attribute \src "ls180.v:5766.36-5766.92" + cell $and $and$ls180.v:5766$1159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5766$1158_Y + connect \Y $and$ls180.v:5766$1159_Y + end + attribute \src "ls180.v:5766.35-5766.142" + cell $and $and$ls180.v:5766$1161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5766$1159_Y + connect \B $eq$ls180.v:5766$1160_Y + connect \Y $and$ls180.v:5766$1161_Y + end + attribute \src "ls180.v:5768.36-5768.89" + cell $and $and$ls180.v:5768$1162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5768$1162_Y + end + attribute \src "ls180.v:5768.35-5768.139" + cell $and $and$ls180.v:5768$1164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5768$1162_Y + connect \B $eq$ls180.v:5768$1163_Y + connect \Y $and$ls180.v:5768$1164_Y + end + attribute \src "ls180.v:5769.36-5769.92" + cell $and $and$ls180.v:5769$1166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5769$1165_Y + connect \Y $and$ls180.v:5769$1166_Y + end + attribute \src "ls180.v:5769.35-5769.142" + cell $and $and$ls180.v:5769$1168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5769$1166_Y + connect \B $eq$ls180.v:5769$1167_Y + connect \Y $and$ls180.v:5769$1168_Y + end + attribute \src "ls180.v:5771.36-5771.89" + cell $and $and$ls180.v:5771$1169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5771$1169_Y + end + attribute \src "ls180.v:5771.35-5771.139" + cell $and $and$ls180.v:5771$1171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5771$1169_Y + connect \B $eq$ls180.v:5771$1170_Y + connect \Y $and$ls180.v:5771$1171_Y + end + attribute \src "ls180.v:5772.36-5772.92" + cell $and $and$ls180.v:5772$1173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5772$1172_Y + connect \Y $and$ls180.v:5772$1173_Y + end + attribute \src "ls180.v:5772.35-5772.142" + cell $and $and$ls180.v:5772$1175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5772$1173_Y + connect \B $eq$ls180.v:5772$1174_Y + connect \Y $and$ls180.v:5772$1175_Y + end + attribute \src "ls180.v:5774.37-5774.90" + cell $and $and$ls180.v:5774$1176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5774$1176_Y + end + attribute \src "ls180.v:5774.36-5774.140" + cell $and $and$ls180.v:5774$1178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5774$1176_Y + connect \B $eq$ls180.v:5774$1177_Y + connect \Y $and$ls180.v:5774$1178_Y + end + attribute \src "ls180.v:5775.37-5775.93" + cell $and $and$ls180.v:5775$1180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5775$1179_Y + connect \Y $and$ls180.v:5775$1180_Y + end + attribute \src "ls180.v:5775.36-5775.143" + cell $and $and$ls180.v:5775$1182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5775$1180_Y + connect \B $eq$ls180.v:5775$1181_Y + connect \Y $and$ls180.v:5775$1182_Y + end + attribute \src "ls180.v:5777.37-5777.90" + cell $and $and$ls180.v:5777$1183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5777$1183_Y + end + attribute \src "ls180.v:5777.36-5777.140" + cell $and $and$ls180.v:5777$1185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5777$1183_Y + connect \B $eq$ls180.v:5777$1184_Y + connect \Y $and$ls180.v:5777$1185_Y + end + attribute \src "ls180.v:5778.37-5778.93" + cell $and $and$ls180.v:5778$1187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5778$1186_Y + connect \Y $and$ls180.v:5778$1187_Y + end + attribute \src "ls180.v:5778.36-5778.143" + cell $and $and$ls180.v:5778$1189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5778$1187_Y + connect \B $eq$ls180.v:5778$1188_Y + connect \Y $and$ls180.v:5778$1189_Y + end + attribute \src "ls180.v:5788.40-5788.93" + cell $and $and$ls180.v:5788$1191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5788$1191_Y + end + attribute \src "ls180.v:5788.39-5788.143" + cell $and $and$ls180.v:5788$1193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5788$1191_Y + connect \B $eq$ls180.v:5788$1192_Y + connect \Y $and$ls180.v:5788$1193_Y + end + attribute \src "ls180.v:5789.40-5789.96" + cell $and $and$ls180.v:5789$1195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5789$1194_Y + connect \Y $and$ls180.v:5789$1195_Y + end + attribute \src "ls180.v:5789.39-5789.146" + cell $and $and$ls180.v:5789$1197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5789$1195_Y + connect \B $eq$ls180.v:5789$1196_Y + connect \Y $and$ls180.v:5789$1197_Y + end + attribute \src "ls180.v:5791.39-5791.92" + cell $and $and$ls180.v:5791$1198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5791$1198_Y + end + attribute \src "ls180.v:5791.38-5791.142" + cell $and $and$ls180.v:5791$1200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5791$1198_Y + connect \B $eq$ls180.v:5791$1199_Y + connect \Y $and$ls180.v:5791$1200_Y + end + attribute \src "ls180.v:5792.39-5792.95" + cell $and $and$ls180.v:5792$1202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5792$1201_Y + connect \Y $and$ls180.v:5792$1202_Y + end + attribute \src "ls180.v:5792.38-5792.145" + cell $and $and$ls180.v:5792$1204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5792$1202_Y + connect \B $eq$ls180.v:5792$1203_Y + connect \Y $and$ls180.v:5792$1204_Y + end + attribute \src "ls180.v:5794.39-5794.92" + cell $and $and$ls180.v:5794$1205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5794$1205_Y + end + attribute \src "ls180.v:5794.38-5794.142" + cell $and $and$ls180.v:5794$1207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5794$1205_Y + connect \B $eq$ls180.v:5794$1206_Y + connect \Y $and$ls180.v:5794$1207_Y + end + attribute \src "ls180.v:5795.39-5795.95" + cell $and $and$ls180.v:5795$1209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5795$1208_Y + connect \Y $and$ls180.v:5795$1209_Y + end + attribute \src "ls180.v:5795.38-5795.145" + cell $and $and$ls180.v:5795$1211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5795$1209_Y + connect \B $eq$ls180.v:5795$1210_Y + connect \Y $and$ls180.v:5795$1211_Y + end + attribute \src "ls180.v:5797.39-5797.92" + cell $and $and$ls180.v:5797$1212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5797$1212_Y + end + attribute \src "ls180.v:5797.38-5797.142" + cell $and $and$ls180.v:5797$1214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5797$1212_Y + connect \B $eq$ls180.v:5797$1213_Y + connect \Y $and$ls180.v:5797$1214_Y + end + attribute \src "ls180.v:5798.39-5798.95" + cell $and $and$ls180.v:5798$1216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5798$1215_Y + connect \Y $and$ls180.v:5798$1216_Y + end + attribute \src "ls180.v:5798.38-5798.145" + cell $and $and$ls180.v:5798$1218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5798$1216_Y + connect \B $eq$ls180.v:5798$1217_Y + connect \Y $and$ls180.v:5798$1218_Y + end + attribute \src "ls180.v:5800.39-5800.92" + cell $and $and$ls180.v:5800$1219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5800$1219_Y + end + attribute \src "ls180.v:5800.38-5800.142" + cell $and $and$ls180.v:5800$1221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5800$1219_Y + connect \B $eq$ls180.v:5800$1220_Y + connect \Y $and$ls180.v:5800$1221_Y + end + attribute \src "ls180.v:5801.39-5801.95" + cell $and $and$ls180.v:5801$1223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5801$1222_Y + connect \Y $and$ls180.v:5801$1223_Y + end + attribute \src "ls180.v:5801.38-5801.145" + cell $and $and$ls180.v:5801$1225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5801$1223_Y + connect \B $eq$ls180.v:5801$1224_Y + connect \Y $and$ls180.v:5801$1225_Y + end + attribute \src "ls180.v:5803.40-5803.93" + cell $and $and$ls180.v:5803$1226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5803$1226_Y + end + attribute \src "ls180.v:5803.39-5803.143" + cell $and $and$ls180.v:5803$1228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5803$1226_Y + connect \B $eq$ls180.v:5803$1227_Y + connect \Y $and$ls180.v:5803$1228_Y + end + attribute \src "ls180.v:5804.40-5804.96" + cell $and $and$ls180.v:5804$1230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5804$1229_Y + connect \Y $and$ls180.v:5804$1230_Y + end + attribute \src "ls180.v:5804.39-5804.146" + cell $and $and$ls180.v:5804$1232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5804$1230_Y + connect \B $eq$ls180.v:5804$1231_Y + connect \Y $and$ls180.v:5804$1232_Y + end + attribute \src "ls180.v:5806.40-5806.93" + cell $and $and$ls180.v:5806$1233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5806$1233_Y + end + attribute \src "ls180.v:5806.39-5806.143" + cell $and $and$ls180.v:5806$1235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5806$1233_Y + connect \B $eq$ls180.v:5806$1234_Y + connect \Y $and$ls180.v:5806$1235_Y + end + attribute \src "ls180.v:5807.40-5807.96" + cell $and $and$ls180.v:5807$1237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5807$1236_Y + connect \Y $and$ls180.v:5807$1237_Y + end + attribute \src "ls180.v:5807.39-5807.146" + cell $and $and$ls180.v:5807$1239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5807$1237_Y + connect \B $eq$ls180.v:5807$1238_Y + connect \Y $and$ls180.v:5807$1239_Y + end + attribute \src "ls180.v:5809.40-5809.93" + cell $and $and$ls180.v:5809$1240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5809$1240_Y + end + attribute \src "ls180.v:5809.39-5809.143" + cell $and $and$ls180.v:5809$1242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5809$1240_Y + connect \B $eq$ls180.v:5809$1241_Y + connect \Y $and$ls180.v:5809$1242_Y + end + attribute \src "ls180.v:5810.40-5810.96" + cell $and $and$ls180.v:5810$1244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5810$1243_Y + connect \Y $and$ls180.v:5810$1244_Y + end + attribute \src "ls180.v:5810.39-5810.146" + cell $and $and$ls180.v:5810$1246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5810$1244_Y + connect \B $eq$ls180.v:5810$1245_Y + connect \Y $and$ls180.v:5810$1246_Y + end + attribute \src "ls180.v:5812.40-5812.93" + cell $and $and$ls180.v:5812$1247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5812$1247_Y + end + attribute \src "ls180.v:5812.39-5812.143" + cell $and $and$ls180.v:5812$1249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5812$1247_Y + connect \B $eq$ls180.v:5812$1248_Y + connect \Y $and$ls180.v:5812$1249_Y + end + attribute \src "ls180.v:5813.40-5813.96" + cell $and $and$ls180.v:5813$1251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5813$1250_Y + connect \Y $and$ls180.v:5813$1251_Y + end + attribute \src "ls180.v:5813.39-5813.146" + cell $and $and$ls180.v:5813$1253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5813$1251_Y + connect \B $eq$ls180.v:5813$1252_Y + connect \Y $and$ls180.v:5813$1253_Y + end + attribute \src "ls180.v:5825.40-5825.93" + cell $and $and$ls180.v:5825$1255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5825$1255_Y + end + attribute \src "ls180.v:5825.39-5825.143" + cell $and $and$ls180.v:5825$1257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5825$1255_Y + connect \B $eq$ls180.v:5825$1256_Y + connect \Y $and$ls180.v:5825$1257_Y + end + attribute \src "ls180.v:5826.40-5826.96" + cell $and $and$ls180.v:5826$1259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5826$1258_Y + connect \Y $and$ls180.v:5826$1259_Y + end + attribute \src "ls180.v:5826.39-5826.146" + cell $and $and$ls180.v:5826$1261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5826$1259_Y + connect \B $eq$ls180.v:5826$1260_Y + connect \Y $and$ls180.v:5826$1261_Y + end + attribute \src "ls180.v:5828.39-5828.92" + cell $and $and$ls180.v:5828$1262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5828$1262_Y + end + attribute \src "ls180.v:5828.38-5828.142" + cell $and $and$ls180.v:5828$1264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5828$1262_Y + connect \B $eq$ls180.v:5828$1263_Y + connect \Y $and$ls180.v:5828$1264_Y + end + attribute \src "ls180.v:5829.39-5829.95" + cell $and $and$ls180.v:5829$1266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5829$1265_Y + connect \Y $and$ls180.v:5829$1266_Y + end + attribute \src "ls180.v:5829.38-5829.145" + cell $and $and$ls180.v:5829$1268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5829$1266_Y + connect \B $eq$ls180.v:5829$1267_Y + connect \Y $and$ls180.v:5829$1268_Y + end + attribute \src "ls180.v:5831.39-5831.92" + cell $and $and$ls180.v:5831$1269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5831$1269_Y + end + attribute \src "ls180.v:5831.38-5831.142" + cell $and $and$ls180.v:5831$1271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5831$1269_Y + connect \B $eq$ls180.v:5831$1270_Y + connect \Y $and$ls180.v:5831$1271_Y + end + attribute \src "ls180.v:5832.39-5832.95" + cell $and $and$ls180.v:5832$1273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5832$1272_Y + connect \Y $and$ls180.v:5832$1273_Y + end + attribute \src "ls180.v:5832.38-5832.145" + cell $and $and$ls180.v:5832$1275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5832$1273_Y + connect \B $eq$ls180.v:5832$1274_Y + connect \Y $and$ls180.v:5832$1275_Y + end + attribute \src "ls180.v:5834.39-5834.92" + cell $and $and$ls180.v:5834$1276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5834$1276_Y + end + attribute \src "ls180.v:5834.38-5834.142" + cell $and $and$ls180.v:5834$1278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5834$1276_Y + connect \B $eq$ls180.v:5834$1277_Y + connect \Y $and$ls180.v:5834$1278_Y + end + attribute \src "ls180.v:5835.39-5835.95" + cell $and $and$ls180.v:5835$1280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5835$1279_Y + connect \Y $and$ls180.v:5835$1280_Y + end + attribute \src "ls180.v:5835.38-5835.145" + cell $and $and$ls180.v:5835$1282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5835$1280_Y + connect \B $eq$ls180.v:5835$1281_Y + connect \Y $and$ls180.v:5835$1282_Y + end + attribute \src "ls180.v:5837.39-5837.92" + cell $and $and$ls180.v:5837$1283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5837$1283_Y + end + attribute \src "ls180.v:5837.38-5837.142" + cell $and $and$ls180.v:5837$1285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5837$1283_Y + connect \B $eq$ls180.v:5837$1284_Y + connect \Y $and$ls180.v:5837$1285_Y + end + attribute \src "ls180.v:5838.39-5838.95" + cell $and $and$ls180.v:5838$1287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5838$1286_Y + connect \Y $and$ls180.v:5838$1287_Y + end + attribute \src "ls180.v:5838.38-5838.145" + cell $and $and$ls180.v:5838$1289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5838$1287_Y + connect \B $eq$ls180.v:5838$1288_Y + connect \Y $and$ls180.v:5838$1289_Y + end + attribute \src "ls180.v:5840.40-5840.93" + cell $and $and$ls180.v:5840$1290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5840$1290_Y + end + attribute \src "ls180.v:5840.39-5840.143" + cell $and $and$ls180.v:5840$1292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5840$1290_Y + connect \B $eq$ls180.v:5840$1291_Y + connect \Y $and$ls180.v:5840$1292_Y + end + attribute \src "ls180.v:5841.40-5841.96" + cell $and $and$ls180.v:5841$1294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5841$1293_Y + connect \Y $and$ls180.v:5841$1294_Y + end + attribute \src "ls180.v:5841.39-5841.146" + cell $and $and$ls180.v:5841$1296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5841$1294_Y + connect \B $eq$ls180.v:5841$1295_Y + connect \Y $and$ls180.v:5841$1296_Y + end + attribute \src "ls180.v:5843.40-5843.93" + cell $and $and$ls180.v:5843$1297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5843$1297_Y + end + attribute \src "ls180.v:5843.39-5843.143" + cell $and $and$ls180.v:5843$1299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5843$1297_Y + connect \B $eq$ls180.v:5843$1298_Y + connect \Y $and$ls180.v:5843$1299_Y + end + attribute \src "ls180.v:5844.40-5844.96" + cell $and $and$ls180.v:5844$1301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5844$1300_Y + connect \Y $and$ls180.v:5844$1301_Y + end + attribute \src "ls180.v:5844.39-5844.146" + cell $and $and$ls180.v:5844$1303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5844$1301_Y + connect \B $eq$ls180.v:5844$1302_Y + connect \Y $and$ls180.v:5844$1303_Y + end + attribute \src "ls180.v:5846.40-5846.93" + cell $and $and$ls180.v:5846$1304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5846$1304_Y + end + attribute \src "ls180.v:5846.39-5846.143" + cell $and $and$ls180.v:5846$1306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5846$1304_Y + connect \B $eq$ls180.v:5846$1305_Y + connect \Y $and$ls180.v:5846$1306_Y + end + attribute \src "ls180.v:5847.40-5847.96" + cell $and $and$ls180.v:5847$1308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5847$1307_Y + connect \Y $and$ls180.v:5847$1308_Y + end + attribute \src "ls180.v:5847.39-5847.146" + cell $and $and$ls180.v:5847$1310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5847$1308_Y + connect \B $eq$ls180.v:5847$1309_Y + connect \Y $and$ls180.v:5847$1310_Y + end + attribute \src "ls180.v:5849.40-5849.93" + cell $and $and$ls180.v:5849$1311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5849$1311_Y + end + attribute \src "ls180.v:5849.39-5849.143" + cell $and $and$ls180.v:5849$1313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5849$1311_Y + connect \B $eq$ls180.v:5849$1312_Y + connect \Y $and$ls180.v:5849$1313_Y + end + attribute \src "ls180.v:5850.40-5850.96" + cell $and $and$ls180.v:5850$1315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5850$1314_Y + connect \Y $and$ls180.v:5850$1315_Y + end + attribute \src "ls180.v:5850.39-5850.146" + cell $and $and$ls180.v:5850$1317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5850$1315_Y + connect \B $eq$ls180.v:5850$1316_Y + connect \Y $and$ls180.v:5850$1317_Y + end + attribute \src "ls180.v:5862.42-5862.95" + cell $and $and$ls180.v:5862$1319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5862$1319_Y + end + attribute \src "ls180.v:5862.41-5862.145" + cell $and $and$ls180.v:5862$1321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5862$1319_Y + connect \B $eq$ls180.v:5862$1320_Y + connect \Y $and$ls180.v:5862$1321_Y + end + attribute \src "ls180.v:5863.42-5863.98" + cell $and $and$ls180.v:5863$1323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5863$1322_Y + connect \Y $and$ls180.v:5863$1323_Y + end + attribute \src "ls180.v:5863.41-5863.148" + cell $and $and$ls180.v:5863$1325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5863$1323_Y + connect \B $eq$ls180.v:5863$1324_Y + connect \Y $and$ls180.v:5863$1325_Y + end + attribute \src "ls180.v:5865.42-5865.95" + cell $and $and$ls180.v:5865$1326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5865$1326_Y + end + attribute \src "ls180.v:5865.41-5865.145" + cell $and $and$ls180.v:5865$1328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5865$1326_Y + connect \B $eq$ls180.v:5865$1327_Y + connect \Y $and$ls180.v:5865$1328_Y + end + attribute \src "ls180.v:5866.42-5866.98" + cell $and $and$ls180.v:5866$1330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5866$1329_Y + connect \Y $and$ls180.v:5866$1330_Y + end + attribute \src "ls180.v:5866.41-5866.148" + cell $and $and$ls180.v:5866$1332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5866$1330_Y + connect \B $eq$ls180.v:5866$1331_Y + connect \Y $and$ls180.v:5866$1332_Y + end + attribute \src "ls180.v:5868.42-5868.95" + cell $and $and$ls180.v:5868$1333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5868$1333_Y + end + attribute \src "ls180.v:5868.41-5868.145" + cell $and $and$ls180.v:5868$1335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5868$1333_Y + connect \B $eq$ls180.v:5868$1334_Y + connect \Y $and$ls180.v:5868$1335_Y + end + attribute \src "ls180.v:5869.42-5869.98" + cell $and $and$ls180.v:5869$1337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5869$1336_Y + connect \Y $and$ls180.v:5869$1337_Y + end + attribute \src "ls180.v:5869.41-5869.148" + cell $and $and$ls180.v:5869$1339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5869$1337_Y + connect \B $eq$ls180.v:5869$1338_Y + connect \Y $and$ls180.v:5869$1339_Y + end + attribute \src "ls180.v:5871.42-5871.95" + cell $and $and$ls180.v:5871$1340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5871$1340_Y + end + attribute \src "ls180.v:5871.41-5871.145" + cell $and $and$ls180.v:5871$1342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5871$1340_Y + connect \B $eq$ls180.v:5871$1341_Y + connect \Y $and$ls180.v:5871$1342_Y + end + attribute \src "ls180.v:5872.42-5872.98" + cell $and $and$ls180.v:5872$1344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5872$1343_Y + connect \Y $and$ls180.v:5872$1344_Y + end + attribute \src "ls180.v:5872.41-5872.148" + cell $and $and$ls180.v:5872$1346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5872$1344_Y + connect \B $eq$ls180.v:5872$1345_Y + connect \Y $and$ls180.v:5872$1346_Y + end + attribute \src "ls180.v:5874.42-5874.95" + cell $and $and$ls180.v:5874$1347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5874$1347_Y + end + attribute \src "ls180.v:5874.41-5874.145" + cell $and $and$ls180.v:5874$1349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5874$1347_Y + connect \B $eq$ls180.v:5874$1348_Y + connect \Y $and$ls180.v:5874$1349_Y + end + attribute \src "ls180.v:5875.42-5875.98" + cell $and $and$ls180.v:5875$1351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5875$1350_Y + connect \Y $and$ls180.v:5875$1351_Y + end + attribute \src "ls180.v:5875.41-5875.148" + cell $and $and$ls180.v:5875$1353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5875$1351_Y + connect \B $eq$ls180.v:5875$1352_Y + connect \Y $and$ls180.v:5875$1353_Y + end + attribute \src "ls180.v:5877.42-5877.95" + cell $and $and$ls180.v:5877$1354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5877$1354_Y + end + attribute \src "ls180.v:5877.41-5877.145" + cell $and $and$ls180.v:5877$1356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5877$1354_Y + connect \B $eq$ls180.v:5877$1355_Y + connect \Y $and$ls180.v:5877$1356_Y + end + attribute \src "ls180.v:5878.42-5878.98" + cell $and $and$ls180.v:5878$1358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5878$1357_Y + connect \Y $and$ls180.v:5878$1358_Y + end + attribute \src "ls180.v:5878.41-5878.148" + cell $and $and$ls180.v:5878$1360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5878$1358_Y + connect \B $eq$ls180.v:5878$1359_Y + connect \Y $and$ls180.v:5878$1360_Y + end + attribute \src "ls180.v:5880.42-5880.95" + cell $and $and$ls180.v:5880$1361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5880$1361_Y + end + attribute \src "ls180.v:5880.41-5880.145" + cell $and $and$ls180.v:5880$1363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5880$1361_Y + connect \B $eq$ls180.v:5880$1362_Y + connect \Y $and$ls180.v:5880$1363_Y + end + attribute \src "ls180.v:5881.42-5881.98" + cell $and $and$ls180.v:5881$1365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5881$1364_Y + connect \Y $and$ls180.v:5881$1365_Y + end + attribute \src "ls180.v:5881.41-5881.148" + cell $and $and$ls180.v:5881$1367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5881$1365_Y + connect \B $eq$ls180.v:5881$1366_Y + connect \Y $and$ls180.v:5881$1367_Y + end + attribute \src "ls180.v:5883.42-5883.95" + cell $and $and$ls180.v:5883$1368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5883$1368_Y + end + attribute \src "ls180.v:5883.41-5883.145" + cell $and $and$ls180.v:5883$1370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5883$1368_Y + connect \B $eq$ls180.v:5883$1369_Y + connect \Y $and$ls180.v:5883$1370_Y + end + attribute \src "ls180.v:5884.42-5884.98" + cell $and $and$ls180.v:5884$1372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5884$1371_Y + connect \Y $and$ls180.v:5884$1372_Y + end + attribute \src "ls180.v:5884.41-5884.148" + cell $and $and$ls180.v:5884$1374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5884$1372_Y + connect \B $eq$ls180.v:5884$1373_Y + connect \Y $and$ls180.v:5884$1374_Y + end + attribute \src "ls180.v:5886.44-5886.97" + cell $and $and$ls180.v:5886$1375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5886$1375_Y + end + attribute \src "ls180.v:5886.43-5886.147" + cell $and $and$ls180.v:5886$1377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5886$1375_Y + connect \B $eq$ls180.v:5886$1376_Y + connect \Y $and$ls180.v:5886$1377_Y + end + attribute \src "ls180.v:5887.44-5887.100" + cell $and $and$ls180.v:5887$1379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5887$1378_Y + connect \Y $and$ls180.v:5887$1379_Y + end + attribute \src "ls180.v:5887.43-5887.150" + cell $and $and$ls180.v:5887$1381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5887$1379_Y + connect \B $eq$ls180.v:5887$1380_Y + connect \Y $and$ls180.v:5887$1381_Y + end + attribute \src "ls180.v:5889.44-5889.97" + cell $and $and$ls180.v:5889$1382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5889$1382_Y + end + attribute \src "ls180.v:5889.43-5889.147" + cell $and $and$ls180.v:5889$1384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5889$1382_Y + connect \B $eq$ls180.v:5889$1383_Y + connect \Y $and$ls180.v:5889$1384_Y + end + attribute \src "ls180.v:5890.44-5890.100" + cell $and $and$ls180.v:5890$1386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5890$1385_Y + connect \Y $and$ls180.v:5890$1386_Y + end + attribute \src "ls180.v:5890.43-5890.150" + cell $and $and$ls180.v:5890$1388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5890$1386_Y + connect \B $eq$ls180.v:5890$1387_Y + connect \Y $and$ls180.v:5890$1388_Y + end + attribute \src "ls180.v:5892.44-5892.97" + cell $and $and$ls180.v:5892$1389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5892$1389_Y + end + attribute \src "ls180.v:5892.43-5892.148" + cell $and $and$ls180.v:5892$1391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5892$1389_Y + connect \B $eq$ls180.v:5892$1390_Y + connect \Y $and$ls180.v:5892$1391_Y + end + attribute \src "ls180.v:5893.44-5893.100" + cell $and $and$ls180.v:5893$1393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5893$1392_Y + connect \Y $and$ls180.v:5893$1393_Y + end + attribute \src "ls180.v:5893.43-5893.151" + cell $and $and$ls180.v:5893$1395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5893$1393_Y + connect \B $eq$ls180.v:5893$1394_Y + connect \Y $and$ls180.v:5893$1395_Y + end + attribute \src "ls180.v:5895.44-5895.97" + cell $and $and$ls180.v:5895$1396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5895$1396_Y + end + attribute \src "ls180.v:5895.43-5895.148" + cell $and $and$ls180.v:5895$1398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5895$1396_Y + connect \B $eq$ls180.v:5895$1397_Y + connect \Y $and$ls180.v:5895$1398_Y + end + attribute \src "ls180.v:5896.44-5896.100" + cell $and $and$ls180.v:5896$1400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5896$1399_Y + connect \Y $and$ls180.v:5896$1400_Y + end + attribute \src "ls180.v:5896.43-5896.151" + cell $and $and$ls180.v:5896$1402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5896$1400_Y + connect \B $eq$ls180.v:5896$1401_Y + connect \Y $and$ls180.v:5896$1402_Y + end + attribute \src "ls180.v:5898.44-5898.97" + cell $and $and$ls180.v:5898$1403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5898$1403_Y + end + attribute \src "ls180.v:5898.43-5898.148" + cell $and $and$ls180.v:5898$1405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5898$1403_Y + connect \B $eq$ls180.v:5898$1404_Y + connect \Y $and$ls180.v:5898$1405_Y + end + attribute \src "ls180.v:5899.44-5899.100" + cell $and $and$ls180.v:5899$1407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5899$1406_Y + connect \Y $and$ls180.v:5899$1407_Y + end + attribute \src "ls180.v:5899.43-5899.151" + cell $and $and$ls180.v:5899$1409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5899$1407_Y + connect \B $eq$ls180.v:5899$1408_Y + connect \Y $and$ls180.v:5899$1409_Y + end + attribute \src "ls180.v:5901.41-5901.94" + cell $and $and$ls180.v:5901$1410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5901$1410_Y + end + attribute \src "ls180.v:5901.40-5901.145" + cell $and $and$ls180.v:5901$1412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5901$1410_Y + connect \B $eq$ls180.v:5901$1411_Y + connect \Y $and$ls180.v:5901$1412_Y + end + attribute \src "ls180.v:5902.41-5902.97" + cell $and $and$ls180.v:5902$1414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5902$1413_Y + connect \Y $and$ls180.v:5902$1414_Y + end + attribute \src "ls180.v:5902.40-5902.148" + cell $and $and$ls180.v:5902$1416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5902$1414_Y + connect \B $eq$ls180.v:5902$1415_Y + connect \Y $and$ls180.v:5902$1416_Y + end + attribute \src "ls180.v:5904.42-5904.95" + cell $and $and$ls180.v:5904$1417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5904$1417_Y + end + attribute \src "ls180.v:5904.41-5904.146" + cell $and $and$ls180.v:5904$1419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5904$1417_Y + connect \B $eq$ls180.v:5904$1418_Y + connect \Y $and$ls180.v:5904$1419_Y + end + attribute \src "ls180.v:5905.42-5905.98" + cell $and $and$ls180.v:5905$1421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5905$1420_Y + connect \Y $and$ls180.v:5905$1421_Y + end + attribute \src "ls180.v:5905.41-5905.149" + cell $and $and$ls180.v:5905$1423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5905$1421_Y + connect \B $eq$ls180.v:5905$1422_Y + connect \Y $and$ls180.v:5905$1423_Y + end + attribute \src "ls180.v:5924.46-5924.99" + cell $and $and$ls180.v:5924$1425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5924$1425_Y + end + attribute \src "ls180.v:5924.45-5924.149" + cell $and $and$ls180.v:5924$1427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5924$1425_Y + connect \B $eq$ls180.v:5924$1426_Y + connect \Y $and$ls180.v:5924$1427_Y + end + attribute \src "ls180.v:5925.46-5925.102" + cell $and $and$ls180.v:5925$1429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5925$1428_Y + connect \Y $and$ls180.v:5925$1429_Y + end + attribute \src "ls180.v:5925.45-5925.152" + cell $and $and$ls180.v:5925$1431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5925$1429_Y + connect \B $eq$ls180.v:5925$1430_Y + connect \Y $and$ls180.v:5925$1431_Y + end + attribute \src "ls180.v:5927.46-5927.99" + cell $and $and$ls180.v:5927$1432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5927$1432_Y + end + attribute \src "ls180.v:5927.45-5927.149" + cell $and $and$ls180.v:5927$1434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5927$1432_Y + connect \B $eq$ls180.v:5927$1433_Y + connect \Y $and$ls180.v:5927$1434_Y + end + attribute \src "ls180.v:5928.46-5928.102" + cell $and $and$ls180.v:5928$1436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5928$1435_Y + connect \Y $and$ls180.v:5928$1436_Y + end + attribute \src "ls180.v:5928.45-5928.152" + cell $and $and$ls180.v:5928$1438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5928$1436_Y + connect \B $eq$ls180.v:5928$1437_Y + connect \Y $and$ls180.v:5928$1438_Y + end + attribute \src "ls180.v:5930.46-5930.99" + cell $and $and$ls180.v:5930$1439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5930$1439_Y + end + attribute \src "ls180.v:5930.45-5930.149" + cell $and $and$ls180.v:5930$1441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5930$1439_Y + connect \B $eq$ls180.v:5930$1440_Y + connect \Y $and$ls180.v:5930$1441_Y + end + attribute \src "ls180.v:5931.46-5931.102" + cell $and $and$ls180.v:5931$1443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5931$1442_Y + connect \Y $and$ls180.v:5931$1443_Y + end + attribute \src "ls180.v:5931.45-5931.152" + cell $and $and$ls180.v:5931$1445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5931$1443_Y + connect \B $eq$ls180.v:5931$1444_Y + connect \Y $and$ls180.v:5931$1445_Y + end + attribute \src "ls180.v:5933.46-5933.99" + cell $and $and$ls180.v:5933$1446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5933$1446_Y + end + attribute \src "ls180.v:5933.45-5933.149" + cell $and $and$ls180.v:5933$1448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5933$1446_Y + connect \B $eq$ls180.v:5933$1447_Y + connect \Y $and$ls180.v:5933$1448_Y + end + attribute \src "ls180.v:5934.46-5934.102" + cell $and $and$ls180.v:5934$1450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5934$1449_Y + connect \Y $and$ls180.v:5934$1450_Y + end + attribute \src "ls180.v:5934.45-5934.152" + cell $and $and$ls180.v:5934$1452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5934$1450_Y + connect \B $eq$ls180.v:5934$1451_Y + connect \Y $and$ls180.v:5934$1452_Y + end + attribute \src "ls180.v:5936.45-5936.98" + cell $and $and$ls180.v:5936$1453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5936$1453_Y + end + attribute \src "ls180.v:5936.44-5936.148" + cell $and $and$ls180.v:5936$1455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5936$1453_Y + connect \B $eq$ls180.v:5936$1454_Y + connect \Y $and$ls180.v:5936$1455_Y + end + attribute \src "ls180.v:5937.45-5937.101" + cell $and $and$ls180.v:5937$1457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5937$1456_Y + connect \Y $and$ls180.v:5937$1457_Y + end + attribute \src "ls180.v:5937.44-5937.151" + cell $and $and$ls180.v:5937$1459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5937$1457_Y + connect \B $eq$ls180.v:5937$1458_Y + connect \Y $and$ls180.v:5937$1459_Y + end + attribute \src "ls180.v:5939.45-5939.98" + cell $and $and$ls180.v:5939$1460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5939$1460_Y + end + attribute \src "ls180.v:5939.44-5939.148" + cell $and $and$ls180.v:5939$1462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5939$1460_Y + connect \B $eq$ls180.v:5939$1461_Y + connect \Y $and$ls180.v:5939$1462_Y + end + attribute \src "ls180.v:5940.45-5940.101" + cell $and $and$ls180.v:5940$1464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5940$1463_Y + connect \Y $and$ls180.v:5940$1464_Y + end + attribute \src "ls180.v:5940.44-5940.151" + cell $and $and$ls180.v:5940$1466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5940$1464_Y + connect \B $eq$ls180.v:5940$1465_Y + connect \Y $and$ls180.v:5940$1466_Y + end + attribute \src "ls180.v:5942.45-5942.98" + cell $and $and$ls180.v:5942$1467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5942$1467_Y + end + attribute \src "ls180.v:5942.44-5942.148" + cell $and $and$ls180.v:5942$1469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5942$1467_Y + connect \B $eq$ls180.v:5942$1468_Y + connect \Y $and$ls180.v:5942$1469_Y + end + attribute \src "ls180.v:5943.45-5943.101" + cell $and $and$ls180.v:5943$1471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5943$1470_Y + connect \Y $and$ls180.v:5943$1471_Y + end + attribute \src "ls180.v:5943.44-5943.151" + cell $and $and$ls180.v:5943$1473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5943$1471_Y + connect \B $eq$ls180.v:5943$1472_Y + connect \Y $and$ls180.v:5943$1473_Y + end + attribute \src "ls180.v:5945.45-5945.98" + cell $and $and$ls180.v:5945$1474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5945$1474_Y + end + attribute \src "ls180.v:5945.44-5945.148" + cell $and $and$ls180.v:5945$1476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5945$1474_Y + connect \B $eq$ls180.v:5945$1475_Y + connect \Y $and$ls180.v:5945$1476_Y + end + attribute \src "ls180.v:5946.45-5946.101" + cell $and $and$ls180.v:5946$1478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5946$1477_Y + connect \Y $and$ls180.v:5946$1478_Y + end + attribute \src "ls180.v:5946.44-5946.151" + cell $and $and$ls180.v:5946$1480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5946$1478_Y + connect \B $eq$ls180.v:5946$1479_Y + connect \Y $and$ls180.v:5946$1480_Y + end + attribute \src "ls180.v:5948.36-5948.89" + cell $and $and$ls180.v:5948$1481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5948$1481_Y + end + attribute \src "ls180.v:5948.35-5948.139" + cell $and $and$ls180.v:5948$1483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5948$1481_Y + connect \B $eq$ls180.v:5948$1482_Y + connect \Y $and$ls180.v:5948$1483_Y + end + attribute \src "ls180.v:5949.36-5949.92" + cell $and $and$ls180.v:5949$1485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5949$1484_Y + connect \Y $and$ls180.v:5949$1485_Y + end + attribute \src "ls180.v:5949.35-5949.142" + cell $and $and$ls180.v:5949$1487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5949$1485_Y + connect \B $eq$ls180.v:5949$1486_Y + connect \Y $and$ls180.v:5949$1487_Y + end + attribute \src "ls180.v:5951.47-5951.100" + cell $and $and$ls180.v:5951$1488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5951$1488_Y + end + attribute \src "ls180.v:5951.46-5951.150" + cell $and $and$ls180.v:5951$1490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5951$1488_Y + connect \B $eq$ls180.v:5951$1489_Y + connect \Y $and$ls180.v:5951$1490_Y + end + attribute \src "ls180.v:5952.47-5952.103" + cell $and $and$ls180.v:5952$1492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5952$1491_Y + connect \Y $and$ls180.v:5952$1492_Y + end + attribute \src "ls180.v:5952.46-5952.153" + cell $and $and$ls180.v:5952$1494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5952$1492_Y + connect \B $eq$ls180.v:5952$1493_Y + connect \Y $and$ls180.v:5952$1494_Y + end + attribute \src "ls180.v:5954.47-5954.100" + cell $and $and$ls180.v:5954$1495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5954$1495_Y + end + attribute \src "ls180.v:5954.46-5954.151" + cell $and $and$ls180.v:5954$1497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5954$1495_Y + connect \B $eq$ls180.v:5954$1496_Y + connect \Y $and$ls180.v:5954$1497_Y + end + attribute \src "ls180.v:5955.47-5955.103" + cell $and $and$ls180.v:5955$1499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5955$1498_Y + connect \Y $and$ls180.v:5955$1499_Y + end + attribute \src "ls180.v:5955.46-5955.154" + cell $and $and$ls180.v:5955$1501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5955$1499_Y + connect \B $eq$ls180.v:5955$1500_Y + connect \Y $and$ls180.v:5955$1501_Y + end + attribute \src "ls180.v:5957.47-5957.100" + cell $and $and$ls180.v:5957$1502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5957$1502_Y + end + attribute \src "ls180.v:5957.46-5957.151" + cell $and $and$ls180.v:5957$1504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5957$1502_Y + connect \B $eq$ls180.v:5957$1503_Y + connect \Y $and$ls180.v:5957$1504_Y + end + attribute \src "ls180.v:5958.47-5958.103" + cell $and $and$ls180.v:5958$1506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5958$1505_Y + connect \Y $and$ls180.v:5958$1506_Y + end + attribute \src "ls180.v:5958.46-5958.154" + cell $and $and$ls180.v:5958$1508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5958$1506_Y + connect \B $eq$ls180.v:5958$1507_Y + connect \Y $and$ls180.v:5958$1508_Y + end + attribute \src "ls180.v:5960.47-5960.100" + cell $and $and$ls180.v:5960$1509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5960$1509_Y + end + attribute \src "ls180.v:5960.46-5960.151" + cell $and $and$ls180.v:5960$1511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5960$1509_Y + connect \B $eq$ls180.v:5960$1510_Y + connect \Y $and$ls180.v:5960$1511_Y + end + attribute \src "ls180.v:5961.47-5961.103" + cell $and $and$ls180.v:5961$1513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5961$1512_Y + connect \Y $and$ls180.v:5961$1513_Y + end + attribute \src "ls180.v:5961.46-5961.154" + cell $and $and$ls180.v:5961$1515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5961$1513_Y + connect \B $eq$ls180.v:5961$1514_Y + connect \Y $and$ls180.v:5961$1515_Y + end + attribute \src "ls180.v:5963.47-5963.100" + cell $and $and$ls180.v:5963$1516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5963$1516_Y + end + attribute \src "ls180.v:5963.46-5963.151" + cell $and $and$ls180.v:5963$1518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5963$1516_Y + connect \B $eq$ls180.v:5963$1517_Y + connect \Y $and$ls180.v:5963$1518_Y + end + attribute \src "ls180.v:5964.47-5964.103" + cell $and $and$ls180.v:5964$1520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5964$1519_Y + connect \Y $and$ls180.v:5964$1520_Y + end + attribute \src "ls180.v:5964.46-5964.154" + cell $and $and$ls180.v:5964$1522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5964$1520_Y + connect \B $eq$ls180.v:5964$1521_Y + connect \Y $and$ls180.v:5964$1522_Y + end + attribute \src "ls180.v:5966.47-5966.100" + cell $and $and$ls180.v:5966$1523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5966$1523_Y + end + attribute \src "ls180.v:5966.46-5966.151" + cell $and $and$ls180.v:5966$1525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5966$1523_Y + connect \B $eq$ls180.v:5966$1524_Y + connect \Y $and$ls180.v:5966$1525_Y + end + attribute \src "ls180.v:5967.47-5967.103" + cell $and $and$ls180.v:5967$1527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5967$1526_Y + connect \Y $and$ls180.v:5967$1527_Y + end + attribute \src "ls180.v:5967.46-5967.154" + cell $and $and$ls180.v:5967$1529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5967$1527_Y + connect \B $eq$ls180.v:5967$1528_Y + connect \Y $and$ls180.v:5967$1529_Y + end + attribute \src "ls180.v:5969.46-5969.99" + cell $and $and$ls180.v:5969$1530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5969$1530_Y + end + attribute \src "ls180.v:5969.45-5969.150" + cell $and $and$ls180.v:5969$1532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5969$1530_Y + connect \B $eq$ls180.v:5969$1531_Y + connect \Y $and$ls180.v:5969$1532_Y + end + attribute \src "ls180.v:5970.46-5970.102" + cell $and $and$ls180.v:5970$1534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5970$1533_Y + connect \Y $and$ls180.v:5970$1534_Y + end + attribute \src "ls180.v:5970.45-5970.153" + cell $and $and$ls180.v:5970$1536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5970$1534_Y + connect \B $eq$ls180.v:5970$1535_Y + connect \Y $and$ls180.v:5970$1536_Y + end + attribute \src "ls180.v:5972.46-5972.99" + cell $and $and$ls180.v:5972$1537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5972$1537_Y + end + attribute \src "ls180.v:5972.45-5972.150" + cell $and $and$ls180.v:5972$1539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5972$1537_Y + connect \B $eq$ls180.v:5972$1538_Y + connect \Y $and$ls180.v:5972$1539_Y + end + attribute \src "ls180.v:5973.46-5973.102" + cell $and $and$ls180.v:5973$1541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5973$1540_Y + connect \Y $and$ls180.v:5973$1541_Y + end + attribute \src "ls180.v:5973.45-5973.153" + cell $and $and$ls180.v:5973$1543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5973$1541_Y + connect \B $eq$ls180.v:5973$1542_Y + connect \Y $and$ls180.v:5973$1543_Y + end + attribute \src "ls180.v:5975.46-5975.99" + cell $and $and$ls180.v:5975$1544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5975$1544_Y + end + attribute \src "ls180.v:5975.45-5975.150" + cell $and $and$ls180.v:5975$1546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5975$1544_Y + connect \B $eq$ls180.v:5975$1545_Y + connect \Y $and$ls180.v:5975$1546_Y + end + attribute \src "ls180.v:5976.46-5976.102" + cell $and $and$ls180.v:5976$1548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5976$1547_Y + connect \Y $and$ls180.v:5976$1548_Y + end + attribute \src "ls180.v:5976.45-5976.153" + cell $and $and$ls180.v:5976$1550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5976$1548_Y + connect \B $eq$ls180.v:5976$1549_Y + connect \Y $and$ls180.v:5976$1550_Y + end + attribute \src "ls180.v:5978.46-5978.99" + cell $and $and$ls180.v:5978$1551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5978$1551_Y + end + attribute \src "ls180.v:5978.45-5978.150" + cell $and $and$ls180.v:5978$1553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5978$1551_Y + connect \B $eq$ls180.v:5978$1552_Y + connect \Y $and$ls180.v:5978$1553_Y + end + attribute \src "ls180.v:5979.46-5979.102" + cell $and $and$ls180.v:5979$1555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5979$1554_Y + connect \Y $and$ls180.v:5979$1555_Y + end + attribute \src "ls180.v:5979.45-5979.153" + cell $and $and$ls180.v:5979$1557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5979$1555_Y + connect \B $eq$ls180.v:5979$1556_Y + connect \Y $and$ls180.v:5979$1557_Y + end + attribute \src "ls180.v:5981.46-5981.99" + cell $and $and$ls180.v:5981$1558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5981$1558_Y + end + attribute \src "ls180.v:5981.45-5981.150" + cell $and $and$ls180.v:5981$1560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5981$1558_Y + connect \B $eq$ls180.v:5981$1559_Y + connect \Y $and$ls180.v:5981$1560_Y + end + attribute \src "ls180.v:5982.46-5982.102" + cell $and $and$ls180.v:5982$1562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5982$1561_Y + connect \Y $and$ls180.v:5982$1562_Y + end + attribute \src "ls180.v:5982.45-5982.153" + cell $and $and$ls180.v:5982$1564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5982$1562_Y + connect \B $eq$ls180.v:5982$1563_Y + connect \Y $and$ls180.v:5982$1564_Y + end + attribute \src "ls180.v:5984.46-5984.99" + cell $and $and$ls180.v:5984$1565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5984$1565_Y + end + attribute \src "ls180.v:5984.45-5984.150" + cell $and $and$ls180.v:5984$1567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5984$1565_Y + connect \B $eq$ls180.v:5984$1566_Y + connect \Y $and$ls180.v:5984$1567_Y + end + attribute \src "ls180.v:5985.46-5985.102" + cell $and $and$ls180.v:5985$1569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5985$1568_Y + connect \Y $and$ls180.v:5985$1569_Y + end + attribute \src "ls180.v:5985.45-5985.153" + cell $and $and$ls180.v:5985$1571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5985$1569_Y + connect \B $eq$ls180.v:5985$1570_Y + connect \Y $and$ls180.v:5985$1571_Y + end + attribute \src "ls180.v:5987.46-5987.99" + cell $and $and$ls180.v:5987$1572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5987$1572_Y + end + attribute \src "ls180.v:5987.45-5987.150" + cell $and $and$ls180.v:5987$1574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5987$1572_Y + connect \B $eq$ls180.v:5987$1573_Y + connect \Y $and$ls180.v:5987$1574_Y + end + attribute \src "ls180.v:5988.46-5988.102" + cell $and $and$ls180.v:5988$1576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5988$1575_Y + connect \Y $and$ls180.v:5988$1576_Y + end + attribute \src "ls180.v:5988.45-5988.153" + cell $and $and$ls180.v:5988$1578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5988$1576_Y + connect \B $eq$ls180.v:5988$1577_Y + connect \Y $and$ls180.v:5988$1578_Y + end + attribute \src "ls180.v:5990.46-5990.99" + cell $and $and$ls180.v:5990$1579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5990$1579_Y + end + attribute \src "ls180.v:5990.45-5990.150" + cell $and $and$ls180.v:5990$1581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5990$1579_Y + connect \B $eq$ls180.v:5990$1580_Y + connect \Y $and$ls180.v:5990$1581_Y + end + attribute \src "ls180.v:5991.46-5991.102" + cell $and $and$ls180.v:5991$1583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5991$1582_Y + connect \Y $and$ls180.v:5991$1583_Y + end + attribute \src "ls180.v:5991.45-5991.153" + cell $and $and$ls180.v:5991$1585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5991$1583_Y + connect \B $eq$ls180.v:5991$1584_Y + connect \Y $and$ls180.v:5991$1585_Y + end + attribute \src "ls180.v:5993.46-5993.99" + cell $and $and$ls180.v:5993$1586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5993$1586_Y + end + attribute \src "ls180.v:5993.45-5993.150" + cell $and $and$ls180.v:5993$1588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5993$1586_Y + connect \B $eq$ls180.v:5993$1587_Y + connect \Y $and$ls180.v:5993$1588_Y + end + attribute \src "ls180.v:5994.46-5994.102" + cell $and $and$ls180.v:5994$1590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5994$1589_Y + connect \Y $and$ls180.v:5994$1590_Y + end + attribute \src "ls180.v:5994.45-5994.153" + cell $and $and$ls180.v:5994$1592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5994$1590_Y + connect \B $eq$ls180.v:5994$1591_Y + connect \Y $and$ls180.v:5994$1592_Y + end + attribute \src "ls180.v:5996.46-5996.99" + cell $and $and$ls180.v:5996$1593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5996$1593_Y + end + attribute \src "ls180.v:5996.45-5996.150" + cell $and $and$ls180.v:5996$1595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5996$1593_Y + connect \B $eq$ls180.v:5996$1594_Y + connect \Y $and$ls180.v:5996$1595_Y + end + attribute \src "ls180.v:5997.46-5997.102" + cell $and $and$ls180.v:5997$1597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5997$1596_Y + connect \Y $and$ls180.v:5997$1597_Y + end + attribute \src "ls180.v:5997.45-5997.153" + cell $and $and$ls180.v:5997$1599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5997$1597_Y + connect \B $eq$ls180.v:5997$1598_Y + connect \Y $and$ls180.v:5997$1599_Y + end + attribute \src "ls180.v:5999.42-5999.95" + cell $and $and$ls180.v:5999$1600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5999$1600_Y + end + attribute \src "ls180.v:5999.41-5999.146" + cell $and $and$ls180.v:5999$1602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5999$1600_Y + connect \B $eq$ls180.v:5999$1601_Y + connect \Y $and$ls180.v:5999$1602_Y + end + attribute \src "ls180.v:6000.42-6000.98" + cell $and $and$ls180.v:6000$1604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6000$1603_Y + connect \Y $and$ls180.v:6000$1604_Y + end + attribute \src "ls180.v:6000.41-6000.149" + cell $and $and$ls180.v:6000$1606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6000$1604_Y + connect \B $eq$ls180.v:6000$1605_Y + connect \Y $and$ls180.v:6000$1606_Y + end + attribute \src "ls180.v:6002.43-6002.96" + cell $and $and$ls180.v:6002$1607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6002$1607_Y + end + attribute \src "ls180.v:6002.42-6002.147" + cell $and $and$ls180.v:6002$1609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6002$1607_Y + connect \B $eq$ls180.v:6002$1608_Y + connect \Y $and$ls180.v:6002$1609_Y + end + attribute \src "ls180.v:6003.43-6003.99" + cell $and $and$ls180.v:6003$1611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6003$1610_Y + connect \Y $and$ls180.v:6003$1611_Y + end + attribute \src "ls180.v:6003.42-6003.150" + cell $and $and$ls180.v:6003$1613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6003$1611_Y + connect \B $eq$ls180.v:6003$1612_Y + connect \Y $and$ls180.v:6003$1613_Y + end + attribute \src "ls180.v:6005.46-6005.99" + cell $and $and$ls180.v:6005$1614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6005$1614_Y + end + attribute \src "ls180.v:6005.45-6005.150" + cell $and $and$ls180.v:6005$1616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6005$1614_Y + connect \B $eq$ls180.v:6005$1615_Y + connect \Y $and$ls180.v:6005$1616_Y + end + attribute \src "ls180.v:6006.46-6006.102" + cell $and $and$ls180.v:6006$1618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6006$1617_Y + connect \Y $and$ls180.v:6006$1618_Y + end + attribute \src "ls180.v:6006.45-6006.153" + cell $and $and$ls180.v:6006$1620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6006$1618_Y + connect \B $eq$ls180.v:6006$1619_Y + connect \Y $and$ls180.v:6006$1620_Y + end + attribute \src "ls180.v:6008.46-6008.99" + cell $and $and$ls180.v:6008$1621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6008$1621_Y + end + attribute \src "ls180.v:6008.45-6008.150" + cell $and $and$ls180.v:6008$1623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6008$1621_Y + connect \B $eq$ls180.v:6008$1622_Y + connect \Y $and$ls180.v:6008$1623_Y + end + attribute \src "ls180.v:6009.46-6009.102" + cell $and $and$ls180.v:6009$1625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6009$1624_Y + connect \Y $and$ls180.v:6009$1625_Y + end + attribute \src "ls180.v:6009.45-6009.153" + cell $and $and$ls180.v:6009$1627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6009$1625_Y + connect \B $eq$ls180.v:6009$1626_Y + connect \Y $and$ls180.v:6009$1627_Y + end + attribute \src "ls180.v:6011.45-6011.98" + cell $and $and$ls180.v:6011$1628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6011$1628_Y + end + attribute \src "ls180.v:6011.44-6011.149" + cell $and $and$ls180.v:6011$1630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6011$1628_Y + connect \B $eq$ls180.v:6011$1629_Y + connect \Y $and$ls180.v:6011$1630_Y + end + attribute \src "ls180.v:6012.45-6012.101" + cell $and $and$ls180.v:6012$1632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6012$1631_Y + connect \Y $and$ls180.v:6012$1632_Y + end + attribute \src "ls180.v:6012.44-6012.152" + cell $and $and$ls180.v:6012$1634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6012$1632_Y + connect \B $eq$ls180.v:6012$1633_Y + connect \Y $and$ls180.v:6012$1634_Y + end + attribute \src "ls180.v:6014.45-6014.98" + cell $and $and$ls180.v:6014$1635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6014$1635_Y + end + attribute \src "ls180.v:6014.44-6014.149" + cell $and $and$ls180.v:6014$1637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6014$1635_Y + connect \B $eq$ls180.v:6014$1636_Y + connect \Y $and$ls180.v:6014$1637_Y + end + attribute \src "ls180.v:6015.45-6015.101" + cell $and $and$ls180.v:6015$1639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6015$1638_Y + connect \Y $and$ls180.v:6015$1639_Y + end + attribute \src "ls180.v:6015.44-6015.152" + cell $and $and$ls180.v:6015$1641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6015$1639_Y + connect \B $eq$ls180.v:6015$1640_Y + connect \Y $and$ls180.v:6015$1641_Y + end + attribute \src "ls180.v:6017.45-6017.98" + cell $and $and$ls180.v:6017$1642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6017$1642_Y + end + attribute \src "ls180.v:6017.44-6017.149" + cell $and $and$ls180.v:6017$1644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6017$1642_Y + connect \B $eq$ls180.v:6017$1643_Y + connect \Y $and$ls180.v:6017$1644_Y + end + attribute \src "ls180.v:6018.45-6018.101" + cell $and $and$ls180.v:6018$1646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6018$1645_Y + connect \Y $and$ls180.v:6018$1646_Y + end + attribute \src "ls180.v:6018.44-6018.152" + cell $and $and$ls180.v:6018$1648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6018$1646_Y + connect \B $eq$ls180.v:6018$1647_Y + connect \Y $and$ls180.v:6018$1648_Y + end + attribute \src "ls180.v:6020.45-6020.98" + cell $and $and$ls180.v:6020$1649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6020$1649_Y + end + attribute \src "ls180.v:6020.44-6020.149" + cell $and $and$ls180.v:6020$1651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6020$1649_Y + connect \B $eq$ls180.v:6020$1650_Y + connect \Y $and$ls180.v:6020$1651_Y + end + attribute \src "ls180.v:6021.45-6021.101" + cell $and $and$ls180.v:6021$1653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6021$1652_Y + connect \Y $and$ls180.v:6021$1653_Y + end + attribute \src "ls180.v:6021.44-6021.152" + cell $and $and$ls180.v:6021$1655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6021$1653_Y + connect \B $eq$ls180.v:6021$1654_Y + connect \Y $and$ls180.v:6021$1655_Y + end + attribute \src "ls180.v:6059.42-6059.95" + cell $and $and$ls180.v:6059$1657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6059$1657_Y + end + attribute \src "ls180.v:6059.41-6059.145" + cell $and $and$ls180.v:6059$1659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6059$1657_Y + connect \B $eq$ls180.v:6059$1658_Y + connect \Y $and$ls180.v:6059$1659_Y + end + attribute \src "ls180.v:6060.42-6060.98" + cell $and $and$ls180.v:6060$1661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6060$1660_Y + connect \Y $and$ls180.v:6060$1661_Y + end + attribute \src "ls180.v:6060.41-6060.148" + cell $and $and$ls180.v:6060$1663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6060$1661_Y + connect \B $eq$ls180.v:6060$1662_Y + connect \Y $and$ls180.v:6060$1663_Y + end + attribute \src "ls180.v:6062.42-6062.95" + cell $and $and$ls180.v:6062$1664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6062$1664_Y + end + attribute \src "ls180.v:6062.41-6062.145" + cell $and $and$ls180.v:6062$1666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6062$1664_Y + connect \B $eq$ls180.v:6062$1665_Y + connect \Y $and$ls180.v:6062$1666_Y + end + attribute \src "ls180.v:6063.42-6063.98" + cell $and $and$ls180.v:6063$1668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6063$1667_Y + connect \Y $and$ls180.v:6063$1668_Y + end + attribute \src "ls180.v:6063.41-6063.148" + cell $and $and$ls180.v:6063$1670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6063$1668_Y + connect \B $eq$ls180.v:6063$1669_Y + connect \Y $and$ls180.v:6063$1670_Y + end + attribute \src "ls180.v:6065.42-6065.95" + cell $and $and$ls180.v:6065$1671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6065$1671_Y + end + attribute \src "ls180.v:6065.41-6065.145" + cell $and $and$ls180.v:6065$1673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6065$1671_Y + connect \B $eq$ls180.v:6065$1672_Y + connect \Y $and$ls180.v:6065$1673_Y + end + attribute \src "ls180.v:6066.42-6066.98" + cell $and $and$ls180.v:6066$1675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6066$1674_Y + connect \Y $and$ls180.v:6066$1675_Y + end + attribute \src "ls180.v:6066.41-6066.148" + cell $and $and$ls180.v:6066$1677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6066$1675_Y + connect \B $eq$ls180.v:6066$1676_Y + connect \Y $and$ls180.v:6066$1677_Y + end + attribute \src "ls180.v:6068.42-6068.95" + cell $and $and$ls180.v:6068$1678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6068$1678_Y + end + attribute \src "ls180.v:6068.41-6068.145" + cell $and $and$ls180.v:6068$1680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6068$1678_Y + connect \B $eq$ls180.v:6068$1679_Y + connect \Y $and$ls180.v:6068$1680_Y + end + attribute \src "ls180.v:6069.42-6069.98" + cell $and $and$ls180.v:6069$1682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6069$1681_Y + connect \Y $and$ls180.v:6069$1682_Y + end + attribute \src "ls180.v:6069.41-6069.148" + cell $and $and$ls180.v:6069$1684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6069$1682_Y + connect \B $eq$ls180.v:6069$1683_Y + connect \Y $and$ls180.v:6069$1684_Y + end + attribute \src "ls180.v:6071.42-6071.95" + cell $and $and$ls180.v:6071$1685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6071$1685_Y + end + attribute \src "ls180.v:6071.41-6071.145" + cell $and $and$ls180.v:6071$1687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6071$1685_Y + connect \B $eq$ls180.v:6071$1686_Y + connect \Y $and$ls180.v:6071$1687_Y + end + attribute \src "ls180.v:6072.42-6072.98" + cell $and $and$ls180.v:6072$1689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6072$1688_Y + connect \Y $and$ls180.v:6072$1689_Y + end + attribute \src "ls180.v:6072.41-6072.148" + cell $and $and$ls180.v:6072$1691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6072$1689_Y + connect \B $eq$ls180.v:6072$1690_Y + connect \Y $and$ls180.v:6072$1691_Y + end + attribute \src "ls180.v:6074.42-6074.95" + cell $and $and$ls180.v:6074$1692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6074$1692_Y + end + attribute \src "ls180.v:6074.41-6074.145" + cell $and $and$ls180.v:6074$1694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6074$1692_Y + connect \B $eq$ls180.v:6074$1693_Y + connect \Y $and$ls180.v:6074$1694_Y + end + attribute \src "ls180.v:6075.42-6075.98" + cell $and $and$ls180.v:6075$1696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6075$1695_Y + connect \Y $and$ls180.v:6075$1696_Y + end + attribute \src "ls180.v:6075.41-6075.148" + cell $and $and$ls180.v:6075$1698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6075$1696_Y + connect \B $eq$ls180.v:6075$1697_Y + connect \Y $and$ls180.v:6075$1698_Y + end + attribute \src "ls180.v:6077.42-6077.95" + cell $and $and$ls180.v:6077$1699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6077$1699_Y + end + attribute \src "ls180.v:6077.41-6077.145" + cell $and $and$ls180.v:6077$1701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6077$1699_Y + connect \B $eq$ls180.v:6077$1700_Y + connect \Y $and$ls180.v:6077$1701_Y + end + attribute \src "ls180.v:6078.42-6078.98" + cell $and $and$ls180.v:6078$1703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6078$1702_Y + connect \Y $and$ls180.v:6078$1703_Y + end + attribute \src "ls180.v:6078.41-6078.148" + cell $and $and$ls180.v:6078$1705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6078$1703_Y + connect \B $eq$ls180.v:6078$1704_Y + connect \Y $and$ls180.v:6078$1705_Y + end + attribute \src "ls180.v:6080.42-6080.95" + cell $and $and$ls180.v:6080$1706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6080$1706_Y + end + attribute \src "ls180.v:6080.41-6080.145" + cell $and $and$ls180.v:6080$1708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6080$1706_Y + connect \B $eq$ls180.v:6080$1707_Y + connect \Y $and$ls180.v:6080$1708_Y + end + attribute \src "ls180.v:6081.42-6081.98" + cell $and $and$ls180.v:6081$1710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6081$1709_Y + connect \Y $and$ls180.v:6081$1710_Y + end + attribute \src "ls180.v:6081.41-6081.148" + cell $and $and$ls180.v:6081$1712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6081$1710_Y + connect \B $eq$ls180.v:6081$1711_Y + connect \Y $and$ls180.v:6081$1712_Y + end + attribute \src "ls180.v:6083.44-6083.97" + cell $and $and$ls180.v:6083$1713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6083$1713_Y + end + attribute \src "ls180.v:6083.43-6083.147" + cell $and $and$ls180.v:6083$1715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6083$1713_Y + connect \B $eq$ls180.v:6083$1714_Y + connect \Y $and$ls180.v:6083$1715_Y + end + attribute \src "ls180.v:6084.44-6084.100" + cell $and $and$ls180.v:6084$1717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6084$1716_Y + connect \Y $and$ls180.v:6084$1717_Y + end + attribute \src "ls180.v:6084.43-6084.150" + cell $and $and$ls180.v:6084$1719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6084$1717_Y + connect \B $eq$ls180.v:6084$1718_Y + connect \Y $and$ls180.v:6084$1719_Y + end + attribute \src "ls180.v:6086.44-6086.97" + cell $and $and$ls180.v:6086$1720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6086$1720_Y + end + attribute \src "ls180.v:6086.43-6086.147" + cell $and $and$ls180.v:6086$1722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6086$1720_Y + connect \B $eq$ls180.v:6086$1721_Y + connect \Y $and$ls180.v:6086$1722_Y + end + attribute \src "ls180.v:6087.44-6087.100" + cell $and $and$ls180.v:6087$1724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6087$1723_Y + connect \Y $and$ls180.v:6087$1724_Y + end + attribute \src "ls180.v:6087.43-6087.150" + cell $and $and$ls180.v:6087$1726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6087$1724_Y + connect \B $eq$ls180.v:6087$1725_Y + connect \Y $and$ls180.v:6087$1726_Y + end + attribute \src "ls180.v:6089.44-6089.97" + cell $and $and$ls180.v:6089$1727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6089$1727_Y + end + attribute \src "ls180.v:6089.43-6089.148" + cell $and $and$ls180.v:6089$1729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6089$1727_Y + connect \B $eq$ls180.v:6089$1728_Y + connect \Y $and$ls180.v:6089$1729_Y + end + attribute \src "ls180.v:6090.44-6090.100" + cell $and $and$ls180.v:6090$1731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6090$1730_Y + connect \Y $and$ls180.v:6090$1731_Y + end + attribute \src "ls180.v:6090.43-6090.151" + cell $and $and$ls180.v:6090$1733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6090$1731_Y + connect \B $eq$ls180.v:6090$1732_Y + connect \Y $and$ls180.v:6090$1733_Y + end + attribute \src "ls180.v:6092.44-6092.97" + cell $and $and$ls180.v:6092$1734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6092$1734_Y + end + attribute \src "ls180.v:6092.43-6092.148" + cell $and $and$ls180.v:6092$1736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6092$1734_Y + connect \B $eq$ls180.v:6092$1735_Y + connect \Y $and$ls180.v:6092$1736_Y + end + attribute \src "ls180.v:6093.44-6093.100" + cell $and $and$ls180.v:6093$1738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6093$1737_Y + connect \Y $and$ls180.v:6093$1738_Y + end + attribute \src "ls180.v:6093.43-6093.151" + cell $and $and$ls180.v:6093$1740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6093$1738_Y + connect \B $eq$ls180.v:6093$1739_Y + connect \Y $and$ls180.v:6093$1740_Y + end + attribute \src "ls180.v:6095.44-6095.97" + cell $and $and$ls180.v:6095$1741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6095$1741_Y + end + attribute \src "ls180.v:6095.43-6095.148" + cell $and $and$ls180.v:6095$1743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6095$1741_Y + connect \B $eq$ls180.v:6095$1742_Y + connect \Y $and$ls180.v:6095$1743_Y + end + attribute \src "ls180.v:6096.44-6096.100" + cell $and $and$ls180.v:6096$1745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6096$1744_Y + connect \Y $and$ls180.v:6096$1745_Y + end + attribute \src "ls180.v:6096.43-6096.151" + cell $and $and$ls180.v:6096$1747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6096$1745_Y + connect \B $eq$ls180.v:6096$1746_Y + connect \Y $and$ls180.v:6096$1747_Y + end + attribute \src "ls180.v:6098.41-6098.94" + cell $and $and$ls180.v:6098$1748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6098$1748_Y + end + attribute \src "ls180.v:6098.40-6098.145" + cell $and $and$ls180.v:6098$1750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6098$1748_Y + connect \B $eq$ls180.v:6098$1749_Y + connect \Y $and$ls180.v:6098$1750_Y + end + attribute \src "ls180.v:6099.41-6099.97" + cell $and $and$ls180.v:6099$1752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6099$1751_Y + connect \Y $and$ls180.v:6099$1752_Y + end + attribute \src "ls180.v:6099.40-6099.148" + cell $and $and$ls180.v:6099$1754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6099$1752_Y + connect \B $eq$ls180.v:6099$1753_Y + connect \Y $and$ls180.v:6099$1754_Y + end + attribute \src "ls180.v:6101.42-6101.95" + cell $and $and$ls180.v:6101$1755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6101$1755_Y + end + attribute \src "ls180.v:6101.41-6101.146" + cell $and $and$ls180.v:6101$1757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6101$1755_Y + connect \B $eq$ls180.v:6101$1756_Y + connect \Y $and$ls180.v:6101$1757_Y + end + attribute \src "ls180.v:6102.42-6102.98" + cell $and $and$ls180.v:6102$1759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6102$1758_Y + connect \Y $and$ls180.v:6102$1759_Y + end + attribute \src "ls180.v:6102.41-6102.149" + cell $and $and$ls180.v:6102$1761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6102$1759_Y + connect \B $eq$ls180.v:6102$1760_Y + connect \Y $and$ls180.v:6102$1761_Y + end + attribute \src "ls180.v:6104.44-6104.97" + cell $and $and$ls180.v:6104$1762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6104$1762_Y + end + attribute \src "ls180.v:6104.43-6104.148" + cell $and $and$ls180.v:6104$1764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6104$1762_Y + connect \B $eq$ls180.v:6104$1763_Y + connect \Y $and$ls180.v:6104$1764_Y + end + attribute \src "ls180.v:6105.44-6105.100" + cell $and $and$ls180.v:6105$1766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6105$1765_Y + connect \Y $and$ls180.v:6105$1766_Y + end + attribute \src "ls180.v:6105.43-6105.151" + cell $and $and$ls180.v:6105$1768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6105$1766_Y + connect \B $eq$ls180.v:6105$1767_Y + connect \Y $and$ls180.v:6105$1768_Y + end + attribute \src "ls180.v:6107.44-6107.97" + cell $and $and$ls180.v:6107$1769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6107$1769_Y + end + attribute \src "ls180.v:6107.43-6107.148" + cell $and $and$ls180.v:6107$1771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6107$1769_Y + connect \B $eq$ls180.v:6107$1770_Y + connect \Y $and$ls180.v:6107$1771_Y + end + attribute \src "ls180.v:6108.44-6108.100" + cell $and $and$ls180.v:6108$1773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6108$1772_Y + connect \Y $and$ls180.v:6108$1773_Y + end + attribute \src "ls180.v:6108.43-6108.151" + cell $and $and$ls180.v:6108$1775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6108$1773_Y + connect \B $eq$ls180.v:6108$1774_Y + connect \Y $and$ls180.v:6108$1775_Y + end + attribute \src "ls180.v:6110.44-6110.97" + cell $and $and$ls180.v:6110$1776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6110$1776_Y + end + attribute \src "ls180.v:6110.43-6110.148" + cell $and $and$ls180.v:6110$1778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6110$1776_Y + connect \B $eq$ls180.v:6110$1777_Y + connect \Y $and$ls180.v:6110$1778_Y + end + attribute \src "ls180.v:6111.44-6111.100" + cell $and $and$ls180.v:6111$1780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6111$1779_Y + connect \Y $and$ls180.v:6111$1780_Y + end + attribute \src "ls180.v:6111.43-6111.151" + cell $and $and$ls180.v:6111$1782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6111$1780_Y + connect \B $eq$ls180.v:6111$1781_Y + connect \Y $and$ls180.v:6111$1782_Y + end + attribute \src "ls180.v:6113.44-6113.97" + cell $and $and$ls180.v:6113$1783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6113$1783_Y + end + attribute \src "ls180.v:6113.43-6113.148" + cell $and $and$ls180.v:6113$1785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6113$1783_Y + connect \B $eq$ls180.v:6113$1784_Y + connect \Y $and$ls180.v:6113$1785_Y + end + attribute \src "ls180.v:6114.44-6114.100" + cell $and $and$ls180.v:6114$1787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6114$1786_Y + connect \Y $and$ls180.v:6114$1787_Y + end + attribute \src "ls180.v:6114.43-6114.151" + cell $and $and$ls180.v:6114$1789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6114$1787_Y + connect \B $eq$ls180.v:6114$1788_Y + connect \Y $and$ls180.v:6114$1789_Y + end + attribute \src "ls180.v:6138.44-6138.97" + cell $and $and$ls180.v:6138$1791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6138$1791_Y + end + attribute \src "ls180.v:6138.43-6138.147" + cell $and $and$ls180.v:6138$1793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6138$1791_Y + connect \B $eq$ls180.v:6138$1792_Y + connect \Y $and$ls180.v:6138$1793_Y + end + attribute \src "ls180.v:6139.44-6139.100" + cell $and $and$ls180.v:6139$1795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6139$1794_Y + connect \Y $and$ls180.v:6139$1795_Y + end + attribute \src "ls180.v:6139.43-6139.150" + cell $and $and$ls180.v:6139$1797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6139$1795_Y + connect \B $eq$ls180.v:6139$1796_Y + connect \Y $and$ls180.v:6139$1797_Y + end + attribute \src "ls180.v:6141.49-6141.102" + cell $and $and$ls180.v:6141$1798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6141$1798_Y + end + attribute \src "ls180.v:6141.48-6141.152" + cell $and $and$ls180.v:6141$1800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6141$1798_Y + connect \B $eq$ls180.v:6141$1799_Y + connect \Y $and$ls180.v:6141$1800_Y + end + attribute \src "ls180.v:6142.49-6142.105" + cell $and $and$ls180.v:6142$1802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6142$1801_Y + connect \Y $and$ls180.v:6142$1802_Y + end + attribute \src "ls180.v:6142.48-6142.155" + cell $and $and$ls180.v:6142$1804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6142$1802_Y + connect \B $eq$ls180.v:6142$1803_Y + connect \Y $and$ls180.v:6142$1804_Y + end + attribute \src "ls180.v:6144.49-6144.102" + cell $and $and$ls180.v:6144$1805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6144$1805_Y + end + attribute \src "ls180.v:6144.48-6144.152" + cell $and $and$ls180.v:6144$1807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6144$1805_Y + connect \B $eq$ls180.v:6144$1806_Y + connect \Y $and$ls180.v:6144$1807_Y + end + attribute \src "ls180.v:6145.49-6145.105" + cell $and $and$ls180.v:6145$1809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6145$1808_Y + connect \Y $and$ls180.v:6145$1809_Y + end + attribute \src "ls180.v:6145.48-6145.155" + cell $and $and$ls180.v:6145$1811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6145$1809_Y + connect \B $eq$ls180.v:6145$1810_Y + connect \Y $and$ls180.v:6145$1811_Y + end + attribute \src "ls180.v:6147.42-6147.95" + cell $and $and$ls180.v:6147$1812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6147$1812_Y + end + attribute \src "ls180.v:6147.41-6147.145" + cell $and $and$ls180.v:6147$1814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6147$1812_Y + connect \B $eq$ls180.v:6147$1813_Y + connect \Y $and$ls180.v:6147$1814_Y + end + attribute \src "ls180.v:6148.42-6148.98" + cell $and $and$ls180.v:6148$1816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6148$1815_Y + connect \Y $and$ls180.v:6148$1816_Y + end + attribute \src "ls180.v:6148.41-6148.148" + cell $and $and$ls180.v:6148$1818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6148$1816_Y + connect \B $eq$ls180.v:6148$1817_Y + connect \Y $and$ls180.v:6148$1818_Y + end + attribute \src "ls180.v:6155.46-6155.99" + cell $and $and$ls180.v:6155$1820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6155$1820_Y + end + attribute \src "ls180.v:6155.45-6155.149" + cell $and $and$ls180.v:6155$1822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6155$1820_Y + connect \B $eq$ls180.v:6155$1821_Y + connect \Y $and$ls180.v:6155$1822_Y + end + attribute \src "ls180.v:6156.46-6156.102" + cell $and $and$ls180.v:6156$1824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6156$1823_Y + connect \Y $and$ls180.v:6156$1824_Y + end + attribute \src "ls180.v:6156.45-6156.152" + cell $and $and$ls180.v:6156$1826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6156$1824_Y + connect \B $eq$ls180.v:6156$1825_Y + connect \Y $and$ls180.v:6156$1826_Y + end + attribute \src "ls180.v:6158.50-6158.103" + cell $and $and$ls180.v:6158$1827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6158$1827_Y + end + attribute \src "ls180.v:6158.49-6158.153" + cell $and $and$ls180.v:6158$1829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6158$1827_Y + connect \B $eq$ls180.v:6158$1828_Y + connect \Y $and$ls180.v:6158$1829_Y + end + attribute \src "ls180.v:6159.50-6159.106" + cell $and $and$ls180.v:6159$1831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6159$1830_Y + connect \Y $and$ls180.v:6159$1831_Y + end + attribute \src "ls180.v:6159.49-6159.156" + cell $and $and$ls180.v:6159$1833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6159$1831_Y + connect \B $eq$ls180.v:6159$1832_Y + connect \Y $and$ls180.v:6159$1833_Y + end + attribute \src "ls180.v:6161.40-6161.93" + cell $and $and$ls180.v:6161$1834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6161$1834_Y + end + attribute \src "ls180.v:6161.39-6161.143" + cell $and $and$ls180.v:6161$1836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6161$1834_Y + connect \B $eq$ls180.v:6161$1835_Y + connect \Y $and$ls180.v:6161$1836_Y + end + attribute \src "ls180.v:6162.40-6162.96" + cell $and $and$ls180.v:6162$1838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6162$1837_Y + connect \Y $and$ls180.v:6162$1838_Y + end + attribute \src "ls180.v:6162.39-6162.146" + cell $and $and$ls180.v:6162$1840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6162$1838_Y + connect \B $eq$ls180.v:6162$1839_Y + connect \Y $and$ls180.v:6162$1840_Y + end + attribute \src "ls180.v:6164.50-6164.103" + cell $and $and$ls180.v:6164$1841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6164$1841_Y + end + attribute \src "ls180.v:6164.49-6164.153" + cell $and $and$ls180.v:6164$1843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6164$1841_Y + connect \B $eq$ls180.v:6164$1842_Y + connect \Y $and$ls180.v:6164$1843_Y + end + attribute \src "ls180.v:6165.50-6165.106" + cell $and $and$ls180.v:6165$1845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6165$1844_Y + connect \Y $and$ls180.v:6165$1845_Y + end + attribute \src "ls180.v:6165.49-6165.156" + cell $and $and$ls180.v:6165$1847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6165$1845_Y + connect \B $eq$ls180.v:6165$1846_Y + connect \Y $and$ls180.v:6165$1847_Y + end + attribute \src "ls180.v:6167.50-6167.103" + cell $and $and$ls180.v:6167$1848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6167$1848_Y + end + attribute \src "ls180.v:6167.49-6167.153" + cell $and $and$ls180.v:6167$1850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6167$1848_Y + connect \B $eq$ls180.v:6167$1849_Y + connect \Y $and$ls180.v:6167$1850_Y + end + attribute \src "ls180.v:6168.50-6168.106" + cell $and $and$ls180.v:6168$1852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6168$1851_Y + connect \Y $and$ls180.v:6168$1852_Y + end + attribute \src "ls180.v:6168.49-6168.156" + cell $and $and$ls180.v:6168$1854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6168$1852_Y + connect \B $eq$ls180.v:6168$1853_Y + connect \Y $and$ls180.v:6168$1854_Y + end + attribute \src "ls180.v:6170.51-6170.104" + cell $and $and$ls180.v:6170$1855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6170$1855_Y + end + attribute \src "ls180.v:6170.50-6170.154" + cell $and $and$ls180.v:6170$1857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6170$1855_Y + connect \B $eq$ls180.v:6170$1856_Y + connect \Y $and$ls180.v:6170$1857_Y + end + attribute \src "ls180.v:6171.51-6171.107" + cell $and $and$ls180.v:6171$1859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6171$1858_Y + connect \Y $and$ls180.v:6171$1859_Y + end + attribute \src "ls180.v:6171.50-6171.157" + cell $and $and$ls180.v:6171$1861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6171$1859_Y + connect \B $eq$ls180.v:6171$1860_Y + connect \Y $and$ls180.v:6171$1861_Y + end + attribute \src "ls180.v:6173.49-6173.102" + cell $and $and$ls180.v:6173$1862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6173$1862_Y + end + attribute \src "ls180.v:6173.48-6173.152" + cell $and $and$ls180.v:6173$1864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6173$1862_Y + connect \B $eq$ls180.v:6173$1863_Y + connect \Y $and$ls180.v:6173$1864_Y + end + attribute \src "ls180.v:6174.49-6174.105" + cell $and $and$ls180.v:6174$1866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6174$1865_Y + connect \Y $and$ls180.v:6174$1866_Y + end + attribute \src "ls180.v:6174.48-6174.155" + cell $and $and$ls180.v:6174$1868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6174$1866_Y + connect \B $eq$ls180.v:6174$1867_Y + connect \Y $and$ls180.v:6174$1868_Y + end + attribute \src "ls180.v:6176.49-6176.102" + cell $and $and$ls180.v:6176$1869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6176$1869_Y + end + attribute \src "ls180.v:6176.48-6176.152" + cell $and $and$ls180.v:6176$1871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6176$1869_Y + connect \B $eq$ls180.v:6176$1870_Y + connect \Y $and$ls180.v:6176$1871_Y + end + attribute \src "ls180.v:6177.49-6177.105" + cell $and $and$ls180.v:6177$1873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6177$1872_Y + connect \Y $and$ls180.v:6177$1873_Y + end + attribute \src "ls180.v:6177.48-6177.155" + cell $and $and$ls180.v:6177$1875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6177$1873_Y + connect \B $eq$ls180.v:6177$1874_Y + connect \Y $and$ls180.v:6177$1875_Y + end + attribute \src "ls180.v:6179.49-6179.102" + cell $and $and$ls180.v:6179$1876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6179$1876_Y + end + attribute \src "ls180.v:6179.48-6179.152" + cell $and $and$ls180.v:6179$1878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6179$1876_Y + connect \B $eq$ls180.v:6179$1877_Y + connect \Y $and$ls180.v:6179$1878_Y + end + attribute \src "ls180.v:6180.49-6180.105" + cell $and $and$ls180.v:6180$1880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6180$1879_Y + connect \Y $and$ls180.v:6180$1880_Y + end + attribute \src "ls180.v:6180.48-6180.155" + cell $and $and$ls180.v:6180$1882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6180$1880_Y + connect \B $eq$ls180.v:6180$1881_Y + connect \Y $and$ls180.v:6180$1882_Y + end + attribute \src "ls180.v:6182.49-6182.102" + cell $and $and$ls180.v:6182$1883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6182$1883_Y + end + attribute \src "ls180.v:6182.48-6182.152" + cell $and $and$ls180.v:6182$1885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6182$1883_Y + connect \B $eq$ls180.v:6182$1884_Y + connect \Y $and$ls180.v:6182$1885_Y + end + attribute \src "ls180.v:6183.49-6183.105" + cell $and $and$ls180.v:6183$1887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6183$1886_Y + connect \Y $and$ls180.v:6183$1887_Y + end + attribute \src "ls180.v:6183.48-6183.155" + cell $and $and$ls180.v:6183$1889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6183$1887_Y + connect \B $eq$ls180.v:6183$1888_Y + connect \Y $and$ls180.v:6183$1889_Y + end + attribute \src "ls180.v:6200.41-6200.94" + cell $and $and$ls180.v:6200$1891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6200$1891_Y + end + attribute \src "ls180.v:6200.40-6200.144" + cell $and $and$ls180.v:6200$1893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6200$1891_Y + connect \B $eq$ls180.v:6200$1892_Y + connect \Y $and$ls180.v:6200$1893_Y + end + attribute \src "ls180.v:6201.41-6201.97" + cell $and $and$ls180.v:6201$1895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6201$1894_Y + connect \Y $and$ls180.v:6201$1895_Y + end + attribute \src "ls180.v:6201.40-6201.147" + cell $and $and$ls180.v:6201$1897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6201$1895_Y + connect \B $eq$ls180.v:6201$1896_Y + connect \Y $and$ls180.v:6201$1897_Y + end + attribute \src "ls180.v:6203.41-6203.94" + cell $and $and$ls180.v:6203$1898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6203$1898_Y + end + attribute \src "ls180.v:6203.40-6203.144" + cell $and $and$ls180.v:6203$1900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6203$1898_Y + connect \B $eq$ls180.v:6203$1899_Y + connect \Y $and$ls180.v:6203$1900_Y + end + attribute \src "ls180.v:6204.41-6204.97" + cell $and $and$ls180.v:6204$1902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6204$1901_Y + connect \Y $and$ls180.v:6204$1902_Y + end + attribute \src "ls180.v:6204.40-6204.147" + cell $and $and$ls180.v:6204$1904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6204$1902_Y + connect \B $eq$ls180.v:6204$1903_Y + connect \Y $and$ls180.v:6204$1904_Y + end + attribute \src "ls180.v:6206.39-6206.92" + cell $and $and$ls180.v:6206$1905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6206$1905_Y + end + attribute \src "ls180.v:6206.38-6206.142" + cell $and $and$ls180.v:6206$1907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6206$1905_Y + connect \B $eq$ls180.v:6206$1906_Y + connect \Y $and$ls180.v:6206$1907_Y + end + attribute \src "ls180.v:6207.39-6207.95" + cell $and $and$ls180.v:6207$1909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6207$1908_Y + connect \Y $and$ls180.v:6207$1909_Y + end + attribute \src "ls180.v:6207.38-6207.145" + cell $and $and$ls180.v:6207$1911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6207$1909_Y + connect \B $eq$ls180.v:6207$1910_Y + connect \Y $and$ls180.v:6207$1911_Y + end + attribute \src "ls180.v:6209.38-6209.91" + cell $and $and$ls180.v:6209$1912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6209$1912_Y + end + attribute \src "ls180.v:6209.37-6209.141" + cell $and $and$ls180.v:6209$1914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6209$1912_Y + connect \B $eq$ls180.v:6209$1913_Y + connect \Y $and$ls180.v:6209$1914_Y + end + attribute \src "ls180.v:6210.38-6210.94" + cell $and $and$ls180.v:6210$1916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6210$1915_Y + connect \Y $and$ls180.v:6210$1916_Y + end + attribute \src "ls180.v:6210.37-6210.144" + cell $and $and$ls180.v:6210$1918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6210$1916_Y + connect \B $eq$ls180.v:6210$1917_Y + connect \Y $and$ls180.v:6210$1918_Y + end + attribute \src "ls180.v:6212.37-6212.90" + cell $and $and$ls180.v:6212$1919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6212$1919_Y + end + attribute \src "ls180.v:6212.36-6212.140" + cell $and $and$ls180.v:6212$1921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6212$1919_Y + connect \B $eq$ls180.v:6212$1920_Y + connect \Y $and$ls180.v:6212$1921_Y + end + attribute \src "ls180.v:6213.37-6213.93" + cell $and $and$ls180.v:6213$1923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6213$1922_Y + connect \Y $and$ls180.v:6213$1923_Y + end + attribute \src "ls180.v:6213.36-6213.143" + cell $and $and$ls180.v:6213$1925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6213$1923_Y + connect \B $eq$ls180.v:6213$1924_Y + connect \Y $and$ls180.v:6213$1925_Y + end + attribute \src "ls180.v:6215.36-6215.89" + cell $and $and$ls180.v:6215$1926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6215$1926_Y + end + attribute \src "ls180.v:6215.35-6215.139" + cell $and $and$ls180.v:6215$1928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6215$1926_Y + connect \B $eq$ls180.v:6215$1927_Y + connect \Y $and$ls180.v:6215$1928_Y + end + attribute \src "ls180.v:6216.36-6216.92" + cell $and $and$ls180.v:6216$1930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6216$1929_Y + connect \Y $and$ls180.v:6216$1930_Y + end + attribute \src "ls180.v:6216.35-6216.142" + cell $and $and$ls180.v:6216$1932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6216$1930_Y + connect \B $eq$ls180.v:6216$1931_Y + connect \Y $and$ls180.v:6216$1932_Y + end + attribute \src "ls180.v:6218.42-6218.95" + cell $and $and$ls180.v:6218$1933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6218$1933_Y + end + attribute \src "ls180.v:6218.41-6218.145" + cell $and $and$ls180.v:6218$1935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6218$1933_Y + connect \B $eq$ls180.v:6218$1934_Y + connect \Y $and$ls180.v:6218$1935_Y + end + attribute \src "ls180.v:6219.42-6219.98" + cell $and $and$ls180.v:6219$1937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6219$1936_Y + connect \Y $and$ls180.v:6219$1937_Y + end + attribute \src "ls180.v:6219.41-6219.148" + cell $and $and$ls180.v:6219$1939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6219$1937_Y + connect \B $eq$ls180.v:6219$1938_Y + connect \Y $and$ls180.v:6219$1939_Y + end + attribute \src "ls180.v:6240.42-6240.97" + cell $and $and$ls180.v:6240$1942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6240$1942_Y + end + attribute \src "ls180.v:6240.41-6240.148" + cell $and $and$ls180.v:6240$1944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6240$1942_Y + connect \B $eq$ls180.v:6240$1943_Y + connect \Y $and$ls180.v:6240$1944_Y + end + attribute \src "ls180.v:6241.42-6241.100" + cell $and $and$ls180.v:6241$1946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6241$1945_Y + connect \Y $and$ls180.v:6241$1946_Y + end + attribute \src "ls180.v:6241.41-6241.151" + cell $and $and$ls180.v:6241$1948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6241$1946_Y + connect \B $eq$ls180.v:6241$1947_Y + connect \Y $and$ls180.v:6241$1948_Y + end + attribute \src "ls180.v:6243.42-6243.97" + cell $and $and$ls180.v:6243$1949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6243$1949_Y + end + attribute \src "ls180.v:6243.41-6243.148" + cell $and $and$ls180.v:6243$1951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6243$1949_Y + connect \B $eq$ls180.v:6243$1950_Y + connect \Y $and$ls180.v:6243$1951_Y + end + attribute \src "ls180.v:6244.42-6244.100" + cell $and $and$ls180.v:6244$1953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6244$1952_Y + connect \Y $and$ls180.v:6244$1953_Y + end + attribute \src "ls180.v:6244.41-6244.151" + cell $and $and$ls180.v:6244$1955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6244$1953_Y + connect \B $eq$ls180.v:6244$1954_Y + connect \Y $and$ls180.v:6244$1955_Y + end + attribute \src "ls180.v:6246.40-6246.95" + cell $and $and$ls180.v:6246$1956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6246$1956_Y + end + attribute \src "ls180.v:6246.39-6246.146" + cell $and $and$ls180.v:6246$1958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6246$1956_Y + connect \B $eq$ls180.v:6246$1957_Y + connect \Y $and$ls180.v:6246$1958_Y + end + attribute \src "ls180.v:6247.40-6247.98" + cell $and $and$ls180.v:6247$1960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6247$1959_Y + connect \Y $and$ls180.v:6247$1960_Y + end + attribute \src "ls180.v:6247.39-6247.149" + cell $and $and$ls180.v:6247$1962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6247$1960_Y + connect \B $eq$ls180.v:6247$1961_Y + connect \Y $and$ls180.v:6247$1962_Y + end + attribute \src "ls180.v:6249.39-6249.94" + cell $and $and$ls180.v:6249$1963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6249$1963_Y + end + attribute \src "ls180.v:6249.38-6249.145" + cell $and $and$ls180.v:6249$1965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6249$1963_Y + connect \B $eq$ls180.v:6249$1964_Y + connect \Y $and$ls180.v:6249$1965_Y + end + attribute \src "ls180.v:6250.39-6250.97" + cell $and $and$ls180.v:6250$1967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6250$1966_Y + connect \Y $and$ls180.v:6250$1967_Y + end + attribute \src "ls180.v:6250.38-6250.148" + cell $and $and$ls180.v:6250$1969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6250$1967_Y + connect \B $eq$ls180.v:6250$1968_Y + connect \Y $and$ls180.v:6250$1969_Y + end + attribute \src "ls180.v:6252.38-6252.93" + cell $and $and$ls180.v:6252$1970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6252$1970_Y + end + attribute \src "ls180.v:6252.37-6252.144" + cell $and $and$ls180.v:6252$1972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6252$1970_Y + connect \B $eq$ls180.v:6252$1971_Y + connect \Y $and$ls180.v:6252$1972_Y + end + attribute \src "ls180.v:6253.38-6253.96" + cell $and $and$ls180.v:6253$1974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6253$1973_Y + connect \Y $and$ls180.v:6253$1974_Y + end + attribute \src "ls180.v:6253.37-6253.147" + cell $and $and$ls180.v:6253$1976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6253$1974_Y + connect \B $eq$ls180.v:6253$1975_Y + connect \Y $and$ls180.v:6253$1976_Y + end + attribute \src "ls180.v:6255.37-6255.92" + cell $and $and$ls180.v:6255$1977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6255$1977_Y + end + attribute \src "ls180.v:6255.36-6255.143" + cell $and $and$ls180.v:6255$1979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6255$1977_Y + connect \B $eq$ls180.v:6255$1978_Y + connect \Y $and$ls180.v:6255$1979_Y + end + attribute \src "ls180.v:6256.37-6256.95" + cell $and $and$ls180.v:6256$1981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6256$1980_Y + connect \Y $and$ls180.v:6256$1981_Y + end + attribute \src "ls180.v:6256.36-6256.146" + cell $and $and$ls180.v:6256$1983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6256$1981_Y + connect \B $eq$ls180.v:6256$1982_Y + connect \Y $and$ls180.v:6256$1983_Y + end + attribute \src "ls180.v:6258.43-6258.98" + cell $and $and$ls180.v:6258$1984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6258$1984_Y + end + attribute \src "ls180.v:6258.42-6258.149" + cell $and $and$ls180.v:6258$1986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6258$1984_Y + connect \B $eq$ls180.v:6258$1985_Y + connect \Y $and$ls180.v:6258$1986_Y + end + attribute \src "ls180.v:6259.43-6259.101" + cell $and $and$ls180.v:6259$1988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6259$1987_Y + connect \Y $and$ls180.v:6259$1988_Y + end + attribute \src "ls180.v:6259.42-6259.152" + cell $and $and$ls180.v:6259$1990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6259$1988_Y + connect \B $eq$ls180.v:6259$1989_Y + connect \Y $and$ls180.v:6259$1990_Y + end + attribute \src "ls180.v:6261.46-6261.101" + cell $and $and$ls180.v:6261$1991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6261$1991_Y + end + attribute \src "ls180.v:6261.45-6261.152" + cell $and $and$ls180.v:6261$1993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6261$1991_Y + connect \B $eq$ls180.v:6261$1992_Y + connect \Y $and$ls180.v:6261$1993_Y + end + attribute \src "ls180.v:6262.46-6262.104" + cell $and $and$ls180.v:6262$1995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6262$1994_Y + connect \Y $and$ls180.v:6262$1995_Y + end + attribute \src "ls180.v:6262.45-6262.155" + cell $and $and$ls180.v:6262$1997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6262$1995_Y + connect \B $eq$ls180.v:6262$1996_Y + connect \Y $and$ls180.v:6262$1997_Y + end + attribute \src "ls180.v:6264.46-6264.101" + cell $and $and$ls180.v:6264$1998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6264$1998_Y + end + attribute \src "ls180.v:6264.45-6264.152" + cell $and $and$ls180.v:6264$2000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6264$1998_Y + connect \B $eq$ls180.v:6264$1999_Y + connect \Y $and$ls180.v:6264$2000_Y + end + attribute \src "ls180.v:6265.46-6265.104" + cell $and $and$ls180.v:6265$2002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6265$2001_Y + connect \Y $and$ls180.v:6265$2002_Y + end + attribute \src "ls180.v:6265.45-6265.155" + cell $and $and$ls180.v:6265$2004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6265$2002_Y + connect \B $eq$ls180.v:6265$2003_Y + connect \Y $and$ls180.v:6265$2004_Y + end + attribute \src "ls180.v:6288.39-6288.94" + cell $and $and$ls180.v:6288$2007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6288$2007_Y + end + attribute \src "ls180.v:6288.38-6288.145" + cell $and $and$ls180.v:6288$2009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6288$2007_Y + connect \B $eq$ls180.v:6288$2008_Y + connect \Y $and$ls180.v:6288$2009_Y + end + attribute \src "ls180.v:6289.39-6289.97" + cell $and $and$ls180.v:6289$2011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6289$2010_Y + connect \Y $and$ls180.v:6289$2011_Y + end + attribute \src "ls180.v:6289.38-6289.148" + cell $and $and$ls180.v:6289$2013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6289$2011_Y + connect \B $eq$ls180.v:6289$2012_Y + connect \Y $and$ls180.v:6289$2013_Y + end + attribute \src "ls180.v:6291.39-6291.94" + cell $and $and$ls180.v:6291$2014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6291$2014_Y + end + attribute \src "ls180.v:6291.38-6291.145" + cell $and $and$ls180.v:6291$2016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6291$2014_Y + connect \B $eq$ls180.v:6291$2015_Y + connect \Y $and$ls180.v:6291$2016_Y + end + attribute \src "ls180.v:6292.39-6292.97" + cell $and $and$ls180.v:6292$2018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6292$2017_Y + connect \Y $and$ls180.v:6292$2018_Y + end + attribute \src "ls180.v:6292.38-6292.148" + cell $and $and$ls180.v:6292$2020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6292$2018_Y + connect \B $eq$ls180.v:6292$2019_Y + connect \Y $and$ls180.v:6292$2020_Y + end + attribute \src "ls180.v:6294.39-6294.94" + cell $and $and$ls180.v:6294$2021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6294$2021_Y + end + attribute \src "ls180.v:6294.38-6294.145" + cell $and $and$ls180.v:6294$2023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6294$2021_Y + connect \B $eq$ls180.v:6294$2022_Y + connect \Y $and$ls180.v:6294$2023_Y + end + attribute \src "ls180.v:6295.39-6295.97" + cell $and $and$ls180.v:6295$2025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6295$2024_Y + connect \Y $and$ls180.v:6295$2025_Y + end + attribute \src "ls180.v:6295.38-6295.148" + cell $and $and$ls180.v:6295$2027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6295$2025_Y + connect \B $eq$ls180.v:6295$2026_Y + connect \Y $and$ls180.v:6295$2027_Y + end + attribute \src "ls180.v:6297.39-6297.94" + cell $and $and$ls180.v:6297$2028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6297$2028_Y + end + attribute \src "ls180.v:6297.38-6297.145" + cell $and $and$ls180.v:6297$2030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6297$2028_Y + connect \B $eq$ls180.v:6297$2029_Y + connect \Y $and$ls180.v:6297$2030_Y + end + attribute \src "ls180.v:6298.39-6298.97" + cell $and $and$ls180.v:6298$2032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6298$2031_Y + connect \Y $and$ls180.v:6298$2032_Y + end + attribute \src "ls180.v:6298.38-6298.148" + cell $and $and$ls180.v:6298$2034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6298$2032_Y + connect \B $eq$ls180.v:6298$2033_Y + connect \Y $and$ls180.v:6298$2034_Y + end + attribute \src "ls180.v:6300.41-6300.96" + cell $and $and$ls180.v:6300$2035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6300$2035_Y + end + attribute \src "ls180.v:6300.40-6300.147" + cell $and $and$ls180.v:6300$2037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6300$2035_Y + connect \B $eq$ls180.v:6300$2036_Y + connect \Y $and$ls180.v:6300$2037_Y + end + attribute \src "ls180.v:6301.41-6301.99" + cell $and $and$ls180.v:6301$2039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6301$2038_Y + connect \Y $and$ls180.v:6301$2039_Y + end + attribute \src "ls180.v:6301.40-6301.150" + cell $and $and$ls180.v:6301$2041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6301$2039_Y + connect \B $eq$ls180.v:6301$2040_Y + connect \Y $and$ls180.v:6301$2041_Y + end + attribute \src "ls180.v:6303.41-6303.96" + cell $and $and$ls180.v:6303$2042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6303$2042_Y + end + attribute \src "ls180.v:6303.40-6303.147" + cell $and $and$ls180.v:6303$2044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6303$2042_Y + connect \B $eq$ls180.v:6303$2043_Y + connect \Y $and$ls180.v:6303$2044_Y + end + attribute \src "ls180.v:6304.41-6304.99" + cell $and $and$ls180.v:6304$2046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6304$2045_Y + connect \Y $and$ls180.v:6304$2046_Y + end + attribute \src "ls180.v:6304.40-6304.150" + cell $and $and$ls180.v:6304$2048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6304$2046_Y + connect \B $eq$ls180.v:6304$2047_Y + connect \Y $and$ls180.v:6304$2048_Y + end + attribute \src "ls180.v:6306.41-6306.96" + cell $and $and$ls180.v:6306$2049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6306$2049_Y + end + attribute \src "ls180.v:6306.40-6306.147" + cell $and $and$ls180.v:6306$2051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6306$2049_Y + connect \B $eq$ls180.v:6306$2050_Y + connect \Y $and$ls180.v:6306$2051_Y + end + attribute \src "ls180.v:6307.41-6307.99" + cell $and $and$ls180.v:6307$2053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6307$2052_Y + connect \Y $and$ls180.v:6307$2053_Y + end + attribute \src "ls180.v:6307.40-6307.150" + cell $and $and$ls180.v:6307$2055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6307$2053_Y + connect \B $eq$ls180.v:6307$2054_Y + connect \Y $and$ls180.v:6307$2055_Y + end + attribute \src "ls180.v:6309.41-6309.96" + cell $and $and$ls180.v:6309$2056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6309$2056_Y + end + attribute \src "ls180.v:6309.40-6309.147" + cell $and $and$ls180.v:6309$2058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6309$2056_Y + connect \B $eq$ls180.v:6309$2057_Y + connect \Y $and$ls180.v:6309$2058_Y + end + attribute \src "ls180.v:6310.41-6310.99" + cell $and $and$ls180.v:6310$2060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6310$2059_Y + connect \Y $and$ls180.v:6310$2060_Y + end + attribute \src "ls180.v:6310.40-6310.150" + cell $and $and$ls180.v:6310$2062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6310$2060_Y + connect \B $eq$ls180.v:6310$2061_Y + connect \Y $and$ls180.v:6310$2062_Y + end + attribute \src "ls180.v:6312.37-6312.92" + cell $and $and$ls180.v:6312$2063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6312$2063_Y + end + attribute \src "ls180.v:6312.36-6312.143" + cell $and $and$ls180.v:6312$2065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6312$2063_Y + connect \B $eq$ls180.v:6312$2064_Y + connect \Y $and$ls180.v:6312$2065_Y + end + attribute \src "ls180.v:6313.37-6313.95" + cell $and $and$ls180.v:6313$2067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6313$2066_Y + connect \Y $and$ls180.v:6313$2067_Y + end + attribute \src "ls180.v:6313.36-6313.146" + cell $and $and$ls180.v:6313$2069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6313$2067_Y + connect \B $eq$ls180.v:6313$2068_Y + connect \Y $and$ls180.v:6313$2069_Y + end + attribute \src "ls180.v:6315.47-6315.102" + cell $and $and$ls180.v:6315$2070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6315$2070_Y + end + attribute \src "ls180.v:6315.46-6315.153" + cell $and $and$ls180.v:6315$2072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6315$2070_Y + connect \B $eq$ls180.v:6315$2071_Y + connect \Y $and$ls180.v:6315$2072_Y + end + attribute \src "ls180.v:6316.47-6316.105" + cell $and $and$ls180.v:6316$2074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6316$2073_Y + connect \Y $and$ls180.v:6316$2074_Y + end + attribute \src "ls180.v:6316.46-6316.156" + cell $and $and$ls180.v:6316$2076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6316$2074_Y + connect \B $eq$ls180.v:6316$2075_Y + connect \Y $and$ls180.v:6316$2076_Y + end + attribute \src "ls180.v:6318.40-6318.95" + cell $and $and$ls180.v:6318$2077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6318$2077_Y + end + attribute \src "ls180.v:6318.39-6318.147" + cell $and $and$ls180.v:6318$2079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6318$2077_Y + connect \B $eq$ls180.v:6318$2078_Y + connect \Y $and$ls180.v:6318$2079_Y + end + attribute \src "ls180.v:6319.40-6319.98" + cell $and $and$ls180.v:6319$2081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6319$2080_Y + connect \Y $and$ls180.v:6319$2081_Y + end + attribute \src "ls180.v:6319.39-6319.150" + cell $and $and$ls180.v:6319$2083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6319$2081_Y + connect \B $eq$ls180.v:6319$2082_Y + connect \Y $and$ls180.v:6319$2083_Y + end + attribute \src "ls180.v:6321.40-6321.95" + cell $and $and$ls180.v:6321$2084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6321$2084_Y + end + attribute \src "ls180.v:6321.39-6321.147" + cell $and $and$ls180.v:6321$2086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6321$2084_Y + connect \B $eq$ls180.v:6321$2085_Y + connect \Y $and$ls180.v:6321$2086_Y + end + attribute \src "ls180.v:6322.40-6322.98" + cell $and $and$ls180.v:6322$2088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6322$2087_Y + connect \Y $and$ls180.v:6322$2088_Y + end + attribute \src "ls180.v:6322.39-6322.150" + cell $and $and$ls180.v:6322$2090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6322$2088_Y + connect \B $eq$ls180.v:6322$2089_Y + connect \Y $and$ls180.v:6322$2090_Y + end + attribute \src "ls180.v:6324.40-6324.95" + cell $and $and$ls180.v:6324$2091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6324$2091_Y + end + attribute \src "ls180.v:6324.39-6324.147" + cell $and $and$ls180.v:6324$2093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6324$2091_Y + connect \B $eq$ls180.v:6324$2092_Y + connect \Y $and$ls180.v:6324$2093_Y + end + attribute \src "ls180.v:6325.40-6325.98" + cell $and $and$ls180.v:6325$2095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6325$2094_Y + connect \Y $and$ls180.v:6325$2095_Y + end + attribute \src "ls180.v:6325.39-6325.150" + cell $and $and$ls180.v:6325$2097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6325$2095_Y + connect \B $eq$ls180.v:6325$2096_Y + connect \Y $and$ls180.v:6325$2097_Y + end + attribute \src "ls180.v:6327.40-6327.95" + cell $and $and$ls180.v:6327$2098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6327$2098_Y + end + attribute \src "ls180.v:6327.39-6327.147" + cell $and $and$ls180.v:6327$2100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6327$2098_Y + connect \B $eq$ls180.v:6327$2099_Y + connect \Y $and$ls180.v:6327$2100_Y + end + attribute \src "ls180.v:6328.40-6328.98" + cell $and $and$ls180.v:6328$2102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6328$2101_Y + connect \Y $and$ls180.v:6328$2102_Y + end + attribute \src "ls180.v:6328.39-6328.150" + cell $and $and$ls180.v:6328$2104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6328$2102_Y + connect \B $eq$ls180.v:6328$2103_Y + connect \Y $and$ls180.v:6328$2104_Y + end + attribute \src "ls180.v:6330.52-6330.107" + cell $and $and$ls180.v:6330$2105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6330$2105_Y + end + attribute \src "ls180.v:6330.51-6330.159" + cell $and $and$ls180.v:6330$2107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6330$2105_Y + connect \B $eq$ls180.v:6330$2106_Y + connect \Y $and$ls180.v:6330$2107_Y + end + attribute \src "ls180.v:6331.52-6331.110" + cell $and $and$ls180.v:6331$2109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6331$2108_Y + connect \Y $and$ls180.v:6331$2109_Y + end + attribute \src "ls180.v:6331.51-6331.162" + cell $and $and$ls180.v:6331$2111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6331$2109_Y + connect \B $eq$ls180.v:6331$2110_Y + connect \Y $and$ls180.v:6331$2111_Y + end + attribute \src "ls180.v:6333.53-6333.108" + cell $and $and$ls180.v:6333$2112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6333$2112_Y + end + attribute \src "ls180.v:6333.52-6333.160" + cell $and $and$ls180.v:6333$2114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6333$2112_Y + connect \B $eq$ls180.v:6333$2113_Y + connect \Y $and$ls180.v:6333$2114_Y + end + attribute \src "ls180.v:6334.53-6334.111" + cell $and $and$ls180.v:6334$2116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6334$2115_Y + connect \Y $and$ls180.v:6334$2116_Y + end + attribute \src "ls180.v:6334.52-6334.163" + cell $and $and$ls180.v:6334$2118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6334$2116_Y + connect \B $eq$ls180.v:6334$2117_Y + connect \Y $and$ls180.v:6334$2118_Y + end + attribute \src "ls180.v:6336.44-6336.99" + cell $and $and$ls180.v:6336$2119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6336$2119_Y + end + attribute \src "ls180.v:6336.43-6336.151" + cell $and $and$ls180.v:6336$2121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6336$2119_Y + connect \B $eq$ls180.v:6336$2120_Y + connect \Y $and$ls180.v:6336$2121_Y + end + attribute \src "ls180.v:6337.44-6337.102" + cell $and $and$ls180.v:6337$2123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6337$2122_Y + connect \Y $and$ls180.v:6337$2123_Y + end + attribute \src "ls180.v:6337.43-6337.154" + cell $and $and$ls180.v:6337$2125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6337$2123_Y + connect \B $eq$ls180.v:6337$2124_Y + connect \Y $and$ls180.v:6337$2125_Y + end + attribute \src "ls180.v:6356.30-6356.85" + cell $and $and$ls180.v:6356$2127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6356$2127_Y + end + attribute \src "ls180.v:6356.29-6356.136" + cell $and $and$ls180.v:6356$2129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6356$2127_Y + connect \B $eq$ls180.v:6356$2128_Y + connect \Y $and$ls180.v:6356$2129_Y + end + attribute \src "ls180.v:6357.30-6357.88" + cell $and $and$ls180.v:6357$2131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6357$2130_Y + connect \Y $and$ls180.v:6357$2131_Y + end + attribute \src "ls180.v:6357.29-6357.139" + cell $and $and$ls180.v:6357$2133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6357$2131_Y + connect \B $eq$ls180.v:6357$2132_Y + connect \Y $and$ls180.v:6357$2133_Y + end + attribute \src "ls180.v:6359.40-6359.95" + cell $and $and$ls180.v:6359$2134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6359$2134_Y + end + attribute \src "ls180.v:6359.39-6359.146" + cell $and $and$ls180.v:6359$2136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6359$2134_Y + connect \B $eq$ls180.v:6359$2135_Y + connect \Y $and$ls180.v:6359$2136_Y + end + attribute \src "ls180.v:6360.40-6360.98" + cell $and $and$ls180.v:6360$2138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6360$2137_Y + connect \Y $and$ls180.v:6360$2138_Y + end + attribute \src "ls180.v:6360.39-6360.149" + cell $and $and$ls180.v:6360$2140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6360$2138_Y + connect \B $eq$ls180.v:6360$2139_Y + connect \Y $and$ls180.v:6360$2140_Y + end + attribute \src "ls180.v:6362.41-6362.96" + cell $and $and$ls180.v:6362$2141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6362$2141_Y + end + attribute \src "ls180.v:6362.40-6362.147" + cell $and $and$ls180.v:6362$2143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6362$2141_Y + connect \B $eq$ls180.v:6362$2142_Y + connect \Y $and$ls180.v:6362$2143_Y + end + attribute \src "ls180.v:6363.41-6363.99" + cell $and $and$ls180.v:6363$2145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6363$2144_Y + connect \Y $and$ls180.v:6363$2145_Y + end + attribute \src "ls180.v:6363.40-6363.150" + cell $and $and$ls180.v:6363$2147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6363$2145_Y + connect \B $eq$ls180.v:6363$2146_Y + connect \Y $and$ls180.v:6363$2147_Y + end + attribute \src "ls180.v:6365.45-6365.100" + cell $and $and$ls180.v:6365$2148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6365$2148_Y + end + attribute \src "ls180.v:6365.44-6365.151" + cell $and $and$ls180.v:6365$2150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6365$2148_Y + connect \B $eq$ls180.v:6365$2149_Y + connect \Y $and$ls180.v:6365$2150_Y + end + attribute \src "ls180.v:6366.45-6366.103" + cell $and $and$ls180.v:6366$2152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6366$2151_Y + connect \Y $and$ls180.v:6366$2152_Y + end + attribute \src "ls180.v:6366.44-6366.154" + cell $and $and$ls180.v:6366$2154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6366$2152_Y + connect \B $eq$ls180.v:6366$2153_Y + connect \Y $and$ls180.v:6366$2154_Y + end + attribute \src "ls180.v:6368.46-6368.101" + cell $and $and$ls180.v:6368$2155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6368$2155_Y + end + attribute \src "ls180.v:6368.45-6368.152" + cell $and $and$ls180.v:6368$2157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6368$2155_Y + connect \B $eq$ls180.v:6368$2156_Y + connect \Y $and$ls180.v:6368$2157_Y + end + attribute \src "ls180.v:6369.46-6369.104" + cell $and $and$ls180.v:6369$2159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6369$2158_Y + connect \Y $and$ls180.v:6369$2159_Y + end + attribute \src "ls180.v:6369.45-6369.155" + cell $and $and$ls180.v:6369$2161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6369$2159_Y + connect \B $eq$ls180.v:6369$2160_Y + connect \Y $and$ls180.v:6369$2161_Y + end + attribute \src "ls180.v:6371.44-6371.99" + cell $and $and$ls180.v:6371$2162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6371$2162_Y + end + attribute \src "ls180.v:6371.43-6371.150" + cell $and $and$ls180.v:6371$2164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6371$2162_Y + connect \B $eq$ls180.v:6371$2163_Y + connect \Y $and$ls180.v:6371$2164_Y + end + attribute \src "ls180.v:6372.44-6372.102" + cell $and $and$ls180.v:6372$2166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6372$2165_Y + connect \Y $and$ls180.v:6372$2166_Y + end + attribute \src "ls180.v:6372.43-6372.153" + cell $and $and$ls180.v:6372$2168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6372$2166_Y + connect \B $eq$ls180.v:6372$2167_Y + connect \Y $and$ls180.v:6372$2168_Y + end + attribute \src "ls180.v:6374.41-6374.96" + cell $and $and$ls180.v:6374$2169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6374$2169_Y + end + attribute \src "ls180.v:6374.40-6374.147" + cell $and $and$ls180.v:6374$2171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6374$2169_Y + connect \B $eq$ls180.v:6374$2170_Y + connect \Y $and$ls180.v:6374$2171_Y + end + attribute \src "ls180.v:6375.41-6375.99" + cell $and $and$ls180.v:6375$2173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6375$2172_Y + connect \Y $and$ls180.v:6375$2173_Y + end + attribute \src "ls180.v:6375.40-6375.150" + cell $and $and$ls180.v:6375$2175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6375$2173_Y + connect \B $eq$ls180.v:6375$2174_Y + connect \Y $and$ls180.v:6375$2175_Y + end + attribute \src "ls180.v:6377.40-6377.95" + cell $and $and$ls180.v:6377$2176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6377$2176_Y + end + attribute \src "ls180.v:6377.39-6377.146" + cell $and $and$ls180.v:6377$2178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6377$2176_Y + connect \B $eq$ls180.v:6377$2177_Y + connect \Y $and$ls180.v:6377$2178_Y + end + attribute \src "ls180.v:6378.40-6378.98" + cell $and $and$ls180.v:6378$2180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6378$2179_Y + connect \Y $and$ls180.v:6378$2180_Y + end + attribute \src "ls180.v:6378.39-6378.149" + cell $and $and$ls180.v:6378$2182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6378$2180_Y + connect \B $eq$ls180.v:6378$2181_Y + connect \Y $and$ls180.v:6378$2182_Y + end + attribute \src "ls180.v:6390.46-6390.101" + cell $and $and$ls180.v:6390$2184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6390$2184_Y + end + attribute \src "ls180.v:6390.45-6390.152" + cell $and $and$ls180.v:6390$2186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6390$2184_Y + connect \B $eq$ls180.v:6390$2185_Y + connect \Y $and$ls180.v:6390$2186_Y + end + attribute \src "ls180.v:6391.46-6391.104" + cell $and $and$ls180.v:6391$2188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6391$2187_Y + connect \Y $and$ls180.v:6391$2188_Y + end + attribute \src "ls180.v:6391.45-6391.155" + cell $and $and$ls180.v:6391$2190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6391$2188_Y + connect \B $eq$ls180.v:6391$2189_Y + connect \Y $and$ls180.v:6391$2190_Y + end + attribute \src "ls180.v:6393.46-6393.101" + cell $and $and$ls180.v:6393$2191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6393$2191_Y + end + attribute \src "ls180.v:6393.45-6393.152" + cell $and $and$ls180.v:6393$2193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6393$2191_Y + connect \B $eq$ls180.v:6393$2192_Y + connect \Y $and$ls180.v:6393$2193_Y + end + attribute \src "ls180.v:6394.46-6394.104" + cell $and $and$ls180.v:6394$2195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6394$2194_Y + connect \Y $and$ls180.v:6394$2195_Y + end + attribute \src "ls180.v:6394.45-6394.155" + cell $and $and$ls180.v:6394$2197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6394$2195_Y + connect \B $eq$ls180.v:6394$2196_Y + connect \Y $and$ls180.v:6394$2197_Y + end + attribute \src "ls180.v:6396.46-6396.101" + cell $and $and$ls180.v:6396$2198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6396$2198_Y + end + attribute \src "ls180.v:6396.45-6396.152" + cell $and $and$ls180.v:6396$2200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6396$2198_Y + connect \B $eq$ls180.v:6396$2199_Y + connect \Y $and$ls180.v:6396$2200_Y + end + attribute \src "ls180.v:6397.46-6397.104" + cell $and $and$ls180.v:6397$2202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6397$2201_Y + connect \Y $and$ls180.v:6397$2202_Y + end + attribute \src "ls180.v:6397.45-6397.155" + cell $and $and$ls180.v:6397$2204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6397$2202_Y + connect \B $eq$ls180.v:6397$2203_Y + connect \Y $and$ls180.v:6397$2204_Y + end + attribute \src "ls180.v:6399.46-6399.101" + cell $and $and$ls180.v:6399$2205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6399$2205_Y + end + attribute \src "ls180.v:6399.45-6399.152" + cell $and $and$ls180.v:6399$2207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6399$2205_Y + connect \B $eq$ls180.v:6399$2206_Y + connect \Y $and$ls180.v:6399$2207_Y + end + attribute \src "ls180.v:6400.46-6400.104" + cell $and $and$ls180.v:6400$2209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6400$2208_Y + connect \Y $and$ls180.v:6400$2209_Y + end + attribute \src "ls180.v:6400.45-6400.155" + cell $and $and$ls180.v:6400$2211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6400$2209_Y + connect \B $eq$ls180.v:6400$2210_Y + connect \Y $and$ls180.v:6400$2211_Y + end + attribute \src "ls180.v:6778.109-6778.178" + cell $and $and$ls180.v:6778$2248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:6778$2247_Y + connect \Y $and$ls180.v:6778$2248_Y + end + attribute \src "ls180.v:6778.184-6778.253" + cell $and $and$ls180.v:6778$2251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:6778$2250_Y + connect \Y $and$ls180.v:6778$2251_Y + end + attribute \src "ls180.v:6778.259-6778.328" + cell $and $and$ls180.v:6778$2254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:6778$2253_Y + connect \Y $and$ls180.v:6778$2254_Y + end + attribute \src "ls180.v:6778.40-6778.331" + cell $and $and$ls180.v:6778$2257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:6778$2246_Y + connect \B $not$ls180.v:6778$2256_Y + connect \Y $and$ls180.v:6778$2257_Y + end + attribute \src "ls180.v:6778.39-6778.354" + cell $and $and$ls180.v:6778$2258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6778$2257_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:6778$2258_Y + end + attribute \src "ls180.v:6802.109-6802.178" + cell $and $and$ls180.v:6802$2264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:6802$2263_Y + connect \Y $and$ls180.v:6802$2264_Y + end + attribute \src "ls180.v:6802.184-6802.253" + cell $and $and$ls180.v:6802$2267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:6802$2266_Y + connect \Y $and$ls180.v:6802$2267_Y + end + attribute \src "ls180.v:6802.259-6802.328" + cell $and $and$ls180.v:6802$2270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:6802$2269_Y + connect \Y $and$ls180.v:6802$2270_Y + end + attribute \src "ls180.v:6802.40-6802.331" + cell $and $and$ls180.v:6802$2273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:6802$2262_Y + connect \B $not$ls180.v:6802$2272_Y + connect \Y $and$ls180.v:6802$2273_Y + end + attribute \src "ls180.v:6802.39-6802.354" + cell $and $and$ls180.v:6802$2274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6802$2273_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:6802$2274_Y + end + attribute \src "ls180.v:6826.109-6826.178" + cell $and $and$ls180.v:6826$2280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:6826$2279_Y + connect \Y $and$ls180.v:6826$2280_Y + end + attribute \src "ls180.v:6826.184-6826.253" + cell $and $and$ls180.v:6826$2283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:6826$2282_Y + connect \Y $and$ls180.v:6826$2283_Y + end + attribute \src "ls180.v:6826.259-6826.328" + cell $and $and$ls180.v:6826$2286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:6826$2285_Y + connect \Y $and$ls180.v:6826$2286_Y + end + attribute \src "ls180.v:6826.40-6826.331" + cell $and $and$ls180.v:6826$2289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:6826$2278_Y + connect \B $not$ls180.v:6826$2288_Y + connect \Y $and$ls180.v:6826$2289_Y + end + attribute \src "ls180.v:6826.39-6826.354" + cell $and $and$ls180.v:6826$2290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6826$2289_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:6826$2290_Y + end + attribute \src "ls180.v:6850.109-6850.178" + cell $and $and$ls180.v:6850$2296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:6850$2295_Y + connect \Y $and$ls180.v:6850$2296_Y + end + attribute \src "ls180.v:6850.184-6850.253" + cell $and $and$ls180.v:6850$2299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:6850$2298_Y + connect \Y $and$ls180.v:6850$2299_Y + end + attribute \src "ls180.v:6850.259-6850.328" + cell $and $and$ls180.v:6850$2302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:6850$2301_Y + connect \Y $and$ls180.v:6850$2302_Y + end + attribute \src "ls180.v:6850.40-6850.331" + cell $and $and$ls180.v:6850$2305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:6850$2294_Y + connect \B $not$ls180.v:6850$2304_Y + connect \Y $and$ls180.v:6850$2305_Y + end + attribute \src "ls180.v:6850.39-6850.354" + cell $and $and$ls180.v:6850$2306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6850$2305_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:6850$2306_Y + end + attribute \src "ls180.v:7055.39-7055.104" + cell $and $and$ls180.v:7055$2318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7055$2318_Y + end + attribute \src "ls180.v:7055.38-7055.145" + cell $and $and$ls180.v:7055$2319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7055$2318_Y + connect \B \main_sdram_choose_req_cmd_payload_cas + connect \Y $and$ls180.v:7055$2319_Y + end + attribute \src "ls180.v:7058.39-7058.104" + cell $and $and$ls180.v:7058$2320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7058$2320_Y + end + attribute \src "ls180.v:7058.38-7058.145" + cell $and $and$ls180.v:7058$2321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7058$2320_Y + connect \B \main_sdram_choose_req_cmd_payload_cas + connect \Y $and$ls180.v:7058$2321_Y + end + attribute \src "ls180.v:7061.39-7061.82" + cell $and $and$ls180.v:7061$2322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7061$2322_Y + end + attribute \src "ls180.v:7061.38-7061.112" + cell $and $and$ls180.v:7061$2323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7061$2322_Y + connect \B \main_sdram_cmd_payload_cas + connect \Y $and$ls180.v:7061$2323_Y + end + attribute \src "ls180.v:7072.39-7072.104" + cell $and $and$ls180.v:7072$2325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7072$2325_Y + end + attribute \src "ls180.v:7072.38-7072.145" + cell $and $and$ls180.v:7072$2326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7072$2325_Y + connect \B \main_sdram_choose_req_cmd_payload_ras + connect \Y $and$ls180.v:7072$2326_Y + end + attribute \src "ls180.v:7075.39-7075.104" + cell $and $and$ls180.v:7075$2327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7075$2327_Y + end + attribute \src "ls180.v:7075.38-7075.145" + cell $and $and$ls180.v:7075$2328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7075$2327_Y + connect \B \main_sdram_choose_req_cmd_payload_ras + connect \Y $and$ls180.v:7075$2328_Y + end + attribute \src "ls180.v:7078.39-7078.82" + cell $and $and$ls180.v:7078$2329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7078$2329_Y + end + attribute \src "ls180.v:7078.38-7078.112" + cell $and $and$ls180.v:7078$2330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7078$2329_Y + connect \B \main_sdram_cmd_payload_ras + connect \Y $and$ls180.v:7078$2330_Y + end + attribute \src "ls180.v:7089.39-7089.104" + cell $and $and$ls180.v:7089$2332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7089$2332_Y + end + attribute \src "ls180.v:7089.38-7089.144" + cell $and $and$ls180.v:7089$2333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7089$2332_Y + connect \B \main_sdram_choose_req_cmd_payload_we + connect \Y $and$ls180.v:7089$2333_Y + end + attribute \src "ls180.v:7092.39-7092.104" + cell $and $and$ls180.v:7092$2334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7092$2334_Y + end + attribute \src "ls180.v:7092.38-7092.144" + cell $and $and$ls180.v:7092$2335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7092$2334_Y + connect \B \main_sdram_choose_req_cmd_payload_we + connect \Y $and$ls180.v:7092$2335_Y + end + attribute \src "ls180.v:7095.39-7095.82" + cell $and $and$ls180.v:7095$2336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7095$2336_Y + end + attribute \src "ls180.v:7095.38-7095.111" + cell $and $and$ls180.v:7095$2337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7095$2336_Y + connect \B \main_sdram_cmd_payload_we + connect \Y $and$ls180.v:7095$2337_Y + end + attribute \src "ls180.v:7106.39-7106.104" + cell $and $and$ls180.v:7106$2339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7106$2339_Y + end + attribute \src "ls180.v:7106.38-7106.149" + cell $and $and$ls180.v:7106$2340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7106$2339_Y + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $and$ls180.v:7106$2340_Y + end + attribute \src "ls180.v:7109.39-7109.104" + cell $and $and$ls180.v:7109$2341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7109$2341_Y + end + attribute \src "ls180.v:7109.38-7109.149" + cell $and $and$ls180.v:7109$2342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7109$2341_Y + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $and$ls180.v:7109$2342_Y + end + attribute \src "ls180.v:7112.39-7112.82" + cell $and $and$ls180.v:7112$2343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7112$2343_Y + end + attribute \src "ls180.v:7112.38-7112.116" + cell $and $and$ls180.v:7112$2344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7112$2343_Y + connect \B \main_sdram_cmd_payload_is_read + connect \Y $and$ls180.v:7112$2344_Y + end + attribute \src "ls180.v:7123.39-7123.104" + cell $and $and$ls180.v:7123$2346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7123$2346_Y + end + attribute \src "ls180.v:7123.38-7123.150" + cell $and $and$ls180.v:7123$2347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7123$2346_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:7123$2347_Y + end + attribute \src "ls180.v:7126.39-7126.104" + cell $and $and$ls180.v:7126$2348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7126$2348_Y + end + attribute \src "ls180.v:7126.38-7126.150" + cell $and $and$ls180.v:7126$2349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7126$2348_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:7126$2349_Y + end + attribute \src "ls180.v:7129.39-7129.82" + cell $and $and$ls180.v:7129$2350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7129$2350_Y + end + attribute \src "ls180.v:7129.38-7129.117" + cell $and $and$ls180.v:7129$2351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7129$2350_Y + connect \B \main_sdram_cmd_payload_is_write + connect \Y $and$ls180.v:7129$2351_Y + end + attribute \src "ls180.v:7344.17-7344.67" + cell $and $and$ls180.v:7344$2358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7344$2357_Y + connect \B \main_sdphy_sdpads_clk + connect \Y $and$ls180.v:7344$2358_Y + end + attribute \src "ls180.v:7442.8-7442.67" + cell $and $and$ls180.v:7442$2408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:7442$2408_Y + end + attribute \src "ls180.v:7442.7-7442.102" + cell $and $and$ls180.v:7442$2410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7442$2408_Y + connect \B $not$ls180.v:7442$2409_Y + connect \Y $and$ls180.v:7442$2410_Y + end + attribute \src "ls180.v:7461.7-7461.75" + cell $and $and$ls180.v:7461$2414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7461$2413_Y + connect \B \main_libresocsim_zero_old_trigger + connect \Y $and$ls180.v:7461$2414_Y + end + attribute \src "ls180.v:7471.7-7471.56" + cell $and $and$ls180.v:7471$2416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_wait + connect \B $not$ls180.v:7471$2415_Y + connect \Y $and$ls180.v:7471$2416_Y + end + attribute \src "ls180.v:7499.7-7499.75" + cell $and $and$ls180.v:7499$2423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_start1 + connect \B $eq$ls180.v:7499$2422_Y + connect \Y $and$ls180.v:7499$2423_Y + end + attribute \src "ls180.v:7541.8-7541.131" + cell $and $and$ls180.v:7541$2429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \Y $and$ls180.v:7541$2429_Y + end + attribute \src "ls180.v:7541.7-7541.190" + cell $and $and$ls180.v:7541$2431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7541$2429_Y + connect \B $not$ls180.v:7541$2430_Y + connect \Y $and$ls180.v:7541$2431_Y + end + attribute \src "ls180.v:7547.8-7547.131" + cell $and $and$ls180.v:7547$2434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \Y $and$ls180.v:7547$2434_Y + end + attribute \src "ls180.v:7547.7-7547.190" + cell $and $and$ls180.v:7547$2436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7547$2434_Y + connect \B $not$ls180.v:7547$2435_Y + connect \Y $and$ls180.v:7547$2436_Y + end + attribute \src "ls180.v:7587.8-7587.131" + cell $and $and$ls180.v:7587$2445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \Y $and$ls180.v:7587$2445_Y + end + attribute \src "ls180.v:7587.7-7587.190" + cell $and $and$ls180.v:7587$2447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7587$2445_Y + connect \B $not$ls180.v:7587$2446_Y + connect \Y $and$ls180.v:7587$2447_Y + end + attribute \src "ls180.v:7593.8-7593.131" + cell $and $and$ls180.v:7593$2450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \Y $and$ls180.v:7593$2450_Y + end + attribute \src "ls180.v:7593.7-7593.190" + cell $and $and$ls180.v:7593$2452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7593$2450_Y + connect \B $not$ls180.v:7593$2451_Y + connect \Y $and$ls180.v:7593$2452_Y + end + attribute \src "ls180.v:7633.8-7633.131" + cell $and $and$ls180.v:7633$2461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \Y $and$ls180.v:7633$2461_Y + end + attribute \src "ls180.v:7633.7-7633.190" + cell $and $and$ls180.v:7633$2463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7633$2461_Y + connect \B $not$ls180.v:7633$2462_Y + connect \Y $and$ls180.v:7633$2463_Y + end + attribute \src "ls180.v:7639.8-7639.131" + cell $and $and$ls180.v:7639$2466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \Y $and$ls180.v:7639$2466_Y + end + attribute \src "ls180.v:7639.7-7639.190" + cell $and $and$ls180.v:7639$2468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7639$2466_Y + connect \B $not$ls180.v:7639$2467_Y + connect \Y $and$ls180.v:7639$2468_Y + end + attribute \src "ls180.v:7679.8-7679.131" + cell $and $and$ls180.v:7679$2477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \Y $and$ls180.v:7679$2477_Y + end + attribute \src "ls180.v:7679.7-7679.190" + cell $and $and$ls180.v:7679$2479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7679$2477_Y + connect \B $not$ls180.v:7679$2478_Y + connect \Y $and$ls180.v:7679$2479_Y + end + attribute \src "ls180.v:7685.8-7685.131" + cell $and $and$ls180.v:7685$2482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \Y $and$ls180.v:7685$2482_Y + end + attribute \src "ls180.v:7685.7-7685.190" + cell $and $and$ls180.v:7685$2484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7685$2482_Y + connect \B $not$ls180.v:7685$2483_Y + connect \Y $and$ls180.v:7685$2484_Y + end + attribute \src "ls180.v:7882.48-7882.124" + cell $and $and$ls180.v:7882$2509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7882$2508_Y + connect \B \main_sdram_interface_bank0_wdata_ready + connect \Y $and$ls180.v:7882$2509_Y + end + attribute \src "ls180.v:7882.130-7882.206" + cell $and $and$ls180.v:7882$2512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7882$2511_Y + connect \B \main_sdram_interface_bank1_wdata_ready + connect \Y $and$ls180.v:7882$2512_Y + end + attribute \src "ls180.v:7882.212-7882.288" + cell $and $and$ls180.v:7882$2515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7882$2514_Y + connect \B \main_sdram_interface_bank2_wdata_ready + connect \Y $and$ls180.v:7882$2515_Y + end + attribute \src "ls180.v:7882.294-7882.370" + cell $and $and$ls180.v:7882$2518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7882$2517_Y + connect \B \main_sdram_interface_bank3_wdata_ready + connect \Y $and$ls180.v:7882$2518_Y + end + attribute \src "ls180.v:7883.49-7883.125" + cell $and $and$ls180.v:7883$2521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7883$2520_Y + connect \B \main_sdram_interface_bank0_rdata_valid + connect \Y $and$ls180.v:7883$2521_Y + end + attribute \src "ls180.v:7883.131-7883.207" + cell $and $and$ls180.v:7883$2524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7883$2523_Y + connect \B \main_sdram_interface_bank1_rdata_valid + connect \Y $and$ls180.v:7883$2524_Y + end + attribute \src "ls180.v:7883.213-7883.289" + cell $and $and$ls180.v:7883$2527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7883$2526_Y + connect \B \main_sdram_interface_bank2_rdata_valid + connect \Y $and$ls180.v:7883$2527_Y + end + attribute \src "ls180.v:7883.295-7883.371" + cell $and $and$ls180.v:7883$2530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7883$2529_Y + connect \B \main_sdram_interface_bank3_rdata_valid + connect \Y $and$ls180.v:7883$2530_Y + end + attribute \src "ls180.v:7902.8-7902.49" + cell $and $and$ls180.v:7902$2533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_port_cmd_ready + connect \Y $and$ls180.v:7902$2533_Y + end + attribute \src "ls180.v:7905.8-7905.53" + cell $and $and$ls180.v:7905$2534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_wdata_valid + connect \B \main_port_wdata_ready + connect \Y $and$ls180.v:7905$2534_Y + end + attribute \src "ls180.v:7910.8-7910.41" + cell $and $and$ls180.v:7910$2536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sink_valid + connect \B $not$ls180.v:7910$2535_Y + connect \Y $and$ls180.v:7910$2536_Y + end + attribute \src "ls180.v:7910.7-7910.63" + cell $and $and$ls180.v:7910$2538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7910$2536_Y + connect \B $not$ls180.v:7910$2537_Y + connect \Y $and$ls180.v:7910$2538_Y + end + attribute \src "ls180.v:7916.8-7916.41" + cell $and $and$ls180.v:7916$2539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_clk_txen + connect \B \main_tx_busy + connect \Y $and$ls180.v:7916$2539_Y + end + attribute \src "ls180.v:7940.8-7940.30" + cell $and $and$ls180.v:7940$2546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7940$2545_Y + connect \B \main_rx_r + connect \Y $and$ls180.v:7940$2546_Y + end + attribute \src "ls180.v:7973.7-7973.57" + cell $and $and$ls180.v:7973$2552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7973$2551_Y + connect \B \main_uart_tx_old_trigger + connect \Y $and$ls180.v:7973$2552_Y + end + attribute \src "ls180.v:7980.7-7980.57" + cell $and $and$ls180.v:7980$2554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7980$2553_Y + connect \B \main_uart_rx_old_trigger + connect \Y $and$ls180.v:7980$2554_Y + end + attribute \src "ls180.v:7990.8-7990.75" + cell $and $and$ls180.v:7990$2555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_we + connect \B \main_uart_tx_fifo_syncfifo_writable + connect \Y $and$ls180.v:7990$2555_Y + end + attribute \src "ls180.v:7990.7-7990.107" + cell $and $and$ls180.v:7990$2557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7990$2555_Y + connect \B $not$ls180.v:7990$2556_Y + connect \Y $and$ls180.v:7990$2557_Y + end + attribute \src "ls180.v:7996.8-7996.75" + cell $and $and$ls180.v:7996$2560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_we + connect \B \main_uart_tx_fifo_syncfifo_writable + connect \Y $and$ls180.v:7996$2560_Y + end + attribute \src "ls180.v:7996.7-7996.107" + cell $and $and$ls180.v:7996$2562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7996$2560_Y + connect \B $not$ls180.v:7996$2561_Y + connect \Y $and$ls180.v:7996$2562_Y + end + attribute \src "ls180.v:8012.8-8012.75" + cell $and $and$ls180.v:8012$2566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_we + connect \B \main_uart_rx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8012$2566_Y + end + attribute \src "ls180.v:8012.7-8012.107" + cell $and $and$ls180.v:8012$2568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8012$2566_Y + connect \B $not$ls180.v:8012$2567_Y + connect \Y $and$ls180.v:8012$2568_Y + end + attribute \src "ls180.v:8018.8-8018.75" + cell $and $and$ls180.v:8018$2571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_we + connect \B \main_uart_rx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8018$2571_Y + end + attribute \src "ls180.v:8018.7-8018.107" + cell $and $and$ls180.v:8018$2573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8018$2571_Y + connect \B $not$ls180.v:8018$2572_Y + connect \Y $and$ls180.v:8018$2573_Y + end + attribute \src "ls180.v:8131.7-8131.96" + cell $and $and$ls180.v:8131$2596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_source_valid + connect \B \main_sdphy_cmdr_cmdr_converter_source_ready + connect \Y $and$ls180.v:8131$2596_Y + end + attribute \src "ls180.v:8132.8-8132.93" + cell $and $and$ls180.v:8132$2597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid + connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready + connect \Y $and$ls180.v:8132$2597_Y + end + attribute \src "ls180.v:8140.8-8140.93" + cell $and $and$ls180.v:8140$2598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid + connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready + connect \Y $and$ls180.v:8140$2598_Y + end + attribute \src "ls180.v:8212.7-8212.98" + cell $and $and$ls180.v:8212$2608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_source_valid + connect \B \main_sdphy_dataw_crcr_converter_source_ready + connect \Y $and$ls180.v:8212$2608_Y + end + attribute \src "ls180.v:8213.8-8213.95" + cell $and $and$ls180.v:8213$2609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_valid + connect \B \main_sdphy_dataw_crcr_converter_sink_ready + connect \Y $and$ls180.v:8213$2609_Y + end + attribute \src "ls180.v:8221.8-8221.95" + cell $and $and$ls180.v:8221$2610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_valid + connect \B \main_sdphy_dataw_crcr_converter_sink_ready + connect \Y $and$ls180.v:8221$2610_Y + end + attribute \src "ls180.v:8291.7-8291.100" + cell $and $and$ls180.v:8291$2620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_source_valid + connect \B \main_sdphy_datar_datar_converter_source_ready + connect \Y $and$ls180.v:8291$2620_Y + end + attribute \src "ls180.v:8292.8-8292.97" + cell $and $and$ls180.v:8292$2621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_valid + connect \B \main_sdphy_datar_datar_converter_sink_ready + connect \Y $and$ls180.v:8292$2621_Y + end + attribute \src "ls180.v:8300.8-8300.97" + cell $and $and$ls180.v:8300$2622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_valid + connect \B \main_sdphy_datar_datar_converter_sink_ready + connect \Y $and$ls180.v:8300$2622_Y + end + attribute \src "ls180.v:8391.7-8391.82" + cell $and $and$ls180.v:8391$2628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8391$2628_Y + end + attribute \src "ls180.v:8394.7-8394.82" + cell $and $and$ls180.v:8394$2629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8394$2629_Y + end + attribute \src "ls180.v:8397.7-8397.82" + cell $and $and$ls180.v:8397$2630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8397$2630_Y + end + attribute \src "ls180.v:8400.7-8400.82" + cell $and $and$ls180.v:8400$2631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8400$2631_Y + end + attribute \src "ls180.v:8403.7-8403.82" + cell $and $and$ls180.v:8403$2632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8403$2632_Y + end + attribute \src "ls180.v:8408.7-8408.82" + cell $and $and$ls180.v:8408$2633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8408$2633_Y + end + attribute \src "ls180.v:8413.7-8413.82" + cell $and $and$ls180.v:8413$2634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8413$2634_Y + end + attribute \src "ls180.v:8418.7-8418.82" + cell $and $and$ls180.v:8418$2635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8418$2635_Y + end + attribute \src "ls180.v:8423.7-8423.82" + cell $and $and$ls180.v:8423$2636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8423$2636_Y + end + attribute \src "ls180.v:8488.8-8488.83" + cell $and $and$ls180.v:8488$2639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_we + connect \B \main_sdblock2mem_fifo_syncfifo_writable + connect \Y $and$ls180.v:8488$2639_Y + end + attribute \src "ls180.v:8488.7-8488.119" + cell $and $and$ls180.v:8488$2641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8488$2639_Y + connect \B $not$ls180.v:8488$2640_Y + connect \Y $and$ls180.v:8488$2641_Y + end + attribute \src "ls180.v:8494.8-8494.83" + cell $and $and$ls180.v:8494$2644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_we + connect \B \main_sdblock2mem_fifo_syncfifo_writable + connect \Y $and$ls180.v:8494$2644_Y + end + attribute \src "ls180.v:8494.7-8494.119" + cell $and $and$ls180.v:8494$2646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8494$2644_Y + connect \B $not$ls180.v:8494$2645_Y + connect \Y $and$ls180.v:8494$2646_Y + end + attribute \src "ls180.v:8514.7-8514.88" + cell $and $and$ls180.v:8514$2653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_source_valid + connect \B \main_sdblock2mem_converter_source_ready + connect \Y $and$ls180.v:8514$2653_Y + end + attribute \src "ls180.v:8515.8-8515.85" + cell $and $and$ls180.v:8515$2654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_valid + connect \B \main_sdblock2mem_converter_sink_ready + connect \Y $and$ls180.v:8515$2654_Y + end + attribute \src "ls180.v:8523.8-8523.85" + cell $and $and$ls180.v:8523$2655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_valid + connect \B \main_sdblock2mem_converter_sink_ready + connect \Y $and$ls180.v:8523$2655_Y + end + attribute \src "ls180.v:8567.7-8567.88" + cell $and $and$ls180.v:8567$2659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_source_valid + connect \B \main_sdmem2block_converter_source_ready + connect \Y $and$ls180.v:8567$2659_Y + end + attribute \src "ls180.v:8574.8-8574.83" + cell $and $and$ls180.v:8574$2661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_we + connect \B \main_sdmem2block_fifo_syncfifo_writable + connect \Y $and$ls180.v:8574$2661_Y + end + attribute \src "ls180.v:8574.7-8574.119" + cell $and $and$ls180.v:8574$2663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8574$2661_Y + connect \B $not$ls180.v:8574$2662_Y + connect \Y $and$ls180.v:8574$2663_Y + end + attribute \src "ls180.v:8580.8-8580.83" + cell $and $and$ls180.v:8580$2666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_we + connect \B \main_sdmem2block_fifo_syncfifo_writable + connect \Y $and$ls180.v:8580$2666_Y + end + attribute \src "ls180.v:8580.7-8580.119" + cell $and $and$ls180.v:8580$2668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8580$2666_Y + connect \B $not$ls180.v:8580$2667_Y + connect \Y $and$ls180.v:8580$2668_Y + end + attribute \src "ls180.v:2762.42-2762.101" + cell $eq $eq$ls180.v:2762$18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface0_converted_interface_sel + connect \B 1'0 + connect \Y $eq$ls180.v:2762$18_Y + end + attribute \src "ls180.v:2769.11-2769.54" + cell $eq $eq$ls180.v:2769$23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter0_counter + connect \B 1'1 + connect \Y $eq$ls180.v:2769$23_Y + end + attribute \src "ls180.v:2822.42-2822.101" + cell $eq $eq$ls180.v:2822$29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface1_converted_interface_sel + connect \B 1'0 + connect \Y $eq$ls180.v:2822$29_Y + end + attribute \src "ls180.v:2829.11-2829.54" + cell $eq $eq$ls180.v:2829$34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter1_counter + connect \B 1'1 + connect \Y $eq$ls180.v:2829$34_Y + end + attribute \src "ls180.v:2882.42-2882.101" + cell $eq $eq$ls180.v:2882$40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface2_converted_interface_sel + connect \B 1'0 + connect \Y $eq$ls180.v:2882$40_Y + end + attribute \src "ls180.v:2889.11-2889.54" + cell $eq $eq$ls180.v:2889$45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter2_counter + connect \B 1'1 + connect \Y $eq$ls180.v:2889$45_Y + end + attribute \src "ls180.v:3080.34-3080.65" + cell $eq $eq$ls180.v:3080$74 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_count1 + connect \B 1'0 + connect \Y $eq$ls180.v:3080$74_Y + end + attribute \src "ls180.v:3084.68-3084.102" + cell $eq $eq$ls180.v:3084$77 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $eq$ls180.v:3084$77_Y + end + attribute \src "ls180.v:3128.43-3128.134" + cell $eq $eq$ls180.v:3128$82 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_row + connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3128$82_Y + end + attribute \src "ls180.v:3145.47-3145.88" + cell $eq $eq$ls180.v:3145$95 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3145$95_Y + end + attribute \src "ls180.v:3285.43-3285.134" + cell $eq $eq$ls180.v:3285$112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_row + connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3285$112_Y + end + attribute \src "ls180.v:3302.47-3302.88" + cell $eq $eq$ls180.v:3302$125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3302$125_Y + end + attribute \src "ls180.v:3442.43-3442.134" + cell $eq $eq$ls180.v:3442$142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_row + connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3442$142_Y + end + attribute \src "ls180.v:3459.47-3459.88" + cell $eq $eq$ls180.v:3459$155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3459$155_Y + end + attribute \src "ls180.v:3599.43-3599.134" + cell $eq $eq$ls180.v:3599$172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_row + connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3599$172_Y + end + attribute \src "ls180.v:3616.47-3616.88" + cell $eq $eq$ls180.v:3616$185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3616$185_Y + end + attribute \src "ls180.v:3753.32-3753.56" + cell $eq $eq$ls180.v:3753$232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_time0 + connect \B 1'0 + connect \Y $eq$ls180.v:3753$232_Y + end + attribute \src "ls180.v:3754.32-3754.56" + cell $eq $eq$ls180.v:3754$233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_time1 + connect \B 1'0 + connect \Y $eq$ls180.v:3754$233_Y + end + attribute \src "ls180.v:3765.339-3765.418" + cell $eq $eq$ls180.v:3765$247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3765$247_Y + end + attribute \src "ls180.v:3765.423-3765.504" + cell $eq $eq$ls180.v:3765$248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3765$248_Y + end + attribute \src "ls180.v:3766.339-3766.418" + cell $eq $eq$ls180.v:3766$260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3766$260_Y + end + attribute \src "ls180.v:3766.423-3766.504" + cell $eq $eq$ls180.v:3766$261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3766$261_Y + end + attribute \src "ls180.v:3767.339-3767.418" + cell $eq $eq$ls180.v:3767$273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3767$273_Y + end + attribute \src "ls180.v:3767.423-3767.504" + cell $eq $eq$ls180.v:3767$274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3767$274_Y + end + attribute \src "ls180.v:3768.339-3768.418" + cell $eq $eq$ls180.v:3768$286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3768$286_Y + end + attribute \src "ls180.v:3768.423-3768.504" + cell $eq $eq$ls180.v:3768$287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3768$287_Y + end + attribute \src "ls180.v:3798.339-3798.418" + cell $eq $eq$ls180.v:3798$305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:3798$305_Y + end + attribute \src "ls180.v:3798.423-3798.504" + cell $eq $eq$ls180.v:3798$306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:3798$306_Y + end + attribute \src "ls180.v:3799.339-3799.418" + cell $eq $eq$ls180.v:3799$318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:3799$318_Y + end + attribute \src "ls180.v:3799.423-3799.504" + cell $eq $eq$ls180.v:3799$319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:3799$319_Y + end + attribute \src "ls180.v:3800.339-3800.418" + cell $eq $eq$ls180.v:3800$331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:3800$331_Y + end + attribute \src "ls180.v:3800.423-3800.504" + cell $eq $eq$ls180.v:3800$332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:3800$332_Y + end + attribute \src "ls180.v:3801.339-3801.418" + cell $eq $eq$ls180.v:3801$344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:3801$344_Y + end + attribute \src "ls180.v:3801.423-3801.504" + cell $eq $eq$ls180.v:3801$345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:3801$345_Y + end + attribute \src "ls180.v:3830.78-3830.113" + cell $eq $eq$ls180.v:3830$354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3830$354_Y + end + attribute \src "ls180.v:3833.78-3833.113" + cell $eq $eq$ls180.v:3833$357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3833$357_Y + end + attribute \src "ls180.v:3839.78-3839.113" + cell $eq $eq$ls180.v:3839$361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 1'1 + connect \Y $eq$ls180.v:3839$361_Y + end + attribute \src "ls180.v:3842.78-3842.113" + cell $eq $eq$ls180.v:3842$364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 1'1 + connect \Y $eq$ls180.v:3842$364_Y + end + attribute \src "ls180.v:3848.78-3848.113" + cell $eq $eq$ls180.v:3848$368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 2'10 + connect \Y $eq$ls180.v:3848$368_Y + end + attribute \src "ls180.v:3851.78-3851.113" + cell $eq $eq$ls180.v:3851$371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 2'10 + connect \Y $eq$ls180.v:3851$371_Y + end + attribute \src "ls180.v:3857.78-3857.113" + cell $eq $eq$ls180.v:3857$375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 2'11 + connect \Y $eq$ls180.v:3857$375_Y + end + attribute \src "ls180.v:3860.78-3860.113" + cell $eq $eq$ls180.v:3860$378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 2'11 + connect \Y $eq$ls180.v:3860$378_Y + end + attribute \src "ls180.v:3941.42-3941.82" + cell $eq $eq$ls180.v:3941$401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:3941$401_Y + end + attribute \src "ls180.v:3941.145-3941.178" + cell $eq $eq$ls180.v:3941$402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3941$402_Y + end + attribute \src "ls180.v:3941.220-3941.253" + cell $eq $eq$ls180.v:3941$405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3941$405_Y + end + attribute \src "ls180.v:3941.295-3941.328" + cell $eq $eq$ls180.v:3941$408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3941$408_Y + end + attribute \src "ls180.v:3946.42-3946.82" + cell $eq $eq$ls180.v:3946$417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:3946$417_Y + end + attribute \src "ls180.v:3946.145-3946.178" + cell $eq $eq$ls180.v:3946$418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3946$418_Y + end + attribute \src "ls180.v:3946.220-3946.253" + cell $eq $eq$ls180.v:3946$421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3946$421_Y + end + attribute \src "ls180.v:3946.295-3946.328" + cell $eq $eq$ls180.v:3946$424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3946$424_Y + end + attribute \src "ls180.v:3951.42-3951.82" + cell $eq $eq$ls180.v:3951$433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:3951$433_Y + end + attribute \src "ls180.v:3951.145-3951.178" + cell $eq $eq$ls180.v:3951$434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3951$434_Y + end + attribute \src "ls180.v:3951.220-3951.253" + cell $eq $eq$ls180.v:3951$437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3951$437_Y + end + attribute \src "ls180.v:3951.295-3951.328" + cell $eq $eq$ls180.v:3951$440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3951$440_Y + end + attribute \src "ls180.v:3956.42-3956.82" + cell $eq $eq$ls180.v:3956$449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:3956$449_Y + end + attribute \src "ls180.v:3956.145-3956.178" + cell $eq $eq$ls180.v:3956$450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3956$450_Y + end + attribute \src "ls180.v:3956.220-3956.253" + cell $eq $eq$ls180.v:3956$453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3956$453_Y + end + attribute \src "ls180.v:3956.295-3956.328" + cell $eq $eq$ls180.v:3956$456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3956$456_Y + end + attribute \src "ls180.v:3961.44-3961.77" + cell $eq $eq$ls180.v:3961$465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3961$465_Y + end + attribute \src "ls180.v:3961.83-3961.123" + cell $eq $eq$ls180.v:3961$466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:3961$466_Y + end + attribute \src "ls180.v:3961.186-3961.219" + cell $eq $eq$ls180.v:3961$467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3961$467_Y + end + attribute \src "ls180.v:3961.261-3961.294" + cell $eq $eq$ls180.v:3961$470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3961$470_Y + end + attribute \src "ls180.v:3961.336-3961.369" + cell $eq $eq$ls180.v:3961$473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3961$473_Y + end + attribute \src "ls180.v:3961.418-3961.451" + cell $eq $eq$ls180.v:3961$481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3961$481_Y + end + attribute \src "ls180.v:3961.457-3961.497" + cell $eq $eq$ls180.v:3961$482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:3961$482_Y + end + attribute \src "ls180.v:3961.560-3961.593" + cell $eq $eq$ls180.v:3961$483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3961$483_Y + end + attribute \src "ls180.v:3961.635-3961.668" + cell $eq $eq$ls180.v:3961$486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3961$486_Y + end + attribute \src "ls180.v:3961.710-3961.743" + cell $eq $eq$ls180.v:3961$489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3961$489_Y + end + attribute \src "ls180.v:3961.792-3961.825" + cell $eq $eq$ls180.v:3961$497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3961$497_Y + end + attribute \src "ls180.v:3961.831-3961.871" + cell $eq $eq$ls180.v:3961$498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:3961$498_Y + end + attribute \src "ls180.v:3961.934-3961.967" + cell $eq $eq$ls180.v:3961$499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3961$499_Y + end + attribute \src "ls180.v:3961.1009-3961.1042" + cell $eq $eq$ls180.v:3961$502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3961$502_Y + end + attribute \src "ls180.v:3961.1084-3961.1117" + cell $eq $eq$ls180.v:3961$505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3961$505_Y + end + attribute \src "ls180.v:3961.1166-3961.1199" + cell $eq $eq$ls180.v:3961$513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3961$513_Y + end + attribute \src "ls180.v:3961.1205-3961.1245" + cell $eq $eq$ls180.v:3961$514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:3961$514_Y + end + attribute \src "ls180.v:3961.1308-3961.1341" + cell $eq $eq$ls180.v:3961$515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3961$515_Y + end + attribute \src "ls180.v:3961.1383-3961.1416" + cell $eq $eq$ls180.v:3961$518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3961$518_Y + end + attribute \src "ls180.v:3961.1458-3961.1491" + cell $eq $eq$ls180.v:3961$521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3961$521_Y + end + attribute \src "ls180.v:4020.29-4020.57" + cell $eq $eq$ls180.v:4020$534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_sel + connect \B 1'0 + connect \Y $eq$ls180.v:4020$534_Y + end + attribute \src "ls180.v:4027.11-4027.41" + cell $eq $eq$ls180.v:4027$539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_counter + connect \B 1'1 + connect \Y $eq$ls180.v:4027$539_Y + end + attribute \src "ls180.v:4184.36-4184.111" + cell $eq $eq$ls180.v:4184$604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spi_master_clk_divider1 + connect \B $sub$ls180.v:4184$603_Y + connect \Y $eq$ls180.v:4184$604_Y + end + attribute \src "ls180.v:4185.36-4185.105" + cell $eq $eq$ls180.v:4185$606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spi_master_clk_divider1 + connect \B $sub$ls180.v:4185$605_Y + connect \Y $eq$ls180.v:4185$606_Y + end + attribute \src "ls180.v:4212.10-4212.67" + cell $eq $eq$ls180.v:4212$610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \main_spi_master_count + connect \B $sub$ls180.v:4212$609_Y + connect \Y $eq$ls180.v:4212$610_Y + end + attribute \src "ls180.v:4312.10-4312.40" + cell $eq $eq$ls180.v:4312$637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_count + connect \B 7'1001111 + connect \Y $eq$ls180.v:4312$637_Y + end + attribute \src "ls180.v:4369.10-4369.39" + cell $eq $eq$ls180.v:4369$640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_count + connect \B 3'111 + connect \Y $eq$ls180.v:4369$640_Y + end + attribute \src "ls180.v:4386.10-4386.39" + cell $eq $eq$ls180.v:4386$642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_count + connect \B 3'111 + connect \Y $eq$ls180.v:4386$642_Y + end + attribute \src "ls180.v:4414.38-4414.88" + cell $eq $eq$ls180.v:4414$644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i + connect \B 1'0 + connect \Y $eq$ls180.v:4414$644_Y + end + attribute \src "ls180.v:4464.9-4464.40" + cell $eq $eq$ls180.v:4464$654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4464$654_Y + end + attribute \src "ls180.v:4473.36-4473.105" + cell $eq $eq$ls180.v:4473$656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_count + connect \B $sub$ls180.v:4473$655_Y + connect \Y $eq$ls180.v:4473$656_Y + end + attribute \src "ls180.v:4492.9-4492.40" + cell $eq $eq$ls180.v:4492$660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4492$660_Y + end + attribute \src "ls180.v:4504.10-4504.39" + cell $eq $eq$ls180.v:4504$662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_count + connect \B 3'111 + connect \Y $eq$ls180.v:4504$662_Y + end + attribute \src "ls180.v:4541.39-4541.94" + cell $eq $eq$ls180.v:4541$666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] + connect \B 1'0 + connect \Y $eq$ls180.v:4541$666_Y + end + attribute \src "ls180.v:4578.32-4578.89" + cell $eq $eq$ls180.v:4578$675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 + connect \B 3'101 + connect \Y $eq$ls180.v:4578$675_Y + end + attribute \src "ls180.v:4626.10-4626.40" + cell $eq $eq$ls180.v:4626$679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_count + connect \B 1'1 + connect \Y $eq$ls180.v:4626$679_Y + end + attribute \src "ls180.v:4675.40-4675.98" + cell $eq $eq$ls180.v:4675$681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_pads_in_payload_data_i + connect \B 1'0 + connect \Y $eq$ls180.v:4675$681_Y + end + attribute \src "ls180.v:4726.9-4726.41" + cell $eq $eq$ls180.v:4726$691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4726$691_Y + end + attribute \src "ls180.v:4735.37-4735.123" + cell $eq $eq$ls180.v:4735$694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_count + connect \B $sub$ls180.v:4735$693_Y + connect \Y $eq$ls180.v:4735$694_Y + end + attribute \src "ls180.v:4758.9-4758.41" + cell $eq $eq$ls180.v:4758$697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4758$697_Y + end + attribute \src "ls180.v:4768.10-4768.41" + cell $eq $eq$ls180.v:4768$699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_count + connect \B 6'100111 + connect \Y $eq$ls180.v:4768$699_Y + end + attribute \src "ls180.v:4937.9-4937.47" + cell $eq $eq$ls180.v:4937$881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:4937$881_Y + end + attribute \src "ls180.v:4967.10-4967.48" + cell $eq $eq$ls180.v:4967$882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:4967$882_Y + end + attribute \src "ls180.v:4998.10-4998.78" + cell $eq $eq$ls180.v:4998$887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo0 + connect \B \main_sdcore_crc16_checker_crctmp0 + connect \Y $eq$ls180.v:4998$887_Y + end + attribute \src "ls180.v:4998.83-4998.151" + cell $eq $eq$ls180.v:4998$888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo1 + connect \B \main_sdcore_crc16_checker_crctmp1 + connect \Y $eq$ls180.v:4998$888_Y + end + attribute \src "ls180.v:4998.157-4998.225" + cell $eq $eq$ls180.v:4998$890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo2 + connect \B \main_sdcore_crc16_checker_crctmp2 + connect \Y $eq$ls180.v:4998$890_Y + end + attribute \src "ls180.v:4998.231-4998.299" + cell $eq $eq$ls180.v:4998$892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo3 + connect \B \main_sdcore_crc16_checker_crctmp3 + connect \Y $eq$ls180.v:4998$892_Y + end + attribute \src "ls180.v:5006.7-5006.44" + cell $eq $eq$ls180.v:5006$896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5006$896_Y + end + attribute \src "ls180.v:5016.7-5016.44" + cell $eq $eq$ls180.v:5016$899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5016$899_Y + end + attribute \src "ls180.v:5026.7-5026.44" + cell $eq $eq$ls180.v:5026$902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5026$902_Y + end + attribute \src "ls180.v:5036.7-5036.44" + cell $eq $eq$ls180.v:5036$905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5036$905_Y + end + attribute \src "ls180.v:5160.36-5160.64" + cell $eq $eq$ls180.v:5160$956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_type + connect \B 1'0 + connect \Y $eq$ls180.v:5160$956_Y + end + attribute \src "ls180.v:5166.10-5166.39" + cell $eq $eq$ls180.v:5166$959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_count + connect \B 3'101 + connect \Y $eq$ls180.v:5166$959_Y + end + attribute \src "ls180.v:5167.11-5167.39" + cell $eq $eq$ls180.v:5167$960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_type + connect \B 1'0 + connect \Y $eq$ls180.v:5167$960_Y + end + attribute \src "ls180.v:5179.34-5179.63" + cell $eq $eq$ls180.v:5179$961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_type + connect \B 1'0 + connect \Y $eq$ls180.v:5179$961_Y + end + attribute \src "ls180.v:5180.9-5180.37" + cell $eq $eq$ls180.v:5180$962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_type + connect \B 2'10 + connect \Y $eq$ls180.v:5180$962_Y + end + attribute \src "ls180.v:5187.10-5187.55" + cell $eq $eq$ls180.v:5187$963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_source_payload_status + connect \B 1'1 + connect \Y $eq$ls180.v:5187$963_Y + end + attribute \src "ls180.v:5193.12-5193.41" + cell $eq $eq$ls180.v:5193$964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_type + connect \B 2'10 + connect \Y $eq$ls180.v:5193$964_Y + end + attribute \src "ls180.v:5196.13-5196.42" + cell $eq $eq$ls180.v:5196$965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_type + connect \B 1'1 + connect \Y $eq$ls180.v:5196$965_Y + end + attribute \src "ls180.v:5218.10-5218.76" + cell $eq $eq$ls180.v:5218$970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_count + connect \B $sub$ls180.v:5218$969_Y + connect \Y $eq$ls180.v:5218$970_Y + end + attribute \src "ls180.v:5233.35-5233.101" + cell $eq $eq$ls180.v:5233$973 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_count + connect \B $sub$ls180.v:5233$972_Y + connect \Y $eq$ls180.v:5233$973_Y + end + attribute \src "ls180.v:5235.10-5235.56" + cell $eq $eq$ls180.v:5235$974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_payload_status + connect \B 1'0 + connect \Y $eq$ls180.v:5235$974_Y + end + attribute \src "ls180.v:5244.12-5244.78" + cell $eq $eq$ls180.v:5244$978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_count + connect \B $sub$ls180.v:5244$977_Y + connect \Y $eq$ls180.v:5244$978_Y + end + attribute \src "ls180.v:5251.11-5251.57" + cell $eq $eq$ls180.v:5251$979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_payload_status + connect \B 1'1 + connect \Y $eq$ls180.v:5251$979_Y + end + attribute \src "ls180.v:5368.10-5368.105" + cell $eq $eq$ls180.v:5368$996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_wishbonedmawriter_offset + connect \B $sub$ls180.v:5368$995_Y + connect \Y $eq$ls180.v:5368$996_Y + end + attribute \src "ls180.v:5458.39-5458.106" + cell $eq $eq$ls180.v:5458$1002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_dma_offset + connect \B $sub$ls180.v:5458$1001_Y + connect \Y $eq$ls180.v:5458$1002_Y + end + attribute \src "ls180.v:5488.44-5488.82" + cell $eq $eq$ls180.v:5488$1005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_mux + connect \B 1'0 + connect \Y $eq$ls180.v:5488$1005_Y + end + attribute \src "ls180.v:5489.43-5489.81" + cell $eq $eq$ls180.v:5489$1006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_mux + connect \B 2'11 + connect \Y $eq$ls180.v:5489$1006_Y + end + attribute \src "ls180.v:5546.32-5546.99" + cell $eq $eq$ls180.v:5546$1019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \libresocsim_clk_divider1 + connect \B $sub$ls180.v:5546$1018_Y + connect \Y $eq$ls180.v:5546$1019_Y + end + attribute \src "ls180.v:5547.32-5547.93" + cell $eq $eq$ls180.v:5547$1021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \libresocsim_clk_divider1 + connect \B $sub$ls180.v:5547$1020_Y + connect \Y $eq$ls180.v:5547$1021_Y + end + attribute \src "ls180.v:5575.10-5575.59" + cell $eq $eq$ls180.v:5575$1025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \libresocsim_count + connect \B $sub$ls180.v:5575$1024_Y + connect \Y $eq$ls180.v:5575$1025_Y + end + attribute \src "ls180.v:5648.85-5648.106" + cell $eq $eq$ls180.v:5648$1030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'0 + connect \Y $eq$ls180.v:5648$1030_Y + end + attribute \src "ls180.v:5649.85-5649.106" + cell $eq $eq$ls180.v:5649$1032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'1 + connect \Y $eq$ls180.v:5649$1032_Y + end + attribute \src "ls180.v:5650.85-5650.106" + cell $eq $eq$ls180.v:5650$1034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'10 + connect \Y $eq$ls180.v:5650$1034_Y + end + attribute \src "ls180.v:5651.57-5651.78" + cell $eq $eq$ls180.v:5651$1036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'11 + connect \Y $eq$ls180.v:5651$1036_Y + end + attribute \src "ls180.v:5652.57-5652.78" + cell $eq $eq$ls180.v:5652$1038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 3'100 + connect \Y $eq$ls180.v:5652$1038_Y + end + attribute \src "ls180.v:5653.85-5653.106" + cell $eq $eq$ls180.v:5653$1040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'0 + connect \Y $eq$ls180.v:5653$1040_Y + end + attribute \src "ls180.v:5654.85-5654.106" + cell $eq $eq$ls180.v:5654$1042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'1 + connect \Y $eq$ls180.v:5654$1042_Y + end + attribute \src "ls180.v:5655.85-5655.106" + cell $eq $eq$ls180.v:5655$1044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'10 + connect \Y $eq$ls180.v:5655$1044_Y + end + attribute \src "ls180.v:5656.57-5656.78" + cell $eq $eq$ls180.v:5656$1046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'11 + connect \Y $eq$ls180.v:5656$1046_Y + end + attribute \src "ls180.v:5657.57-5657.78" + cell $eq $eq$ls180.v:5657$1048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 3'100 + connect \Y $eq$ls180.v:5657$1048_Y + end + attribute \src "ls180.v:5661.27-5661.59" + cell $eq $eq$ls180.v:5661$1051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 23 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:7] + connect \B 1'0 + connect \Y $eq$ls180.v:5661$1051_Y + end + attribute \src "ls180.v:5662.27-5662.68" + cell $eq $eq$ls180.v:5662$1052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 27 + parameter \B_SIGNED 0 + parameter \B_WIDTH 27 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:3] + connect \B 27'110000000000000100000000000 + connect \Y $eq$ls180.v:5662$1052_Y + end + attribute \src "ls180.v:5663.27-5663.66" + cell $eq $eq$ls180.v:5663$1053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 20 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:10] + connect \B 20'11000000000000010001 + connect \Y $eq$ls180.v:5663$1053_Y + end + attribute \src "ls180.v:5664.27-5664.61" + cell $eq $eq$ls180.v:5664$1054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:23] + connect \B 7'1001000 + connect \Y $eq$ls180.v:5664$1054_Y + end + attribute \src "ls180.v:5665.27-5665.65" + cell $eq $eq$ls180.v:5665$1055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:14] + connect \B 16'1100000000000000 + connect \Y $eq$ls180.v:5665$1055_Y + end + attribute \src "ls180.v:5721.24-5721.45" + cell $eq $eq$ls180.v:5721$1082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_count + connect \B 1'0 + connect \Y $eq$ls180.v:5721$1082_Y + end + attribute \src "ls180.v:5722.32-5722.77" + cell $eq $eq$ls180.v:5722$1083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [13:9] + connect \B 1'0 + connect \Y $eq$ls180.v:5722$1083_Y + end + attribute \src "ls180.v:5724.97-5724.141" + cell $eq $eq$ls180.v:5724$1085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5724$1085_Y + end + attribute \src "ls180.v:5725.100-5725.144" + cell $eq $eq$ls180.v:5725$1089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5725$1089_Y + end + attribute \src "ls180.v:5727.99-5727.143" + cell $eq $eq$ls180.v:5727$1092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5727$1092_Y + end + attribute \src "ls180.v:5728.102-5728.146" + cell $eq $eq$ls180.v:5728$1096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5728$1096_Y + end + attribute \src "ls180.v:5730.99-5730.143" + cell $eq $eq$ls180.v:5730$1099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5730$1099_Y + end + attribute \src "ls180.v:5731.102-5731.146" + cell $eq $eq$ls180.v:5731$1103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5731$1103_Y + end + attribute \src "ls180.v:5733.99-5733.143" + cell $eq $eq$ls180.v:5733$1106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5733$1106_Y + end + attribute \src "ls180.v:5734.102-5734.146" + cell $eq $eq$ls180.v:5734$1110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5734$1110_Y + end + attribute \src "ls180.v:5736.99-5736.143" + cell $eq $eq$ls180.v:5736$1113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5736$1113_Y + end + attribute \src "ls180.v:5737.102-5737.146" + cell $eq $eq$ls180.v:5737$1117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5737$1117_Y + end + attribute \src "ls180.v:5739.102-5739.146" + cell $eq $eq$ls180.v:5739$1120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5739$1120_Y + end + attribute \src "ls180.v:5740.105-5740.149" + cell $eq $eq$ls180.v:5740$1124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5740$1124_Y + end + attribute \src "ls180.v:5742.102-5742.146" + cell $eq $eq$ls180.v:5742$1127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5742$1127_Y + end + attribute \src "ls180.v:5743.105-5743.149" + cell $eq $eq$ls180.v:5743$1131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5743$1131_Y + end + attribute \src "ls180.v:5745.102-5745.146" + cell $eq $eq$ls180.v:5745$1134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5745$1134_Y + end + attribute \src "ls180.v:5746.105-5746.149" + cell $eq $eq$ls180.v:5746$1138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5746$1138_Y + end + attribute \src "ls180.v:5748.102-5748.146" + cell $eq $eq$ls180.v:5748$1141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5748$1141_Y + end + attribute \src "ls180.v:5749.105-5749.149" + cell $eq $eq$ls180.v:5749$1145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5749$1145_Y + end + attribute \src "ls180.v:5760.32-5760.77" + cell $eq $eq$ls180.v:5760$1147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [13:9] + connect \B 3'110 + connect \Y $eq$ls180.v:5760$1147_Y + end + attribute \src "ls180.v:5762.94-5762.138" + cell $eq $eq$ls180.v:5762$1149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5762$1149_Y + end + attribute \src "ls180.v:5763.97-5763.141" + cell $eq $eq$ls180.v:5763$1153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5763$1153_Y + end + attribute \src "ls180.v:5765.94-5765.138" + cell $eq $eq$ls180.v:5765$1156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5765$1156_Y + end + attribute \src "ls180.v:5766.97-5766.141" + cell $eq $eq$ls180.v:5766$1160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5766$1160_Y + end + attribute \src "ls180.v:5768.94-5768.138" + cell $eq $eq$ls180.v:5768$1163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5768$1163_Y + end + attribute \src "ls180.v:5769.97-5769.141" + cell $eq $eq$ls180.v:5769$1167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5769$1167_Y + end + attribute \src "ls180.v:5771.94-5771.138" + cell $eq $eq$ls180.v:5771$1170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5771$1170_Y + end + attribute \src "ls180.v:5772.97-5772.141" + cell $eq $eq$ls180.v:5772$1174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5772$1174_Y + end + attribute \src "ls180.v:5774.95-5774.139" + cell $eq $eq$ls180.v:5774$1177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5774$1177_Y + end + attribute \src "ls180.v:5775.98-5775.142" + cell $eq $eq$ls180.v:5775$1181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5775$1181_Y + end + attribute \src "ls180.v:5777.95-5777.139" + cell $eq $eq$ls180.v:5777$1184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5777$1184_Y + end + attribute \src "ls180.v:5778.98-5778.142" + cell $eq $eq$ls180.v:5778$1188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5778$1188_Y + end + attribute \src "ls180.v:5786.32-5786.77" + cell $eq $eq$ls180.v:5786$1190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [13:9] + connect \B 4'1000 + connect \Y $eq$ls180.v:5786$1190_Y + end + attribute \src "ls180.v:5788.98-5788.142" + cell $eq $eq$ls180.v:5788$1192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5788$1192_Y + end + attribute \src "ls180.v:5789.101-5789.145" + cell $eq $eq$ls180.v:5789$1196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5789$1196_Y + end + attribute \src "ls180.v:5791.97-5791.141" + cell $eq $eq$ls180.v:5791$1199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5791$1199_Y + end + attribute \src "ls180.v:5792.100-5792.144" + cell $eq $eq$ls180.v:5792$1203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5792$1203_Y + end + attribute \src "ls180.v:5794.97-5794.141" + cell $eq $eq$ls180.v:5794$1206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5794$1206_Y + end + attribute \src "ls180.v:5795.100-5795.144" + cell $eq $eq$ls180.v:5795$1210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5795$1210_Y + end + attribute \src "ls180.v:5797.97-5797.141" + cell $eq $eq$ls180.v:5797$1213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5797$1213_Y + end + attribute \src "ls180.v:5798.100-5798.144" + cell $eq $eq$ls180.v:5798$1217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5798$1217_Y + end + attribute \src "ls180.v:5800.97-5800.141" + cell $eq $eq$ls180.v:5800$1220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5800$1220_Y + end + attribute \src "ls180.v:5801.100-5801.144" + cell $eq $eq$ls180.v:5801$1224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5801$1224_Y + end + attribute \src "ls180.v:5803.98-5803.142" + cell $eq $eq$ls180.v:5803$1227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5803$1227_Y + end + attribute \src "ls180.v:5804.101-5804.145" + cell $eq $eq$ls180.v:5804$1231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5804$1231_Y + end + attribute \src "ls180.v:5806.98-5806.142" + cell $eq $eq$ls180.v:5806$1234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5806$1234_Y + end + attribute \src "ls180.v:5807.101-5807.145" + cell $eq $eq$ls180.v:5807$1238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5807$1238_Y + end + attribute \src "ls180.v:5809.98-5809.142" + cell $eq $eq$ls180.v:5809$1241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5809$1241_Y + end + attribute \src "ls180.v:5810.101-5810.145" + cell $eq $eq$ls180.v:5810$1245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5810$1245_Y + end + attribute \src "ls180.v:5812.98-5812.142" + cell $eq $eq$ls180.v:5812$1248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5812$1248_Y + end + attribute \src "ls180.v:5813.101-5813.145" + cell $eq $eq$ls180.v:5813$1252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5813$1252_Y + end + attribute \src "ls180.v:5823.32-5823.77" + cell $eq $eq$ls180.v:5823$1254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [13:9] + connect \B 4'1001 + connect \Y $eq$ls180.v:5823$1254_Y + end + attribute \src "ls180.v:5825.98-5825.142" + cell $eq $eq$ls180.v:5825$1256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5825$1256_Y + end + attribute \src "ls180.v:5826.101-5826.145" + cell $eq $eq$ls180.v:5826$1260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5826$1260_Y + end + attribute \src "ls180.v:5828.97-5828.141" + cell $eq $eq$ls180.v:5828$1263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5828$1263_Y + end + attribute \src "ls180.v:5829.100-5829.144" + cell $eq $eq$ls180.v:5829$1267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5829$1267_Y + end + attribute \src "ls180.v:5831.97-5831.141" + cell $eq $eq$ls180.v:5831$1270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5831$1270_Y + end + attribute \src "ls180.v:5832.100-5832.144" + cell $eq $eq$ls180.v:5832$1274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5832$1274_Y + end + attribute \src "ls180.v:5834.97-5834.141" + cell $eq $eq$ls180.v:5834$1277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5834$1277_Y + end + attribute \src "ls180.v:5835.100-5835.144" + cell $eq $eq$ls180.v:5835$1281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5835$1281_Y + end + attribute \src "ls180.v:5837.97-5837.141" + cell $eq $eq$ls180.v:5837$1284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5837$1284_Y + end + attribute \src "ls180.v:5838.100-5838.144" + cell $eq $eq$ls180.v:5838$1288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5838$1288_Y + end + attribute \src "ls180.v:5840.98-5840.142" + cell $eq $eq$ls180.v:5840$1291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5840$1291_Y + end + attribute \src "ls180.v:5841.101-5841.145" + cell $eq $eq$ls180.v:5841$1295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5841$1295_Y + end + attribute \src "ls180.v:5843.98-5843.142" + cell $eq $eq$ls180.v:5843$1298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5843$1298_Y + end + attribute \src "ls180.v:5844.101-5844.145" + cell $eq $eq$ls180.v:5844$1302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5844$1302_Y + end + attribute \src "ls180.v:5846.98-5846.142" + cell $eq $eq$ls180.v:5846$1305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5846$1305_Y + end + attribute \src "ls180.v:5847.101-5847.145" + cell $eq $eq$ls180.v:5847$1309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5847$1309_Y + end + attribute \src "ls180.v:5849.98-5849.142" + cell $eq $eq$ls180.v:5849$1312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5849$1312_Y + end + attribute \src "ls180.v:5850.101-5850.145" + cell $eq $eq$ls180.v:5850$1316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5850$1316_Y + end + attribute \src "ls180.v:5860.32-5860.78" + cell $eq $eq$ls180.v:5860$1318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [13:9] + connect \B 4'1100 + connect \Y $eq$ls180.v:5860$1318_Y + end + attribute \src "ls180.v:5862.100-5862.144" + cell $eq $eq$ls180.v:5862$1320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5862$1320_Y + end + attribute \src "ls180.v:5863.103-5863.147" + cell $eq $eq$ls180.v:5863$1324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5863$1324_Y + end + attribute \src "ls180.v:5865.100-5865.144" + cell $eq $eq$ls180.v:5865$1327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5865$1327_Y + end + attribute \src "ls180.v:5866.103-5866.147" + cell $eq $eq$ls180.v:5866$1331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5866$1331_Y + end + attribute \src "ls180.v:5868.100-5868.144" + cell $eq $eq$ls180.v:5868$1334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5868$1334_Y + end + attribute \src "ls180.v:5869.103-5869.147" + cell $eq $eq$ls180.v:5869$1338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5869$1338_Y + end + attribute \src "ls180.v:5871.100-5871.144" + cell $eq $eq$ls180.v:5871$1341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5871$1341_Y + end + attribute \src "ls180.v:5872.103-5872.147" + cell $eq $eq$ls180.v:5872$1345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5872$1345_Y + end + attribute \src "ls180.v:5874.100-5874.144" + cell $eq $eq$ls180.v:5874$1348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5874$1348_Y + end + attribute \src "ls180.v:5875.103-5875.147" + cell $eq $eq$ls180.v:5875$1352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5875$1352_Y + end + attribute \src "ls180.v:5877.100-5877.144" + cell $eq $eq$ls180.v:5877$1355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5877$1355_Y + end + attribute \src "ls180.v:5878.103-5878.147" + cell $eq $eq$ls180.v:5878$1359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5878$1359_Y + end + attribute \src "ls180.v:5880.100-5880.144" + cell $eq $eq$ls180.v:5880$1362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5880$1362_Y + end + attribute \src "ls180.v:5881.103-5881.147" + cell $eq $eq$ls180.v:5881$1366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5881$1366_Y + end + attribute \src "ls180.v:5883.100-5883.144" + cell $eq $eq$ls180.v:5883$1369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5883$1369_Y + end + attribute \src "ls180.v:5884.103-5884.147" + cell $eq $eq$ls180.v:5884$1373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5884$1373_Y + end + attribute \src "ls180.v:5886.102-5886.146" + cell $eq $eq$ls180.v:5886$1376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5886$1376_Y + end + attribute \src "ls180.v:5887.105-5887.149" + cell $eq $eq$ls180.v:5887$1380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5887$1380_Y + end + attribute \src "ls180.v:5889.102-5889.146" + cell $eq $eq$ls180.v:5889$1383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:5889$1383_Y + end + attribute \src "ls180.v:5890.105-5890.149" + cell $eq $eq$ls180.v:5890$1387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:5890$1387_Y + end + attribute \src "ls180.v:5892.102-5892.147" + cell $eq $eq$ls180.v:5892$1390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:5892$1390_Y + end + attribute \src "ls180.v:5893.105-5893.150" + cell $eq $eq$ls180.v:5893$1394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:5893$1394_Y + end + attribute \src "ls180.v:5895.102-5895.147" + cell $eq $eq$ls180.v:5895$1397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:5895$1397_Y + end + attribute \src "ls180.v:5896.105-5896.150" + cell $eq $eq$ls180.v:5896$1401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:5896$1401_Y + end + attribute \src "ls180.v:5898.102-5898.147" + cell $eq $eq$ls180.v:5898$1404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:5898$1404_Y + end + attribute \src "ls180.v:5899.105-5899.150" + cell $eq $eq$ls180.v:5899$1408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:5899$1408_Y + end + attribute \src "ls180.v:5901.99-5901.144" + cell $eq $eq$ls180.v:5901$1411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:5901$1411_Y + end + attribute \src "ls180.v:5902.102-5902.147" + cell $eq $eq$ls180.v:5902$1415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:5902$1415_Y + end + attribute \src "ls180.v:5904.100-5904.145" + cell $eq $eq$ls180.v:5904$1418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:5904$1418_Y + end + attribute \src "ls180.v:5905.103-5905.148" + cell $eq $eq$ls180.v:5905$1422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:5905$1422_Y + end + attribute \src "ls180.v:5922.32-5922.78" + cell $eq $eq$ls180.v:5922$1424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [13:9] + connect \B 4'1011 + connect \Y $eq$ls180.v:5922$1424_Y + end + attribute \src "ls180.v:5924.104-5924.148" + cell $eq $eq$ls180.v:5924$1426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5924$1426_Y + end + attribute \src "ls180.v:5925.107-5925.151" + cell $eq $eq$ls180.v:5925$1430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5925$1430_Y + end + attribute \src "ls180.v:5927.104-5927.148" + cell $eq $eq$ls180.v:5927$1433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5927$1433_Y + end + attribute \src "ls180.v:5928.107-5928.151" + cell $eq $eq$ls180.v:5928$1437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5928$1437_Y + end + attribute \src "ls180.v:5930.104-5930.148" + cell $eq $eq$ls180.v:5930$1440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5930$1440_Y + end + attribute \src "ls180.v:5931.107-5931.151" + cell $eq $eq$ls180.v:5931$1444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5931$1444_Y + end + attribute \src "ls180.v:5933.104-5933.148" + cell $eq $eq$ls180.v:5933$1447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5933$1447_Y + end + attribute \src "ls180.v:5934.107-5934.151" + cell $eq $eq$ls180.v:5934$1451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5934$1451_Y + end + attribute \src "ls180.v:5936.103-5936.147" + cell $eq $eq$ls180.v:5936$1454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5936$1454_Y + end + attribute \src "ls180.v:5937.106-5937.150" + cell $eq $eq$ls180.v:5937$1458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5937$1458_Y + end + attribute \src "ls180.v:5939.103-5939.147" + cell $eq $eq$ls180.v:5939$1461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5939$1461_Y + end + attribute \src "ls180.v:5940.106-5940.150" + cell $eq $eq$ls180.v:5940$1465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5940$1465_Y + end + attribute \src "ls180.v:5942.103-5942.147" + cell $eq $eq$ls180.v:5942$1468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5942$1468_Y + end + attribute \src "ls180.v:5943.106-5943.150" + cell $eq $eq$ls180.v:5943$1472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5943$1472_Y + end + attribute \src "ls180.v:5945.103-5945.147" + cell $eq $eq$ls180.v:5945$1475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5945$1475_Y + end + attribute \src "ls180.v:5946.106-5946.150" + cell $eq $eq$ls180.v:5946$1479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5946$1479_Y + end + attribute \src "ls180.v:5948.94-5948.138" + cell $eq $eq$ls180.v:5948$1482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5948$1482_Y + end + attribute \src "ls180.v:5949.97-5949.141" + cell $eq $eq$ls180.v:5949$1486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5949$1486_Y + end + attribute \src "ls180.v:5951.105-5951.149" + cell $eq $eq$ls180.v:5951$1489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:5951$1489_Y + end + attribute \src "ls180.v:5952.108-5952.152" + cell $eq $eq$ls180.v:5952$1493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:5952$1493_Y + end + attribute \src "ls180.v:5954.105-5954.150" + cell $eq $eq$ls180.v:5954$1496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:5954$1496_Y + end + attribute \src "ls180.v:5955.108-5955.153" + cell $eq $eq$ls180.v:5955$1500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:5955$1500_Y + end + attribute \src "ls180.v:5957.105-5957.150" + cell $eq $eq$ls180.v:5957$1503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:5957$1503_Y + end + attribute \src "ls180.v:5958.108-5958.153" + cell $eq $eq$ls180.v:5958$1507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:5958$1507_Y + end + attribute \src "ls180.v:5960.105-5960.150" + cell $eq $eq$ls180.v:5960$1510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:5960$1510_Y + end + attribute \src "ls180.v:5961.108-5961.153" + cell $eq $eq$ls180.v:5961$1514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:5961$1514_Y + end + attribute \src "ls180.v:5963.105-5963.150" + cell $eq $eq$ls180.v:5963$1517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:5963$1517_Y + end + attribute \src "ls180.v:5964.108-5964.153" + cell $eq $eq$ls180.v:5964$1521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:5964$1521_Y + end + attribute \src "ls180.v:5966.105-5966.150" + cell $eq $eq$ls180.v:5966$1524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:5966$1524_Y + end + attribute \src "ls180.v:5967.108-5967.153" + cell $eq $eq$ls180.v:5967$1528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:5967$1528_Y + end + attribute \src "ls180.v:5969.104-5969.149" + cell $eq $eq$ls180.v:5969$1531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:5969$1531_Y + end + attribute \src "ls180.v:5970.107-5970.152" + cell $eq $eq$ls180.v:5970$1535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:5970$1535_Y + end + attribute \src "ls180.v:5972.104-5972.149" + cell $eq $eq$ls180.v:5972$1538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:5972$1538_Y + end + attribute \src "ls180.v:5973.107-5973.152" + cell $eq $eq$ls180.v:5973$1542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:5973$1542_Y + end + attribute \src "ls180.v:5975.104-5975.149" + cell $eq $eq$ls180.v:5975$1545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:5975$1545_Y + end + attribute \src "ls180.v:5976.107-5976.152" + cell $eq $eq$ls180.v:5976$1549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:5976$1549_Y + end + attribute \src "ls180.v:5978.104-5978.149" + cell $eq $eq$ls180.v:5978$1552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:5978$1552_Y + end + attribute \src "ls180.v:5979.107-5979.152" + cell $eq $eq$ls180.v:5979$1556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:5979$1556_Y + end + attribute \src "ls180.v:5981.104-5981.149" + cell $eq $eq$ls180.v:5981$1559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10011 + connect \Y $eq$ls180.v:5981$1559_Y + end + attribute \src "ls180.v:5982.107-5982.152" + cell $eq $eq$ls180.v:5982$1563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10011 + connect \Y $eq$ls180.v:5982$1563_Y + end + attribute \src "ls180.v:5984.104-5984.149" + cell $eq $eq$ls180.v:5984$1566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10100 + connect \Y $eq$ls180.v:5984$1566_Y + end + attribute \src "ls180.v:5985.107-5985.152" + cell $eq $eq$ls180.v:5985$1570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10100 + connect \Y $eq$ls180.v:5985$1570_Y + end + attribute \src "ls180.v:5987.104-5987.149" + cell $eq $eq$ls180.v:5987$1573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10101 + connect \Y $eq$ls180.v:5987$1573_Y + end + attribute \src "ls180.v:5988.107-5988.152" + cell $eq $eq$ls180.v:5988$1577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10101 + connect \Y $eq$ls180.v:5988$1577_Y + end + attribute \src "ls180.v:5990.104-5990.149" + cell $eq $eq$ls180.v:5990$1580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10110 + connect \Y $eq$ls180.v:5990$1580_Y + end + attribute \src "ls180.v:5991.107-5991.152" + cell $eq $eq$ls180.v:5991$1584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10110 + connect \Y $eq$ls180.v:5991$1584_Y + end + attribute \src "ls180.v:5993.104-5993.149" + cell $eq $eq$ls180.v:5993$1587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10111 + connect \Y $eq$ls180.v:5993$1587_Y + end + attribute \src "ls180.v:5994.107-5994.152" + cell $eq $eq$ls180.v:5994$1591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10111 + connect \Y $eq$ls180.v:5994$1591_Y + end + attribute \src "ls180.v:5996.104-5996.149" + cell $eq $eq$ls180.v:5996$1594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11000 + connect \Y $eq$ls180.v:5996$1594_Y + end + attribute \src "ls180.v:5997.107-5997.152" + cell $eq $eq$ls180.v:5997$1598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11000 + connect \Y $eq$ls180.v:5997$1598_Y + end + attribute \src "ls180.v:5999.100-5999.145" + cell $eq $eq$ls180.v:5999$1601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11001 + connect \Y $eq$ls180.v:5999$1601_Y + end + attribute \src "ls180.v:6000.103-6000.148" + cell $eq $eq$ls180.v:6000$1605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11001 + connect \Y $eq$ls180.v:6000$1605_Y + end + attribute \src "ls180.v:6002.101-6002.146" + cell $eq $eq$ls180.v:6002$1608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11010 + connect \Y $eq$ls180.v:6002$1608_Y + end + attribute \src "ls180.v:6003.104-6003.149" + cell $eq $eq$ls180.v:6003$1612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11010 + connect \Y $eq$ls180.v:6003$1612_Y + end + attribute \src "ls180.v:6005.104-6005.149" + cell $eq $eq$ls180.v:6005$1615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11011 + connect \Y $eq$ls180.v:6005$1615_Y + end + attribute \src "ls180.v:6006.107-6006.152" + cell $eq $eq$ls180.v:6006$1619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11011 + connect \Y $eq$ls180.v:6006$1619_Y + end + attribute \src "ls180.v:6008.104-6008.149" + cell $eq $eq$ls180.v:6008$1622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11100 + connect \Y $eq$ls180.v:6008$1622_Y + end + attribute \src "ls180.v:6009.107-6009.152" + cell $eq $eq$ls180.v:6009$1626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11100 + connect \Y $eq$ls180.v:6009$1626_Y + end + attribute \src "ls180.v:6011.103-6011.148" + cell $eq $eq$ls180.v:6011$1629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11101 + connect \Y $eq$ls180.v:6011$1629_Y + end + attribute \src "ls180.v:6012.106-6012.151" + cell $eq $eq$ls180.v:6012$1633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11101 + connect \Y $eq$ls180.v:6012$1633_Y + end + attribute \src "ls180.v:6014.103-6014.148" + cell $eq $eq$ls180.v:6014$1636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11110 + connect \Y $eq$ls180.v:6014$1636_Y + end + attribute \src "ls180.v:6015.106-6015.151" + cell $eq $eq$ls180.v:6015$1640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11110 + connect \Y $eq$ls180.v:6015$1640_Y + end + attribute \src "ls180.v:6017.103-6017.148" + cell $eq $eq$ls180.v:6017$1643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11111 + connect \Y $eq$ls180.v:6017$1643_Y + end + attribute \src "ls180.v:6018.106-6018.151" + cell $eq $eq$ls180.v:6018$1647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11111 + connect \Y $eq$ls180.v:6018$1647_Y + end + attribute \src "ls180.v:6020.103-6020.148" + cell $eq $eq$ls180.v:6020$1650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 6'100000 + connect \Y $eq$ls180.v:6020$1650_Y + end + attribute \src "ls180.v:6021.106-6021.151" + cell $eq $eq$ls180.v:6021$1654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 6'100000 + connect \Y $eq$ls180.v:6021$1654_Y + end + attribute \src "ls180.v:6057.32-6057.78" + cell $eq $eq$ls180.v:6057$1656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [13:9] + connect \B 4'1101 + connect \Y $eq$ls180.v:6057$1656_Y + end + attribute \src "ls180.v:6059.100-6059.144" + cell $eq $eq$ls180.v:6059$1658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6059$1658_Y + end + attribute \src "ls180.v:6060.103-6060.147" + cell $eq $eq$ls180.v:6060$1662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6060$1662_Y + end + attribute \src "ls180.v:6062.100-6062.144" + cell $eq $eq$ls180.v:6062$1665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6062$1665_Y + end + attribute \src "ls180.v:6063.103-6063.147" + cell $eq $eq$ls180.v:6063$1669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6063$1669_Y + end + attribute \src "ls180.v:6065.100-6065.144" + cell $eq $eq$ls180.v:6065$1672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6065$1672_Y + end + attribute \src "ls180.v:6066.103-6066.147" + cell $eq $eq$ls180.v:6066$1676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6066$1676_Y + end + attribute \src "ls180.v:6068.100-6068.144" + cell $eq $eq$ls180.v:6068$1679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6068$1679_Y + end + attribute \src "ls180.v:6069.103-6069.147" + cell $eq $eq$ls180.v:6069$1683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6069$1683_Y + end + attribute \src "ls180.v:6071.100-6071.144" + cell $eq $eq$ls180.v:6071$1686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6071$1686_Y + end + attribute \src "ls180.v:6072.103-6072.147" + cell $eq $eq$ls180.v:6072$1690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6072$1690_Y + end + attribute \src "ls180.v:6074.100-6074.144" + cell $eq $eq$ls180.v:6074$1693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6074$1693_Y + end + attribute \src "ls180.v:6075.103-6075.147" + cell $eq $eq$ls180.v:6075$1697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6075$1697_Y + end + attribute \src "ls180.v:6077.100-6077.144" + cell $eq $eq$ls180.v:6077$1700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6077$1700_Y + end + attribute \src "ls180.v:6078.103-6078.147" + cell $eq $eq$ls180.v:6078$1704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6078$1704_Y + end + attribute \src "ls180.v:6080.100-6080.144" + cell $eq $eq$ls180.v:6080$1707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6080$1707_Y + end + attribute \src "ls180.v:6081.103-6081.147" + cell $eq $eq$ls180.v:6081$1711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6081$1711_Y + end + attribute \src "ls180.v:6083.102-6083.146" + cell $eq $eq$ls180.v:6083$1714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6083$1714_Y + end + attribute \src "ls180.v:6084.105-6084.149" + cell $eq $eq$ls180.v:6084$1718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6084$1718_Y + end + attribute \src "ls180.v:6086.102-6086.146" + cell $eq $eq$ls180.v:6086$1721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6086$1721_Y + end + attribute \src "ls180.v:6087.105-6087.149" + cell $eq $eq$ls180.v:6087$1725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6087$1725_Y + end + attribute \src "ls180.v:6089.102-6089.147" + cell $eq $eq$ls180.v:6089$1728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6089$1728_Y + end + attribute \src "ls180.v:6090.105-6090.150" + cell $eq $eq$ls180.v:6090$1732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6090$1732_Y + end + attribute \src "ls180.v:6092.102-6092.147" + cell $eq $eq$ls180.v:6092$1735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6092$1735_Y + end + attribute \src "ls180.v:6093.105-6093.150" + cell $eq $eq$ls180.v:6093$1739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6093$1739_Y + end + attribute \src "ls180.v:6095.102-6095.147" + cell $eq $eq$ls180.v:6095$1742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6095$1742_Y + end + attribute \src "ls180.v:6096.105-6096.150" + cell $eq $eq$ls180.v:6096$1746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6096$1746_Y + end + attribute \src "ls180.v:6098.99-6098.144" + cell $eq $eq$ls180.v:6098$1749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6098$1749_Y + end + attribute \src "ls180.v:6099.102-6099.147" + cell $eq $eq$ls180.v:6099$1753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6099$1753_Y + end + attribute \src "ls180.v:6101.100-6101.145" + cell $eq $eq$ls180.v:6101$1756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6101$1756_Y + end + attribute \src "ls180.v:6102.103-6102.148" + cell $eq $eq$ls180.v:6102$1760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6102$1760_Y + end + attribute \src "ls180.v:6104.102-6104.147" + cell $eq $eq$ls180.v:6104$1763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6104$1763_Y + end + attribute \src "ls180.v:6105.105-6105.150" + cell $eq $eq$ls180.v:6105$1767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6105$1767_Y + end + attribute \src "ls180.v:6107.102-6107.147" + cell $eq $eq$ls180.v:6107$1770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6107$1770_Y + end + attribute \src "ls180.v:6108.105-6108.150" + cell $eq $eq$ls180.v:6108$1774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6108$1774_Y + end + attribute \src "ls180.v:6110.102-6110.147" + cell $eq $eq$ls180.v:6110$1777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6110$1777_Y + end + attribute \src "ls180.v:6111.105-6111.150" + cell $eq $eq$ls180.v:6111$1781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6111$1781_Y + end + attribute \src "ls180.v:6113.102-6113.147" + cell $eq $eq$ls180.v:6113$1784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6113$1784_Y + end + attribute \src "ls180.v:6114.105-6114.150" + cell $eq $eq$ls180.v:6114$1788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6114$1788_Y + end + attribute \src "ls180.v:6136.32-6136.78" + cell $eq $eq$ls180.v:6136$1790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [13:9] + connect \B 4'1010 + connect \Y $eq$ls180.v:6136$1790_Y + end + attribute \src "ls180.v:6138.102-6138.146" + cell $eq $eq$ls180.v:6138$1792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6138$1792_Y + end + attribute \src "ls180.v:6139.105-6139.149" + cell $eq $eq$ls180.v:6139$1796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6139$1796_Y + end + attribute \src "ls180.v:6141.107-6141.151" + cell $eq $eq$ls180.v:6141$1799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6141$1799_Y + end + attribute \src "ls180.v:6142.110-6142.154" + cell $eq $eq$ls180.v:6142$1803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6142$1803_Y + end + attribute \src "ls180.v:6144.107-6144.151" + cell $eq $eq$ls180.v:6144$1806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6144$1806_Y + end + attribute \src "ls180.v:6145.110-6145.154" + cell $eq $eq$ls180.v:6145$1810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6145$1810_Y + end + attribute \src "ls180.v:6147.100-6147.144" + cell $eq $eq$ls180.v:6147$1813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6147$1813_Y + end + attribute \src "ls180.v:6148.103-6148.147" + cell $eq $eq$ls180.v:6148$1817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6148$1817_Y + end + attribute \src "ls180.v:6153.32-6153.77" + cell $eq $eq$ls180.v:6153$1819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [13:9] + connect \B 2'11 + connect \Y $eq$ls180.v:6153$1819_Y + end + attribute \src "ls180.v:6155.104-6155.148" + cell $eq $eq$ls180.v:6155$1821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6155$1821_Y + end + attribute \src "ls180.v:6156.107-6156.151" + cell $eq $eq$ls180.v:6156$1825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6156$1825_Y + end + attribute \src "ls180.v:6158.108-6158.152" + cell $eq $eq$ls180.v:6158$1828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6158$1828_Y + end + attribute \src "ls180.v:6159.111-6159.155" + cell $eq $eq$ls180.v:6159$1832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6159$1832_Y + end + attribute \src "ls180.v:6161.98-6161.142" + cell $eq $eq$ls180.v:6161$1835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6161$1835_Y + end + attribute \src "ls180.v:6162.101-6162.145" + cell $eq $eq$ls180.v:6162$1839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6162$1839_Y + end + attribute \src "ls180.v:6164.108-6164.152" + cell $eq $eq$ls180.v:6164$1842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6164$1842_Y + end + attribute \src "ls180.v:6165.111-6165.155" + cell $eq $eq$ls180.v:6165$1846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6165$1846_Y + end + attribute \src "ls180.v:6167.108-6167.152" + cell $eq $eq$ls180.v:6167$1849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6167$1849_Y + end + attribute \src "ls180.v:6168.111-6168.155" + cell $eq $eq$ls180.v:6168$1853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6168$1853_Y + end + attribute \src "ls180.v:6170.109-6170.153" + cell $eq $eq$ls180.v:6170$1856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6170$1856_Y + end + attribute \src "ls180.v:6171.112-6171.156" + cell $eq $eq$ls180.v:6171$1860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6171$1860_Y + end + attribute \src "ls180.v:6173.107-6173.151" + cell $eq $eq$ls180.v:6173$1863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6173$1863_Y + end + attribute \src "ls180.v:6174.110-6174.154" + cell $eq $eq$ls180.v:6174$1867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6174$1867_Y + end + attribute \src "ls180.v:6176.107-6176.151" + cell $eq $eq$ls180.v:6176$1870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6176$1870_Y + end + attribute \src "ls180.v:6177.110-6177.154" + cell $eq $eq$ls180.v:6177$1874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6177$1874_Y + end + attribute \src "ls180.v:6179.107-6179.151" + cell $eq $eq$ls180.v:6179$1877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6179$1877_Y + end + attribute \src "ls180.v:6180.110-6180.154" + cell $eq $eq$ls180.v:6180$1881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6180$1881_Y + end + attribute \src "ls180.v:6182.107-6182.151" + cell $eq $eq$ls180.v:6182$1884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6182$1884_Y + end + attribute \src "ls180.v:6183.110-6183.154" + cell $eq $eq$ls180.v:6183$1888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6183$1888_Y + end + attribute \src "ls180.v:6198.32-6198.77" + cell $eq $eq$ls180.v:6198$1890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [13:9] + connect \B 3'111 + connect \Y $eq$ls180.v:6198$1890_Y + end + attribute \src "ls180.v:6200.99-6200.143" + cell $eq $eq$ls180.v:6200$1892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6200$1892_Y + end + attribute \src "ls180.v:6201.102-6201.146" + cell $eq $eq$ls180.v:6201$1896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6201$1896_Y + end + attribute \src "ls180.v:6203.99-6203.143" + cell $eq $eq$ls180.v:6203$1899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6203$1899_Y + end + attribute \src "ls180.v:6204.102-6204.146" + cell $eq $eq$ls180.v:6204$1903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6204$1903_Y + end + attribute \src "ls180.v:6206.97-6206.141" + cell $eq $eq$ls180.v:6206$1906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6206$1906_Y + end + attribute \src "ls180.v:6207.100-6207.144" + cell $eq $eq$ls180.v:6207$1910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6207$1910_Y + end + attribute \src "ls180.v:6209.96-6209.140" + cell $eq $eq$ls180.v:6209$1913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6209$1913_Y + end + attribute \src "ls180.v:6210.99-6210.143" + cell $eq $eq$ls180.v:6210$1917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6210$1917_Y + end + attribute \src "ls180.v:6212.95-6212.139" + cell $eq $eq$ls180.v:6212$1920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6212$1920_Y + end + attribute \src "ls180.v:6213.98-6213.142" + cell $eq $eq$ls180.v:6213$1924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6213$1924_Y + end + attribute \src "ls180.v:6215.94-6215.138" + cell $eq $eq$ls180.v:6215$1927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6215$1927_Y + end + attribute \src "ls180.v:6216.97-6216.141" + cell $eq $eq$ls180.v:6216$1931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6216$1931_Y + end + attribute \src "ls180.v:6218.100-6218.144" + cell $eq $eq$ls180.v:6218$1934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6218$1934_Y + end + attribute \src "ls180.v:6219.103-6219.147" + cell $eq $eq$ls180.v:6219$1938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6219$1938_Y + end + attribute \src "ls180.v:6238.33-6238.80" + cell $eq $eq$ls180.v:6238$1941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [13:9] + connect \B 4'1110 + connect \Y $eq$ls180.v:6238$1941_Y + end + attribute \src "ls180.v:6240.102-6240.147" + cell $eq $eq$ls180.v:6240$1943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6240$1943_Y + end + attribute \src "ls180.v:6241.105-6241.150" + cell $eq $eq$ls180.v:6241$1947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6241$1947_Y + end + attribute \src "ls180.v:6243.102-6243.147" + cell $eq $eq$ls180.v:6243$1950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6243$1950_Y + end + attribute \src "ls180.v:6244.105-6244.150" + cell $eq $eq$ls180.v:6244$1954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6244$1954_Y + end + attribute \src "ls180.v:6246.100-6246.145" + cell $eq $eq$ls180.v:6246$1957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6246$1957_Y + end + attribute \src "ls180.v:6247.103-6247.148" + cell $eq $eq$ls180.v:6247$1961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6247$1961_Y + end + attribute \src "ls180.v:6249.99-6249.144" + cell $eq $eq$ls180.v:6249$1964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6249$1964_Y + end + attribute \src "ls180.v:6250.102-6250.147" + cell $eq $eq$ls180.v:6250$1968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6250$1968_Y + end + attribute \src "ls180.v:6252.98-6252.143" + cell $eq $eq$ls180.v:6252$1971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6252$1971_Y + end + attribute \src "ls180.v:6253.101-6253.146" + cell $eq $eq$ls180.v:6253$1975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6253$1975_Y + end + attribute \src "ls180.v:6255.97-6255.142" + cell $eq $eq$ls180.v:6255$1978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6255$1978_Y + end + attribute \src "ls180.v:6256.100-6256.145" + cell $eq $eq$ls180.v:6256$1982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6256$1982_Y + end + attribute \src "ls180.v:6258.103-6258.148" + cell $eq $eq$ls180.v:6258$1985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6258$1985_Y + end + attribute \src "ls180.v:6259.106-6259.151" + cell $eq $eq$ls180.v:6259$1989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6259$1989_Y + end + attribute \src "ls180.v:6261.106-6261.151" + cell $eq $eq$ls180.v:6261$1992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6261$1992_Y + end + attribute \src "ls180.v:6262.109-6262.154" + cell $eq $eq$ls180.v:6262$1996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6262$1996_Y + end + attribute \src "ls180.v:6264.106-6264.151" + cell $eq $eq$ls180.v:6264$1999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6264$1999_Y + end + attribute \src "ls180.v:6265.109-6265.154" + cell $eq $eq$ls180.v:6265$2003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6265$2003_Y + end + attribute \src "ls180.v:6286.33-6286.79" + cell $eq $eq$ls180.v:6286$2006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [13:9] + connect \B 2'10 + connect \Y $eq$ls180.v:6286$2006_Y + end + attribute \src "ls180.v:6288.99-6288.144" + cell $eq $eq$ls180.v:6288$2008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6288$2008_Y + end + attribute \src "ls180.v:6289.102-6289.147" + cell $eq $eq$ls180.v:6289$2012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6289$2012_Y + end + attribute \src "ls180.v:6291.99-6291.144" + cell $eq $eq$ls180.v:6291$2015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6291$2015_Y + end + attribute \src "ls180.v:6292.102-6292.147" + cell $eq $eq$ls180.v:6292$2019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6292$2019_Y + end + attribute \src "ls180.v:6294.99-6294.144" + cell $eq $eq$ls180.v:6294$2022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6294$2022_Y + end + attribute \src "ls180.v:6295.102-6295.147" + cell $eq $eq$ls180.v:6295$2026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6295$2026_Y + end + attribute \src "ls180.v:6297.99-6297.144" + cell $eq $eq$ls180.v:6297$2029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6297$2029_Y + end + attribute \src "ls180.v:6298.102-6298.147" + cell $eq $eq$ls180.v:6298$2033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6298$2033_Y + end + attribute \src "ls180.v:6300.101-6300.146" + cell $eq $eq$ls180.v:6300$2036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6300$2036_Y + end + attribute \src "ls180.v:6301.104-6301.149" + cell $eq $eq$ls180.v:6301$2040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6301$2040_Y + end + attribute \src "ls180.v:6303.101-6303.146" + cell $eq $eq$ls180.v:6303$2043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6303$2043_Y + end + attribute \src "ls180.v:6304.104-6304.149" + cell $eq $eq$ls180.v:6304$2047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6304$2047_Y + end + attribute \src "ls180.v:6306.101-6306.146" + cell $eq $eq$ls180.v:6306$2050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6306$2050_Y + end + attribute \src "ls180.v:6307.104-6307.149" + cell $eq $eq$ls180.v:6307$2054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6307$2054_Y + end + attribute \src "ls180.v:6309.101-6309.146" + cell $eq $eq$ls180.v:6309$2057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6309$2057_Y + end + attribute \src "ls180.v:6310.104-6310.149" + cell $eq $eq$ls180.v:6310$2061 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6310$2061_Y + end + attribute \src "ls180.v:6312.97-6312.142" + cell $eq $eq$ls180.v:6312$2064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6312$2064_Y + end + attribute \src "ls180.v:6313.100-6313.145" + cell $eq $eq$ls180.v:6313$2068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6313$2068_Y + end + attribute \src "ls180.v:6315.107-6315.152" + cell $eq $eq$ls180.v:6315$2071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6315$2071_Y + end + attribute \src "ls180.v:6316.110-6316.155" + cell $eq $eq$ls180.v:6316$2075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6316$2075_Y + end + attribute \src "ls180.v:6318.100-6318.146" + cell $eq $eq$ls180.v:6318$2078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6318$2078_Y + end + attribute \src "ls180.v:6319.103-6319.149" + cell $eq $eq$ls180.v:6319$2082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6319$2082_Y + end + attribute \src "ls180.v:6321.100-6321.146" + cell $eq $eq$ls180.v:6321$2085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6321$2085_Y + end + attribute \src "ls180.v:6322.103-6322.149" + cell $eq $eq$ls180.v:6322$2089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6322$2089_Y + end + attribute \src "ls180.v:6324.100-6324.146" + cell $eq $eq$ls180.v:6324$2092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6324$2092_Y + end + attribute \src "ls180.v:6325.103-6325.149" + cell $eq $eq$ls180.v:6325$2096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6325$2096_Y + end + attribute \src "ls180.v:6327.100-6327.146" + cell $eq $eq$ls180.v:6327$2099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6327$2099_Y + end + attribute \src "ls180.v:6328.103-6328.149" + cell $eq $eq$ls180.v:6328$2103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6328$2103_Y + end + attribute \src "ls180.v:6330.112-6330.158" + cell $eq $eq$ls180.v:6330$2106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6330$2106_Y + end + attribute \src "ls180.v:6331.115-6331.161" + cell $eq $eq$ls180.v:6331$2110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6331$2110_Y + end + attribute \src "ls180.v:6333.113-6333.159" + cell $eq $eq$ls180.v:6333$2113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6333$2113_Y + end + attribute \src "ls180.v:6334.116-6334.162" + cell $eq $eq$ls180.v:6334$2117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6334$2117_Y + end + attribute \src "ls180.v:6336.104-6336.150" + cell $eq $eq$ls180.v:6336$2120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6336$2120_Y + end + attribute \src "ls180.v:6337.107-6337.153" + cell $eq $eq$ls180.v:6337$2124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6337$2124_Y + end + attribute \src "ls180.v:6354.33-6354.79" + cell $eq $eq$ls180.v:6354$2126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [13:9] + connect \B 3'101 + connect \Y $eq$ls180.v:6354$2126_Y + end + attribute \src "ls180.v:6356.90-6356.135" + cell $eq $eq$ls180.v:6356$2128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6356$2128_Y + end + attribute \src "ls180.v:6357.93-6357.138" + cell $eq $eq$ls180.v:6357$2132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6357$2132_Y + end + attribute \src "ls180.v:6359.100-6359.145" + cell $eq $eq$ls180.v:6359$2135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6359$2135_Y + end + attribute \src "ls180.v:6360.103-6360.148" + cell $eq $eq$ls180.v:6360$2139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6360$2139_Y + end + attribute \src "ls180.v:6362.101-6362.146" + cell $eq $eq$ls180.v:6362$2142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6362$2142_Y + end + attribute \src "ls180.v:6363.104-6363.149" + cell $eq $eq$ls180.v:6363$2146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6363$2146_Y + end + attribute \src "ls180.v:6365.105-6365.150" + cell $eq $eq$ls180.v:6365$2149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6365$2149_Y + end + attribute \src "ls180.v:6366.108-6366.153" + cell $eq $eq$ls180.v:6366$2153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6366$2153_Y + end + attribute \src "ls180.v:6368.106-6368.151" + cell $eq $eq$ls180.v:6368$2156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6368$2156_Y + end + attribute \src "ls180.v:6369.109-6369.154" + cell $eq $eq$ls180.v:6369$2160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6369$2160_Y + end + attribute \src "ls180.v:6371.104-6371.149" + cell $eq $eq$ls180.v:6371$2163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6371$2163_Y + end + attribute \src "ls180.v:6372.107-6372.152" + cell $eq $eq$ls180.v:6372$2167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6372$2167_Y + end + attribute \src "ls180.v:6374.101-6374.146" + cell $eq $eq$ls180.v:6374$2170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6374$2170_Y + end + attribute \src "ls180.v:6375.104-6375.149" + cell $eq $eq$ls180.v:6375$2174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6375$2174_Y + end + attribute \src "ls180.v:6377.100-6377.145" + cell $eq $eq$ls180.v:6377$2177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6377$2177_Y + end + attribute \src "ls180.v:6378.103-6378.148" + cell $eq $eq$ls180.v:6378$2181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6378$2181_Y + end + attribute \src "ls180.v:6388.33-6388.79" + cell $eq $eq$ls180.v:6388$2183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [13:9] + connect \B 3'100 + connect \Y $eq$ls180.v:6388$2183_Y + end + attribute \src "ls180.v:6390.106-6390.151" + cell $eq $eq$ls180.v:6390$2185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6390$2185_Y + end + attribute \src "ls180.v:6391.109-6391.154" + cell $eq $eq$ls180.v:6391$2189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6391$2189_Y + end + attribute \src "ls180.v:6393.106-6393.151" + cell $eq $eq$ls180.v:6393$2192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6393$2192_Y + end + attribute \src "ls180.v:6394.109-6394.154" + cell $eq $eq$ls180.v:6394$2196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6394$2196_Y + end + attribute \src "ls180.v:6396.106-6396.151" + cell $eq $eq$ls180.v:6396$2199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6396$2199_Y + end + attribute \src "ls180.v:6397.109-6397.154" + cell $eq $eq$ls180.v:6397$2203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6397$2203_Y + end + attribute \src "ls180.v:6399.106-6399.151" + cell $eq $eq$ls180.v:6399$2206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6399$2206_Y + end + attribute \src "ls180.v:6400.109-6400.154" + cell $eq $eq$ls180.v:6400$2210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6400$2210_Y + end + attribute \src "ls180.v:6778.41-6778.81" + cell $eq $eq$ls180.v:6778$2246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:6778$2246_Y + end + attribute \src "ls180.v:6778.144-6778.177" + cell $eq $eq$ls180.v:6778$2247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6778$2247_Y + end + attribute \src "ls180.v:6778.219-6778.252" + cell $eq $eq$ls180.v:6778$2250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6778$2250_Y + end + attribute \src "ls180.v:6778.294-6778.327" + cell $eq $eq$ls180.v:6778$2253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6778$2253_Y + end + attribute \src "ls180.v:6802.41-6802.81" + cell $eq $eq$ls180.v:6802$2262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:6802$2262_Y + end + attribute \src "ls180.v:6802.144-6802.177" + cell $eq $eq$ls180.v:6802$2263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6802$2263_Y + end + attribute \src "ls180.v:6802.219-6802.252" + cell $eq $eq$ls180.v:6802$2266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6802$2266_Y + end + attribute \src "ls180.v:6802.294-6802.327" + cell $eq $eq$ls180.v:6802$2269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6802$2269_Y + end + attribute \src "ls180.v:6826.41-6826.81" + cell $eq $eq$ls180.v:6826$2278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:6826$2278_Y + end + attribute \src "ls180.v:6826.144-6826.177" + cell $eq $eq$ls180.v:6826$2279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6826$2279_Y + end + attribute \src "ls180.v:6826.219-6826.252" + cell $eq $eq$ls180.v:6826$2282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6826$2282_Y + end + attribute \src "ls180.v:6826.294-6826.327" + cell $eq $eq$ls180.v:6826$2285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6826$2285_Y + end + attribute \src "ls180.v:6850.41-6850.81" + cell $eq $eq$ls180.v:6850$2294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:6850$2294_Y + end + attribute \src "ls180.v:6850.144-6850.177" + cell $eq $eq$ls180.v:6850$2295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6850$2295_Y + end + attribute \src "ls180.v:6850.219-6850.252" + cell $eq $eq$ls180.v:6850$2298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6850$2298_Y + end + attribute \src "ls180.v:6850.294-6850.327" + cell $eq $eq$ls180.v:6850$2301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6850$2301_Y + end + attribute \src "ls180.v:7446.8-7446.38" + cell $eq $eq$ls180.v:7446$2411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_value + connect \B 1'0 + connect \Y $eq$ls180.v:7446$2411_Y + end + attribute \src "ls180.v:7479.8-7479.42" + cell $eq $eq$ls180.v:7479$2419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_postponer_count + connect \B 1'0 + connect \Y $eq$ls180.v:7479$2419_Y + end + attribute \src "ls180.v:7499.38-7499.74" + cell $eq $eq$ls180.v:7499$2422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 1'0 + connect \Y $eq$ls180.v:7499$2422_Y + end + attribute \src "ls180.v:7506.7-7506.43" + cell $eq $eq$ls180.v:7506$2424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 2'10 + connect \Y $eq$ls180.v:7506$2424_Y + end + attribute \src "ls180.v:7513.7-7513.43" + cell $eq $eq$ls180.v:7513$2425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 4'1000 + connect \Y $eq$ls180.v:7513$2425_Y + end + attribute \src "ls180.v:7521.7-7521.43" + cell $eq $eq$ls180.v:7521$2426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 4'1000 + connect \Y $eq$ls180.v:7521$2426_Y + end + attribute \src "ls180.v:7573.9-7573.54" + cell $eq $eq$ls180.v:7573$2444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7573$2444_Y + end + attribute \src "ls180.v:7619.9-7619.54" + cell $eq $eq$ls180.v:7619$2460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7619$2460_Y + end + attribute \src "ls180.v:7665.9-7665.54" + cell $eq $eq$ls180.v:7665$2476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7665$2476_Y + end + attribute \src "ls180.v:7711.9-7711.54" + cell $eq $eq$ls180.v:7711$2492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7711$2492_Y + end + attribute \src "ls180.v:7861.9-7861.41" + cell $eq $eq$ls180.v:7861$2504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7861$2504_Y + end + attribute \src "ls180.v:7876.9-7876.41" + cell $eq $eq$ls180.v:7876$2507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_twtrcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7876$2507_Y + end + attribute \src "ls180.v:7882.49-7882.82" + cell $eq $eq$ls180.v:7882$2508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7882$2508_Y + end + attribute \src "ls180.v:7882.131-7882.164" + cell $eq $eq$ls180.v:7882$2511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7882$2511_Y + end + attribute \src "ls180.v:7882.213-7882.246" + cell $eq $eq$ls180.v:7882$2514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7882$2514_Y + end + attribute \src "ls180.v:7882.295-7882.328" + cell $eq $eq$ls180.v:7882$2517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7882$2517_Y + end + attribute \src "ls180.v:7883.50-7883.83" + cell $eq $eq$ls180.v:7883$2520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7883$2520_Y + end + attribute \src "ls180.v:7883.132-7883.165" + cell $eq $eq$ls180.v:7883$2523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7883$2523_Y + end + attribute \src "ls180.v:7883.214-7883.247" + cell $eq $eq$ls180.v:7883$2526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7883$2526_Y + end + attribute \src "ls180.v:7883.296-7883.329" + cell $eq $eq$ls180.v:7883$2529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7883$2529_Y + end + attribute \src "ls180.v:7918.9-7918.33" + cell $eq $eq$ls180.v:7918$2541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_tx_bitcount + connect \B 4'1000 + connect \Y $eq$ls180.v:7918$2541_Y + end + attribute \src "ls180.v:7921.10-7921.34" + cell $eq $eq$ls180.v:7921$2542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_tx_bitcount + connect \B 4'1001 + connect \Y $eq$ls180.v:7921$2542_Y + end + attribute \src "ls180.v:7947.9-7947.33" + cell $eq $eq$ls180.v:7947$2548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_rx_bitcount + connect \B 1'0 + connect \Y $eq$ls180.v:7947$2548_Y + end + attribute \src "ls180.v:7952.10-7952.34" + cell $eq $eq$ls180.v:7952$2549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_rx_bitcount + connect \B 4'1001 + connect \Y $eq$ls180.v:7952$2549_Y + end + attribute \src "ls180.v:8124.9-8124.53" + cell $eq $eq$ls180.v:8124$2593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_demux + connect \B 3'111 + connect \Y $eq$ls180.v:8124$2593_Y + end + attribute \src "ls180.v:8205.9-8205.54" + cell $eq $eq$ls180.v:8205$2605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_demux + connect \B 3'111 + connect \Y $eq$ls180.v:8205$2605_Y + end + attribute \src "ls180.v:8284.9-8284.55" + cell $eq $eq$ls180.v:8284$2617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_demux + connect \B 1'1 + connect \Y $eq$ls180.v:8284$2617_Y + end + attribute \src "ls180.v:8507.9-8507.49" + cell $eq $eq$ls180.v:8507$2650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_demux + connect \B 2'11 + connect \Y $eq$ls180.v:8507$2650_Y + end + attribute \src "ls180.v:8083.8-8083.54" + cell $ge $ge$ls180.v:8083$2585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm0_counter + connect \B $sub$ls180.v:8083$2584_Y + connect \Y $ge$ls180.v:8083$2585_Y + end + attribute \src "ls180.v:8097.8-8097.54" + cell $ge $ge$ls180.v:8097$2589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm1_counter + connect \B $sub$ls180.v:8097$2588_Y + connect \Y $ge$ls180.v:8097$2589_Y + end + attribute \src "ls180.v:5045.47-5045.83" + cell $gt $gt$ls180.v:5045$907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $gt$ls180.v:5045$907_Y + end + attribute \src "ls180.v:5051.7-5051.43" + cell $lt $lt$ls180.v:5051$910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 4'1000 + connect \Y $lt$ls180.v:5051$910_Y + end + attribute \src "ls180.v:8078.8-8078.43" + cell $lt $lt$ls180.v:8078$2583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm0_counter + connect \B \main_pwm0_width + connect \Y $lt$ls180.v:8078$2583_Y + end + attribute \src "ls180.v:8092.8-8092.43" + cell $lt $lt$ls180.v:8092$2587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm1_counter + connect \B \main_pwm1_width + connect \Y $lt$ls180.v:8092$2587_Y + end + attribute \src "ls180.v:9993.33-9993.36" + cell $memrd $memrd$\mem$ls180.v:9993$2697 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \TRANSPARENT 0 + parameter \WIDTH 32 + connect \ADDR \memadr + connect \CLK 1'x + connect \DATA $memrd$\mem$ls180.v:9993$2697_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10004.12-10004.19" + cell $memrd $memrd$\storage$ls180.v:10004$2702 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage$ls180.v:10004$2702_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10011.68-10011.75" + cell $memrd $memrd$\storage$ls180.v:10011$2704 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage$ls180.v:10011$2704_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10018.14-10018.23" + cell $memrd $memrd$\storage_1$ls180.v:10018$2709 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_1$ls180.v:10018$2709_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10025.68-10025.77" + cell $memrd $memrd$\storage_1$ls180.v:10025$2711 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_1$ls180.v:10025$2711_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10032.14-10032.23" + cell $memrd $memrd$\storage_2$ls180.v:10032$2716 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_2$ls180.v:10032$2716_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10039.68-10039.77" + cell $memrd $memrd$\storage_2$ls180.v:10039$2718 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_2$ls180.v:10039$2718_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10046.14-10046.23" + cell $memrd $memrd$\storage_3$ls180.v:10046$2723 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_3$ls180.v:10046$2723_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10053.68-10053.77" + cell $memrd $memrd$\storage_3$ls180.v:10053$2725 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_3$ls180.v:10053$2725_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10061.14-10061.23" + cell $memrd $memrd$\storage_4$ls180.v:10061$2730 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_tx_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_4$ls180.v:10061$2730_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10066.15-10066.24" + cell $memrd $memrd$\storage_4$ls180.v:10066$2732 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_tx_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_4$ls180.v:10066$2732_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10078.14-10078.23" + cell $memrd $memrd$\storage_5$ls180.v:10078$2737 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_rx_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_5$ls180.v:10078$2737_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10083.15-10083.24" + cell $memrd $memrd$\storage_5$ls180.v:10083$2739 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_rx_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_5$ls180.v:10083$2739_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10094.14-10094.23" + cell $memrd $memrd$\storage_6$ls180.v:10094$2744 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdblock2mem_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_6$ls180.v:10094$2744_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10101.45-10101.54" + cell $memrd $memrd$\storage_6$ls180.v:10101$2746 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdblock2mem_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_6$ls180.v:10101$2746_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10108.14-10108.23" + cell $memrd $memrd$\storage_7$ls180.v:10108$2751 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdmem2block_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_7$ls180.v:10108$2751_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10115.45-10115.54" + cell $memrd $memrd$\storage_7$ls180.v:10115$2753 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdmem2block_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_7$ls180.v:10115$2753_DATA + connect \EN 1'x + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2755 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2755 + parameter \WIDTH 32 + connect \ADDR $memwr$\mem$ls180.v:9983$1_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:9983$1_DATA + connect \EN $memwr$\mem$ls180.v:9983$1_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2756 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2756 + parameter \WIDTH 32 + connect \ADDR $memwr$\mem$ls180.v:9985$2_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:9985$2_DATA + connect \EN $memwr$\mem$ls180.v:9985$2_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2757 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2757 + parameter \WIDTH 32 + connect \ADDR $memwr$\mem$ls180.v:9987$3_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:9987$3_DATA + connect \EN $memwr$\mem$ls180.v:9987$3_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2758 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2758 + parameter \WIDTH 32 + connect \ADDR $memwr$\mem$ls180.v:9989$4_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:9989$4_DATA + connect \EN $memwr$\mem$ls180.v:9989$4_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage$ls180.v:0$2759 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \PRIORITY 2759 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage$ls180.v:10003$5_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage$ls180.v:10003$5_DATA + connect \EN $memwr$\storage$ls180.v:10003$5_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_1$ls180.v:0$2760 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \PRIORITY 2760 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_1$ls180.v:10017$6_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_1$ls180.v:10017$6_DATA + connect \EN $memwr$\storage_1$ls180.v:10017$6_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_2$ls180.v:0$2761 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \PRIORITY 2761 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_2$ls180.v:10031$7_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_2$ls180.v:10031$7_DATA + connect \EN $memwr$\storage_2$ls180.v:10031$7_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_3$ls180.v:0$2762 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \PRIORITY 2762 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_3$ls180.v:10045$8_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_3$ls180.v:10045$8_DATA + connect \EN $memwr$\storage_3$ls180.v:10045$8_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_4$ls180.v:0$2763 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \PRIORITY 2763 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_4$ls180.v:10060$9_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_4$ls180.v:10060$9_DATA + connect \EN $memwr$\storage_4$ls180.v:10060$9_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_5$ls180.v:0$2764 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \PRIORITY 2764 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_5$ls180.v:10077$10_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_5$ls180.v:10077$10_DATA + connect \EN $memwr$\storage_5$ls180.v:10077$10_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_6$ls180.v:0$2765 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \PRIORITY 2765 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_6$ls180.v:10093$11_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_6$ls180.v:10093$11_DATA + connect \EN $memwr$\storage_6$ls180.v:10093$11_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_7$ls180.v:0$2766 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \PRIORITY 2766 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_7$ls180.v:10107$12_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_7$ls180.v:10107$12_DATA + connect \EN $memwr$\storage_7$ls180.v:10107$12_EN + end + attribute \src "ls180.v:2917.41-2917.71" + cell $ne $ne$ls180.v:2917$60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_value + connect \B 1'0 + connect \Y $ne$ls180.v:2917$60_Y + end + attribute \src "ls180.v:3083.70-3083.104" + cell $ne $ne$ls180.v:3083$75 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $ne$ls180.v:3083$75_Y + end + attribute \src "ls180.v:3144.8-3144.142" + cell $ne $ne$ls180.v:3144$94 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3144$94_Y + end + attribute \src "ls180.v:3176.75-3176.133" + cell $ne $ne$ls180.v:3176$101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3176$101_Y + end + attribute \src "ls180.v:3177.75-3177.133" + cell $ne $ne$ls180.v:3177$102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3177$102_Y + end + attribute \src "ls180.v:3301.8-3301.142" + cell $ne $ne$ls180.v:3301$124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3301$124_Y + end + attribute \src "ls180.v:3333.75-3333.133" + cell $ne $ne$ls180.v:3333$131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3333$131_Y + end + attribute \src "ls180.v:3334.75-3334.133" + cell $ne $ne$ls180.v:3334$132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3334$132_Y + end + attribute \src "ls180.v:3458.8-3458.142" + cell $ne $ne$ls180.v:3458$154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3458$154_Y + end + attribute \src "ls180.v:3490.75-3490.133" + cell $ne $ne$ls180.v:3490$161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3490$161_Y + end + attribute \src "ls180.v:3491.75-3491.133" + cell $ne $ne$ls180.v:3491$162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3491$162_Y + end + attribute \src "ls180.v:3615.8-3615.142" + cell $ne $ne$ls180.v:3615$184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3615$184_Y + end + attribute \src "ls180.v:3647.75-3647.133" + cell $ne $ne$ls180.v:3647$191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3647$191_Y + end + attribute \src "ls180.v:3648.75-3648.133" + cell $ne $ne$ls180.v:3648$192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3648$192_Y + end + attribute \src "ls180.v:4140.47-4140.80" + cell $ne $ne$ls180.v:4140$590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_level0 + connect \B 5'10000 + connect \Y $ne$ls180.v:4140$590_Y + end + attribute \src "ls180.v:4141.47-4141.79" + cell $ne $ne$ls180.v:4141$591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_level0 + connect \B 1'0 + connect \Y $ne$ls180.v:4141$591_Y + end + attribute \src "ls180.v:4170.47-4170.80" + cell $ne $ne$ls180.v:4170$601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_level0 + connect \B 5'10000 + connect \Y $ne$ls180.v:4170$601_Y + end + attribute \src "ls180.v:4171.47-4171.79" + cell $ne $ne$ls180.v:4171$602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_level0 + connect \B 1'0 + connect \Y $ne$ls180.v:4171$602_Y + end + attribute \src "ls180.v:4577.32-4577.89" + cell $ne $ne$ls180.v:4577$674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 + connect \B 3'101 + connect \Y $ne$ls180.v:4577$674_Y + end + attribute \src "ls180.v:5224.10-5224.56" + cell $ne $ne$ls180.v:5224$971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_payload_status + connect \B 2'10 + connect \Y $ne$ls180.v:5224$971_Y + end + attribute \src "ls180.v:5329.51-5329.87" + cell $ne $ne$ls180.v:5329$985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_level + connect \B 6'100000 + connect \Y $ne$ls180.v:5329$985_Y + end + attribute \src "ls180.v:5330.51-5330.86" + cell $ne $ne$ls180.v:5330$986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_level + connect \B 1'0 + connect \Y $ne$ls180.v:5330$986_Y + end + attribute \src "ls180.v:5537.51-5537.87" + cell $ne $ne$ls180.v:5537$1016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_level + connect \B 6'100000 + connect \Y $ne$ls180.v:5537$1016_Y + end + attribute \src "ls180.v:5538.51-5538.86" + cell $ne $ne$ls180.v:5538$1017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_level + connect \B 1'0 + connect \Y $ne$ls180.v:5538$1017_Y + end + attribute \src "ls180.v:5628.79-5628.119" + cell $ne $ne$ls180.v:5628$1028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_sel + connect \B 1'0 + connect \Y $ne$ls180.v:5628$1028_Y + end + attribute \src "ls180.v:7436.7-7436.52" + cell $ne $ne$ls180.v:7436$2406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_bus_errors + connect \B 32'11111111111111111111111111111111 + connect \Y $ne$ls180.v:7436$2406_Y + end + attribute \src "ls180.v:7488.9-7488.43" + cell $ne $ne$ls180.v:7488$2420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $ne$ls180.v:7488$2420_Y + end + attribute \src "ls180.v:7524.8-7524.44" + cell $ne $ne$ls180.v:7524$2427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 1'0 + connect \Y $ne$ls180.v:7524$2427_Y + end + attribute \src "ls180.v:8427.9-8427.47" + cell $ne $ne$ls180.v:8427$2637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 4'1010 + connect \Y $ne$ls180.v:8427$2637_Y + end + attribute \src "ls180.v:2725.45-2725.80" + cell $not $not$ls180.v:2725$14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_ibus_cyc + connect \Y $not$ls180.v:2725$14_Y + end + attribute \src "ls180.v:2764.61-2764.94" + cell $not $not$ls180.v:2764$19 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter0_skip + connect \Y $not$ls180.v:2764$19_Y + end + attribute \src "ls180.v:2765.61-2765.94" + cell $not $not$ls180.v:2765$20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter0_skip + connect \Y $not$ls180.v:2765$20_Y + end + attribute \src "ls180.v:2785.45-2785.80" + cell $not $not$ls180.v:2785$25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_dbus_cyc + connect \Y $not$ls180.v:2785$25_Y + end + attribute \src "ls180.v:2824.61-2824.94" + cell $not $not$ls180.v:2824$30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter1_skip + connect \Y $not$ls180.v:2824$30_Y + end + attribute \src "ls180.v:2825.61-2825.94" + cell $not $not$ls180.v:2825$31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter1_skip + connect \Y $not$ls180.v:2825$31_Y + end + attribute \src "ls180.v:2845.45-2845.83" + cell $not $not$ls180.v:2845$36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_jtag_wb_cyc + connect \Y $not$ls180.v:2845$36_Y + end + attribute \src "ls180.v:2884.61-2884.94" + cell $not $not$ls180.v:2884$41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter2_skip + connect \Y $not$ls180.v:2884$41_Y + end + attribute \src "ls180.v:2885.61-2885.94" + cell $not $not$ls180.v:2885$42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter2_skip + connect \Y $not$ls180.v:2885$42_Y + end + attribute \src "ls180.v:3032.34-3032.64" + cell $not $not$ls180.v:3032$67 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [0] + connect \Y $not$ls180.v:3032$67_Y + end + attribute \src "ls180.v:3033.31-3033.61" + cell $not $not$ls180.v:3033$68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [1] + connect \Y $not$ls180.v:3033$68_Y + end + attribute \src "ls180.v:3034.32-3034.62" + cell $not $not$ls180.v:3034$69 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [2] + connect \Y $not$ls180.v:3034$69_Y + end + attribute \src "ls180.v:3035.32-3035.62" + cell $not $not$ls180.v:3035$70 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [3] + connect \Y $not$ls180.v:3035$70_Y + end + attribute \src "ls180.v:3077.33-3077.56" + cell $not $not$ls180.v:3077$73 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_done0 + connect \Y $not$ls180.v:3077$73_Y + end + attribute \src "ls180.v:3178.58-3178.106" + cell $not $not$ls180.v:3178$103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $not$ls180.v:3178$103_Y + end + attribute \src "ls180.v:3232.9-3232.45" + cell $not $not$ls180.v:3232$108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_refresh_req + connect \Y $not$ls180.v:3232$108_Y + end + attribute \src "ls180.v:3335.58-3335.106" + cell $not $not$ls180.v:3335$133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $not$ls180.v:3335$133_Y + end + attribute \src "ls180.v:3389.9-3389.45" + cell $not $not$ls180.v:3389$138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_refresh_req + connect \Y $not$ls180.v:3389$138_Y + end + attribute \src "ls180.v:3492.58-3492.106" + cell $not $not$ls180.v:3492$163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $not$ls180.v:3492$163_Y + end + attribute \src "ls180.v:3546.9-3546.45" + cell $not $not$ls180.v:3546$168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_refresh_req + connect \Y $not$ls180.v:3546$168_Y + end + attribute \src "ls180.v:3649.58-3649.106" + cell $not $not$ls180.v:3649$193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $not$ls180.v:3649$193_Y + end + attribute \src "ls180.v:3703.9-3703.45" + cell $not $not$ls180.v:3703$198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_refresh_req + connect \Y $not$ls180.v:3703$198_Y + end + attribute \src "ls180.v:3745.149-3745.187" + cell $not $not$ls180.v:3745$201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3745$201_Y + end + attribute \src "ls180.v:3745.193-3745.230" + cell $not $not$ls180.v:3745$203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3745$203_Y + end + attribute \src "ls180.v:3746.149-3746.187" + cell $not $not$ls180.v:3746$207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3746$207_Y + end + attribute \src "ls180.v:3746.193-3746.230" + cell $not $not$ls180.v:3746$209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3746$209_Y + end + attribute \src "ls180.v:3762.43-3762.73" + cell $not $not$ls180.v:3762$237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \main_sdram_interface_wdata_we + connect \Y $not$ls180.v:3762$237_Y + end + attribute \src "ls180.v:3765.205-3765.245" + cell $not $not$ls180.v:3765$240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_cas + connect \Y $not$ls180.v:3765$240_Y + end + attribute \src "ls180.v:3765.251-3765.290" + cell $not $not$ls180.v:3765$242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_we + connect \Y $not$ls180.v:3765$242_Y + end + attribute \src "ls180.v:3765.159-3765.292" + cell $not $not$ls180.v:3765$244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3765$243_Y + connect \Y $not$ls180.v:3765$244_Y + end + attribute \src "ls180.v:3766.205-3766.245" + cell $not $not$ls180.v:3766$253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_cas + connect \Y $not$ls180.v:3766$253_Y + end + attribute \src "ls180.v:3766.251-3766.290" + cell $not $not$ls180.v:3766$255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_we + connect \Y $not$ls180.v:3766$255_Y + end + attribute \src "ls180.v:3766.159-3766.292" + cell $not $not$ls180.v:3766$257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3766$256_Y + connect \Y $not$ls180.v:3766$257_Y + end + attribute \src "ls180.v:3767.205-3767.245" + cell $not $not$ls180.v:3767$266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_cas + connect \Y $not$ls180.v:3767$266_Y + end + attribute \src "ls180.v:3767.251-3767.290" + cell $not $not$ls180.v:3767$268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_we + connect \Y $not$ls180.v:3767$268_Y + end + attribute \src "ls180.v:3767.159-3767.292" + cell $not $not$ls180.v:3767$270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3767$269_Y + connect \Y $not$ls180.v:3767$270_Y + end + attribute \src "ls180.v:3768.205-3768.245" + cell $not $not$ls180.v:3768$279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_cas + connect \Y $not$ls180.v:3768$279_Y + end + attribute \src "ls180.v:3768.251-3768.290" + cell $not $not$ls180.v:3768$281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_we + connect \Y $not$ls180.v:3768$281_Y + end + attribute \src "ls180.v:3768.159-3768.292" + cell $not $not$ls180.v:3768$283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3768$282_Y + connect \Y $not$ls180.v:3768$283_Y + end + attribute \src "ls180.v:3795.71-3795.103" + cell $not $not$ls180.v:3795$294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \Y $not$ls180.v:3795$294_Y + end + attribute \src "ls180.v:3798.205-3798.245" + cell $not $not$ls180.v:3798$298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_cas + connect \Y $not$ls180.v:3798$298_Y + end + attribute \src "ls180.v:3798.251-3798.290" + cell $not $not$ls180.v:3798$300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_we + connect \Y $not$ls180.v:3798$300_Y + end + attribute \src "ls180.v:3798.159-3798.292" + cell $not $not$ls180.v:3798$302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3798$301_Y + connect \Y $not$ls180.v:3798$302_Y + end + attribute \src "ls180.v:3799.205-3799.245" + cell $not $not$ls180.v:3799$311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_cas + connect \Y $not$ls180.v:3799$311_Y + end + attribute \src "ls180.v:3799.251-3799.290" + cell $not $not$ls180.v:3799$313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_we + connect \Y $not$ls180.v:3799$313_Y + end + attribute \src "ls180.v:3799.159-3799.292" + cell $not $not$ls180.v:3799$315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3799$314_Y + connect \Y $not$ls180.v:3799$315_Y + end + attribute \src "ls180.v:3800.205-3800.245" + cell $not $not$ls180.v:3800$324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_cas + connect \Y $not$ls180.v:3800$324_Y + end + attribute \src "ls180.v:3800.251-3800.290" + cell $not $not$ls180.v:3800$326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_we + connect \Y $not$ls180.v:3800$326_Y + end + attribute \src "ls180.v:3800.159-3800.292" + cell $not $not$ls180.v:3800$328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3800$327_Y + connect \Y $not$ls180.v:3800$328_Y + end + attribute \src "ls180.v:3801.205-3801.245" + cell $not $not$ls180.v:3801$337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_cas + connect \Y $not$ls180.v:3801$337_Y + end + attribute \src "ls180.v:3801.251-3801.290" + cell $not $not$ls180.v:3801$339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_we + connect \Y $not$ls180.v:3801$339_Y + end + attribute \src "ls180.v:3801.159-3801.292" + cell $not $not$ls180.v:3801$341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3801$340_Y + connect \Y $not$ls180.v:3801$341_Y + end + attribute \src "ls180.v:3864.71-3864.103" + cell $not $not$ls180.v:3864$380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \Y $not$ls180.v:3864$380_Y + end + attribute \src "ls180.v:3885.112-3885.150" + cell $not $not$ls180.v:3885$383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3885$383_Y + end + attribute \src "ls180.v:3885.156-3885.193" + cell $not $not$ls180.v:3885$385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3885$385_Y + end + attribute \src "ls180.v:3885.68-3885.195" + cell $not $not$ls180.v:3885$387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3885$386_Y + connect \Y $not$ls180.v:3885$387_Y + end + attribute \src "ls180.v:3893.11-3893.38" + cell $not $not$ls180.v:3893$390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_write_available + connect \Y $not$ls180.v:3893$390_Y + end + attribute \src "ls180.v:3923.112-3923.150" + cell $not $not$ls180.v:3923$392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3923$392_Y + end + attribute \src "ls180.v:3923.156-3923.193" + cell $not $not$ls180.v:3923$394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3923$394_Y + end + attribute \src "ls180.v:3923.68-3923.195" + cell $not $not$ls180.v:3923$396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3923$395_Y + connect \Y $not$ls180.v:3923$396_Y + end + attribute \src "ls180.v:3931.11-3931.37" + cell $not $not$ls180.v:3931$399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_read_available + connect \Y $not$ls180.v:3931$399_Y + end + attribute \src "ls180.v:3941.87-3941.331" + cell $not $not$ls180.v:3941$411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3941$410_Y + connect \Y $not$ls180.v:3941$411_Y + end + attribute \src "ls180.v:3942.35-3942.68" + cell $not $not$ls180.v:3942$414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_valid + connect \Y $not$ls180.v:3942$414_Y + end + attribute \src "ls180.v:3942.73-3942.105" + cell $not $not$ls180.v:3942$415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \Y $not$ls180.v:3942$415_Y + end + attribute \src "ls180.v:3946.87-3946.331" + cell $not $not$ls180.v:3946$427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3946$426_Y + connect \Y $not$ls180.v:3946$427_Y + end + attribute \src "ls180.v:3947.35-3947.68" + cell $not $not$ls180.v:3947$430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_valid + connect \Y $not$ls180.v:3947$430_Y + end + attribute \src "ls180.v:3947.73-3947.105" + cell $not $not$ls180.v:3947$431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \Y $not$ls180.v:3947$431_Y + end + attribute \src "ls180.v:3951.87-3951.331" + cell $not $not$ls180.v:3951$443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3951$442_Y + connect \Y $not$ls180.v:3951$443_Y + end + attribute \src "ls180.v:3952.35-3952.68" + cell $not $not$ls180.v:3952$446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_valid + connect \Y $not$ls180.v:3952$446_Y + end + attribute \src "ls180.v:3952.73-3952.105" + cell $not $not$ls180.v:3952$447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \Y $not$ls180.v:3952$447_Y + end + attribute \src "ls180.v:3956.87-3956.331" + cell $not $not$ls180.v:3956$459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3956$458_Y + connect \Y $not$ls180.v:3956$459_Y + end + attribute \src "ls180.v:3957.35-3957.68" + cell $not $not$ls180.v:3957$462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_valid + connect \Y $not$ls180.v:3957$462_Y + end + attribute \src "ls180.v:3957.73-3957.105" + cell $not $not$ls180.v:3957$463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \Y $not$ls180.v:3957$463_Y + end + attribute \src "ls180.v:3961.128-3961.372" + cell $not $not$ls180.v:3961$476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3961$475_Y + connect \Y $not$ls180.v:3961$476_Y + end + attribute \src "ls180.v:3961.502-3961.746" + cell $not $not$ls180.v:3961$492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3961$491_Y + connect \Y $not$ls180.v:3961$492_Y + end + attribute \src "ls180.v:3961.876-3961.1120" + cell $not $not$ls180.v:3961$508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3961$507_Y + connect \Y $not$ls180.v:3961$508_Y + end + attribute \src "ls180.v:3961.1250-3961.1494" + cell $not $not$ls180.v:3961$524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3961$523_Y + connect \Y $not$ls180.v:3961$524_Y + end + attribute \src "ls180.v:3983.32-3983.50" + cell $not $not$ls180.v:3983$530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_cyc + connect \Y $not$ls180.v:3983$530_Y + end + attribute \src "ls180.v:4022.30-4022.50" + cell $not $not$ls180.v:4022$535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_skip + connect \Y $not$ls180.v:4022$535_Y + end + attribute \src "ls180.v:4023.30-4023.50" + cell $not $not$ls180.v:4023$536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_skip + connect \Y $not$ls180.v:4023$536_Y + end + attribute \src "ls180.v:4048.27-4048.48" + cell $not $not$ls180.v:4048$542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_cyc + connect \Y $not$ls180.v:4048$542_Y + end + attribute \src "ls180.v:4049.30-4049.50" + cell $not $not$ls180.v:4049$543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \Y $not$ls180.v:4049$543_Y + end + attribute \src "ls180.v:4050.80-4050.98" + cell $not $not$ls180.v:4050$545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_cmd_consumed + connect \Y $not$ls180.v:4050$545_Y + end + attribute \src "ls180.v:4051.107-4051.127" + cell $not $not$ls180.v:4051$549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wdata_consumed + connect \Y $not$ls180.v:4051$549_Y + end + attribute \src "ls180.v:4052.78-4052.103" + cell $not $not$ls180.v:4052$552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_we + connect \Y $not$ls180.v:4052$552_Y + end + attribute \src "ls180.v:4053.91-4053.111" + cell $not $not$ls180.v:4053$555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \Y $not$ls180.v:4053$555_Y + end + attribute \src "ls180.v:4069.35-4069.64" + cell $not $not$ls180.v:4069$564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_sink_ready + connect \Y $not$ls180.v:4069$564_Y + end + attribute \src "ls180.v:4070.36-4070.67" + cell $not $not$ls180.v:4070$565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_source_valid + connect \Y $not$ls180.v:4070$565_Y + end + attribute \src "ls180.v:4076.32-4076.61" + cell $not $not$ls180.v:4076$566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_sink_ready + connect \Y $not$ls180.v:4076$566_Y + end + attribute \src "ls180.v:4082.36-4082.67" + cell $not $not$ls180.v:4082$567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_source_valid + connect \Y $not$ls180.v:4082$567_Y + end + attribute \src "ls180.v:4083.35-4083.64" + cell $not $not$ls180.v:4083$568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_sink_ready + connect \Y $not$ls180.v:4083$568_Y + end + attribute \src "ls180.v:4086.32-4086.63" + cell $not $not$ls180.v:4086$571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_source_valid + connect \Y $not$ls180.v:4086$571_Y + end + attribute \src "ls180.v:4124.81-4124.108" + cell $not $not$ls180.v:4124$581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_readable + connect \Y $not$ls180.v:4124$581_Y + end + attribute \src "ls180.v:4154.81-4154.108" + cell $not $not$ls180.v:4154$592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_readable + connect \Y $not$ls180.v:4154$592_Y + end + attribute \src "ls180.v:4291.60-4291.85" + cell $not $not$ls180.v:4291$633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_clk_d + connect \Y $not$ls180.v:4291$633_Y + end + attribute \src "ls180.v:4432.54-4432.96" + cell $not $not$ls180.v:4432$647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_strobe_all + connect \Y $not$ls180.v:4432$647_Y + end + attribute \src "ls180.v:4435.48-4435.86" + cell $not $not$ls180.v:4435$650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_buf_source_valid + connect \Y $not$ls180.v:4435$650_Y + end + attribute \src "ls180.v:4559.55-4559.98" + cell $not $not$ls180.v:4559$668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_strobe_all + connect \Y $not$ls180.v:4559$668_Y + end + attribute \src "ls180.v:4562.49-4562.88" + cell $not $not$ls180.v:4562$671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_buf_source_valid + connect \Y $not$ls180.v:4562$671_Y + end + attribute \src "ls180.v:4612.30-4612.58" + cell $not $not$ls180.v:4612$677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_sink_valid + connect \Y $not$ls180.v:4612$677_Y + end + attribute \src "ls180.v:4693.56-4693.100" + cell $not $not$ls180.v:4693$683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_strobe_all + connect \Y $not$ls180.v:4693$683_Y + end + attribute \src "ls180.v:4696.50-4696.90" + cell $not $not$ls180.v:4696$686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_buf_source_valid + connect \Y $not$ls180.v:4696$686_Y + end + attribute \src "ls180.v:4812.42-4812.74" + cell $not $not$ls180.v:4812$702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_valid + connect \Y $not$ls180.v:4812$702_Y + end + attribute \src "ls180.v:5336.50-5336.88" + cell $not $not$ls180.v:5336$987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_strobe_all + connect \Y $not$ls180.v:5336$987_Y + end + attribute \src "ls180.v:5348.52-5348.102" + cell $not $not$ls180.v:5348$990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_wishbonedmawriter_enable_storage + connect \Y $not$ls180.v:5348$990_Y + end + attribute \src "ls180.v:5407.38-5407.74" + cell $not $not$ls180.v:5407$997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_dma_enable_storage + connect \Y $not$ls180.v:5407$997_Y + end + attribute \src "ls180.v:5708.69-5708.88" + cell $not $not$ls180.v:5708$1066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \Y $not$ls180.v:5708$1066_Y + end + attribute \src "ls180.v:5725.63-5725.94" + cell $not $not$ls180.v:5725$1087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5725$1087_Y + end + attribute \src "ls180.v:5728.65-5728.96" + cell $not $not$ls180.v:5728$1094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5728$1094_Y + end + attribute \src "ls180.v:5731.65-5731.96" + cell $not $not$ls180.v:5731$1101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5731$1101_Y + end + attribute \src "ls180.v:5734.65-5734.96" + cell $not $not$ls180.v:5734$1108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5734$1108_Y + end + attribute \src "ls180.v:5737.65-5737.96" + cell $not $not$ls180.v:5737$1115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5737$1115_Y + end + attribute \src "ls180.v:5740.68-5740.99" + cell $not $not$ls180.v:5740$1122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5740$1122_Y + end + attribute \src "ls180.v:5743.68-5743.99" + cell $not $not$ls180.v:5743$1129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5743$1129_Y + end + attribute \src "ls180.v:5746.68-5746.99" + cell $not $not$ls180.v:5746$1136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5746$1136_Y + end + attribute \src "ls180.v:5749.68-5749.99" + cell $not $not$ls180.v:5749$1143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5749$1143_Y + end + attribute \src "ls180.v:5763.60-5763.91" + cell $not $not$ls180.v:5763$1151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5763$1151_Y + end + attribute \src "ls180.v:5766.60-5766.91" + cell $not $not$ls180.v:5766$1158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5766$1158_Y + end + attribute \src "ls180.v:5769.60-5769.91" + cell $not $not$ls180.v:5769$1165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5769$1165_Y + end + attribute \src "ls180.v:5772.60-5772.91" + cell $not $not$ls180.v:5772$1172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5772$1172_Y + end + attribute \src "ls180.v:5775.61-5775.92" + cell $not $not$ls180.v:5775$1179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5775$1179_Y + end + attribute \src "ls180.v:5778.61-5778.92" + cell $not $not$ls180.v:5778$1186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5778$1186_Y + end + attribute \src "ls180.v:5789.64-5789.95" + cell $not $not$ls180.v:5789$1194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5789$1194_Y + end + attribute \src "ls180.v:5792.63-5792.94" + cell $not $not$ls180.v:5792$1201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5792$1201_Y + end + attribute \src "ls180.v:5795.63-5795.94" + cell $not $not$ls180.v:5795$1208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5795$1208_Y + end + attribute \src "ls180.v:5798.63-5798.94" + cell $not $not$ls180.v:5798$1215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5798$1215_Y + end + attribute \src "ls180.v:5801.63-5801.94" + cell $not $not$ls180.v:5801$1222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5801$1222_Y + end + attribute \src "ls180.v:5804.64-5804.95" + cell $not $not$ls180.v:5804$1229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5804$1229_Y + end + attribute \src "ls180.v:5807.64-5807.95" + cell $not $not$ls180.v:5807$1236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5807$1236_Y + end + attribute \src "ls180.v:5810.64-5810.95" + cell $not $not$ls180.v:5810$1243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5810$1243_Y + end + attribute \src "ls180.v:5813.64-5813.95" + cell $not $not$ls180.v:5813$1250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5813$1250_Y + end + attribute \src "ls180.v:5826.64-5826.95" + cell $not $not$ls180.v:5826$1258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5826$1258_Y + end + attribute \src "ls180.v:5829.63-5829.94" + cell $not $not$ls180.v:5829$1265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5829$1265_Y + end + attribute \src "ls180.v:5832.63-5832.94" + cell $not $not$ls180.v:5832$1272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5832$1272_Y + end + attribute \src "ls180.v:5835.63-5835.94" + cell $not $not$ls180.v:5835$1279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5835$1279_Y + end + attribute \src "ls180.v:5838.63-5838.94" + cell $not $not$ls180.v:5838$1286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5838$1286_Y + end + attribute \src "ls180.v:5841.64-5841.95" + cell $not $not$ls180.v:5841$1293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5841$1293_Y + end + attribute \src "ls180.v:5844.64-5844.95" + cell $not $not$ls180.v:5844$1300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5844$1300_Y + end + attribute \src "ls180.v:5847.64-5847.95" + cell $not $not$ls180.v:5847$1307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5847$1307_Y + end + attribute \src "ls180.v:5850.64-5850.95" + cell $not $not$ls180.v:5850$1314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5850$1314_Y + end + attribute \src "ls180.v:5863.66-5863.97" + cell $not $not$ls180.v:5863$1322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5863$1322_Y + end + attribute \src "ls180.v:5866.66-5866.97" + cell $not $not$ls180.v:5866$1329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5866$1329_Y + end + attribute \src "ls180.v:5869.66-5869.97" + cell $not $not$ls180.v:5869$1336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5869$1336_Y + end + attribute \src "ls180.v:5872.66-5872.97" + cell $not $not$ls180.v:5872$1343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5872$1343_Y + end + attribute \src "ls180.v:5875.66-5875.97" + cell $not $not$ls180.v:5875$1350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5875$1350_Y + end + attribute \src "ls180.v:5878.66-5878.97" + cell $not $not$ls180.v:5878$1357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5878$1357_Y + end + attribute \src "ls180.v:5881.66-5881.97" + cell $not $not$ls180.v:5881$1364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5881$1364_Y + end + attribute \src "ls180.v:5884.66-5884.97" + cell $not $not$ls180.v:5884$1371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5884$1371_Y + end + attribute \src "ls180.v:5887.68-5887.99" + cell $not $not$ls180.v:5887$1378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5887$1378_Y + end + attribute \src "ls180.v:5890.68-5890.99" + cell $not $not$ls180.v:5890$1385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5890$1385_Y + end + attribute \src "ls180.v:5893.68-5893.99" + cell $not $not$ls180.v:5893$1392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5893$1392_Y + end + attribute \src "ls180.v:5896.68-5896.99" + cell $not $not$ls180.v:5896$1399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5896$1399_Y + end + attribute \src "ls180.v:5899.68-5899.99" + cell $not $not$ls180.v:5899$1406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5899$1406_Y + end + attribute \src "ls180.v:5902.65-5902.96" + cell $not $not$ls180.v:5902$1413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5902$1413_Y + end + attribute \src "ls180.v:5905.66-5905.97" + cell $not $not$ls180.v:5905$1420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5905$1420_Y + end + attribute \src "ls180.v:5925.70-5925.101" + cell $not $not$ls180.v:5925$1428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5925$1428_Y + end + attribute \src "ls180.v:5928.70-5928.101" + cell $not $not$ls180.v:5928$1435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5928$1435_Y + end + attribute \src "ls180.v:5931.70-5931.101" + cell $not $not$ls180.v:5931$1442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5931$1442_Y + end + attribute \src "ls180.v:5934.70-5934.101" + cell $not $not$ls180.v:5934$1449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5934$1449_Y + end + attribute \src "ls180.v:5937.69-5937.100" + cell $not $not$ls180.v:5937$1456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5937$1456_Y + end + attribute \src "ls180.v:5940.69-5940.100" + cell $not $not$ls180.v:5940$1463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5940$1463_Y + end + attribute \src "ls180.v:5943.69-5943.100" + cell $not $not$ls180.v:5943$1470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5943$1470_Y + end + attribute \src "ls180.v:5946.69-5946.100" + cell $not $not$ls180.v:5946$1477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5946$1477_Y + end + attribute \src "ls180.v:5949.60-5949.91" + cell $not $not$ls180.v:5949$1484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5949$1484_Y + end + attribute \src "ls180.v:5952.71-5952.102" + cell $not $not$ls180.v:5952$1491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5952$1491_Y + end + attribute \src "ls180.v:5955.71-5955.102" + cell $not $not$ls180.v:5955$1498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5955$1498_Y + end + attribute \src "ls180.v:5958.71-5958.102" + cell $not $not$ls180.v:5958$1505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5958$1505_Y + end + attribute \src "ls180.v:5961.71-5961.102" + cell $not $not$ls180.v:5961$1512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5961$1512_Y + end + attribute \src "ls180.v:5964.71-5964.102" + cell $not $not$ls180.v:5964$1519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5964$1519_Y + end + attribute \src "ls180.v:5967.71-5967.102" + cell $not $not$ls180.v:5967$1526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5967$1526_Y + end + attribute \src "ls180.v:5970.70-5970.101" + cell $not $not$ls180.v:5970$1533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5970$1533_Y + end + attribute \src "ls180.v:5973.70-5973.101" + cell $not $not$ls180.v:5973$1540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5973$1540_Y + end + attribute \src "ls180.v:5976.70-5976.101" + cell $not $not$ls180.v:5976$1547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5976$1547_Y + end + attribute \src "ls180.v:5979.70-5979.101" + cell $not $not$ls180.v:5979$1554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5979$1554_Y + end + attribute \src "ls180.v:5982.70-5982.101" + cell $not $not$ls180.v:5982$1561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5982$1561_Y + end + attribute \src "ls180.v:5985.70-5985.101" + cell $not $not$ls180.v:5985$1568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5985$1568_Y + end + attribute \src "ls180.v:5988.70-5988.101" + cell $not $not$ls180.v:5988$1575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5988$1575_Y + end + attribute \src "ls180.v:5991.70-5991.101" + cell $not $not$ls180.v:5991$1582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5991$1582_Y + end + attribute \src "ls180.v:5994.70-5994.101" + cell $not $not$ls180.v:5994$1589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5994$1589_Y + end + attribute \src "ls180.v:5997.70-5997.101" + cell $not $not$ls180.v:5997$1596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5997$1596_Y + end + attribute \src "ls180.v:6000.66-6000.97" + cell $not $not$ls180.v:6000$1603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6000$1603_Y + end + attribute \src "ls180.v:6003.67-6003.98" + cell $not $not$ls180.v:6003$1610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6003$1610_Y + end + attribute \src "ls180.v:6006.70-6006.101" + cell $not $not$ls180.v:6006$1617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6006$1617_Y + end + attribute \src "ls180.v:6009.70-6009.101" + cell $not $not$ls180.v:6009$1624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6009$1624_Y + end + attribute \src "ls180.v:6012.69-6012.100" + cell $not $not$ls180.v:6012$1631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6012$1631_Y + end + attribute \src "ls180.v:6015.69-6015.100" + cell $not $not$ls180.v:6015$1638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6015$1638_Y + end + attribute \src "ls180.v:6018.69-6018.100" + cell $not $not$ls180.v:6018$1645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6018$1645_Y + end + attribute \src "ls180.v:6021.69-6021.100" + cell $not $not$ls180.v:6021$1652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6021$1652_Y + end + attribute \src "ls180.v:6060.66-6060.97" + cell $not $not$ls180.v:6060$1660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6060$1660_Y + end + attribute \src "ls180.v:6063.66-6063.97" + cell $not $not$ls180.v:6063$1667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6063$1667_Y + end + attribute \src "ls180.v:6066.66-6066.97" + cell $not $not$ls180.v:6066$1674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6066$1674_Y + end + attribute \src "ls180.v:6069.66-6069.97" + cell $not $not$ls180.v:6069$1681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6069$1681_Y + end + attribute \src "ls180.v:6072.66-6072.97" + cell $not $not$ls180.v:6072$1688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6072$1688_Y + end + attribute \src "ls180.v:6075.66-6075.97" + cell $not $not$ls180.v:6075$1695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6075$1695_Y + end + attribute \src "ls180.v:6078.66-6078.97" + cell $not $not$ls180.v:6078$1702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6078$1702_Y + end + attribute \src "ls180.v:6081.66-6081.97" + cell $not $not$ls180.v:6081$1709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6081$1709_Y + end + attribute \src "ls180.v:6084.68-6084.99" + cell $not $not$ls180.v:6084$1716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6084$1716_Y + end + attribute \src "ls180.v:6087.68-6087.99" + cell $not $not$ls180.v:6087$1723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6087$1723_Y + end + attribute \src "ls180.v:6090.68-6090.99" + cell $not $not$ls180.v:6090$1730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6090$1730_Y + end + attribute \src "ls180.v:6093.68-6093.99" + cell $not $not$ls180.v:6093$1737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6093$1737_Y + end + attribute \src "ls180.v:6096.68-6096.99" + cell $not $not$ls180.v:6096$1744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6096$1744_Y + end + attribute \src "ls180.v:6099.65-6099.96" + cell $not $not$ls180.v:6099$1751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6099$1751_Y + end + attribute \src "ls180.v:6102.66-6102.97" + cell $not $not$ls180.v:6102$1758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6102$1758_Y + end + attribute \src "ls180.v:6105.68-6105.99" + cell $not $not$ls180.v:6105$1765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6105$1765_Y + end + attribute \src "ls180.v:6108.68-6108.99" + cell $not $not$ls180.v:6108$1772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6108$1772_Y + end + attribute \src "ls180.v:6111.68-6111.99" + cell $not $not$ls180.v:6111$1779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6111$1779_Y + end + attribute \src "ls180.v:6114.68-6114.99" + cell $not $not$ls180.v:6114$1786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6114$1786_Y + end + attribute \src "ls180.v:6139.68-6139.99" + cell $not $not$ls180.v:6139$1794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6139$1794_Y + end + attribute \src "ls180.v:6142.73-6142.104" + cell $not $not$ls180.v:6142$1801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6142$1801_Y + end + attribute \src "ls180.v:6145.73-6145.104" + cell $not $not$ls180.v:6145$1808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6145$1808_Y + end + attribute \src "ls180.v:6148.66-6148.97" + cell $not $not$ls180.v:6148$1815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6148$1815_Y + end + attribute \src "ls180.v:6156.70-6156.101" + cell $not $not$ls180.v:6156$1823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6156$1823_Y + end + attribute \src "ls180.v:6159.74-6159.105" + cell $not $not$ls180.v:6159$1830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6159$1830_Y + end + attribute \src "ls180.v:6162.64-6162.95" + cell $not $not$ls180.v:6162$1837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6162$1837_Y + end + attribute \src "ls180.v:6165.74-6165.105" + cell $not $not$ls180.v:6165$1844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6165$1844_Y + end + attribute \src "ls180.v:6168.74-6168.105" + cell $not $not$ls180.v:6168$1851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6168$1851_Y + end + attribute \src "ls180.v:6171.75-6171.106" + cell $not $not$ls180.v:6171$1858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6171$1858_Y + end + attribute \src "ls180.v:6174.73-6174.104" + cell $not $not$ls180.v:6174$1865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6174$1865_Y + end + attribute \src "ls180.v:6177.73-6177.104" + cell $not $not$ls180.v:6177$1872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6177$1872_Y + end + attribute \src "ls180.v:6180.73-6180.104" + cell $not $not$ls180.v:6180$1879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6180$1879_Y + end + attribute \src "ls180.v:6183.73-6183.104" + cell $not $not$ls180.v:6183$1886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6183$1886_Y + end + attribute \src "ls180.v:6201.65-6201.96" + cell $not $not$ls180.v:6201$1894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6201$1894_Y + end + attribute \src "ls180.v:6204.65-6204.96" + cell $not $not$ls180.v:6204$1901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6204$1901_Y + end + attribute \src "ls180.v:6207.63-6207.94" + cell $not $not$ls180.v:6207$1908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6207$1908_Y + end + attribute \src "ls180.v:6210.62-6210.93" + cell $not $not$ls180.v:6210$1915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6210$1915_Y + end + attribute \src "ls180.v:6213.61-6213.92" + cell $not $not$ls180.v:6213$1922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6213$1922_Y + end + attribute \src "ls180.v:6216.60-6216.91" + cell $not $not$ls180.v:6216$1929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6216$1929_Y + end + attribute \src "ls180.v:6219.66-6219.97" + cell $not $not$ls180.v:6219$1936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6219$1936_Y + end + attribute \src "ls180.v:6241.67-6241.99" + cell $not $not$ls180.v:6241$1945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6241$1945_Y + end + attribute \src "ls180.v:6244.67-6244.99" + cell $not $not$ls180.v:6244$1952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6244$1952_Y + end + attribute \src "ls180.v:6247.65-6247.97" + cell $not $not$ls180.v:6247$1959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6247$1959_Y + end + attribute \src "ls180.v:6250.64-6250.96" + cell $not $not$ls180.v:6250$1966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6250$1966_Y + end + attribute \src "ls180.v:6253.63-6253.95" + cell $not $not$ls180.v:6253$1973 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6253$1973_Y + end + attribute \src "ls180.v:6256.62-6256.94" + cell $not $not$ls180.v:6256$1980 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6256$1980_Y + end + attribute \src "ls180.v:6259.68-6259.100" + cell $not $not$ls180.v:6259$1987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6259$1987_Y + end + attribute \src "ls180.v:6262.71-6262.103" + cell $not $not$ls180.v:6262$1994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6262$1994_Y + end + attribute \src "ls180.v:6265.71-6265.103" + cell $not $not$ls180.v:6265$2001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6265$2001_Y + end + attribute \src "ls180.v:6289.64-6289.96" + cell $not $not$ls180.v:6289$2010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6289$2010_Y + end + attribute \src "ls180.v:6292.64-6292.96" + cell $not $not$ls180.v:6292$2017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6292$2017_Y + end + attribute \src "ls180.v:6295.64-6295.96" + cell $not $not$ls180.v:6295$2024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6295$2024_Y + end + attribute \src "ls180.v:6298.64-6298.96" + cell $not $not$ls180.v:6298$2031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6298$2031_Y + end + attribute \src "ls180.v:6301.66-6301.98" + cell $not $not$ls180.v:6301$2038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6301$2038_Y + end + attribute \src "ls180.v:6304.66-6304.98" + cell $not $not$ls180.v:6304$2045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6304$2045_Y + end + attribute \src "ls180.v:6307.66-6307.98" + cell $not $not$ls180.v:6307$2052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6307$2052_Y + end + attribute \src "ls180.v:6310.66-6310.98" + cell $not $not$ls180.v:6310$2059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6310$2059_Y + end + attribute \src "ls180.v:6313.62-6313.94" + cell $not $not$ls180.v:6313$2066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6313$2066_Y + end + attribute \src "ls180.v:6316.72-6316.104" + cell $not $not$ls180.v:6316$2073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6316$2073_Y + end + attribute \src "ls180.v:6319.65-6319.97" + cell $not $not$ls180.v:6319$2080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6319$2080_Y + end + attribute \src "ls180.v:6322.65-6322.97" + cell $not $not$ls180.v:6322$2087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6322$2087_Y + end + attribute \src "ls180.v:6325.65-6325.97" + cell $not $not$ls180.v:6325$2094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6325$2094_Y + end + attribute \src "ls180.v:6328.65-6328.97" + cell $not $not$ls180.v:6328$2101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6328$2101_Y + end + attribute \src "ls180.v:6331.77-6331.109" + cell $not $not$ls180.v:6331$2108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6331$2108_Y + end + attribute \src "ls180.v:6334.78-6334.110" + cell $not $not$ls180.v:6334$2115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6334$2115_Y + end + attribute \src "ls180.v:6337.69-6337.101" + cell $not $not$ls180.v:6337$2122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6337$2122_Y + end + attribute \src "ls180.v:6357.55-6357.87" + cell $not $not$ls180.v:6357$2130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6357$2130_Y + end + attribute \src "ls180.v:6360.65-6360.97" + cell $not $not$ls180.v:6360$2137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6360$2137_Y + end + attribute \src "ls180.v:6363.66-6363.98" + cell $not $not$ls180.v:6363$2144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6363$2144_Y + end + attribute \src "ls180.v:6366.70-6366.102" + cell $not $not$ls180.v:6366$2151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6366$2151_Y + end + attribute \src "ls180.v:6369.71-6369.103" + cell $not $not$ls180.v:6369$2158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6369$2158_Y + end + attribute \src "ls180.v:6372.69-6372.101" + cell $not $not$ls180.v:6372$2165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6372$2165_Y + end + attribute \src "ls180.v:6375.66-6375.98" + cell $not $not$ls180.v:6375$2172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6375$2172_Y + end + attribute \src "ls180.v:6378.65-6378.97" + cell $not $not$ls180.v:6378$2179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6378$2179_Y + end + attribute \src "ls180.v:6391.71-6391.103" + cell $not $not$ls180.v:6391$2187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6391$2187_Y + end + attribute \src "ls180.v:6394.71-6394.103" + cell $not $not$ls180.v:6394$2194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6394$2194_Y + end + attribute \src "ls180.v:6397.71-6397.103" + cell $not $not$ls180.v:6397$2201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6397$2201_Y + end + attribute \src "ls180.v:6400.71-6400.103" + cell $not $not$ls180.v:6400$2208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6400$2208_Y + end + attribute \src "ls180.v:6778.86-6778.330" + cell $not $not$ls180.v:6778$2256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6778$2255_Y + connect \Y $not$ls180.v:6778$2256_Y + end + attribute \src "ls180.v:6802.86-6802.330" + cell $not $not$ls180.v:6802$2272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6802$2271_Y + connect \Y $not$ls180.v:6802$2272_Y + end + attribute \src "ls180.v:6826.86-6826.330" + cell $not $not$ls180.v:6826$2288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6826$2287_Y + connect \Y $not$ls180.v:6826$2288_Y + end + attribute \src "ls180.v:6850.86-6850.330" + cell $not $not$ls180.v:6850$2304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6850$2303_Y + connect \Y $not$ls180.v:6850$2304_Y + end + attribute \src "ls180.v:7344.18-7344.42" + cell $not $not$ls180.v:7344$2357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_clk0 + connect \Y $not$ls180.v:7344$2357_Y + end + attribute \src "ls180.v:7442.72-7442.101" + cell $not $not$ls180.v:7442$2409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_ack + connect \Y $not$ls180.v:7442$2409_Y + end + attribute \src "ls180.v:7461.8-7461.38" + cell $not $not$ls180.v:7461$2413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_zero_trigger + connect \Y $not$ls180.v:7461$2413_Y + end + attribute \src "ls180.v:7471.32-7471.55" + cell $not $not$ls180.v:7471$2415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_done0 + connect \Y $not$ls180.v:7471$2415_Y + end + attribute \src "ls180.v:7541.136-7541.189" + cell $not $not$ls180.v:7541$2430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7541$2430_Y + end + attribute \src "ls180.v:7547.136-7547.189" + cell $not $not$ls180.v:7547$2435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7547$2435_Y + end + attribute \src "ls180.v:7548.8-7548.61" + cell $not $not$ls180.v:7548$2437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7548$2437_Y + end + attribute \src "ls180.v:7556.8-7556.56" + cell $not $not$ls180.v:7556$2440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $not$ls180.v:7556$2440_Y + end + attribute \src "ls180.v:7571.8-7571.46" + cell $not $not$ls180.v:7571$2442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \Y $not$ls180.v:7571$2442_Y + end + attribute \src "ls180.v:7587.136-7587.189" + cell $not $not$ls180.v:7587$2446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7587$2446_Y + end + attribute \src "ls180.v:7593.136-7593.189" + cell $not $not$ls180.v:7593$2451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7593$2451_Y + end + attribute \src "ls180.v:7594.8-7594.61" + cell $not $not$ls180.v:7594$2453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7594$2453_Y + end + attribute \src "ls180.v:7602.8-7602.56" + cell $not $not$ls180.v:7602$2456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $not$ls180.v:7602$2456_Y + end + attribute \src "ls180.v:7617.8-7617.46" + cell $not $not$ls180.v:7617$2458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \Y $not$ls180.v:7617$2458_Y + end + attribute \src "ls180.v:7633.136-7633.189" + cell $not $not$ls180.v:7633$2462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7633$2462_Y + end + attribute \src "ls180.v:7639.136-7639.189" + cell $not $not$ls180.v:7639$2467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7639$2467_Y + end + attribute \src "ls180.v:7640.8-7640.61" + cell $not $not$ls180.v:7640$2469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7640$2469_Y + end + attribute \src "ls180.v:7648.8-7648.56" + cell $not $not$ls180.v:7648$2472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $not$ls180.v:7648$2472_Y + end + attribute \src "ls180.v:7663.8-7663.46" + cell $not $not$ls180.v:7663$2474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \Y $not$ls180.v:7663$2474_Y + end + attribute \src "ls180.v:7679.136-7679.189" + cell $not $not$ls180.v:7679$2478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7679$2478_Y + end + attribute \src "ls180.v:7685.136-7685.189" + cell $not $not$ls180.v:7685$2483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7685$2483_Y + end + attribute \src "ls180.v:7686.8-7686.61" + cell $not $not$ls180.v:7686$2485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7686$2485_Y + end + attribute \src "ls180.v:7694.8-7694.56" + cell $not $not$ls180.v:7694$2488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $not$ls180.v:7694$2488_Y + end + attribute \src "ls180.v:7709.8-7709.46" + cell $not $not$ls180.v:7709$2490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \Y $not$ls180.v:7709$2490_Y + end + attribute \src "ls180.v:7717.7-7717.22" + cell $not $not$ls180.v:7717$2493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_en0 + connect \Y $not$ls180.v:7717$2493_Y + end + attribute \src "ls180.v:7720.8-7720.29" + cell $not $not$ls180.v:7720$2494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_max_time0 + connect \Y $not$ls180.v:7720$2494_Y + end + attribute \src "ls180.v:7724.7-7724.22" + cell $not $not$ls180.v:7724$2496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_en1 + connect \Y $not$ls180.v:7724$2496_Y + end + attribute \src "ls180.v:7727.8-7727.29" + cell $not $not$ls180.v:7727$2497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_max_time1 + connect \Y $not$ls180.v:7727$2497_Y + end + attribute \src "ls180.v:7846.30-7846.60" + cell $not $not$ls180.v:7846$2499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed2 + connect \Y $not$ls180.v:7846$2499_Y + end + attribute \src "ls180.v:7847.30-7847.60" + cell $not $not$ls180.v:7847$2500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed3 + connect \Y $not$ls180.v:7847$2500_Y + end + attribute \src "ls180.v:7848.29-7848.59" + cell $not $not$ls180.v:7848$2501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed4 + connect \Y $not$ls180.v:7848$2501_Y + end + attribute \src "ls180.v:7859.8-7859.33" + cell $not $not$ls180.v:7859$2502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_ready + connect \Y $not$ls180.v:7859$2502_Y + end + attribute \src "ls180.v:7874.8-7874.33" + cell $not $not$ls180.v:7874$2505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_twtrcon_ready + connect \Y $not$ls180.v:7874$2505_Y + end + attribute \src "ls180.v:7910.27-7910.40" + cell $not $not$ls180.v:7910$2535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_tx_busy + connect \Y $not$ls180.v:7910$2535_Y + end + attribute \src "ls180.v:7910.46-7910.62" + cell $not $not$ls180.v:7910$2537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sink_ready + connect \Y $not$ls180.v:7910$2537_Y + end + attribute \src "ls180.v:7939.7-7939.20" + cell $not $not$ls180.v:7939$2544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_rx_busy + connect \Y $not$ls180.v:7939$2544_Y + end + attribute \src "ls180.v:7940.9-7940.17" + cell $not $not$ls180.v:7940$2545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_rx + connect \Y $not$ls180.v:7940$2545_Y + end + attribute \src "ls180.v:7973.8-7973.29" + cell $not $not$ls180.v:7973$2551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_trigger + connect \Y $not$ls180.v:7973$2551_Y + end + attribute \src "ls180.v:7980.8-7980.29" + cell $not $not$ls180.v:7980$2553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_trigger + connect \Y $not$ls180.v:7980$2553_Y + end + attribute \src "ls180.v:7990.80-7990.106" + cell $not $not$ls180.v:7990$2556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_replace + connect \Y $not$ls180.v:7990$2556_Y + end + attribute \src "ls180.v:7996.80-7996.106" + cell $not $not$ls180.v:7996$2561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_replace + connect \Y $not$ls180.v:7996$2561_Y + end + attribute \src "ls180.v:7997.8-7997.34" + cell $not $not$ls180.v:7997$2563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_do_read + connect \Y $not$ls180.v:7997$2563_Y + end + attribute \src "ls180.v:8012.80-8012.106" + cell $not $not$ls180.v:8012$2567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_replace + connect \Y $not$ls180.v:8012$2567_Y + end + attribute \src "ls180.v:8018.80-8018.106" + cell $not $not$ls180.v:8018$2572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_replace + connect \Y $not$ls180.v:8018$2572_Y + end + attribute \src "ls180.v:8019.8-8019.34" + cell $not $not$ls180.v:8019$2574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_do_read + connect \Y $not$ls180.v:8019$2574_Y + end + attribute \src "ls180.v:8050.23-8050.42" + cell $not $not$ls180.v:8050$2578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spi_master_cs + connect \Y $not$ls180.v:8050$2578_Y + end + attribute \src "ls180.v:8050.47-8050.73" + cell $not $not$ls180.v:8050$2579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spi_master_cs_enable + connect \Y $not$ls180.v:8050$2579_Y + end + attribute \src "ls180.v:8104.7-8104.31" + cell $not $not$ls180.v:8104$2590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_stop + connect \Y $not$ls180.v:8104$2590_Y + end + attribute \src "ls180.v:8176.8-8176.46" + cell $not $not$ls180.v:8176$2602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_buf_source_valid + connect \Y $not$ls180.v:8176$2602_Y + end + attribute \src "ls180.v:8257.8-8257.47" + cell $not $not$ls180.v:8257$2614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_buf_source_valid + connect \Y $not$ls180.v:8257$2614_Y + end + attribute \src "ls180.v:8318.8-8318.48" + cell $not $not$ls180.v:8318$2626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_buf_source_valid + connect \Y $not$ls180.v:8318$2626_Y + end + attribute \src "ls180.v:8488.88-8488.118" + cell $not $not$ls180.v:8488$2640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_replace + connect \Y $not$ls180.v:8488$2640_Y + end + attribute \src "ls180.v:8494.88-8494.118" + cell $not $not$ls180.v:8494$2645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_replace + connect \Y $not$ls180.v:8494$2645_Y + end + attribute \src "ls180.v:8495.8-8495.38" + cell $not $not$ls180.v:8495$2647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_do_read + connect \Y $not$ls180.v:8495$2647_Y + end + attribute \src "ls180.v:8574.88-8574.118" + cell $not $not$ls180.v:8574$2662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_replace + connect \Y $not$ls180.v:8574$2662_Y + end + attribute \src "ls180.v:8580.88-8580.118" + cell $not $not$ls180.v:8580$2667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_replace + connect \Y $not$ls180.v:8580$2667_Y + end + attribute \src "ls180.v:8581.8-8581.38" + cell $not $not$ls180.v:8581$2669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_do_read + connect \Y $not$ls180.v:8581$2669_Y + end + attribute \src "ls180.v:8598.22-8598.37" + cell $not $not$ls180.v:8598$2673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cs + connect \Y $not$ls180.v:8598$2673_Y + end + attribute \src "ls180.v:8598.42-8598.64" + cell $not $not$ls180.v:8598$2674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cs_enable + connect \Y $not$ls180.v:8598$2674_Y + end + attribute \src "ls180.v:8636.9-8636.28" + cell $not $not$ls180.v:8636$2677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [0] + connect \Y $not$ls180.v:8636$2677_Y + end + attribute \src "ls180.v:8655.9-8655.28" + cell $not $not$ls180.v:8655$2678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [1] + connect \Y $not$ls180.v:8655$2678_Y + end + attribute \src "ls180.v:8674.9-8674.28" + cell $not $not$ls180.v:8674$2679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [2] + connect \Y $not$ls180.v:8674$2679_Y + end + attribute \src "ls180.v:8693.9-8693.28" + cell $not $not$ls180.v:8693$2680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [3] + connect \Y $not$ls180.v:8693$2680_Y + end + attribute \src "ls180.v:8712.9-8712.28" + cell $not $not$ls180.v:8712$2681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [4] + connect \Y $not$ls180.v:8712$2681_Y + end + attribute \src "ls180.v:8733.8-8733.21" + cell $not $not$ls180.v:8733$2682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_done + connect \Y $not$ls180.v:8733$2682_Y + end + attribute \src "ls180.v:10199.8-10199.51" + cell $or $or$ls180.v:10199$2754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sys_rst_1 + connect \B \main_libresocsim_libresoc_reset + connect \Y $or$ls180.v:10199$2754_Y + end + attribute \src "ls180.v:2766.10-2766.96" + cell $or $or$ls180.v:2766$21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface0_converted_interface_ack + connect \B \main_libresocsim_converter0_skip + connect \Y $or$ls180.v:2766$21_Y + end + attribute \src "ls180.v:2826.10-2826.96" + cell $or $or$ls180.v:2826$32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface1_converted_interface_ack + connect \B \main_libresocsim_converter1_skip + connect \Y $or$ls180.v:2826$32_Y + end + attribute \src "ls180.v:2886.10-2886.96" + cell $or $or$ls180.v:2886$43 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface2_converted_interface_ack + connect \B \main_libresocsim_converter2_skip + connect \Y $or$ls180.v:2886$43_Y + end + attribute \src "ls180.v:3083.39-3083.105" + cell $or $or$ls180.v:3083$76 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_start0 + connect \B $ne$ls180.v:3083$75_Y + connect \Y $or$ls180.v:3083$76_Y + end + attribute \src "ls180.v:3126.59-3126.140" + cell $or $or$ls180.v:3126$80 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_req_wdata_ready + connect \B \main_sdram_bankmachine0_req_rdata_valid + connect \Y $or$ls180.v:3126$80_Y + end + attribute \src "ls180.v:3127.44-3127.151" + cell $or $or$ls180.v:3127$81 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $or$ls180.v:3127$81_Y + end + attribute \src "ls180.v:3135.45-3135.170" + cell $or $or$ls180.v:3135$85 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3135$84_Y + connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3135$85_Y + end + attribute \src "ls180.v:3172.127-3172.245" + cell $or $or$ls180.v:3172$98 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3172$98_Y + end + attribute \src "ls180.v:3178.57-3178.157" + cell $or $or$ls180.v:3178$104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3178$103_Y + connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready + connect \Y $or$ls180.v:3178$104_Y + end + attribute \src "ls180.v:3283.59-3283.140" + cell $or $or$ls180.v:3283$110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_req_wdata_ready + connect \B \main_sdram_bankmachine1_req_rdata_valid + connect \Y $or$ls180.v:3283$110_Y + end + attribute \src "ls180.v:3284.44-3284.151" + cell $or $or$ls180.v:3284$111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $or$ls180.v:3284$111_Y + end + attribute \src "ls180.v:3292.45-3292.170" + cell $or $or$ls180.v:3292$115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3292$114_Y + connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3292$115_Y + end + attribute \src "ls180.v:3329.127-3329.245" + cell $or $or$ls180.v:3329$128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3329$128_Y + end + attribute \src "ls180.v:3335.57-3335.157" + cell $or $or$ls180.v:3335$134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3335$133_Y + connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready + connect \Y $or$ls180.v:3335$134_Y + end + attribute \src "ls180.v:3440.59-3440.140" + cell $or $or$ls180.v:3440$140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_req_wdata_ready + connect \B \main_sdram_bankmachine2_req_rdata_valid + connect \Y $or$ls180.v:3440$140_Y + end + attribute \src "ls180.v:3441.44-3441.151" + cell $or $or$ls180.v:3441$141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $or$ls180.v:3441$141_Y + end + attribute \src "ls180.v:3449.45-3449.170" + cell $or $or$ls180.v:3449$145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3449$144_Y + connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3449$145_Y + end + attribute \src "ls180.v:3486.127-3486.245" + cell $or $or$ls180.v:3486$158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3486$158_Y + end + attribute \src "ls180.v:3492.57-3492.157" + cell $or $or$ls180.v:3492$164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3492$163_Y + connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready + connect \Y $or$ls180.v:3492$164_Y + end + attribute \src "ls180.v:3597.59-3597.140" + cell $or $or$ls180.v:3597$170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_req_wdata_ready + connect \B \main_sdram_bankmachine3_req_rdata_valid + connect \Y $or$ls180.v:3597$170_Y + end + attribute \src "ls180.v:3598.44-3598.151" + cell $or $or$ls180.v:3598$171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $or$ls180.v:3598$171_Y + end + attribute \src "ls180.v:3606.45-3606.170" + cell $or $or$ls180.v:3606$175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3606$174_Y + connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3606$175_Y + end + attribute \src "ls180.v:3643.127-3643.245" + cell $or $or$ls180.v:3643$188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3643$188_Y + end + attribute \src "ls180.v:3649.57-3649.157" + cell $or $or$ls180.v:3649$194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3649$193_Y + connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready + connect \Y $or$ls180.v:3649$194_Y + end + attribute \src "ls180.v:3748.107-3748.193" + cell $or $or$ls180.v:3748$214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_is_write + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $or$ls180.v:3748$214_Y + end + attribute \src "ls180.v:3751.39-3751.204" + cell $or $or$ls180.v:3751$220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3751$218_Y + connect \B $and$ls180.v:3751$219_Y + connect \Y $or$ls180.v:3751$220_Y + end + attribute \src "ls180.v:3751.38-3751.289" + cell $or $or$ls180.v:3751$222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3751$220_Y + connect \B $and$ls180.v:3751$221_Y + connect \Y $or$ls180.v:3751$222_Y + end + attribute \src "ls180.v:3751.37-3751.374" + cell $or $or$ls180.v:3751$224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3751$222_Y + connect \B $and$ls180.v:3751$223_Y + connect \Y $or$ls180.v:3751$224_Y + end + attribute \src "ls180.v:3752.40-3752.207" + cell $or $or$ls180.v:3752$227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3752$225_Y + connect \B $and$ls180.v:3752$226_Y + connect \Y $or$ls180.v:3752$227_Y + end + attribute \src "ls180.v:3752.39-3752.293" + cell $or $or$ls180.v:3752$229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3752$227_Y + connect \B $and$ls180.v:3752$228_Y + connect \Y $or$ls180.v:3752$229_Y + end + attribute \src "ls180.v:3752.38-3752.379" + cell $or $or$ls180.v:3752$231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3752$229_Y + connect \B $and$ls180.v:3752$230_Y + connect \Y $or$ls180.v:3752$231_Y + end + attribute \src "ls180.v:3765.158-3765.332" + cell $or $or$ls180.v:3765$245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3765$244_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3765$245_Y + end + attribute \src "ls180.v:3765.75-3765.506" + cell $or $or$ls180.v:3765$250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3765$246_Y + connect \B $and$ls180.v:3765$249_Y + connect \Y $or$ls180.v:3765$250_Y + end + attribute \src "ls180.v:3766.158-3766.332" + cell $or $or$ls180.v:3766$258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3766$257_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3766$258_Y + end + attribute \src "ls180.v:3766.75-3766.506" + cell $or $or$ls180.v:3766$263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3766$259_Y + connect \B $and$ls180.v:3766$262_Y + connect \Y $or$ls180.v:3766$263_Y + end + attribute \src "ls180.v:3767.158-3767.332" + cell $or $or$ls180.v:3767$271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3767$270_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3767$271_Y + end + attribute \src "ls180.v:3767.75-3767.506" + cell $or $or$ls180.v:3767$276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3767$272_Y + connect \B $and$ls180.v:3767$275_Y + connect \Y $or$ls180.v:3767$276_Y + end + attribute \src "ls180.v:3768.158-3768.332" + cell $or $or$ls180.v:3768$284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3768$283_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3768$284_Y + end + attribute \src "ls180.v:3768.75-3768.506" + cell $or $or$ls180.v:3768$289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3768$285_Y + connect \B $and$ls180.v:3768$288_Y + connect \Y $or$ls180.v:3768$289_Y + end + attribute \src "ls180.v:3795.36-3795.104" + cell $or $or$ls180.v:3795$295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_ready + connect \B $not$ls180.v:3795$294_Y + connect \Y $or$ls180.v:3795$295_Y + end + attribute \src "ls180.v:3798.158-3798.332" + cell $or $or$ls180.v:3798$303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3798$302_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:3798$303_Y + end + attribute \src "ls180.v:3798.75-3798.506" + cell $or $or$ls180.v:3798$308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3798$304_Y + connect \B $and$ls180.v:3798$307_Y + connect \Y $or$ls180.v:3798$308_Y + end + attribute \src "ls180.v:3799.158-3799.332" + cell $or $or$ls180.v:3799$316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3799$315_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:3799$316_Y + end + attribute \src "ls180.v:3799.75-3799.506" + cell $or $or$ls180.v:3799$321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3799$317_Y + connect \B $and$ls180.v:3799$320_Y + connect \Y $or$ls180.v:3799$321_Y + end + attribute \src "ls180.v:3800.158-3800.332" + cell $or $or$ls180.v:3800$329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3800$328_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:3800$329_Y + end + attribute \src "ls180.v:3800.75-3800.506" + cell $or $or$ls180.v:3800$334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3800$330_Y + connect \B $and$ls180.v:3800$333_Y + connect \Y $or$ls180.v:3800$334_Y + end + attribute \src "ls180.v:3801.158-3801.332" + cell $or $or$ls180.v:3801$342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3801$341_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:3801$342_Y + end + attribute \src "ls180.v:3801.75-3801.506" + cell $or $or$ls180.v:3801$347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3801$343_Y + connect \B $and$ls180.v:3801$346_Y + connect \Y $or$ls180.v:3801$347_Y + end + attribute \src "ls180.v:3864.36-3864.104" + cell $or $or$ls180.v:3864$381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_ready + connect \B $not$ls180.v:3864$380_Y + connect \Y $or$ls180.v:3864$381_Y + end + attribute \src "ls180.v:3885.67-3885.221" + cell $or $or$ls180.v:3885$388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3885$387_Y + connect \B \main_sdram_ras_allowed + connect \Y $or$ls180.v:3885$388_Y + end + attribute \src "ls180.v:3893.10-3893.62" + cell $or $or$ls180.v:3893$391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3893$390_Y + connect \B \main_sdram_max_time1 + connect \Y $or$ls180.v:3893$391_Y + end + attribute \src "ls180.v:3923.67-3923.221" + cell $or $or$ls180.v:3923$397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3923$396_Y + connect \B \main_sdram_ras_allowed + connect \Y $or$ls180.v:3923$397_Y + end + attribute \src "ls180.v:3931.10-3931.61" + cell $or $or$ls180.v:3931$400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3931$399_Y + connect \B \main_sdram_max_time0 + connect \Y $or$ls180.v:3931$400_Y + end + attribute \src "ls180.v:3941.91-3941.180" + cell $or $or$ls180.v:3941$404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$ls180.v:3941$403_Y + connect \Y $or$ls180.v:3941$404_Y + end + attribute \src "ls180.v:3941.90-3941.255" + cell $or $or$ls180.v:3941$407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3941$404_Y + connect \B $and$ls180.v:3941$406_Y + connect \Y $or$ls180.v:3941$407_Y + end + attribute \src "ls180.v:3941.89-3941.330" + cell $or $or$ls180.v:3941$410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3941$407_Y + connect \B $and$ls180.v:3941$409_Y + connect \Y $or$ls180.v:3941$410_Y + end + attribute \src "ls180.v:3946.91-3946.180" + cell $or $or$ls180.v:3946$420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$ls180.v:3946$419_Y + connect \Y $or$ls180.v:3946$420_Y + end + attribute \src "ls180.v:3946.90-3946.255" + cell $or $or$ls180.v:3946$423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3946$420_Y + connect \B $and$ls180.v:3946$422_Y + connect \Y $or$ls180.v:3946$423_Y + end + attribute \src "ls180.v:3946.89-3946.330" + cell $or $or$ls180.v:3946$426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3946$423_Y + connect \B $and$ls180.v:3946$425_Y + connect \Y $or$ls180.v:3946$426_Y + end + attribute \src "ls180.v:3951.91-3951.180" + cell $or $or$ls180.v:3951$436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$ls180.v:3951$435_Y + connect \Y $or$ls180.v:3951$436_Y + end + attribute \src "ls180.v:3951.90-3951.255" + cell $or $or$ls180.v:3951$439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3951$436_Y + connect \B $and$ls180.v:3951$438_Y + connect \Y $or$ls180.v:3951$439_Y + end + attribute \src "ls180.v:3951.89-3951.330" + cell $or $or$ls180.v:3951$442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3951$439_Y + connect \B $and$ls180.v:3951$441_Y + connect \Y $or$ls180.v:3951$442_Y + end + attribute \src "ls180.v:3956.91-3956.180" + cell $or $or$ls180.v:3956$452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$ls180.v:3956$451_Y + connect \Y $or$ls180.v:3956$452_Y + end + attribute \src "ls180.v:3956.90-3956.255" + cell $or $or$ls180.v:3956$455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3956$452_Y + connect \B $and$ls180.v:3956$454_Y + connect \Y $or$ls180.v:3956$455_Y + end + attribute \src "ls180.v:3956.89-3956.330" + cell $or $or$ls180.v:3956$458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3956$455_Y + connect \B $and$ls180.v:3956$457_Y + connect \Y $or$ls180.v:3956$458_Y + end + attribute \src "ls180.v:3961.132-3961.221" + cell $or $or$ls180.v:3961$469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$ls180.v:3961$468_Y + connect \Y $or$ls180.v:3961$469_Y + end + attribute \src "ls180.v:3961.131-3961.296" + cell $or $or$ls180.v:3961$472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3961$469_Y + connect \B $and$ls180.v:3961$471_Y + connect \Y $or$ls180.v:3961$472_Y + end + attribute \src "ls180.v:3961.130-3961.371" + cell $or $or$ls180.v:3961$475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3961$472_Y + connect \B $and$ls180.v:3961$474_Y + connect \Y $or$ls180.v:3961$475_Y + end + attribute \src "ls180.v:3961.34-3961.411" + cell $or $or$ls180.v:3961$480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$ls180.v:3961$479_Y + connect \Y $or$ls180.v:3961$480_Y + end + attribute \src "ls180.v:3961.506-3961.595" + cell $or $or$ls180.v:3961$485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$ls180.v:3961$484_Y + connect \Y $or$ls180.v:3961$485_Y + end + attribute \src "ls180.v:3961.505-3961.670" + cell $or $or$ls180.v:3961$488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3961$485_Y + connect \B $and$ls180.v:3961$487_Y + connect \Y $or$ls180.v:3961$488_Y + end + attribute \src "ls180.v:3961.504-3961.745" + cell $or $or$ls180.v:3961$491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3961$488_Y + connect \B $and$ls180.v:3961$490_Y + connect \Y $or$ls180.v:3961$491_Y + end + attribute \src "ls180.v:3961.33-3961.785" + cell $or $or$ls180.v:3961$496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3961$480_Y + connect \B $and$ls180.v:3961$495_Y + connect \Y $or$ls180.v:3961$496_Y + end + attribute \src "ls180.v:3961.880-3961.969" + cell $or $or$ls180.v:3961$501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$ls180.v:3961$500_Y + connect \Y $or$ls180.v:3961$501_Y + end + attribute \src "ls180.v:3961.879-3961.1044" + cell $or $or$ls180.v:3961$504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3961$501_Y + connect \B $and$ls180.v:3961$503_Y + connect \Y $or$ls180.v:3961$504_Y + end + attribute \src "ls180.v:3961.878-3961.1119" + cell $or $or$ls180.v:3961$507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3961$504_Y + connect \B $and$ls180.v:3961$506_Y + connect \Y $or$ls180.v:3961$507_Y + end + attribute \src "ls180.v:3961.32-3961.1159" + cell $or $or$ls180.v:3961$512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3961$496_Y + connect \B $and$ls180.v:3961$511_Y + connect \Y $or$ls180.v:3961$512_Y + end + attribute \src "ls180.v:3961.1254-3961.1343" + cell $or $or$ls180.v:3961$517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$ls180.v:3961$516_Y + connect \Y $or$ls180.v:3961$517_Y + end + attribute \src "ls180.v:3961.1253-3961.1418" + cell $or $or$ls180.v:3961$520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3961$517_Y + connect \B $and$ls180.v:3961$519_Y + connect \Y $or$ls180.v:3961$520_Y + end + attribute \src "ls180.v:3961.1252-3961.1493" + cell $or $or$ls180.v:3961$523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3961$520_Y + connect \B $and$ls180.v:3961$522_Y + connect \Y $or$ls180.v:3961$523_Y + end + attribute \src "ls180.v:3961.31-3961.1533" + cell $or $or$ls180.v:3961$528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3961$512_Y + connect \B $and$ls180.v:3961$527_Y + connect \Y $or$ls180.v:3961$528_Y + end + attribute \src "ls180.v:4024.10-4024.52" + cell $or $or$ls180.v:4024$537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_ack + connect \B \main_converter_skip + connect \Y $or$ls180.v:4024$537_Y + end + attribute \src "ls180.v:4051.35-4051.74" + cell $or $or$ls180.v:4051$547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_cmd_consumed + connect \Y $or$ls180.v:4051$547_Y + end + attribute \src "ls180.v:4052.34-4052.73" + cell $or $or$ls180.v:4052$551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_cmd_consumed + connect \Y $or$ls180.v:4052$551_Y + end + attribute \src "ls180.v:4053.48-4053.130" + cell $or $or$ls180.v:4053$557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4053$554_Y + connect \B $and$ls180.v:4053$556_Y + connect \Y $or$ls180.v:4053$557_Y + end + attribute \src "ls180.v:4054.24-4054.87" + cell $or $or$ls180.v:4054$560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4054$559_Y + connect \B \main_cmd_consumed + connect \Y $or$ls180.v:4054$560_Y + end + attribute \src "ls180.v:4055.26-4055.95" + cell $or $or$ls180.v:4055$562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4055$561_Y + connect \B \main_wdata_consumed + connect \Y $or$ls180.v:4055$562_Y + end + attribute \src "ls180.v:4085.42-4085.89" + cell $or $or$ls180.v:4085$570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_clear + connect \B $and$ls180.v:4085$569_Y + connect \Y $or$ls180.v:4085$570_Y + end + attribute \src "ls180.v:4109.25-4109.174" + cell $or $or$ls180.v:4109$580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4109$578_Y + connect \B $and$ls180.v:4109$579_Y + connect \Y $or$ls180.v:4109$580_Y + end + attribute \src "ls180.v:4124.80-4124.132" + cell $or $or$ls180.v:4124$582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4124$581_Y + connect \B \main_uart_tx_fifo_re + connect \Y $or$ls180.v:4124$582_Y + end + attribute \src "ls180.v:4135.72-4135.135" + cell $or $or$ls180.v:4135$587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_writable + connect \B \main_uart_tx_fifo_replace + connect \Y $or$ls180.v:4135$587_Y + end + attribute \src "ls180.v:4154.80-4154.132" + cell $or $or$ls180.v:4154$593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4154$592_Y + connect \B \main_uart_rx_fifo_re + connect \Y $or$ls180.v:4154$593_Y + end + attribute \src "ls180.v:4165.72-4165.135" + cell $or $or$ls180.v:4165$598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_writable + connect \B \main_uart_rx_fifo_replace + connect \Y $or$ls180.v:4165$598_Y + end + attribute \src "ls180.v:4236.36-4236.111" + cell $or $or$ls180.v:4236$611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_clk + connect \B \main_sdphy_cmdw_pads_out_payload_clk + connect \Y $or$ls180.v:4236$611_Y + end + attribute \src "ls180.v:4236.35-4236.151" + cell $or $or$ls180.v:4236$612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4236$611_Y + connect \B \main_sdphy_cmdr_pads_out_payload_clk + connect \Y $or$ls180.v:4236$612_Y + end + attribute \src "ls180.v:4236.34-4236.192" + cell $or $or$ls180.v:4236$613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4236$612_Y + connect \B \main_sdphy_dataw_pads_out_payload_clk + connect \Y $or$ls180.v:4236$613_Y + end + attribute \src "ls180.v:4236.33-4236.233" + cell $or $or$ls180.v:4236$614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4236$613_Y + connect \B \main_sdphy_datar_pads_out_payload_clk + connect \Y $or$ls180.v:4236$614_Y + end + attribute \src "ls180.v:4237.39-4237.120" + cell $or $or$ls180.v:4237$615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_cmd_oe + connect \B \main_sdphy_cmdw_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4237$615_Y + end + attribute \src "ls180.v:4237.38-4237.163" + cell $or $or$ls180.v:4237$616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4237$615_Y + connect \B \main_sdphy_cmdr_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4237$616_Y + end + attribute \src "ls180.v:4237.37-4237.207" + cell $or $or$ls180.v:4237$617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4237$616_Y + connect \B \main_sdphy_dataw_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4237$617_Y + end + attribute \src "ls180.v:4237.36-4237.251" + cell $or $or$ls180.v:4237$618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4237$617_Y + connect \B \main_sdphy_datar_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4237$618_Y + end + attribute \src "ls180.v:4238.38-4238.117" + cell $or $or$ls180.v:4238$619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_cmd_o + connect \B \main_sdphy_cmdw_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4238$619_Y + end + attribute \src "ls180.v:4238.37-4238.159" + cell $or $or$ls180.v:4238$620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4238$619_Y + connect \B \main_sdphy_cmdr_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4238$620_Y + end + attribute \src "ls180.v:4238.36-4238.202" + cell $or $or$ls180.v:4238$621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4238$620_Y + connect \B \main_sdphy_dataw_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4238$621_Y + end + attribute \src "ls180.v:4238.35-4238.245" + cell $or $or$ls180.v:4238$622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4238$621_Y + connect \B \main_sdphy_datar_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4238$622_Y + end + attribute \src "ls180.v:4239.40-4239.123" + cell $or $or$ls180.v:4239$623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_data_oe + connect \B \main_sdphy_cmdw_pads_out_payload_data_oe + connect \Y $or$ls180.v:4239$623_Y + end + attribute \src "ls180.v:4239.39-4239.167" + cell $or $or$ls180.v:4239$624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4239$623_Y + connect \B \main_sdphy_cmdr_pads_out_payload_data_oe + connect \Y $or$ls180.v:4239$624_Y + end + attribute \src "ls180.v:4239.38-4239.212" + cell $or $or$ls180.v:4239$625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4239$624_Y + connect \B \main_sdphy_dataw_pads_out_payload_data_oe + connect \Y $or$ls180.v:4239$625_Y + end + attribute \src "ls180.v:4239.37-4239.257" + cell $or $or$ls180.v:4239$626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4239$625_Y + connect \B \main_sdphy_datar_pads_out_payload_data_oe + connect \Y $or$ls180.v:4239$626_Y + end + attribute \src "ls180.v:4240.39-4240.120" + cell $or $or$ls180.v:4240$627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \main_sdphy_init_pads_out_payload_data_o + connect \B \main_sdphy_cmdw_pads_out_payload_data_o + connect \Y $or$ls180.v:4240$627_Y + end + attribute \src "ls180.v:4240.38-4240.163" + cell $or $or$ls180.v:4240$628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$ls180.v:4240$627_Y + connect \B \main_sdphy_cmdr_pads_out_payload_data_o + connect \Y $or$ls180.v:4240$628_Y + end + attribute \src "ls180.v:4240.37-4240.207" + cell $or $or$ls180.v:4240$629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$ls180.v:4240$628_Y + connect \B \main_sdphy_dataw_pads_out_payload_data_o + connect \Y $or$ls180.v:4240$629_Y + end + attribute \src "ls180.v:4240.36-4240.251" + cell $or $or$ls180.v:4240$630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$ls180.v:4240$629_Y + connect \B \main_sdphy_datar_pads_out_payload_data_o + connect \Y $or$ls180.v:4240$630_Y + end + attribute \src "ls180.v:4261.35-4261.80" + cell $or $or$ls180.v:4261$631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_stop + connect \B \main_sdphy_datar_stop + connect \Y $or$ls180.v:4261$631_Y + end + attribute \src "ls180.v:4415.91-4415.144" + cell $or $or$ls180.v:4415$645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_start + connect \B \main_sdphy_cmdr_cmdr_run + connect \Y $or$ls180.v:4415$645_Y + end + attribute \src "ls180.v:4432.53-4432.143" + cell $or $or$ls180.v:4432$648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4432$647_Y + connect \B \main_sdphy_cmdr_cmdr_converter_source_ready + connect \Y $or$ls180.v:4432$648_Y + end + attribute \src "ls180.v:4435.47-4435.127" + cell $or $or$ls180.v:4435$651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4435$650_Y + connect \B \main_sdphy_cmdr_cmdr_buf_source_ready + connect \Y $or$ls180.v:4435$651_Y + end + attribute \src "ls180.v:4559.54-4559.146" + cell $or $or$ls180.v:4559$669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4559$668_Y + connect \B \main_sdphy_dataw_crcr_converter_source_ready + connect \Y $or$ls180.v:4559$669_Y + end + attribute \src "ls180.v:4562.48-4562.130" + cell $or $or$ls180.v:4562$672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4562$671_Y + connect \B \main_sdphy_dataw_crcr_buf_source_ready + connect \Y $or$ls180.v:4562$672_Y + end + attribute \src "ls180.v:4693.55-4693.149" + cell $or $or$ls180.v:4693$684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4693$683_Y + connect \B \main_sdphy_datar_datar_converter_source_ready + connect \Y $or$ls180.v:4693$684_Y + end + attribute \src "ls180.v:4696.49-4696.133" + cell $or $or$ls180.v:4696$687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4696$686_Y + connect \B \main_sdphy_datar_datar_buf_source_ready + connect \Y $or$ls180.v:4696$687_Y + end + attribute \src "ls180.v:5325.80-5325.151" + cell $or $or$ls180.v:5325$982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_writable + connect \B \main_sdblock2mem_fifo_replace + connect \Y $or$ls180.v:5325$982_Y + end + attribute \src "ls180.v:5336.49-5336.131" + cell $or $or$ls180.v:5336$988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:5336$987_Y + connect \B \main_sdblock2mem_converter_source_ready + connect \Y $or$ls180.v:5336$988_Y + end + attribute \src "ls180.v:5533.80-5533.151" + cell $or $or$ls180.v:5533$1013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_writable + connect \B \main_sdmem2block_fifo_replace + connect \Y $or$ls180.v:5533$1013_Y + end + attribute \src "ls180.v:5707.33-5707.102" + cell $or $or$ls180.v:5707$1061 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_err + connect \B \main_libresocsim_libresoc_xics_icp_err + connect \Y $or$ls180.v:5707$1061_Y + end + attribute \src "ls180.v:5707.32-5707.144" + cell $or $or$ls180.v:5707$1062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5707$1061_Y + connect \B \main_libresocsim_libresoc_xics_ics_err + connect \Y $or$ls180.v:5707$1062_Y + end + attribute \src "ls180.v:5707.31-5707.165" + cell $or $or$ls180.v:5707$1063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5707$1062_Y + connect \B \main_wb_sdram_err + connect \Y $or$ls180.v:5707$1063_Y + end + attribute \src "ls180.v:5707.30-5707.201" + cell $or $or$ls180.v:5707$1064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5707$1063_Y + connect \B \builder_libresocsim_wishbone_err + connect \Y $or$ls180.v:5707$1064_Y + end + attribute \src "ls180.v:5713.28-5713.97" + cell $or $or$ls180.v:5713$1069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_ack + connect \B \main_libresocsim_libresoc_xics_icp_ack + connect \Y $or$ls180.v:5713$1069_Y + end + attribute \src "ls180.v:5713.27-5713.139" + cell $or $or$ls180.v:5713$1070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5713$1069_Y + connect \B \main_libresocsim_libresoc_xics_ics_ack + connect \Y $or$ls180.v:5713$1070_Y + end + attribute \src "ls180.v:5713.26-5713.160" + cell $or $or$ls180.v:5713$1071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5713$1070_Y + connect \B \main_wb_sdram_ack + connect \Y $or$ls180.v:5713$1071_Y + end + attribute \src "ls180.v:5713.25-5713.196" + cell $or $or$ls180.v:5713$1072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5713$1071_Y + connect \B \builder_libresocsim_wishbone_ack + connect \Y $or$ls180.v:5713$1072_Y + end + attribute \src "ls180.v:5714.30-5714.169" + cell $or $or$ls180.v:5714$1075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $and$ls180.v:5714$1073_Y + connect \B $and$ls180.v:5714$1074_Y + connect \Y $or$ls180.v:5714$1075_Y + end + attribute \src "ls180.v:5714.29-5714.246" + cell $or $or$ls180.v:5714$1077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $or$ls180.v:5714$1075_Y + connect \B $and$ls180.v:5714$1076_Y + connect \Y $or$ls180.v:5714$1077_Y + end + attribute \src "ls180.v:5714.28-5714.302" + cell $or $or$ls180.v:5714$1079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $or$ls180.v:5714$1077_Y + connect \B $and$ls180.v:5714$1078_Y + connect \Y $or$ls180.v:5714$1079_Y + end + attribute \src "ls180.v:5714.27-5714.373" + cell $or $or$ls180.v:5714$1081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $or$ls180.v:5714$1079_Y + connect \B $and$ls180.v:5714$1080_Y + connect \Y $or$ls180.v:5714$1081_Y + end + attribute \src "ls180.v:6451.54-6451.123" + cell $or $or$ls180.v:6451$2212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \builder_interface0_bank_bus_dat_r + connect \B \builder_interface1_bank_bus_dat_r + connect \Y $or$ls180.v:6451$2212_Y + end + attribute \src "ls180.v:6451.53-6451.160" + cell $or $or$ls180.v:6451$2213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6451$2212_Y + connect \B \builder_interface2_bank_bus_dat_r + connect \Y $or$ls180.v:6451$2213_Y + end + attribute \src "ls180.v:6451.52-6451.197" + cell $or $or$ls180.v:6451$2214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6451$2213_Y + connect \B \builder_interface3_bank_bus_dat_r + connect \Y $or$ls180.v:6451$2214_Y + end + attribute \src "ls180.v:6451.51-6451.234" + cell $or $or$ls180.v:6451$2215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6451$2214_Y + connect \B \builder_interface4_bank_bus_dat_r + connect \Y $or$ls180.v:6451$2215_Y + end + attribute \src "ls180.v:6451.50-6451.271" + cell $or $or$ls180.v:6451$2216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6451$2215_Y + connect \B \builder_interface5_bank_bus_dat_r + connect \Y $or$ls180.v:6451$2216_Y + end + attribute \src "ls180.v:6451.49-6451.308" + cell $or $or$ls180.v:6451$2217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6451$2216_Y + connect \B \builder_interface6_bank_bus_dat_r + connect \Y $or$ls180.v:6451$2217_Y + end + attribute \src "ls180.v:6451.48-6451.345" + cell $or $or$ls180.v:6451$2218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6451$2217_Y + connect \B \builder_interface7_bank_bus_dat_r + connect \Y $or$ls180.v:6451$2218_Y + end + attribute \src "ls180.v:6451.47-6451.382" + cell $or $or$ls180.v:6451$2219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6451$2218_Y + connect \B \builder_interface8_bank_bus_dat_r + connect \Y $or$ls180.v:6451$2219_Y + end + attribute \src "ls180.v:6451.46-6451.419" + cell $or $or$ls180.v:6451$2220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6451$2219_Y + connect \B \builder_interface9_bank_bus_dat_r + connect \Y $or$ls180.v:6451$2220_Y + end + attribute \src "ls180.v:6451.45-6451.457" + cell $or $or$ls180.v:6451$2221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6451$2220_Y + connect \B \builder_interface10_bank_bus_dat_r + connect \Y $or$ls180.v:6451$2221_Y + end + attribute \src "ls180.v:6451.44-6451.495" + cell $or $or$ls180.v:6451$2222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6451$2221_Y + connect \B \builder_interface11_bank_bus_dat_r + connect \Y $or$ls180.v:6451$2222_Y + end + attribute \src "ls180.v:6451.43-6451.533" + cell $or $or$ls180.v:6451$2223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6451$2222_Y + connect \B \builder_interface12_bank_bus_dat_r + connect \Y $or$ls180.v:6451$2223_Y + end + attribute \src "ls180.v:6451.42-6451.571" + cell $or $or$ls180.v:6451$2224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6451$2223_Y + connect \B \builder_interface13_bank_bus_dat_r + connect \Y $or$ls180.v:6451$2224_Y + end + attribute \src "ls180.v:6778.90-6778.179" + cell $or $or$ls180.v:6778$2249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$ls180.v:6778$2248_Y + connect \Y $or$ls180.v:6778$2249_Y + end + attribute \src "ls180.v:6778.89-6778.254" + cell $or $or$ls180.v:6778$2252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6778$2249_Y + connect \B $and$ls180.v:6778$2251_Y + connect \Y $or$ls180.v:6778$2252_Y + end + attribute \src "ls180.v:6778.88-6778.329" + cell $or $or$ls180.v:6778$2255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6778$2252_Y + connect \B $and$ls180.v:6778$2254_Y + connect \Y $or$ls180.v:6778$2255_Y + end + attribute \src "ls180.v:6802.90-6802.179" + cell $or $or$ls180.v:6802$2265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$ls180.v:6802$2264_Y + connect \Y $or$ls180.v:6802$2265_Y + end + attribute \src "ls180.v:6802.89-6802.254" + cell $or $or$ls180.v:6802$2268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6802$2265_Y + connect \B $and$ls180.v:6802$2267_Y + connect \Y $or$ls180.v:6802$2268_Y + end + attribute \src "ls180.v:6802.88-6802.329" + cell $or $or$ls180.v:6802$2271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6802$2268_Y + connect \B $and$ls180.v:6802$2270_Y + connect \Y $or$ls180.v:6802$2271_Y + end + attribute \src "ls180.v:6826.90-6826.179" + cell $or $or$ls180.v:6826$2281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$ls180.v:6826$2280_Y + connect \Y $or$ls180.v:6826$2281_Y + end + attribute \src "ls180.v:6826.89-6826.254" + cell $or $or$ls180.v:6826$2284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6826$2281_Y + connect \B $and$ls180.v:6826$2283_Y + connect \Y $or$ls180.v:6826$2284_Y + end + attribute \src "ls180.v:6826.88-6826.329" + cell $or $or$ls180.v:6826$2287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6826$2284_Y + connect \B $and$ls180.v:6826$2286_Y + connect \Y $or$ls180.v:6826$2287_Y + end + attribute \src "ls180.v:6850.90-6850.179" + cell $or $or$ls180.v:6850$2297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$ls180.v:6850$2296_Y + connect \Y $or$ls180.v:6850$2297_Y + end + attribute \src "ls180.v:6850.89-6850.254" + cell $or $or$ls180.v:6850$2300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6850$2297_Y + connect \B $and$ls180.v:6850$2299_Y + connect \Y $or$ls180.v:6850$2300_Y + end + attribute \src "ls180.v:6850.88-6850.329" + cell $or $or$ls180.v:6850$2303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6850$2300_Y + connect \B $and$ls180.v:6850$2302_Y + connect \Y $or$ls180.v:6850$2303_Y + end + attribute \src "ls180.v:7360.20-7360.71" + cell $or $or$ls180.v:7360$2360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [0] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7360$2360_Y + end + attribute \src "ls180.v:7361.20-7361.71" + cell $or $or$ls180.v:7361$2361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [1] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7361$2361_Y + end + attribute \src "ls180.v:7362.20-7362.71" + cell $or $or$ls180.v:7362$2362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [2] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7362$2362_Y + end + attribute \src "ls180.v:7363.20-7363.71" + cell $or $or$ls180.v:7363$2363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [3] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7363$2363_Y + end + attribute \src "ls180.v:7364.20-7364.71" + cell $or $or$ls180.v:7364$2364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [4] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7364$2364_Y + end + attribute \src "ls180.v:7365.20-7365.71" + cell $or $or$ls180.v:7365$2365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [5] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7365$2365_Y + end + attribute \src "ls180.v:7366.20-7366.71" + cell $or $or$ls180.v:7366$2366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [6] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7366$2366_Y + end + attribute \src "ls180.v:7367.20-7367.71" + cell $or $or$ls180.v:7367$2367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [7] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7367$2367_Y + end + attribute \src "ls180.v:7368.20-7368.71" + cell $or $or$ls180.v:7368$2368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [8] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7368$2368_Y + end + attribute \src "ls180.v:7369.20-7369.71" + cell $or $or$ls180.v:7369$2369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [9] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7369$2369_Y + end + attribute \src "ls180.v:7370.21-7370.73" + cell $or $or$ls180.v:7370$2370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [10] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7370$2370_Y + end + attribute \src "ls180.v:7371.21-7371.73" + cell $or $or$ls180.v:7371$2371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [11] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7371$2371_Y + end + attribute \src "ls180.v:7372.21-7372.73" + cell $or $or$ls180.v:7372$2372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [12] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7372$2372_Y + end + attribute \src "ls180.v:7373.21-7373.73" + cell $or $or$ls180.v:7373$2373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [13] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7373$2373_Y + end + attribute \src "ls180.v:7374.21-7374.73" + cell $or $or$ls180.v:7374$2374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [14] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7374$2374_Y + end + attribute \src "ls180.v:7375.21-7375.73" + cell $or $or$ls180.v:7375$2375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [15] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7375$2375_Y + end + attribute \src "ls180.v:7376.21-7376.73" + cell $or $or$ls180.v:7376$2376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [16] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7376$2376_Y + end + attribute \src "ls180.v:7377.21-7377.73" + cell $or $or$ls180.v:7377$2377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [17] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7377$2377_Y + end + attribute \src "ls180.v:7378.21-7378.73" + cell $or $or$ls180.v:7378$2378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [18] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7378$2378_Y + end + attribute \src "ls180.v:7379.21-7379.73" + cell $or $or$ls180.v:7379$2379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [19] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7379$2379_Y + end + attribute \src "ls180.v:7380.21-7380.73" + cell $or $or$ls180.v:7380$2380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [20] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7380$2380_Y + end + attribute \src "ls180.v:7381.21-7381.73" + cell $or $or$ls180.v:7381$2381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [21] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7381$2381_Y + end + attribute \src "ls180.v:7382.21-7382.73" + cell $or $or$ls180.v:7382$2382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [22] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7382$2382_Y + end + attribute \src "ls180.v:7383.21-7383.73" + cell $or $or$ls180.v:7383$2383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [23] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7383$2383_Y + end + attribute \src "ls180.v:7384.21-7384.73" + cell $or $or$ls180.v:7384$2384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [24] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7384$2384_Y + end + attribute \src "ls180.v:7385.21-7385.73" + cell $or $or$ls180.v:7385$2385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [25] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7385$2385_Y + end + attribute \src "ls180.v:7386.21-7386.73" + cell $or $or$ls180.v:7386$2386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [26] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7386$2386_Y + end + attribute \src "ls180.v:7387.21-7387.73" + cell $or $or$ls180.v:7387$2387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [27] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7387$2387_Y + end + attribute \src "ls180.v:7388.21-7388.73" + cell $or $or$ls180.v:7388$2388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [28] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7388$2388_Y + end + attribute \src "ls180.v:7389.21-7389.73" + cell $or $or$ls180.v:7389$2389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [29] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7389$2389_Y + end + attribute \src "ls180.v:7390.21-7390.73" + cell $or $or$ls180.v:7390$2390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [30] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7390$2390_Y + end + attribute \src "ls180.v:7391.21-7391.73" + cell $or $or$ls180.v:7391$2391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [31] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7391$2391_Y + end + attribute \src "ls180.v:7392.21-7392.73" + cell $or $or$ls180.v:7392$2392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [32] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7392$2392_Y + end + attribute \src "ls180.v:7393.21-7393.73" + cell $or $or$ls180.v:7393$2393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [33] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7393$2393_Y + end + attribute \src "ls180.v:7394.21-7394.73" + cell $or $or$ls180.v:7394$2394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [34] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7394$2394_Y + end + attribute \src "ls180.v:7395.21-7395.73" + cell $or $or$ls180.v:7395$2395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [35] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7395$2395_Y + end + attribute \src "ls180.v:7396.21-7396.73" + cell $or $or$ls180.v:7396$2396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [36] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7396$2396_Y + end + attribute \src "ls180.v:7397.21-7397.73" + cell $or $or$ls180.v:7397$2397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [37] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7397$2397_Y + end + attribute \src "ls180.v:7398.21-7398.73" + cell $or $or$ls180.v:7398$2398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [38] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7398$2398_Y + end + attribute \src "ls180.v:7399.21-7399.73" + cell $or $or$ls180.v:7399$2399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [39] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7399$2399_Y + end + attribute \src "ls180.v:7400.21-7400.73" + cell $or $or$ls180.v:7400$2400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [40] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7400$2400_Y + end + attribute \src "ls180.v:7401.21-7401.73" + cell $or $or$ls180.v:7401$2401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [41] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7401$2401_Y + end + attribute \src "ls180.v:7402.21-7402.73" + cell $or $or$ls180.v:7402$2402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [42] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7402$2402_Y + end + attribute \src "ls180.v:7403.7-7403.93" + cell $or $or$ls180.v:7403$2403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface0_converted_interface_ack + connect \B \main_libresocsim_converter0_skip + connect \Y $or$ls180.v:7403$2403_Y + end + attribute \src "ls180.v:7414.7-7414.93" + cell $or $or$ls180.v:7414$2404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface1_converted_interface_ack + connect \B \main_libresocsim_converter1_skip + connect \Y $or$ls180.v:7414$2404_Y + end + attribute \src "ls180.v:7425.7-7425.93" + cell $or $or$ls180.v:7425$2405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface2_converted_interface_ack + connect \B \main_libresocsim_converter2_skip + connect \Y $or$ls180.v:7425$2405_Y + end + attribute \src "ls180.v:7556.7-7556.107" + cell $or $or$ls180.v:7556$2441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7556$2440_Y + connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready + connect \Y $or$ls180.v:7556$2441_Y + end + attribute \src "ls180.v:7602.7-7602.107" + cell $or $or$ls180.v:7602$2457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7602$2456_Y + connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready + connect \Y $or$ls180.v:7602$2457_Y + end + attribute \src "ls180.v:7648.7-7648.107" + cell $or $or$ls180.v:7648$2473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7648$2472_Y + connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready + connect \Y $or$ls180.v:7648$2473_Y + end + attribute \src "ls180.v:7694.7-7694.107" + cell $or $or$ls180.v:7694$2489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7694$2488_Y + connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready + connect \Y $or$ls180.v:7694$2489_Y + end + attribute \src "ls180.v:7882.40-7882.125" + cell $or $or$ls180.v:7882$2510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$ls180.v:7882$2509_Y + connect \Y $or$ls180.v:7882$2510_Y + end + attribute \src "ls180.v:7882.39-7882.207" + cell $or $or$ls180.v:7882$2513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7882$2510_Y + connect \B $and$ls180.v:7882$2512_Y + connect \Y $or$ls180.v:7882$2513_Y + end + attribute \src "ls180.v:7882.38-7882.289" + cell $or $or$ls180.v:7882$2516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7882$2513_Y + connect \B $and$ls180.v:7882$2515_Y + connect \Y $or$ls180.v:7882$2516_Y + end + attribute \src "ls180.v:7882.37-7882.371" + cell $or $or$ls180.v:7882$2519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7882$2516_Y + connect \B $and$ls180.v:7882$2518_Y + connect \Y $or$ls180.v:7882$2519_Y + end + attribute \src "ls180.v:7883.41-7883.126" + cell $or $or$ls180.v:7883$2522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$ls180.v:7883$2521_Y + connect \Y $or$ls180.v:7883$2522_Y + end + attribute \src "ls180.v:7883.40-7883.208" + cell $or $or$ls180.v:7883$2525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7883$2522_Y + connect \B $and$ls180.v:7883$2524_Y + connect \Y $or$ls180.v:7883$2525_Y + end + attribute \src "ls180.v:7883.39-7883.290" + cell $or $or$ls180.v:7883$2528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7883$2525_Y + connect \B $and$ls180.v:7883$2527_Y + connect \Y $or$ls180.v:7883$2528_Y + end + attribute \src "ls180.v:7883.38-7883.372" + cell $or $or$ls180.v:7883$2531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7883$2528_Y + connect \B $and$ls180.v:7883$2530_Y + connect \Y $or$ls180.v:7883$2531_Y + end + attribute \src "ls180.v:7887.7-7887.49" + cell $or $or$ls180.v:7887$2532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_ack + connect \B \main_converter_skip + connect \Y $or$ls180.v:7887$2532_Y + end + attribute \src "ls180.v:8050.22-8050.74" + cell $or $or$ls180.v:8050$2580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8050$2578_Y + connect \B $not$ls180.v:8050$2579_Y + connect \Y $or$ls180.v:8050$2580_Y + end + attribute \src "ls180.v:8118.32-8118.85" + cell $or $or$ls180.v:8118$2592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_start + connect \B \main_sdphy_cmdr_cmdr_run + connect \Y $or$ls180.v:8118$2592_Y + end + attribute \src "ls180.v:8124.8-8124.97" + cell $or $or$ls180.v:8124$2594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8124$2593_Y + connect \B \main_sdphy_cmdr_cmdr_converter_sink_last + connect \Y $or$ls180.v:8124$2594_Y + end + attribute \src "ls180.v:8141.52-8141.139" + cell $or $or$ls180.v:8141$2599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_first + connect \B \main_sdphy_cmdr_cmdr_converter_source_first + connect \Y $or$ls180.v:8141$2599_Y + end + attribute \src "ls180.v:8142.51-8142.136" + cell $or $or$ls180.v:8142$2600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_last + connect \B \main_sdphy_cmdr_cmdr_converter_source_last + connect \Y $or$ls180.v:8142$2600_Y + end + attribute \src "ls180.v:8176.7-8176.87" + cell $or $or$ls180.v:8176$2603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8176$2602_Y + connect \B \main_sdphy_cmdr_cmdr_buf_source_ready + connect \Y $or$ls180.v:8176$2603_Y + end + attribute \src "ls180.v:8199.33-8199.88" + cell $or $or$ls180.v:8199$2604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_start + connect \B \main_sdphy_dataw_crcr_run + connect \Y $or$ls180.v:8199$2604_Y + end + attribute \src "ls180.v:8205.8-8205.99" + cell $or $or$ls180.v:8205$2606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8205$2605_Y + connect \B \main_sdphy_dataw_crcr_converter_sink_last + connect \Y $or$ls180.v:8205$2606_Y + end + attribute \src "ls180.v:8222.53-8222.142" + cell $or $or$ls180.v:8222$2611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_first + connect \B \main_sdphy_dataw_crcr_converter_source_first + connect \Y $or$ls180.v:8222$2611_Y + end + attribute \src "ls180.v:8223.52-8223.139" + cell $or $or$ls180.v:8223$2612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_last + connect \B \main_sdphy_dataw_crcr_converter_source_last + connect \Y $or$ls180.v:8223$2612_Y + end + attribute \src "ls180.v:8257.7-8257.89" + cell $or $or$ls180.v:8257$2615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8257$2614_Y + connect \B \main_sdphy_dataw_crcr_buf_source_ready + connect \Y $or$ls180.v:8257$2615_Y + end + attribute \src "ls180.v:8278.34-8278.91" + cell $or $or$ls180.v:8278$2616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_start + connect \B \main_sdphy_datar_datar_run + connect \Y $or$ls180.v:8278$2616_Y + end + attribute \src "ls180.v:8284.8-8284.101" + cell $or $or$ls180.v:8284$2618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8284$2617_Y + connect \B \main_sdphy_datar_datar_converter_sink_last + connect \Y $or$ls180.v:8284$2618_Y + end + attribute \src "ls180.v:8301.54-8301.145" + cell $or $or$ls180.v:8301$2623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_first + connect \B \main_sdphy_datar_datar_converter_source_first + connect \Y $or$ls180.v:8301$2623_Y + end + attribute \src "ls180.v:8302.53-8302.142" + cell $or $or$ls180.v:8302$2624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_last + connect \B \main_sdphy_datar_datar_converter_source_last + connect \Y $or$ls180.v:8302$2624_Y + end + attribute \src "ls180.v:8318.7-8318.91" + cell $or $or$ls180.v:8318$2627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8318$2626_Y + connect \B \main_sdphy_datar_datar_buf_source_ready + connect \Y $or$ls180.v:8318$2627_Y + end + attribute \src "ls180.v:8507.8-8507.89" + cell $or $or$ls180.v:8507$2651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8507$2650_Y + connect \B \main_sdblock2mem_converter_sink_last + connect \Y $or$ls180.v:8507$2651_Y + end + attribute \src "ls180.v:8524.48-8524.127" + cell $or $or$ls180.v:8524$2656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_first + connect \B \main_sdblock2mem_converter_source_first + connect \Y $or$ls180.v:8524$2656_Y + end + attribute \src "ls180.v:8525.47-8525.124" + cell $or $or$ls180.v:8525$2657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_last + connect \B \main_sdblock2mem_converter_source_last + connect \Y $or$ls180.v:8525$2657_Y + end + attribute \src "ls180.v:8598.21-8598.65" + cell $or $or$ls180.v:8598$2675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8598$2673_Y + connect \B $not$ls180.v:8598$2674_Y + connect \Y $or$ls180.v:8598$2675_Y + end + attribute \src "ls180.v:3135.46-3135.94" + cell $sshl $sshl$ls180.v:3135$84 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine0_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3135$84_Y + end + attribute \src "ls180.v:3292.46-3292.94" + cell $sshl $sshl$ls180.v:3292$114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine1_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3292$114_Y + end + attribute \src "ls180.v:3449.46-3449.94" + cell $sshl $sshl$ls180.v:3449$144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine2_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3449$144_Y + end + attribute \src "ls180.v:3606.46-3606.94" + cell $sshl $sshl$ls180.v:3606$174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine3_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3606$174_Y + end + attribute \src "ls180.v:3166.63-3166.122" + cell $sub $sub$ls180.v:3166$97 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3166$97_Y + end + attribute \src "ls180.v:3323.63-3323.122" + cell $sub $sub$ls180.v:3323$127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3323$127_Y + end + attribute \src "ls180.v:3480.63-3480.122" + cell $sub $sub$ls180.v:3480$157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3480$157_Y + end + attribute \src "ls180.v:3637.63-3637.122" + cell $sub $sub$ls180.v:3637$187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3637$187_Y + end + attribute \src "ls180.v:4043.38-4043.75" + cell $sub $sub$ls180.v:4043$541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 30 + parameter \B_SIGNED 0 + parameter \B_WIDTH 31 + parameter \Y_WIDTH 31 + connect \A \main_litedram_wb_adr + connect \B 31'1001000000000000000000000000000 + connect \Y $sub$ls180.v:4043$541_Y + end + attribute \src "ls180.v:4129.36-4129.68" + cell $sub $sub$ls180.v:4129$586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_tx_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:4129$586_Y + end + attribute \src "ls180.v:4159.36-4159.68" + cell $sub $sub$ls180.v:4159$597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_rx_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:4159$597_Y + end + attribute \src "ls180.v:4184.69-4184.110" + cell $sub $sub$ls180.v:4184$603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 15 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spi_master_clk_divider0 [15:1] + connect \B 1'1 + connect \Y $sub$ls180.v:4184$603_Y + end + attribute \src "ls180.v:4185.69-4185.104" + cell $sub $sub$ls180.v:4185$605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spi_master_clk_divider0 + connect \B 1'1 + connect \Y $sub$ls180.v:4185$605_Y + end + attribute \src "ls180.v:4212.36-4212.66" + cell $sub $sub$ls180.v:4212$609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_spi_master_length0 + connect \B 1'1 + connect \Y $sub$ls180.v:4212$609_Y + end + attribute \src "ls180.v:4462.60-4462.90" + cell $sub $sub$ls180.v:4462$653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4462$653_Y + end + attribute \src "ls180.v:4473.62-4473.104" + cell $sub $sub$ls180.v:4473$655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdr_sink_payload_length + connect \B 1'1 + connect \Y $sub$ls180.v:4473$655_Y + end + attribute \src "ls180.v:4490.60-4490.90" + cell $sub $sub$ls180.v:4490$659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4490$659_Y + end + attribute \src "ls180.v:4719.62-4719.93" + cell $sub $sub$ls180.v:4719$689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_datar_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4719$689_Y + end + attribute \src "ls180.v:4724.62-4724.93" + cell $sub $sub$ls180.v:4724$690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_datar_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4724$690_Y + end + attribute \src "ls180.v:4735.64-4735.122" + cell $sub $sub$ls180.v:4735$693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A $add$ls180.v:4735$692_Y + connect \B 1'1 + connect \Y $sub$ls180.v:4735$693_Y + end + attribute \src "ls180.v:4756.62-4756.93" + cell $sub $sub$ls180.v:4756$696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_datar_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4756$696_Y + end + attribute \src "ls180.v:5218.37-5218.75" + cell $sub $sub$ls180.v:5218$969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$ls180.v:5218$969_Y + end + attribute \src "ls180.v:5233.62-5233.100" + cell $sub $sub$ls180.v:5233$972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$ls180.v:5233$972_Y + end + attribute \src "ls180.v:5244.39-5244.77" + cell $sub $sub$ls180.v:5244$977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$ls180.v:5244$977_Y + end + attribute \src "ls180.v:5319.40-5319.76" + cell $sub $sub$ls180.v:5319$981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdblock2mem_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:5319$981_Y + end + attribute \src "ls180.v:5368.56-5368.104" + cell $sub $sub$ls180.v:5368$995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdblock2mem_wishbonedmawriter_length + connect \B 1'1 + connect \Y $sub$ls180.v:5368$995_Y + end + attribute \src "ls180.v:5458.71-5458.105" + cell $sub $sub$ls180.v:5458$1001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdmem2block_dma_length + connect \B 1'1 + connect \Y $sub$ls180.v:5458$1001_Y + end + attribute \src "ls180.v:5527.40-5527.76" + cell $sub $sub$ls180.v:5527$1012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdmem2block_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:5527$1012_Y + end + attribute \src "ls180.v:5546.61-5546.98" + cell $sub $sub$ls180.v:5546$1018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 15 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \libresocsim_clk_divider0 [15:1] + connect \B 1'1 + connect \Y $sub$ls180.v:5546$1018_Y + end + attribute \src "ls180.v:5547.61-5547.92" + cell $sub $sub$ls180.v:5547$1020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \libresocsim_clk_divider0 + connect \B 1'1 + connect \Y $sub$ls180.v:5547$1020_Y + end + attribute \src "ls180.v:5575.32-5575.58" + cell $sub $sub$ls180.v:5575$1024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \libresocsim_length0 + connect \B 1'1 + connect \Y $sub$ls180.v:5575$1024_Y + end + attribute \src "ls180.v:7449.31-7449.60" + cell $sub $sub$ls180.v:7449$2412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_libresocsim_value + connect \B 1'1 + connect \Y $sub$ls180.v:7449$2412_Y + end + attribute \src "ls180.v:7472.31-7472.61" + cell $sub $sub$ls180.v:7472$2417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdram_timer_count1 + connect \B 1'1 + connect \Y $sub$ls180.v:7472$2417_Y + end + attribute \src "ls180.v:7478.34-7478.67" + cell $sub $sub$ls180.v:7478$2418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_postponer_count + connect \B 1'1 + connect \Y $sub$ls180.v:7478$2418_Y + end + attribute \src "ls180.v:7489.36-7489.69" + cell $sub $sub$ls180.v:7489$2421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'1 + connect \Y $sub$ls180.v:7489$2421_Y + end + attribute \src "ls180.v:7553.59-7553.116" + cell $sub $sub$ls180.v:7553$2439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7553$2439_Y + end + attribute \src "ls180.v:7572.46-7572.90" + cell $sub $sub$ls180.v:7572$2443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7572$2443_Y + end + attribute \src "ls180.v:7599.59-7599.116" + cell $sub $sub$ls180.v:7599$2455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7599$2455_Y + end + attribute \src "ls180.v:7618.46-7618.90" + cell $sub $sub$ls180.v:7618$2459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7618$2459_Y + end + attribute \src "ls180.v:7645.59-7645.116" + cell $sub $sub$ls180.v:7645$2471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7645$2471_Y + end + attribute \src "ls180.v:7664.46-7664.90" + cell $sub $sub$ls180.v:7664$2475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7664$2475_Y + end + attribute \src "ls180.v:7691.59-7691.116" + cell $sub $sub$ls180.v:7691$2487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7691$2487_Y + end + attribute \src "ls180.v:7710.46-7710.90" + cell $sub $sub$ls180.v:7710$2491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7710$2491_Y + end + attribute \src "ls180.v:7721.25-7721.48" + cell $sub $sub$ls180.v:7721$2495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdram_time0 + connect \B 1'1 + connect \Y $sub$ls180.v:7721$2495_Y + end + attribute \src "ls180.v:7728.25-7728.48" + cell $sub $sub$ls180.v:7728$2498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_time1 + connect \B 1'1 + connect \Y $sub$ls180.v:7728$2498_Y + end + attribute \src "ls180.v:7860.33-7860.64" + cell $sub $sub$ls180.v:7860$2503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7860$2503_Y + end + attribute \src "ls180.v:7875.33-7875.64" + cell $sub $sub$ls180.v:7875$2506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_twtrcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7875$2506_Y + end + attribute \src "ls180.v:8002.33-8002.64" + cell $sub $sub$ls180.v:8002$2565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_tx_fifo_level0 + connect \B 1'1 + connect \Y $sub$ls180.v:8002$2565_Y + end + attribute \src "ls180.v:8024.33-8024.64" + cell $sub $sub$ls180.v:8024$2576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_rx_fifo_level0 + connect \B 1'1 + connect \Y $sub$ls180.v:8024$2576_Y + end + attribute \src "ls180.v:8059.33-8059.64" + cell $sub $sub$ls180.v:8059$2581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spi_master_mosi_sel + connect \B 1'1 + connect \Y $sub$ls180.v:8059$2581_Y + end + attribute \src "ls180.v:8083.30-8083.53" + cell $sub $sub$ls180.v:8083$2584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm0_period + connect \B 1'1 + connect \Y $sub$ls180.v:8083$2584_Y + end + attribute \src "ls180.v:8097.30-8097.53" + cell $sub $sub$ls180.v:8097$2588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm1_period + connect \B 1'1 + connect \Y $sub$ls180.v:8097$2588_Y + end + attribute \src "ls180.v:8500.36-8500.70" + cell $sub $sub$ls180.v:8500$2649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdblock2mem_fifo_level + connect \B 1'1 + connect \Y $sub$ls180.v:8500$2649_Y + end + attribute \src "ls180.v:8586.36-8586.70" + cell $sub $sub$ls180.v:8586$2671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdmem2block_fifo_level + connect \B 1'1 + connect \Y $sub$ls180.v:8586$2671_Y + end + attribute \src "ls180.v:8607.29-8607.56" + cell $sub $sub$ls180.v:8607$2676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \libresocsim_mosi_sel + connect \B 1'1 + connect \Y $sub$ls180.v:8607$2676_Y + end + attribute \src "ls180.v:8734.22-8734.42" + cell $sub $sub$ls180.v:8734$2683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 20 + connect \A \builder_count + connect \B 1'1 + connect \Y $sub$ls180.v:8734$2683_Y + end + attribute \src "ls180.v:4816.353-4816.425" + cell $xor $xor$ls180.v:4816$703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [39] + connect \B \main_sdcore_crc7_inserter_crcreg0 [6] + connect \Y $xor$ls180.v:4816$703_Y + end + attribute \src "ls180.v:4816.200-4816.272" + cell $xor $xor$ls180.v:4816$704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [39] + connect \B \main_sdcore_crc7_inserter_crcreg0 [6] + connect \Y $xor$ls180.v:4816$704_Y + end + attribute \src "ls180.v:4816.160-4816.273" + cell $xor $xor$ls180.v:4816$705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg0 [2] + connect \B $xor$ls180.v:4816$704_Y + connect \Y $xor$ls180.v:4816$705_Y + end + attribute \src "ls180.v:4817.353-4817.425" + cell $xor $xor$ls180.v:4817$706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [38] + connect \B \main_sdcore_crc7_inserter_crcreg1 [6] + connect \Y $xor$ls180.v:4817$706_Y + end + attribute \src "ls180.v:4817.200-4817.272" + cell $xor $xor$ls180.v:4817$707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [38] + connect \B \main_sdcore_crc7_inserter_crcreg1 [6] + connect \Y $xor$ls180.v:4817$707_Y + end + attribute \src "ls180.v:4817.160-4817.273" + cell $xor $xor$ls180.v:4817$708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg1 [2] + connect \B $xor$ls180.v:4817$707_Y + connect \Y $xor$ls180.v:4817$708_Y + end + attribute \src "ls180.v:4818.353-4818.425" + cell $xor $xor$ls180.v:4818$709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [37] + connect \B \main_sdcore_crc7_inserter_crcreg2 [6] + connect \Y $xor$ls180.v:4818$709_Y + end + attribute \src "ls180.v:4818.200-4818.272" + cell $xor $xor$ls180.v:4818$710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [37] + connect \B \main_sdcore_crc7_inserter_crcreg2 [6] + connect \Y $xor$ls180.v:4818$710_Y + end + attribute \src "ls180.v:4818.160-4818.273" + cell $xor $xor$ls180.v:4818$711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg2 [2] + connect \B $xor$ls180.v:4818$710_Y + connect \Y $xor$ls180.v:4818$711_Y + end + attribute \src "ls180.v:4819.353-4819.425" + cell $xor $xor$ls180.v:4819$712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [36] + connect \B \main_sdcore_crc7_inserter_crcreg3 [6] + connect \Y $xor$ls180.v:4819$712_Y + end + attribute \src "ls180.v:4819.200-4819.272" + cell $xor $xor$ls180.v:4819$713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [36] + connect \B \main_sdcore_crc7_inserter_crcreg3 [6] + connect \Y $xor$ls180.v:4819$713_Y + end + attribute \src "ls180.v:4819.160-4819.273" + cell $xor $xor$ls180.v:4819$714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg3 [2] + connect \B $xor$ls180.v:4819$713_Y + connect \Y $xor$ls180.v:4819$714_Y + end + attribute \src "ls180.v:4820.353-4820.425" + cell $xor $xor$ls180.v:4820$715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [35] + connect \B \main_sdcore_crc7_inserter_crcreg4 [6] + connect \Y $xor$ls180.v:4820$715_Y + end + attribute \src "ls180.v:4820.200-4820.272" + cell $xor $xor$ls180.v:4820$716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [35] + connect \B \main_sdcore_crc7_inserter_crcreg4 [6] + connect \Y $xor$ls180.v:4820$716_Y + end + attribute \src "ls180.v:4820.160-4820.273" + cell $xor $xor$ls180.v:4820$717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg4 [2] + connect \B $xor$ls180.v:4820$716_Y + connect \Y $xor$ls180.v:4820$717_Y + end + attribute \src "ls180.v:4821.353-4821.425" + cell $xor $xor$ls180.v:4821$718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [34] + connect \B \main_sdcore_crc7_inserter_crcreg5 [6] + connect \Y $xor$ls180.v:4821$718_Y + end + attribute \src "ls180.v:4821.200-4821.272" + cell $xor $xor$ls180.v:4821$719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [34] + connect \B \main_sdcore_crc7_inserter_crcreg5 [6] + connect \Y $xor$ls180.v:4821$719_Y + end + attribute \src "ls180.v:4821.160-4821.273" + cell $xor $xor$ls180.v:4821$720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg5 [2] + connect \B $xor$ls180.v:4821$719_Y + connect \Y $xor$ls180.v:4821$720_Y + end + attribute \src "ls180.v:4822.353-4822.425" + cell $xor $xor$ls180.v:4822$721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [33] + connect \B \main_sdcore_crc7_inserter_crcreg6 [6] + connect \Y $xor$ls180.v:4822$721_Y + end + attribute \src "ls180.v:4822.200-4822.272" + cell $xor $xor$ls180.v:4822$722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [33] + connect \B \main_sdcore_crc7_inserter_crcreg6 [6] + connect \Y $xor$ls180.v:4822$722_Y + end + attribute \src "ls180.v:4822.160-4822.273" + cell $xor $xor$ls180.v:4822$723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg6 [2] + connect \B $xor$ls180.v:4822$722_Y + connect \Y $xor$ls180.v:4822$723_Y + end + attribute \src "ls180.v:4823.353-4823.425" + cell $xor $xor$ls180.v:4823$724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [32] + connect \B \main_sdcore_crc7_inserter_crcreg7 [6] + connect \Y $xor$ls180.v:4823$724_Y + end + attribute \src "ls180.v:4823.200-4823.272" + cell $xor $xor$ls180.v:4823$725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [32] + connect \B \main_sdcore_crc7_inserter_crcreg7 [6] + connect \Y $xor$ls180.v:4823$725_Y + end + attribute \src "ls180.v:4823.160-4823.273" + cell $xor $xor$ls180.v:4823$726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg7 [2] + connect \B $xor$ls180.v:4823$725_Y + connect \Y $xor$ls180.v:4823$726_Y + end + attribute \src "ls180.v:4824.353-4824.425" + cell $xor $xor$ls180.v:4824$727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [31] + connect \B \main_sdcore_crc7_inserter_crcreg8 [6] + connect \Y $xor$ls180.v:4824$727_Y + end + attribute \src "ls180.v:4824.200-4824.272" + cell $xor $xor$ls180.v:4824$728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [31] + connect \B \main_sdcore_crc7_inserter_crcreg8 [6] + connect \Y $xor$ls180.v:4824$728_Y + end + attribute \src "ls180.v:4824.160-4824.273" + cell $xor $xor$ls180.v:4824$729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg8 [2] + connect \B $xor$ls180.v:4824$728_Y + connect \Y $xor$ls180.v:4824$729_Y + end + attribute \src "ls180.v:4825.354-4825.426" + cell $xor $xor$ls180.v:4825$730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [30] + connect \B \main_sdcore_crc7_inserter_crcreg9 [6] + connect \Y $xor$ls180.v:4825$730_Y + end + attribute \src "ls180.v:4825.201-4825.273" + cell $xor $xor$ls180.v:4825$731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [30] + connect \B \main_sdcore_crc7_inserter_crcreg9 [6] + connect \Y $xor$ls180.v:4825$731_Y + end + attribute \src "ls180.v:4825.161-4825.274" + cell $xor $xor$ls180.v:4825$732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg9 [2] + connect \B $xor$ls180.v:4825$731_Y + connect \Y $xor$ls180.v:4825$732_Y + end + attribute \src "ls180.v:4826.361-4826.434" + cell $xor $xor$ls180.v:4826$733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [29] + connect \B \main_sdcore_crc7_inserter_crcreg10 [6] + connect \Y $xor$ls180.v:4826$733_Y + end + attribute \src "ls180.v:4826.205-4826.278" + cell $xor $xor$ls180.v:4826$734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [29] + connect \B \main_sdcore_crc7_inserter_crcreg10 [6] + connect \Y $xor$ls180.v:4826$734_Y + end + attribute \src "ls180.v:4826.164-4826.279" + cell $xor $xor$ls180.v:4826$735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg10 [2] + connect \B $xor$ls180.v:4826$734_Y + connect \Y $xor$ls180.v:4826$735_Y + end + attribute \src "ls180.v:4827.361-4827.434" + cell $xor $xor$ls180.v:4827$736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [28] + connect \B \main_sdcore_crc7_inserter_crcreg11 [6] + connect \Y $xor$ls180.v:4827$736_Y + end + attribute \src "ls180.v:4827.205-4827.278" + cell $xor $xor$ls180.v:4827$737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [28] + connect \B \main_sdcore_crc7_inserter_crcreg11 [6] + connect \Y $xor$ls180.v:4827$737_Y + end + attribute \src "ls180.v:4827.164-4827.279" + cell $xor $xor$ls180.v:4827$738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg11 [2] + connect \B $xor$ls180.v:4827$737_Y + connect \Y $xor$ls180.v:4827$738_Y + end + attribute \src "ls180.v:4828.361-4828.434" + cell $xor $xor$ls180.v:4828$739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [27] + connect \B \main_sdcore_crc7_inserter_crcreg12 [6] + connect \Y $xor$ls180.v:4828$739_Y + end + attribute \src "ls180.v:4828.205-4828.278" + cell $xor $xor$ls180.v:4828$740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [27] + connect \B \main_sdcore_crc7_inserter_crcreg12 [6] + connect \Y $xor$ls180.v:4828$740_Y + end + attribute \src "ls180.v:4828.164-4828.279" + cell $xor $xor$ls180.v:4828$741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg12 [2] + connect \B $xor$ls180.v:4828$740_Y + connect \Y $xor$ls180.v:4828$741_Y + end + attribute \src "ls180.v:4829.361-4829.434" + cell $xor $xor$ls180.v:4829$742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [26] + connect \B \main_sdcore_crc7_inserter_crcreg13 [6] + connect \Y $xor$ls180.v:4829$742_Y + end + attribute \src "ls180.v:4829.205-4829.278" + cell $xor $xor$ls180.v:4829$743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [26] + connect \B \main_sdcore_crc7_inserter_crcreg13 [6] + connect \Y $xor$ls180.v:4829$743_Y + end + attribute \src "ls180.v:4829.164-4829.279" + cell $xor $xor$ls180.v:4829$744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg13 [2] + connect \B $xor$ls180.v:4829$743_Y + connect \Y $xor$ls180.v:4829$744_Y + end + attribute \src "ls180.v:4830.361-4830.434" + cell $xor $xor$ls180.v:4830$745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [25] + connect \B \main_sdcore_crc7_inserter_crcreg14 [6] + connect \Y $xor$ls180.v:4830$745_Y + end + attribute \src "ls180.v:4830.205-4830.278" + cell $xor $xor$ls180.v:4830$746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [25] + connect \B \main_sdcore_crc7_inserter_crcreg14 [6] + connect \Y $xor$ls180.v:4830$746_Y + end + attribute \src "ls180.v:4830.164-4830.279" + cell $xor $xor$ls180.v:4830$747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg14 [2] + connect \B $xor$ls180.v:4830$746_Y + connect \Y $xor$ls180.v:4830$747_Y + end + attribute \src "ls180.v:4831.361-4831.434" + cell $xor $xor$ls180.v:4831$748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [24] + connect \B \main_sdcore_crc7_inserter_crcreg15 [6] + connect \Y $xor$ls180.v:4831$748_Y + end + attribute \src "ls180.v:4831.205-4831.278" + cell $xor $xor$ls180.v:4831$749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [24] + connect \B \main_sdcore_crc7_inserter_crcreg15 [6] + connect \Y $xor$ls180.v:4831$749_Y + end + attribute \src "ls180.v:4831.164-4831.279" + cell $xor $xor$ls180.v:4831$750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg15 [2] + connect \B $xor$ls180.v:4831$749_Y + connect \Y $xor$ls180.v:4831$750_Y + end + attribute \src "ls180.v:4832.361-4832.434" + cell $xor $xor$ls180.v:4832$751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [23] + connect \B \main_sdcore_crc7_inserter_crcreg16 [6] + connect \Y $xor$ls180.v:4832$751_Y + end + attribute \src "ls180.v:4832.205-4832.278" + cell $xor $xor$ls180.v:4832$752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [23] + connect \B \main_sdcore_crc7_inserter_crcreg16 [6] + connect \Y $xor$ls180.v:4832$752_Y + end + attribute \src "ls180.v:4832.164-4832.279" + cell $xor $xor$ls180.v:4832$753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg16 [2] + connect \B $xor$ls180.v:4832$752_Y + connect \Y $xor$ls180.v:4832$753_Y + end + attribute \src "ls180.v:4833.361-4833.434" + cell $xor $xor$ls180.v:4833$754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [22] + connect \B \main_sdcore_crc7_inserter_crcreg17 [6] + connect \Y $xor$ls180.v:4833$754_Y + end + attribute \src "ls180.v:4833.205-4833.278" + cell $xor $xor$ls180.v:4833$755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [22] + connect \B \main_sdcore_crc7_inserter_crcreg17 [6] + connect \Y $xor$ls180.v:4833$755_Y + end + attribute \src "ls180.v:4833.164-4833.279" + cell $xor $xor$ls180.v:4833$756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg17 [2] + connect \B $xor$ls180.v:4833$755_Y + connect \Y $xor$ls180.v:4833$756_Y + end + attribute \src "ls180.v:4834.361-4834.434" + cell $xor $xor$ls180.v:4834$757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [21] + connect \B \main_sdcore_crc7_inserter_crcreg18 [6] + connect \Y $xor$ls180.v:4834$757_Y + end + attribute \src "ls180.v:4834.205-4834.278" + cell $xor $xor$ls180.v:4834$758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [21] + connect \B \main_sdcore_crc7_inserter_crcreg18 [6] + connect \Y $xor$ls180.v:4834$758_Y + end + attribute \src "ls180.v:4834.164-4834.279" + cell $xor $xor$ls180.v:4834$759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg18 [2] + connect \B $xor$ls180.v:4834$758_Y + connect \Y $xor$ls180.v:4834$759_Y + end + attribute \src "ls180.v:4835.361-4835.434" + cell $xor $xor$ls180.v:4835$760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [20] + connect \B \main_sdcore_crc7_inserter_crcreg19 [6] + connect \Y $xor$ls180.v:4835$760_Y + end + attribute \src "ls180.v:4835.205-4835.278" + cell $xor $xor$ls180.v:4835$761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [20] + connect \B \main_sdcore_crc7_inserter_crcreg19 [6] + connect \Y $xor$ls180.v:4835$761_Y + end + attribute \src "ls180.v:4835.164-4835.279" + cell $xor $xor$ls180.v:4835$762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg19 [2] + connect \B $xor$ls180.v:4835$761_Y + connect \Y $xor$ls180.v:4835$762_Y + end + attribute \src "ls180.v:4836.361-4836.434" + cell $xor $xor$ls180.v:4836$763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [19] + connect \B \main_sdcore_crc7_inserter_crcreg20 [6] + connect \Y $xor$ls180.v:4836$763_Y + end + attribute \src "ls180.v:4836.205-4836.278" + cell $xor $xor$ls180.v:4836$764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [19] + connect \B \main_sdcore_crc7_inserter_crcreg20 [6] + connect \Y $xor$ls180.v:4836$764_Y + end + attribute \src "ls180.v:4836.164-4836.279" + cell $xor $xor$ls180.v:4836$765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg20 [2] + connect \B $xor$ls180.v:4836$764_Y + connect \Y $xor$ls180.v:4836$765_Y + end + attribute \src "ls180.v:4837.361-4837.434" + cell $xor $xor$ls180.v:4837$766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [18] + connect \B \main_sdcore_crc7_inserter_crcreg21 [6] + connect \Y $xor$ls180.v:4837$766_Y + end + attribute \src "ls180.v:4837.205-4837.278" + cell $xor $xor$ls180.v:4837$767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [18] + connect \B \main_sdcore_crc7_inserter_crcreg21 [6] + connect \Y $xor$ls180.v:4837$767_Y + end + attribute \src "ls180.v:4837.164-4837.279" + cell $xor $xor$ls180.v:4837$768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg21 [2] + connect \B $xor$ls180.v:4837$767_Y + connect \Y $xor$ls180.v:4837$768_Y + end + attribute \src "ls180.v:4838.361-4838.434" + cell $xor $xor$ls180.v:4838$769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [17] + connect \B \main_sdcore_crc7_inserter_crcreg22 [6] + connect \Y $xor$ls180.v:4838$769_Y + end + attribute \src "ls180.v:4838.205-4838.278" + cell $xor $xor$ls180.v:4838$770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [17] + connect \B \main_sdcore_crc7_inserter_crcreg22 [6] + connect \Y $xor$ls180.v:4838$770_Y + end + attribute \src "ls180.v:4838.164-4838.279" + cell $xor $xor$ls180.v:4838$771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg22 [2] + connect \B $xor$ls180.v:4838$770_Y + connect \Y $xor$ls180.v:4838$771_Y + end + attribute \src "ls180.v:4839.361-4839.434" + cell $xor $xor$ls180.v:4839$772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [16] + connect \B \main_sdcore_crc7_inserter_crcreg23 [6] + connect \Y $xor$ls180.v:4839$772_Y + end + attribute \src "ls180.v:4839.205-4839.278" + cell $xor $xor$ls180.v:4839$773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [16] + connect \B \main_sdcore_crc7_inserter_crcreg23 [6] + connect \Y $xor$ls180.v:4839$773_Y + end + attribute \src "ls180.v:4839.164-4839.279" + cell $xor $xor$ls180.v:4839$774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg23 [2] + connect \B $xor$ls180.v:4839$773_Y + connect \Y $xor$ls180.v:4839$774_Y + end + attribute \src "ls180.v:4840.361-4840.434" + cell $xor $xor$ls180.v:4840$775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [15] + connect \B \main_sdcore_crc7_inserter_crcreg24 [6] + connect \Y $xor$ls180.v:4840$775_Y + end + attribute \src "ls180.v:4840.205-4840.278" + cell $xor $xor$ls180.v:4840$776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [15] + connect \B \main_sdcore_crc7_inserter_crcreg24 [6] + connect \Y $xor$ls180.v:4840$776_Y + end + attribute \src "ls180.v:4840.164-4840.279" + cell $xor $xor$ls180.v:4840$777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg24 [2] + connect \B $xor$ls180.v:4840$776_Y + connect \Y $xor$ls180.v:4840$777_Y + end + attribute \src "ls180.v:4841.361-4841.434" + cell $xor $xor$ls180.v:4841$778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [14] + connect \B \main_sdcore_crc7_inserter_crcreg25 [6] + connect \Y $xor$ls180.v:4841$778_Y + end + attribute \src "ls180.v:4841.205-4841.278" + cell $xor $xor$ls180.v:4841$779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [14] + connect \B \main_sdcore_crc7_inserter_crcreg25 [6] + connect \Y $xor$ls180.v:4841$779_Y + end + attribute \src "ls180.v:4841.164-4841.279" + cell $xor $xor$ls180.v:4841$780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg25 [2] + connect \B $xor$ls180.v:4841$779_Y + connect \Y $xor$ls180.v:4841$780_Y + end + attribute \src "ls180.v:4842.361-4842.434" + cell $xor $xor$ls180.v:4842$781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [13] + connect \B \main_sdcore_crc7_inserter_crcreg26 [6] + connect \Y $xor$ls180.v:4842$781_Y + end + attribute \src "ls180.v:4842.205-4842.278" + cell $xor $xor$ls180.v:4842$782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [13] + connect \B \main_sdcore_crc7_inserter_crcreg26 [6] + connect \Y $xor$ls180.v:4842$782_Y + end + attribute \src "ls180.v:4842.164-4842.279" + cell $xor $xor$ls180.v:4842$783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg26 [2] + connect \B $xor$ls180.v:4842$782_Y + connect \Y $xor$ls180.v:4842$783_Y + end + attribute \src "ls180.v:4843.361-4843.434" + cell $xor $xor$ls180.v:4843$784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [12] + connect \B \main_sdcore_crc7_inserter_crcreg27 [6] + connect \Y $xor$ls180.v:4843$784_Y + end + attribute \src "ls180.v:4843.205-4843.278" + cell $xor $xor$ls180.v:4843$785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [12] + connect \B \main_sdcore_crc7_inserter_crcreg27 [6] + connect \Y $xor$ls180.v:4843$785_Y + end + attribute \src "ls180.v:4843.164-4843.279" + cell $xor $xor$ls180.v:4843$786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg27 [2] + connect \B $xor$ls180.v:4843$785_Y + connect \Y $xor$ls180.v:4843$786_Y + end + attribute \src "ls180.v:4844.361-4844.434" + cell $xor $xor$ls180.v:4844$787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [11] + connect \B \main_sdcore_crc7_inserter_crcreg28 [6] + connect \Y $xor$ls180.v:4844$787_Y + end + attribute \src "ls180.v:4844.205-4844.278" + cell $xor $xor$ls180.v:4844$788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [11] + connect \B \main_sdcore_crc7_inserter_crcreg28 [6] + connect \Y $xor$ls180.v:4844$788_Y + end + attribute \src "ls180.v:4844.164-4844.279" + cell $xor $xor$ls180.v:4844$789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg28 [2] + connect \B $xor$ls180.v:4844$788_Y + connect \Y $xor$ls180.v:4844$789_Y + end + attribute \src "ls180.v:4845.361-4845.434" + cell $xor $xor$ls180.v:4845$790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [10] + connect \B \main_sdcore_crc7_inserter_crcreg29 [6] + connect \Y $xor$ls180.v:4845$790_Y + end + attribute \src "ls180.v:4845.205-4845.278" + cell $xor $xor$ls180.v:4845$791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [10] + connect \B \main_sdcore_crc7_inserter_crcreg29 [6] + connect \Y $xor$ls180.v:4845$791_Y + end + attribute \src "ls180.v:4845.164-4845.279" + cell $xor $xor$ls180.v:4845$792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg29 [2] + connect \B $xor$ls180.v:4845$791_Y + connect \Y $xor$ls180.v:4845$792_Y + end + attribute \src "ls180.v:4846.360-4846.432" + cell $xor $xor$ls180.v:4846$793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [9] + connect \B \main_sdcore_crc7_inserter_crcreg30 [6] + connect \Y $xor$ls180.v:4846$793_Y + end + attribute \src "ls180.v:4846.205-4846.277" + cell $xor $xor$ls180.v:4846$794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [9] + connect \B \main_sdcore_crc7_inserter_crcreg30 [6] + connect \Y $xor$ls180.v:4846$794_Y + end + attribute \src "ls180.v:4846.164-4846.278" + cell $xor $xor$ls180.v:4846$795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg30 [2] + connect \B $xor$ls180.v:4846$794_Y + connect \Y $xor$ls180.v:4846$795_Y + end + attribute \src "ls180.v:4847.360-4847.432" + cell $xor $xor$ls180.v:4847$796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [8] + connect \B \main_sdcore_crc7_inserter_crcreg31 [6] + connect \Y $xor$ls180.v:4847$796_Y + end + attribute \src "ls180.v:4847.205-4847.277" + cell $xor $xor$ls180.v:4847$797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [8] + connect \B \main_sdcore_crc7_inserter_crcreg31 [6] + connect \Y $xor$ls180.v:4847$797_Y + end + attribute \src "ls180.v:4847.164-4847.278" + cell $xor $xor$ls180.v:4847$798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg31 [2] + connect \B $xor$ls180.v:4847$797_Y + connect \Y $xor$ls180.v:4847$798_Y + end + attribute \src "ls180.v:4848.360-4848.432" + cell $xor $xor$ls180.v:4848$799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [7] + connect \B \main_sdcore_crc7_inserter_crcreg32 [6] + connect \Y $xor$ls180.v:4848$799_Y + end + attribute \src "ls180.v:4848.205-4848.277" + cell $xor $xor$ls180.v:4848$800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [7] + connect \B \main_sdcore_crc7_inserter_crcreg32 [6] + connect \Y $xor$ls180.v:4848$800_Y + end + attribute \src "ls180.v:4848.164-4848.278" + cell $xor $xor$ls180.v:4848$801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg32 [2] + connect \B $xor$ls180.v:4848$800_Y + connect \Y $xor$ls180.v:4848$801_Y + end + attribute \src "ls180.v:4849.360-4849.432" + cell $xor $xor$ls180.v:4849$802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [6] + connect \B \main_sdcore_crc7_inserter_crcreg33 [6] + connect \Y $xor$ls180.v:4849$802_Y + end + attribute \src "ls180.v:4849.205-4849.277" + cell $xor $xor$ls180.v:4849$803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [6] + connect \B \main_sdcore_crc7_inserter_crcreg33 [6] + connect \Y $xor$ls180.v:4849$803_Y + end + attribute \src "ls180.v:4849.164-4849.278" + cell $xor $xor$ls180.v:4849$804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg33 [2] + connect \B $xor$ls180.v:4849$803_Y + connect \Y $xor$ls180.v:4849$804_Y + end + attribute \src "ls180.v:4850.360-4850.432" + cell $xor $xor$ls180.v:4850$805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [5] + connect \B \main_sdcore_crc7_inserter_crcreg34 [6] + connect \Y $xor$ls180.v:4850$805_Y + end + attribute \src "ls180.v:4850.205-4850.277" + cell $xor $xor$ls180.v:4850$806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [5] + connect \B \main_sdcore_crc7_inserter_crcreg34 [6] + connect \Y $xor$ls180.v:4850$806_Y + end + attribute \src "ls180.v:4850.164-4850.278" + cell $xor $xor$ls180.v:4850$807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg34 [2] + connect \B $xor$ls180.v:4850$806_Y + connect \Y $xor$ls180.v:4850$807_Y + end + attribute \src "ls180.v:4851.360-4851.432" + cell $xor $xor$ls180.v:4851$808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [4] + connect \B \main_sdcore_crc7_inserter_crcreg35 [6] + connect \Y $xor$ls180.v:4851$808_Y + end + attribute \src "ls180.v:4851.205-4851.277" + cell $xor $xor$ls180.v:4851$809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [4] + connect \B \main_sdcore_crc7_inserter_crcreg35 [6] + connect \Y $xor$ls180.v:4851$809_Y + end + attribute \src "ls180.v:4851.164-4851.278" + cell $xor $xor$ls180.v:4851$810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg35 [2] + connect \B $xor$ls180.v:4851$809_Y + connect \Y $xor$ls180.v:4851$810_Y + end + attribute \src "ls180.v:4852.360-4852.432" + cell $xor $xor$ls180.v:4852$811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [3] + connect \B \main_sdcore_crc7_inserter_crcreg36 [6] + connect \Y $xor$ls180.v:4852$811_Y + end + attribute \src "ls180.v:4852.205-4852.277" + cell $xor $xor$ls180.v:4852$812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [3] + connect \B \main_sdcore_crc7_inserter_crcreg36 [6] + connect \Y $xor$ls180.v:4852$812_Y + end + attribute \src "ls180.v:4852.164-4852.278" + cell $xor $xor$ls180.v:4852$813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg36 [2] + connect \B $xor$ls180.v:4852$812_Y + connect \Y $xor$ls180.v:4852$813_Y + end + attribute \src "ls180.v:4853.360-4853.432" + cell $xor $xor$ls180.v:4853$814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [2] + connect \B \main_sdcore_crc7_inserter_crcreg37 [6] + connect \Y $xor$ls180.v:4853$814_Y + end + attribute \src "ls180.v:4853.205-4853.277" + cell $xor $xor$ls180.v:4853$815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [2] + connect \B \main_sdcore_crc7_inserter_crcreg37 [6] + connect \Y $xor$ls180.v:4853$815_Y + end + attribute \src "ls180.v:4853.164-4853.278" + cell $xor $xor$ls180.v:4853$816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg37 [2] + connect \B $xor$ls180.v:4853$815_Y + connect \Y $xor$ls180.v:4853$816_Y + end + attribute \src "ls180.v:4854.360-4854.432" + cell $xor $xor$ls180.v:4854$817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [1] + connect \B \main_sdcore_crc7_inserter_crcreg38 [6] + connect \Y $xor$ls180.v:4854$817_Y + end + attribute \src "ls180.v:4854.205-4854.277" + cell $xor $xor$ls180.v:4854$818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [1] + connect \B \main_sdcore_crc7_inserter_crcreg38 [6] + connect \Y $xor$ls180.v:4854$818_Y + end + attribute \src "ls180.v:4854.164-4854.278" + cell $xor $xor$ls180.v:4854$819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg38 [2] + connect \B $xor$ls180.v:4854$818_Y + connect \Y $xor$ls180.v:4854$819_Y + end + attribute \src "ls180.v:4855.360-4855.432" + cell $xor $xor$ls180.v:4855$820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [0] + connect \B \main_sdcore_crc7_inserter_crcreg39 [6] + connect \Y $xor$ls180.v:4855$820_Y + end + attribute \src "ls180.v:4855.205-4855.277" + cell $xor $xor$ls180.v:4855$821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [0] + connect \B \main_sdcore_crc7_inserter_crcreg39 [6] + connect \Y $xor$ls180.v:4855$821_Y + end + attribute \src "ls180.v:4855.164-4855.278" + cell $xor $xor$ls180.v:4855$822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg39 [2] + connect \B $xor$ls180.v:4855$821_Y + connect \Y $xor$ls180.v:4855$822_Y + end + attribute \src "ls180.v:4876.899-4876.983" + cell $xor $xor$ls180.v:4876$836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [1] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:4876$836_Y + end + attribute \src "ls180.v:4876.634-4876.718" + cell $xor $xor$ls180.v:4876$837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [1] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:4876$837_Y + end + attribute \src "ls180.v:4876.588-4876.719" + cell $xor $xor$ls180.v:4876$838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [4] + connect \B $xor$ls180.v:4876$837_Y + connect \Y $xor$ls180.v:4876$838_Y + end + attribute \src "ls180.v:4876.234-4876.318" + cell $xor $xor$ls180.v:4876$839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [1] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:4876$839_Y + end + attribute \src "ls180.v:4876.187-4876.319" + cell $xor $xor$ls180.v:4876$840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [11] + connect \B $xor$ls180.v:4876$839_Y + connect \Y $xor$ls180.v:4876$840_Y + end + attribute \src "ls180.v:4877.899-4877.983" + cell $xor $xor$ls180.v:4877$841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:4877$841_Y + end + attribute \src "ls180.v:4877.634-4877.718" + cell $xor $xor$ls180.v:4877$842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:4877$842_Y + end + attribute \src "ls180.v:4877.588-4877.719" + cell $xor $xor$ls180.v:4877$843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4] + connect \B $xor$ls180.v:4877$842_Y + connect \Y $xor$ls180.v:4877$843_Y + end + attribute \src "ls180.v:4877.234-4877.318" + cell $xor $xor$ls180.v:4877$844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:4877$844_Y + end + attribute \src "ls180.v:4877.187-4877.319" + cell $xor $xor$ls180.v:4877$845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11] + connect \B $xor$ls180.v:4877$844_Y + connect \Y $xor$ls180.v:4877$845_Y + end + attribute \src "ls180.v:4886.899-4886.983" + cell $xor $xor$ls180.v:4886$847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [1] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:4886$847_Y + end + attribute \src "ls180.v:4886.634-4886.718" + cell $xor $xor$ls180.v:4886$848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [1] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:4886$848_Y + end + attribute \src "ls180.v:4886.588-4886.719" + cell $xor $xor$ls180.v:4886$849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [4] + connect \B $xor$ls180.v:4886$848_Y + connect \Y $xor$ls180.v:4886$849_Y + end + attribute \src "ls180.v:4886.234-4886.318" + cell $xor $xor$ls180.v:4886$850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [1] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:4886$850_Y + end + attribute \src "ls180.v:4886.187-4886.319" + cell $xor $xor$ls180.v:4886$851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [11] + connect \B $xor$ls180.v:4886$850_Y + connect \Y $xor$ls180.v:4886$851_Y + end + attribute \src "ls180.v:4887.899-4887.983" + cell $xor $xor$ls180.v:4887$852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [0] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:4887$852_Y + end + attribute \src "ls180.v:4887.634-4887.718" + cell $xor $xor$ls180.v:4887$853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [0] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:4887$853_Y + end + attribute \src "ls180.v:4887.588-4887.719" + cell $xor $xor$ls180.v:4887$854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [4] + connect \B $xor$ls180.v:4887$853_Y + connect \Y $xor$ls180.v:4887$854_Y + end + attribute \src "ls180.v:4887.234-4887.318" + cell $xor $xor$ls180.v:4887$855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [0] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:4887$855_Y + end + attribute \src "ls180.v:4887.187-4887.319" + cell $xor $xor$ls180.v:4887$856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [11] + connect \B $xor$ls180.v:4887$855_Y + connect \Y $xor$ls180.v:4887$856_Y + end + attribute \src "ls180.v:4896.899-4896.983" + cell $xor $xor$ls180.v:4896$858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [1] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:4896$858_Y + end + attribute \src "ls180.v:4896.634-4896.718" + cell $xor $xor$ls180.v:4896$859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [1] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:4896$859_Y + end + attribute \src "ls180.v:4896.588-4896.719" + cell $xor $xor$ls180.v:4896$860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [4] + connect \B $xor$ls180.v:4896$859_Y + connect \Y $xor$ls180.v:4896$860_Y + end + attribute \src "ls180.v:4896.234-4896.318" + cell $xor $xor$ls180.v:4896$861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [1] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:4896$861_Y + end + attribute \src "ls180.v:4896.187-4896.319" + cell $xor $xor$ls180.v:4896$862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [11] + connect \B $xor$ls180.v:4896$861_Y + connect \Y $xor$ls180.v:4896$862_Y + end + attribute \src "ls180.v:4897.899-4897.983" + cell $xor $xor$ls180.v:4897$863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [0] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:4897$863_Y + end + attribute \src "ls180.v:4897.634-4897.718" + cell $xor $xor$ls180.v:4897$864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [0] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:4897$864_Y + end + attribute \src "ls180.v:4897.588-4897.719" + cell $xor $xor$ls180.v:4897$865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [4] + connect \B $xor$ls180.v:4897$864_Y + connect \Y $xor$ls180.v:4897$865_Y + end + attribute \src "ls180.v:4897.234-4897.318" + cell $xor $xor$ls180.v:4897$866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [0] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:4897$866_Y + end + attribute \src "ls180.v:4897.187-4897.319" + cell $xor $xor$ls180.v:4897$867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [11] + connect \B $xor$ls180.v:4897$866_Y + connect \Y $xor$ls180.v:4897$867_Y + end + attribute \src "ls180.v:4906.899-4906.983" + cell $xor $xor$ls180.v:4906$869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [1] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:4906$869_Y + end + attribute \src "ls180.v:4906.634-4906.718" + cell $xor $xor$ls180.v:4906$870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [1] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:4906$870_Y + end + attribute \src "ls180.v:4906.588-4906.719" + cell $xor $xor$ls180.v:4906$871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [4] + connect \B $xor$ls180.v:4906$870_Y + connect \Y $xor$ls180.v:4906$871_Y + end + attribute \src "ls180.v:4906.234-4906.318" + cell $xor $xor$ls180.v:4906$872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [1] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:4906$872_Y + end + attribute \src "ls180.v:4906.187-4906.319" + cell $xor $xor$ls180.v:4906$873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [11] + connect \B $xor$ls180.v:4906$872_Y + connect \Y $xor$ls180.v:4906$873_Y + end + attribute \src "ls180.v:4907.899-4907.983" + cell $xor $xor$ls180.v:4907$874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:4907$874_Y + end + attribute \src "ls180.v:4907.634-4907.718" + cell $xor $xor$ls180.v:4907$875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:4907$875_Y + end + attribute \src "ls180.v:4907.588-4907.719" + cell $xor $xor$ls180.v:4907$876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4] + connect \B $xor$ls180.v:4907$875_Y + connect \Y $xor$ls180.v:4907$876_Y + end + attribute \src "ls180.v:4907.234-4907.318" + cell $xor $xor$ls180.v:4907$877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:4907$877_Y + end + attribute \src "ls180.v:4907.187-4907.319" + cell $xor $xor$ls180.v:4907$878 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \core_issue__data_o - connect \B 1'1 - connect \Y $add$issuer_ls180.v:177414$12452_Y + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11] + connect \B $xor$ls180.v:4907$877_Y + connect \Y $xor$ls180.v:4907$878_Y + end + attribute \src "ls180.v:5058.879-5058.961" + cell $xor $xor$ls180.v:5058$911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [1] + connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5058$911_Y + end + attribute \src "ls180.v:5058.620-5058.702" + cell $xor $xor$ls180.v:5058$912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [1] + connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5058$912_Y + end + attribute \src "ls180.v:5058.575-5058.703" + cell $xor $xor$ls180.v:5058$913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [4] + connect \B $xor$ls180.v:5058$912_Y + connect \Y $xor$ls180.v:5058$913_Y + end + attribute \src "ls180.v:5058.229-5058.311" + cell $xor $xor$ls180.v:5058$914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [1] + connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5058$914_Y + end + attribute \src "ls180.v:5058.183-5058.312" + cell $xor $xor$ls180.v:5058$915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [11] + connect \B $xor$ls180.v:5058$914_Y + connect \Y $xor$ls180.v:5058$915_Y + end + attribute \src "ls180.v:5059.879-5059.961" + cell $xor $xor$ls180.v:5059$916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [0] + connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5059$916_Y + end + attribute \src "ls180.v:5059.620-5059.702" + cell $xor $xor$ls180.v:5059$917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [0] + connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5059$917_Y + end + attribute \src "ls180.v:5059.575-5059.703" + cell $xor $xor$ls180.v:5059$918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [4] + connect \B $xor$ls180.v:5059$917_Y + connect \Y $xor$ls180.v:5059$918_Y + end + attribute \src "ls180.v:5059.229-5059.311" + cell $xor $xor$ls180.v:5059$919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [0] + connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5059$919_Y + end + attribute \src "ls180.v:5059.183-5059.312" + cell $xor $xor$ls180.v:5059$920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [11] + connect \B $xor$ls180.v:5059$919_Y + connect \Y $xor$ls180.v:5059$920_Y + end + attribute \src "ls180.v:5068.879-5068.961" + cell $xor $xor$ls180.v:5068$922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [1] + connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5068$922_Y + end + attribute \src "ls180.v:5068.620-5068.702" + cell $xor $xor$ls180.v:5068$923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [1] + connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5068$923_Y + end + attribute \src "ls180.v:5068.575-5068.703" + cell $xor $xor$ls180.v:5068$924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [4] + connect \B $xor$ls180.v:5068$923_Y + connect \Y $xor$ls180.v:5068$924_Y + end + attribute \src "ls180.v:5068.229-5068.311" + cell $xor $xor$ls180.v:5068$925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [1] + connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5068$925_Y + end + attribute \src "ls180.v:5068.183-5068.312" + cell $xor $xor$ls180.v:5068$926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [11] + connect \B $xor$ls180.v:5068$925_Y + connect \Y $xor$ls180.v:5068$926_Y + end + attribute \src "ls180.v:5069.879-5069.961" + cell $xor $xor$ls180.v:5069$927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [0] + connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5069$927_Y + end + attribute \src "ls180.v:5069.620-5069.702" + cell $xor $xor$ls180.v:5069$928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [0] + connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5069$928_Y + end + attribute \src "ls180.v:5069.575-5069.703" + cell $xor $xor$ls180.v:5069$929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [4] + connect \B $xor$ls180.v:5069$928_Y + connect \Y $xor$ls180.v:5069$929_Y + end + attribute \src "ls180.v:5069.229-5069.311" + cell $xor $xor$ls180.v:5069$930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [0] + connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5069$930_Y + end + attribute \src "ls180.v:5069.183-5069.312" + cell $xor $xor$ls180.v:5069$931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [11] + connect \B $xor$ls180.v:5069$930_Y + connect \Y $xor$ls180.v:5069$931_Y + end + attribute \src "ls180.v:5078.879-5078.961" + cell $xor $xor$ls180.v:5078$933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [1] + connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5078$933_Y + end + attribute \src "ls180.v:5078.620-5078.702" + cell $xor $xor$ls180.v:5078$934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [1] + connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5078$934_Y + end + attribute \src "ls180.v:5078.575-5078.703" + cell $xor $xor$ls180.v:5078$935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [4] + connect \B $xor$ls180.v:5078$934_Y + connect \Y $xor$ls180.v:5078$935_Y + end + attribute \src "ls180.v:5078.229-5078.311" + cell $xor $xor$ls180.v:5078$936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [1] + connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5078$936_Y + end + attribute \src "ls180.v:5078.183-5078.312" + cell $xor $xor$ls180.v:5078$937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [11] + connect \B $xor$ls180.v:5078$936_Y + connect \Y $xor$ls180.v:5078$937_Y + end + attribute \src "ls180.v:5079.879-5079.961" + cell $xor $xor$ls180.v:5079$938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5079$938_Y + end + attribute \src "ls180.v:5079.620-5079.702" + cell $xor $xor$ls180.v:5079$939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5079$939_Y + end + attribute \src "ls180.v:5079.575-5079.703" + cell $xor $xor$ls180.v:5079$940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4] + connect \B $xor$ls180.v:5079$939_Y + connect \Y $xor$ls180.v:5079$940_Y + end + attribute \src "ls180.v:5079.229-5079.311" + cell $xor $xor$ls180.v:5079$941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5079$941_Y + end + attribute \src "ls180.v:5079.183-5079.312" + cell $xor $xor$ls180.v:5079$942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11] + connect \B $xor$ls180.v:5079$941_Y + connect \Y $xor$ls180.v:5079$942_Y + end + attribute \src "ls180.v:5088.879-5088.961" + cell $xor $xor$ls180.v:5088$944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [1] + connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5088$944_Y + end + attribute \src "ls180.v:5088.620-5088.702" + cell $xor $xor$ls180.v:5088$945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [1] + connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5088$945_Y + end + attribute \src "ls180.v:5088.575-5088.703" + cell $xor $xor$ls180.v:5088$946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [4] + connect \B $xor$ls180.v:5088$945_Y + connect \Y $xor$ls180.v:5088$946_Y + end + attribute \src "ls180.v:5088.229-5088.311" + cell $xor $xor$ls180.v:5088$947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [1] + connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5088$947_Y + end + attribute \src "ls180.v:5088.183-5088.312" + cell $xor $xor$ls180.v:5088$948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [11] + connect \B $xor$ls180.v:5088$947_Y + connect \Y $xor$ls180.v:5088$948_Y + end + attribute \src "ls180.v:5089.879-5089.961" + cell $xor $xor$ls180.v:5089$949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [0] + connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5089$949_Y + end + attribute \src "ls180.v:5089.620-5089.702" + cell $xor $xor$ls180.v:5089$950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [0] + connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5089$950_Y + end + attribute \src "ls180.v:5089.575-5089.703" + cell $xor $xor$ls180.v:5089$951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [4] + connect \B $xor$ls180.v:5089$950_Y + connect \Y $xor$ls180.v:5089$951_Y + end + attribute \src "ls180.v:5089.229-5089.311" + cell $xor $xor$ls180.v:5089$952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [0] + connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5089$952_Y + end + attribute \src "ls180.v:5089.183-5089.312" + cell $xor $xor$ls180.v:5089$953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [11] + connect \B $xor$ls180.v:5089$952_Y + connect \Y $xor$ls180.v:5089$953_Y + end + attribute \module_not_derived 1 + attribute \src "ls180.v:10117.13-10284.2" + cell \test_issuer \test_issuer + connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck + connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi + connect \TAP_bus__tdo \main_libresocsim_libresoc_jtag_tdo + connect \TAP_bus__tms \main_libresocsim_libresoc_jtag_tms + connect \busy_o \main_libresocsim_libresoc0 + connect \clk \sys_clk_1 + connect \core_bigendian_i 1'0 + connect \dbus__ack \main_libresocsim_libresoc_dbus_ack + connect \dbus__adr \main_libresocsim_libresoc_dbus_adr + connect \dbus__bte \main_libresocsim_libresoc_dbus_bte + connect \dbus__cti \main_libresocsim_libresoc_dbus_cti + connect \dbus__cyc \main_libresocsim_libresoc_dbus_cyc + connect \dbus__dat_r \main_libresocsim_libresoc_dbus_dat_r + connect \dbus__dat_w \main_libresocsim_libresoc_dbus_dat_w + connect \dbus__err \main_libresocsim_libresoc_dbus_err + connect \dbus__sel \main_libresocsim_libresoc_dbus_sel + connect \dbus__stb \main_libresocsim_libresoc_dbus_stb + connect \dbus__we \main_libresocsim_libresoc_dbus_we + connect \gpio_gpio0__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [0] + connect \gpio_gpio0__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [0] + connect \gpio_gpio0__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [0] + connect \gpio_gpio0__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [0] + connect \gpio_gpio0__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [0] + connect \gpio_gpio0__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [0] + connect \gpio_gpio10__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [10] + connect \gpio_gpio10__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [10] + connect \gpio_gpio10__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [10] + connect \gpio_gpio10__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [10] + connect \gpio_gpio10__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [10] + connect \gpio_gpio10__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [10] + connect \gpio_gpio11__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [11] + connect \gpio_gpio11__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [11] + connect \gpio_gpio11__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [11] + connect \gpio_gpio11__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [11] + connect \gpio_gpio11__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [11] + connect \gpio_gpio11__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [11] + connect \gpio_gpio12__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [12] + connect \gpio_gpio12__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [12] + connect \gpio_gpio12__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [12] + connect \gpio_gpio12__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [12] + connect \gpio_gpio12__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [12] + connect \gpio_gpio12__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [12] + connect \gpio_gpio13__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [13] + connect \gpio_gpio13__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [13] + connect \gpio_gpio13__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [13] + connect \gpio_gpio13__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [13] + connect \gpio_gpio13__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [13] + connect \gpio_gpio13__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [13] + connect \gpio_gpio14__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [14] + connect \gpio_gpio14__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [14] + connect \gpio_gpio14__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [14] + connect \gpio_gpio14__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [14] + connect \gpio_gpio14__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [14] + connect \gpio_gpio14__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [14] + connect \gpio_gpio15__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [15] + connect \gpio_gpio15__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [15] + connect \gpio_gpio15__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [15] + connect \gpio_gpio15__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [15] + connect \gpio_gpio15__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [15] + connect \gpio_gpio15__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [15] + connect \gpio_gpio1__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [1] + connect \gpio_gpio1__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [1] + connect \gpio_gpio1__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [1] + connect \gpio_gpio1__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [1] + connect \gpio_gpio1__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [1] + connect \gpio_gpio1__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [1] + connect \gpio_gpio2__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [2] + connect \gpio_gpio2__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [2] + connect \gpio_gpio2__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [2] + connect \gpio_gpio2__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [2] + connect \gpio_gpio2__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [2] + connect \gpio_gpio2__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [2] + connect \gpio_gpio3__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [3] + connect \gpio_gpio3__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [3] + connect \gpio_gpio3__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [3] + connect \gpio_gpio3__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [3] + connect \gpio_gpio3__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [3] + connect \gpio_gpio3__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [3] + connect \gpio_gpio4__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [4] + connect \gpio_gpio4__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [4] + connect \gpio_gpio4__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [4] + connect \gpio_gpio4__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [4] + connect \gpio_gpio4__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [4] + connect \gpio_gpio4__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [4] + connect \gpio_gpio5__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [5] + connect \gpio_gpio5__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [5] + connect \gpio_gpio5__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [5] + connect \gpio_gpio5__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [5] + connect \gpio_gpio5__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [5] + connect \gpio_gpio5__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [5] + connect \gpio_gpio6__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [6] + connect \gpio_gpio6__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [6] + connect \gpio_gpio6__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [6] + connect \gpio_gpio6__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [6] + connect \gpio_gpio6__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [6] + connect \gpio_gpio6__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [6] + connect \gpio_gpio7__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [7] + connect \gpio_gpio7__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [7] + connect \gpio_gpio7__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [7] + connect \gpio_gpio7__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [7] + connect \gpio_gpio7__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [7] + connect \gpio_gpio7__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [7] + connect \gpio_gpio8__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [8] + connect \gpio_gpio8__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [8] + connect \gpio_gpio8__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [8] + connect \gpio_gpio8__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [8] + connect \gpio_gpio8__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [8] + connect \gpio_gpio8__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [8] + connect \gpio_gpio9__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [9] + connect \gpio_gpio9__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [9] + connect \gpio_gpio9__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [9] + connect \gpio_gpio9__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [9] + connect \gpio_gpio9__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [9] + connect \gpio_gpio9__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [9] + connect \ibus__ack \main_libresocsim_libresoc_ibus_ack + connect \ibus__adr \main_libresocsim_libresoc_ibus_adr + connect \ibus__bte \main_libresocsim_libresoc_ibus_bte + connect \ibus__cti \main_libresocsim_libresoc_ibus_cti + connect \ibus__cyc \main_libresocsim_libresoc_ibus_cyc + connect \ibus__dat_r \main_libresocsim_libresoc_ibus_dat_r + connect \ibus__dat_w \main_libresocsim_libresoc_ibus_dat_w + connect \ibus__err \main_libresocsim_libresoc_ibus_err + connect \ibus__sel \main_libresocsim_libresoc_ibus_sel + connect \ibus__stb \main_libresocsim_libresoc_ibus_stb + connect \ibus__we \main_libresocsim_libresoc_ibus_we + connect \icp_wb__ack \main_libresocsim_libresoc_xics_icp_ack + connect \icp_wb__adr \main_libresocsim_libresoc_xics_icp_adr + connect \icp_wb__bte \main_libresocsim_libresoc_xics_icp_bte + connect \icp_wb__cti \main_libresocsim_libresoc_xics_icp_cti + connect \icp_wb__cyc \main_libresocsim_libresoc_xics_icp_cyc + connect \icp_wb__dat_r \main_libresocsim_libresoc_xics_icp_dat_r + connect \icp_wb__dat_w \main_libresocsim_libresoc_xics_icp_dat_w + connect \icp_wb__err \main_libresocsim_libresoc_xics_icp_err + connect \icp_wb__sel \main_libresocsim_libresoc_xics_icp_sel + connect \icp_wb__stb \main_libresocsim_libresoc_xics_icp_stb + connect \icp_wb__we \main_libresocsim_libresoc_xics_icp_we + connect \ics_wb__ack \main_libresocsim_libresoc_xics_ics_ack + connect \ics_wb__adr \main_libresocsim_libresoc_xics_ics_adr + connect \ics_wb__bte \main_libresocsim_libresoc_xics_ics_bte + connect \ics_wb__cti \main_libresocsim_libresoc_xics_ics_cti + connect \ics_wb__cyc \main_libresocsim_libresoc_xics_ics_cyc + connect \ics_wb__dat_r \main_libresocsim_libresoc_xics_ics_dat_r + connect \ics_wb__dat_w \main_libresocsim_libresoc_xics_ics_dat_w + connect \ics_wb__err \main_libresocsim_libresoc_xics_ics_err + connect \ics_wb__sel \main_libresocsim_libresoc_xics_ics_sel + connect \ics_wb__stb \main_libresocsim_libresoc_xics_ics_stb + connect \ics_wb__we \main_libresocsim_libresoc_xics_ics_we + connect \int_level_i \main_libresocsim_libresoc_interrupt + connect \jtag_wb__ack \main_libresocsim_libresoc_jtag_wb_ack + connect \jtag_wb__adr \main_libresocsim_libresoc_jtag_wb_adr + connect \jtag_wb__cyc \main_libresocsim_libresoc_jtag_wb_cyc + connect \jtag_wb__dat_r \main_libresocsim_libresoc_jtag_wb_dat_r + connect \jtag_wb__dat_w \main_libresocsim_libresoc_jtag_wb_dat_w + connect \jtag_wb__err \main_libresocsim_libresoc_jtag_wb_err + connect \jtag_wb__sel \main_libresocsim_libresoc_jtag_wb_sel + connect \jtag_wb__stb \main_libresocsim_libresoc_jtag_wb_stb + connect \jtag_wb__we \main_libresocsim_libresoc_jtag_wb_we + connect \memerr_o \main_libresocsim_libresoc1 + connect \pc_i 1'0 + connect \pc_i_ok 1'0 + connect \pc_o \main_libresocsim_libresoc2 + connect \rst $or$ls180.v:10199$2754_Y + connect \uart_rx__core__i \main_libresocsim_libresoc_constraintmanager0_uart0_rx + connect \uart_rx__pad__i \main_libresocsim_libresoc_constraintmanager1_uart0_rx + connect \uart_tx__core__o \main_libresocsim_libresoc_constraintmanager0_uart0_tx + connect \uart_tx__pad__o \main_libresocsim_libresoc_constraintmanager1_uart0_tx + end + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$3704 + sync always + sync init + end + attribute \src "ls180.v:10001.1-10005.4" + process $proc$ls180.v:10001$2698 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage$ls180.v:10003$5_ADDR[2:0]$2699 3'xxx + assign $0$memwr$\storage$ls180.v:10003$5_DATA[24:0]$2700 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage$ls180.v:10003$5_EN[24:0]$2701 25'0000000000000000000000000 + assign $0\memdat[24:0] $memrd$\storage$ls180.v:10004$2702_DATA + attribute \src "ls180.v:10002.2-10003.129" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10002.6-10002.60" + case 1'1 + assign $0$memwr$\storage$ls180.v:10003$5_ADDR[2:0]$2699 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage$ls180.v:10003$5_DATA[24:0]$2700 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage$ls180.v:10003$5_EN[24:0]$2701 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat $0\memdat[24:0] + update $memwr$\storage$ls180.v:10003$5_ADDR $0$memwr$\storage$ls180.v:10003$5_ADDR[2:0]$2699 + update $memwr$\storage$ls180.v:10003$5_DATA $0$memwr$\storage$ls180.v:10003$5_DATA[24:0]$2700 + update $memwr$\storage$ls180.v:10003$5_EN $0$memwr$\storage$ls180.v:10003$5_EN[24:0]$2701 + end + attribute \src "ls180.v:10007.1-10008.4" + process $proc$ls180.v:10007$2703 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10015.1-10019.4" + process $proc$ls180.v:10015$2705 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_1$ls180.v:10017$6_ADDR[2:0]$2706 3'xxx + assign $0$memwr$\storage_1$ls180.v:10017$6_DATA[24:0]$2707 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_1$ls180.v:10017$6_EN[24:0]$2708 25'0000000000000000000000000 + assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10018$2709_DATA + attribute \src "ls180.v:10016.2-10017.131" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10016.6-10016.60" + case 1'1 + assign $0$memwr$\storage_1$ls180.v:10017$6_ADDR[2:0]$2706 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_1$ls180.v:10017$6_DATA[24:0]$2707 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_1$ls180.v:10017$6_EN[24:0]$2708 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_1 $0\memdat_1[24:0] + update $memwr$\storage_1$ls180.v:10017$6_ADDR $0$memwr$\storage_1$ls180.v:10017$6_ADDR[2:0]$2706 + update $memwr$\storage_1$ls180.v:10017$6_DATA $0$memwr$\storage_1$ls180.v:10017$6_DATA[24:0]$2707 + update $memwr$\storage_1$ls180.v:10017$6_EN $0$memwr$\storage_1$ls180.v:10017$6_EN[24:0]$2708 + end + attribute \src "ls180.v:1002.12-1002.37" + process $proc$ls180.v:1002$3153 + assign { } { } + assign $1\main_pwm0_counter[31:0] 0 + sync always + sync init + update \main_pwm0_counter $1\main_pwm0_counter[31:0] + end + attribute \src "ls180.v:10021.1-10022.4" + process $proc$ls180.v:10021$2710 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10029.1-10033.4" + process $proc$ls180.v:10029$2712 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_2$ls180.v:10031$7_ADDR[2:0]$2713 3'xxx + assign $0$memwr$\storage_2$ls180.v:10031$7_DATA[24:0]$2714 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_2$ls180.v:10031$7_EN[24:0]$2715 25'0000000000000000000000000 + assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10032$2716_DATA + attribute \src "ls180.v:10030.2-10031.131" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10030.6-10030.60" + case 1'1 + assign $0$memwr$\storage_2$ls180.v:10031$7_ADDR[2:0]$2713 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_2$ls180.v:10031$7_DATA[24:0]$2714 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_2$ls180.v:10031$7_EN[24:0]$2715 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_2 $0\memdat_2[24:0] + update $memwr$\storage_2$ls180.v:10031$7_ADDR $0$memwr$\storage_2$ls180.v:10031$7_ADDR[2:0]$2713 + update $memwr$\storage_2$ls180.v:10031$7_DATA $0$memwr$\storage_2$ls180.v:10031$7_DATA[24:0]$2714 + update $memwr$\storage_2$ls180.v:10031$7_EN $0$memwr$\storage_2$ls180.v:10031$7_EN[24:0]$2715 + end + attribute \src "ls180.v:1003.5-1003.36" + process $proc$ls180.v:1003$3154 + assign { } { } + assign $1\main_pwm0_enable_storage[0:0] 1'0 + sync always + sync init + update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0] + end + attribute \src "ls180.v:10035.1-10036.4" + process $proc$ls180.v:10035$2717 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:1004.5-1004.31" + process $proc$ls180.v:1004$3155 + assign { } { } + assign $1\main_pwm0_enable_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0] + end + attribute \src "ls180.v:10043.1-10047.4" + process $proc$ls180.v:10043$2719 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_3$ls180.v:10045$8_ADDR[2:0]$2720 3'xxx + assign $0$memwr$\storage_3$ls180.v:10045$8_DATA[24:0]$2721 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_3$ls180.v:10045$8_EN[24:0]$2722 25'0000000000000000000000000 + assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10046$2723_DATA + attribute \src "ls180.v:10044.2-10045.131" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10044.6-10044.60" + case 1'1 + assign $0$memwr$\storage_3$ls180.v:10045$8_ADDR[2:0]$2720 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_3$ls180.v:10045$8_DATA[24:0]$2721 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_3$ls180.v:10045$8_EN[24:0]$2722 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_3 $0\memdat_3[24:0] + update $memwr$\storage_3$ls180.v:10045$8_ADDR $0$memwr$\storage_3$ls180.v:10045$8_ADDR[2:0]$2720 + update $memwr$\storage_3$ls180.v:10045$8_DATA $0$memwr$\storage_3$ls180.v:10045$8_DATA[24:0]$2721 + update $memwr$\storage_3$ls180.v:10045$8_EN $0$memwr$\storage_3$ls180.v:10045$8_EN[24:0]$2722 + end + attribute \src "ls180.v:10049.1-10050.4" + process $proc$ls180.v:10049$2724 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:1005.12-1005.43" + process $proc$ls180.v:1005$3156 + assign { } { } + assign $1\main_pwm0_width_storage[31:0] 0 + sync always + sync init + update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0] + end + attribute \src "ls180.v:10058.1-10062.4" + process $proc$ls180.v:10058$2726 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_4$ls180.v:10060$9_ADDR[3:0]$2727 4'xxxx + assign $0$memwr$\storage_4$ls180.v:10060$9_DATA[9:0]$2728 10'xxxxxxxxxx + assign $0$memwr$\storage_4$ls180.v:10060$9_EN[9:0]$2729 10'0000000000 + assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10061$2730_DATA + attribute \src "ls180.v:10059.2-10060.77" + switch \main_uart_tx_fifo_wrport_we + attribute \src "ls180.v:10059.6-10059.33" + case 1'1 + assign $0$memwr$\storage_4$ls180.v:10060$9_ADDR[3:0]$2727 \main_uart_tx_fifo_wrport_adr + assign $0$memwr$\storage_4$ls180.v:10060$9_DATA[9:0]$2728 \main_uart_tx_fifo_wrport_dat_w + assign $0$memwr$\storage_4$ls180.v:10060$9_EN[9:0]$2729 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_4 $0\memdat_4[9:0] + update $memwr$\storage_4$ls180.v:10060$9_ADDR $0$memwr$\storage_4$ls180.v:10060$9_ADDR[3:0]$2727 + update $memwr$\storage_4$ls180.v:10060$9_DATA $0$memwr$\storage_4$ls180.v:10060$9_DATA[9:0]$2728 + update $memwr$\storage_4$ls180.v:10060$9_EN $0$memwr$\storage_4$ls180.v:10060$9_EN[9:0]$2729 + end + attribute \src "ls180.v:1006.5-1006.30" + process $proc$ls180.v:1006$3157 + assign { } { } + assign $1\main_pwm0_width_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_width_re $1\main_pwm0_width_re[0:0] + end + attribute \src "ls180.v:10064.1-10067.4" + process $proc$ls180.v:10064$2731 + assign $0\memdat_5[9:0] \memdat_5 + attribute \src "ls180.v:10065.2-10066.55" + switch \main_uart_tx_fifo_rdport_re + attribute \src "ls180.v:10065.6-10065.33" + case 1'1 + assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10066$2732_DATA + case + end + sync posedge \sys_clk_1 + update \memdat_5 $0\memdat_5[9:0] + end + attribute \src "ls180.v:1007.12-1007.44" + process $proc$ls180.v:1007$3158 + assign { } { } + assign $1\main_pwm0_period_storage[31:0] 0 + sync always + sync init + update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0] + end + attribute \src "ls180.v:10075.1-10079.4" + process $proc$ls180.v:10075$2733 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_5$ls180.v:10077$10_ADDR[3:0]$2734 4'xxxx + assign $0$memwr$\storage_5$ls180.v:10077$10_DATA[9:0]$2735 10'xxxxxxxxxx + assign $0$memwr$\storage_5$ls180.v:10077$10_EN[9:0]$2736 10'0000000000 + assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10078$2737_DATA + attribute \src "ls180.v:10076.2-10077.77" + switch \main_uart_rx_fifo_wrport_we + attribute \src "ls180.v:10076.6-10076.33" + case 1'1 + assign $0$memwr$\storage_5$ls180.v:10077$10_ADDR[3:0]$2734 \main_uart_rx_fifo_wrport_adr + assign $0$memwr$\storage_5$ls180.v:10077$10_DATA[9:0]$2735 \main_uart_rx_fifo_wrport_dat_w + assign $0$memwr$\storage_5$ls180.v:10077$10_EN[9:0]$2736 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_6 $0\memdat_6[9:0] + update $memwr$\storage_5$ls180.v:10077$10_ADDR $0$memwr$\storage_5$ls180.v:10077$10_ADDR[3:0]$2734 + update $memwr$\storage_5$ls180.v:10077$10_DATA $0$memwr$\storage_5$ls180.v:10077$10_DATA[9:0]$2735 + update $memwr$\storage_5$ls180.v:10077$10_EN $0$memwr$\storage_5$ls180.v:10077$10_EN[9:0]$2736 + end + attribute \src "ls180.v:1008.5-1008.31" + process $proc$ls180.v:1008$3159 + assign { } { } + assign $1\main_pwm0_period_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_period_re $1\main_pwm0_period_re[0:0] + end + attribute \src "ls180.v:10081.1-10084.4" + process $proc$ls180.v:10081$2738 + assign $0\memdat_7[9:0] \memdat_7 + attribute \src "ls180.v:10082.2-10083.55" + switch \main_uart_rx_fifo_rdport_re + attribute \src "ls180.v:10082.6-10082.33" + case 1'1 + assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10083$2739_DATA + case + end + sync posedge \sys_clk_1 + update \memdat_7 $0\memdat_7[9:0] + end + attribute \src "ls180.v:10091.1-10095.4" + process $proc$ls180.v:10091$2740 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_6$ls180.v:10093$11_ADDR[4:0]$2741 5'xxxxx + assign $0$memwr$\storage_6$ls180.v:10093$11_DATA[9:0]$2742 10'xxxxxxxxxx + assign $0$memwr$\storage_6$ls180.v:10093$11_EN[9:0]$2743 10'0000000000 + assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10094$2744_DATA + attribute \src "ls180.v:10092.2-10093.85" + switch \main_sdblock2mem_fifo_wrport_we + attribute \src "ls180.v:10092.6-10092.37" + case 1'1 + assign $0$memwr$\storage_6$ls180.v:10093$11_ADDR[4:0]$2741 \main_sdblock2mem_fifo_wrport_adr + assign $0$memwr$\storage_6$ls180.v:10093$11_DATA[9:0]$2742 \main_sdblock2mem_fifo_wrport_dat_w + assign $0$memwr$\storage_6$ls180.v:10093$11_EN[9:0]$2743 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_8 $0\memdat_8[9:0] + update $memwr$\storage_6$ls180.v:10093$11_ADDR $0$memwr$\storage_6$ls180.v:10093$11_ADDR[4:0]$2741 + update $memwr$\storage_6$ls180.v:10093$11_DATA $0$memwr$\storage_6$ls180.v:10093$11_DATA[9:0]$2742 + update $memwr$\storage_6$ls180.v:10093$11_EN $0$memwr$\storage_6$ls180.v:10093$11_EN[9:0]$2743 + end + attribute \src "ls180.v:10097.1-10098.4" + process $proc$ls180.v:10097$2745 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10105.1-10109.4" + process $proc$ls180.v:10105$2747 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_7$ls180.v:10107$12_ADDR[4:0]$2748 5'xxxxx + assign $0$memwr$\storage_7$ls180.v:10107$12_DATA[9:0]$2749 10'xxxxxxxxxx + assign $0$memwr$\storage_7$ls180.v:10107$12_EN[9:0]$2750 10'0000000000 + assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10108$2751_DATA + attribute \src "ls180.v:10106.2-10107.85" + switch \main_sdmem2block_fifo_wrport_we + attribute \src "ls180.v:10106.6-10106.37" + case 1'1 + assign $0$memwr$\storage_7$ls180.v:10107$12_ADDR[4:0]$2748 \main_sdmem2block_fifo_wrport_adr + assign $0$memwr$\storage_7$ls180.v:10107$12_DATA[9:0]$2749 \main_sdmem2block_fifo_wrport_dat_w + assign $0$memwr$\storage_7$ls180.v:10107$12_EN[9:0]$2750 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_9 $0\memdat_9[9:0] + update $memwr$\storage_7$ls180.v:10107$12_ADDR $0$memwr$\storage_7$ls180.v:10107$12_ADDR[4:0]$2748 + update $memwr$\storage_7$ls180.v:10107$12_DATA $0$memwr$\storage_7$ls180.v:10107$12_DATA[9:0]$2749 + update $memwr$\storage_7$ls180.v:10107$12_EN $0$memwr$\storage_7$ls180.v:10107$12_EN[9:0]$2750 + end + attribute \src "ls180.v:10111.1-10112.4" + process $proc$ls180.v:10111$2752 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:1012.12-1012.37" + process $proc$ls180.v:1012$3160 + assign { } { } + assign $1\main_pwm1_counter[31:0] 0 + sync always + sync init + update \main_pwm1_counter $1\main_pwm1_counter[31:0] + end + attribute \src "ls180.v:1013.5-1013.36" + process $proc$ls180.v:1013$3161 + assign { } { } + assign $1\main_pwm1_enable_storage[0:0] 1'0 + sync always + sync init + update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0] + end + attribute \src "ls180.v:1014.5-1014.31" + process $proc$ls180.v:1014$3162 + assign { } { } + assign $1\main_pwm1_enable_re[0:0] 1'0 + sync always + sync init + update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0] + end + attribute \src "ls180.v:1015.12-1015.43" + process $proc$ls180.v:1015$3163 + assign { } { } + assign $1\main_pwm1_width_storage[31:0] 0 + sync always + sync init + update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0] + end + attribute \src "ls180.v:1016.5-1016.30" + process $proc$ls180.v:1016$3164 + assign { } { } + assign $1\main_pwm1_width_re[0:0] 1'0 + sync always + sync init + update \main_pwm1_width_re $1\main_pwm1_width_re[0:0] + end + attribute \src "ls180.v:1017.12-1017.44" + process $proc$ls180.v:1017$3165 + assign { } { } + assign $1\main_pwm1_period_storage[31:0] 0 + sync always + sync init + update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0] + end + attribute \src "ls180.v:1018.5-1018.31" + process $proc$ls180.v:1018$3166 + assign { } { } + assign $1\main_pwm1_period_re[0:0] 1'0 + sync always + sync init + update \main_pwm1_period_re $1\main_pwm1_period_re[0:0] + end + attribute \src "ls180.v:1021.11-1021.46" + process $proc$ls180.v:1021$3167 + assign { } { } + assign $1\main_sdphy_clocker_storage[8:0] 9'100000000 + sync always + sync init + update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0] + end + attribute \src "ls180.v:1022.5-1022.33" + process $proc$ls180.v:1022$3168 + assign { } { } + assign $1\main_sdphy_clocker_re[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0] + end + attribute \src "ls180.v:1024.5-1024.35" + process $proc$ls180.v:1024$3169 + assign { } { } + assign $1\main_sdphy_clocker_clk0[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0] + end + attribute \src "ls180.v:1026.11-1026.41" + process $proc$ls180.v:1026$3170 + assign { } { } + assign $1\main_sdphy_clocker_clks[8:0] 9'000000000 + sync always + sync init + update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0] + end + attribute \src "ls180.v:1027.5-1027.35" + process $proc$ls180.v:1027$3171 + assign { } { } + assign $1\main_sdphy_clocker_clk1[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0] + end + attribute \src "ls180.v:1028.5-1028.36" + process $proc$ls180.v:1028$3172 + assign { } { } + assign $1\main_sdphy_clocker_clk_d[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0] + end + attribute \src "ls180.v:1032.5-1032.40" + process $proc$ls180.v:1032$3173 + assign { } { } + assign $0\main_sdphy_init_initialize_w[0:0] 1'0 + sync always + update \main_sdphy_init_initialize_w $0\main_sdphy_init_initialize_w[0:0] + sync init + end + attribute \src "ls180.v:1037.5-1037.48" + process $proc$ls180.v:1037$3174 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1038.5-1038.50" + process $proc$ls180.v:1038$3175 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] + end + attribute \src "ls180.v:1039.5-1039.51" + process $proc$ls180.v:1039$3176 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + end + attribute \src "ls180.v:1040.11-1040.57" + process $proc$ls180.v:1040$3177 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 + sync always + sync init + update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0] + end + attribute \src "ls180.v:1041.5-1041.52" + process $proc$ls180.v:1041$3178 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0] + end + attribute \src "ls180.v:1042.11-1042.39" + process $proc$ls180.v:1042$3179 + assign { } { } + assign $1\main_sdphy_init_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_init_count $1\main_sdphy_init_count[7:0] + end + attribute \src "ls180.v:1047.5-1047.48" + process $proc$ls180.v:1047$3180 + assign { } { } + assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1048.5-1048.50" + process $proc$ls180.v:1048$3181 + assign { } { } + assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + end + attribute \src "ls180.v:1049.5-1049.51" + process $proc$ls180.v:1049$3182 + assign { } { } + assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + end + attribute \src "ls180.v:1050.11-1050.57" + process $proc$ls180.v:1050$3183 + assign { } { } + assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_cmdw_pads_out_payload_data_o $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1051.5-1051.52" + process $proc$ls180.v:1051$3184 + assign { } { } + assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdw_pads_out_payload_data_oe $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1052.5-1052.38" + process $proc$ls180.v:1052$3185 + assign { } { } + assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0] + end + attribute \src "ls180.v:1053.5-1053.38" + process $proc$ls180.v:1053$3186 + assign { } { } + assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0] + end + attribute \src "ls180.v:1054.5-1054.37" + process $proc$ls180.v:1054$3187 + assign { } { } + assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0] + end + attribute \src "ls180.v:1055.11-1055.51" + process $proc$ls180.v:1055$3188 + assign { } { } + assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0] + end + attribute \src "ls180.v:1056.5-1056.32" + process $proc$ls180.v:1056$3189 + assign { } { } + assign $1\main_sdphy_cmdw_done[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0] + end + attribute \src "ls180.v:1057.11-1057.39" + process $proc$ls180.v:1057$3190 + assign { } { } + assign $1\main_sdphy_cmdw_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0] + end + attribute \src "ls180.v:1060.5-1060.49" + process $proc$ls180.v:1060$3191 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_first $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "ls180.v:1061.5-1061.48" + process $proc$ls180.v:1061$3192 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_last $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "ls180.v:1062.5-1062.55" + process $proc$ls180.v:1062$3193 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_clk $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "ls180.v:1064.5-1064.57" + process $proc$ls180.v:1064$3194 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1065.5-1065.58" + process $proc$ls180.v:1065$3195 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1067.11-1067.64" + process $proc$ls180.v:1067$3196 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_data_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1068.5-1068.59" + process $proc$ls180.v:1068$3197 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1070.5-1070.48" + process $proc$ls180.v:1070$3198 + assign { } { } + assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1071.5-1071.50" + process $proc$ls180.v:1071$3199 + assign { } { } + assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + end + attribute \src "ls180.v:1072.5-1072.51" + process $proc$ls180.v:1072$3200 + assign { } { } + assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + end + attribute \src "ls180.v:1073.11-1073.57" + process $proc$ls180.v:1073$3201 + assign { } { } + assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_cmdr_pads_out_payload_data_o $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1074.5-1074.52" + process $proc$ls180.v:1074$3202 + assign { } { } + assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_out_payload_data_oe $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1075.5-1075.38" + process $proc$ls180.v:1075$3203 + assign { } { } + assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0] + end + attribute \src "ls180.v:1076.5-1076.38" + process $proc$ls180.v:1076$3204 + assign { } { } + assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0] + end + attribute \src "ls180.v:1077.5-1077.37" + process $proc$ls180.v:1077$3205 + assign { } { } + assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0] + end + attribute \src "ls180.v:1078.11-1078.53" + process $proc$ls180.v:1078$3206 + assign { } { } + assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0] + end + attribute \src "ls180.v:1079.5-1079.40" + process $proc$ls180.v:1079$3207 + assign { } { } + assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0] + end + attribute \src "ls180.v:1080.5-1080.40" + process $proc$ls180.v:1080$3208 + assign { } { } + assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0] + end + attribute \src "ls180.v:1081.5-1081.39" + process $proc$ls180.v:1081$3209 + assign { } { } + assign $1\main_sdphy_cmdr_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0] + end + attribute \src "ls180.v:1082.11-1082.53" + process $proc$ls180.v:1082$3210 + assign { } { } + assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0] + end + attribute \src "ls180.v:1083.11-1083.55" + process $proc$ls180.v:1083$3211 + assign { } { } + assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + sync always + sync init + update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0] + end + attribute \src "ls180.v:1084.12-1084.48" + process $proc$ls180.v:1084$3212 + assign { } { } + assign $1\main_sdphy_cmdr_timeout[31:0] 500000 + sync always + sync init + update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0] + end + attribute \src "ls180.v:1085.11-1085.39" + process $proc$ls180.v:1085$3213 + assign { } { } + assign $1\main_sdphy_cmdr_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0] + end + attribute \src "ls180.v:1087.5-1087.46" + process $proc$ls180.v:1087$3214 + assign { } { } + assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0 + sync always + update \main_sdphy_cmdr_cmdr_pads_in_ready $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] + sync init + end + attribute \src "ls180.v:1098.5-1098.53" + process $proc$ls180.v:1098$3215 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + end + attribute \src "ls180.v:110.5-110.49" + process $proc$ls180.v:110$2777 + assign { } { } + assign $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_jtag_wb_ack $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] + end + attribute \src "ls180.v:1103.5-1103.36" + process $proc$ls180.v:1103$3216 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0] + end + attribute \src "ls180.v:1106.5-1106.53" + process $proc$ls180.v:1106$3217 + assign { } { } + assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0 + sync always + update \main_sdphy_cmdr_cmdr_converter_sink_first $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] + sync init + end + attribute \src "ls180.v:1107.5-1107.52" + process $proc$ls180.v:1107$3218 + assign { } { } + assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0 + sync always + update \main_sdphy_cmdr_cmdr_converter_sink_last $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1111.5-1111.55" + process $proc$ls180.v:1111$3219 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + end + attribute \src "ls180.v:1112.5-1112.54" + process $proc$ls180.v:1112$3220 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + end + attribute \src "ls180.v:1113.11-1113.68" + process $proc$ls180.v:1113$3221 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1114.11-1114.81" + process $proc$ls180.v:1114$3222 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + end + attribute \src "ls180.v:1115.11-1115.54" + process $proc$ls180.v:1115$3223 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] + end + attribute \src "ls180.v:1117.5-1117.53" + process $proc$ls180.v:1117$3224 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + end + attribute \src "ls180.v:112.5-112.49" + process $proc$ls180.v:112$2778 + assign { } { } + assign $0\main_libresocsim_libresoc_jtag_wb_err[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_jtag_wb_err $0\main_libresocsim_libresoc_jtag_wb_err[0:0] + sync init + end + attribute \src "ls180.v:1128.5-1128.49" + process $proc$ls180.v:1128$3225 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + end + attribute \src "ls180.v:1130.5-1130.49" + process $proc$ls180.v:1130$3226 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + end + attribute \src "ls180.v:1131.5-1131.48" + process $proc$ls180.v:1131$3227 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + end + attribute \src "ls180.v:1132.11-1132.62" + process $proc$ls180.v:1132$3228 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + end + attribute \src "ls180.v:1133.5-1133.38" + process $proc$ls180.v:1133$3229 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0] + end + attribute \src "ls180.v:1138.5-1138.49" + process $proc$ls180.v:1138$3230 + assign { } { } + assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1139.5-1139.51" + process $proc$ls180.v:1139$3231 + assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_out_payload_cmd_o $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1140.5-1140.52" + process $proc$ls180.v:1140$3232 + assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_out_payload_cmd_oe $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1141.11-1141.58" + process $proc$ls180.v:1141$3233 + assign { } { } + assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 + sync always + sync init + update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] + end + attribute \src "ls180.v:1142.5-1142.53" + process $proc$ls180.v:1142$3234 + assign { } { } + assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + end + attribute \src "ls180.v:1143.5-1143.39" + process $proc$ls180.v:1143$3235 + assign { } { } + assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0] + end + attribute \src "ls180.v:1144.5-1144.39" + process $proc$ls180.v:1144$3236 + assign { } { } + assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0] + end + attribute \src "ls180.v:1145.5-1145.39" + process $proc$ls180.v:1145$3237 + assign { } { } + assign $1\main_sdphy_dataw_sink_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0] + end + attribute \src "ls180.v:1146.5-1146.38" + process $proc$ls180.v:1146$3238 + assign { } { } + assign $1\main_sdphy_dataw_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0] + end + attribute \src "ls180.v:1147.11-1147.52" + process $proc$ls180.v:1147$3239 + assign { } { } + assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0] + end + attribute \src "ls180.v:1148.5-1148.33" + process $proc$ls180.v:1148$3240 + assign { } { } + assign $1\main_sdphy_dataw_stop[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0] + end + attribute \src "ls180.v:1149.11-1149.40" + process $proc$ls180.v:1149$3241 + assign { } { } + assign $1\main_sdphy_dataw_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0] + end + attribute \src "ls180.v:1150.5-1150.50" + process $proc$ls180.v:1150$3242 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_valid $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] + sync init + end + attribute \src "ls180.v:1152.5-1152.50" + process $proc$ls180.v:1152$3243 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_first $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "ls180.v:1153.5-1153.49" + process $proc$ls180.v:1153$3244 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_last $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "ls180.v:1154.5-1154.56" + process $proc$ls180.v:1154$3245 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_clk $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "ls180.v:1155.5-1155.58" + process $proc$ls180.v:1155$3246 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] + sync init + end + attribute \src "ls180.v:1156.5-1156.58" + process $proc$ls180.v:1156$3247 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1157.5-1157.59" + process $proc$ls180.v:1157$3248 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1158.11-1158.65" + process $proc$ls180.v:1158$3249 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_data_i $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] + sync init + end + attribute \src "ls180.v:1159.11-1159.65" + process $proc$ls180.v:1159$3250 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_data_o $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1160.5-1160.60" + process $proc$ls180.v:1160$3251 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_data_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1161.5-1161.34" + process $proc$ls180.v:1161$3252 + assign { } { } + assign $1\main_sdphy_dataw_start[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0] + end + attribute \src "ls180.v:1162.5-1162.34" + process $proc$ls180.v:1162$3253 + assign { } { } + assign $1\main_sdphy_dataw_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0] + end + attribute \src "ls180.v:1163.5-1163.34" + process $proc$ls180.v:1163$3254 + assign { } { } + assign $1\main_sdphy_dataw_error[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0] + end + attribute \src "ls180.v:1165.5-1165.47" + process $proc$ls180.v:1165$3255 + assign { } { } + assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0 + sync always + update \main_sdphy_dataw_crcr_pads_in_ready $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] + sync init + end + attribute \src "ls180.v:1176.5-1176.54" + process $proc$ls180.v:1176$3256 + assign { } { } + assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] + end + attribute \src "ls180.v:1181.5-1181.37" + process $proc$ls180.v:1181$3257 + assign { } { } + assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0] + end + attribute \src "ls180.v:1184.5-1184.54" + process $proc$ls180.v:1184$3258 + assign { } { } + assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0 + sync always + update \main_sdphy_dataw_crcr_converter_sink_first $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] + sync init + end + attribute \src "ls180.v:1185.5-1185.53" + process $proc$ls180.v:1185$3259 + assign { } { } + assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0 + sync always + update \main_sdphy_dataw_crcr_converter_sink_last $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1189.5-1189.56" + process $proc$ls180.v:1189$3260 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0] + end + attribute \src "ls180.v:1190.5-1190.55" + process $proc$ls180.v:1190$3261 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0] + end + attribute \src "ls180.v:1191.11-1191.69" + process $proc$ls180.v:1191$3262 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1192.11-1192.82" + process $proc$ls180.v:1192$3263 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + end + attribute \src "ls180.v:1193.11-1193.55" + process $proc$ls180.v:1193$3264 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0] + end + attribute \src "ls180.v:1195.5-1195.54" + process $proc$ls180.v:1195$3265 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + end + attribute \src "ls180.v:120.5-120.65" + process $proc$ls180.v:120$2779 + assign { } { } + assign $1\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1 + sync always + sync init + update \main_libresocsim_libresoc_constraintmanager0_uart0_tx $1\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] + end + attribute \src "ls180.v:1206.5-1206.50" + process $proc$ls180.v:1206$3266 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] + end + attribute \src "ls180.v:1208.5-1208.50" + process $proc$ls180.v:1208$3267 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0] + end + attribute \src "ls180.v:1209.5-1209.49" + process $proc$ls180.v:1209$3268 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0] + end + attribute \src "ls180.v:1210.11-1210.63" + process $proc$ls180.v:1210$3269 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + end + attribute \src "ls180.v:1211.5-1211.39" + process $proc$ls180.v:1211$3270 + assign { } { } + assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0] + end + attribute \src "ls180.v:1214.5-1214.50" + process $proc$ls180.v:1214$3271 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_first $0\main_sdphy_datar_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "ls180.v:1215.5-1215.49" + process $proc$ls180.v:1215$3272 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_last $0\main_sdphy_datar_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "ls180.v:1216.5-1216.56" + process $proc$ls180.v:1216$3273 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_clk $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "ls180.v:1218.5-1218.58" + process $proc$ls180.v:1218$3274 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_cmd_o $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1219.5-1219.59" + process $proc$ls180.v:1219$3275 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1221.11-1221.65" + process $proc$ls180.v:1221$3276 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_data_o $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1222.5-1222.60" + process $proc$ls180.v:1222$3277 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1224.5-1224.49" + process $proc$ls180.v:1224$3278 + assign { } { } + assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1225.5-1225.51" + process $proc$ls180.v:1225$3279 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_out_payload_cmd_o $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1226.5-1226.52" + process $proc$ls180.v:1226$3280 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_out_payload_cmd_oe $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1227.11-1227.58" + process $proc$ls180.v:1227$3281 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_datar_pads_out_payload_data_o $0\main_sdphy_datar_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1228.5-1228.53" + process $proc$ls180.v:1228$3282 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_out_payload_data_oe $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1229.5-1229.39" + process $proc$ls180.v:1229$3283 + assign { } { } + assign $1\main_sdphy_datar_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0] + end + attribute \src "ls180.v:1230.5-1230.39" + process $proc$ls180.v:1230$3284 + assign { } { } + assign $1\main_sdphy_datar_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0] + end + attribute \src "ls180.v:1231.5-1231.38" + process $proc$ls180.v:1231$3285 + assign { } { } + assign $1\main_sdphy_datar_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0] + end + attribute \src "ls180.v:1232.11-1232.61" + process $proc$ls180.v:1232$3286 + assign { } { } + assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 + sync always + sync init + update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0] + end + attribute \src "ls180.v:1233.5-1233.41" + process $proc$ls180.v:1233$3287 + assign { } { } + assign $1\main_sdphy_datar_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0] + end + attribute \src "ls180.v:1234.5-1234.41" + process $proc$ls180.v:1234$3288 + assign { } { } + assign $1\main_sdphy_datar_source_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0] + end + attribute \src "ls180.v:1235.5-1235.41" + process $proc$ls180.v:1235$3289 + assign { } { } + assign $0\main_sdphy_datar_source_first[0:0] 1'0 + sync always + update \main_sdphy_datar_source_first $0\main_sdphy_datar_source_first[0:0] + sync init + end + attribute \src "ls180.v:1236.5-1236.40" + process $proc$ls180.v:1236$3290 + assign { } { } + assign $1\main_sdphy_datar_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0] + end + attribute \src "ls180.v:1237.11-1237.54" + process $proc$ls180.v:1237$3291 + assign { } { } + assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0] + end + attribute \src "ls180.v:1238.11-1238.56" + process $proc$ls180.v:1238$3292 + assign { } { } + assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000 + sync always + sync init + update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0] + end + attribute \src "ls180.v:1239.5-1239.33" + process $proc$ls180.v:1239$3293 + assign { } { } + assign $1\main_sdphy_datar_stop[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0] + end + attribute \src "ls180.v:1240.12-1240.49" + process $proc$ls180.v:1240$3294 + assign { } { } + assign $1\main_sdphy_datar_timeout[31:0] 500000 + sync always + sync init + update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0] + end + attribute \src "ls180.v:1241.11-1241.41" + process $proc$ls180.v:1241$3295 + assign { } { } + assign $1\main_sdphy_datar_count[9:0] 10'0000000000 + sync always + sync init + update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0] + end + attribute \src "ls180.v:1243.5-1243.48" + process $proc$ls180.v:1243$3296 + assign { } { } + assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0 + sync always + update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0] + sync init + end + attribute \src "ls180.v:1254.5-1254.55" + process $proc$ls180.v:1254$3297 + assign { } { } + assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0] + end + attribute \src "ls180.v:1259.5-1259.38" + process $proc$ls180.v:1259$3298 + assign { } { } + assign $1\main_sdphy_datar_datar_run[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0] + end + attribute \src "ls180.v:1262.5-1262.55" + process $proc$ls180.v:1262$3299 + assign { } { } + assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0 + sync always + update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0] + sync init + end + attribute \src "ls180.v:1263.5-1263.54" + process $proc$ls180.v:1263$3300 + assign { } { } + assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0 + sync always + update \main_sdphy_datar_datar_converter_sink_last $0\main_sdphy_datar_datar_converter_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1267.5-1267.57" + process $proc$ls180.v:1267$3301 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0] + end + attribute \src "ls180.v:1268.5-1268.56" + process $proc$ls180.v:1268$3302 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0] + end + attribute \src "ls180.v:1269.11-1269.70" + process $proc$ls180.v:1269$3303 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1270.11-1270.83" + process $proc$ls180.v:1270$3304 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + end + attribute \src "ls180.v:1271.5-1271.50" + process $proc$ls180.v:1271$3305 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0] + end + attribute \src "ls180.v:1273.5-1273.55" + process $proc$ls180.v:1273$3306 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1284.5-1284.51" + process $proc$ls180.v:1284$3307 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0] + end + attribute \src "ls180.v:1286.5-1286.51" + process $proc$ls180.v:1286$3308 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0] + end + attribute \src "ls180.v:1287.5-1287.50" + process $proc$ls180.v:1287$3309 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0] + end + attribute \src "ls180.v:1288.11-1288.64" + process $proc$ls180.v:1288$3310 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] + end + attribute \src "ls180.v:1289.5-1289.40" + process $proc$ls180.v:1289$3311 + assign { } { } + assign $1\main_sdphy_datar_datar_reset[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0] + end + attribute \src "ls180.v:1291.5-1291.35" + process $proc$ls180.v:1291$3312 + assign { } { } + assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0 + sync always + sync init + update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0] + end + attribute \src "ls180.v:1294.11-1294.42" + process $proc$ls180.v:1294$3313 + assign { } { } + assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000 + sync always + sync init + update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0] + end + attribute \src "ls180.v:130.12-130.71" + process $proc$ls180.v:130$2780 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_adr $1\main_libresocsim_interface0_converted_interface_adr[29:0] + end + attribute \src "ls180.v:1307.12-1307.52" + process $proc$ls180.v:1307$3314 + assign { } { } + assign $1\main_sdcore_cmd_argument_storage[31:0] 0 + sync always + sync init + update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0] + end + attribute \src "ls180.v:1308.5-1308.39" + process $proc$ls180.v:1308$3315 + assign { } { } + assign $1\main_sdcore_cmd_argument_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0] + end + attribute \src "ls180.v:1309.12-1309.51" + process $proc$ls180.v:1309$3316 + assign { } { } + assign $1\main_sdcore_cmd_command_storage[31:0] 0 + sync always + sync init + update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0] + end + attribute \src "ls180.v:131.12-131.73" + process $proc$ls180.v:131$2781 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:1310.5-1310.38" + process $proc$ls180.v:1310$3317 + assign { } { } + assign $1\main_sdcore_cmd_command_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0] + end + attribute \src "ls180.v:1314.5-1314.34" + process $proc$ls180.v:1314$3318 + assign { } { } + assign $0\main_sdcore_cmd_send_w[0:0] 1'0 + sync always + update \main_sdcore_cmd_send_w $0\main_sdcore_cmd_send_w[0:0] + sync init + end + attribute \src "ls180.v:1315.13-1315.53" + process $proc$ls180.v:1315$3319 + assign { } { } + assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0] + end + attribute \src "ls180.v:1321.11-1321.51" + process $proc$ls180.v:1321$3320 + assign { } { } + assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000 + sync always + sync init + update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0] + end + attribute \src "ls180.v:1322.5-1322.39" + process $proc$ls180.v:1322$3321 + assign { } { } + assign $1\main_sdcore_block_length_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0] + end + attribute \src "ls180.v:1323.12-1323.51" + process $proc$ls180.v:1323$3322 + assign { } { } + assign $1\main_sdcore_block_count_storage[31:0] 0 + sync always + sync init + update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0] + end + attribute \src "ls180.v:1324.5-1324.38" + process $proc$ls180.v:1324$3323 + assign { } { } + assign $1\main_sdcore_block_count_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0] + end + attribute \src "ls180.v:1325.11-1325.51" + process $proc$ls180.v:1325$3324 + assign { } { } + assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + sync always + sync init + update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0] + end + attribute \src "ls180.v:133.11-133.69" + process $proc$ls180.v:133$2782 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_sel $1\main_libresocsim_interface0_converted_interface_sel[3:0] + end + attribute \src "ls180.v:134.5-134.63" + process $proc$ls180.v:134$2783 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_cyc $1\main_libresocsim_interface0_converted_interface_cyc[0:0] + end + attribute \src "ls180.v:135.5-135.63" + process $proc$ls180.v:135$2784 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_stb $1\main_libresocsim_interface0_converted_interface_stb[0:0] + end + attribute \src "ls180.v:1367.11-1367.47" + process $proc$ls180.v:1367$3325 + assign { } { } + assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 + sync always + sync init + update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0] + end + attribute \src "ls180.v:137.5-137.62" + process $proc$ls180.v:137$2785 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_we $1\main_libresocsim_interface0_converted_interface_we[0:0] + end + attribute \src "ls180.v:1371.5-1371.49" + process $proc$ls180.v:1371$3326 + assign { } { } + assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0] + end + attribute \src "ls180.v:1375.5-1375.51" + process $proc$ls180.v:1375$3327 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0] + end + attribute \src "ls180.v:1376.5-1376.51" + process $proc$ls180.v:1376$3328 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0] + end + attribute \src "ls180.v:1377.5-1377.51" + process $proc$ls180.v:1377$3329 + assign { } { } + assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0 + sync always + update \main_sdcore_crc16_inserter_source_first $0\main_sdcore_crc16_inserter_source_first[0:0] + sync init + end + attribute \src "ls180.v:1378.5-1378.50" + process $proc$ls180.v:1378$3330 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0] + end + attribute \src "ls180.v:1379.11-1379.64" + process $proc$ls180.v:1379$3331 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0] + end + attribute \src "ls180.v:138.11-138.69" + process $proc$ls180.v:138$2786 + assign { } { } + assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000 + sync always + update \main_libresocsim_interface0_converted_interface_cti $0\main_libresocsim_interface0_converted_interface_cti[2:0] + sync init + end + attribute \src "ls180.v:1380.11-1380.48" + process $proc$ls180.v:1380$3332 + assign { } { } + assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000 + sync always + sync init + update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0] + end + attribute \src "ls180.v:1381.12-1381.59" + process $proc$ls180.v:1381$3333 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + end + attribute \src "ls180.v:1385.12-1385.55" + process $proc$ls180.v:1385$3334 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0] + end + attribute \src "ls180.v:1388.12-1388.59" + process $proc$ls180.v:1388$3335 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + end + attribute \src "ls180.v:139.11-139.69" + process $proc$ls180.v:139$2787 + assign { } { } + assign $0\main_libresocsim_interface0_converted_interface_bte[1:0] 2'00 + sync always + update \main_libresocsim_interface0_converted_interface_bte $0\main_libresocsim_interface0_converted_interface_bte[1:0] + sync init + end + attribute \src "ls180.v:1392.12-1392.55" + process $proc$ls180.v:1392$3336 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0] + end + attribute \src "ls180.v:1395.12-1395.59" + process $proc$ls180.v:1395$3337 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + end + attribute \src "ls180.v:1399.12-1399.55" + process $proc$ls180.v:1399$3338 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0] + end + attribute \src "ls180.v:1402.12-1402.59" + process $proc$ls180.v:1402$3339 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + end + attribute \src "ls180.v:1406.12-1406.55" + process $proc$ls180.v:1406$3340 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0] + end + attribute \src "ls180.v:1409.12-1409.54" + process $proc$ls180.v:1409$3341 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0] + end + attribute \src "ls180.v:141.5-141.44" + process $proc$ls180.v:141$2788 + assign { } { } + assign $1\main_libresocsim_converter0_skip[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0] + end + attribute \src "ls180.v:1410.12-1410.54" + process $proc$ls180.v:1410$3342 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0] + end + attribute \src "ls180.v:1411.12-1411.54" + process $proc$ls180.v:1411$3343 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0] + end + attribute \src "ls180.v:1412.12-1412.54" + process $proc$ls180.v:1412$3344 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0] + end + attribute \src "ls180.v:1413.5-1413.48" + process $proc$ls180.v:1413$3345 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0] + end + attribute \src "ls180.v:1414.5-1414.48" + process $proc$ls180.v:1414$3346 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0] + end + attribute \src "ls180.v:1415.5-1415.48" + process $proc$ls180.v:1415$3347 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0] + end + attribute \src "ls180.v:1416.5-1416.47" + process $proc$ls180.v:1416$3348 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0] + end + attribute \src "ls180.v:1417.11-1417.61" + process $proc$ls180.v:1417$3349 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0] + end + attribute \src "ls180.v:1418.5-1418.50" + process $proc$ls180.v:1418$3350 + assign { } { } + assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0] + end + attribute \src "ls180.v:142.5-142.47" + process $proc$ls180.v:142$2789 + assign { } { } + assign $1\main_libresocsim_converter0_counter[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0] + end + attribute \src "ls180.v:1420.5-1420.50" + process $proc$ls180.v:1420$3351 + assign { } { } + assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0 + sync always + update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0] + sync init + end + attribute \src "ls180.v:1423.11-1423.47" + process $proc$ls180.v:1423$3352 + assign { } { } + assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000 + sync always + sync init + update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0] + end + attribute \src "ls180.v:1424.11-1424.47" + process $proc$ls180.v:1424$3353 + assign { } { } + assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000 + sync always + sync init + update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0] + end + attribute \src "ls180.v:1425.12-1425.58" + process $proc$ls180.v:1425$3354 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + end + attribute \src "ls180.v:1429.12-1429.54" + process $proc$ls180.v:1429$3355 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0] + end + attribute \src "ls180.v:1430.5-1430.46" + process $proc$ls180.v:1430$3356 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0] + end + attribute \src "ls180.v:1432.12-1432.58" + process $proc$ls180.v:1432$3357 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + end + attribute \src "ls180.v:1436.12-1436.54" + process $proc$ls180.v:1436$3358 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0] + end + attribute \src "ls180.v:1437.5-1437.46" + process $proc$ls180.v:1437$3359 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0] + end + attribute \src "ls180.v:1439.12-1439.58" + process $proc$ls180.v:1439$3360 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + end + attribute \src "ls180.v:144.12-144.53" + process $proc$ls180.v:144$2790 + assign { } { } + assign $1\main_libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_converter0_dat_r $1\main_libresocsim_converter0_dat_r[63:0] + end + attribute \src "ls180.v:1443.12-1443.54" + process $proc$ls180.v:1443$3361 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0] + end + attribute \src "ls180.v:1444.5-1444.46" + process $proc$ls180.v:1444$3362 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0] + end + attribute \src "ls180.v:1446.12-1446.58" + process $proc$ls180.v:1446$3363 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + end + attribute \src "ls180.v:145.12-145.71" + process $proc$ls180.v:145$2791 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0] + end + attribute \src "ls180.v:1450.12-1450.54" + process $proc$ls180.v:1450$3364 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0] + end + attribute \src "ls180.v:1451.5-1451.46" + process $proc$ls180.v:1451$3365 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0] + end + attribute \src "ls180.v:1453.12-1453.53" + process $proc$ls180.v:1453$3366 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0] + end + attribute \src "ls180.v:1454.12-1454.53" + process $proc$ls180.v:1454$3367 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0] + end + attribute \src "ls180.v:1455.12-1455.53" + process $proc$ls180.v:1455$3368 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0] + end + attribute \src "ls180.v:1456.12-1456.53" + process $proc$ls180.v:1456$3369 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0] + end + attribute \src "ls180.v:1457.5-1457.43" + process $proc$ls180.v:1457$3370 + assign { } { } + assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0] + end + attribute \src "ls180.v:1458.12-1458.51" + process $proc$ls180.v:1458$3371 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0] + end + attribute \src "ls180.v:1459.12-1459.51" + process $proc$ls180.v:1459$3372 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0] + end + attribute \src "ls180.v:146.12-146.73" + process $proc$ls180.v:146$2792 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:1460.12-1460.51" + process $proc$ls180.v:1460$3373 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0] + end + attribute \src "ls180.v:1461.12-1461.51" + process $proc$ls180.v:1461$3374 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0] + end + attribute \src "ls180.v:1463.11-1463.39" + process $proc$ls180.v:1463$3375 + assign { } { } + assign $1\main_sdcore_cmd_count[2:0] 3'000 + sync always + sync init + update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0] + end + attribute \src "ls180.v:1464.5-1464.32" + process $proc$ls180.v:1464$3376 + assign { } { } + assign $1\main_sdcore_cmd_done[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0] + end + attribute \src "ls180.v:1465.5-1465.33" + process $proc$ls180.v:1465$3377 + assign { } { } + assign $1\main_sdcore_cmd_error[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0] + end + attribute \src "ls180.v:1466.5-1466.35" + process $proc$ls180.v:1466$3378 + assign { } { } + assign $1\main_sdcore_cmd_timeout[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0] + end + attribute \src "ls180.v:1468.12-1468.42" + process $proc$ls180.v:1468$3379 + assign { } { } + assign $1\main_sdcore_data_count[31:0] 0 + sync always + sync init + update \main_sdcore_data_count $1\main_sdcore_data_count[31:0] + end + attribute \src "ls180.v:1469.5-1469.33" + process $proc$ls180.v:1469$3380 + assign { } { } + assign $1\main_sdcore_data_done[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_done $1\main_sdcore_data_done[0:0] + end + attribute \src "ls180.v:1470.5-1470.34" + process $proc$ls180.v:1470$3381 + assign { } { } + assign $1\main_sdcore_data_error[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_error $1\main_sdcore_data_error[0:0] + end + attribute \src "ls180.v:1471.5-1471.36" + process $proc$ls180.v:1471$3382 + assign { } { } + assign $1\main_sdcore_data_timeout[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0] + end + attribute \src "ls180.v:148.11-148.69" + process $proc$ls180.v:148$2793 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0] + end + attribute \src "ls180.v:1480.11-1480.41" + process $proc$ls180.v:1480$3383 + assign { } { } + assign $0\main_interface0_bus_cti[2:0] 3'000 + sync always + update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0] + sync init + end + attribute \src "ls180.v:1481.11-1481.41" + process $proc$ls180.v:1481$3384 + assign { } { } + assign $0\main_interface0_bus_bte[1:0] 2'00 + sync always + update \main_interface0_bus_bte $0\main_interface0_bus_bte[1:0] + sync init + end + attribute \src "ls180.v:149.5-149.63" + process $proc$ls180.v:149$2794 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_cyc $1\main_libresocsim_interface1_converted_interface_cyc[0:0] + end + attribute \src "ls180.v:150.5-150.63" + process $proc$ls180.v:150$2795 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_stb $1\main_libresocsim_interface1_converted_interface_stb[0:0] + end + attribute \src "ls180.v:1504.11-1504.45" + process $proc$ls180.v:1504$3385 + assign { } { } + assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000 + sync always + sync init + update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0] + end + attribute \src "ls180.v:1505.5-1505.41" + process $proc$ls180.v:1505$3386 + assign { } { } + assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0 + sync always + update \main_sdblock2mem_fifo_replace $0\main_sdblock2mem_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:1506.11-1506.47" + process $proc$ls180.v:1506$3387 + assign { } { } + assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000 + sync always + sync init + update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0] + end + attribute \src "ls180.v:1507.11-1507.47" + process $proc$ls180.v:1507$3388 + assign { } { } + assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000 + sync always + sync init + update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0] + end + attribute \src "ls180.v:1508.11-1508.50" + process $proc$ls180.v:1508$3389 + assign { } { } + assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 + sync always + sync init + update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:152.5-152.62" + process $proc$ls180.v:152$2796 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_we $1\main_libresocsim_interface1_converted_interface_we[0:0] + end + attribute \src "ls180.v:1528.5-1528.51" + process $proc$ls180.v:1528$3390 + assign { } { } + assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0] + end + attribute \src "ls180.v:1529.5-1529.50" + process $proc$ls180.v:1529$3391 + assign { } { } + assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0] + end + attribute \src "ls180.v:153.11-153.69" + process $proc$ls180.v:153$2797 + assign { } { } + assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000 + sync always + update \main_libresocsim_interface1_converted_interface_cti $0\main_libresocsim_interface1_converted_interface_cti[2:0] + sync init + end + attribute \src "ls180.v:1530.12-1530.66" + process $proc$ls180.v:1530$3392 + assign { } { } + assign $1\main_sdblock2mem_converter_source_payload_data[31:0] 0 + sync always + sync init + update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[31:0] + end + attribute \src "ls180.v:1531.11-1531.77" + process $proc$ls180.v:1531$3393 + assign { } { } + assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] 3'000 + sync always + sync init + update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] + end + attribute \src "ls180.v:1532.11-1532.50" + process $proc$ls180.v:1532$3394 + assign { } { } + assign $1\main_sdblock2mem_converter_demux[1:0] 2'00 + sync always + sync init + update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[1:0] + end + attribute \src "ls180.v:1534.5-1534.49" + process $proc$ls180.v:1534$3395 + assign { } { } + assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0] + end + attribute \src "ls180.v:154.11-154.69" + process $proc$ls180.v:154$2798 + assign { } { } + assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00 + sync always + update \main_libresocsim_interface1_converted_interface_bte $0\main_libresocsim_interface1_converted_interface_bte[1:0] + sync init + end + attribute \src "ls180.v:1540.5-1540.45" + process $proc$ls180.v:1540$3396 + assign { } { } + assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] + end + attribute \src "ls180.v:1542.12-1542.62" + process $proc$ls180.v:1542$3397 + assign { } { } + assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0 + sync always + sync init + update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0] + end + attribute \src "ls180.v:1543.12-1543.60" + process $proc$ls180.v:1543$3398 + assign { } { } + assign $1\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 + sync always + sync init + update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[31:0] + end + attribute \src "ls180.v:1545.5-1545.57" + process $proc$ls180.v:1545$3399 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + end + attribute \src "ls180.v:1549.12-1549.67" + process $proc$ls180.v:1549$3400 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + end + attribute \src "ls180.v:1550.5-1550.54" + process $proc$ls180.v:1550$3401 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + end + attribute \src "ls180.v:1551.12-1551.69" + process $proc$ls180.v:1551$3402 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + end + attribute \src "ls180.v:1552.5-1552.56" + process $proc$ls180.v:1552$3403 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + end + attribute \src "ls180.v:1553.5-1553.61" + process $proc$ls180.v:1553$3404 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + end + attribute \src "ls180.v:1554.5-1554.56" + process $proc$ls180.v:1554$3405 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + end + attribute \src "ls180.v:1555.5-1555.53" + process $proc$ls180.v:1555$3406 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0] + end + attribute \src "ls180.v:1557.5-1557.59" + process $proc$ls180.v:1557$3407 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + end + attribute \src "ls180.v:1558.5-1558.54" + process $proc$ls180.v:1558$3408 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + end + attribute \src "ls180.v:156.5-156.44" + process $proc$ls180.v:156$2799 + assign { } { } + assign $1\main_libresocsim_converter1_skip[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0] + end + attribute \src "ls180.v:1560.12-1560.61" + process $proc$ls180.v:1560$3409 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] + end + attribute \src "ls180.v:1563.12-1563.43" + process $proc$ls180.v:1563$3410 + assign { } { } + assign $1\main_interface1_bus_adr[31:0] 0 + sync always + sync init + update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0] + end + attribute \src "ls180.v:1564.12-1564.45" + process $proc$ls180.v:1564$3411 + assign { } { } + assign $0\main_interface1_bus_dat_w[31:0] 0 + sync always + update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[31:0] + sync init + end + attribute \src "ls180.v:1566.11-1566.41" + process $proc$ls180.v:1566$3412 + assign { } { } + assign $1\main_interface1_bus_sel[3:0] 4'0000 + sync always + sync init + update \main_interface1_bus_sel $1\main_interface1_bus_sel[3:0] + end + attribute \src "ls180.v:1567.5-1567.35" + process $proc$ls180.v:1567$3413 + assign { } { } + assign $1\main_interface1_bus_cyc[0:0] 1'0 + sync always + sync init + update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0] + end + attribute \src "ls180.v:1568.5-1568.35" + process $proc$ls180.v:1568$3414 + assign { } { } + assign $1\main_interface1_bus_stb[0:0] 1'0 + sync always + sync init + update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0] + end + attribute \src "ls180.v:157.5-157.47" + process $proc$ls180.v:157$2800 + assign { } { } + assign $1\main_libresocsim_converter1_counter[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0] + end + attribute \src "ls180.v:1570.5-1570.34" + process $proc$ls180.v:1570$3415 + assign { } { } + assign $1\main_interface1_bus_we[0:0] 1'0 + sync always + sync init + update \main_interface1_bus_we $1\main_interface1_bus_we[0:0] + end + attribute \src "ls180.v:1571.11-1571.41" + process $proc$ls180.v:1571$3416 + assign { } { } + assign $0\main_interface1_bus_cti[2:0] 3'000 + sync always + update \main_interface1_bus_cti $0\main_interface1_bus_cti[2:0] + sync init + end + attribute \src "ls180.v:1572.11-1572.41" + process $proc$ls180.v:1572$3417 + assign { } { } + assign $0\main_interface1_bus_bte[1:0] 2'00 + sync always + update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] + sync init + end + attribute \src "ls180.v:1579.5-1579.43" + process $proc$ls180.v:1579$3418 + assign { } { } + assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0] + end + attribute \src "ls180.v:1580.5-1580.43" + process $proc$ls180.v:1580$3419 + assign { } { } + assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0] + end + attribute \src "ls180.v:1581.5-1581.42" + process $proc$ls180.v:1581$3420 + assign { } { } + assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0] + end + attribute \src "ls180.v:1582.12-1582.61" + process $proc$ls180.v:1582$3421 + assign { } { } + assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0] + end + attribute \src "ls180.v:1583.5-1583.45" + process $proc$ls180.v:1583$3422 + assign { } { } + assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0] + end + attribute \src "ls180.v:1585.5-1585.45" + process $proc$ls180.v:1585$3423 + assign { } { } + assign $0\main_sdmem2block_dma_source_first[0:0] 1'0 + sync always + update \main_sdmem2block_dma_source_first $0\main_sdmem2block_dma_source_first[0:0] + sync init + end + attribute \src "ls180.v:1586.5-1586.44" + process $proc$ls180.v:1586$3424 + assign { } { } + assign $1\main_sdmem2block_dma_source_last[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0] + end + attribute \src "ls180.v:1587.12-1587.60" + process $proc$ls180.v:1587$3425 + assign { } { } + assign $1\main_sdmem2block_dma_source_payload_data[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[31:0] + end + attribute \src "ls180.v:1588.12-1588.45" + process $proc$ls180.v:1588$3426 + assign { } { } + assign $1\main_sdmem2block_dma_data[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[31:0] + end + attribute \src "ls180.v:1589.12-1589.53" + process $proc$ls180.v:1589$3427 + assign { } { } + assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0] + end + attribute \src "ls180.v:159.12-159.53" + process $proc$ls180.v:159$2801 + assign { } { } + assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0] + end + attribute \src "ls180.v:1590.5-1590.40" + process $proc$ls180.v:1590$3428 + assign { } { } + assign $1\main_sdmem2block_dma_base_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0] + end + attribute \src "ls180.v:1591.12-1591.55" + process $proc$ls180.v:1591$3429 + assign { } { } + assign $1\main_sdmem2block_dma_length_storage[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0] + end + attribute \src "ls180.v:1592.5-1592.42" + process $proc$ls180.v:1592$3430 + assign { } { } + assign $1\main_sdmem2block_dma_length_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0] + end + attribute \src "ls180.v:1593.5-1593.47" + process $proc$ls180.v:1593$3431 + assign { } { } + assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0] + end + attribute \src "ls180.v:1594.5-1594.42" + process $proc$ls180.v:1594$3432 + assign { } { } + assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0] + end + attribute \src "ls180.v:1595.5-1595.44" + process $proc$ls180.v:1595$3433 + assign { } { } + assign $1\main_sdmem2block_dma_done_status[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0] + end + attribute \src "ls180.v:1597.5-1597.45" + process $proc$ls180.v:1597$3434 + assign { } { } + assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0] + end + attribute \src "ls180.v:1598.5-1598.40" + process $proc$ls180.v:1598$3435 + assign { } { } + assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0] + end + attribute \src "ls180.v:160.12-160.71" + process $proc$ls180.v:160$2802 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_adr $1\main_libresocsim_interface2_converted_interface_adr[29:0] + end + attribute \src "ls180.v:1602.12-1602.47" + process $proc$ls180.v:1602$3436 + assign { } { } + assign $1\main_sdmem2block_dma_offset[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0] + end + attribute \src "ls180.v:161.12-161.73" + process $proc$ls180.v:161$2803 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_dat_w $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:1614.11-1614.64" + process $proc$ls180.v:1614$3437 + assign { } { } + assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1616.11-1616.48" + process $proc$ls180.v:1616$3438 + assign { } { } + assign $1\main_sdmem2block_converter_mux[1:0] 2'00 + sync always + sync init + update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[1:0] + end + attribute \src "ls180.v:163.11-163.69" + process $proc$ls180.v:163$2804 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_sel $1\main_libresocsim_interface2_converted_interface_sel[3:0] + end + attribute \src "ls180.v:164.5-164.63" + process $proc$ls180.v:164$2805 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_cyc $1\main_libresocsim_interface2_converted_interface_cyc[0:0] + end + attribute \src "ls180.v:1640.11-1640.45" + process $proc$ls180.v:1640$3439 + assign { } { } + assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 + sync always + sync init + update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] + end + attribute \src "ls180.v:1641.5-1641.41" + process $proc$ls180.v:1641$3440 + assign { } { } + assign $0\main_sdmem2block_fifo_replace[0:0] 1'0 + sync always + update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:1642.11-1642.47" + process $proc$ls180.v:1642$3441 + assign { } { } + assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000 + sync always + sync init + update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0] + end + attribute \src "ls180.v:1643.11-1643.47" + process $proc$ls180.v:1643$3442 + assign { } { } + assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000 + sync always + sync init + update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0] + end + attribute \src "ls180.v:1644.11-1644.50" + process $proc$ls180.v:1644$3443 + assign { } { } + assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 + sync always + sync init + update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:165.5-165.63" + process $proc$ls180.v:165$2806 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_stb $1\main_libresocsim_interface2_converted_interface_stb[0:0] + end + attribute \src "ls180.v:1659.5-1659.29" + process $proc$ls180.v:1659$3444 + assign { } { } + assign $1\libresocsim_done0[0:0] 1'0 + sync always + sync init + update \libresocsim_done0 $1\libresocsim_done0[0:0] + end + attribute \src "ls180.v:1660.5-1660.27" + process $proc$ls180.v:1660$3445 + assign { } { } + assign $1\libresocsim_irq[0:0] 1'0 + sync always + sync init + update \libresocsim_irq $1\libresocsim_irq[0:0] + end + attribute \src "ls180.v:1662.11-1662.34" + process $proc$ls180.v:1662$3446 + assign { } { } + assign $1\libresocsim_miso[7:0] 8'00000000 + sync always + sync init + update \libresocsim_miso $1\libresocsim_miso[7:0] + end + attribute \src "ls180.v:1666.5-1666.30" + process $proc$ls180.v:1666$3447 + assign { } { } + assign $1\libresocsim_start1[0:0] 1'0 + sync always + sync init + update \libresocsim_start1 $1\libresocsim_start1[0:0] + end + attribute \src "ls180.v:1668.12-1668.47" + process $proc$ls180.v:1668$3448 + assign { } { } + assign $1\libresocsim_control_storage[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_control_storage $1\libresocsim_control_storage[15:0] + end + attribute \src "ls180.v:1669.5-1669.34" + process $proc$ls180.v:1669$3449 + assign { } { } + assign $1\libresocsim_control_re[0:0] 1'0 + sync always + sync init + update \libresocsim_control_re $1\libresocsim_control_re[0:0] + end + attribute \src "ls180.v:167.5-167.62" + process $proc$ls180.v:167$2807 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_we $1\main_libresocsim_interface2_converted_interface_we[0:0] + end + attribute \src "ls180.v:1673.11-1673.42" + process $proc$ls180.v:1673$3450 + assign { } { } + assign $1\libresocsim_mosi_storage[7:0] 8'00000000 + sync always + sync init + update \libresocsim_mosi_storage $1\libresocsim_mosi_storage[7:0] + end + attribute \src "ls180.v:1674.5-1674.31" + process $proc$ls180.v:1674$3451 + assign { } { } + assign $1\libresocsim_mosi_re[0:0] 1'0 + sync always + sync init + update \libresocsim_mosi_re $1\libresocsim_mosi_re[0:0] + end + attribute \src "ls180.v:1678.5-1678.34" + process $proc$ls180.v:1678$3452 + assign { } { } + assign $1\libresocsim_cs_storage[0:0] 1'1 + sync always + sync init + update \libresocsim_cs_storage $1\libresocsim_cs_storage[0:0] + end + attribute \src "ls180.v:1679.5-1679.29" + process $proc$ls180.v:1679$3453 + assign { } { } + assign $1\libresocsim_cs_re[0:0] 1'0 + sync always + sync init + update \libresocsim_cs_re $1\libresocsim_cs_re[0:0] + end + attribute \src "ls180.v:168.11-168.69" + process $proc$ls180.v:168$2808 + assign { } { } + assign $0\main_libresocsim_interface2_converted_interface_cti[2:0] 3'000 + sync always + update \main_libresocsim_interface2_converted_interface_cti $0\main_libresocsim_interface2_converted_interface_cti[2:0] + sync init + end + attribute \src "ls180.v:1680.5-1680.40" + process $proc$ls180.v:1680$3454 + assign { } { } + assign $1\libresocsim_loopback_storage[0:0] 1'0 + sync always + sync init + update \libresocsim_loopback_storage $1\libresocsim_loopback_storage[0:0] + end + attribute \src "ls180.v:1681.5-1681.35" + process $proc$ls180.v:1681$3455 + assign { } { } + assign $1\libresocsim_loopback_re[0:0] 1'0 + sync always + sync init + update \libresocsim_loopback_re $1\libresocsim_loopback_re[0:0] + end + attribute \src "ls180.v:1682.5-1682.34" + process $proc$ls180.v:1682$3456 + assign { } { } + assign $1\libresocsim_clk_enable[0:0] 1'0 + sync always + sync init + update \libresocsim_clk_enable $1\libresocsim_clk_enable[0:0] + end + attribute \src "ls180.v:1683.5-1683.33" + process $proc$ls180.v:1683$3457 + assign { } { } + assign $1\libresocsim_cs_enable[0:0] 1'0 + sync always + sync init + update \libresocsim_cs_enable $1\libresocsim_cs_enable[0:0] + end + attribute \src "ls180.v:1684.11-1684.35" + process $proc$ls180.v:1684$3458 + assign { } { } + assign $1\libresocsim_count[2:0] 3'000 + sync always + sync init + update \libresocsim_count $1\libresocsim_count[2:0] + end + attribute \src "ls180.v:1685.5-1685.34" + process $proc$ls180.v:1685$3459 + assign { } { } + assign $1\libresocsim_mosi_latch[0:0] 1'0 + sync always + sync init + update \libresocsim_mosi_latch $1\libresocsim_mosi_latch[0:0] + end + attribute \src "ls180.v:1686.5-1686.34" + process $proc$ls180.v:1686$3460 + assign { } { } + assign $1\libresocsim_miso_latch[0:0] 1'0 + sync always + sync init + update \libresocsim_miso_latch $1\libresocsim_miso_latch[0:0] + end + attribute \src "ls180.v:1687.12-1687.44" + process $proc$ls180.v:1687$3461 + assign { } { } + assign $1\libresocsim_clk_divider1[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_clk_divider1 $1\libresocsim_clk_divider1[15:0] + end + attribute \src "ls180.v:169.11-169.69" + process $proc$ls180.v:169$2809 + assign { } { } + assign $0\main_libresocsim_interface2_converted_interface_bte[1:0] 2'00 + sync always + update \main_libresocsim_interface2_converted_interface_bte $0\main_libresocsim_interface2_converted_interface_bte[1:0] + sync init + end + attribute \src "ls180.v:1690.11-1690.39" + process $proc$ls180.v:1690$3462 + assign { } { } + assign $1\libresocsim_mosi_data[7:0] 8'00000000 + sync always + sync init + update \libresocsim_mosi_data $1\libresocsim_mosi_data[7:0] + end + attribute \src "ls180.v:1691.11-1691.38" + process $proc$ls180.v:1691$3463 + assign { } { } + assign $1\libresocsim_mosi_sel[2:0] 3'000 + sync always + sync init + update \libresocsim_mosi_sel $1\libresocsim_mosi_sel[2:0] + end + attribute \src "ls180.v:1692.11-1692.39" + process $proc$ls180.v:1692$3464 + assign { } { } + assign $1\libresocsim_miso_data[7:0] 8'00000000 + sync always + sync init + update \libresocsim_miso_data $1\libresocsim_miso_data[7:0] + end + attribute \src "ls180.v:1693.12-1693.41" + process $proc$ls180.v:1693$3465 + assign { } { } + assign $1\libresocsim_storage[15:0] 16'0000000001111101 + sync always + sync init + update \libresocsim_storage $1\libresocsim_storage[15:0] + end + attribute \src "ls180.v:1694.5-1694.26" + process $proc$ls180.v:1694$3466 + assign { } { } + assign $1\libresocsim_re[0:0] 1'0 + sync always + sync init + update \libresocsim_re $1\libresocsim_re[0:0] + end + attribute \src "ls180.v:1695.5-1695.36" + process $proc$ls180.v:1695$3467 + assign { } { } + assign $1\builder_converter0_state[0:0] 1'0 + sync always + sync init + update \builder_converter0_state $1\builder_converter0_state[0:0] + end + attribute \src "ls180.v:1696.5-1696.41" + process $proc$ls180.v:1696$3468 + assign { } { } + assign $1\builder_converter0_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter0_next_state $1\builder_converter0_next_state[0:0] + end + attribute \src "ls180.v:1697.5-1697.69" + process $proc$ls180.v:1697$3469 + assign { } { } + assign $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter0_counter_converter0_next_value $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] + end + attribute \src "ls180.v:1698.5-1698.72" + process $proc$ls180.v:1698$3470 + assign { } { } + assign $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter0_counter_converter0_next_value_ce $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + end + attribute \src "ls180.v:1699.5-1699.36" + process $proc$ls180.v:1699$3471 + assign { } { } + assign $1\builder_converter1_state[0:0] 1'0 + sync always + sync init + update \builder_converter1_state $1\builder_converter1_state[0:0] + end + attribute \src "ls180.v:1700.5-1700.41" + process $proc$ls180.v:1700$3472 + assign { } { } + assign $1\builder_converter1_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter1_next_state $1\builder_converter1_next_state[0:0] + end + attribute \src "ls180.v:1701.5-1701.69" + process $proc$ls180.v:1701$3473 + assign { } { } + assign $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_counter_converter1_next_value $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] + end + attribute \src "ls180.v:1702.5-1702.72" + process $proc$ls180.v:1702$3474 + assign { } { } + assign $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_counter_converter1_next_value_ce $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + end + attribute \src "ls180.v:1703.5-1703.36" + process $proc$ls180.v:1703$3475 + assign { } { } + assign $1\builder_converter2_state[0:0] 1'0 + sync always + sync init + update \builder_converter2_state $1\builder_converter2_state[0:0] + end + attribute \src "ls180.v:1704.5-1704.41" + process $proc$ls180.v:1704$3476 + assign { } { } + assign $1\builder_converter2_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter2_next_state $1\builder_converter2_next_state[0:0] + end + attribute \src "ls180.v:1705.5-1705.69" + process $proc$ls180.v:1705$3477 + assign { } { } + assign $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter2_counter_converter2_next_value $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] + end + attribute \src "ls180.v:1706.5-1706.72" + process $proc$ls180.v:1706$3478 + assign { } { } + assign $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter2_counter_converter2_next_value_ce $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + end + attribute \src "ls180.v:1707.11-1707.41" + process $proc$ls180.v:1707$3479 + assign { } { } + assign $1\builder_refresher_state[1:0] 2'00 + sync always + sync init + update \builder_refresher_state $1\builder_refresher_state[1:0] + end + attribute \src "ls180.v:1708.11-1708.46" + process $proc$ls180.v:1708$3480 + assign { } { } + assign $1\builder_refresher_next_state[1:0] 2'00 + sync always + sync init + update \builder_refresher_next_state $1\builder_refresher_next_state[1:0] + end + attribute \src "ls180.v:1709.11-1709.44" + process $proc$ls180.v:1709$3481 + assign { } { } + assign $1\builder_bankmachine0_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0] + end + attribute \src "ls180.v:171.5-171.44" + process $proc$ls180.v:171$2810 + assign { } { } + assign $1\main_libresocsim_converter2_skip[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter2_skip $1\main_libresocsim_converter2_skip[0:0] + end + attribute \src "ls180.v:1710.11-1710.49" + process $proc$ls180.v:1710$3482 + assign { } { } + assign $1\builder_bankmachine0_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] + end + attribute \src "ls180.v:1711.11-1711.44" + process $proc$ls180.v:1711$3483 + assign { } { } + assign $1\builder_bankmachine1_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0] + end + attribute \src "ls180.v:1712.11-1712.49" + process $proc$ls180.v:1712$3484 + assign { } { } + assign $1\builder_bankmachine1_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0] + end + attribute \src "ls180.v:1713.11-1713.44" + process $proc$ls180.v:1713$3485 + assign { } { } + assign $1\builder_bankmachine2_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0] + end + attribute \src "ls180.v:1714.11-1714.49" + process $proc$ls180.v:1714$3486 + assign { } { } + assign $1\builder_bankmachine2_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0] + end + attribute \src "ls180.v:1715.11-1715.44" + process $proc$ls180.v:1715$3487 + assign { } { } + assign $1\builder_bankmachine3_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0] + end + attribute \src "ls180.v:1716.11-1716.49" + process $proc$ls180.v:1716$3488 + assign { } { } + assign $1\builder_bankmachine3_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0] + end + attribute \src "ls180.v:1717.11-1717.43" + process $proc$ls180.v:1717$3489 + assign { } { } + assign $1\builder_multiplexer_state[2:0] 3'000 + sync always + sync init + update \builder_multiplexer_state $1\builder_multiplexer_state[2:0] + end + attribute \src "ls180.v:1718.11-1718.48" + process $proc$ls180.v:1718$3490 + assign { } { } + assign $1\builder_multiplexer_next_state[2:0] 3'000 + sync always + sync init + update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0] + end + attribute \src "ls180.v:172.5-172.47" + process $proc$ls180.v:172$2811 + assign { } { } + assign $1\main_libresocsim_converter2_counter[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter2_counter $1\main_libresocsim_converter2_counter[0:0] + end + attribute \src "ls180.v:1731.5-1731.27" + process $proc$ls180.v:1731$3491 + assign { } { } + assign $0\builder_locked0[0:0] 1'0 + sync always + update \builder_locked0 $0\builder_locked0[0:0] + sync init + end + attribute \src "ls180.v:1732.5-1732.27" + process $proc$ls180.v:1732$3492 + assign { } { } + assign $0\builder_locked1[0:0] 1'0 + sync always + update \builder_locked1 $0\builder_locked1[0:0] + sync init + end + attribute \src "ls180.v:1733.5-1733.27" + process $proc$ls180.v:1733$3493 + assign { } { } + assign $0\builder_locked2[0:0] 1'0 + sync always + update \builder_locked2 $0\builder_locked2[0:0] + sync init + end + attribute \src "ls180.v:1734.5-1734.27" + process $proc$ls180.v:1734$3494 + assign { } { } + assign $0\builder_locked3[0:0] 1'0 + sync always + update \builder_locked3 $0\builder_locked3[0:0] + sync init + end + attribute \src "ls180.v:1735.5-1735.42" + process $proc$ls180.v:1735$3495 + assign { } { } + assign $1\builder_new_master_wdata_ready[0:0] 1'0 + sync always + sync init + update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0] + end + attribute \src "ls180.v:1736.5-1736.43" + process $proc$ls180.v:1736$3496 + assign { } { } + assign $1\builder_new_master_rdata_valid0[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0] + end + attribute \src "ls180.v:1737.5-1737.43" + process $proc$ls180.v:1737$3497 + assign { } { } + assign $1\builder_new_master_rdata_valid1[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0] + end + attribute \src "ls180.v:1738.5-1738.43" + process $proc$ls180.v:1738$3498 + assign { } { } + assign $1\builder_new_master_rdata_valid2[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0] + end + attribute \src "ls180.v:1739.5-1739.43" + process $proc$ls180.v:1739$3499 + assign { } { } + assign $1\builder_new_master_rdata_valid3[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0] + end + attribute \src "ls180.v:174.12-174.53" + process $proc$ls180.v:174$2812 + assign { } { } + assign $1\main_libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_converter2_dat_r $1\main_libresocsim_converter2_dat_r[63:0] + end + attribute \src "ls180.v:1740.5-1740.35" + process $proc$ls180.v:1740$3500 + assign { } { } + assign $1\builder_converter_state[0:0] 1'0 + sync always + sync init + update \builder_converter_state $1\builder_converter_state[0:0] + end + attribute \src "ls180.v:1741.5-1741.40" + process $proc$ls180.v:1741$3501 + assign { } { } + assign $1\builder_converter_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter_next_state $1\builder_converter_next_state[0:0] + end + attribute \src "ls180.v:1742.5-1742.55" + process $proc$ls180.v:1742$3502 + assign { } { } + assign $1\main_converter_counter_converter_next_value[0:0] 1'0 + sync always + sync init + update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] + end + attribute \src "ls180.v:1743.5-1743.58" + process $proc$ls180.v:1743$3503 + assign { } { } + assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0] + end + attribute \src "ls180.v:1744.11-1744.42" + process $proc$ls180.v:1744$3504 + assign { } { } + assign $1\builder_spimaster0_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster0_state $1\builder_spimaster0_state[1:0] + end + attribute \src "ls180.v:1745.11-1745.47" + process $proc$ls180.v:1745$3505 + assign { } { } + assign $1\builder_spimaster0_next_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0] + end + attribute \src "ls180.v:1746.11-1746.61" + process $proc$ls180.v:1746$3506 + assign { } { } + assign $1\main_spi_master_count_spimaster0_next_value[2:0] 3'000 + sync always + sync init + update \main_spi_master_count_spimaster0_next_value $1\main_spi_master_count_spimaster0_next_value[2:0] + end + attribute \src "ls180.v:1747.5-1747.58" + process $proc$ls180.v:1747$3507 + assign { } { } + assign $1\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_spi_master_count_spimaster0_next_value_ce $1\main_spi_master_count_spimaster0_next_value_ce[0:0] + end + attribute \src "ls180.v:1748.5-1748.41" + process $proc$ls180.v:1748$3508 + assign { } { } + assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0] + end + attribute \src "ls180.v:1749.5-1749.46" + process $proc$ls180.v:1749$3509 + assign { } { } + assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0] + end + attribute \src "ls180.v:1750.11-1750.66" + process $proc$ls180.v:1750$3510 + assign { } { } + assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + end + attribute \src "ls180.v:1751.5-1751.63" + process $proc$ls180.v:1751$3511 + assign { } { } + assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + end + attribute \src "ls180.v:1752.11-1752.47" + process $proc$ls180.v:1752$3512 + assign { } { } + assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00 + sync always + sync init + update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0] + end + attribute \src "ls180.v:1753.11-1753.52" + process $proc$ls180.v:1753$3513 + assign { } { } + assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0] + end + attribute \src "ls180.v:1754.11-1754.66" + process $proc$ls180.v:1754$3514 + assign { } { } + assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + end + attribute \src "ls180.v:1755.5-1755.63" + process $proc$ls180.v:1755$3515 + assign { } { } + assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + end + attribute \src "ls180.v:1756.11-1756.47" + process $proc$ls180.v:1756$3516 + assign { } { } + assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0] + end + attribute \src "ls180.v:1757.11-1757.52" + process $proc$ls180.v:1757$3517 + assign { } { } + assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0] + end + attribute \src "ls180.v:1758.11-1758.67" + process $proc$ls180.v:1758$3518 + assign { } { } + assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + end + attribute \src "ls180.v:1759.5-1759.64" + process $proc$ls180.v:1759$3519 + assign { } { } + assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + end + attribute \src "ls180.v:1760.12-1760.71" + process $proc$ls180.v:1760$3520 + assign { } { } + assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 + sync always + sync init + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + end + attribute \src "ls180.v:1761.5-1761.66" + process $proc$ls180.v:1761$3521 + assign { } { } + assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + end + attribute \src "ls180.v:1762.5-1762.66" + process $proc$ls180.v:1762$3522 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + end + attribute \src "ls180.v:1763.5-1763.69" + process $proc$ls180.v:1763$3523 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + end + attribute \src "ls180.v:1764.5-1764.41" + process $proc$ls180.v:1764$3524 + assign { } { } + assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0] + end + attribute \src "ls180.v:1765.5-1765.46" + process $proc$ls180.v:1765$3525 + assign { } { } + assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0] + end + attribute \src "ls180.v:1766.5-1766.66" + process $proc$ls180.v:1766$3526 + assign { } { } + assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + end + attribute \src "ls180.v:1767.5-1767.69" + process $proc$ls180.v:1767$3527 + assign { } { } + assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + end + attribute \src "ls180.v:1768.11-1768.41" + process $proc$ls180.v:1768$3528 + assign { } { } + assign $1\builder_sdphy_fsm_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0] + end + attribute \src "ls180.v:1769.11-1769.46" + process $proc$ls180.v:1769$3529 + assign { } { } + assign $1\builder_sdphy_fsm_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0] + end + attribute \src "ls180.v:1770.11-1770.61" + process $proc$ls180.v:1770$3530 + assign { } { } + assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + end + attribute \src "ls180.v:1771.5-1771.58" + process $proc$ls180.v:1771$3531 + assign { } { } + assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:1772.11-1772.48" + process $proc$ls180.v:1772$3532 + assign { } { } + assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0] + end + attribute \src "ls180.v:1773.11-1773.53" + process $proc$ls180.v:1773$3533 + assign { } { } + assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0] + end + attribute \src "ls180.v:1774.11-1774.70" + process $proc$ls180.v:1774$3534 + assign { } { } + assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + sync always + sync init + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + end + attribute \src "ls180.v:1775.5-1775.66" + process $proc$ls180.v:1775$3535 + assign { } { } + assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + end + attribute \src "ls180.v:1776.12-1776.73" + process $proc$ls180.v:1776$3536 + assign { } { } + assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 + sync always + sync init + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + end + attribute \src "ls180.v:1777.5-1777.68" + process $proc$ls180.v:1777$3537 + assign { } { } + assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + end + attribute \src "ls180.v:1778.5-1778.69" + process $proc$ls180.v:1778$3538 + assign { } { } + assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + end + attribute \src "ls180.v:1779.5-1779.72" + process $proc$ls180.v:1779$3539 + assign { } { } + assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + end + attribute \src "ls180.v:1780.5-1780.52" + process $proc$ls180.v:1780$3540 + assign { } { } + assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 + sync always + sync init + update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0] + end + attribute \src "ls180.v:1781.5-1781.57" + process $proc$ls180.v:1781$3541 + assign { } { } + assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0] + end + attribute \src "ls180.v:1782.12-1782.93" + process $proc$ls180.v:1782$3542 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + end + attribute \src "ls180.v:1783.5-1783.88" + process $proc$ls180.v:1783$3543 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + end + attribute \src "ls180.v:1784.12-1784.93" + process $proc$ls180.v:1784$3544 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + end + attribute \src "ls180.v:1785.5-1785.88" + process $proc$ls180.v:1785$3545 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + end + attribute \src "ls180.v:1786.12-1786.93" + process $proc$ls180.v:1786$3546 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + end + attribute \src "ls180.v:1787.5-1787.88" + process $proc$ls180.v:1787$3547 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + end + attribute \src "ls180.v:1788.12-1788.93" + process $proc$ls180.v:1788$3548 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + end + attribute \src "ls180.v:1789.5-1789.88" + process $proc$ls180.v:1789$3549 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + end + attribute \src "ls180.v:1790.11-1790.87" + process $proc$ls180.v:1790$3550 + assign { } { } + assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + sync always + sync init + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + end + attribute \src "ls180.v:1791.5-1791.84" + process $proc$ls180.v:1791$3551 + assign { } { } + assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + end + attribute \src "ls180.v:1792.11-1792.42" + process $proc$ls180.v:1792$3552 + assign { } { } + assign $1\builder_sdcore_fsm_state[2:0] 3'000 + sync always + sync init + update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0] + end + attribute \src "ls180.v:1793.11-1793.47" + process $proc$ls180.v:1793$3553 + assign { } { } + assign $1\builder_sdcore_fsm_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0] + end + attribute \src "ls180.v:1794.5-1794.55" + process $proc$ls180.v:1794$3554 + assign { } { } + assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + end + attribute \src "ls180.v:1795.5-1795.58" + process $proc$ls180.v:1795$3555 + assign { } { } + assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + end + attribute \src "ls180.v:1796.5-1796.56" + process $proc$ls180.v:1796$3556 + assign { } { } + assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + end + attribute \src "ls180.v:1797.5-1797.59" + process $proc$ls180.v:1797$3557 + assign { } { } + assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + end + attribute \src "ls180.v:1798.11-1798.62" + process $proc$ls180.v:1798$3558 + assign { } { } + assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + sync always + sync init + update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + end + attribute \src "ls180.v:1799.5-1799.59" + process $proc$ls180.v:1799$3559 + assign { } { } + assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + end + attribute \src "ls180.v:1800.12-1800.65" + process $proc$ls180.v:1800$3560 + assign { } { } + assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + sync always + sync init + update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + end + attribute \src "ls180.v:1801.5-1801.60" + process $proc$ls180.v:1801$3561 + assign { } { } + assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + end + attribute \src "ls180.v:1802.5-1802.56" + process $proc$ls180.v:1802$3562 + assign { } { } + assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + end + attribute \src "ls180.v:1803.5-1803.59" + process $proc$ls180.v:1803$3563 + assign { } { } + assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + end + attribute \src "ls180.v:1804.5-1804.58" + process $proc$ls180.v:1804$3564 + assign { } { } + assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + end + attribute \src "ls180.v:1805.5-1805.61" + process $proc$ls180.v:1805$3565 + assign { } { } + assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + end + attribute \src "ls180.v:1806.5-1806.57" + process $proc$ls180.v:1806$3566 + assign { } { } + assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + end + attribute \src "ls180.v:1807.5-1807.60" + process $proc$ls180.v:1807$3567 + assign { } { } + assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + end + attribute \src "ls180.v:1808.5-1808.59" + process $proc$ls180.v:1808$3568 + assign { } { } + assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + end + attribute \src "ls180.v:1809.5-1809.62" + process $proc$ls180.v:1809$3569 + assign { } { } + assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + end + attribute \src "ls180.v:181.5-181.40" + process $proc$ls180.v:181$2813 + assign { } { } + assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] + end + attribute \src "ls180.v:1810.13-1810.76" + process $proc$ls180.v:1810$3570 + assign { } { } + assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + end + attribute \src "ls180.v:1811.5-1811.69" + process $proc$ls180.v:1811$3571 + assign { } { } + assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + end + attribute \src "ls180.v:1812.11-1812.46" + process $proc$ls180.v:1812$3572 + assign { } { } + assign $1\builder_sdblock2memdma_state[1:0] 2'00 + sync always + sync init + update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0] + end + attribute \src "ls180.v:1813.11-1813.51" + process $proc$ls180.v:1813$3573 + assign { } { } + assign $1\builder_sdblock2memdma_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0] + end + attribute \src "ls180.v:1814.12-1814.87" + process $proc$ls180.v:1814$3574 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + end + attribute \src "ls180.v:1815.5-1815.82" + process $proc$ls180.v:1815$3575 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + end + attribute \src "ls180.v:1816.5-1816.44" + process $proc$ls180.v:1816$3576 + assign { } { } + assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0 + sync always + sync init + update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0] + end + attribute \src "ls180.v:1817.5-1817.49" + process $proc$ls180.v:1817$3577 + assign { } { } + assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0] + end + attribute \src "ls180.v:1818.12-1818.75" + process $proc$ls180.v:1818$3578 + assign { } { } + assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + end + attribute \src "ls180.v:1819.5-1819.70" + process $proc$ls180.v:1819$3579 + assign { } { } + assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:1820.11-1820.60" + process $proc$ls180.v:1820$3580 + assign { } { } + assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + sync always + sync init + update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0] + end + attribute \src "ls180.v:1821.11-1821.65" + process $proc$ls180.v:1821$3581 + assign { } { } + assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] + end + attribute \src "ls180.v:1822.12-1822.87" + process $proc$ls180.v:1822$3582 + assign { } { } + assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + end + attribute \src "ls180.v:1823.5-1823.82" + process $proc$ls180.v:1823$3583 + assign { } { } + assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + end + attribute \src "ls180.v:1824.11-1824.42" + process $proc$ls180.v:1824$3584 + assign { } { } + assign $1\builder_spimaster1_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] + end + attribute \src "ls180.v:1825.11-1825.47" + process $proc$ls180.v:1825$3585 + assign { } { } + assign $1\builder_spimaster1_next_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] + end + attribute \src "ls180.v:1826.11-1826.57" + process $proc$ls180.v:1826$3586 + assign { } { } + assign $1\libresocsim_count_spimaster1_next_value[2:0] 3'000 + sync always + sync init + update \libresocsim_count_spimaster1_next_value $1\libresocsim_count_spimaster1_next_value[2:0] + end + attribute \src "ls180.v:1827.5-1827.54" + process $proc$ls180.v:1827$3587 + assign { } { } + assign $1\libresocsim_count_spimaster1_next_value_ce[0:0] 1'0 + sync always + sync init + update \libresocsim_count_spimaster1_next_value_ce $1\libresocsim_count_spimaster1_next_value_ce[0:0] + end + attribute \src "ls180.v:1828.12-1828.43" + process $proc$ls180.v:1828$3588 + assign { } { } + assign $1\builder_libresocsim_adr[13:0] 14'00000000000000 + sync always + sync init + update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0] + end + attribute \src "ls180.v:1829.5-1829.34" + process $proc$ls180.v:1829$3589 + assign { } { } + assign $1\builder_libresocsim_we[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we $1\builder_libresocsim_we[0:0] + end + attribute \src "ls180.v:1830.11-1830.43" + process $proc$ls180.v:1830$3590 + assign { } { } + assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 + sync always + sync init + update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] + end + attribute \src "ls180.v:1834.12-1834.54" + process $proc$ls180.v:1834$3591 + assign { } { } + assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 + sync always + sync init + update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] + end + attribute \src "ls180.v:1838.5-1838.44" + process $proc$ls180.v:1838$3592 + assign { } { } + assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] + end + attribute \src "ls180.v:1842.5-1842.44" + process $proc$ls180.v:1842$3593 + assign { } { } + assign $0\builder_libresocsim_wishbone_err[0:0] 1'0 + sync always + update \builder_libresocsim_wishbone_err $0\builder_libresocsim_wishbone_err[0:0] + sync init + end + attribute \src "ls180.v:1845.12-1845.40" + process $proc$ls180.v:1845$3594 + assign { } { } + assign $1\builder_shared_dat_r[31:0] 0 + sync always + sync init + update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] + end + attribute \src "ls180.v:1849.5-1849.30" + process $proc$ls180.v:1849$3595 + assign { } { } + assign $1\builder_shared_ack[0:0] 1'0 + sync always + sync init + update \builder_shared_ack $1\builder_shared_ack[0:0] + end + attribute \src "ls180.v:185.5-185.40" + process $proc$ls180.v:185$2814 + assign { } { } + assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 + sync always + update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] + sync init + end + attribute \src "ls180.v:1855.11-1855.31" + process $proc$ls180.v:1855$3596 + assign { } { } + assign $1\builder_grant[2:0] 3'000 + sync always + sync init + update \builder_grant $1\builder_grant[2:0] + end + attribute \src "ls180.v:1856.11-1856.35" + process $proc$ls180.v:1856$3597 + assign { } { } + assign $1\builder_slave_sel[4:0] 5'00000 + sync always + sync init + update \builder_slave_sel $1\builder_slave_sel[4:0] + end + attribute \src "ls180.v:1857.11-1857.37" + process $proc$ls180.v:1857$3598 + assign { } { } + assign $1\builder_slave_sel_r[4:0] 5'00000 + sync always + sync init + update \builder_slave_sel_r $1\builder_slave_sel_r[4:0] + end + attribute \src "ls180.v:1858.5-1858.25" + process $proc$ls180.v:1858$3599 + assign { } { } + assign $1\builder_error[0:0] 1'0 + sync always + sync init + update \builder_error $1\builder_error[0:0] + end + attribute \src "ls180.v:1861.12-1861.39" + process $proc$ls180.v:1861$3600 + assign { } { } + assign $1\builder_count[19:0] 20'11110100001001000000 + sync always + sync init + update \builder_count $1\builder_count[19:0] + end + attribute \src "ls180.v:1865.11-1865.51" + process $proc$ls180.v:1865$3601 + assign { } { } + assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:188.11-188.37" + process $proc$ls180.v:188$2815 + assign { } { } + assign $1\main_libresocsim_we[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_we $1\main_libresocsim_we[3:0] + end + attribute \src "ls180.v:190.12-190.49" + process $proc$ls180.v:190$2816 + assign { } { } + assign $1\main_libresocsim_load_storage[31:0] 0 + sync always + sync init + update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] + end + attribute \src "ls180.v:1906.11-1906.51" + process $proc$ls180.v:1906$3602 + assign { } { } + assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:191.5-191.36" + process $proc$ls180.v:191$2817 + assign { } { } + assign $1\main_libresocsim_load_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] + end + attribute \src "ls180.v:192.12-192.51" + process $proc$ls180.v:192$2818 + assign { } { } + assign $1\main_libresocsim_reload_storage[31:0] 0 + sync always + sync init + update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] + end + attribute \src "ls180.v:193.5-193.38" + process $proc$ls180.v:193$2819 + assign { } { } + assign $1\main_libresocsim_reload_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] + end + attribute \src "ls180.v:1935.11-1935.51" + process $proc$ls180.v:1935$3603 + assign { } { } + assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:194.5-194.39" + process $proc$ls180.v:194$2820 + assign { } { } + assign $1\main_libresocsim_en_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] + end + attribute \src "ls180.v:195.5-195.34" + process $proc$ls180.v:195$2821 + assign { } { } + assign $1\main_libresocsim_en_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] + end + attribute \src "ls180.v:196.5-196.49" + process $proc$ls180.v:196$2822 + assign { } { } + assign $1\main_libresocsim_update_value_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] + end + attribute \src "ls180.v:197.5-197.44" + process $proc$ls180.v:197$2823 + assign { } { } + assign $1\main_libresocsim_update_value_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] + end + attribute \src "ls180.v:1976.11-1976.51" + process $proc$ls180.v:1976$3604 + assign { } { } + assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:198.12-198.49" + process $proc$ls180.v:198$2824 + assign { } { } + assign $1\main_libresocsim_value_status[31:0] 0 + sync always + sync init + update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] + end + attribute \src "ls180.v:2017.11-2017.51" + process $proc$ls180.v:2017$3605 + assign { } { } + assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:202.5-202.41" + process $proc$ls180.v:202$2825 + assign { } { } + assign $1\main_libresocsim_zero_pending[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] + end + attribute \src "ls180.v:204.5-204.39" + process $proc$ls180.v:204$2826 + assign { } { } + assign $1\main_libresocsim_zero_clear[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] + end + attribute \src "ls180.v:205.5-205.45" + process $proc$ls180.v:205$2827 + assign { } { } + assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] + end + attribute \src "ls180.v:2082.11-2082.51" + process $proc$ls180.v:2082$3606 + assign { } { } + assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:214.5-214.49" + process $proc$ls180.v:214$2828 + assign { } { } + assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] + end + attribute \src "ls180.v:215.5-215.44" + process $proc$ls180.v:215$2829 + assign { } { } + assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] + end + attribute \src "ls180.v:216.12-216.42" + process $proc$ls180.v:216$2830 + assign { } { } + assign $1\main_libresocsim_value[31:0] 0 + sync always + sync init + update \main_libresocsim_value $1\main_libresocsim_value[31:0] + end + attribute \src "ls180.v:220.5-220.24" + process $proc$ls180.v:220$2831 + assign { } { } + assign $1\main_int_rst[0:0] 1'1 + sync always + sync init + update \main_int_rst $1\main_int_rst[0:0] + end + attribute \src "ls180.v:2215.11-2215.51" + process $proc$ls180.v:2215$3607 + assign { } { } + assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2296.11-2296.51" + process $proc$ls180.v:2296$3608 + assign { } { } + assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2313.11-2313.51" + process $proc$ls180.v:2313$3609 + assign { } { } + assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:235.12-235.38" + process $proc$ls180.v:235$2832 + assign { } { } + assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] + end + attribute \src "ls180.v:2354.11-2354.51" + process $proc$ls180.v:2354$3610 + assign { } { } + assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:236.5-236.36" + process $proc$ls180.v:236$2833 + assign { } { } + assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:237.11-237.25" + process $proc$ls180.v:237$2834 + assign { } { } + assign $1\main_dm[1:0] 2'00 + sync always + sync init + update \main_dm $1\main_dm[1:0] + end + attribute \src "ls180.v:238.11-238.32" + process $proc$ls180.v:238$2835 + assign { } { } + assign $1\main_rddata_en[2:0] 3'000 + sync always + sync init + update \main_rddata_en $1\main_rddata_en[2:0] + end + attribute \src "ls180.v:2387.11-2387.52" + process $proc$ls180.v:2387$3611 + assign { } { } + assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:241.5-241.36" + process $proc$ls180.v:241$2836 + assign { } { } + assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] + end + attribute \src "ls180.v:242.5-242.35" + process $proc$ls180.v:242$2837 + assign { } { } + assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] + end + attribute \src "ls180.v:2428.11-2428.52" + process $proc$ls180.v:2428$3612 + assign { } { } + assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:243.5-243.36" + process $proc$ls180.v:243$2838 + assign { } { } + assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] + end + attribute \src "ls180.v:244.5-244.35" + process $proc$ls180.v:244$2839 + assign { } { } + assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] + end + attribute \src "ls180.v:248.5-248.36" + process $proc$ls180.v:248$2840 + assign { } { } + assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 + sync always + update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] + sync init + end + attribute \src "ls180.v:2493.11-2493.52" + process $proc$ls180.v:2493$3613 + assign { } { } + assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2518.11-2518.52" + process $proc$ls180.v:2518$3614 + assign { } { } + assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:253.12-253.45" + process $proc$ls180.v:253$2841 + assign { } { } + assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] + end + attribute \src "ls180.v:254.5-254.43" + process $proc$ls180.v:254$2842 + assign { } { } + assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:2540.11-2540.31" + process $proc$ls180.v:2540$3615 + assign { } { } + assign $1\builder_state[1:0] 2'00 + sync always + sync init + update \builder_state $1\builder_state[1:0] + end + attribute \src "ls180.v:2541.11-2541.36" + process $proc$ls180.v:2541$3616 + assign { } { } + assign $1\builder_next_state[1:0] 2'00 + sync always + sync init + update \builder_next_state $1\builder_next_state[1:0] + end + attribute \src "ls180.v:2542.11-2542.55" + process $proc$ls180.v:2542$3617 + assign { } { } + assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 + sync always + sync init + update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0] + end + attribute \src "ls180.v:2543.5-2543.52" + process $proc$ls180.v:2543$3618 + assign { } { } + assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0] + end + attribute \src "ls180.v:2544.12-2544.55" + process $proc$ls180.v:2544$3619 + assign { } { } + assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + sync always + sync init + update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0] + end + attribute \src "ls180.v:2545.5-2545.50" + process $proc$ls180.v:2545$3620 + assign { } { } + assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0] + end + attribute \src "ls180.v:2546.5-2546.46" + process $proc$ls180.v:2546$3621 + assign { } { } + assign $1\builder_libresocsim_we_next_value2[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0] + end + attribute \src "ls180.v:2547.5-2547.49" + process $proc$ls180.v:2547$3622 + assign { } { } + assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0] + end + attribute \src "ls180.v:2548.5-2548.41" + process $proc$ls180.v:2548$3623 + assign { } { } + assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0] + end + attribute \src "ls180.v:2549.12-2549.49" + process $proc$ls180.v:2549$3624 + assign { } { } + assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:2550.11-2550.47" + process $proc$ls180.v:2550$3625 + assign { } { } + assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0] + end + attribute \src "ls180.v:2551.5-2551.41" + process $proc$ls180.v:2551$3626 + assign { } { } + assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:2552.5-2552.41" + process $proc$ls180.v:2552$3627 + assign { } { } + assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:2553.5-2553.41" + process $proc$ls180.v:2553$3628 + assign { } { } + assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:2554.5-2554.39" + process $proc$ls180.v:2554$3629 + assign { } { } + assign $1\builder_comb_t_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0] + end + attribute \src "ls180.v:2555.5-2555.39" + process $proc$ls180.v:2555$3630 + assign { } { } + assign $1\builder_comb_t_array_muxed1[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0] + end + attribute \src "ls180.v:2556.5-2556.39" + process $proc$ls180.v:2556$3631 + assign { } { } + assign $1\builder_comb_t_array_muxed2[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0] + end + attribute \src "ls180.v:2557.5-2557.41" + process $proc$ls180.v:2557$3632 + assign { } { } + assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:2558.12-2558.49" + process $proc$ls180.v:2558$3633 + assign { } { } + assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0] + end + attribute \src "ls180.v:2559.11-2559.47" + process $proc$ls180.v:2559$3634 + assign { } { } + assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0] + end + attribute \src "ls180.v:2560.5-2560.41" + process $proc$ls180.v:2560$3635 + assign { } { } + assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0] + end + attribute \src "ls180.v:2561.5-2561.42" + process $proc$ls180.v:2561$3636 + assign { } { } + assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0] + end + attribute \src "ls180.v:2562.5-2562.42" + process $proc$ls180.v:2562$3637 + assign { } { } + assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0] + end + attribute \src "ls180.v:2563.5-2563.39" + process $proc$ls180.v:2563$3638 + assign { } { } + assign $1\builder_comb_t_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0] + end + attribute \src "ls180.v:2564.5-2564.39" + process $proc$ls180.v:2564$3639 + assign { } { } + assign $1\builder_comb_t_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0] + end + attribute \src "ls180.v:2565.5-2565.39" + process $proc$ls180.v:2565$3640 + assign { } { } + assign $1\builder_comb_t_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0] + end + attribute \src "ls180.v:2566.12-2566.50" + process $proc$ls180.v:2566$3641 + assign { } { } + assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0] + end + attribute \src "ls180.v:2567.5-2567.42" + process $proc$ls180.v:2567$3642 + assign { } { } + assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0] + end + attribute \src "ls180.v:2568.5-2568.42" + process $proc$ls180.v:2568$3643 + assign { } { } + assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0] + end + attribute \src "ls180.v:2569.12-2569.50" + process $proc$ls180.v:2569$3644 + assign { } { } + assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0] + end + attribute \src "ls180.v:2570.5-2570.42" + process $proc$ls180.v:2570$3645 + assign { } { } + assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0] + end + attribute \src "ls180.v:2571.5-2571.42" + process $proc$ls180.v:2571$3646 + assign { } { } + assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0] + end + attribute \src "ls180.v:2572.12-2572.50" + process $proc$ls180.v:2572$3647 + assign { } { } + assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0] + end + attribute \src "ls180.v:2573.5-2573.42" + process $proc$ls180.v:2573$3648 + assign { } { } + assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0] + end + attribute \src "ls180.v:2574.5-2574.42" + process $proc$ls180.v:2574$3649 + assign { } { } + assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0] + end + attribute \src "ls180.v:2575.12-2575.50" + process $proc$ls180.v:2575$3650 + assign { } { } + assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0] + end + attribute \src "ls180.v:2576.5-2576.42" + process $proc$ls180.v:2576$3651 + assign { } { } + assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0] + end + attribute \src "ls180.v:2577.5-2577.42" + process $proc$ls180.v:2577$3652 + assign { } { } + assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0] + end + attribute \src "ls180.v:2578.12-2578.50" + process $proc$ls180.v:2578$3653 + assign { } { } + assign $1\builder_comb_rhs_array_muxed24[31:0] 0 + sync always + sync init + update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0] + end + attribute \src "ls180.v:2579.12-2579.50" + process $proc$ls180.v:2579$3654 + assign { } { } + assign $1\builder_comb_rhs_array_muxed25[31:0] 0 + sync always + sync init + update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[31:0] + end + attribute \src "ls180.v:2580.11-2580.48" + process $proc$ls180.v:2580$3655 + assign { } { } + assign $1\builder_comb_rhs_array_muxed26[3:0] 4'0000 + sync always + sync init + update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[3:0] + end + attribute \src "ls180.v:2581.5-2581.42" + process $proc$ls180.v:2581$3656 + assign { } { } + assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] + end + attribute \src "ls180.v:2582.5-2582.42" + process $proc$ls180.v:2582$3657 + assign { } { } + assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0] + end + attribute \src "ls180.v:2583.5-2583.42" + process $proc$ls180.v:2583$3658 + assign { } { } + assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0] + end + attribute \src "ls180.v:2584.11-2584.48" + process $proc$ls180.v:2584$3659 + assign { } { } + assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000 + sync always + sync init + update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0] + end + attribute \src "ls180.v:2585.11-2585.48" + process $proc$ls180.v:2585$3660 + assign { } { } + assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0] + end + attribute \src "ls180.v:2586.11-2586.47" + process $proc$ls180.v:2586$3661 + assign { } { } + assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00 + sync always + sync init + update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0] + end + attribute \src "ls180.v:2587.12-2587.49" + process $proc$ls180.v:2587$3662 + assign { } { } + assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 + sync always + sync init + update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:2588.5-2588.41" + process $proc$ls180.v:2588$3663 + assign { } { } + assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0] + end + attribute \src "ls180.v:2589.5-2589.41" + process $proc$ls180.v:2589$3664 + assign { } { } + assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:2590.5-2590.41" + process $proc$ls180.v:2590$3665 + assign { } { } + assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:2591.5-2591.41" + process $proc$ls180.v:2591$3666 + assign { } { } + assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:2592.5-2592.41" + process $proc$ls180.v:2592$3667 + assign { } { } + assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:2593.5-2593.39" + process $proc$ls180.v:2593$3668 + assign { } { } + assign $1\builder_sync_f_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0] + end + attribute \src "ls180.v:2594.5-2594.39" + process $proc$ls180.v:2594$3669 + assign { } { } + assign $1\builder_sync_f_array_muxed1[0:0] 1'0 + sync always + sync init + update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0] + end + attribute \src "ls180.v:2649.32-2649.66" + process $proc$ls180.v:2649$3670 + assign { } { } + assign $1\builder_multiregimpl0_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0] + end + attribute \src "ls180.v:2650.32-2650.66" + process $proc$ls180.v:2650$3671 + assign { } { } + assign $1\builder_multiregimpl0_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0] + end + attribute \src "ls180.v:2651.32-2651.66" + process $proc$ls180.v:2651$3672 + assign { } { } + assign $1\builder_multiregimpl1_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0] + end + attribute \src "ls180.v:2652.32-2652.66" + process $proc$ls180.v:2652$3673 + assign { } { } + assign $1\builder_multiregimpl1_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0] + end + attribute \src "ls180.v:2653.32-2653.66" + process $proc$ls180.v:2653$3674 + assign { } { } + assign $1\builder_multiregimpl2_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0] + end + attribute \src "ls180.v:2654.32-2654.66" + process $proc$ls180.v:2654$3675 + assign { } { } + assign $1\builder_multiregimpl2_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0] + end + attribute \src "ls180.v:2655.32-2655.66" + process $proc$ls180.v:2655$3676 + assign { } { } + assign $1\builder_multiregimpl3_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0] + end + attribute \src "ls180.v:2656.32-2656.66" + process $proc$ls180.v:2656$3677 + assign { } { } + assign $1\builder_multiregimpl3_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0] + end + attribute \src "ls180.v:2657.32-2657.66" + process $proc$ls180.v:2657$3678 + assign { } { } + assign $1\builder_multiregimpl4_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0] + end + attribute \src "ls180.v:2658.32-2658.66" + process $proc$ls180.v:2658$3679 + assign { } { } + assign $1\builder_multiregimpl4_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0] + end + attribute \src "ls180.v:2659.32-2659.66" + process $proc$ls180.v:2659$3680 + assign { } { } + assign $1\builder_multiregimpl5_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0] + end + attribute \src "ls180.v:2660.32-2660.66" + process $proc$ls180.v:2660$3681 + assign { } { } + assign $1\builder_multiregimpl5_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0] + end + attribute \src "ls180.v:2661.32-2661.66" + process $proc$ls180.v:2661$3682 + assign { } { } + assign $1\builder_multiregimpl6_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0] + end + attribute \src "ls180.v:2662.32-2662.66" + process $proc$ls180.v:2662$3683 + assign { } { } + assign $1\builder_multiregimpl6_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0] + end + attribute \src "ls180.v:2663.32-2663.66" + process $proc$ls180.v:2663$3684 + assign { } { } + assign $1\builder_multiregimpl7_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0] + end + attribute \src "ls180.v:2664.32-2664.66" + process $proc$ls180.v:2664$3685 + assign { } { } + assign $1\builder_multiregimpl7_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0] + end + attribute \src "ls180.v:2665.32-2665.66" + process $proc$ls180.v:2665$3686 + assign { } { } + assign $1\builder_multiregimpl8_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0] + end + attribute \src "ls180.v:2666.32-2666.66" + process $proc$ls180.v:2666$3687 + assign { } { } + assign $1\builder_multiregimpl8_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0] + end + attribute \src "ls180.v:2667.32-2667.66" + process $proc$ls180.v:2667$3688 + assign { } { } + assign $1\builder_multiregimpl9_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0] + end + attribute \src "ls180.v:2668.32-2668.66" + process $proc$ls180.v:2668$3689 + assign { } { } + assign $1\builder_multiregimpl9_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0] + end + attribute \src "ls180.v:2669.32-2669.67" + process $proc$ls180.v:2669$3690 + assign { } { } + assign $1\builder_multiregimpl10_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0] + end + attribute \src "ls180.v:2670.32-2670.67" + process $proc$ls180.v:2670$3691 + assign { } { } + assign $1\builder_multiregimpl10_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0] + end + attribute \src "ls180.v:2671.32-2671.67" + process $proc$ls180.v:2671$3692 + assign { } { } + assign $1\builder_multiregimpl11_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0] + end + attribute \src "ls180.v:2672.32-2672.67" + process $proc$ls180.v:2672$3693 + assign { } { } + assign $1\builder_multiregimpl11_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0] + end + attribute \src "ls180.v:2673.32-2673.67" + process $proc$ls180.v:2673$3694 + assign { } { } + assign $1\builder_multiregimpl12_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0] + end + attribute \src "ls180.v:2674.32-2674.67" + process $proc$ls180.v:2674$3695 + assign { } { } + assign $1\builder_multiregimpl12_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0] + end + attribute \src "ls180.v:2675.32-2675.67" + process $proc$ls180.v:2675$3696 + assign { } { } + assign $1\builder_multiregimpl13_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0] + end + attribute \src "ls180.v:2676.32-2676.67" + process $proc$ls180.v:2676$3697 + assign { } { } + assign $1\builder_multiregimpl13_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0] + end + attribute \src "ls180.v:2677.32-2677.67" + process $proc$ls180.v:2677$3698 + assign { } { } + assign $1\builder_multiregimpl14_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0] + end + attribute \src "ls180.v:2678.32-2678.67" + process $proc$ls180.v:2678$3699 + assign { } { } + assign $1\builder_multiregimpl14_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0] + end + attribute \src "ls180.v:2679.32-2679.67" + process $proc$ls180.v:2679$3700 + assign { } { } + assign $1\builder_multiregimpl15_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0] + end + attribute \src "ls180.v:2680.32-2680.67" + process $proc$ls180.v:2680$3701 + assign { } { } + assign $1\builder_multiregimpl15_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0] + end + attribute \src "ls180.v:2681.32-2681.67" + process $proc$ls180.v:2681$3702 + assign { } { } + assign $1\builder_multiregimpl16_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0] + end + attribute \src "ls180.v:2682.32-2682.67" + process $proc$ls180.v:2682$3703 + assign { } { } + assign $1\builder_multiregimpl16_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0] + end + attribute \src "ls180.v:269.12-269.46" + process $proc$ls180.v:269$2843 + assign { } { } + assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] + end + attribute \src "ls180.v:270.5-270.44" + process $proc$ls180.v:270$2844 + assign { } { } + assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:271.12-271.48" + process $proc$ls180.v:271$2845 + assign { } { } + assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] + end + attribute \src "ls180.v:2719.1-2724.4" + process $proc$ls180.v:2719$13 + assign { } { } + assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000 + assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint } + assign $0\main_libresocsim_libresoc_interrupt[15:0] [0] \main_libresocsim_irq + assign $0\main_libresocsim_libresoc_interrupt[15:0] [1] \main_uart_irq + sync always + update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0] + end + attribute \src "ls180.v:272.11-272.43" + process $proc$ls180.v:272$2846 + assign { } { } + assign $1\main_sdram_master_p0_bank[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] + end + attribute \src "ls180.v:2726.1-2736.4" + process $proc$ls180.v:2726$15 + assign { } { } + assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 + attribute \src "ls180.v:2728.2-2735.9" + switch \main_libresocsim_converter0_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [31:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [63:32] + case + end + sync always + update \main_libresocsim_interface0_converted_interface_dat_w $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:273.5-273.38" + process $proc$ls180.v:273$2847 + assign { } { } + assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] + end + attribute \src "ls180.v:2738.1-2784.4" + process $proc$ls180.v:2738$16 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 + assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 + assign { } { } + assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_converter0_skip[0:0] 1'0 + assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 + assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 + assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 + assign $0\builder_converter0_next_state[0:0] \builder_converter0_state + attribute \src "ls180.v:2750.2-2783.9" + switch \builder_converter0_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] { \main_libresocsim_libresoc_ibus_adr \main_libresocsim_converter0_counter } + attribute \src "ls180.v:2753.4-2760.11" + switch \main_libresocsim_converter0_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [3:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [7:4] + case + end + attribute \src "ls180.v:2761.4-2774.7" + switch $and$ls180.v:2761$17_Y + attribute \src "ls180.v:2761.8-2761.81" + case 1'1 + assign $0\main_libresocsim_converter0_skip[0:0] $eq$ls180.v:2762$18_Y + assign $0\main_libresocsim_interface0_converted_interface_we[0:0] \main_libresocsim_libresoc_ibus_we + assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:2764$19_Y + assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:2765$20_Y + attribute \src "ls180.v:2766.5-2773.8" + switch $or$ls180.v:2766$21_Y + attribute \src "ls180.v:2766.9-2766.97" + case 1'1 + assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2767$22_Y + assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2769.6-2772.9" + switch $eq$ls180.v:2769$23_Y + attribute \src "ls180.v:2769.10-2769.55" + case 1'1 + assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'1 + assign $0\builder_converter0_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2779.4-2781.7" + switch $and$ls180.v:2779$24_Y + attribute \src "ls180.v:2779.8-2779.81" + case 1'1 + assign $0\builder_converter0_next_state[0:0] 1'1 + case + end + end + sync always + update \main_libresocsim_libresoc_ibus_ack $0\main_libresocsim_libresoc_ibus_ack[0:0] + update \main_libresocsim_interface0_converted_interface_adr $0\main_libresocsim_interface0_converted_interface_adr[29:0] + update \main_libresocsim_interface0_converted_interface_sel $0\main_libresocsim_interface0_converted_interface_sel[3:0] + update \main_libresocsim_interface0_converted_interface_cyc $0\main_libresocsim_interface0_converted_interface_cyc[0:0] + update \main_libresocsim_interface0_converted_interface_stb $0\main_libresocsim_interface0_converted_interface_stb[0:0] + update \main_libresocsim_interface0_converted_interface_we $0\main_libresocsim_interface0_converted_interface_we[0:0] + update \main_libresocsim_converter0_skip $0\main_libresocsim_converter0_skip[0:0] + update \builder_converter0_next_state $0\builder_converter0_next_state[0:0] + update \main_libresocsim_converter0_counter_converter0_next_value $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] + update \main_libresocsim_converter0_counter_converter0_next_value_ce $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + end + attribute \src "ls180.v:274.5-274.37" + process $proc$ls180.v:274$2848 + assign { } { } + assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] + end + attribute \src "ls180.v:275.5-275.38" + process $proc$ls180.v:275$2849 + assign { } { } + assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] + end + attribute \src "ls180.v:276.5-276.37" + process $proc$ls180.v:276$2850 + assign { } { } + assign $1\main_sdram_master_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] + end + attribute \src "ls180.v:277.5-277.36" + process $proc$ls180.v:277$2851 + assign { } { } + assign $1\main_sdram_master_p0_cke[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] + end + attribute \src "ls180.v:278.5-278.36" + process $proc$ls180.v:278$2852 + assign { } { } + assign $1\main_sdram_master_p0_odt[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] + end + attribute \src "ls180.v:2786.1-2796.4" + process $proc$ls180.v:2786$26 + assign { } { } + assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 + attribute \src "ls180.v:2788.2-2795.9" + switch \main_libresocsim_converter1_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [31:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [63:32] + case + end + sync always + update \main_libresocsim_interface1_converted_interface_dat_w $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:279.5-279.40" + process $proc$ls180.v:279$2853 + assign { } { } + assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] + end + attribute \src "ls180.v:2798.1-2844.4" + process $proc$ls180.v:2798$27 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_libresocsim_converter1_skip[0:0] 1'0 + assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 + assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 + assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 + assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 + assign $0\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 + assign $0\builder_converter1_next_state[0:0] \builder_converter1_state + attribute \src "ls180.v:2810.2-2843.9" + switch \builder_converter1_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] { \main_libresocsim_libresoc_dbus_adr \main_libresocsim_converter1_counter } + attribute \src "ls180.v:2813.4-2820.11" + switch \main_libresocsim_converter1_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [3:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [7:4] + case + end + attribute \src "ls180.v:2821.4-2834.7" + switch $and$ls180.v:2821$28_Y + attribute \src "ls180.v:2821.8-2821.81" + case 1'1 + assign $0\main_libresocsim_converter1_skip[0:0] $eq$ls180.v:2822$29_Y + assign $0\main_libresocsim_interface1_converted_interface_we[0:0] \main_libresocsim_libresoc_dbus_we + assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:2824$30_Y + assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:2825$31_Y + attribute \src "ls180.v:2826.5-2833.8" + switch $or$ls180.v:2826$32_Y + attribute \src "ls180.v:2826.9-2826.97" + case 1'1 + assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2827$33_Y + assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2829.6-2832.9" + switch $eq$ls180.v:2829$34_Y + attribute \src "ls180.v:2829.10-2829.55" + case 1'1 + assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'1 + assign $0\builder_converter1_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2839.4-2841.7" + switch $and$ls180.v:2839$35_Y + attribute \src "ls180.v:2839.8-2839.81" + case 1'1 + assign $0\builder_converter1_next_state[0:0] 1'1 + case + end + end + sync always + update \main_libresocsim_libresoc_dbus_ack $0\main_libresocsim_libresoc_dbus_ack[0:0] + update \main_libresocsim_interface1_converted_interface_adr $0\main_libresocsim_interface1_converted_interface_adr[29:0] + update \main_libresocsim_interface1_converted_interface_sel $0\main_libresocsim_interface1_converted_interface_sel[3:0] + update \main_libresocsim_interface1_converted_interface_cyc $0\main_libresocsim_interface1_converted_interface_cyc[0:0] + update \main_libresocsim_interface1_converted_interface_stb $0\main_libresocsim_interface1_converted_interface_stb[0:0] + update \main_libresocsim_interface1_converted_interface_we $0\main_libresocsim_interface1_converted_interface_we[0:0] + update \main_libresocsim_converter1_skip $0\main_libresocsim_converter1_skip[0:0] + update \builder_converter1_next_state $0\builder_converter1_next_state[0:0] + update \main_libresocsim_converter1_counter_converter1_next_value $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] + update \main_libresocsim_converter1_counter_converter1_next_value_ce $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + end + attribute \src "ls180.v:280.5-280.38" + process $proc$ls180.v:280$2854 + assign { } { } + assign $1\main_sdram_master_p0_act_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] + end + attribute \src "ls180.v:281.12-281.47" + process $proc$ls180.v:281$2855 + assign { } { } + assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] + end + attribute \src "ls180.v:282.5-282.42" + process $proc$ls180.v:282$2856 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] + end + attribute \src "ls180.v:283.11-283.50" + process $proc$ls180.v:283$2857 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] + end + attribute \src "ls180.v:284.5-284.42" + process $proc$ls180.v:284$2858 + assign { } { } + assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] + end + attribute \src "ls180.v:2846.1-2856.4" + process $proc$ls180.v:2846$37 + assign { } { } + assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 + attribute \src "ls180.v:2848.2-2855.9" + switch \main_libresocsim_converter2_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_jtag_wb_dat_w [31:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_jtag_wb_dat_w [63:32] + case + end + sync always + update \main_libresocsim_interface2_converted_interface_dat_w $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:2858.1-2904.4" + process $proc$ls180.v:2858$38 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 + assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 + assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 + assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 + assign $0\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 + assign $0\main_libresocsim_converter2_skip[0:0] 1'0 + assign { } { } + assign $0\builder_converter2_next_state[0:0] \builder_converter2_state + attribute \src "ls180.v:2870.2-2903.9" + switch \builder_converter2_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] { \main_libresocsim_libresoc_jtag_wb_adr \main_libresocsim_converter2_counter } + attribute \src "ls180.v:2873.4-2880.11" + switch \main_libresocsim_converter2_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [3:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [7:4] + case + end + attribute \src "ls180.v:2881.4-2894.7" + switch $and$ls180.v:2881$39_Y + attribute \src "ls180.v:2881.8-2881.87" + case 1'1 + assign $0\main_libresocsim_converter2_skip[0:0] $eq$ls180.v:2882$40_Y + assign $0\main_libresocsim_interface2_converted_interface_we[0:0] \main_libresocsim_libresoc_jtag_wb_we + assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:2884$41_Y + assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:2885$42_Y + attribute \src "ls180.v:2886.5-2893.8" + switch $or$ls180.v:2886$43_Y + attribute \src "ls180.v:2886.9-2886.97" + case 1'1 + assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] $add$ls180.v:2887$44_Y + assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2889.6-2892.9" + switch $eq$ls180.v:2889$45_Y + attribute \src "ls180.v:2889.10-2889.55" + case 1'1 + assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'1 + assign $0\builder_converter2_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2899.4-2901.7" + switch $and$ls180.v:2899$46_Y + attribute \src "ls180.v:2899.8-2899.87" + case 1'1 + assign $0\builder_converter2_next_state[0:0] 1'1 + case + end + end + sync always + update \main_libresocsim_libresoc_jtag_wb_ack $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] + update \main_libresocsim_interface2_converted_interface_adr $0\main_libresocsim_interface2_converted_interface_adr[29:0] + update \main_libresocsim_interface2_converted_interface_sel $0\main_libresocsim_interface2_converted_interface_sel[3:0] + update \main_libresocsim_interface2_converted_interface_cyc $0\main_libresocsim_interface2_converted_interface_cyc[0:0] + update \main_libresocsim_interface2_converted_interface_stb $0\main_libresocsim_interface2_converted_interface_stb[0:0] + update \main_libresocsim_interface2_converted_interface_we $0\main_libresocsim_interface2_converted_interface_we[0:0] + update \main_libresocsim_converter2_skip $0\main_libresocsim_converter2_skip[0:0] + update \builder_converter2_next_state $0\builder_converter2_next_state[0:0] + update \main_libresocsim_converter2_counter_converter2_next_value $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] + update \main_libresocsim_converter2_counter_converter2_next_value_ce $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + end + attribute \src "ls180.v:2907.1-2913.4" + process $proc$ls180.v:2907$47 + assign { } { } + assign { } { } + assign $0\main_libresocsim_we[3:0] [0] $and$ls180.v:2909$50_Y + assign $0\main_libresocsim_we[3:0] [1] $and$ls180.v:2910$53_Y + assign $0\main_libresocsim_we[3:0] [2] $and$ls180.v:2911$56_Y + assign $0\main_libresocsim_we[3:0] [3] $and$ls180.v:2912$59_Y + sync always + update \main_libresocsim_we $0\main_libresocsim_we[3:0] + end + attribute \src "ls180.v:291.11-291.36" + process $proc$ls180.v:291$2859 + assign { } { } + assign $1\main_sdram_storage[3:0] 4'0001 + sync always + sync init + update \main_sdram_storage $1\main_sdram_storage[3:0] + end + attribute \src "ls180.v:2919.1-2924.4" + process $proc$ls180.v:2919$61 + assign { } { } + assign $0\main_libresocsim_zero_clear[0:0] 1'0 + attribute \src "ls180.v:2921.2-2923.5" + switch $and$ls180.v:2921$62_Y + attribute \src "ls180.v:2921.6-2921.90" + case 1'1 + assign $0\main_libresocsim_zero_clear[0:0] 1'1 + case + end + sync always + update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0] + end + attribute \src "ls180.v:292.5-292.25" + process $proc$ls180.v:292$2860 + assign { } { } + assign $1\main_sdram_re[0:0] 1'0 + sync always + sync init + update \main_sdram_re $1\main_sdram_re[0:0] + end + attribute \src "ls180.v:293.11-293.44" + process $proc$ls180.v:293$2861 + assign { } { } + assign $1\main_sdram_command_storage[5:0] 6'000000 + sync always + sync init + update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] + end + attribute \src "ls180.v:2931.1-2935.4" + process $proc$ls180.v:2931$64 + assign { } { } + assign { } { } + assign $0\main_dm[1:0] [0] 1'1 + assign $0\main_dm[1:0] [1] 1'1 + sync always + update \main_dm $0\main_dm[1:0] + end + attribute \src "ls180.v:294.5-294.33" + process $proc$ls180.v:294$2862 + assign { } { } + assign $1\main_sdram_command_re[0:0] 1'0 + sync always + sync init + update \main_sdram_command_re $1\main_sdram_command_re[0:0] + end + attribute \src "ls180.v:2968.1-3022.4" + process $proc$ls180.v:2968$65 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000 + assign $0\main_sdram_master_p0_bank[1:0] 2'00 + assign $0\main_sdram_master_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_master_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_master_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_master_p0_we_n[0:0] 1'1 + assign $0\main_sdram_master_p0_cke[0:0] 1'0 + assign $0\main_sdram_master_p0_odt[0:0] 1'0 + assign $0\main_sdram_master_p0_reset_n[0:0] 1'0 + assign $0\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + assign $0\main_sdram_master_p0_act_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_rddata_valid[0:0] 1'0 + assign $0\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0 + assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0 + assign $0\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 + assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0 + attribute \src "ls180.v:2987.2-3021.5" + switch \main_sdram_sel + attribute \src "ls180.v:2987.6-2987.20" + case 1'1 + assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address + assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank + assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_slave_p0_cas_n + assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_slave_p0_cs_n + assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_slave_p0_ras_n + assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_slave_p0_we_n + assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_slave_p0_cke + assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_slave_p0_odt + assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_slave_p0_reset_n + assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_slave_p0_act_n + assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_slave_p0_wrdata + assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_slave_p0_wrdata_en + assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_slave_p0_wrdata_mask + assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en + assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata + assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid + attribute \src "ls180.v:3004.6-3004.10" + case + assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address + assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank + assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_inti_p0_cas_n + assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_inti_p0_cs_n + assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_inti_p0_ras_n + assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_inti_p0_we_n + assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_inti_p0_cke + assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_inti_p0_odt + assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_inti_p0_reset_n + assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_inti_p0_act_n + assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_inti_p0_wrdata + assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_inti_p0_wrdata_en + assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_inti_p0_wrdata_mask + assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_inti_p0_rddata_en + assign $0\main_sdram_inti_p0_rddata[15:0] \main_sdram_master_p0_rddata + assign $0\main_sdram_inti_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid + end + sync always + update \main_sdram_inti_p0_rddata $0\main_sdram_inti_p0_rddata[15:0] + update \main_sdram_inti_p0_rddata_valid $0\main_sdram_inti_p0_rddata_valid[0:0] + update \main_sdram_slave_p0_rddata $0\main_sdram_slave_p0_rddata[15:0] + update \main_sdram_slave_p0_rddata_valid $0\main_sdram_slave_p0_rddata_valid[0:0] + update \main_sdram_master_p0_address $0\main_sdram_master_p0_address[12:0] + update \main_sdram_master_p0_bank $0\main_sdram_master_p0_bank[1:0] + update \main_sdram_master_p0_cas_n $0\main_sdram_master_p0_cas_n[0:0] + update \main_sdram_master_p0_cs_n $0\main_sdram_master_p0_cs_n[0:0] + update \main_sdram_master_p0_ras_n $0\main_sdram_master_p0_ras_n[0:0] + update \main_sdram_master_p0_we_n $0\main_sdram_master_p0_we_n[0:0] + update \main_sdram_master_p0_cke $0\main_sdram_master_p0_cke[0:0] + update \main_sdram_master_p0_odt $0\main_sdram_master_p0_odt[0:0] + update \main_sdram_master_p0_reset_n $0\main_sdram_master_p0_reset_n[0:0] + update \main_sdram_master_p0_act_n $0\main_sdram_master_p0_act_n[0:0] + update \main_sdram_master_p0_wrdata $0\main_sdram_master_p0_wrdata[15:0] + update \main_sdram_master_p0_wrdata_en $0\main_sdram_master_p0_wrdata_en[0:0] + update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0] + update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0] + end + attribute \src "ls180.v:298.5-298.38" + process $proc$ls180.v:298$2863 + assign { } { } + assign $0\main_sdram_command_issue_w[0:0] 1'0 + sync always + update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] + sync init + end + attribute \src "ls180.v:299.12-299.46" + process $proc$ls180.v:299$2864 + assign { } { } + assign $1\main_sdram_address_storage[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] + end + attribute \src "ls180.v:300.5-300.33" + process $proc$ls180.v:300$2865 + assign { } { } + assign $1\main_sdram_address_re[0:0] 1'0 + sync always + sync init + update \main_sdram_address_re $1\main_sdram_address_re[0:0] + end + attribute \src "ls180.v:301.11-301.45" + process $proc$ls180.v:301$2866 + assign { } { } + assign $1\main_sdram_baddress_storage[1:0] 2'00 + sync always + sync init + update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] + end + attribute \src "ls180.v:302.5-302.34" + process $proc$ls180.v:302$2867 + assign { } { } + assign $1\main_sdram_baddress_re[0:0] 1'0 + sync always + sync init + update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] + end + attribute \src "ls180.v:3026.1-3042.4" + process $proc$ls180.v:3026$66 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 + attribute \src "ls180.v:3031.2-3041.5" + switch \main_sdram_command_issue_re + attribute \src "ls180.v:3031.6-3031.33" + case 1'1 + assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3032$67_Y + assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3033$68_Y + assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3034$69_Y + assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3035$70_Y + attribute \src "ls180.v:3036.6-3036.10" + case + assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 + end + sync always + update \main_sdram_inti_p0_cas_n $0\main_sdram_inti_p0_cas_n[0:0] + update \main_sdram_inti_p0_cs_n $0\main_sdram_inti_p0_cs_n[0:0] + update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0] + update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0] + end + attribute \src "ls180.v:303.12-303.45" + process $proc$ls180.v:303$2868 + assign { } { } + assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] + end + attribute \src "ls180.v:304.5-304.32" + process $proc$ls180.v:304$2869 + assign { } { } + assign $1\main_sdram_wrdata_re[0:0] 1'0 + sync always + sync init + update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] + end + attribute \src "ls180.v:305.12-305.37" + process $proc$ls180.v:305$2870 + assign { } { } + assign $1\main_sdram_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_status $1\main_sdram_status[15:0] + end + attribute \src "ls180.v:3085.1-3115.4" + process $proc$ls180.v:3085$79 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_cmd_valid[0:0] 1'0 + assign { } { } + assign $0\main_sdram_cmd_last[0:0] 1'0 + assign $0\main_sdram_sequencer_start0[0:0] 1'0 + assign $0\builder_refresher_next_state[1:0] \builder_refresher_state + attribute \src "ls180.v:3091.2-3114.9" + switch \builder_refresher_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdram_cmd_valid[0:0] 1'1 + attribute \src "ls180.v:3094.4-3097.7" + switch \main_sdram_cmd_ready + attribute \src "ls180.v:3094.8-3094.28" + case 1'1 + assign $0\main_sdram_sequencer_start0[0:0] 1'1 + assign $0\builder_refresher_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdram_cmd_valid[0:0] 1'1 + attribute \src "ls180.v:3101.4-3105.7" + switch \main_sdram_sequencer_done0 + attribute \src "ls180.v:3101.8-3101.34" + case 1'1 + assign $0\main_sdram_cmd_valid[0:0] 1'0 + assign $0\main_sdram_cmd_last[0:0] 1'1 + assign $0\builder_refresher_next_state[1:0] 2'00 + case + end + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3108.4-3112.7" + switch 1'1 + attribute \src "ls180.v:3108.8-3108.12" + case 1'1 + attribute \src "ls180.v:3109.5-3111.8" + switch \main_sdram_wants_refresh + attribute \src "ls180.v:3109.9-3109.33" + case 1'1 + assign $0\builder_refresher_next_state[1:0] 2'01 + case + end + case + end + end + sync always + update \main_sdram_cmd_valid $0\main_sdram_cmd_valid[0:0] + update \main_sdram_cmd_last $0\main_sdram_cmd_last[0:0] + update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0] + update \builder_refresher_next_state $0\builder_refresher_next_state[1:0] + end + attribute \src "ls180.v:3130.1-3137.4" + process $proc$ls180.v:3130$83 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3132.2-3136.5" + switch \main_sdram_bankmachine0_row_col_n_addr_sel + attribute \src "ls180.v:3132.6-3132.48" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3134.6-3134.10" + case + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3135$85_Y + end + sync always + update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0] + end + attribute \src "ls180.v:3141.1-3148.4" + process $proc$ls180.v:3141$92 + assign { } { } + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3143.2-3147.5" + switch $and$ls180.v:3143$93_Y + attribute \src "ls180.v:3143.6-3143.115" + case 1'1 + attribute \src "ls180.v:3144.3-3146.6" + switch $ne$ls180.v:3144$94_Y + attribute \src "ls180.v:3144.7-3144.143" + case 1'1 + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3145$95_Y + case + end + case + end + sync always + update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0] + end + attribute \src "ls180.v:3163.1-3170.4" + process $proc$ls180.v:3163$96 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3165.2-3169.5" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3165.6-3165.58" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3166$97_Y + attribute \src "ls180.v:3167.6-3167.10" + case + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:3179.1-3272.4" + process $proc$ls180.v:3179$105 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state + attribute \src "ls180.v:3195.2-3271.9" + switch \builder_bankmachine0_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + attribute \src "ls180.v:3197.4-3205.7" + switch $and$ls180.v:3197$106_Y + attribute \src "ls180.v:3197.8-3197.87" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3199.5-3201.8" + switch \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:3199.9-3199.42" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + attribute \src "ls180.v:3209.4-3211.7" + switch $and$ls180.v:3209$107_Y + attribute \src "ls180.v:3209.8-3209.87" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3215.4-3224.7" + switch \main_sdram_bankmachine0_trccon_ready + attribute \src "ls180.v:3215.8-3215.44" + case 1'1 + assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3220.5-3222.8" + switch \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:3220.9-3220.42" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3227.4-3229.7" + switch \main_sdram_bankmachine0_twtpcon_ready + attribute \src "ls180.v:3227.8-3227.45" + case 1'1 + assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3232.4-3234.7" + switch $not$ls180.v:3232$108_Y + attribute \src "ls180.v:3232.8-3232.46" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine0_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine0_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3243.4-3269.7" + switch \main_sdram_bankmachine0_refresh_req + attribute \src "ls180.v:3243.8-3243.43" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'100 + attribute \src "ls180.v:3245.8-3245.12" + case + attribute \src "ls180.v:3246.5-3268.8" + switch \main_sdram_bankmachine0_cmd_buffer_source_valid + attribute \src "ls180.v:3246.9-3246.56" + case 1'1 + attribute \src "ls180.v:3247.6-3267.9" + switch \main_sdram_bankmachine0_row_opened + attribute \src "ls180.v:3247.10-3247.44" + case 1'1 + attribute \src "ls180.v:3248.7-3264.10" + switch \main_sdram_bankmachine0_row_hit + attribute \src "ls180.v:3248.11-3248.42" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3250.8-3257.11" + switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we + attribute \src "ls180.v:3250.12-3250.64" + case 1'1 + assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready + assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3254.12-3254.16" + case + assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready + assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3259.8-3261.11" + switch $and$ls180.v:3259$109_Y + attribute \src "ls180.v:3259.12-3259.88" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3262.11-3262.15" + case + assign $0\builder_bankmachine0_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3265.10-3265.14" + case + assign $0\builder_bankmachine0_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine0_req_wdata_ready $0\main_sdram_bankmachine0_req_wdata_ready[0:0] + update \main_sdram_bankmachine0_req_rdata_valid $0\main_sdram_bankmachine0_req_rdata_valid[0:0] + update \main_sdram_bankmachine0_refresh_gnt $0\main_sdram_bankmachine0_refresh_gnt[0:0] + update \main_sdram_bankmachine0_cmd_valid $0\main_sdram_bankmachine0_cmd_valid[0:0] + update \main_sdram_bankmachine0_cmd_payload_cas $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] + update \main_sdram_bankmachine0_cmd_payload_ras $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] + update \main_sdram_bankmachine0_cmd_payload_we $0\main_sdram_bankmachine0_cmd_payload_we[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_cmd $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_read $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_write $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine0_row_open $0\main_sdram_bankmachine0_row_open[0:0] + update \main_sdram_bankmachine0_row_close $0\main_sdram_bankmachine0_row_close[0:0] + update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0] + end + attribute \src "ls180.v:3287.1-3294.4" + process $proc$ls180.v:3287$113 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3289.2-3293.5" + switch \main_sdram_bankmachine1_row_col_n_addr_sel + attribute \src "ls180.v:3289.6-3289.48" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3291.6-3291.10" + case + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3292$115_Y + end + sync always + update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0] + end + attribute \src "ls180.v:3298.1-3305.4" + process $proc$ls180.v:3298$122 + assign { } { } + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3300.2-3304.5" + switch $and$ls180.v:3300$123_Y + attribute \src "ls180.v:3300.6-3300.115" + case 1'1 + attribute \src "ls180.v:3301.3-3303.6" + switch $ne$ls180.v:3301$124_Y + attribute \src "ls180.v:3301.7-3301.143" + case 1'1 + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3302$125_Y + case + end + case + end + sync always + update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0] + end + attribute \src "ls180.v:3320.1-3327.4" + process $proc$ls180.v:3320$126 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3322.2-3326.5" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3322.6-3322.58" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3323$127_Y + attribute \src "ls180.v:3324.6-3324.10" + case + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:3336.1-3429.4" + process $proc$ls180.v:3336$135 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state + attribute \src "ls180.v:3352.2-3428.9" + switch \builder_bankmachine1_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + attribute \src "ls180.v:3354.4-3362.7" + switch $and$ls180.v:3354$136_Y + attribute \src "ls180.v:3354.8-3354.87" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3356.5-3358.8" + switch \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:3356.9-3356.42" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + attribute \src "ls180.v:3366.4-3368.7" + switch $and$ls180.v:3366$137_Y + attribute \src "ls180.v:3366.8-3366.87" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3372.4-3381.7" + switch \main_sdram_bankmachine1_trccon_ready + attribute \src "ls180.v:3372.8-3372.44" + case 1'1 + assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3377.5-3379.8" + switch \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:3377.9-3377.42" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3384.4-3386.7" + switch \main_sdram_bankmachine1_twtpcon_ready + attribute \src "ls180.v:3384.8-3384.45" + case 1'1 + assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3389.4-3391.7" + switch $not$ls180.v:3389$138_Y + attribute \src "ls180.v:3389.8-3389.46" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine1_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine1_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3400.4-3426.7" + switch \main_sdram_bankmachine1_refresh_req + attribute \src "ls180.v:3400.8-3400.43" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'100 + attribute \src "ls180.v:3402.8-3402.12" + case + attribute \src "ls180.v:3403.5-3425.8" + switch \main_sdram_bankmachine1_cmd_buffer_source_valid + attribute \src "ls180.v:3403.9-3403.56" + case 1'1 + attribute \src "ls180.v:3404.6-3424.9" + switch \main_sdram_bankmachine1_row_opened + attribute \src "ls180.v:3404.10-3404.44" + case 1'1 + attribute \src "ls180.v:3405.7-3421.10" + switch \main_sdram_bankmachine1_row_hit + attribute \src "ls180.v:3405.11-3405.42" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3407.8-3414.11" + switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we + attribute \src "ls180.v:3407.12-3407.64" + case 1'1 + assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready + assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3411.12-3411.16" + case + assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready + assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3416.8-3418.11" + switch $and$ls180.v:3416$139_Y + attribute \src "ls180.v:3416.12-3416.88" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3419.11-3419.15" + case + assign $0\builder_bankmachine1_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3422.10-3422.14" + case + assign $0\builder_bankmachine1_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine1_req_wdata_ready $0\main_sdram_bankmachine1_req_wdata_ready[0:0] + update \main_sdram_bankmachine1_req_rdata_valid $0\main_sdram_bankmachine1_req_rdata_valid[0:0] + update \main_sdram_bankmachine1_refresh_gnt $0\main_sdram_bankmachine1_refresh_gnt[0:0] + update \main_sdram_bankmachine1_cmd_valid $0\main_sdram_bankmachine1_cmd_valid[0:0] + update \main_sdram_bankmachine1_cmd_payload_cas $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] + update \main_sdram_bankmachine1_cmd_payload_ras $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] + update \main_sdram_bankmachine1_cmd_payload_we $0\main_sdram_bankmachine1_cmd_payload_we[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_cmd $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_read $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_write $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine1_row_open $0\main_sdram_bankmachine1_row_open[0:0] + update \main_sdram_bankmachine1_row_close $0\main_sdram_bankmachine1_row_close[0:0] + update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0] + end + attribute \src "ls180.v:335.12-335.46" + process $proc$ls180.v:335$2871 + assign { } { } + assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] + end + attribute \src "ls180.v:336.11-336.47" + process $proc$ls180.v:336$2872 + assign { } { } + assign $1\main_sdram_interface_wdata_we[1:0] 2'00 + sync always + sync init + update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] + end + attribute \src "ls180.v:338.12-338.45" + process $proc$ls180.v:338$2873 + assign { } { } + assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] + end + attribute \src "ls180.v:339.11-339.40" + process $proc$ls180.v:339$2874 + assign { } { } + assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 + sync always + sync init + update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] + end + attribute \src "ls180.v:340.5-340.35" + process $proc$ls180.v:340$2875 + assign { } { } + assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] + end + attribute \src "ls180.v:341.5-341.34" + process $proc$ls180.v:341$2876 + assign { } { } + assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] + end + attribute \src "ls180.v:342.5-342.35" + process $proc$ls180.v:342$2877 + assign { } { } + assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] + end + attribute \src "ls180.v:343.5-343.34" + process $proc$ls180.v:343$2878 + assign { } { } + assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] + end + attribute \src "ls180.v:3444.1-3451.4" + process $proc$ls180.v:3444$143 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3446.2-3450.5" + switch \main_sdram_bankmachine2_row_col_n_addr_sel + attribute \src "ls180.v:3446.6-3446.48" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3448.6-3448.10" + case + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3449$145_Y + end + sync always + update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0] + end + attribute \src "ls180.v:3455.1-3462.4" + process $proc$ls180.v:3455$152 + assign { } { } + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3457.2-3461.5" + switch $and$ls180.v:3457$153_Y + attribute \src "ls180.v:3457.6-3457.115" + case 1'1 + attribute \src "ls180.v:3458.3-3460.6" + switch $ne$ls180.v:3458$154_Y + attribute \src "ls180.v:3458.7-3458.143" + case 1'1 + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3459$155_Y + case + end + case + end + sync always + update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0] + end + attribute \src "ls180.v:347.5-347.35" + process $proc$ls180.v:347$2879 + assign { } { } + assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 + sync always + update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] + sync init + end + attribute \src "ls180.v:3477.1-3484.4" + process $proc$ls180.v:3477$156 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3479.2-3483.5" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3479.6-3479.58" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3480$157_Y + attribute \src "ls180.v:3481.6-3481.10" + case + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:349.5-349.39" + process $proc$ls180.v:349$2880 + assign { } { } + assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] + end + attribute \src "ls180.v:3493.1-3586.4" + process $proc$ls180.v:3493$165 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state + attribute \src "ls180.v:3509.2-3585.9" + switch \builder_bankmachine2_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + attribute \src "ls180.v:3511.4-3519.7" + switch $and$ls180.v:3511$166_Y + attribute \src "ls180.v:3511.8-3511.87" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3513.5-3515.8" + switch \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:3513.9-3513.42" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + attribute \src "ls180.v:3523.4-3525.7" + switch $and$ls180.v:3523$167_Y + attribute \src "ls180.v:3523.8-3523.87" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3529.4-3538.7" + switch \main_sdram_bankmachine2_trccon_ready + attribute \src "ls180.v:3529.8-3529.44" + case 1'1 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3534.5-3536.8" + switch \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:3534.9-3534.42" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3541.4-3543.7" + switch \main_sdram_bankmachine2_twtpcon_ready + attribute \src "ls180.v:3541.8-3541.45" + case 1'1 + assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3546.4-3548.7" + switch $not$ls180.v:3546$168_Y + attribute \src "ls180.v:3546.8-3546.46" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine2_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine2_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3557.4-3583.7" + switch \main_sdram_bankmachine2_refresh_req + attribute \src "ls180.v:3557.8-3557.43" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'100 + attribute \src "ls180.v:3559.8-3559.12" + case + attribute \src "ls180.v:3560.5-3582.8" + switch \main_sdram_bankmachine2_cmd_buffer_source_valid + attribute \src "ls180.v:3560.9-3560.56" + case 1'1 + attribute \src "ls180.v:3561.6-3581.9" + switch \main_sdram_bankmachine2_row_opened + attribute \src "ls180.v:3561.10-3561.44" + case 1'1 + attribute \src "ls180.v:3562.7-3578.10" + switch \main_sdram_bankmachine2_row_hit + attribute \src "ls180.v:3562.11-3562.42" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3564.8-3571.11" + switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we + attribute \src "ls180.v:3564.12-3564.64" + case 1'1 + assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready + assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3568.12-3568.16" + case + assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready + assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3573.8-3575.11" + switch $and$ls180.v:3573$169_Y + attribute \src "ls180.v:3573.12-3573.88" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3576.11-3576.15" + case + assign $0\builder_bankmachine2_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3579.10-3579.14" + case + assign $0\builder_bankmachine2_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine2_req_wdata_ready $0\main_sdram_bankmachine2_req_wdata_ready[0:0] + update \main_sdram_bankmachine2_req_rdata_valid $0\main_sdram_bankmachine2_req_rdata_valid[0:0] + update \main_sdram_bankmachine2_refresh_gnt $0\main_sdram_bankmachine2_refresh_gnt[0:0] + update \main_sdram_bankmachine2_cmd_valid $0\main_sdram_bankmachine2_cmd_valid[0:0] + update \main_sdram_bankmachine2_cmd_payload_cas $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] + update \main_sdram_bankmachine2_cmd_payload_ras $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] + update \main_sdram_bankmachine2_cmd_payload_we $0\main_sdram_bankmachine2_cmd_payload_we[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_cmd $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_read $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_write $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine2_row_open $0\main_sdram_bankmachine2_row_open[0:0] + update \main_sdram_bankmachine2_row_close $0\main_sdram_bankmachine2_row_close[0:0] + update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0] + end + attribute \src "ls180.v:351.5-351.39" + process $proc$ls180.v:351$2881 + assign { } { } + assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] + end + attribute \src "ls180.v:354.5-354.32" + process $proc$ls180.v:354$2882 + assign { } { } + assign $1\main_sdram_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] + end + attribute \src "ls180.v:355.5-355.32" + process $proc$ls180.v:355$2883 + assign { } { } + assign $1\main_sdram_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] + end + attribute \src "ls180.v:356.5-356.31" + process $proc$ls180.v:356$2884 + assign { } { } + assign $1\main_sdram_cmd_last[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] + end + attribute \src "ls180.v:357.12-357.44" + process $proc$ls180.v:357$2885 + assign { } { } + assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] + end + attribute \src "ls180.v:358.11-358.43" + process $proc$ls180.v:358$2886 + assign { } { } + assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 + sync always + sync init + update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] + end + attribute \src "ls180.v:359.5-359.38" + process $proc$ls180.v:359$2887 + assign { } { } + assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:360.5-360.38" + process $proc$ls180.v:360$2888 + assign { } { } + assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:3601.1-3608.4" + process $proc$ls180.v:3601$173 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3603.2-3607.5" + switch \main_sdram_bankmachine3_row_col_n_addr_sel + attribute \src "ls180.v:3603.6-3603.48" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3605.6-3605.10" + case + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3606$175_Y + end + sync always + update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0] + end + attribute \src "ls180.v:361.5-361.37" + process $proc$ls180.v:361$2889 + assign { } { } + assign $1\main_sdram_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] + end + attribute \src "ls180.v:3612.1-3619.4" + process $proc$ls180.v:3612$182 + assign { } { } + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3614.2-3618.5" + switch $and$ls180.v:3614$183_Y + attribute \src "ls180.v:3614.6-3614.115" + case 1'1 + attribute \src "ls180.v:3615.3-3617.6" + switch $ne$ls180.v:3615$184_Y + attribute \src "ls180.v:3615.7-3615.143" + case 1'1 + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3616$185_Y + case + end + case + end + sync always + update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0] + end + attribute \src "ls180.v:362.5-362.42" + process $proc$ls180.v:362$2890 + assign { } { } + assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] + sync init + end + attribute \src "ls180.v:363.5-363.43" + process $proc$ls180.v:363$2891 + assign { } { } + assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] + sync init + end + attribute \src "ls180.v:3634.1-3641.4" + process $proc$ls180.v:3634$186 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3636.2-3640.5" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3636.6-3636.58" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3637$187_Y + attribute \src "ls180.v:3638.6-3638.10" + case + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:3650.1-3743.4" + process $proc$ls180.v:3650$195 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + assign { } { } + assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state + attribute \src "ls180.v:3666.2-3742.9" + switch \builder_bankmachine3_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + attribute \src "ls180.v:3668.4-3676.7" + switch $and$ls180.v:3668$196_Y + attribute \src "ls180.v:3668.8-3668.87" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3670.5-3672.8" + switch \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:3670.9-3670.42" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + attribute \src "ls180.v:3680.4-3682.7" + switch $and$ls180.v:3680$197_Y + attribute \src "ls180.v:3680.8-3680.87" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3686.4-3695.7" + switch \main_sdram_bankmachine3_trccon_ready + attribute \src "ls180.v:3686.8-3686.44" + case 1'1 + assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3691.5-3693.8" + switch \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:3691.9-3691.42" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3698.4-3700.7" + switch \main_sdram_bankmachine3_twtpcon_ready + attribute \src "ls180.v:3698.8-3698.45" + case 1'1 + assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3703.4-3705.7" + switch $not$ls180.v:3703$198_Y + attribute \src "ls180.v:3703.8-3703.46" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine3_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine3_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3714.4-3740.7" + switch \main_sdram_bankmachine3_refresh_req + attribute \src "ls180.v:3714.8-3714.43" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'100 + attribute \src "ls180.v:3716.8-3716.12" + case + attribute \src "ls180.v:3717.5-3739.8" + switch \main_sdram_bankmachine3_cmd_buffer_source_valid + attribute \src "ls180.v:3717.9-3717.56" + case 1'1 + attribute \src "ls180.v:3718.6-3738.9" + switch \main_sdram_bankmachine3_row_opened + attribute \src "ls180.v:3718.10-3718.44" + case 1'1 + attribute \src "ls180.v:3719.7-3735.10" + switch \main_sdram_bankmachine3_row_hit + attribute \src "ls180.v:3719.11-3719.42" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3721.8-3728.11" + switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we + attribute \src "ls180.v:3721.12-3721.64" + case 1'1 + assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready + assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3725.12-3725.16" + case + assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready + assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3730.8-3732.11" + switch $and$ls180.v:3730$199_Y + attribute \src "ls180.v:3730.12-3730.88" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3733.11-3733.15" + case + assign $0\builder_bankmachine3_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3736.10-3736.14" + case + assign $0\builder_bankmachine3_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine3_req_wdata_ready $0\main_sdram_bankmachine3_req_wdata_ready[0:0] + update \main_sdram_bankmachine3_req_rdata_valid $0\main_sdram_bankmachine3_req_rdata_valid[0:0] + update \main_sdram_bankmachine3_refresh_gnt $0\main_sdram_bankmachine3_refresh_gnt[0:0] + update \main_sdram_bankmachine3_cmd_valid $0\main_sdram_bankmachine3_cmd_valid[0:0] + update \main_sdram_bankmachine3_cmd_payload_cas $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] + update \main_sdram_bankmachine3_cmd_payload_ras $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] + update \main_sdram_bankmachine3_cmd_payload_we $0\main_sdram_bankmachine3_cmd_payload_we[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_cmd $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_read $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_write $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine3_row_open $0\main_sdram_bankmachine3_row_open[0:0] + update \main_sdram_bankmachine3_row_close $0\main_sdram_bankmachine3_row_close[0:0] + update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0] + end + attribute \src "ls180.v:369.11-369.44" + process $proc$ls180.v:369$2892 + assign { } { } + assign $1\main_sdram_timer_count1[9:0] 10'1100001101 + sync always + sync init + update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] + end + attribute \src "ls180.v:371.5-371.38" + process $proc$ls180.v:371$2893 + assign { } { } + assign $1\main_sdram_postponer_req_o[0:0] 1'0 + sync always + sync init + update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] + end + attribute \src "ls180.v:372.5-372.38" + process $proc$ls180.v:372$2894 + assign { } { } + assign $1\main_sdram_postponer_count[0:0] 1'0 + sync always + sync init + update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] + end + attribute \src "ls180.v:373.5-373.39" + process $proc$ls180.v:373$2895 + assign { } { } + assign $1\main_sdram_sequencer_start0[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] + end + attribute \src "ls180.v:376.5-376.38" + process $proc$ls180.v:376$2896 + assign { } { } + assign $1\main_sdram_sequencer_done1[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] + end + attribute \src "ls180.v:3763.1-3769.4" + process $proc$ls180.v:3763$238 + assign { } { } + assign { } { } + assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3765$251_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3766$264_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3767$277_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3768$290_Y + sync always + update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] + end + attribute \src "ls180.v:377.11-377.46" + process $proc$ls180.v:377$2897 + assign { } { } + assign $1\main_sdram_sequencer_counter[3:0] 4'0000 + sync always + sync init + update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] + end + attribute \src "ls180.v:3777.1-3782.4" + process $proc$ls180.v:3777$291 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + attribute \src "ls180.v:3779.2-3781.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:3779.6-3779.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:378.5-378.38" + process $proc$ls180.v:378$2898 + assign { } { } + assign $1\main_sdram_sequencer_count[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] + end + attribute \src "ls180.v:3783.1-3788.4" + process $proc$ls180.v:3783$292 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + attribute \src "ls180.v:3785.2-3787.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:3785.6-3785.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:3789.1-3794.4" + process $proc$ls180.v:3789$293 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + attribute \src "ls180.v:3791.2-3793.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:3791.6-3791.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0] + end + attribute \src "ls180.v:3796.1-3802.4" + process $proc$ls180.v:3796$296 + assign { } { } + assign { } { } + assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3798$309_Y + assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3799$322_Y + assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3800$335_Y + assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3801$348_Y + sync always + update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] + end + attribute \src "ls180.v:3810.1-3815.4" + process $proc$ls180.v:3810$349 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 + attribute \src "ls180.v:3812.2-3814.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:3812.6-3812.37" + case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3 + case + end + sync always + update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:3816.1-3821.4" + process $proc$ls180.v:3816$350 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 + attribute \src "ls180.v:3818.2-3820.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:3818.6-3818.37" + case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4 + case + end + sync always + update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:3822.1-3827.4" + process $proc$ls180.v:3822$351 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 + attribute \src "ls180.v:3824.2-3826.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:3824.6-3824.37" + case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5 + case + end + sync always + update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0] + end + attribute \src "ls180.v:3828.1-3836.4" + process $proc$ls180.v:3828$352 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:3830.2-3832.5" + switch $and$ls180.v:3830$355_Y + attribute \src "ls180.v:3830.6-3830.115" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:3833.2-3835.5" + switch $and$ls180.v:3833$358_Y + attribute \src "ls180.v:3833.6-3833.115" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0] + end + attribute \src "ls180.v:3837.1-3845.4" + process $proc$ls180.v:3837$359 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:3839.2-3841.5" + switch $and$ls180.v:3839$362_Y + attribute \src "ls180.v:3839.6-3839.115" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:3842.2-3844.5" + switch $and$ls180.v:3842$365_Y + attribute \src "ls180.v:3842.6-3842.115" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0] + end + attribute \src "ls180.v:384.5-384.51" + process $proc$ls180.v:384$2899 + assign { } { } + assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + end + attribute \src "ls180.v:3846.1-3854.4" + process $proc$ls180.v:3846$366 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:3848.2-3850.5" + switch $and$ls180.v:3848$369_Y + attribute \src "ls180.v:3848.6-3848.115" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:3851.2-3853.5" + switch $and$ls180.v:3851$372_Y + attribute \src "ls180.v:3851.6-3851.115" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0] + end + attribute \src "ls180.v:385.5-385.51" + process $proc$ls180.v:385$2900 + assign { } { } + assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] + end + attribute \src "ls180.v:3855.1-3863.4" + process $proc$ls180.v:3855$373 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:3857.2-3859.5" + switch $and$ls180.v:3857$376_Y + attribute \src "ls180.v:3857.6-3857.115" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:3860.2-3862.5" + switch $and$ls180.v:3860$379_Y + attribute \src "ls180.v:3860.6-3860.115" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0] + end + attribute \src "ls180.v:3868.1-3940.4" + process $proc$ls180.v:3868$382 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_en0[0:0] 1'0 + assign $0\main_sdram_en1[0:0] 1'0 + assign $0\main_sdram_choose_req_want_reads[0:0] 1'0 + assign $0\main_sdram_choose_req_want_writes[0:0] 1'0 + assign $0\main_sdram_cmd_ready[0:0] 1'0 + assign { } { } + assign { } { } + assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 + assign $0\main_sdram_steerer_sel[1:0] 2'00 + assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed + assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state + attribute \src "ls180.v:3880.2-3939.9" + switch \builder_multiplexer_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_en1[0:0] 1'1 + assign $0\main_sdram_choose_req_want_writes[0:0] 1'1 + assign $0\main_sdram_steerer_sel[1:0] 2'10 + attribute \src "ls180.v:3884.4-3890.7" + switch 1'1 + attribute \src "ls180.v:3884.8-3884.12" + case 1'1 + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3885$389_Y + case + end + attribute \src "ls180.v:3892.4-3896.7" + switch \main_sdram_read_available + attribute \src "ls180.v:3892.8-3892.33" + case 1'1 + attribute \src "ls180.v:3893.5-3895.8" + switch $or$ls180.v:3893$391_Y + attribute \src "ls180.v:3893.9-3893.63" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'011 + case + end + case + end + attribute \src "ls180.v:3897.4-3899.7" + switch \main_sdram_go_to_refresh + attribute \src "ls180.v:3897.8-3897.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_steerer_sel[1:0] 2'11 + assign $0\main_sdram_cmd_ready[0:0] 1'1 + attribute \src "ls180.v:3904.4-3906.7" + switch \main_sdram_cmd_last + attribute \src "ls180.v:3904.8-3904.27" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3909.4-3911.7" + switch \main_sdram_twtrcon_ready + attribute \src "ls180.v:3909.8-3909.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_multiplexer_next_state[2:0] 3'101 + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_multiplexer_next_state[2:0] 3'001 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdram_en0[0:0] 1'1 + assign $0\main_sdram_choose_req_want_reads[0:0] 1'1 + assign $0\main_sdram_steerer_sel[1:0] 2'10 + attribute \src "ls180.v:3922.4-3928.7" + switch 1'1 + attribute \src "ls180.v:3922.8-3922.12" + case 1'1 + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3923$398_Y + case + end + attribute \src "ls180.v:3930.4-3934.7" + switch \main_sdram_write_available + attribute \src "ls180.v:3930.8-3930.34" + case 1'1 + attribute \src "ls180.v:3931.5-3933.8" + switch $or$ls180.v:3931$400_Y + attribute \src "ls180.v:3931.9-3931.62" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'100 + case + end + case + end + attribute \src "ls180.v:3935.4-3937.7" + switch \main_sdram_go_to_refresh + attribute \src "ls180.v:3935.8-3935.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'010 + case + end + end + sync always + update \main_sdram_cmd_ready $0\main_sdram_cmd_ready[0:0] + update \main_sdram_choose_req_want_reads $0\main_sdram_choose_req_want_reads[0:0] + update \main_sdram_choose_req_want_writes $0\main_sdram_choose_req_want_writes[0:0] + update \main_sdram_choose_req_want_activates $0\main_sdram_choose_req_want_activates[0:0] + update \main_sdram_choose_req_cmd_ready $0\main_sdram_choose_req_cmd_ready[0:0] + update \main_sdram_steerer_sel $0\main_sdram_steerer_sel[1:0] + update \main_sdram_en0 $0\main_sdram_en0[0:0] + update \main_sdram_en1 $0\main_sdram_en1[0:0] + update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0] + end + attribute \src "ls180.v:387.5-387.47" + process $proc$ls180.v:387$2901 + assign { } { } + assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] + end + attribute \src "ls180.v:388.5-388.45" + process $proc$ls180.v:388$2902 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] + end + attribute \src "ls180.v:389.5-389.45" + process $proc$ls180.v:389$2903 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] + end + attribute \src "ls180.v:390.12-390.57" + process $proc$ls180.v:390$2904 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + end + attribute \src "ls180.v:392.5-392.51" + process $proc$ls180.v:392$2905 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:393.5-393.51" + process $proc$ls180.v:393$2906 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:394.5-394.50" + process $proc$ls180.v:394$2907 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] + end + attribute \src "ls180.v:395.5-395.54" + process $proc$ls180.v:395$2908 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:396.5-396.55" + process $proc$ls180.v:396$2909 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:3964.1-3977.4" + process $proc$ls180.v:3964$529 + assign { } { } + assign { } { } + assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 + assign $0\main_sdram_interface_wdata_we[1:0] 2'00 + attribute \src "ls180.v:3967.2-3976.9" + switch \builder_new_master_wdata_ready + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdram_interface_wdata[15:0] \main_port_wdata_payload_data + assign $0\main_sdram_interface_wdata_we[1:0] \main_port_wdata_payload_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 + assign $0\main_sdram_interface_wdata_we[1:0] 2'00 + end + sync always + update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0] + update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0] + end + attribute \src "ls180.v:397.5-397.56" + process $proc$ls180.v:397$2910 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:398.5-398.50" + process $proc$ls180.v:398$2911 + assign { } { } + assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] + end + attribute \src "ls180.v:3984.1-3994.4" + process $proc$ls180.v:3984$531 + assign { } { } + assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000 + attribute \src "ls180.v:3986.2-3993.9" + switch \main_converter_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [15:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [31:16] + case + end + sync always + update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0] + end + attribute \src "ls180.v:3996.1-4042.4" + process $proc$ls180.v:3996$532 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_converter_skip[0:0] 1'0 + assign { } { } + assign $0\main_wb_sdram_ack[0:0] 1'0 + assign $0\main_converter_counter_converter_next_value[0:0] 1'0 + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0 + assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_litedram_wb_sel[1:0] 2'00 + assign $0\main_litedram_wb_cyc[0:0] 1'0 + assign $0\main_litedram_wb_stb[0:0] 1'0 + assign $0\main_litedram_wb_we[0:0] 1'0 + assign $0\builder_converter_next_state[0:0] \builder_converter_state + attribute \src "ls180.v:4008.2-4041.9" + switch \builder_converter_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter } + attribute \src "ls180.v:4011.4-4018.11" + switch \main_converter_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [1:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2] + case + end + attribute \src "ls180.v:4019.4-4032.7" + switch $and$ls180.v:4019$533_Y + attribute \src "ls180.v:4019.8-4019.47" + case 1'1 + assign $0\main_converter_skip[0:0] $eq$ls180.v:4020$534_Y + assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we + assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4022$535_Y + assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4023$536_Y + attribute \src "ls180.v:4024.5-4031.8" + switch $or$ls180.v:4024$537_Y + attribute \src "ls180.v:4024.9-4024.53" + case 1'1 + assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4025$538_Y + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4027.6-4030.9" + switch $eq$ls180.v:4027$539_Y + attribute \src "ls180.v:4027.10-4027.42" + case 1'1 + assign $0\main_wb_sdram_ack[0:0] 1'1 + assign $0\builder_converter_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_converter_counter_converter_next_value[0:0] 1'0 + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4037.4-4039.7" + switch $and$ls180.v:4037$540_Y + attribute \src "ls180.v:4037.8-4037.47" + case 1'1 + assign $0\builder_converter_next_state[0:0] 1'1 + case + end + end + sync always + update \main_wb_sdram_ack $0\main_wb_sdram_ack[0:0] + update \main_litedram_wb_adr $0\main_litedram_wb_adr[29:0] + update \main_litedram_wb_sel $0\main_litedram_wb_sel[1:0] + update \main_litedram_wb_cyc $0\main_litedram_wb_cyc[0:0] + update \main_litedram_wb_stb $0\main_litedram_wb_stb[0:0] + update \main_litedram_wb_we $0\main_litedram_wb_we[0:0] + update \main_converter_skip $0\main_converter_skip[0:0] + update \builder_converter_next_state $0\builder_converter_next_state[0:0] + update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0] + update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0] + end + attribute \src "ls180.v:401.5-401.67" + process $proc$ls180.v:401$2912 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:402.5-402.66" + process $proc$ls180.v:402$2913 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:4087.1-4092.4" + process $proc$ls180.v:4087$572 + assign { } { } + assign $0\main_uart_tx_clear[0:0] 1'0 + attribute \src "ls180.v:4089.2-4091.5" + switch $and$ls180.v:4089$573_Y + attribute \src "ls180.v:4089.6-4089.79" + case 1'1 + assign $0\main_uart_tx_clear[0:0] 1'1 + case + end + sync always + update \main_uart_tx_clear $0\main_uart_tx_clear[0:0] + end + attribute \src "ls180.v:4093.1-4097.4" + process $proc$ls180.v:4093$574 + assign { } { } + assign { } { } + assign $0\main_uart_eventmanager_status_w[1:0] [0] \main_uart_tx_status + assign $0\main_uart_eventmanager_status_w[1:0] [1] \main_uart_rx_status + sync always + update \main_uart_eventmanager_status_w $0\main_uart_eventmanager_status_w[1:0] + end + attribute \src "ls180.v:4098.1-4103.4" + process $proc$ls180.v:4098$575 + assign { } { } + assign $0\main_uart_rx_clear[0:0] 1'0 + attribute \src "ls180.v:4100.2-4102.5" + switch $and$ls180.v:4100$576_Y + attribute \src "ls180.v:4100.6-4100.79" + case 1'1 + assign $0\main_uart_rx_clear[0:0] 1'1 + case + end + sync always + update \main_uart_rx_clear $0\main_uart_rx_clear[0:0] + end + attribute \src "ls180.v:4104.1-4108.4" + process $proc$ls180.v:4104$577 + assign { } { } + assign { } { } + assign $0\main_uart_eventmanager_pending_w[1:0] [0] \main_uart_tx_pending + assign $0\main_uart_eventmanager_pending_w[1:0] [1] \main_uart_rx_pending + sync always + update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0] + end + attribute \src "ls180.v:4126.1-4133.4" + process $proc$ls180.v:4126$585 + assign { } { } + assign $0\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 + attribute \src "ls180.v:4128.2-4132.5" + switch \main_uart_tx_fifo_replace + attribute \src "ls180.v:4128.6-4128.31" + case 1'1 + assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4129$586_Y + attribute \src "ls180.v:4130.6-4130.10" + case + assign $0\main_uart_tx_fifo_wrport_adr[3:0] \main_uart_tx_fifo_produce + end + sync always + update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:4156.1-4163.4" + process $proc$ls180.v:4156$596 + assign { } { } + assign $0\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 + attribute \src "ls180.v:4158.2-4162.5" + switch \main_uart_rx_fifo_replace + attribute \src "ls180.v:4158.6-4158.31" + case 1'1 + assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4159$597_Y + attribute \src "ls180.v:4160.6-4160.10" + case + assign $0\main_uart_rx_fifo_wrport_adr[3:0] \main_uart_rx_fifo_produce + end + sync always + update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:417.11-417.68" + process $proc$ls180.v:417$2914 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:418.5-418.64" + process $proc$ls180.v:418$2915 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:4186.1-4234.4" + process $proc$ls180.v:4186$607 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_spi_master_irq[0:0] 1'0 + assign $0\main_spi_master_count_spimaster0_next_value[2:0] 3'000 + assign $0\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'0 + assign $0\main_spi_master_miso_latch[0:0] 1'0 + assign $0\main_spi_master_clk_enable[0:0] 1'0 + assign $0\main_spi_master_cs_enable[0:0] 1'0 + assign $0\main_spi_master_mosi_latch[0:0] 1'0 + assign $0\main_spi_master_done0[0:0] 1'0 + assign { } { } + assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state + attribute \src "ls180.v:4197.2-4233.9" + switch \builder_spimaster0_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_spi_master_count_spimaster0_next_value[2:0] 3'000 + assign $0\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4201.4-4204.7" + switch \main_spi_master_clk_fall + attribute \src "ls180.v:4201.8-4201.32" + case 1'1 + assign $0\main_spi_master_cs_enable[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_spi_master_clk_enable[0:0] 1'1 + assign $0\main_spi_master_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4209.4-4215.7" + switch \main_spi_master_clk_fall + attribute \src "ls180.v:4209.8-4209.32" + case 1'1 + assign $0\main_spi_master_count_spimaster0_next_value[2:0] $add$ls180.v:4210$608_Y + assign $0\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4212.5-4214.8" + switch $eq$ls180.v:4212$610_Y + attribute \src "ls180.v:4212.9-4212.68" + case 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'11 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\main_spi_master_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4219.4-4223.7" + switch \main_spi_master_clk_rise + attribute \src "ls180.v:4219.8-4219.32" + case 1'1 + assign $0\main_spi_master_miso_latch[0:0] 1'1 + assign $0\main_spi_master_irq[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'00 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_spi_master_done0[0:0] 1'1 + attribute \src "ls180.v:4227.4-4231.7" + switch \main_spi_master_start0 + attribute \src "ls180.v:4227.8-4227.30" + case 1'1 + assign $0\main_spi_master_done0[0:0] 1'0 + assign $0\main_spi_master_mosi_latch[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'01 + case + end + end + sync always + update \main_spi_master_done0 $0\main_spi_master_done0[0:0] + update \main_spi_master_irq $0\main_spi_master_irq[0:0] + update \main_spi_master_clk_enable $0\main_spi_master_clk_enable[0:0] + update \main_spi_master_cs_enable $0\main_spi_master_cs_enable[0:0] + update \main_spi_master_mosi_latch $0\main_spi_master_mosi_latch[0:0] + update \main_spi_master_miso_latch $0\main_spi_master_miso_latch[0:0] + update \builder_spimaster0_next_state $0\builder_spimaster0_next_state[1:0] + update \main_spi_master_count_spimaster0_next_value $0\main_spi_master_count_spimaster0_next_value[2:0] + update \main_spi_master_count_spimaster0_next_value_ce $0\main_spi_master_count_spimaster0_next_value_ce[0:0] + end + attribute \src "ls180.v:419.11-419.70" + process $proc$ls180.v:419$2916 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:420.11-420.70" + process $proc$ls180.v:420$2917 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:421.11-421.73" + process $proc$ls180.v:421$2918 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:4262.1-4290.4" + process $proc$ls180.v:4262$632 + assign { } { } + assign $0\main_sdphy_clocker_clk1[0:0] 1'0 + attribute \src "ls180.v:4264.2-4289.9" + switch \main_sdphy_clocker_storage + attribute \src "ls180.v:0.0-0.0" + case 9'000000100 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [1] + attribute \src "ls180.v:0.0-0.0" + case 9'000001000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [2] + attribute \src "ls180.v:0.0-0.0" + case 9'000010000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [3] + attribute \src "ls180.v:0.0-0.0" + case 9'000100000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [4] + attribute \src "ls180.v:0.0-0.0" + case 9'001000000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [5] + attribute \src "ls180.v:0.0-0.0" + case 9'010000000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [6] + attribute \src "ls180.v:0.0-0.0" + case 9'100000000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [7] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [0] + end + sync always + update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0] + end + attribute \src "ls180.v:4292.1-4325.4" + process $proc$ls180.v:4292$635 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 + assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state + attribute \src "ls180.v:4302.2-4324.9" + switch \builder_sdphy_sdphyinit_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'1111 + attribute \src "ls180.v:4309.4-4315.7" + switch \main_sdphy_init_pads_out_ready + attribute \src "ls180.v:4309.8-4309.38" + case 1'1 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4310$636_Y + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4312.5-4314.8" + switch $eq$ls180.v:4312$637_Y + attribute \src "ls180.v:4312.9-4312.41" + case 1'1 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4320.4-4322.7" + switch \main_sdphy_init_initialize_re + attribute \src "ls180.v:4320.8-4320.37" + case 1'1 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1 + case + end + end + sync always + update \main_sdphy_init_pads_out_payload_clk $0\main_sdphy_init_pads_out_payload_clk[0:0] + update \main_sdphy_init_pads_out_payload_cmd_o $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] + update \main_sdphy_init_pads_out_payload_cmd_oe $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + update \main_sdphy_init_pads_out_payload_data_o $0\main_sdphy_init_pads_out_payload_data_o[3:0] + update \main_sdphy_init_pads_out_payload_data_oe $0\main_sdphy_init_pads_out_payload_data_oe[0:0] + update \builder_sdphy_sdphyinit_next_state $0\builder_sdphy_sdphyinit_next_state[0:0] + update \main_sdphy_init_count_sdphy_sdphyinit_next_value $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + end + attribute \src "ls180.v:4326.1-4402.4" + process $proc$ls180.v:4326$638 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_cmdw_done[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state + attribute \src "ls180.v:4336.2-4401.9" + switch \builder_sdphy_sdphycmdw_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 + attribute \src "ls180.v:4340.4-4365.11" + switch \main_sdphy_cmdw_count + attribute \src "ls180.v:0.0-0.0" + case 8'00000000 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [7] + attribute \src "ls180.v:0.0-0.0" + case 8'00000001 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [6] + attribute \src "ls180.v:0.0-0.0" + case 8'00000010 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [5] + attribute \src "ls180.v:0.0-0.0" + case 8'00000011 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [4] + attribute \src "ls180.v:0.0-0.0" + case 8'00000100 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [3] + attribute \src "ls180.v:0.0-0.0" + case 8'00000101 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [2] + attribute \src "ls180.v:0.0-0.0" + case 8'00000110 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [1] + attribute \src "ls180.v:0.0-0.0" + case 8'00000111 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [0] + case + end + attribute \src "ls180.v:4366.4-4377.7" + switch \main_sdphy_cmdw_pads_out_ready + attribute \src "ls180.v:4366.8-4366.38" + case 1'1 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4367$639_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4369.5-4376.8" + switch $eq$ls180.v:4369$640_Y + attribute \src "ls180.v:4369.9-4369.40" + case 1'1 + attribute \src "ls180.v:4370.6-4375.9" + switch \main_sdphy_cmdw_sink_last + attribute \src "ls180.v:4370.10-4370.35" + case 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10 + attribute \src "ls180.v:4372.10-4372.14" + case + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'1 + attribute \src "ls180.v:4383.4-4390.7" + switch \main_sdphy_cmdw_pads_out_ready + attribute \src "ls180.v:4383.8-4383.38" + case 1'1 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4384$641_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4386.5-4389.8" + switch $eq$ls180.v:4386$642_Y + attribute \src "ls180.v:4386.9-4386.40" + case 1'1 + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4395.4-4399.7" + switch $and$ls180.v:4395$643_Y + attribute \src "ls180.v:4395.8-4395.69" + case 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01 + attribute \src "ls180.v:4397.8-4397.12" + case + assign $0\main_sdphy_cmdw_done[0:0] 1'1 + end + end + sync always + update \main_sdphy_cmdw_pads_out_payload_clk $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] + update \main_sdphy_cmdw_pads_out_payload_cmd_o $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + update \main_sdphy_cmdw_pads_out_payload_cmd_oe $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + update \main_sdphy_cmdw_sink_ready $0\main_sdphy_cmdw_sink_ready[0:0] + update \main_sdphy_cmdw_done $0\main_sdphy_cmdw_done[0:0] + update \builder_sdphy_sdphycmdw_next_state $0\builder_sdphy_sdphycmdw_next_state[1:0] + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + end + attribute \src "ls180.v:442.5-442.59" + process $proc$ls180.v:442$2919 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:4436.1-4529.4" + process $proc$ls180.v:4436$652 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 + assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 + assign $0\main_sdphy_cmdr_source_last[0:0] 1'0 + assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state + attribute \src "ls180.v:4454.2-4528.9" + switch \builder_sdphy_sdphycmdr_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4462$653_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4459.4-4461.7" + switch \main_sdphy_cmdr_cmdr_source_source_valid0 + attribute \src "ls180.v:4459.8-4459.49" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:4464.4-4467.7" + switch $eq$ls180.v:4464$654_Y + attribute \src "ls180.v:4464.8-4464.41" + case 1'1 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdr_source_valid[0:0] \main_sdphy_cmdr_cmdr_source_source_valid0 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4473$656_Y + assign $0\main_sdphy_cmdr_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_source_source_payload_data0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4490$659_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4475.4-4489.7" + switch $and$ls180.v:4475$657_Y + attribute \src "ls180.v:4475.8-4475.69" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'1 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4477$658_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4479.5-4488.8" + switch \main_sdphy_cmdr_source_last + attribute \src "ls180.v:4479.9-4479.36" + case 1'1 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 + attribute \src "ls180.v:4481.6-4487.9" + switch \main_sdphy_cmdr_sink_last + attribute \src "ls180.v:4481.10-4481.35" + case 1'1 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011 + attribute \src "ls180.v:4485.10-4485.14" + case + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + end + case + end + case + end + attribute \src "ls180.v:4492.4-4495.7" + switch $eq$ls180.v:4492$660_Y + attribute \src "ls180.v:4492.8-4492.41" + case 1'1 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'1 + attribute \src "ls180.v:4501.4-4507.7" + switch \main_sdphy_cmdr_pads_out_ready + attribute \src "ls180.v:4501.8-4501.38" + case 1'1 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4502$661_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4504.5-4506.8" + switch $eq$ls180.v:4504$662_Y + attribute \src "ls180.v:4504.9-4504.40" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_cmdr_source_valid[0:0] 1'1 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'001 + assign $0\main_sdphy_cmdr_source_last[0:0] 1'1 + attribute \src "ls180.v:4513.4-4515.7" + switch $and$ls180.v:4513$663_Y + attribute \src "ls180.v:4513.8-4513.69" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4522.4-4526.7" + switch $and$ls180.v:4522$665_Y + attribute \src "ls180.v:4522.8-4522.94" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'001 + case + end + end + sync always + update \main_sdphy_cmdr_pads_out_payload_clk $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] + update \main_sdphy_cmdr_pads_out_payload_cmd_o $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + update \main_sdphy_cmdr_pads_out_payload_cmd_oe $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + update \main_sdphy_cmdr_sink_ready $0\main_sdphy_cmdr_sink_ready[0:0] + update \main_sdphy_cmdr_source_valid $0\main_sdphy_cmdr_source_valid[0:0] + update \main_sdphy_cmdr_source_last $0\main_sdphy_cmdr_source_last[0:0] + update \main_sdphy_cmdr_source_payload_data $0\main_sdphy_cmdr_source_payload_data[7:0] + update \main_sdphy_cmdr_source_payload_status $0\main_sdphy_cmdr_source_payload_status[2:0] + update \main_sdphy_cmdr_cmdr_source_source_ready0 $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + update \builder_sdphy_sdphycmdr_next_state $0\builder_sdphy_sdphycmdr_next_state[2:0] + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + end + attribute \src "ls180.v:444.5-444.59" + process $proc$ls180.v:444$2920 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:445.5-445.58" + process $proc$ls180.v:445$2921 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:446.5-446.64" + process $proc$ls180.v:446$2922 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:447.12-447.74" + process $proc$ls180.v:447$2923 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:448.12-448.47" + process $proc$ls180.v:448$2924 + assign { } { } + assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] + end + attribute \src "ls180.v:449.5-449.46" + process $proc$ls180.v:449$2925 + assign { } { } + assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] + end + attribute \src "ls180.v:451.5-451.44" + process $proc$ls180.v:451$2926 + assign { } { } + assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] + end + attribute \src "ls180.v:452.5-452.45" + process $proc$ls180.v:452$2927 + assign { } { } + assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] + end + attribute \src "ls180.v:453.5-453.54" + process $proc$ls180.v:453$2928 + assign { } { } + assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:455.32-455.76" + process $proc$ls180.v:455$2929 + assign { } { } + assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] + end + attribute \src "ls180.v:456.11-456.55" + process $proc$ls180.v:456$2930 + assign { } { } + assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] + end + attribute \src "ls180.v:4563.1-4590.4" + process $proc$ls180.v:4563$673 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_dataw_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + assign $0\main_sdphy_dataw_error[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state + attribute \src "ls180.v:4571.2-4589.9" + switch \builder_sdphy_sdphycrcr_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 + assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'1 + attribute \src "ls180.v:4576.4-4580.7" + switch \main_sdphy_dataw_crcr_source_source_valid0 + attribute \src "ls180.v:4576.8-4576.50" + case 1'1 + assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4577$674_Y + assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4578$675_Y + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 + case + end + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:4583.4-4587.7" + switch \main_sdphy_dataw_start + attribute \src "ls180.v:4583.8-4583.30" + case 1'1 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'1 + case + end + end + sync always + update \main_sdphy_dataw_valid $0\main_sdphy_dataw_valid[0:0] + update \main_sdphy_dataw_error $0\main_sdphy_dataw_error[0:0] + update \main_sdphy_dataw_crcr_source_source_ready0 $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] + update \builder_sdphy_sdphycrcr_next_state $0\builder_sdphy_sdphycrcr_next_state[0:0] + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + end + attribute \src "ls180.v:458.32-458.75" + process $proc$ls180.v:458$2931 + assign { } { } + assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:4591.1-4663.4" + process $proc$ls180.v:4591$676 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_dataw_stop[0:0] 1'0 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0 + assign $0\main_sdphy_dataw_start[0:0] 1'0 + assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state + attribute \src "ls180.v:4602.2-4662.9" + switch \builder_sdphy_fsm_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 + attribute \src "ls180.v:4607.4-4609.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4607.8-4607.39" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4612$677_Y + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 + attribute \src "ls180.v:4615.4-4622.11" + switch \main_sdphy_dataw_count + attribute \src "ls180.v:0.0-0.0" + case 8'00000000 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [7:4] + attribute \src "ls180.v:0.0-0.0" + case 8'00000001 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [3:0] + case + end + attribute \src "ls180.v:4623.4-4635.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4623.8-4623.39" + case 1'1 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4624$678_Y + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4626.5-4634.8" + switch $eq$ls180.v:4626$679_Y + attribute \src "ls180.v:4626.9-4626.41" + case 1'1 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4629.6-4633.9" + switch \main_sdphy_dataw_sink_last + attribute \src "ls180.v:4629.10-4629.36" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'011 + attribute \src "ls180.v:4631.10-4631.14" + case + assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'1111 + attribute \src "ls180.v:4641.4-4644.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4641.8-4641.39" + case 1'1 + assign $0\main_sdphy_dataw_start[0:0] 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + attribute \src "ls180.v:4648.4-4653.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4648.8-4648.39" + case 1'1 + attribute \src "ls180.v:4649.5-4652.8" + switch \main_sdphy_dataw_pads_in_payload_data_i [0] + attribute \src "ls180.v:4649.9-4649.51" + case 1'1 + assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4658.4-4660.7" + switch $and$ls180.v:4658$680_Y + attribute \src "ls180.v:4658.8-4658.71" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'001 + case + end + end + sync always + update \main_sdphy_dataw_pads_out_payload_clk $0\main_sdphy_dataw_pads_out_payload_clk[0:0] + update \main_sdphy_dataw_pads_out_payload_data_o $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] + update \main_sdphy_dataw_pads_out_payload_data_oe $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + update \main_sdphy_dataw_sink_ready $0\main_sdphy_dataw_sink_ready[0:0] + update \main_sdphy_dataw_stop $0\main_sdphy_dataw_stop[0:0] + update \main_sdphy_dataw_start $0\main_sdphy_dataw_start[0:0] + update \builder_sdphy_fsm_next_state $0\builder_sdphy_fsm_next_state[2:0] + update \main_sdphy_dataw_count_sdphy_fsm_next_value $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:460.32-460.76" + process $proc$ls180.v:460$2932 + assign { } { } + assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:466.5-466.51" + process $proc$ls180.v:466$2933 + assign { } { } + assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] + end + attribute \src "ls180.v:467.5-467.51" + process $proc$ls180.v:467$2934 + assign { } { } + assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + end + attribute \src "ls180.v:469.5-469.47" + process $proc$ls180.v:469$2935 + assign { } { } + assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] + end + attribute \src "ls180.v:4697.1-4798.4" + process $proc$ls180.v:4697$688 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 + assign $0\main_sdphy_datar_source_valid[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 + assign $0\main_sdphy_datar_source_last[0:0] 1'0 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_datar_stop[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state + attribute \src "ls180.v:4714.2-4797.9" + switch \builder_sdphy_sdphydatar_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 + assign { } { } + assign { } { } + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4724$690_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4721.4-4723.7" + switch \main_sdphy_datar_datar_source_source_valid0 + attribute \src "ls180.v:4721.8-4721.51" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:4726.4-4729.7" + switch $eq$ls180.v:4726$691_Y + attribute \src "ls180.v:4726.8-4726.42" + case 1'1 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_datar_source_valid[0:0] \main_sdphy_datar_datar_source_source_valid0 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4735$694_Y + assign $0\main_sdphy_datar_source_payload_data[7:0] \main_sdphy_datar_datar_source_source_payload_data0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4756$696_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4737.4-4755.7" + switch \main_sdphy_datar_source_valid + attribute \src "ls180.v:4737.8-4737.37" + case 1'1 + attribute \src "ls180.v:4738.5-4754.8" + switch \main_sdphy_datar_source_ready + attribute \src "ls180.v:4738.9-4738.38" + case 1'1 + assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4740$695_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4742.6-4751.9" + switch \main_sdphy_datar_source_last + attribute \src "ls180.v:4742.10-4742.38" + case 1'1 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 + attribute \src "ls180.v:4744.7-4750.10" + switch \main_sdphy_datar_sink_last + attribute \src "ls180.v:4744.11-4744.37" + case 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011 + attribute \src "ls180.v:4748.11-4748.15" + case + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + end + case + end + attribute \src "ls180.v:4752.9-4752.13" + case + assign $0\main_sdphy_datar_stop[0:0] 1'1 + end + case + end + attribute \src "ls180.v:4758.4-4761.7" + switch $eq$ls180.v:4758$697_Y + attribute \src "ls180.v:4758.8-4758.42" + case 1'1 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + attribute \src "ls180.v:4765.4-4771.7" + switch \main_sdphy_datar_pads_out_ready + attribute \src "ls180.v:4765.8-4765.39" + case 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4766$698_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4768.5-4770.8" + switch $eq$ls180.v:4768$699_Y + attribute \src "ls180.v:4768.9-4768.42" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_datar_source_valid[0:0] 1'1 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'001 + assign $0\main_sdphy_datar_source_last[0:0] 1'1 + attribute \src "ls180.v:4777.4-4779.7" + switch $and$ls180.v:4777$700_Y + attribute \src "ls180.v:4777.8-4777.71" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4784.4-4795.7" + switch $and$ls180.v:4784$701_Y + attribute \src "ls180.v:4784.8-4784.71" + case 1'1 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + attribute \src "ls180.v:4786.5-4794.8" + switch \main_sdphy_datar_pads_out_ready + attribute \src "ls180.v:4786.9-4786.40" + case 1'1 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'1 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'001 + case + end + case + end + end + sync always + update \main_sdphy_datar_pads_out_payload_clk $0\main_sdphy_datar_pads_out_payload_clk[0:0] + update \main_sdphy_datar_sink_ready $0\main_sdphy_datar_sink_ready[0:0] + update \main_sdphy_datar_source_valid $0\main_sdphy_datar_source_valid[0:0] + update \main_sdphy_datar_source_last $0\main_sdphy_datar_source_last[0:0] + update \main_sdphy_datar_source_payload_data $0\main_sdphy_datar_source_payload_data[7:0] + update \main_sdphy_datar_source_payload_status $0\main_sdphy_datar_source_payload_status[2:0] + update \main_sdphy_datar_stop $0\main_sdphy_datar_stop[0:0] + update \main_sdphy_datar_datar_source_source_ready0 $0\main_sdphy_datar_datar_source_source_ready0[0:0] + update \builder_sdphy_sdphydatar_next_state $0\builder_sdphy_sdphydatar_next_state[2:0] + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + end + attribute \src "ls180.v:470.5-470.45" + process $proc$ls180.v:470$2936 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] + end + attribute \src "ls180.v:471.5-471.45" + process $proc$ls180.v:471$2937 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] + end + attribute \src "ls180.v:472.12-472.57" + process $proc$ls180.v:472$2938 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] + end + attribute \src "ls180.v:474.5-474.51" + process $proc$ls180.v:474$2939 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:475.5-475.51" + process $proc$ls180.v:475$2940 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:476.5-476.50" + process $proc$ls180.v:476$2941 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + end + attribute \src "ls180.v:477.5-477.54" + process $proc$ls180.v:477$2942 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:478.5-478.55" + process $proc$ls180.v:478$2943 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:479.5-479.56" + process $proc$ls180.v:479$2944 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:480.5-480.50" + process $proc$ls180.v:480$2945 + assign { } { } + assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] + end + attribute \src "ls180.v:483.5-483.67" + process $proc$ls180.v:483$2946 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:484.5-484.66" + process $proc$ls180.v:484$2947 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:4856.1-4863.4" + process $proc$ls180.v:4856$823 + assign { } { } + assign $0\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 + attribute \src "ls180.v:4858.2-4862.5" + switch \main_sdcore_crc7_inserter_enable + attribute \src "ls180.v:4858.6-4858.38" + case 1'1 + assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg40 + attribute \src "ls180.v:4860.6-4860.10" + case + assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg0 + end + sync always + update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0] + end + attribute \src "ls180.v:4878.1-4885.4" + process $proc$ls180.v:4878$846 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:4880.2-4884.5" + switch \main_sdcore_crc16_inserter_crc0_enable + attribute \src "ls180.v:4880.6-4880.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 + attribute \src "ls180.v:4882.6-4882.10" + case + assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0] + end + attribute \src "ls180.v:4888.1-4895.4" + process $proc$ls180.v:4888$857 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:4890.2-4894.5" + switch \main_sdcore_crc16_inserter_crc1_enable + attribute \src "ls180.v:4890.6-4890.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 + attribute \src "ls180.v:4892.6-4892.10" + case + assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0] + end + attribute \src "ls180.v:4898.1-4905.4" + process $proc$ls180.v:4898$868 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:4900.2-4904.5" + switch \main_sdcore_crc16_inserter_crc2_enable + attribute \src "ls180.v:4900.6-4900.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 + attribute \src "ls180.v:4902.6-4902.10" + case + assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0] + end + attribute \src "ls180.v:49.5-49.42" + process $proc$ls180.v:49$2767 + assign { } { } + assign $1\main_libresocsim_reset_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] + end + attribute \src "ls180.v:4908.1-4915.4" + process $proc$ls180.v:4908$879 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:4910.2-4914.5" + switch \main_sdcore_crc16_inserter_crc3_enable + attribute \src "ls180.v:4910.6-4910.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 + attribute \src "ls180.v:4912.6-4912.10" + case + assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0] + end + attribute \src "ls180.v:4916.1-4995.4" + process $proc$ls180.v:4916$880 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state + attribute \src "ls180.v:4933.2-4994.9" + switch \builder_sdcore_crcupstreaminserter_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'1 + attribute \src "ls180.v:4937.4-4939.7" + switch $eq$ls180.v:4937$881_Y + attribute \src "ls180.v:4937.8-4937.48" + case 1'1 + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'1 + case + end + attribute \src "ls180.v:4940.4-4965.11" + switch \main_sdcore_crc16_inserter_cnt + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [15] \main_sdcore_crc16_inserter_crctmp2 [15] \main_sdcore_crc16_inserter_crctmp1 [15] \main_sdcore_crc16_inserter_crctmp0 [15] \main_sdcore_crc16_inserter_crctmp3 [14] \main_sdcore_crc16_inserter_crctmp2 [14] \main_sdcore_crc16_inserter_crctmp1 [14] \main_sdcore_crc16_inserter_crctmp0 [14] } + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [13] \main_sdcore_crc16_inserter_crctmp2 [13] \main_sdcore_crc16_inserter_crctmp1 [13] \main_sdcore_crc16_inserter_crctmp0 [13] \main_sdcore_crc16_inserter_crctmp3 [12] \main_sdcore_crc16_inserter_crctmp2 [12] \main_sdcore_crc16_inserter_crctmp1 [12] \main_sdcore_crc16_inserter_crctmp0 [12] } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [11] \main_sdcore_crc16_inserter_crctmp2 [11] \main_sdcore_crc16_inserter_crctmp1 [11] \main_sdcore_crc16_inserter_crctmp0 [11] \main_sdcore_crc16_inserter_crctmp3 [10] \main_sdcore_crc16_inserter_crctmp2 [10] \main_sdcore_crc16_inserter_crctmp1 [10] \main_sdcore_crc16_inserter_crctmp0 [10] } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [9] \main_sdcore_crc16_inserter_crctmp2 [9] \main_sdcore_crc16_inserter_crctmp1 [9] \main_sdcore_crc16_inserter_crctmp0 [9] \main_sdcore_crc16_inserter_crctmp3 [8] \main_sdcore_crc16_inserter_crctmp2 [8] \main_sdcore_crc16_inserter_crctmp1 [8] \main_sdcore_crc16_inserter_crctmp0 [8] } + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [7] \main_sdcore_crc16_inserter_crctmp2 [7] \main_sdcore_crc16_inserter_crctmp1 [7] \main_sdcore_crc16_inserter_crctmp0 [7] \main_sdcore_crc16_inserter_crctmp3 [6] \main_sdcore_crc16_inserter_crctmp2 [6] \main_sdcore_crc16_inserter_crctmp1 [6] \main_sdcore_crc16_inserter_crctmp0 [6] } + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [5] \main_sdcore_crc16_inserter_crctmp2 [5] \main_sdcore_crc16_inserter_crctmp1 [5] \main_sdcore_crc16_inserter_crctmp0 [5] \main_sdcore_crc16_inserter_crctmp3 [4] \main_sdcore_crc16_inserter_crctmp2 [4] \main_sdcore_crc16_inserter_crctmp1 [4] \main_sdcore_crc16_inserter_crctmp0 [4] } + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [3] \main_sdcore_crc16_inserter_crctmp2 [3] \main_sdcore_crc16_inserter_crctmp1 [3] \main_sdcore_crc16_inserter_crctmp0 [3] \main_sdcore_crc16_inserter_crctmp3 [2] \main_sdcore_crc16_inserter_crctmp2 [2] \main_sdcore_crc16_inserter_crctmp1 [2] \main_sdcore_crc16_inserter_crctmp0 [2] } + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [1] \main_sdcore_crc16_inserter_crctmp2 [1] \main_sdcore_crc16_inserter_crctmp1 [1] \main_sdcore_crc16_inserter_crctmp0 [1] \main_sdcore_crc16_inserter_crctmp3 [0] \main_sdcore_crc16_inserter_crctmp2 [0] \main_sdcore_crc16_inserter_crctmp1 [0] \main_sdcore_crc16_inserter_crctmp0 [0] } + case + end + attribute \src "ls180.v:4966.4-4973.7" + switch \main_sdcore_crc16_inserter_source_ready + attribute \src "ls180.v:4966.8-4966.47" + case 1'1 + attribute \src "ls180.v:4967.5-4972.8" + switch $eq$ls180.v:4967$882_Y + attribute \src "ls180.v:4967.9-4967.49" + case 1'1 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 + attribute \src "ls180.v:4969.9-4969.13" + case + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:4970$883_Y + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] \main_sdcore_crc16_inserter_sink_payload_data + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] \main_sdcore_crc16_inserter_sink_valid + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] \main_sdcore_crc16_inserter_source_ready + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] \main_sdcore_crc16_inserter_crc0_crc + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] \main_sdcore_crc16_inserter_crc1_crc + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] \main_sdcore_crc16_inserter_crc2_crc + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \main_sdcore_crc16_inserter_crc3_crc + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:4988.4-4992.7" + switch $and$ls180.v:4988$885_Y + attribute \src "ls180.v:4988.8-4988.128" + case 1'1 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 + case + end + end + sync always + update \main_sdcore_crc16_inserter_sink_ready $0\main_sdcore_crc16_inserter_sink_ready[0:0] + update \main_sdcore_crc16_inserter_source_valid $0\main_sdcore_crc16_inserter_source_valid[0:0] + update \main_sdcore_crc16_inserter_source_last $0\main_sdcore_crc16_inserter_source_last[0:0] + update \main_sdcore_crc16_inserter_source_payload_data $0\main_sdcore_crc16_inserter_source_payload_data[7:0] + update \builder_sdcore_crcupstreaminserter_next_state $0\builder_sdcore_crcupstreaminserter_next_state[0:0] + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + end + attribute \src "ls180.v:499.11-499.68" + process $proc$ls180.v:499$2948 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:4996.1-5001.4" + process $proc$ls180.v:4996$886 + assign { } { } + assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0 + attribute \src "ls180.v:4998.2-5000.5" + switch $and$ls180.v:4998$893_Y + attribute \src "ls180.v:4998.6-4998.301" + case 1'1 + assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1 + case + end + sync always + update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0] + end + attribute \src "ls180.v:50.5-50.37" + process $proc$ls180.v:50$2768 + assign { } { } + assign $1\main_libresocsim_reset_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] + end + attribute \src "ls180.v:500.5-500.64" + process $proc$ls180.v:500$2949 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:5004.1-5011.4" + process $proc$ls180.v:5004$895 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + attribute \src "ls180.v:5006.2-5010.5" + switch $eq$ls180.v:5006$896_Y + attribute \src "ls180.v:5006.6-5006.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'1 + attribute \src "ls180.v:5008.6-5008.10" + case + assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc0_clr $0\main_sdcore_crc16_checker_crc0_clr[0:0] + end + attribute \src "ls180.v:501.11-501.70" + process $proc$ls180.v:501$2950 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:5014.1-5021.4" + process $proc$ls180.v:5014$898 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + attribute \src "ls180.v:5016.2-5020.5" + switch $eq$ls180.v:5016$899_Y + attribute \src "ls180.v:5016.6-5016.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'1 + attribute \src "ls180.v:5018.6-5018.10" + case + assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc1_clr $0\main_sdcore_crc16_checker_crc1_clr[0:0] + end + attribute \src "ls180.v:502.11-502.70" + process $proc$ls180.v:502$2951 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:5024.1-5031.4" + process $proc$ls180.v:5024$901 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + attribute \src "ls180.v:5026.2-5030.5" + switch $eq$ls180.v:5026$902_Y + attribute \src "ls180.v:5026.6-5026.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'1 + attribute \src "ls180.v:5028.6-5028.10" + case + assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0] + end + attribute \src "ls180.v:503.11-503.73" + process $proc$ls180.v:503$2952 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:5034.1-5041.4" + process $proc$ls180.v:5034$904 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + attribute \src "ls180.v:5036.2-5040.5" + switch $eq$ls180.v:5036$905_Y + attribute \src "ls180.v:5036.6-5036.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'1 + attribute \src "ls180.v:5038.6-5038.10" + case + assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0] + end + attribute \src "ls180.v:5043.1-5048.4" + process $proc$ls180.v:5043$906 + assign { } { } + assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'0 + attribute \src "ls180.v:5045.2-5047.5" + switch $and$ls180.v:5045$908_Y + attribute \src "ls180.v:5045.6-5045.85" + case 1'1 + assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'1 + case + end + sync always + update \main_sdcore_crc16_checker_source_valid $0\main_sdcore_crc16_checker_source_valid[0:0] + end + attribute \src "ls180.v:5049.1-5056.4" + process $proc$ls180.v:5049$909 + assign { } { } + assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 + attribute \src "ls180.v:5051.2-5055.5" + switch $lt$ls180.v:5051$910_Y + attribute \src "ls180.v:5051.6-5051.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'1 + attribute \src "ls180.v:5053.6-5053.10" + case + assign $0\main_sdcore_crc16_checker_sink_ready[0:0] \main_sdcore_crc16_checker_source_ready + end + sync always + update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0] + end + attribute \src "ls180.v:5060.1-5067.4" + process $proc$ls180.v:5060$921 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5062.2-5066.5" + switch \main_sdcore_crc16_checker_crc0_enable + attribute \src "ls180.v:5062.6-5062.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 + attribute \src "ls180.v:5064.6-5064.10" + case + assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0] + end + attribute \src "ls180.v:5070.1-5077.4" + process $proc$ls180.v:5070$932 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5072.2-5076.5" + switch \main_sdcore_crc16_checker_crc1_enable + attribute \src "ls180.v:5072.6-5072.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 + attribute \src "ls180.v:5074.6-5074.10" + case + assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0] + end + attribute \src "ls180.v:5080.1-5087.4" + process $proc$ls180.v:5080$943 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5082.2-5086.5" + switch \main_sdcore_crc16_checker_crc2_enable + attribute \src "ls180.v:5082.6-5082.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 + attribute \src "ls180.v:5084.6-5084.10" + case + assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0] + end + attribute \src "ls180.v:5090.1-5097.4" + process $proc$ls180.v:5090$954 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5092.2-5096.5" + switch \main_sdcore_crc16_checker_crc3_enable + attribute \src "ls180.v:5092.6-5092.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 + attribute \src "ls180.v:5094.6-5094.10" + case + assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0] + end + attribute \src "ls180.v:5098.1-5288.4" + process $proc$ls180.v:5098$955 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_first[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_last[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 + assign $0\main_sdphy_datar_sink_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_first[0:0] 1'0 + assign $0\main_sdphy_datar_sink_last[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_last[0:0] 1'0 + assign $0\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 + assign $0\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0 + assign $0\main_sdphy_datar_source_ready[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 + assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state + attribute \src "ls180.v:5139.2-5287.9" + switch \builder_sdcore_fsm_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'1 + attribute \src "ls180.v:5142.4-5162.11" + switch \main_sdcore_cmd_count + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { 2'01 \main_sdcore_cmd_command_storage [13:8] } + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [31:24] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [23:16] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [15:8] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [7:0] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { \main_sdcore_crc7_inserter_crc 1'1 } + assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5160$956_Y + case + end + attribute \src "ls180.v:5163.4-5175.7" + switch $and$ls180.v:5163$957_Y + attribute \src "ls180.v:5163.8-5163.65" + case 1'1 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5164$958_Y + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 + attribute \src "ls180.v:5166.5-5174.8" + switch $eq$ls180.v:5166$959_Y + attribute \src "ls180.v:5166.9-5166.40" + case 1'1 + attribute \src "ls180.v:5167.6-5173.9" + switch $eq$ls180.v:5167$960_Y + attribute \src "ls180.v:5167.10-5167.40" + case 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "ls180.v:5171.10-5171.14" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'010 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'1 + assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5179$961_Y + assign $0\main_sdphy_cmdr_source_ready[0:0] 1'1 + attribute \src "ls180.v:5180.4-5184.7" + switch $eq$ls180.v:5180$962_Y + attribute \src "ls180.v:5180.8-5180.38" + case 1'1 + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00010001 + attribute \src "ls180.v:5182.8-5182.12" + case + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000110 + end + attribute \src "ls180.v:5186.4-5207.7" + switch \main_sdphy_cmdr_source_valid + attribute \src "ls180.v:5186.8-5186.36" + case 1'1 + attribute \src "ls180.v:5187.5-5206.8" + switch $eq$ls180.v:5187$963_Y + attribute \src "ls180.v:5187.9-5187.56" + case 1'1 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "ls180.v:5191.9-5191.13" + case + attribute \src "ls180.v:5192.6-5205.9" + switch \main_sdphy_cmdr_source_last + attribute \src "ls180.v:5192.10-5192.37" + case 1'1 + attribute \src "ls180.v:5193.7-5201.10" + switch $eq$ls180.v:5193$964_Y + attribute \src "ls180.v:5193.11-5193.42" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'011 + attribute \src "ls180.v:5195.11-5195.15" + case + attribute \src "ls180.v:5196.8-5200.11" + switch $eq$ls180.v:5196$965_Y + attribute \src "ls180.v:5196.12-5196.43" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 + attribute \src "ls180.v:5198.12-5198.16" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + end + end + attribute \src "ls180.v:5202.10-5202.14" + case + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \main_sdcore_cmd_response_status [119:0] \main_sdphy_cmdr_source_payload_data } + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1 + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_dataw_sink_valid[0:0] \main_sdcore_crc16_inserter_source_valid + assign $0\main_sdcore_crc16_inserter_source_ready[0:0] \main_sdphy_dataw_sink_ready + assign $0\main_sdphy_dataw_sink_first[0:0] \main_sdcore_crc16_inserter_source_first + assign $0\main_sdphy_dataw_sink_last[0:0] \main_sdcore_crc16_inserter_source_last + assign $0\main_sdphy_dataw_sink_payload_data[7:0] \main_sdcore_crc16_inserter_source_payload_data + assign $0\main_sdphy_datar_source_ready[0:0] 1'1 + attribute \src "ls180.v:5215.4-5221.7" + switch $and$ls180.v:5215$967_Y + attribute \src "ls180.v:5215.8-5215.98" + case 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5216$968_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5218.5-5220.8" + switch $eq$ls180.v:5218$970_Y + attribute \src "ls180.v:5218.9-5218.77" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:5223.4-5228.7" + switch \main_sdphy_datar_source_valid + attribute \src "ls180.v:5223.8-5223.37" + case 1'1 + attribute \src "ls180.v:5224.5-5227.8" + switch $ne$ls180.v:5224$971_Y + attribute \src "ls180.v:5224.9-5224.57" + case 1'1 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_datar_sink_valid[0:0] 1'1 + assign $0\main_sdphy_datar_sink_payload_block_length[9:0] \main_sdcore_block_length_storage + assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5233$973_Y + attribute \src "ls180.v:5234.4-5260.7" + switch \main_sdphy_datar_source_valid + attribute \src "ls180.v:5234.8-5234.37" + case 1'1 + attribute \src "ls180.v:5235.5-5259.8" + switch $eq$ls180.v:5235$974_Y + attribute \src "ls180.v:5235.9-5235.57" + case 1'1 + assign $0\main_sdcore_crc16_checker_sink_valid[0:0] \main_sdphy_datar_source_valid + assign $0\main_sdphy_datar_source_ready[0:0] \main_sdcore_crc16_checker_sink_ready + assign $0\main_sdcore_crc16_checker_sink_first[0:0] \main_sdphy_datar_source_first + assign $0\main_sdcore_crc16_checker_sink_last[0:0] \main_sdphy_datar_source_last + assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] \main_sdphy_datar_source_payload_data + attribute \src "ls180.v:5241.6-5249.9" + switch $and$ls180.v:5241$975_Y + attribute \src "ls180.v:5241.10-5241.72" + case 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5242$976_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5244.7-5248.10" + switch $eq$ls180.v:5244$978_Y + attribute \src "ls180.v:5244.11-5244.79" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "ls180.v:5246.11-5246.15" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 + end + case + end + attribute \src "ls180.v:5250.9-5250.13" + case + attribute \src "ls180.v:5251.6-5258.9" + switch $eq$ls180.v:5251$979_Y + attribute \src "ls180.v:5251.10-5251.58" + case 1'1 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + assign $0\main_sdphy_datar_source_ready[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + case + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'1 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5271.4-5285.7" + switch \main_sdcore_cmd_send_re + attribute \src "ls180.v:5271.8-5271.31" + case 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'1 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'001 + case + end + end + sync always + update \main_sdphy_cmdw_sink_valid $0\main_sdphy_cmdw_sink_valid[0:0] + update \main_sdphy_cmdw_sink_last $0\main_sdphy_cmdw_sink_last[0:0] + update \main_sdphy_cmdw_sink_payload_data $0\main_sdphy_cmdw_sink_payload_data[7:0] + update \main_sdphy_cmdr_sink_valid $0\main_sdphy_cmdr_sink_valid[0:0] + update \main_sdphy_cmdr_sink_last $0\main_sdphy_cmdr_sink_last[0:0] + update \main_sdphy_cmdr_sink_payload_length $0\main_sdphy_cmdr_sink_payload_length[7:0] + update \main_sdphy_cmdr_source_ready $0\main_sdphy_cmdr_source_ready[0:0] + update \main_sdphy_dataw_sink_valid $0\main_sdphy_dataw_sink_valid[0:0] + update \main_sdphy_dataw_sink_first $0\main_sdphy_dataw_sink_first[0:0] + update \main_sdphy_dataw_sink_last $0\main_sdphy_dataw_sink_last[0:0] + update \main_sdphy_dataw_sink_payload_data $0\main_sdphy_dataw_sink_payload_data[7:0] + update \main_sdphy_datar_sink_valid $0\main_sdphy_datar_sink_valid[0:0] + update \main_sdphy_datar_sink_last $0\main_sdphy_datar_sink_last[0:0] + update \main_sdphy_datar_sink_payload_block_length $0\main_sdphy_datar_sink_payload_block_length[9:0] + update \main_sdphy_datar_source_ready $0\main_sdphy_datar_source_ready[0:0] + update \main_sdcore_crc16_inserter_source_ready $0\main_sdcore_crc16_inserter_source_ready[0:0] + update \main_sdcore_crc16_checker_sink_valid $0\main_sdcore_crc16_checker_sink_valid[0:0] + update \main_sdcore_crc16_checker_sink_first $0\main_sdcore_crc16_checker_sink_first[0:0] + update \main_sdcore_crc16_checker_sink_last $0\main_sdcore_crc16_checker_sink_last[0:0] + update \main_sdcore_crc16_checker_sink_payload_data $0\main_sdcore_crc16_checker_sink_payload_data[7:0] + update \builder_sdcore_fsm_next_state $0\builder_sdcore_fsm_next_state[2:0] + update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + update \main_sdcore_data_done_sdcore_fsm_next_value1 $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + update \main_sdcore_data_count_sdcore_fsm_next_value3 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + update \main_sdcore_data_error_sdcore_fsm_next_value6 $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + end + attribute \src "ls180.v:51.12-51.60" + process $proc$ls180.v:51$2769 + assign { } { } + assign $1\main_libresocsim_scratch_storage[31:0] 305419896 + sync always + sync init + update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] + end + attribute \src "ls180.v:52.5-52.39" + process $proc$ls180.v:52$2770 + assign { } { } + assign $1\main_libresocsim_scratch_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] + end + attribute \src "ls180.v:524.5-524.59" + process $proc$ls180.v:524$2953 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:526.5-526.59" + process $proc$ls180.v:526$2954 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:527.5-527.58" + process $proc$ls180.v:527$2955 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:528.5-528.64" + process $proc$ls180.v:528$2956 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:529.12-529.74" + process $proc$ls180.v:529$2957 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:530.12-530.47" + process $proc$ls180.v:530$2958 + assign { } { } + assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] + end + attribute \src "ls180.v:531.5-531.46" + process $proc$ls180.v:531$2959 + assign { } { } + assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] + end + attribute \src "ls180.v:5316.1-5323.4" + process $proc$ls180.v:5316$980 + assign { } { } + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 + attribute \src "ls180.v:5318.2-5322.5" + switch \main_sdblock2mem_fifo_replace + attribute \src "ls180.v:5318.6-5318.35" + case 1'1 + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5319$981_Y + attribute \src "ls180.v:5320.6-5320.10" + case + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce + end + sync always + update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:533.5-533.44" + process $proc$ls180.v:533$2960 + assign { } { } + assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] + end + attribute \src "ls180.v:534.5-534.45" + process $proc$ls180.v:534$2961 + assign { } { } + assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] + end + attribute \src "ls180.v:5349.1-5388.4" + process $proc$ls180.v:5349$991 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0 + assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 + assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state + attribute \src "ls180.v:5359.2-5387.9" + switch \builder_sdblock2memdma_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdblock2mem_sink_sink_valid1[0:0] \main_sdblock2mem_wishbonedmawriter_sink_valid + assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5363$992_Y + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \main_sdblock2mem_sink_sink_ready1 + attribute \src "ls180.v:5365.4-5376.7" + switch $and$ls180.v:5365$993_Y + attribute \src "ls180.v:5365.8-5365.103" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5366$994_Y + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5368.5-5375.8" + switch $eq$ls180.v:5368$996_Y + attribute \src "ls180.v:5368.9-5368.106" + case 1'1 + attribute \src "ls180.v:5369.6-5374.9" + switch \main_sdblock2mem_wishbonedmawriter_loop_storage + attribute \src "ls180.v:5369.10-5369.57" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5372.10-5372.14" + case + assign $0\builder_sdblock2memdma_next_state[1:0] 2'10 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'1 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + assign $0\builder_sdblock2memdma_next_state[1:0] 2'01 + end + sync always + update \main_sdblock2mem_sink_sink_valid1 $0\main_sdblock2mem_sink_sink_valid1[0:0] + update \main_sdblock2mem_sink_sink_payload_address $0\main_sdblock2mem_sink_sink_payload_address[31:0] + update \main_sdblock2mem_sink_sink_payload_data1 $0\main_sdblock2mem_sink_sink_payload_data1[31:0] + update \main_sdblock2mem_wishbonedmawriter_sink_ready $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + update \main_sdblock2mem_wishbonedmawriter_status $0\main_sdblock2mem_wishbonedmawriter_status[0:0] + update \builder_sdblock2memdma_next_state $0\builder_sdblock2memdma_next_state[1:0] + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:170" - cell $add $add$issuer_ls180.v:177419$12457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 65 - connect \A \dec2_cur_pc - connect \B 3'100 - connect \Y $add$issuer_ls180.v:177419$12457_Y + attribute \src "ls180.v:535.5-535.54" + process $proc$ls180.v:535$2962 + assign { } { } + assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $and $and$issuer_ls180.v:177403$12439 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$95 - connect \B \$97 - connect \Y $and$issuer_ls180.v:177403$12439_Y + attribute \src "ls180.v:537.32-537.76" + process $proc$ls180.v:537$2963 + assign { } { } + assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:177418$12456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_cu_st__rel_o - connect \B \$16 - connect \Y $and$issuer_ls180.v:177418$12456_Y + attribute \src "ls180.v:538.11-538.55" + process $proc$ls180.v:538$2964 + assign { } { } + assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $and $and$issuer_ls180.v:177427$12465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$33 - connect \B \$35 - connect \Y $and$issuer_ls180.v:177427$12465_Y + attribute \src "ls180.v:540.32-540.75" + process $proc$ls180.v:540$2965 + assign { } { } + assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" - cell $and $and$issuer_ls180.v:177428$12466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \core_state_nia_wen - connect \B 1'1 - connect \Y $and$issuer_ls180.v:177428$12466_Y + attribute \src "ls180.v:5408.1-5445.4" + process $proc$ls180.v:5408$998 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 + assign $0\main_interface1_bus_adr[31:0] 0 + assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 + assign { } { } + assign $0\main_interface1_bus_sel[3:0] 4'0000 + assign $0\main_interface1_bus_cyc[0:0] 1'0 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 + assign $0\main_interface1_bus_stb[0:0] 1'0 + assign $0\main_interface1_bus_we[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_payload_data[31:0] 0 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state + attribute \src "ls180.v:5422.2-5444.9" + switch \builder_sdmem2blockdma_fsm_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdmem2block_dma_source_valid[0:0] 1'1 + assign $0\main_sdmem2block_dma_source_last[0:0] \main_sdmem2block_dma_sink_last + assign $0\main_sdmem2block_dma_source_payload_data[31:0] \main_sdmem2block_dma_data + attribute \src "ls180.v:5427.4-5430.7" + switch \main_sdmem2block_dma_source_ready + attribute \src "ls180.v:5427.8-5427.41" + case 1'1 + assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'1 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_interface1_bus_stb[0:0] \main_sdmem2block_dma_sink_valid + assign $0\main_interface1_bus_cyc[0:0] \main_sdmem2block_dma_sink_valid + assign $0\main_interface1_bus_we[0:0] 1'0 + assign $0\main_interface1_bus_sel[3:0] 4'1111 + assign $0\main_interface1_bus_adr[31:0] \main_sdmem2block_dma_sink_payload_address + attribute \src "ls180.v:5438.4-5442.7" + switch $and$ls180.v:5438$999_Y + attribute \src "ls180.v:5438.8-5438.59" + case 1'1 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] } + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'1 + case + end + end + sync always + update \main_interface1_bus_adr $0\main_interface1_bus_adr[31:0] + update \main_interface1_bus_sel $0\main_interface1_bus_sel[3:0] + update \main_interface1_bus_cyc $0\main_interface1_bus_cyc[0:0] + update \main_interface1_bus_stb $0\main_interface1_bus_stb[0:0] + update \main_interface1_bus_we $0\main_interface1_bus_we[0:0] + update \main_sdmem2block_dma_sink_ready $0\main_sdmem2block_dma_sink_ready[0:0] + update \main_sdmem2block_dma_source_valid $0\main_sdmem2block_dma_source_valid[0:0] + update \main_sdmem2block_dma_source_last $0\main_sdmem2block_dma_source_last[0:0] + update \main_sdmem2block_dma_source_payload_data $0\main_sdmem2block_dma_source_payload_data[31:0] + update \builder_sdmem2blockdma_fsm_next_state $0\builder_sdmem2blockdma_fsm_next_state[0:0] + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:542.32-542.76" + process $proc$ls180.v:542$2966 + assign { } { } + assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:5446.1-5482.4" + process $proc$ls180.v:5446$1000 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 + assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 + assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state + attribute \src "ls180.v:5455.2-5481.9" + switch \builder_sdmem2blockdma_resetinserter_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'1 + assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5458$1002_Y + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5459$1003_Y + attribute \src "ls180.v:5460.4-5471.7" + switch \main_sdmem2block_dma_sink_ready + attribute \src "ls180.v:5460.8-5460.39" + case 1'1 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5461$1004_Y + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5463.5-5470.8" + switch \main_sdmem2block_dma_sink_last + attribute \src "ls180.v:5463.9-5463.39" + case 1'1 + attribute \src "ls180.v:5464.6-5469.9" + switch \main_sdmem2block_dma_loop_storage + attribute \src "ls180.v:5464.10-5464.43" + case 1'1 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5467.10-5467.14" + case + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdmem2block_dma_done_status[0:0] 1'1 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'01 + end + sync always + update \main_sdmem2block_dma_sink_valid $0\main_sdmem2block_dma_sink_valid[0:0] + update \main_sdmem2block_dma_sink_last $0\main_sdmem2block_dma_sink_last[0:0] + update \main_sdmem2block_dma_sink_payload_address $0\main_sdmem2block_dma_sink_payload_address[31:0] + update \main_sdmem2block_dma_done_status $0\main_sdmem2block_dma_done_status[0:0] + update \builder_sdmem2blockdma_resetinserter_next_state $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + end + attribute \src "ls180.v:548.5-548.51" + process $proc$ls180.v:548$2967 + assign { } { } + assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] + end + attribute \src "ls180.v:549.5-549.51" + process $proc$ls180.v:549$2968 + assign { } { } + assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] + end + attribute \src "ls180.v:5494.1-5510.4" + process $proc$ls180.v:5494$1010 + assign { } { } + assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 + attribute \src "ls180.v:5496.2-5509.9" + switch \main_sdmem2block_converter_mux + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [31:24] + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [23:16] + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [15:8] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [7:0] + end + sync always + update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:551.5-551.47" + process $proc$ls180.v:551$2969 + assign { } { } + assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] + end + attribute \src "ls180.v:552.5-552.45" + process $proc$ls180.v:552$2970 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] + end + attribute \src "ls180.v:5524.1-5531.4" + process $proc$ls180.v:5524$1011 + assign { } { } + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 + attribute \src "ls180.v:5526.2-5530.5" + switch \main_sdmem2block_fifo_replace + attribute \src "ls180.v:5526.6-5526.35" + case 1'1 + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5527$1012_Y + attribute \src "ls180.v:5528.6-5528.10" + case + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce + end + sync always + update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:553.5-553.45" + process $proc$ls180.v:553$2971 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] + end + attribute \src "ls180.v:554.12-554.57" + process $proc$ls180.v:554$2972 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] + end + attribute \src "ls180.v:5549.1-5597.4" + process $proc$ls180.v:5549$1022 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'0 + assign $0\libresocsim_mosi_latch[0:0] 1'0 + assign $0\libresocsim_done0[0:0] 1'0 + assign $0\libresocsim_miso_latch[0:0] 1'0 + assign $0\libresocsim_irq[0:0] 1'0 + assign $0\libresocsim_cs_enable[0:0] 1'0 + assign { } { } + assign $0\libresocsim_clk_enable[0:0] 1'0 + assign $0\libresocsim_count_spimaster1_next_value[2:0] 3'000 + assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state + attribute \src "ls180.v:5560.2-5596.9" + switch \builder_spimaster1_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\libresocsim_count_spimaster1_next_value[2:0] 3'000 + assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5564.4-5567.7" + switch \libresocsim_clk_fall + attribute \src "ls180.v:5564.8-5564.28" + case 1'1 + assign $0\libresocsim_cs_enable[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\libresocsim_clk_enable[0:0] 1'1 + assign $0\libresocsim_cs_enable[0:0] 1'1 + attribute \src "ls180.v:5572.4-5578.7" + switch \libresocsim_clk_fall + attribute \src "ls180.v:5572.8-5572.28" + case 1'1 + assign $0\libresocsim_count_spimaster1_next_value[2:0] $add$ls180.v:5573$1023_Y + assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5575.5-5577.8" + switch $eq$ls180.v:5575$1025_Y + attribute \src "ls180.v:5575.9-5575.60" + case 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'11 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\libresocsim_cs_enable[0:0] 1'1 + attribute \src "ls180.v:5582.4-5586.7" + switch \libresocsim_clk_rise + attribute \src "ls180.v:5582.8-5582.28" + case 1'1 + assign $0\libresocsim_miso_latch[0:0] 1'1 + assign $0\libresocsim_irq[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'00 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\libresocsim_done0[0:0] 1'1 + attribute \src "ls180.v:5590.4-5594.7" + switch \libresocsim_start0 + attribute \src "ls180.v:5590.8-5590.26" + case 1'1 + assign $0\libresocsim_done0[0:0] 1'0 + assign $0\libresocsim_mosi_latch[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'01 + case + end + end + sync always + update \libresocsim_done0 $0\libresocsim_done0[0:0] + update \libresocsim_irq $0\libresocsim_irq[0:0] + update \libresocsim_clk_enable $0\libresocsim_clk_enable[0:0] + update \libresocsim_cs_enable $0\libresocsim_cs_enable[0:0] + update \libresocsim_mosi_latch $0\libresocsim_mosi_latch[0:0] + update \libresocsim_miso_latch $0\libresocsim_miso_latch[0:0] + update \builder_spimaster1_next_state $0\builder_spimaster1_next_state[1:0] + update \libresocsim_count_spimaster1_next_value $0\libresocsim_count_spimaster1_next_value[2:0] + update \libresocsim_count_spimaster1_next_value_ce $0\libresocsim_count_spimaster1_next_value_ce[0:0] + end + attribute \src "ls180.v:556.5-556.51" + process $proc$ls180.v:556$2973 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:557.5-557.51" + process $proc$ls180.v:557$2974 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:558.5-558.50" + process $proc$ls180.v:558$2975 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0] + end + attribute \src "ls180.v:559.5-559.54" + process $proc$ls180.v:559$2976 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:5598.1-5634.4" + process $proc$ls180.v:5598$1026 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 + assign { } { } + assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 + assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 + assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 + assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 + assign $0\builder_next_state[1:0] \builder_state + attribute \src "ls180.v:5609.2-5633.9" + switch \builder_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 + assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 + assign $0\builder_next_state[1:0] 2'10 + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_libresocsim_wishbone_ack[0:0] 1'1 + assign $0\builder_libresocsim_wishbone_dat_r[31:0] { 24'000000000000000000000000 \builder_libresocsim_dat_r } + assign $0\builder_next_state[1:0] 2'00 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0] + assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:5625.4-5631.7" + switch $and$ls180.v:5625$1027_Y + attribute \src "ls180.v:5625.8-5625.77" + case 1'1 + assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0] + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 + assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5628$1029_Y + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 + assign $0\builder_next_state[1:0] 2'01 + case + end + end + sync always + update \builder_libresocsim_wishbone_dat_r $0\builder_libresocsim_wishbone_dat_r[31:0] + update \builder_libresocsim_wishbone_ack $0\builder_libresocsim_wishbone_ack[0:0] + update \builder_next_state $0\builder_next_state[1:0] + update \builder_libresocsim_dat_w_next_value0 $0\builder_libresocsim_dat_w_next_value0[7:0] + update \builder_libresocsim_dat_w_next_value_ce0 $0\builder_libresocsim_dat_w_next_value_ce0[0:0] + update \builder_libresocsim_adr_next_value1 $0\builder_libresocsim_adr_next_value1[13:0] + update \builder_libresocsim_adr_next_value_ce1 $0\builder_libresocsim_adr_next_value_ce1[0:0] + update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0] + update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0] + end + attribute \src "ls180.v:560.5-560.55" + process $proc$ls180.v:560$2977 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:561.5-561.56" + process $proc$ls180.v:561$2978 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:562.5-562.50" + process $proc$ls180.v:562$2979 + assign { } { } + assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] + end + attribute \src "ls180.v:565.5-565.67" + process $proc$ls180.v:565$2980 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:5659.1-5666.4" + process $proc$ls180.v:5659$1050 + assign { } { } + assign { } { } + assign $0\builder_slave_sel[4:0] [0] $eq$ls180.v:5661$1051_Y + assign $0\builder_slave_sel[4:0] [1] $eq$ls180.v:5662$1052_Y + assign $0\builder_slave_sel[4:0] [2] $eq$ls180.v:5663$1053_Y + assign $0\builder_slave_sel[4:0] [3] $eq$ls180.v:5664$1054_Y + assign $0\builder_slave_sel[4:0] [4] $eq$ls180.v:5665$1055_Y + sync always + update \builder_slave_sel $0\builder_slave_sel[4:0] + end + attribute \src "ls180.v:566.5-566.66" + process $proc$ls180.v:566$2981 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:57.12-57.47" + process $proc$ls180.v:57$2771 + assign { } { } + assign $1\main_libresocsim_bus_errors[31:0] 0 + sync always + sync init + update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] + end + attribute \src "ls180.v:5709.1-5720.4" + process $proc$ls180.v:5709$1068 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_error[0:0] 1'0 + assign $0\builder_shared_ack[0:0] $or$ls180.v:5713$1072_Y + assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5714$1081_Y + attribute \src "ls180.v:5715.2-5719.5" + switch \builder_done + attribute \src "ls180.v:5715.6-5715.18" + case 1'1 + assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111 + assign $0\builder_shared_ack[0:0] 1'1 + assign $0\builder_error[0:0] 1'1 + case + end + sync always + update \builder_shared_dat_r $0\builder_shared_dat_r[31:0] + update \builder_shared_ack $0\builder_shared_ack[0:0] + update \builder_error $0\builder_error[0:0] + end + attribute \src "ls180.v:581.11-581.68" + process $proc$ls180.v:581$2982 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:582.5-582.64" + process $proc$ls180.v:582$2983 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:583.11-583.70" + process $proc$ls180.v:583$2984 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:584.11-584.70" + process $proc$ls180.v:584$2985 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:585.11-585.73" + process $proc$ls180.v:585$2986 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:59.12-59.55" + process $proc$ls180.v:59$2772 + assign { } { } + assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 + sync always + sync init + update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] + end + attribute \src "ls180.v:606.5-606.59" + process $proc$ls180.v:606$2987 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:608.5-608.59" + process $proc$ls180.v:608$2988 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:609.5-609.58" + process $proc$ls180.v:609$2989 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:610.5-610.64" + process $proc$ls180.v:610$2990 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:611.12-611.74" + process $proc$ls180.v:611$2991 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:612.12-612.47" + process $proc$ls180.v:612$2992 + assign { } { } + assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] + end + attribute \src "ls180.v:613.5-613.46" + process $proc$ls180.v:613$2993 + assign { } { } + assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] + end + attribute \src "ls180.v:615.5-615.44" + process $proc$ls180.v:615$2994 + assign { } { } + assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] + end + attribute \src "ls180.v:616.5-616.45" + process $proc$ls180.v:616$2995 + assign { } { } + assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] + end + attribute \src "ls180.v:617.5-617.54" + process $proc$ls180.v:617$2996 + assign { } { } + assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:619.32-619.76" + process $proc$ls180.v:619$2997 + assign { } { } + assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] + end + attribute \src "ls180.v:620.11-620.55" + process $proc$ls180.v:620$2998 + assign { } { } + assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] + end + attribute \src "ls180.v:622.32-622.75" + process $proc$ls180.v:622$2999 + assign { } { } + assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:6220.1-6225.4" + process $proc$ls180.v:6220$1940 + assign { } { } + assign $0\main_spi_master_start1[0:0] 1'0 + attribute \src "ls180.v:6222.2-6224.5" + switch \main_spi_master_control_re + attribute \src "ls180.v:6222.6-6222.32" + case 1'1 + assign $0\main_spi_master_start1[0:0] \main_spi_master_control_storage [0] + case + end + sync always + update \main_spi_master_start1 $0\main_spi_master_start1[0:0] + end + attribute \src "ls180.v:624.32-624.76" + process $proc$ls180.v:624$3000 + assign { } { } + assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:6266.1-6271.4" + process $proc$ls180.v:6266$2005 + assign { } { } + assign $0\libresocsim_start1[0:0] 1'0 + attribute \src "ls180.v:6268.2-6270.5" + switch \libresocsim_control_re + attribute \src "ls180.v:6268.6-6268.28" + case 1'1 + assign $0\libresocsim_start1[0:0] \libresocsim_control_storage [0] + case + end + sync always + update \libresocsim_start1 $0\libresocsim_start1[0:0] + end + attribute \src "ls180.v:630.5-630.51" + process $proc$ls180.v:630$3001 + assign { } { } + assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] + end + attribute \src "ls180.v:631.5-631.51" + process $proc$ls180.v:631$3002 + assign { } { } + assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] + end + attribute \src "ls180.v:633.5-633.47" + process $proc$ls180.v:633$3003 + assign { } { } + assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] + end + attribute \src "ls180.v:634.5-634.45" + process $proc$ls180.v:634$3004 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] + end + attribute \src "ls180.v:635.5-635.45" + process $proc$ls180.v:635$3005 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] + end + attribute \src "ls180.v:636.12-636.57" + process $proc$ls180.v:636$3006 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] + end + attribute \src "ls180.v:638.5-638.51" + process $proc$ls180.v:638$3007 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:639.5-639.51" + process $proc$ls180.v:639$3008 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:640.5-640.50" + process $proc$ls180.v:640$3009 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] + end + attribute \src "ls180.v:641.5-641.54" + process $proc$ls180.v:641$3010 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:642.5-642.55" + process $proc$ls180.v:642$3011 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:643.5-643.56" + process $proc$ls180.v:643$3012 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:644.5-644.50" + process $proc$ls180.v:644$3013 + assign { } { } + assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] + end + attribute \src "ls180.v:6452.1-6468.4" + process $proc$ls180.v:6452$2225 + assign { } { } + assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:6454.2-6467.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [0] + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [1] + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [2] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [3] + end + sync always + update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0] + end + attribute \src "ls180.v:6469.1-6485.4" + process $proc$ls180.v:6469$2226 + assign { } { } + assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 + attribute \src "ls180.v:6471.2-6484.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine3_cmd_payload_a + end + sync always + update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:647.5-647.67" + process $proc$ls180.v:647$3014 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:648.5-648.66" + process $proc$ls180.v:648$3015 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:6486.1-6502.4" + process $proc$ls180.v:6486$2227 + assign { } { } + assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00 + attribute \src "ls180.v:6488.2-6501.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine3_cmd_payload_ba + end + sync always + update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0] + end + attribute \src "ls180.v:6503.1-6519.4" + process $proc$ls180.v:6503$2228 + assign { } { } + assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:6505.2-6518.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_is_read + end + sync always + update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:6520.1-6536.4" + process $proc$ls180.v:6520$2229 + assign { } { } + assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:6522.2-6535.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_is_write + end + sync always + update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:6537.1-6553.4" + process $proc$ls180.v:6537$2230 + assign { } { } + assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:6539.2-6552.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd + end + sync always + update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:6554.1-6570.4" + process $proc$ls180.v:6554$2231 + assign { } { } + assign $0\builder_comb_t_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:6556.2-6569.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine3_cmd_payload_cas + end + sync always + update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0] + end + attribute \src "ls180.v:6571.1-6587.4" + process $proc$ls180.v:6571$2232 + assign { } { } + assign $0\builder_comb_t_array_muxed1[0:0] 1'0 + attribute \src "ls180.v:6573.2-6586.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine3_cmd_payload_ras + end + sync always + update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0] + end + attribute \src "ls180.v:6588.1-6604.4" + process $proc$ls180.v:6588$2233 + assign { } { } + assign $0\builder_comb_t_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:6590.2-6603.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine3_cmd_payload_we + end + sync always + update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0] + end + attribute \src "ls180.v:66.5-66.46" + process $proc$ls180.v:66$2773 + assign { } { } + assign $1\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_dbus_ack $1\main_libresocsim_libresoc_dbus_ack[0:0] + end + attribute \src "ls180.v:6605.1-6621.4" + process $proc$ls180.v:6605$2234 + assign { } { } + assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:6607.2-6620.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [0] + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [1] + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [2] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [3] + end + sync always + update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:6622.1-6638.4" + process $proc$ls180.v:6622$2235 + assign { } { } + assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 + attribute \src "ls180.v:6624.2-6637.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine3_cmd_payload_a + end + sync always + update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0] + end + attribute \src "ls180.v:663.11-663.68" + process $proc$ls180.v:663$3016 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:6639.1-6655.4" + process $proc$ls180.v:6639$2236 + assign { } { } + assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00 + attribute \src "ls180.v:6641.2-6654.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine3_cmd_payload_ba + end + sync always + update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0] + end + attribute \src "ls180.v:664.5-664.64" + process $proc$ls180.v:664$3017 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:665.11-665.70" + process $proc$ls180.v:665$3018 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:6656.1-6672.4" + process $proc$ls180.v:6656$2237 + assign { } { } + assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0 + attribute \src "ls180.v:6658.2-6671.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine3_cmd_payload_is_read + end + sync always + update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0] + end + attribute \src "ls180.v:666.11-666.70" + process $proc$ls180.v:666$3019 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:667.11-667.73" + process $proc$ls180.v:667$3020 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:6673.1-6689.4" + process $proc$ls180.v:6673$2238 + assign { } { } + assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0 + attribute \src "ls180.v:6675.2-6688.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine3_cmd_payload_is_write + end + sync always + update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0] + end + attribute \src "ls180.v:6690.1-6706.4" + process $proc$ls180.v:6690$2239 + assign { } { } + assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0 + attribute \src "ls180.v:6692.2-6705.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd + end + sync always + update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0] + end + attribute \src "ls180.v:6707.1-6723.4" + process $proc$ls180.v:6707$2240 + assign { } { } + assign $0\builder_comb_t_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:6709.2-6722.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_cas + end + sync always + update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0] + end + attribute \src "ls180.v:6724.1-6740.4" + process $proc$ls180.v:6724$2241 + assign { } { } + assign $0\builder_comb_t_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:6726.2-6739.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_ras + end + sync always + update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0] + end + attribute \src "ls180.v:6741.1-6757.4" + process $proc$ls180.v:6741$2242 + assign { } { } + assign $0\builder_comb_t_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:6743.2-6756.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_we + end + sync always + update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0] + end + attribute \src "ls180.v:6758.1-6765.4" + process $proc$ls180.v:6758$2243 + assign { } { } + assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:6760.2-6764.9" + switch \builder_roundrobin0_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed12[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0] + end + attribute \src "ls180.v:6766.1-6773.4" + process $proc$ls180.v:6766$2244 + assign { } { } + assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0 + attribute \src "ls180.v:6768.2-6772.9" + switch \builder_roundrobin0_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed13[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0] + end + attribute \src "ls180.v:6774.1-6781.4" + process $proc$ls180.v:6774$2245 + assign { } { } + assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0 + attribute \src "ls180.v:6776.2-6780.9" + switch \builder_roundrobin0_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6778$2258_Y + end + sync always + update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0] + end + attribute \src "ls180.v:6782.1-6789.4" + process $proc$ls180.v:6782$2259 + assign { } { } + assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:6784.2-6788.9" + switch \builder_roundrobin1_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed15[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $and $and$issuer_ls180.v:177435$12473 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$49 - connect \B \$51 - connect \Y $and$issuer_ls180.v:177435$12473_Y + attribute \src "ls180.v:6790.1-6797.4" + process $proc$ls180.v:6790$2260 + assign { } { } + assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0 + attribute \src "ls180.v:6792.2-6796.9" + switch \builder_roundrobin1_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed16[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $and $and$issuer_ls180.v:177438$12476 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$55 - connect \B \$57 - connect \Y $and$issuer_ls180.v:177438$12476_Y + attribute \src "ls180.v:6798.1-6805.4" + process $proc$ls180.v:6798$2261 + assign { } { } + assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0 + attribute \src "ls180.v:6800.2-6804.9" + switch \builder_roundrobin1_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:6802$2274_Y + end + sync always + update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $and $and$issuer_ls180.v:177441$12479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$61 - connect \B \$63 - connect \Y $and$issuer_ls180.v:177441$12479_Y + attribute \src "ls180.v:6806.1-6813.4" + process $proc$ls180.v:6806$2275 + assign { } { } + assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:6808.2-6812.9" + switch \builder_roundrobin2_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed18[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $and $and$issuer_ls180.v:177444$12482 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$67 - connect \B \$69 - connect \Y $and$issuer_ls180.v:177444$12482_Y + attribute \src "ls180.v:6814.1-6821.4" + process $proc$ls180.v:6814$2276 + assign { } { } + assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0 + attribute \src "ls180.v:6816.2-6820.9" + switch \builder_roundrobin2_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed19[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $and $and$issuer_ls180.v:177447$12485 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$73 - connect \B \$75 - connect \Y $and$issuer_ls180.v:177447$12485_Y + attribute \src "ls180.v:6822.1-6829.4" + process $proc$ls180.v:6822$2277 + assign { } { } + assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0 + attribute \src "ls180.v:6824.2-6828.9" + switch \builder_roundrobin2_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:6826$2290_Y + end + sync always + update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $and $and$issuer_ls180.v:177452$12490 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$81 - connect \B \$83 - connect \Y $and$issuer_ls180.v:177452$12490_Y + attribute \src "ls180.v:6830.1-6837.4" + process $proc$ls180.v:6830$2291 + assign { } { } + assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:6832.2-6836.9" + switch \builder_roundrobin3_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed21[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $and $and$issuer_ls180.v:177456$12494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$89 - connect \B \$91 - connect \Y $and$issuer_ls180.v:177456$12494_Y + attribute \src "ls180.v:6838.1-6845.4" + process $proc$ls180.v:6838$2292 + assign { } { } + assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0 + attribute \src "ls180.v:6840.2-6844.9" + switch \builder_roundrobin3_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed22[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $extend$issuer_ls180.v:177411$12447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \core_full_rd2__data_o - connect \Y $extend$issuer_ls180.v:177411$12447_Y + attribute \src "ls180.v:6846.1-6853.4" + process $proc$ls180.v:6846$2293 + assign { } { } + assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0 + attribute \src "ls180.v:6848.2-6852.9" + switch \builder_roundrobin3_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:6850$2306_Y + end + sync always + update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $extend$issuer_ls180.v:177412$12449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \core_full_rd__data_o - connect \Y $extend$issuer_ls180.v:177412$12449_Y + attribute \src "ls180.v:6854.1-6873.4" + process $proc$ls180.v:6854$2307 + assign { } { } + assign $0\builder_comb_rhs_array_muxed24[31:0] 0 + attribute \src "ls180.v:6856.2-6872.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface0_converted_interface_adr } + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface1_converted_interface_adr } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface2_converted_interface_adr } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface0_bus_adr + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface1_bus_adr + end + sync always + update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0] end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$issuer_ls180.v:177405$12441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 7 - connect \A \dec2_cur_pc [2] - connect \B 6'100000 - connect \Y $mul$issuer_ls180.v:177405$12441_Y + attribute \src "ls180.v:6874.1-6893.4" + process $proc$ls180.v:6874$2308 + assign { } { } + assign $0\builder_comb_rhs_array_muxed25[31:0] 0 + attribute \src "ls180.v:6876.2-6892.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface0_converted_interface_dat_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface1_converted_interface_dat_w + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface2_converted_interface_dat_w + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_interface0_bus_dat_w + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_interface1_bus_dat_w + end + sync always + update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[31:0] end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$issuer_ls180.v:177407$12443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 7 - connect \A \dec2_cur_pc [2] - connect \B 6'100000 - connect \Y $mul$issuer_ls180.v:177407$12443_Y + attribute \src "ls180.v:688.5-688.59" + process $proc$ls180.v:688$3021 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:276" - cell $ne $ne$issuer_ls180.v:177410$12446 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \core_core_core_insn_type - connect \B 7'0000001 - connect \Y $ne$issuer_ls180.v:177410$12446_Y + attribute \src "ls180.v:6894.1-6913.4" + process $proc$ls180.v:6894$2309 + assign { } { } + assign $0\builder_comb_rhs_array_muxed26[3:0] 4'0000 + attribute \src "ls180.v:6896.2-6912.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface0_converted_interface_sel + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface1_converted_interface_sel + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface2_converted_interface_sel + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_interface0_bus_sel + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_interface1_bus_sel + end + sync always + update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:150" - cell $ne $ne$issuer_ls180.v:177416$12454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \delay - connect \B \$12 - connect \Y $ne$issuer_ls180.v:177416$12454_Y + attribute \src "ls180.v:690.5-690.59" + process $proc$ls180.v:690$3022 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:145" - cell $ne $ne$issuer_ls180.v:177448$12486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \delay - connect \B 1'0 - connect \Y $ne$issuer_ls180.v:177448$12486_Y + attribute \src "ls180.v:691.5-691.58" + process $proc$ls180.v:691$3023 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - cell $not $not$issuer_ls180.v:177404$12440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msr_read - connect \Y $not$issuer_ls180.v:177404$12440_Y + attribute \src "ls180.v:6914.1-6933.4" + process $proc$ls180.v:6914$2310 + assign { } { } + assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0 + attribute \src "ls180.v:6916.2-6932.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface0_converted_interface_cyc + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface1_converted_interface_cyc + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface2_converted_interface_cyc + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface0_bus_cyc + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface1_bus_cyc + end + sync always + update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:177417$12455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_st__rel_o_dly - connect \Y $not$issuer_ls180.v:177417$12455_Y + attribute \src "ls180.v:692.5-692.64" + process $proc$ls180.v:692$3024 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" - cell $not $not$issuer_ls180.v:177420$12458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pc_i_ok - connect \Y $not$issuer_ls180.v:177420$12458_Y + attribute \src "ls180.v:693.12-693.74" + process $proc$ls180.v:693$3025 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" - cell $not $not$issuer_ls180.v:177421$12459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $not$issuer_ls180.v:177421$12459_Y + attribute \src "ls180.v:6934.1-6953.4" + process $proc$ls180.v:6934$2311 + assign { } { } + assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0 + attribute \src "ls180.v:6936.2-6952.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface0_converted_interface_stb + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface1_converted_interface_stb + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface2_converted_interface_stb + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface0_bus_stb + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface1_bus_stb + end + sync always + update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:284" - cell $not $not$issuer_ls180.v:177422$12460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pc_changed - connect \Y $not$issuer_ls180.v:177422$12460_Y + attribute \src "ls180.v:694.12-694.47" + process $proc$ls180.v:694$3026 + assign { } { } + assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" - cell $not $not$issuer_ls180.v:177423$12461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $not$issuer_ls180.v:177423$12461_Y + attribute \src "ls180.v:695.5-695.46" + process $proc$ls180.v:695$3027 + assign { } { } + assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:284" - cell $not $not$issuer_ls180.v:177424$12462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pc_changed - connect \Y $not$issuer_ls180.v:177424$12462_Y + attribute \src "ls180.v:6954.1-6973.4" + process $proc$ls180.v:6954$2312 + assign { } { } + assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0 + attribute \src "ls180.v:6956.2-6972.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface0_converted_interface_we + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface1_converted_interface_we + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface2_converted_interface_we + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface0_bus_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface1_bus_we + end + sync always + update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $not $not$issuer_ls180.v:177425$12463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$issuer_ls180.v:177425$12463_Y + attribute \src "ls180.v:697.5-697.44" + process $proc$ls180.v:697$3028 + assign { } { } + assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $not $not$issuer_ls180.v:177426$12464 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $not$issuer_ls180.v:177426$12464_Y + attribute \src "ls180.v:6974.1-6993.4" + process $proc$ls180.v:6974$2313 + assign { } { } + assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000 + attribute \src "ls180.v:6976.2-6992.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface0_converted_interface_cti + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface1_converted_interface_cti + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface2_converted_interface_cti + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface0_bus_cti + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface1_bus_cti + end + sync always + update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" - cell $not $not$issuer_ls180.v:177430$12468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $not$issuer_ls180.v:177430$12468_Y + attribute \src "ls180.v:698.5-698.45" + process $proc$ls180.v:698$3029 + assign { } { } + assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" - cell $not $not$issuer_ls180.v:177431$12469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $not$issuer_ls180.v:177431$12469_Y + attribute \src "ls180.v:699.5-699.54" + process $proc$ls180.v:699$3030 + assign { } { } + assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" - cell $not $not$issuer_ls180.v:177432$12470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $not$issuer_ls180.v:177432$12470_Y + attribute \src "ls180.v:6994.1-7013.4" + process $proc$ls180.v:6994$2314 + assign { } { } + assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00 + attribute \src "ls180.v:6996.2-7012.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface0_converted_interface_bte + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface1_converted_interface_bte + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface2_converted_interface_bte + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface0_bus_bte + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface1_bus_bte + end + sync always + update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $not $not$issuer_ls180.v:177433$12471 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$issuer_ls180.v:177433$12471_Y + attribute \src "ls180.v:70.5-70.46" + process $proc$ls180.v:70$2774 + assign { } { } + assign $0\main_libresocsim_libresoc_dbus_err[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_dbus_err $0\main_libresocsim_libresoc_dbus_err[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $not $not$issuer_ls180.v:177434$12472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $not$issuer_ls180.v:177434$12472_Y + attribute \src "ls180.v:701.32-701.76" + process $proc$ls180.v:701$3031 + assign { } { } + assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $not $not$issuer_ls180.v:177436$12474 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$issuer_ls180.v:177436$12474_Y + attribute \src "ls180.v:7014.1-7030.4" + process $proc$ls180.v:7014$2315 + assign { } { } + assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00 + attribute \src "ls180.v:7016.2-7029.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_nop_ba + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_cmd_payload_ba + end + sync always + update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $not $not$issuer_ls180.v:177437$12475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $not$issuer_ls180.v:177437$12475_Y + attribute \src "ls180.v:702.11-702.55" + process $proc$ls180.v:702$3032 + assign { } { } + assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $not $not$issuer_ls180.v:177439$12477 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$issuer_ls180.v:177439$12477_Y + attribute \src "ls180.v:7031.1-7047.4" + process $proc$ls180.v:7031$2316 + assign { } { } + assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 + attribute \src "ls180.v:7033.2-7046.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_nop_a + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_cmd_payload_a + end + sync always + update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $not $not$issuer_ls180.v:177440$12478 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $not$issuer_ls180.v:177440$12478_Y + attribute \src "ls180.v:704.32-704.75" + process $proc$ls180.v:704$3033 + assign { } { } + assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $not $not$issuer_ls180.v:177442$12480 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$issuer_ls180.v:177442$12480_Y + attribute \src "ls180.v:7048.1-7064.4" + process $proc$ls180.v:7048$2317 + assign { } { } + assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:7050.2-7063.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7055$2319_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7058$2321_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7061$2323_Y + end + sync always + update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $not $not$issuer_ls180.v:177443$12481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $not$issuer_ls180.v:177443$12481_Y + attribute \src "ls180.v:706.32-706.76" + process $proc$ls180.v:706$3034 + assign { } { } + assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $not $not$issuer_ls180.v:177445$12483 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$issuer_ls180.v:177445$12483_Y + attribute \src "ls180.v:7065.1-7081.4" + process $proc$ls180.v:7065$2324 + assign { } { } + assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:7067.2-7080.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7072$2326_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7075$2328_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7078$2330_Y + end + sync always + update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $not $not$issuer_ls180.v:177446$12484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $not$issuer_ls180.v:177446$12484_Y + attribute \src "ls180.v:7082.1-7098.4" + process $proc$ls180.v:7082$2331 + assign { } { } + assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:7084.2-7097.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7089$2333_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7092$2335_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7095$2337_Y + end + sync always + update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - cell $not $not$issuer_ls180.v:177449$12487 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msr_read - connect \Y $not$issuer_ls180.v:177449$12487_Y + attribute \src "ls180.v:709.5-709.44" + process $proc$ls180.v:709$3035 + assign { } { } + assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $not $not$issuer_ls180.v:177450$12488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$issuer_ls180.v:177450$12488_Y + attribute \src "ls180.v:7099.1-7115.4" + process $proc$ls180.v:7099$2338 + assign { } { } + assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:7101.2-7114.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7106$2340_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7109$2342_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7112$2344_Y + end + sync always + update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $not $not$issuer_ls180.v:177451$12489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $not$issuer_ls180.v:177451$12489_Y + attribute \src "ls180.v:710.5-710.45" + process $proc$ls180.v:710$3036 + assign { } { } + assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" - cell $not $not$issuer_ls180.v:177453$12491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $not$issuer_ls180.v:177453$12491_Y + attribute \src "ls180.v:711.5-711.43" + process $proc$ls180.v:711$3037 + assign { } { } + assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $not $not$issuer_ls180.v:177454$12492 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$issuer_ls180.v:177454$12492_Y + attribute \src "ls180.v:7116.1-7132.4" + process $proc$ls180.v:7116$2345 + assign { } { } + assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:7118.2-7131.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7123$2347_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7126$2349_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7129$2351_Y + end + sync always + update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $not $not$issuer_ls180.v:177455$12493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $not$issuer_ls180.v:177455$12493_Y + attribute \src "ls180.v:712.5-712.48" + process $proc$ls180.v:712$3038 + assign { } { } + assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $not $not$issuer_ls180.v:177457$12495 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$issuer_ls180.v:177457$12495_Y + attribute \src "ls180.v:7133.1-7161.4" + process $proc$ls180.v:7133$2352 + assign { } { } + assign $0\builder_sync_f_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:7135.2-7160.9" + switch \main_spi_master_mosi_sel + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [0] + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [1] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [2] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [3] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [4] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [5] + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [6] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [7] + end + sync always + update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - cell $not $not$issuer_ls180.v:177458$12496 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $not$issuer_ls180.v:177458$12496_Y + attribute \src "ls180.v:714.5-714.43" + process $proc$ls180.v:714$3039 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:150" - cell $or $or$issuer_ls180.v:177415$12453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B \dbg_core_rst_o - connect \Y $or$issuer_ls180.v:177415$12453_Y + attribute \src "ls180.v:7162.1-7190.4" + process $proc$ls180.v:7162$2353 + assign { } { } + assign $0\builder_sync_f_array_muxed1[0:0] 1'0 + attribute \src "ls180.v:7164.2-7189.9" + switch \libresocsim_mosi_sel + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [0] + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [1] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [2] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [3] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [4] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [5] + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [6] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [7] + end + sync always + update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $pos$issuer_ls180.v:177411$12448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:177411$12447_Y - connect \Y $pos$issuer_ls180.v:177411$12448_Y + attribute \src "ls180.v:717.5-717.49" + process $proc$ls180.v:717$3040 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $pos$issuer_ls180.v:177412$12450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$issuer_ls180.v:177412$12449_Y - connect \Y $pos$issuer_ls180.v:177412$12450_Y + attribute \src "ls180.v:718.5-718.49" + process $proc$ls180.v:718$3041 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$issuer_ls180.v:177429$12467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \$40 - connect \Y $reduce_or$issuer_ls180.v:177429$12467_Y + attribute \src "ls180.v:719.5-719.48" + process $proc$ls180.v:719$3042 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] end - attribute \src "issuer_ls180.v:177406.19-177406.42" - cell $shr $shr$issuer_ls180.v:177406$12442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 64 - connect \A \imem_f_instr_o - connect \B \$104 - connect \Y $shr$issuer_ls180.v:177406$12442_Y + attribute \src "ls180.v:723.11-723.46" + process $proc$ls180.v:723$3043 + assign { } { } + assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 + sync always + sync init + update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] end - attribute \src "issuer_ls180.v:177409.19-177409.42" - cell $shr $shr$issuer_ls180.v:177409$12445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 64 - connect \A \imem_f_instr_o - connect \B \$108 - connect \Y $shr$issuer_ls180.v:177409$12445_Y + attribute \src "ls180.v:7246.1-7264.4" + process $proc$ls180.v:7246$2354 + assign { } { } + assign { } { } + assign $0\main_gpio_status[15:0] [0] \builder_multiregimpl1_regs1 + assign $0\main_gpio_status[15:0] [1] \builder_multiregimpl2_regs1 + assign $0\main_gpio_status[15:0] [2] \builder_multiregimpl3_regs1 + assign $0\main_gpio_status[15:0] [3] \builder_multiregimpl4_regs1 + assign $0\main_gpio_status[15:0] [4] \builder_multiregimpl5_regs1 + assign $0\main_gpio_status[15:0] [5] \builder_multiregimpl6_regs1 + assign $0\main_gpio_status[15:0] [6] \builder_multiregimpl7_regs1 + assign $0\main_gpio_status[15:0] [7] \builder_multiregimpl8_regs1 + assign $0\main_gpio_status[15:0] [8] \builder_multiregimpl9_regs1 + assign $0\main_gpio_status[15:0] [9] \builder_multiregimpl10_regs1 + assign $0\main_gpio_status[15:0] [10] \builder_multiregimpl11_regs1 + assign $0\main_gpio_status[15:0] [11] \builder_multiregimpl12_regs1 + assign $0\main_gpio_status[15:0] [12] \builder_multiregimpl13_regs1 + assign $0\main_gpio_status[15:0] [13] \builder_multiregimpl14_regs1 + assign $0\main_gpio_status[15:0] [14] \builder_multiregimpl15_regs1 + assign $0\main_gpio_status[15:0] [15] \builder_multiregimpl16_regs1 + sync always + update \main_gpio_status $0\main_gpio_status[15:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:146" - cell $sub $sub$issuer_ls180.v:177408$12444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \delay - connect \B 1'1 - connect \Y $sub$issuer_ls180.v:177408$12444_Y + attribute \src "ls180.v:725.11-725.45" + process $proc$ls180.v:725$3044 + assign { } { } + assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 + sync always + sync init + update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:362" - cell $sub $sub$issuer_ls180.v:177413$12451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \core_issue__data_o - connect \B 1'1 - connect \Y $sub$issuer_ls180.v:177413$12451_Y + attribute \src "ls180.v:727.5-727.44" + process $proc$ls180.v:727$3045 + assign { } { } + assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:177603.8-177687.4" - cell \core \core - connect \bigendian_i \core_bigendian_i$3 - connect \cia__data_o \core_cia__data_o - connect \cia__ren \core_cia__ren - connect \core_core_cia \core_core_core_cia - connect \core_core_cr_rd \core_core_core_cr_rd - connect \core_core_cr_rd_ok \core_core_core_cr_rd_ok - connect \core_core_cr_wr \core_core_core_cr_wr - connect \core_core_fn_unit \core_core_core_fn_unit - connect \core_core_input_carry \core_core_core_input_carry - connect \core_core_insn \core_core_core_insn - connect \core_core_insn_type \core_core_core_insn_type - connect \core_core_is_32bit \core_core_core_is_32bit - connect \core_core_msr \core_core_core_msr - connect \core_core_oe \core_core_core_oe - connect \core_core_oe_ok \core_core_core_oe_ok - connect \core_core_rc \core_core_core_rc - connect \core_core_rc_ok \core_core_core_rc_ok - connect \core_core_trapaddr \core_core_core_trapaddr - connect \core_core_traptype \core_core_core_traptype - connect \core_cr_in1 \core_core_cr_in1 - connect \core_cr_in1_ok \core_core_cr_in1_ok - connect \core_cr_in2 \core_core_cr_in2 - connect \core_cr_in2$1 \core_core_cr_in2$1 - connect \core_cr_in2_ok \core_core_cr_in2_ok - connect \core_cr_in2_ok$2 \core_core_cr_in2_ok$2 - connect \core_cr_out \core_core_cr_out - connect \core_ea \core_core_ea - connect \core_fast1 \core_core_fast1 - connect \core_fast1_ok \core_core_fast1_ok - connect \core_fast2 \core_core_fast2 - connect \core_fast2_ok \core_core_fast2_ok - connect \core_fasto1 \core_core_fasto1 - connect \core_fasto2 \core_core_fasto2 - connect \core_pc \core_core_pc - connect \core_reg1 \core_core_reg1 - connect \core_reg1_ok \core_core_reg1_ok - connect \core_reg2 \core_core_reg2 - connect \core_reg2_ok \core_core_reg2_ok - connect \core_reg3 \core_core_reg3 - connect \core_reg3_ok \core_core_reg3_ok - connect \core_rego \core_core_rego - connect \core_reset_i \core_core_reset_i - connect \core_spr1 \core_core_spr1 - connect \core_spr1_ok \core_core_spr1_ok - connect \core_spro \core_core_spro - connect \core_terminate_o \core_core_terminate_o - connect \core_xer_in \core_core_xer_in - connect \corebusy_o \core_corebusy_o - connect \coresync_clk \core_coresync_clk - connect \cu_ad__go_i \core_cu_ad__go_i - connect \cu_ad__rel_o \core_cu_ad__rel_o - connect \cu_st__go_i \core_cu_st__go_i - connect \cu_st__rel_o \core_cu_st__rel_o - connect \data_i \core_data_i - connect \dbus__ack \dbus__ack - connect \dbus__adr \dbus__adr - connect \dbus__cyc \dbus__cyc - connect \dbus__dat_r \dbus__dat_r - connect \dbus__dat_w \dbus__dat_w - connect \dbus__err \dbus__err - connect \dbus__sel \dbus__sel - connect \dbus__stb \dbus__stb - connect \dbus__we \dbus__we - connect \dmi__addr \core_dmi__addr - connect \dmi__data_o \core_dmi__data_o - connect \dmi__ren \core_dmi__ren - connect \full_rd2__data_o \core_full_rd2__data_o - connect \full_rd2__ren \core_full_rd2__ren - connect \full_rd__data_o \core_full_rd__data_o - connect \full_rd__ren \core_full_rd__ren - connect \issue__addr \core_issue__addr - connect \issue__addr$3 \core_issue__addr$4 - connect \issue__data_i \core_issue__data_i - connect \issue__data_o \core_issue__data_o - connect \issue__ren \core_issue__ren - connect \issue__wen \core_issue__wen - connect \issue_i \core_issue_i - connect \ivalid_i \core_ivalid_i - connect \msr__data_o \core_msr__data_o - connect \msr__ren \core_msr__ren - connect \raw_insn_i \core_raw_insn_i - connect \state_nia_wen \core_state_nia_wen - connect \wen \core_wen + attribute \src "ls180.v:728.5-728.45" + process $proc$ls180.v:728$3046 + assign { } { } + assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:177688.7-177713.4" - cell \dbg \dbg - connect \clk \clk - connect \core_dbg_msr \dbg_core_dbg_msr - connect \core_dbg_pc \dbg_core_dbg_pc - connect \core_rst_o \dbg_core_rst_o - connect \core_stop_o \dbg_core_stop_o - connect \core_stopped_i \dbg_core_stopped_i - connect \d_cr_ack \dbg_d_cr_ack - connect \d_cr_data \dbg_d_cr_data - connect \d_cr_req \dbg_d_cr_req - connect \d_gpr_ack \dbg_d_gpr_ack - connect \d_gpr_addr \dbg_d_gpr_addr - connect \d_gpr_data \dbg_d_gpr_data - connect \d_gpr_req \dbg_d_gpr_req - connect \d_xer_ack \dbg_d_xer_ack - connect \d_xer_data \dbg_d_xer_data - connect \d_xer_req \dbg_d_xer_req - connect \dmi_ack_o \dmi_ack_o - connect \dmi_addr_i \dmi_addr_i - connect \dmi_din \dmi_din - connect \dmi_dout \dmi_dout - connect \dmi_req_i \dmi_req_i - connect \dmi_we_i \dmi_we_i - connect \rst \rst - connect \terminate_i \dbg_terminate_i + attribute \src "ls180.v:7285.1-7287.4" + process $proc$ls180.v:7285$2355 + assign { } { } + assign $0\main_int_rst[0:0] \sys_rst + sync posedge \por_clk + update \main_int_rst $0\main_int_rst[0:0] end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:177714.8-177772.4" - cell \dec2 \dec2 - connect \asmcode \dec2_asmcode - connect \bigendian \dec2_bigendian - connect \cia \dec2_cia - connect \cr_in1 \dec2_cr_in1 - connect \cr_in1_ok \dec2_cr_in1_ok - connect \cr_in2 \dec2_cr_in2 - connect \cr_in2$1 \dec2_cr_in2$5 - connect \cr_in2_ok \dec2_cr_in2_ok - connect \cr_in2_ok$2 \dec2_cr_in2_ok$6 - connect \cr_out \dec2_cr_out - connect \cr_out_ok \dec2_cr_out_ok - connect \cr_rd \dec2_cr_rd - connect \cr_rd_ok \dec2_cr_rd_ok - connect \cr_wr \dec2_cr_wr - connect \cr_wr_ok \dec2_cr_wr_ok - connect \cur_dec \dec2_cur_dec - connect \cur_eint \dec2_cur_eint - connect \cur_msr \dec2_cur_msr - connect \cur_pc \dec2_cur_pc - connect \ea \dec2_ea - connect \ea_ok \dec2_ea_ok - connect \fast1 \dec2_fast1 - connect \fast1_ok \dec2_fast1_ok - connect \fast2 \dec2_fast2 - connect \fast2_ok \dec2_fast2_ok - connect \fasto1 \dec2_fasto1 - connect \fasto1_ok \dec2_fasto1_ok - connect \fasto2 \dec2_fasto2 - connect \fasto2_ok \dec2_fasto2_ok - connect \fn_unit \dec2_fn_unit - connect \input_carry \dec2_input_carry - connect \insn \dec2_insn - connect \insn_type \dec2_insn_type - connect \is_32bit \dec2_is_32bit - connect \lk \dec2_lk - connect \msr \dec2_msr - connect \oe \dec2_oe - connect \oe_ok \dec2_oe_ok - connect \raw_opcode_in \dec2_raw_opcode_in - connect \rc \dec2_rc - connect \rc_ok \dec2_rc_ok - connect \reg1 \dec2_reg1 - connect \reg1_ok \dec2_reg1_ok - connect \reg2 \dec2_reg2 - connect \reg2_ok \dec2_reg2_ok - connect \reg3 \dec2_reg3 - connect \reg3_ok \dec2_reg3_ok - connect \rego \dec2_rego - connect \rego_ok \dec2_rego_ok - connect \spr1 \dec2_spr1 - connect \spr1_ok \dec2_spr1_ok - connect \spro \dec2_spro - connect \spro_ok \dec2_spro_ok - connect \trapaddr \dec2_trapaddr - connect \traptype \dec2_traptype - connect \xer_in \dec2_xer_in - connect \xer_out \dec2_xer_out + attribute \src "ls180.v:7289.1-7357.4" + process $proc$ls180.v:7289$2356 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sdram_a[12:0] [0] \main_dfi_p0_address [0] + assign $0\sdram_a[12:0] [1] \main_dfi_p0_address [1] + assign $0\sdram_a[12:0] [2] \main_dfi_p0_address [2] + assign $0\sdram_a[12:0] [3] \main_dfi_p0_address [3] + assign $0\sdram_a[12:0] [4] \main_dfi_p0_address [4] + assign $0\sdram_a[12:0] [5] \main_dfi_p0_address [5] + assign $0\sdram_a[12:0] [6] \main_dfi_p0_address [6] + assign $0\sdram_a[12:0] [7] \main_dfi_p0_address [7] + assign $0\sdram_a[12:0] [8] \main_dfi_p0_address [8] + assign $0\sdram_a[12:0] [9] \main_dfi_p0_address [9] + assign $0\sdram_a[12:0] [10] \main_dfi_p0_address [10] + assign $0\sdram_a[12:0] [11] \main_dfi_p0_address [11] + assign $0\sdram_a[12:0] [12] \main_dfi_p0_address [12] + assign $0\sdram_ba[1:0] [0] \main_dfi_p0_bank [0] + assign $0\sdram_ba[1:0] [1] \main_dfi_p0_bank [1] + assign $0\sdram_cas_n[0:0] \main_dfi_p0_cas_n + assign $0\sdram_ras_n[0:0] \main_dfi_p0_ras_n + assign $0\sdram_we_n[0:0] \main_dfi_p0_we_n + assign $0\sdram_cke[0:0] \main_dfi_p0_cke + assign $0\sdram_cs_n[0:0] \main_dfi_p0_cs_n + assign $0\sdram_dq_oe[0:0] \main_dfi_p0_wrdata_en + assign $0\sdram_dq_o[15:0] [0] \main_dfi_p0_wrdata [0] + assign $0\main_dfi_p0_rddata[15:0] [0] \sdram_dq_i [0] + assign $0\sdram_dq_o[15:0] [1] \main_dfi_p0_wrdata [1] + assign $0\main_dfi_p0_rddata[15:0] [1] \sdram_dq_i [1] + assign $0\sdram_dq_o[15:0] [2] \main_dfi_p0_wrdata [2] + assign $0\main_dfi_p0_rddata[15:0] [2] \sdram_dq_i [2] + assign $0\sdram_dq_o[15:0] [3] \main_dfi_p0_wrdata [3] + assign $0\main_dfi_p0_rddata[15:0] [3] \sdram_dq_i [3] + assign $0\sdram_dq_o[15:0] [4] \main_dfi_p0_wrdata [4] + assign $0\main_dfi_p0_rddata[15:0] [4] \sdram_dq_i [4] + assign $0\sdram_dq_o[15:0] [5] \main_dfi_p0_wrdata [5] + assign $0\main_dfi_p0_rddata[15:0] [5] \sdram_dq_i [5] + assign $0\sdram_dq_o[15:0] [6] \main_dfi_p0_wrdata [6] + assign $0\main_dfi_p0_rddata[15:0] [6] \sdram_dq_i [6] + assign $0\sdram_dq_o[15:0] [7] \main_dfi_p0_wrdata [7] + assign $0\main_dfi_p0_rddata[15:0] [7] \sdram_dq_i [7] + assign $0\sdram_dq_o[15:0] [8] \main_dfi_p0_wrdata [8] + assign $0\main_dfi_p0_rddata[15:0] [8] \sdram_dq_i [8] + assign $0\sdram_dq_o[15:0] [9] \main_dfi_p0_wrdata [9] + assign $0\main_dfi_p0_rddata[15:0] [9] \sdram_dq_i [9] + assign $0\sdram_dq_o[15:0] [10] \main_dfi_p0_wrdata [10] + assign $0\main_dfi_p0_rddata[15:0] [10] \sdram_dq_i [10] + assign $0\sdram_dq_o[15:0] [11] \main_dfi_p0_wrdata [11] + assign $0\main_dfi_p0_rddata[15:0] [11] \sdram_dq_i [11] + assign $0\sdram_dq_o[15:0] [12] \main_dfi_p0_wrdata [12] + assign $0\main_dfi_p0_rddata[15:0] [12] \sdram_dq_i [12] + assign $0\sdram_dq_o[15:0] [13] \main_dfi_p0_wrdata [13] + assign $0\main_dfi_p0_rddata[15:0] [13] \sdram_dq_i [13] + assign $0\sdram_dq_o[15:0] [14] \main_dfi_p0_wrdata [14] + assign $0\main_dfi_p0_rddata[15:0] [14] \sdram_dq_i [14] + assign $0\sdram_dq_o[15:0] [15] \main_dfi_p0_wrdata [15] + assign $0\main_dfi_p0_rddata[15:0] [15] \sdram_dq_i [15] + assign $0\sdram_clock[0:0] \sys_clk_1 + assign $0\sdcard_clk[0:0] $and$ls180.v:7344$2358_Y + assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe + assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o + assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i + assign $0\sdcard_data_oe[0:0] \main_sdphy_sdpads_data_oe + assign $0\sdcard_data_o[3:0] [0] \main_sdphy_sdpads_data_o [0] + assign $0\main_sdphy_sdpads_data_i[3:0] [0] \sdcard_data_i [0] + assign $0\sdcard_data_o[3:0] [1] \main_sdphy_sdpads_data_o [1] + assign $0\main_sdphy_sdpads_data_i[3:0] [1] \sdcard_data_i [1] + assign $0\sdcard_data_o[3:0] [2] \main_sdphy_sdpads_data_o [2] + assign $0\main_sdphy_sdpads_data_i[3:0] [2] \sdcard_data_i [2] + assign $0\sdcard_data_o[3:0] [3] \main_sdphy_sdpads_data_o [3] + assign $0\main_sdphy_sdpads_data_i[3:0] [3] \sdcard_data_i [3] + sync posedge \sdrio_clk + update \sdram_a $0\sdram_a[12:0] + update \sdram_dq_o $0\sdram_dq_o[15:0] + update \sdram_dq_oe $0\sdram_dq_oe[0:0] + update \sdram_we_n $0\sdram_we_n[0:0] + update \sdram_ras_n $0\sdram_ras_n[0:0] + update \sdram_cas_n $0\sdram_cas_n[0:0] + update \sdram_cs_n $0\sdram_cs_n[0:0] + update \sdram_cke $0\sdram_cke[0:0] + update \sdram_ba $0\sdram_ba[1:0] + update \sdram_clock $0\sdram_clock[0:0] + update \sdcard_clk $0\sdcard_clk[0:0] + update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] + update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] + update \sdcard_data_o $0\sdcard_data_o[3:0] + update \sdcard_data_oe $0\sdcard_data_oe[0:0] + update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0] + update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0] + update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0] end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:177773.8-177788.4" - cell \imem \imem - connect \a_pc_i \imem_a_pc_i - connect \a_valid_i \imem_a_valid_i - connect \clk \clk - connect \f_busy_o \imem_f_busy_o - connect \f_instr_o \imem_f_instr_o - connect \f_valid_i \imem_f_valid_i - connect \ibus__ack \ibus__ack - connect \ibus__adr \ibus__adr - connect \ibus__cyc \ibus__cyc - connect \ibus__dat_r \ibus__dat_r - connect \ibus__err \ibus__err - connect \ibus__sel \ibus__sel - connect \ibus__stb \ibus__stb - connect \rst \rst + attribute \src "ls180.v:730.5-730.48" + process $proc$ls180.v:730$3047 + assign { } { } + assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:177789.12-177803.4" - cell \xics_icp \xics_icp - connect \clk \clk - connect \core_irq_o \xics_icp_core_irq_o - connect \icp_wb__ack \icp_wb__ack - connect \icp_wb__adr \icp_wb__adr - connect \icp_wb__cyc \icp_wb__cyc - connect \icp_wb__dat_r \icp_wb__dat_r - connect \icp_wb__dat_w \icp_wb__dat_w - connect \icp_wb__sel \icp_wb__sel - connect \icp_wb__stb \icp_wb__stb - connect \icp_wb__we \icp_wb__we - connect \ics_i_pri \xics_icp_ics_i_pri - connect \ics_i_src \xics_icp_ics_i_src - connect \rst \rst + attribute \src "ls180.v:732.5-732.43" + process $proc$ls180.v:732$3048 + assign { } { } + assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:177804.12-177817.4" - cell \xics_ics \xics_ics - connect \clk \clk - connect \icp_o_pri \xics_ics_icp_o_pri - connect \icp_o_src \xics_ics_icp_o_src - connect \ics_wb__ack \ics_wb__ack - connect \ics_wb__adr \ics_wb__adr - connect \ics_wb__cyc \ics_wb__cyc - connect \ics_wb__dat_r \ics_wb__dat_r - connect \ics_wb__dat_w \ics_wb__dat_w - connect \ics_wb__stb \ics_wb__stb - connect \ics_wb__we \ics_wb__we - connect \int_level_i \int_level_i - connect \rst \rst + attribute \src "ls180.v:735.5-735.49" + process $proc$ls180.v:735$3049 + assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:7359.1-9977.4" + process $proc$ls180.v:7359$2359 + assign { } { } + assign $0\spi_master_clk[0:0] \spi_master_clk + assign $0\spi_master_mosi[0:0] \spi_master_mosi + assign { } { } + assign $0\pwm0[0:0] \pwm0 + assign $0\pwm1[0:0] \pwm1 + assign $0\spisdcard_clk[0:0] \spisdcard_clk + assign $0\spisdcard_mosi[0:0] \spisdcard_mosi + assign { } { } + assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage + assign { } { } + assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage + assign { } { } + assign $0\main_libresocsim_bus_errors[31:0] \main_libresocsim_bus_errors + assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] \main_libresocsim_libresoc_constraintmanager0_uart0_tx + assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter + assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_converter0_dat_r + assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter + assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_converter1_dat_r + assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter + assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_converter2_dat_r + assign { } { } + assign $0\main_libresocsim_load_storage[31:0] \main_libresocsim_load_storage + assign { } { } + assign $0\main_libresocsim_reload_storage[31:0] \main_libresocsim_reload_storage + assign { } { } + assign $0\main_libresocsim_en_storage[0:0] \main_libresocsim_en_storage + assign { } { } + assign $0\main_libresocsim_update_value_storage[0:0] \main_libresocsim_update_value_storage + assign { } { } + assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value_status + assign $0\main_libresocsim_zero_pending[0:0] \main_libresocsim_zero_pending + assign { } { } + assign $0\main_libresocsim_eventmanager_storage[0:0] \main_libresocsim_eventmanager_storage + assign { } { } + assign $0\main_libresocsim_value[31:0] \main_libresocsim_value + assign { } { } + assign { } { } + assign $0\main_sdram_storage[3:0] \main_sdram_storage + assign { } { } + assign $0\main_sdram_command_storage[5:0] \main_sdram_command_storage + assign { } { } + assign $0\main_sdram_address_storage[12:0] \main_sdram_address_storage + assign { } { } + assign $0\main_sdram_baddress_storage[1:0] \main_sdram_baddress_storage + assign { } { } + assign $0\main_sdram_wrdata_storage[15:0] \main_sdram_wrdata_storage + assign { } { } + assign $0\main_sdram_status[15:0] \main_sdram_status + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_timer_count1[9:0] \main_sdram_timer_count1 + assign { } { } + assign $0\main_sdram_postponer_count[0:0] \main_sdram_postponer_count + assign { } { } + assign $0\main_sdram_sequencer_counter[3:0] \main_sdram_sequencer_counter + assign $0\main_sdram_sequencer_count[0:0] \main_sdram_sequencer_count + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_source_first + assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_source_last + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_row + assign $0\main_sdram_bankmachine0_row_opened[0:0] \main_sdram_bankmachine0_row_opened + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] \main_sdram_bankmachine0_twtpcon_ready + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] \main_sdram_bankmachine0_twtpcon_count + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_source_first + assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_source_last + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_row + assign $0\main_sdram_bankmachine1_row_opened[0:0] \main_sdram_bankmachine1_row_opened + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] \main_sdram_bankmachine1_twtpcon_ready + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] \main_sdram_bankmachine1_twtpcon_count + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_source_first + assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_source_last + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_row + assign $0\main_sdram_bankmachine2_row_opened[0:0] \main_sdram_bankmachine2_row_opened + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] \main_sdram_bankmachine2_twtpcon_ready + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] \main_sdram_bankmachine2_twtpcon_count + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_source_first + assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_source_last + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_row + assign $0\main_sdram_bankmachine3_row_opened[0:0] \main_sdram_bankmachine3_row_opened + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] \main_sdram_bankmachine3_twtpcon_ready + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] \main_sdram_bankmachine3_twtpcon_count + assign $0\main_sdram_choose_cmd_grant[1:0] \main_sdram_choose_cmd_grant + assign $0\main_sdram_choose_req_grant[1:0] \main_sdram_choose_req_grant + assign $0\main_sdram_tccdcon_ready[0:0] \main_sdram_tccdcon_ready + assign $0\main_sdram_tccdcon_count[0:0] \main_sdram_tccdcon_count + assign $0\main_sdram_twtrcon_ready[0:0] \main_sdram_twtrcon_ready + assign $0\main_sdram_twtrcon_count[2:0] \main_sdram_twtrcon_count + assign $0\main_sdram_time0[4:0] \main_sdram_time0 + assign $0\main_sdram_time1[3:0] \main_sdram_time1 + assign $0\main_converter_counter[0:0] \main_converter_counter + assign $0\main_converter_dat_r[31:0] \main_converter_dat_r + assign $0\main_cmd_consumed[0:0] \main_cmd_consumed + assign $0\main_wdata_consumed[0:0] \main_wdata_consumed + assign $0\main_storage[31:0] \main_storage + assign { } { } + assign { } { } + assign $0\main_uart_clk_txen[0:0] \main_uart_clk_txen + assign $0\main_phase_accumulator_tx[31:0] \main_phase_accumulator_tx + assign $0\main_tx_reg[7:0] \main_tx_reg + assign $0\main_tx_bitcount[3:0] \main_tx_bitcount + assign $0\main_tx_busy[0:0] \main_tx_busy + assign { } { } + assign $0\main_source_payload_data[7:0] \main_source_payload_data + assign $0\main_uart_clk_rxen[0:0] \main_uart_clk_rxen + assign $0\main_phase_accumulator_rx[31:0] \main_phase_accumulator_rx + assign { } { } + assign $0\main_rx_reg[7:0] \main_rx_reg + assign $0\main_rx_bitcount[3:0] \main_rx_bitcount + assign $0\main_rx_busy[0:0] \main_rx_busy + assign $0\main_uart_tx_pending[0:0] \main_uart_tx_pending + assign { } { } + assign $0\main_uart_rx_pending[0:0] \main_uart_rx_pending + assign { } { } + assign $0\main_uart_eventmanager_storage[1:0] \main_uart_eventmanager_storage + assign { } { } + assign $0\main_uart_tx_fifo_readable[0:0] \main_uart_tx_fifo_readable + assign $0\main_uart_tx_fifo_level0[4:0] \main_uart_tx_fifo_level0 + assign $0\main_uart_tx_fifo_produce[3:0] \main_uart_tx_fifo_produce + assign $0\main_uart_tx_fifo_consume[3:0] \main_uart_tx_fifo_consume + assign $0\main_uart_rx_fifo_readable[0:0] \main_uart_rx_fifo_readable + assign $0\main_uart_rx_fifo_level0[4:0] \main_uart_rx_fifo_level0 + assign $0\main_uart_rx_fifo_produce[3:0] \main_uart_rx_fifo_produce + assign $0\main_uart_rx_fifo_consume[3:0] \main_uart_rx_fifo_consume + assign $0\main_gpio_oe_storage[15:0] \main_gpio_oe_storage + assign { } { } + assign $0\main_gpio_out_storage[15:0] \main_gpio_out_storage + assign { } { } + assign $0\main_spi_master_miso[7:0] \main_spi_master_miso + assign $0\main_spi_master_control_storage[15:0] \main_spi_master_control_storage + assign { } { } + assign $0\main_spi_master_mosi_storage[7:0] \main_spi_master_mosi_storage + assign { } { } + assign $0\main_spi_master_cs_storage[0:0] \main_spi_master_cs_storage + assign { } { } + assign $0\main_spi_master_loopback_storage[0:0] \main_spi_master_loopback_storage + assign { } { } + assign $0\main_spi_master_count[2:0] \main_spi_master_count + assign { } { } + assign $0\main_spi_master_mosi_data[7:0] \main_spi_master_mosi_data + assign $0\main_spi_master_mosi_sel[2:0] \main_spi_master_mosi_sel + assign $0\main_spi_master_miso_data[7:0] \main_spi_master_miso_data + assign { } { } + assign $0\main_pwm0_counter[31:0] \main_pwm0_counter + assign $0\main_pwm0_enable_storage[0:0] \main_pwm0_enable_storage + assign { } { } + assign $0\main_pwm0_width_storage[31:0] \main_pwm0_width_storage + assign { } { } + assign $0\main_pwm0_period_storage[31:0] \main_pwm0_period_storage + assign { } { } + assign $0\main_pwm1_counter[31:0] \main_pwm1_counter + assign $0\main_pwm1_enable_storage[0:0] \main_pwm1_enable_storage + assign { } { } + assign $0\main_pwm1_width_storage[31:0] \main_pwm1_width_storage + assign { } { } + assign $0\main_pwm1_period_storage[31:0] \main_pwm1_period_storage + assign { } { } + assign $0\main_sdphy_clocker_storage[8:0] \main_sdphy_clocker_storage + assign { } { } + assign { } { } + assign $0\main_sdphy_clocker_clks[8:0] \main_sdphy_clocker_clks + assign { } { } + assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count + assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count + assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout + assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count + assign $0\main_sdphy_cmdr_cmdr_run[0:0] \main_sdphy_cmdr_cmdr_run + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_source_first + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_source_last + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_converter_source_payload_data + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] \main_sdphy_cmdr_cmdr_converter_demux + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] \main_sdphy_cmdr_cmdr_converter_strobe_all + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_source_valid + assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_source_first + assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_source_last + assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_source_payload_data + assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset + assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count + assign $0\main_sdphy_dataw_crcr_run[0:0] \main_sdphy_dataw_crcr_run + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_source_first + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_source_last + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] \main_sdphy_dataw_crcr_converter_source_payload_data + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] \main_sdphy_dataw_crcr_converter_demux + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] \main_sdphy_dataw_crcr_converter_strobe_all + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_source_valid + assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_source_first + assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_source_last + assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_source_payload_data + assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset + assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout + assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count + assign $0\main_sdphy_datar_datar_run[0:0] \main_sdphy_datar_datar_run + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_source_first + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_source_last + assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] \main_sdphy_datar_datar_converter_source_payload_data + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] \main_sdphy_datar_datar_converter_source_payload_valid_token_count + assign $0\main_sdphy_datar_datar_converter_demux[0:0] \main_sdphy_datar_datar_converter_demux + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] \main_sdphy_datar_datar_converter_strobe_all + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_source_valid + assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_source_first + assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_source_last + assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_source_payload_data + assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset + assign $0\main_sdcore_cmd_argument_storage[31:0] \main_sdcore_cmd_argument_storage + assign { } { } + assign $0\main_sdcore_cmd_command_storage[31:0] \main_sdcore_cmd_command_storage + assign { } { } + assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status + assign $0\main_sdcore_block_length_storage[9:0] \main_sdcore_block_length_storage + assign { } { } + assign $0\main_sdcore_block_count_storage[31:0] \main_sdcore_block_count_storage + assign { } { } + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg0 + assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 + assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0 + assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1 + assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2 + assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3 + assign $0\main_sdcore_crc16_checker_val[7:0] \main_sdcore_crc16_checker_val + assign $0\main_sdcore_crc16_checker_cnt[3:0] \main_sdcore_crc16_checker_cnt + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crctmp0 + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crctmp1 + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crctmp2 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crctmp3 + assign $0\main_sdcore_crc16_checker_fifo0[15:0] \main_sdcore_crc16_checker_fifo0 + assign $0\main_sdcore_crc16_checker_fifo1[15:0] \main_sdcore_crc16_checker_fifo1 + assign $0\main_sdcore_crc16_checker_fifo2[15:0] \main_sdcore_crc16_checker_fifo2 + assign $0\main_sdcore_crc16_checker_fifo3[15:0] \main_sdcore_crc16_checker_fifo3 + assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count + assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done + assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error + assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout + assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count + assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done + assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error + assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout + assign $0\main_sdblock2mem_fifo_level[5:0] \main_sdblock2mem_fifo_level + assign $0\main_sdblock2mem_fifo_produce[4:0] \main_sdblock2mem_fifo_produce + assign $0\main_sdblock2mem_fifo_consume[4:0] \main_sdblock2mem_fifo_consume + assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_source_first + assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_source_last + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] \main_sdblock2mem_converter_source_payload_data + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] \main_sdblock2mem_converter_source_payload_valid_token_count + assign $0\main_sdblock2mem_converter_demux[1:0] \main_sdblock2mem_converter_demux + assign $0\main_sdblock2mem_converter_strobe_all[0:0] \main_sdblock2mem_converter_strobe_all + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] \main_sdblock2mem_wishbonedmawriter_base_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] \main_sdblock2mem_wishbonedmawriter_length_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \main_sdblock2mem_wishbonedmawriter_enable_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \main_sdblock2mem_wishbonedmawriter_loop_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset + assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data + assign $0\main_sdmem2block_dma_base_storage[63:0] \main_sdmem2block_dma_base_storage + assign { } { } + assign $0\main_sdmem2block_dma_length_storage[31:0] \main_sdmem2block_dma_length_storage + assign { } { } + assign $0\main_sdmem2block_dma_enable_storage[0:0] \main_sdmem2block_dma_enable_storage + assign { } { } + assign $0\main_sdmem2block_dma_loop_storage[0:0] \main_sdmem2block_dma_loop_storage + assign { } { } + assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset + assign $0\main_sdmem2block_converter_mux[1:0] \main_sdmem2block_converter_mux + assign $0\main_sdmem2block_fifo_level[5:0] \main_sdmem2block_fifo_level + assign $0\main_sdmem2block_fifo_produce[4:0] \main_sdmem2block_fifo_produce + assign $0\main_sdmem2block_fifo_consume[4:0] \main_sdmem2block_fifo_consume + assign $0\libresocsim_miso[7:0] \libresocsim_miso + assign $0\libresocsim_control_storage[15:0] \libresocsim_control_storage + assign { } { } + assign $0\libresocsim_mosi_storage[7:0] \libresocsim_mosi_storage + assign { } { } + assign $0\libresocsim_cs_storage[0:0] \libresocsim_cs_storage + assign { } { } + assign $0\libresocsim_loopback_storage[0:0] \libresocsim_loopback_storage + assign { } { } + assign $0\libresocsim_count[2:0] \libresocsim_count + assign { } { } + assign $0\libresocsim_mosi_data[7:0] \libresocsim_mosi_data + assign $0\libresocsim_mosi_sel[2:0] \libresocsim_mosi_sel + assign $0\libresocsim_miso_data[7:0] \libresocsim_miso_data + assign $0\libresocsim_storage[15:0] \libresocsim_storage + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr + assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we + assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w + assign $0\builder_grant[2:0] \builder_grant + assign { } { } + assign $0\builder_count[19:0] \builder_count + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_dummy[42:0] [0] $or$ls180.v:7360$2360_Y + assign $0\main_dummy[42:0] [1] $or$ls180.v:7361$2361_Y + assign $0\main_dummy[42:0] [2] $or$ls180.v:7362$2362_Y + assign $0\main_dummy[42:0] [3] $or$ls180.v:7363$2363_Y + assign $0\main_dummy[42:0] [4] $or$ls180.v:7364$2364_Y + assign $0\main_dummy[42:0] [5] $or$ls180.v:7365$2365_Y + assign $0\main_dummy[42:0] [6] $or$ls180.v:7366$2366_Y + assign $0\main_dummy[42:0] [7] $or$ls180.v:7367$2367_Y + assign $0\main_dummy[42:0] [8] $or$ls180.v:7368$2368_Y + assign $0\main_dummy[42:0] [9] $or$ls180.v:7369$2369_Y + assign $0\main_dummy[42:0] [10] $or$ls180.v:7370$2370_Y + assign $0\main_dummy[42:0] [11] $or$ls180.v:7371$2371_Y + assign $0\main_dummy[42:0] [12] $or$ls180.v:7372$2372_Y + assign $0\main_dummy[42:0] [13] $or$ls180.v:7373$2373_Y + assign $0\main_dummy[42:0] [14] $or$ls180.v:7374$2374_Y + assign $0\main_dummy[42:0] [15] $or$ls180.v:7375$2375_Y + assign $0\main_dummy[42:0] [16] $or$ls180.v:7376$2376_Y + assign $0\main_dummy[42:0] [17] $or$ls180.v:7377$2377_Y + assign $0\main_dummy[42:0] [18] $or$ls180.v:7378$2378_Y + assign $0\main_dummy[42:0] [19] $or$ls180.v:7379$2379_Y + assign $0\main_dummy[42:0] [20] $or$ls180.v:7380$2380_Y + assign $0\main_dummy[42:0] [21] $or$ls180.v:7381$2381_Y + assign $0\main_dummy[42:0] [22] $or$ls180.v:7382$2382_Y + assign $0\main_dummy[42:0] [23] $or$ls180.v:7383$2383_Y + assign $0\main_dummy[42:0] [24] $or$ls180.v:7384$2384_Y + assign $0\main_dummy[42:0] [25] $or$ls180.v:7385$2385_Y + assign $0\main_dummy[42:0] [26] $or$ls180.v:7386$2386_Y + assign $0\main_dummy[42:0] [27] $or$ls180.v:7387$2387_Y + assign $0\main_dummy[42:0] [28] $or$ls180.v:7388$2388_Y + assign $0\main_dummy[42:0] [29] $or$ls180.v:7389$2389_Y + assign $0\main_dummy[42:0] [30] $or$ls180.v:7390$2390_Y + assign $0\main_dummy[42:0] [31] $or$ls180.v:7391$2391_Y + assign $0\main_dummy[42:0] [32] $or$ls180.v:7392$2392_Y + assign $0\main_dummy[42:0] [33] $or$ls180.v:7393$2393_Y + assign $0\main_dummy[42:0] [34] $or$ls180.v:7394$2394_Y + assign $0\main_dummy[42:0] [35] $or$ls180.v:7395$2395_Y + assign $0\main_dummy[42:0] [36] $or$ls180.v:7396$2396_Y + assign $0\main_dummy[42:0] [37] $or$ls180.v:7397$2397_Y + assign $0\main_dummy[42:0] [38] $or$ls180.v:7398$2398_Y + assign $0\main_dummy[42:0] [39] $or$ls180.v:7399$2399_Y + assign $0\main_dummy[42:0] [40] $or$ls180.v:7400$2400_Y + assign $0\main_dummy[42:0] [41] $or$ls180.v:7401$2401_Y + assign $0\main_dummy[42:0] [42] $or$ls180.v:7402$2402_Y + assign $0\builder_converter0_state[0:0] \builder_converter0_next_state + assign $0\builder_converter1_state[0:0] \builder_converter1_next_state + assign $0\builder_converter2_state[0:0] \builder_converter2_next_state + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 + assign $0\main_libresocsim_zero_old_trigger[0:0] \main_libresocsim_zero_trigger + assign $0\sdram_dm[1:0] [0] \main_dm [0] + assign $0\sdram_dm[1:0] [1] \main_dm [1] + assign $0\main_rddata_en[2:0] { \main_rddata_en [1:0] \main_dfi_p0_rddata_en } + assign $0\main_dfi_p0_rddata_valid[0:0] \main_rddata_en [2] + assign $0\main_sdram_postponer_req_o[0:0] 1'0 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'0 + assign $0\builder_refresher_state[1:0] \builder_refresher_next_state + assign $0\builder_bankmachine0_state[2:0] \builder_bankmachine0_next_state + assign $0\builder_bankmachine1_state[2:0] \builder_bankmachine1_next_state + assign $0\builder_bankmachine2_state[2:0] \builder_bankmachine2_next_state + assign $0\builder_bankmachine3_state[2:0] \builder_bankmachine3_next_state + assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0 + assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0 + assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1 + assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:7846$2499_Y + assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:7847$2500_Y + assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:7848$2501_Y + assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5 + assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6 + assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state + assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:7882$2519_Y + assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:7883$2531_Y + assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0 + assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1 + assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2 + assign $0\builder_converter_state[0:0] \builder_converter_next_state + assign $0\main_sink_ready[0:0] 1'0 + assign $0\main_source_valid[0:0] 1'0 + assign $0\main_rx_r[0:0] \main_rx + assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger + assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger + assign $0\main_spi_master_clk_divider1[15:0] $add$ls180.v:8041$2577_Y + assign $0\spi_master_cs_n[0:0] $or$ls180.v:8050$2580_Y + assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state + assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1 + assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1 + assign $0\builder_sdphy_sdphyinit_state[0:0] \builder_sdphy_sdphyinit_next_state + assign $0\builder_sdphy_sdphycmdw_state[1:0] \builder_sdphy_sdphycmdw_next_state + assign $0\builder_sdphy_sdphycmdr_state[2:0] \builder_sdphy_sdphycmdr_next_state + assign $0\builder_sdphy_sdphycrcr_state[0:0] \builder_sdphy_sdphycrcr_next_state + assign $0\builder_sdphy_fsm_state[2:0] \builder_sdphy_fsm_next_state + assign $0\builder_sdphy_sdphydatar_state[2:0] \builder_sdphy_sdphydatar_next_state + assign $0\builder_sdcore_crcupstreaminserter_state[0:0] \builder_sdcore_crcupstreaminserter_next_state + assign $0\builder_sdcore_fsm_state[2:0] \builder_sdcore_fsm_next_state + assign $0\builder_sdblock2memdma_state[1:0] \builder_sdblock2memdma_next_state + assign $0\builder_sdmem2blockdma_fsm_state[0:0] \builder_sdmem2blockdma_fsm_next_state + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] \builder_sdmem2blockdma_resetinserter_next_state + assign $0\libresocsim_clk_divider1[15:0] $add$ls180.v:8589$2672_Y + assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8598$2675_Y + assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state + assign $0\builder_state[1:0] \builder_next_state + assign $0\builder_slave_sel_r[4:0] \builder_slave_sel + assign $0\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_libresocsim_reset_re[0:0] \builder_csrbank0_reset0_re + assign $0\main_libresocsim_scratch_re[0:0] \builder_csrbank0_scratch0_re + assign $0\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_gpio_oe_re[0:0] \builder_csrbank1_oe0_re + assign $0\main_gpio_out_re[0:0] \builder_csrbank1_out0_re + assign $0\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_pwm0_enable_re[0:0] \builder_csrbank2_enable0_re + assign $0\main_pwm0_width_re[0:0] \builder_csrbank2_width0_re + assign $0\main_pwm0_period_re[0:0] \builder_csrbank2_period0_re + assign $0\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_pwm1_enable_re[0:0] \builder_csrbank3_enable0_re + assign $0\main_pwm1_width_re[0:0] \builder_csrbank3_width0_re + assign $0\main_pwm1_period_re[0:0] \builder_csrbank3_period0_re + assign $0\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] \builder_csrbank4_dma_base0_re + assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] \builder_csrbank4_dma_length0_re + assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] \builder_csrbank4_dma_enable0_re + assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] \builder_csrbank4_dma_loop0_re + assign $0\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdcore_cmd_argument_re[0:0] \builder_csrbank5_cmd_argument0_re + assign $0\main_sdcore_cmd_command_re[0:0] \builder_csrbank5_cmd_command0_re + assign $0\main_sdcore_block_length_re[0:0] \builder_csrbank5_block_length0_re + assign $0\main_sdcore_block_count_re[0:0] \builder_csrbank5_block_count0_re + assign $0\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdmem2block_dma_base_re[0:0] \builder_csrbank6_dma_base0_re + assign $0\main_sdmem2block_dma_length_re[0:0] \builder_csrbank6_dma_length0_re + assign $0\main_sdmem2block_dma_enable_re[0:0] \builder_csrbank6_dma_enable0_re + assign $0\main_sdmem2block_dma_loop_re[0:0] \builder_csrbank6_dma_loop0_re + assign $0\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdphy_clocker_re[0:0] \builder_csrbank7_clocker_divider0_re + assign $0\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdram_re[0:0] \builder_csrbank8_dfii_control0_re + assign $0\main_sdram_command_re[0:0] \builder_csrbank8_dfii_pi0_command0_re + assign $0\main_sdram_address_re[0:0] \builder_csrbank8_dfii_pi0_address0_re + assign $0\main_sdram_baddress_re[0:0] \builder_csrbank8_dfii_pi0_baddress0_re + assign $0\main_sdram_wrdata_re[0:0] \builder_csrbank8_dfii_pi0_wrdata0_re + assign $0\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_spi_master_control_re[0:0] \builder_csrbank9_control0_re + assign $0\main_spi_master_mosi_re[0:0] \builder_csrbank9_mosi0_re + assign $0\main_spi_master_cs_re[0:0] \builder_csrbank9_cs0_re + assign $0\main_spi_master_loopback_re[0:0] \builder_csrbank9_loopback0_re + assign $0\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 + assign $0\libresocsim_control_re[0:0] \builder_csrbank10_control0_re + assign $0\libresocsim_mosi_re[0:0] \builder_csrbank10_mosi0_re + assign $0\libresocsim_cs_re[0:0] \builder_csrbank10_cs0_re + assign $0\libresocsim_loopback_re[0:0] \builder_csrbank10_loopback0_re + assign $0\libresocsim_re[0:0] \builder_csrbank10_clk_divider0_re + assign $0\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_libresocsim_load_re[0:0] \builder_csrbank11_load0_re + assign $0\main_libresocsim_reload_re[0:0] \builder_csrbank11_reload0_re + assign $0\main_libresocsim_en_re[0:0] \builder_csrbank11_en0_re + assign $0\main_libresocsim_update_value_re[0:0] \builder_csrbank11_update_value0_re + assign $0\main_libresocsim_eventmanager_re[0:0] \builder_csrbank11_ev_enable0_re + assign $0\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_uart_eventmanager_re[0:0] \builder_csrbank12_ev_enable0_re + assign $0\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_re[0:0] \builder_csrbank13_tuning_word0_re + assign $0\builder_multiregimpl0_regs0[0:0] \main_libresocsim_libresoc_constraintmanager0_uart0_rx + assign $0\builder_multiregimpl0_regs1[0:0] \builder_multiregimpl0_regs0 + assign $0\builder_multiregimpl1_regs0[0:0] \main_gpio_pads_i [0] + assign $0\builder_multiregimpl1_regs1[0:0] \builder_multiregimpl1_regs0 + assign $0\builder_multiregimpl2_regs0[0:0] \main_gpio_pads_i [1] + assign $0\builder_multiregimpl2_regs1[0:0] \builder_multiregimpl2_regs0 + assign $0\builder_multiregimpl3_regs0[0:0] \main_gpio_pads_i [2] + assign $0\builder_multiregimpl3_regs1[0:0] \builder_multiregimpl3_regs0 + assign $0\builder_multiregimpl4_regs0[0:0] \main_gpio_pads_i [3] + assign $0\builder_multiregimpl4_regs1[0:0] \builder_multiregimpl4_regs0 + assign $0\builder_multiregimpl5_regs0[0:0] \main_gpio_pads_i [4] + assign $0\builder_multiregimpl5_regs1[0:0] \builder_multiregimpl5_regs0 + assign $0\builder_multiregimpl6_regs0[0:0] \main_gpio_pads_i [5] + assign $0\builder_multiregimpl6_regs1[0:0] \builder_multiregimpl6_regs0 + assign $0\builder_multiregimpl7_regs0[0:0] \main_gpio_pads_i [6] + assign $0\builder_multiregimpl7_regs1[0:0] \builder_multiregimpl7_regs0 + assign $0\builder_multiregimpl8_regs0[0:0] \main_gpio_pads_i [7] + assign $0\builder_multiregimpl8_regs1[0:0] \builder_multiregimpl8_regs0 + assign $0\builder_multiregimpl9_regs0[0:0] \main_gpio_pads_i [8] + assign $0\builder_multiregimpl9_regs1[0:0] \builder_multiregimpl9_regs0 + assign $0\builder_multiregimpl10_regs0[0:0] \main_gpio_pads_i [9] + assign $0\builder_multiregimpl10_regs1[0:0] \builder_multiregimpl10_regs0 + assign $0\builder_multiregimpl11_regs0[0:0] \main_gpio_pads_i [10] + assign $0\builder_multiregimpl11_regs1[0:0] \builder_multiregimpl11_regs0 + assign $0\builder_multiregimpl12_regs0[0:0] \main_gpio_pads_i [11] + assign $0\builder_multiregimpl12_regs1[0:0] \builder_multiregimpl12_regs0 + assign $0\builder_multiregimpl13_regs0[0:0] \main_gpio_pads_i [12] + assign $0\builder_multiregimpl13_regs1[0:0] \builder_multiregimpl13_regs0 + assign $0\builder_multiregimpl14_regs0[0:0] \main_gpio_pads_i [13] + assign $0\builder_multiregimpl14_regs1[0:0] \builder_multiregimpl14_regs0 + assign $0\builder_multiregimpl15_regs0[0:0] \main_gpio_pads_i [14] + assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0 + assign $0\builder_multiregimpl16_regs0[0:0] \main_gpio_pads_i [15] + assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0 + attribute \src "ls180.v:7403.2-7405.5" + switch $or$ls180.v:7403$2403_Y + attribute \src "ls180.v:7403.6-7403.94" + case 1'1 + assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_libresoc_ibus_dat_r + case + end + attribute \src "ls180.v:7407.2-7409.5" + switch \main_libresocsim_converter0_counter_converter0_next_value_ce + attribute \src "ls180.v:7407.6-7407.66" + case 1'1 + assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter_converter0_next_value + case + end + attribute \src "ls180.v:7410.2-7413.5" + switch \main_libresocsim_converter0_reset + attribute \src "ls180.v:7410.6-7410.39" + case 1'1 + assign $0\main_libresocsim_converter0_counter[0:0] 1'0 + assign $0\builder_converter0_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7414.2-7416.5" + switch $or$ls180.v:7414$2404_Y + attribute \src "ls180.v:7414.6-7414.94" + case 1'1 + assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_libresoc_dbus_dat_r + case + end + attribute \src "ls180.v:7418.2-7420.5" + switch \main_libresocsim_converter1_counter_converter1_next_value_ce + attribute \src "ls180.v:7418.6-7418.66" + case 1'1 + assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter_converter1_next_value + case + end + attribute \src "ls180.v:7421.2-7424.5" + switch \main_libresocsim_converter1_reset + attribute \src "ls180.v:7421.6-7421.39" + case 1'1 + assign $0\main_libresocsim_converter1_counter[0:0] 1'0 + assign $0\builder_converter1_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7425.2-7427.5" + switch $or$ls180.v:7425$2405_Y + attribute \src "ls180.v:7425.6-7425.94" + case 1'1 + assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_libresoc_jtag_wb_dat_r + case + end + attribute \src "ls180.v:7429.2-7431.5" + switch \main_libresocsim_converter2_counter_converter2_next_value_ce + attribute \src "ls180.v:7429.6-7429.66" + case 1'1 + assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter_converter2_next_value + case + end + attribute \src "ls180.v:7432.2-7435.5" + switch \main_libresocsim_converter2_reset + attribute \src "ls180.v:7432.6-7432.39" + case 1'1 + assign $0\main_libresocsim_converter2_counter[0:0] 1'0 + assign $0\builder_converter2_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7436.2-7440.5" + switch $ne$ls180.v:7436$2406_Y + attribute \src "ls180.v:7436.6-7436.53" + case 1'1 + attribute \src "ls180.v:7437.3-7439.6" + switch \main_libresocsim_bus_error + attribute \src "ls180.v:7437.7-7437.33" + case 1'1 + assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7438$2407_Y + case + end + case + end + attribute \src "ls180.v:7442.2-7444.5" + switch $and$ls180.v:7442$2410_Y + attribute \src "ls180.v:7442.6-7442.103" + case 1'1 + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1 + case + end + attribute \src "ls180.v:7445.2-7453.5" + switch \main_libresocsim_en_storage + attribute \src "ls180.v:7445.6-7445.33" + case 1'1 + attribute \src "ls180.v:7446.3-7450.6" + switch $eq$ls180.v:7446$2411_Y + attribute \src "ls180.v:7446.7-7446.39" + case 1'1 + assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage + attribute \src "ls180.v:7448.7-7448.11" + case + assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7449$2412_Y + end + attribute \src "ls180.v:7451.6-7451.10" + case + assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage + end + attribute \src "ls180.v:7454.2-7456.5" + switch \main_libresocsim_update_value_re + attribute \src "ls180.v:7454.6-7454.38" + case 1'1 + assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value + case + end + attribute \src "ls180.v:7457.2-7459.5" + switch \main_libresocsim_zero_clear + attribute \src "ls180.v:7457.6-7457.33" + case 1'1 + assign $0\main_libresocsim_zero_pending[0:0] 1'0 + case + end + attribute \src "ls180.v:7461.2-7463.5" + switch $and$ls180.v:7461$2414_Y + attribute \src "ls180.v:7461.6-7461.76" + case 1'1 + assign $0\main_libresocsim_zero_pending[0:0] 1'1 + case + end + attribute \src "ls180.v:7468.2-7470.5" + switch \main_sdram_inti_p0_rddata_valid + attribute \src "ls180.v:7468.6-7468.37" + case 1'1 + assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata + case + end + attribute \src "ls180.v:7471.2-7475.5" + switch $and$ls180.v:7471$2416_Y + attribute \src "ls180.v:7471.6-7471.57" + case 1'1 + assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7472$2417_Y + attribute \src "ls180.v:7473.6-7473.10" + case + assign $0\main_sdram_timer_count1[9:0] 10'1100001101 + end + attribute \src "ls180.v:7477.2-7483.5" + switch \main_sdram_postponer_req_i + attribute \src "ls180.v:7477.6-7477.32" + case 1'1 + assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7478$2418_Y + attribute \src "ls180.v:7479.3-7482.6" + switch $eq$ls180.v:7479$2419_Y + attribute \src "ls180.v:7479.7-7479.43" + case 1'1 + assign $0\main_sdram_postponer_count[0:0] 1'0 + assign $0\main_sdram_postponer_req_o[0:0] 1'1 + case + end + case + end + attribute \src "ls180.v:7484.2-7492.5" + switch \main_sdram_sequencer_start0 + attribute \src "ls180.v:7484.6-7484.33" + case 1'1 + assign $0\main_sdram_sequencer_count[0:0] 1'0 + attribute \src "ls180.v:7486.6-7486.10" + case + attribute \src "ls180.v:7487.3-7491.6" + switch \main_sdram_sequencer_done1 + attribute \src "ls180.v:7487.7-7487.33" + case 1'1 + attribute \src "ls180.v:7488.4-7490.7" + switch $ne$ls180.v:7488$2420_Y + attribute \src "ls180.v:7488.8-7488.44" + case 1'1 + assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7489$2421_Y + case + end + case + end + end + attribute \src "ls180.v:7499.2-7505.5" + switch $and$ls180.v:7499$2423_Y + attribute \src "ls180.v:7499.6-7499.76" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_cmd_payload_we[0:0] 1'1 + case + end + attribute \src "ls180.v:7506.2-7512.5" + switch $eq$ls180.v:7506$2424_Y + attribute \src "ls180.v:7506.6-7506.44" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'1 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + case + end + attribute \src "ls180.v:7513.2-7520.5" + switch $eq$ls180.v:7513$2425_Y + attribute \src "ls180.v:7513.6-7513.44" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'1 + case + end + attribute \src "ls180.v:7521.2-7531.5" + switch $eq$ls180.v:7521$2426_Y + attribute \src "ls180.v:7521.6-7521.44" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] 4'0000 + attribute \src "ls180.v:7523.6-7523.10" + case + attribute \src "ls180.v:7524.3-7530.6" + switch $ne$ls180.v:7524$2427_Y + attribute \src "ls180.v:7524.7-7524.45" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7525$2428_Y + attribute \src "ls180.v:7526.7-7526.11" + case + attribute \src "ls180.v:7527.4-7529.7" + switch \main_sdram_sequencer_start1 + attribute \src "ls180.v:7527.8-7527.35" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] 4'0001 + case + end + end + end + attribute \src "ls180.v:7533.2-7540.5" + switch \main_sdram_bankmachine0_row_close + attribute \src "ls180.v:7533.6-7533.39" + case 1'1 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 + attribute \src "ls180.v:7535.6-7535.10" + case + attribute \src "ls180.v:7536.3-7539.6" + switch \main_sdram_bankmachine0_row_open + attribute \src "ls180.v:7536.7-7536.39" + case 1'1 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7541.2-7543.5" + switch $and$ls180.v:7541$2431_Y + attribute \src "ls180.v:7541.6-7541.191" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7542$2432_Y + case + end + attribute \src "ls180.v:7544.2-7546.5" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7544.6-7544.58" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7545$2433_Y + case + end + attribute \src "ls180.v:7547.2-7555.5" + switch $and$ls180.v:7547$2436_Y + attribute \src "ls180.v:7547.6-7547.191" + case 1'1 + attribute \src "ls180.v:7548.3-7550.6" + switch $not$ls180.v:7548$2437_Y + attribute \src "ls180.v:7548.7-7548.62" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7549$2438_Y + case + end + attribute \src "ls180.v:7551.6-7551.10" + case + attribute \src "ls180.v:7552.3-7554.6" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7552.7-7552.59" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7553$2439_Y + case + end + end + attribute \src "ls180.v:7556.2-7562.5" + switch $or$ls180.v:7556$2441_Y + attribute \src "ls180.v:7556.6-7556.108" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7563.2-7577.5" + switch \main_sdram_bankmachine0_twtpcon_valid + attribute \src "ls180.v:7563.6-7563.43" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7565.3-7569.6" + switch 1'0 + attribute \src "ls180.v:7567.7-7567.11" + case + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7570.6-7570.10" + case + attribute \src "ls180.v:7571.3-7576.6" + switch $not$ls180.v:7571$2442_Y + attribute \src "ls180.v:7571.7-7571.47" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7572$2443_Y + attribute \src "ls180.v:7573.4-7575.7" + switch $eq$ls180.v:7573$2444_Y + attribute \src "ls180.v:7573.8-7573.55" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7579.2-7586.5" + switch \main_sdram_bankmachine1_row_close + attribute \src "ls180.v:7579.6-7579.39" + case 1'1 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 + attribute \src "ls180.v:7581.6-7581.10" + case + attribute \src "ls180.v:7582.3-7585.6" + switch \main_sdram_bankmachine1_row_open + attribute \src "ls180.v:7582.7-7582.39" + case 1'1 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7587.2-7589.5" + switch $and$ls180.v:7587$2447_Y + attribute \src "ls180.v:7587.6-7587.191" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7588$2448_Y + case + end + attribute \src "ls180.v:7590.2-7592.5" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7590.6-7590.58" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7591$2449_Y + case + end + attribute \src "ls180.v:7593.2-7601.5" + switch $and$ls180.v:7593$2452_Y + attribute \src "ls180.v:7593.6-7593.191" + case 1'1 + attribute \src "ls180.v:7594.3-7596.6" + switch $not$ls180.v:7594$2453_Y + attribute \src "ls180.v:7594.7-7594.62" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7595$2454_Y + case + end + attribute \src "ls180.v:7597.6-7597.10" + case + attribute \src "ls180.v:7598.3-7600.6" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7598.7-7598.59" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7599$2455_Y + case + end + end + attribute \src "ls180.v:7602.2-7608.5" + switch $or$ls180.v:7602$2457_Y + attribute \src "ls180.v:7602.6-7602.108" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7609.2-7623.5" + switch \main_sdram_bankmachine1_twtpcon_valid + attribute \src "ls180.v:7609.6-7609.43" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7611.3-7615.6" + switch 1'0 + attribute \src "ls180.v:7613.7-7613.11" + case + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7616.6-7616.10" + case + attribute \src "ls180.v:7617.3-7622.6" + switch $not$ls180.v:7617$2458_Y + attribute \src "ls180.v:7617.7-7617.47" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7618$2459_Y + attribute \src "ls180.v:7619.4-7621.7" + switch $eq$ls180.v:7619$2460_Y + attribute \src "ls180.v:7619.8-7619.55" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7625.2-7632.5" + switch \main_sdram_bankmachine2_row_close + attribute \src "ls180.v:7625.6-7625.39" + case 1'1 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 + attribute \src "ls180.v:7627.6-7627.10" + case + attribute \src "ls180.v:7628.3-7631.6" + switch \main_sdram_bankmachine2_row_open + attribute \src "ls180.v:7628.7-7628.39" + case 1'1 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7633.2-7635.5" + switch $and$ls180.v:7633$2463_Y + attribute \src "ls180.v:7633.6-7633.191" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7634$2464_Y + case + end + attribute \src "ls180.v:7636.2-7638.5" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7636.6-7636.58" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7637$2465_Y + case + end + attribute \src "ls180.v:7639.2-7647.5" + switch $and$ls180.v:7639$2468_Y + attribute \src "ls180.v:7639.6-7639.191" + case 1'1 + attribute \src "ls180.v:7640.3-7642.6" + switch $not$ls180.v:7640$2469_Y + attribute \src "ls180.v:7640.7-7640.62" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7641$2470_Y + case + end + attribute \src "ls180.v:7643.6-7643.10" + case + attribute \src "ls180.v:7644.3-7646.6" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7644.7-7644.59" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7645$2471_Y + case + end + end + attribute \src "ls180.v:7648.2-7654.5" + switch $or$ls180.v:7648$2473_Y + attribute \src "ls180.v:7648.6-7648.108" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7655.2-7669.5" + switch \main_sdram_bankmachine2_twtpcon_valid + attribute \src "ls180.v:7655.6-7655.43" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7657.3-7661.6" + switch 1'0 + attribute \src "ls180.v:7659.7-7659.11" + case + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7662.6-7662.10" + case + attribute \src "ls180.v:7663.3-7668.6" + switch $not$ls180.v:7663$2474_Y + attribute \src "ls180.v:7663.7-7663.47" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7664$2475_Y + attribute \src "ls180.v:7665.4-7667.7" + switch $eq$ls180.v:7665$2476_Y + attribute \src "ls180.v:7665.8-7665.55" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7671.2-7678.5" + switch \main_sdram_bankmachine3_row_close + attribute \src "ls180.v:7671.6-7671.39" + case 1'1 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 + attribute \src "ls180.v:7673.6-7673.10" + case + attribute \src "ls180.v:7674.3-7677.6" + switch \main_sdram_bankmachine3_row_open + attribute \src "ls180.v:7674.7-7674.39" + case 1'1 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7679.2-7681.5" + switch $and$ls180.v:7679$2479_Y + attribute \src "ls180.v:7679.6-7679.191" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7680$2480_Y + case + end + attribute \src "ls180.v:7682.2-7684.5" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7682.6-7682.58" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7683$2481_Y + case + end + attribute \src "ls180.v:7685.2-7693.5" + switch $and$ls180.v:7685$2484_Y + attribute \src "ls180.v:7685.6-7685.191" + case 1'1 + attribute \src "ls180.v:7686.3-7688.6" + switch $not$ls180.v:7686$2485_Y + attribute \src "ls180.v:7686.7-7686.62" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7687$2486_Y + case + end + attribute \src "ls180.v:7689.6-7689.10" + case + attribute \src "ls180.v:7690.3-7692.6" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7690.7-7690.59" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7691$2487_Y + case + end + end + attribute \src "ls180.v:7694.2-7700.5" + switch $or$ls180.v:7694$2489_Y + attribute \src "ls180.v:7694.6-7694.108" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7701.2-7715.5" + switch \main_sdram_bankmachine3_twtpcon_valid + attribute \src "ls180.v:7701.6-7701.43" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7703.3-7707.6" + switch 1'0 + attribute \src "ls180.v:7705.7-7705.11" + case + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7708.6-7708.10" + case + attribute \src "ls180.v:7709.3-7714.6" + switch $not$ls180.v:7709$2490_Y + attribute \src "ls180.v:7709.7-7709.47" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7710$2491_Y + attribute \src "ls180.v:7711.4-7713.7" + switch $eq$ls180.v:7711$2492_Y + attribute \src "ls180.v:7711.8-7711.55" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7717.2-7723.5" + switch $not$ls180.v:7717$2493_Y + attribute \src "ls180.v:7717.6-7717.23" + case 1'1 + assign $0\main_sdram_time0[4:0] 5'11111 + attribute \src "ls180.v:7719.6-7719.10" + case + attribute \src "ls180.v:7720.3-7722.6" + switch $not$ls180.v:7720$2494_Y + attribute \src "ls180.v:7720.7-7720.30" + case 1'1 + assign $0\main_sdram_time0[4:0] $sub$ls180.v:7721$2495_Y + case + end + end + attribute \src "ls180.v:7724.2-7730.5" + switch $not$ls180.v:7724$2496_Y + attribute \src "ls180.v:7724.6-7724.23" + case 1'1 + assign $0\main_sdram_time1[3:0] 4'1111 + attribute \src "ls180.v:7726.6-7726.10" + case + attribute \src "ls180.v:7727.3-7729.6" + switch $not$ls180.v:7727$2497_Y + attribute \src "ls180.v:7727.7-7727.30" + case 1'1 + assign $0\main_sdram_time1[3:0] $sub$ls180.v:7728$2498_Y + case + end + end + attribute \src "ls180.v:7731.2-7786.5" + switch \main_sdram_choose_cmd_ce + attribute \src "ls180.v:7731.6-7731.30" + case 1'1 + attribute \src "ls180.v:7732.3-7785.10" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + attribute \src "ls180.v:7734.5-7744.8" + switch \main_sdram_choose_cmd_request [1] + attribute \src "ls180.v:7734.9-7734.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + attribute \src "ls180.v:7736.9-7736.13" + case + attribute \src "ls180.v:7737.6-7743.9" + switch \main_sdram_choose_cmd_request [2] + attribute \src "ls180.v:7737.10-7737.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + attribute \src "ls180.v:7739.10-7739.14" + case + attribute \src "ls180.v:7740.7-7742.10" + switch \main_sdram_choose_cmd_request [3] + attribute \src "ls180.v:7740.11-7740.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'01 + attribute \src "ls180.v:7747.5-7757.8" + switch \main_sdram_choose_cmd_request [2] + attribute \src "ls180.v:7747.9-7747.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + attribute \src "ls180.v:7749.9-7749.13" + case + attribute \src "ls180.v:7750.6-7756.9" + switch \main_sdram_choose_cmd_request [3] + attribute \src "ls180.v:7750.10-7750.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + attribute \src "ls180.v:7752.10-7752.14" + case + attribute \src "ls180.v:7753.7-7755.10" + switch \main_sdram_choose_cmd_request [0] + attribute \src "ls180.v:7753.11-7753.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + attribute \src "ls180.v:7760.5-7770.8" + switch \main_sdram_choose_cmd_request [3] + attribute \src "ls180.v:7760.9-7760.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + attribute \src "ls180.v:7762.9-7762.13" + case + attribute \src "ls180.v:7763.6-7769.9" + switch \main_sdram_choose_cmd_request [0] + attribute \src "ls180.v:7763.10-7763.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + attribute \src "ls180.v:7765.10-7765.14" + case + attribute \src "ls180.v:7766.7-7768.10" + switch \main_sdram_choose_cmd_request [1] + attribute \src "ls180.v:7766.11-7766.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + attribute \src "ls180.v:7773.5-7783.8" + switch \main_sdram_choose_cmd_request [0] + attribute \src "ls180.v:7773.9-7773.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + attribute \src "ls180.v:7775.9-7775.13" + case + attribute \src "ls180.v:7776.6-7782.9" + switch \main_sdram_choose_cmd_request [1] + attribute \src "ls180.v:7776.10-7776.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + attribute \src "ls180.v:7778.10-7778.14" + case + attribute \src "ls180.v:7779.7-7781.10" + switch \main_sdram_choose_cmd_request [2] + attribute \src "ls180.v:7779.11-7779.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + case + end + end + end + case + end + case + end + attribute \src "ls180.v:7787.2-7842.5" + switch \main_sdram_choose_req_ce + attribute \src "ls180.v:7787.6-7787.30" + case 1'1 + attribute \src "ls180.v:7788.3-7841.10" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + attribute \src "ls180.v:7790.5-7800.8" + switch \main_sdram_choose_req_request [1] + attribute \src "ls180.v:7790.9-7790.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + attribute \src "ls180.v:7792.9-7792.13" + case + attribute \src "ls180.v:7793.6-7799.9" + switch \main_sdram_choose_req_request [2] + attribute \src "ls180.v:7793.10-7793.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + attribute \src "ls180.v:7795.10-7795.14" + case + attribute \src "ls180.v:7796.7-7798.10" + switch \main_sdram_choose_req_request [3] + attribute \src "ls180.v:7796.11-7796.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'01 + attribute \src "ls180.v:7803.5-7813.8" + switch \main_sdram_choose_req_request [2] + attribute \src "ls180.v:7803.9-7803.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + attribute \src "ls180.v:7805.9-7805.13" + case + attribute \src "ls180.v:7806.6-7812.9" + switch \main_sdram_choose_req_request [3] + attribute \src "ls180.v:7806.10-7806.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + attribute \src "ls180.v:7808.10-7808.14" + case + attribute \src "ls180.v:7809.7-7811.10" + switch \main_sdram_choose_req_request [0] + attribute \src "ls180.v:7809.11-7809.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + attribute \src "ls180.v:7816.5-7826.8" + switch \main_sdram_choose_req_request [3] + attribute \src "ls180.v:7816.9-7816.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + attribute \src "ls180.v:7818.9-7818.13" + case + attribute \src "ls180.v:7819.6-7825.9" + switch \main_sdram_choose_req_request [0] + attribute \src "ls180.v:7819.10-7819.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + attribute \src "ls180.v:7821.10-7821.14" + case + attribute \src "ls180.v:7822.7-7824.10" + switch \main_sdram_choose_req_request [1] + attribute \src "ls180.v:7822.11-7822.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + attribute \src "ls180.v:7829.5-7839.8" + switch \main_sdram_choose_req_request [0] + attribute \src "ls180.v:7829.9-7829.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + attribute \src "ls180.v:7831.9-7831.13" + case + attribute \src "ls180.v:7832.6-7838.9" + switch \main_sdram_choose_req_request [1] + attribute \src "ls180.v:7832.10-7832.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + attribute \src "ls180.v:7834.10-7834.14" + case + attribute \src "ls180.v:7835.7-7837.10" + switch \main_sdram_choose_req_request [2] + attribute \src "ls180.v:7835.11-7835.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + case + end + end + end + case + end + case + end + attribute \src "ls180.v:7851.2-7865.5" + switch \main_sdram_tccdcon_valid + attribute \src "ls180.v:7851.6-7851.30" + case 1'1 + assign $0\main_sdram_tccdcon_count[0:0] 1'0 + attribute \src "ls180.v:7853.3-7857.6" + switch 1'1 + attribute \src "ls180.v:7853.7-7853.11" + case 1'1 + assign $0\main_sdram_tccdcon_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:7858.6-7858.10" + case + attribute \src "ls180.v:7859.3-7864.6" + switch $not$ls180.v:7859$2502_Y + attribute \src "ls180.v:7859.7-7859.34" + case 1'1 + assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:7860$2503_Y + attribute \src "ls180.v:7861.4-7863.7" + switch $eq$ls180.v:7861$2504_Y + attribute \src "ls180.v:7861.8-7861.42" + case 1'1 + assign $0\main_sdram_tccdcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7866.2-7880.5" + switch \main_sdram_twtrcon_valid + attribute \src "ls180.v:7866.6-7866.30" + case 1'1 + assign $0\main_sdram_twtrcon_count[2:0] 3'100 + attribute \src "ls180.v:7868.3-7872.6" + switch 1'0 + attribute \src "ls180.v:7870.7-7870.11" + case + assign $0\main_sdram_twtrcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7873.6-7873.10" + case + attribute \src "ls180.v:7874.3-7879.6" + switch $not$ls180.v:7874$2505_Y + attribute \src "ls180.v:7874.7-7874.34" + case 1'1 + assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:7875$2506_Y + attribute \src "ls180.v:7876.4-7878.7" + switch $eq$ls180.v:7876$2507_Y + attribute \src "ls180.v:7876.8-7876.42" + case 1'1 + assign $0\main_sdram_twtrcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7887.2-7889.5" + switch $or$ls180.v:7887$2532_Y + attribute \src "ls180.v:7887.6-7887.50" + case 1'1 + assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r + case + end + attribute \src "ls180.v:7891.2-7893.5" + switch \main_converter_counter_converter_next_value_ce + attribute \src "ls180.v:7891.6-7891.52" + case 1'1 + assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value + case + end + attribute \src "ls180.v:7894.2-7897.5" + switch \main_converter_reset + attribute \src "ls180.v:7894.6-7894.26" + case 1'1 + assign $0\main_converter_counter[0:0] 1'0 + assign $0\builder_converter_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7898.2-7908.5" + switch \main_litedram_wb_ack + attribute \src "ls180.v:7898.6-7898.26" + case 1'1 + assign $0\main_cmd_consumed[0:0] 1'0 + assign $0\main_wdata_consumed[0:0] 1'0 + attribute \src "ls180.v:7901.6-7901.10" + case + attribute \src "ls180.v:7902.3-7904.6" + switch $and$ls180.v:7902$2533_Y + attribute \src "ls180.v:7902.7-7902.50" + case 1'1 + assign $0\main_cmd_consumed[0:0] 1'1 + case + end + attribute \src "ls180.v:7905.3-7907.6" + switch $and$ls180.v:7905$2534_Y + attribute \src "ls180.v:7905.7-7905.54" + case 1'1 + assign $0\main_wdata_consumed[0:0] 1'1 + case + end + end + attribute \src "ls180.v:7910.2-7931.5" + switch $and$ls180.v:7910$2538_Y + attribute \src "ls180.v:7910.6-7910.64" + case 1'1 + assign $0\main_tx_reg[7:0] \main_sink_payload_data + assign $0\main_tx_bitcount[3:0] 4'0000 + assign $0\main_tx_busy[0:0] 1'1 + assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'0 + attribute \src "ls180.v:7915.6-7915.10" + case + attribute \src "ls180.v:7916.3-7930.6" + switch $and$ls180.v:7916$2539_Y + attribute \src "ls180.v:7916.7-7916.42" + case 1'1 + assign $0\main_tx_bitcount[3:0] $add$ls180.v:7917$2540_Y + attribute \src "ls180.v:7918.4-7929.7" + switch $eq$ls180.v:7918$2541_Y + attribute \src "ls180.v:7918.8-7918.34" + case 1'1 + assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1 + attribute \src "ls180.v:7920.8-7920.12" + case + attribute \src "ls180.v:7921.5-7928.8" + switch $eq$ls180.v:7921$2542_Y + attribute \src "ls180.v:7921.9-7921.35" + case 1'1 + assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1 + assign $0\main_tx_busy[0:0] 1'0 + assign $0\main_sink_ready[0:0] 1'1 + attribute \src "ls180.v:7925.9-7925.13" + case + assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] \main_tx_reg [0] + assign $0\main_tx_reg[7:0] { 1'0 \main_tx_reg [7:1] } + end + end + case + end + end + attribute \src "ls180.v:7932.2-7936.5" + switch \main_tx_busy + attribute \src "ls180.v:7932.6-7932.18" + case 1'1 + assign { $0\main_uart_clk_txen[0:0] $0\main_phase_accumulator_tx[31:0] } $add$ls180.v:7933$2543_Y + attribute \src "ls180.v:7934.6-7934.10" + case + assign { $0\main_uart_clk_txen[0:0] $0\main_phase_accumulator_tx[31:0] } { 1'0 \main_storage } + end + attribute \src "ls180.v:7939.2-7963.5" + switch $not$ls180.v:7939$2544_Y + attribute \src "ls180.v:7939.6-7939.21" + case 1'1 + attribute \src "ls180.v:7940.3-7943.6" + switch $and$ls180.v:7940$2546_Y + attribute \src "ls180.v:7940.7-7940.31" + case 1'1 + assign $0\main_rx_busy[0:0] 1'1 + assign $0\main_rx_bitcount[3:0] 4'0000 + case + end + attribute \src "ls180.v:7944.6-7944.10" + case + attribute \src "ls180.v:7945.3-7962.6" + switch \main_uart_clk_rxen + attribute \src "ls180.v:7945.7-7945.25" + case 1'1 + assign $0\main_rx_bitcount[3:0] $add$ls180.v:7946$2547_Y + attribute \src "ls180.v:7947.4-7961.7" + switch $eq$ls180.v:7947$2548_Y + attribute \src "ls180.v:7947.8-7947.34" + case 1'1 + attribute \src "ls180.v:7948.5-7950.8" + switch \main_rx + attribute \src "ls180.v:7948.9-7948.16" + case 1'1 + assign $0\main_rx_busy[0:0] 1'0 + case + end + attribute \src "ls180.v:7951.8-7951.12" + case + attribute \src "ls180.v:7952.5-7960.8" + switch $eq$ls180.v:7952$2549_Y + attribute \src "ls180.v:7952.9-7952.35" + case 1'1 + assign $0\main_rx_busy[0:0] 1'0 + attribute \src "ls180.v:7954.6-7957.9" + switch \main_rx + attribute \src "ls180.v:7954.10-7954.17" + case 1'1 + assign $0\main_source_payload_data[7:0] \main_rx_reg + assign $0\main_source_valid[0:0] 1'1 + case + end + attribute \src "ls180.v:7958.9-7958.13" + case + assign $0\main_rx_reg[7:0] { \main_rx \main_rx_reg [7:1] } + end + end + case + end + end + attribute \src "ls180.v:7964.2-7968.5" + switch \main_rx_busy + attribute \src "ls180.v:7964.6-7964.18" + case 1'1 + assign { $0\main_uart_clk_rxen[0:0] $0\main_phase_accumulator_rx[31:0] } $add$ls180.v:7965$2550_Y + attribute \src "ls180.v:7966.6-7966.10" + case + assign { $0\main_uart_clk_rxen[0:0] $0\main_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 + end + attribute \src "ls180.v:7969.2-7971.5" + switch \main_uart_tx_clear + attribute \src "ls180.v:7969.6-7969.24" + case 1'1 + assign $0\main_uart_tx_pending[0:0] 1'0 + case + end + attribute \src "ls180.v:7973.2-7975.5" + switch $and$ls180.v:7973$2552_Y + attribute \src "ls180.v:7973.6-7973.58" + case 1'1 + assign $0\main_uart_tx_pending[0:0] 1'1 + case + end + attribute \src "ls180.v:7976.2-7978.5" + switch \main_uart_rx_clear + attribute \src "ls180.v:7976.6-7976.24" + case 1'1 + assign $0\main_uart_rx_pending[0:0] 1'0 + case + end + attribute \src "ls180.v:7980.2-7982.5" + switch $and$ls180.v:7980$2554_Y + attribute \src "ls180.v:7980.6-7980.58" + case 1'1 + assign $0\main_uart_rx_pending[0:0] 1'1 + case + end + attribute \src "ls180.v:7983.2-7989.5" + switch \main_uart_tx_fifo_syncfifo_re + attribute \src "ls180.v:7983.6-7983.35" + case 1'1 + assign $0\main_uart_tx_fifo_readable[0:0] 1'1 + attribute \src "ls180.v:7985.6-7985.10" + case + attribute \src "ls180.v:7986.3-7988.6" + switch \main_uart_tx_fifo_re + attribute \src "ls180.v:7986.7-7986.27" + case 1'1 + assign $0\main_uart_tx_fifo_readable[0:0] 1'0 + case + end + end + attribute \src "ls180.v:7990.2-7992.5" + switch $and$ls180.v:7990$2557_Y + attribute \src "ls180.v:7990.6-7990.108" + case 1'1 + assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:7991$2558_Y + case + end + attribute \src "ls180.v:7993.2-7995.5" + switch \main_uart_tx_fifo_do_read + attribute \src "ls180.v:7993.6-7993.31" + case 1'1 + assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:7994$2559_Y + case + end + attribute \src "ls180.v:7996.2-8004.5" + switch $and$ls180.v:7996$2562_Y + attribute \src "ls180.v:7996.6-7996.108" + case 1'1 + attribute \src "ls180.v:7997.3-7999.6" + switch $not$ls180.v:7997$2563_Y + attribute \src "ls180.v:7997.7-7997.35" + case 1'1 + assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:7998$2564_Y + case + end + attribute \src "ls180.v:8000.6-8000.10" + case + attribute \src "ls180.v:8001.3-8003.6" + switch \main_uart_tx_fifo_do_read + attribute \src "ls180.v:8001.7-8001.32" + case 1'1 + assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8002$2565_Y + case + end + end + attribute \src "ls180.v:8005.2-8011.5" + switch \main_uart_rx_fifo_syncfifo_re + attribute \src "ls180.v:8005.6-8005.35" + case 1'1 + assign $0\main_uart_rx_fifo_readable[0:0] 1'1 + attribute \src "ls180.v:8007.6-8007.10" + case + attribute \src "ls180.v:8008.3-8010.6" + switch \main_uart_rx_fifo_re + attribute \src "ls180.v:8008.7-8008.27" + case 1'1 + assign $0\main_uart_rx_fifo_readable[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8012.2-8014.5" + switch $and$ls180.v:8012$2568_Y + attribute \src "ls180.v:8012.6-8012.108" + case 1'1 + assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8013$2569_Y + case + end + attribute \src "ls180.v:8015.2-8017.5" + switch \main_uart_rx_fifo_do_read + attribute \src "ls180.v:8015.6-8015.31" + case 1'1 + assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8016$2570_Y + case + end + attribute \src "ls180.v:8018.2-8026.5" + switch $and$ls180.v:8018$2573_Y + attribute \src "ls180.v:8018.6-8018.108" + case 1'1 + attribute \src "ls180.v:8019.3-8021.6" + switch $not$ls180.v:8019$2574_Y + attribute \src "ls180.v:8019.7-8019.35" + case 1'1 + assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8020$2575_Y + case + end + attribute \src "ls180.v:8022.6-8022.10" + case + attribute \src "ls180.v:8023.3-8025.6" + switch \main_uart_rx_fifo_do_read + attribute \src "ls180.v:8023.7-8023.32" + case 1'1 + assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8024$2576_Y + case + end + end + attribute \src "ls180.v:8027.2-8040.5" + switch \main_uart_reset + attribute \src "ls180.v:8027.6-8027.21" + case 1'1 + assign $0\main_uart_tx_pending[0:0] 1'0 + assign $0\main_uart_tx_old_trigger[0:0] 1'0 + assign $0\main_uart_rx_pending[0:0] 1'0 + assign $0\main_uart_rx_old_trigger[0:0] 1'0 + assign $0\main_uart_tx_fifo_readable[0:0] 1'0 + assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 + assign $0\main_uart_rx_fifo_readable[0:0] 1'0 + assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 + case + end + attribute \src "ls180.v:8042.2-8049.5" + switch \main_spi_master_clk_rise + attribute \src "ls180.v:8042.6-8042.30" + case 1'1 + assign $0\spi_master_clk[0:0] \main_spi_master_clk_enable + attribute \src "ls180.v:8044.6-8044.10" + case + attribute \src "ls180.v:8045.3-8048.6" + switch \main_spi_master_clk_fall + attribute \src "ls180.v:8045.7-8045.31" + case 1'1 + assign $0\main_spi_master_clk_divider1[15:0] 16'0000000000000000 + assign $0\spi_master_clk[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8051.2-8061.5" + switch \main_spi_master_mosi_latch + attribute \src "ls180.v:8051.6-8051.32" + case 1'1 + assign $0\main_spi_master_mosi_data[7:0] \main_spi_master_mosi + assign $0\main_spi_master_mosi_sel[2:0] 3'111 + attribute \src "ls180.v:8054.6-8054.10" + case + attribute \src "ls180.v:8055.3-8060.6" + switch \main_spi_master_clk_fall + attribute \src "ls180.v:8055.7-8055.31" + case 1'1 + assign $0\main_spi_master_mosi_sel[2:0] $sub$ls180.v:8059$2581_Y + attribute \src "ls180.v:8056.4-8058.7" + switch \main_spi_master_cs_enable + attribute \src "ls180.v:8056.8-8056.33" + case 1'1 + assign $0\spi_master_mosi[0:0] \builder_sync_f_array_muxed0 + case + end + case + end + end + attribute \src "ls180.v:8062.2-8068.5" + switch \main_spi_master_clk_rise + attribute \src "ls180.v:8062.6-8062.30" + case 1'1 + attribute \src "ls180.v:8063.3-8067.6" + switch \main_spi_master_loopback + attribute \src "ls180.v:8063.7-8063.31" + case 1'1 + assign $0\main_spi_master_miso_data[7:0] { \main_spi_master_miso_data [6:0] \spi_master_mosi } + attribute \src "ls180.v:8065.7-8065.11" + case + assign $0\main_spi_master_miso_data[7:0] { \main_spi_master_miso_data [6:0] \spi_master_miso } + end + case + end + attribute \src "ls180.v:8069.2-8071.5" + switch \main_spi_master_miso_latch + attribute \src "ls180.v:8069.6-8069.32" + case 1'1 + assign $0\main_spi_master_miso[7:0] \main_spi_master_miso_data + case + end + attribute \src "ls180.v:8073.2-8075.5" + switch \main_spi_master_count_spimaster0_next_value_ce + attribute \src "ls180.v:8073.6-8073.52" + case 1'1 + assign $0\main_spi_master_count[2:0] \main_spi_master_count_spimaster0_next_value + case + end + attribute \src "ls180.v:8076.2-8089.5" + switch \main_pwm0_enable + attribute \src "ls180.v:8076.6-8076.22" + case 1'1 + assign $0\main_pwm0_counter[31:0] $add$ls180.v:8077$2582_Y + attribute \src "ls180.v:8078.3-8082.6" + switch $lt$ls180.v:8078$2583_Y + attribute \src "ls180.v:8078.7-8078.44" + case 1'1 + assign $0\pwm0[0:0] 1'1 + attribute \src "ls180.v:8080.7-8080.11" + case + assign $0\pwm0[0:0] 1'0 + end + attribute \src "ls180.v:8083.3-8085.6" + switch $ge$ls180.v:8083$2585_Y + attribute \src "ls180.v:8083.7-8083.55" + case 1'1 + assign $0\main_pwm0_counter[31:0] 0 + case + end + attribute \src "ls180.v:8086.6-8086.10" + case + assign $0\main_pwm0_counter[31:0] 0 + assign $0\pwm0[0:0] 1'0 + end + attribute \src "ls180.v:8090.2-8103.5" + switch \main_pwm1_enable + attribute \src "ls180.v:8090.6-8090.22" + case 1'1 + assign $0\main_pwm1_counter[31:0] $add$ls180.v:8091$2586_Y + attribute \src "ls180.v:8092.3-8096.6" + switch $lt$ls180.v:8092$2587_Y + attribute \src "ls180.v:8092.7-8092.44" + case 1'1 + assign $0\pwm1[0:0] 1'1 + attribute \src "ls180.v:8094.7-8094.11" + case + assign $0\pwm1[0:0] 1'0 + end + attribute \src "ls180.v:8097.3-8099.6" + switch $ge$ls180.v:8097$2589_Y + attribute \src "ls180.v:8097.7-8097.55" + case 1'1 + assign $0\main_pwm1_counter[31:0] 0 + case + end + attribute \src "ls180.v:8100.6-8100.10" + case + assign $0\main_pwm1_counter[31:0] 0 + assign $0\pwm1[0:0] 1'0 + end + attribute \src "ls180.v:8104.2-8106.5" + switch $not$ls180.v:8104$2590_Y + attribute \src "ls180.v:8104.6-8104.32" + case 1'1 + assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8105$2591_Y + case + end + attribute \src "ls180.v:8110.2-8112.5" + switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce + attribute \src "ls180.v:8110.6-8110.57" + case 1'1 + assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value + case + end + attribute \src "ls180.v:8114.2-8116.5" + switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce + attribute \src "ls180.v:8114.6-8114.57" + case 1'1 + assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value + case + end + attribute \src "ls180.v:8117.2-8119.5" + switch \main_sdphy_cmdr_cmdr_pads_in_valid + attribute \src "ls180.v:8117.6-8117.40" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8118$2592_Y + case + end + attribute \src "ls180.v:8120.2-8122.5" + switch \main_sdphy_cmdr_cmdr_converter_source_ready + attribute \src "ls180.v:8120.6-8120.49" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8123.2-8130.5" + switch \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:8123.6-8123.46" + case 1'1 + attribute \src "ls180.v:8124.3-8129.6" + switch $or$ls180.v:8124$2594_Y + attribute \src "ls180.v:8124.7-8124.98" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8127.7-8127.11" + case + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8128$2595_Y + end + case + end + attribute \src "ls180.v:8131.2-8144.5" + switch $and$ls180.v:8131$2596_Y + attribute \src "ls180.v:8131.6-8131.97" + case 1'1 + attribute \src "ls180.v:8132.3-8138.6" + switch $and$ls180.v:8132$2597_Y + attribute \src "ls180.v:8132.7-8132.94" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last + attribute \src "ls180.v:8135.7-8135.11" + case + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8139.6-8139.10" + case + attribute \src "ls180.v:8140.3-8143.6" + switch $and$ls180.v:8140$2598_Y + attribute \src "ls180.v:8140.7-8140.94" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8141$2599_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8142$2600_Y + case + end + end + attribute \src "ls180.v:8145.2-8172.5" + switch \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:8145.6-8145.46" + case 1'1 + attribute \src "ls180.v:8146.3-8171.10" + switch \main_sdphy_cmdr_cmdr_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [7] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [6] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [5] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [4] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [3] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [2] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [1] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [0] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8173.2-8175.5" + switch \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:8173.6-8173.46" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8174$2601_Y + case + end + attribute \src "ls180.v:8176.2-8181.5" + switch $or$ls180.v:8176$2603_Y + attribute \src "ls180.v:8176.6-8176.88" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid + assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first + assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_sink_last + assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data + case + end + attribute \src "ls180.v:8182.2-8187.5" + switch \main_sdphy_cmdr_cmdr_reset + attribute \src "ls180.v:8182.6-8182.32" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 + case + end + attribute \src "ls180.v:8189.2-8191.5" + switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 + attribute \src "ls180.v:8189.6-8189.58" + case 1'1 + assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 + case + end + attribute \src "ls180.v:8192.2-8194.5" + switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 + attribute \src "ls180.v:8192.6-8192.60" + case 1'1 + assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 + case + end + attribute \src "ls180.v:8195.2-8197.5" + switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 + attribute \src "ls180.v:8195.6-8195.63" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 + case + end + attribute \src "ls180.v:8198.2-8200.5" + switch \main_sdphy_dataw_crcr_pads_in_valid + attribute \src "ls180.v:8198.6-8198.41" + case 1'1 + assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8199$2604_Y + case + end + attribute \src "ls180.v:8201.2-8203.5" + switch \main_sdphy_dataw_crcr_converter_source_ready + attribute \src "ls180.v:8201.6-8201.50" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8204.2-8211.5" + switch \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:8204.6-8204.47" + case 1'1 + attribute \src "ls180.v:8205.3-8210.6" + switch $or$ls180.v:8205$2606_Y + attribute \src "ls180.v:8205.7-8205.100" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8208.7-8208.11" + case + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8209$2607_Y + end + case + end + attribute \src "ls180.v:8212.2-8225.5" + switch $and$ls180.v:8212$2608_Y + attribute \src "ls180.v:8212.6-8212.99" + case 1'1 + attribute \src "ls180.v:8213.3-8219.6" + switch $and$ls180.v:8213$2609_Y + attribute \src "ls180.v:8213.7-8213.96" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last + attribute \src "ls180.v:8216.7-8216.11" + case + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8220.6-8220.10" + case + attribute \src "ls180.v:8221.3-8224.6" + switch $and$ls180.v:8221$2610_Y + attribute \src "ls180.v:8221.7-8221.96" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8222$2611_Y + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8223$2612_Y + case + end + end + attribute \src "ls180.v:8226.2-8253.5" + switch \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:8226.6-8226.47" + case 1'1 + attribute \src "ls180.v:8227.3-8252.10" + switch \main_sdphy_dataw_crcr_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [7] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [6] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [5] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [4] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [3] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [2] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [1] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [0] \main_sdphy_dataw_crcr_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8254.2-8256.5" + switch \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:8254.6-8254.47" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8255$2613_Y + case + end + attribute \src "ls180.v:8257.2-8262.5" + switch $or$ls180.v:8257$2615_Y + attribute \src "ls180.v:8257.6-8257.90" + case 1'1 + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid + assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first + assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_sink_last + assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data + case + end + attribute \src "ls180.v:8263.2-8268.5" + switch \main_sdphy_dataw_crcr_reset + attribute \src "ls180.v:8263.6-8263.33" + case 1'1 + assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 + case + end + attribute \src "ls180.v:8270.2-8272.5" + switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce + attribute \src "ls180.v:8270.6-8270.63" + case 1'1 + assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value + case + end + attribute \src "ls180.v:8274.2-8276.5" + switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce + attribute \src "ls180.v:8274.6-8274.52" + case 1'1 + assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value + case + end + attribute \src "ls180.v:8277.2-8279.5" + switch \main_sdphy_datar_datar_pads_in_valid + attribute \src "ls180.v:8277.6-8277.42" + case 1'1 + assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8278$2616_Y + case + end + attribute \src "ls180.v:8280.2-8282.5" + switch \main_sdphy_datar_datar_converter_source_ready + attribute \src "ls180.v:8280.6-8280.51" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8283.2-8290.5" + switch \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:8283.6-8283.48" + case 1'1 + attribute \src "ls180.v:8284.3-8289.6" + switch $or$ls180.v:8284$2618_Y + attribute \src "ls180.v:8284.7-8284.102" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8287.7-8287.11" + case + assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8288$2619_Y + end + case + end + attribute \src "ls180.v:8291.2-8304.5" + switch $and$ls180.v:8291$2620_Y + attribute \src "ls180.v:8291.6-8291.101" + case 1'1 + attribute \src "ls180.v:8292.3-8298.6" + switch $and$ls180.v:8292$2621_Y + attribute \src "ls180.v:8292.7-8292.98" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last + attribute \src "ls180.v:8295.7-8295.11" + case + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8299.6-8299.10" + case + attribute \src "ls180.v:8300.3-8303.6" + switch $and$ls180.v:8300$2622_Y + attribute \src "ls180.v:8300.7-8300.98" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8301$2623_Y + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8302$2624_Y + case + end + end + attribute \src "ls180.v:8305.2-8314.5" + switch \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:8305.6-8305.48" + case 1'1 + attribute \src "ls180.v:8306.3-8313.10" + switch \main_sdphy_datar_datar_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [7:4] \main_sdphy_datar_datar_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [3:0] \main_sdphy_datar_datar_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8315.2-8317.5" + switch \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:8315.6-8315.48" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8316$2625_Y + case + end + attribute \src "ls180.v:8318.2-8323.5" + switch $or$ls180.v:8318$2627_Y + attribute \src "ls180.v:8318.6-8318.92" + case 1'1 + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid + assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first + assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_sink_last + assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data + case + end + attribute \src "ls180.v:8324.2-8329.5" + switch \main_sdphy_datar_datar_reset + attribute \src "ls180.v:8324.6-8324.34" + case 1'1 + assign $0\main_sdphy_datar_datar_run[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 + case + end + attribute \src "ls180.v:8331.2-8333.5" + switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 + attribute \src "ls180.v:8331.6-8331.60" + case 1'1 + assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 + case + end + attribute \src "ls180.v:8334.2-8336.5" + switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 + attribute \src "ls180.v:8334.6-8334.62" + case 1'1 + assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 + case + end + attribute \src "ls180.v:8337.2-8339.5" + switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 + attribute \src "ls180.v:8337.6-8337.66" + case 1'1 + assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 + case + end + attribute \src "ls180.v:8340.2-8346.5" + switch \main_sdcore_crc7_inserter_clr + attribute \src "ls180.v:8340.6-8340.35" + case 1'1 + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + attribute \src "ls180.v:8342.6-8342.10" + case + attribute \src "ls180.v:8343.3-8345.6" + switch \main_sdcore_crc7_inserter_enable + attribute \src "ls180.v:8343.7-8343.39" + case 1'1 + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40 + case + end + end + attribute \src "ls180.v:8347.2-8353.5" + switch \main_sdcore_crc16_inserter_crc0_clr + attribute \src "ls180.v:8347.6-8347.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8349.6-8349.10" + case + attribute \src "ls180.v:8350.3-8352.6" + switch \main_sdcore_crc16_inserter_crc0_enable + attribute \src "ls180.v:8350.7-8350.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 + case + end + end + attribute \src "ls180.v:8354.2-8360.5" + switch \main_sdcore_crc16_inserter_crc1_clr + attribute \src "ls180.v:8354.6-8354.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8356.6-8356.10" + case + attribute \src "ls180.v:8357.3-8359.6" + switch \main_sdcore_crc16_inserter_crc1_enable + attribute \src "ls180.v:8357.7-8357.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 + case + end + end + attribute \src "ls180.v:8361.2-8367.5" + switch \main_sdcore_crc16_inserter_crc2_clr + attribute \src "ls180.v:8361.6-8361.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8363.6-8363.10" + case + attribute \src "ls180.v:8364.3-8366.6" + switch \main_sdcore_crc16_inserter_crc2_enable + attribute \src "ls180.v:8364.7-8364.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 + case + end + end + attribute \src "ls180.v:8368.2-8374.5" + switch \main_sdcore_crc16_inserter_crc3_clr + attribute \src "ls180.v:8368.6-8368.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8370.6-8370.10" + case + attribute \src "ls180.v:8371.3-8373.6" + switch \main_sdcore_crc16_inserter_crc3_enable + attribute \src "ls180.v:8371.7-8371.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 + case + end + end + attribute \src "ls180.v:8376.2-8378.5" + switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 + attribute \src "ls180.v:8376.6-8376.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 + case + end + attribute \src "ls180.v:8379.2-8381.5" + switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 + attribute \src "ls180.v:8379.6-8379.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 + case + end + attribute \src "ls180.v:8382.2-8384.5" + switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 + attribute \src "ls180.v:8382.6-8382.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 + case + end + attribute \src "ls180.v:8385.2-8387.5" + switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 + attribute \src "ls180.v:8385.6-8385.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 + case + end + attribute \src "ls180.v:8388.2-8390.5" + switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 + attribute \src "ls180.v:8388.6-8388.78" + case 1'1 + assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 + case + end + attribute \src "ls180.v:8391.2-8393.5" + switch $and$ls180.v:8391$2628_Y + attribute \src "ls180.v:8391.6-8391.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc + case + end + attribute \src "ls180.v:8394.2-8396.5" + switch $and$ls180.v:8394$2629_Y + attribute \src "ls180.v:8394.6-8394.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc + case + end + attribute \src "ls180.v:8397.2-8399.5" + switch $and$ls180.v:8397$2630_Y + attribute \src "ls180.v:8397.6-8397.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc + case + end + attribute \src "ls180.v:8400.2-8402.5" + switch $and$ls180.v:8400$2631_Y + attribute \src "ls180.v:8400.6-8400.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc + case + end + attribute \src "ls180.v:8403.2-8407.5" + switch $and$ls180.v:8403$2632_Y + attribute \src "ls180.v:8403.6-8403.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] } + assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12] + case + end + attribute \src "ls180.v:8408.2-8412.5" + switch $and$ls180.v:8408$2633_Y + attribute \src "ls180.v:8408.6-8408.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] } + assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12] + case + end + attribute \src "ls180.v:8413.2-8417.5" + switch $and$ls180.v:8413$2634_Y + attribute \src "ls180.v:8413.6-8413.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] } + assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12] + case + end + attribute \src "ls180.v:8418.2-8422.5" + switch $and$ls180.v:8418$2635_Y + attribute \src "ls180.v:8418.6-8418.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] } + assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12] + case + end + attribute \src "ls180.v:8423.2-8431.5" + switch $and$ls180.v:8423$2636_Y + attribute \src "ls180.v:8423.6-8423.83" + case 1'1 + attribute \src "ls180.v:8424.3-8430.6" + switch \main_sdcore_crc16_checker_sink_last + attribute \src "ls180.v:8424.7-8424.42" + case 1'1 + assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 + attribute \src "ls180.v:8426.7-8426.11" + case + attribute \src "ls180.v:8427.4-8429.7" + switch $ne$ls180.v:8427$2637_Y + attribute \src "ls180.v:8427.8-8427.48" + case 1'1 + assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8428$2638_Y + case + end + end + case + end + attribute \src "ls180.v:8432.2-8438.5" + switch \main_sdcore_crc16_checker_crc0_clr + attribute \src "ls180.v:8432.6-8432.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8434.6-8434.10" + case + attribute \src "ls180.v:8435.3-8437.6" + switch \main_sdcore_crc16_checker_crc0_enable + attribute \src "ls180.v:8435.7-8435.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 + case + end + end + attribute \src "ls180.v:8439.2-8445.5" + switch \main_sdcore_crc16_checker_crc1_clr + attribute \src "ls180.v:8439.6-8439.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8441.6-8441.10" + case + attribute \src "ls180.v:8442.3-8444.6" + switch \main_sdcore_crc16_checker_crc1_enable + attribute \src "ls180.v:8442.7-8442.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 + case + end + end + attribute \src "ls180.v:8446.2-8452.5" + switch \main_sdcore_crc16_checker_crc2_clr + attribute \src "ls180.v:8446.6-8446.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8448.6-8448.10" + case + attribute \src "ls180.v:8449.3-8451.6" + switch \main_sdcore_crc16_checker_crc2_enable + attribute \src "ls180.v:8449.7-8449.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 + case + end + end + attribute \src "ls180.v:8453.2-8459.5" + switch \main_sdcore_crc16_checker_crc3_clr + attribute \src "ls180.v:8453.6-8453.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8455.6-8455.10" + case + attribute \src "ls180.v:8456.3-8458.6" + switch \main_sdcore_crc16_checker_crc3_enable + attribute \src "ls180.v:8456.7-8456.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 + case + end + end + attribute \src "ls180.v:8461.2-8463.5" + switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 + attribute \src "ls180.v:8461.6-8461.52" + case 1'1 + assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0 + case + end + attribute \src "ls180.v:8464.2-8466.5" + switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1 + attribute \src "ls180.v:8464.6-8464.53" + case 1'1 + assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1 + case + end + attribute \src "ls180.v:8467.2-8469.5" + switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 + attribute \src "ls180.v:8467.6-8467.53" + case 1'1 + assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2 + case + end + attribute \src "ls180.v:8470.2-8472.5" + switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3 + attribute \src "ls180.v:8470.6-8470.54" + case 1'1 + assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3 + case + end + attribute \src "ls180.v:8473.2-8475.5" + switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 + attribute \src "ls180.v:8473.6-8473.53" + case 1'1 + assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4 + case + end + attribute \src "ls180.v:8476.2-8478.5" + switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 + attribute \src "ls180.v:8476.6-8476.55" + case 1'1 + assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 + case + end + attribute \src "ls180.v:8479.2-8481.5" + switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6 + attribute \src "ls180.v:8479.6-8479.54" + case 1'1 + assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6 + case + end + attribute \src "ls180.v:8482.2-8484.5" + switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 + attribute \src "ls180.v:8482.6-8482.56" + case 1'1 + assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7 + case + end + attribute \src "ls180.v:8485.2-8487.5" + switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 + attribute \src "ls180.v:8485.6-8485.63" + case 1'1 + assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 + case + end + attribute \src "ls180.v:8488.2-8490.5" + switch $and$ls180.v:8488$2641_Y + attribute \src "ls180.v:8488.6-8488.120" + case 1'1 + assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8489$2642_Y + case + end + attribute \src "ls180.v:8491.2-8493.5" + switch \main_sdblock2mem_fifo_do_read + attribute \src "ls180.v:8491.6-8491.35" + case 1'1 + assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8492$2643_Y + case + end + attribute \src "ls180.v:8494.2-8502.5" + switch $and$ls180.v:8494$2646_Y + attribute \src "ls180.v:8494.6-8494.120" + case 1'1 + attribute \src "ls180.v:8495.3-8497.6" + switch $not$ls180.v:8495$2647_Y + attribute \src "ls180.v:8495.7-8495.39" + case 1'1 + assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8496$2648_Y + case + end + attribute \src "ls180.v:8498.6-8498.10" + case + attribute \src "ls180.v:8499.3-8501.6" + switch \main_sdblock2mem_fifo_do_read + attribute \src "ls180.v:8499.7-8499.36" + case 1'1 + assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8500$2649_Y + case + end + end + attribute \src "ls180.v:8503.2-8505.5" + switch \main_sdblock2mem_converter_source_ready + attribute \src "ls180.v:8503.6-8503.45" + case 1'1 + assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8506.2-8513.5" + switch \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:8506.6-8506.42" + case 1'1 + attribute \src "ls180.v:8507.3-8512.6" + switch $or$ls180.v:8507$2651_Y + attribute \src "ls180.v:8507.7-8507.90" + case 1'1 + assign $0\main_sdblock2mem_converter_demux[1:0] 2'00 + assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8510.7-8510.11" + case + assign $0\main_sdblock2mem_converter_demux[1:0] $add$ls180.v:8511$2652_Y + end + case + end + attribute \src "ls180.v:8514.2-8527.5" + switch $and$ls180.v:8514$2653_Y + attribute \src "ls180.v:8514.6-8514.89" + case 1'1 + attribute \src "ls180.v:8515.3-8521.6" + switch $and$ls180.v:8515$2654_Y + attribute \src "ls180.v:8515.7-8515.86" + case 1'1 + assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first + assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last + attribute \src "ls180.v:8518.7-8518.11" + case + assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0 + assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8522.6-8522.10" + case + attribute \src "ls180.v:8523.3-8526.6" + switch $and$ls180.v:8523$2655_Y + attribute \src "ls180.v:8523.7-8523.86" + case 1'1 + assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8524$2656_Y + assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8525$2657_Y + case + end + end + attribute \src "ls180.v:8528.2-8543.5" + switch \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:8528.6-8528.42" + case 1'1 + attribute \src "ls180.v:8529.3-8542.10" + switch \main_sdblock2mem_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [31:24] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [23:16] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [15:8] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [7:0] \main_sdblock2mem_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8544.2-8546.5" + switch \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:8544.6-8544.42" + case 1'1 + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$ls180.v:8545$2658_Y + case + end + attribute \src "ls180.v:8548.2-8550.5" + switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce + attribute \src "ls180.v:8548.6-8548.76" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value + case + end + attribute \src "ls180.v:8551.2-8554.5" + switch \main_sdblock2mem_wishbonedmawriter_reset + attribute \src "ls180.v:8551.6-8551.46" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + assign $0\builder_sdblock2memdma_state[1:0] 2'00 + case + end + attribute \src "ls180.v:8556.2-8558.5" + switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce + attribute \src "ls180.v:8556.6-8556.64" + case 1'1 + assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + case + end + attribute \src "ls180.v:8560.2-8562.5" + switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce + attribute \src "ls180.v:8560.6-8560.76" + case 1'1 + assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value + case + end + attribute \src "ls180.v:8563.2-8566.5" + switch \main_sdmem2block_dma_reset + attribute \src "ls180.v:8563.6-8563.32" + case 1'1 + assign $0\main_sdmem2block_dma_offset[31:0] 0 + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + case + end + attribute \src "ls180.v:8567.2-8573.5" + switch $and$ls180.v:8567$2659_Y + attribute \src "ls180.v:8567.6-8567.89" + case 1'1 + attribute \src "ls180.v:8568.3-8572.6" + switch \main_sdmem2block_converter_last + attribute \src "ls180.v:8568.7-8568.38" + case 1'1 + assign $0\main_sdmem2block_converter_mux[1:0] 2'00 + attribute \src "ls180.v:8570.7-8570.11" + case + assign $0\main_sdmem2block_converter_mux[1:0] $add$ls180.v:8571$2660_Y + end + case + end + attribute \src "ls180.v:8574.2-8576.5" + switch $and$ls180.v:8574$2663_Y + attribute \src "ls180.v:8574.6-8574.120" + case 1'1 + assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8575$2664_Y + case + end + attribute \src "ls180.v:8577.2-8579.5" + switch \main_sdmem2block_fifo_do_read + attribute \src "ls180.v:8577.6-8577.35" + case 1'1 + assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8578$2665_Y + case + end + attribute \src "ls180.v:8580.2-8588.5" + switch $and$ls180.v:8580$2668_Y + attribute \src "ls180.v:8580.6-8580.120" + case 1'1 + attribute \src "ls180.v:8581.3-8583.6" + switch $not$ls180.v:8581$2669_Y + attribute \src "ls180.v:8581.7-8581.39" + case 1'1 + assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8582$2670_Y + case + end + attribute \src "ls180.v:8584.6-8584.10" + case + attribute \src "ls180.v:8585.3-8587.6" + switch \main_sdmem2block_fifo_do_read + attribute \src "ls180.v:8585.7-8585.36" + case 1'1 + assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8586$2671_Y + case + end + end + attribute \src "ls180.v:8590.2-8597.5" + switch \libresocsim_clk_rise + attribute \src "ls180.v:8590.6-8590.26" + case 1'1 + assign $0\spisdcard_clk[0:0] \libresocsim_clk_enable + attribute \src "ls180.v:8592.6-8592.10" + case + attribute \src "ls180.v:8593.3-8596.6" + switch \libresocsim_clk_fall + attribute \src "ls180.v:8593.7-8593.27" + case 1'1 + assign $0\libresocsim_clk_divider1[15:0] 16'0000000000000000 + assign $0\spisdcard_clk[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8599.2-8609.5" + switch \libresocsim_mosi_latch + attribute \src "ls180.v:8599.6-8599.28" + case 1'1 + assign $0\libresocsim_mosi_data[7:0] \libresocsim_mosi + assign $0\libresocsim_mosi_sel[2:0] 3'111 + attribute \src "ls180.v:8602.6-8602.10" + case + attribute \src "ls180.v:8603.3-8608.6" + switch \libresocsim_clk_fall + attribute \src "ls180.v:8603.7-8603.27" + case 1'1 + assign $0\libresocsim_mosi_sel[2:0] $sub$ls180.v:8607$2676_Y + attribute \src "ls180.v:8604.4-8606.7" + switch \libresocsim_cs_enable + attribute \src "ls180.v:8604.8-8604.29" + case 1'1 + assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed1 + case + end + case + end + end + attribute \src "ls180.v:8610.2-8616.5" + switch \libresocsim_clk_rise + attribute \src "ls180.v:8610.6-8610.26" + case 1'1 + attribute \src "ls180.v:8611.3-8615.6" + switch \libresocsim_loopback + attribute \src "ls180.v:8611.7-8611.27" + case 1'1 + assign $0\libresocsim_miso_data[7:0] { \libresocsim_miso_data [6:0] \spisdcard_mosi } + attribute \src "ls180.v:8613.7-8613.11" + case + assign $0\libresocsim_miso_data[7:0] { \libresocsim_miso_data [6:0] \spisdcard_miso } + end + case + end + attribute \src "ls180.v:8617.2-8619.5" + switch \libresocsim_miso_latch + attribute \src "ls180.v:8617.6-8617.28" + case 1'1 + assign $0\libresocsim_miso[7:0] \libresocsim_miso_data + case + end + attribute \src "ls180.v:8621.2-8623.5" + switch \libresocsim_count_spimaster1_next_value_ce + attribute \src "ls180.v:8621.6-8621.48" + case 1'1 + assign $0\libresocsim_count[2:0] \libresocsim_count_spimaster1_next_value + case + end + attribute \src "ls180.v:8625.2-8627.5" + switch \builder_libresocsim_dat_w_next_value_ce0 + attribute \src "ls180.v:8625.6-8625.46" + case 1'1 + assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0 + case + end + attribute \src "ls180.v:8628.2-8630.5" + switch \builder_libresocsim_adr_next_value_ce1 + attribute \src "ls180.v:8628.6-8628.44" + case 1'1 + assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1 + case + end + attribute \src "ls180.v:8631.2-8633.5" + switch \builder_libresocsim_we_next_value_ce2 + attribute \src "ls180.v:8631.6-8631.43" + case 1'1 + assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2 + case + end + attribute \src "ls180.v:8634.2-8730.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + attribute \src "ls180.v:8636.4-8652.7" + switch $not$ls180.v:8636$2677_Y + attribute \src "ls180.v:8636.8-8636.29" + case 1'1 + attribute \src "ls180.v:8637.5-8651.8" + switch \builder_request [1] + attribute \src "ls180.v:8637.9-8637.27" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + attribute \src "ls180.v:8639.9-8639.13" + case + attribute \src "ls180.v:8640.6-8650.9" + switch \builder_request [2] + attribute \src "ls180.v:8640.10-8640.28" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + attribute \src "ls180.v:8642.10-8642.14" + case + attribute \src "ls180.v:8643.7-8649.10" + switch \builder_request [3] + attribute \src "ls180.v:8643.11-8643.29" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + attribute \src "ls180.v:8645.11-8645.15" + case + attribute \src "ls180.v:8646.8-8648.11" + switch \builder_request [4] + attribute \src "ls180.v:8646.12-8646.30" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'001 + attribute \src "ls180.v:8655.4-8671.7" + switch $not$ls180.v:8655$2678_Y + attribute \src "ls180.v:8655.8-8655.29" + case 1'1 + attribute \src "ls180.v:8656.5-8670.8" + switch \builder_request [2] + attribute \src "ls180.v:8656.9-8656.27" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + attribute \src "ls180.v:8658.9-8658.13" + case + attribute \src "ls180.v:8659.6-8669.9" + switch \builder_request [3] + attribute \src "ls180.v:8659.10-8659.28" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + attribute \src "ls180.v:8661.10-8661.14" + case + attribute \src "ls180.v:8662.7-8668.10" + switch \builder_request [4] + attribute \src "ls180.v:8662.11-8662.29" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + attribute \src "ls180.v:8664.11-8664.15" + case + attribute \src "ls180.v:8665.8-8667.11" + switch \builder_request [0] + attribute \src "ls180.v:8665.12-8665.30" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + attribute \src "ls180.v:8674.4-8690.7" + switch $not$ls180.v:8674$2679_Y + attribute \src "ls180.v:8674.8-8674.29" + case 1'1 + attribute \src "ls180.v:8675.5-8689.8" + switch \builder_request [3] + attribute \src "ls180.v:8675.9-8675.27" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + attribute \src "ls180.v:8677.9-8677.13" + case + attribute \src "ls180.v:8678.6-8688.9" + switch \builder_request [4] + attribute \src "ls180.v:8678.10-8678.28" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + attribute \src "ls180.v:8680.10-8680.14" + case + attribute \src "ls180.v:8681.7-8687.10" + switch \builder_request [0] + attribute \src "ls180.v:8681.11-8681.29" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + attribute \src "ls180.v:8683.11-8683.15" + case + attribute \src "ls180.v:8684.8-8686.11" + switch \builder_request [1] + attribute \src "ls180.v:8684.12-8684.30" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:8693.4-8709.7" + switch $not$ls180.v:8693$2680_Y + attribute \src "ls180.v:8693.8-8693.29" + case 1'1 + attribute \src "ls180.v:8694.5-8708.8" + switch \builder_request [4] + attribute \src "ls180.v:8694.9-8694.27" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + attribute \src "ls180.v:8696.9-8696.13" + case + attribute \src "ls180.v:8697.6-8707.9" + switch \builder_request [0] + attribute \src "ls180.v:8697.10-8697.28" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + attribute \src "ls180.v:8699.10-8699.14" + case + attribute \src "ls180.v:8700.7-8706.10" + switch \builder_request [1] + attribute \src "ls180.v:8700.11-8700.29" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + attribute \src "ls180.v:8702.11-8702.15" + case + attribute \src "ls180.v:8703.8-8705.11" + switch \builder_request [2] + attribute \src "ls180.v:8703.12-8703.30" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + attribute \src "ls180.v:8712.4-8728.7" + switch $not$ls180.v:8712$2681_Y + attribute \src "ls180.v:8712.8-8712.29" + case 1'1 + attribute \src "ls180.v:8713.5-8727.8" + switch \builder_request [0] + attribute \src "ls180.v:8713.9-8713.27" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + attribute \src "ls180.v:8715.9-8715.13" + case + attribute \src "ls180.v:8716.6-8726.9" + switch \builder_request [1] + attribute \src "ls180.v:8716.10-8716.28" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + attribute \src "ls180.v:8718.10-8718.14" + case + attribute \src "ls180.v:8719.7-8725.10" + switch \builder_request [2] + attribute \src "ls180.v:8719.11-8719.29" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + attribute \src "ls180.v:8721.11-8721.15" + case + attribute \src "ls180.v:8722.8-8724.11" + switch \builder_request [3] + attribute \src "ls180.v:8722.12-8722.30" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + case + end + end + end + end + case + end + case + end + attribute \src "ls180.v:8732.2-8738.5" + switch \builder_wait + attribute \src "ls180.v:8732.6-8732.18" + case 1'1 + attribute \src "ls180.v:8733.3-8735.6" + switch $not$ls180.v:8733$2682_Y + attribute \src "ls180.v:8733.7-8733.22" + case 1'1 + assign $0\builder_count[19:0] $sub$ls180.v:8734$2683_Y + case + end + attribute \src "ls180.v:8736.6-8736.10" + case + assign $0\builder_count[19:0] 20'11110100001001000000 + end + attribute \src "ls180.v:8740.2-8770.5" + switch \builder_csrbank0_sel + attribute \src "ls180.v:8740.6-8740.26" + case 1'1 + attribute \src "ls180.v:8741.3-8769.10" + switch \builder_interface0_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface0_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank0_reset0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors0_w + case + end + case + end + attribute \src "ls180.v:8771.2-8773.5" + switch \builder_csrbank0_reset0_re + attribute \src "ls180.v:8771.6-8771.32" + case 1'1 + assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r + case + end + attribute \src "ls180.v:8775.2-8777.5" + switch \builder_csrbank0_scratch3_re + attribute \src "ls180.v:8775.6-8775.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r + case + end + attribute \src "ls180.v:8778.2-8780.5" + switch \builder_csrbank0_scratch2_re + attribute \src "ls180.v:8778.6-8778.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r + case + end + attribute \src "ls180.v:8781.2-8783.5" + switch \builder_csrbank0_scratch1_re + attribute \src "ls180.v:8781.6-8781.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r + case + end + attribute \src "ls180.v:8784.2-8786.5" + switch \builder_csrbank0_scratch0_re + attribute \src "ls180.v:8784.6-8784.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r + case + end + attribute \src "ls180.v:8789.2-8810.5" + switch \builder_csrbank1_sel + attribute \src "ls180.v:8789.6-8789.26" + case 1'1 + attribute \src "ls180.v:8790.3-8809.10" + switch \builder_interface1_bank_bus_adr [2:0] + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe1_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe0_w + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in1_w + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in0_w + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out1_w + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out0_w + case + end + case + end + attribute \src "ls180.v:8811.2-8813.5" + switch \builder_csrbank1_oe1_re + attribute \src "ls180.v:8811.6-8811.29" + case 1'1 + assign $0\main_gpio_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r + case + end + attribute \src "ls180.v:8814.2-8816.5" + switch \builder_csrbank1_oe0_re + attribute \src "ls180.v:8814.6-8814.29" + case 1'1 + assign $0\main_gpio_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r + case + end + attribute \src "ls180.v:8818.2-8820.5" + switch \builder_csrbank1_out1_re + attribute \src "ls180.v:8818.6-8818.30" + case 1'1 + assign $0\main_gpio_out_storage[15:0] [15:8] \builder_csrbank1_out1_r + case + end + attribute \src "ls180.v:8821.2-8823.5" + switch \builder_csrbank1_out0_re + attribute \src "ls180.v:8821.6-8821.30" + case 1'1 + assign $0\main_gpio_out_storage[15:0] [7:0] \builder_csrbank1_out0_r + case + end + attribute \src "ls180.v:8826.2-8856.5" + switch \builder_csrbank2_sel + attribute \src "ls180.v:8826.6-8826.26" + case 1'1 + attribute \src "ls180.v:8827.3-8855.10" + switch \builder_interface2_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface2_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank2_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_width3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_width2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_width1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_width0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_period3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_period2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_period1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_period0_w + case + end + case + end + attribute \src "ls180.v:8857.2-8859.5" + switch \builder_csrbank2_enable0_re + attribute \src "ls180.v:8857.6-8857.33" + case 1'1 + assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank2_enable0_r + case + end + attribute \src "ls180.v:8861.2-8863.5" + switch \builder_csrbank2_width3_re + attribute \src "ls180.v:8861.6-8861.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank2_width3_r + case + end + attribute \src "ls180.v:8864.2-8866.5" + switch \builder_csrbank2_width2_re + attribute \src "ls180.v:8864.6-8864.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank2_width2_r + case + end + attribute \src "ls180.v:8867.2-8869.5" + switch \builder_csrbank2_width1_re + attribute \src "ls180.v:8867.6-8867.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank2_width1_r + case + end + attribute \src "ls180.v:8870.2-8872.5" + switch \builder_csrbank2_width0_re + attribute \src "ls180.v:8870.6-8870.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank2_width0_r + case + end + attribute \src "ls180.v:8874.2-8876.5" + switch \builder_csrbank2_period3_re + attribute \src "ls180.v:8874.6-8874.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank2_period3_r + case + end + attribute \src "ls180.v:8877.2-8879.5" + switch \builder_csrbank2_period2_re + attribute \src "ls180.v:8877.6-8877.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank2_period2_r + case + end + attribute \src "ls180.v:8880.2-8882.5" + switch \builder_csrbank2_period1_re + attribute \src "ls180.v:8880.6-8880.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank2_period1_r + case + end + attribute \src "ls180.v:8883.2-8885.5" + switch \builder_csrbank2_period0_re + attribute \src "ls180.v:8883.6-8883.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank2_period0_r + case + end + attribute \src "ls180.v:8888.2-8918.5" + switch \builder_csrbank3_sel + attribute \src "ls180.v:8888.6-8888.26" + case 1'1 + attribute \src "ls180.v:8889.3-8917.10" + switch \builder_interface3_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface3_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank3_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period0_w + case + end + case + end + attribute \src "ls180.v:8919.2-8921.5" + switch \builder_csrbank3_enable0_re + attribute \src "ls180.v:8919.6-8919.33" + case 1'1 + assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank3_enable0_r + case + end + attribute \src "ls180.v:8923.2-8925.5" + switch \builder_csrbank3_width3_re + attribute \src "ls180.v:8923.6-8923.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank3_width3_r + case + end + attribute \src "ls180.v:8926.2-8928.5" + switch \builder_csrbank3_width2_re + attribute \src "ls180.v:8926.6-8926.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank3_width2_r + case + end + attribute \src "ls180.v:8929.2-8931.5" + switch \builder_csrbank3_width1_re + attribute \src "ls180.v:8929.6-8929.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank3_width1_r + case + end + attribute \src "ls180.v:8932.2-8934.5" + switch \builder_csrbank3_width0_re + attribute \src "ls180.v:8932.6-8932.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank3_width0_r + case + end + attribute \src "ls180.v:8936.2-8938.5" + switch \builder_csrbank3_period3_re + attribute \src "ls180.v:8936.6-8936.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank3_period3_r + case + end + attribute \src "ls180.v:8939.2-8941.5" + switch \builder_csrbank3_period2_re + attribute \src "ls180.v:8939.6-8939.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank3_period2_r + case + end + attribute \src "ls180.v:8942.2-8944.5" + switch \builder_csrbank3_period1_re + attribute \src "ls180.v:8942.6-8942.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank3_period1_r + case + end + attribute \src "ls180.v:8945.2-8947.5" + switch \builder_csrbank3_period0_re + attribute \src "ls180.v:8945.6-8945.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank3_period0_r + case + end + attribute \src "ls180.v:8950.2-8998.5" + switch \builder_csrbank4_sel + attribute \src "ls180.v:8950.6-8950.26" + case 1'1 + attribute \src "ls180.v:8951.3-8997.10" + switch \builder_interface4_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base7_w + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base6_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base5_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base4_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base0_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_length3_w + attribute \src "ls180.v:0.0-0.0" + case 4'1001 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_length2_w + attribute \src "ls180.v:0.0-0.0" + case 4'1010 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_length1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1011 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_length0_w + attribute \src "ls180.v:0.0-0.0" + case 4'1100 + assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_dma_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'1101 + assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_dma_done_w } + attribute \src "ls180.v:0.0-0.0" + case 4'1110 + assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_dma_loop0_w } + case + end + case + end + attribute \src "ls180.v:8999.2-9001.5" + switch \builder_csrbank4_dma_base7_re + attribute \src "ls180.v:8999.6-8999.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank4_dma_base7_r + case + end + attribute \src "ls180.v:9002.2-9004.5" + switch \builder_csrbank4_dma_base6_re + attribute \src "ls180.v:9002.6-9002.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank4_dma_base6_r + case + end + attribute \src "ls180.v:9005.2-9007.5" + switch \builder_csrbank4_dma_base5_re + attribute \src "ls180.v:9005.6-9005.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank4_dma_base5_r + case + end + attribute \src "ls180.v:9008.2-9010.5" + switch \builder_csrbank4_dma_base4_re + attribute \src "ls180.v:9008.6-9008.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank4_dma_base4_r + case + end + attribute \src "ls180.v:9011.2-9013.5" + switch \builder_csrbank4_dma_base3_re + attribute \src "ls180.v:9011.6-9011.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank4_dma_base3_r + case + end + attribute \src "ls180.v:9014.2-9016.5" + switch \builder_csrbank4_dma_base2_re + attribute \src "ls180.v:9014.6-9014.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank4_dma_base2_r + case + end + attribute \src "ls180.v:9017.2-9019.5" + switch \builder_csrbank4_dma_base1_re + attribute \src "ls180.v:9017.6-9017.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank4_dma_base1_r + case + end + attribute \src "ls180.v:9020.2-9022.5" + switch \builder_csrbank4_dma_base0_re + attribute \src "ls180.v:9020.6-9020.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank4_dma_base0_r + case + end + attribute \src "ls180.v:9024.2-9026.5" + switch \builder_csrbank4_dma_length3_re + attribute \src "ls180.v:9024.6-9024.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank4_dma_length3_r + case + end + attribute \src "ls180.v:9027.2-9029.5" + switch \builder_csrbank4_dma_length2_re + attribute \src "ls180.v:9027.6-9027.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank4_dma_length2_r + case + end + attribute \src "ls180.v:9030.2-9032.5" + switch \builder_csrbank4_dma_length1_re + attribute \src "ls180.v:9030.6-9030.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank4_dma_length1_r + case + end + attribute \src "ls180.v:9033.2-9035.5" + switch \builder_csrbank4_dma_length0_re + attribute \src "ls180.v:9033.6-9033.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank4_dma_length0_r + case + end + attribute \src "ls180.v:9037.2-9039.5" + switch \builder_csrbank4_dma_enable0_re + attribute \src "ls180.v:9037.6-9037.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank4_dma_enable0_r + case + end + attribute \src "ls180.v:9041.2-9043.5" + switch \builder_csrbank4_dma_loop0_re + attribute \src "ls180.v:9041.6-9041.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank4_dma_loop0_r + case + end + attribute \src "ls180.v:9046.2-9148.5" + switch \builder_csrbank5_sel + attribute \src "ls180.v:9046.6-9046.26" + case 1'1 + attribute \src "ls180.v:9047.3-9147.10" + switch \builder_interface5_bank_bus_adr [5:0] + attribute \src "ls180.v:0.0-0.0" + case 6'000000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_argument3_w + attribute \src "ls180.v:0.0-0.0" + case 6'000001 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_argument2_w + attribute \src "ls180.v:0.0-0.0" + case 6'000010 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_argument1_w + attribute \src "ls180.v:0.0-0.0" + case 6'000011 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_argument0_w + attribute \src "ls180.v:0.0-0.0" + case 6'000100 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_command3_w + attribute \src "ls180.v:0.0-0.0" + case 6'000101 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_command2_w + attribute \src "ls180.v:0.0-0.0" + case 6'000110 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_command1_w + attribute \src "ls180.v:0.0-0.0" + case 6'000111 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_command0_w + attribute \src "ls180.v:0.0-0.0" + case 6'001000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \main_sdcore_cmd_send_w } + attribute \src "ls180.v:0.0-0.0" + case 6'001001 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response15_w + attribute \src "ls180.v:0.0-0.0" + case 6'001010 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response14_w + attribute \src "ls180.v:0.0-0.0" + case 6'001011 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response13_w + attribute \src "ls180.v:0.0-0.0" + case 6'001100 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response12_w + attribute \src "ls180.v:0.0-0.0" + case 6'001101 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response11_w + attribute \src "ls180.v:0.0-0.0" + case 6'001110 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response10_w + attribute \src "ls180.v:0.0-0.0" + case 6'001111 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response9_w + attribute \src "ls180.v:0.0-0.0" + case 6'010000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response8_w + attribute \src "ls180.v:0.0-0.0" + case 6'010001 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response7_w + attribute \src "ls180.v:0.0-0.0" + case 6'010010 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response6_w + attribute \src "ls180.v:0.0-0.0" + case 6'010011 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response5_w + attribute \src "ls180.v:0.0-0.0" + case 6'010100 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response4_w + attribute \src "ls180.v:0.0-0.0" + case 6'010101 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response3_w + attribute \src "ls180.v:0.0-0.0" + case 6'010110 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response2_w + attribute \src "ls180.v:0.0-0.0" + case 6'010111 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response1_w + attribute \src "ls180.v:0.0-0.0" + case 6'011000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response0_w + attribute \src "ls180.v:0.0-0.0" + case 6'011001 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank5_cmd_event_w } + attribute \src "ls180.v:0.0-0.0" + case 6'011010 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank5_data_event_w } + attribute \src "ls180.v:0.0-0.0" + case 6'011011 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank5_block_length1_w } + attribute \src "ls180.v:0.0-0.0" + case 6'011100 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_block_length0_w + attribute \src "ls180.v:0.0-0.0" + case 6'011101 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_block_count3_w + attribute \src "ls180.v:0.0-0.0" + case 6'011110 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_block_count2_w + attribute \src "ls180.v:0.0-0.0" + case 6'011111 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_block_count1_w + attribute \src "ls180.v:0.0-0.0" + case 6'100000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_block_count0_w + case + end + case + end + attribute \src "ls180.v:9149.2-9151.5" + switch \builder_csrbank5_cmd_argument3_re + attribute \src "ls180.v:9149.6-9149.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank5_cmd_argument3_r + case + end + attribute \src "ls180.v:9152.2-9154.5" + switch \builder_csrbank5_cmd_argument2_re + attribute \src "ls180.v:9152.6-9152.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank5_cmd_argument2_r + case + end + attribute \src "ls180.v:9155.2-9157.5" + switch \builder_csrbank5_cmd_argument1_re + attribute \src "ls180.v:9155.6-9155.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank5_cmd_argument1_r + case + end + attribute \src "ls180.v:9158.2-9160.5" + switch \builder_csrbank5_cmd_argument0_re + attribute \src "ls180.v:9158.6-9158.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank5_cmd_argument0_r + case + end + attribute \src "ls180.v:9162.2-9164.5" + switch \builder_csrbank5_cmd_command3_re + attribute \src "ls180.v:9162.6-9162.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank5_cmd_command3_r + case + end + attribute \src "ls180.v:9165.2-9167.5" + switch \builder_csrbank5_cmd_command2_re + attribute \src "ls180.v:9165.6-9165.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank5_cmd_command2_r + case + end + attribute \src "ls180.v:9168.2-9170.5" + switch \builder_csrbank5_cmd_command1_re + attribute \src "ls180.v:9168.6-9168.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank5_cmd_command1_r + case + end + attribute \src "ls180.v:9171.2-9173.5" + switch \builder_csrbank5_cmd_command0_re + attribute \src "ls180.v:9171.6-9171.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank5_cmd_command0_r + case + end + attribute \src "ls180.v:9175.2-9177.5" + switch \builder_csrbank5_block_length1_re + attribute \src "ls180.v:9175.6-9175.39" + case 1'1 + assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank5_block_length1_r + case + end + attribute \src "ls180.v:9178.2-9180.5" + switch \builder_csrbank5_block_length0_re + attribute \src "ls180.v:9178.6-9178.39" + case 1'1 + assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank5_block_length0_r + case + end + attribute \src "ls180.v:9182.2-9184.5" + switch \builder_csrbank5_block_count3_re + attribute \src "ls180.v:9182.6-9182.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank5_block_count3_r + case + end + attribute \src "ls180.v:9185.2-9187.5" + switch \builder_csrbank5_block_count2_re + attribute \src "ls180.v:9185.6-9185.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank5_block_count2_r + case + end + attribute \src "ls180.v:9188.2-9190.5" + switch \builder_csrbank5_block_count1_re + attribute \src "ls180.v:9188.6-9188.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank5_block_count1_r + case + end + attribute \src "ls180.v:9191.2-9193.5" + switch \builder_csrbank5_block_count0_re + attribute \src "ls180.v:9191.6-9191.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank5_block_count0_r + case + end + attribute \src "ls180.v:9196.2-9256.5" + switch \builder_csrbank6_sel + attribute \src "ls180.v:9196.6-9196.26" + case 1'1 + attribute \src "ls180.v:9197.3-9255.10" + switch \builder_interface6_bank_bus_adr [4:0] + attribute \src "ls180.v:0.0-0.0" + case 5'00000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base7_w + attribute \src "ls180.v:0.0-0.0" + case 5'00001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base6_w + attribute \src "ls180.v:0.0-0.0" + case 5'00010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base5_w + attribute \src "ls180.v:0.0-0.0" + case 5'00011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base4_w + attribute \src "ls180.v:0.0-0.0" + case 5'00100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base3_w + attribute \src "ls180.v:0.0-0.0" + case 5'00101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base2_w + attribute \src "ls180.v:0.0-0.0" + case 5'00110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base1_w + attribute \src "ls180.v:0.0-0.0" + case 5'00111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_length3_w + attribute \src "ls180.v:0.0-0.0" + case 5'01001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_length2_w + attribute \src "ls180.v:0.0-0.0" + case 5'01010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_length1_w + attribute \src "ls180.v:0.0-0.0" + case 5'01011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_length0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank6_dma_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank6_dma_done_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank6_dma_loop0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_offset3_w + attribute \src "ls180.v:0.0-0.0" + case 5'10000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_offset2_w + attribute \src "ls180.v:0.0-0.0" + case 5'10001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_offset1_w + attribute \src "ls180.v:0.0-0.0" + case 5'10010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_offset0_w + case + end + case + end + attribute \src "ls180.v:9257.2-9259.5" + switch \builder_csrbank6_dma_base7_re + attribute \src "ls180.v:9257.6-9257.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank6_dma_base7_r + case + end + attribute \src "ls180.v:9260.2-9262.5" + switch \builder_csrbank6_dma_base6_re + attribute \src "ls180.v:9260.6-9260.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank6_dma_base6_r + case + end + attribute \src "ls180.v:9263.2-9265.5" + switch \builder_csrbank6_dma_base5_re + attribute \src "ls180.v:9263.6-9263.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank6_dma_base5_r + case + end + attribute \src "ls180.v:9266.2-9268.5" + switch \builder_csrbank6_dma_base4_re + attribute \src "ls180.v:9266.6-9266.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank6_dma_base4_r + case + end + attribute \src "ls180.v:9269.2-9271.5" + switch \builder_csrbank6_dma_base3_re + attribute \src "ls180.v:9269.6-9269.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank6_dma_base3_r + case + end + attribute \src "ls180.v:9272.2-9274.5" + switch \builder_csrbank6_dma_base2_re + attribute \src "ls180.v:9272.6-9272.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank6_dma_base2_r + case + end + attribute \src "ls180.v:9275.2-9277.5" + switch \builder_csrbank6_dma_base1_re + attribute \src "ls180.v:9275.6-9275.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank6_dma_base1_r + case + end + attribute \src "ls180.v:9278.2-9280.5" + switch \builder_csrbank6_dma_base0_re + attribute \src "ls180.v:9278.6-9278.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank6_dma_base0_r + case + end + attribute \src "ls180.v:9282.2-9284.5" + switch \builder_csrbank6_dma_length3_re + attribute \src "ls180.v:9282.6-9282.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank6_dma_length3_r + case + end + attribute \src "ls180.v:9285.2-9287.5" + switch \builder_csrbank6_dma_length2_re + attribute \src "ls180.v:9285.6-9285.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank6_dma_length2_r + case + end + attribute \src "ls180.v:9288.2-9290.5" + switch \builder_csrbank6_dma_length1_re + attribute \src "ls180.v:9288.6-9288.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank6_dma_length1_r + case + end + attribute \src "ls180.v:9291.2-9293.5" + switch \builder_csrbank6_dma_length0_re + attribute \src "ls180.v:9291.6-9291.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank6_dma_length0_r + case + end + attribute \src "ls180.v:9295.2-9297.5" + switch \builder_csrbank6_dma_enable0_re + attribute \src "ls180.v:9295.6-9295.37" + case 1'1 + assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank6_dma_enable0_r + case + end + attribute \src "ls180.v:9299.2-9301.5" + switch \builder_csrbank6_dma_loop0_re + attribute \src "ls180.v:9299.6-9299.35" + case 1'1 + assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank6_dma_loop0_r + case + end + attribute \src "ls180.v:9304.2-9319.5" + switch \builder_csrbank7_sel + attribute \src "ls180.v:9304.6-9304.26" + case 1'1 + attribute \src "ls180.v:9305.3-9318.10" + switch \builder_interface7_bank_bus_adr [1:0] + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_card_detect_w } + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_clocker_divider1_w } + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_clocker_divider0_w + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \main_sdphy_init_initialize_w } + case + end + case + end + attribute \src "ls180.v:9320.2-9322.5" + switch \builder_csrbank7_clocker_divider1_re + attribute \src "ls180.v:9320.6-9320.42" + case 1'1 + assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank7_clocker_divider1_r + case + end + attribute \src "ls180.v:9323.2-9325.5" + switch \builder_csrbank7_clocker_divider0_re + attribute \src "ls180.v:9323.6-9323.42" + case 1'1 + assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank7_clocker_divider0_r + case + end + attribute \src "ls180.v:9328.2-9361.5" + switch \builder_csrbank8_sel + attribute \src "ls180.v:9328.6-9328.26" + case 1'1 + attribute \src "ls180.v:9329.3-9360.10" + switch \builder_interface8_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank8_dfii_control0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 2'00 \builder_csrbank8_dfii_pi0_command0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \main_sdram_command_issue_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 3'000 \builder_csrbank8_dfii_pi0_address1_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_dfii_pi0_address0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank8_dfii_pi0_baddress0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_dfii_pi0_wrdata1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_dfii_pi0_wrdata0_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_dfii_pi0_rddata1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1001 + assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_dfii_pi0_rddata0_w + case + end + case + end + attribute \src "ls180.v:9362.2-9364.5" + switch \builder_csrbank8_dfii_control0_re + attribute \src "ls180.v:9362.6-9362.39" + case 1'1 + assign $0\main_sdram_storage[3:0] \builder_csrbank8_dfii_control0_r + case + end + attribute \src "ls180.v:9366.2-9368.5" + switch \builder_csrbank8_dfii_pi0_command0_re + attribute \src "ls180.v:9366.6-9366.43" + case 1'1 + assign $0\main_sdram_command_storage[5:0] \builder_csrbank8_dfii_pi0_command0_r + case + end + attribute \src "ls180.v:9370.2-9372.5" + switch \builder_csrbank8_dfii_pi0_address1_re + attribute \src "ls180.v:9370.6-9370.43" + case 1'1 + assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank8_dfii_pi0_address1_r + case + end + attribute \src "ls180.v:9373.2-9375.5" + switch \builder_csrbank8_dfii_pi0_address0_re + attribute \src "ls180.v:9373.6-9373.43" + case 1'1 + assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank8_dfii_pi0_address0_r + case + end + attribute \src "ls180.v:9377.2-9379.5" + switch \builder_csrbank8_dfii_pi0_baddress0_re + attribute \src "ls180.v:9377.6-9377.44" + case 1'1 + assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank8_dfii_pi0_baddress0_r + case + end + attribute \src "ls180.v:9381.2-9383.5" + switch \builder_csrbank8_dfii_pi0_wrdata1_re + attribute \src "ls180.v:9381.6-9381.42" + case 1'1 + assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank8_dfii_pi0_wrdata1_r + case + end + attribute \src "ls180.v:9384.2-9386.5" + switch \builder_csrbank8_dfii_pi0_wrdata0_re + attribute \src "ls180.v:9384.6-9384.42" + case 1'1 + assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank8_dfii_pi0_wrdata0_r + case + end + attribute \src "ls180.v:9389.2-9413.5" + switch \builder_csrbank9_sel + attribute \src "ls180.v:9389.6-9389.26" + case 1'1 + attribute \src "ls180.v:9390.3-9412.10" + switch \builder_interface9_bank_bus_adr [2:0] + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_control1_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_control0_w + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank9_status_w } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_mosi0_w + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_miso_w + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank9_cs0_w } + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank9_loopback0_w } + case + end + case + end + attribute \src "ls180.v:9414.2-9416.5" + switch \builder_csrbank9_control1_re + attribute \src "ls180.v:9414.6-9414.34" + case 1'1 + assign $0\main_spi_master_control_storage[15:0] [15:8] \builder_csrbank9_control1_r + case + end + attribute \src "ls180.v:9417.2-9419.5" + switch \builder_csrbank9_control0_re + attribute \src "ls180.v:9417.6-9417.34" + case 1'1 + assign $0\main_spi_master_control_storage[15:0] [7:0] \builder_csrbank9_control0_r + case + end + attribute \src "ls180.v:9421.2-9423.5" + switch \builder_csrbank9_mosi0_re + attribute \src "ls180.v:9421.6-9421.31" + case 1'1 + assign $0\main_spi_master_mosi_storage[7:0] \builder_csrbank9_mosi0_r + case + end + attribute \src "ls180.v:9425.2-9427.5" + switch \builder_csrbank9_cs0_re + attribute \src "ls180.v:9425.6-9425.29" + case 1'1 + assign $0\main_spi_master_cs_storage[0:0] \builder_csrbank9_cs0_r + case + end + attribute \src "ls180.v:9429.2-9431.5" + switch \builder_csrbank9_loopback0_re + attribute \src "ls180.v:9429.6-9429.35" + case 1'1 + assign $0\main_spi_master_loopback_storage[0:0] \builder_csrbank9_loopback0_r + case + end + attribute \src "ls180.v:9434.2-9464.5" + switch \builder_csrbank10_sel + attribute \src "ls180.v:9434.6-9434.27" + case 1'1 + attribute \src "ls180.v:9435.3-9463.10" + switch \builder_interface10_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_status_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_mosi0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_miso_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_cs0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_loopback0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_clk_divider1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_clk_divider0_w + case + end + case + end + attribute \src "ls180.v:9465.2-9467.5" + switch \builder_csrbank10_control1_re + attribute \src "ls180.v:9465.6-9465.35" + case 1'1 + assign $0\libresocsim_control_storage[15:0] [15:8] \builder_csrbank10_control1_r + case + end + attribute \src "ls180.v:9468.2-9470.5" + switch \builder_csrbank10_control0_re + attribute \src "ls180.v:9468.6-9468.35" + case 1'1 + assign $0\libresocsim_control_storage[15:0] [7:0] \builder_csrbank10_control0_r + case + end + attribute \src "ls180.v:9472.2-9474.5" + switch \builder_csrbank10_mosi0_re + attribute \src "ls180.v:9472.6-9472.32" + case 1'1 + assign $0\libresocsim_mosi_storage[7:0] \builder_csrbank10_mosi0_r + case + end + attribute \src "ls180.v:9476.2-9478.5" + switch \builder_csrbank10_cs0_re + attribute \src "ls180.v:9476.6-9476.30" + case 1'1 + assign $0\libresocsim_cs_storage[0:0] \builder_csrbank10_cs0_r + case + end + attribute \src "ls180.v:9480.2-9482.5" + switch \builder_csrbank10_loopback0_re + attribute \src "ls180.v:9480.6-9480.36" + case 1'1 + assign $0\libresocsim_loopback_storage[0:0] \builder_csrbank10_loopback0_r + case + end + attribute \src "ls180.v:9484.2-9486.5" + switch \builder_csrbank10_clk_divider1_re + attribute \src "ls180.v:9484.6-9484.39" + case 1'1 + assign $0\libresocsim_storage[15:0] [15:8] \builder_csrbank10_clk_divider1_r + case + end + attribute \src "ls180.v:9487.2-9489.5" + switch \builder_csrbank10_clk_divider0_re + attribute \src "ls180.v:9487.6-9487.39" + case 1'1 + assign $0\libresocsim_storage[15:0] [7:0] \builder_csrbank10_clk_divider0_r + case + end + attribute \src "ls180.v:9492.2-9546.5" + switch \builder_csrbank11_sel + attribute \src "ls180.v:9492.6-9492.27" + case 1'1 + attribute \src "ls180.v:9493.3-9545.10" + switch \builder_interface11_bank_bus_adr [4:0] + attribute \src "ls180.v:0.0-0.0" + case 5'00000 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_load3_w + attribute \src "ls180.v:0.0-0.0" + case 5'00001 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_load2_w + attribute \src "ls180.v:0.0-0.0" + case 5'00010 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_load1_w + attribute \src "ls180.v:0.0-0.0" + case 5'00011 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_load0_w + attribute \src "ls180.v:0.0-0.0" + case 5'00100 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_reload3_w + attribute \src "ls180.v:0.0-0.0" + case 5'00101 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_reload2_w + attribute \src "ls180.v:0.0-0.0" + case 5'00110 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_reload1_w + attribute \src "ls180.v:0.0-0.0" + case 5'00111 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_reload0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01000 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_en0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01001 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_update_value0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01010 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_value3_w + attribute \src "ls180.v:0.0-0.0" + case 5'01011 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_value2_w + attribute \src "ls180.v:0.0-0.0" + case 5'01100 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_value1_w + attribute \src "ls180.v:0.0-0.0" + case 5'01101 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_value0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01110 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_status_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01111 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_pending_w } + attribute \src "ls180.v:0.0-0.0" + case 5'10000 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_ev_enable0_w } + case + end + case + end + attribute \src "ls180.v:9547.2-9549.5" + switch \builder_csrbank11_load3_re + attribute \src "ls180.v:9547.6-9547.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank11_load3_r + case + end + attribute \src "ls180.v:9550.2-9552.5" + switch \builder_csrbank11_load2_re + attribute \src "ls180.v:9550.6-9550.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank11_load2_r + case + end + attribute \src "ls180.v:9553.2-9555.5" + switch \builder_csrbank11_load1_re + attribute \src "ls180.v:9553.6-9553.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank11_load1_r + case + end + attribute \src "ls180.v:9556.2-9558.5" + switch \builder_csrbank11_load0_re + attribute \src "ls180.v:9556.6-9556.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank11_load0_r + case + end + attribute \src "ls180.v:9560.2-9562.5" + switch \builder_csrbank11_reload3_re + attribute \src "ls180.v:9560.6-9560.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank11_reload3_r + case + end + attribute \src "ls180.v:9563.2-9565.5" + switch \builder_csrbank11_reload2_re + attribute \src "ls180.v:9563.6-9563.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank11_reload2_r + case + end + attribute \src "ls180.v:9566.2-9568.5" + switch \builder_csrbank11_reload1_re + attribute \src "ls180.v:9566.6-9566.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank11_reload1_r + case + end + attribute \src "ls180.v:9569.2-9571.5" + switch \builder_csrbank11_reload0_re + attribute \src "ls180.v:9569.6-9569.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank11_reload0_r + case + end + attribute \src "ls180.v:9573.2-9575.5" + switch \builder_csrbank11_en0_re + attribute \src "ls180.v:9573.6-9573.30" + case 1'1 + assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank11_en0_r + case + end + attribute \src "ls180.v:9577.2-9579.5" + switch \builder_csrbank11_update_value0_re + attribute \src "ls180.v:9577.6-9577.40" + case 1'1 + assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank11_update_value0_r + case + end + attribute \src "ls180.v:9581.2-9583.5" + switch \builder_csrbank11_ev_enable0_re + attribute \src "ls180.v:9581.6-9581.37" + case 1'1 + assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank11_ev_enable0_r + case + end + attribute \src "ls180.v:9586.2-9613.5" + switch \builder_csrbank12_sel + attribute \src "ls180.v:9586.6-9586.27" + case 1'1 + attribute \src "ls180.v:9587.3-9612.10" + switch \builder_interface12_bank_bus_adr [2:0] + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \main_uart_rxtx_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_txfull_w } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_rxempty_w } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_status_w } + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_pending_w } + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank12_ev_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_txempty_w } + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_rxfull_w } + case + end + case + end + attribute \src "ls180.v:9614.2-9616.5" + switch \builder_csrbank12_ev_enable0_re + attribute \src "ls180.v:9614.6-9614.37" + case 1'1 + assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank12_ev_enable0_r + case + end + attribute \src "ls180.v:9619.2-9634.5" + switch \builder_csrbank13_sel + attribute \src "ls180.v:9619.6-9619.27" + case 1'1 + attribute \src "ls180.v:9620.3-9633.10" + switch \builder_interface13_bank_bus_adr [1:0] + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_interface13_bank_bus_dat_r[7:0] \builder_csrbank13_tuning_word3_w + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_interface13_bank_bus_dat_r[7:0] \builder_csrbank13_tuning_word2_w + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_interface13_bank_bus_dat_r[7:0] \builder_csrbank13_tuning_word1_w + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\builder_interface13_bank_bus_dat_r[7:0] \builder_csrbank13_tuning_word0_w + case + end + case + end + attribute \src "ls180.v:9635.2-9637.5" + switch \builder_csrbank13_tuning_word3_re + attribute \src "ls180.v:9635.6-9635.39" + case 1'1 + assign $0\main_storage[31:0] [31:24] \builder_csrbank13_tuning_word3_r + case + end + attribute \src "ls180.v:9638.2-9640.5" + switch \builder_csrbank13_tuning_word2_re + attribute \src "ls180.v:9638.6-9638.39" + case 1'1 + assign $0\main_storage[31:0] [23:16] \builder_csrbank13_tuning_word2_r + case + end + attribute \src "ls180.v:9641.2-9643.5" + switch \builder_csrbank13_tuning_word1_re + attribute \src "ls180.v:9641.6-9641.39" + case 1'1 + assign $0\main_storage[31:0] [15:8] \builder_csrbank13_tuning_word1_r + case + end + attribute \src "ls180.v:9644.2-9646.5" + switch \builder_csrbank13_tuning_word0_re + attribute \src "ls180.v:9644.6-9644.39" + case 1'1 + assign $0\main_storage[31:0] [7:0] \builder_csrbank13_tuning_word0_r + case + end + attribute \src "ls180.v:9648.2-9942.5" + switch \sys_rst_1 + attribute \src "ls180.v:9648.6-9648.15" + case 1'1 + assign $0\main_libresocsim_reset_storage[0:0] 1'0 + assign $0\main_libresocsim_reset_re[0:0] 1'0 + assign $0\main_libresocsim_scratch_storage[31:0] 305419896 + assign $0\main_libresocsim_scratch_re[0:0] 1'0 + assign $0\main_libresocsim_bus_errors[31:0] 0 + assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1 + assign $0\main_libresocsim_converter0_counter[0:0] 1'0 + assign $0\main_libresocsim_converter1_counter[0:0] 1'0 + assign $0\main_libresocsim_converter2_counter[0:0] 1'0 + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 + assign $0\main_libresocsim_load_storage[31:0] 0 + assign $0\main_libresocsim_load_re[0:0] 1'0 + assign $0\main_libresocsim_reload_storage[31:0] 0 + assign $0\main_libresocsim_reload_re[0:0] 1'0 + assign $0\main_libresocsim_en_storage[0:0] 1'0 + assign $0\main_libresocsim_en_re[0:0] 1'0 + assign $0\main_libresocsim_update_value_storage[0:0] 1'0 + assign $0\main_libresocsim_update_value_re[0:0] 1'0 + assign $0\main_libresocsim_value_status[31:0] 0 + assign $0\main_libresocsim_zero_pending[0:0] 1'0 + assign $0\main_libresocsim_zero_old_trigger[0:0] 1'0 + assign $0\main_libresocsim_eventmanager_storage[0:0] 1'0 + assign $0\main_libresocsim_eventmanager_re[0:0] 1'0 + assign $0\main_libresocsim_value[31:0] 0 + assign $0\sdram_dm[1:0] 2'00 + assign $0\main_dfi_p0_rddata_valid[0:0] 1'0 + assign $0\main_rddata_en[2:0] 3'000 + assign $0\main_sdram_storage[3:0] 4'0001 + assign $0\main_sdram_re[0:0] 1'0 + assign $0\main_sdram_command_storage[5:0] 6'000000 + assign $0\main_sdram_command_re[0:0] 1'0 + assign $0\main_sdram_address_re[0:0] 1'0 + assign $0\main_sdram_baddress_re[0:0] 1'0 + assign $0\main_sdram_wrdata_re[0:0] 1'0 + assign $0\main_sdram_status[15:0] 16'0000000000000000 + assign $0\main_sdram_dfi_p0_address[12:0] 13'0000000000000 + assign $0\main_sdram_dfi_p0_bank[1:0] 2'00 + assign $0\main_sdram_dfi_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_we_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 + assign $0\main_sdram_dfi_p0_rddata_en[0:0] 1'0 + assign $0\main_sdram_timer_count1[9:0] 10'1100001101 + assign $0\main_sdram_postponer_req_o[0:0] 1'0 + assign $0\main_sdram_postponer_count[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'0 + assign $0\main_sdram_sequencer_counter[3:0] 4'0000 + assign $0\main_sdram_sequencer_count[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + assign $0\main_sdram_tccdcon_ready[0:0] 1'0 + assign $0\main_sdram_tccdcon_count[0:0] 1'0 + assign $0\main_sdram_twtrcon_ready[0:0] 1'0 + assign $0\main_sdram_twtrcon_count[2:0] 3'000 + assign $0\main_sdram_time0[4:0] 5'00000 + assign $0\main_sdram_time1[3:0] 4'0000 + assign $0\main_converter_counter[0:0] 1'0 + assign $0\main_cmd_consumed[0:0] 1'0 + assign $0\main_wdata_consumed[0:0] 1'0 + assign $0\main_storage[31:0] 9895604 + assign $0\main_re[0:0] 1'0 + assign $0\main_sink_ready[0:0] 1'0 + assign $0\main_uart_clk_txen[0:0] 1'0 + assign $0\main_tx_busy[0:0] 1'0 + assign $0\main_source_valid[0:0] 1'0 + assign $0\main_uart_clk_rxen[0:0] 1'0 + assign $0\main_rx_r[0:0] 1'0 + assign $0\main_rx_busy[0:0] 1'0 + assign $0\main_uart_tx_pending[0:0] 1'0 + assign $0\main_uart_tx_old_trigger[0:0] 1'0 + assign $0\main_uart_rx_pending[0:0] 1'0 + assign $0\main_uart_rx_old_trigger[0:0] 1'0 + assign $0\main_uart_eventmanager_storage[1:0] 2'00 + assign $0\main_uart_eventmanager_re[0:0] 1'0 + assign $0\main_uart_tx_fifo_readable[0:0] 1'0 + assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 + assign $0\main_uart_rx_fifo_readable[0:0] 1'0 + assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 + assign $0\main_gpio_oe_storage[15:0] 16'0000000000000000 + assign $0\main_gpio_oe_re[0:0] 1'0 + assign $0\main_gpio_out_storage[15:0] 16'0000000000000000 + assign $0\main_gpio_out_re[0:0] 1'0 + assign $0\spi_master_clk[0:0] 1'0 + assign $0\spi_master_mosi[0:0] 1'0 + assign $0\spi_master_cs_n[0:0] 1'0 + assign $0\main_spi_master_miso[7:0] 8'00000000 + assign $0\main_spi_master_control_storage[15:0] 16'0000000000000000 + assign $0\main_spi_master_control_re[0:0] 1'0 + assign $0\main_spi_master_mosi_re[0:0] 1'0 + assign $0\main_spi_master_cs_storage[0:0] 1'1 + assign $0\main_spi_master_cs_re[0:0] 1'0 + assign $0\main_spi_master_loopback_storage[0:0] 1'0 + assign $0\main_spi_master_loopback_re[0:0] 1'0 + assign $0\main_spi_master_count[2:0] 3'000 + assign $0\main_spi_master_clk_divider1[15:0] 16'0000000000000000 + assign $0\main_spi_master_mosi_data[7:0] 8'00000000 + assign $0\main_spi_master_mosi_sel[2:0] 3'000 + assign $0\main_spi_master_miso_data[7:0] 8'00000000 + assign $0\main_dummy[42:0] 43'0000000000000000000000000000000000000000000 + assign $0\pwm0[0:0] 1'0 + assign $0\main_pwm0_enable_storage[0:0] 1'0 + assign $0\main_pwm0_enable_re[0:0] 1'0 + assign $0\main_pwm0_width_re[0:0] 1'0 + assign $0\main_pwm0_period_re[0:0] 1'0 + assign $0\pwm1[0:0] 1'0 + assign $0\main_pwm1_enable_storage[0:0] 1'0 + assign $0\main_pwm1_enable_re[0:0] 1'0 + assign $0\main_pwm1_width_re[0:0] 1'0 + assign $0\main_pwm1_period_re[0:0] 1'0 + assign $0\main_sdphy_clocker_storage[8:0] 9'100000000 + assign $0\main_sdphy_clocker_re[0:0] 1'0 + assign $0\main_sdphy_clocker_clk0[0:0] 1'0 + assign $0\main_sdphy_clocker_clks[8:0] 9'000000000 + assign $0\main_sdphy_clocker_clk_d[0:0] 1'0 + assign $0\main_sdphy_init_count[7:0] 8'00000000 + assign $0\main_sdphy_cmdw_count[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_timeout[31:0] 500000 + assign $0\main_sdphy_cmdr_count[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 + assign $0\main_sdphy_dataw_count[7:0] 8'00000000 + assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset[0:0] 1'0 + assign $0\main_sdphy_datar_timeout[31:0] 500000 + assign $0\main_sdphy_datar_count[9:0] 10'0000000000 + assign $0\main_sdphy_datar_datar_run[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset[0:0] 1'0 + assign $0\main_sdcore_cmd_argument_storage[31:0] 0 + assign $0\main_sdcore_cmd_argument_re[0:0] 1'0 + assign $0\main_sdcore_cmd_command_storage[31:0] 0 + assign $0\main_sdcore_cmd_command_re[0:0] 1'0 + assign $0\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdcore_block_length_storage[9:0] 10'0000000000 + assign $0\main_sdcore_block_length_re[0:0] 1'0 + assign $0\main_sdcore_block_count_storage[31:0] 0 + assign $0\main_sdcore_block_count_re[0:0] 1'0 + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + assign $0\main_sdcore_crc16_inserter_cnt[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_val[7:0] 8'00000000 + assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 + assign $0\main_sdcore_cmd_count[2:0] 3'000 + assign $0\main_sdcore_cmd_done[0:0] 1'0 + assign $0\main_sdcore_cmd_error[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout[0:0] 1'0 + assign $0\main_sdcore_data_count[31:0] 0 + assign $0\main_sdcore_data_done[0:0] 1'0 + assign $0\main_sdcore_data_error[0:0] 1'0 + assign $0\main_sdcore_data_timeout[0:0] 1'0 + assign $0\main_sdblock2mem_fifo_level[5:0] 6'000000 + assign $0\main_sdblock2mem_fifo_produce[4:0] 5'00000 + assign $0\main_sdblock2mem_fifo_consume[4:0] 5'00000 + assign $0\main_sdblock2mem_converter_demux[1:0] 2'00 + assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + assign $0\main_sdmem2block_dma_data[31:0] 0 + assign $0\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdmem2block_dma_base_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_length_storage[31:0] 0 + assign $0\main_sdmem2block_dma_length_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_enable_storage[0:0] 1'0 + assign $0\main_sdmem2block_dma_enable_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_loop_storage[0:0] 1'0 + assign $0\main_sdmem2block_dma_loop_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_offset[31:0] 0 + assign $0\main_sdmem2block_converter_mux[1:0] 2'00 + assign $0\main_sdmem2block_fifo_level[5:0] 6'000000 + assign $0\main_sdmem2block_fifo_produce[4:0] 5'00000 + assign $0\main_sdmem2block_fifo_consume[4:0] 5'00000 + assign $0\spisdcard_clk[0:0] 1'0 + assign $0\spisdcard_mosi[0:0] 1'0 + assign $0\spisdcard_cs_n[0:0] 1'0 + assign $0\libresocsim_miso[7:0] 8'00000000 + assign $0\libresocsim_control_storage[15:0] 16'0000000000000000 + assign $0\libresocsim_control_re[0:0] 1'0 + assign $0\libresocsim_mosi_re[0:0] 1'0 + assign $0\libresocsim_cs_storage[0:0] 1'1 + assign $0\libresocsim_cs_re[0:0] 1'0 + assign $0\libresocsim_loopback_storage[0:0] 1'0 + assign $0\libresocsim_loopback_re[0:0] 1'0 + assign $0\libresocsim_count[2:0] 3'000 + assign $0\libresocsim_clk_divider1[15:0] 16'0000000000000000 + assign $0\libresocsim_mosi_data[7:0] 8'00000000 + assign $0\libresocsim_mosi_sel[2:0] 3'000 + assign $0\libresocsim_miso_data[7:0] 8'00000000 + assign $0\libresocsim_storage[15:0] 16'0000000001111101 + assign $0\libresocsim_re[0:0] 1'0 + assign $0\builder_converter0_state[0:0] 1'0 + assign $0\builder_converter1_state[0:0] 1'0 + assign $0\builder_converter2_state[0:0] 1'0 + assign $0\builder_refresher_state[1:0] 2'00 + assign $0\builder_bankmachine0_state[2:0] 3'000 + assign $0\builder_bankmachine1_state[2:0] 3'000 + assign $0\builder_bankmachine2_state[2:0] 3'000 + assign $0\builder_bankmachine3_state[2:0] 3'000 + assign $0\builder_multiplexer_state[2:0] 3'000 + assign $0\builder_new_master_wdata_ready[0:0] 1'0 + assign $0\builder_new_master_rdata_valid0[0:0] 1'0 + assign $0\builder_new_master_rdata_valid1[0:0] 1'0 + assign $0\builder_new_master_rdata_valid2[0:0] 1'0 + assign $0\builder_new_master_rdata_valid3[0:0] 1'0 + assign $0\builder_converter_state[0:0] 1'0 + assign $0\builder_spimaster0_state[1:0] 2'00 + assign $0\builder_sdphy_sdphyinit_state[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdw_state[1:0] 2'00 + assign $0\builder_sdphy_sdphycmdr_state[2:0] 3'000 + assign $0\builder_sdphy_sdphycrcr_state[0:0] 1'0 + assign $0\builder_sdphy_fsm_state[2:0] 3'000 + assign $0\builder_sdphy_sdphydatar_state[2:0] 3'000 + assign $0\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 + assign $0\builder_sdcore_fsm_state[2:0] 3'000 + assign $0\builder_sdblock2memdma_state[1:0] 2'00 + assign $0\builder_sdmem2blockdma_fsm_state[0:0] 1'0 + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + assign $0\builder_spimaster1_state[1:0] 2'00 + assign $0\builder_libresocsim_we[0:0] 1'0 + assign $0\builder_grant[2:0] 3'000 + assign $0\builder_slave_sel_r[4:0] 5'00000 + assign $0\builder_count[19:0] 20'11110100001001000000 + assign $0\builder_state[1:0] 2'00 + case + end + sync posedge \sys_clk_1 + update \sdram_dm $0\sdram_dm[1:0] + update \spi_master_clk $0\spi_master_clk[0:0] + update \spi_master_mosi $0\spi_master_mosi[0:0] + update \spi_master_cs_n $0\spi_master_cs_n[0:0] + update \pwm0 $0\pwm0[0:0] + update \pwm1 $0\pwm1[0:0] + update \spisdcard_clk $0\spisdcard_clk[0:0] + update \spisdcard_mosi $0\spisdcard_mosi[0:0] + update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] + update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0] + update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0] + update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0] + update \main_libresocsim_scratch_re $0\main_libresocsim_scratch_re[0:0] + update \main_libresocsim_bus_errors $0\main_libresocsim_bus_errors[31:0] + update \main_libresocsim_libresoc_constraintmanager0_uart0_tx $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] + update \main_libresocsim_converter0_counter $0\main_libresocsim_converter0_counter[0:0] + update \main_libresocsim_converter0_dat_r $0\main_libresocsim_converter0_dat_r[63:0] + update \main_libresocsim_converter1_counter $0\main_libresocsim_converter1_counter[0:0] + update \main_libresocsim_converter1_dat_r $0\main_libresocsim_converter1_dat_r[63:0] + update \main_libresocsim_converter2_counter $0\main_libresocsim_converter2_counter[0:0] + update \main_libresocsim_converter2_dat_r $0\main_libresocsim_converter2_dat_r[63:0] + update \main_libresocsim_ram_bus_ack $0\main_libresocsim_ram_bus_ack[0:0] + update \main_libresocsim_load_storage $0\main_libresocsim_load_storage[31:0] + update \main_libresocsim_load_re $0\main_libresocsim_load_re[0:0] + update \main_libresocsim_reload_storage $0\main_libresocsim_reload_storage[31:0] + update \main_libresocsim_reload_re $0\main_libresocsim_reload_re[0:0] + update \main_libresocsim_en_storage $0\main_libresocsim_en_storage[0:0] + update \main_libresocsim_en_re $0\main_libresocsim_en_re[0:0] + update \main_libresocsim_update_value_storage $0\main_libresocsim_update_value_storage[0:0] + update \main_libresocsim_update_value_re $0\main_libresocsim_update_value_re[0:0] + update \main_libresocsim_value_status $0\main_libresocsim_value_status[31:0] + update \main_libresocsim_zero_pending $0\main_libresocsim_zero_pending[0:0] + update \main_libresocsim_zero_old_trigger $0\main_libresocsim_zero_old_trigger[0:0] + update \main_libresocsim_eventmanager_storage $0\main_libresocsim_eventmanager_storage[0:0] + update \main_libresocsim_eventmanager_re $0\main_libresocsim_eventmanager_re[0:0] + update \main_libresocsim_value $0\main_libresocsim_value[31:0] + update \main_dfi_p0_rddata_valid $0\main_dfi_p0_rddata_valid[0:0] + update \main_rddata_en $0\main_rddata_en[2:0] + update \main_sdram_storage $0\main_sdram_storage[3:0] + update \main_sdram_re $0\main_sdram_re[0:0] + update \main_sdram_command_storage $0\main_sdram_command_storage[5:0] + update \main_sdram_command_re $0\main_sdram_command_re[0:0] + update \main_sdram_address_storage $0\main_sdram_address_storage[12:0] + update \main_sdram_address_re $0\main_sdram_address_re[0:0] + update \main_sdram_baddress_storage $0\main_sdram_baddress_storage[1:0] + update \main_sdram_baddress_re $0\main_sdram_baddress_re[0:0] + update \main_sdram_wrdata_storage $0\main_sdram_wrdata_storage[15:0] + update \main_sdram_wrdata_re $0\main_sdram_wrdata_re[0:0] + update \main_sdram_status $0\main_sdram_status[15:0] + update \main_sdram_dfi_p0_address $0\main_sdram_dfi_p0_address[12:0] + update \main_sdram_dfi_p0_bank $0\main_sdram_dfi_p0_bank[1:0] + update \main_sdram_dfi_p0_cas_n $0\main_sdram_dfi_p0_cas_n[0:0] + update \main_sdram_dfi_p0_cs_n $0\main_sdram_dfi_p0_cs_n[0:0] + update \main_sdram_dfi_p0_ras_n $0\main_sdram_dfi_p0_ras_n[0:0] + update \main_sdram_dfi_p0_we_n $0\main_sdram_dfi_p0_we_n[0:0] + update \main_sdram_dfi_p0_wrdata_en $0\main_sdram_dfi_p0_wrdata_en[0:0] + update \main_sdram_dfi_p0_rddata_en $0\main_sdram_dfi_p0_rddata_en[0:0] + update \main_sdram_cmd_payload_a $0\main_sdram_cmd_payload_a[12:0] + update \main_sdram_cmd_payload_ba $0\main_sdram_cmd_payload_ba[1:0] + update \main_sdram_cmd_payload_cas $0\main_sdram_cmd_payload_cas[0:0] + update \main_sdram_cmd_payload_ras $0\main_sdram_cmd_payload_ras[0:0] + update \main_sdram_cmd_payload_we $0\main_sdram_cmd_payload_we[0:0] + update \main_sdram_timer_count1 $0\main_sdram_timer_count1[9:0] + update \main_sdram_postponer_req_o $0\main_sdram_postponer_req_o[0:0] + update \main_sdram_postponer_count $0\main_sdram_postponer_count[0:0] + update \main_sdram_sequencer_done1 $0\main_sdram_sequencer_done1[0:0] + update \main_sdram_sequencer_counter $0\main_sdram_sequencer_counter[3:0] + update \main_sdram_sequencer_count $0\main_sdram_sequencer_count[0:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine0_cmd_buffer_source_valid $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_first $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_last $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine0_row $0\main_sdram_bankmachine0_row[12:0] + update \main_sdram_bankmachine0_row_opened $0\main_sdram_bankmachine0_row_opened[0:0] + update \main_sdram_bankmachine0_twtpcon_ready $0\main_sdram_bankmachine0_twtpcon_ready[0:0] + update \main_sdram_bankmachine0_twtpcon_count $0\main_sdram_bankmachine0_twtpcon_count[2:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine1_cmd_buffer_source_valid $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_first $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_last $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine1_row $0\main_sdram_bankmachine1_row[12:0] + update \main_sdram_bankmachine1_row_opened $0\main_sdram_bankmachine1_row_opened[0:0] + update \main_sdram_bankmachine1_twtpcon_ready $0\main_sdram_bankmachine1_twtpcon_ready[0:0] + update \main_sdram_bankmachine1_twtpcon_count $0\main_sdram_bankmachine1_twtpcon_count[2:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine2_cmd_buffer_source_valid $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_first $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_last $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine2_row $0\main_sdram_bankmachine2_row[12:0] + update \main_sdram_bankmachine2_row_opened $0\main_sdram_bankmachine2_row_opened[0:0] + update \main_sdram_bankmachine2_twtpcon_ready $0\main_sdram_bankmachine2_twtpcon_ready[0:0] + update \main_sdram_bankmachine2_twtpcon_count $0\main_sdram_bankmachine2_twtpcon_count[2:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine3_cmd_buffer_source_valid $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_first $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_last $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine3_row $0\main_sdram_bankmachine3_row[12:0] + update \main_sdram_bankmachine3_row_opened $0\main_sdram_bankmachine3_row_opened[0:0] + update \main_sdram_bankmachine3_twtpcon_ready $0\main_sdram_bankmachine3_twtpcon_ready[0:0] + update \main_sdram_bankmachine3_twtpcon_count $0\main_sdram_bankmachine3_twtpcon_count[2:0] + update \main_sdram_choose_cmd_grant $0\main_sdram_choose_cmd_grant[1:0] + update \main_sdram_choose_req_grant $0\main_sdram_choose_req_grant[1:0] + update \main_sdram_tccdcon_ready $0\main_sdram_tccdcon_ready[0:0] + update \main_sdram_tccdcon_count $0\main_sdram_tccdcon_count[0:0] + update \main_sdram_twtrcon_ready $0\main_sdram_twtrcon_ready[0:0] + update \main_sdram_twtrcon_count $0\main_sdram_twtrcon_count[2:0] + update \main_sdram_time0 $0\main_sdram_time0[4:0] + update \main_sdram_time1 $0\main_sdram_time1[3:0] + update \main_converter_counter $0\main_converter_counter[0:0] + update \main_converter_dat_r $0\main_converter_dat_r[31:0] + update \main_cmd_consumed $0\main_cmd_consumed[0:0] + update \main_wdata_consumed $0\main_wdata_consumed[0:0] + update \main_storage $0\main_storage[31:0] + update \main_re $0\main_re[0:0] + update \main_sink_ready $0\main_sink_ready[0:0] + update \main_uart_clk_txen $0\main_uart_clk_txen[0:0] + update \main_phase_accumulator_tx $0\main_phase_accumulator_tx[31:0] + update \main_tx_reg $0\main_tx_reg[7:0] + update \main_tx_bitcount $0\main_tx_bitcount[3:0] + update \main_tx_busy $0\main_tx_busy[0:0] + update \main_source_valid $0\main_source_valid[0:0] + update \main_source_payload_data $0\main_source_payload_data[7:0] + update \main_uart_clk_rxen $0\main_uart_clk_rxen[0:0] + update \main_phase_accumulator_rx $0\main_phase_accumulator_rx[31:0] + update \main_rx_r $0\main_rx_r[0:0] + update \main_rx_reg $0\main_rx_reg[7:0] + update \main_rx_bitcount $0\main_rx_bitcount[3:0] + update \main_rx_busy $0\main_rx_busy[0:0] + update \main_uart_tx_pending $0\main_uart_tx_pending[0:0] + update \main_uart_tx_old_trigger $0\main_uart_tx_old_trigger[0:0] + update \main_uart_rx_pending $0\main_uart_rx_pending[0:0] + update \main_uart_rx_old_trigger $0\main_uart_rx_old_trigger[0:0] + update \main_uart_eventmanager_storage $0\main_uart_eventmanager_storage[1:0] + update \main_uart_eventmanager_re $0\main_uart_eventmanager_re[0:0] + update \main_uart_tx_fifo_readable $0\main_uart_tx_fifo_readable[0:0] + update \main_uart_tx_fifo_level0 $0\main_uart_tx_fifo_level0[4:0] + update \main_uart_tx_fifo_produce $0\main_uart_tx_fifo_produce[3:0] + update \main_uart_tx_fifo_consume $0\main_uart_tx_fifo_consume[3:0] + update \main_uart_rx_fifo_readable $0\main_uart_rx_fifo_readable[0:0] + update \main_uart_rx_fifo_level0 $0\main_uart_rx_fifo_level0[4:0] + update \main_uart_rx_fifo_produce $0\main_uart_rx_fifo_produce[3:0] + update \main_uart_rx_fifo_consume $0\main_uart_rx_fifo_consume[3:0] + update \main_gpio_oe_storage $0\main_gpio_oe_storage[15:0] + update \main_gpio_oe_re $0\main_gpio_oe_re[0:0] + update \main_gpio_out_storage $0\main_gpio_out_storage[15:0] + update \main_gpio_out_re $0\main_gpio_out_re[0:0] + update \main_spi_master_miso $0\main_spi_master_miso[7:0] + update \main_spi_master_control_storage $0\main_spi_master_control_storage[15:0] + update \main_spi_master_control_re $0\main_spi_master_control_re[0:0] + update \main_spi_master_mosi_storage $0\main_spi_master_mosi_storage[7:0] + update \main_spi_master_mosi_re $0\main_spi_master_mosi_re[0:0] + update \main_spi_master_cs_storage $0\main_spi_master_cs_storage[0:0] + update \main_spi_master_cs_re $0\main_spi_master_cs_re[0:0] + update \main_spi_master_loopback_storage $0\main_spi_master_loopback_storage[0:0] + update \main_spi_master_loopback_re $0\main_spi_master_loopback_re[0:0] + update \main_spi_master_count $0\main_spi_master_count[2:0] + update \main_spi_master_clk_divider1 $0\main_spi_master_clk_divider1[15:0] + update \main_spi_master_mosi_data $0\main_spi_master_mosi_data[7:0] + update \main_spi_master_mosi_sel $0\main_spi_master_mosi_sel[2:0] + update \main_spi_master_miso_data $0\main_spi_master_miso_data[7:0] + update \main_dummy $0\main_dummy[42:0] + update \main_pwm0_counter $0\main_pwm0_counter[31:0] + update \main_pwm0_enable_storage $0\main_pwm0_enable_storage[0:0] + update \main_pwm0_enable_re $0\main_pwm0_enable_re[0:0] + update \main_pwm0_width_storage $0\main_pwm0_width_storage[31:0] + update \main_pwm0_width_re $0\main_pwm0_width_re[0:0] + update \main_pwm0_period_storage $0\main_pwm0_period_storage[31:0] + update \main_pwm0_period_re $0\main_pwm0_period_re[0:0] + update \main_pwm1_counter $0\main_pwm1_counter[31:0] + update \main_pwm1_enable_storage $0\main_pwm1_enable_storage[0:0] + update \main_pwm1_enable_re $0\main_pwm1_enable_re[0:0] + update \main_pwm1_width_storage $0\main_pwm1_width_storage[31:0] + update \main_pwm1_width_re $0\main_pwm1_width_re[0:0] + update \main_pwm1_period_storage $0\main_pwm1_period_storage[31:0] + update \main_pwm1_period_re $0\main_pwm1_period_re[0:0] + update \main_sdphy_clocker_storage $0\main_sdphy_clocker_storage[8:0] + update \main_sdphy_clocker_re $0\main_sdphy_clocker_re[0:0] + update \main_sdphy_clocker_clk0 $0\main_sdphy_clocker_clk0[0:0] + update \main_sdphy_clocker_clks $0\main_sdphy_clocker_clks[8:0] + update \main_sdphy_clocker_clk_d $0\main_sdphy_clocker_clk_d[0:0] + update \main_sdphy_init_count $0\main_sdphy_init_count[7:0] + update \main_sdphy_cmdw_count $0\main_sdphy_cmdw_count[7:0] + update \main_sdphy_cmdr_timeout $0\main_sdphy_cmdr_timeout[31:0] + update \main_sdphy_cmdr_count $0\main_sdphy_cmdr_count[7:0] + update \main_sdphy_cmdr_cmdr_run $0\main_sdphy_cmdr_cmdr_run[0:0] + update \main_sdphy_cmdr_cmdr_converter_source_first $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + update \main_sdphy_cmdr_cmdr_converter_source_last $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + update \main_sdphy_cmdr_cmdr_converter_source_payload_data $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + update \main_sdphy_cmdr_cmdr_converter_demux $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] + update \main_sdphy_cmdr_cmdr_converter_strobe_all $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_valid $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_first $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_last $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_payload_data $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + update \main_sdphy_cmdr_cmdr_reset $0\main_sdphy_cmdr_cmdr_reset[0:0] + update \main_sdphy_dataw_count $0\main_sdphy_dataw_count[7:0] + update \main_sdphy_dataw_crcr_run $0\main_sdphy_dataw_crcr_run[0:0] + update \main_sdphy_dataw_crcr_converter_source_first $0\main_sdphy_dataw_crcr_converter_source_first[0:0] + update \main_sdphy_dataw_crcr_converter_source_last $0\main_sdphy_dataw_crcr_converter_source_last[0:0] + update \main_sdphy_dataw_crcr_converter_source_payload_data $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + update \main_sdphy_dataw_crcr_converter_demux $0\main_sdphy_dataw_crcr_converter_demux[2:0] + update \main_sdphy_dataw_crcr_converter_strobe_all $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + update \main_sdphy_dataw_crcr_buf_source_valid $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] + update \main_sdphy_dataw_crcr_buf_source_first $0\main_sdphy_dataw_crcr_buf_source_first[0:0] + update \main_sdphy_dataw_crcr_buf_source_last $0\main_sdphy_dataw_crcr_buf_source_last[0:0] + update \main_sdphy_dataw_crcr_buf_source_payload_data $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + update \main_sdphy_dataw_crcr_reset $0\main_sdphy_dataw_crcr_reset[0:0] + update \main_sdphy_datar_timeout $0\main_sdphy_datar_timeout[31:0] + update \main_sdphy_datar_count $0\main_sdphy_datar_count[9:0] + update \main_sdphy_datar_datar_run $0\main_sdphy_datar_datar_run[0:0] + update \main_sdphy_datar_datar_converter_source_first $0\main_sdphy_datar_datar_converter_source_first[0:0] + update \main_sdphy_datar_datar_converter_source_last $0\main_sdphy_datar_datar_converter_source_last[0:0] + update \main_sdphy_datar_datar_converter_source_payload_data $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] + update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + update \main_sdphy_datar_datar_converter_demux $0\main_sdphy_datar_datar_converter_demux[0:0] + update \main_sdphy_datar_datar_converter_strobe_all $0\main_sdphy_datar_datar_converter_strobe_all[0:0] + update \main_sdphy_datar_datar_buf_source_valid $0\main_sdphy_datar_datar_buf_source_valid[0:0] + update \main_sdphy_datar_datar_buf_source_first $0\main_sdphy_datar_datar_buf_source_first[0:0] + update \main_sdphy_datar_datar_buf_source_last $0\main_sdphy_datar_datar_buf_source_last[0:0] + update \main_sdphy_datar_datar_buf_source_payload_data $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] + update \main_sdphy_datar_datar_reset $0\main_sdphy_datar_datar_reset[0:0] + update \main_sdcore_cmd_argument_storage $0\main_sdcore_cmd_argument_storage[31:0] + update \main_sdcore_cmd_argument_re $0\main_sdcore_cmd_argument_re[0:0] + update \main_sdcore_cmd_command_storage $0\main_sdcore_cmd_command_storage[31:0] + update \main_sdcore_cmd_command_re $0\main_sdcore_cmd_command_re[0:0] + update \main_sdcore_cmd_response_status $0\main_sdcore_cmd_response_status[127:0] + update \main_sdcore_block_length_storage $0\main_sdcore_block_length_storage[9:0] + update \main_sdcore_block_length_re $0\main_sdcore_block_length_re[0:0] + update \main_sdcore_block_count_storage $0\main_sdcore_block_count_storage[31:0] + update \main_sdcore_block_count_re $0\main_sdcore_block_count_re[0:0] + update \main_sdcore_crc7_inserter_crcreg0 $0\main_sdcore_crc7_inserter_crcreg0[6:0] + update \main_sdcore_crc16_inserter_cnt $0\main_sdcore_crc16_inserter_cnt[2:0] + update \main_sdcore_crc16_inserter_crc0_crcreg0 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crc1_crcreg0 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crc2_crcreg0 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crc3_crcreg0 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crctmp0 $0\main_sdcore_crc16_inserter_crctmp0[15:0] + update \main_sdcore_crc16_inserter_crctmp1 $0\main_sdcore_crc16_inserter_crctmp1[15:0] + update \main_sdcore_crc16_inserter_crctmp2 $0\main_sdcore_crc16_inserter_crctmp2[15:0] + update \main_sdcore_crc16_inserter_crctmp3 $0\main_sdcore_crc16_inserter_crctmp3[15:0] + update \main_sdcore_crc16_checker_val $0\main_sdcore_crc16_checker_val[7:0] + update \main_sdcore_crc16_checker_cnt $0\main_sdcore_crc16_checker_cnt[3:0] + update \main_sdcore_crc16_checker_crc0_crcreg0 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + update \main_sdcore_crc16_checker_crc1_crcreg0 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + update \main_sdcore_crc16_checker_crc2_crcreg0 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + update \main_sdcore_crc16_checker_crc3_crcreg0 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + update \main_sdcore_crc16_checker_crctmp0 $0\main_sdcore_crc16_checker_crctmp0[15:0] + update \main_sdcore_crc16_checker_crctmp1 $0\main_sdcore_crc16_checker_crctmp1[15:0] + update \main_sdcore_crc16_checker_crctmp2 $0\main_sdcore_crc16_checker_crctmp2[15:0] + update \main_sdcore_crc16_checker_crctmp3 $0\main_sdcore_crc16_checker_crctmp3[15:0] + update \main_sdcore_crc16_checker_fifo0 $0\main_sdcore_crc16_checker_fifo0[15:0] + update \main_sdcore_crc16_checker_fifo1 $0\main_sdcore_crc16_checker_fifo1[15:0] + update \main_sdcore_crc16_checker_fifo2 $0\main_sdcore_crc16_checker_fifo2[15:0] + update \main_sdcore_crc16_checker_fifo3 $0\main_sdcore_crc16_checker_fifo3[15:0] + update \main_sdcore_cmd_count $0\main_sdcore_cmd_count[2:0] + update \main_sdcore_cmd_done $0\main_sdcore_cmd_done[0:0] + update \main_sdcore_cmd_error $0\main_sdcore_cmd_error[0:0] + update \main_sdcore_cmd_timeout $0\main_sdcore_cmd_timeout[0:0] + update \main_sdcore_data_count $0\main_sdcore_data_count[31:0] + update \main_sdcore_data_done $0\main_sdcore_data_done[0:0] + update \main_sdcore_data_error $0\main_sdcore_data_error[0:0] + update \main_sdcore_data_timeout $0\main_sdcore_data_timeout[0:0] + update \main_sdblock2mem_fifo_level $0\main_sdblock2mem_fifo_level[5:0] + update \main_sdblock2mem_fifo_produce $0\main_sdblock2mem_fifo_produce[4:0] + update \main_sdblock2mem_fifo_consume $0\main_sdblock2mem_fifo_consume[4:0] + update \main_sdblock2mem_converter_source_first $0\main_sdblock2mem_converter_source_first[0:0] + update \main_sdblock2mem_converter_source_last $0\main_sdblock2mem_converter_source_last[0:0] + update \main_sdblock2mem_converter_source_payload_data $0\main_sdblock2mem_converter_source_payload_data[31:0] + update \main_sdblock2mem_converter_source_payload_valid_token_count $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] + update \main_sdblock2mem_converter_demux $0\main_sdblock2mem_converter_demux[1:0] + update \main_sdblock2mem_converter_strobe_all $0\main_sdblock2mem_converter_strobe_all[0:0] + update \main_sdblock2mem_wishbonedmawriter_base_storage $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + update \main_sdblock2mem_wishbonedmawriter_base_re $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_length_storage $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + update \main_sdblock2mem_wishbonedmawriter_length_re $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_enable_storage $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + update \main_sdblock2mem_wishbonedmawriter_enable_re $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_loop_storage $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + update \main_sdblock2mem_wishbonedmawriter_loop_re $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_offset $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] + update \main_sdmem2block_dma_data $0\main_sdmem2block_dma_data[31:0] + update \main_sdmem2block_dma_base_storage $0\main_sdmem2block_dma_base_storage[63:0] + update \main_sdmem2block_dma_base_re $0\main_sdmem2block_dma_base_re[0:0] + update \main_sdmem2block_dma_length_storage $0\main_sdmem2block_dma_length_storage[31:0] + update \main_sdmem2block_dma_length_re $0\main_sdmem2block_dma_length_re[0:0] + update \main_sdmem2block_dma_enable_storage $0\main_sdmem2block_dma_enable_storage[0:0] + update \main_sdmem2block_dma_enable_re $0\main_sdmem2block_dma_enable_re[0:0] + update \main_sdmem2block_dma_loop_storage $0\main_sdmem2block_dma_loop_storage[0:0] + update \main_sdmem2block_dma_loop_re $0\main_sdmem2block_dma_loop_re[0:0] + update \main_sdmem2block_dma_offset $0\main_sdmem2block_dma_offset[31:0] + update \main_sdmem2block_converter_mux $0\main_sdmem2block_converter_mux[1:0] + update \main_sdmem2block_fifo_level $0\main_sdmem2block_fifo_level[5:0] + update \main_sdmem2block_fifo_produce $0\main_sdmem2block_fifo_produce[4:0] + update \main_sdmem2block_fifo_consume $0\main_sdmem2block_fifo_consume[4:0] + update \libresocsim_miso $0\libresocsim_miso[7:0] + update \libresocsim_control_storage $0\libresocsim_control_storage[15:0] + update \libresocsim_control_re $0\libresocsim_control_re[0:0] + update \libresocsim_mosi_storage $0\libresocsim_mosi_storage[7:0] + update \libresocsim_mosi_re $0\libresocsim_mosi_re[0:0] + update \libresocsim_cs_storage $0\libresocsim_cs_storage[0:0] + update \libresocsim_cs_re $0\libresocsim_cs_re[0:0] + update \libresocsim_loopback_storage $0\libresocsim_loopback_storage[0:0] + update \libresocsim_loopback_re $0\libresocsim_loopback_re[0:0] + update \libresocsim_count $0\libresocsim_count[2:0] + update \libresocsim_clk_divider1 $0\libresocsim_clk_divider1[15:0] + update \libresocsim_mosi_data $0\libresocsim_mosi_data[7:0] + update \libresocsim_mosi_sel $0\libresocsim_mosi_sel[2:0] + update \libresocsim_miso_data $0\libresocsim_miso_data[7:0] + update \libresocsim_storage $0\libresocsim_storage[15:0] + update \libresocsim_re $0\libresocsim_re[0:0] + update \builder_converter0_state $0\builder_converter0_state[0:0] + update \builder_converter1_state $0\builder_converter1_state[0:0] + update \builder_converter2_state $0\builder_converter2_state[0:0] + update \builder_refresher_state $0\builder_refresher_state[1:0] + update \builder_bankmachine0_state $0\builder_bankmachine0_state[2:0] + update \builder_bankmachine1_state $0\builder_bankmachine1_state[2:0] + update \builder_bankmachine2_state $0\builder_bankmachine2_state[2:0] + update \builder_bankmachine3_state $0\builder_bankmachine3_state[2:0] + update \builder_multiplexer_state $0\builder_multiplexer_state[2:0] + update \builder_new_master_wdata_ready $0\builder_new_master_wdata_ready[0:0] + update \builder_new_master_rdata_valid0 $0\builder_new_master_rdata_valid0[0:0] + update \builder_new_master_rdata_valid1 $0\builder_new_master_rdata_valid1[0:0] + update \builder_new_master_rdata_valid2 $0\builder_new_master_rdata_valid2[0:0] + update \builder_new_master_rdata_valid3 $0\builder_new_master_rdata_valid3[0:0] + update \builder_converter_state $0\builder_converter_state[0:0] + update \builder_spimaster0_state $0\builder_spimaster0_state[1:0] + update \builder_sdphy_sdphyinit_state $0\builder_sdphy_sdphyinit_state[0:0] + update \builder_sdphy_sdphycmdw_state $0\builder_sdphy_sdphycmdw_state[1:0] + update \builder_sdphy_sdphycmdr_state $0\builder_sdphy_sdphycmdr_state[2:0] + update \builder_sdphy_sdphycrcr_state $0\builder_sdphy_sdphycrcr_state[0:0] + update \builder_sdphy_fsm_state $0\builder_sdphy_fsm_state[2:0] + update \builder_sdphy_sdphydatar_state $0\builder_sdphy_sdphydatar_state[2:0] + update \builder_sdcore_crcupstreaminserter_state $0\builder_sdcore_crcupstreaminserter_state[0:0] + update \builder_sdcore_fsm_state $0\builder_sdcore_fsm_state[2:0] + update \builder_sdblock2memdma_state $0\builder_sdblock2memdma_state[1:0] + update \builder_sdmem2blockdma_fsm_state $0\builder_sdmem2blockdma_fsm_state[0:0] + update \builder_sdmem2blockdma_resetinserter_state $0\builder_sdmem2blockdma_resetinserter_state[1:0] + update \builder_spimaster1_state $0\builder_spimaster1_state[1:0] + update \builder_libresocsim_adr $0\builder_libresocsim_adr[13:0] + update \builder_libresocsim_we $0\builder_libresocsim_we[0:0] + update \builder_libresocsim_dat_w $0\builder_libresocsim_dat_w[7:0] + update \builder_grant $0\builder_grant[2:0] + update \builder_slave_sel_r $0\builder_slave_sel_r[4:0] + update \builder_count $0\builder_count[19:0] + update \builder_interface0_bank_bus_dat_r $0\builder_interface0_bank_bus_dat_r[7:0] + update \builder_interface1_bank_bus_dat_r $0\builder_interface1_bank_bus_dat_r[7:0] + update \builder_interface2_bank_bus_dat_r $0\builder_interface2_bank_bus_dat_r[7:0] + update \builder_interface3_bank_bus_dat_r $0\builder_interface3_bank_bus_dat_r[7:0] + update \builder_interface4_bank_bus_dat_r $0\builder_interface4_bank_bus_dat_r[7:0] + update \builder_interface5_bank_bus_dat_r $0\builder_interface5_bank_bus_dat_r[7:0] + update \builder_interface6_bank_bus_dat_r $0\builder_interface6_bank_bus_dat_r[7:0] + update \builder_interface7_bank_bus_dat_r $0\builder_interface7_bank_bus_dat_r[7:0] + update \builder_interface8_bank_bus_dat_r $0\builder_interface8_bank_bus_dat_r[7:0] + update \builder_interface9_bank_bus_dat_r $0\builder_interface9_bank_bus_dat_r[7:0] + update \builder_interface10_bank_bus_dat_r $0\builder_interface10_bank_bus_dat_r[7:0] + update \builder_interface11_bank_bus_dat_r $0\builder_interface11_bank_bus_dat_r[7:0] + update \builder_interface12_bank_bus_dat_r $0\builder_interface12_bank_bus_dat_r[7:0] + update \builder_interface13_bank_bus_dat_r $0\builder_interface13_bank_bus_dat_r[7:0] + update \builder_state $0\builder_state[1:0] + update \builder_multiregimpl0_regs0 $0\builder_multiregimpl0_regs0[0:0] + update \builder_multiregimpl0_regs1 $0\builder_multiregimpl0_regs1[0:0] + update \builder_multiregimpl1_regs0 $0\builder_multiregimpl1_regs0[0:0] + update \builder_multiregimpl1_regs1 $0\builder_multiregimpl1_regs1[0:0] + update \builder_multiregimpl2_regs0 $0\builder_multiregimpl2_regs0[0:0] + update \builder_multiregimpl2_regs1 $0\builder_multiregimpl2_regs1[0:0] + update \builder_multiregimpl3_regs0 $0\builder_multiregimpl3_regs0[0:0] + update \builder_multiregimpl3_regs1 $0\builder_multiregimpl3_regs1[0:0] + update \builder_multiregimpl4_regs0 $0\builder_multiregimpl4_regs0[0:0] + update \builder_multiregimpl4_regs1 $0\builder_multiregimpl4_regs1[0:0] + update \builder_multiregimpl5_regs0 $0\builder_multiregimpl5_regs0[0:0] + update \builder_multiregimpl5_regs1 $0\builder_multiregimpl5_regs1[0:0] + update \builder_multiregimpl6_regs0 $0\builder_multiregimpl6_regs0[0:0] + update \builder_multiregimpl6_regs1 $0\builder_multiregimpl6_regs1[0:0] + update \builder_multiregimpl7_regs0 $0\builder_multiregimpl7_regs0[0:0] + update \builder_multiregimpl7_regs1 $0\builder_multiregimpl7_regs1[0:0] + update \builder_multiregimpl8_regs0 $0\builder_multiregimpl8_regs0[0:0] + update \builder_multiregimpl8_regs1 $0\builder_multiregimpl8_regs1[0:0] + update \builder_multiregimpl9_regs0 $0\builder_multiregimpl9_regs0[0:0] + update \builder_multiregimpl9_regs1 $0\builder_multiregimpl9_regs1[0:0] + update \builder_multiregimpl10_regs0 $0\builder_multiregimpl10_regs0[0:0] + update \builder_multiregimpl10_regs1 $0\builder_multiregimpl10_regs1[0:0] + update \builder_multiregimpl11_regs0 $0\builder_multiregimpl11_regs0[0:0] + update \builder_multiregimpl11_regs1 $0\builder_multiregimpl11_regs1[0:0] + update \builder_multiregimpl12_regs0 $0\builder_multiregimpl12_regs0[0:0] + update \builder_multiregimpl12_regs1 $0\builder_multiregimpl12_regs1[0:0] + update \builder_multiregimpl13_regs0 $0\builder_multiregimpl13_regs0[0:0] + update \builder_multiregimpl13_regs1 $0\builder_multiregimpl13_regs1[0:0] + update \builder_multiregimpl14_regs0 $0\builder_multiregimpl14_regs0[0:0] + update \builder_multiregimpl14_regs1 $0\builder_multiregimpl14_regs1[0:0] + update \builder_multiregimpl15_regs0 $0\builder_multiregimpl15_regs0[0:0] + update \builder_multiregimpl15_regs1 $0\builder_multiregimpl15_regs1[0:0] + update \builder_multiregimpl16_regs0 $0\builder_multiregimpl16_regs0[0:0] + update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0] end - attribute \src "issuer_ls180.v:176018.7-176018.20" - process $proc$issuer_ls180.v:176018$12917 + attribute \src "ls180.v:736.5-736.49" + process $proc$ls180.v:736$3050 assign { } { } - assign $0\initial[0:0] 1'0 + assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 sync always - update \initial $0\initial[0:0] sync init + update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] end - attribute \src "issuer_ls180.v:176144.13-176144.33" - process $proc$issuer_ls180.v:176144$12918 + attribute \src "ls180.v:737.5-737.48" + process $proc$ls180.v:737$3051 assign { } { } - assign $1\core_asmcode[7:0] 8'00000000 + assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 sync always sync init - update \core_asmcode $1\core_asmcode[7:0] + update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0] end - attribute \src "issuer_ls180.v:176150.7-176150.34" - process $proc$issuer_ls180.v:176150$12919 + attribute \src "ls180.v:741.11-741.46" + process $proc$ls180.v:741$3052 assign { } { } - assign $0\core_bigendian_i$3[0:0]$12920 1'0 + assign $1\main_sdram_choose_req_valids[3:0] 4'0000 sync always sync init - update \core_bigendian_i$3 $0\core_bigendian_i$3[0:0]$12920 + update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] end - attribute \src "issuer_ls180.v:176158.14-176158.55" - process $proc$issuer_ls180.v:176158$12921 + attribute \src "ls180.v:743.11-743.45" + process $proc$ls180.v:743$3053 assign { } { } - assign $1\core_core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\main_sdram_choose_req_grant[1:0] 2'00 sync always sync init - update \core_core_core_cia $1\core_core_core_cia[63:0] + update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0] end - attribute \src "issuer_ls180.v:176162.13-176162.41" - process $proc$issuer_ls180.v:176162$12922 + attribute \src "ls180.v:745.12-745.36" + process $proc$ls180.v:745$3054 assign { } { } - assign $1\core_core_core_cr_rd[7:0] 8'00000000 + assign $0\main_sdram_nop_a[12:0] 13'0000000000000 sync always + update \main_sdram_nop_a $0\main_sdram_nop_a[12:0] sync init - update \core_core_core_cr_rd $1\core_core_core_cr_rd[7:0] end - attribute \src "issuer_ls180.v:176166.7-176166.37" - process $proc$issuer_ls180.v:176166$12923 + attribute \src "ls180.v:746.11-746.35" + process $proc$ls180.v:746$3055 assign { } { } - assign $1\core_core_core_cr_rd_ok[0:0] 1'0 + assign $0\main_sdram_nop_ba[1:0] 2'00 sync always + update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0] sync init - update \core_core_core_cr_rd_ok $1\core_core_core_cr_rd_ok[0:0] end - attribute \src "issuer_ls180.v:176170.13-176170.41" - process $proc$issuer_ls180.v:176170$12924 + attribute \src "ls180.v:747.11-747.40" + process $proc$ls180.v:747$3056 assign { } { } - assign $1\core_core_core_cr_wr[7:0] 8'00000000 + assign $1\main_sdram_steerer_sel[1:0] 2'00 sync always sync init - update \core_core_core_cr_wr $1\core_core_core_cr_wr[7:0] + update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0] end - attribute \src "issuer_ls180.v:176187.14-176187.46" - process $proc$issuer_ls180.v:176187$12925 + attribute \src "ls180.v:748.5-748.31" + process $proc$ls180.v:748$3057 assign { } { } - assign $1\core_core_core_fn_unit[11:0] 12'000000000000 + assign $0\main_sdram_steerer0[0:0] 1'1 sync always + update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0] sync init - update \core_core_core_fn_unit $1\core_core_core_fn_unit[11:0] end - attribute \src "issuer_ls180.v:176195.13-176195.46" - process $proc$issuer_ls180.v:176195$12926 + attribute \src "ls180.v:749.5-749.31" + process $proc$ls180.v:749$3058 assign { } { } - assign $1\core_core_core_input_carry[1:0] 2'00 + assign $0\main_sdram_steerer1[0:0] 1'1 sync always + update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0] sync init - update \core_core_core_input_carry $1\core_core_core_input_carry[1:0] end - attribute \src "issuer_ls180.v:176199.14-176199.41" - process $proc$issuer_ls180.v:176199$12927 + attribute \src "ls180.v:751.32-751.63" + process $proc$ls180.v:751$3059 assign { } { } - assign $1\core_core_core_insn[31:0] 0 + assign $0\main_sdram_trrdcon_ready[0:0] 1'1 sync always + update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0] sync init - update \core_core_core_insn $1\core_core_core_insn[31:0] end - attribute \src "issuer_ls180.v:176277.13-176277.45" - process $proc$issuer_ls180.v:176277$12928 + attribute \src "ls180.v:753.32-753.63" + process $proc$ls180.v:753$3060 assign { } { } - assign $1\core_core_core_insn_type[6:0] 7'0000000 + assign $0\main_sdram_tfawcon_ready[0:0] 1'1 sync always + update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0] sync init - update \core_core_core_insn_type $1\core_core_core_insn_type[6:0] end - attribute \src "issuer_ls180.v:176281.7-176281.37" - process $proc$issuer_ls180.v:176281$12929 + attribute \src "ls180.v:755.32-755.63" + process $proc$ls180.v:755$3061 assign { } { } - assign $1\core_core_core_is_32bit[0:0] 1'0 + assign $1\main_sdram_tccdcon_ready[0:0] 1'0 sync always sync init - update \core_core_core_is_32bit $1\core_core_core_is_32bit[0:0] + update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0] end - attribute \src "issuer_ls180.v:176285.14-176285.55" - process $proc$issuer_ls180.v:176285$12930 + attribute \src "ls180.v:756.5-756.36" + process $proc$ls180.v:756$3062 assign { } { } - assign $1\core_core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\main_sdram_tccdcon_count[0:0] 1'0 sync always sync init - update \core_core_core_msr $1\core_core_core_msr[63:0] + update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0] end - attribute \src "issuer_ls180.v:176289.7-176289.31" - process $proc$issuer_ls180.v:176289$12931 + attribute \src "ls180.v:758.32-758.63" + process $proc$ls180.v:758$3063 assign { } { } - assign $1\core_core_core_oe[0:0] 1'0 + assign $1\main_sdram_twtrcon_ready[0:0] 1'0 sync always sync init - update \core_core_core_oe $1\core_core_core_oe[0:0] + update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] end - attribute \src "issuer_ls180.v:176293.7-176293.34" - process $proc$issuer_ls180.v:176293$12932 + attribute \src "ls180.v:759.11-759.42" + process $proc$ls180.v:759$3064 assign { } { } - assign $1\core_core_core_oe_ok[0:0] 1'0 + assign $1\main_sdram_twtrcon_count[2:0] 3'000 sync always sync init - update \core_core_core_oe_ok $1\core_core_core_oe_ok[0:0] + update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] end - attribute \src "issuer_ls180.v:176297.7-176297.31" - process $proc$issuer_ls180.v:176297$12933 + attribute \src "ls180.v:762.5-762.26" + process $proc$ls180.v:762$3065 assign { } { } - assign $1\core_core_core_rc[0:0] 1'0 + assign $1\main_sdram_en0[0:0] 1'0 sync always sync init - update \core_core_core_rc $1\core_core_core_rc[0:0] + update \main_sdram_en0 $1\main_sdram_en0[0:0] end - attribute \src "issuer_ls180.v:176301.7-176301.34" - process $proc$issuer_ls180.v:176301$12934 + attribute \src "ls180.v:764.11-764.34" + process $proc$ls180.v:764$3066 assign { } { } - assign $1\core_core_core_rc_ok[0:0] 1'0 + assign $1\main_sdram_time0[4:0] 5'00000 sync always sync init - update \core_core_core_rc_ok $1\core_core_core_rc_ok[0:0] + update \main_sdram_time0 $1\main_sdram_time0[4:0] end - attribute \src "issuer_ls180.v:176305.14-176305.48" - process $proc$issuer_ls180.v:176305$12935 + attribute \src "ls180.v:765.5-765.26" + process $proc$ls180.v:765$3067 assign { } { } - assign $1\core_core_core_trapaddr[12:0] 13'0000000000000 + assign $1\main_sdram_en1[0:0] 1'0 sync always sync init - update \core_core_core_trapaddr $1\core_core_core_trapaddr[12:0] + update \main_sdram_en1 $1\main_sdram_en1[0:0] end - attribute \src "issuer_ls180.v:176309.13-176309.44" - process $proc$issuer_ls180.v:176309$12936 + attribute \src "ls180.v:767.11-767.34" + process $proc$ls180.v:767$3068 assign { } { } - assign $1\core_core_core_traptype[6:0] 7'0000000 + assign $1\main_sdram_time1[3:0] 4'0000 sync always sync init - update \core_core_core_traptype $1\core_core_core_traptype[6:0] + update \main_sdram_time1 $1\main_sdram_time1[3:0] end - attribute \src "issuer_ls180.v:176313.13-176313.36" - process $proc$issuer_ls180.v:176313$12937 + attribute \src "ls180.v:77.5-77.46" + process $proc$ls180.v:77$2775 assign { } { } - assign $1\core_core_cr_in1[2:0] 3'000 + assign $1\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 sync always sync init - update \core_core_cr_in1 $1\core_core_cr_in1[2:0] + update \main_libresocsim_libresoc_ibus_ack $1\main_libresocsim_libresoc_ibus_ack[0:0] end - attribute \src "issuer_ls180.v:176317.7-176317.33" - process $proc$issuer_ls180.v:176317$12938 + attribute \src "ls180.v:788.5-788.29" + process $proc$ls180.v:788$3069 assign { } { } - assign $1\core_core_cr_in1_ok[0:0] 1'0 + assign $1\main_wb_sdram_ack[0:0] 1'0 sync always sync init - update \core_core_cr_in1_ok $1\core_core_cr_in1_ok[0:0] + update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] end - attribute \src "issuer_ls180.v:176321.13-176321.36" - process $proc$issuer_ls180.v:176321$12939 + attribute \src "ls180.v:792.5-792.29" + process $proc$ls180.v:792$3070 assign { } { } - assign $1\core_core_cr_in2[2:0] 3'000 + assign $0\main_wb_sdram_err[0:0] 1'0 sync always + update \main_wb_sdram_err $0\main_wb_sdram_err[0:0] sync init - update \core_core_cr_in2 $1\core_core_cr_in2[2:0] end - attribute \src "issuer_ls180.v:176323.13-176323.40" - process $proc$issuer_ls180.v:176323$12940 + attribute \src "ls180.v:793.12-793.40" + process $proc$ls180.v:793$3071 assign { } { } - assign $0\core_core_cr_in2$1[2:0]$12941 3'000 + assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 sync always sync init - update \core_core_cr_in2$1 $0\core_core_cr_in2$1[2:0]$12941 + update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0] end - attribute \src "issuer_ls180.v:176329.7-176329.33" - process $proc$issuer_ls180.v:176329$12942 + attribute \src "ls180.v:794.12-794.42" + process $proc$ls180.v:794$3072 assign { } { } - assign $1\core_core_cr_in2_ok[0:0] 1'0 + assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000 sync always sync init - update \core_core_cr_in2_ok $1\core_core_cr_in2_ok[0:0] + update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0] end - attribute \src "issuer_ls180.v:176331.7-176331.37" - process $proc$issuer_ls180.v:176331$12943 + attribute \src "ls180.v:796.11-796.38" + process $proc$ls180.v:796$3073 assign { } { } - assign $0\core_core_cr_in2_ok$2[0:0]$12944 1'0 + assign $1\main_litedram_wb_sel[1:0] 2'00 sync always sync init - update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$12944 + update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0] end - attribute \src "issuer_ls180.v:176337.13-176337.36" - process $proc$issuer_ls180.v:176337$12945 + attribute \src "ls180.v:797.5-797.32" + process $proc$ls180.v:797$3074 assign { } { } - assign $1\core_core_cr_out[2:0] 3'000 + assign $1\main_litedram_wb_cyc[0:0] 1'0 sync always sync init - update \core_core_cr_out $1\core_core_cr_out[2:0] + update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] end - attribute \src "issuer_ls180.v:176341.7-176341.32" - process $proc$issuer_ls180.v:176341$12946 + attribute \src "ls180.v:798.5-798.32" + process $proc$ls180.v:798$3075 assign { } { } - assign $1\core_core_cr_wr_ok[0:0] 1'0 + assign $1\main_litedram_wb_stb[0:0] 1'0 sync always sync init - update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0] + update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] end - attribute \src "issuer_ls180.v:176345.13-176345.33" - process $proc$issuer_ls180.v:176345$12947 + attribute \src "ls180.v:800.5-800.31" + process $proc$ls180.v:800$3076 assign { } { } - assign $1\core_core_ea[4:0] 5'00000 + assign $1\main_litedram_wb_we[0:0] 1'0 sync always sync init - update \core_core_ea $1\core_core_ea[4:0] + update \main_litedram_wb_we $1\main_litedram_wb_we[0:0] end - attribute \src "issuer_ls180.v:176349.13-176349.35" - process $proc$issuer_ls180.v:176349$12948 + attribute \src "ls180.v:801.5-801.31" + process $proc$ls180.v:801$3077 assign { } { } - assign $1\core_core_fast1[2:0] 3'000 + assign $1\main_converter_skip[0:0] 1'0 sync always sync init - update \core_core_fast1 $1\core_core_fast1[2:0] + update \main_converter_skip $1\main_converter_skip[0:0] end - attribute \src "issuer_ls180.v:176353.7-176353.32" - process $proc$issuer_ls180.v:176353$12949 + attribute \src "ls180.v:802.5-802.34" + process $proc$ls180.v:802$3078 assign { } { } - assign $1\core_core_fast1_ok[0:0] 1'0 + assign $1\main_converter_counter[0:0] 1'0 sync always sync init - update \core_core_fast1_ok $1\core_core_fast1_ok[0:0] + update \main_converter_counter $1\main_converter_counter[0:0] end - attribute \src "issuer_ls180.v:176357.13-176357.35" - process $proc$issuer_ls180.v:176357$12950 + attribute \src "ls180.v:804.12-804.40" + process $proc$ls180.v:804$3079 assign { } { } - assign $1\core_core_fast2[2:0] 3'000 + assign $1\main_converter_dat_r[31:0] 0 sync always sync init - update \core_core_fast2 $1\core_core_fast2[2:0] + update \main_converter_dat_r $1\main_converter_dat_r[31:0] end - attribute \src "issuer_ls180.v:176361.7-176361.32" - process $proc$issuer_ls180.v:176361$12951 + attribute \src "ls180.v:805.5-805.29" + process $proc$ls180.v:805$3080 assign { } { } - assign $1\core_core_fast2_ok[0:0] 1'0 + assign $1\main_cmd_consumed[0:0] 1'0 sync always sync init - update \core_core_fast2_ok $1\core_core_fast2_ok[0:0] + update \main_cmd_consumed $1\main_cmd_consumed[0:0] end - attribute \src "issuer_ls180.v:176365.13-176365.36" - process $proc$issuer_ls180.v:176365$12952 + attribute \src "ls180.v:806.5-806.31" + process $proc$ls180.v:806$3081 assign { } { } - assign $1\core_core_fasto1[2:0] 3'000 + assign $1\main_wdata_consumed[0:0] 1'0 sync always sync init - update \core_core_fasto1 $1\core_core_fasto1[2:0] + update \main_wdata_consumed $1\main_wdata_consumed[0:0] end - attribute \src "issuer_ls180.v:176369.13-176369.36" - process $proc$issuer_ls180.v:176369$12953 + attribute \src "ls180.v:81.5-81.46" + process $proc$ls180.v:81$2776 assign { } { } - assign $1\core_core_fasto2[2:0] 3'000 + assign $0\main_libresocsim_libresoc_ibus_err[0:0] 1'0 sync always + update \main_libresocsim_libresoc_ibus_err $0\main_libresocsim_libresoc_ibus_err[0:0] sync init - update \core_core_fasto2 $1\core_core_fasto2[2:0] end - attribute \src "issuer_ls180.v:176373.7-176373.26" - process $proc$issuer_ls180.v:176373$12954 + attribute \src "ls180.v:810.12-810.38" + process $proc$ls180.v:810$3082 assign { } { } - assign $1\core_core_lk[0:0] 1'0 + assign $1\main_storage[31:0] 9895604 sync always sync init - update \core_core_lk $1\core_core_lk[0:0] + update \main_storage $1\main_storage[31:0] end - attribute \src "issuer_ls180.v:176377.14-176377.49" - process $proc$issuer_ls180.v:176377$12955 + attribute \src "ls180.v:811.5-811.19" + process $proc$ls180.v:811$3083 assign { } { } - assign $1\core_core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\main_re[0:0] 1'0 sync always sync init - update \core_core_pc $1\core_core_pc[63:0] + update \main_re $1\main_re[0:0] end - attribute \src "issuer_ls180.v:176381.13-176381.35" - process $proc$issuer_ls180.v:176381$12956 + attribute \src "ls180.v:813.5-813.27" + process $proc$ls180.v:813$3084 assign { } { } - assign $1\core_core_reg1[4:0] 5'00000 + assign $1\main_sink_ready[0:0] 1'0 sync always sync init - update \core_core_reg1 $1\core_core_reg1[4:0] + update \main_sink_ready $1\main_sink_ready[0:0] end - attribute \src "issuer_ls180.v:176385.7-176385.31" - process $proc$issuer_ls180.v:176385$12957 + attribute \src "ls180.v:817.5-817.30" + process $proc$ls180.v:817$3085 assign { } { } - assign $1\core_core_reg1_ok[0:0] 1'0 + assign $1\main_uart_clk_txen[0:0] 1'0 sync always sync init - update \core_core_reg1_ok $1\core_core_reg1_ok[0:0] + update \main_uart_clk_txen $1\main_uart_clk_txen[0:0] end - attribute \src "issuer_ls180.v:176389.13-176389.35" - process $proc$issuer_ls180.v:176389$12958 + attribute \src "ls180.v:818.12-818.45" + process $proc$ls180.v:818$3086 assign { } { } - assign $1\core_core_reg2[4:0] 5'00000 + assign $1\main_phase_accumulator_tx[31:0] 0 sync always sync init - update \core_core_reg2 $1\core_core_reg2[4:0] + update \main_phase_accumulator_tx $1\main_phase_accumulator_tx[31:0] end - attribute \src "issuer_ls180.v:176393.7-176393.31" - process $proc$issuer_ls180.v:176393$12959 + attribute \src "ls180.v:819.11-819.29" + process $proc$ls180.v:819$3087 assign { } { } - assign $1\core_core_reg2_ok[0:0] 1'0 + assign $1\main_tx_reg[7:0] 8'00000000 sync always sync init - update \core_core_reg2_ok $1\core_core_reg2_ok[0:0] + update \main_tx_reg $1\main_tx_reg[7:0] end - attribute \src "issuer_ls180.v:176397.13-176397.35" - process $proc$issuer_ls180.v:176397$12960 + attribute \src "ls180.v:820.11-820.34" + process $proc$ls180.v:820$3088 assign { } { } - assign $1\core_core_reg3[4:0] 5'00000 + assign $1\main_tx_bitcount[3:0] 4'0000 sync always sync init - update \core_core_reg3 $1\core_core_reg3[4:0] + update \main_tx_bitcount $1\main_tx_bitcount[3:0] end - attribute \src "issuer_ls180.v:176401.7-176401.31" - process $proc$issuer_ls180.v:176401$12961 + attribute \src "ls180.v:821.5-821.24" + process $proc$ls180.v:821$3089 assign { } { } - assign $1\core_core_reg3_ok[0:0] 1'0 + assign $1\main_tx_busy[0:0] 1'0 sync always sync init - update \core_core_reg3_ok $1\core_core_reg3_ok[0:0] + update \main_tx_busy $1\main_tx_busy[0:0] end - attribute \src "issuer_ls180.v:176405.13-176405.35" - process $proc$issuer_ls180.v:176405$12962 + attribute \src "ls180.v:822.5-822.29" + process $proc$ls180.v:822$3090 assign { } { } - assign $1\core_core_rego[4:0] 5'00000 + assign $1\main_source_valid[0:0] 1'0 sync always sync init - update \core_core_rego $1\core_core_rego[4:0] + update \main_source_valid $1\main_source_valid[0:0] end - attribute \src "issuer_ls180.v:176522.13-176522.37" - process $proc$issuer_ls180.v:176522$12963 + attribute \src "ls180.v:824.5-824.29" + process $proc$ls180.v:824$3091 assign { } { } - assign $1\core_core_spr1[9:0] 10'0000000000 + assign $0\main_source_first[0:0] 1'0 sync always + update \main_source_first $0\main_source_first[0:0] sync init - update \core_core_spr1 $1\core_core_spr1[9:0] end - attribute \src "issuer_ls180.v:176526.7-176526.31" - process $proc$issuer_ls180.v:176526$12964 + attribute \src "ls180.v:825.5-825.28" + process $proc$ls180.v:825$3092 assign { } { } - assign $1\core_core_spr1_ok[0:0] 1'0 + assign $0\main_source_last[0:0] 1'0 sync always + update \main_source_last $0\main_source_last[0:0] sync init - update \core_core_spr1_ok $1\core_core_spr1_ok[0:0] end - attribute \src "issuer_ls180.v:176641.13-176641.37" - process $proc$issuer_ls180.v:176641$12965 + attribute \src "ls180.v:826.11-826.42" + process $proc$ls180.v:826$3093 assign { } { } - assign $1\core_core_spro[9:0] 10'0000000000 + assign $1\main_source_payload_data[7:0] 8'00000000 sync always sync init - update \core_core_spro $1\core_core_spro[9:0] + update \main_source_payload_data $1\main_source_payload_data[7:0] end - attribute \src "issuer_ls180.v:176647.13-176647.36" - process $proc$issuer_ls180.v:176647$12966 + attribute \src "ls180.v:827.5-827.30" + process $proc$ls180.v:827$3094 assign { } { } - assign $1\core_core_xer_in[2:0] 3'000 + assign $1\main_uart_clk_rxen[0:0] 1'0 sync always sync init - update \core_core_xer_in $1\core_core_xer_in[2:0] + update \main_uart_clk_rxen $1\main_uart_clk_rxen[0:0] end - attribute \src "issuer_ls180.v:176655.7-176655.28" - process $proc$issuer_ls180.v:176655$12967 + attribute \src "ls180.v:828.12-828.45" + process $proc$ls180.v:828$3095 assign { } { } - assign $1\core_cr_out_ok[0:0] 1'0 + assign $1\main_phase_accumulator_rx[31:0] 0 sync always sync init - update \core_cr_out_ok $1\core_cr_out_ok[0:0] + update \main_phase_accumulator_rx $1\main_phase_accumulator_rx[31:0] end - attribute \src "issuer_ls180.v:176669.14-176669.45" - process $proc$issuer_ls180.v:176669$12968 + attribute \src "ls180.v:830.5-830.21" + process $proc$ls180.v:830$3096 assign { } { } - assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\main_rx_r[0:0] 1'0 sync always sync init - update \core_dec $1\core_dec[63:0] + update \main_rx_r $1\main_rx_r[0:0] end - attribute \src "issuer_ls180.v:176679.7-176679.24" - process $proc$issuer_ls180.v:176679$12969 + attribute \src "ls180.v:831.11-831.29" + process $proc$ls180.v:831$3097 assign { } { } - assign $1\core_ea_ok[0:0] 1'0 + assign $1\main_rx_reg[7:0] 8'00000000 sync always sync init - update \core_ea_ok $1\core_ea_ok[0:0] + update \main_rx_reg $1\main_rx_reg[7:0] end - attribute \src "issuer_ls180.v:176683.7-176683.23" - process $proc$issuer_ls180.v:176683$12970 + attribute \src "ls180.v:832.11-832.34" + process $proc$ls180.v:832$3098 assign { } { } - assign $1\core_eint[0:0] 1'0 + assign $1\main_rx_bitcount[3:0] 4'0000 sync always sync init - update \core_eint $1\core_eint[0:0] + update \main_rx_bitcount $1\main_rx_bitcount[3:0] end - attribute \src "issuer_ls180.v:176687.7-176687.28" - process $proc$issuer_ls180.v:176687$12971 + attribute \src "ls180.v:833.5-833.24" + process $proc$ls180.v:833$3099 assign { } { } - assign $1\core_fasto1_ok[0:0] 1'0 + assign $1\main_rx_busy[0:0] 1'0 sync always sync init - update \core_fasto1_ok $1\core_fasto1_ok[0:0] + update \main_rx_busy $1\main_rx_busy[0:0] end - attribute \src "issuer_ls180.v:176691.7-176691.28" - process $proc$issuer_ls180.v:176691$12972 + attribute \src "ls180.v:844.5-844.32" + process $proc$ls180.v:844$3100 assign { } { } - assign $1\core_fasto2_ok[0:0] 1'0 + assign $1\main_uart_tx_pending[0:0] 1'0 sync always sync init - update \core_fasto2_ok $1\core_fasto2_ok[0:0] + update \main_uart_tx_pending $1\main_uart_tx_pending[0:0] end - attribute \src "issuer_ls180.v:176719.14-176719.45" - process $proc$issuer_ls180.v:176719$12973 + attribute \src "ls180.v:846.5-846.30" + process $proc$ls180.v:846$3101 assign { } { } - assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\main_uart_tx_clear[0:0] 1'0 sync always sync init - update \core_msr $1\core_msr[63:0] + update \main_uart_tx_clear $1\main_uart_tx_clear[0:0] end - attribute \src "issuer_ls180.v:176727.14-176727.37" - process $proc$issuer_ls180.v:176727$12974 + attribute \src "ls180.v:847.5-847.36" + process $proc$ls180.v:847$3102 assign { } { } - assign $1\core_raw_insn_i[31:0] 0 + assign $1\main_uart_tx_old_trigger[0:0] 1'0 sync always sync init - update \core_raw_insn_i $1\core_raw_insn_i[31:0] + update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0] end - attribute \src "issuer_ls180.v:176731.7-176731.26" - process $proc$issuer_ls180.v:176731$12975 + attribute \src "ls180.v:849.5-849.32" + process $proc$ls180.v:849$3103 assign { } { } - assign $1\core_rego_ok[0:0] 1'0 + assign $1\main_uart_rx_pending[0:0] 1'0 sync always sync init - update \core_rego_ok $1\core_rego_ok[0:0] + update \main_uart_rx_pending $1\main_uart_rx_pending[0:0] end - attribute \src "issuer_ls180.v:176735.7-176735.26" - process $proc$issuer_ls180.v:176735$12976 + attribute \src "ls180.v:851.5-851.30" + process $proc$ls180.v:851$3104 assign { } { } - assign $1\core_spro_ok[0:0] 1'0 + assign $1\main_uart_rx_clear[0:0] 1'0 sync always sync init - update \core_spro_ok $1\core_spro_ok[0:0] + update \main_uart_rx_clear $1\main_uart_rx_clear[0:0] end - attribute \src "issuer_ls180.v:176745.7-176745.26" - process $proc$issuer_ls180.v:176745$12977 + attribute \src "ls180.v:852.5-852.36" + process $proc$ls180.v:852$3105 assign { } { } - assign $1\core_xer_out[0:0] 1'0 + assign $1\main_uart_rx_old_trigger[0:0] 1'0 sync always sync init - update \core_xer_out $1\core_xer_out[0:0] + update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0] end - attribute \src "issuer_ls180.v:176749.7-176749.30" - process $proc$issuer_ls180.v:176749$12978 + attribute \src "ls180.v:856.11-856.49" + process $proc$ls180.v:856$3106 assign { } { } - assign $1\cu_st__rel_o_dly[0:0] 1'0 + assign $1\main_uart_eventmanager_status_w[1:0] 2'00 sync always sync init - update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0] + update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0] end - attribute \src "issuer_ls180.v:176755.7-176755.24" - process $proc$issuer_ls180.v:176755$12979 + attribute \src "ls180.v:860.11-860.50" + process $proc$ls180.v:860$3107 assign { } { } - assign $1\d_cr_delay[0:0] 1'0 + assign $1\main_uart_eventmanager_pending_w[1:0] 2'00 sync always sync init - update \d_cr_delay $1\d_cr_delay[0:0] + update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0] end - attribute \src "issuer_ls180.v:176759.7-176759.25" - process $proc$issuer_ls180.v:176759$12980 + attribute \src "ls180.v:861.11-861.48" + process $proc$ls180.v:861$3108 assign { } { } - assign $1\d_reg_delay[0:0] 1'0 + assign $1\main_uart_eventmanager_storage[1:0] 2'00 sync always sync init - update \d_reg_delay $1\d_reg_delay[0:0] + update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0] end - attribute \src "issuer_ls180.v:176763.7-176763.25" - process $proc$issuer_ls180.v:176763$12981 + attribute \src "ls180.v:862.5-862.37" + process $proc$ls180.v:862$3109 assign { } { } - assign $1\d_xer_delay[0:0] 1'0 + assign $1\main_uart_eventmanager_re[0:0] 1'0 sync always sync init - update \d_xer_delay $1\d_xer_delay[0:0] + update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0] end - attribute \src "issuer_ls180.v:176851.14-176851.49" - process $proc$issuer_ls180.v:176851$12982 + attribute \src "ls180.v:879.5-879.40" + process $proc$ls180.v:879$3110 assign { } { } - assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 sync always + update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0] sync init - update \dec2_cur_dec $1\dec2_cur_dec[63:0] end - attribute \src "issuer_ls180.v:176855.7-176855.27" - process $proc$issuer_ls180.v:176855$12983 + attribute \src "ls180.v:880.5-880.39" + process $proc$ls180.v:880$3111 assign { } { } - assign $1\dec2_cur_eint[0:0] 1'0 + assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 sync always + update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0] sync init - update \dec2_cur_eint $1\dec2_cur_eint[0:0] end - attribute \src "issuer_ls180.v:176859.14-176859.49" - process $proc$issuer_ls180.v:176859$12984 + attribute \src "ls180.v:888.5-888.38" + process $proc$ls180.v:888$3112 assign { } { } - assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\main_uart_tx_fifo_readable[0:0] 1'0 sync always sync init - update \dec2_cur_msr $1\dec2_cur_msr[63:0] + update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] end - attribute \src "issuer_ls180.v:176863.14-176863.48" - process $proc$issuer_ls180.v:176863$12985 + attribute \src "ls180.v:895.11-895.42" + process $proc$ls180.v:895$3113 assign { } { } - assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\main_uart_tx_fifo_level0[4:0] 5'00000 sync always sync init - update \dec2_cur_pc $1\dec2_cur_pc[63:0] + update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0] end - attribute \src "issuer_ls180.v:177256.13-177256.25" - process $proc$issuer_ls180.v:177256$12986 + attribute \src "ls180.v:896.5-896.37" + process $proc$ls180.v:896$3114 assign { } { } - assign $1\delay[1:0] 2'11 + assign $0\main_uart_tx_fifo_replace[0:0] 1'0 sync always + update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0] sync init - update \delay $1\delay[1:0] end - attribute \src "issuer_ls180.v:177272.13-177272.29" - process $proc$issuer_ls180.v:177272$12987 + attribute \src "ls180.v:897.11-897.43" + process $proc$ls180.v:897$3115 assign { } { } - assign $1\fsm_state[1:0] 2'00 + assign $1\main_uart_tx_fifo_produce[3:0] 4'0000 sync always sync init - update \fsm_state $1\fsm_state[1:0] + update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0] end - attribute \src "issuer_ls180.v:177274.13-177274.35" - process $proc$issuer_ls180.v:177274$12988 + attribute \src "ls180.v:898.11-898.43" + process $proc$ls180.v:898$3116 assign { } { } - assign $0\fsm_state$117[1:0]$12989 2'00 + assign $1\main_uart_tx_fifo_consume[3:0] 4'0000 sync always sync init - update \fsm_state$117 $0\fsm_state$117[1:0]$12989 + update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0] end - attribute \src "issuer_ls180.v:177346.14-177346.28" - process $proc$issuer_ls180.v:177346$12990 + attribute \src "ls180.v:899.11-899.46" + process $proc$ls180.v:899$3117 assign { } { } - assign $1\ilatch[31:0] 0 + assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 sync always sync init - update \ilatch $1\ilatch[31:0] + update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] end - attribute \src "issuer_ls180.v:177364.7-177364.22" - process $proc$issuer_ls180.v:177364$12991 + attribute \src "ls180.v:925.5-925.38" + process $proc$ls180.v:925$3118 assign { } { } - assign $1\msr_read[0:0] 1'1 + assign $1\main_uart_rx_fifo_readable[0:0] 1'0 sync always sync init - update \msr_read $1\msr_read[0:0] + update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] end - attribute \src "issuer_ls180.v:177376.7-177376.24" - process $proc$issuer_ls180.v:177376$12992 + attribute \src "ls180.v:932.11-932.42" + process $proc$ls180.v:932$3119 assign { } { } - assign $1\pc_changed[0:0] 1'0 + assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 sync always sync init - update \pc_changed $1\pc_changed[0:0] + update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] end - attribute \src "issuer_ls180.v:177386.7-177386.25" - process $proc$issuer_ls180.v:177386$12993 + attribute \src "ls180.v:933.5-933.37" + process $proc$ls180.v:933$3120 assign { } { } - assign $1\pc_ok_delay[0:0] 1'0 + assign $0\main_uart_rx_fifo_replace[0:0] 1'0 sync always + update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0] sync init - update \pc_ok_delay $1\pc_ok_delay[0:0] end - attribute \src "issuer_ls180.v:177459.3-177460.41" - process $proc$issuer_ls180.v:177459$12497 + attribute \src "ls180.v:934.11-934.43" + process $proc$ls180.v:934$3121 assign { } { } - assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next - sync posedge \clk - update \dec2_cur_dec $0\dec2_cur_dec[63:0] + assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] end - attribute \src "issuer_ls180.v:177461.3-177462.33" - process $proc$issuer_ls180.v:177461$12498 + attribute \src "ls180.v:935.11-935.43" + process $proc$ls180.v:935$3122 assign { } { } - assign $0\core_dec[63:0] \core_dec$next - sync posedge \clk - update \core_dec $0\core_dec[63:0] + assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] end - attribute \src "issuer_ls180.v:177463.3-177464.41" - process $proc$issuer_ls180.v:177463$12499 + attribute \src "ls180.v:936.11-936.46" + process $proc$ls180.v:936$3123 assign { } { } - assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next - sync posedge \clk - update \dec2_cur_msr $0\dec2_cur_msr[63:0] + assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] end - attribute \src "issuer_ls180.v:177465.3-177466.35" - process $proc$issuer_ls180.v:177465$12500 + attribute \src "ls180.v:951.5-951.27" + process $proc$ls180.v:951$3124 assign { } { } - assign $0\fsm_state[1:0] \fsm_state$next - sync posedge \clk - update \fsm_state $0\fsm_state[1:0] + assign $0\main_uart_reset[0:0] 1'0 + sync always + update \main_uart_reset $0\main_uart_reset[0:0] + sync init end - attribute \src "issuer_ls180.v:177467.3-177468.33" - process $proc$issuer_ls180.v:177467$12501 + attribute \src "ls180.v:952.12-952.40" + process $proc$ls180.v:952$3125 assign { } { } - assign $0\msr_read[0:0] \msr_read$next - sync posedge \clk - update \msr_read $0\msr_read[0:0] + assign $1\main_gpio_oe_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpio_oe_storage $1\main_gpio_oe_storage[15:0] end - attribute \src "issuer_ls180.v:177469.3-177470.39" - process $proc$issuer_ls180.v:177469$12502 + attribute \src "ls180.v:953.5-953.27" + process $proc$ls180.v:953$3126 assign { } { } - assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next - sync posedge \clk - update \dec2_cur_pc $0\dec2_cur_pc[63:0] + assign $1\main_gpio_oe_re[0:0] 1'0 + sync always + sync init + update \main_gpio_oe_re $1\main_gpio_oe_re[0:0] end - attribute \src "issuer_ls180.v:177471.3-177472.55" - process $proc$issuer_ls180.v:177471$12503 + attribute \src "ls180.v:954.12-954.36" + process $proc$ls180.v:954$3127 assign { } { } - assign $0\core_bigendian_i$3[0:0]$12504 \core_bigendian_i$3$next - sync posedge \clk - update \core_bigendian_i$3 $0\core_bigendian_i$3[0:0]$12504 + assign $1\main_gpio_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpio_status $1\main_gpio_status[15:0] end - attribute \src "issuer_ls180.v:177473.3-177474.47" - process $proc$issuer_ls180.v:177473$12505 + attribute \src "ls180.v:956.12-956.41" + process $proc$ls180.v:956$3128 assign { } { } - assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next - sync posedge \clk - update \core_raw_insn_i $0\core_raw_insn_i[31:0] + assign $1\main_gpio_out_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpio_out_storage $1\main_gpio_out_storage[15:0] end - attribute \src "issuer_ls180.v:177475.3-177476.41" - process $proc$issuer_ls180.v:177475$12506 + attribute \src "ls180.v:957.5-957.28" + process $proc$ls180.v:957$3129 assign { } { } - assign $0\core_asmcode[7:0] \core_asmcode$next - sync posedge \clk - update \core_asmcode $0\core_asmcode[7:0] + assign $1\main_gpio_out_re[0:0] 1'0 + sync always + sync init + update \main_gpio_out_re $1\main_gpio_out_re[0:0] end - attribute \src "issuer_ls180.v:177477.3-177478.45" - process $proc$issuer_ls180.v:177477$12507 + attribute \src "ls180.v:963.5-963.33" + process $proc$ls180.v:963$3130 assign { } { } - assign $0\core_core_rego[4:0] \core_core_rego$next - sync posedge \clk - update \core_core_rego $0\core_core_rego[4:0] + assign $1\main_spi_master_done0[0:0] 1'0 + sync always + sync init + update \main_spi_master_done0 $1\main_spi_master_done0[0:0] end - attribute \src "issuer_ls180.v:177479.3-177480.41" - process $proc$issuer_ls180.v:177479$12508 + attribute \src "ls180.v:964.5-964.31" + process $proc$ls180.v:964$3131 assign { } { } - assign $0\core_rego_ok[0:0] \core_rego_ok$next - sync posedge \clk - update \core_rego_ok $0\core_rego_ok[0:0] + assign $1\main_spi_master_irq[0:0] 1'0 + sync always + sync init + update \main_spi_master_irq $1\main_spi_master_irq[0:0] end - attribute \src "issuer_ls180.v:177481.3-177482.45" - process $proc$issuer_ls180.v:177481$12509 + attribute \src "ls180.v:966.11-966.38" + process $proc$ls180.v:966$3132 assign { } { } - assign $0\fsm_state$117[1:0]$12510 \fsm_state$117$next - sync posedge \clk - update \fsm_state$117 $0\fsm_state$117[1:0]$12510 + assign $1\main_spi_master_miso[7:0] 8'00000000 + sync always + sync init + update \main_spi_master_miso $1\main_spi_master_miso[7:0] end - attribute \src "issuer_ls180.v:177483.3-177484.41" - process $proc$issuer_ls180.v:177483$12511 + attribute \src "ls180.v:969.12-969.48" + process $proc$ls180.v:969$3133 assign { } { } - assign $0\core_core_ea[4:0] \core_core_ea$next - sync posedge \clk - update \core_core_ea $0\core_core_ea[4:0] + assign $0\main_spi_master_clk_divider0[15:0] 16'0000000000000111 + sync always + update \main_spi_master_clk_divider0 $0\main_spi_master_clk_divider0[15:0] + sync init end - attribute \src "issuer_ls180.v:177485.3-177486.37" - process $proc$issuer_ls180.v:177485$12512 + attribute \src "ls180.v:970.5-970.34" + process $proc$ls180.v:970$3134 assign { } { } - assign $0\core_ea_ok[0:0] \core_ea_ok$next - sync posedge \clk - update \core_ea_ok $0\core_ea_ok[0:0] + assign $1\main_spi_master_start1[0:0] 1'0 + sync always + sync init + update \main_spi_master_start1 $1\main_spi_master_start1[0:0] end - attribute \src "issuer_ls180.v:177487.3-177488.45" - process $proc$issuer_ls180.v:177487$12513 + attribute \src "ls180.v:972.12-972.51" + process $proc$ls180.v:972$3135 assign { } { } - assign $0\core_core_reg1[4:0] \core_core_reg1$next - sync posedge \clk - update \core_core_reg1 $0\core_core_reg1[4:0] + assign $1\main_spi_master_control_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_spi_master_control_storage $1\main_spi_master_control_storage[15:0] end - attribute \src "issuer_ls180.v:177489.3-177490.51" - process $proc$issuer_ls180.v:177489$12514 + attribute \src "ls180.v:973.5-973.38" + process $proc$ls180.v:973$3136 assign { } { } - assign $0\core_core_reg1_ok[0:0] \core_core_reg1_ok$next - sync posedge \clk - update \core_core_reg1_ok $0\core_core_reg1_ok[0:0] + assign $1\main_spi_master_control_re[0:0] 1'0 + sync always + sync init + update \main_spi_master_control_re $1\main_spi_master_control_re[0:0] end - attribute \src "issuer_ls180.v:177491.3-177492.45" - process $proc$issuer_ls180.v:177491$12515 + attribute \src "ls180.v:977.11-977.46" + process $proc$ls180.v:977$3137 assign { } { } - assign $0\core_core_reg2[4:0] \core_core_reg2$next - sync posedge \clk - update \core_core_reg2 $0\core_core_reg2[4:0] + assign $1\main_spi_master_mosi_storage[7:0] 8'00000000 + sync always + sync init + update \main_spi_master_mosi_storage $1\main_spi_master_mosi_storage[7:0] end - attribute \src "issuer_ls180.v:177493.3-177494.51" - process $proc$issuer_ls180.v:177493$12516 + attribute \src "ls180.v:978.5-978.35" + process $proc$ls180.v:978$3138 assign { } { } - assign $0\core_core_reg2_ok[0:0] \core_core_reg2_ok$next - sync posedge \clk - update \core_core_reg2_ok $0\core_core_reg2_ok[0:0] + assign $1\main_spi_master_mosi_re[0:0] 1'0 + sync always + sync init + update \main_spi_master_mosi_re $1\main_spi_master_mosi_re[0:0] end - attribute \src "issuer_ls180.v:177495.3-177496.45" - process $proc$issuer_ls180.v:177495$12517 + attribute \src "ls180.v:982.5-982.38" + process $proc$ls180.v:982$3139 assign { } { } - assign $0\core_core_reg3[4:0] \core_core_reg3$next - sync posedge \clk - update \core_core_reg3 $0\core_core_reg3[4:0] + assign $1\main_spi_master_cs_storage[0:0] 1'1 + sync always + sync init + update \main_spi_master_cs_storage $1\main_spi_master_cs_storage[0:0] end - attribute \src "issuer_ls180.v:177497.3-177498.51" - process $proc$issuer_ls180.v:177497$12518 + attribute \src "ls180.v:983.5-983.33" + process $proc$ls180.v:983$3140 assign { } { } - assign $0\core_core_reg3_ok[0:0] \core_core_reg3_ok$next - sync posedge \clk - update \core_core_reg3_ok $0\core_core_reg3_ok[0:0] + assign $1\main_spi_master_cs_re[0:0] 1'0 + sync always + sync init + update \main_spi_master_cs_re $1\main_spi_master_cs_re[0:0] end - attribute \src "issuer_ls180.v:177499.3-177500.45" - process $proc$issuer_ls180.v:177499$12519 + attribute \src "ls180.v:984.5-984.44" + process $proc$ls180.v:984$3141 assign { } { } - assign $0\core_core_spro[9:0] \core_core_spro$next - sync posedge \clk - update \core_core_spro $0\core_core_spro[9:0] + assign $1\main_spi_master_loopback_storage[0:0] 1'0 + sync always + sync init + update \main_spi_master_loopback_storage $1\main_spi_master_loopback_storage[0:0] end - attribute \src "issuer_ls180.v:177501.3-177502.41" - process $proc$issuer_ls180.v:177501$12520 + attribute \src "ls180.v:985.5-985.39" + process $proc$ls180.v:985$3142 assign { } { } - assign $0\core_spro_ok[0:0] \core_spro_ok$next - sync posedge \clk - update \core_spro_ok $0\core_spro_ok[0:0] + assign $1\main_spi_master_loopback_re[0:0] 1'0 + sync always + sync init + update \main_spi_master_loopback_re $1\main_spi_master_loopback_re[0:0] end - attribute \src "issuer_ls180.v:177503.3-177504.39" - process $proc$issuer_ls180.v:177503$12521 + attribute \src "ls180.v:986.5-986.38" + process $proc$ls180.v:986$3143 assign { } { } - assign $0\d_xer_delay[0:0] \d_xer_delay$next - sync posedge \clk - update \d_xer_delay $0\d_xer_delay[0:0] + assign $1\main_spi_master_clk_enable[0:0] 1'0 + sync always + sync init + update \main_spi_master_clk_enable $1\main_spi_master_clk_enable[0:0] end - attribute \src "issuer_ls180.v:177505.3-177506.45" - process $proc$issuer_ls180.v:177505$12522 + attribute \src "ls180.v:987.5-987.37" + process $proc$ls180.v:987$3144 assign { } { } - assign $0\core_core_spr1[9:0] \core_core_spr1$next - sync posedge \clk - update \core_core_spr1 $0\core_core_spr1[9:0] + assign $1\main_spi_master_cs_enable[0:0] 1'0 + sync always + sync init + update \main_spi_master_cs_enable $1\main_spi_master_cs_enable[0:0] end - attribute \src "issuer_ls180.v:177507.3-177508.51" - process $proc$issuer_ls180.v:177507$12523 + attribute \src "ls180.v:988.11-988.39" + process $proc$ls180.v:988$3145 assign { } { } - assign $0\core_core_spr1_ok[0:0] \core_core_spr1_ok$next - sync posedge \clk - update \core_core_spr1_ok $0\core_core_spr1_ok[0:0] + assign $1\main_spi_master_count[2:0] 3'000 + sync always + sync init + update \main_spi_master_count $1\main_spi_master_count[2:0] end - attribute \src "issuer_ls180.v:177509.3-177510.49" - process $proc$issuer_ls180.v:177509$12524 + attribute \src "ls180.v:989.5-989.38" + process $proc$ls180.v:989$3146 assign { } { } - assign $0\core_core_xer_in[2:0] \core_core_xer_in$next - sync posedge \clk - update \core_core_xer_in $0\core_core_xer_in[2:0] + assign $1\main_spi_master_mosi_latch[0:0] 1'0 + sync always + sync init + update \main_spi_master_mosi_latch $1\main_spi_master_mosi_latch[0:0] end - attribute \src "issuer_ls180.v:177511.3-177512.41" - process $proc$issuer_ls180.v:177511$12525 + attribute \src "ls180.v:990.5-990.38" + process $proc$ls180.v:990$3147 assign { } { } - assign $0\core_xer_out[0:0] \core_xer_out$next - sync posedge \clk - update \core_xer_out $0\core_xer_out[0:0] + assign $1\main_spi_master_miso_latch[0:0] 1'0 + sync always + sync init + update \main_spi_master_miso_latch $1\main_spi_master_miso_latch[0:0] end - attribute \src "issuer_ls180.v:177513.3-177514.47" - process $proc$issuer_ls180.v:177513$12526 + attribute \src "ls180.v:991.12-991.48" + process $proc$ls180.v:991$3148 assign { } { } - assign $0\core_core_fast1[2:0] \core_core_fast1$next - sync posedge \clk - update \core_core_fast1 $0\core_core_fast1[2:0] + assign $1\main_spi_master_clk_divider1[15:0] 16'0000000000000000 + sync always + sync init + update \main_spi_master_clk_divider1 $1\main_spi_master_clk_divider1[15:0] end - attribute \src "issuer_ls180.v:177515.3-177516.53" - process $proc$issuer_ls180.v:177515$12527 + attribute \src "ls180.v:994.11-994.43" + process $proc$ls180.v:994$3149 assign { } { } - assign $0\core_core_fast1_ok[0:0] \core_core_fast1_ok$next - sync posedge \clk - update \core_core_fast1_ok $0\core_core_fast1_ok[0:0] + assign $1\main_spi_master_mosi_data[7:0] 8'00000000 + sync always + sync init + update \main_spi_master_mosi_data $1\main_spi_master_mosi_data[7:0] end - attribute \src "issuer_ls180.v:177517.3-177518.47" - process $proc$issuer_ls180.v:177517$12528 + attribute \src "ls180.v:995.11-995.42" + process $proc$ls180.v:995$3150 assign { } { } - assign $0\core_core_fast2[2:0] \core_core_fast2$next - sync posedge \clk - update \core_core_fast2 $0\core_core_fast2[2:0] + assign $1\main_spi_master_mosi_sel[2:0] 3'000 + sync always + sync init + update \main_spi_master_mosi_sel $1\main_spi_master_mosi_sel[2:0] end - attribute \src "issuer_ls180.v:177519.3-177520.53" - process $proc$issuer_ls180.v:177519$12529 + attribute \src "ls180.v:996.11-996.43" + process $proc$ls180.v:996$3151 assign { } { } - assign $0\core_core_fast2_ok[0:0] \core_core_fast2_ok$next - sync posedge \clk - update \core_core_fast2_ok $0\core_core_fast2_ok[0:0] + assign $1\main_spi_master_miso_data[7:0] 8'00000000 + sync always + sync init + update \main_spi_master_miso_data $1\main_spi_master_miso_data[7:0] end - attribute \src "issuer_ls180.v:177521.3-177522.49" - process $proc$issuer_ls180.v:177521$12530 + attribute \src "ls180.v:998.12-998.30" + process $proc$ls180.v:998$3152 assign { } { } - assign $0\core_core_fasto1[2:0] \core_core_fasto1$next - sync posedge \clk - update \core_core_fasto1 $0\core_core_fasto1[2:0] + assign $1\main_dummy[42:0] 43'0000000000000000000000000000000000000000000 + sync always + sync init + update \main_dummy $1\main_dummy[42:0] end - attribute \src "issuer_ls180.v:177523.3-177524.45" - process $proc$issuer_ls180.v:177523$12531 + attribute \src "ls180.v:9981.1-9991.4" + process $proc$ls180.v:9981$2684 assign { } { } - assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next - sync posedge \clk - update \core_fasto1_ok $0\core_fasto1_ok[0:0] - end - attribute \src "issuer_ls180.v:177525.3-177526.37" - process $proc$issuer_ls180.v:177525$12532 assign { } { } - assign $0\d_cr_delay[0:0] \d_cr_delay$next - sync posedge \clk - update \d_cr_delay $0\d_cr_delay[0:0] - end - attribute \src "issuer_ls180.v:177527.3-177528.49" - process $proc$issuer_ls180.v:177527$12533 assign { } { } - assign $0\core_core_fasto2[2:0] \core_core_fasto2$next - sync posedge \clk - update \core_core_fasto2 $0\core_core_fasto2[2:0] - end - attribute \src "issuer_ls180.v:177529.3-177530.45" - process $proc$issuer_ls180.v:177529$12534 assign { } { } - assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next - sync posedge \clk - update \core_fasto2_ok $0\core_fasto2_ok[0:0] - end - attribute \src "issuer_ls180.v:177531.3-177532.49" - process $proc$issuer_ls180.v:177531$12535 assign { } { } - assign $0\core_core_cr_in1[2:0] \core_core_cr_in1$next - sync posedge \clk - update \core_core_cr_in1 $0\core_core_cr_in1[2:0] - end - attribute \src "issuer_ls180.v:177533.3-177534.55" - process $proc$issuer_ls180.v:177533$12536 assign { } { } - assign $0\core_core_cr_in1_ok[0:0] \core_core_cr_in1_ok$next - sync posedge \clk - update \core_core_cr_in1_ok $0\core_core_cr_in1_ok[0:0] + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem$ls180.v:9989$4_ADDR[6:0]$2694 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:9989$4_DATA[31:0]$2695 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:9989$4_EN[31:0]$2696 0 + assign $0$memwr$\mem$ls180.v:9987$3_ADDR[6:0]$2691 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:9987$3_DATA[31:0]$2692 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:9987$3_EN[31:0]$2693 0 + assign $0$memwr$\mem$ls180.v:9985$2_ADDR[6:0]$2688 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:9985$2_DATA[31:0]$2689 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:9985$2_EN[31:0]$2690 0 + assign $0$memwr$\mem$ls180.v:9983$1_ADDR[6:0]$2685 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:9983$1_DATA[31:0]$2686 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:9983$1_EN[31:0]$2687 0 + assign $0\memadr[6:0] \main_libresocsim_adr + attribute \src "ls180.v:9982.2-9983.65" + switch \main_libresocsim_we [0] + attribute \src "ls180.v:9982.6-9982.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:9983$1_ADDR[6:0]$2685 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:9983$1_DATA[31:0]$2686 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] } + assign $0$memwr$\mem$ls180.v:9983$1_EN[31:0]$2687 255 + case + end + attribute \src "ls180.v:9984.2-9985.67" + switch \main_libresocsim_we [1] + attribute \src "ls180.v:9984.6-9984.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:9985$2_ADDR[6:0]$2688 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:9985$2_DATA[31:0]$2689 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem$ls180.v:9985$2_EN[31:0]$2690 65280 + case + end + attribute \src "ls180.v:9986.2-9987.69" + switch \main_libresocsim_we [2] + attribute \src "ls180.v:9986.6-9986.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:9987$3_ADDR[6:0]$2691 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:9987$3_DATA[31:0]$2692 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:9987$3_EN[31:0]$2693 16711680 + case + end + attribute \src "ls180.v:9988.2-9989.69" + switch \main_libresocsim_we [3] + attribute \src "ls180.v:9988.6-9988.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:9989$4_ADDR[6:0]$2694 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:9989$4_DATA[31:0]$2695 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:9989$4_EN[31:0]$2696 32'11111111000000000000000000000000 + case + end + sync posedge \sys_clk_1 + update \memadr $0\memadr[6:0] + update $memwr$\mem$ls180.v:9983$1_ADDR $0$memwr$\mem$ls180.v:9983$1_ADDR[6:0]$2685 + update $memwr$\mem$ls180.v:9983$1_DATA $0$memwr$\mem$ls180.v:9983$1_DATA[31:0]$2686 + update $memwr$\mem$ls180.v:9983$1_EN $0$memwr$\mem$ls180.v:9983$1_EN[31:0]$2687 + update $memwr$\mem$ls180.v:9985$2_ADDR $0$memwr$\mem$ls180.v:9985$2_ADDR[6:0]$2688 + update $memwr$\mem$ls180.v:9985$2_DATA $0$memwr$\mem$ls180.v:9985$2_DATA[31:0]$2689 + update $memwr$\mem$ls180.v:9985$2_EN $0$memwr$\mem$ls180.v:9985$2_EN[31:0]$2690 + update $memwr$\mem$ls180.v:9987$3_ADDR $0$memwr$\mem$ls180.v:9987$3_ADDR[6:0]$2691 + update $memwr$\mem$ls180.v:9987$3_DATA $0$memwr$\mem$ls180.v:9987$3_DATA[31:0]$2692 + update $memwr$\mem$ls180.v:9987$3_EN $0$memwr$\mem$ls180.v:9987$3_EN[31:0]$2693 + update $memwr$\mem$ls180.v:9989$4_ADDR $0$memwr$\mem$ls180.v:9989$4_ADDR[6:0]$2694 + update $memwr$\mem$ls180.v:9989$4_DATA $0$memwr$\mem$ls180.v:9989$4_DATA[31:0]$2695 + update $memwr$\mem$ls180.v:9989$4_EN $0$memwr$\mem$ls180.v:9989$4_EN[31:0]$2696 + end + connect \main_libresocsim_libresoc_reset \main_libresocsim_reset + connect \uart_tx \main_libresocsim_libresoc_constraintmanager1_uart0_tx + connect \main_libresocsim_libresoc_constraintmanager1_uart0_rx \uart_rx + connect \main_libresocsim_libresoc_constraintmanager1_gpio0_i \gpio_i + connect \gpio_o \main_libresocsim_libresoc_constraintmanager1_gpio0_o + connect \gpio_oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe + connect \main_libresocsim_libresoc_jtag_tck \jtag_tck + connect \main_libresocsim_libresoc_jtag_tms \jtag_tms + connect \main_libresocsim_libresoc_jtag_tdi \jtag_tdi + connect \jtag_tdo \main_libresocsim_libresoc_jtag_tdo + connect \main_nc \nc + connect \main_sdblock2mem_sink_sink_valid0 \main_sdcore_source_source_valid + connect \main_sdcore_source_source_ready \main_sdblock2mem_sink_sink_ready0 + connect \main_sdblock2mem_sink_sink_first \main_sdcore_source_source_first + connect \main_sdblock2mem_sink_sink_last \main_sdcore_source_source_last + connect \main_sdblock2mem_sink_sink_payload_data0 \main_sdcore_source_source_payload_data + connect \main_sdcore_sink_sink_valid \main_sdmem2block_source_source_valid0 + connect \main_sdmem2block_source_source_ready0 \main_sdcore_sink_sink_ready + connect \main_sdcore_sink_sink_first \main_sdmem2block_source_source_first0 + connect \main_sdcore_sink_sink_last \main_sdmem2block_source_source_last0 + connect \main_sdcore_sink_sink_payload_data \main_sdmem2block_source_source_payload_data0 + connect \main_libresocsim_bus_error \builder_error + connect \main_libresocsim_converter0_reset $not$ls180.v:2725$14_Y + connect \main_libresocsim_libresoc_ibus_dat_r { \main_libresocsim_interface0_converted_interface_dat_r \main_libresocsim_converter0_dat_r [63:32] } + connect \main_libresocsim_converter1_reset $not$ls180.v:2785$25_Y + connect \main_libresocsim_libresoc_dbus_dat_r { \main_libresocsim_interface1_converted_interface_dat_r \main_libresocsim_converter1_dat_r [63:32] } + connect \main_libresocsim_converter2_reset $not$ls180.v:2845$36_Y + connect \main_libresocsim_libresoc_jtag_wb_dat_r { \main_libresocsim_interface2_converted_interface_dat_r \main_libresocsim_converter2_dat_r [63:32] } + connect \main_libresocsim_reset \main_libresocsim_reset_re + connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors + connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [6:0] + connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r + connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w + connect \main_libresocsim_zero_trigger $ne$ls180.v:2917$60_Y + connect \main_libresocsim_eventmanager_status_w \main_libresocsim_zero_status + connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending + connect \main_libresocsim_irq $and$ls180.v:2926$63_Y + connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger + connect \sys_clk_1 \sys_clk + connect \por_clk \sys_clk + connect \sys_rst_1 \main_int_rst + connect \main_dfi_p0_address \main_sdram_master_p0_address + connect \main_dfi_p0_bank \main_sdram_master_p0_bank + connect \main_dfi_p0_cas_n \main_sdram_master_p0_cas_n + connect \main_dfi_p0_cs_n \main_sdram_master_p0_cs_n + connect \main_dfi_p0_ras_n \main_sdram_master_p0_ras_n + connect \main_dfi_p0_we_n \main_sdram_master_p0_we_n + connect \main_dfi_p0_cke \main_sdram_master_p0_cke + connect \main_dfi_p0_odt \main_sdram_master_p0_odt + connect \main_dfi_p0_reset_n \main_sdram_master_p0_reset_n + connect \main_dfi_p0_act_n \main_sdram_master_p0_act_n + connect \main_dfi_p0_wrdata \main_sdram_master_p0_wrdata + connect \main_dfi_p0_wrdata_en \main_sdram_master_p0_wrdata_en + connect \main_dfi_p0_wrdata_mask \main_sdram_master_p0_wrdata_mask + connect \main_dfi_p0_rddata_en \main_sdram_master_p0_rddata_en + connect \main_sdram_master_p0_rddata \main_dfi_p0_rddata + connect \main_sdram_master_p0_rddata_valid \main_dfi_p0_rddata_valid + connect \main_sdram_slave_p0_address \main_sdram_dfi_p0_address + connect \main_sdram_slave_p0_bank \main_sdram_dfi_p0_bank + connect \main_sdram_slave_p0_cas_n \main_sdram_dfi_p0_cas_n + connect \main_sdram_slave_p0_cs_n \main_sdram_dfi_p0_cs_n + connect \main_sdram_slave_p0_ras_n \main_sdram_dfi_p0_ras_n + connect \main_sdram_slave_p0_we_n \main_sdram_dfi_p0_we_n + connect \main_sdram_slave_p0_cke \main_sdram_dfi_p0_cke + connect \main_sdram_slave_p0_odt \main_sdram_dfi_p0_odt + connect \main_sdram_slave_p0_reset_n \main_sdram_dfi_p0_reset_n + connect \main_sdram_slave_p0_act_n \main_sdram_dfi_p0_act_n + connect \main_sdram_slave_p0_wrdata \main_sdram_dfi_p0_wrdata + connect \main_sdram_slave_p0_wrdata_en \main_sdram_dfi_p0_wrdata_en + connect \main_sdram_slave_p0_wrdata_mask \main_sdram_dfi_p0_wrdata_mask + connect \main_sdram_slave_p0_rddata_en \main_sdram_dfi_p0_rddata_en + connect \main_sdram_dfi_p0_rddata \main_sdram_slave_p0_rddata + connect \main_sdram_dfi_p0_rddata_valid \main_sdram_slave_p0_rddata_valid + connect \main_sdram_inti_p0_cke \main_sdram_cke + connect \main_sdram_inti_p0_odt \main_sdram_odt + connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n + connect \main_sdram_inti_p0_address \main_sdram_address_storage + connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage + connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3045$71_Y + connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3046$72_Y + connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage + connect \main_sdram_inti_p0_wrdata_mask 2'00 + connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid + connect \main_sdram_interface_bank0_ready \main_sdram_bankmachine0_req_ready + connect \main_sdram_bankmachine0_req_we \main_sdram_interface_bank0_we + connect \main_sdram_bankmachine0_req_addr \main_sdram_interface_bank0_addr + connect \main_sdram_interface_bank0_lock \main_sdram_bankmachine0_req_lock + connect \main_sdram_interface_bank0_wdata_ready \main_sdram_bankmachine0_req_wdata_ready + connect \main_sdram_interface_bank0_rdata_valid \main_sdram_bankmachine0_req_rdata_valid + connect \main_sdram_bankmachine1_req_valid \main_sdram_interface_bank1_valid + connect \main_sdram_interface_bank1_ready \main_sdram_bankmachine1_req_ready + connect \main_sdram_bankmachine1_req_we \main_sdram_interface_bank1_we + connect \main_sdram_bankmachine1_req_addr \main_sdram_interface_bank1_addr + connect \main_sdram_interface_bank1_lock \main_sdram_bankmachine1_req_lock + connect \main_sdram_interface_bank1_wdata_ready \main_sdram_bankmachine1_req_wdata_ready + connect \main_sdram_interface_bank1_rdata_valid \main_sdram_bankmachine1_req_rdata_valid + connect \main_sdram_bankmachine2_req_valid \main_sdram_interface_bank2_valid + connect \main_sdram_interface_bank2_ready \main_sdram_bankmachine2_req_ready + connect \main_sdram_bankmachine2_req_we \main_sdram_interface_bank2_we + connect \main_sdram_bankmachine2_req_addr \main_sdram_interface_bank2_addr + connect \main_sdram_interface_bank2_lock \main_sdram_bankmachine2_req_lock + connect \main_sdram_interface_bank2_wdata_ready \main_sdram_bankmachine2_req_wdata_ready + connect \main_sdram_interface_bank2_rdata_valid \main_sdram_bankmachine2_req_rdata_valid + connect \main_sdram_bankmachine3_req_valid \main_sdram_interface_bank3_valid + connect \main_sdram_interface_bank3_ready \main_sdram_bankmachine3_req_ready + connect \main_sdram_bankmachine3_req_we \main_sdram_interface_bank3_we + connect \main_sdram_bankmachine3_req_addr \main_sdram_interface_bank3_addr + connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock + connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready + connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid + connect \main_sdram_timer_wait $not$ls180.v:3077$73_Y + connect \main_sdram_postponer_req_i \main_sdram_timer_done0 + connect \main_sdram_wants_refresh \main_sdram_postponer_req_o + connect \main_sdram_timer_done1 $eq$ls180.v:3080$74_Y + connect \main_sdram_timer_done0 \main_sdram_timer_done1 + connect \main_sdram_timer_count0 \main_sdram_timer_count1 + connect \main_sdram_sequencer_start1 $or$ls180.v:3083$76_Y + connect \main_sdram_sequencer_done0 $and$ls180.v:3084$78_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid + connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine0_req_addr + connect \main_sdram_bankmachine0_cmd_buffer_sink_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine0_cmd_buffer_sink_ready + connect \main_sdram_bankmachine0_cmd_buffer_sink_first \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3126$80_Y + connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3127$81_Y + connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3128$82_Y + connect \main_sdram_bankmachine0_cmd_payload_ba 2'00 + connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3138$87_Y + connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3139$89_Y + connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3140$91_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3172$99_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3173$100_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3176$101_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3177$102_Y + connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3178$104_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid + connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine1_req_addr + connect \main_sdram_bankmachine1_cmd_buffer_sink_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine1_cmd_buffer_sink_ready + connect \main_sdram_bankmachine1_cmd_buffer_sink_first \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3283$110_Y + connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3284$111_Y + connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3285$112_Y + connect \main_sdram_bankmachine1_cmd_payload_ba 2'01 + connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3295$117_Y + connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3296$119_Y + connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3297$121_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3329$129_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3330$130_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3333$131_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3334$132_Y + connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3335$134_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid + connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine2_req_addr + connect \main_sdram_bankmachine2_cmd_buffer_sink_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine2_cmd_buffer_sink_ready + connect \main_sdram_bankmachine2_cmd_buffer_sink_first \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3440$140_Y + connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3441$141_Y + connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3442$142_Y + connect \main_sdram_bankmachine2_cmd_payload_ba 2'10 + connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3452$147_Y + connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3453$149_Y + connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3454$151_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3486$159_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3487$160_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3490$161_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3491$162_Y + connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3492$164_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid + connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine3_req_addr + connect \main_sdram_bankmachine3_cmd_buffer_sink_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine3_cmd_buffer_sink_ready + connect \main_sdram_bankmachine3_cmd_buffer_sink_first \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3597$170_Y + connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3598$171_Y + connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3599$172_Y + connect \main_sdram_bankmachine3_cmd_payload_ba 2'11 + connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3609$177_Y + connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3610$179_Y + connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3611$181_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3643$189_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3644$190_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3647$191_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3648$192_Y + connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3649$194_Y + connect \main_sdram_choose_req_want_cmds 1'1 + connect \main_sdram_trrdcon_valid $and$ls180.v:3745$205_Y + connect \main_sdram_tfawcon_valid $and$ls180.v:3746$211_Y + connect \main_sdram_ras_allowed $and$ls180.v:3747$212_Y + connect \main_sdram_tccdcon_valid $and$ls180.v:3748$215_Y + connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready + connect \main_sdram_twtrcon_valid $and$ls180.v:3750$217_Y + connect \main_sdram_read_available $or$ls180.v:3751$224_Y + connect \main_sdram_write_available $or$ls180.v:3752$231_Y + connect \main_sdram_max_time0 $eq$ls180.v:3753$232_Y + connect \main_sdram_max_time1 $eq$ls180.v:3754$233_Y + connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid + connect \main_sdram_go_to_refresh $and$ls180.v:3759$236_Y + connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata + connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata + connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3762$237_Y + connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids + connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0 + connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1 + connect \main_sdram_choose_cmd_cmd_payload_ba \builder_comb_rhs_array_muxed2 + connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3 + connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4 + connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5 + connect \main_sdram_choose_cmd_ce $or$ls180.v:3795$295_Y + connect \main_sdram_choose_req_request \main_sdram_choose_req_valids + connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6 + connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7 + connect \main_sdram_choose_req_cmd_payload_ba \builder_comb_rhs_array_muxed8 + connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9 + connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10 + connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11 + connect \main_sdram_choose_req_ce $or$ls180.v:3864$381_Y + connect \main_sdram_dfi_p0_reset_n 1'1 + connect \main_sdram_dfi_p0_cke \main_sdram_steerer0 + connect \main_sdram_dfi_p0_odt \main_sdram_steerer1 + connect \builder_roundrobin0_request $and$ls180.v:3941$413_Y + connect \builder_roundrobin0_ce $and$ls180.v:3942$416_Y + connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12 + connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13 + connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14 + connect \builder_roundrobin1_request $and$ls180.v:3946$429_Y + connect \builder_roundrobin1_ce $and$ls180.v:3947$432_Y + connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15 + connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16 + connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17 + connect \builder_roundrobin2_request $and$ls180.v:3951$445_Y + connect \builder_roundrobin2_ce $and$ls180.v:3952$448_Y + connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18 + connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19 + connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20 + connect \builder_roundrobin3_request $and$ls180.v:3956$461_Y + connect \builder_roundrobin3_ce $and$ls180.v:3957$464_Y + connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21 + connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22 + connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23 + connect \main_port_cmd_ready $or$ls180.v:3961$528_Y + connect \main_port_wdata_ready \builder_new_master_wdata_ready + connect \main_port_rdata_valid \builder_new_master_rdata_valid3 + connect \main_port_rdata_payload_data \main_sdram_interface_rdata + connect \builder_roundrobin0_grant 1'0 + connect \builder_roundrobin1_grant 1'0 + connect \builder_roundrobin2_grant 1'0 + connect \builder_roundrobin3_grant 1'0 + connect \main_converter_reset $not$ls180.v:3983$530_Y + connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] } + connect \main_port_cmd_payload_addr $sub$ls180.v:4043$541_Y [23:0] + connect \main_port_cmd_payload_we \main_litedram_wb_we + connect \main_port_wdata_payload_data \main_litedram_wb_dat_w + connect \main_port_wdata_payload_we \main_litedram_wb_sel + connect \main_litedram_wb_dat_r \main_port_rdata_payload_data + connect \main_port_flush $not$ls180.v:4048$542_Y + connect \main_port_cmd_last $not$ls180.v:4049$543_Y + connect \main_port_cmd_valid $and$ls180.v:4050$546_Y + connect \main_port_wdata_valid $and$ls180.v:4051$550_Y + connect \main_port_rdata_ready $and$ls180.v:4052$553_Y + connect \main_litedram_wb_ack $and$ls180.v:4053$558_Y + connect \main_ack_cmd $or$ls180.v:4054$560_Y + connect \main_ack_wdata $or$ls180.v:4055$562_Y + connect \main_ack_rdata $and$ls180.v:4056$563_Y + connect \main_uart_uart_sink_valid \main_source_valid + connect \main_source_ready \main_uart_uart_sink_ready + connect \main_uart_uart_sink_first \main_source_first + connect \main_uart_uart_sink_last \main_source_last + connect \main_uart_uart_sink_payload_data \main_source_payload_data + connect \main_sink_valid \main_uart_uart_source_valid + connect \main_uart_uart_source_ready \main_sink_ready + connect \main_sink_first \main_uart_uart_source_first + connect \main_sink_last \main_uart_uart_source_last + connect \main_sink_payload_data \main_uart_uart_source_payload_data + connect \main_uart_tx_fifo_sink_valid \main_uart_rxtx_re + connect \main_uart_tx_fifo_sink_payload_data \main_uart_rxtx_r + connect \main_uart_txfull_status $not$ls180.v:4069$564_Y + connect \main_uart_txempty_status $not$ls180.v:4070$565_Y + connect \main_uart_uart_source_valid \main_uart_tx_fifo_source_valid + connect \main_uart_tx_fifo_source_ready \main_uart_uart_source_ready + connect \main_uart_uart_source_first \main_uart_tx_fifo_source_first + connect \main_uart_uart_source_last \main_uart_tx_fifo_source_last + connect \main_uart_uart_source_payload_data \main_uart_tx_fifo_source_payload_data + connect \main_uart_tx_trigger $not$ls180.v:4076$566_Y + connect \main_uart_rx_fifo_sink_valid \main_uart_uart_sink_valid + connect \main_uart_uart_sink_ready \main_uart_rx_fifo_sink_ready + connect \main_uart_rx_fifo_sink_first \main_uart_uart_sink_first + connect \main_uart_rx_fifo_sink_last \main_uart_uart_sink_last + connect \main_uart_rx_fifo_sink_payload_data \main_uart_uart_sink_payload_data + connect \main_uart_rxempty_status $not$ls180.v:4082$567_Y + connect \main_uart_rxfull_status $not$ls180.v:4083$568_Y + connect \main_uart_rxtx_w \main_uart_rx_fifo_source_payload_data + connect \main_uart_rx_fifo_source_ready $or$ls180.v:4085$570_Y + connect \main_uart_rx_trigger $not$ls180.v:4086$571_Y + connect \main_uart_irq $or$ls180.v:4109$580_Y + connect \main_uart_tx_status \main_uart_tx_trigger + connect \main_uart_rx_status \main_uart_rx_trigger + connect \main_uart_tx_fifo_syncfifo_din { \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_fifo_in_payload_data } + connect { \main_uart_tx_fifo_fifo_out_last \main_uart_tx_fifo_fifo_out_first \main_uart_tx_fifo_fifo_out_payload_data } \main_uart_tx_fifo_syncfifo_dout + connect \main_uart_tx_fifo_sink_ready \main_uart_tx_fifo_syncfifo_writable + connect \main_uart_tx_fifo_syncfifo_we \main_uart_tx_fifo_sink_valid + connect \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_sink_first + connect \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_sink_last + connect \main_uart_tx_fifo_fifo_in_payload_data \main_uart_tx_fifo_sink_payload_data + connect \main_uart_tx_fifo_source_valid \main_uart_tx_fifo_readable + connect \main_uart_tx_fifo_source_first \main_uart_tx_fifo_fifo_out_first + connect \main_uart_tx_fifo_source_last \main_uart_tx_fifo_fifo_out_last + connect \main_uart_tx_fifo_source_payload_data \main_uart_tx_fifo_fifo_out_payload_data + connect \main_uart_tx_fifo_re \main_uart_tx_fifo_source_ready + connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4124$583_Y + connect \main_uart_tx_fifo_level1 $add$ls180.v:4125$584_Y + connect \main_uart_tx_fifo_wrport_dat_w \main_uart_tx_fifo_syncfifo_din + connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4135$588_Y + connect \main_uart_tx_fifo_do_read $and$ls180.v:4136$589_Y + connect \main_uart_tx_fifo_rdport_adr \main_uart_tx_fifo_consume + connect \main_uart_tx_fifo_syncfifo_dout \main_uart_tx_fifo_rdport_dat_r + connect \main_uart_tx_fifo_rdport_re \main_uart_tx_fifo_do_read + connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4140$590_Y + connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4141$591_Y + connect \main_uart_rx_fifo_syncfifo_din { \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_fifo_in_payload_data } + connect { \main_uart_rx_fifo_fifo_out_last \main_uart_rx_fifo_fifo_out_first \main_uart_rx_fifo_fifo_out_payload_data } \main_uart_rx_fifo_syncfifo_dout + connect \main_uart_rx_fifo_sink_ready \main_uart_rx_fifo_syncfifo_writable + connect \main_uart_rx_fifo_syncfifo_we \main_uart_rx_fifo_sink_valid + connect \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_sink_first + connect \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_sink_last + connect \main_uart_rx_fifo_fifo_in_payload_data \main_uart_rx_fifo_sink_payload_data + connect \main_uart_rx_fifo_source_valid \main_uart_rx_fifo_readable + connect \main_uart_rx_fifo_source_first \main_uart_rx_fifo_fifo_out_first + connect \main_uart_rx_fifo_source_last \main_uart_rx_fifo_fifo_out_last + connect \main_uart_rx_fifo_source_payload_data \main_uart_rx_fifo_fifo_out_payload_data + connect \main_uart_rx_fifo_re \main_uart_rx_fifo_source_ready + connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4154$594_Y + connect \main_uart_rx_fifo_level1 $add$ls180.v:4155$595_Y + connect \main_uart_rx_fifo_wrport_dat_w \main_uart_rx_fifo_syncfifo_din + connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4165$599_Y + connect \main_uart_rx_fifo_do_read $and$ls180.v:4166$600_Y + connect \main_uart_rx_fifo_rdport_adr \main_uart_rx_fifo_consume + connect \main_uart_rx_fifo_syncfifo_dout \main_uart_rx_fifo_rdport_dat_r + connect \main_uart_rx_fifo_rdport_re \main_uart_rx_fifo_do_read + connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4170$601_Y + connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4171$602_Y + connect \main_gpio_pads_i \main_libresocsim_libresoc_constraintmanager0_gpio0_i + connect \main_libresocsim_libresoc_constraintmanager0_gpio0_o \main_gpio_pads_o + connect \main_libresocsim_libresoc_constraintmanager0_gpio0_oe \main_gpio_pads_oe + connect \main_gpio_pads_oe \main_gpio_oe_storage + connect \main_gpio_pads_o \main_gpio_out_storage + connect \main_spi_master_start0 \main_spi_master_start1 + connect \main_spi_master_length0 \main_spi_master_length1 + connect \main_spi_master_mosi \main_spi_master_mosi_storage + connect \main_spi_master_done1 \main_spi_master_done0 + connect \main_spi_master_miso_status \main_spi_master_miso + connect \main_spi_master_cs \main_spi_master_cs_storage + connect \main_spi_master_loopback \main_spi_master_loopback_storage + connect \main_spi_master_clk_rise $eq$ls180.v:4184$604_Y + connect \main_spi_master_clk_fall $eq$ls180.v:4185$606_Y + connect \main_sdphy_status 1'0 + connect \main_sdphy_sdpads_clk $or$ls180.v:4236$614_Y + connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4237$618_Y + connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4238$622_Y + connect \main_sdphy_sdpads_data_oe $or$ls180.v:4239$626_Y + connect \main_sdphy_sdpads_data_o $or$ls180.v:4240$630_Y + connect \main_sdphy_init_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_cmdw_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_cmdr_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_dataw_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_datar_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_init_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_init_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_init_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_cmdw_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_cmdw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_cmdw_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_cmdr_pads_in_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_cmdr_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_dataw_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_dataw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_dataw_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_datar_pads_in_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_datar_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_datar_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_clocker_stop $or$ls180.v:4261$631_Y + connect \main_sdphy_clocker_ce $and$ls180.v:4291$634_Y + connect \main_sdphy_cmdr_cmdr_pads_in_valid \main_sdphy_cmdr_pads_in_pads_in_valid + connect \main_sdphy_cmdr_pads_in_pads_in_ready \main_sdphy_cmdr_cmdr_pads_in_ready + connect \main_sdphy_cmdr_cmdr_pads_in_first \main_sdphy_cmdr_pads_in_pads_in_first + connect \main_sdphy_cmdr_cmdr_pads_in_last \main_sdphy_cmdr_pads_in_pads_in_last + connect \main_sdphy_cmdr_cmdr_pads_in_payload_clk \main_sdphy_cmdr_pads_in_pads_in_payload_clk + connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i + connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o + connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe + connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_i \main_sdphy_cmdr_pads_in_pads_in_payload_data_i + connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_o \main_sdphy_cmdr_pads_in_pads_in_payload_data_o + connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe + connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4414$644_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4415$646_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_payload_data \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i + connect \main_sdphy_cmdr_cmdr_buf_sink_valid \main_sdphy_cmdr_cmdr_source_source_valid1 + connect \main_sdphy_cmdr_cmdr_source_source_ready1 \main_sdphy_cmdr_cmdr_buf_sink_ready + connect \main_sdphy_cmdr_cmdr_buf_sink_first \main_sdphy_cmdr_cmdr_source_source_first1 + connect \main_sdphy_cmdr_cmdr_buf_sink_last \main_sdphy_cmdr_cmdr_source_source_last1 + connect \main_sdphy_cmdr_cmdr_buf_sink_payload_data \main_sdphy_cmdr_cmdr_source_source_payload_data1 + connect \main_sdphy_cmdr_cmdr_source_source_valid0 \main_sdphy_cmdr_cmdr_buf_source_valid + connect \main_sdphy_cmdr_cmdr_buf_source_ready \main_sdphy_cmdr_cmdr_source_source_ready0 + connect \main_sdphy_cmdr_cmdr_source_source_first0 \main_sdphy_cmdr_cmdr_buf_source_first + connect \main_sdphy_cmdr_cmdr_source_source_last0 \main_sdphy_cmdr_cmdr_buf_source_last + connect \main_sdphy_cmdr_cmdr_source_source_payload_data0 \main_sdphy_cmdr_cmdr_buf_source_payload_data + connect \main_sdphy_cmdr_cmdr_source_source_valid1 \main_sdphy_cmdr_cmdr_converter_source_valid + connect \main_sdphy_cmdr_cmdr_converter_source_ready \main_sdphy_cmdr_cmdr_source_source_ready1 + connect \main_sdphy_cmdr_cmdr_source_source_first1 \main_sdphy_cmdr_cmdr_converter_source_first + connect \main_sdphy_cmdr_cmdr_source_source_last1 \main_sdphy_cmdr_cmdr_converter_source_last + connect \main_sdphy_cmdr_cmdr_source_source_payload_data1 \main_sdphy_cmdr_cmdr_converter_source_payload_data + connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4432$648_Y + connect \main_sdphy_cmdr_cmdr_converter_source_valid \main_sdphy_cmdr_cmdr_converter_strobe_all + connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4434$649_Y + connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4435$651_Y + connect \main_sdphy_dataw_crcr_pads_in_valid \main_sdphy_dataw_pads_in_pads_in_valid + connect \main_sdphy_dataw_pads_in_pads_in_ready \main_sdphy_dataw_crcr_pads_in_ready + connect \main_sdphy_dataw_crcr_pads_in_first \main_sdphy_dataw_pads_in_pads_in_first + connect \main_sdphy_dataw_crcr_pads_in_last \main_sdphy_dataw_pads_in_pads_in_last + connect \main_sdphy_dataw_crcr_pads_in_payload_clk \main_sdphy_dataw_pads_in_pads_in_payload_clk + connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_i \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i + connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_o \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o + connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe + connect \main_sdphy_dataw_crcr_pads_in_payload_data_i \main_sdphy_dataw_pads_in_pads_in_payload_data_i + connect \main_sdphy_dataw_crcr_pads_in_payload_data_o \main_sdphy_dataw_pads_in_pads_in_payload_data_o + connect \main_sdphy_dataw_crcr_pads_in_payload_data_oe \main_sdphy_dataw_pads_in_pads_in_payload_data_oe + connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4541$666_Y + connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4542$667_Y + connect \main_sdphy_dataw_crcr_converter_sink_payload_data \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] + connect \main_sdphy_dataw_crcr_buf_sink_valid \main_sdphy_dataw_crcr_source_source_valid1 + connect \main_sdphy_dataw_crcr_source_source_ready1 \main_sdphy_dataw_crcr_buf_sink_ready + connect \main_sdphy_dataw_crcr_buf_sink_first \main_sdphy_dataw_crcr_source_source_first1 + connect \main_sdphy_dataw_crcr_buf_sink_last \main_sdphy_dataw_crcr_source_source_last1 + connect \main_sdphy_dataw_crcr_buf_sink_payload_data \main_sdphy_dataw_crcr_source_source_payload_data1 + connect \main_sdphy_dataw_crcr_source_source_valid0 \main_sdphy_dataw_crcr_buf_source_valid + connect \main_sdphy_dataw_crcr_buf_source_ready \main_sdphy_dataw_crcr_source_source_ready0 + connect \main_sdphy_dataw_crcr_source_source_first0 \main_sdphy_dataw_crcr_buf_source_first + connect \main_sdphy_dataw_crcr_source_source_last0 \main_sdphy_dataw_crcr_buf_source_last + connect \main_sdphy_dataw_crcr_source_source_payload_data0 \main_sdphy_dataw_crcr_buf_source_payload_data + connect \main_sdphy_dataw_crcr_source_source_valid1 \main_sdphy_dataw_crcr_converter_source_valid + connect \main_sdphy_dataw_crcr_converter_source_ready \main_sdphy_dataw_crcr_source_source_ready1 + connect \main_sdphy_dataw_crcr_source_source_first1 \main_sdphy_dataw_crcr_converter_source_first + connect \main_sdphy_dataw_crcr_source_source_last1 \main_sdphy_dataw_crcr_converter_source_last + connect \main_sdphy_dataw_crcr_source_source_payload_data1 \main_sdphy_dataw_crcr_converter_source_payload_data + connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4559$669_Y + connect \main_sdphy_dataw_crcr_converter_source_valid \main_sdphy_dataw_crcr_converter_strobe_all + connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4561$670_Y + connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4562$672_Y + connect \main_sdphy_datar_datar_pads_in_valid \main_sdphy_datar_pads_in_pads_in_valid + connect \main_sdphy_datar_pads_in_pads_in_ready \main_sdphy_datar_datar_pads_in_ready + connect \main_sdphy_datar_datar_pads_in_first \main_sdphy_datar_pads_in_pads_in_first + connect \main_sdphy_datar_datar_pads_in_last \main_sdphy_datar_pads_in_pads_in_last + connect \main_sdphy_datar_datar_pads_in_payload_clk \main_sdphy_datar_pads_in_pads_in_payload_clk + connect \main_sdphy_datar_datar_pads_in_payload_cmd_i \main_sdphy_datar_pads_in_pads_in_payload_cmd_i + connect \main_sdphy_datar_datar_pads_in_payload_cmd_o \main_sdphy_datar_pads_in_pads_in_payload_cmd_o + connect \main_sdphy_datar_datar_pads_in_payload_cmd_oe \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe + connect \main_sdphy_datar_datar_pads_in_payload_data_i \main_sdphy_datar_pads_in_pads_in_payload_data_i + connect \main_sdphy_datar_datar_pads_in_payload_data_o \main_sdphy_datar_pads_in_pads_in_payload_data_o + connect \main_sdphy_datar_datar_pads_in_payload_data_oe \main_sdphy_datar_pads_in_pads_in_payload_data_oe + connect \main_sdphy_datar_datar_start $eq$ls180.v:4675$681_Y + connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4676$682_Y + connect \main_sdphy_datar_datar_converter_sink_payload_data \main_sdphy_datar_datar_pads_in_payload_data_i + connect \main_sdphy_datar_datar_buf_sink_valid \main_sdphy_datar_datar_source_source_valid1 + connect \main_sdphy_datar_datar_source_source_ready1 \main_sdphy_datar_datar_buf_sink_ready + connect \main_sdphy_datar_datar_buf_sink_first \main_sdphy_datar_datar_source_source_first1 + connect \main_sdphy_datar_datar_buf_sink_last \main_sdphy_datar_datar_source_source_last1 + connect \main_sdphy_datar_datar_buf_sink_payload_data \main_sdphy_datar_datar_source_source_payload_data1 + connect \main_sdphy_datar_datar_source_source_valid0 \main_sdphy_datar_datar_buf_source_valid + connect \main_sdphy_datar_datar_buf_source_ready \main_sdphy_datar_datar_source_source_ready0 + connect \main_sdphy_datar_datar_source_source_first0 \main_sdphy_datar_datar_buf_source_first + connect \main_sdphy_datar_datar_source_source_last0 \main_sdphy_datar_datar_buf_source_last + connect \main_sdphy_datar_datar_source_source_payload_data0 \main_sdphy_datar_datar_buf_source_payload_data + connect \main_sdphy_datar_datar_source_source_valid1 \main_sdphy_datar_datar_converter_source_valid + connect \main_sdphy_datar_datar_converter_source_ready \main_sdphy_datar_datar_source_source_ready1 + connect \main_sdphy_datar_datar_source_source_first1 \main_sdphy_datar_datar_converter_source_first + connect \main_sdphy_datar_datar_source_source_last1 \main_sdphy_datar_datar_converter_source_last + connect \main_sdphy_datar_datar_source_source_payload_data1 \main_sdphy_datar_datar_converter_source_payload_data + connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4693$684_Y + connect \main_sdphy_datar_datar_converter_source_valid \main_sdphy_datar_datar_converter_strobe_all + connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4695$685_Y + connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4696$687_Y + connect \main_sdcore_crc16_inserter_sink_valid \main_sdcore_sink_sink_valid + connect \main_sdcore_sink_sink_ready \main_sdcore_crc16_inserter_sink_ready + connect \main_sdcore_crc16_inserter_sink_first \main_sdcore_sink_sink_first + connect \main_sdcore_crc16_inserter_sink_last \main_sdcore_sink_sink_last + connect \main_sdcore_crc16_inserter_sink_payload_data \main_sdcore_sink_sink_payload_data + connect \main_sdcore_source_source_valid \main_sdcore_crc16_checker_source_valid + connect \main_sdcore_crc16_checker_source_ready \main_sdcore_source_source_ready + connect \main_sdcore_source_source_first \main_sdcore_crc16_checker_source_first + connect \main_sdcore_source_source_last \main_sdcore_crc16_checker_source_last + connect \main_sdcore_source_source_payload_data \main_sdcore_crc16_checker_source_payload_data + connect \main_sdcore_cmd_type \main_sdcore_cmd_command_storage [1:0] + connect \main_sdcore_data_type \main_sdcore_cmd_command_storage [6:5] + connect \main_sdcore_cmd_event_status { 1'0 \main_sdcore_cmd_timeout \main_sdcore_cmd_error \main_sdcore_cmd_done } + connect \main_sdcore_data_event_status { $not$ls180.v:4812$702_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } + connect \main_sdcore_crc7_inserter_val { 2'01 \main_sdcore_cmd_command_storage [13:8] \main_sdcore_cmd_argument_storage } + connect \main_sdcore_crc7_inserter_clr 1'1 + connect \main_sdcore_crc7_inserter_enable 1'1 + connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:4816$705_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:4816$703_Y } + connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:4817$708_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:4817$706_Y } + connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:4818$711_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:4818$709_Y } + connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:4819$714_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:4819$712_Y } + connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:4820$717_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:4820$715_Y } + connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:4821$720_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:4821$718_Y } + connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:4822$723_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:4822$721_Y } + connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:4823$726_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:4823$724_Y } + connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:4824$729_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:4824$727_Y } + connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:4825$732_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:4825$730_Y } + connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:4826$735_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:4826$733_Y } + connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:4827$738_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:4827$736_Y } + connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:4828$741_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:4828$739_Y } + connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:4829$744_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:4829$742_Y } + connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:4830$747_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:4830$745_Y } + connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:4831$750_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:4831$748_Y } + connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:4832$753_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:4832$751_Y } + connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:4833$756_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:4833$754_Y } + connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:4834$759_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:4834$757_Y } + connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:4835$762_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:4835$760_Y } + connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:4836$765_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:4836$763_Y } + connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:4837$768_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:4837$766_Y } + connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:4838$771_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:4838$769_Y } + connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:4839$774_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:4839$772_Y } + connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:4840$777_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:4840$775_Y } + connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:4841$780_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:4841$778_Y } + connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:4842$783_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:4842$781_Y } + connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:4843$786_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:4843$784_Y } + connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:4844$789_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:4844$787_Y } + connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:4845$792_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:4845$790_Y } + connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:4846$795_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:4846$793_Y } + connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:4847$798_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:4847$796_Y } + connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:4848$801_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:4848$799_Y } + connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:4849$804_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:4849$802_Y } + connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:4850$807_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:4850$805_Y } + connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:4851$810_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:4851$808_Y } + connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:4852$813_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:4852$811_Y } + connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:4853$816_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:4853$814_Y } + connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:4854$819_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:4854$817_Y } + connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:4855$822_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:4855$820_Y } + connect \main_sdcore_crc16_inserter_crc0_val { \main_sdcore_crc16_inserter_sink_payload_data [4] \main_sdcore_crc16_inserter_sink_payload_data [0] } + connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:4865$825_Y + connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:4866$826_Y + connect \main_sdcore_crc16_inserter_crc1_val { \main_sdcore_crc16_inserter_sink_payload_data [5] \main_sdcore_crc16_inserter_sink_payload_data [1] } + connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:4868$828_Y + connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:4869$829_Y + connect \main_sdcore_crc16_inserter_crc2_val { \main_sdcore_crc16_inserter_sink_payload_data [6] \main_sdcore_crc16_inserter_sink_payload_data [2] } + connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:4871$831_Y + connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:4872$832_Y + connect \main_sdcore_crc16_inserter_crc3_val { \main_sdcore_crc16_inserter_sink_payload_data [7] \main_sdcore_crc16_inserter_sink_payload_data [3] } + connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:4874$834_Y + connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:4875$835_Y + connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:4876$840_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:4876$838_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:4876$836_Y } + connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:4877$845_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:4877$843_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:4877$841_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:4886$851_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:4886$849_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:4886$847_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:4887$856_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:4887$854_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:4887$852_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:4896$862_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:4896$860_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:4896$858_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:4897$867_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:4897$865_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:4897$863_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:4906$873_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:4906$871_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:4906$869_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:4907$878_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:4907$876_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:4907$874_Y } + connect \main_sdcore_crc16_checker_crc0_val { \main_sdcore_crc16_checker_val [7] \main_sdcore_crc16_checker_val [3] } + connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5003$894_Y + connect \main_sdcore_crc16_checker_crc1_val { \main_sdcore_crc16_checker_val [6] \main_sdcore_crc16_checker_val [2] } + connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5013$897_Y + connect \main_sdcore_crc16_checker_crc2_val { \main_sdcore_crc16_checker_val [5] \main_sdcore_crc16_checker_val [1] } + connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5023$900_Y + connect \main_sdcore_crc16_checker_crc3_val { \main_sdcore_crc16_checker_val [4] \main_sdcore_crc16_checker_val [0] } + connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5033$903_Y + connect \main_sdcore_crc16_checker_source_payload_data \main_sdcore_crc16_checker_val + connect \main_sdcore_crc16_checker_source_last \main_sdcore_crc16_checker_sink_last + connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5058$915_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5058$913_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5058$911_Y } + connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5059$920_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5059$918_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5059$916_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5068$926_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5068$924_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5068$922_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5069$931_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5069$929_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5069$927_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5078$937_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5078$935_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5078$933_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5079$942_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5079$940_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5079$938_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5088$948_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5088$946_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5088$944_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5089$953_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5089$951_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5089$949_Y } + connect \main_sdblock2mem_fifo_sink_valid \main_sdblock2mem_sink_sink_valid0 + connect \main_sdblock2mem_sink_sink_ready0 \main_sdblock2mem_fifo_sink_ready + connect \main_sdblock2mem_fifo_sink_first \main_sdblock2mem_sink_sink_first + connect \main_sdblock2mem_fifo_sink_last \main_sdblock2mem_sink_sink_last + connect \main_sdblock2mem_fifo_sink_payload_data \main_sdblock2mem_sink_sink_payload_data0 + connect \main_sdblock2mem_converter_sink_valid \main_sdblock2mem_fifo_source_valid + connect \main_sdblock2mem_fifo_source_ready \main_sdblock2mem_converter_sink_ready + connect \main_sdblock2mem_converter_sink_first \main_sdblock2mem_fifo_source_first + connect \main_sdblock2mem_converter_sink_last \main_sdblock2mem_fifo_source_last + connect \main_sdblock2mem_converter_sink_payload_data \main_sdblock2mem_fifo_source_payload_data + connect \main_sdblock2mem_wishbonedmawriter_sink_valid \main_sdblock2mem_source_source_valid + connect \main_sdblock2mem_source_source_ready \main_sdblock2mem_wishbonedmawriter_sink_ready + connect \main_sdblock2mem_wishbonedmawriter_sink_first \main_sdblock2mem_source_source_first + connect \main_sdblock2mem_wishbonedmawriter_sink_last \main_sdblock2mem_source_source_last + connect \main_sdblock2mem_wishbonedmawriter_sink_payload_data \main_sdblock2mem_source_source_payload_data + connect \main_sdblock2mem_fifo_syncfifo_din { \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_fifo_in_payload_data } + connect { \main_sdblock2mem_fifo_fifo_out_last \main_sdblock2mem_fifo_fifo_out_first \main_sdblock2mem_fifo_fifo_out_payload_data } \main_sdblock2mem_fifo_syncfifo_dout + connect \main_sdblock2mem_fifo_sink_ready \main_sdblock2mem_fifo_syncfifo_writable + connect \main_sdblock2mem_fifo_syncfifo_we \main_sdblock2mem_fifo_sink_valid + connect \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_sink_first + connect \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_sink_last + connect \main_sdblock2mem_fifo_fifo_in_payload_data \main_sdblock2mem_fifo_sink_payload_data + connect \main_sdblock2mem_fifo_source_valid \main_sdblock2mem_fifo_syncfifo_readable + connect \main_sdblock2mem_fifo_source_first \main_sdblock2mem_fifo_fifo_out_first + connect \main_sdblock2mem_fifo_source_last \main_sdblock2mem_fifo_fifo_out_last + connect \main_sdblock2mem_fifo_source_payload_data \main_sdblock2mem_fifo_fifo_out_payload_data + connect \main_sdblock2mem_fifo_syncfifo_re \main_sdblock2mem_fifo_source_ready + connect \main_sdblock2mem_fifo_wrport_dat_w \main_sdblock2mem_fifo_syncfifo_din + connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5325$983_Y + connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5326$984_Y + connect \main_sdblock2mem_fifo_rdport_adr \main_sdblock2mem_fifo_consume + connect \main_sdblock2mem_fifo_syncfifo_dout \main_sdblock2mem_fifo_rdport_dat_r + connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5329$985_Y + connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5330$986_Y + connect \main_sdblock2mem_source_source_valid \main_sdblock2mem_converter_source_valid + connect \main_sdblock2mem_converter_source_ready \main_sdblock2mem_source_source_ready + connect \main_sdblock2mem_source_source_first \main_sdblock2mem_converter_source_first + connect \main_sdblock2mem_source_source_last \main_sdblock2mem_converter_source_last + connect \main_sdblock2mem_source_source_payload_data \main_sdblock2mem_converter_source_payload_data + connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5336$988_Y + connect \main_sdblock2mem_converter_source_valid \main_sdblock2mem_converter_strobe_all + connect \main_sdblock2mem_converter_load_part $and$ls180.v:5338$989_Y + connect \main_interface0_bus_stb \main_sdblock2mem_sink_sink_valid1 + connect \main_interface0_bus_cyc \main_sdblock2mem_sink_sink_valid1 + connect \main_interface0_bus_we 1'1 + connect \main_interface0_bus_sel 4'1111 + connect \main_interface0_bus_adr \main_sdblock2mem_sink_sink_payload_address + connect \main_interface0_bus_dat_w { \main_sdblock2mem_sink_sink_payload_data1 [7:0] \main_sdblock2mem_sink_sink_payload_data1 [15:8] \main_sdblock2mem_sink_sink_payload_data1 [23:16] \main_sdblock2mem_sink_sink_payload_data1 [31:24] } + connect \main_sdblock2mem_sink_sink_ready1 \main_interface0_bus_ack + connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [33:2] + connect \main_sdblock2mem_wishbonedmawriter_length { 2'00 \main_sdblock2mem_wishbonedmawriter_length_storage [31:2] } + connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5348$990_Y + connect \main_sdmem2block_converter_sink_valid \main_sdmem2block_dma_source_valid + connect \main_sdmem2block_dma_source_ready \main_sdmem2block_converter_sink_ready + connect \main_sdmem2block_converter_sink_first \main_sdmem2block_dma_source_first + connect \main_sdmem2block_converter_sink_last \main_sdmem2block_dma_source_last + connect \main_sdmem2block_converter_sink_payload_data \main_sdmem2block_dma_source_payload_data + connect \main_sdmem2block_fifo_sink_valid \main_sdmem2block_source_source_valid1 + connect \main_sdmem2block_source_source_ready1 \main_sdmem2block_fifo_sink_ready + connect \main_sdmem2block_fifo_sink_first \main_sdmem2block_source_source_first1 + connect \main_sdmem2block_fifo_sink_last \main_sdmem2block_source_source_last1 + connect \main_sdmem2block_fifo_sink_payload_data \main_sdmem2block_source_source_payload_data1 + connect \main_sdmem2block_source_source_valid0 \main_sdmem2block_fifo_source_valid + connect \main_sdmem2block_fifo_source_ready \main_sdmem2block_source_source_ready0 + connect \main_sdmem2block_source_source_first0 \main_sdmem2block_fifo_source_first + connect \main_sdmem2block_source_source_last0 \main_sdmem2block_fifo_source_last + connect \main_sdmem2block_source_source_payload_data0 \main_sdmem2block_fifo_source_payload_data + connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [33:2] + connect \main_sdmem2block_dma_length { 2'00 \main_sdmem2block_dma_length_storage [31:2] } + connect \main_sdmem2block_dma_offset_status \main_sdmem2block_dma_offset + connect \main_sdmem2block_dma_reset $not$ls180.v:5407$997_Y + connect \main_sdmem2block_source_source_valid1 \main_sdmem2block_converter_source_valid + connect \main_sdmem2block_converter_source_ready \main_sdmem2block_source_source_ready1 + connect \main_sdmem2block_source_source_first1 \main_sdmem2block_converter_source_first + connect \main_sdmem2block_source_source_last1 \main_sdmem2block_converter_source_last + connect \main_sdmem2block_source_source_payload_data1 \main_sdmem2block_converter_source_payload_data + connect \main_sdmem2block_converter_first $eq$ls180.v:5488$1005_Y + connect \main_sdmem2block_converter_last $eq$ls180.v:5489$1006_Y + connect \main_sdmem2block_converter_source_valid \main_sdmem2block_converter_sink_valid + connect \main_sdmem2block_converter_source_first $and$ls180.v:5491$1007_Y + connect \main_sdmem2block_converter_source_last $and$ls180.v:5492$1008_Y + connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5493$1009_Y + connect \main_sdmem2block_converter_source_payload_valid_token_count \main_sdmem2block_converter_last + connect \main_sdmem2block_fifo_syncfifo_din { \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_fifo_in_payload_data } + connect { \main_sdmem2block_fifo_fifo_out_last \main_sdmem2block_fifo_fifo_out_first \main_sdmem2block_fifo_fifo_out_payload_data } \main_sdmem2block_fifo_syncfifo_dout + connect \main_sdmem2block_fifo_sink_ready \main_sdmem2block_fifo_syncfifo_writable + connect \main_sdmem2block_fifo_syncfifo_we \main_sdmem2block_fifo_sink_valid + connect \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_sink_first + connect \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_sink_last + connect \main_sdmem2block_fifo_fifo_in_payload_data \main_sdmem2block_fifo_sink_payload_data + connect \main_sdmem2block_fifo_source_valid \main_sdmem2block_fifo_syncfifo_readable + connect \main_sdmem2block_fifo_source_first \main_sdmem2block_fifo_fifo_out_first + connect \main_sdmem2block_fifo_source_last \main_sdmem2block_fifo_fifo_out_last + connect \main_sdmem2block_fifo_source_payload_data \main_sdmem2block_fifo_fifo_out_payload_data + connect \main_sdmem2block_fifo_syncfifo_re \main_sdmem2block_fifo_source_ready + connect \main_sdmem2block_fifo_wrport_dat_w \main_sdmem2block_fifo_syncfifo_din + connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5533$1014_Y + connect \main_sdmem2block_fifo_do_read $and$ls180.v:5534$1015_Y + connect \main_sdmem2block_fifo_rdport_adr \main_sdmem2block_fifo_consume + connect \main_sdmem2block_fifo_syncfifo_dout \main_sdmem2block_fifo_rdport_dat_r + connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5537$1016_Y + connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5538$1017_Y + connect \libresocsim_start0 \libresocsim_start1 + connect \libresocsim_length0 \libresocsim_length1 + connect \libresocsim_mosi \libresocsim_mosi_storage + connect \libresocsim_done1 \libresocsim_done0 + connect \libresocsim_miso_status \libresocsim_miso + connect \libresocsim_cs \libresocsim_cs_storage + connect \libresocsim_loopback \libresocsim_loopback_storage + connect \libresocsim_clk_rise $eq$ls180.v:5546$1019_Y + connect \libresocsim_clk_fall $eq$ls180.v:5547$1021_Y + connect \libresocsim_clk_divider0 \libresocsim_storage + connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0] + connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 + connect \builder_shared_sel \builder_comb_rhs_array_muxed26 + connect \builder_shared_cyc \builder_comb_rhs_array_muxed27 + connect \builder_shared_stb \builder_comb_rhs_array_muxed28 + connect \builder_shared_we \builder_comb_rhs_array_muxed29 + connect \builder_shared_cti \builder_comb_rhs_array_muxed30 + connect \builder_shared_bte \builder_comb_rhs_array_muxed31 + connect \main_libresocsim_interface0_converted_interface_dat_r \builder_shared_dat_r + connect \main_libresocsim_interface1_converted_interface_dat_r \builder_shared_dat_r + connect \main_libresocsim_interface2_converted_interface_dat_r \builder_shared_dat_r + connect \main_interface0_bus_dat_r \builder_shared_dat_r + connect \main_interface1_bus_dat_r \builder_shared_dat_r + connect \main_libresocsim_interface0_converted_interface_ack $and$ls180.v:5648$1031_Y + connect \main_libresocsim_interface1_converted_interface_ack $and$ls180.v:5649$1033_Y + connect \main_libresocsim_interface2_converted_interface_ack $and$ls180.v:5650$1035_Y + connect \main_interface0_bus_ack $and$ls180.v:5651$1037_Y + connect \main_interface1_bus_ack $and$ls180.v:5652$1039_Y + connect \main_libresocsim_interface0_converted_interface_err $and$ls180.v:5653$1041_Y + connect \main_libresocsim_interface1_converted_interface_err $and$ls180.v:5654$1043_Y + connect \main_libresocsim_interface2_converted_interface_err $and$ls180.v:5655$1045_Y + connect \main_interface0_bus_err $and$ls180.v:5656$1047_Y + connect \main_interface1_bus_err $and$ls180.v:5657$1049_Y + connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_interface2_converted_interface_cyc \main_libresocsim_interface1_converted_interface_cyc \main_libresocsim_interface0_converted_interface_cyc } + connect \main_libresocsim_ram_bus_adr \builder_shared_adr + connect \main_libresocsim_ram_bus_dat_w \builder_shared_dat_w + connect \main_libresocsim_ram_bus_sel \builder_shared_sel + connect \main_libresocsim_ram_bus_stb \builder_shared_stb + connect \main_libresocsim_ram_bus_we \builder_shared_we + connect \main_libresocsim_ram_bus_cti \builder_shared_cti + connect \main_libresocsim_ram_bus_bte \builder_shared_bte + connect \main_libresocsim_libresoc_xics_icp_adr \builder_shared_adr + connect \main_libresocsim_libresoc_xics_icp_dat_w \builder_shared_dat_w + connect \main_libresocsim_libresoc_xics_icp_sel \builder_shared_sel + connect \main_libresocsim_libresoc_xics_icp_stb \builder_shared_stb + connect \main_libresocsim_libresoc_xics_icp_we \builder_shared_we + connect \main_libresocsim_libresoc_xics_icp_cti \builder_shared_cti + connect \main_libresocsim_libresoc_xics_icp_bte \builder_shared_bte + connect \main_libresocsim_libresoc_xics_ics_adr \builder_shared_adr + connect \main_libresocsim_libresoc_xics_ics_dat_w \builder_shared_dat_w + connect \main_libresocsim_libresoc_xics_ics_sel \builder_shared_sel + connect \main_libresocsim_libresoc_xics_ics_stb \builder_shared_stb + connect \main_libresocsim_libresoc_xics_ics_we \builder_shared_we + connect \main_libresocsim_libresoc_xics_ics_cti \builder_shared_cti + connect \main_libresocsim_libresoc_xics_ics_bte \builder_shared_bte + connect \main_wb_sdram_adr \builder_shared_adr + connect \main_wb_sdram_dat_w \builder_shared_dat_w + connect \main_wb_sdram_sel \builder_shared_sel + connect \main_wb_sdram_stb \builder_shared_stb + connect \main_wb_sdram_we \builder_shared_we + connect \main_wb_sdram_cti \builder_shared_cti + connect \main_wb_sdram_bte \builder_shared_bte + connect \builder_libresocsim_wishbone_adr \builder_shared_adr + connect \builder_libresocsim_wishbone_dat_w \builder_shared_dat_w + connect \builder_libresocsim_wishbone_sel \builder_shared_sel + connect \builder_libresocsim_wishbone_stb \builder_shared_stb + connect \builder_libresocsim_wishbone_we \builder_shared_we + connect \builder_libresocsim_wishbone_cti \builder_shared_cti + connect \builder_libresocsim_wishbone_bte \builder_shared_bte + connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5702$1056_Y + connect \main_libresocsim_libresoc_xics_icp_cyc $and$ls180.v:5703$1057_Y + connect \main_libresocsim_libresoc_xics_ics_cyc $and$ls180.v:5704$1058_Y + connect \main_wb_sdram_cyc $and$ls180.v:5705$1059_Y + connect \builder_libresocsim_wishbone_cyc $and$ls180.v:5706$1060_Y + connect \builder_shared_err $or$ls180.v:5707$1064_Y + connect \builder_wait $and$ls180.v:5708$1067_Y + connect \builder_done $eq$ls180.v:5721$1082_Y + connect \builder_csrbank0_sel $eq$ls180.v:5722$1083_Y + connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0] + connect \builder_csrbank0_reset0_re $and$ls180.v:5724$1086_Y + connect \builder_csrbank0_reset0_we $and$ls180.v:5725$1090_Y + connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch3_re $and$ls180.v:5727$1093_Y + connect \builder_csrbank0_scratch3_we $and$ls180.v:5728$1097_Y + connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch2_re $and$ls180.v:5730$1100_Y + connect \builder_csrbank0_scratch2_we $and$ls180.v:5731$1104_Y + connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch1_re $and$ls180.v:5733$1107_Y + connect \builder_csrbank0_scratch1_we $and$ls180.v:5734$1111_Y + connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch0_re $and$ls180.v:5736$1114_Y + connect \builder_csrbank0_scratch0_we $and$ls180.v:5737$1118_Y + connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5739$1121_Y + connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5740$1125_Y + connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5742$1128_Y + connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5743$1132_Y + connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5745$1135_Y + connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5746$1139_Y + connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5748$1142_Y + connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5749$1146_Y + connect \builder_csrbank0_reset0_w \main_libresocsim_reset_storage + connect \builder_csrbank0_scratch3_w \main_libresocsim_scratch_storage [31:24] + connect \builder_csrbank0_scratch2_w \main_libresocsim_scratch_storage [23:16] + connect \builder_csrbank0_scratch1_w \main_libresocsim_scratch_storage [15:8] + connect \builder_csrbank0_scratch0_w \main_libresocsim_scratch_storage [7:0] + connect \builder_csrbank0_bus_errors3_w \main_libresocsim_bus_errors_status [31:24] + connect \builder_csrbank0_bus_errors2_w \main_libresocsim_bus_errors_status [23:16] + connect \builder_csrbank0_bus_errors1_w \main_libresocsim_bus_errors_status [15:8] + connect \builder_csrbank0_bus_errors0_w \main_libresocsim_bus_errors_status [7:0] + connect \main_libresocsim_bus_errors_we \builder_csrbank0_bus_errors0_we + connect \builder_csrbank1_sel $eq$ls180.v:5760$1147_Y + connect \builder_csrbank1_oe1_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_oe1_re $and$ls180.v:5762$1150_Y + connect \builder_csrbank1_oe1_we $and$ls180.v:5763$1154_Y + connect \builder_csrbank1_oe0_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_oe0_re $and$ls180.v:5765$1157_Y + connect \builder_csrbank1_oe0_we $and$ls180.v:5766$1161_Y + connect \builder_csrbank1_in1_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_in1_re $and$ls180.v:5768$1164_Y + connect \builder_csrbank1_in1_we $and$ls180.v:5769$1168_Y + connect \builder_csrbank1_in0_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_in0_re $and$ls180.v:5771$1171_Y + connect \builder_csrbank1_in0_we $and$ls180.v:5772$1175_Y + connect \builder_csrbank1_out1_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_out1_re $and$ls180.v:5774$1178_Y + connect \builder_csrbank1_out1_we $and$ls180.v:5775$1182_Y + connect \builder_csrbank1_out0_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_out0_re $and$ls180.v:5777$1185_Y + connect \builder_csrbank1_out0_we $and$ls180.v:5778$1189_Y + connect \builder_csrbank1_oe1_w \main_gpio_oe_storage [15:8] + connect \builder_csrbank1_oe0_w \main_gpio_oe_storage [7:0] + connect \builder_csrbank1_in1_w \main_gpio_status [15:8] + connect \builder_csrbank1_in0_w \main_gpio_status [7:0] + connect \main_gpio_we \builder_csrbank1_in0_we + connect \builder_csrbank1_out1_w \main_gpio_out_storage [15:8] + connect \builder_csrbank1_out0_w \main_gpio_out_storage [7:0] + connect \builder_csrbank2_sel $eq$ls180.v:5786$1190_Y + connect \builder_csrbank2_enable0_r \builder_interface2_bank_bus_dat_w [0] + connect \builder_csrbank2_enable0_re $and$ls180.v:5788$1193_Y + connect \builder_csrbank2_enable0_we $and$ls180.v:5789$1197_Y + connect \builder_csrbank2_width3_r \builder_interface2_bank_bus_dat_w + connect \builder_csrbank2_width3_re $and$ls180.v:5791$1200_Y + connect \builder_csrbank2_width3_we $and$ls180.v:5792$1204_Y + connect \builder_csrbank2_width2_r \builder_interface2_bank_bus_dat_w + connect \builder_csrbank2_width2_re $and$ls180.v:5794$1207_Y + connect \builder_csrbank2_width2_we $and$ls180.v:5795$1211_Y + connect \builder_csrbank2_width1_r \builder_interface2_bank_bus_dat_w + connect \builder_csrbank2_width1_re $and$ls180.v:5797$1214_Y + connect \builder_csrbank2_width1_we $and$ls180.v:5798$1218_Y + connect \builder_csrbank2_width0_r \builder_interface2_bank_bus_dat_w + connect \builder_csrbank2_width0_re $and$ls180.v:5800$1221_Y + connect \builder_csrbank2_width0_we $and$ls180.v:5801$1225_Y + connect \builder_csrbank2_period3_r \builder_interface2_bank_bus_dat_w + connect \builder_csrbank2_period3_re $and$ls180.v:5803$1228_Y + connect \builder_csrbank2_period3_we $and$ls180.v:5804$1232_Y + connect \builder_csrbank2_period2_r \builder_interface2_bank_bus_dat_w + connect \builder_csrbank2_period2_re $and$ls180.v:5806$1235_Y + connect \builder_csrbank2_period2_we $and$ls180.v:5807$1239_Y + connect \builder_csrbank2_period1_r \builder_interface2_bank_bus_dat_w + connect \builder_csrbank2_period1_re $and$ls180.v:5809$1242_Y + connect \builder_csrbank2_period1_we $and$ls180.v:5810$1246_Y + connect \builder_csrbank2_period0_r \builder_interface2_bank_bus_dat_w + connect \builder_csrbank2_period0_re $and$ls180.v:5812$1249_Y + connect \builder_csrbank2_period0_we $and$ls180.v:5813$1253_Y + connect \builder_csrbank2_enable0_w \main_pwm0_enable_storage + connect \builder_csrbank2_width3_w \main_pwm0_width_storage [31:24] + connect \builder_csrbank2_width2_w \main_pwm0_width_storage [23:16] + connect \builder_csrbank2_width1_w \main_pwm0_width_storage [15:8] + connect \builder_csrbank2_width0_w \main_pwm0_width_storage [7:0] + connect \builder_csrbank2_period3_w \main_pwm0_period_storage [31:24] + connect \builder_csrbank2_period2_w \main_pwm0_period_storage [23:16] + connect \builder_csrbank2_period1_w \main_pwm0_period_storage [15:8] + connect \builder_csrbank2_period0_w \main_pwm0_period_storage [7:0] + connect \builder_csrbank3_sel $eq$ls180.v:5823$1254_Y + connect \builder_csrbank3_enable0_r \builder_interface3_bank_bus_dat_w [0] + connect \builder_csrbank3_enable0_re $and$ls180.v:5825$1257_Y + connect \builder_csrbank3_enable0_we $and$ls180.v:5826$1261_Y + connect \builder_csrbank3_width3_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width3_re $and$ls180.v:5828$1264_Y + connect \builder_csrbank3_width3_we $and$ls180.v:5829$1268_Y + connect \builder_csrbank3_width2_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width2_re $and$ls180.v:5831$1271_Y + connect \builder_csrbank3_width2_we $and$ls180.v:5832$1275_Y + connect \builder_csrbank3_width1_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width1_re $and$ls180.v:5834$1278_Y + connect \builder_csrbank3_width1_we $and$ls180.v:5835$1282_Y + connect \builder_csrbank3_width0_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width0_re $and$ls180.v:5837$1285_Y + connect \builder_csrbank3_width0_we $and$ls180.v:5838$1289_Y + connect \builder_csrbank3_period3_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period3_re $and$ls180.v:5840$1292_Y + connect \builder_csrbank3_period3_we $and$ls180.v:5841$1296_Y + connect \builder_csrbank3_period2_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period2_re $and$ls180.v:5843$1299_Y + connect \builder_csrbank3_period2_we $and$ls180.v:5844$1303_Y + connect \builder_csrbank3_period1_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period1_re $and$ls180.v:5846$1306_Y + connect \builder_csrbank3_period1_we $and$ls180.v:5847$1310_Y + connect \builder_csrbank3_period0_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period0_re $and$ls180.v:5849$1313_Y + connect \builder_csrbank3_period0_we $and$ls180.v:5850$1317_Y + connect \builder_csrbank3_enable0_w \main_pwm1_enable_storage + connect \builder_csrbank3_width3_w \main_pwm1_width_storage [31:24] + connect \builder_csrbank3_width2_w \main_pwm1_width_storage [23:16] + connect \builder_csrbank3_width1_w \main_pwm1_width_storage [15:8] + connect \builder_csrbank3_width0_w \main_pwm1_width_storage [7:0] + connect \builder_csrbank3_period3_w \main_pwm1_period_storage [31:24] + connect \builder_csrbank3_period2_w \main_pwm1_period_storage [23:16] + connect \builder_csrbank3_period1_w \main_pwm1_period_storage [15:8] + connect \builder_csrbank3_period0_w \main_pwm1_period_storage [7:0] + connect \builder_csrbank4_sel $eq$ls180.v:5860$1318_Y + connect \builder_csrbank4_dma_base7_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_dma_base7_re $and$ls180.v:5862$1321_Y + connect \builder_csrbank4_dma_base7_we $and$ls180.v:5863$1325_Y + connect \builder_csrbank4_dma_base6_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_dma_base6_re $and$ls180.v:5865$1328_Y + connect \builder_csrbank4_dma_base6_we $and$ls180.v:5866$1332_Y + connect \builder_csrbank4_dma_base5_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_dma_base5_re $and$ls180.v:5868$1335_Y + connect \builder_csrbank4_dma_base5_we $and$ls180.v:5869$1339_Y + connect \builder_csrbank4_dma_base4_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_dma_base4_re $and$ls180.v:5871$1342_Y + connect \builder_csrbank4_dma_base4_we $and$ls180.v:5872$1346_Y + connect \builder_csrbank4_dma_base3_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_dma_base3_re $and$ls180.v:5874$1349_Y + connect \builder_csrbank4_dma_base3_we $and$ls180.v:5875$1353_Y + connect \builder_csrbank4_dma_base2_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_dma_base2_re $and$ls180.v:5877$1356_Y + connect \builder_csrbank4_dma_base2_we $and$ls180.v:5878$1360_Y + connect \builder_csrbank4_dma_base1_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_dma_base1_re $and$ls180.v:5880$1363_Y + connect \builder_csrbank4_dma_base1_we $and$ls180.v:5881$1367_Y + connect \builder_csrbank4_dma_base0_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_dma_base0_re $and$ls180.v:5883$1370_Y + connect \builder_csrbank4_dma_base0_we $and$ls180.v:5884$1374_Y + connect \builder_csrbank4_dma_length3_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_dma_length3_re $and$ls180.v:5886$1377_Y + connect \builder_csrbank4_dma_length3_we $and$ls180.v:5887$1381_Y + connect \builder_csrbank4_dma_length2_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_dma_length2_re $and$ls180.v:5889$1384_Y + connect \builder_csrbank4_dma_length2_we $and$ls180.v:5890$1388_Y + connect \builder_csrbank4_dma_length1_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_dma_length1_re $and$ls180.v:5892$1391_Y + connect \builder_csrbank4_dma_length1_we $and$ls180.v:5893$1395_Y + connect \builder_csrbank4_dma_length0_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_dma_length0_re $and$ls180.v:5895$1398_Y + connect \builder_csrbank4_dma_length0_we $and$ls180.v:5896$1402_Y + connect \builder_csrbank4_dma_enable0_r \builder_interface4_bank_bus_dat_w [0] + connect \builder_csrbank4_dma_enable0_re $and$ls180.v:5898$1405_Y + connect \builder_csrbank4_dma_enable0_we $and$ls180.v:5899$1409_Y + connect \builder_csrbank4_dma_done_r \builder_interface4_bank_bus_dat_w [0] + connect \builder_csrbank4_dma_done_re $and$ls180.v:5901$1412_Y + connect \builder_csrbank4_dma_done_we $and$ls180.v:5902$1416_Y + connect \builder_csrbank4_dma_loop0_r \builder_interface4_bank_bus_dat_w [0] + connect \builder_csrbank4_dma_loop0_re $and$ls180.v:5904$1419_Y + connect \builder_csrbank4_dma_loop0_we $and$ls180.v:5905$1423_Y + connect \builder_csrbank4_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56] + connect \builder_csrbank4_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48] + connect \builder_csrbank4_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40] + connect \builder_csrbank4_dma_base4_w \main_sdblock2mem_wishbonedmawriter_base_storage [39:32] + connect \builder_csrbank4_dma_base3_w \main_sdblock2mem_wishbonedmawriter_base_storage [31:24] + connect \builder_csrbank4_dma_base2_w \main_sdblock2mem_wishbonedmawriter_base_storage [23:16] + connect \builder_csrbank4_dma_base1_w \main_sdblock2mem_wishbonedmawriter_base_storage [15:8] + connect \builder_csrbank4_dma_base0_w \main_sdblock2mem_wishbonedmawriter_base_storage [7:0] + connect \builder_csrbank4_dma_length3_w \main_sdblock2mem_wishbonedmawriter_length_storage [31:24] + connect \builder_csrbank4_dma_length2_w \main_sdblock2mem_wishbonedmawriter_length_storage [23:16] + connect \builder_csrbank4_dma_length1_w \main_sdblock2mem_wishbonedmawriter_length_storage [15:8] + connect \builder_csrbank4_dma_length0_w \main_sdblock2mem_wishbonedmawriter_length_storage [7:0] + connect \builder_csrbank4_dma_enable0_w \main_sdblock2mem_wishbonedmawriter_enable_storage + connect \builder_csrbank4_dma_done_w \main_sdblock2mem_wishbonedmawriter_status + connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank4_dma_done_we + connect \builder_csrbank4_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage + connect \builder_csrbank5_sel $eq$ls180.v:5922$1424_Y + connect \builder_csrbank5_cmd_argument3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_argument3_re $and$ls180.v:5924$1427_Y + connect \builder_csrbank5_cmd_argument3_we $and$ls180.v:5925$1431_Y + connect \builder_csrbank5_cmd_argument2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_argument2_re $and$ls180.v:5927$1434_Y + connect \builder_csrbank5_cmd_argument2_we $and$ls180.v:5928$1438_Y + connect \builder_csrbank5_cmd_argument1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_argument1_re $and$ls180.v:5930$1441_Y + connect \builder_csrbank5_cmd_argument1_we $and$ls180.v:5931$1445_Y + connect \builder_csrbank5_cmd_argument0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_argument0_re $and$ls180.v:5933$1448_Y + connect \builder_csrbank5_cmd_argument0_we $and$ls180.v:5934$1452_Y + connect \builder_csrbank5_cmd_command3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_command3_re $and$ls180.v:5936$1455_Y + connect \builder_csrbank5_cmd_command3_we $and$ls180.v:5937$1459_Y + connect \builder_csrbank5_cmd_command2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_command2_re $and$ls180.v:5939$1462_Y + connect \builder_csrbank5_cmd_command2_we $and$ls180.v:5940$1466_Y + connect \builder_csrbank5_cmd_command1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_command1_re $and$ls180.v:5942$1469_Y + connect \builder_csrbank5_cmd_command1_we $and$ls180.v:5943$1473_Y + connect \builder_csrbank5_cmd_command0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_command0_re $and$ls180.v:5945$1476_Y + connect \builder_csrbank5_cmd_command0_we $and$ls180.v:5946$1480_Y + connect \main_sdcore_cmd_send_r \builder_interface5_bank_bus_dat_w [0] + connect \main_sdcore_cmd_send_re $and$ls180.v:5948$1483_Y + connect \main_sdcore_cmd_send_we $and$ls180.v:5949$1487_Y + connect \builder_csrbank5_cmd_response15_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response15_re $and$ls180.v:5951$1490_Y + connect \builder_csrbank5_cmd_response15_we $and$ls180.v:5952$1494_Y + connect \builder_csrbank5_cmd_response14_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response14_re $and$ls180.v:5954$1497_Y + connect \builder_csrbank5_cmd_response14_we $and$ls180.v:5955$1501_Y + connect \builder_csrbank5_cmd_response13_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response13_re $and$ls180.v:5957$1504_Y + connect \builder_csrbank5_cmd_response13_we $and$ls180.v:5958$1508_Y + connect \builder_csrbank5_cmd_response12_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response12_re $and$ls180.v:5960$1511_Y + connect \builder_csrbank5_cmd_response12_we $and$ls180.v:5961$1515_Y + connect \builder_csrbank5_cmd_response11_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response11_re $and$ls180.v:5963$1518_Y + connect \builder_csrbank5_cmd_response11_we $and$ls180.v:5964$1522_Y + connect \builder_csrbank5_cmd_response10_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response10_re $and$ls180.v:5966$1525_Y + connect \builder_csrbank5_cmd_response10_we $and$ls180.v:5967$1529_Y + connect \builder_csrbank5_cmd_response9_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response9_re $and$ls180.v:5969$1532_Y + connect \builder_csrbank5_cmd_response9_we $and$ls180.v:5970$1536_Y + connect \builder_csrbank5_cmd_response8_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response8_re $and$ls180.v:5972$1539_Y + connect \builder_csrbank5_cmd_response8_we $and$ls180.v:5973$1543_Y + connect \builder_csrbank5_cmd_response7_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response7_re $and$ls180.v:5975$1546_Y + connect \builder_csrbank5_cmd_response7_we $and$ls180.v:5976$1550_Y + connect \builder_csrbank5_cmd_response6_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response6_re $and$ls180.v:5978$1553_Y + connect \builder_csrbank5_cmd_response6_we $and$ls180.v:5979$1557_Y + connect \builder_csrbank5_cmd_response5_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response5_re $and$ls180.v:5981$1560_Y + connect \builder_csrbank5_cmd_response5_we $and$ls180.v:5982$1564_Y + connect \builder_csrbank5_cmd_response4_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response4_re $and$ls180.v:5984$1567_Y + connect \builder_csrbank5_cmd_response4_we $and$ls180.v:5985$1571_Y + connect \builder_csrbank5_cmd_response3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response3_re $and$ls180.v:5987$1574_Y + connect \builder_csrbank5_cmd_response3_we $and$ls180.v:5988$1578_Y + connect \builder_csrbank5_cmd_response2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response2_re $and$ls180.v:5990$1581_Y + connect \builder_csrbank5_cmd_response2_we $and$ls180.v:5991$1585_Y + connect \builder_csrbank5_cmd_response1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response1_re $and$ls180.v:5993$1588_Y + connect \builder_csrbank5_cmd_response1_we $and$ls180.v:5994$1592_Y + connect \builder_csrbank5_cmd_response0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response0_re $and$ls180.v:5996$1595_Y + connect \builder_csrbank5_cmd_response0_we $and$ls180.v:5997$1599_Y + connect \builder_csrbank5_cmd_event_r \builder_interface5_bank_bus_dat_w [3:0] + connect \builder_csrbank5_cmd_event_re $and$ls180.v:5999$1602_Y + connect \builder_csrbank5_cmd_event_we $and$ls180.v:6000$1606_Y + connect \builder_csrbank5_data_event_r \builder_interface5_bank_bus_dat_w [3:0] + connect \builder_csrbank5_data_event_re $and$ls180.v:6002$1609_Y + connect \builder_csrbank5_data_event_we $and$ls180.v:6003$1613_Y + connect \builder_csrbank5_block_length1_r \builder_interface5_bank_bus_dat_w [1:0] + connect \builder_csrbank5_block_length1_re $and$ls180.v:6005$1616_Y + connect \builder_csrbank5_block_length1_we $and$ls180.v:6006$1620_Y + connect \builder_csrbank5_block_length0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_block_length0_re $and$ls180.v:6008$1623_Y + connect \builder_csrbank5_block_length0_we $and$ls180.v:6009$1627_Y + connect \builder_csrbank5_block_count3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_block_count3_re $and$ls180.v:6011$1630_Y + connect \builder_csrbank5_block_count3_we $and$ls180.v:6012$1634_Y + connect \builder_csrbank5_block_count2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_block_count2_re $and$ls180.v:6014$1637_Y + connect \builder_csrbank5_block_count2_we $and$ls180.v:6015$1641_Y + connect \builder_csrbank5_block_count1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_block_count1_re $and$ls180.v:6017$1644_Y + connect \builder_csrbank5_block_count1_we $and$ls180.v:6018$1648_Y + connect \builder_csrbank5_block_count0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_block_count0_re $and$ls180.v:6020$1651_Y + connect \builder_csrbank5_block_count0_we $and$ls180.v:6021$1655_Y + connect \builder_csrbank5_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24] + connect \builder_csrbank5_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16] + connect \builder_csrbank5_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8] + connect \builder_csrbank5_cmd_argument0_w \main_sdcore_cmd_argument_storage [7:0] + connect \builder_csrbank5_cmd_command3_w \main_sdcore_cmd_command_storage [31:24] + connect \builder_csrbank5_cmd_command2_w \main_sdcore_cmd_command_storage [23:16] + connect \builder_csrbank5_cmd_command1_w \main_sdcore_cmd_command_storage [15:8] + connect \builder_csrbank5_cmd_command0_w \main_sdcore_cmd_command_storage [7:0] + connect \builder_csrbank5_cmd_response15_w \main_sdcore_cmd_response_status [127:120] + connect \builder_csrbank5_cmd_response14_w \main_sdcore_cmd_response_status [119:112] + connect \builder_csrbank5_cmd_response13_w \main_sdcore_cmd_response_status [111:104] + connect \builder_csrbank5_cmd_response12_w \main_sdcore_cmd_response_status [103:96] + connect \builder_csrbank5_cmd_response11_w \main_sdcore_cmd_response_status [95:88] + connect \builder_csrbank5_cmd_response10_w \main_sdcore_cmd_response_status [87:80] + connect \builder_csrbank5_cmd_response9_w \main_sdcore_cmd_response_status [79:72] + connect \builder_csrbank5_cmd_response8_w \main_sdcore_cmd_response_status [71:64] + connect \builder_csrbank5_cmd_response7_w \main_sdcore_cmd_response_status [63:56] + connect \builder_csrbank5_cmd_response6_w \main_sdcore_cmd_response_status [55:48] + connect \builder_csrbank5_cmd_response5_w \main_sdcore_cmd_response_status [47:40] + connect \builder_csrbank5_cmd_response4_w \main_sdcore_cmd_response_status [39:32] + connect \builder_csrbank5_cmd_response3_w \main_sdcore_cmd_response_status [31:24] + connect \builder_csrbank5_cmd_response2_w \main_sdcore_cmd_response_status [23:16] + connect \builder_csrbank5_cmd_response1_w \main_sdcore_cmd_response_status [15:8] + connect \builder_csrbank5_cmd_response0_w \main_sdcore_cmd_response_status [7:0] + connect \main_sdcore_cmd_response_we \builder_csrbank5_cmd_response0_we + connect \builder_csrbank5_cmd_event_w \main_sdcore_cmd_event_status + connect \main_sdcore_cmd_event_we \builder_csrbank5_cmd_event_we + connect \builder_csrbank5_data_event_w \main_sdcore_data_event_status + connect \main_sdcore_data_event_we \builder_csrbank5_data_event_we + connect \builder_csrbank5_block_length1_w \main_sdcore_block_length_storage [9:8] + connect \builder_csrbank5_block_length0_w \main_sdcore_block_length_storage [7:0] + connect \builder_csrbank5_block_count3_w \main_sdcore_block_count_storage [31:24] + connect \builder_csrbank5_block_count2_w \main_sdcore_block_count_storage [23:16] + connect \builder_csrbank5_block_count1_w \main_sdcore_block_count_storage [15:8] + connect \builder_csrbank5_block_count0_w \main_sdcore_block_count_storage [7:0] + connect \builder_csrbank6_sel $eq$ls180.v:6057$1656_Y + connect \builder_csrbank6_dma_base7_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_base7_re $and$ls180.v:6059$1659_Y + connect \builder_csrbank6_dma_base7_we $and$ls180.v:6060$1663_Y + connect \builder_csrbank6_dma_base6_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_base6_re $and$ls180.v:6062$1666_Y + connect \builder_csrbank6_dma_base6_we $and$ls180.v:6063$1670_Y + connect \builder_csrbank6_dma_base5_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_base5_re $and$ls180.v:6065$1673_Y + connect \builder_csrbank6_dma_base5_we $and$ls180.v:6066$1677_Y + connect \builder_csrbank6_dma_base4_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_base4_re $and$ls180.v:6068$1680_Y + connect \builder_csrbank6_dma_base4_we $and$ls180.v:6069$1684_Y + connect \builder_csrbank6_dma_base3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_base3_re $and$ls180.v:6071$1687_Y + connect \builder_csrbank6_dma_base3_we $and$ls180.v:6072$1691_Y + connect \builder_csrbank6_dma_base2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_base2_re $and$ls180.v:6074$1694_Y + connect \builder_csrbank6_dma_base2_we $and$ls180.v:6075$1698_Y + connect \builder_csrbank6_dma_base1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_base1_re $and$ls180.v:6077$1701_Y + connect \builder_csrbank6_dma_base1_we $and$ls180.v:6078$1705_Y + connect \builder_csrbank6_dma_base0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_base0_re $and$ls180.v:6080$1708_Y + connect \builder_csrbank6_dma_base0_we $and$ls180.v:6081$1712_Y + connect \builder_csrbank6_dma_length3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_length3_re $and$ls180.v:6083$1715_Y + connect \builder_csrbank6_dma_length3_we $and$ls180.v:6084$1719_Y + connect \builder_csrbank6_dma_length2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_length2_re $and$ls180.v:6086$1722_Y + connect \builder_csrbank6_dma_length2_we $and$ls180.v:6087$1726_Y + connect \builder_csrbank6_dma_length1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_length1_re $and$ls180.v:6089$1729_Y + connect \builder_csrbank6_dma_length1_we $and$ls180.v:6090$1733_Y + connect \builder_csrbank6_dma_length0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_length0_re $and$ls180.v:6092$1736_Y + connect \builder_csrbank6_dma_length0_we $and$ls180.v:6093$1740_Y + connect \builder_csrbank6_dma_enable0_r \builder_interface6_bank_bus_dat_w [0] + connect \builder_csrbank6_dma_enable0_re $and$ls180.v:6095$1743_Y + connect \builder_csrbank6_dma_enable0_we $and$ls180.v:6096$1747_Y + connect \builder_csrbank6_dma_done_r \builder_interface6_bank_bus_dat_w [0] + connect \builder_csrbank6_dma_done_re $and$ls180.v:6098$1750_Y + connect \builder_csrbank6_dma_done_we $and$ls180.v:6099$1754_Y + connect \builder_csrbank6_dma_loop0_r \builder_interface6_bank_bus_dat_w [0] + connect \builder_csrbank6_dma_loop0_re $and$ls180.v:6101$1757_Y + connect \builder_csrbank6_dma_loop0_we $and$ls180.v:6102$1761_Y + connect \builder_csrbank6_dma_offset3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_offset3_re $and$ls180.v:6104$1764_Y + connect \builder_csrbank6_dma_offset3_we $and$ls180.v:6105$1768_Y + connect \builder_csrbank6_dma_offset2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_offset2_re $and$ls180.v:6107$1771_Y + connect \builder_csrbank6_dma_offset2_we $and$ls180.v:6108$1775_Y + connect \builder_csrbank6_dma_offset1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_offset1_re $and$ls180.v:6110$1778_Y + connect \builder_csrbank6_dma_offset1_we $and$ls180.v:6111$1782_Y + connect \builder_csrbank6_dma_offset0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_offset0_re $and$ls180.v:6113$1785_Y + connect \builder_csrbank6_dma_offset0_we $and$ls180.v:6114$1789_Y + connect \builder_csrbank6_dma_base7_w \main_sdmem2block_dma_base_storage [63:56] + connect \builder_csrbank6_dma_base6_w \main_sdmem2block_dma_base_storage [55:48] + connect \builder_csrbank6_dma_base5_w \main_sdmem2block_dma_base_storage [47:40] + connect \builder_csrbank6_dma_base4_w \main_sdmem2block_dma_base_storage [39:32] + connect \builder_csrbank6_dma_base3_w \main_sdmem2block_dma_base_storage [31:24] + connect \builder_csrbank6_dma_base2_w \main_sdmem2block_dma_base_storage [23:16] + connect \builder_csrbank6_dma_base1_w \main_sdmem2block_dma_base_storage [15:8] + connect \builder_csrbank6_dma_base0_w \main_sdmem2block_dma_base_storage [7:0] + connect \builder_csrbank6_dma_length3_w \main_sdmem2block_dma_length_storage [31:24] + connect \builder_csrbank6_dma_length2_w \main_sdmem2block_dma_length_storage [23:16] + connect \builder_csrbank6_dma_length1_w \main_sdmem2block_dma_length_storage [15:8] + connect \builder_csrbank6_dma_length0_w \main_sdmem2block_dma_length_storage [7:0] + connect \builder_csrbank6_dma_enable0_w \main_sdmem2block_dma_enable_storage + connect \builder_csrbank6_dma_done_w \main_sdmem2block_dma_done_status + connect \main_sdmem2block_dma_done_we \builder_csrbank6_dma_done_we + connect \builder_csrbank6_dma_loop0_w \main_sdmem2block_dma_loop_storage + connect \builder_csrbank6_dma_offset3_w \main_sdmem2block_dma_offset_status [31:24] + connect \builder_csrbank6_dma_offset2_w \main_sdmem2block_dma_offset_status [23:16] + connect \builder_csrbank6_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8] + connect \builder_csrbank6_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0] + connect \main_sdmem2block_dma_offset_we \builder_csrbank6_dma_offset0_we + connect \builder_csrbank7_sel $eq$ls180.v:6136$1790_Y + connect \builder_csrbank7_card_detect_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_card_detect_re $and$ls180.v:6138$1793_Y + connect \builder_csrbank7_card_detect_we $and$ls180.v:6139$1797_Y + connect \builder_csrbank7_clocker_divider1_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_clocker_divider1_re $and$ls180.v:6141$1800_Y + connect \builder_csrbank7_clocker_divider1_we $and$ls180.v:6142$1804_Y + connect \builder_csrbank7_clocker_divider0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_clocker_divider0_re $and$ls180.v:6144$1807_Y + connect \builder_csrbank7_clocker_divider0_we $and$ls180.v:6145$1811_Y + connect \main_sdphy_init_initialize_r \builder_interface7_bank_bus_dat_w [0] + connect \main_sdphy_init_initialize_re $and$ls180.v:6147$1814_Y + connect \main_sdphy_init_initialize_we $and$ls180.v:6148$1818_Y + connect \builder_csrbank7_card_detect_w \main_sdphy_status + connect \main_sdphy_we \builder_csrbank7_card_detect_we + connect \builder_csrbank7_clocker_divider1_w \main_sdphy_clocker_storage [8] + connect \builder_csrbank7_clocker_divider0_w \main_sdphy_clocker_storage [7:0] + connect \builder_csrbank8_sel $eq$ls180.v:6153$1819_Y + connect \builder_csrbank8_dfii_control0_r \builder_interface8_bank_bus_dat_w [3:0] + connect \builder_csrbank8_dfii_control0_re $and$ls180.v:6155$1822_Y + connect \builder_csrbank8_dfii_control0_we $and$ls180.v:6156$1826_Y + connect \builder_csrbank8_dfii_pi0_command0_r \builder_interface8_bank_bus_dat_w [5:0] + connect \builder_csrbank8_dfii_pi0_command0_re $and$ls180.v:6158$1829_Y + connect \builder_csrbank8_dfii_pi0_command0_we $and$ls180.v:6159$1833_Y + connect \main_sdram_command_issue_r \builder_interface8_bank_bus_dat_w [0] + connect \main_sdram_command_issue_re $and$ls180.v:6161$1836_Y + connect \main_sdram_command_issue_we $and$ls180.v:6162$1840_Y + connect \builder_csrbank8_dfii_pi0_address1_r \builder_interface8_bank_bus_dat_w [4:0] + connect \builder_csrbank8_dfii_pi0_address1_re $and$ls180.v:6164$1843_Y + connect \builder_csrbank8_dfii_pi0_address1_we $and$ls180.v:6165$1847_Y + connect \builder_csrbank8_dfii_pi0_address0_r \builder_interface8_bank_bus_dat_w + connect \builder_csrbank8_dfii_pi0_address0_re $and$ls180.v:6167$1850_Y + connect \builder_csrbank8_dfii_pi0_address0_we $and$ls180.v:6168$1854_Y + connect \builder_csrbank8_dfii_pi0_baddress0_r \builder_interface8_bank_bus_dat_w [1:0] + connect \builder_csrbank8_dfii_pi0_baddress0_re $and$ls180.v:6170$1857_Y + connect \builder_csrbank8_dfii_pi0_baddress0_we $and$ls180.v:6171$1861_Y + connect \builder_csrbank8_dfii_pi0_wrdata1_r \builder_interface8_bank_bus_dat_w + connect \builder_csrbank8_dfii_pi0_wrdata1_re $and$ls180.v:6173$1864_Y + connect \builder_csrbank8_dfii_pi0_wrdata1_we $and$ls180.v:6174$1868_Y + connect \builder_csrbank8_dfii_pi0_wrdata0_r \builder_interface8_bank_bus_dat_w + connect \builder_csrbank8_dfii_pi0_wrdata0_re $and$ls180.v:6176$1871_Y + connect \builder_csrbank8_dfii_pi0_wrdata0_we $and$ls180.v:6177$1875_Y + connect \builder_csrbank8_dfii_pi0_rddata1_r \builder_interface8_bank_bus_dat_w + connect \builder_csrbank8_dfii_pi0_rddata1_re $and$ls180.v:6179$1878_Y + connect \builder_csrbank8_dfii_pi0_rddata1_we $and$ls180.v:6180$1882_Y + connect \builder_csrbank8_dfii_pi0_rddata0_r \builder_interface8_bank_bus_dat_w + connect \builder_csrbank8_dfii_pi0_rddata0_re $and$ls180.v:6182$1885_Y + connect \builder_csrbank8_dfii_pi0_rddata0_we $and$ls180.v:6183$1889_Y + connect \main_sdram_sel \main_sdram_storage [0] + connect \main_sdram_cke \main_sdram_storage [1] + connect \main_sdram_odt \main_sdram_storage [2] + connect \main_sdram_reset_n \main_sdram_storage [3] + connect \builder_csrbank8_dfii_control0_w \main_sdram_storage + connect \builder_csrbank8_dfii_pi0_command0_w \main_sdram_command_storage + connect \builder_csrbank8_dfii_pi0_address1_w \main_sdram_address_storage [12:8] + connect \builder_csrbank8_dfii_pi0_address0_w \main_sdram_address_storage [7:0] + connect \builder_csrbank8_dfii_pi0_baddress0_w \main_sdram_baddress_storage + connect \builder_csrbank8_dfii_pi0_wrdata1_w \main_sdram_wrdata_storage [15:8] + connect \builder_csrbank8_dfii_pi0_wrdata0_w \main_sdram_wrdata_storage [7:0] + connect \builder_csrbank8_dfii_pi0_rddata1_w \main_sdram_status [15:8] + connect \builder_csrbank8_dfii_pi0_rddata0_w \main_sdram_status [7:0] + connect \main_sdram_we \builder_csrbank8_dfii_pi0_rddata0_we + connect \builder_csrbank9_sel $eq$ls180.v:6198$1890_Y + connect \builder_csrbank9_control1_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_control1_re $and$ls180.v:6200$1893_Y + connect \builder_csrbank9_control1_we $and$ls180.v:6201$1897_Y + connect \builder_csrbank9_control0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_control0_re $and$ls180.v:6203$1900_Y + connect \builder_csrbank9_control0_we $and$ls180.v:6204$1904_Y + connect \builder_csrbank9_status_r \builder_interface9_bank_bus_dat_w [0] + connect \builder_csrbank9_status_re $and$ls180.v:6206$1907_Y + connect \builder_csrbank9_status_we $and$ls180.v:6207$1911_Y + connect \builder_csrbank9_mosi0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_mosi0_re $and$ls180.v:6209$1914_Y + connect \builder_csrbank9_mosi0_we $and$ls180.v:6210$1918_Y + connect \builder_csrbank9_miso_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_miso_re $and$ls180.v:6212$1921_Y + connect \builder_csrbank9_miso_we $and$ls180.v:6213$1925_Y + connect \builder_csrbank9_cs0_r \builder_interface9_bank_bus_dat_w [0] + connect \builder_csrbank9_cs0_re $and$ls180.v:6215$1928_Y + connect \builder_csrbank9_cs0_we $and$ls180.v:6216$1932_Y + connect \builder_csrbank9_loopback0_r \builder_interface9_bank_bus_dat_w [0] + connect \builder_csrbank9_loopback0_re $and$ls180.v:6218$1935_Y + connect \builder_csrbank9_loopback0_we $and$ls180.v:6219$1939_Y + connect \main_spi_master_length1 \main_spi_master_control_storage [15:8] + connect \builder_csrbank9_control1_w \main_spi_master_control_storage [15:8] + connect \builder_csrbank9_control0_w \main_spi_master_control_storage [7:0] + connect \main_spi_master_status_status \main_spi_master_done1 + connect \builder_csrbank9_status_w \main_spi_master_status_status + connect \main_spi_master_status_we \builder_csrbank9_status_we + connect \builder_csrbank9_mosi0_w \main_spi_master_mosi_storage + connect \builder_csrbank9_miso_w \main_spi_master_miso_status + connect \main_spi_master_miso_we \builder_csrbank9_miso_we + connect \main_spi_master_sel \main_spi_master_cs_storage + connect \builder_csrbank9_cs0_w \main_spi_master_cs_storage + connect \builder_csrbank9_loopback0_w \main_spi_master_loopback_storage + connect \builder_csrbank10_sel $eq$ls180.v:6238$1941_Y + connect \builder_csrbank10_control1_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_control1_re $and$ls180.v:6240$1944_Y + connect \builder_csrbank10_control1_we $and$ls180.v:6241$1948_Y + connect \builder_csrbank10_control0_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_control0_re $and$ls180.v:6243$1951_Y + connect \builder_csrbank10_control0_we $and$ls180.v:6244$1955_Y + connect \builder_csrbank10_status_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_status_re $and$ls180.v:6246$1958_Y + connect \builder_csrbank10_status_we $and$ls180.v:6247$1962_Y + connect \builder_csrbank10_mosi0_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_mosi0_re $and$ls180.v:6249$1965_Y + connect \builder_csrbank10_mosi0_we $and$ls180.v:6250$1969_Y + connect \builder_csrbank10_miso_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_miso_re $and$ls180.v:6252$1972_Y + connect \builder_csrbank10_miso_we $and$ls180.v:6253$1976_Y + connect \builder_csrbank10_cs0_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_cs0_re $and$ls180.v:6255$1979_Y + connect \builder_csrbank10_cs0_we $and$ls180.v:6256$1983_Y + connect \builder_csrbank10_loopback0_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_loopback0_re $and$ls180.v:6258$1986_Y + connect \builder_csrbank10_loopback0_we $and$ls180.v:6259$1990_Y + connect \builder_csrbank10_clk_divider1_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_clk_divider1_re $and$ls180.v:6261$1993_Y + connect \builder_csrbank10_clk_divider1_we $and$ls180.v:6262$1997_Y + connect \builder_csrbank10_clk_divider0_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_clk_divider0_re $and$ls180.v:6264$2000_Y + connect \builder_csrbank10_clk_divider0_we $and$ls180.v:6265$2004_Y + connect \libresocsim_length1 \libresocsim_control_storage [15:8] + connect \builder_csrbank10_control1_w \libresocsim_control_storage [15:8] + connect \builder_csrbank10_control0_w \libresocsim_control_storage [7:0] + connect \libresocsim_status_status \libresocsim_done1 + connect \builder_csrbank10_status_w \libresocsim_status_status + connect \libresocsim_status_we \builder_csrbank10_status_we + connect \builder_csrbank10_mosi0_w \libresocsim_mosi_storage + connect \builder_csrbank10_miso_w \libresocsim_miso_status + connect \libresocsim_miso_we \builder_csrbank10_miso_we + connect \libresocsim_sel \libresocsim_cs_storage + connect \builder_csrbank10_cs0_w \libresocsim_cs_storage + connect \builder_csrbank10_loopback0_w \libresocsim_loopback_storage + connect \builder_csrbank10_clk_divider1_w \libresocsim_storage [15:8] + connect \builder_csrbank10_clk_divider0_w \libresocsim_storage [7:0] + connect \builder_csrbank11_sel $eq$ls180.v:6286$2006_Y + connect \builder_csrbank11_load3_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_load3_re $and$ls180.v:6288$2009_Y + connect \builder_csrbank11_load3_we $and$ls180.v:6289$2013_Y + connect \builder_csrbank11_load2_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_load2_re $and$ls180.v:6291$2016_Y + connect \builder_csrbank11_load2_we $and$ls180.v:6292$2020_Y + connect \builder_csrbank11_load1_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_load1_re $and$ls180.v:6294$2023_Y + connect \builder_csrbank11_load1_we $and$ls180.v:6295$2027_Y + connect \builder_csrbank11_load0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_load0_re $and$ls180.v:6297$2030_Y + connect \builder_csrbank11_load0_we $and$ls180.v:6298$2034_Y + connect \builder_csrbank11_reload3_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_reload3_re $and$ls180.v:6300$2037_Y + connect \builder_csrbank11_reload3_we $and$ls180.v:6301$2041_Y + connect \builder_csrbank11_reload2_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_reload2_re $and$ls180.v:6303$2044_Y + connect \builder_csrbank11_reload2_we $and$ls180.v:6304$2048_Y + connect \builder_csrbank11_reload1_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_reload1_re $and$ls180.v:6306$2051_Y + connect \builder_csrbank11_reload1_we $and$ls180.v:6307$2055_Y + connect \builder_csrbank11_reload0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_reload0_re $and$ls180.v:6309$2058_Y + connect \builder_csrbank11_reload0_we $and$ls180.v:6310$2062_Y + connect \builder_csrbank11_en0_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_en0_re $and$ls180.v:6312$2065_Y + connect \builder_csrbank11_en0_we $and$ls180.v:6313$2069_Y + connect \builder_csrbank11_update_value0_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_update_value0_re $and$ls180.v:6315$2072_Y + connect \builder_csrbank11_update_value0_we $and$ls180.v:6316$2076_Y + connect \builder_csrbank11_value3_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_value3_re $and$ls180.v:6318$2079_Y + connect \builder_csrbank11_value3_we $and$ls180.v:6319$2083_Y + connect \builder_csrbank11_value2_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_value2_re $and$ls180.v:6321$2086_Y + connect \builder_csrbank11_value2_we $and$ls180.v:6322$2090_Y + connect \builder_csrbank11_value1_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_value1_re $and$ls180.v:6324$2093_Y + connect \builder_csrbank11_value1_we $and$ls180.v:6325$2097_Y + connect \builder_csrbank11_value0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_value0_re $and$ls180.v:6327$2100_Y + connect \builder_csrbank11_value0_we $and$ls180.v:6328$2104_Y + connect \main_libresocsim_eventmanager_status_r \builder_interface11_bank_bus_dat_w [0] + connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6330$2107_Y + connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6331$2111_Y + connect \main_libresocsim_eventmanager_pending_r \builder_interface11_bank_bus_dat_w [0] + connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6333$2114_Y + connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6334$2118_Y + connect \builder_csrbank11_ev_enable0_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_ev_enable0_re $and$ls180.v:6336$2121_Y + connect \builder_csrbank11_ev_enable0_we $and$ls180.v:6337$2125_Y + connect \builder_csrbank11_load3_w \main_libresocsim_load_storage [31:24] + connect \builder_csrbank11_load2_w \main_libresocsim_load_storage [23:16] + connect \builder_csrbank11_load1_w \main_libresocsim_load_storage [15:8] + connect \builder_csrbank11_load0_w \main_libresocsim_load_storage [7:0] + connect \builder_csrbank11_reload3_w \main_libresocsim_reload_storage [31:24] + connect \builder_csrbank11_reload2_w \main_libresocsim_reload_storage [23:16] + connect \builder_csrbank11_reload1_w \main_libresocsim_reload_storage [15:8] + connect \builder_csrbank11_reload0_w \main_libresocsim_reload_storage [7:0] + connect \builder_csrbank11_en0_w \main_libresocsim_en_storage + connect \builder_csrbank11_update_value0_w \main_libresocsim_update_value_storage + connect \builder_csrbank11_value3_w \main_libresocsim_value_status [31:24] + connect \builder_csrbank11_value2_w \main_libresocsim_value_status [23:16] + connect \builder_csrbank11_value1_w \main_libresocsim_value_status [15:8] + connect \builder_csrbank11_value0_w \main_libresocsim_value_status [7:0] + connect \main_libresocsim_value_we \builder_csrbank11_value0_we + connect \builder_csrbank11_ev_enable0_w \main_libresocsim_eventmanager_storage + connect \builder_csrbank12_sel $eq$ls180.v:6354$2126_Y + connect \main_uart_rxtx_r \builder_interface12_bank_bus_dat_w + connect \main_uart_rxtx_re $and$ls180.v:6356$2129_Y + connect \main_uart_rxtx_we $and$ls180.v:6357$2133_Y + connect \builder_csrbank12_txfull_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_txfull_re $and$ls180.v:6359$2136_Y + connect \builder_csrbank12_txfull_we $and$ls180.v:6360$2140_Y + connect \builder_csrbank12_rxempty_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_rxempty_re $and$ls180.v:6362$2143_Y + connect \builder_csrbank12_rxempty_we $and$ls180.v:6363$2147_Y + connect \main_uart_eventmanager_status_r \builder_interface12_bank_bus_dat_w [1:0] + connect \main_uart_eventmanager_status_re $and$ls180.v:6365$2150_Y + connect \main_uart_eventmanager_status_we $and$ls180.v:6366$2154_Y + connect \main_uart_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [1:0] + connect \main_uart_eventmanager_pending_re $and$ls180.v:6368$2157_Y + connect \main_uart_eventmanager_pending_we $and$ls180.v:6369$2161_Y + connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [1:0] + connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6371$2164_Y + connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6372$2168_Y + connect \builder_csrbank12_txempty_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_txempty_re $and$ls180.v:6374$2171_Y + connect \builder_csrbank12_txempty_we $and$ls180.v:6375$2175_Y + connect \builder_csrbank12_rxfull_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_rxfull_re $and$ls180.v:6377$2178_Y + connect \builder_csrbank12_rxfull_we $and$ls180.v:6378$2182_Y + connect \builder_csrbank12_txfull_w \main_uart_txfull_status + connect \main_uart_txfull_we \builder_csrbank12_txfull_we + connect \builder_csrbank12_rxempty_w \main_uart_rxempty_status + connect \main_uart_rxempty_we \builder_csrbank12_rxempty_we + connect \builder_csrbank12_ev_enable0_w \main_uart_eventmanager_storage + connect \builder_csrbank12_txempty_w \main_uart_txempty_status + connect \main_uart_txempty_we \builder_csrbank12_txempty_we + connect \builder_csrbank12_rxfull_w \main_uart_rxfull_status + connect \main_uart_rxfull_we \builder_csrbank12_rxfull_we + connect \builder_csrbank13_sel $eq$ls180.v:6388$2183_Y + connect \builder_csrbank13_tuning_word3_r \builder_interface13_bank_bus_dat_w + connect \builder_csrbank13_tuning_word3_re $and$ls180.v:6390$2186_Y + connect \builder_csrbank13_tuning_word3_we $and$ls180.v:6391$2190_Y + connect \builder_csrbank13_tuning_word2_r \builder_interface13_bank_bus_dat_w + connect \builder_csrbank13_tuning_word2_re $and$ls180.v:6393$2193_Y + connect \builder_csrbank13_tuning_word2_we $and$ls180.v:6394$2197_Y + connect \builder_csrbank13_tuning_word1_r \builder_interface13_bank_bus_dat_w + connect \builder_csrbank13_tuning_word1_re $and$ls180.v:6396$2200_Y + connect \builder_csrbank13_tuning_word1_we $and$ls180.v:6397$2204_Y + connect \builder_csrbank13_tuning_word0_r \builder_interface13_bank_bus_dat_w + connect \builder_csrbank13_tuning_word0_re $and$ls180.v:6399$2207_Y + connect \builder_csrbank13_tuning_word0_we $and$ls180.v:6400$2211_Y + connect \builder_csrbank13_tuning_word3_w \main_storage [31:24] + connect \builder_csrbank13_tuning_word2_w \main_storage [23:16] + connect \builder_csrbank13_tuning_word1_w \main_storage [15:8] + connect \builder_csrbank13_tuning_word0_w \main_storage [7:0] + connect \builder_csr_interconnect_adr \builder_libresocsim_adr + connect \builder_csr_interconnect_we \builder_libresocsim_we + connect \builder_csr_interconnect_dat_w \builder_libresocsim_dat_w + connect \builder_libresocsim_dat_r \builder_csr_interconnect_dat_r + connect \builder_interface0_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface1_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface2_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface3_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface4_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface5_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface6_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface7_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface8_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface9_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface10_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface11_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface12_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface13_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface0_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface1_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface2_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface3_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface4_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface5_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface6_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface7_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface8_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface9_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface10_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface11_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface12_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface13_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface0_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface1_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface2_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface3_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface4_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface5_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface6_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface7_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface8_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface9_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface10_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface11_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface13_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_csr_interconnect_dat_r $or$ls180.v:6451$2224_Y + connect \sdrio_clk \sys_clk_1 + connect \sdrio_clk_1 \sys_clk_1 + connect \sdrio_clk_2 \sys_clk_1 + connect \sdrio_clk_3 \sys_clk_1 + connect \sdrio_clk_4 \sys_clk_1 + connect \sdrio_clk_5 \sys_clk_1 + connect \sdrio_clk_6 \sys_clk_1 + connect \sdrio_clk_7 \sys_clk_1 + connect \sdrio_clk_8 \sys_clk_1 + connect \sdrio_clk_9 \sys_clk_1 + connect \sdrio_clk_10 \sys_clk_1 + connect \sdrio_clk_11 \sys_clk_1 + connect \sdrio_clk_12 \sys_clk_1 + connect \sdrio_clk_13 \sys_clk_1 + connect \sdrio_clk_14 \sys_clk_1 + connect \sdrio_clk_15 \sys_clk_1 + connect \sdrio_clk_16 \sys_clk_1 + connect \sdrio_clk_17 \sys_clk_1 + connect \sdrio_clk_18 \sys_clk_1 + connect \sdrio_clk_19 \sys_clk_1 + connect \sdrio_clk_20 \sys_clk_1 + connect \sdrio_clk_21 \sys_clk_1 + connect \sdrio_clk_22 \sys_clk_1 + connect \sdrio_clk_23 \sys_clk_1 + connect \sdrio_clk_24 \sys_clk_1 + connect \sdrio_clk_25 \sys_clk_1 + connect \sdrio_clk_26 \sys_clk_1 + connect \sdrio_clk_27 \sys_clk_1 + connect \sdrio_clk_28 \sys_clk_1 + connect \sdrio_clk_29 \sys_clk_1 + connect \sdrio_clk_30 \sys_clk_1 + connect \sdrio_clk_31 \sys_clk_1 + connect \sdrio_clk_32 \sys_clk_1 + connect \sdrio_clk_33 \sys_clk_1 + connect \sdrio_clk_34 \sys_clk_1 + connect \sdrio_clk_35 \sys_clk_1 + connect \sdrio_clk_36 \sys_clk_1 + connect \sdrio_clk_37 \sys_clk_1 + connect \sdrio_clk_38 \sys_clk_1 + connect \sdrio_clk_39 \sys_clk_1 + connect \sdrio_clk_40 \sys_clk_1 + connect \sdrio_clk_41 \sys_clk_1 + connect \sdrio_clk_42 \sys_clk_1 + connect \sdrio_clk_43 \sys_clk_1 + connect \sdrio_clk_44 \sys_clk_1 + connect \sdrio_clk_45 \sys_clk_1 + connect \sdrio_clk_46 \sys_clk_1 + connect \sdrio_clk_47 \sys_clk_1 + connect \sdrio_clk_48 \sys_clk_1 + connect \sdrio_clk_49 \sys_clk_1 + connect \sdrio_clk_50 \sys_clk_1 + connect \sdrio_clk_51 \sys_clk_1 + connect \sdrio_clk_52 \sys_clk_1 + connect \sdrio_clk_53 \sys_clk_1 + connect \main_rx \builder_multiregimpl0_regs1 + connect \main_pwm0_enable \main_pwm0_enable_storage + connect \main_pwm0_width \main_pwm0_width_storage + connect \main_pwm0_period \main_pwm0_period_storage + connect \main_pwm1_enable \main_pwm1_enable_storage + connect \main_pwm1_width \main_pwm1_width_storage + connect \main_pwm1_period \main_pwm1_period_storage + connect \sdrio_clk_54 \sys_clk_1 + connect \sdrio_clk_55 \sys_clk_1 + connect \sdrio_clk_56 \sys_clk_1 + connect \sdrio_clk_57 \sys_clk_1 + connect \sdrio_clk_58 \sys_clk_1 + connect \sdrio_clk_59 \sys_clk_1 + connect \sdrio_clk_60 \sys_clk_1 + connect \sdrio_clk_61 \sys_clk_1 + connect \sdrio_clk_62 \sys_clk_1 + connect \sdrio_clk_63 \sys_clk_1 + connect \sdrio_clk_64 \sys_clk_1 + connect \sdrio_clk_65 \sys_clk_1 + connect \sdrio_clk_66 \sys_clk_1 + connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:9993$2697_DATA + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10011$2704_DATA + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10025$2711_DATA + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10039$2718_DATA + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10053$2725_DATA + connect \main_uart_tx_fifo_wrport_dat_r \memdat_4 + connect \main_uart_tx_fifo_rdport_dat_r \memdat_5 + connect \main_uart_rx_fifo_wrport_dat_r \memdat_6 + connect \main_uart_rx_fifo_rdport_dat_r \memdat_7 + connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8 + connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10101$2746_DATA + connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 + connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10115$2753_DATA +end +attribute \src "libresoc.v:44585.1-44669.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick + attribute \src "libresoc.v:44642.17-44642.91" + wire $not$libresoc.v:44642$1361_Y + attribute \src "libresoc.v:44644.18-44644.93" + wire $not$libresoc.v:44644$1363_Y + attribute \src "libresoc.v:44646.18-44646.93" + wire $not$libresoc.v:44646$1365_Y + attribute \src "libresoc.v:44647.17-44647.138" + wire width 8 $not$libresoc.v:44647$1366_Y + attribute \src "libresoc.v:44649.18-44649.93" + wire $not$libresoc.v:44649$1368_Y + attribute \src "libresoc.v:44651.18-44651.93" + wire $not$libresoc.v:44651$1370_Y + attribute \src "libresoc.v:44653.18-44653.93" + wire $not$libresoc.v:44653$1372_Y + attribute \src "libresoc.v:44656.17-44656.91" + wire $not$libresoc.v:44656$1375_Y + attribute \src "libresoc.v:44643.18-44643.116" + wire $reduce_or$libresoc.v:44643$1362_Y + attribute \src "libresoc.v:44645.18-44645.122" + wire $reduce_or$libresoc.v:44645$1364_Y + attribute \src "libresoc.v:44648.18-44648.128" + wire $reduce_or$libresoc.v:44648$1367_Y + attribute \src "libresoc.v:44650.18-44650.134" + wire $reduce_or$libresoc.v:44650$1369_Y + attribute \src "libresoc.v:44652.18-44652.140" + wire $reduce_or$libresoc.v:44652$1371_Y + attribute \src "libresoc.v:44654.18-44654.90" + wire $reduce_or$libresoc.v:44654$1373_Y + attribute \src "libresoc.v:44655.17-44655.103" + wire $reduce_or$libresoc.v:44655$1374_Y + attribute \src "libresoc.v:44657.17-44657.109" + wire $reduce_or$libresoc.v:44657$1376_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44642$1361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:44642$1361_Y end - attribute \src "issuer_ls180.v:177535.3-177536.49" - process $proc$issuer_ls180.v:177535$12537 - assign { } { } - assign $0\core_core_cr_in2[2:0] \core_core_cr_in2$next - sync posedge \clk - update \core_core_cr_in2 $0\core_core_cr_in2[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44644$1363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:44644$1363_Y end - attribute \src "issuer_ls180.v:177537.3-177538.55" - process $proc$issuer_ls180.v:177537$12538 - assign { } { } - assign $0\core_core_cr_in2_ok[0:0] \core_core_cr_in2_ok$next - sync posedge \clk - update \core_core_cr_in2_ok $0\core_core_cr_in2_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44646$1365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:44646$1365_Y end - attribute \src "issuer_ls180.v:177539.3-177540.55" - process $proc$issuer_ls180.v:177539$12539 - assign { } { } - assign $0\core_core_cr_in2$1[2:0]$12540 \core_core_cr_in2$1$next - sync posedge \clk - update \core_core_cr_in2$1 $0\core_core_cr_in2$1[2:0]$12540 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:44647$1366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:44647$1366_Y end - attribute \src "issuer_ls180.v:177541.3-177542.61" - process $proc$issuer_ls180.v:177541$12541 - assign { } { } - assign $0\core_core_cr_in2_ok$2[0:0]$12542 \core_core_cr_in2_ok$2$next - sync posedge \clk - update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$12542 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44649$1368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:44649$1368_Y end - attribute \src "issuer_ls180.v:177543.3-177544.49" - process $proc$issuer_ls180.v:177543$12543 - assign { } { } - assign $0\core_core_cr_out[2:0] \core_core_cr_out$next - sync posedge \clk - update \core_core_cr_out $0\core_core_cr_out[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44651$1370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:44651$1370_Y end - attribute \src "issuer_ls180.v:177545.3-177546.45" - process $proc$issuer_ls180.v:177545$12544 - assign { } { } - assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next - sync posedge \clk - update \core_cr_out_ok $0\core_cr_out_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44653$1372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:44653$1372_Y end - attribute \src "issuer_ls180.v:177547.3-177548.39" - process $proc$issuer_ls180.v:177547$12545 - assign { } { } - assign $0\d_reg_delay[0:0] \d_reg_delay$next - sync posedge \clk - update \d_reg_delay $0\d_reg_delay[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44656$1375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:44656$1375_Y end - attribute \src "issuer_ls180.v:177549.3-177550.53" - process $proc$issuer_ls180.v:177549$12546 - assign { } { } - assign $0\core_core_core_msr[63:0] \core_core_core_msr$next - sync posedge \clk - update \core_core_core_msr $0\core_core_core_msr[63:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44643$1362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:44643$1362_Y end - attribute \src "issuer_ls180.v:177551.3-177552.53" - process $proc$issuer_ls180.v:177551$12547 - assign { } { } - assign $0\core_core_core_cia[63:0] \core_core_core_cia$next - sync posedge \clk - update \core_core_core_cia $0\core_core_core_cia[63:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44645$1364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:44645$1364_Y end - attribute \src "issuer_ls180.v:177553.3-177554.55" - process $proc$issuer_ls180.v:177553$12548 - assign { } { } - assign $0\core_core_core_insn[31:0] \core_core_core_insn$next - sync posedge \clk - update \core_core_core_insn $0\core_core_core_insn[31:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44648$1367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:44648$1367_Y end - attribute \src "issuer_ls180.v:177555.3-177556.65" - process $proc$issuer_ls180.v:177555$12549 - assign { } { } - assign $0\core_core_core_insn_type[6:0] \core_core_core_insn_type$next - sync posedge \clk - update \core_core_core_insn_type $0\core_core_core_insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44650$1369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:44650$1369_Y end - attribute \src "issuer_ls180.v:177557.3-177558.61" - process $proc$issuer_ls180.v:177557$12550 - assign { } { } - assign $0\core_core_core_fn_unit[11:0] \core_core_core_fn_unit$next - sync posedge \clk - update \core_core_core_fn_unit $0\core_core_core_fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44652$1371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:44652$1371_Y end - attribute \src "issuer_ls180.v:177559.3-177560.41" - process $proc$issuer_ls180.v:177559$12551 - assign { } { } - assign $0\core_core_lk[0:0] \core_core_lk$next - sync posedge \clk - update \core_core_lk $0\core_core_lk[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:44654$1373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:44654$1373_Y end - attribute \src "issuer_ls180.v:177561.3-177562.51" - process $proc$issuer_ls180.v:177561$12552 - assign { } { } - assign $0\core_core_core_rc[0:0] \core_core_core_rc$next - sync posedge \clk - update \core_core_core_rc $0\core_core_core_rc[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44655$1374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:44655$1374_Y end - attribute \src "issuer_ls180.v:177563.3-177564.57" - process $proc$issuer_ls180.v:177563$12553 - assign { } { } - assign $0\core_core_core_rc_ok[0:0] \core_core_core_rc_ok$next - sync posedge \clk - update \core_core_core_rc_ok $0\core_core_core_rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44657$1376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:44657$1376_Y + end + connect \$7 $not$libresoc.v:44642$1361_Y + connect \$12 $reduce_or$libresoc.v:44643$1362_Y + connect \$11 $not$libresoc.v:44644$1363_Y + connect \$16 $reduce_or$libresoc.v:44645$1364_Y + connect \$15 $not$libresoc.v:44646$1365_Y + connect \$1 $not$libresoc.v:44647$1366_Y + connect \$20 $reduce_or$libresoc.v:44648$1367_Y + connect \$19 $not$libresoc.v:44649$1368_Y + connect \$24 $reduce_or$libresoc.v:44650$1369_Y + connect \$23 $not$libresoc.v:44651$1370_Y + connect \$28 $reduce_or$libresoc.v:44652$1371_Y + connect \$27 $not$libresoc.v:44653$1372_Y + connect \$31 $reduce_or$libresoc.v:44654$1373_Y + connect \$4 $reduce_or$libresoc.v:44655$1374_Y + connect \$3 $not$libresoc.v:44656$1375_Y + connect \$8 $reduce_or$libresoc.v:44657$1376_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:44673.1-44757.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$1 + attribute \src "libresoc.v:44730.17-44730.91" + wire $not$libresoc.v:44730$1377_Y + attribute \src "libresoc.v:44732.18-44732.93" + wire $not$libresoc.v:44732$1379_Y + attribute \src "libresoc.v:44734.18-44734.93" + wire $not$libresoc.v:44734$1381_Y + attribute \src "libresoc.v:44735.17-44735.138" + wire width 8 $not$libresoc.v:44735$1382_Y + attribute \src "libresoc.v:44737.18-44737.93" + wire $not$libresoc.v:44737$1384_Y + attribute \src "libresoc.v:44739.18-44739.93" + wire $not$libresoc.v:44739$1386_Y + attribute \src "libresoc.v:44741.18-44741.93" + wire $not$libresoc.v:44741$1388_Y + attribute \src "libresoc.v:44744.17-44744.91" + wire $not$libresoc.v:44744$1391_Y + attribute \src "libresoc.v:44731.18-44731.116" + wire $reduce_or$libresoc.v:44731$1378_Y + attribute \src "libresoc.v:44733.18-44733.122" + wire $reduce_or$libresoc.v:44733$1380_Y + attribute \src "libresoc.v:44736.18-44736.128" + wire $reduce_or$libresoc.v:44736$1383_Y + attribute \src "libresoc.v:44738.18-44738.134" + wire $reduce_or$libresoc.v:44738$1385_Y + attribute \src "libresoc.v:44740.18-44740.140" + wire $reduce_or$libresoc.v:44740$1387_Y + attribute \src "libresoc.v:44742.18-44742.90" + wire $reduce_or$libresoc.v:44742$1389_Y + attribute \src "libresoc.v:44743.17-44743.103" + wire $reduce_or$libresoc.v:44743$1390_Y + attribute \src "libresoc.v:44745.17-44745.109" + wire $reduce_or$libresoc.v:44745$1392_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44730$1377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:44730$1377_Y end - attribute \src "issuer_ls180.v:177565.3-177566.51" - process $proc$issuer_ls180.v:177565$12554 - assign { } { } - assign $0\core_core_core_oe[0:0] \core_core_core_oe$next - sync posedge \clk - update \core_core_core_oe $0\core_core_core_oe[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44732$1379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:44732$1379_Y end - attribute \src "issuer_ls180.v:177567.3-177568.57" - process $proc$issuer_ls180.v:177567$12555 - assign { } { } - assign $0\core_core_core_oe_ok[0:0] \core_core_core_oe_ok$next - sync posedge \clk - update \core_core_core_oe_ok $0\core_core_core_oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44734$1381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:44734$1381_Y end - attribute \src "issuer_ls180.v:177569.3-177570.29" - process $proc$issuer_ls180.v:177569$12556 - assign { } { } - assign $0\ilatch[31:0] \ilatch$next - sync posedge \clk - update \ilatch $0\ilatch[31:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:44735$1382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:44735$1382_Y end - attribute \src "issuer_ls180.v:177571.3-177572.69" - process $proc$issuer_ls180.v:177571$12557 - assign { } { } - assign $0\core_core_core_input_carry[1:0] \core_core_core_input_carry$next - sync posedge \clk - update \core_core_core_input_carry $0\core_core_core_input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44737$1384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:44737$1384_Y end - attribute \src "issuer_ls180.v:177573.3-177574.63" - process $proc$issuer_ls180.v:177573$12558 - assign { } { } - assign $0\core_core_core_traptype[6:0] \core_core_core_traptype$next - sync posedge \clk - update \core_core_core_traptype $0\core_core_core_traptype[6:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44739$1386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:44739$1386_Y end - attribute \src "issuer_ls180.v:177575.3-177576.63" - process $proc$issuer_ls180.v:177575$12559 - assign { } { } - assign $0\core_core_core_trapaddr[12:0] \core_core_core_trapaddr$next - sync posedge \clk - update \core_core_core_trapaddr $0\core_core_core_trapaddr[12:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44741$1388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:44741$1388_Y end - attribute \src "issuer_ls180.v:177577.3-177578.57" - process $proc$issuer_ls180.v:177577$12560 - assign { } { } - assign $0\core_core_core_cr_rd[7:0] \core_core_core_cr_rd$next - sync posedge \clk - update \core_core_core_cr_rd $0\core_core_core_cr_rd[7:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:44744$1391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:44744$1391_Y end - attribute \src "issuer_ls180.v:177579.3-177580.63" - process $proc$issuer_ls180.v:177579$12561 - assign { } { } - assign $0\core_core_core_cr_rd_ok[0:0] \core_core_core_cr_rd_ok$next - sync posedge \clk - update \core_core_core_cr_rd_ok $0\core_core_core_cr_rd_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44731$1378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:44731$1378_Y end - attribute \src "issuer_ls180.v:177581.3-177582.57" - process $proc$issuer_ls180.v:177581$12562 - assign { } { } - assign $0\core_core_core_cr_wr[7:0] \core_core_core_cr_wr$next - sync posedge \clk - update \core_core_core_cr_wr $0\core_core_core_cr_wr[7:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44733$1380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:44733$1380_Y end - attribute \src "issuer_ls180.v:177583.3-177584.53" - process $proc$issuer_ls180.v:177583$12563 - assign { } { } - assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next - sync posedge \clk - update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44736$1383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:44736$1383_Y end - attribute \src "issuer_ls180.v:177585.3-177586.63" - process $proc$issuer_ls180.v:177585$12564 - assign { } { } - assign $0\core_core_core_is_32bit[0:0] \core_core_core_is_32bit$next - sync posedge \clk - update \core_core_core_is_32bit $0\core_core_core_is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44738$1385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:44738$1385_Y end - attribute \src "issuer_ls180.v:177587.3-177588.37" - process $proc$issuer_ls180.v:177587$12565 - assign { } { } - assign $0\pc_changed[0:0] \pc_changed$next - sync posedge \clk - update \pc_changed $0\pc_changed[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44740$1387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:44740$1387_Y end - attribute \src "issuer_ls180.v:177589.3-177590.39" - process $proc$issuer_ls180.v:177589$12566 - assign { } { } - assign $0\pc_ok_delay[0:0] \pc_ok_delay$next - sync posedge \clk - update \pc_ok_delay $0\pc_ok_delay[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:44742$1389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:44742$1389_Y end - attribute \src "issuer_ls180.v:177591.3-177592.41" - process $proc$issuer_ls180.v:177591$12567 - assign { } { } - assign $0\core_core_pc[63:0] \core_core_pc$next - sync posedge \clk - update \core_core_pc $0\core_core_pc[63:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44743$1390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:44743$1390_Y end - attribute \src "issuer_ls180.v:177593.3-177594.43" - process $proc$issuer_ls180.v:177593$12568 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:44745$1392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:44745$1392_Y + end + connect \$7 $not$libresoc.v:44730$1377_Y + connect \$12 $reduce_or$libresoc.v:44731$1378_Y + connect \$11 $not$libresoc.v:44732$1379_Y + connect \$16 $reduce_or$libresoc.v:44733$1380_Y + connect \$15 $not$libresoc.v:44734$1381_Y + connect \$1 $not$libresoc.v:44735$1382_Y + connect \$20 $reduce_or$libresoc.v:44736$1383_Y + connect \$19 $not$libresoc.v:44737$1384_Y + connect \$24 $reduce_or$libresoc.v:44738$1385_Y + connect \$23 $not$libresoc.v:44739$1386_Y + connect \$28 $reduce_or$libresoc.v:44740$1387_Y + connect \$27 $not$libresoc.v:44741$1388_Y + connect \$31 $reduce_or$libresoc.v:44742$1389_Y + connect \$4 $reduce_or$libresoc.v:44743$1390_Y + connect \$3 $not$libresoc.v:44744$1391_Y + connect \$8 $reduce_or$libresoc.v:44745$1392_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:44761.1-45576.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_a.sprmap" +attribute \generator "nMigen" +module \sprmap + attribute \src "libresoc.v:44888.3-44918.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:44919.3-44949.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:44762.7-44762.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:44950.3-45262.6" + wire width 10 $0\spr_o[9:0] + attribute \src "libresoc.v:45263.3-45575.6" + wire $0\spr_o_ok[0:0] + attribute \src "libresoc.v:44888.3-44918.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:44919.3-44949.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:44950.3-45262.6" + wire width 10 $1\spr_o[9:0] + attribute \src "libresoc.v:45263.3-45575.6" + wire $1\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 3 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \fast_o_ok + attribute \src "libresoc.v:44762.7-44762.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" + wire width 10 input 5 \spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 output 1 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \spr_o_ok + attribute \src "libresoc.v:44762.7-44762.20" + process $proc$libresoc.v:44762$1397 assign { } { } - assign $0\cu_st__rel_o_dly[0:0] \core_cu_st__rel_o - sync posedge \clk - update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "issuer_ls180.v:177595.3-177596.27" - process $proc$issuer_ls180.v:177595$12569 + attribute \src "libresoc.v:44888.3-44918.6" + process $proc$libresoc.v:44888$1393 assign { } { } - assign $0\delay[1:0] \delay$next - sync posedge \por_clk - update \delay $0\delay[1:0] - end - attribute \src "issuer_ls180.v:177597.3-177598.43" - process $proc$issuer_ls180.v:177597$12570 assign { } { } - assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next - sync posedge \clk - update \dec2_cur_eint $0\dec2_cur_eint[0:0] + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "libresoc.v:44889.5-44889.29" + switch \initial + attribute \src "libresoc.v:44889.9-44889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o[2:0] 3'111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o[2:0] 3'010 + case + assign $1\fast_o[2:0] 3'000 + end + sync always + update \fast_o $0\fast_o[2:0] end - attribute \src "issuer_ls180.v:177599.3-177600.33" - process $proc$issuer_ls180.v:177599$12571 + attribute \src "libresoc.v:44919.3-44949.6" + process $proc$libresoc.v:44919$1394 assign { } { } - assign $0\core_msr[63:0] \core_msr$next - sync posedge \clk - update \core_msr $0\core_msr[63:0] - end - attribute \src "issuer_ls180.v:177601.3-177602.35" - process $proc$issuer_ls180.v:177601$12572 assign { } { } - assign $0\core_eint[0:0] \core_eint$next - sync posedge \clk - update \core_eint $0\core_eint[0:0] + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "libresoc.v:44920.5-44920.29" + switch \initial + attribute \src "libresoc.v:44920.9-44920.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + case + assign $1\fast_o_ok[0:0] 1'0 + end + sync always + update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "issuer_ls180.v:177818.3-177827.6" - process $proc$issuer_ls180.v:177818$12573 + attribute \src "libresoc.v:44950.3-45262.6" + process $proc$libresoc.v:44950$1395 assign { } { } assign { } { } - assign $0\core_full_rd2__ren[7:0] $1\core_full_rd2__ren[7:0] - attribute \src "issuer_ls180.v:177819.5-177819.29" + assign $0\spr_o[9:0] $1\spr_o[9:0] + attribute \src "libresoc.v:44951.5-44951.29" switch \initial - attribute \src "issuer_ls180.v:177819.9-177819.17" + attribute \src "libresoc.v:44951.9-44951.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" - switch \dbg_d_cr_req - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o[9:0] 10'0000010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0000101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000101101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o[9:0] 10'0000101110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o[9:0] 10'0000101111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000110001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o[9:0] 10'0000110010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o[9:0] 10'0000110100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000110101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o[9:0] 10'0000111000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000111010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000111011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000111100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000111101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000111110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o[9:0] 10'0001000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001000010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0001000011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o[9:0] 10'0001000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o[9:0] 10'0001000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o[9:0] 10'0001000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o[9:0] 10'0001000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o[9:0] 10'0001001001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o[9:0] 10'0001001010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0001001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o[9:0] 10'0001001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0001001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o[9:0] 10'0001010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o[9:0] 10'0001010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o[9:0] 10'0001010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0001011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o[9:0] 10'0001011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o[9:0] 10'0001011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o[9:0] 10'0001011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o[9:0] 10'0001011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o[9:0] 10'0001011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o[9:0] 10'0001100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 assign { } { } - assign $1\core_full_rd2__ren[7:0] 8'11111111 - case - assign $1\core_full_rd2__ren[7:0] 8'00000000 - end - sync always - update \core_full_rd2__ren $0\core_full_rd2__ren[7:0] - end - attribute \src "issuer_ls180.v:177828.3-177836.6" - process $proc$issuer_ls180.v:177828$12574 - assign { } { } - assign { } { } - assign $0\d_cr_delay$next[0:0]$12575 $1\d_cr_delay$next[0:0]$12576 - attribute \src "issuer_ls180.v:177829.5-177829.29" - switch \initial - attribute \src "issuer_ls180.v:177829.9-177829.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o[9:0] 10'0001100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 assign { } { } - assign $1\d_cr_delay$next[0:0]$12576 1'0 - case - assign $1\d_cr_delay$next[0:0]$12576 \dbg_d_cr_req - end - sync always - update \d_cr_delay$next $0\d_cr_delay$next[0:0]$12575 - end - attribute \src "issuer_ls180.v:177837.3-177846.6" - process $proc$issuer_ls180.v:177837$12577 - assign { } { } - assign { } { } - assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] - attribute \src "issuer_ls180.v:177838.5-177838.29" - switch \initial - attribute \src "issuer_ls180.v:177838.9-177838.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314" - switch \d_cr_delay - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o[9:0] 10'0001100010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 assign { } { } - assign $1\dbg_d_cr_data[63:0] \$113 - case - assign $1\dbg_d_cr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] - end - attribute \src "issuer_ls180.v:177847.3-177856.6" - process $proc$issuer_ls180.v:177847$12578 - assign { } { } - assign { } { } - assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] - attribute \src "issuer_ls180.v:177848.5-177848.29" - switch \initial - attribute \src "issuer_ls180.v:177848.9-177848.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314" - switch \d_cr_delay - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o[9:0] 10'0001100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 assign { } { } - assign $1\dbg_d_cr_ack[0:0] 1'1 - case - assign $1\dbg_d_cr_ack[0:0] 1'0 - end - sync always - update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] - end - attribute \src "issuer_ls180.v:177857.3-177866.6" - process $proc$issuer_ls180.v:177857$12579 - assign { } { } - assign { } { } - assign $0\core_full_rd__ren[2:0] $1\core_full_rd__ren[2:0] - attribute \src "issuer_ls180.v:177858.5-177858.29" - switch \initial - attribute \src "issuer_ls180.v:177858.9-177858.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" - switch \dbg_d_xer_req - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o[9:0] 10'0001100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 assign { } { } - assign $1\core_full_rd__ren[2:0] 3'111 - case - assign $1\core_full_rd__ren[2:0] 3'000 - end - sync always - update \core_full_rd__ren $0\core_full_rd__ren[2:0] - end - attribute \src "issuer_ls180.v:177867.3-177875.6" - process $proc$issuer_ls180.v:177867$12580 - assign { } { } - assign { } { } - assign $0\d_xer_delay$next[0:0]$12581 $1\d_xer_delay$next[0:0]$12582 - attribute \src "issuer_ls180.v:177868.5-177868.29" - switch \initial - attribute \src "issuer_ls180.v:177868.9-177868.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o[9:0] 10'0001100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 assign { } { } - assign $1\d_xer_delay$next[0:0]$12582 1'0 - case - assign $1\d_xer_delay$next[0:0]$12582 \dbg_d_xer_req - end - sync always - update \d_xer_delay$next $0\d_xer_delay$next[0:0]$12581 - end - attribute \src "issuer_ls180.v:177876.3-177885.6" - process $proc$issuer_ls180.v:177876$12583 - assign { } { } - assign { } { } - assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] - attribute \src "issuer_ls180.v:177877.5-177877.29" - switch \initial - attribute \src "issuer_ls180.v:177877.9-177877.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:324" - switch \d_xer_delay - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o[9:0] 10'0001100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 assign { } { } - assign $1\dbg_d_xer_data[63:0] \$115 - case - assign $1\dbg_d_xer_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] - end - attribute \src "issuer_ls180.v:177886.3-177895.6" - process $proc$issuer_ls180.v:177886$12584 - assign { } { } - assign { } { } - assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] - attribute \src "issuer_ls180.v:177887.5-177887.29" - switch \initial - attribute \src "issuer_ls180.v:177887.9-177887.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:324" - switch \d_xer_delay - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o[9:0] 10'0001101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 assign { } { } - assign $1\dbg_d_xer_ack[0:0] 1'1 - case - assign $1\dbg_d_xer_ack[0:0] 1'0 - end - sync always - update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] - end - attribute \src "issuer_ls180.v:177896.3-177910.6" - process $proc$issuer_ls180.v:177896$12585 - assign { } { } - assign { } { } - assign $0\core_issue__addr[2:0] $1\core_issue__addr[2:0] - attribute \src "issuer_ls180.v:177897.5-177897.29" - switch \initial - attribute \src "issuer_ls180.v:177897.9-177897.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" - switch \fsm_state$117 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\spr_o[9:0] 10'0001101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 assign { } { } - assign $1\core_issue__addr[2:0] 3'110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 + assign $1\spr_o[9:0] 10'0001101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 assign { } { } - assign $1\core_issue__addr[2:0] 3'111 - case - assign $1\core_issue__addr[2:0] 3'000 - end - sync always - update \core_issue__addr $0\core_issue__addr[2:0] - end - attribute \src "issuer_ls180.v:177911.3-177925.6" - process $proc$issuer_ls180.v:177911$12586 - assign { } { } - assign { } { } - assign $0\core_issue__ren[0:0] $1\core_issue__ren[0:0] - attribute \src "issuer_ls180.v:177912.5-177912.29" - switch \initial - attribute \src "issuer_ls180.v:177912.9-177912.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" - switch \fsm_state$117 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\spr_o[9:0] 10'0001101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 assign { } { } - assign $1\core_issue__ren[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 + assign $1\spr_o[9:0] 10'0001101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 assign { } { } - assign $1\core_issue__ren[0:0] 1'1 + assign $1\spr_o[9:0] 10'0001101101 case - assign $1\core_issue__ren[0:0] 1'0 + assign $1\spr_o[9:0] 10'0000000000 end sync always - update \core_issue__ren $0\core_issue__ren[0:0] + update \spr_o $0\spr_o[9:0] end - attribute \src "issuer_ls180.v:177926.3-177953.6" - process $proc$issuer_ls180.v:177926$12587 + attribute \src "libresoc.v:45263.3-45575.6" + process $proc$libresoc.v:45263$1396 assign { } { } assign { } { } - assign { } { } - assign $0\fsm_state$117$next[1:0]$12588 $2\fsm_state$117$next[1:0]$12590 - attribute \src "issuer_ls180.v:177927.5-177927.29" + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:45264.5-45264.29" switch \initial - attribute \src "issuer_ls180.v:177927.9-177927.17" + attribute \src "libresoc.v:45264.9-45264.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" - switch \fsm_state$117 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 assign { } { } - assign $1\fsm_state$117$next[1:0]$12589 2'01 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 assign { } { } - assign $1\fsm_state$117$next[1:0]$12589 2'10 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 assign { } { } - assign $1\fsm_state$117$next[1:0]$12589 2'11 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'11 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 assign { } { } - assign $1\fsm_state$117$next[1:0]$12589 2'00 - case - assign $1\fsm_state$117$next[1:0]$12589 \fsm_state$117 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 assign { } { } - assign $2\fsm_state$117$next[1:0]$12590 2'00 - case - assign $2\fsm_state$117$next[1:0]$12590 $1\fsm_state$117$next[1:0]$12589 - end - sync always - update \fsm_state$117$next $0\fsm_state$117$next[1:0]$12588 - end - attribute \src "issuer_ls180.v:177954.3-177964.6" - process $proc$issuer_ls180.v:177954$12591 - assign { } { } - assign { } { } - assign $0\new_dec[63:0] $1\new_dec[63:0] - attribute \src "issuer_ls180.v:177955.5-177955.29" - switch \initial - attribute \src "issuer_ls180.v:177955.9-177955.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" - switch \fsm_state$117 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 assign { } { } - assign $1\new_dec[63:0] \$118 [63:0] - case - assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \new_dec $0\new_dec[63:0] - end - attribute \src "issuer_ls180.v:177965.3-177979.6" - process $proc$issuer_ls180.v:177965$12592 - assign { } { } - assign { } { } - assign $0\core_issue__addr$4[2:0]$12593 $1\core_issue__addr$4[2:0]$12594 - attribute \src "issuer_ls180.v:177966.5-177966.29" - switch \initial - attribute \src "issuer_ls180.v:177966.9-177966.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" - switch \fsm_state$117 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 assign { } { } - assign $1\core_issue__addr$4[2:0]$12594 3'110 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'11 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 assign { } { } - assign $1\core_issue__addr$4[2:0]$12594 3'111 - case - assign $1\core_issue__addr$4[2:0]$12594 3'000 - end - sync always - update \core_issue__addr$4 $0\core_issue__addr$4[2:0]$12593 - end - attribute \src "issuer_ls180.v:177980.3-177994.6" - process $proc$issuer_ls180.v:177980$12595 - assign { } { } - assign { } { } - assign $0\core_issue__wen[0:0] $1\core_issue__wen[0:0] - attribute \src "issuer_ls180.v:177981.5-177981.29" - switch \initial - attribute \src "issuer_ls180.v:177981.9-177981.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" - switch \fsm_state$117 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 assign { } { } - assign $1\core_issue__wen[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'11 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 assign { } { } - assign $1\core_issue__wen[0:0] 1'1 - case - assign $1\core_issue__wen[0:0] 1'0 - end - sync always - update \core_issue__wen $0\core_issue__wen[0:0] - end - attribute \src "issuer_ls180.v:177995.3-178009.6" - process $proc$issuer_ls180.v:177995$12596 - assign { } { } - assign { } { } - assign $0\core_issue__data_i[63:0] $1\core_issue__data_i[63:0] - attribute \src "issuer_ls180.v:177996.5-177996.29" - switch \initial - attribute \src "issuer_ls180.v:177996.9-177996.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" - switch \fsm_state$117 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign $1\core_issue__data_i[63:0] \new_dec - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'11 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 assign { } { } - assign $1\core_issue__data_i[63:0] \new_tb - case - assign $1\core_issue__data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \core_issue__data_i $0\core_issue__data_i[63:0] - end - attribute \src "issuer_ls180.v:178010.3-178025.6" - process $proc$issuer_ls180.v:178010$12597 - assign { } { } - assign { } { } - assign { } { } - assign $0\dec2_cur_dec$next[63:0]$12598 $2\dec2_cur_dec$next[63:0]$12600 - attribute \src "issuer_ls180.v:178011.5-178011.29" - switch \initial - attribute \src "issuer_ls180.v:178011.9-178011.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" - switch \fsm_state$117 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 assign { } { } - assign $1\dec2_cur_dec$next[63:0]$12599 \new_dec - case - assign $1\dec2_cur_dec$next[63:0]$12599 \dec2_cur_dec - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 assign { } { } - assign $2\dec2_cur_dec$next[63:0]$12600 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\dec2_cur_dec$next[63:0]$12600 $1\dec2_cur_dec$next[63:0]$12599 - end - sync always - update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$12598 - end - attribute \src "issuer_ls180.v:178026.3-178036.6" - process $proc$issuer_ls180.v:178026$12601 - assign { } { } - assign { } { } - assign $0\new_tb[63:0] $1\new_tb[63:0] - attribute \src "issuer_ls180.v:178027.5-178027.29" - switch \initial - attribute \src "issuer_ls180.v:178027.9-178027.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" - switch \fsm_state$117 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'11 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 assign { } { } - assign $1\new_tb[63:0] \$121 [63:0] - case - assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \new_tb $0\new_tb[63:0] - end - attribute \src "issuer_ls180.v:178037.3-178045.6" - process $proc$issuer_ls180.v:178037$12602 - assign { } { } - assign { } { } - assign $0\pc_ok_delay$next[0:0]$12603 $1\pc_ok_delay$next[0:0]$12604 - attribute \src "issuer_ls180.v:178038.5-178038.29" - switch \initial - attribute \src "issuer_ls180.v:178038.9-178038.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 assign { } { } - assign $1\pc_ok_delay$next[0:0]$12604 1'0 - case - assign $1\pc_ok_delay$next[0:0]$12604 \$23 - end - sync always - update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$12603 - end - attribute \src "issuer_ls180.v:178046.3-178061.6" - process $proc$issuer_ls180.v:178046$12605 - assign { } { } - assign { } { } - assign { } { } - assign $0\pc[63:0] $2\pc[63:0] - attribute \src "issuer_ls180.v:178047.5-178047.29" - switch \initial - attribute \src "issuer_ls180.v:178047.9-178047.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:176" - switch \pc_i_ok - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 assign { } { } - assign $1\pc[63:0] \pc_i - case - assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:183" - switch \pc_ok_delay - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 assign { } { } - assign $2\pc[63:0] \core_cia__data_o - case - assign $2\pc[63:0] $1\pc[63:0] - end - sync always - update \pc $0\pc[63:0] - end - attribute \src "issuer_ls180.v:178062.3-178074.6" - process $proc$issuer_ls180.v:178062$12606 - assign { } { } - assign { } { } - assign $0\core_cia__ren[3:0] $1\core_cia__ren[3:0] - attribute \src "issuer_ls180.v:178063.5-178063.29" - switch \initial - attribute \src "issuer_ls180.v:178063.9-178063.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:176" - switch \pc_i_ok - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign $1\core_cia__ren[3:0] 4'0000 - attribute \src "issuer_ls180.v:0.0-0.0" - case + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 assign { } { } - assign $1\core_cia__ren[3:0] 4'0001 - end - sync always - update \core_cia__ren $0\core_cia__ren[3:0] - end - attribute \src "issuer_ls180.v:178075.3-178095.6" - process $proc$issuer_ls180.v:178075$12607 - assign { } { } - assign { } { } - assign $0\core_wen[3:0] $1\core_wen[3:0] - attribute \src "issuer_ls180.v:178076.5-178076.29" - switch \initial - attribute \src "issuer_ls180.v:178076.9-178076.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" - switch \fsm_state - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'11 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 assign { } { } - assign $1\core_wen[3:0] $2\core_wen[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" - switch \$25 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\core_wen[3:0] $3\core_wen[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:284" - switch \$27 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\core_wen[3:0] 4'0001 - case - assign $3\core_wen[3:0] 4'0000 - end - case - assign $2\core_wen[3:0] 4'0000 - end - case - assign $1\core_wen[3:0] 4'0000 - end - sync always - update \core_wen $0\core_wen[3:0] - end - attribute \src "issuer_ls180.v:178096.3-178116.6" - process $proc$issuer_ls180.v:178096$12608 - assign { } { } - assign { } { } - assign $0\core_data_i[63:0] $1\core_data_i[63:0] - attribute \src "issuer_ls180.v:178097.5-178097.29" - switch \initial - attribute \src "issuer_ls180.v:178097.9-178097.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" - switch \fsm_state - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'11 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 assign { } { } - assign $1\core_data_i[63:0] $2\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" - switch \$29 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\core_data_i[63:0] $3\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:284" - switch \$31 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\core_data_i[63:0] \nia - case - assign $3\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $2\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 case - assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\spr_o_ok[0:0] 1'0 end sync always - update \core_data_i $0\core_data_i[63:0] + update \spr_o_ok $0\spr_o_ok[0:0] end - attribute \src "issuer_ls180.v:178117.3-178125.6" - process $proc$issuer_ls180.v:178117$12609 - assign { } { } +end +attribute \src "libresoc.v:45580.1-46395.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_o.sprmap" +attribute \generator "nMigen" +module \sprmap$2 + attribute \src "libresoc.v:45707.3-45737.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:45738.3-45768.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:45581.7-45581.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:45769.3-46081.6" + wire width 10 $0\spr_o[9:0] + attribute \src "libresoc.v:46082.3-46394.6" + wire $0\spr_o_ok[0:0] + attribute \src "libresoc.v:45707.3-45737.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:45738.3-45768.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:45769.3-46081.6" + wire width 10 $1\spr_o[9:0] + attribute \src "libresoc.v:46082.3-46394.6" + wire $1\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 3 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \fast_o_ok + attribute \src "libresoc.v:45581.7-45581.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" + wire width 10 input 5 \spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 output 1 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \spr_o_ok + attribute \src "libresoc.v:45581.7-45581.20" + process $proc$libresoc.v:45581$1402 assign { } { } - assign $0\dec2_cur_eint$next[0:0]$12610 $1\dec2_cur_eint$next[0:0]$12611 - attribute \src "issuer_ls180.v:178118.5-178118.29" - switch \initial - attribute \src "issuer_ls180.v:178118.9-178118.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dec2_cur_eint$next[0:0]$12611 1'0 - case - assign $1\dec2_cur_eint$next[0:0]$12611 \xics_icp_core_irq_o - end + assign $0\initial[0:0] 1'0 sync always - update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$12610 + update \initial $0\initial[0:0] + sync init end - attribute \src "issuer_ls180.v:178126.3-178141.6" - process $proc$issuer_ls180.v:178126$12612 + attribute \src "libresoc.v:45707.3-45737.6" + process $proc$libresoc.v:45707$1398 assign { } { } assign { } { } - assign $0\core_msr__ren[3:0] $1\core_msr__ren[3:0] - attribute \src "issuer_ls180.v:178127.5-178127.29" + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "libresoc.v:45708.5-45708.29" switch \initial - attribute \src "issuer_ls180.v:178127.9-178127.17" + attribute \src "libresoc.v:45708.9-45708.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" - switch \fsm_state - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 assign { } { } - assign $1\core_msr__ren[3:0] $2\core_msr__ren[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - switch \$37 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\core_msr__ren[3:0] 4'0010 - case - assign $2\core_msr__ren[3:0] 4'0000 - end + assign $1\fast_o[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o[2:0] 3'111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o[2:0] 3'010 case - assign $1\core_msr__ren[3:0] 4'0000 + assign $1\fast_o[2:0] 3'000 end sync always - update \core_msr__ren $0\core_msr__ren[3:0] + update \fast_o $0\fast_o[2:0] end - attribute \src "issuer_ls180.v:178142.3-178166.6" - process $proc$issuer_ls180.v:178142$12613 + attribute \src "libresoc.v:45738.3-45768.6" + process $proc$libresoc.v:45738$1399 assign { } { } assign { } { } - assign { } { } - assign $0\pc_changed$next[0:0]$12614 $3\pc_changed$next[0:0]$12617 - attribute \src "issuer_ls180.v:178143.5-178143.29" + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "libresoc.v:45739.5-45739.29" switch \initial - attribute \src "issuer_ls180.v:178143.9-178143.17" + attribute \src "libresoc.v:45739.9-45739.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" - switch \fsm_state - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 assign { } { } - assign $1\pc_changed$next[0:0]$12615 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'11 + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 assign { } { } - assign $1\pc_changed$next[0:0]$12615 $2\pc_changed$next[0:0]$12616 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" - switch \$39 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\pc_changed$next[0:0]$12616 1'1 - case - assign $2\pc_changed$next[0:0]$12616 \pc_changed - end - case - assign $1\pc_changed$next[0:0]$12615 \pc_changed - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 assign { } { } - assign $3\pc_changed$next[0:0]$12617 1'0 + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 case - assign $3\pc_changed$next[0:0]$12617 $1\pc_changed$next[0:0]$12615 + assign $1\fast_o_ok[0:0] 1'0 end sync always - update \pc_changed$next $0\pc_changed$next[0:0]$12614 + update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "issuer_ls180.v:178167.3-178273.6" - process $proc$issuer_ls180.v:178167$12618 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:45769.3-46081.6" + process $proc$libresoc.v:45769$1400 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\core_asmcode$next[7:0]$12619 $1\core_asmcode$next[7:0]$12670 - assign $0\core_core_core_cia$next[63:0]$12620 $1\core_core_core_cia$next[63:0]$12671 - assign $0\core_core_core_cr_rd$next[7:0]$12621 $1\core_core_core_cr_rd$next[7:0]$12672 - assign { } { } - assign $0\core_core_core_cr_wr$next[7:0]$12623 $1\core_core_core_cr_wr$next[7:0]$12674 - assign $0\core_core_core_fn_unit$next[11:0]$12624 $1\core_core_core_fn_unit$next[11:0]$12675 - assign $0\core_core_core_input_carry$next[1:0]$12625 $1\core_core_core_input_carry$next[1:0]$12676 - assign $0\core_core_core_insn$next[31:0]$12626 $1\core_core_core_insn$next[31:0]$12677 - assign $0\core_core_core_insn_type$next[6:0]$12627 $1\core_core_core_insn_type$next[6:0]$12678 - assign $0\core_core_core_is_32bit$next[0:0]$12628 $1\core_core_core_is_32bit$next[0:0]$12679 - assign $0\core_core_core_msr$next[63:0]$12629 $1\core_core_core_msr$next[63:0]$12680 - assign $0\core_core_core_oe$next[0:0]$12630 $1\core_core_core_oe$next[0:0]$12681 - assign { } { } - assign $0\core_core_core_rc$next[0:0]$12632 $1\core_core_core_rc$next[0:0]$12683 - assign { } { } - assign $0\core_core_core_trapaddr$next[12:0]$12634 $1\core_core_core_trapaddr$next[12:0]$12685 - assign $0\core_core_core_traptype$next[6:0]$12635 $1\core_core_core_traptype$next[6:0]$12686 - assign $0\core_core_cr_in1$next[2:0]$12636 $1\core_core_cr_in1$next[2:0]$12687 - assign { } { } - assign $0\core_core_cr_in2$1$next[2:0]$12638 $1\core_core_cr_in2$1$next[2:0]$12689 - assign $0\core_core_cr_in2$next[2:0]$12639 $1\core_core_cr_in2$next[2:0]$12690 - assign { } { } - assign { } { } - assign $0\core_core_cr_out$next[2:0]$12642 $1\core_core_cr_out$next[2:0]$12693 - assign { } { } - assign $0\core_core_ea$next[4:0]$12644 $1\core_core_ea$next[4:0]$12695 - assign $0\core_core_fast1$next[2:0]$12645 $1\core_core_fast1$next[2:0]$12696 - assign { } { } - assign $0\core_core_fast2$next[2:0]$12647 $1\core_core_fast2$next[2:0]$12698 - assign { } { } - assign $0\core_core_fasto1$next[2:0]$12649 $1\core_core_fasto1$next[2:0]$12700 - assign $0\core_core_fasto2$next[2:0]$12650 $1\core_core_fasto2$next[2:0]$12701 - assign $0\core_core_lk$next[0:0]$12651 $1\core_core_lk$next[0:0]$12702 - assign $0\core_core_reg1$next[4:0]$12652 $1\core_core_reg1$next[4:0]$12703 - assign { } { } - assign $0\core_core_reg2$next[4:0]$12654 $1\core_core_reg2$next[4:0]$12705 - assign { } { } - assign $0\core_core_reg3$next[4:0]$12656 $1\core_core_reg3$next[4:0]$12707 - assign { } { } - assign $0\core_core_rego$next[4:0]$12658 $1\core_core_rego$next[4:0]$12709 - assign $0\core_core_spr1$next[9:0]$12659 $1\core_core_spr1$next[9:0]$12710 - assign { } { } - assign $0\core_core_spro$next[9:0]$12661 $1\core_core_spro$next[9:0]$12712 - assign $0\core_core_xer_in$next[2:0]$12662 $1\core_core_xer_in$next[2:0]$12713 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\core_xer_out$next[0:0]$12669 $1\core_xer_out$next[0:0]$12720 - assign $0\core_core_core_cr_rd_ok$next[0:0]$12622 $4\core_core_core_cr_rd_ok$next[0:0]$12823 - assign $0\core_core_core_oe_ok$next[0:0]$12631 $4\core_core_core_oe_ok$next[0:0]$12824 - assign $0\core_core_core_rc_ok$next[0:0]$12633 $4\core_core_core_rc_ok$next[0:0]$12825 - assign $0\core_core_cr_in1_ok$next[0:0]$12637 $4\core_core_cr_in1_ok$next[0:0]$12826 - assign $0\core_core_cr_in2_ok$2$next[0:0]$12640 $4\core_core_cr_in2_ok$2$next[0:0]$12827 - assign $0\core_core_cr_in2_ok$next[0:0]$12641 $4\core_core_cr_in2_ok$next[0:0]$12828 - assign $0\core_core_cr_wr_ok$next[0:0]$12643 $4\core_core_cr_wr_ok$next[0:0]$12829 - assign $0\core_core_fast1_ok$next[0:0]$12646 $4\core_core_fast1_ok$next[0:0]$12830 - assign $0\core_core_fast2_ok$next[0:0]$12648 $4\core_core_fast2_ok$next[0:0]$12831 - assign $0\core_core_reg1_ok$next[0:0]$12653 $4\core_core_reg1_ok$next[0:0]$12832 - assign $0\core_core_reg2_ok$next[0:0]$12655 $4\core_core_reg2_ok$next[0:0]$12833 - assign $0\core_core_reg3_ok$next[0:0]$12657 $4\core_core_reg3_ok$next[0:0]$12834 - assign $0\core_core_spr1_ok$next[0:0]$12660 $4\core_core_spr1_ok$next[0:0]$12835 - assign $0\core_cr_out_ok$next[0:0]$12663 $4\core_cr_out_ok$next[0:0]$12836 - assign $0\core_ea_ok$next[0:0]$12664 $4\core_ea_ok$next[0:0]$12837 - assign $0\core_fasto1_ok$next[0:0]$12665 $4\core_fasto1_ok$next[0:0]$12838 - assign $0\core_fasto2_ok$next[0:0]$12666 $4\core_fasto2_ok$next[0:0]$12839 - assign $0\core_rego_ok$next[0:0]$12667 $4\core_rego_ok$next[0:0]$12840 - assign $0\core_spro_ok$next[0:0]$12668 $4\core_spro_ok$next[0:0]$12841 - attribute \src "issuer_ls180.v:178168.5-178168.29" + assign $0\spr_o[9:0] $1\spr_o[9:0] + attribute \src "libresoc.v:45770.5-45770.29" switch \initial - attribute \src "issuer_ls180.v:178168.9-178168.17" + attribute \src "libresoc.v:45770.9-45770.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" - switch \fsm_state - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 assign { } { } + assign $1\spr_o[9:0] 10'0000000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 assign { } { } + assign $1\spr_o[9:0] 10'0000001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 assign { } { } + assign $1\spr_o[9:0] 10'0000001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 assign { } { } + assign $1\spr_o[9:0] 10'0000001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 assign { } { } + assign $1\spr_o[9:0] 10'0000001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 assign { } { } + assign $1\spr_o[9:0] 10'0000001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } + assign $1\spr_o[9:0] 10'0000010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 assign { } { } + assign $1\spr_o[9:0] 10'0000010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 assign { } { } + assign $1\spr_o[9:0] 10'0000010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 assign { } { } + assign $1\spr_o[9:0] 10'0000010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 assign { } { } + assign $1\spr_o[9:0] 10'0000010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 assign { } { } + assign $1\spr_o[9:0] 10'0000010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 assign { } { } + assign $1\spr_o[9:0] 10'0000010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 assign { } { } + assign $1\spr_o[9:0] 10'0000010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 assign { } { } + assign $1\spr_o[9:0] 10'0000011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 assign { } { } + assign $1\spr_o[9:0] 10'0000011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 assign { } { } + assign $1\spr_o[9:0] 10'0000011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 assign { } { } + assign $1\spr_o[9:0] 10'0000011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 assign { } { } + assign $1\spr_o[9:0] 10'0000011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 assign { } { } + assign $1\spr_o[9:0] 10'0000011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 assign { } { } + assign $1\spr_o[9:0] 10'0000011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 assign { } { } + assign $1\spr_o[9:0] 10'0000011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 assign { } { } + assign $1\spr_o[9:0] 10'0000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 assign { } { } + assign $1\spr_o[9:0] 10'0000100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 assign { } { } + assign $1\spr_o[9:0] 10'0000100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 assign { } { } + assign $1\spr_o[9:0] 10'0000100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 assign { } { } + assign $1\spr_o[9:0] 10'0000100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } + assign $1\spr_o[9:0] 10'0000100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 assign { } { } + assign $1\spr_o[9:0] 10'0000100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 assign { } { } + assign $1\spr_o[9:0] 10'0000101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 assign { } { } + assign $1\spr_o[9:0] 10'0000101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 assign { } { } + assign $1\spr_o[9:0] 10'0000101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 assign { } { } + assign $1\spr_o[9:0] 10'0000101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 assign { } { } + assign $1\spr_o[9:0] 10'0000101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 assign { } { } + assign $1\spr_o[9:0] 10'0000101101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 assign { } { } + assign $1\spr_o[9:0] 10'0000101110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 assign { } { } + assign $1\spr_o[9:0] 10'0000101111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 assign { } { } + assign $1\spr_o[9:0] 10'0000110000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 assign { } { } + assign $1\spr_o[9:0] 10'0000110001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 assign { } { } + assign $1\spr_o[9:0] 10'0000110010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 assign { } { } + assign $1\spr_o[9:0] 10'0000110011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 assign { } { } + assign $1\spr_o[9:0] 10'0000110100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 assign { } { } + assign $1\spr_o[9:0] 10'0000110101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 assign { } { } + assign $1\spr_o[9:0] 10'0000110110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 assign { } { } + assign $1\spr_o[9:0] 10'0000110111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 assign { } { } + assign $1\spr_o[9:0] 10'0000111000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 assign { } { } + assign $1\spr_o[9:0] 10'0000111001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 assign { } { } + assign $1\spr_o[9:0] 10'0000111010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 assign { } { } + assign $1\spr_o[9:0] 10'0000111011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 assign { } { } + assign $1\spr_o[9:0] 10'0000111100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 assign { } { } - assign { $1\core_core_core_is_32bit$next[0:0]$12679 $1\core_core_cr_wr_ok$next[0:0]$12694 $1\core_core_core_cr_wr$next[7:0]$12674 $1\core_core_core_cr_rd_ok$next[0:0]$12673 $1\core_core_core_cr_rd$next[7:0]$12672 $1\core_core_core_trapaddr$next[12:0]$12685 $1\core_core_core_traptype$next[6:0]$12686 $1\core_core_core_input_carry$next[1:0]$12676 $1\core_core_core_oe_ok$next[0:0]$12682 $1\core_core_core_oe$next[0:0]$12681 $1\core_core_core_rc_ok$next[0:0]$12684 $1\core_core_core_rc$next[0:0]$12683 $1\core_core_lk$next[0:0]$12702 $1\core_core_core_fn_unit$next[11:0]$12675 $1\core_core_core_insn_type$next[6:0]$12678 $1\core_core_core_insn$next[31:0]$12677 $1\core_core_core_cia$next[63:0]$12671 $1\core_core_core_msr$next[63:0]$12680 $1\core_cr_out_ok$next[0:0]$12714 $1\core_core_cr_out$next[2:0]$12693 $1\core_core_cr_in2_ok$2$next[0:0]$12691 $1\core_core_cr_in2$1$next[2:0]$12689 $1\core_core_cr_in2_ok$next[0:0]$12692 $1\core_core_cr_in2$next[2:0]$12690 $1\core_core_cr_in1_ok$next[0:0]$12688 $1\core_core_cr_in1$next[2:0]$12687 $1\core_fasto2_ok$next[0:0]$12717 $1\core_core_fasto2$next[2:0]$12701 $1\core_fasto1_ok$next[0:0]$12716 $1\core_core_fasto1$next[2:0]$12700 $1\core_core_fast2_ok$next[0:0]$12699 $1\core_core_fast2$next[2:0]$12698 $1\core_core_fast1_ok$next[0:0]$12697 $1\core_core_fast1$next[2:0]$12696 $1\core_xer_out$next[0:0]$12720 $1\core_core_xer_in$next[2:0]$12713 $1\core_core_spr1_ok$next[0:0]$12711 $1\core_core_spr1$next[9:0]$12710 $1\core_spro_ok$next[0:0]$12719 $1\core_core_spro$next[9:0]$12712 $1\core_core_reg3_ok$next[0:0]$12708 $1\core_core_reg3$next[4:0]$12707 $1\core_core_reg2_ok$next[0:0]$12706 $1\core_core_reg2$next[4:0]$12705 $1\core_core_reg1_ok$next[0:0]$12704 $1\core_core_reg1$next[4:0]$12703 $1\core_ea_ok$next[0:0]$12715 $1\core_core_ea$next[4:0]$12695 $1\core_rego_ok$next[0:0]$12718 $1\core_core_rego$next[4:0]$12709 $1\core_asmcode$next[7:0]$12670 } 321'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\spr_o[9:0] 10'0000111101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 assign { } { } + assign $1\spr_o[9:0] 10'0000111110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 assign { } { } + assign $1\spr_o[9:0] 10'0000111111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 assign { } { } + assign $1\spr_o[9:0] 10'0001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 assign { } { } + assign $1\spr_o[9:0] 10'0001000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 assign { } { } + assign $1\spr_o[9:0] 10'0001000010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 assign { } { } + assign $1\spr_o[9:0] 10'0001000011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 assign { } { } + assign $1\spr_o[9:0] 10'0001000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 assign { } { } + assign $1\spr_o[9:0] 10'0001000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 assign { } { } + assign $1\spr_o[9:0] 10'0001000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 assign { } { } + assign $1\spr_o[9:0] 10'0001000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 assign { } { } + assign $1\spr_o[9:0] 10'0001001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 assign { } { } + assign $1\spr_o[9:0] 10'0001001001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 assign { } { } + assign $1\spr_o[9:0] 10'0001001010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 assign { } { } + assign $1\spr_o[9:0] 10'0001001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 assign { } { } + assign $1\spr_o[9:0] 10'0001001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 assign { } { } + assign $1\spr_o[9:0] 10'0001001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 assign { } { } + assign $1\spr_o[9:0] 10'0001001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 assign { } { } + assign $1\spr_o[9:0] 10'0001001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 assign { } { } + assign $1\spr_o[9:0] 10'0001010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 assign { } { } + assign $1\spr_o[9:0] 10'0001010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 assign { } { } + assign $1\spr_o[9:0] 10'0001010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 assign { } { } + assign $1\spr_o[9:0] 10'0001010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 assign { } { } + assign $1\spr_o[9:0] 10'0001010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 assign { } { } + assign $1\spr_o[9:0] 10'0001010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 assign { } { } + assign $1\spr_o[9:0] 10'0001010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 assign { } { } + assign $1\spr_o[9:0] 10'0001010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 assign { } { } + assign $1\spr_o[9:0] 10'0001011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 assign { } { } + assign $1\spr_o[9:0] 10'0001011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 assign { } { } + assign $1\spr_o[9:0] 10'0001011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 assign { } { } + assign $1\spr_o[9:0] 10'0001011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 assign { } { } + assign $1\spr_o[9:0] 10'0001011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 assign { } { } + assign $1\spr_o[9:0] 10'0001011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 assign { } { } + assign $1\spr_o[9:0] 10'0001011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 assign { } { } + assign $1\spr_o[9:0] 10'0001011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 assign { } { } + assign $1\spr_o[9:0] 10'0001100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 assign { } { } + assign $1\spr_o[9:0] 10'0001100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 assign { } { } + assign $1\spr_o[9:0] 10'0001100010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 assign { } { } + assign $1\spr_o[9:0] 10'0001100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 assign { } { } + assign $1\spr_o[9:0] 10'0001100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 assign { } { } + assign $1\spr_o[9:0] 10'0001100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 assign { } { } + assign $1\spr_o[9:0] 10'0001100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 assign { } { } + assign $1\spr_o[9:0] 10'0001101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 assign { } { } + assign $1\spr_o[9:0] 10'0001101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 assign { } { } + assign $1\spr_o[9:0] 10'0001101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 assign { } { } + assign $1\spr_o[9:0] 10'0001101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 assign { } { } + assign $1\spr_o[9:0] 10'0001101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 assign { } { } + assign $1\spr_o[9:0] 10'0001101101 + case + assign $1\spr_o[9:0] 10'0000000000 + end + sync always + update \spr_o $0\spr_o[9:0] + end + attribute \src "libresoc.v:46082.3-46394.6" + process $proc$libresoc.v:46082$1401 + assign { } { } + assign { } { } + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:46083.5-46083.29" + switch \initial + attribute \src "libresoc.v:46083.9-46083.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 assign { } { } - assign $1\core_asmcode$next[7:0]$12670 $2\core_asmcode$next[7:0]$12721 - assign $1\core_core_core_cia$next[63:0]$12671 $2\core_core_core_cia$next[63:0]$12722 - assign $1\core_core_core_cr_rd$next[7:0]$12672 $2\core_core_core_cr_rd$next[7:0]$12723 - assign $1\core_core_core_cr_rd_ok$next[0:0]$12673 $2\core_core_core_cr_rd_ok$next[0:0]$12724 - assign $1\core_core_core_cr_wr$next[7:0]$12674 $2\core_core_core_cr_wr$next[7:0]$12725 - assign $1\core_core_core_fn_unit$next[11:0]$12675 $2\core_core_core_fn_unit$next[11:0]$12726 - assign $1\core_core_core_input_carry$next[1:0]$12676 $2\core_core_core_input_carry$next[1:0]$12727 - assign $1\core_core_core_insn$next[31:0]$12677 $2\core_core_core_insn$next[31:0]$12728 - assign $1\core_core_core_insn_type$next[6:0]$12678 $2\core_core_core_insn_type$next[6:0]$12729 - assign $1\core_core_core_is_32bit$next[0:0]$12679 $2\core_core_core_is_32bit$next[0:0]$12730 - assign $1\core_core_core_msr$next[63:0]$12680 $2\core_core_core_msr$next[63:0]$12731 - assign $1\core_core_core_oe$next[0:0]$12681 $2\core_core_core_oe$next[0:0]$12732 - assign $1\core_core_core_oe_ok$next[0:0]$12682 $2\core_core_core_oe_ok$next[0:0]$12733 - assign $1\core_core_core_rc$next[0:0]$12683 $2\core_core_core_rc$next[0:0]$12734 - assign $1\core_core_core_rc_ok$next[0:0]$12684 $2\core_core_core_rc_ok$next[0:0]$12735 - assign $1\core_core_core_trapaddr$next[12:0]$12685 $2\core_core_core_trapaddr$next[12:0]$12736 - assign $1\core_core_core_traptype$next[6:0]$12686 $2\core_core_core_traptype$next[6:0]$12737 - assign $1\core_core_cr_in1$next[2:0]$12687 $2\core_core_cr_in1$next[2:0]$12738 - assign $1\core_core_cr_in1_ok$next[0:0]$12688 $2\core_core_cr_in1_ok$next[0:0]$12739 - assign $1\core_core_cr_in2$1$next[2:0]$12689 $2\core_core_cr_in2$1$next[2:0]$12740 - assign $1\core_core_cr_in2$next[2:0]$12690 $2\core_core_cr_in2$next[2:0]$12741 - assign $1\core_core_cr_in2_ok$2$next[0:0]$12691 $2\core_core_cr_in2_ok$2$next[0:0]$12742 - assign $1\core_core_cr_in2_ok$next[0:0]$12692 $2\core_core_cr_in2_ok$next[0:0]$12743 - assign $1\core_core_cr_out$next[2:0]$12693 $2\core_core_cr_out$next[2:0]$12744 - assign $1\core_core_cr_wr_ok$next[0:0]$12694 $2\core_core_cr_wr_ok$next[0:0]$12745 - assign $1\core_core_ea$next[4:0]$12695 $2\core_core_ea$next[4:0]$12746 - assign $1\core_core_fast1$next[2:0]$12696 $2\core_core_fast1$next[2:0]$12747 - assign $1\core_core_fast1_ok$next[0:0]$12697 $2\core_core_fast1_ok$next[0:0]$12748 - assign $1\core_core_fast2$next[2:0]$12698 $2\core_core_fast2$next[2:0]$12749 - assign $1\core_core_fast2_ok$next[0:0]$12699 $2\core_core_fast2_ok$next[0:0]$12750 - assign $1\core_core_fasto1$next[2:0]$12700 $2\core_core_fasto1$next[2:0]$12751 - assign $1\core_core_fasto2$next[2:0]$12701 $2\core_core_fasto2$next[2:0]$12752 - assign $1\core_core_lk$next[0:0]$12702 $2\core_core_lk$next[0:0]$12753 - assign $1\core_core_reg1$next[4:0]$12703 $2\core_core_reg1$next[4:0]$12754 - assign $1\core_core_reg1_ok$next[0:0]$12704 $2\core_core_reg1_ok$next[0:0]$12755 - assign $1\core_core_reg2$next[4:0]$12705 $2\core_core_reg2$next[4:0]$12756 - assign $1\core_core_reg2_ok$next[0:0]$12706 $2\core_core_reg2_ok$next[0:0]$12757 - assign $1\core_core_reg3$next[4:0]$12707 $2\core_core_reg3$next[4:0]$12758 - assign $1\core_core_reg3_ok$next[0:0]$12708 $2\core_core_reg3_ok$next[0:0]$12759 - assign $1\core_core_rego$next[4:0]$12709 $2\core_core_rego$next[4:0]$12760 - assign $1\core_core_spr1$next[9:0]$12710 $2\core_core_spr1$next[9:0]$12761 - assign $1\core_core_spr1_ok$next[0:0]$12711 $2\core_core_spr1_ok$next[0:0]$12762 - assign $1\core_core_spro$next[9:0]$12712 $2\core_core_spro$next[9:0]$12763 - assign $1\core_core_xer_in$next[2:0]$12713 $2\core_core_xer_in$next[2:0]$12764 - assign $1\core_cr_out_ok$next[0:0]$12714 $2\core_cr_out_ok$next[0:0]$12765 - assign $1\core_ea_ok$next[0:0]$12715 $2\core_ea_ok$next[0:0]$12766 - assign $1\core_fasto1_ok$next[0:0]$12716 $2\core_fasto1_ok$next[0:0]$12767 - assign $1\core_fasto2_ok$next[0:0]$12717 $2\core_fasto2_ok$next[0:0]$12768 - assign $1\core_rego_ok$next[0:0]$12718 $2\core_rego_ok$next[0:0]$12769 - assign $1\core_spro_ok$next[0:0]$12719 $2\core_spro_ok$next[0:0]$12770 - assign $1\core_xer_out$next[0:0]$12720 $2\core_xer_out$next[0:0]$12771 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" - switch \imem_f_busy_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign $2\core_asmcode$next[7:0]$12721 \core_asmcode - assign $2\core_core_core_cia$next[63:0]$12722 \core_core_core_cia - assign $2\core_core_core_cr_rd$next[7:0]$12723 \core_core_core_cr_rd - assign $2\core_core_core_cr_rd_ok$next[0:0]$12724 \core_core_core_cr_rd_ok - assign $2\core_core_core_cr_wr$next[7:0]$12725 \core_core_core_cr_wr - assign $2\core_core_core_fn_unit$next[11:0]$12726 \core_core_core_fn_unit - assign $2\core_core_core_input_carry$next[1:0]$12727 \core_core_core_input_carry - assign $2\core_core_core_insn$next[31:0]$12728 \core_core_core_insn - assign $2\core_core_core_insn_type$next[6:0]$12729 \core_core_core_insn_type - assign $2\core_core_core_is_32bit$next[0:0]$12730 \core_core_core_is_32bit - assign $2\core_core_core_msr$next[63:0]$12731 \core_core_core_msr - assign $2\core_core_core_oe$next[0:0]$12732 \core_core_core_oe - assign $2\core_core_core_oe_ok$next[0:0]$12733 \core_core_core_oe_ok - assign $2\core_core_core_rc$next[0:0]$12734 \core_core_core_rc - assign $2\core_core_core_rc_ok$next[0:0]$12735 \core_core_core_rc_ok - assign $2\core_core_core_trapaddr$next[12:0]$12736 \core_core_core_trapaddr - assign $2\core_core_core_traptype$next[6:0]$12737 \core_core_core_traptype - assign $2\core_core_cr_in1$next[2:0]$12738 \core_core_cr_in1 - assign $2\core_core_cr_in1_ok$next[0:0]$12739 \core_core_cr_in1_ok - assign $2\core_core_cr_in2$1$next[2:0]$12740 \core_core_cr_in2$1 - assign $2\core_core_cr_in2$next[2:0]$12741 \core_core_cr_in2 - assign $2\core_core_cr_in2_ok$2$next[0:0]$12742 \core_core_cr_in2_ok$2 - assign $2\core_core_cr_in2_ok$next[0:0]$12743 \core_core_cr_in2_ok - assign $2\core_core_cr_out$next[2:0]$12744 \core_core_cr_out - assign $2\core_core_cr_wr_ok$next[0:0]$12745 \core_core_cr_wr_ok - assign $2\core_core_ea$next[4:0]$12746 \core_core_ea - assign $2\core_core_fast1$next[2:0]$12747 \core_core_fast1 - assign $2\core_core_fast1_ok$next[0:0]$12748 \core_core_fast1_ok - assign $2\core_core_fast2$next[2:0]$12749 \core_core_fast2 - assign $2\core_core_fast2_ok$next[0:0]$12750 \core_core_fast2_ok - assign $2\core_core_fasto1$next[2:0]$12751 \core_core_fasto1 - assign $2\core_core_fasto2$next[2:0]$12752 \core_core_fasto2 - assign $2\core_core_lk$next[0:0]$12753 \core_core_lk - assign $2\core_core_reg1$next[4:0]$12754 \core_core_reg1 - assign $2\core_core_reg1_ok$next[0:0]$12755 \core_core_reg1_ok - assign $2\core_core_reg2$next[4:0]$12756 \core_core_reg2 - assign $2\core_core_reg2_ok$next[0:0]$12757 \core_core_reg2_ok - assign $2\core_core_reg3$next[4:0]$12758 \core_core_reg3 - assign $2\core_core_reg3_ok$next[0:0]$12759 \core_core_reg3_ok - assign $2\core_core_rego$next[4:0]$12760 \core_core_rego - assign $2\core_core_spr1$next[9:0]$12761 \core_core_spr1 - assign $2\core_core_spr1_ok$next[0:0]$12762 \core_core_spr1_ok - assign $2\core_core_spro$next[9:0]$12763 \core_core_spro - assign $2\core_core_xer_in$next[2:0]$12764 \core_core_xer_in - assign $2\core_cr_out_ok$next[0:0]$12765 \core_cr_out_ok - assign $2\core_ea_ok$next[0:0]$12766 \core_ea_ok - assign $2\core_fasto1_ok$next[0:0]$12767 \core_fasto1_ok - assign $2\core_fasto2_ok$next[0:0]$12768 \core_fasto2_ok - assign $2\core_rego_ok$next[0:0]$12769 \core_rego_ok - assign $2\core_spro_ok$next[0:0]$12770 \core_spro_ok - assign $2\core_xer_out$next[0:0]$12771 \core_xer_out - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $2\core_core_core_is_32bit$next[0:0]$12730 $2\core_core_cr_wr_ok$next[0:0]$12745 $2\core_core_core_cr_wr$next[7:0]$12725 $2\core_core_core_cr_rd_ok$next[0:0]$12724 $2\core_core_core_cr_rd$next[7:0]$12723 $2\core_core_core_trapaddr$next[12:0]$12736 $2\core_core_core_traptype$next[6:0]$12737 $2\core_core_core_input_carry$next[1:0]$12727 $2\core_core_core_oe_ok$next[0:0]$12733 $2\core_core_core_oe$next[0:0]$12732 $2\core_core_core_rc_ok$next[0:0]$12735 $2\core_core_core_rc$next[0:0]$12734 $2\core_core_lk$next[0:0]$12753 $2\core_core_core_fn_unit$next[11:0]$12726 $2\core_core_core_insn_type$next[6:0]$12729 $2\core_core_core_insn$next[31:0]$12728 $2\core_core_core_cia$next[63:0]$12722 $2\core_core_core_msr$next[63:0]$12731 $2\core_cr_out_ok$next[0:0]$12765 $2\core_core_cr_out$next[2:0]$12744 $2\core_core_cr_in2_ok$2$next[0:0]$12742 $2\core_core_cr_in2$1$next[2:0]$12740 $2\core_core_cr_in2_ok$next[0:0]$12743 $2\core_core_cr_in2$next[2:0]$12741 $2\core_core_cr_in1_ok$next[0:0]$12739 $2\core_core_cr_in1$next[2:0]$12738 $2\core_fasto2_ok$next[0:0]$12768 $2\core_core_fasto2$next[2:0]$12752 $2\core_fasto1_ok$next[0:0]$12767 $2\core_core_fasto1$next[2:0]$12751 $2\core_core_fast2_ok$next[0:0]$12750 $2\core_core_fast2$next[2:0]$12749 $2\core_core_fast1_ok$next[0:0]$12748 $2\core_core_fast1$next[2:0]$12747 $2\core_xer_out$next[0:0]$12771 $2\core_core_xer_in$next[2:0]$12764 $2\core_core_spr1_ok$next[0:0]$12762 $2\core_core_spr1$next[9:0]$12761 $2\core_spro_ok$next[0:0]$12770 $2\core_core_spro$next[9:0]$12763 $2\core_core_reg3_ok$next[0:0]$12759 $2\core_core_reg3$next[4:0]$12758 $2\core_core_reg2_ok$next[0:0]$12757 $2\core_core_reg2$next[4:0]$12756 $2\core_core_reg1_ok$next[0:0]$12755 $2\core_core_reg1$next[4:0]$12754 $2\core_ea_ok$next[0:0]$12766 $2\core_core_ea$next[4:0]$12746 $2\core_rego_ok$next[0:0]$12769 $2\core_core_rego$next[4:0]$12760 $2\core_asmcode$next[7:0]$12721 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$6 \dec2_cr_in2$5 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'11 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 assign { } { } - assign $1\core_asmcode$next[7:0]$12670 $3\core_asmcode$next[7:0]$12772 - assign $1\core_core_core_cia$next[63:0]$12671 $3\core_core_core_cia$next[63:0]$12773 - assign $1\core_core_core_cr_rd$next[7:0]$12672 $3\core_core_core_cr_rd$next[7:0]$12774 - assign $1\core_core_core_cr_rd_ok$next[0:0]$12673 $3\core_core_core_cr_rd_ok$next[0:0]$12775 - assign $1\core_core_core_cr_wr$next[7:0]$12674 $3\core_core_core_cr_wr$next[7:0]$12776 - assign $1\core_core_core_fn_unit$next[11:0]$12675 $3\core_core_core_fn_unit$next[11:0]$12777 - assign $1\core_core_core_input_carry$next[1:0]$12676 $3\core_core_core_input_carry$next[1:0]$12778 - assign $1\core_core_core_insn$next[31:0]$12677 $3\core_core_core_insn$next[31:0]$12779 - assign $1\core_core_core_insn_type$next[6:0]$12678 $3\core_core_core_insn_type$next[6:0]$12780 - assign $1\core_core_core_is_32bit$next[0:0]$12679 $3\core_core_core_is_32bit$next[0:0]$12781 - assign $1\core_core_core_msr$next[63:0]$12680 $3\core_core_core_msr$next[63:0]$12782 - assign $1\core_core_core_oe$next[0:0]$12681 $3\core_core_core_oe$next[0:0]$12783 - assign $1\core_core_core_oe_ok$next[0:0]$12682 $3\core_core_core_oe_ok$next[0:0]$12784 - assign $1\core_core_core_rc$next[0:0]$12683 $3\core_core_core_rc$next[0:0]$12785 - assign $1\core_core_core_rc_ok$next[0:0]$12684 $3\core_core_core_rc_ok$next[0:0]$12786 - assign $1\core_core_core_trapaddr$next[12:0]$12685 $3\core_core_core_trapaddr$next[12:0]$12787 - assign $1\core_core_core_traptype$next[6:0]$12686 $3\core_core_core_traptype$next[6:0]$12788 - assign $1\core_core_cr_in1$next[2:0]$12687 $3\core_core_cr_in1$next[2:0]$12789 - assign $1\core_core_cr_in1_ok$next[0:0]$12688 $3\core_core_cr_in1_ok$next[0:0]$12790 - assign $1\core_core_cr_in2$1$next[2:0]$12689 $3\core_core_cr_in2$1$next[2:0]$12791 - assign $1\core_core_cr_in2$next[2:0]$12690 $3\core_core_cr_in2$next[2:0]$12792 - assign $1\core_core_cr_in2_ok$2$next[0:0]$12691 $3\core_core_cr_in2_ok$2$next[0:0]$12793 - assign $1\core_core_cr_in2_ok$next[0:0]$12692 $3\core_core_cr_in2_ok$next[0:0]$12794 - assign $1\core_core_cr_out$next[2:0]$12693 $3\core_core_cr_out$next[2:0]$12795 - assign $1\core_core_cr_wr_ok$next[0:0]$12694 $3\core_core_cr_wr_ok$next[0:0]$12796 - assign $1\core_core_ea$next[4:0]$12695 $3\core_core_ea$next[4:0]$12797 - assign $1\core_core_fast1$next[2:0]$12696 $3\core_core_fast1$next[2:0]$12798 - assign $1\core_core_fast1_ok$next[0:0]$12697 $3\core_core_fast1_ok$next[0:0]$12799 - assign $1\core_core_fast2$next[2:0]$12698 $3\core_core_fast2$next[2:0]$12800 - assign $1\core_core_fast2_ok$next[0:0]$12699 $3\core_core_fast2_ok$next[0:0]$12801 - assign $1\core_core_fasto1$next[2:0]$12700 $3\core_core_fasto1$next[2:0]$12802 - assign $1\core_core_fasto2$next[2:0]$12701 $3\core_core_fasto2$next[2:0]$12803 - assign $1\core_core_lk$next[0:0]$12702 $3\core_core_lk$next[0:0]$12804 - assign $1\core_core_reg1$next[4:0]$12703 $3\core_core_reg1$next[4:0]$12805 - assign $1\core_core_reg1_ok$next[0:0]$12704 $3\core_core_reg1_ok$next[0:0]$12806 - assign $1\core_core_reg2$next[4:0]$12705 $3\core_core_reg2$next[4:0]$12807 - assign $1\core_core_reg2_ok$next[0:0]$12706 $3\core_core_reg2_ok$next[0:0]$12808 - assign $1\core_core_reg3$next[4:0]$12707 $3\core_core_reg3$next[4:0]$12809 - assign $1\core_core_reg3_ok$next[0:0]$12708 $3\core_core_reg3_ok$next[0:0]$12810 - assign $1\core_core_rego$next[4:0]$12709 $3\core_core_rego$next[4:0]$12811 - assign $1\core_core_spr1$next[9:0]$12710 $3\core_core_spr1$next[9:0]$12812 - assign $1\core_core_spr1_ok$next[0:0]$12711 $3\core_core_spr1_ok$next[0:0]$12813 - assign $1\core_core_spro$next[9:0]$12712 $3\core_core_spro$next[9:0]$12814 - assign $1\core_core_xer_in$next[2:0]$12713 $3\core_core_xer_in$next[2:0]$12815 - assign $1\core_cr_out_ok$next[0:0]$12714 $3\core_cr_out_ok$next[0:0]$12816 - assign $1\core_ea_ok$next[0:0]$12715 $3\core_ea_ok$next[0:0]$12817 - assign $1\core_fasto1_ok$next[0:0]$12716 $3\core_fasto1_ok$next[0:0]$12818 - assign $1\core_fasto2_ok$next[0:0]$12717 $3\core_fasto2_ok$next[0:0]$12819 - assign $1\core_rego_ok$next[0:0]$12718 $3\core_rego_ok$next[0:0]$12820 - assign $1\core_spro_ok$next[0:0]$12719 $3\core_spro_ok$next[0:0]$12821 - assign $1\core_xer_out$next[0:0]$12720 $3\core_xer_out$next[0:0]$12822 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" - switch \$43 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $3\core_core_core_is_32bit$next[0:0]$12781 $3\core_core_cr_wr_ok$next[0:0]$12796 $3\core_core_core_cr_wr$next[7:0]$12776 $3\core_core_core_cr_rd_ok$next[0:0]$12775 $3\core_core_core_cr_rd$next[7:0]$12774 $3\core_core_core_trapaddr$next[12:0]$12787 $3\core_core_core_traptype$next[6:0]$12788 $3\core_core_core_input_carry$next[1:0]$12778 $3\core_core_core_oe_ok$next[0:0]$12784 $3\core_core_core_oe$next[0:0]$12783 $3\core_core_core_rc_ok$next[0:0]$12786 $3\core_core_core_rc$next[0:0]$12785 $3\core_core_lk$next[0:0]$12804 $3\core_core_core_fn_unit$next[11:0]$12777 $3\core_core_core_insn_type$next[6:0]$12780 $3\core_core_core_insn$next[31:0]$12779 $3\core_core_core_cia$next[63:0]$12773 $3\core_core_core_msr$next[63:0]$12782 $3\core_cr_out_ok$next[0:0]$12816 $3\core_core_cr_out$next[2:0]$12795 $3\core_core_cr_in2_ok$2$next[0:0]$12793 $3\core_core_cr_in2$1$next[2:0]$12791 $3\core_core_cr_in2_ok$next[0:0]$12794 $3\core_core_cr_in2$next[2:0]$12792 $3\core_core_cr_in1_ok$next[0:0]$12790 $3\core_core_cr_in1$next[2:0]$12789 $3\core_fasto2_ok$next[0:0]$12819 $3\core_core_fasto2$next[2:0]$12803 $3\core_fasto1_ok$next[0:0]$12818 $3\core_core_fasto1$next[2:0]$12802 $3\core_core_fast2_ok$next[0:0]$12801 $3\core_core_fast2$next[2:0]$12800 $3\core_core_fast1_ok$next[0:0]$12799 $3\core_core_fast1$next[2:0]$12798 $3\core_xer_out$next[0:0]$12822 $3\core_core_xer_in$next[2:0]$12815 $3\core_core_spr1_ok$next[0:0]$12813 $3\core_core_spr1$next[9:0]$12812 $3\core_spro_ok$next[0:0]$12821 $3\core_core_spro$next[9:0]$12814 $3\core_core_reg3_ok$next[0:0]$12810 $3\core_core_reg3$next[4:0]$12809 $3\core_core_reg2_ok$next[0:0]$12808 $3\core_core_reg2$next[4:0]$12807 $3\core_core_reg1_ok$next[0:0]$12806 $3\core_core_reg1$next[4:0]$12805 $3\core_ea_ok$next[0:0]$12817 $3\core_core_ea$next[4:0]$12797 $3\core_rego_ok$next[0:0]$12820 $3\core_core_rego$next[4:0]$12811 $3\core_asmcode$next[7:0]$12772 } 321'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\core_asmcode$next[7:0]$12772 \core_asmcode - assign $3\core_core_core_cia$next[63:0]$12773 \core_core_core_cia - assign $3\core_core_core_cr_rd$next[7:0]$12774 \core_core_core_cr_rd - assign $3\core_core_core_cr_rd_ok$next[0:0]$12775 \core_core_core_cr_rd_ok - assign $3\core_core_core_cr_wr$next[7:0]$12776 \core_core_core_cr_wr - assign $3\core_core_core_fn_unit$next[11:0]$12777 \core_core_core_fn_unit - assign $3\core_core_core_input_carry$next[1:0]$12778 \core_core_core_input_carry - assign $3\core_core_core_insn$next[31:0]$12779 \core_core_core_insn - assign $3\core_core_core_insn_type$next[6:0]$12780 \core_core_core_insn_type - assign $3\core_core_core_is_32bit$next[0:0]$12781 \core_core_core_is_32bit - assign $3\core_core_core_msr$next[63:0]$12782 \core_core_core_msr - assign $3\core_core_core_oe$next[0:0]$12783 \core_core_core_oe - assign $3\core_core_core_oe_ok$next[0:0]$12784 \core_core_core_oe_ok - assign $3\core_core_core_rc$next[0:0]$12785 \core_core_core_rc - assign $3\core_core_core_rc_ok$next[0:0]$12786 \core_core_core_rc_ok - assign $3\core_core_core_trapaddr$next[12:0]$12787 \core_core_core_trapaddr - assign $3\core_core_core_traptype$next[6:0]$12788 \core_core_core_traptype - assign $3\core_core_cr_in1$next[2:0]$12789 \core_core_cr_in1 - assign $3\core_core_cr_in1_ok$next[0:0]$12790 \core_core_cr_in1_ok - assign $3\core_core_cr_in2$1$next[2:0]$12791 \core_core_cr_in2$1 - assign $3\core_core_cr_in2$next[2:0]$12792 \core_core_cr_in2 - assign $3\core_core_cr_in2_ok$2$next[0:0]$12793 \core_core_cr_in2_ok$2 - assign $3\core_core_cr_in2_ok$next[0:0]$12794 \core_core_cr_in2_ok - assign $3\core_core_cr_out$next[2:0]$12795 \core_core_cr_out - assign $3\core_core_cr_wr_ok$next[0:0]$12796 \core_core_cr_wr_ok - assign $3\core_core_ea$next[4:0]$12797 \core_core_ea - assign $3\core_core_fast1$next[2:0]$12798 \core_core_fast1 - assign $3\core_core_fast1_ok$next[0:0]$12799 \core_core_fast1_ok - assign $3\core_core_fast2$next[2:0]$12800 \core_core_fast2 - assign $3\core_core_fast2_ok$next[0:0]$12801 \core_core_fast2_ok - assign $3\core_core_fasto1$next[2:0]$12802 \core_core_fasto1 - assign $3\core_core_fasto2$next[2:0]$12803 \core_core_fasto2 - assign $3\core_core_lk$next[0:0]$12804 \core_core_lk - assign $3\core_core_reg1$next[4:0]$12805 \core_core_reg1 - assign $3\core_core_reg1_ok$next[0:0]$12806 \core_core_reg1_ok - assign $3\core_core_reg2$next[4:0]$12807 \core_core_reg2 - assign $3\core_core_reg2_ok$next[0:0]$12808 \core_core_reg2_ok - assign $3\core_core_reg3$next[4:0]$12809 \core_core_reg3 - assign $3\core_core_reg3_ok$next[0:0]$12810 \core_core_reg3_ok - assign $3\core_core_rego$next[4:0]$12811 \core_core_rego - assign $3\core_core_spr1$next[9:0]$12812 \core_core_spr1 - assign $3\core_core_spr1_ok$next[0:0]$12813 \core_core_spr1_ok - assign $3\core_core_spro$next[9:0]$12814 \core_core_spro - assign $3\core_core_xer_in$next[2:0]$12815 \core_core_xer_in - assign $3\core_cr_out_ok$next[0:0]$12816 \core_cr_out_ok - assign $3\core_ea_ok$next[0:0]$12817 \core_ea_ok - assign $3\core_fasto1_ok$next[0:0]$12818 \core_fasto1_ok - assign $3\core_fasto2_ok$next[0:0]$12819 \core_fasto2_ok - assign $3\core_rego_ok$next[0:0]$12820 \core_rego_ok - assign $3\core_spro_ok$next[0:0]$12821 \core_spro_ok - assign $3\core_xer_out$next[0:0]$12822 \core_xer_out - end - case - assign $1\core_asmcode$next[7:0]$12670 \core_asmcode - assign $1\core_core_core_cia$next[63:0]$12671 \core_core_core_cia - assign $1\core_core_core_cr_rd$next[7:0]$12672 \core_core_core_cr_rd - assign $1\core_core_core_cr_rd_ok$next[0:0]$12673 \core_core_core_cr_rd_ok - assign $1\core_core_core_cr_wr$next[7:0]$12674 \core_core_core_cr_wr - assign $1\core_core_core_fn_unit$next[11:0]$12675 \core_core_core_fn_unit - assign $1\core_core_core_input_carry$next[1:0]$12676 \core_core_core_input_carry - assign $1\core_core_core_insn$next[31:0]$12677 \core_core_core_insn - assign $1\core_core_core_insn_type$next[6:0]$12678 \core_core_core_insn_type - assign $1\core_core_core_is_32bit$next[0:0]$12679 \core_core_core_is_32bit - assign $1\core_core_core_msr$next[63:0]$12680 \core_core_core_msr - assign $1\core_core_core_oe$next[0:0]$12681 \core_core_core_oe - assign $1\core_core_core_oe_ok$next[0:0]$12682 \core_core_core_oe_ok - assign $1\core_core_core_rc$next[0:0]$12683 \core_core_core_rc - assign $1\core_core_core_rc_ok$next[0:0]$12684 \core_core_core_rc_ok - assign $1\core_core_core_trapaddr$next[12:0]$12685 \core_core_core_trapaddr - assign $1\core_core_core_traptype$next[6:0]$12686 \core_core_core_traptype - assign $1\core_core_cr_in1$next[2:0]$12687 \core_core_cr_in1 - assign $1\core_core_cr_in1_ok$next[0:0]$12688 \core_core_cr_in1_ok - assign $1\core_core_cr_in2$1$next[2:0]$12689 \core_core_cr_in2$1 - assign $1\core_core_cr_in2$next[2:0]$12690 \core_core_cr_in2 - assign $1\core_core_cr_in2_ok$2$next[0:0]$12691 \core_core_cr_in2_ok$2 - assign $1\core_core_cr_in2_ok$next[0:0]$12692 \core_core_cr_in2_ok - assign $1\core_core_cr_out$next[2:0]$12693 \core_core_cr_out - assign $1\core_core_cr_wr_ok$next[0:0]$12694 \core_core_cr_wr_ok - assign $1\core_core_ea$next[4:0]$12695 \core_core_ea - assign $1\core_core_fast1$next[2:0]$12696 \core_core_fast1 - assign $1\core_core_fast1_ok$next[0:0]$12697 \core_core_fast1_ok - assign $1\core_core_fast2$next[2:0]$12698 \core_core_fast2 - assign $1\core_core_fast2_ok$next[0:0]$12699 \core_core_fast2_ok - assign $1\core_core_fasto1$next[2:0]$12700 \core_core_fasto1 - assign $1\core_core_fasto2$next[2:0]$12701 \core_core_fasto2 - assign $1\core_core_lk$next[0:0]$12702 \core_core_lk - assign $1\core_core_reg1$next[4:0]$12703 \core_core_reg1 - assign $1\core_core_reg1_ok$next[0:0]$12704 \core_core_reg1_ok - assign $1\core_core_reg2$next[4:0]$12705 \core_core_reg2 - assign $1\core_core_reg2_ok$next[0:0]$12706 \core_core_reg2_ok - assign $1\core_core_reg3$next[4:0]$12707 \core_core_reg3 - assign $1\core_core_reg3_ok$next[0:0]$12708 \core_core_reg3_ok - assign $1\core_core_rego$next[4:0]$12709 \core_core_rego - assign $1\core_core_spr1$next[9:0]$12710 \core_core_spr1 - assign $1\core_core_spr1_ok$next[0:0]$12711 \core_core_spr1_ok - assign $1\core_core_spro$next[9:0]$12712 \core_core_spro - assign $1\core_core_xer_in$next[2:0]$12713 \core_core_xer_in - assign $1\core_cr_out_ok$next[0:0]$12714 \core_cr_out_ok - assign $1\core_ea_ok$next[0:0]$12715 \core_ea_ok - assign $1\core_fasto1_ok$next[0:0]$12716 \core_fasto1_ok - assign $1\core_fasto2_ok$next[0:0]$12717 \core_fasto2_ok - assign $1\core_rego_ok$next[0:0]$12718 \core_rego_ok - assign $1\core_spro_ok$next[0:0]$12719 \core_spro_ok - assign $1\core_xer_out$next[0:0]$12720 \core_xer_out - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $4\core_rego_ok$next[0:0]$12840 1'0 - assign $4\core_ea_ok$next[0:0]$12837 1'0 - assign $4\core_core_reg1_ok$next[0:0]$12832 1'0 - assign $4\core_core_reg2_ok$next[0:0]$12833 1'0 - assign $4\core_core_reg3_ok$next[0:0]$12834 1'0 - assign $4\core_spro_ok$next[0:0]$12841 1'0 - assign $4\core_core_spr1_ok$next[0:0]$12835 1'0 - assign $4\core_core_fast1_ok$next[0:0]$12830 1'0 - assign $4\core_core_fast2_ok$next[0:0]$12831 1'0 - assign $4\core_fasto1_ok$next[0:0]$12838 1'0 - assign $4\core_fasto2_ok$next[0:0]$12839 1'0 - assign $4\core_core_cr_in1_ok$next[0:0]$12826 1'0 - assign $4\core_core_cr_in2_ok$next[0:0]$12828 1'0 - assign $4\core_core_cr_in2_ok$2$next[0:0]$12827 1'0 - assign $4\core_cr_out_ok$next[0:0]$12836 1'0 - assign $4\core_core_core_rc_ok$next[0:0]$12825 1'0 - assign $4\core_core_core_oe_ok$next[0:0]$12824 1'0 - assign $4\core_core_core_cr_rd_ok$next[0:0]$12823 1'0 - assign $4\core_core_cr_wr_ok$next[0:0]$12829 1'0 - case - assign $4\core_core_core_cr_rd_ok$next[0:0]$12823 $1\core_core_core_cr_rd_ok$next[0:0]$12673 - assign $4\core_core_core_oe_ok$next[0:0]$12824 $1\core_core_core_oe_ok$next[0:0]$12682 - assign $4\core_core_core_rc_ok$next[0:0]$12825 $1\core_core_core_rc_ok$next[0:0]$12684 - assign $4\core_core_cr_in1_ok$next[0:0]$12826 $1\core_core_cr_in1_ok$next[0:0]$12688 - assign $4\core_core_cr_in2_ok$2$next[0:0]$12827 $1\core_core_cr_in2_ok$2$next[0:0]$12691 - assign $4\core_core_cr_in2_ok$next[0:0]$12828 $1\core_core_cr_in2_ok$next[0:0]$12692 - assign $4\core_core_cr_wr_ok$next[0:0]$12829 $1\core_core_cr_wr_ok$next[0:0]$12694 - assign $4\core_core_fast1_ok$next[0:0]$12830 $1\core_core_fast1_ok$next[0:0]$12697 - assign $4\core_core_fast2_ok$next[0:0]$12831 $1\core_core_fast2_ok$next[0:0]$12699 - assign $4\core_core_reg1_ok$next[0:0]$12832 $1\core_core_reg1_ok$next[0:0]$12704 - assign $4\core_core_reg2_ok$next[0:0]$12833 $1\core_core_reg2_ok$next[0:0]$12706 - assign $4\core_core_reg3_ok$next[0:0]$12834 $1\core_core_reg3_ok$next[0:0]$12708 - assign $4\core_core_spr1_ok$next[0:0]$12835 $1\core_core_spr1_ok$next[0:0]$12711 - assign $4\core_cr_out_ok$next[0:0]$12836 $1\core_cr_out_ok$next[0:0]$12714 - assign $4\core_ea_ok$next[0:0]$12837 $1\core_ea_ok$next[0:0]$12715 - assign $4\core_fasto1_ok$next[0:0]$12838 $1\core_fasto1_ok$next[0:0]$12716 - assign $4\core_fasto2_ok$next[0:0]$12839 $1\core_fasto2_ok$next[0:0]$12717 - assign $4\core_rego_ok$next[0:0]$12840 $1\core_rego_ok$next[0:0]$12718 - assign $4\core_spro_ok$next[0:0]$12841 $1\core_spro_ok$next[0:0]$12719 - end - sync always - update \core_asmcode$next $0\core_asmcode$next[7:0]$12619 - update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$12620 - update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$12621 - update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$12622 - update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$12623 - update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[11:0]$12624 - update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$12625 - update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$12626 - update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$12627 - update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$12628 - update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$12629 - update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$12630 - update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$12631 - update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$12632 - update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$12633 - update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$12634 - update \core_core_core_traptype$next $0\core_core_core_traptype$next[6:0]$12635 - update \core_core_cr_in1$next $0\core_core_cr_in1$next[2:0]$12636 - update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$12637 - update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[2:0]$12638 - update \core_core_cr_in2$next $0\core_core_cr_in2$next[2:0]$12639 - update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$12640 - update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$12641 - update \core_core_cr_out$next $0\core_core_cr_out$next[2:0]$12642 - update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$12643 - update \core_core_ea$next $0\core_core_ea$next[4:0]$12644 - update \core_core_fast1$next $0\core_core_fast1$next[2:0]$12645 - update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$12646 - update \core_core_fast2$next $0\core_core_fast2$next[2:0]$12647 - update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$12648 - update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$12649 - update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$12650 - update \core_core_lk$next $0\core_core_lk$next[0:0]$12651 - update \core_core_reg1$next $0\core_core_reg1$next[4:0]$12652 - update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$12653 - update \core_core_reg2$next $0\core_core_reg2$next[4:0]$12654 - update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$12655 - update \core_core_reg3$next $0\core_core_reg3$next[4:0]$12656 - update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$12657 - update \core_core_rego$next $0\core_core_rego$next[4:0]$12658 - update \core_core_spr1$next $0\core_core_spr1$next[9:0]$12659 - update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$12660 - update \core_core_spro$next $0\core_core_spro$next[9:0]$12661 - update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$12662 - update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$12663 - update \core_ea_ok$next $0\core_ea_ok$next[0:0]$12664 - update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$12665 - update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$12666 - update \core_rego_ok$next $0\core_rego_ok$next[0:0]$12667 - update \core_spro_ok$next $0\core_spro_ok$next[0:0]$12668 - update \core_xer_out$next $0\core_xer_out$next[0:0]$12669 - end - attribute \src "issuer_ls180.v:178274.3-178283.6" - process $proc$issuer_ls180.v:178274$12842 - assign { } { } - assign { } { } - assign $0\delay$next[1:0]$12843 $1\delay$next[1:0]$12844 - attribute \src "issuer_ls180.v:178275.5-178275.29" - switch \initial - attribute \src "issuer_ls180.v:178275.9-178275.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:145" - switch \$7 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 assign { } { } - assign $1\delay$next[1:0]$12844 \$9 [1:0] - case - assign $1\delay$next[1:0]$12844 \delay - end - sync always - update \delay$next $0\delay$next[1:0]$12843 - end - attribute \src "issuer_ls180.v:178284.3-178320.6" - process $proc$issuer_ls180.v:178284$12845 - assign { } { } - assign { } { } - assign { } { } - assign $0\core_raw_insn_i$next[31:0]$12846 $4\core_raw_insn_i$next[31:0]$12850 - attribute \src "issuer_ls180.v:178285.5-178285.29" - switch \initial - attribute \src "issuer_ls180.v:178285.9-178285.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" - switch \fsm_state - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 assign { } { } - assign $1\core_raw_insn_i$next[31:0]$12847 0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 assign { } { } - assign $1\core_raw_insn_i$next[31:0]$12847 $2\core_raw_insn_i$next[31:0]$12848 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" - switch \imem_f_busy_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign $2\core_raw_insn_i$next[31:0]$12848 \core_raw_insn_i - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\core_raw_insn_i$next[31:0]$12848 \dec2_raw_opcode_in - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'11 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 assign { } { } - assign $1\core_raw_insn_i$next[31:0]$12847 $3\core_raw_insn_i$next[31:0]$12849 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" - switch \$45 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\core_raw_insn_i$next[31:0]$12849 0 - case - assign $3\core_raw_insn_i$next[31:0]$12849 \core_raw_insn_i - end - case - assign $1\core_raw_insn_i$next[31:0]$12847 \core_raw_insn_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 assign { } { } - assign $4\core_raw_insn_i$next[31:0]$12850 0 - case - assign $4\core_raw_insn_i$next[31:0]$12850 $1\core_raw_insn_i$next[31:0]$12847 - end - sync always - update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$12846 - end - attribute \src "issuer_ls180.v:178321.3-178357.6" - process $proc$issuer_ls180.v:178321$12851 - assign { } { } - assign { } { } - assign { } { } - assign $0\core_bigendian_i$3$next[0:0]$12852 $4\core_bigendian_i$3$next[0:0]$12856 - attribute \src "issuer_ls180.v:178322.5-178322.29" - switch \initial - attribute \src "issuer_ls180.v:178322.9-178322.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" - switch \fsm_state - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 assign { } { } - assign $1\core_bigendian_i$3$next[0:0]$12853 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 assign { } { } - assign $1\core_bigendian_i$3$next[0:0]$12853 $2\core_bigendian_i$3$next[0:0]$12854 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" - switch \imem_f_busy_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign $2\core_bigendian_i$3$next[0:0]$12854 \core_bigendian_i$3 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\core_bigendian_i$3$next[0:0]$12854 \core_bigendian_i - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'11 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 assign { } { } - assign $1\core_bigendian_i$3$next[0:0]$12853 $3\core_bigendian_i$3$next[0:0]$12855 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" - switch \$47 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\core_bigendian_i$3$next[0:0]$12855 1'0 - case - assign $3\core_bigendian_i$3$next[0:0]$12855 \core_bigendian_i$3 - end - case - assign $1\core_bigendian_i$3$next[0:0]$12853 \core_bigendian_i$3 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 assign { } { } - assign $4\core_bigendian_i$3$next[0:0]$12856 1'0 - case - assign $4\core_bigendian_i$3$next[0:0]$12856 $1\core_bigendian_i$3$next[0:0]$12853 - end - sync always - update \core_bigendian_i$3$next $0\core_bigendian_i$3$next[0:0]$12852 - end - attribute \src "issuer_ls180.v:178358.3-178373.6" - process $proc$issuer_ls180.v:178358$12857 - assign { } { } - assign { } { } - assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] - attribute \src "issuer_ls180.v:178359.5-178359.29" - switch \initial - attribute \src "issuer_ls180.v:178359.9-178359.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" - switch \fsm_state - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 assign { } { } - assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - switch \$53 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\imem_a_pc_i[47:0] \pc [47:0] - case - assign $2\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 - end - case - assign $1\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 - end - sync always - update \imem_a_pc_i $0\imem_a_pc_i[47:0] - end - attribute \src "issuer_ls180.v:178374.3-178398.6" - process $proc$issuer_ls180.v:178374$12858 - assign { } { } - assign { } { } - assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] - attribute \src "issuer_ls180.v:178375.5-178375.29" - switch \initial - attribute \src "issuer_ls180.v:178375.9-178375.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" - switch \fsm_state - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 assign { } { } - assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - switch \$59 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\imem_a_valid_i[0:0] 1'1 - case - assign $2\imem_a_valid_i[0:0] 1'0 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 assign { } { } - assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" - switch \imem_f_busy_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\imem_a_valid_i[0:0] 1'1 - case - assign $3\imem_a_valid_i[0:0] 1'0 - end - case - assign $1\imem_a_valid_i[0:0] 1'0 - end - sync always - update \imem_a_valid_i $0\imem_a_valid_i[0:0] - end - attribute \src "issuer_ls180.v:178399.3-178423.6" - process $proc$issuer_ls180.v:178399$12859 - assign { } { } - assign { } { } - assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] - attribute \src "issuer_ls180.v:178400.5-178400.29" - switch \initial - attribute \src "issuer_ls180.v:178400.9-178400.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" - switch \fsm_state - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 assign { } { } - assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - switch \$65 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\imem_f_valid_i[0:0] 1'1 - case - assign $2\imem_f_valid_i[0:0] 1'0 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 assign { } { } - assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" - switch \imem_f_busy_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\imem_f_valid_i[0:0] 1'1 - case - assign $3\imem_f_valid_i[0:0] 1'0 - end - case - assign $1\imem_f_valid_i[0:0] 1'0 - end - sync always - update \imem_f_valid_i $0\imem_f_valid_i[0:0] - end - attribute \src "issuer_ls180.v:178424.3-178444.6" - process $proc$issuer_ls180.v:178424$12860 - assign { } { } - assign { } { } - assign { } { } - assign $0\dec2_cur_pc$next[63:0]$12861 $3\dec2_cur_pc$next[63:0]$12864 - attribute \src "issuer_ls180.v:178425.5-178425.29" - switch \initial - attribute \src "issuer_ls180.v:178425.9-178425.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" - switch \fsm_state - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 assign { } { } - assign $1\dec2_cur_pc$next[63:0]$12862 $2\dec2_cur_pc$next[63:0]$12863 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - switch \$71 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dec2_cur_pc$next[63:0]$12863 \pc - case - assign $2\dec2_cur_pc$next[63:0]$12863 \dec2_cur_pc - end - case - assign $1\dec2_cur_pc$next[63:0]$12862 \dec2_cur_pc - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 assign { } { } - assign $3\dec2_cur_pc$next[63:0]$12864 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\dec2_cur_pc$next[63:0]$12864 $1\dec2_cur_pc$next[63:0]$12862 - end - sync always - update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$12861 - end - attribute \src "issuer_ls180.v:178445.3-178474.6" - process $proc$issuer_ls180.v:178445$12865 - assign { } { } - assign { } { } - assign { } { } - assign $0\msr_read$next[0:0]$12866 $4\msr_read$next[0:0]$12870 - attribute \src "issuer_ls180.v:178446.5-178446.29" - switch \initial - attribute \src "issuer_ls180.v:178446.9-178446.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" - switch \fsm_state - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 assign { } { } - assign $1\msr_read$next[0:0]$12867 $2\msr_read$next[0:0]$12868 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - switch \$77 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\msr_read$next[0:0]$12868 1'0 - case - assign $2\msr_read$next[0:0]$12868 \msr_read - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 assign { } { } - assign $1\msr_read$next[0:0]$12867 $3\msr_read$next[0:0]$12869 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - switch \$79 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\msr_read$next[0:0]$12869 1'1 - case - assign $3\msr_read$next[0:0]$12869 \msr_read - end - case - assign $1\msr_read$next[0:0]$12867 \msr_read - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 assign { } { } - assign $4\msr_read$next[0:0]$12870 1'1 - case - assign $4\msr_read$next[0:0]$12870 $1\msr_read$next[0:0]$12867 - end - sync always - update \msr_read$next $0\msr_read$next[0:0]$12866 - end - attribute \src "issuer_ls180.v:178475.3-178520.6" - process $proc$issuer_ls180.v:178475$12871 - assign { } { } - assign { } { } - assign { } { } - assign $0\fsm_state$next[1:0]$12872 $5\fsm_state$next[1:0]$12877 - attribute \src "issuer_ls180.v:178476.5-178476.29" - switch \initial - attribute \src "issuer_ls180.v:178476.9-178476.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" - switch \fsm_state - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 assign { } { } - assign $1\fsm_state$next[1:0]$12873 $2\fsm_state$next[1:0]$12874 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - switch \$85 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fsm_state$next[1:0]$12874 2'01 - case - assign $2\fsm_state$next[1:0]$12874 \fsm_state - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 assign { } { } - assign $1\fsm_state$next[1:0]$12873 $3\fsm_state$next[1:0]$12875 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" - switch \imem_f_busy_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign $3\fsm_state$next[1:0]$12875 \fsm_state - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $3\fsm_state$next[1:0]$12875 2'10 - end - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 assign { } { } - assign $1\fsm_state$next[1:0]$12873 2'11 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'11 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 assign { } { } - assign $1\fsm_state$next[1:0]$12873 $4\fsm_state$next[1:0]$12876 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" - switch \$87 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fsm_state$next[1:0]$12876 2'00 - case - assign $4\fsm_state$next[1:0]$12876 \fsm_state - end - case - assign $1\fsm_state$next[1:0]$12873 \fsm_state - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 assign { } { } - assign $5\fsm_state$next[1:0]$12877 2'00 - case - assign $5\fsm_state$next[1:0]$12877 $1\fsm_state$next[1:0]$12873 - end - sync always - update \fsm_state$next $0\fsm_state$next[1:0]$12872 - end - attribute \src "issuer_ls180.v:178521.3-178539.6" - process $proc$issuer_ls180.v:178521$12878 - assign { } { } - assign { } { } - assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] - attribute \src "issuer_ls180.v:178522.5-178522.29" - switch \initial - attribute \src "issuer_ls180.v:178522.9-178522.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" - switch \fsm_state - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 assign { } { } - assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - switch \$93 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign $2\core_stopped_i[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\core_stopped_i[0:0] 1'1 - end - case - assign $1\core_stopped_i[0:0] 1'0 - end - sync always - update \core_stopped_i $0\core_stopped_i[0:0] - end - attribute \src "issuer_ls180.v:178540.3-178558.6" - process $proc$issuer_ls180.v:178540$12879 - assign { } { } - assign { } { } - assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] - attribute \src "issuer_ls180.v:178541.5-178541.29" - switch \initial - attribute \src "issuer_ls180.v:178541.9-178541.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" - switch \fsm_state - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'00 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 assign { } { } - assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - switch \$99 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign $2\dbg_core_stopped_i[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\dbg_core_stopped_i[0:0] 1'1 - end - case - assign $1\dbg_core_stopped_i[0:0] 1'0 - end - sync always - update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] - end - attribute \src "issuer_ls180.v:178559.3-178579.6" - process $proc$issuer_ls180.v:178559$12880 - assign { } { } - assign { } { } - assign { } { } - assign $0\dec2_cur_msr$next[63:0]$12881 $3\dec2_cur_msr$next[63:0]$12884 - attribute \src "issuer_ls180.v:178560.5-178560.29" - switch \initial - attribute \src "issuer_ls180.v:178560.9-178560.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" - switch \fsm_state - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 assign { } { } - assign $1\dec2_cur_msr$next[63:0]$12882 $2\dec2_cur_msr$next[63:0]$12883 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - switch \$101 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dec2_cur_msr$next[63:0]$12883 \core_msr__data_o - case - assign $2\dec2_cur_msr$next[63:0]$12883 \dec2_cur_msr - end - case - assign $1\dec2_cur_msr$next[63:0]$12882 \dec2_cur_msr - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 assign { } { } - assign $3\dec2_cur_msr$next[63:0]$12884 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\dec2_cur_msr$next[63:0]$12884 $1\dec2_cur_msr$next[63:0]$12882 - end - sync always - update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$12881 - end - attribute \src "issuer_ls180.v:178580.3-178598.6" - process $proc$issuer_ls180.v:178580$12885 - assign { } { } - assign { } { } - assign $0\dec2_raw_opcode_in[31:0] $1\dec2_raw_opcode_in[31:0] - attribute \src "issuer_ls180.v:178581.5-178581.29" - switch \initial - attribute \src "issuer_ls180.v:178581.9-178581.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" - switch \fsm_state - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 assign { } { } - assign $1\dec2_raw_opcode_in[31:0] $2\dec2_raw_opcode_in[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" - switch \imem_f_busy_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign $2\dec2_raw_opcode_in[31:0] 0 - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\dec2_raw_opcode_in[31:0] \$103 - end - case - assign $1\dec2_raw_opcode_in[31:0] 0 - end - sync always - update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] - end - attribute \src "issuer_ls180.v:178599.3-178630.6" - process $proc$issuer_ls180.v:178599$12886 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\core_core_pc$next[63:0]$12887 $3\core_core_pc$next[63:0]$12899 - assign $0\core_dec$next[63:0]$12888 $3\core_dec$next[63:0]$12900 - assign $0\core_eint$next[0:0]$12889 $3\core_eint$next[0:0]$12901 - assign $0\core_msr$next[63:0]$12890 $3\core_msr$next[63:0]$12902 - attribute \src "issuer_ls180.v:178600.5-178600.29" - switch \initial - attribute \src "issuer_ls180.v:178600.9-178600.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" - switch \fsm_state - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 assign { } { } - assign $1\core_core_pc$next[63:0]$12891 $2\core_core_pc$next[63:0]$12895 - assign $1\core_dec$next[63:0]$12892 $2\core_dec$next[63:0]$12896 - assign $1\core_eint$next[0:0]$12893 $2\core_eint$next[0:0]$12897 - assign $1\core_msr$next[63:0]$12894 $2\core_msr$next[63:0]$12898 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" - switch \imem_f_busy_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign $2\core_core_pc$next[63:0]$12895 \core_core_pc - assign $2\core_dec$next[63:0]$12896 \core_dec - assign $2\core_eint$next[0:0]$12897 \core_eint - assign $2\core_msr$next[63:0]$12898 \core_msr - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $2\core_dec$next[63:0]$12896 $2\core_eint$next[0:0]$12897 $2\core_msr$next[63:0]$12898 $2\core_core_pc$next[63:0]$12895 } { \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } - end - case - assign $1\core_core_pc$next[63:0]$12891 \core_core_pc - assign $1\core_dec$next[63:0]$12892 \core_dec - assign $1\core_eint$next[0:0]$12893 \core_eint - assign $1\core_msr$next[63:0]$12894 \core_msr - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 assign { } { } - assign $3\core_core_pc$next[63:0]$12899 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_msr$next[63:0]$12902 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_eint$next[0:0]$12901 1'0 - assign $3\core_dec$next[63:0]$12900 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\core_core_pc$next[63:0]$12899 $1\core_core_pc$next[63:0]$12891 - assign $3\core_dec$next[63:0]$12900 $1\core_dec$next[63:0]$12892 - assign $3\core_eint$next[0:0]$12901 $1\core_eint$next[0:0]$12893 - assign $3\core_msr$next[63:0]$12902 $1\core_msr$next[63:0]$12894 - end - sync always - update \core_core_pc$next $0\core_core_pc$next[63:0]$12887 - update \core_dec$next $0\core_dec$next[63:0]$12888 - update \core_eint$next $0\core_eint$next[0:0]$12889 - update \core_msr$next $0\core_msr$next[63:0]$12890 - end - attribute \src "issuer_ls180.v:178631.3-178654.6" - process $proc$issuer_ls180.v:178631$12903 - assign { } { } - assign { } { } - assign { } { } - assign $0\ilatch$next[31:0]$12904 $3\ilatch$next[31:0]$12907 - attribute \src "issuer_ls180.v:178632.5-178632.29" - switch \initial - attribute \src "issuer_ls180.v:178632.9-178632.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" - switch \fsm_state - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'01 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 assign { } { } - assign $1\ilatch$next[31:0]$12905 $2\ilatch$next[31:0]$12906 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" - switch \imem_f_busy_o - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign $2\ilatch$next[31:0]$12906 \ilatch - attribute \src "issuer_ls180.v:0.0-0.0" - case - assign { } { } - assign $2\ilatch$next[31:0]$12906 \$107 - end - case - assign $1\ilatch$next[31:0]$12905 \ilatch - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 assign { } { } - assign $3\ilatch$next[31:0]$12907 0 - case - assign $3\ilatch$next[31:0]$12907 $1\ilatch$next[31:0]$12905 - end - sync always - update \ilatch$next $0\ilatch$next[31:0]$12904 - end - attribute \src "issuer_ls180.v:178655.3-178674.6" - process $proc$issuer_ls180.v:178655$12908 - assign { } { } - assign { } { } - assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0] - attribute \src "issuer_ls180.v:178656.5-178656.29" - switch \initial - attribute \src "issuer_ls180.v:178656.9-178656.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" - switch \fsm_state - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 assign { } { } - assign $1\core_ivalid_i[0:0] 1'1 - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'11 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 assign { } { } - assign $1\core_ivalid_i[0:0] $2\core_ivalid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:276" - switch \$111 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\core_ivalid_i[0:0] 1'1 - case - assign $2\core_ivalid_i[0:0] 1'0 - end - case - assign $1\core_ivalid_i[0:0] 1'0 - end - sync always - update \core_ivalid_i $0\core_ivalid_i[0:0] - end - attribute \src "issuer_ls180.v:178675.3-178685.6" - process $proc$issuer_ls180.v:178675$12909 - assign { } { } - assign { } { } - assign $0\core_issue_i[0:0] $1\core_issue_i[0:0] - attribute \src "issuer_ls180.v:178676.5-178676.29" - switch \initial - attribute \src "issuer_ls180.v:178676.9-178676.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" - switch \fsm_state - attribute \src "issuer_ls180.v:0.0-0.0" - case 2'10 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 assign { } { } - assign $1\core_issue_i[0:0] 1'1 - case - assign $1\core_issue_i[0:0] 1'0 - end - sync always - update \core_issue_i $0\core_issue_i[0:0] - end - attribute \src "issuer_ls180.v:178686.3-178695.6" - process $proc$issuer_ls180.v:178686$12910 - assign { } { } - assign { } { } - assign $0\core_dmi__addr[4:0] $1\core_dmi__addr[4:0] - attribute \src "issuer_ls180.v:178687.5-178687.29" - switch \initial - attribute \src "issuer_ls180.v:178687.9-178687.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - switch \dbg_d_gpr_req - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 assign { } { } - assign $1\core_dmi__addr[4:0] \dbg_d_gpr_addr [4:0] - case - assign $1\core_dmi__addr[4:0] 5'00000 - end - sync always - update \core_dmi__addr $0\core_dmi__addr[4:0] - end - attribute \src "issuer_ls180.v:178696.3-178705.6" - process $proc$issuer_ls180.v:178696$12911 - assign { } { } - assign { } { } - assign $0\core_dmi__ren[0:0] $1\core_dmi__ren[0:0] - attribute \src "issuer_ls180.v:178697.5-178697.29" - switch \initial - attribute \src "issuer_ls180.v:178697.9-178697.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - switch \dbg_d_gpr_req - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 assign { } { } - assign $1\core_dmi__ren[0:0] 1'1 - case - assign $1\core_dmi__ren[0:0] 1'0 - end - sync always - update \core_dmi__ren $0\core_dmi__ren[0:0] - end - attribute \src "issuer_ls180.v:178706.3-178714.6" - process $proc$issuer_ls180.v:178706$12912 - assign { } { } - assign { } { } - assign $0\d_reg_delay$next[0:0]$12913 $1\d_reg_delay$next[0:0]$12914 - attribute \src "issuer_ls180.v:178707.5-178707.29" - switch \initial - attribute \src "issuer_ls180.v:178707.9-178707.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 assign { } { } - assign $1\d_reg_delay$next[0:0]$12914 1'0 - case - assign $1\d_reg_delay$next[0:0]$12914 \dbg_d_gpr_req - end - sync always - update \d_reg_delay$next $0\d_reg_delay$next[0:0]$12913 - end - attribute \src "issuer_ls180.v:178715.3-178724.6" - process $proc$issuer_ls180.v:178715$12915 - assign { } { } - assign { } { } - assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] - attribute \src "issuer_ls180.v:178716.5-178716.29" - switch \initial - attribute \src "issuer_ls180.v:178716.9-178716.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:304" - switch \d_reg_delay - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 assign { } { } - assign $1\dbg_d_gpr_data[63:0] \core_dmi__data_o - case - assign $1\dbg_d_gpr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] - end - attribute \src "issuer_ls180.v:178725.3-178734.6" - process $proc$issuer_ls180.v:178725$12916 - assign { } { } - assign { } { } - assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] - attribute \src "issuer_ls180.v:178726.5-178726.29" - switch \initial - attribute \src "issuer_ls180.v:178726.9-178726.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:304" - switch \d_reg_delay - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 assign { } { } - assign $1\dbg_d_gpr_ack[0:0] 1'1 + assign $1\spr_o_ok[0:0] 1'1 case - assign $1\dbg_d_gpr_ack[0:0] 1'0 + assign $1\spr_o_ok[0:0] 1'0 end sync always - update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] + update \spr_o_ok $0\spr_o_ok[0:0] end - connect \$99 $and$issuer_ls180.v:177403$12439_Y - connect \$101 $not$issuer_ls180.v:177404$12440_Y - connect \$104 $mul$issuer_ls180.v:177405$12441_Y - connect \$103 $shr$issuer_ls180.v:177406$12442_Y [31:0] - connect \$108 $mul$issuer_ls180.v:177407$12443_Y - connect \$10 $sub$issuer_ls180.v:177408$12444_Y - connect \$107 $shr$issuer_ls180.v:177409$12445_Y [31:0] - connect \$111 $ne$issuer_ls180.v:177410$12446_Y - connect \$113 $pos$issuer_ls180.v:177411$12448_Y - connect \$115 $pos$issuer_ls180.v:177412$12450_Y - connect \$119 $sub$issuer_ls180.v:177413$12451_Y - connect \$122 $add$issuer_ls180.v:177414$12452_Y - connect \$12 $or$issuer_ls180.v:177415$12453_Y - connect \$14 $ne$issuer_ls180.v:177416$12454_Y - connect \$16 $not$issuer_ls180.v:177417$12455_Y - connect \$18 $and$issuer_ls180.v:177418$12456_Y - connect \$21 $add$issuer_ls180.v:177419$12457_Y - connect \$23 $not$issuer_ls180.v:177420$12458_Y - connect \$25 $not$issuer_ls180.v:177421$12459_Y - connect \$27 $not$issuer_ls180.v:177422$12460_Y - connect \$29 $not$issuer_ls180.v:177423$12461_Y - connect \$31 $not$issuer_ls180.v:177424$12462_Y - connect \$33 $not$issuer_ls180.v:177425$12463_Y - connect \$35 $not$issuer_ls180.v:177426$12464_Y - connect \$37 $and$issuer_ls180.v:177427$12465_Y - connect \$40 $and$issuer_ls180.v:177428$12466_Y - connect \$39 $reduce_or$issuer_ls180.v:177429$12467_Y - connect \$43 $not$issuer_ls180.v:177430$12468_Y - connect \$45 $not$issuer_ls180.v:177431$12469_Y - connect \$47 $not$issuer_ls180.v:177432$12470_Y - connect \$49 $not$issuer_ls180.v:177433$12471_Y - connect \$51 $not$issuer_ls180.v:177434$12472_Y - connect \$53 $and$issuer_ls180.v:177435$12473_Y - connect \$55 $not$issuer_ls180.v:177436$12474_Y - connect \$57 $not$issuer_ls180.v:177437$12475_Y - connect \$59 $and$issuer_ls180.v:177438$12476_Y - connect \$61 $not$issuer_ls180.v:177439$12477_Y - connect \$63 $not$issuer_ls180.v:177440$12478_Y - connect \$65 $and$issuer_ls180.v:177441$12479_Y - connect \$67 $not$issuer_ls180.v:177442$12480_Y - connect \$69 $not$issuer_ls180.v:177443$12481_Y - connect \$71 $and$issuer_ls180.v:177444$12482_Y - connect \$73 $not$issuer_ls180.v:177445$12483_Y - connect \$75 $not$issuer_ls180.v:177446$12484_Y - connect \$77 $and$issuer_ls180.v:177447$12485_Y - connect \$7 $ne$issuer_ls180.v:177448$12486_Y - connect \$79 $not$issuer_ls180.v:177449$12487_Y - connect \$81 $not$issuer_ls180.v:177450$12488_Y - connect \$83 $not$issuer_ls180.v:177451$12489_Y - connect \$85 $and$issuer_ls180.v:177452$12490_Y - connect \$87 $not$issuer_ls180.v:177453$12491_Y - connect \$89 $not$issuer_ls180.v:177454$12492_Y - connect \$91 $not$issuer_ls180.v:177455$12493_Y - connect \$93 $and$issuer_ls180.v:177456$12494_Y - connect \$95 $not$issuer_ls180.v:177457$12495_Y - connect \$97 $not$issuer_ls180.v:177458$12496_Y - connect \$9 \$10 - connect \$20 \$21 - connect \$118 \$119 - connect \$121 \$122 - connect \dbg_core_dbg_msr \dec2_cur_msr - connect \dbg_core_dbg_pc \pc - connect \dbg_terminate_i \core_core_terminate_o - connect \nia \$21 [63:0] - connect \pc_o \dec2_cur_pc - connect \core_cu_st__go_i \cu_st__rel_o_rise - connect \core_cu_ad__go_i \core_cu_ad__rel_o - connect \cu_st__rel_o_rise \$18 - connect \cu_st__rel_o_dly$next \core_cu_st__rel_o - connect \dec2_bigendian \core_bigendian_i - connect \busy_o \core_corebusy_o - connect \core_core_reset_i \$14 - connect \core_coresync_clk \clk - connect \por_clk \clk - connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src } end -attribute \src "issuer_ls180.v:178758.1-179933.10" +attribute \src "libresoc.v:46400.1-49501.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0" +attribute \top 1 +attribute \nmigen.hierarchy "test_issuer" attribute \generator "nMigen" -module \trap0 - attribute \src "issuer_ls180.v:179480.3-179481.25" - wire $0\all_rd_dly[0:0] - attribute \src "issuer_ls180.v:179478.3-179479.41" - wire $0\alu_done_dly[0:0] - attribute \src "issuer_ls180.v:179836.3-179844.6" - wire $0\alu_l_r_alu$next[0:0]$13196 - attribute \src "issuer_ls180.v:179408.3-179409.39" - wire $0\alu_l_r_alu[0:0] - attribute \src "issuer_ls180.v:179660.3-179676.6" - wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$13124 - attribute \src "issuer_ls180.v:179448.3-179449.61" - wire width 64 $0\alu_trap0_trap_op__cia[63:0] - attribute \src "issuer_ls180.v:179660.3-179676.6" - wire width 12 $0\alu_trap0_trap_op__fn_unit$next[11:0]$13125 - attribute \src "issuer_ls180.v:179442.3-179443.69" - wire width 12 $0\alu_trap0_trap_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:179660.3-179676.6" - wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$13126 - attribute \src "issuer_ls180.v:179444.3-179445.63" - wire width 32 $0\alu_trap0_trap_op__insn[31:0] - attribute \src "issuer_ls180.v:179660.3-179676.6" - wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$13127 - attribute \src "issuer_ls180.v:179440.3-179441.73" - wire width 7 $0\alu_trap0_trap_op__insn_type[6:0] - attribute \src "issuer_ls180.v:179660.3-179676.6" - wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$13128 - attribute \src "issuer_ls180.v:179450.3-179451.71" - wire $0\alu_trap0_trap_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:179660.3-179676.6" - wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$13129 - attribute \src "issuer_ls180.v:179446.3-179447.61" - wire width 64 $0\alu_trap0_trap_op__msr[63:0] - attribute \src "issuer_ls180.v:179660.3-179676.6" - wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$13130 - attribute \src "issuer_ls180.v:179454.3-179455.71" - wire width 13 $0\alu_trap0_trap_op__trapaddr[12:0] - attribute \src "issuer_ls180.v:179660.3-179676.6" - wire width 7 $0\alu_trap0_trap_op__traptype$next[6:0]$13131 - attribute \src "issuer_ls180.v:179452.3-179453.71" - wire width 7 $0\alu_trap0_trap_op__traptype[6:0] - attribute \src "issuer_ls180.v:179827.3-179835.6" - wire $0\alui_l_r_alui$next[0:0]$13193 - attribute \src "issuer_ls180.v:179410.3-179411.43" - wire $0\alui_l_r_alui[0:0] - attribute \src "issuer_ls180.v:179677.3-179698.6" - wire width 64 $0\data_r0__o$next[63:0]$13141 - attribute \src "issuer_ls180.v:179436.3-179437.37" - wire width 64 $0\data_r0__o[63:0] - attribute \src "issuer_ls180.v:179677.3-179698.6" - wire $0\data_r0__o_ok$next[0:0]$13142 - attribute \src "issuer_ls180.v:179438.3-179439.43" - wire $0\data_r0__o_ok[0:0] - attribute \src "issuer_ls180.v:179699.3-179720.6" - wire width 64 $0\data_r1__fast1$next[63:0]$13149 - attribute \src "issuer_ls180.v:179432.3-179433.45" - wire width 64 $0\data_r1__fast1[63:0] - attribute \src "issuer_ls180.v:179699.3-179720.6" - wire $0\data_r1__fast1_ok$next[0:0]$13150 - attribute \src "issuer_ls180.v:179434.3-179435.51" - wire $0\data_r1__fast1_ok[0:0] - attribute \src "issuer_ls180.v:179721.3-179742.6" - wire width 64 $0\data_r2__fast2$next[63:0]$13157 - attribute \src "issuer_ls180.v:179428.3-179429.45" - wire width 64 $0\data_r2__fast2[63:0] - attribute \src "issuer_ls180.v:179721.3-179742.6" - wire $0\data_r2__fast2_ok$next[0:0]$13158 - attribute \src "issuer_ls180.v:179430.3-179431.51" - wire $0\data_r2__fast2_ok[0:0] - attribute \src "issuer_ls180.v:179743.3-179764.6" - wire width 64 $0\data_r3__nia$next[63:0]$13165 - attribute \src "issuer_ls180.v:179424.3-179425.41" - wire width 64 $0\data_r3__nia[63:0] - attribute \src "issuer_ls180.v:179743.3-179764.6" - wire $0\data_r3__nia_ok$next[0:0]$13166 - attribute \src "issuer_ls180.v:179426.3-179427.47" - wire $0\data_r3__nia_ok[0:0] - attribute \src "issuer_ls180.v:179765.3-179786.6" - wire width 64 $0\data_r4__msr$next[63:0]$13173 - attribute \src "issuer_ls180.v:179420.3-179421.41" - wire width 64 $0\data_r4__msr[63:0] - attribute \src "issuer_ls180.v:179765.3-179786.6" - wire $0\data_r4__msr_ok$next[0:0]$13174 - attribute \src "issuer_ls180.v:179422.3-179423.47" - wire $0\data_r4__msr_ok[0:0] - attribute \src "issuer_ls180.v:179845.3-179854.6" - wire width 64 $0\dest1_o[63:0] - attribute \src "issuer_ls180.v:179855.3-179864.6" - wire width 64 $0\dest2_o[63:0] - attribute \src "issuer_ls180.v:179865.3-179874.6" - wire width 64 $0\dest3_o[63:0] - attribute \src "issuer_ls180.v:179875.3-179884.6" - wire width 64 $0\dest4_o[63:0] - attribute \src "issuer_ls180.v:179885.3-179894.6" - wire width 64 $0\dest5_o[63:0] - attribute \src "issuer_ls180.v:178759.7-178759.20" +module \test_issuer + attribute \src "libresoc.v:49107.3-49143.6" + wire $0\bigendian_i$next[0:0]$1844 + attribute \src "libresoc.v:48104.3-48105.39" + wire $0\bigendian_i[0:0] + attribute \src "libresoc.v:48831.3-48843.6" + wire width 4 $0\cia__ren[3:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 8 $0\core_asmcode$next[7:0]$1605 + attribute \src "libresoc.v:48108.3-48109.41" + wire width 8 $0\core_asmcode[7:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 64 $0\core_core_cia$next[63:0]$1606 + attribute \src "libresoc.v:48184.3-48185.43" + wire width 64 $0\core_core_cia[63:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 8 $0\core_core_cr_rd$next[7:0]$1607 + attribute \src "libresoc.v:48210.3-48211.47" + wire width 8 $0\core_core_cr_rd[7:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $0\core_core_cr_rd_ok$next[0:0]$1608 + attribute \src "libresoc.v:48212.3-48213.53" + wire $0\core_core_cr_rd_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 8 $0\core_core_cr_wr$next[7:0]$1609 + attribute \src "libresoc.v:48214.3-48215.47" + wire width 8 $0\core_core_cr_wr[7:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $0\core_core_cr_wr_ok$next[0:0]$1610 + attribute \src "libresoc.v:48216.3-48217.53" + wire $0\core_core_cr_wr_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 12 $0\core_core_fn_unit$next[11:0]$1611 + attribute \src "libresoc.v:48190.3-48191.51" + wire width 12 $0\core_core_fn_unit[11:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 2 $0\core_core_input_carry$next[1:0]$1612 + attribute \src "libresoc.v:48204.3-48205.59" + wire width 2 $0\core_core_input_carry[1:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 32 $0\core_core_insn$next[31:0]$1613 + attribute \src "libresoc.v:48186.3-48187.45" + wire width 32 $0\core_core_insn[31:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 7 $0\core_core_insn_type$next[6:0]$1614 + attribute \src "libresoc.v:48188.3-48189.55" + wire width 7 $0\core_core_insn_type[6:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $0\core_core_is_32bit$next[0:0]$1615 + attribute \src "libresoc.v:48218.3-48219.53" + wire $0\core_core_is_32bit[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $0\core_core_lk$next[0:0]$1616 + attribute \src "libresoc.v:48192.3-48193.41" + wire $0\core_core_lk[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 64 $0\core_core_msr$next[63:0]$1617 + attribute \src "libresoc.v:48182.3-48183.43" + wire width 64 $0\core_core_msr[63:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $0\core_core_oe$next[0:0]$1618 + attribute \src "libresoc.v:48198.3-48199.41" + wire $0\core_core_oe[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $0\core_core_oe_ok$next[0:0]$1619 + attribute \src "libresoc.v:48200.3-48201.47" + wire $0\core_core_oe_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $0\core_core_rc$next[0:0]$1620 + attribute \src "libresoc.v:48194.3-48195.41" + wire $0\core_core_rc[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $0\core_core_rc_ok$next[0:0]$1621 + attribute \src "libresoc.v:48196.3-48197.47" + wire $0\core_core_rc_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 13 $0\core_core_trapaddr$next[12:0]$1622 + attribute \src "libresoc.v:48208.3-48209.53" + wire width 13 $0\core_core_trapaddr[12:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 7 $0\core_core_traptype$next[6:0]$1623 + attribute \src "libresoc.v:48206.3-48207.53" + wire width 7 $0\core_core_traptype[6:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $0\core_cr_in1$next[2:0]$1624 + attribute \src "libresoc.v:48164.3-48165.39" + wire width 3 $0\core_cr_in1[2:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $0\core_cr_in1_ok$next[0:0]$1625 + attribute \src "libresoc.v:48166.3-48167.45" + wire $0\core_cr_in1_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $0\core_cr_in2$39$next[2:0]$1626 + attribute \src "libresoc.v:48172.3-48173.47" + wire width 3 $0\core_cr_in2$39[2:0]$1503 + attribute \src "libresoc.v:46722.13-46722.36" + wire width 3 $0\core_cr_in2$39[2:0]$1929 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $0\core_cr_in2$next[2:0]$1627 + attribute \src "libresoc.v:48168.3-48169.39" + wire width 3 $0\core_cr_in2[2:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $0\core_cr_in2_ok$40$next[0:0]$1628 + attribute \src "libresoc.v:48174.3-48175.53" + wire $0\core_cr_in2_ok$40[0:0]$1505 + attribute \src "libresoc.v:46730.7-46730.33" + wire $0\core_cr_in2_ok$40[0:0]$1932 + attribute \src "libresoc.v:48936.3-49042.6" + wire $0\core_cr_in2_ok$next[0:0]$1629 + attribute \src "libresoc.v:48170.3-48171.45" + wire $0\core_cr_in2_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $0\core_cr_out$next[2:0]$1630 + attribute \src "libresoc.v:48176.3-48177.39" + wire width 3 $0\core_cr_out[2:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $0\core_cr_out_ok$next[0:0]$1631 + attribute \src "libresoc.v:48178.3-48179.45" + wire $0\core_cr_out_ok[0:0] + attribute \src "libresoc.v:49395.3-49426.6" + wire width 64 $0\core_dec$next[63:0]$1882 + attribute \src "libresoc.v:48094.3-48095.33" + wire width 64 $0\core_dec[63:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 5 $0\core_ea$next[4:0]$1632 + attribute \src "libresoc.v:48116.3-48117.31" + wire width 5 $0\core_ea[4:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $0\core_ea_ok$next[0:0]$1633 + attribute \src "libresoc.v:48118.3-48119.37" + wire $0\core_ea_ok[0:0] + attribute \src "libresoc.v:49395.3-49426.6" + wire $0\core_eint$next[0:0]$1883 + attribute \src "libresoc.v:48246.3-48247.35" + wire $0\core_eint[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $0\core_fast1$next[2:0]$1634 + attribute \src "libresoc.v:48146.3-48147.37" + wire width 3 $0\core_fast1[2:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $0\core_fast1_ok$next[0:0]$1635 + attribute \src "libresoc.v:48148.3-48149.43" + wire $0\core_fast1_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $0\core_fast2$next[2:0]$1636 + attribute \src "libresoc.v:48150.3-48151.37" + wire width 3 $0\core_fast2[2:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $0\core_fast2_ok$next[0:0]$1637 + attribute \src "libresoc.v:48152.3-48153.43" + wire $0\core_fast2_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $0\core_fasto1$next[2:0]$1638 + attribute \src "libresoc.v:48154.3-48155.39" + wire width 3 $0\core_fasto1[2:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $0\core_fasto1_ok$next[0:0]$1639 + attribute \src "libresoc.v:48156.3-48157.45" + wire $0\core_fasto1_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $0\core_fasto2$next[2:0]$1640 + attribute \src "libresoc.v:48160.3-48161.39" + wire width 3 $0\core_fasto2[2:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $0\core_fasto2_ok$next[0:0]$1641 + attribute \src "libresoc.v:48162.3-48163.45" + wire $0\core_fasto2_ok[0:0] + attribute \src "libresoc.v:49395.3-49426.6" + wire width 64 $0\core_msr$next[63:0]$1884 + attribute \src "libresoc.v:48244.3-48245.33" + wire width 64 $0\core_msr[63:0] + attribute \src "libresoc.v:49395.3-49426.6" + wire width 64 $0\core_pc$next[63:0]$1885 + attribute \src "libresoc.v:48224.3-48225.31" + wire width 64 $0\core_pc[63:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 5 $0\core_reg1$next[4:0]$1642 + attribute \src "libresoc.v:48120.3-48121.35" + wire width 5 $0\core_reg1[4:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $0\core_reg1_ok$next[0:0]$1643 + attribute \src "libresoc.v:48122.3-48123.41" + wire $0\core_reg1_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 5 $0\core_reg2$next[4:0]$1644 + attribute \src "libresoc.v:48124.3-48125.35" + wire width 5 $0\core_reg2[4:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $0\core_reg2_ok$next[0:0]$1645 + attribute \src "libresoc.v:48126.3-48127.41" + wire $0\core_reg2_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 5 $0\core_reg3$next[4:0]$1646 + attribute \src "libresoc.v:48128.3-48129.35" + wire width 5 $0\core_reg3[4:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $0\core_reg3_ok$next[0:0]$1647 + attribute \src "libresoc.v:48130.3-48131.41" + wire $0\core_reg3_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 5 $0\core_rego$next[4:0]$1648 + attribute \src "libresoc.v:48110.3-48111.35" + wire width 5 $0\core_rego[4:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $0\core_rego_ok$next[0:0]$1649 + attribute \src "libresoc.v:48112.3-48113.41" + wire $0\core_rego_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 10 $0\core_spr1$next[9:0]$1650 + attribute \src "libresoc.v:48138.3-48139.35" + wire width 10 $0\core_spr1[9:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $0\core_spr1_ok$next[0:0]$1651 + attribute \src "libresoc.v:48140.3-48141.41" + wire $0\core_spr1_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 10 $0\core_spro$next[9:0]$1652 + attribute \src "libresoc.v:48132.3-48133.35" + wire width 10 $0\core_spro[9:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $0\core_spro_ok$next[0:0]$1653 + attribute \src "libresoc.v:48134.3-48135.41" + wire $0\core_spro_ok[0:0] + attribute \src "libresoc.v:49317.3-49335.6" + wire $0\core_stopped_i[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $0\core_xer_in$next[2:0]$1654 + attribute \src "libresoc.v:48142.3-48143.39" + wire width 3 $0\core_xer_in[2:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $0\core_xer_out$next[0:0]$1655 + attribute \src "libresoc.v:48144.3-48145.41" + wire $0\core_xer_out[0:0] + attribute \src "libresoc.v:48226.3-48227.30" + wire $0\cu_st__rel_o_dly[0:0] + attribute \src "libresoc.v:48588.3-48596.6" + wire $0\d_cr_delay$next[0:0]$1558 + attribute \src "libresoc.v:48158.3-48159.37" + wire $0\d_cr_delay[0:0] + attribute \src "libresoc.v:48549.3-48557.6" + wire $0\d_reg_delay$next[0:0]$1552 + attribute \src "libresoc.v:48180.3-48181.39" + wire $0\d_reg_delay[0:0] + attribute \src "libresoc.v:48627.3-48635.6" + wire $0\d_xer_delay$next[0:0]$1564 + attribute \src "libresoc.v:48136.3-48137.39" + wire $0\d_xer_delay[0:0] + attribute \src "libresoc.v:48865.3-48885.6" + wire width 64 $0\data_i[63:0] + attribute \src "libresoc.v:49336.3-49354.6" + wire $0\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:48607.3-48616.6" + wire $0\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:48597.3-48606.6" + wire width 64 $0\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:48568.3-48577.6" + wire $0\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:48558.3-48567.6" + wire width 64 $0\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:48646.3-48655.6" + wire $0\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:48636.3-48645.6" + wire width 64 $0\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:48500.3-48508.6" + wire width 4 $0\dbg_dmi_addr_i$next[3:0]$1543 + attribute \src "libresoc.v:48242.3-48243.45" + wire width 4 $0\dbg_dmi_addr_i[3:0] + attribute \src "libresoc.v:48902.3-48910.6" + wire width 64 $0\dbg_dmi_din$next[63:0]$1597 + attribute \src "libresoc.v:48236.3-48237.39" + wire width 64 $0\dbg_dmi_din[63:0] + attribute \src "libresoc.v:48509.3-48517.6" + wire $0\dbg_dmi_req_i$next[0:0]$1546 + attribute \src "libresoc.v:48240.3-48241.43" + wire $0\dbg_dmi_req_i[0:0] + attribute \src "libresoc.v:48797.3-48805.6" + wire $0\dbg_dmi_we_i$next[0:0]$1586 + attribute \src "libresoc.v:48238.3-48239.41" + wire $0\dbg_dmi_we_i[0:0] + attribute \src "libresoc.v:48770.3-48785.6" + wire width 64 $0\dec2_cur_dec$next[63:0]$1581 + attribute \src "libresoc.v:48092.3-48093.41" + wire width 64 $0\dec2_cur_dec[63:0] + attribute \src "libresoc.v:49061.3-49069.6" + wire $0\dec2_cur_eint$next[0:0]$1835 + attribute \src "libresoc.v:48230.3-48231.43" + wire $0\dec2_cur_eint[0:0] + attribute \src "libresoc.v:49355.3-49375.6" + wire width 64 $0\dec2_cur_msr$next[63:0]$1876 + attribute \src "libresoc.v:48096.3-48097.41" + wire width 64 $0\dec2_cur_msr[63:0] + attribute \src "libresoc.v:49210.3-49230.6" + wire width 64 $0\dec2_cur_pc$next[63:0]$1853 + attribute \src "libresoc.v:48102.3-48103.39" + wire width 64 $0\dec2_cur_pc[63:0] + attribute \src "libresoc.v:49376.3-49394.6" + wire width 32 $0\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:49307.3-49316.6" + wire width 2 $0\delay$next[1:0]$1871 + attribute \src "libresoc.v:48228.3-48229.27" + wire width 2 $0\delay[1:0] + attribute \src "libresoc.v:48529.3-48538.6" + wire width 5 $0\dmi__addr[4:0] + attribute \src "libresoc.v:48539.3-48548.6" + wire $0\dmi__ren[0:0] + attribute \src "libresoc.v:48686.3-48713.6" + wire width 2 $0\fsm_state$115$next[1:0]$1571 + attribute \src "libresoc.v:48114.3-48115.45" + wire width 2 $0\fsm_state$115[1:0]$1473 + attribute \src "libresoc.v:47637.13-47637.35" + wire width 2 $0\fsm_state$115[1:0]$1978 + attribute \src "libresoc.v:49261.3-49306.6" + wire width 2 $0\fsm_state$next[1:0]$1864 + attribute \src "libresoc.v:48098.3-48099.35" + wire width 2 $0\fsm_state[1:0] + attribute \src "libresoc.v:48578.3-48587.6" + wire width 8 $0\full_rd2__ren[7:0] + attribute \src "libresoc.v:48617.3-48626.6" + wire width 3 $0\full_rd__ren[2:0] + attribute \src "libresoc.v:49427.3-49450.6" + wire width 32 $0\ilatch$next[31:0]$1899 + attribute \src "libresoc.v:48202.3-48203.29" + wire width 32 $0\ilatch[31:0] + attribute \src "libresoc.v:49144.3-49159.6" + wire width 48 $0\imem_a_pc_i[47:0] + attribute \src "libresoc.v:49160.3-49184.6" + wire $0\imem_a_valid_i[0:0] + attribute \src "libresoc.v:49185.3-49209.6" + wire $0\imem_f_valid_i[0:0] + attribute \src "libresoc.v:46401.7-46401.20" wire $0\initial[0:0] - attribute \src "issuer_ls180.v:179615.3-179623.6" - wire $0\opc_l_r_opc$next[0:0]$13109 - attribute \src "issuer_ls180.v:179464.3-179465.39" - wire $0\opc_l_r_opc[0:0] - attribute \src "issuer_ls180.v:179606.3-179614.6" - wire $0\opc_l_s_opc$next[0:0]$13106 - attribute \src "issuer_ls180.v:179466.3-179467.39" - wire $0\opc_l_s_opc[0:0] - attribute \src "issuer_ls180.v:179895.3-179903.6" - wire width 5 $0\prev_wr_go$next[4:0]$13204 - attribute \src "issuer_ls180.v:179476.3-179477.37" - wire width 5 $0\prev_wr_go[4:0] - attribute \src "issuer_ls180.v:179560.3-179569.6" - wire $0\req_done[0:0] - attribute \src "issuer_ls180.v:179651.3-179659.6" - wire width 5 $0\req_l_r_req$next[4:0]$13121 - attribute \src "issuer_ls180.v:179456.3-179457.39" - wire width 5 $0\req_l_r_req[4:0] - attribute \src "issuer_ls180.v:179642.3-179650.6" - wire width 5 $0\req_l_s_req$next[4:0]$13118 - attribute \src "issuer_ls180.v:179458.3-179459.39" - wire width 5 $0\req_l_s_req[4:0] - attribute \src "issuer_ls180.v:179579.3-179587.6" - wire $0\rok_l_r_rdok$next[0:0]$13097 - attribute \src "issuer_ls180.v:179472.3-179473.41" - wire $0\rok_l_r_rdok[0:0] - attribute \src "issuer_ls180.v:179570.3-179578.6" - wire $0\rok_l_s_rdok$next[0:0]$13094 - attribute \src "issuer_ls180.v:179474.3-179475.41" - wire $0\rok_l_s_rdok[0:0] - attribute \src "issuer_ls180.v:179597.3-179605.6" - wire $0\rst_l_r_rst$next[0:0]$13103 - attribute \src "issuer_ls180.v:179468.3-179469.39" - wire $0\rst_l_r_rst[0:0] - attribute \src "issuer_ls180.v:179588.3-179596.6" - wire $0\rst_l_s_rst$next[0:0]$13100 - attribute \src "issuer_ls180.v:179470.3-179471.39" - wire $0\rst_l_s_rst[0:0] - attribute \src "issuer_ls180.v:179633.3-179641.6" - wire width 4 $0\src_l_r_src$next[3:0]$13115 - attribute \src "issuer_ls180.v:179460.3-179461.39" - wire width 4 $0\src_l_r_src[3:0] - attribute \src "issuer_ls180.v:179624.3-179632.6" - wire width 4 $0\src_l_s_src$next[3:0]$13112 - attribute \src "issuer_ls180.v:179462.3-179463.39" - wire width 4 $0\src_l_s_src[3:0] - attribute \src "issuer_ls180.v:179787.3-179796.6" - wire width 64 $0\src_r0$next[63:0]$13181 - attribute \src "issuer_ls180.v:179418.3-179419.29" - wire width 64 $0\src_r0[63:0] - attribute \src "issuer_ls180.v:179797.3-179806.6" - wire width 64 $0\src_r1$next[63:0]$13184 - attribute \src "issuer_ls180.v:179416.3-179417.29" - wire width 64 $0\src_r1[63:0] - attribute \src "issuer_ls180.v:179807.3-179816.6" - wire width 64 $0\src_r2$next[63:0]$13187 - attribute \src "issuer_ls180.v:179414.3-179415.29" - wire width 64 $0\src_r2[63:0] - attribute \src "issuer_ls180.v:179817.3-179826.6" - wire width 64 $0\src_r3$next[63:0]$13190 - attribute \src "issuer_ls180.v:179412.3-179413.29" - wire width 64 $0\src_r3[63:0] - attribute \src "issuer_ls180.v:178885.7-178885.24" - wire $1\all_rd_dly[0:0] - attribute \src "issuer_ls180.v:178895.7-178895.26" - wire $1\alu_done_dly[0:0] - attribute \src "issuer_ls180.v:179836.3-179844.6" - wire $1\alu_l_r_alu$next[0:0]$13197 - attribute \src "issuer_ls180.v:178903.7-178903.25" - wire $1\alu_l_r_alu[0:0] - attribute \src "issuer_ls180.v:179660.3-179676.6" - wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$13132 - attribute \src "issuer_ls180.v:178939.14-178939.59" - wire width 64 $1\alu_trap0_trap_op__cia[63:0] - attribute \src "issuer_ls180.v:179660.3-179676.6" - wire width 12 $1\alu_trap0_trap_op__fn_unit$next[11:0]$13133 - attribute \src "issuer_ls180.v:178956.14-178956.50" - wire width 12 $1\alu_trap0_trap_op__fn_unit[11:0] - attribute \src "issuer_ls180.v:179660.3-179676.6" - wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$13134 - attribute \src "issuer_ls180.v:178960.14-178960.45" - wire width 32 $1\alu_trap0_trap_op__insn[31:0] - attribute \src "issuer_ls180.v:179660.3-179676.6" - wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$13135 - attribute \src "issuer_ls180.v:179038.13-179038.49" - wire width 7 $1\alu_trap0_trap_op__insn_type[6:0] - attribute \src "issuer_ls180.v:179660.3-179676.6" - wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$13136 - attribute \src "issuer_ls180.v:179042.7-179042.41" - wire $1\alu_trap0_trap_op__is_32bit[0:0] - attribute \src "issuer_ls180.v:179660.3-179676.6" - wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$13137 - attribute \src "issuer_ls180.v:179046.14-179046.59" - wire width 64 $1\alu_trap0_trap_op__msr[63:0] - attribute \src "issuer_ls180.v:179660.3-179676.6" - wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$13138 - attribute \src "issuer_ls180.v:179050.14-179050.52" - wire width 13 $1\alu_trap0_trap_op__trapaddr[12:0] - attribute \src "issuer_ls180.v:179660.3-179676.6" - wire width 7 $1\alu_trap0_trap_op__traptype$next[6:0]$13139 - attribute \src "issuer_ls180.v:179054.13-179054.48" - wire width 7 $1\alu_trap0_trap_op__traptype[6:0] - attribute \src "issuer_ls180.v:179827.3-179835.6" - wire $1\alui_l_r_alui$next[0:0]$13194 - attribute \src "issuer_ls180.v:179060.7-179060.27" - wire $1\alui_l_r_alui[0:0] - attribute \src "issuer_ls180.v:179677.3-179698.6" - wire width 64 $1\data_r0__o$next[63:0]$13143 - attribute \src "issuer_ls180.v:179092.14-179092.47" - wire width 64 $1\data_r0__o[63:0] - attribute \src "issuer_ls180.v:179677.3-179698.6" - wire $1\data_r0__o_ok$next[0:0]$13144 - attribute \src "issuer_ls180.v:179096.7-179096.27" - wire $1\data_r0__o_ok[0:0] - attribute \src "issuer_ls180.v:179699.3-179720.6" - wire width 64 $1\data_r1__fast1$next[63:0]$13151 - attribute \src "issuer_ls180.v:179100.14-179100.51" - wire width 64 $1\data_r1__fast1[63:0] - attribute \src "issuer_ls180.v:179699.3-179720.6" - wire $1\data_r1__fast1_ok$next[0:0]$13152 - attribute \src "issuer_ls180.v:179104.7-179104.31" - wire $1\data_r1__fast1_ok[0:0] - attribute \src "issuer_ls180.v:179721.3-179742.6" - wire width 64 $1\data_r2__fast2$next[63:0]$13159 - attribute \src "issuer_ls180.v:179108.14-179108.51" - wire width 64 $1\data_r2__fast2[63:0] - attribute \src "issuer_ls180.v:179721.3-179742.6" - wire $1\data_r2__fast2_ok$next[0:0]$13160 - attribute \src "issuer_ls180.v:179112.7-179112.31" - wire $1\data_r2__fast2_ok[0:0] - attribute \src "issuer_ls180.v:179743.3-179764.6" - wire width 64 $1\data_r3__nia$next[63:0]$13167 - attribute \src "issuer_ls180.v:179116.14-179116.49" - wire width 64 $1\data_r3__nia[63:0] - attribute \src "issuer_ls180.v:179743.3-179764.6" - wire $1\data_r3__nia_ok$next[0:0]$13168 - attribute \src "issuer_ls180.v:179120.7-179120.29" - wire $1\data_r3__nia_ok[0:0] - attribute \src "issuer_ls180.v:179765.3-179786.6" - wire width 64 $1\data_r4__msr$next[63:0]$13175 - attribute \src "issuer_ls180.v:179124.14-179124.49" - wire width 64 $1\data_r4__msr[63:0] - attribute \src "issuer_ls180.v:179765.3-179786.6" - wire $1\data_r4__msr_ok$next[0:0]$13176 - attribute \src "issuer_ls180.v:179128.7-179128.29" - wire $1\data_r4__msr_ok[0:0] - attribute \src "issuer_ls180.v:179845.3-179854.6" - wire width 64 $1\dest1_o[63:0] - attribute \src "issuer_ls180.v:179855.3-179864.6" - wire width 64 $1\dest2_o[63:0] - attribute \src "issuer_ls180.v:179865.3-179874.6" - wire width 64 $1\dest3_o[63:0] - attribute \src "issuer_ls180.v:179875.3-179884.6" - wire width 64 $1\dest4_o[63:0] - attribute \src "issuer_ls180.v:179885.3-179894.6" - wire width 64 $1\dest5_o[63:0] - attribute \src "issuer_ls180.v:179615.3-179623.6" - wire $1\opc_l_r_opc$next[0:0]$13110 - attribute \src "issuer_ls180.v:179159.7-179159.25" - wire $1\opc_l_r_opc[0:0] - attribute \src "issuer_ls180.v:179606.3-179614.6" - wire $1\opc_l_s_opc$next[0:0]$13107 - attribute \src "issuer_ls180.v:179163.7-179163.25" - wire $1\opc_l_s_opc[0:0] - attribute \src "issuer_ls180.v:179895.3-179903.6" - wire width 5 $1\prev_wr_go$next[4:0]$13205 - attribute \src "issuer_ls180.v:179270.13-179270.31" - wire width 5 $1\prev_wr_go[4:0] - attribute \src "issuer_ls180.v:179560.3-179569.6" - wire $1\req_done[0:0] - attribute \src "issuer_ls180.v:179651.3-179659.6" - wire width 5 $1\req_l_r_req$next[4:0]$13122 - attribute \src "issuer_ls180.v:179278.13-179278.32" - wire width 5 $1\req_l_r_req[4:0] - attribute \src "issuer_ls180.v:179642.3-179650.6" - wire width 5 $1\req_l_s_req$next[4:0]$13119 - attribute \src "issuer_ls180.v:179282.13-179282.32" - wire width 5 $1\req_l_s_req[4:0] - attribute \src "issuer_ls180.v:179579.3-179587.6" - wire $1\rok_l_r_rdok$next[0:0]$13098 - attribute \src "issuer_ls180.v:179294.7-179294.26" - wire $1\rok_l_r_rdok[0:0] - attribute \src "issuer_ls180.v:179570.3-179578.6" - wire $1\rok_l_s_rdok$next[0:0]$13095 - attribute \src "issuer_ls180.v:179298.7-179298.26" - wire $1\rok_l_s_rdok[0:0] - attribute \src "issuer_ls180.v:179597.3-179605.6" - wire $1\rst_l_r_rst$next[0:0]$13104 - attribute \src "issuer_ls180.v:179302.7-179302.25" - wire $1\rst_l_r_rst[0:0] - attribute \src "issuer_ls180.v:179588.3-179596.6" - wire $1\rst_l_s_rst$next[0:0]$13101 - attribute \src "issuer_ls180.v:179306.7-179306.25" - wire $1\rst_l_s_rst[0:0] - attribute \src "issuer_ls180.v:179633.3-179641.6" - wire width 4 $1\src_l_r_src$next[3:0]$13116 - attribute \src "issuer_ls180.v:179322.13-179322.31" - wire width 4 $1\src_l_r_src[3:0] - attribute \src "issuer_ls180.v:179624.3-179632.6" - wire width 4 $1\src_l_s_src$next[3:0]$13113 - attribute \src "issuer_ls180.v:179326.13-179326.31" - wire width 4 $1\src_l_s_src[3:0] - attribute \src "issuer_ls180.v:179787.3-179796.6" - wire width 64 $1\src_r0$next[63:0]$13182 - attribute \src "issuer_ls180.v:179330.14-179330.43" - wire width 64 $1\src_r0[63:0] - attribute \src "issuer_ls180.v:179797.3-179806.6" - wire width 64 $1\src_r1$next[63:0]$13185 - attribute \src "issuer_ls180.v:179334.14-179334.43" - wire width 64 $1\src_r1[63:0] - attribute \src "issuer_ls180.v:179807.3-179816.6" - wire width 64 $1\src_r2$next[63:0]$13188 - attribute \src "issuer_ls180.v:179338.14-179338.43" - wire width 64 $1\src_r2[63:0] - attribute \src "issuer_ls180.v:179817.3-179826.6" - wire width 64 $1\src_r3$next[63:0]$13191 - attribute \src "issuer_ls180.v:179342.14-179342.43" - wire width 64 $1\src_r3[63:0] - attribute \src "issuer_ls180.v:179677.3-179698.6" - wire width 64 $2\data_r0__o$next[63:0]$13145 - attribute \src "issuer_ls180.v:179677.3-179698.6" - wire $2\data_r0__o_ok$next[0:0]$13146 - attribute \src "issuer_ls180.v:179699.3-179720.6" - wire width 64 $2\data_r1__fast1$next[63:0]$13153 - attribute \src "issuer_ls180.v:179699.3-179720.6" - wire $2\data_r1__fast1_ok$next[0:0]$13154 - attribute \src "issuer_ls180.v:179721.3-179742.6" - wire width 64 $2\data_r2__fast2$next[63:0]$13161 - attribute \src "issuer_ls180.v:179721.3-179742.6" - wire $2\data_r2__fast2_ok$next[0:0]$13162 - attribute \src "issuer_ls180.v:179743.3-179764.6" - wire width 64 $2\data_r3__nia$next[63:0]$13169 - attribute \src "issuer_ls180.v:179743.3-179764.6" - wire $2\data_r3__nia_ok$next[0:0]$13170 - attribute \src "issuer_ls180.v:179765.3-179786.6" - wire width 64 $2\data_r4__msr$next[63:0]$13177 - attribute \src "issuer_ls180.v:179765.3-179786.6" - wire $2\data_r4__msr_ok$next[0:0]$13178 - attribute \src "issuer_ls180.v:179677.3-179698.6" - wire $3\data_r0__o_ok$next[0:0]$13147 - attribute \src "issuer_ls180.v:179699.3-179720.6" - wire $3\data_r1__fast1_ok$next[0:0]$13155 - attribute \src "issuer_ls180.v:179721.3-179742.6" - wire $3\data_r2__fast2_ok$next[0:0]$13163 - attribute \src "issuer_ls180.v:179743.3-179764.6" - wire $3\data_r3__nia_ok$next[0:0]$13171 - attribute \src "issuer_ls180.v:179765.3-179786.6" - wire $3\data_r4__msr_ok$next[0:0]$13179 - attribute \src "issuer_ls180.v:179348.18-179348.112" - wire width 4 $and$issuer_ls180.v:179348$12995_Y - attribute \src "issuer_ls180.v:179349.19-179349.125" - wire $and$issuer_ls180.v:179349$12996_Y - attribute \src "issuer_ls180.v:179350.19-179350.125" - wire $and$issuer_ls180.v:179350$12997_Y - attribute \src "issuer_ls180.v:179351.19-179351.125" - wire $and$issuer_ls180.v:179351$12998_Y - attribute \src "issuer_ls180.v:179352.19-179352.125" - wire $and$issuer_ls180.v:179352$12999_Y - attribute \src "issuer_ls180.v:179353.19-179353.125" - wire $and$issuer_ls180.v:179353$13000_Y - attribute \src "issuer_ls180.v:179354.19-179354.157" - wire width 5 $and$issuer_ls180.v:179354$13001_Y - attribute \src "issuer_ls180.v:179355.19-179355.121" - wire width 5 $and$issuer_ls180.v:179355$13002_Y - attribute \src "issuer_ls180.v:179356.19-179356.127" - wire $and$issuer_ls180.v:179356$13003_Y - attribute \src "issuer_ls180.v:179357.19-179357.127" - wire $and$issuer_ls180.v:179357$13004_Y - attribute \src "issuer_ls180.v:179358.18-179358.110" - wire $and$issuer_ls180.v:179358$13005_Y - attribute \src "issuer_ls180.v:179359.19-179359.127" - wire $and$issuer_ls180.v:179359$13006_Y - attribute \src "issuer_ls180.v:179360.19-179360.127" - wire $and$issuer_ls180.v:179360$13007_Y - attribute \src "issuer_ls180.v:179361.19-179361.127" - wire $and$issuer_ls180.v:179361$13008_Y - attribute \src "issuer_ls180.v:179363.18-179363.98" - wire $and$issuer_ls180.v:179363$13010_Y - attribute \src "issuer_ls180.v:179365.18-179365.100" - wire $and$issuer_ls180.v:179365$13012_Y - attribute \src "issuer_ls180.v:179366.18-179366.171" - wire width 5 $and$issuer_ls180.v:179366$13013_Y - attribute \src "issuer_ls180.v:179368.18-179368.119" - wire width 5 $and$issuer_ls180.v:179368$13015_Y - attribute \src "issuer_ls180.v:179371.18-179371.116" - wire $and$issuer_ls180.v:179371$13018_Y - attribute \src "issuer_ls180.v:179375.17-179375.123" - wire $and$issuer_ls180.v:179375$13022_Y - attribute \src "issuer_ls180.v:179377.18-179377.113" - wire $and$issuer_ls180.v:179377$13024_Y - attribute \src "issuer_ls180.v:179378.18-179378.125" - wire width 5 $and$issuer_ls180.v:179378$13025_Y - attribute \src "issuer_ls180.v:179380.18-179380.112" - wire $and$issuer_ls180.v:179380$13027_Y - attribute \src "issuer_ls180.v:179382.18-179382.127" - wire $and$issuer_ls180.v:179382$13029_Y - attribute \src "issuer_ls180.v:179383.18-179383.127" - wire $and$issuer_ls180.v:179383$13030_Y - attribute \src "issuer_ls180.v:179384.18-179384.117" - wire $and$issuer_ls180.v:179384$13031_Y - attribute \src "issuer_ls180.v:179389.18-179389.131" - wire $and$issuer_ls180.v:179389$13036_Y - attribute \src "issuer_ls180.v:179390.18-179390.124" - wire width 5 $and$issuer_ls180.v:179390$13037_Y - attribute \src "issuer_ls180.v:179393.18-179393.116" - wire $and$issuer_ls180.v:179393$13040_Y - attribute \src "issuer_ls180.v:179394.18-179394.120" - wire $and$issuer_ls180.v:179394$13041_Y - attribute \src "issuer_ls180.v:179395.18-179395.120" - wire $and$issuer_ls180.v:179395$13042_Y - attribute \src "issuer_ls180.v:179396.18-179396.118" - wire $and$issuer_ls180.v:179396$13043_Y - attribute \src "issuer_ls180.v:179397.18-179397.118" - wire $and$issuer_ls180.v:179397$13044_Y - attribute \src "issuer_ls180.v:179403.18-179403.135" - wire $and$issuer_ls180.v:179403$13050_Y - attribute \src "issuer_ls180.v:179404.18-179404.133" - wire $and$issuer_ls180.v:179404$13051_Y - attribute \src "issuer_ls180.v:179405.18-179405.160" - wire width 4 $and$issuer_ls180.v:179405$13052_Y - attribute \src "issuer_ls180.v:179406.18-179406.112" - wire width 4 $and$issuer_ls180.v:179406$13053_Y - attribute \src "issuer_ls180.v:179379.18-179379.113" - wire $eq$issuer_ls180.v:179379$13026_Y - attribute \src "issuer_ls180.v:179381.18-179381.119" - wire $eq$issuer_ls180.v:179381$13028_Y - attribute \src "issuer_ls180.v:179362.18-179362.97" - wire $not$issuer_ls180.v:179362$13009_Y - attribute \src "issuer_ls180.v:179364.18-179364.99" - wire $not$issuer_ls180.v:179364$13011_Y - attribute \src "issuer_ls180.v:179367.18-179367.113" - wire width 5 $not$issuer_ls180.v:179367$13014_Y - attribute \src "issuer_ls180.v:179370.18-179370.106" - wire $not$issuer_ls180.v:179370$13017_Y - attribute \src "issuer_ls180.v:179376.18-179376.121" - wire $not$issuer_ls180.v:179376$13023_Y - attribute \src "issuer_ls180.v:179391.17-179391.113" - wire width 4 $not$issuer_ls180.v:179391$13038_Y - attribute \src "issuer_ls180.v:179407.18-179407.114" - wire width 4 $not$issuer_ls180.v:179407$13054_Y - attribute \src "issuer_ls180.v:179374.18-179374.112" - wire $or$issuer_ls180.v:179374$13021_Y - attribute \src "issuer_ls180.v:179385.18-179385.122" - wire $or$issuer_ls180.v:179385$13032_Y - attribute \src "issuer_ls180.v:179386.18-179386.124" - wire $or$issuer_ls180.v:179386$13033_Y - attribute \src "issuer_ls180.v:179387.18-179387.181" - wire width 5 $or$issuer_ls180.v:179387$13034_Y - attribute \src "issuer_ls180.v:179388.18-179388.168" - wire width 4 $or$issuer_ls180.v:179388$13035_Y - attribute \src "issuer_ls180.v:179392.18-179392.120" - wire width 5 $or$issuer_ls180.v:179392$13039_Y - attribute \src "issuer_ls180.v:179402.17-179402.117" - wire width 4 $or$issuer_ls180.v:179402$13049_Y - attribute \src "issuer_ls180.v:179347.17-179347.104" - wire $reduce_and$issuer_ls180.v:179347$12994_Y - attribute \src "issuer_ls180.v:179369.18-179369.106" - wire $reduce_or$issuer_ls180.v:179369$13016_Y - attribute \src "issuer_ls180.v:179372.18-179372.113" - wire $reduce_or$issuer_ls180.v:179372$13019_Y - attribute \src "issuer_ls180.v:179373.18-179373.112" - wire $reduce_or$issuer_ls180.v:179373$13020_Y - attribute \src "issuer_ls180.v:179398.18-179398.118" - wire width 64 $ternary$issuer_ls180.v:179398$13045_Y - attribute \src "issuer_ls180.v:179399.18-179399.118" - wire width 64 $ternary$issuer_ls180.v:179399$13046_Y - attribute \src "issuer_ls180.v:179400.18-179400.118" - wire width 64 $ternary$issuer_ls180.v:179400$13047_Y - attribute \src "issuer_ls180.v:179401.18-179401.118" - wire width 64 $ternary$issuer_ls180.v:179401$13048_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire \$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire \$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire \$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire \$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + attribute \src "libresoc.v:48725.3-48739.6" + wire width 3 $0\issue__addr$119[2:0]$1576 + attribute \src "libresoc.v:48656.3-48670.6" + wire width 3 $0\issue__addr[2:0] + attribute \src "libresoc.v:48755.3-48769.6" + wire width 64 $0\issue__data_i[63:0] + attribute \src "libresoc.v:48671.3-48685.6" + wire $0\issue__ren[0:0] + attribute \src "libresoc.v:48740.3-48754.6" + wire $0\issue__wen[0:0] + attribute \src "libresoc.v:48518.3-48528.6" + wire $0\issue_i[0:0] + attribute \src "libresoc.v:49451.3-49470.6" + wire $0\ivalid_i[0:0] + attribute \src "libresoc.v:49043.3-49051.6" + wire $0\jtag_dmi0_ack_o$next[0:0]$1829 + attribute \src "libresoc.v:48234.3-48235.47" + wire $0\jtag_dmi0_ack_o[0:0] + attribute \src "libresoc.v:49052.3-49060.6" + wire width 64 $0\jtag_dmi0_dout$next[63:0]$1832 + attribute \src "libresoc.v:48232.3-48233.45" + wire width 64 $0\jtag_dmi0_dout[63:0] + attribute \src "libresoc.v:48886.3-48901.6" + wire width 4 $0\msr__ren[3:0] + attribute \src "libresoc.v:49231.3-49260.6" + wire $0\msr_read$next[0:0]$1858 + attribute \src "libresoc.v:48100.3-48101.33" + wire $0\msr_read[0:0] + attribute \src "libresoc.v:48714.3-48724.6" + wire width 64 $0\new_dec[63:0] + attribute \src "libresoc.v:48786.3-48796.6" + wire width 64 $0\new_tb[63:0] + attribute \src "libresoc.v:48815.3-48830.6" + wire width 64 $0\pc[63:0] + attribute \src "libresoc.v:48911.3-48935.6" + wire $0\pc_changed$next[0:0]$1600 + attribute \src "libresoc.v:48220.3-48221.37" + wire $0\pc_changed[0:0] + attribute \src "libresoc.v:48806.3-48814.6" + wire $0\pc_ok_delay$next[0:0]$1589 + attribute \src "libresoc.v:48222.3-48223.39" + wire $0\pc_ok_delay[0:0] + attribute \src "libresoc.v:49070.3-49106.6" + wire width 32 $0\raw_insn_i$next[31:0]$1838 + attribute \src "libresoc.v:48106.3-48107.37" + wire width 32 $0\raw_insn_i[31:0] + attribute \src "libresoc.v:48844.3-48864.6" + wire width 4 $0\wen[3:0] + attribute \src "libresoc.v:49107.3-49143.6" + wire $1\bigendian_i$next[0:0]$1845 + attribute \src "libresoc.v:46531.7-46531.25" + wire $1\bigendian_i[0:0] + attribute \src "libresoc.v:48831.3-48843.6" + wire width 4 $1\cia__ren[3:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 8 $1\core_asmcode$next[7:0]$1656 + attribute \src "libresoc.v:46543.13-46543.33" + wire width 8 $1\core_asmcode[7:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 64 $1\core_core_cia$next[63:0]$1657 + attribute \src "libresoc.v:46549.14-46549.50" + wire width 64 $1\core_core_cia[63:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 8 $1\core_core_cr_rd$next[7:0]$1658 + attribute \src "libresoc.v:46553.13-46553.36" + wire width 8 $1\core_core_cr_rd[7:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $1\core_core_cr_rd_ok$next[0:0]$1659 + attribute \src "libresoc.v:46557.7-46557.32" + wire $1\core_core_cr_rd_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 8 $1\core_core_cr_wr$next[7:0]$1660 + attribute \src "libresoc.v:46561.13-46561.36" + wire width 8 $1\core_core_cr_wr[7:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $1\core_core_cr_wr_ok$next[0:0]$1661 + attribute \src "libresoc.v:46565.7-46565.32" + wire $1\core_core_cr_wr_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 12 $1\core_core_fn_unit$next[11:0]$1662 + attribute \src "libresoc.v:46582.14-46582.41" + wire width 12 $1\core_core_fn_unit[11:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 2 $1\core_core_input_carry$next[1:0]$1663 + attribute \src "libresoc.v:46590.13-46590.41" + wire width 2 $1\core_core_input_carry[1:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 32 $1\core_core_insn$next[31:0]$1664 + attribute \src "libresoc.v:46594.14-46594.36" + wire width 32 $1\core_core_insn[31:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 7 $1\core_core_insn_type$next[6:0]$1665 + attribute \src "libresoc.v:46672.13-46672.40" + wire width 7 $1\core_core_insn_type[6:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $1\core_core_is_32bit$next[0:0]$1666 + attribute \src "libresoc.v:46676.7-46676.32" + wire $1\core_core_is_32bit[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $1\core_core_lk$next[0:0]$1667 + attribute \src "libresoc.v:46680.7-46680.26" + wire $1\core_core_lk[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 64 $1\core_core_msr$next[63:0]$1668 + attribute \src "libresoc.v:46684.14-46684.50" + wire width 64 $1\core_core_msr[63:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $1\core_core_oe$next[0:0]$1669 + attribute \src "libresoc.v:46688.7-46688.26" + wire $1\core_core_oe[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $1\core_core_oe_ok$next[0:0]$1670 + attribute \src "libresoc.v:46692.7-46692.29" + wire $1\core_core_oe_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $1\core_core_rc$next[0:0]$1671 + attribute \src "libresoc.v:46696.7-46696.26" + wire $1\core_core_rc[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $1\core_core_rc_ok$next[0:0]$1672 + attribute \src "libresoc.v:46700.7-46700.29" + wire $1\core_core_rc_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 13 $1\core_core_trapaddr$next[12:0]$1673 + attribute \src "libresoc.v:46704.14-46704.43" + wire width 13 $1\core_core_trapaddr[12:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 7 $1\core_core_traptype$next[6:0]$1674 + attribute \src "libresoc.v:46708.13-46708.39" + wire width 7 $1\core_core_traptype[6:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $1\core_cr_in1$next[2:0]$1675 + attribute \src "libresoc.v:46712.13-46712.31" + wire width 3 $1\core_cr_in1[2:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $1\core_cr_in1_ok$next[0:0]$1676 + attribute \src "libresoc.v:46716.7-46716.28" + wire $1\core_cr_in1_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $1\core_cr_in2$39$next[2:0]$1677 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $1\core_cr_in2$next[2:0]$1678 + attribute \src "libresoc.v:46720.13-46720.31" + wire width 3 $1\core_cr_in2[2:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $1\core_cr_in2_ok$40$next[0:0]$1679 + attribute \src "libresoc.v:48936.3-49042.6" + wire $1\core_cr_in2_ok$next[0:0]$1680 + attribute \src "libresoc.v:46728.7-46728.28" + wire $1\core_cr_in2_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $1\core_cr_out$next[2:0]$1681 + attribute \src "libresoc.v:46736.13-46736.31" + wire width 3 $1\core_cr_out[2:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $1\core_cr_out_ok$next[0:0]$1682 + attribute \src "libresoc.v:46740.7-46740.28" + wire $1\core_cr_out_ok[0:0] + attribute \src "libresoc.v:49395.3-49426.6" + wire width 64 $1\core_dec$next[63:0]$1886 + attribute \src "libresoc.v:46744.14-46744.45" + wire width 64 $1\core_dec[63:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 5 $1\core_ea$next[4:0]$1683 + attribute \src "libresoc.v:46748.13-46748.28" + wire width 5 $1\core_ea[4:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $1\core_ea_ok$next[0:0]$1684 + attribute \src "libresoc.v:46752.7-46752.24" + wire $1\core_ea_ok[0:0] + attribute \src "libresoc.v:49395.3-49426.6" + wire $1\core_eint$next[0:0]$1887 + attribute \src "libresoc.v:46756.7-46756.23" + wire $1\core_eint[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $1\core_fast1$next[2:0]$1685 + attribute \src "libresoc.v:46760.13-46760.30" + wire width 3 $1\core_fast1[2:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $1\core_fast1_ok$next[0:0]$1686 + attribute \src "libresoc.v:46764.7-46764.27" + wire $1\core_fast1_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $1\core_fast2$next[2:0]$1687 + attribute \src "libresoc.v:46768.13-46768.30" + wire width 3 $1\core_fast2[2:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $1\core_fast2_ok$next[0:0]$1688 + attribute \src "libresoc.v:46772.7-46772.27" + wire $1\core_fast2_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $1\core_fasto1$next[2:0]$1689 + attribute \src "libresoc.v:46776.13-46776.31" + wire width 3 $1\core_fasto1[2:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $1\core_fasto1_ok$next[0:0]$1690 + attribute \src "libresoc.v:46780.7-46780.28" + wire $1\core_fasto1_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $1\core_fasto2$next[2:0]$1691 + attribute \src "libresoc.v:46784.13-46784.31" + wire width 3 $1\core_fasto2[2:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $1\core_fasto2_ok$next[0:0]$1692 + attribute \src "libresoc.v:46788.7-46788.28" + wire $1\core_fasto2_ok[0:0] + attribute \src "libresoc.v:49395.3-49426.6" + wire width 64 $1\core_msr$next[63:0]$1888 + attribute \src "libresoc.v:46792.14-46792.45" + wire width 64 $1\core_msr[63:0] + attribute \src "libresoc.v:49395.3-49426.6" + wire width 64 $1\core_pc$next[63:0]$1889 + attribute \src "libresoc.v:46796.14-46796.44" + wire width 64 $1\core_pc[63:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 5 $1\core_reg1$next[4:0]$1693 + attribute \src "libresoc.v:46800.13-46800.30" + wire width 5 $1\core_reg1[4:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $1\core_reg1_ok$next[0:0]$1694 + attribute \src "libresoc.v:46804.7-46804.26" + wire $1\core_reg1_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 5 $1\core_reg2$next[4:0]$1695 + attribute \src "libresoc.v:46808.13-46808.30" + wire width 5 $1\core_reg2[4:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $1\core_reg2_ok$next[0:0]$1696 + attribute \src "libresoc.v:46812.7-46812.26" + wire $1\core_reg2_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 5 $1\core_reg3$next[4:0]$1697 + attribute \src "libresoc.v:46816.13-46816.30" + wire width 5 $1\core_reg3[4:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $1\core_reg3_ok$next[0:0]$1698 + attribute \src "libresoc.v:46820.7-46820.26" + wire $1\core_reg3_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 5 $1\core_rego$next[4:0]$1699 + attribute \src "libresoc.v:46824.13-46824.30" + wire width 5 $1\core_rego[4:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $1\core_rego_ok$next[0:0]$1700 + attribute \src "libresoc.v:46828.7-46828.26" + wire $1\core_rego_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 10 $1\core_spr1$next[9:0]$1701 + attribute \src "libresoc.v:46945.13-46945.32" + wire width 10 $1\core_spr1[9:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $1\core_spr1_ok$next[0:0]$1702 + attribute \src "libresoc.v:46949.7-46949.26" + wire $1\core_spr1_ok[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 10 $1\core_spro$next[9:0]$1703 + attribute \src "libresoc.v:47064.13-47064.32" + wire width 10 $1\core_spro[9:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $1\core_spro_ok$next[0:0]$1704 + attribute \src "libresoc.v:47068.7-47068.26" + wire $1\core_spro_ok[0:0] + attribute \src "libresoc.v:49317.3-49335.6" + wire $1\core_stopped_i[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $1\core_xer_in$next[2:0]$1705 + attribute \src "libresoc.v:47076.13-47076.31" + wire width 3 $1\core_xer_in[2:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire $1\core_xer_out$next[0:0]$1706 + attribute \src "libresoc.v:47080.7-47080.26" + wire $1\core_xer_out[0:0] + attribute \src "libresoc.v:47096.7-47096.30" + wire $1\cu_st__rel_o_dly[0:0] + attribute \src "libresoc.v:48588.3-48596.6" + wire $1\d_cr_delay$next[0:0]$1559 + attribute \src "libresoc.v:47102.7-47102.24" + wire $1\d_cr_delay[0:0] + attribute \src "libresoc.v:48549.3-48557.6" + wire $1\d_reg_delay$next[0:0]$1553 + attribute \src "libresoc.v:47106.7-47106.25" + wire $1\d_reg_delay[0:0] + attribute \src "libresoc.v:48627.3-48635.6" + wire $1\d_xer_delay$next[0:0]$1565 + attribute \src "libresoc.v:47110.7-47110.25" + wire $1\d_xer_delay[0:0] + attribute \src "libresoc.v:48865.3-48885.6" + wire width 64 $1\data_i[63:0] + attribute \src "libresoc.v:49336.3-49354.6" + wire $1\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:48607.3-48616.6" + wire $1\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:48597.3-48606.6" + wire width 64 $1\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:48568.3-48577.6" + wire $1\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:48558.3-48567.6" + wire width 64 $1\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:48646.3-48655.6" + wire $1\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:48636.3-48645.6" + wire width 64 $1\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:48500.3-48508.6" + wire width 4 $1\dbg_dmi_addr_i$next[3:0]$1544 + attribute \src "libresoc.v:47148.13-47148.34" + wire width 4 $1\dbg_dmi_addr_i[3:0] + attribute \src "libresoc.v:48902.3-48910.6" + wire width 64 $1\dbg_dmi_din$next[63:0]$1598 + attribute \src "libresoc.v:47152.14-47152.48" + wire width 64 $1\dbg_dmi_din[63:0] + attribute \src "libresoc.v:48509.3-48517.6" + wire $1\dbg_dmi_req_i$next[0:0]$1547 + attribute \src "libresoc.v:47158.7-47158.27" + wire $1\dbg_dmi_req_i[0:0] + attribute \src "libresoc.v:48797.3-48805.6" + wire $1\dbg_dmi_we_i$next[0:0]$1587 + attribute \src "libresoc.v:47162.7-47162.26" + wire $1\dbg_dmi_we_i[0:0] + attribute \src "libresoc.v:48770.3-48785.6" + wire width 64 $1\dec2_cur_dec$next[63:0]$1582 + attribute \src "libresoc.v:47220.14-47220.49" + wire width 64 $1\dec2_cur_dec[63:0] + attribute \src "libresoc.v:49061.3-49069.6" + wire $1\dec2_cur_eint$next[0:0]$1836 + attribute \src "libresoc.v:47224.7-47224.27" + wire $1\dec2_cur_eint[0:0] + attribute \src "libresoc.v:49355.3-49375.6" + wire width 64 $1\dec2_cur_msr$next[63:0]$1877 + attribute \src "libresoc.v:47228.14-47228.49" + wire width 64 $1\dec2_cur_msr[63:0] + attribute \src "libresoc.v:49210.3-49230.6" + wire width 64 $1\dec2_cur_pc$next[63:0]$1854 + attribute \src "libresoc.v:47232.14-47232.48" + wire width 64 $1\dec2_cur_pc[63:0] + attribute \src "libresoc.v:49376.3-49394.6" + wire width 32 $1\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:49307.3-49316.6" + wire width 2 $1\delay$next[1:0]$1872 + attribute \src "libresoc.v:47625.13-47625.25" + wire width 2 $1\delay[1:0] + attribute \src "libresoc.v:48529.3-48538.6" + wire width 5 $1\dmi__addr[4:0] + attribute \src "libresoc.v:48539.3-48548.6" + wire $1\dmi__ren[0:0] + attribute \src "libresoc.v:48686.3-48713.6" + wire width 2 $1\fsm_state$115$next[1:0]$1572 + attribute \src "libresoc.v:49261.3-49306.6" + wire width 2 $1\fsm_state$next[1:0]$1865 + attribute \src "libresoc.v:47635.13-47635.29" + wire width 2 $1\fsm_state[1:0] + attribute \src "libresoc.v:48578.3-48587.6" + wire width 8 $1\full_rd2__ren[7:0] + attribute \src "libresoc.v:48617.3-48626.6" + wire width 3 $1\full_rd__ren[2:0] + attribute \src "libresoc.v:49427.3-49450.6" + wire width 32 $1\ilatch$next[31:0]$1900 + attribute \src "libresoc.v:47909.14-47909.28" + wire width 32 $1\ilatch[31:0] + attribute \src "libresoc.v:49144.3-49159.6" + wire width 48 $1\imem_a_pc_i[47:0] + attribute \src "libresoc.v:49160.3-49184.6" + wire $1\imem_a_valid_i[0:0] + attribute \src "libresoc.v:49185.3-49209.6" + wire $1\imem_f_valid_i[0:0] + attribute \src "libresoc.v:48725.3-48739.6" + wire width 3 $1\issue__addr$119[2:0]$1577 + attribute \src "libresoc.v:48656.3-48670.6" + wire width 3 $1\issue__addr[2:0] + attribute \src "libresoc.v:48755.3-48769.6" + wire width 64 $1\issue__data_i[63:0] + attribute \src "libresoc.v:48671.3-48685.6" + wire $1\issue__ren[0:0] + attribute \src "libresoc.v:48740.3-48754.6" + wire $1\issue__wen[0:0] + attribute \src "libresoc.v:48518.3-48528.6" + wire $1\issue_i[0:0] + attribute \src "libresoc.v:49451.3-49470.6" + wire $1\ivalid_i[0:0] + attribute \src "libresoc.v:49043.3-49051.6" + wire $1\jtag_dmi0_ack_o$next[0:0]$1830 + attribute \src "libresoc.v:47941.7-47941.29" + wire $1\jtag_dmi0_ack_o[0:0] + attribute \src "libresoc.v:49052.3-49060.6" + wire width 64 $1\jtag_dmi0_dout$next[63:0]$1833 + attribute \src "libresoc.v:47949.14-47949.51" + wire width 64 $1\jtag_dmi0_dout[63:0] + attribute \src "libresoc.v:48886.3-48901.6" + wire width 4 $1\msr__ren[3:0] + attribute \src "libresoc.v:49231.3-49260.6" + wire $1\msr_read$next[0:0]$1859 + attribute \src "libresoc.v:47981.7-47981.22" + wire $1\msr_read[0:0] + attribute \src "libresoc.v:48714.3-48724.6" + wire width 64 $1\new_dec[63:0] + attribute \src "libresoc.v:48786.3-48796.6" + wire width 64 $1\new_tb[63:0] + attribute \src "libresoc.v:48815.3-48830.6" + wire width 64 $1\pc[63:0] + attribute \src "libresoc.v:48911.3-48935.6" + wire $1\pc_changed$next[0:0]$1601 + attribute \src "libresoc.v:47993.7-47993.24" + wire $1\pc_changed[0:0] + attribute \src "libresoc.v:48806.3-48814.6" + wire $1\pc_ok_delay$next[0:0]$1590 + attribute \src "libresoc.v:48003.7-48003.25" + wire $1\pc_ok_delay[0:0] + attribute \src "libresoc.v:49070.3-49106.6" + wire width 32 $1\raw_insn_i$next[31:0]$1839 + attribute \src "libresoc.v:48009.14-48009.32" + wire width 32 $1\raw_insn_i[31:0] + attribute \src "libresoc.v:48844.3-48864.6" + wire width 4 $1\wen[3:0] + attribute \src "libresoc.v:49107.3-49143.6" + wire $2\bigendian_i$next[0:0]$1846 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 8 $2\core_asmcode$next[7:0]$1707 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 64 $2\core_core_cia$next[63:0]$1708 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 8 $2\core_core_cr_rd$next[7:0]$1709 + attribute \src "libresoc.v:48936.3-49042.6" + wire $2\core_core_cr_rd_ok$next[0:0]$1710 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 8 $2\core_core_cr_wr$next[7:0]$1711 + attribute \src "libresoc.v:48936.3-49042.6" + wire $2\core_core_cr_wr_ok$next[0:0]$1712 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 12 $2\core_core_fn_unit$next[11:0]$1713 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 2 $2\core_core_input_carry$next[1:0]$1714 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 32 $2\core_core_insn$next[31:0]$1715 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 7 $2\core_core_insn_type$next[6:0]$1716 + attribute \src "libresoc.v:48936.3-49042.6" + wire $2\core_core_is_32bit$next[0:0]$1717 + attribute \src "libresoc.v:48936.3-49042.6" + wire $2\core_core_lk$next[0:0]$1718 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 64 $2\core_core_msr$next[63:0]$1719 + attribute \src "libresoc.v:48936.3-49042.6" + wire $2\core_core_oe$next[0:0]$1720 + attribute \src "libresoc.v:48936.3-49042.6" + wire $2\core_core_oe_ok$next[0:0]$1721 + attribute \src "libresoc.v:48936.3-49042.6" + wire $2\core_core_rc$next[0:0]$1722 + attribute \src "libresoc.v:48936.3-49042.6" + wire $2\core_core_rc_ok$next[0:0]$1723 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 13 $2\core_core_trapaddr$next[12:0]$1724 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 7 $2\core_core_traptype$next[6:0]$1725 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $2\core_cr_in1$next[2:0]$1726 + attribute \src "libresoc.v:48936.3-49042.6" + wire $2\core_cr_in1_ok$next[0:0]$1727 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $2\core_cr_in2$39$next[2:0]$1728 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $2\core_cr_in2$next[2:0]$1729 + attribute \src "libresoc.v:48936.3-49042.6" + wire $2\core_cr_in2_ok$40$next[0:0]$1730 + attribute \src "libresoc.v:48936.3-49042.6" + wire $2\core_cr_in2_ok$next[0:0]$1731 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $2\core_cr_out$next[2:0]$1732 + attribute \src "libresoc.v:48936.3-49042.6" + wire $2\core_cr_out_ok$next[0:0]$1733 + attribute \src "libresoc.v:49395.3-49426.6" + wire width 64 $2\core_dec$next[63:0]$1890 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 5 $2\core_ea$next[4:0]$1734 + attribute \src "libresoc.v:48936.3-49042.6" + wire $2\core_ea_ok$next[0:0]$1735 + attribute \src "libresoc.v:49395.3-49426.6" + wire $2\core_eint$next[0:0]$1891 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $2\core_fast1$next[2:0]$1736 + attribute \src "libresoc.v:48936.3-49042.6" + wire $2\core_fast1_ok$next[0:0]$1737 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $2\core_fast2$next[2:0]$1738 + attribute \src "libresoc.v:48936.3-49042.6" + wire $2\core_fast2_ok$next[0:0]$1739 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $2\core_fasto1$next[2:0]$1740 + attribute \src "libresoc.v:48936.3-49042.6" + wire $2\core_fasto1_ok$next[0:0]$1741 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $2\core_fasto2$next[2:0]$1742 + attribute \src "libresoc.v:48936.3-49042.6" + wire $2\core_fasto2_ok$next[0:0]$1743 + attribute \src "libresoc.v:49395.3-49426.6" + wire width 64 $2\core_msr$next[63:0]$1892 + attribute \src "libresoc.v:49395.3-49426.6" + wire width 64 $2\core_pc$next[63:0]$1893 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 5 $2\core_reg1$next[4:0]$1744 + attribute \src "libresoc.v:48936.3-49042.6" + wire $2\core_reg1_ok$next[0:0]$1745 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 5 $2\core_reg2$next[4:0]$1746 + attribute \src "libresoc.v:48936.3-49042.6" + wire $2\core_reg2_ok$next[0:0]$1747 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 5 $2\core_reg3$next[4:0]$1748 + attribute \src "libresoc.v:48936.3-49042.6" + wire $2\core_reg3_ok$next[0:0]$1749 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 5 $2\core_rego$next[4:0]$1750 + attribute \src "libresoc.v:48936.3-49042.6" + wire $2\core_rego_ok$next[0:0]$1751 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 10 $2\core_spr1$next[9:0]$1752 + attribute \src "libresoc.v:48936.3-49042.6" + wire $2\core_spr1_ok$next[0:0]$1753 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 10 $2\core_spro$next[9:0]$1754 + attribute \src "libresoc.v:48936.3-49042.6" + wire $2\core_spro_ok$next[0:0]$1755 + attribute \src "libresoc.v:49317.3-49335.6" + wire $2\core_stopped_i[0:0] + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $2\core_xer_in$next[2:0]$1756 + attribute \src "libresoc.v:48936.3-49042.6" + wire $2\core_xer_out$next[0:0]$1757 + attribute \src "libresoc.v:48865.3-48885.6" + wire width 64 $2\data_i[63:0] + attribute \src "libresoc.v:49336.3-49354.6" + wire $2\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:48770.3-48785.6" + wire width 64 $2\dec2_cur_dec$next[63:0]$1583 + attribute \src "libresoc.v:49355.3-49375.6" + wire width 64 $2\dec2_cur_msr$next[63:0]$1878 + attribute \src "libresoc.v:49210.3-49230.6" + wire width 64 $2\dec2_cur_pc$next[63:0]$1855 + attribute \src "libresoc.v:49376.3-49394.6" + wire width 32 $2\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:48686.3-48713.6" + wire width 2 $2\fsm_state$115$next[1:0]$1573 + attribute \src "libresoc.v:49261.3-49306.6" + wire width 2 $2\fsm_state$next[1:0]$1866 + attribute \src "libresoc.v:49427.3-49450.6" + wire width 32 $2\ilatch$next[31:0]$1901 + attribute \src "libresoc.v:49144.3-49159.6" + wire width 48 $2\imem_a_pc_i[47:0] + attribute \src "libresoc.v:49160.3-49184.6" + wire $2\imem_a_valid_i[0:0] + attribute \src "libresoc.v:49185.3-49209.6" + wire $2\imem_f_valid_i[0:0] + attribute \src "libresoc.v:49451.3-49470.6" + wire $2\ivalid_i[0:0] + attribute \src "libresoc.v:48886.3-48901.6" + wire width 4 $2\msr__ren[3:0] + attribute \src "libresoc.v:49231.3-49260.6" + wire $2\msr_read$next[0:0]$1860 + attribute \src "libresoc.v:48815.3-48830.6" + wire width 64 $2\pc[63:0] + attribute \src "libresoc.v:48911.3-48935.6" + wire $2\pc_changed$next[0:0]$1602 + attribute \src "libresoc.v:49070.3-49106.6" + wire width 32 $2\raw_insn_i$next[31:0]$1840 + attribute \src "libresoc.v:48844.3-48864.6" + wire width 4 $2\wen[3:0] + attribute \src "libresoc.v:49107.3-49143.6" + wire $3\bigendian_i$next[0:0]$1847 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 8 $3\core_asmcode$next[7:0]$1758 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 64 $3\core_core_cia$next[63:0]$1759 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 8 $3\core_core_cr_rd$next[7:0]$1760 + attribute \src "libresoc.v:48936.3-49042.6" + wire $3\core_core_cr_rd_ok$next[0:0]$1761 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 8 $3\core_core_cr_wr$next[7:0]$1762 + attribute \src "libresoc.v:48936.3-49042.6" + wire $3\core_core_cr_wr_ok$next[0:0]$1763 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 12 $3\core_core_fn_unit$next[11:0]$1764 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 2 $3\core_core_input_carry$next[1:0]$1765 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 32 $3\core_core_insn$next[31:0]$1766 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 7 $3\core_core_insn_type$next[6:0]$1767 + attribute \src "libresoc.v:48936.3-49042.6" + wire $3\core_core_is_32bit$next[0:0]$1768 + attribute \src "libresoc.v:48936.3-49042.6" + wire $3\core_core_lk$next[0:0]$1769 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 64 $3\core_core_msr$next[63:0]$1770 + attribute \src "libresoc.v:48936.3-49042.6" + wire $3\core_core_oe$next[0:0]$1771 + attribute \src "libresoc.v:48936.3-49042.6" + wire $3\core_core_oe_ok$next[0:0]$1772 + attribute \src "libresoc.v:48936.3-49042.6" + wire $3\core_core_rc$next[0:0]$1773 + attribute \src "libresoc.v:48936.3-49042.6" + wire $3\core_core_rc_ok$next[0:0]$1774 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 13 $3\core_core_trapaddr$next[12:0]$1775 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 7 $3\core_core_traptype$next[6:0]$1776 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $3\core_cr_in1$next[2:0]$1777 + attribute \src "libresoc.v:48936.3-49042.6" + wire $3\core_cr_in1_ok$next[0:0]$1778 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $3\core_cr_in2$39$next[2:0]$1779 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $3\core_cr_in2$next[2:0]$1780 + attribute \src "libresoc.v:48936.3-49042.6" + wire $3\core_cr_in2_ok$40$next[0:0]$1781 + attribute \src "libresoc.v:48936.3-49042.6" + wire $3\core_cr_in2_ok$next[0:0]$1782 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $3\core_cr_out$next[2:0]$1783 + attribute \src "libresoc.v:48936.3-49042.6" + wire $3\core_cr_out_ok$next[0:0]$1784 + attribute \src "libresoc.v:49395.3-49426.6" + wire width 64 $3\core_dec$next[63:0]$1894 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 5 $3\core_ea$next[4:0]$1785 + attribute \src "libresoc.v:48936.3-49042.6" + wire $3\core_ea_ok$next[0:0]$1786 + attribute \src "libresoc.v:49395.3-49426.6" + wire $3\core_eint$next[0:0]$1895 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $3\core_fast1$next[2:0]$1787 + attribute \src "libresoc.v:48936.3-49042.6" + wire $3\core_fast1_ok$next[0:0]$1788 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $3\core_fast2$next[2:0]$1789 + attribute \src "libresoc.v:48936.3-49042.6" + wire $3\core_fast2_ok$next[0:0]$1790 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $3\core_fasto1$next[2:0]$1791 + attribute \src "libresoc.v:48936.3-49042.6" + wire $3\core_fasto1_ok$next[0:0]$1792 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $3\core_fasto2$next[2:0]$1793 + attribute \src "libresoc.v:48936.3-49042.6" + wire $3\core_fasto2_ok$next[0:0]$1794 + attribute \src "libresoc.v:49395.3-49426.6" + wire width 64 $3\core_msr$next[63:0]$1896 + attribute \src "libresoc.v:49395.3-49426.6" + wire width 64 $3\core_pc$next[63:0]$1897 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 5 $3\core_reg1$next[4:0]$1795 + attribute \src "libresoc.v:48936.3-49042.6" + wire $3\core_reg1_ok$next[0:0]$1796 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 5 $3\core_reg2$next[4:0]$1797 + attribute \src "libresoc.v:48936.3-49042.6" + wire $3\core_reg2_ok$next[0:0]$1798 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 5 $3\core_reg3$next[4:0]$1799 + attribute \src "libresoc.v:48936.3-49042.6" + wire $3\core_reg3_ok$next[0:0]$1800 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 5 $3\core_rego$next[4:0]$1801 + attribute \src "libresoc.v:48936.3-49042.6" + wire $3\core_rego_ok$next[0:0]$1802 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 10 $3\core_spr1$next[9:0]$1803 + attribute \src "libresoc.v:48936.3-49042.6" + wire $3\core_spr1_ok$next[0:0]$1804 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 10 $3\core_spro$next[9:0]$1805 + attribute \src "libresoc.v:48936.3-49042.6" + wire $3\core_spro_ok$next[0:0]$1806 + attribute \src "libresoc.v:48936.3-49042.6" + wire width 3 $3\core_xer_in$next[2:0]$1807 + attribute \src "libresoc.v:48936.3-49042.6" + wire $3\core_xer_out$next[0:0]$1808 + attribute \src "libresoc.v:48865.3-48885.6" + wire width 64 $3\data_i[63:0] + attribute \src "libresoc.v:49355.3-49375.6" + wire width 64 $3\dec2_cur_msr$next[63:0]$1879 + attribute \src "libresoc.v:49210.3-49230.6" + wire width 64 $3\dec2_cur_pc$next[63:0]$1856 + attribute \src "libresoc.v:49261.3-49306.6" + wire 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:161" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" wire \$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" wire \$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 4 \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 4 \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 4 \$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 4 \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - wire \all_rd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \all_rd_dly$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" - wire \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \all_rd_rise - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" - wire \alu_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \alu_done_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \alu_l_s_alu - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 5 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:255" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 11 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 9 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire output 8 \TAP_bus__tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 10 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" + wire \bigendian_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" + wire \bigendian_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:90" + wire output 5 \busy_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \cia__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \cia__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" + wire input 6 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" + wire width 8 \core_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" + wire width 8 \core_asmcode$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:89" + wire input 4 \core_bigendian_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 \core_core_cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 \core_core_cia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \core_core_cr_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \core_core_cr_rd$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_trap0_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_trap0_fast1$1 + wire \core_core_cr_rd_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_trap0_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_trap0_fast2$2 + wire \core_core_cr_rd_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_trap0_msr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \alu_trap0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \alu_trap0_n_valid_o + wire width 8 \core_core_cr_wr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_trap0_nia + wire width 8 \core_core_cr_wr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_trap0_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \alu_trap0_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \alu_trap0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_trap0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_trap0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_trap0_trap_op__cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_trap0_trap_op__cia$next + wire \core_core_cr_wr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_cr_wr_ok$next attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -371455,14 +134112,22 @@ module \trap0 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_trap0_trap_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_trap0_trap_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_trap0_trap_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_trap0_trap_op__insn$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 12 \core_core_fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 12 \core_core_fn_unit$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + wire width 2 \core_core_input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + wire width 2 \core_core_input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + wire width 32 \core_core_insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + wire width 32 \core_core_insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -371537,134 +134202,590 @@ module \trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_trap0_trap_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_trap0_trap_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_trap0_trap_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_trap0_trap_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_trap0_trap_op__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_trap0_trap_op__msr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_trap0_trap_op__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_trap0_trap_op__trapaddr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_trap0_trap_op__traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_trap0_trap_op__traptype$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 30 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 10 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 9 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 7 \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 7 \core_core_insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire \core_core_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire \core_core_is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire \core_core_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire \core_core_lk$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + wire width 64 \core_core_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + wire width 64 \core_core_msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_oe_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_rc_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 13 \core_core_trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 13 \core_core_trapaddr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 7 \core_core_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 7 \core_core_traptype$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_cr_in1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_cr_in1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_cr_in1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_cr_in1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_cr_in2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_cr_in2$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_cr_in2$39$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_cr_in2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_cr_in2_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_cr_in2_ok$40$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_cr_in2_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_cr_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_cr_out_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_cr_out_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + wire width 64 \core_dec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + wire width 64 \core_dec$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \core_ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \core_ea$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_ea_ok$next + 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"/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire \dbg_d_gpr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire \dbg_d_xer_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 \dbg_d_xer_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire \dbg_d_xer_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" + wire \dbg_dmi_ack_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 4 \dbg_dmi_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 4 \dbg_dmi_addr_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 \dbg_dmi_din + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 \dbg_dmi_din$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 64 \dbg_dmi_dout + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire \dbg_dmi_req_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire \dbg_dmi_req_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + wire \dbg_dmi_we_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + wire \dbg_dmi_we_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:102" + wire \dbg_terminate_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 138 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 input 132 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 2 input 141 \dbus__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 3 input 140 \dbus__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 136 \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 134 \dbus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 133 \dbus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 142 \dbus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 input 135 \dbus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 137 \dbus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 139 \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" + wire width 8 \dec2_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec2_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 \dec2_cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 22 \fast1_ok + wire width 3 \dec2_cr_in1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 23 \fast2_ok - attribute \src "issuer_ls180.v:178759.7-178759.15" - wire \initial + wire \dec2_cr_in1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_cr_in2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_cr_in2$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_cr_in2_ok$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_cr_out_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \dec2_cr_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_cr_rd_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \dec2_cr_wr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_cr_wr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + wire width 64 \dec2_cur_dec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + wire width 64 \dec2_cur_dec$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + wire \dec2_cur_eint + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + wire \dec2_cur_eint$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 \dec2_cur_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 \dec2_cur_msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 \dec2_cur_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 \dec2_cur_pc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec2_ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_fasto1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 28 \msr_ok + wire \dec2_fasto1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 26 \nia_ok + wire width 3 \dec2_fasto2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 18 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 5 \oper_i_alu_trap0__cia + wire \dec2_fasto2_ok attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -371678,10 +134799,16 @@ module \trap0 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \oper_i_alu_trap0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 3 \oper_i_alu_trap0__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 12 \dec2_fn_unit + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + wire width 2 \dec2_input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + wire width 32 \dec2_insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -371756,4927 +134883,5452 @@ module \trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \oper_i_alu_trap0__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \oper_i_alu_trap0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 4 \oper_i_alu_trap0__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 8 \oper_i_alu_trap0__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 7 \oper_i_alu_trap0__traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 5 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 5 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" - wire \req_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 5 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 \req_l_r_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 \req_l_s_req$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" - wire \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 4 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" - wire width 5 \reset_w - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \rok_l_r_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \rok_l_s_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \rst_l_r_rst$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \rst_l_s_rst$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" - wire \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 14 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 15 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 16 \src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 17 \src4_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 \src_l_q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" - wire \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$issuer_ls180.v:179348$12995 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 7 \dec2_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire \dec2_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire \dec2_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + wire width 64 \dec2_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 \dec2_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec2_reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec2_reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec2_reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec2_rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_rego_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \dec2_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_spr1_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \dec2_spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 13 \dec2_trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 7 \dec2_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + wire width 3 \dec2_xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" + wire \dec2_xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:155" + wire width 2 \delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:155" + wire width 2 \delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 \dmi__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \dmi__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \dmi__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + wire width 2 \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" + wire width 2 \fsm_state$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" + wire width 2 \fsm_state$115$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + wire width 2 \fsm_state$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 \full_rd2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \full_rd2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 6 \full_rd__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \full_rd__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 25 \gpio_gpio0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 26 \gpio_gpio0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 27 \gpio_gpio0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 28 \gpio_gpio0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 29 \gpio_gpio0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 30 \gpio_gpio0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 85 \gpio_gpio10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 86 \gpio_gpio10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 87 \gpio_gpio10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 88 \gpio_gpio10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 89 \gpio_gpio10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 90 \gpio_gpio10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 91 \gpio_gpio11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 92 \gpio_gpio11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 93 \gpio_gpio11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 94 \gpio_gpio11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 95 \gpio_gpio11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 96 \gpio_gpio11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 97 \gpio_gpio12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 98 \gpio_gpio12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 99 \gpio_gpio12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 100 \gpio_gpio12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 101 \gpio_gpio12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 102 \gpio_gpio12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 103 \gpio_gpio13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 104 \gpio_gpio13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 105 \gpio_gpio13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 106 \gpio_gpio13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 107 \gpio_gpio13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 108 \gpio_gpio13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 109 \gpio_gpio14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 110 \gpio_gpio14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 111 \gpio_gpio14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 112 \gpio_gpio14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 113 \gpio_gpio14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 114 \gpio_gpio14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 115 \gpio_gpio15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 116 \gpio_gpio15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 117 \gpio_gpio15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 118 \gpio_gpio15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 119 \gpio_gpio15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 120 \gpio_gpio15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 31 \gpio_gpio1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 32 \gpio_gpio1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 33 \gpio_gpio1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 34 \gpio_gpio1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 35 \gpio_gpio1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 36 \gpio_gpio1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 37 \gpio_gpio2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 38 \gpio_gpio2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 39 \gpio_gpio2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 40 \gpio_gpio2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 41 \gpio_gpio2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 42 \gpio_gpio2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 43 \gpio_gpio3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 44 \gpio_gpio3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 45 \gpio_gpio3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 46 \gpio_gpio3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 47 \gpio_gpio3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 48 \gpio_gpio3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 49 \gpio_gpio4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 50 \gpio_gpio4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 51 \gpio_gpio4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 52 \gpio_gpio4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 53 \gpio_gpio4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 54 \gpio_gpio4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 55 \gpio_gpio5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 56 \gpio_gpio5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 57 \gpio_gpio5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 58 \gpio_gpio5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 59 \gpio_gpio5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 60 \gpio_gpio5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 61 \gpio_gpio6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 62 \gpio_gpio6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 63 \gpio_gpio6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 64 \gpio_gpio6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 65 \gpio_gpio6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 66 \gpio_gpio6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 67 \gpio_gpio7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 68 \gpio_gpio7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 69 \gpio_gpio7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 70 \gpio_gpio7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 71 \gpio_gpio7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 72 \gpio_gpio7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 73 \gpio_gpio8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 74 \gpio_gpio8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 75 \gpio_gpio8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 76 \gpio_gpio8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 77 \gpio_gpio8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 78 \gpio_gpio8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 79 \gpio_gpio9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 80 \gpio_gpio9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 81 \gpio_gpio9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 82 \gpio_gpio9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 83 \gpio_gpio9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 84 \gpio_gpio9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 127 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 121 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 2 input 130 \ibus__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 3 input 129 \ibus__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 125 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 123 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 122 \ibus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 131 \ibus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 output 124 \ibus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 126 \ibus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 128 \ibus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire output 149 \icp_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 28 input 143 \icp_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 2 input 152 \icp_wb__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 3 input 151 \icp_wb__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 147 \icp_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 output 145 \icp_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 input 144 \icp_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 153 \icp_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 4 input 146 \icp_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 148 \icp_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 150 \icp_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire output 160 \ics_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 28 input 154 \ics_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 2 input 163 \ics_wb__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 3 input 162 \ics_wb__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 158 \ics_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 output 156 \ics_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 input 155 \ics_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 164 \ics_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 4 input 157 \ics_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 159 \ics_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 161 \ics_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177" + wire width 32 \ilatch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177" + wire width 32 \ilatch$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" + wire width 48 \imem_a_pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" + wire \imem_a_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" + wire \imem_f_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" + wire width 64 \imem_f_instr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" + wire \imem_f_valid_i + attribute \src "libresoc.v:46401.7-46401.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" + wire width 16 input 165 \int_level_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \issue__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \issue__addr$119 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \issue__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \issue__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \issue__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \issue__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" + wire \issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:96" + wire \ivalid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" + wire \jtag_dmi0_ack_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" + wire \jtag_dmi0_ack_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 4 \jtag_dmi0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 \jtag_dmi0_din + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 64 \jtag_dmi0_dout + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 64 \jtag_dmi0_dout$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire \jtag_dmi0_req_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + wire \jtag_dmi0_we_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire input 19 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 29 output 12 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 16 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 64 input 14 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 64 output 13 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire input 20 \jtag_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 15 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 17 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 18 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:91" + wire input 3 \memerr_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \msr__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \msr__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" + wire \msr_read + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" + wire \msr_read$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:371" + wire width 64 \new_dec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:388" + wire width 64 \new_tb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + wire width 64 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:184" + wire width 64 \pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + wire \pc_changed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + wire \pc_changed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 166 \pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 1 \pc_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:87" + wire width 64 output 2 \pc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:185" + wire \pc_ok_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:185" + wire \pc_ok_delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:150" + wire \por_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:92" + wire width 32 \raw_insn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:92" + wire width 32 \raw_insn_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" + wire input 7 \rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \state_nia_wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 23 \uart_rx__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 24 \uart_rx__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 21 \uart_tx__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 22 \uart_tx__pad__o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" + wire \xics_icp_core_irq_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 \xics_icp_ics_i_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 \xics_icp_ics_i_src + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 \xics_ics_icp_o_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 \xics_ics_icp_o_src + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:389" + cell $add $add$libresoc.v:48046$1415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \issue__data_o + connect \B 1'1 + connect \Y $add$libresoc.v:48046$1415_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:181" + cell $add $add$libresoc.v:48049$1418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \dec2_cur_pc + connect \B 3'100 + connect \Y $add$libresoc.v:48049$1418_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:48048$1417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_st__rel_o + connect \B \$12 + connect \Y $and$libresoc.v:48048$1417_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $and $and$libresoc.v:48057$1426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$29 + connect \B \$31 + connect \Y $and$libresoc.v:48057$1426_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + cell $and $and$libresoc.v:48058$1427 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 + parameter \B_WIDTH 1 parameter \Y_WIDTH 4 - connect \A \$95 - connect \B \$97 - connect \Y $and$issuer_ls180.v:179348$12995_Y + connect \A \state_nia_wen + connect \B 1'1 + connect \Y $and$libresoc.v:48058$1427_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $and $and$libresoc.v:48066$1435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$47 + connect \B \$49 + connect \Y $and$libresoc.v:48066$1435_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $and $and$libresoc.v:48069$1438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$53 + connect \B \$55 + connect \Y $and$libresoc.v:48069$1438_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $and $and$libresoc.v:48072$1441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$59 + connect \B \$61 + connect \Y $and$libresoc.v:48072$1441_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$issuer_ls180.v:179349$12996 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $and $and$libresoc.v:48076$1445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $and$issuer_ls180.v:179349$12996_Y + connect \A \$65 + connect \B \$67 + connect \Y $and$libresoc.v:48076$1445_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$issuer_ls180.v:179350$12997 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $and $and$libresoc.v:48079$1448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $and$issuer_ls180.v:179350$12997_Y + connect \A \$71 + connect \B \$73 + connect \Y $and$libresoc.v:48079$1448_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$issuer_ls180.v:179351$12998 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $and $and$libresoc.v:48083$1452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $and$issuer_ls180.v:179351$12998_Y + connect \A \$79 + connect \B \$81 + connect \Y $and$libresoc.v:48083$1452_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$issuer_ls180.v:179352$12999 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $and $and$libresoc.v:48088$1457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $and$issuer_ls180.v:179352$12999_Y + connect \A \$87 + connect \B \$89 + connect \Y $and$libresoc.v:48088$1457_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$issuer_ls180.v:179353$13000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $and $and$libresoc.v:48091$1460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $and$issuer_ls180.v:179353$13000_Y + connect \A \$93 + connect \B \$95 + connect \Y $and$libresoc.v:48091$1460_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$issuer_ls180.v:179354$13001 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $extend$libresoc.v:48043$1410 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \req_l_q_req - connect \B { \$101 \$103 \$105 \$107 \$109 } - connect \Y $and$issuer_ls180.v:179354$13001_Y + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \full_rd2__data_o + connect \Y $extend$libresoc.v:48043$1410_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$issuer_ls180.v:179355$13002 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $extend$libresoc.v:48044$1412 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$111 - connect \B \cu_wrmask_o - connect \Y $and$issuer_ls180.v:179355$13002_Y + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \full_rd__data_o + connect \Y $extend$libresoc.v:48044$1412_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$issuer_ls180.v:179356$13003 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + cell $mul $mul$libresoc.v:48037$1404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:179356$13003_Y + parameter \B_WIDTH 6 + parameter \Y_WIDTH 7 + connect \A \dec2_cur_pc [2] + connect \B 6'100000 + connect \Y $mul$libresoc.v:48037$1404_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$issuer_ls180.v:179357$13004 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + cell $mul $mul$libresoc.v:48039$1406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:179357$13004_Y + parameter \B_WIDTH 6 + parameter \Y_WIDTH 7 + connect \A \dec2_cur_pc [2] + connect \B 6'100000 + connect \Y $mul$libresoc.v:48039$1406_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$issuer_ls180.v:179358$13005 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:161" + cell $ne $ne$libresoc.v:48041$1408 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \$5 - connect \Y $and$issuer_ls180.v:179358$13005_Y + connect \A \delay + connect \B \$8 + connect \Y $ne$libresoc.v:48041$1408_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$issuer_ls180.v:179359$13006 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + cell $ne $ne$libresoc.v:48042$1409 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [2] - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:179359$13006_Y + connect \A \core_core_insn_type + connect \B 7'0000001 + connect \Y $ne$libresoc.v:48042$1409_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$issuer_ls180.v:179360$13007 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:156" + cell $ne $ne$libresoc.v:48060$1429 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [3] - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:179360$13007_Y + connect \A \delay + connect \B 1'0 + connect \Y $ne$libresoc.v:48060$1429_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$issuer_ls180.v:179361$13008 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:255" + cell $not $not$libresoc.v:48036$1403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [4] - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:179361$13008_Y + connect \A \msr_read + connect \Y $not$libresoc.v:48036$1403_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:179363$13010 + cell $not $not$libresoc.v:48047$1416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \all_rd - connect \B \$13 - connect \Y $and$issuer_ls180.v:179363$13010_Y + connect \A \cu_st__rel_o_dly + connect \Y $not$libresoc.v:48047$1416_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$issuer_ls180.v:179365$13012 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:186" + cell $not $not$libresoc.v:48050$1419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_done - connect \B \$17 - connect \Y $and$issuer_ls180.v:179365$13012_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$issuer_ls180.v:179366$13013 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$issuer_ls180.v:179366$13013_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$issuer_ls180.v:179368$13015 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wr__rel_o - connect \B \$25 - connect \Y $and$issuer_ls180.v:179368$13015_Y + connect \A \pc_i_ok + connect \Y $not$libresoc.v:48050$1419_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$issuer_ls180.v:179371$13018 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + cell $not $not$libresoc.v:48051$1420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \$23 - connect \Y $and$issuer_ls180.v:179371$13018_Y + connect \A \corebusy_o + connect \Y $not$libresoc.v:48051$1420_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$issuer_ls180.v:179375$13022 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:48052$1421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \rok_l_q_rdok - connect \Y $and$issuer_ls180.v:179375$13022_Y + connect \A \pc_changed + connect \Y $not$libresoc.v:48052$1421_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$issuer_ls180.v:179377$13024 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + cell $not $not$libresoc.v:48053$1422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_any - connect \B \$39 - connect \Y $and$issuer_ls180.v:179377$13024_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$issuer_ls180.v:179378$13025 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \req_l_q_req - connect \B \cu_wrmask_o - connect \Y $and$issuer_ls180.v:179378$13025_Y + connect \A \corebusy_o + connect \Y $not$libresoc.v:48053$1422_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$issuer_ls180.v:179380$13027 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:48054$1423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$41 - connect \B \$45 - connect \Y $and$issuer_ls180.v:179380$13027_Y + connect \A \pc_changed + connect \Y $not$libresoc.v:48054$1423_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$issuer_ls180.v:179382$13029 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:48055$1424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$49 - connect \B \alu_trap0_n_ready_i - connect \Y $and$issuer_ls180.v:179382$13029_Y + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:48055$1424_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$issuer_ls180.v:179383$13030 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:48056$1425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$51 - connect \B \alu_trap0_n_valid_o - connect \Y $and$issuer_ls180.v:179383$13030_Y + connect \A \core_reset_i + connect \Y $not$libresoc.v:48056$1425_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$issuer_ls180.v:179384$13031 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + cell $not $not$libresoc.v:48061$1430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$53 - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:179384$13031_Y + connect \A \corebusy_o + connect \Y $not$libresoc.v:48061$1430_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$issuer_ls180.v:179389$13036 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + cell $not $not$libresoc.v:48062$1431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_trap0_n_valid_o - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:179389$13036_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$issuer_ls180.v:179390$13037 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $and$issuer_ls180.v:179390$13037_Y + connect \A \corebusy_o + connect \Y $not$libresoc.v:48062$1431_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$issuer_ls180.v:179393$13040 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + cell $not $not$libresoc.v:48063$1432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \o_ok - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:179393$13040_Y + connect \A \corebusy_o + connect \Y $not$libresoc.v:48063$1432_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$issuer_ls180.v:179394$13041 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:48064$1433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fast1_ok - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:179394$13041_Y + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:48064$1433_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$issuer_ls180.v:179395$13042 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:48065$1434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fast2_ok - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:179395$13042_Y + connect \A \core_reset_i + connect \Y $not$libresoc.v:48065$1434_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$issuer_ls180.v:179396$13043 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:48067$1436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \nia_ok - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:179396$13043_Y + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:48067$1436_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$issuer_ls180.v:179397$13044 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:48068$1437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \msr_ok - connect \B \cu_busy_o - connect \Y $and$issuer_ls180.v:179397$13044_Y + connect \A \core_reset_i + connect \Y $not$libresoc.v:48068$1437_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$issuer_ls180.v:179403$13050 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:48070$1439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_trap0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $and$issuer_ls180.v:179403$13050_Y + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:48070$1439_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$issuer_ls180.v:179404$13051 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:48071$1440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_trap0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $and$issuer_ls180.v:179404$13051_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$issuer_ls180.v:179405$13052 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$issuer_ls180.v:179405$13052_Y + connect \A \core_reset_i + connect \Y $not$libresoc.v:48071$1440_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$issuer_ls180.v:179406$13053 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:48073$1442 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$93 - connect \B 4'1111 - connect \Y $and$issuer_ls180.v:179406$13053_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:48073$1442_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$issuer_ls180.v:179379$13026 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:48074$1443 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$43 - connect \B 1'0 - connect \Y $eq$issuer_ls180.v:179379$13026_Y + connect \A \core_reset_i + connect \Y $not$libresoc.v:48074$1443_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$issuer_ls180.v:179381$13028 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:48077$1446 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o - connect \B 1'0 - connect \Y $eq$issuer_ls180.v:179381$13028_Y + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:48077$1446_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:179362$13009 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:48078$1447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $not$issuer_ls180.v:179362$13009_Y + connect \A \core_reset_i + connect \Y $not$libresoc.v:48078$1447_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$issuer_ls180.v:179364$13011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:255" + cell $not $not$libresoc.v:48080$1449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $not$issuer_ls180.v:179364$13011_Y + connect \A \msr_read + connect \Y $not$libresoc.v:48080$1449_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$issuer_ls180.v:179367$13014 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:48081$1450 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wrmask_o - connect \Y $not$issuer_ls180.v:179367$13014_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:48081$1450_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$issuer_ls180.v:179370$13017 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:48082$1451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:179370$13017_Y + connect \A \core_reset_i + connect \Y $not$libresoc.v:48082$1451_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$issuer_ls180.v:179376$13023 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + cell $not $not$libresoc.v:48084$1453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_trap0_n_ready_i - connect \Y $not$issuer_ls180.v:179376$13023_Y + connect \A \corebusy_o + connect \Y $not$libresoc.v:48084$1453_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$issuer_ls180.v:179391$13038 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:48085$1454 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rd__rel_o - connect \Y $not$issuer_ls180.v:179391$13038_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:48085$1454_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$issuer_ls180.v:179407$13054 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:48087$1456 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rdmaskn_i - connect \Y $not$issuer_ls180.v:179407$13054_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_reset_i + connect \Y $not$libresoc.v:48087$1456_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$issuer_ls180.v:179374$13021 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:48089$1458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$33 - connect \B \$35 - connect \Y $or$issuer_ls180.v:179374$13021_Y + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:48089$1458_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$issuer_ls180.v:179385$13032 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:48090$1459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $or$issuer_ls180.v:179385$13032_Y + connect \A \core_reset_i + connect \Y $not$libresoc.v:48090$1459_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$issuer_ls180.v:179386$13033 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:161" + cell $or $or$libresoc.v:48086$1455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $or$issuer_ls180.v:179386$13033_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$issuer_ls180.v:179387$13034 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$issuer_ls180.v:179387$13034_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$issuer_ls180.v:179388$13035 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$issuer_ls180.v:179388$13035_Y + connect \A 1'0 + connect \B \dbg_core_rst_o + connect \Y $or$libresoc.v:48086$1455_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$issuer_ls180.v:179392$13039 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $pos$libresoc.v:48043$1411 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $or$issuer_ls180.v:179392$13039_Y + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:48043$1410_Y + connect \Y $pos$libresoc.v:48043$1411_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$issuer_ls180.v:179402$13049 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $pos$libresoc.v:48044$1413 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$6 - connect \B \cu_rd__go_i - connect \Y $or$issuer_ls180.v:179402$13049_Y + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:48044$1412_Y + connect \Y $pos$libresoc.v:48044$1413_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$issuer_ls180.v:179347$12994 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:48059$1428 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $reduce_and$issuer_ls180.v:179347$12994_Y + connect \A \$36 + connect \Y $reduce_or$libresoc.v:48059$1428_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$issuer_ls180.v:179369$13016 + attribute \src "libresoc.v:48038.19-48038.42" + cell $shr $shr$libresoc.v:48038$1405 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \$27 - connect \Y $reduce_or$issuer_ls180.v:179369$13016_Y + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \imem_f_instr_o + connect \B \$102 + connect \Y $shr$libresoc.v:48038$1405_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$issuer_ls180.v:179372$13019 + attribute \src "libresoc.v:48040.19-48040.42" + cell $shr $shr$libresoc.v:48040$1407 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $reduce_or$issuer_ls180.v:179372$13019_Y + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \imem_f_instr_o + connect \B \$106 + connect \Y $shr$libresoc.v:48040$1407_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$issuer_ls180.v:179373$13020 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:373" + cell $sub $sub$libresoc.v:48045$1414 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $reduce_or$issuer_ls180.v:179373$13020_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:179398$13045 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src1_i - connect \S \src_l_q_src [0] - connect \Y $ternary$issuer_ls180.v:179398$13045_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:179399$13046 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src2_i - connect \S \src_l_q_src [1] - connect \Y $ternary$issuer_ls180.v:179399$13046_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:179400$13047 - parameter \WIDTH 64 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $ternary$issuer_ls180.v:179400$13047_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$issuer_ls180.v:179401$13048 - parameter \WIDTH 64 - connect \A \src_r3 - connect \B \src4_i - connect \S \src_l_q_src [3] - connect \Y $ternary$issuer_ls180.v:179401$13048_Y - end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:179482.14-179488.4" - cell \alu_l$42 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \issue__data_o + connect \B 1'1 + connect \Y $sub$libresoc.v:48045$1414_Y end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:179489.13-179518.4" - cell \alu_trap0 \alu_trap0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \fast1 \alu_trap0_fast1 - connect \fast1$1 \alu_trap0_fast1$1 - connect \fast1_ok \fast1_ok - connect \fast2 \alu_trap0_fast2 - connect \fast2$2 \alu_trap0_fast2$2 - connect \fast2_ok \fast2_ok - connect \msr \alu_trap0_msr - connect \msr_ok \msr_ok - connect \n_ready_i \alu_trap0_n_ready_i - connect \n_valid_o \alu_trap0_n_valid_o - connect \nia \alu_trap0_nia - connect \nia_ok \nia_ok - connect \o \alu_trap0_o - connect \o_ok \o_ok - connect \p_ready_o \alu_trap0_p_ready_o - connect \p_valid_i \alu_trap0_p_valid_i - connect \ra \alu_trap0_ra - connect \rb \alu_trap0_rb - connect \trap_op__cia \alu_trap0_trap_op__cia - connect \trap_op__fn_unit \alu_trap0_trap_op__fn_unit - connect \trap_op__insn \alu_trap0_trap_op__insn - connect \trap_op__insn_type \alu_trap0_trap_op__insn_type - connect \trap_op__is_32bit \alu_trap0_trap_op__is_32bit - connect \trap_op__msr \alu_trap0_trap_op__msr - connect \trap_op__trapaddr \alu_trap0_trap_op__trapaddr - connect \trap_op__traptype \alu_trap0_trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:157" + cell $sub $sub$libresoc.v:48075$1444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \delay + connect \B 1'1 + connect \Y $sub$libresoc.v:48075$1444_Y end attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:179519.15-179525.4" - cell \alui_l$41 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui + attribute \src "libresoc.v:48248.7-48273.4" + cell \dbg \dbg + connect \clk \clk + connect \core_dbg_msr \dbg_core_dbg_msr + connect \core_dbg_pc \dbg_core_dbg_pc + connect \core_rst_o \dbg_core_rst_o + connect \core_stop_o \dbg_core_stop_o + connect \core_stopped_i \dbg_core_stopped_i + connect \d_cr_ack \dbg_d_cr_ack + connect \d_cr_data \dbg_d_cr_data + connect \d_cr_req \dbg_d_cr_req + connect \d_gpr_ack \dbg_d_gpr_ack + connect \d_gpr_addr \dbg_d_gpr_addr + connect \d_gpr_data \dbg_d_gpr_data + connect \d_gpr_req \dbg_d_gpr_req + connect \d_xer_ack \dbg_d_xer_ack + connect \d_xer_data \dbg_d_xer_data + connect \d_xer_req \dbg_d_xer_req + connect \dmi_ack_o \dbg_dmi_ack_o + connect \dmi_addr_i \dbg_dmi_addr_i + connect \dmi_din \dbg_dmi_din + connect \dmi_dout \dbg_dmi_dout + connect \dmi_req_i \dbg_dmi_req_i + connect \dmi_we_i \dbg_dmi_we_i + connect \rst \rst + connect \terminate_i \dbg_terminate_i end attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:179526.14-179532.4" - cell \opc_l$37 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_opc \opc_l_q_opc - connect \r_opc \opc_l_r_opc - connect \s_opc \opc_l_s_opc + attribute \src "libresoc.v:48274.8-48332.4" + cell \dec2 \dec2 + connect \asmcode \dec2_asmcode + connect \bigendian \dec2_bigendian + connect \cia \dec2_cia + connect \cr_in1 \dec2_cr_in1 + connect \cr_in1_ok \dec2_cr_in1_ok + connect \cr_in2 \dec2_cr_in2 + connect \cr_in2$1 \dec2_cr_in2$1 + connect \cr_in2_ok \dec2_cr_in2_ok + connect \cr_in2_ok$2 \dec2_cr_in2_ok$2 + connect \cr_out \dec2_cr_out + connect \cr_out_ok \dec2_cr_out_ok + connect \cr_rd \dec2_cr_rd + connect \cr_rd_ok \dec2_cr_rd_ok + connect \cr_wr \dec2_cr_wr + connect \cr_wr_ok \dec2_cr_wr_ok + connect \cur_dec \dec2_cur_dec + connect \cur_eint \dec2_cur_eint + connect \cur_msr \dec2_cur_msr + connect \cur_pc \dec2_cur_pc + connect \ea \dec2_ea + connect \ea_ok \dec2_ea_ok + connect \fast1 \dec2_fast1 + connect \fast1_ok \dec2_fast1_ok + connect \fast2 \dec2_fast2 + connect \fast2_ok \dec2_fast2_ok + connect \fasto1 \dec2_fasto1 + connect \fasto1_ok \dec2_fasto1_ok + connect \fasto2 \dec2_fasto2 + connect \fasto2_ok \dec2_fasto2_ok + connect \fn_unit \dec2_fn_unit + connect \input_carry \dec2_input_carry + connect \insn \dec2_insn + connect \insn_type \dec2_insn_type + connect \is_32bit \dec2_is_32bit + connect \lk \dec2_lk + connect \msr \dec2_msr + connect \oe \dec2_oe + connect \oe_ok \dec2_oe_ok + connect \raw_opcode_in \dec2_raw_opcode_in + connect \rc \dec2_rc + connect \rc_ok \dec2_rc_ok + connect \reg1 \dec2_reg1 + connect \reg1_ok \dec2_reg1_ok + connect \reg2 \dec2_reg2 + connect \reg2_ok \dec2_reg2_ok + connect \reg3 \dec2_reg3 + connect \reg3_ok \dec2_reg3_ok + connect \rego \dec2_rego + connect \rego_ok \dec2_rego_ok + connect \spr1 \dec2_spr1 + connect \spr1_ok \dec2_spr1_ok + connect \spro \dec2_spro + connect \spro_ok \dec2_spro_ok + connect \trapaddr \dec2_trapaddr + connect \traptype \dec2_traptype + connect \xer_in \dec2_xer_in + connect \xer_out \dec2_xer_out end attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:179533.14-179539.4" - cell \req_l$38 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \r_req \req_l_r_req - connect \s_req \req_l_s_req + attribute \src "libresoc.v:48333.8-48348.4" + cell \imem \imem + connect \a_pc_i \imem_a_pc_i + connect \a_valid_i \imem_a_valid_i + connect \clk \clk + connect \f_busy_o \imem_f_busy_o + connect \f_instr_o \imem_f_instr_o + connect \f_valid_i \imem_f_valid_i + connect \ibus__ack \ibus__ack + connect \ibus__adr \ibus__adr + connect \ibus__cyc \ibus__cyc + connect \ibus__dat_r \ibus__dat_r + connect \ibus__err \ibus__err + connect \ibus__sel \ibus__sel + connect \ibus__stb \ibus__stb + connect \rst \rst end attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:179540.14-179546.4" - cell \rok_l$40 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \r_rdok \rok_l_r_rdok - connect \s_rdok \rok_l_s_rdok + attribute \src "libresoc.v:48349.8-48470.4" + cell \jtag \jtag + connect \TAP_bus__tck \TAP_bus__tck + connect \TAP_bus__tdi \TAP_bus__tdi + connect \TAP_bus__tdo \TAP_bus__tdo + connect \TAP_bus__tms \TAP_bus__tms + connect \clk \clk + connect \dmi0_ack_o \jtag_dmi0_ack_o + connect \dmi0_addr_i \jtag_dmi0_addr_i + connect \dmi0_din \jtag_dmi0_din + connect \dmi0_dout \jtag_dmi0_dout + connect \dmi0_req_i \jtag_dmi0_req_i + connect \dmi0_we_i \jtag_dmi0_we_i + connect \gpio_gpio0__core__i \gpio_gpio0__core__i + connect \gpio_gpio0__core__o \gpio_gpio0__core__o + connect \gpio_gpio0__core__oe \gpio_gpio0__core__oe + connect \gpio_gpio0__pad__i \gpio_gpio0__pad__i + connect \gpio_gpio0__pad__o \gpio_gpio0__pad__o + connect \gpio_gpio0__pad__oe \gpio_gpio0__pad__oe + connect \gpio_gpio10__core__i \gpio_gpio10__core__i + connect \gpio_gpio10__core__o \gpio_gpio10__core__o + connect \gpio_gpio10__core__oe \gpio_gpio10__core__oe + connect \gpio_gpio10__pad__i \gpio_gpio10__pad__i + connect \gpio_gpio10__pad__o \gpio_gpio10__pad__o + connect \gpio_gpio10__pad__oe \gpio_gpio10__pad__oe + connect \gpio_gpio11__core__i \gpio_gpio11__core__i + connect \gpio_gpio11__core__o \gpio_gpio11__core__o + connect \gpio_gpio11__core__oe \gpio_gpio11__core__oe + connect \gpio_gpio11__pad__i \gpio_gpio11__pad__i + connect \gpio_gpio11__pad__o \gpio_gpio11__pad__o + connect \gpio_gpio11__pad__oe \gpio_gpio11__pad__oe + connect \gpio_gpio12__core__i \gpio_gpio12__core__i + connect \gpio_gpio12__core__o \gpio_gpio12__core__o + connect \gpio_gpio12__core__oe \gpio_gpio12__core__oe + connect \gpio_gpio12__pad__i \gpio_gpio12__pad__i + connect \gpio_gpio12__pad__o \gpio_gpio12__pad__o + connect \gpio_gpio12__pad__oe \gpio_gpio12__pad__oe + connect \gpio_gpio13__core__i \gpio_gpio13__core__i + connect \gpio_gpio13__core__o \gpio_gpio13__core__o + connect \gpio_gpio13__core__oe \gpio_gpio13__core__oe + connect \gpio_gpio13__pad__i \gpio_gpio13__pad__i + connect \gpio_gpio13__pad__o \gpio_gpio13__pad__o + connect \gpio_gpio13__pad__oe \gpio_gpio13__pad__oe + connect \gpio_gpio14__core__i \gpio_gpio14__core__i + connect \gpio_gpio14__core__o \gpio_gpio14__core__o + connect \gpio_gpio14__core__oe \gpio_gpio14__core__oe + connect \gpio_gpio14__pad__i \gpio_gpio14__pad__i + connect \gpio_gpio14__pad__o \gpio_gpio14__pad__o + connect \gpio_gpio14__pad__oe \gpio_gpio14__pad__oe + connect \gpio_gpio15__core__i \gpio_gpio15__core__i + connect \gpio_gpio15__core__o \gpio_gpio15__core__o + connect \gpio_gpio15__core__oe \gpio_gpio15__core__oe + connect \gpio_gpio15__pad__i \gpio_gpio15__pad__i + connect \gpio_gpio15__pad__o \gpio_gpio15__pad__o + connect \gpio_gpio15__pad__oe \gpio_gpio15__pad__oe + connect \gpio_gpio1__core__i \gpio_gpio1__core__i + connect \gpio_gpio1__core__o \gpio_gpio1__core__o + connect \gpio_gpio1__core__oe \gpio_gpio1__core__oe + connect \gpio_gpio1__pad__i \gpio_gpio1__pad__i + connect \gpio_gpio1__pad__o \gpio_gpio1__pad__o + connect \gpio_gpio1__pad__oe \gpio_gpio1__pad__oe + connect \gpio_gpio2__core__i \gpio_gpio2__core__i + connect \gpio_gpio2__core__o \gpio_gpio2__core__o + connect \gpio_gpio2__core__oe \gpio_gpio2__core__oe + connect \gpio_gpio2__pad__i \gpio_gpio2__pad__i + connect \gpio_gpio2__pad__o \gpio_gpio2__pad__o + connect \gpio_gpio2__pad__oe \gpio_gpio2__pad__oe + connect \gpio_gpio3__core__i \gpio_gpio3__core__i + connect \gpio_gpio3__core__o \gpio_gpio3__core__o + connect \gpio_gpio3__core__oe \gpio_gpio3__core__oe + connect \gpio_gpio3__pad__i \gpio_gpio3__pad__i + connect \gpio_gpio3__pad__o \gpio_gpio3__pad__o + connect \gpio_gpio3__pad__oe \gpio_gpio3__pad__oe + connect \gpio_gpio4__core__i \gpio_gpio4__core__i + connect \gpio_gpio4__core__o \gpio_gpio4__core__o + connect \gpio_gpio4__core__oe \gpio_gpio4__core__oe + connect \gpio_gpio4__pad__i \gpio_gpio4__pad__i + connect \gpio_gpio4__pad__o \gpio_gpio4__pad__o + connect \gpio_gpio4__pad__oe \gpio_gpio4__pad__oe + connect \gpio_gpio5__core__i \gpio_gpio5__core__i + connect \gpio_gpio5__core__o \gpio_gpio5__core__o + connect \gpio_gpio5__core__oe \gpio_gpio5__core__oe + connect \gpio_gpio5__pad__i \gpio_gpio5__pad__i + connect \gpio_gpio5__pad__o \gpio_gpio5__pad__o + connect \gpio_gpio5__pad__oe \gpio_gpio5__pad__oe + connect \gpio_gpio6__core__i \gpio_gpio6__core__i + connect \gpio_gpio6__core__o \gpio_gpio6__core__o + connect \gpio_gpio6__core__oe \gpio_gpio6__core__oe + connect \gpio_gpio6__pad__i \gpio_gpio6__pad__i + connect \gpio_gpio6__pad__o \gpio_gpio6__pad__o + connect \gpio_gpio6__pad__oe \gpio_gpio6__pad__oe + connect \gpio_gpio7__core__i \gpio_gpio7__core__i + connect \gpio_gpio7__core__o \gpio_gpio7__core__o + connect \gpio_gpio7__core__oe \gpio_gpio7__core__oe + connect \gpio_gpio7__pad__i \gpio_gpio7__pad__i + connect \gpio_gpio7__pad__o \gpio_gpio7__pad__o + connect \gpio_gpio7__pad__oe \gpio_gpio7__pad__oe + connect \gpio_gpio8__core__i \gpio_gpio8__core__i + connect \gpio_gpio8__core__o \gpio_gpio8__core__o + connect \gpio_gpio8__core__oe \gpio_gpio8__core__oe + connect \gpio_gpio8__pad__i \gpio_gpio8__pad__i + connect \gpio_gpio8__pad__o \gpio_gpio8__pad__o + connect \gpio_gpio8__pad__oe \gpio_gpio8__pad__oe + connect \gpio_gpio9__core__i \gpio_gpio9__core__i + connect \gpio_gpio9__core__o \gpio_gpio9__core__o + connect \gpio_gpio9__core__oe \gpio_gpio9__core__oe + connect \gpio_gpio9__pad__i \gpio_gpio9__pad__i + connect \gpio_gpio9__pad__o \gpio_gpio9__pad__o + connect \gpio_gpio9__pad__oe \gpio_gpio9__pad__oe + connect \jtag_wb__ack \jtag_wb__ack + connect \jtag_wb__adr \jtag_wb__adr + connect \jtag_wb__cyc \jtag_wb__cyc + connect \jtag_wb__dat_r \jtag_wb__dat_r + connect \jtag_wb__dat_w \jtag_wb__dat_w + connect \jtag_wb__sel \jtag_wb__sel + connect \jtag_wb__stb \jtag_wb__stb + connect \jtag_wb__we \jtag_wb__we + connect \rst \rst + connect \uart_rx__core__i \uart_rx__core__i + connect \uart_rx__pad__i \uart_rx__pad__i + connect \uart_tx__core__o \uart_tx__core__o + connect \uart_tx__pad__o \uart_tx__pad__o end attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:179547.14-179552.4" - cell \rst_l$39 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_rst \rst_l_r_rst - connect \s_rst \rst_l_s_rst + attribute \src "libresoc.v:48471.12-48485.4" + cell \xics_icp \xics_icp + connect \clk \clk + connect \core_irq_o \xics_icp_core_irq_o + connect \icp_wb__ack \icp_wb__ack + connect \icp_wb__adr \icp_wb__adr + connect \icp_wb__cyc \icp_wb__cyc + connect \icp_wb__dat_r \icp_wb__dat_r + connect \icp_wb__dat_w \icp_wb__dat_w + connect \icp_wb__sel \icp_wb__sel + connect \icp_wb__stb \icp_wb__stb + connect \icp_wb__we \icp_wb__we + connect \ics_i_pri \xics_icp_ics_i_pri + connect \ics_i_src \xics_icp_ics_i_src + connect \rst \rst end attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:179553.14-179559.4" - cell \src_l$36 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_src \src_l_q_src - connect \r_src \src_l_r_src - connect \s_src \src_l_s_src + attribute \src "libresoc.v:48486.12-48499.4" + cell \xics_ics \xics_ics + connect \clk \clk + connect \icp_o_pri \xics_ics_icp_o_pri + connect \icp_o_src \xics_ics_icp_o_src + connect \ics_wb__ack \ics_wb__ack + connect \ics_wb__adr \ics_wb__adr + connect \ics_wb__cyc \ics_wb__cyc + connect \ics_wb__dat_r \ics_wb__dat_r + connect \ics_wb__dat_w \ics_wb__dat_w + connect \ics_wb__stb \ics_wb__stb + connect \ics_wb__we \ics_wb__we + connect \int_level_i \int_level_i + connect \rst \rst end - attribute \src "issuer_ls180.v:178759.7-178759.20" - process $proc$issuer_ls180.v:178759$13206 + attribute \src "libresoc.v:46401.7-46401.20" + process $proc$libresoc.v:46401$1904 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "issuer_ls180.v:178885.7-178885.24" - process $proc$issuer_ls180.v:178885$13207 + attribute \src "libresoc.v:46531.7-46531.25" + process $proc$libresoc.v:46531$1905 assign { } { } - assign $1\all_rd_dly[0:0] 1'0 + assign $1\bigendian_i[0:0] 1'0 sync always sync init - update \all_rd_dly $1\all_rd_dly[0:0] + update \bigendian_i $1\bigendian_i[0:0] end - attribute \src "issuer_ls180.v:178895.7-178895.26" - process $proc$issuer_ls180.v:178895$13208 + attribute \src "libresoc.v:46543.13-46543.33" + process $proc$libresoc.v:46543$1906 assign { } { } - assign $1\alu_done_dly[0:0] 1'0 + assign $1\core_asmcode[7:0] 8'00000000 sync always sync init - update \alu_done_dly $1\alu_done_dly[0:0] + update \core_asmcode $1\core_asmcode[7:0] end - attribute \src "issuer_ls180.v:178903.7-178903.25" - process $proc$issuer_ls180.v:178903$13209 + attribute \src "libresoc.v:46549.14-46549.50" + process $proc$libresoc.v:46549$1907 assign { } { } - assign $1\alu_l_r_alu[0:0] 1'1 + assign $1\core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \alu_l_r_alu $1\alu_l_r_alu[0:0] + update \core_core_cia $1\core_core_cia[63:0] end - attribute \src "issuer_ls180.v:178939.14-178939.59" - process $proc$issuer_ls180.v:178939$13210 + attribute \src "libresoc.v:46553.13-46553.36" + process $proc$libresoc.v:46553$1908 assign { } { } - assign $1\alu_trap0_trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_core_cr_rd[7:0] 8'00000000 sync always sync init - update \alu_trap0_trap_op__cia $1\alu_trap0_trap_op__cia[63:0] + update \core_core_cr_rd $1\core_core_cr_rd[7:0] end - attribute \src "issuer_ls180.v:178956.14-178956.50" - process $proc$issuer_ls180.v:178956$13211 + attribute \src "libresoc.v:46557.7-46557.32" + process $proc$libresoc.v:46557$1909 assign { } { } - assign $1\alu_trap0_trap_op__fn_unit[11:0] 12'000000000000 + assign $1\core_core_cr_rd_ok[0:0] 1'0 sync always sync init - update \alu_trap0_trap_op__fn_unit $1\alu_trap0_trap_op__fn_unit[11:0] + update \core_core_cr_rd_ok $1\core_core_cr_rd_ok[0:0] end - attribute \src "issuer_ls180.v:178960.14-178960.45" - process $proc$issuer_ls180.v:178960$13212 + attribute \src "libresoc.v:46561.13-46561.36" + process $proc$libresoc.v:46561$1910 assign { } { } - assign $1\alu_trap0_trap_op__insn[31:0] 0 + assign $1\core_core_cr_wr[7:0] 8'00000000 sync always sync init - update \alu_trap0_trap_op__insn $1\alu_trap0_trap_op__insn[31:0] + update \core_core_cr_wr $1\core_core_cr_wr[7:0] end - attribute \src "issuer_ls180.v:179038.13-179038.49" - process $proc$issuer_ls180.v:179038$13213 + attribute \src "libresoc.v:46565.7-46565.32" + process $proc$libresoc.v:46565$1911 assign { } { } - assign $1\alu_trap0_trap_op__insn_type[6:0] 7'0000000 + assign $1\core_core_cr_wr_ok[0:0] 1'0 sync always sync init - update \alu_trap0_trap_op__insn_type $1\alu_trap0_trap_op__insn_type[6:0] + update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0] end - attribute \src "issuer_ls180.v:179042.7-179042.41" - process $proc$issuer_ls180.v:179042$13214 + attribute \src "libresoc.v:46582.14-46582.41" + process $proc$libresoc.v:46582$1912 assign { } { } - assign $1\alu_trap0_trap_op__is_32bit[0:0] 1'0 + assign $1\core_core_fn_unit[11:0] 12'000000000000 sync always sync init - update \alu_trap0_trap_op__is_32bit $1\alu_trap0_trap_op__is_32bit[0:0] + update \core_core_fn_unit $1\core_core_fn_unit[11:0] end - attribute \src "issuer_ls180.v:179046.14-179046.59" - process $proc$issuer_ls180.v:179046$13215 + attribute \src "libresoc.v:46590.13-46590.41" + process $proc$libresoc.v:46590$1913 assign { } { } - assign $1\alu_trap0_trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_core_input_carry[1:0] 2'00 sync always sync init - update \alu_trap0_trap_op__msr $1\alu_trap0_trap_op__msr[63:0] + update \core_core_input_carry $1\core_core_input_carry[1:0] end - attribute \src "issuer_ls180.v:179050.14-179050.52" - process $proc$issuer_ls180.v:179050$13216 + attribute \src "libresoc.v:46594.14-46594.36" + process $proc$libresoc.v:46594$1914 assign { } { } - assign $1\alu_trap0_trap_op__trapaddr[12:0] 13'0000000000000 + assign $1\core_core_insn[31:0] 0 sync always sync init - update \alu_trap0_trap_op__trapaddr $1\alu_trap0_trap_op__trapaddr[12:0] + update \core_core_insn $1\core_core_insn[31:0] end - attribute \src "issuer_ls180.v:179054.13-179054.48" - process $proc$issuer_ls180.v:179054$13217 + attribute \src "libresoc.v:46672.13-46672.40" + process $proc$libresoc.v:46672$1915 assign { } { } - assign $1\alu_trap0_trap_op__traptype[6:0] 7'0000000 + assign $1\core_core_insn_type[6:0] 7'0000000 sync always sync init - update \alu_trap0_trap_op__traptype $1\alu_trap0_trap_op__traptype[6:0] + update \core_core_insn_type $1\core_core_insn_type[6:0] end - attribute \src "issuer_ls180.v:179060.7-179060.27" - process $proc$issuer_ls180.v:179060$13218 + attribute \src "libresoc.v:46676.7-46676.32" + process $proc$libresoc.v:46676$1916 assign { } { } - assign $1\alui_l_r_alui[0:0] 1'1 + assign $1\core_core_is_32bit[0:0] 1'0 sync always sync init - update \alui_l_r_alui $1\alui_l_r_alui[0:0] + update \core_core_is_32bit $1\core_core_is_32bit[0:0] end - attribute \src "issuer_ls180.v:179092.14-179092.47" - process $proc$issuer_ls180.v:179092$13219 + attribute \src "libresoc.v:46680.7-46680.26" + process $proc$libresoc.v:46680$1917 assign { } { } - assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_core_lk[0:0] 1'0 sync always sync init - update \data_r0__o $1\data_r0__o[63:0] + update \core_core_lk $1\core_core_lk[0:0] end - attribute \src "issuer_ls180.v:179096.7-179096.27" - process $proc$issuer_ls180.v:179096$13220 + attribute \src "libresoc.v:46684.14-46684.50" + process $proc$libresoc.v:46684$1918 assign { } { } - assign $1\data_r0__o_ok[0:0] 1'0 + assign $1\core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \data_r0__o_ok $1\data_r0__o_ok[0:0] + update \core_core_msr $1\core_core_msr[63:0] end - attribute \src "issuer_ls180.v:179100.14-179100.51" - process $proc$issuer_ls180.v:179100$13221 + attribute \src "libresoc.v:46688.7-46688.26" + process $proc$libresoc.v:46688$1919 assign { } { } - assign $1\data_r1__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_core_oe[0:0] 1'0 sync always sync init - update \data_r1__fast1 $1\data_r1__fast1[63:0] + update \core_core_oe $1\core_core_oe[0:0] end - attribute \src "issuer_ls180.v:179104.7-179104.31" - process $proc$issuer_ls180.v:179104$13222 + attribute \src "libresoc.v:46692.7-46692.29" + process $proc$libresoc.v:46692$1920 assign { } { } - assign $1\data_r1__fast1_ok[0:0] 1'0 + assign $1\core_core_oe_ok[0:0] 1'0 sync always sync init - update \data_r1__fast1_ok $1\data_r1__fast1_ok[0:0] + update \core_core_oe_ok $1\core_core_oe_ok[0:0] end - attribute \src "issuer_ls180.v:179108.14-179108.51" - process $proc$issuer_ls180.v:179108$13223 + attribute \src "libresoc.v:46696.7-46696.26" + process $proc$libresoc.v:46696$1921 assign { } { } - assign $1\data_r2__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_core_rc[0:0] 1'0 sync always sync init - update \data_r2__fast2 $1\data_r2__fast2[63:0] + update \core_core_rc $1\core_core_rc[0:0] end - attribute \src "issuer_ls180.v:179112.7-179112.31" - process $proc$issuer_ls180.v:179112$13224 + attribute \src "libresoc.v:46700.7-46700.29" + process $proc$libresoc.v:46700$1922 assign { } { } - assign $1\data_r2__fast2_ok[0:0] 1'0 + assign $1\core_core_rc_ok[0:0] 1'0 sync always sync init - update \data_r2__fast2_ok $1\data_r2__fast2_ok[0:0] + update \core_core_rc_ok $1\core_core_rc_ok[0:0] end - attribute \src "issuer_ls180.v:179116.14-179116.49" - process $proc$issuer_ls180.v:179116$13225 + attribute \src "libresoc.v:46704.14-46704.43" + process $proc$libresoc.v:46704$1923 assign { } { } - assign $1\data_r3__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_core_trapaddr[12:0] 13'0000000000000 sync always sync init - update \data_r3__nia $1\data_r3__nia[63:0] + update \core_core_trapaddr $1\core_core_trapaddr[12:0] end - attribute \src "issuer_ls180.v:179120.7-179120.29" - process $proc$issuer_ls180.v:179120$13226 + attribute \src "libresoc.v:46708.13-46708.39" + process $proc$libresoc.v:46708$1924 assign { } { } - assign $1\data_r3__nia_ok[0:0] 1'0 + assign $1\core_core_traptype[6:0] 7'0000000 sync always sync init - update \data_r3__nia_ok $1\data_r3__nia_ok[0:0] + update \core_core_traptype $1\core_core_traptype[6:0] end - attribute \src "issuer_ls180.v:179124.14-179124.49" - process $proc$issuer_ls180.v:179124$13227 + attribute \src "libresoc.v:46712.13-46712.31" + process $proc$libresoc.v:46712$1925 assign { } { } - assign $1\data_r4__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_cr_in1[2:0] 3'000 sync always sync init - update \data_r4__msr $1\data_r4__msr[63:0] + update \core_cr_in1 $1\core_cr_in1[2:0] end - attribute \src "issuer_ls180.v:179128.7-179128.29" - process $proc$issuer_ls180.v:179128$13228 + attribute \src "libresoc.v:46716.7-46716.28" + process $proc$libresoc.v:46716$1926 assign { } { } - assign $1\data_r4__msr_ok[0:0] 1'0 + assign $1\core_cr_in1_ok[0:0] 1'0 sync always sync init - update \data_r4__msr_ok $1\data_r4__msr_ok[0:0] + update \core_cr_in1_ok $1\core_cr_in1_ok[0:0] end - attribute \src "issuer_ls180.v:179159.7-179159.25" - process $proc$issuer_ls180.v:179159$13229 + attribute \src "libresoc.v:46720.13-46720.31" + process $proc$libresoc.v:46720$1927 assign { } { } - assign $1\opc_l_r_opc[0:0] 1'1 + assign $1\core_cr_in2[2:0] 3'000 sync always sync init - update \opc_l_r_opc $1\opc_l_r_opc[0:0] + update \core_cr_in2 $1\core_cr_in2[2:0] end - attribute \src "issuer_ls180.v:179163.7-179163.25" - process $proc$issuer_ls180.v:179163$13230 + attribute \src "libresoc.v:46722.13-46722.36" + process $proc$libresoc.v:46722$1928 assign { } { } - assign $1\opc_l_s_opc[0:0] 1'0 + assign $0\core_cr_in2$39[2:0]$1929 3'000 sync always sync init - update \opc_l_s_opc $1\opc_l_s_opc[0:0] + update \core_cr_in2$39 $0\core_cr_in2$39[2:0]$1929 end - attribute \src "issuer_ls180.v:179270.13-179270.31" - process $proc$issuer_ls180.v:179270$13231 + attribute \src "libresoc.v:46728.7-46728.28" + process $proc$libresoc.v:46728$1930 assign { } { } - assign $1\prev_wr_go[4:0] 5'00000 + assign $1\core_cr_in2_ok[0:0] 1'0 sync always sync init - update \prev_wr_go $1\prev_wr_go[4:0] + update \core_cr_in2_ok $1\core_cr_in2_ok[0:0] end - attribute \src "issuer_ls180.v:179278.13-179278.32" - process $proc$issuer_ls180.v:179278$13232 + attribute \src "libresoc.v:46730.7-46730.33" + process $proc$libresoc.v:46730$1931 assign { } { } - assign $1\req_l_r_req[4:0] 5'11111 + assign $0\core_cr_in2_ok$40[0:0]$1932 1'0 sync always sync init - update \req_l_r_req $1\req_l_r_req[4:0] + update \core_cr_in2_ok$40 $0\core_cr_in2_ok$40[0:0]$1932 end - attribute \src "issuer_ls180.v:179282.13-179282.32" - process $proc$issuer_ls180.v:179282$13233 + attribute \src "libresoc.v:46736.13-46736.31" + process $proc$libresoc.v:46736$1933 assign { } { } - assign $1\req_l_s_req[4:0] 5'00000 + assign $1\core_cr_out[2:0] 3'000 sync always sync init - update \req_l_s_req $1\req_l_s_req[4:0] + update \core_cr_out $1\core_cr_out[2:0] end - attribute \src "issuer_ls180.v:179294.7-179294.26" - process $proc$issuer_ls180.v:179294$13234 + attribute \src "libresoc.v:46740.7-46740.28" + process $proc$libresoc.v:46740$1934 assign { } { } - assign $1\rok_l_r_rdok[0:0] 1'1 + assign $1\core_cr_out_ok[0:0] 1'0 sync always sync init - update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + update \core_cr_out_ok $1\core_cr_out_ok[0:0] end - attribute \src "issuer_ls180.v:179298.7-179298.26" - process $proc$issuer_ls180.v:179298$13235 + attribute \src "libresoc.v:46744.14-46744.45" + process $proc$libresoc.v:46744$1935 assign { } { } - assign $1\rok_l_s_rdok[0:0] 1'0 + assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + update \core_dec $1\core_dec[63:0] end - attribute \src "issuer_ls180.v:179302.7-179302.25" - process $proc$issuer_ls180.v:179302$13236 + attribute \src "libresoc.v:46748.13-46748.28" + process $proc$libresoc.v:46748$1936 assign { } { } - assign $1\rst_l_r_rst[0:0] 1'1 + assign $1\core_ea[4:0] 5'00000 sync always sync init - update \rst_l_r_rst $1\rst_l_r_rst[0:0] + update \core_ea $1\core_ea[4:0] end - attribute \src "issuer_ls180.v:179306.7-179306.25" - process $proc$issuer_ls180.v:179306$13237 + attribute \src "libresoc.v:46752.7-46752.24" + process $proc$libresoc.v:46752$1937 assign { } { } - assign $1\rst_l_s_rst[0:0] 1'0 + assign $1\core_ea_ok[0:0] 1'0 sync always sync init - update \rst_l_s_rst $1\rst_l_s_rst[0:0] + update \core_ea_ok $1\core_ea_ok[0:0] end - attribute \src "issuer_ls180.v:179322.13-179322.31" - process $proc$issuer_ls180.v:179322$13238 + attribute \src "libresoc.v:46756.7-46756.23" + process $proc$libresoc.v:46756$1938 assign { } { } - assign $1\src_l_r_src[3:0] 4'1111 + assign $1\core_eint[0:0] 1'0 sync always sync init - update \src_l_r_src $1\src_l_r_src[3:0] + update \core_eint $1\core_eint[0:0] end - attribute \src "issuer_ls180.v:179326.13-179326.31" - process $proc$issuer_ls180.v:179326$13239 + attribute \src "libresoc.v:46760.13-46760.30" + process $proc$libresoc.v:46760$1939 assign { } { } - assign $1\src_l_s_src[3:0] 4'0000 + assign $1\core_fast1[2:0] 3'000 sync always sync init - update \src_l_s_src $1\src_l_s_src[3:0] + update \core_fast1 $1\core_fast1[2:0] end - attribute \src "issuer_ls180.v:179330.14-179330.43" - process $proc$issuer_ls180.v:179330$13240 + attribute \src "libresoc.v:46764.7-46764.27" + process $proc$libresoc.v:46764$1940 assign { } { } - assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_fast1_ok[0:0] 1'0 sync always sync init - update \src_r0 $1\src_r0[63:0] + update \core_fast1_ok $1\core_fast1_ok[0:0] end - attribute \src "issuer_ls180.v:179334.14-179334.43" - process $proc$issuer_ls180.v:179334$13241 + attribute \src "libresoc.v:46768.13-46768.30" + process $proc$libresoc.v:46768$1941 assign { } { } - assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_fast2[2:0] 3'000 sync always sync init - update \src_r1 $1\src_r1[63:0] + update \core_fast2 $1\core_fast2[2:0] end - attribute \src "issuer_ls180.v:179338.14-179338.43" - process $proc$issuer_ls180.v:179338$13242 + attribute \src "libresoc.v:46772.7-46772.27" + process $proc$libresoc.v:46772$1942 assign { } { } - assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_fast2_ok[0:0] 1'0 sync always sync init - update \src_r2 $1\src_r2[63:0] + update \core_fast2_ok $1\core_fast2_ok[0:0] end - attribute \src "issuer_ls180.v:179342.14-179342.43" - process $proc$issuer_ls180.v:179342$13243 + attribute \src "libresoc.v:46776.13-46776.31" + process $proc$libresoc.v:46776$1943 assign { } { } - assign $1\src_r3[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_fasto1[2:0] 3'000 sync always sync init - update \src_r3 $1\src_r3[63:0] + update \core_fasto1 $1\core_fasto1[2:0] end - attribute \src "issuer_ls180.v:179408.3-179409.39" - process $proc$issuer_ls180.v:179408$13055 + attribute \src "libresoc.v:46780.7-46780.28" + process $proc$libresoc.v:46780$1944 assign { } { } - assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next - sync posedge \coresync_clk - update \alu_l_r_alu $0\alu_l_r_alu[0:0] + assign $1\core_fasto1_ok[0:0] 1'0 + sync always + sync init + update \core_fasto1_ok $1\core_fasto1_ok[0:0] end - attribute \src "issuer_ls180.v:179410.3-179411.43" - process $proc$issuer_ls180.v:179410$13056 + attribute \src "libresoc.v:46784.13-46784.31" + process $proc$libresoc.v:46784$1945 assign { } { } - assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next - sync posedge \coresync_clk - update \alui_l_r_alui $0\alui_l_r_alui[0:0] + assign $1\core_fasto2[2:0] 3'000 + sync always + sync init + update \core_fasto2 $1\core_fasto2[2:0] end - attribute \src "issuer_ls180.v:179412.3-179413.29" - process $proc$issuer_ls180.v:179412$13057 + attribute \src "libresoc.v:46788.7-46788.28" + process $proc$libresoc.v:46788$1946 assign { } { } - assign $0\src_r3[63:0] \src_r3$next - sync posedge \coresync_clk - update \src_r3 $0\src_r3[63:0] + assign $1\core_fasto2_ok[0:0] 1'0 + sync always + sync init + update \core_fasto2_ok $1\core_fasto2_ok[0:0] end - attribute \src "issuer_ls180.v:179414.3-179415.29" - process $proc$issuer_ls180.v:179414$13058 + attribute \src "libresoc.v:46792.14-46792.45" + process $proc$libresoc.v:46792$1947 assign { } { } - assign $0\src_r2[63:0] \src_r2$next - sync posedge \coresync_clk - update \src_r2 $0\src_r2[63:0] + assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_msr $1\core_msr[63:0] end - attribute \src "issuer_ls180.v:179416.3-179417.29" - process $proc$issuer_ls180.v:179416$13059 + attribute \src "libresoc.v:46796.14-46796.44" + process $proc$libresoc.v:46796$1948 assign { } { } - assign $0\src_r1[63:0] \src_r1$next - sync posedge \coresync_clk - update \src_r1 $0\src_r1[63:0] + assign $1\core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_pc $1\core_pc[63:0] end - attribute \src "issuer_ls180.v:179418.3-179419.29" - process $proc$issuer_ls180.v:179418$13060 + attribute \src "libresoc.v:46800.13-46800.30" + process $proc$libresoc.v:46800$1949 assign { } { } - assign $0\src_r0[63:0] \src_r0$next - sync posedge \coresync_clk - update \src_r0 $0\src_r0[63:0] + assign $1\core_reg1[4:0] 5'00000 + sync always + sync init + update \core_reg1 $1\core_reg1[4:0] end - attribute \src "issuer_ls180.v:179420.3-179421.41" - process $proc$issuer_ls180.v:179420$13061 + attribute \src "libresoc.v:46804.7-46804.26" + process $proc$libresoc.v:46804$1950 assign { } { } - assign $0\data_r4__msr[63:0] \data_r4__msr$next - sync posedge \coresync_clk - update \data_r4__msr $0\data_r4__msr[63:0] + assign $1\core_reg1_ok[0:0] 1'0 + sync always + sync init + update \core_reg1_ok $1\core_reg1_ok[0:0] end - attribute \src "issuer_ls180.v:179422.3-179423.47" - process $proc$issuer_ls180.v:179422$13062 + attribute \src "libresoc.v:46808.13-46808.30" + process $proc$libresoc.v:46808$1951 assign { } { } - assign $0\data_r4__msr_ok[0:0] \data_r4__msr_ok$next - sync posedge \coresync_clk - update \data_r4__msr_ok $0\data_r4__msr_ok[0:0] + assign $1\core_reg2[4:0] 5'00000 + sync always + sync init + update \core_reg2 $1\core_reg2[4:0] end - attribute \src "issuer_ls180.v:179424.3-179425.41" - process $proc$issuer_ls180.v:179424$13063 + attribute \src "libresoc.v:46812.7-46812.26" + process $proc$libresoc.v:46812$1952 assign { } { } - assign $0\data_r3__nia[63:0] \data_r3__nia$next - sync posedge \coresync_clk - update \data_r3__nia $0\data_r3__nia[63:0] + assign $1\core_reg2_ok[0:0] 1'0 + sync always + sync init + update \core_reg2_ok $1\core_reg2_ok[0:0] end - attribute \src "issuer_ls180.v:179426.3-179427.47" - process $proc$issuer_ls180.v:179426$13064 + attribute \src "libresoc.v:46816.13-46816.30" + process $proc$libresoc.v:46816$1953 assign { } { } - assign $0\data_r3__nia_ok[0:0] \data_r3__nia_ok$next - sync posedge \coresync_clk - update \data_r3__nia_ok $0\data_r3__nia_ok[0:0] + assign $1\core_reg3[4:0] 5'00000 + sync always + sync init + update \core_reg3 $1\core_reg3[4:0] end - attribute \src "issuer_ls180.v:179428.3-179429.45" - process $proc$issuer_ls180.v:179428$13065 + attribute \src "libresoc.v:46820.7-46820.26" + process $proc$libresoc.v:46820$1954 assign { } { } - assign $0\data_r2__fast2[63:0] \data_r2__fast2$next - sync posedge \coresync_clk - update \data_r2__fast2 $0\data_r2__fast2[63:0] + assign $1\core_reg3_ok[0:0] 1'0 + sync always + sync init + update \core_reg3_ok $1\core_reg3_ok[0:0] end - attribute \src "issuer_ls180.v:179430.3-179431.51" - process $proc$issuer_ls180.v:179430$13066 + attribute \src "libresoc.v:46824.13-46824.30" + process $proc$libresoc.v:46824$1955 assign { } { } - assign $0\data_r2__fast2_ok[0:0] \data_r2__fast2_ok$next - sync posedge \coresync_clk - update \data_r2__fast2_ok $0\data_r2__fast2_ok[0:0] + assign $1\core_rego[4:0] 5'00000 + sync always + sync init + update \core_rego $1\core_rego[4:0] end - attribute \src "issuer_ls180.v:179432.3-179433.45" - process $proc$issuer_ls180.v:179432$13067 + attribute \src "libresoc.v:46828.7-46828.26" + process $proc$libresoc.v:46828$1956 assign { } { } - assign $0\data_r1__fast1[63:0] \data_r1__fast1$next - sync posedge \coresync_clk - update \data_r1__fast1 $0\data_r1__fast1[63:0] + assign $1\core_rego_ok[0:0] 1'0 + sync always + sync init + update \core_rego_ok $1\core_rego_ok[0:0] end - attribute \src "issuer_ls180.v:179434.3-179435.51" - process $proc$issuer_ls180.v:179434$13068 + attribute \src "libresoc.v:46945.13-46945.32" + process $proc$libresoc.v:46945$1957 assign { } { } - assign $0\data_r1__fast1_ok[0:0] \data_r1__fast1_ok$next - sync posedge \coresync_clk - update \data_r1__fast1_ok $0\data_r1__fast1_ok[0:0] + assign $1\core_spr1[9:0] 10'0000000000 + sync always + sync init + update \core_spr1 $1\core_spr1[9:0] end - attribute \src "issuer_ls180.v:179436.3-179437.37" - process $proc$issuer_ls180.v:179436$13069 + attribute \src "libresoc.v:46949.7-46949.26" + process $proc$libresoc.v:46949$1958 assign { } { } - assign $0\data_r0__o[63:0] \data_r0__o$next - sync posedge \coresync_clk - update \data_r0__o $0\data_r0__o[63:0] + assign $1\core_spr1_ok[0:0] 1'0 + sync always + sync init + update \core_spr1_ok $1\core_spr1_ok[0:0] end - attribute \src "issuer_ls180.v:179438.3-179439.43" - process $proc$issuer_ls180.v:179438$13070 + attribute \src "libresoc.v:47064.13-47064.32" + process $proc$libresoc.v:47064$1959 assign { } { } - assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next - sync posedge \coresync_clk - update \data_r0__o_ok $0\data_r0__o_ok[0:0] + assign $1\core_spro[9:0] 10'0000000000 + sync always + sync init + update \core_spro $1\core_spro[9:0] end - attribute \src "issuer_ls180.v:179440.3-179441.73" - process $proc$issuer_ls180.v:179440$13071 + attribute \src "libresoc.v:47068.7-47068.26" + process $proc$libresoc.v:47068$1960 assign { } { } - assign $0\alu_trap0_trap_op__insn_type[6:0] \alu_trap0_trap_op__insn_type$next - sync posedge \coresync_clk - update \alu_trap0_trap_op__insn_type $0\alu_trap0_trap_op__insn_type[6:0] + assign $1\core_spro_ok[0:0] 1'0 + sync always + sync init + update \core_spro_ok $1\core_spro_ok[0:0] end - attribute \src "issuer_ls180.v:179442.3-179443.69" - process $proc$issuer_ls180.v:179442$13072 + attribute \src "libresoc.v:47076.13-47076.31" + process $proc$libresoc.v:47076$1961 assign { } { } - assign $0\alu_trap0_trap_op__fn_unit[11:0] \alu_trap0_trap_op__fn_unit$next - sync posedge \coresync_clk - update \alu_trap0_trap_op__fn_unit $0\alu_trap0_trap_op__fn_unit[11:0] + assign $1\core_xer_in[2:0] 3'000 + sync always + sync init + update \core_xer_in $1\core_xer_in[2:0] end - attribute \src "issuer_ls180.v:179444.3-179445.63" - process $proc$issuer_ls180.v:179444$13073 + attribute \src "libresoc.v:47080.7-47080.26" + process $proc$libresoc.v:47080$1962 assign { } { } - assign $0\alu_trap0_trap_op__insn[31:0] \alu_trap0_trap_op__insn$next - sync posedge \coresync_clk - update \alu_trap0_trap_op__insn $0\alu_trap0_trap_op__insn[31:0] + assign $1\core_xer_out[0:0] 1'0 + sync always + sync init + update \core_xer_out $1\core_xer_out[0:0] end - attribute \src "issuer_ls180.v:179446.3-179447.61" - process $proc$issuer_ls180.v:179446$13074 + attribute \src "libresoc.v:47096.7-47096.30" + process $proc$libresoc.v:47096$1963 assign { } { } - assign $0\alu_trap0_trap_op__msr[63:0] \alu_trap0_trap_op__msr$next - sync posedge \coresync_clk - update \alu_trap0_trap_op__msr $0\alu_trap0_trap_op__msr[63:0] + assign $1\cu_st__rel_o_dly[0:0] 1'0 + sync always + sync init + update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0] end - attribute \src "issuer_ls180.v:179448.3-179449.61" - process $proc$issuer_ls180.v:179448$13075 + attribute \src "libresoc.v:47102.7-47102.24" + process $proc$libresoc.v:47102$1964 assign { } { } - assign $0\alu_trap0_trap_op__cia[63:0] \alu_trap0_trap_op__cia$next - sync posedge \coresync_clk - update \alu_trap0_trap_op__cia $0\alu_trap0_trap_op__cia[63:0] + assign $1\d_cr_delay[0:0] 1'0 + sync always + sync init + update \d_cr_delay $1\d_cr_delay[0:0] end - attribute \src "issuer_ls180.v:179450.3-179451.71" - process $proc$issuer_ls180.v:179450$13076 + attribute \src "libresoc.v:47106.7-47106.25" + process $proc$libresoc.v:47106$1965 assign { } { } - assign $0\alu_trap0_trap_op__is_32bit[0:0] \alu_trap0_trap_op__is_32bit$next - sync posedge \coresync_clk - update \alu_trap0_trap_op__is_32bit $0\alu_trap0_trap_op__is_32bit[0:0] + assign $1\d_reg_delay[0:0] 1'0 + sync always + sync init + update \d_reg_delay $1\d_reg_delay[0:0] end - attribute \src "issuer_ls180.v:179452.3-179453.71" - process $proc$issuer_ls180.v:179452$13077 + attribute \src "libresoc.v:47110.7-47110.25" + process $proc$libresoc.v:47110$1966 assign { } { } - assign $0\alu_trap0_trap_op__traptype[6:0] \alu_trap0_trap_op__traptype$next - sync posedge \coresync_clk - update \alu_trap0_trap_op__traptype $0\alu_trap0_trap_op__traptype[6:0] + assign $1\d_xer_delay[0:0] 1'0 + sync always + sync init + update \d_xer_delay $1\d_xer_delay[0:0] end - attribute \src "issuer_ls180.v:179454.3-179455.71" - process $proc$issuer_ls180.v:179454$13078 + attribute \src "libresoc.v:47148.13-47148.34" + process $proc$libresoc.v:47148$1967 assign { } { } - assign $0\alu_trap0_trap_op__trapaddr[12:0] \alu_trap0_trap_op__trapaddr$next - sync posedge \coresync_clk - update \alu_trap0_trap_op__trapaddr $0\alu_trap0_trap_op__trapaddr[12:0] + assign $1\dbg_dmi_addr_i[3:0] 4'0000 + sync always + sync init + update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0] end - attribute \src "issuer_ls180.v:179456.3-179457.39" - process $proc$issuer_ls180.v:179456$13079 + attribute \src "libresoc.v:47152.14-47152.48" + process $proc$libresoc.v:47152$1968 assign { } { } - assign $0\req_l_r_req[4:0] \req_l_r_req$next - sync posedge \coresync_clk - update \req_l_r_req $0\req_l_r_req[4:0] + assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dbg_dmi_din $1\dbg_dmi_din[63:0] end - attribute \src "issuer_ls180.v:179458.3-179459.39" - process $proc$issuer_ls180.v:179458$13080 + attribute \src "libresoc.v:47158.7-47158.27" + process $proc$libresoc.v:47158$1969 assign { } { } - assign $0\req_l_s_req[4:0] \req_l_s_req$next - sync posedge \coresync_clk - update \req_l_s_req $0\req_l_s_req[4:0] + assign $1\dbg_dmi_req_i[0:0] 1'0 + sync always + sync init + update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0] end - attribute \src "issuer_ls180.v:179460.3-179461.39" - process $proc$issuer_ls180.v:179460$13081 + attribute \src "libresoc.v:47162.7-47162.26" + process $proc$libresoc.v:47162$1970 assign { } { } - assign $0\src_l_r_src[3:0] \src_l_r_src$next - sync posedge \coresync_clk - update \src_l_r_src $0\src_l_r_src[3:0] + assign $1\dbg_dmi_we_i[0:0] 1'0 + sync always + sync init + update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0] end - attribute \src "issuer_ls180.v:179462.3-179463.39" - process $proc$issuer_ls180.v:179462$13082 + attribute \src "libresoc.v:47220.14-47220.49" + process $proc$libresoc.v:47220$1971 assign { } { } - assign $0\src_l_s_src[3:0] \src_l_s_src$next - sync posedge \coresync_clk - update \src_l_s_src $0\src_l_s_src[3:0] + assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dec2_cur_dec $1\dec2_cur_dec[63:0] end - attribute \src "issuer_ls180.v:179464.3-179465.39" - process $proc$issuer_ls180.v:179464$13083 + attribute \src "libresoc.v:47224.7-47224.27" + process $proc$libresoc.v:47224$1972 assign { } { } - assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next - sync posedge \coresync_clk - update \opc_l_r_opc $0\opc_l_r_opc[0:0] + assign $1\dec2_cur_eint[0:0] 1'0 + sync always + sync init + update \dec2_cur_eint $1\dec2_cur_eint[0:0] end - attribute \src "issuer_ls180.v:179466.3-179467.39" - process $proc$issuer_ls180.v:179466$13084 + attribute \src "libresoc.v:47228.14-47228.49" + process $proc$libresoc.v:47228$1973 assign { } { } - assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next - sync posedge \coresync_clk - update \opc_l_s_opc $0\opc_l_s_opc[0:0] + assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dec2_cur_msr $1\dec2_cur_msr[63:0] end - attribute \src "issuer_ls180.v:179468.3-179469.39" - process $proc$issuer_ls180.v:179468$13085 + attribute \src "libresoc.v:47232.14-47232.48" + process $proc$libresoc.v:47232$1974 assign { } { } - assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next - sync posedge \coresync_clk - update \rst_l_r_rst $0\rst_l_r_rst[0:0] + assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dec2_cur_pc $1\dec2_cur_pc[63:0] end - attribute \src "issuer_ls180.v:179470.3-179471.39" - process $proc$issuer_ls180.v:179470$13086 + attribute \src "libresoc.v:47625.13-47625.25" + process $proc$libresoc.v:47625$1975 assign { } { } - assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next - sync posedge \coresync_clk - update \rst_l_s_rst $0\rst_l_s_rst[0:0] + assign $1\delay[1:0] 2'11 + sync always + sync init + update \delay $1\delay[1:0] end - attribute \src "issuer_ls180.v:179472.3-179473.41" - process $proc$issuer_ls180.v:179472$13087 + attribute \src "libresoc.v:47635.13-47635.29" + process $proc$libresoc.v:47635$1976 assign { } { } - assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next - sync posedge \coresync_clk - update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + assign $1\fsm_state[1:0] 2'00 + sync always + sync init + update \fsm_state $1\fsm_state[1:0] end - attribute \src "issuer_ls180.v:179474.3-179475.41" - process $proc$issuer_ls180.v:179474$13088 + attribute \src "libresoc.v:47637.13-47637.35" + process $proc$libresoc.v:47637$1977 assign { } { } - assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next - sync posedge \coresync_clk - update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + assign $0\fsm_state$115[1:0]$1978 2'00 + sync always + sync init + update \fsm_state$115 $0\fsm_state$115[1:0]$1978 end - attribute \src "issuer_ls180.v:179476.3-179477.37" - process $proc$issuer_ls180.v:179476$13089 + attribute \src "libresoc.v:47909.14-47909.28" + process $proc$libresoc.v:47909$1979 assign { } { } - assign $0\prev_wr_go[4:0] \prev_wr_go$next - sync posedge \coresync_clk - update \prev_wr_go $0\prev_wr_go[4:0] + assign $1\ilatch[31:0] 0 + sync always + sync init + update \ilatch $1\ilatch[31:0] end - attribute \src "issuer_ls180.v:179478.3-179479.41" - process $proc$issuer_ls180.v:179478$13090 + attribute \src "libresoc.v:47941.7-47941.29" + process $proc$libresoc.v:47941$1980 assign { } { } - assign $0\alu_done_dly[0:0] \alu_trap0_n_valid_o - sync posedge \coresync_clk - update \alu_done_dly $0\alu_done_dly[0:0] + assign $1\jtag_dmi0_ack_o[0:0] 1'0 + sync always + sync init + update \jtag_dmi0_ack_o $1\jtag_dmi0_ack_o[0:0] end - attribute \src "issuer_ls180.v:179480.3-179481.25" - process $proc$issuer_ls180.v:179480$13091 + attribute \src "libresoc.v:47949.14-47949.51" + process $proc$libresoc.v:47949$1981 assign { } { } - assign $0\all_rd_dly[0:0] \$11 - sync posedge \coresync_clk - update \all_rd_dly $0\all_rd_dly[0:0] + assign $1\jtag_dmi0_dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_dmi0_dout $1\jtag_dmi0_dout[63:0] end - attribute \src "issuer_ls180.v:179560.3-179569.6" - process $proc$issuer_ls180.v:179560$13092 + attribute \src "libresoc.v:47981.7-47981.22" + process $proc$libresoc.v:47981$1982 assign { } { } + assign $1\msr_read[0:0] 1'1 + sync always + sync init + update \msr_read $1\msr_read[0:0] + end + attribute \src "libresoc.v:47993.7-47993.24" + process $proc$libresoc.v:47993$1983 assign { } { } - assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "issuer_ls180.v:179561.5-179561.29" - switch \initial - attribute \src "issuer_ls180.v:179561.9-179561.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch \$55 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_done[0:0] 1'1 - case - assign $1\req_done[0:0] \$47 - end + assign $1\pc_changed[0:0] 1'0 sync always - update \req_done $0\req_done[0:0] + sync init + update \pc_changed $1\pc_changed[0:0] end - attribute \src "issuer_ls180.v:179570.3-179578.6" - process $proc$issuer_ls180.v:179570$13093 + attribute \src "libresoc.v:48003.7-48003.25" + process $proc$libresoc.v:48003$1984 assign { } { } + assign $1\pc_ok_delay[0:0] 1'0 + sync always + sync init + update \pc_ok_delay $1\pc_ok_delay[0:0] + end + attribute \src "libresoc.v:48009.14-48009.32" + process $proc$libresoc.v:48009$1985 assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$13094 $1\rok_l_s_rdok$next[0:0]$13095 - attribute \src "issuer_ls180.v:179571.5-179571.29" - switch \initial - attribute \src "issuer_ls180.v:179571.9-179571.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$13095 1'0 - case - assign $1\rok_l_s_rdok$next[0:0]$13095 \cu_issue_i - end + assign $1\raw_insn_i[31:0] 0 sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$13094 + sync init + update \raw_insn_i $1\raw_insn_i[31:0] end - attribute \src "issuer_ls180.v:179579.3-179587.6" - process $proc$issuer_ls180.v:179579$13096 + attribute \src "libresoc.v:48092.3-48093.41" + process $proc$libresoc.v:48092$1461 assign { } { } + assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next + sync posedge \clk + update \dec2_cur_dec $0\dec2_cur_dec[63:0] + end + attribute \src "libresoc.v:48094.3-48095.33" + process $proc$libresoc.v:48094$1462 assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$13097 $1\rok_l_r_rdok$next[0:0]$13098 - attribute \src "issuer_ls180.v:179580.5-179580.29" - switch \initial - attribute \src "issuer_ls180.v:179580.9-179580.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$13098 1'1 - case - assign $1\rok_l_r_rdok$next[0:0]$13098 \$65 - end - sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$13097 + assign $0\core_dec[63:0] \core_dec$next + sync posedge \clk + update \core_dec $0\core_dec[63:0] end - attribute \src "issuer_ls180.v:179588.3-179596.6" - process $proc$issuer_ls180.v:179588$13099 + attribute \src "libresoc.v:48096.3-48097.41" + process $proc$libresoc.v:48096$1463 assign { } { } + assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next + sync posedge \clk + update \dec2_cur_msr $0\dec2_cur_msr[63:0] + end + attribute \src "libresoc.v:48098.3-48099.35" + process $proc$libresoc.v:48098$1464 assign { } { } - assign $0\rst_l_s_rst$next[0:0]$13100 $1\rst_l_s_rst$next[0:0]$13101 - attribute \src "issuer_ls180.v:179589.5-179589.29" - switch \initial - attribute \src "issuer_ls180.v:179589.9-179589.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_s_rst$next[0:0]$13101 1'0 - case - assign $1\rst_l_s_rst$next[0:0]$13101 \all_rd - end - sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$13100 + assign $0\fsm_state[1:0] \fsm_state$next + sync posedge \clk + update \fsm_state $0\fsm_state[1:0] end - attribute \src "issuer_ls180.v:179597.3-179605.6" - process $proc$issuer_ls180.v:179597$13102 + attribute \src "libresoc.v:48100.3-48101.33" + process $proc$libresoc.v:48100$1465 assign { } { } + assign $0\msr_read[0:0] \msr_read$next + sync posedge \clk + update \msr_read $0\msr_read[0:0] + end + attribute \src "libresoc.v:48102.3-48103.39" + process $proc$libresoc.v:48102$1466 assign { } { } - assign $0\rst_l_r_rst$next[0:0]$13103 $1\rst_l_r_rst$next[0:0]$13104 - attribute \src "issuer_ls180.v:179598.5-179598.29" - switch \initial - attribute \src "issuer_ls180.v:179598.9-179598.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_r_rst$next[0:0]$13104 1'1 - case - assign $1\rst_l_r_rst$next[0:0]$13104 \rst_r - end - sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$13103 + assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next + sync posedge \clk + update \dec2_cur_pc $0\dec2_cur_pc[63:0] end - attribute \src "issuer_ls180.v:179606.3-179614.6" - process $proc$issuer_ls180.v:179606$13105 + attribute \src "libresoc.v:48104.3-48105.39" + process $proc$libresoc.v:48104$1467 assign { } { } + assign $0\bigendian_i[0:0] \bigendian_i$next + sync posedge \clk + update \bigendian_i $0\bigendian_i[0:0] + end + attribute \src "libresoc.v:48106.3-48107.37" + process $proc$libresoc.v:48106$1468 assign { } { } - assign $0\opc_l_s_opc$next[0:0]$13106 $1\opc_l_s_opc$next[0:0]$13107 - attribute \src "issuer_ls180.v:179607.5-179607.29" - switch \initial - attribute \src "issuer_ls180.v:179607.9-179607.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_s_opc$next[0:0]$13107 1'0 - case - assign $1\opc_l_s_opc$next[0:0]$13107 \cu_issue_i - end - sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$13106 + assign $0\raw_insn_i[31:0] \raw_insn_i$next + sync posedge \clk + update \raw_insn_i $0\raw_insn_i[31:0] end - attribute \src "issuer_ls180.v:179615.3-179623.6" - process $proc$issuer_ls180.v:179615$13108 + attribute \src "libresoc.v:48108.3-48109.41" + process $proc$libresoc.v:48108$1469 assign { } { } + assign $0\core_asmcode[7:0] \core_asmcode$next + sync posedge \clk + update \core_asmcode $0\core_asmcode[7:0] + end + attribute \src "libresoc.v:48110.3-48111.35" + process $proc$libresoc.v:48110$1470 assign { } { } - assign $0\opc_l_r_opc$next[0:0]$13109 $1\opc_l_r_opc$next[0:0]$13110 - attribute \src "issuer_ls180.v:179616.5-179616.29" - switch \initial - attribute \src "issuer_ls180.v:179616.9-179616.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_r_opc$next[0:0]$13110 1'1 - case - assign $1\opc_l_r_opc$next[0:0]$13110 \req_done - end - sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$13109 + assign $0\core_rego[4:0] \core_rego$next + sync posedge \clk + update \core_rego $0\core_rego[4:0] end - attribute \src "issuer_ls180.v:179624.3-179632.6" - process $proc$issuer_ls180.v:179624$13111 + attribute \src "libresoc.v:48112.3-48113.41" + process $proc$libresoc.v:48112$1471 assign { } { } + assign $0\core_rego_ok[0:0] \core_rego_ok$next + sync posedge \clk + update \core_rego_ok $0\core_rego_ok[0:0] + end + attribute \src "libresoc.v:48114.3-48115.45" + process $proc$libresoc.v:48114$1472 assign { } { } - assign $0\src_l_s_src$next[3:0]$13112 $1\src_l_s_src$next[3:0]$13113 - attribute \src "issuer_ls180.v:179625.5-179625.29" - switch \initial - attribute \src "issuer_ls180.v:179625.9-179625.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_s_src$next[3:0]$13113 4'0000 - case - assign $1\src_l_s_src$next[3:0]$13113 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } - end - sync always - update \src_l_s_src$next $0\src_l_s_src$next[3:0]$13112 + assign $0\fsm_state$115[1:0]$1473 \fsm_state$115$next + sync posedge \clk + update \fsm_state$115 $0\fsm_state$115[1:0]$1473 end - attribute \src "issuer_ls180.v:179633.3-179641.6" - process $proc$issuer_ls180.v:179633$13114 + attribute \src "libresoc.v:48116.3-48117.31" + process $proc$libresoc.v:48116$1474 assign { } { } + assign $0\core_ea[4:0] \core_ea$next + sync posedge \clk + update \core_ea $0\core_ea[4:0] + end + attribute \src "libresoc.v:48118.3-48119.37" + process $proc$libresoc.v:48118$1475 assign { } { } - assign $0\src_l_r_src$next[3:0]$13115 $1\src_l_r_src$next[3:0]$13116 - attribute \src "issuer_ls180.v:179634.5-179634.29" - switch \initial - attribute \src "issuer_ls180.v:179634.9-179634.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_r_src$next[3:0]$13116 4'1111 - case - assign $1\src_l_r_src$next[3:0]$13116 \reset_r - end - sync always - update \src_l_r_src$next $0\src_l_r_src$next[3:0]$13115 + assign $0\core_ea_ok[0:0] \core_ea_ok$next + sync posedge \clk + update \core_ea_ok $0\core_ea_ok[0:0] end - attribute \src "issuer_ls180.v:179642.3-179650.6" - process $proc$issuer_ls180.v:179642$13117 + attribute \src "libresoc.v:48120.3-48121.35" + process $proc$libresoc.v:48120$1476 assign { } { } + assign $0\core_reg1[4:0] \core_reg1$next + sync posedge \clk + update \core_reg1 $0\core_reg1[4:0] + end + attribute \src "libresoc.v:48122.3-48123.41" + process $proc$libresoc.v:48122$1477 assign { } { } - assign $0\req_l_s_req$next[4:0]$13118 $1\req_l_s_req$next[4:0]$13119 - attribute \src "issuer_ls180.v:179643.5-179643.29" - switch \initial - attribute \src "issuer_ls180.v:179643.9-179643.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_s_req$next[4:0]$13119 5'00000 - case - assign $1\req_l_s_req$next[4:0]$13119 \$67 - end - sync always - update \req_l_s_req$next $0\req_l_s_req$next[4:0]$13118 + assign $0\core_reg1_ok[0:0] \core_reg1_ok$next + sync posedge \clk + update \core_reg1_ok $0\core_reg1_ok[0:0] end - attribute \src "issuer_ls180.v:179651.3-179659.6" - process $proc$issuer_ls180.v:179651$13120 + attribute \src "libresoc.v:48124.3-48125.35" + process $proc$libresoc.v:48124$1478 assign { } { } + assign $0\core_reg2[4:0] \core_reg2$next + sync posedge \clk + update \core_reg2 $0\core_reg2[4:0] + end + attribute \src "libresoc.v:48126.3-48127.41" + process $proc$libresoc.v:48126$1479 assign { } { } - assign $0\req_l_r_req$next[4:0]$13121 $1\req_l_r_req$next[4:0]$13122 - attribute \src "issuer_ls180.v:179652.5-179652.29" - switch \initial - attribute \src "issuer_ls180.v:179652.9-179652.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_r_req$next[4:0]$13122 5'11111 - case - assign $1\req_l_r_req$next[4:0]$13122 \$69 - end - sync always - update \req_l_r_req$next $0\req_l_r_req$next[4:0]$13121 + assign $0\core_reg2_ok[0:0] \core_reg2_ok$next + sync posedge \clk + update \core_reg2_ok $0\core_reg2_ok[0:0] end - attribute \src "issuer_ls180.v:179660.3-179676.6" - process $proc$issuer_ls180.v:179660$13123 + attribute \src "libresoc.v:48128.3-48129.35" + process $proc$libresoc.v:48128$1480 assign { } { } + assign $0\core_reg3[4:0] \core_reg3$next + sync posedge \clk + update \core_reg3 $0\core_reg3[4:0] + end + attribute \src "libresoc.v:48130.3-48131.41" + process $proc$libresoc.v:48130$1481 assign { } { } + assign $0\core_reg3_ok[0:0] \core_reg3_ok$next + sync posedge \clk + update \core_reg3_ok $0\core_reg3_ok[0:0] + end + attribute \src "libresoc.v:48132.3-48133.35" + process $proc$libresoc.v:48132$1482 assign { } { } + assign $0\core_spro[9:0] \core_spro$next + sync posedge \clk + update \core_spro $0\core_spro[9:0] + end + attribute \src "libresoc.v:48134.3-48135.41" + process $proc$libresoc.v:48134$1483 assign { } { } + assign $0\core_spro_ok[0:0] \core_spro_ok$next + sync posedge \clk + update \core_spro_ok $0\core_spro_ok[0:0] + end + attribute \src "libresoc.v:48136.3-48137.39" + process $proc$libresoc.v:48136$1484 assign { } { } + assign $0\d_xer_delay[0:0] \d_xer_delay$next + sync posedge \clk + update \d_xer_delay $0\d_xer_delay[0:0] + end + attribute \src "libresoc.v:48138.3-48139.35" + process $proc$libresoc.v:48138$1485 assign { } { } + assign $0\core_spr1[9:0] \core_spr1$next + sync posedge \clk + update \core_spr1 $0\core_spr1[9:0] + end + attribute \src "libresoc.v:48140.3-48141.41" + process $proc$libresoc.v:48140$1486 assign { } { } + assign $0\core_spr1_ok[0:0] \core_spr1_ok$next + sync posedge \clk + update \core_spr1_ok $0\core_spr1_ok[0:0] + end + attribute \src "libresoc.v:48142.3-48143.39" + process $proc$libresoc.v:48142$1487 assign { } { } + assign $0\core_xer_in[2:0] \core_xer_in$next + sync posedge \clk + update \core_xer_in $0\core_xer_in[2:0] + end + attribute \src "libresoc.v:48144.3-48145.41" + process $proc$libresoc.v:48144$1488 assign { } { } + assign $0\core_xer_out[0:0] \core_xer_out$next + sync posedge \clk + update \core_xer_out $0\core_xer_out[0:0] + end + attribute \src "libresoc.v:48146.3-48147.37" + process $proc$libresoc.v:48146$1489 assign { } { } + assign $0\core_fast1[2:0] \core_fast1$next + sync posedge \clk + update \core_fast1 $0\core_fast1[2:0] + end + attribute \src "libresoc.v:48148.3-48149.43" + process $proc$libresoc.v:48148$1490 assign { } { } + assign $0\core_fast1_ok[0:0] \core_fast1_ok$next + sync posedge \clk + update \core_fast1_ok $0\core_fast1_ok[0:0] + end + attribute \src "libresoc.v:48150.3-48151.37" + process $proc$libresoc.v:48150$1491 assign { } { } + assign $0\core_fast2[2:0] \core_fast2$next + sync posedge \clk + update \core_fast2 $0\core_fast2[2:0] + end + attribute \src "libresoc.v:48152.3-48153.43" + process $proc$libresoc.v:48152$1492 assign { } { } + assign $0\core_fast2_ok[0:0] \core_fast2_ok$next + sync posedge \clk + update \core_fast2_ok $0\core_fast2_ok[0:0] + end + attribute \src "libresoc.v:48154.3-48155.39" + process $proc$libresoc.v:48154$1493 assign { } { } + assign $0\core_fasto1[2:0] \core_fasto1$next + sync posedge \clk + update \core_fasto1 $0\core_fasto1[2:0] + end + attribute \src "libresoc.v:48156.3-48157.45" + process $proc$libresoc.v:48156$1494 assign { } { } + assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next + sync posedge \clk + update \core_fasto1_ok $0\core_fasto1_ok[0:0] + end + attribute \src "libresoc.v:48158.3-48159.37" + process $proc$libresoc.v:48158$1495 assign { } { } - assign $0\alu_trap0_trap_op__cia$next[63:0]$13124 $1\alu_trap0_trap_op__cia$next[63:0]$13132 - assign $0\alu_trap0_trap_op__fn_unit$next[11:0]$13125 $1\alu_trap0_trap_op__fn_unit$next[11:0]$13133 - assign $0\alu_trap0_trap_op__insn$next[31:0]$13126 $1\alu_trap0_trap_op__insn$next[31:0]$13134 - assign $0\alu_trap0_trap_op__insn_type$next[6:0]$13127 $1\alu_trap0_trap_op__insn_type$next[6:0]$13135 - assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$13128 $1\alu_trap0_trap_op__is_32bit$next[0:0]$13136 - assign $0\alu_trap0_trap_op__msr$next[63:0]$13129 $1\alu_trap0_trap_op__msr$next[63:0]$13137 - assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$13130 $1\alu_trap0_trap_op__trapaddr$next[12:0]$13138 - assign $0\alu_trap0_trap_op__traptype$next[6:0]$13131 $1\alu_trap0_trap_op__traptype$next[6:0]$13139 - attribute \src "issuer_ls180.v:179661.5-179661.29" - switch \initial - attribute \src "issuer_ls180.v:179661.9-179661.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_trap0_trap_op__trapaddr$next[12:0]$13138 $1\alu_trap0_trap_op__traptype$next[6:0]$13139 $1\alu_trap0_trap_op__is_32bit$next[0:0]$13136 $1\alu_trap0_trap_op__cia$next[63:0]$13132 $1\alu_trap0_trap_op__msr$next[63:0]$13137 $1\alu_trap0_trap_op__insn$next[31:0]$13134 $1\alu_trap0_trap_op__fn_unit$next[11:0]$13133 $1\alu_trap0_trap_op__insn_type$next[6:0]$13135 } { \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } - case - assign $1\alu_trap0_trap_op__cia$next[63:0]$13132 \alu_trap0_trap_op__cia - assign $1\alu_trap0_trap_op__fn_unit$next[11:0]$13133 \alu_trap0_trap_op__fn_unit - assign $1\alu_trap0_trap_op__insn$next[31:0]$13134 \alu_trap0_trap_op__insn - assign $1\alu_trap0_trap_op__insn_type$next[6:0]$13135 \alu_trap0_trap_op__insn_type - assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$13136 \alu_trap0_trap_op__is_32bit - assign $1\alu_trap0_trap_op__msr$next[63:0]$13137 \alu_trap0_trap_op__msr - assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$13138 \alu_trap0_trap_op__trapaddr - assign $1\alu_trap0_trap_op__traptype$next[6:0]$13139 \alu_trap0_trap_op__traptype - end - sync always - update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$13124 - update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[11:0]$13125 - update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$13126 - update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$13127 - update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$13128 - update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$13129 - update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$13130 - update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[6:0]$13131 + assign $0\d_cr_delay[0:0] \d_cr_delay$next + sync posedge \clk + update \d_cr_delay $0\d_cr_delay[0:0] end - attribute \src "issuer_ls180.v:179677.3-179698.6" - process $proc$issuer_ls180.v:179677$13140 + attribute \src "libresoc.v:48160.3-48161.39" + process $proc$libresoc.v:48160$1496 assign { } { } + assign $0\core_fasto2[2:0] \core_fasto2$next + sync posedge \clk + update \core_fasto2 $0\core_fasto2[2:0] + end + attribute \src "libresoc.v:48162.3-48163.45" + process $proc$libresoc.v:48162$1497 assign { } { } + assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next + sync posedge \clk + update \core_fasto2_ok $0\core_fasto2_ok[0:0] + end + attribute \src "libresoc.v:48164.3-48165.39" + process $proc$libresoc.v:48164$1498 assign { } { } + assign $0\core_cr_in1[2:0] \core_cr_in1$next + sync posedge \clk + update \core_cr_in1 $0\core_cr_in1[2:0] + end + attribute \src "libresoc.v:48166.3-48167.45" + process $proc$libresoc.v:48166$1499 assign { } { } + assign $0\core_cr_in1_ok[0:0] \core_cr_in1_ok$next + sync posedge \clk + update \core_cr_in1_ok $0\core_cr_in1_ok[0:0] + end + attribute \src "libresoc.v:48168.3-48169.39" + process $proc$libresoc.v:48168$1500 assign { } { } + assign $0\core_cr_in2[2:0] \core_cr_in2$next + sync posedge \clk + update \core_cr_in2 $0\core_cr_in2[2:0] + end + attribute \src "libresoc.v:48170.3-48171.45" + process $proc$libresoc.v:48170$1501 assign { } { } - assign $0\data_r0__o$next[63:0]$13141 $2\data_r0__o$next[63:0]$13145 + assign $0\core_cr_in2_ok[0:0] \core_cr_in2_ok$next + sync posedge \clk + update \core_cr_in2_ok $0\core_cr_in2_ok[0:0] + end + attribute \src "libresoc.v:48172.3-48173.47" + process $proc$libresoc.v:48172$1502 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$13142 $3\data_r0__o_ok$next[0:0]$13147 - attribute \src "issuer_ls180.v:179678.5-179678.29" - switch \initial - attribute \src "issuer_ls180.v:179678.9-179678.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$13144 $1\data_r0__o$next[63:0]$13143 } { \o_ok \alu_trap0_o } - case - assign $1\data_r0__o$next[63:0]$13143 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$13144 \data_r0__o_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$13146 $2\data_r0__o$next[63:0]$13145 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r0__o$next[63:0]$13145 $1\data_r0__o$next[63:0]$13143 - assign $2\data_r0__o_ok$next[0:0]$13146 $1\data_r0__o_ok$next[0:0]$13144 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r0__o_ok$next[0:0]$13147 1'0 - case - assign $3\data_r0__o_ok$next[0:0]$13147 $2\data_r0__o_ok$next[0:0]$13146 - end - sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$13141 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$13142 + assign $0\core_cr_in2$39[2:0]$1503 \core_cr_in2$39$next + sync posedge \clk + update \core_cr_in2$39 $0\core_cr_in2$39[2:0]$1503 end - attribute \src "issuer_ls180.v:179699.3-179720.6" - process $proc$issuer_ls180.v:179699$13148 + attribute \src "libresoc.v:48174.3-48175.53" + process $proc$libresoc.v:48174$1504 assign { } { } + assign $0\core_cr_in2_ok$40[0:0]$1505 \core_cr_in2_ok$40$next + sync posedge \clk + update \core_cr_in2_ok$40 $0\core_cr_in2_ok$40[0:0]$1505 + end + attribute \src "libresoc.v:48176.3-48177.39" + process $proc$libresoc.v:48176$1506 assign { } { } + assign $0\core_cr_out[2:0] \core_cr_out$next + sync posedge \clk + update \core_cr_out $0\core_cr_out[2:0] + end + attribute \src "libresoc.v:48178.3-48179.45" + process $proc$libresoc.v:48178$1507 assign { } { } + assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next + sync posedge \clk + update \core_cr_out_ok $0\core_cr_out_ok[0:0] + end + attribute \src "libresoc.v:48180.3-48181.39" + process $proc$libresoc.v:48180$1508 assign { } { } + assign $0\d_reg_delay[0:0] \d_reg_delay$next + sync posedge \clk + update \d_reg_delay $0\d_reg_delay[0:0] + end + attribute \src "libresoc.v:48182.3-48183.43" + process $proc$libresoc.v:48182$1509 assign { } { } + assign $0\core_core_msr[63:0] \core_core_msr$next + sync posedge \clk + update \core_core_msr $0\core_core_msr[63:0] + end + attribute \src "libresoc.v:48184.3-48185.43" + process $proc$libresoc.v:48184$1510 assign { } { } - assign $0\data_r1__fast1$next[63:0]$13149 $2\data_r1__fast1$next[63:0]$13153 + assign $0\core_core_cia[63:0] \core_core_cia$next + sync posedge \clk + update \core_core_cia $0\core_core_cia[63:0] + end + attribute \src "libresoc.v:48186.3-48187.45" + process $proc$libresoc.v:48186$1511 assign { } { } - assign $0\data_r1__fast1_ok$next[0:0]$13150 $3\data_r1__fast1_ok$next[0:0]$13155 - attribute \src "issuer_ls180.v:179700.5-179700.29" - switch \initial - attribute \src "issuer_ls180.v:179700.9-179700.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r1__fast1_ok$next[0:0]$13152 $1\data_r1__fast1$next[63:0]$13151 } { \fast1_ok \alu_trap0_fast1 } - case - assign $1\data_r1__fast1$next[63:0]$13151 \data_r1__fast1 - assign $1\data_r1__fast1_ok$next[0:0]$13152 \data_r1__fast1_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r1__fast1_ok$next[0:0]$13154 $2\data_r1__fast1$next[63:0]$13153 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r1__fast1$next[63:0]$13153 $1\data_r1__fast1$next[63:0]$13151 - assign $2\data_r1__fast1_ok$next[0:0]$13154 $1\data_r1__fast1_ok$next[0:0]$13152 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r1__fast1_ok$next[0:0]$13155 1'0 - case - assign $3\data_r1__fast1_ok$next[0:0]$13155 $2\data_r1__fast1_ok$next[0:0]$13154 - end - sync always - update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$13149 - update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$13150 + assign $0\core_core_insn[31:0] \core_core_insn$next + sync posedge \clk + update \core_core_insn $0\core_core_insn[31:0] end - attribute \src "issuer_ls180.v:179721.3-179742.6" - process $proc$issuer_ls180.v:179721$13156 + attribute \src "libresoc.v:48188.3-48189.55" + process $proc$libresoc.v:48188$1512 assign { } { } + assign $0\core_core_insn_type[6:0] \core_core_insn_type$next + sync posedge \clk + update \core_core_insn_type $0\core_core_insn_type[6:0] + end + attribute \src "libresoc.v:48190.3-48191.51" + process $proc$libresoc.v:48190$1513 assign { } { } + assign $0\core_core_fn_unit[11:0] \core_core_fn_unit$next + sync posedge \clk + update \core_core_fn_unit $0\core_core_fn_unit[11:0] + end + attribute \src "libresoc.v:48192.3-48193.41" + process $proc$libresoc.v:48192$1514 assign { } { } + assign $0\core_core_lk[0:0] \core_core_lk$next + sync posedge \clk + update \core_core_lk $0\core_core_lk[0:0] + end + attribute \src "libresoc.v:48194.3-48195.41" + process $proc$libresoc.v:48194$1515 assign { } { } + assign $0\core_core_rc[0:0] \core_core_rc$next + sync posedge \clk + update \core_core_rc $0\core_core_rc[0:0] + end + attribute \src "libresoc.v:48196.3-48197.47" + process $proc$libresoc.v:48196$1516 assign { } { } + assign $0\core_core_rc_ok[0:0] \core_core_rc_ok$next + sync posedge \clk + update \core_core_rc_ok $0\core_core_rc_ok[0:0] + end + attribute \src "libresoc.v:48198.3-48199.41" + process $proc$libresoc.v:48198$1517 assign { } { } - assign $0\data_r2__fast2$next[63:0]$13157 $2\data_r2__fast2$next[63:0]$13161 + assign $0\core_core_oe[0:0] \core_core_oe$next + sync posedge \clk + update \core_core_oe $0\core_core_oe[0:0] + end + attribute \src "libresoc.v:48200.3-48201.47" + process $proc$libresoc.v:48200$1518 assign { } { } - assign $0\data_r2__fast2_ok$next[0:0]$13158 $3\data_r2__fast2_ok$next[0:0]$13163 - attribute \src "issuer_ls180.v:179722.5-179722.29" - switch \initial - attribute \src "issuer_ls180.v:179722.9-179722.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r2__fast2_ok$next[0:0]$13160 $1\data_r2__fast2$next[63:0]$13159 } { \fast2_ok \alu_trap0_fast2 } - case - assign $1\data_r2__fast2$next[63:0]$13159 \data_r2__fast2 - assign $1\data_r2__fast2_ok$next[0:0]$13160 \data_r2__fast2_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r2__fast2_ok$next[0:0]$13162 $2\data_r2__fast2$next[63:0]$13161 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r2__fast2$next[63:0]$13161 $1\data_r2__fast2$next[63:0]$13159 - assign $2\data_r2__fast2_ok$next[0:0]$13162 $1\data_r2__fast2_ok$next[0:0]$13160 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r2__fast2_ok$next[0:0]$13163 1'0 - case - assign $3\data_r2__fast2_ok$next[0:0]$13163 $2\data_r2__fast2_ok$next[0:0]$13162 - end - sync always - update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$13157 - update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$13158 + assign $0\core_core_oe_ok[0:0] \core_core_oe_ok$next + sync posedge \clk + update \core_core_oe_ok $0\core_core_oe_ok[0:0] + end + attribute \src "libresoc.v:48202.3-48203.29" + process $proc$libresoc.v:48202$1519 + assign { } { } + assign $0\ilatch[31:0] \ilatch$next + sync posedge \clk + update \ilatch $0\ilatch[31:0] + end + attribute \src "libresoc.v:48204.3-48205.59" + process $proc$libresoc.v:48204$1520 + assign { } { } + assign $0\core_core_input_carry[1:0] \core_core_input_carry$next + sync posedge \clk + update \core_core_input_carry $0\core_core_input_carry[1:0] + end + attribute \src "libresoc.v:48206.3-48207.53" + process $proc$libresoc.v:48206$1521 + assign { } { } + assign $0\core_core_traptype[6:0] \core_core_traptype$next + sync posedge \clk + update \core_core_traptype $0\core_core_traptype[6:0] + end + attribute \src "libresoc.v:48208.3-48209.53" + process $proc$libresoc.v:48208$1522 + assign { } { } + assign $0\core_core_trapaddr[12:0] \core_core_trapaddr$next + sync posedge \clk + update \core_core_trapaddr $0\core_core_trapaddr[12:0] + end + attribute \src "libresoc.v:48210.3-48211.47" + process $proc$libresoc.v:48210$1523 + assign { } { } + assign $0\core_core_cr_rd[7:0] \core_core_cr_rd$next + sync posedge \clk + update \core_core_cr_rd $0\core_core_cr_rd[7:0] + end + attribute \src "libresoc.v:48212.3-48213.53" + process $proc$libresoc.v:48212$1524 + assign { } { } + assign $0\core_core_cr_rd_ok[0:0] \core_core_cr_rd_ok$next + sync posedge \clk + update \core_core_cr_rd_ok $0\core_core_cr_rd_ok[0:0] end - attribute \src "issuer_ls180.v:179743.3-179764.6" - process $proc$issuer_ls180.v:179743$13164 + attribute \src "libresoc.v:48214.3-48215.47" + process $proc$libresoc.v:48214$1525 assign { } { } + assign $0\core_core_cr_wr[7:0] \core_core_cr_wr$next + sync posedge \clk + update \core_core_cr_wr $0\core_core_cr_wr[7:0] + end + attribute \src "libresoc.v:48216.3-48217.53" + process $proc$libresoc.v:48216$1526 + assign { } { } + assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next + sync posedge \clk + update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0] + end + attribute \src "libresoc.v:48218.3-48219.53" + process $proc$libresoc.v:48218$1527 + assign { } { } + assign $0\core_core_is_32bit[0:0] \core_core_is_32bit$next + sync posedge \clk + update \core_core_is_32bit $0\core_core_is_32bit[0:0] + end + attribute \src "libresoc.v:48220.3-48221.37" + process $proc$libresoc.v:48220$1528 + assign { } { } + assign $0\pc_changed[0:0] \pc_changed$next + sync posedge \clk + update \pc_changed $0\pc_changed[0:0] + end + attribute \src "libresoc.v:48222.3-48223.39" + process $proc$libresoc.v:48222$1529 + assign { } { } + assign $0\pc_ok_delay[0:0] \pc_ok_delay$next + sync posedge \clk + update \pc_ok_delay $0\pc_ok_delay[0:0] + end + attribute \src "libresoc.v:48224.3-48225.31" + process $proc$libresoc.v:48224$1530 + assign { } { } + assign $0\core_pc[63:0] \core_pc$next + sync posedge \clk + update \core_pc $0\core_pc[63:0] + end + attribute \src "libresoc.v:48226.3-48227.30" + process $proc$libresoc.v:48226$1531 + assign { } { } + assign $0\cu_st__rel_o_dly[0:0] 1'0 + sync posedge \clk + update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] + end + attribute \src "libresoc.v:48228.3-48229.27" + process $proc$libresoc.v:48228$1532 + assign { } { } + assign $0\delay[1:0] \delay$next + sync posedge \por_clk + update \delay $0\delay[1:0] + end + attribute \src "libresoc.v:48230.3-48231.43" + process $proc$libresoc.v:48230$1533 assign { } { } + assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next + sync posedge \clk + update \dec2_cur_eint $0\dec2_cur_eint[0:0] + end + attribute \src "libresoc.v:48232.3-48233.45" + process $proc$libresoc.v:48232$1534 + assign { } { } + assign $0\jtag_dmi0_dout[63:0] \jtag_dmi0_dout$next + sync posedge \clk + update \jtag_dmi0_dout $0\jtag_dmi0_dout[63:0] + end + attribute \src "libresoc.v:48234.3-48235.47" + process $proc$libresoc.v:48234$1535 + assign { } { } + assign $0\jtag_dmi0_ack_o[0:0] \jtag_dmi0_ack_o$next + sync posedge \clk + update \jtag_dmi0_ack_o $0\jtag_dmi0_ack_o[0:0] + end + attribute \src "libresoc.v:48236.3-48237.39" + process $proc$libresoc.v:48236$1536 + assign { } { } + assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next + sync posedge \clk + update \dbg_dmi_din $0\dbg_dmi_din[63:0] + end + attribute \src "libresoc.v:48238.3-48239.41" + process $proc$libresoc.v:48238$1537 + assign { } { } + assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next + sync posedge \clk + update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0] + end + attribute \src "libresoc.v:48240.3-48241.43" + process $proc$libresoc.v:48240$1538 assign { } { } + assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next + sync posedge \clk + update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0] + end + attribute \src "libresoc.v:48242.3-48243.45" + process $proc$libresoc.v:48242$1539 + assign { } { } + assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next + sync posedge \clk + update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0] + end + attribute \src "libresoc.v:48244.3-48245.33" + process $proc$libresoc.v:48244$1540 assign { } { } + assign $0\core_msr[63:0] \core_msr$next + sync posedge \clk + update \core_msr $0\core_msr[63:0] + end + attribute \src "libresoc.v:48246.3-48247.35" + process $proc$libresoc.v:48246$1541 assign { } { } + assign $0\core_eint[0:0] \core_eint$next + sync posedge \clk + update \core_eint $0\core_eint[0:0] + end + attribute \src "libresoc.v:48500.3-48508.6" + process $proc$libresoc.v:48500$1542 assign { } { } - assign $0\data_r3__nia$next[63:0]$13165 $2\data_r3__nia$next[63:0]$13169 assign { } { } - assign $0\data_r3__nia_ok$next[0:0]$13166 $3\data_r3__nia_ok$next[0:0]$13171 - attribute \src "issuer_ls180.v:179744.5-179744.29" + assign $0\dbg_dmi_addr_i$next[3:0]$1543 $1\dbg_dmi_addr_i$next[3:0]$1544 + attribute \src "libresoc.v:48501.5-48501.29" switch \initial - attribute \src "issuer_ls180.v:179744.9-179744.17" + attribute \src "libresoc.v:48501.9-48501.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign { $1\data_r3__nia_ok$next[0:0]$13168 $1\data_r3__nia$next[63:0]$13167 } { \nia_ok \alu_trap0_nia } + assign $1\dbg_dmi_addr_i$next[3:0]$1544 4'0000 case - assign $1\data_r3__nia$next[63:0]$13167 \data_r3__nia - assign $1\data_r3__nia_ok$next[0:0]$13168 \data_r3__nia_ok + assign $1\dbg_dmi_addr_i$next[3:0]$1544 \jtag_dmi0_addr_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" + sync always + update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$1543 + end + attribute \src "libresoc.v:48509.3-48517.6" + process $proc$libresoc.v:48509$1545 + assign { } { } + assign { } { } + assign $0\dbg_dmi_req_i$next[0:0]$1546 $1\dbg_dmi_req_i$next[0:0]$1547 + attribute \src "libresoc.v:48510.5-48510.29" + switch \initial + attribute \src "libresoc.v:48510.9-48510.17" case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r3__nia_ok$next[0:0]$13170 $2\data_r3__nia$next[63:0]$13169 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r3__nia$next[63:0]$13169 $1\data_r3__nia$next[63:0]$13167 - assign $2\data_r3__nia_ok$next[0:0]$13170 $1\data_r3__nia_ok$next[0:0]$13168 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__nia_ok$next[0:0]$13171 1'0 + assign $1\dbg_dmi_req_i$next[0:0]$1547 1'0 case - assign $3\data_r3__nia_ok$next[0:0]$13171 $2\data_r3__nia_ok$next[0:0]$13170 + assign $1\dbg_dmi_req_i$next[0:0]$1547 \jtag_dmi0_req_i end sync always - update \data_r3__nia$next $0\data_r3__nia$next[63:0]$13165 - update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$13166 + update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$1546 end - attribute \src "issuer_ls180.v:179765.3-179786.6" - process $proc$issuer_ls180.v:179765$13172 + attribute \src "libresoc.v:48518.3-48528.6" + process $proc$libresoc.v:48518$1548 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r4__msr$next[63:0]$13173 $2\data_r4__msr$next[63:0]$13177 - assign { } { } - assign $0\data_r4__msr_ok$next[0:0]$13174 $3\data_r4__msr_ok$next[0:0]$13179 - attribute \src "issuer_ls180.v:179766.5-179766.29" + assign $0\issue_i[0:0] $1\issue_i[0:0] + attribute \src "libresoc.v:48519.5-48519.29" switch \initial - attribute \src "issuer_ls180.v:179766.9-179766.17" + attribute \src "libresoc.v:48519.9-48519.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'10 assign { } { } - assign { $1\data_r4__msr_ok$next[0:0]$13176 $1\data_r4__msr$next[63:0]$13175 } { \msr_ok \alu_trap0_msr } + assign $1\issue_i[0:0] 1'1 case - assign $1\data_r4__msr$next[63:0]$13175 \data_r4__msr - assign $1\data_r4__msr_ok$next[0:0]$13176 \data_r4__msr_ok + assign $1\issue_i[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "issuer_ls180.v:0.0-0.0" + sync always + update \issue_i $0\issue_i[0:0] + end + attribute \src "libresoc.v:48529.3-48538.6" + process $proc$libresoc.v:48529$1549 + assign { } { } + assign { } { } + assign $0\dmi__addr[4:0] $1\dmi__addr[4:0] + attribute \src "libresoc.v:48530.5-48530.29" + switch \initial + attribute \src "libresoc.v:48530.9-48530.17" case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r4__msr_ok$next[0:0]$13178 $2\data_r4__msr$next[63:0]$13177 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r4__msr$next[63:0]$13177 $1\data_r4__msr$next[63:0]$13175 - assign $2\data_r4__msr_ok$next[0:0]$13178 $1\data_r4__msr_ok$next[0:0]$13176 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" + switch \dbg_d_gpr_req + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r4__msr_ok$next[0:0]$13179 1'0 + assign $1\dmi__addr[4:0] \dbg_d_gpr_addr [4:0] case - assign $3\data_r4__msr_ok$next[0:0]$13179 $2\data_r4__msr_ok$next[0:0]$13178 + assign $1\dmi__addr[4:0] 5'00000 end sync always - update \data_r4__msr$next $0\data_r4__msr$next[63:0]$13173 - update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$13174 + update \dmi__addr $0\dmi__addr[4:0] end - attribute \src "issuer_ls180.v:179787.3-179796.6" - process $proc$issuer_ls180.v:179787$13180 + attribute \src "libresoc.v:48539.3-48548.6" + process $proc$libresoc.v:48539$1550 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$13181 $1\src_r0$next[63:0]$13182 - attribute \src "issuer_ls180.v:179788.5-179788.29" + assign $0\dmi__ren[0:0] $1\dmi__ren[0:0] + attribute \src "libresoc.v:48540.5-48540.29" switch \initial - attribute \src "issuer_ls180.v:179788.9-179788.17" + attribute \src "libresoc.v:48540.9-48540.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [0] - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" + switch \dbg_d_gpr_req + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$13182 \src1_i + assign $1\dmi__ren[0:0] 1'1 case - assign $1\src_r0$next[63:0]$13182 \src_r0 + assign $1\dmi__ren[0:0] 1'0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$13181 + update \dmi__ren $0\dmi__ren[0:0] end - attribute \src "issuer_ls180.v:179797.3-179806.6" - process $proc$issuer_ls180.v:179797$13183 + attribute \src "libresoc.v:48549.3-48557.6" + process $proc$libresoc.v:48549$1551 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$13184 $1\src_r1$next[63:0]$13185 - attribute \src "issuer_ls180.v:179798.5-179798.29" + assign $0\d_reg_delay$next[0:0]$1552 $1\d_reg_delay$next[0:0]$1553 + attribute \src "libresoc.v:48550.5-48550.29" switch \initial - attribute \src "issuer_ls180.v:179798.9-179798.17" + attribute \src "libresoc.v:48550.9-48550.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [1] - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$13185 \src2_i + assign $1\d_reg_delay$next[0:0]$1553 1'0 case - assign $1\src_r1$next[63:0]$13185 \src_r1 + assign $1\d_reg_delay$next[0:0]$1553 \dbg_d_gpr_req end sync always - update \src_r1$next $0\src_r1$next[63:0]$13184 + update \d_reg_delay$next $0\d_reg_delay$next[0:0]$1552 end - attribute \src "issuer_ls180.v:179807.3-179816.6" - process $proc$issuer_ls180.v:179807$13186 + attribute \src "libresoc.v:48558.3-48567.6" + process $proc$libresoc.v:48558$1554 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$13187 $1\src_r2$next[63:0]$13188 - attribute \src "issuer_ls180.v:179808.5-179808.29" + assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:48559.5-48559.29" switch \initial - attribute \src "issuer_ls180.v:179808.9-179808.17" + attribute \src "libresoc.v:48559.9-48559.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [2] - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + switch \d_reg_delay + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$13188 \src3_i + assign $1\dbg_d_gpr_data[63:0] \dmi__data_o case - assign $1\src_r2$next[63:0]$13188 \src_r2 + assign $1\dbg_d_gpr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \src_r2$next $0\src_r2$next[63:0]$13187 + update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] end - attribute \src "issuer_ls180.v:179817.3-179826.6" - process $proc$issuer_ls180.v:179817$13189 + attribute \src "libresoc.v:48568.3-48577.6" + process $proc$libresoc.v:48568$1555 assign { } { } assign { } { } - assign $0\src_r3$next[63:0]$13190 $1\src_r3$next[63:0]$13191 - attribute \src "issuer_ls180.v:179818.5-179818.29" + assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:48569.5-48569.29" switch \initial - attribute \src "issuer_ls180.v:179818.9-179818.17" + attribute \src "libresoc.v:48569.9-48569.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [3] - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + switch \d_reg_delay + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[63:0]$13191 \src4_i + assign $1\dbg_d_gpr_ack[0:0] 1'1 case - assign $1\src_r3$next[63:0]$13191 \src_r3 + assign $1\dbg_d_gpr_ack[0:0] 1'0 end sync always - update \src_r3$next $0\src_r3$next[63:0]$13190 + update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] end - attribute \src "issuer_ls180.v:179827.3-179835.6" - process $proc$issuer_ls180.v:179827$13192 + attribute \src "libresoc.v:48578.3-48587.6" + process $proc$libresoc.v:48578$1556 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$13193 $1\alui_l_r_alui$next[0:0]$13194 - attribute \src "issuer_ls180.v:179828.5-179828.29" + assign $0\full_rd2__ren[7:0] $1\full_rd2__ren[7:0] + attribute \src "libresoc.v:48579.5-48579.29" switch \initial - attribute \src "issuer_ls180.v:179828.9-179828.17" + attribute \src "libresoc.v:48579.9-48579.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" + switch \dbg_d_cr_req + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$13194 1'1 + assign $1\full_rd2__ren[7:0] 8'11111111 case - assign $1\alui_l_r_alui$next[0:0]$13194 \$89 + assign $1\full_rd2__ren[7:0] 8'00000000 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$13193 + update \full_rd2__ren $0\full_rd2__ren[7:0] end - attribute \src "issuer_ls180.v:179836.3-179844.6" - process $proc$issuer_ls180.v:179836$13195 + attribute \src "libresoc.v:48588.3-48596.6" + process $proc$libresoc.v:48588$1557 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$13196 $1\alu_l_r_alu$next[0:0]$13197 - attribute \src "issuer_ls180.v:179837.5-179837.29" + assign $0\d_cr_delay$next[0:0]$1558 $1\d_cr_delay$next[0:0]$1559 + attribute \src "libresoc.v:48589.5-48589.29" switch \initial - attribute \src "issuer_ls180.v:179837.9-179837.17" + attribute \src "libresoc.v:48589.9-48589.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$13197 1'1 + assign $1\d_cr_delay$next[0:0]$1559 1'0 case - assign $1\alu_l_r_alu$next[0:0]$13197 \$91 + assign $1\d_cr_delay$next[0:0]$1559 \dbg_d_cr_req end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$13196 + update \d_cr_delay$next $0\d_cr_delay$next[0:0]$1558 end - attribute \src "issuer_ls180.v:179845.3-179854.6" - process $proc$issuer_ls180.v:179845$13198 + attribute \src "libresoc.v:48597.3-48606.6" + process $proc$libresoc.v:48597$1560 assign { } { } assign { } { } - assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "issuer_ls180.v:179846.5-179846.29" + assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:48598.5-48598.29" switch \initial - attribute \src "issuer_ls180.v:179846.9-179846.17" + attribute \src "libresoc.v:48598.9-48598.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$115 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" + switch \d_cr_delay + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dest1_o[63:0] \data_r0__o + assign $1\dbg_d_cr_data[63:0] \$111 case - assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dbg_d_cr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \dest1_o $0\dest1_o[63:0] + update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] end - attribute \src "issuer_ls180.v:179855.3-179864.6" - process $proc$issuer_ls180.v:179855$13199 + attribute \src "libresoc.v:48607.3-48616.6" + process $proc$libresoc.v:48607$1561 assign { } { } assign { } { } - assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "issuer_ls180.v:179856.5-179856.29" + assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:48608.5-48608.29" switch \initial - attribute \src "issuer_ls180.v:179856.9-179856.17" + attribute \src "libresoc.v:48608.9-48608.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$117 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" + switch \d_cr_delay + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dest2_o[63:0] \data_r1__fast1 + assign $1\dbg_d_cr_ack[0:0] 1'1 case - assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dbg_d_cr_ack[0:0] 1'0 end sync always - update \dest2_o $0\dest2_o[63:0] + update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] end - attribute \src "issuer_ls180.v:179865.3-179874.6" - process $proc$issuer_ls180.v:179865$13200 + attribute \src "libresoc.v:48617.3-48626.6" + process $proc$libresoc.v:48617$1562 assign { } { } assign { } { } - assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "issuer_ls180.v:179866.5-179866.29" + assign $0\full_rd__ren[2:0] $1\full_rd__ren[2:0] + attribute \src "libresoc.v:48618.5-48618.29" switch \initial - attribute \src "issuer_ls180.v:179866.9-179866.17" + attribute \src "libresoc.v:48618.9-48618.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$119 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:331" + switch \dbg_d_xer_req + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dest3_o[63:0] \data_r2__fast2 + assign $1\full_rd__ren[2:0] 3'111 case - assign $1\dest3_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\full_rd__ren[2:0] 3'000 end sync always - update \dest3_o $0\dest3_o[63:0] + update \full_rd__ren $0\full_rd__ren[2:0] end - attribute \src "issuer_ls180.v:179875.3-179884.6" - process $proc$issuer_ls180.v:179875$13201 + attribute \src "libresoc.v:48627.3-48635.6" + process $proc$libresoc.v:48627$1563 assign { } { } assign { } { } - assign $0\dest4_o[63:0] $1\dest4_o[63:0] - attribute \src "issuer_ls180.v:179876.5-179876.29" + assign $0\d_xer_delay$next[0:0]$1564 $1\d_xer_delay$next[0:0]$1565 + attribute \src "libresoc.v:48628.5-48628.29" switch \initial - attribute \src "issuer_ls180.v:179876.9-179876.17" + attribute \src "libresoc.v:48628.9-48628.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$121 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dest4_o[63:0] \data_r3__nia + assign $1\d_xer_delay$next[0:0]$1565 1'0 case - assign $1\dest4_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\d_xer_delay$next[0:0]$1565 \dbg_d_xer_req end sync always - update \dest4_o $0\dest4_o[63:0] + update \d_xer_delay$next $0\d_xer_delay$next[0:0]$1564 end - attribute \src "issuer_ls180.v:179885.3-179894.6" - process $proc$issuer_ls180.v:179885$13202 + attribute \src "libresoc.v:48636.3-48645.6" + process $proc$libresoc.v:48636$1566 assign { } { } assign { } { } - assign $0\dest5_o[63:0] $1\dest5_o[63:0] - attribute \src "issuer_ls180.v:179886.5-179886.29" + assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:48637.5-48637.29" switch \initial - attribute \src "issuer_ls180.v:179886.9-179886.17" + attribute \src "libresoc.v:48637.9-48637.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$123 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335" + switch \d_xer_delay + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dest5_o[63:0] \data_r4__msr + assign $1\dbg_d_xer_data[63:0] \$113 case - assign $1\dest5_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dbg_d_xer_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \dest5_o $0\dest5_o[63:0] + update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] end - attribute \src "issuer_ls180.v:179895.3-179903.6" - process $proc$issuer_ls180.v:179895$13203 + attribute \src "libresoc.v:48646.3-48655.6" + process $proc$libresoc.v:48646$1567 assign { } { } assign { } { } - assign $0\prev_wr_go$next[4:0]$13204 $1\prev_wr_go$next[4:0]$13205 - attribute \src "issuer_ls180.v:179896.5-179896.29" + assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:48647.5-48647.29" switch \initial - attribute \src "issuer_ls180.v:179896.9-179896.17" + attribute \src "libresoc.v:48647.9-48647.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\prev_wr_go$next[4:0]$13205 5'00000 - case - assign $1\prev_wr_go$next[4:0]$13205 \$21 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[4:0]$13204 - end - connect \$5 $reduce_and$issuer_ls180.v:179347$12994_Y - connect \$99 $and$issuer_ls180.v:179348$12995_Y - connect \$101 $and$issuer_ls180.v:179349$12996_Y - connect \$103 $and$issuer_ls180.v:179350$12997_Y - connect \$105 $and$issuer_ls180.v:179351$12998_Y - connect \$107 $and$issuer_ls180.v:179352$12999_Y - connect \$109 $and$issuer_ls180.v:179353$13000_Y - connect \$111 $and$issuer_ls180.v:179354$13001_Y - connect \$113 $and$issuer_ls180.v:179355$13002_Y - connect \$115 $and$issuer_ls180.v:179356$13003_Y - connect \$117 $and$issuer_ls180.v:179357$13004_Y - connect \$11 $and$issuer_ls180.v:179358$13005_Y - connect \$119 $and$issuer_ls180.v:179359$13006_Y - connect \$121 $and$issuer_ls180.v:179360$13007_Y - connect \$123 $and$issuer_ls180.v:179361$13008_Y - connect \$13 $not$issuer_ls180.v:179362$13009_Y - connect \$15 $and$issuer_ls180.v:179363$13010_Y - connect \$17 $not$issuer_ls180.v:179364$13011_Y - connect \$19 $and$issuer_ls180.v:179365$13012_Y - connect \$21 $and$issuer_ls180.v:179366$13013_Y - connect \$25 $not$issuer_ls180.v:179367$13014_Y - connect \$27 $and$issuer_ls180.v:179368$13015_Y - connect \$24 $reduce_or$issuer_ls180.v:179369$13016_Y - connect \$23 $not$issuer_ls180.v:179370$13017_Y - connect \$31 $and$issuer_ls180.v:179371$13018_Y - connect \$33 $reduce_or$issuer_ls180.v:179372$13019_Y - connect \$35 $reduce_or$issuer_ls180.v:179373$13020_Y - connect \$37 $or$issuer_ls180.v:179374$13021_Y - connect \$3 $and$issuer_ls180.v:179375$13022_Y - connect \$39 $not$issuer_ls180.v:179376$13023_Y - connect \$41 $and$issuer_ls180.v:179377$13024_Y - connect \$43 $and$issuer_ls180.v:179378$13025_Y - connect \$45 $eq$issuer_ls180.v:179379$13026_Y - connect \$47 $and$issuer_ls180.v:179380$13027_Y - connect \$49 $eq$issuer_ls180.v:179381$13028_Y - connect \$51 $and$issuer_ls180.v:179382$13029_Y - connect \$53 $and$issuer_ls180.v:179383$13030_Y - connect \$55 $and$issuer_ls180.v:179384$13031_Y - connect \$57 $or$issuer_ls180.v:179385$13032_Y - connect \$59 $or$issuer_ls180.v:179386$13033_Y - connect \$61 $or$issuer_ls180.v:179387$13034_Y - connect \$63 $or$issuer_ls180.v:179388$13035_Y - connect \$65 $and$issuer_ls180.v:179389$13036_Y - connect \$67 $and$issuer_ls180.v:179390$13037_Y - connect \$6 $not$issuer_ls180.v:179391$13038_Y - connect \$69 $or$issuer_ls180.v:179392$13039_Y - connect \$71 $and$issuer_ls180.v:179393$13040_Y - connect \$73 $and$issuer_ls180.v:179394$13041_Y - connect \$75 $and$issuer_ls180.v:179395$13042_Y - connect \$77 $and$issuer_ls180.v:179396$13043_Y - connect \$79 $and$issuer_ls180.v:179397$13044_Y - connect \$81 $ternary$issuer_ls180.v:179398$13045_Y - connect \$83 $ternary$issuer_ls180.v:179399$13046_Y - connect \$85 $ternary$issuer_ls180.v:179400$13047_Y - connect \$87 $ternary$issuer_ls180.v:179401$13048_Y - connect \$8 $or$issuer_ls180.v:179402$13049_Y - connect \$89 $and$issuer_ls180.v:179403$13050_Y - connect \$91 $and$issuer_ls180.v:179404$13051_Y - connect \$93 $and$issuer_ls180.v:179405$13052_Y - connect \$95 $and$issuer_ls180.v:179406$13053_Y - connect \$97 $not$issuer_ls180.v:179407$13054_Y - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 - connect \cu_wr__rel_o \$113 - connect \cu_rd__rel_o \$99 - connect \cu_busy_o \opc_l_q_opc - connect \alu_l_s_alu \all_rd_pulse - connect \alu_trap0_n_ready_i \alu_l_q_alu - connect \alui_l_s_alui \all_rd_pulse - connect \alu_trap0_p_valid_i \alui_l_q_alui - connect \alu_trap0_fast2$2 \$87 - connect \alu_trap0_fast1$1 \$85 - connect \alu_trap0_rb \$83 - connect \alu_trap0_ra \$81 - connect \cu_wrmask_o { \$79 \$77 \$75 \$73 \$71 } - connect \reset_r \$63 - connect \reset_w \$61 - connect \rst_r \$59 - connect \reset \$57 - connect \wr_any \$37 - connect \cu_done_o \$31 - connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } - connect \alu_pulse \alu_done_rise - connect \alu_done_rise \$19 - connect \alu_done_dly$next \alu_done - connect \alu_done \alu_trap0_n_valid_o - connect \all_rd_pulse \all_rd_rise - connect \all_rd_rise \$15 - connect \all_rd_dly$next \all_rd - connect \all_rd \$11 -end -attribute \src "issuer_ls180.v:179937.1-179995.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.upd_l" -attribute \generator "nMigen" -module \upd_l - attribute \src "issuer_ls180.v:179938.7-179938.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:179983.3-179991.6" - wire $0\q_int$next[0:0]$13254 - attribute \src "issuer_ls180.v:179981.3-179982.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:179983.3-179991.6" - wire $1\q_int$next[0:0]$13255 - attribute \src "issuer_ls180.v:179960.7-179960.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:179973.17-179973.96" - wire $and$issuer_ls180.v:179973$13244_Y - attribute \src "issuer_ls180.v:179978.17-179978.96" - wire $and$issuer_ls180.v:179978$13249_Y - attribute \src "issuer_ls180.v:179975.18-179975.93" - wire $not$issuer_ls180.v:179975$13246_Y - attribute \src "issuer_ls180.v:179977.17-179977.92" - wire $not$issuer_ls180.v:179977$13248_Y - attribute \src "issuer_ls180.v:179980.17-179980.92" - wire $not$issuer_ls180.v:179980$13251_Y - attribute \src "issuer_ls180.v:179974.18-179974.98" - wire $or$issuer_ls180.v:179974$13245_Y - attribute \src "issuer_ls180.v:179976.18-179976.99" - wire $or$issuer_ls180.v:179976$13247_Y - attribute \src "issuer_ls180.v:179979.17-179979.97" - wire $or$issuer_ls180.v:179979$13250_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:179938.7-179938.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:179973$13244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:179973$13244_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:179978$13249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:179978$13249_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:179975$13246 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_upd - connect \Y $not$issuer_ls180.v:179975$13246_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:179977$13248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_upd - connect \Y $not$issuer_ls180.v:179977$13248_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:179980$13251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_upd - connect \Y $not$issuer_ls180.v:179980$13251_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:179974$13245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_upd - connect \Y $or$issuer_ls180.v:179974$13245_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:179976$13247 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_upd - connect \B \q_int - connect \Y $or$issuer_ls180.v:179976$13247_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:179979$13250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_upd - connect \Y $or$issuer_ls180.v:179979$13250_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335" + switch \d_xer_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_xer_ack[0:0] 1'1 + case + assign $1\dbg_d_xer_ack[0:0] 1'0 + end + sync always + update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] end - attribute \src "issuer_ls180.v:179938.7-179938.20" - process $proc$issuer_ls180.v:179938$13256 + attribute \src "libresoc.v:48656.3-48670.6" + process $proc$libresoc.v:48656$1568 assign { } { } - assign $0\initial[0:0] 1'0 + assign { } { } + assign $0\issue__addr[2:0] $1\issue__addr[2:0] + attribute \src "libresoc.v:48657.5-48657.29" + switch \initial + attribute \src "libresoc.v:48657.9-48657.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" + switch \fsm_state$115 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\issue__addr[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\issue__addr[2:0] 3'111 + case + assign $1\issue__addr[2:0] 3'000 + end sync always - update \initial $0\initial[0:0] - sync init + update \issue__addr $0\issue__addr[2:0] end - attribute \src "issuer_ls180.v:179960.7-179960.19" - process $proc$issuer_ls180.v:179960$13257 + attribute \src "libresoc.v:48671.3-48685.6" + process $proc$libresoc.v:48671$1569 assign { } { } - assign $1\q_int[0:0] 1'0 + assign { } { } + assign $0\issue__ren[0:0] $1\issue__ren[0:0] + attribute \src "libresoc.v:48672.5-48672.29" + switch \initial + attribute \src "libresoc.v:48672.9-48672.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" + switch \fsm_state$115 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\issue__ren[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\issue__ren[0:0] 1'1 + case + assign $1\issue__ren[0:0] 1'0 + end sync always - sync init - update \q_int $1\q_int[0:0] + update \issue__ren $0\issue__ren[0:0] end - attribute \src "issuer_ls180.v:179981.3-179982.27" - process $proc$issuer_ls180.v:179981$13252 + attribute \src "libresoc.v:48686.3-48713.6" + process $proc$libresoc.v:48686$1570 assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:179983.3-179991.6" - process $proc$issuer_ls180.v:179983$13253 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13254 $1\q_int$next[0:0]$13255 - attribute \src "issuer_ls180.v:179984.5-179984.29" + assign $0\fsm_state$115$next[1:0]$1571 $2\fsm_state$115$next[1:0]$1573 + attribute \src "libresoc.v:48687.5-48687.29" switch \initial - attribute \src "issuer_ls180.v:179984.9-179984.17" + attribute \src "libresoc.v:48687.9-48687.17" case 1'1 case end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" + switch \fsm_state$115 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fsm_state$115$next[1:0]$1572 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fsm_state$115$next[1:0]$1572 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fsm_state$115$next[1:0]$1572 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\fsm_state$115$next[1:0]$1572 2'00 + case + assign $1\fsm_state$115$next[1:0]$1572 \fsm_state$115 + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13255 1'0 + assign $2\fsm_state$115$next[1:0]$1573 2'00 case - assign $1\q_int$next[0:0]$13255 \$5 + assign $2\fsm_state$115$next[1:0]$1573 $1\fsm_state$115$next[1:0]$1572 end sync always - update \q_int$next $0\q_int$next[0:0]$13254 - end - connect \$9 $and$issuer_ls180.v:179973$13244_Y - connect \$11 $or$issuer_ls180.v:179974$13245_Y - connect \$13 $not$issuer_ls180.v:179975$13246_Y - connect \$15 $or$issuer_ls180.v:179976$13247_Y - connect \$1 $not$issuer_ls180.v:179977$13248_Y - connect \$3 $and$issuer_ls180.v:179978$13249_Y - connect \$5 $or$issuer_ls180.v:179979$13250_Y - connect \$7 $not$issuer_ls180.v:179980$13251_Y - connect \qlq_upd \$15 - connect \qn_upd \$13 - connect \q_upd \$11 -end -attribute \src "issuer_ls180.v:179999.1-180057.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.valid_l" -attribute \generator "nMigen" -module \valid_l - attribute \src "issuer_ls180.v:180000.7-180000.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:180045.3-180053.6" - wire $0\q_int$next[0:0]$13268 - attribute \src "issuer_ls180.v:180043.3-180044.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:180045.3-180053.6" - wire $1\q_int$next[0:0]$13269 - attribute \src "issuer_ls180.v:180022.7-180022.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:180035.17-180035.96" - wire $and$issuer_ls180.v:180035$13258_Y - attribute \src "issuer_ls180.v:180040.17-180040.96" - wire $and$issuer_ls180.v:180040$13263_Y - attribute \src "issuer_ls180.v:180037.18-180037.95" - wire $not$issuer_ls180.v:180037$13260_Y - attribute \src "issuer_ls180.v:180039.17-180039.94" - wire $not$issuer_ls180.v:180039$13262_Y - attribute \src "issuer_ls180.v:180042.17-180042.94" - wire $not$issuer_ls180.v:180042$13265_Y - attribute \src "issuer_ls180.v:180036.18-180036.100" - wire $or$issuer_ls180.v:180036$13259_Y - attribute \src "issuer_ls180.v:180038.18-180038.101" - wire $or$issuer_ls180.v:180038$13261_Y - attribute \src "issuer_ls180.v:180041.17-180041.99" - wire $or$issuer_ls180.v:180041$13264_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:180000.7-180000.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 3 \q_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 4 \r_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:180035$13258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:180035$13258_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:180040$13263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:180040$13263_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:180037$13260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_valid - connect \Y $not$issuer_ls180.v:180037$13260_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:180039$13262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_valid - connect \Y $not$issuer_ls180.v:180039$13262_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:180042$13265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_valid - connect \Y $not$issuer_ls180.v:180042$13265_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:180036$13259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_valid - connect \Y $or$issuer_ls180.v:180036$13259_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:180038$13261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_valid - connect \B \q_int - connect \Y $or$issuer_ls180.v:180038$13261_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:180041$13264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_valid - connect \Y $or$issuer_ls180.v:180041$13264_Y + update \fsm_state$115$next $0\fsm_state$115$next[1:0]$1571 end - attribute \src "issuer_ls180.v:180000.7-180000.20" - process $proc$issuer_ls180.v:180000$13270 + attribute \src "libresoc.v:48714.3-48724.6" + process $proc$libresoc.v:48714$1574 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "issuer_ls180.v:180022.7-180022.19" - process $proc$issuer_ls180.v:180022$13271 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $0\new_dec[63:0] $1\new_dec[63:0] + attribute \src "libresoc.v:48715.5-48715.29" + switch \initial + attribute \src "libresoc.v:48715.9-48715.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" + switch \fsm_state$115 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\new_dec[63:0] \$116 [63:0] + case + assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "issuer_ls180.v:180043.3-180044.27" - process $proc$issuer_ls180.v:180043$13266 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \new_dec $0\new_dec[63:0] end - attribute \src "issuer_ls180.v:180045.3-180053.6" - process $proc$issuer_ls180.v:180045$13267 + attribute \src "libresoc.v:48725.3-48739.6" + process $proc$libresoc.v:48725$1575 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13268 $1\q_int$next[0:0]$13269 - attribute \src "issuer_ls180.v:180046.5-180046.29" + assign $0\issue__addr$119[2:0]$1576 $1\issue__addr$119[2:0]$1577 + attribute \src "libresoc.v:48726.5-48726.29" switch \initial - attribute \src "issuer_ls180.v:180046.9-180046.17" + attribute \src "libresoc.v:48726.9-48726.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" + switch \fsm_state$115 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\issue__addr$119[2:0]$1577 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 assign { } { } - assign $1\q_int$next[0:0]$13269 1'0 + assign $1\issue__addr$119[2:0]$1577 3'111 case - assign $1\q_int$next[0:0]$13269 \$5 + assign $1\issue__addr$119[2:0]$1577 3'000 end sync always - update \q_int$next $0\q_int$next[0:0]$13268 - end - connect \$9 $and$issuer_ls180.v:180035$13258_Y - connect \$11 $or$issuer_ls180.v:180036$13259_Y - connect \$13 $not$issuer_ls180.v:180037$13260_Y - connect \$15 $or$issuer_ls180.v:180038$13261_Y - connect \$1 $not$issuer_ls180.v:180039$13262_Y - connect \$3 $and$issuer_ls180.v:180040$13263_Y - connect \$5 $or$issuer_ls180.v:180041$13264_Y - connect \$7 $not$issuer_ls180.v:180042$13265_Y - connect \qlq_valid \$15 - connect \qn_valid \$13 - connect \q_valid \$11 -end -attribute \src "issuer_ls180.v:180061.1-180119.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.wri_l" -attribute \generator "nMigen" -module \wri_l - attribute \src "issuer_ls180.v:180062.7-180062.20" - wire $0\initial[0:0] - attribute \src "issuer_ls180.v:180107.3-180115.6" - wire $0\q_int$next[0:0]$13282 - attribute \src "issuer_ls180.v:180105.3-180106.27" - wire $0\q_int[0:0] - attribute \src "issuer_ls180.v:180107.3-180115.6" - wire $1\q_int$next[0:0]$13283 - attribute \src "issuer_ls180.v:180084.7-180084.19" - wire $1\q_int[0:0] - attribute \src "issuer_ls180.v:180097.17-180097.96" - wire $and$issuer_ls180.v:180097$13272_Y - attribute \src "issuer_ls180.v:180102.17-180102.96" - wire $and$issuer_ls180.v:180102$13277_Y - attribute \src "issuer_ls180.v:180099.18-180099.93" - wire $not$issuer_ls180.v:180099$13274_Y - attribute \src "issuer_ls180.v:180101.17-180101.92" - wire $not$issuer_ls180.v:180101$13276_Y - attribute \src "issuer_ls180.v:180104.17-180104.92" - wire $not$issuer_ls180.v:180104$13279_Y - attribute \src "issuer_ls180.v:180098.18-180098.98" - wire $or$issuer_ls180.v:180098$13273_Y - attribute \src "issuer_ls180.v:180100.18-180100.99" - wire $or$issuer_ls180.v:180100$13275_Y - attribute \src "issuer_ls180.v:180103.17-180103.97" - wire $or$issuer_ls180.v:180103$13278_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" - wire input 1 \coresync_rst - attribute \src "issuer_ls180.v:180062.7-180062.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$issuer_ls180.v:180097$13272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$issuer_ls180.v:180097$13272_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$issuer_ls180.v:180102$13277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$issuer_ls180.v:180102$13277_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$issuer_ls180.v:180099$13274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_wri - connect \Y $not$issuer_ls180.v:180099$13274_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$issuer_ls180.v:180101$13276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_wri - connect \Y $not$issuer_ls180.v:180101$13276_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$issuer_ls180.v:180104$13279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_wri - connect \Y $not$issuer_ls180.v:180104$13279_Y + update \issue__addr$119 $0\issue__addr$119[2:0]$1576 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$issuer_ls180.v:180098$13273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_wri - connect \Y $or$issuer_ls180.v:180098$13273_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$issuer_ls180.v:180100$13275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_wri - connect \B \q_int - connect \Y $or$issuer_ls180.v:180100$13275_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$issuer_ls180.v:180103$13278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_wri - connect \Y $or$issuer_ls180.v:180103$13278_Y - end - attribute \src "issuer_ls180.v:180062.7-180062.20" - process $proc$issuer_ls180.v:180062$13284 + attribute \src "libresoc.v:48740.3-48754.6" + process $proc$libresoc.v:48740$1578 assign { } { } - assign $0\initial[0:0] 1'0 + assign { } { } + assign $0\issue__wen[0:0] $1\issue__wen[0:0] + attribute \src "libresoc.v:48741.5-48741.29" + switch \initial + attribute \src "libresoc.v:48741.9-48741.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" + switch \fsm_state$115 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\issue__wen[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\issue__wen[0:0] 1'1 + case + assign $1\issue__wen[0:0] 1'0 + end sync always - update \initial $0\initial[0:0] - sync init + update \issue__wen $0\issue__wen[0:0] end - attribute \src "issuer_ls180.v:180084.7-180084.19" - process $proc$issuer_ls180.v:180084$13285 + attribute \src "libresoc.v:48755.3-48769.6" + process $proc$libresoc.v:48755$1579 assign { } { } - assign $1\q_int[0:0] 1'0 + assign { } { } + assign $0\issue__data_i[63:0] $1\issue__data_i[63:0] + attribute \src "libresoc.v:48756.5-48756.29" + switch \initial + attribute \src "libresoc.v:48756.9-48756.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" + switch \fsm_state$115 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\issue__data_i[63:0] \new_dec + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\issue__data_i[63:0] \new_tb + case + assign $1\issue__data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end sync always - sync init - update \q_int $1\q_int[0:0] + update \issue__data_i $0\issue__data_i[63:0] end - attribute \src "issuer_ls180.v:180105.3-180106.27" - process $proc$issuer_ls180.v:180105$13280 + attribute \src "libresoc.v:48770.3-48785.6" + process $proc$libresoc.v:48770$1580 assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "issuer_ls180.v:180107.3-180115.6" - process $proc$issuer_ls180.v:180107$13281 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13282 $1\q_int$next[0:0]$13283 - attribute \src "issuer_ls180.v:180108.5-180108.29" + assign $0\dec2_cur_dec$next[63:0]$1581 $2\dec2_cur_dec$next[63:0]$1583 + attribute \src "libresoc.v:48771.5-48771.29" switch \initial - attribute \src "issuer_ls180.v:180108.9-180108.17" + attribute \src "libresoc.v:48771.9-48771.17" case 1'1 case end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" + switch \fsm_state$115 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_cur_dec$next[63:0]$1582 \new_dec + case + assign $1\dec2_cur_dec$next[63:0]$1582 \dec2_cur_dec + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13283 1'0 + assign $2\dec2_cur_dec$next[63:0]$1583 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\q_int$next[0:0]$13283 \$5 + assign $2\dec2_cur_dec$next[63:0]$1583 $1\dec2_cur_dec$next[63:0]$1582 end sync always - update \q_int$next $0\q_int$next[0:0]$13282 - end - connect \$9 $and$issuer_ls180.v:180097$13272_Y - connect \$11 $or$issuer_ls180.v:180098$13273_Y - connect \$13 $not$issuer_ls180.v:180099$13274_Y - connect \$15 $or$issuer_ls180.v:180100$13275_Y - connect \$1 $not$issuer_ls180.v:180101$13276_Y - connect \$3 $and$issuer_ls180.v:180102$13277_Y - connect \$5 $or$issuer_ls180.v:180103$13278_Y - connect \$7 $not$issuer_ls180.v:180104$13279_Y - connect \qlq_wri \$15 - connect \qn_wri \$13 - connect \q_wri \$11 -end -attribute \src "issuer_ls180.v:180123.1-180189.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.wrpick_CR_cr_a" -attribute \generator "nMigen" -module \wrpick_CR_cr_a - attribute \src "issuer_ls180.v:180168.17-180168.91" - wire $not$issuer_ls180.v:180168$13286_Y - attribute \src "issuer_ls180.v:180170.18-180170.93" - wire $not$issuer_ls180.v:180170$13288_Y - attribute \src "issuer_ls180.v:180172.18-180172.93" - wire $not$issuer_ls180.v:180172$13290_Y - attribute \src "issuer_ls180.v:180173.17-180173.89" - wire width 6 $not$issuer_ls180.v:180173$13291_Y - attribute \src "issuer_ls180.v:180175.18-180175.93" - wire $not$issuer_ls180.v:180175$13293_Y - attribute \src "issuer_ls180.v:180178.17-180178.91" - wire $not$issuer_ls180.v:180178$13296_Y - attribute \src "issuer_ls180.v:180169.18-180169.106" - wire $reduce_or$issuer_ls180.v:180169$13287_Y - attribute \src "issuer_ls180.v:180171.18-180171.106" - wire $reduce_or$issuer_ls180.v:180171$13289_Y - attribute \src "issuer_ls180.v:180174.18-180174.106" - wire $reduce_or$issuer_ls180.v:180174$13292_Y - attribute \src "issuer_ls180.v:180176.18-180176.90" - wire $reduce_or$issuer_ls180.v:180176$13294_Y - attribute \src "issuer_ls180.v:180177.17-180177.103" - wire $reduce_or$issuer_ls180.v:180177$13295_Y - attribute \src "issuer_ls180.v:180179.17-180179.105" - wire $reduce_or$issuer_ls180.v:180179$13297_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 6 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 6 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 6 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 6 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:180168$13286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:180168$13286_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:180170$13288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:180170$13288_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:180172$13290 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:180172$13290_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:180173$13291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \i - connect \Y $not$issuer_ls180.v:180173$13291_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:180175$13293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$issuer_ls180.v:180175$13293_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:180178$13296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:180178$13296_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:180169$13287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:180169$13287_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:180171$13289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:180171$13289_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:180174$13292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$issuer_ls180.v:180174$13292_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:180176$13294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:180176$13294_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:180177$13295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:180177$13295_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:180179$13297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:180179$13297_Y - end - connect \$7 $not$issuer_ls180.v:180168$13286_Y - connect \$12 $reduce_or$issuer_ls180.v:180169$13287_Y - connect \$11 $not$issuer_ls180.v:180170$13288_Y - connect \$16 $reduce_or$issuer_ls180.v:180171$13289_Y - connect \$15 $not$issuer_ls180.v:180172$13290_Y - connect \$1 $not$issuer_ls180.v:180173$13291_Y - connect \$20 $reduce_or$issuer_ls180.v:180174$13292_Y - connect \$19 $not$issuer_ls180.v:180175$13293_Y - connect \$23 $reduce_or$issuer_ls180.v:180176$13294_Y - connect \$4 $reduce_or$issuer_ls180.v:180177$13295_Y - connect \$3 $not$issuer_ls180.v:180178$13296_Y - connect \$8 $reduce_or$issuer_ls180.v:180179$13297_Y - connect \en_o \$23 - connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:180193.1-180214.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.wrpick_CR_full_cr" -attribute \generator "nMigen" -module \wrpick_CR_full_cr - attribute \src "issuer_ls180.v:180208.17-180208.89" - wire $not$issuer_ls180.v:180208$13298_Y - attribute \src "issuer_ls180.v:180209.17-180209.89" - wire $reduce_or$issuer_ls180.v:180209$13299_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:180208$13298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \Y $not$issuer_ls180.v:180208$13298_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:180209$13299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:180209$13299_Y - end - connect \$1 $not$issuer_ls180.v:180208$13298_Y - connect \$3 $reduce_or$issuer_ls180.v:180209$13299_Y - connect \en_o \$3 - connect \o \t0 - connect \t0 \i - connect \ni \$1 -end -attribute \src "issuer_ls180.v:180218.1-180275.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.wrpick_FAST_fast1" -attribute \generator "nMigen" -module \wrpick_FAST_fast1 - attribute \src "issuer_ls180.v:180257.17-180257.91" - wire $not$issuer_ls180.v:180257$13300_Y - attribute \src "issuer_ls180.v:180259.18-180259.93" - wire $not$issuer_ls180.v:180259$13302_Y - attribute \src "issuer_ls180.v:180261.18-180261.93" - wire $not$issuer_ls180.v:180261$13304_Y - attribute \src "issuer_ls180.v:180262.17-180262.89" - wire width 5 $not$issuer_ls180.v:180262$13305_Y - attribute \src "issuer_ls180.v:180265.17-180265.91" - wire $not$issuer_ls180.v:180265$13308_Y - attribute \src "issuer_ls180.v:180258.18-180258.106" - wire $reduce_or$issuer_ls180.v:180258$13301_Y - attribute \src "issuer_ls180.v:180260.18-180260.106" - wire $reduce_or$issuer_ls180.v:180260$13303_Y - attribute \src "issuer_ls180.v:180263.18-180263.90" - wire $reduce_or$issuer_ls180.v:180263$13306_Y - attribute \src "issuer_ls180.v:180264.17-180264.103" - wire $reduce_or$issuer_ls180.v:180264$13307_Y - attribute \src "issuer_ls180.v:180266.17-180266.105" - wire $reduce_or$issuer_ls180.v:180266$13309_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 5 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 5 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 5 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 5 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:180257$13300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:180257$13300_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:180259$13302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:180259$13302_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:180261$13304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:180261$13304_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:180262$13305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \i - connect \Y $not$issuer_ls180.v:180262$13305_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:180265$13308 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:180265$13308_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:180258$13301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:180258$13301_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:180260$13303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:180260$13303_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:180263$13306 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:180263$13306_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:180264$13307 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:180264$13307_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:180266$13309 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:180266$13309_Y - end - connect \$7 $not$issuer_ls180.v:180257$13300_Y - connect \$12 $reduce_or$issuer_ls180.v:180258$13301_Y - connect \$11 $not$issuer_ls180.v:180259$13302_Y - connect \$16 $reduce_or$issuer_ls180.v:180260$13303_Y - connect \$15 $not$issuer_ls180.v:180261$13304_Y - connect \$1 $not$issuer_ls180.v:180262$13305_Y - connect \$19 $reduce_or$issuer_ls180.v:180263$13306_Y - connect \$4 $reduce_or$issuer_ls180.v:180264$13307_Y - connect \$3 $not$issuer_ls180.v:180265$13308_Y - connect \$8 $reduce_or$issuer_ls180.v:180266$13309_Y - connect \en_o \$19 - connect \o { \t4 \t3 \t2 \t1 \t0 } - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:180279.1-180381.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.wrpick_INT_o" -attribute \generator "nMigen" -module \wrpick_INT_o - attribute \src "issuer_ls180.v:180348.17-180348.91" - wire $not$issuer_ls180.v:180348$13310_Y - attribute \src "issuer_ls180.v:180350.18-180350.93" - wire $not$issuer_ls180.v:180350$13312_Y - attribute \src "issuer_ls180.v:180352.18-180352.93" - wire $not$issuer_ls180.v:180352$13314_Y - attribute \src "issuer_ls180.v:180353.17-180353.89" - wire width 10 $not$issuer_ls180.v:180353$13315_Y - attribute \src "issuer_ls180.v:180355.18-180355.93" - wire $not$issuer_ls180.v:180355$13317_Y - attribute \src "issuer_ls180.v:180357.18-180357.93" - wire $not$issuer_ls180.v:180357$13319_Y - attribute \src "issuer_ls180.v:180359.18-180359.93" - wire $not$issuer_ls180.v:180359$13321_Y - attribute \src "issuer_ls180.v:180361.18-180361.93" - wire $not$issuer_ls180.v:180361$13323_Y - attribute \src "issuer_ls180.v:180363.18-180363.93" - wire $not$issuer_ls180.v:180363$13325_Y - attribute \src "issuer_ls180.v:180366.17-180366.91" - wire $not$issuer_ls180.v:180366$13328_Y - attribute \src "issuer_ls180.v:180349.18-180349.106" - wire $reduce_or$issuer_ls180.v:180349$13311_Y - attribute \src "issuer_ls180.v:180351.18-180351.106" - wire $reduce_or$issuer_ls180.v:180351$13313_Y - attribute \src "issuer_ls180.v:180354.18-180354.106" - wire $reduce_or$issuer_ls180.v:180354$13316_Y - attribute \src "issuer_ls180.v:180356.18-180356.106" - wire $reduce_or$issuer_ls180.v:180356$13318_Y - attribute \src "issuer_ls180.v:180358.18-180358.106" - wire $reduce_or$issuer_ls180.v:180358$13320_Y - attribute \src "issuer_ls180.v:180360.18-180360.106" - wire $reduce_or$issuer_ls180.v:180360$13322_Y - attribute \src "issuer_ls180.v:180362.18-180362.106" - wire $reduce_or$issuer_ls180.v:180362$13324_Y - attribute \src "issuer_ls180.v:180364.18-180364.90" - wire $reduce_or$issuer_ls180.v:180364$13326_Y - attribute \src "issuer_ls180.v:180365.17-180365.103" - wire $reduce_or$issuer_ls180.v:180365$13327_Y - attribute \src "issuer_ls180.v:180367.17-180367.105" - wire $reduce_or$issuer_ls180.v:180367$13329_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 10 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$36 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$39 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 10 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 10 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 10 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:180348$13310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:180348$13310_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:180350$13312 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:180350$13312_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:180352$13314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$issuer_ls180.v:180352$13314_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:180353$13315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \Y_WIDTH 10 - connect \A \i - connect \Y $not$issuer_ls180.v:180353$13315_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:180355$13317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$issuer_ls180.v:180355$13317_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:180357$13319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$issuer_ls180.v:180357$13319_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:180359$13321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$issuer_ls180.v:180359$13321_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:180361$13323 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$32 - connect \Y $not$issuer_ls180.v:180361$13323_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:180363$13325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$36 - connect \Y $not$issuer_ls180.v:180363$13325_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:180366$13328 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:180366$13328_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:180349$13311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$issuer_ls180.v:180349$13311_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:180351$13313 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$issuer_ls180.v:180351$13313_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:180354$13316 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$issuer_ls180.v:180354$13316_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:180356$13318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$issuer_ls180.v:180356$13318_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:180358$13320 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$issuer_ls180.v:180358$13320_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:180360$13322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 9 - parameter \Y_WIDTH 1 - connect \A { \i [7:0] \ni [8] } - connect \Y $reduce_or$issuer_ls180.v:180360$13322_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:180362$13324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A { \i [8:0] \ni [9] } - connect \Y $reduce_or$issuer_ls180.v:180362$13324_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:180364$13326 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:180364$13326_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:180365$13327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:180365$13327_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:180367$13329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:180367$13329_Y - end - connect \$7 $not$issuer_ls180.v:180348$13310_Y - connect \$12 $reduce_or$issuer_ls180.v:180349$13311_Y - connect \$11 $not$issuer_ls180.v:180350$13312_Y - connect \$16 $reduce_or$issuer_ls180.v:180351$13313_Y - connect \$15 $not$issuer_ls180.v:180352$13314_Y - connect \$1 $not$issuer_ls180.v:180353$13315_Y - connect \$20 $reduce_or$issuer_ls180.v:180354$13316_Y - connect \$19 $not$issuer_ls180.v:180355$13317_Y - connect \$24 $reduce_or$issuer_ls180.v:180356$13318_Y - connect \$23 $not$issuer_ls180.v:180357$13319_Y - connect \$28 $reduce_or$issuer_ls180.v:180358$13320_Y - connect \$27 $not$issuer_ls180.v:180359$13321_Y - connect \$32 $reduce_or$issuer_ls180.v:180360$13322_Y - connect \$31 $not$issuer_ls180.v:180361$13323_Y - connect \$36 $reduce_or$issuer_ls180.v:180362$13324_Y - connect \$35 $not$issuer_ls180.v:180363$13325_Y - connect \$39 $reduce_or$issuer_ls180.v:180364$13326_Y - connect \$4 $reduce_or$issuer_ls180.v:180365$13327_Y - connect \$3 $not$issuer_ls180.v:180366$13328_Y - connect \$8 $reduce_or$issuer_ls180.v:180367$13329_Y - connect \en_o \$39 - connect \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } - connect \t9 \$35 - connect \t8 \$31 - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:180385.1-180406.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.wrpick_SPR_spr1" -attribute \generator "nMigen" -module \wrpick_SPR_spr1 - attribute \src "issuer_ls180.v:180400.17-180400.89" - wire $not$issuer_ls180.v:180400$13330_Y - attribute \src "issuer_ls180.v:180401.17-180401.89" - wire $reduce_or$issuer_ls180.v:180401$13331_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:180400$13330 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \Y $not$issuer_ls180.v:180400$13330_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:180401$13331 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:180401$13331_Y - end - connect \$1 $not$issuer_ls180.v:180400$13330_Y - connect \$3 $reduce_or$issuer_ls180.v:180401$13331_Y - connect \en_o \$3 - connect \o \t0 - connect \t0 \i - connect \ni \$1 -end -attribute \src "issuer_ls180.v:180410.1-180431.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.wrpick_STATE_msr" -attribute \generator "nMigen" -module \wrpick_STATE_msr - attribute \src "issuer_ls180.v:180425.17-180425.89" - wire $not$issuer_ls180.v:180425$13332_Y - attribute \src "issuer_ls180.v:180426.17-180426.89" - wire $reduce_or$issuer_ls180.v:180426$13333_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:180425$13332 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \Y $not$issuer_ls180.v:180425$13332_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:180426$13333 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:180426$13333_Y - end - connect \$1 $not$issuer_ls180.v:180425$13332_Y - connect \$3 $reduce_or$issuer_ls180.v:180426$13333_Y - connect \en_o \$3 - connect \o \t0 - connect \t0 \i - connect \ni \$1 -end -attribute \src "issuer_ls180.v:180435.1-180465.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.wrpick_STATE_nia" -attribute \generator "nMigen" -module \wrpick_STATE_nia - attribute \src "issuer_ls180.v:180456.17-180456.89" - wire width 2 $not$issuer_ls180.v:180456$13334_Y - attribute \src "issuer_ls180.v:180458.17-180458.91" - wire $not$issuer_ls180.v:180458$13336_Y - attribute \src "issuer_ls180.v:180457.17-180457.103" - wire $reduce_or$issuer_ls180.v:180457$13335_Y - attribute \src "issuer_ls180.v:180459.17-180459.89" - wire $reduce_or$issuer_ls180.v:180459$13337_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 2 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 2 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 2 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 2 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:180456$13334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \i - connect \Y $not$issuer_ls180.v:180456$13334_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:180458$13336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:180458$13336_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:180457$13335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:180457$13335_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:180459$13337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:180459$13337_Y - end - connect \$1 $not$issuer_ls180.v:180456$13334_Y - connect \$4 $reduce_or$issuer_ls180.v:180457$13335_Y - connect \$3 $not$issuer_ls180.v:180458$13336_Y - connect \$7 $reduce_or$issuer_ls180.v:180459$13337_Y - connect \en_o \$7 - connect \o { \t1 \t0 } - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:180469.1-180508.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ca" -attribute \generator "nMigen" -module \wrpick_XER_xer_ca - attribute \src "issuer_ls180.v:180496.17-180496.91" - wire $not$issuer_ls180.v:180496$13338_Y - attribute \src "issuer_ls180.v:180498.17-180498.89" - wire width 3 $not$issuer_ls180.v:180498$13340_Y - attribute \src "issuer_ls180.v:180500.17-180500.91" - wire $not$issuer_ls180.v:180500$13342_Y - attribute \src "issuer_ls180.v:180497.18-180497.90" - wire $reduce_or$issuer_ls180.v:180497$13339_Y - attribute \src "issuer_ls180.v:180499.17-180499.103" - wire $reduce_or$issuer_ls180.v:180499$13341_Y - attribute \src "issuer_ls180.v:180501.17-180501.105" - wire $reduce_or$issuer_ls180.v:180501$13343_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 3 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 3 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 3 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:180496$13338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:180496$13338_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:180498$13340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \i - connect \Y $not$issuer_ls180.v:180498$13340_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:180500$13342 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$issuer_ls180.v:180500$13342_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$issuer_ls180.v:180497$13339 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$issuer_ls180.v:180497$13339_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:180499$13341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$issuer_ls180.v:180499$13341_Y + update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$1581 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$issuer_ls180.v:180501$13343 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$issuer_ls180.v:180501$13343_Y - end - connect \$7 $not$issuer_ls180.v:180496$13338_Y - connect \$11 $reduce_or$issuer_ls180.v:180497$13339_Y - connect \$1 $not$issuer_ls180.v:180498$13340_Y - connect \$4 $reduce_or$issuer_ls180.v:180499$13341_Y - connect \$3 $not$issuer_ls180.v:180500$13342_Y - connect \$8 $reduce_or$issuer_ls180.v:180501$13343_Y - connect \en_o \$11 - connect \o { \t2 \t1 \t0 } - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 -end -attribute \src "issuer_ls180.v:180512.1-180560.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ov" -attribute \generator "nMigen" -module \wrpick_XER_xer_ov - attribute \src "issuer_ls180.v:180545.17-180545.91" - wire $not$issuer_ls180.v:180545$13344_Y - attribute \src "issuer_ls180.v:180547.18-180547.93" - wire $not$issuer_ls180.v:180547$13346_Y - attribute \src "issuer_ls180.v:180549.17-180549.89" - wire width 4 $not$issuer_ls180.v:180549$13348_Y - attribute \src "issuer_ls180.v:180551.17-180551.91" - wire $not$issuer_ls180.v:180551$13350_Y - attribute \src "issuer_ls180.v:180546.18-180546.106" - wire $reduce_or$issuer_ls180.v:180546$13345_Y - attribute \src "issuer_ls180.v:180548.18-180548.90" - wire $reduce_or$issuer_ls180.v:180548$13347_Y - attribute \src "issuer_ls180.v:180550.17-180550.103" - wire $reduce_or$issuer_ls180.v:180550$13349_Y - attribute \src "issuer_ls180.v:180552.17-180552.105" - wire $reduce_or$issuer_ls180.v:180552$13351_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 4 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 4 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 4 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 4 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:180545$13344 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$issuer_ls180.v:180545$13344_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$issuer_ls180.v:180547$13346 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$issuer_ls180.v:180547$13346_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$issuer_ls180.v:180549$13348 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \i - connect \Y $not$issuer_ls180.v:180549$13348_Y - end - attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_1_src21__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_1_src31__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_1_src31__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_1_w1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_1_w1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_dest12__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_2_dest12__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_dest22__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_2_dest22__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_dest32__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_2_dest32__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_r2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_2_r2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_src12__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_2_src12__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_src22__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_2_src22__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_src32__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_2_src32__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_w2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_2_w2__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 3 \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 3 \ren_delay$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 3 \ren_delay$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 3 \ren_delay$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 3 \ren_delay$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 3 \ren_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 3 \src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 4 \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 5 \src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 6 \src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 7 \src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 8 \src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 10 \wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 12 \wen$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 14 \wen$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:180783$13360 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reg_0_src10__data_o - connect \B \$7 - connect \Y $or$issuer_ls180.v:180783$13360_Y + attribute \src "libresoc.v:48786.3-48796.6" + process $proc$libresoc.v:48786$1584 + assign { } { } + assign { } { } + assign $0\new_tb[63:0] $1\new_tb[63:0] + attribute \src "libresoc.v:48787.5-48787.29" + switch \initial + attribute \src "libresoc.v:48787.9-48787.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" + switch \fsm_state$115 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\new_tb[63:0] \$120 [63:0] + case + assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \new_tb $0\new_tb[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:180785$13362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reg_1_src21__data_o - connect \B \reg_2_src22__data_o - connect \Y $or$issuer_ls180.v:180785$13362_Y + attribute \src "libresoc.v:48797.3-48805.6" + process $proc$libresoc.v:48797$1585 + assign { } { } + assign { } { } + assign $0\dbg_dmi_we_i$next[0:0]$1586 $1\dbg_dmi_we_i$next[0:0]$1587 + attribute \src "libresoc.v:48798.5-48798.29" + switch \initial + attribute \src "libresoc.v:48798.9-48798.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_we_i$next[0:0]$1587 1'0 + case + assign $1\dbg_dmi_we_i$next[0:0]$1587 \jtag_dmi0_we_i + end + sync always + update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$1586 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:180786$13363 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reg_0_src20__data_o - connect \B \$14 - connect \Y $or$issuer_ls180.v:180786$13363_Y + attribute \src "libresoc.v:48806.3-48814.6" + process $proc$libresoc.v:48806$1588 + assign { } { } + assign { } { } + assign $0\pc_ok_delay$next[0:0]$1589 $1\pc_ok_delay$next[0:0]$1590 + attribute \src "libresoc.v:48807.5-48807.29" + switch \initial + attribute \src "libresoc.v:48807.9-48807.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pc_ok_delay$next[0:0]$1590 1'0 + case + assign $1\pc_ok_delay$next[0:0]$1590 \$19 + end + sync always + update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$1589 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:180788$13365 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reg_1_src31__data_o - connect \B \reg_2_src32__data_o - connect \Y $or$issuer_ls180.v:180788$13365_Y + attribute \src "libresoc.v:48815.3-48830.6" + process $proc$libresoc.v:48815$1591 + assign { } { } + assign { } { } + assign { } { } + assign $0\pc[63:0] $2\pc[63:0] + attribute \src "libresoc.v:48816.5-48816.29" + switch \initial + attribute \src "libresoc.v:48816.9-48816.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:187" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pc[63:0] \pc_i + case + assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + switch \pc_ok_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\pc[63:0] \cia__data_o + case + assign $2\pc[63:0] $1\pc[63:0] + end + sync always + update \pc $0\pc[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$issuer_ls180.v:180789$13366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reg_0_src30__data_o - connect \B \$21 - connect \Y $or$issuer_ls180.v:180789$13366_Y + attribute \src "libresoc.v:48831.3-48843.6" + process $proc$libresoc.v:48831$1592 + assign { } { } + assign { } { } + assign $0\cia__ren[3:0] $1\cia__ren[3:0] + attribute \src "libresoc.v:48832.5-48832.29" + switch \initial + attribute \src "libresoc.v:48832.9-48832.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:187" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\cia__ren[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cia__ren[3:0] 4'0001 + end + sync always + update \cia__ren $0\cia__ren[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$issuer_ls180.v:180791$13368 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reg_1_src11__data_o - connect \B \reg_2_src12__data_o - connect \Y $or$issuer_ls180.v:180791$13368_Y + attribute \src "libresoc.v:48844.3-48864.6" + process $proc$libresoc.v:48844$1593 + assign { } { } + assign { } { } + assign $0\wen[3:0] $1\wen[3:0] + attribute \src "libresoc.v:48845.5-48845.29" + switch \initial + attribute \src "libresoc.v:48845.9-48845.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\wen[3:0] $2\wen[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wen[3:0] $3\wen[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wen[3:0] 4'0001 + case + assign $3\wen[3:0] 4'0000 + end + case + assign $2\wen[3:0] 4'0000 + end + case + assign $1\wen[3:0] 4'0000 + end + sync always + update \wen $0\wen[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$issuer_ls180.v:180784$13361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \ren_delay$11 - connect \Y $reduce_or$issuer_ls180.v:180784$13361_Y + attribute \src "libresoc.v:48865.3-48885.6" + process $proc$libresoc.v:48865$1594 + assign { } { } + assign { } { } + assign $0\data_i[63:0] $1\data_i[63:0] + attribute \src "libresoc.v:48866.5-48866.29" + switch \initial + attribute \src "libresoc.v:48866.9-48866.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\data_i[63:0] $2\data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\data_i[63:0] $3\data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_i[63:0] \nia + case + assign $3\data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $2\data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \data_i $0\data_i[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$issuer_ls180.v:180787$13364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \ren_delay$18 - connect \Y $reduce_or$issuer_ls180.v:180787$13364_Y + attribute \src "libresoc.v:48886.3-48901.6" + process $proc$libresoc.v:48886$1595 + assign { } { } + assign { } { } + assign $0\msr__ren[3:0] $1\msr__ren[3:0] + attribute \src "libresoc.v:48887.5-48887.29" + switch \initial + attribute \src "libresoc.v:48887.9-48887.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\msr__ren[3:0] $2\msr__ren[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + switch \$33 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr__ren[3:0] 4'0010 + case + assign $2\msr__ren[3:0] 4'0000 + end + case + assign $1\msr__ren[3:0] 4'0000 + end + sync always + update \msr__ren $0\msr__ren[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$issuer_ls180.v:180790$13367 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \ren_delay - connect \Y $reduce_or$issuer_ls180.v:180790$13367_Y + attribute \src "libresoc.v:48902.3-48910.6" + process $proc$libresoc.v:48902$1596 + assign { } { } + assign { } { } + assign $0\dbg_dmi_din$next[63:0]$1597 $1\dbg_dmi_din$next[63:0]$1598 + attribute \src "libresoc.v:48903.5-48903.29" + switch \initial + attribute \src "libresoc.v:48903.9-48903.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_din$next[63:0]$1598 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\dbg_dmi_din$next[63:0]$1598 \jtag_dmi0_din + end + sync always + update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$1597 end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:180798.15-180817.4" - cell \reg_0$129 \reg_0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dest10__data_i \reg_0_dest10__data_i - connect \dest10__wen \reg_0_dest10__wen - connect \dest20__data_i \reg_0_dest20__data_i - connect \dest20__wen \reg_0_dest20__wen - connect \dest30__data_i \reg_0_dest30__data_i - connect \dest30__wen \reg_0_dest30__wen - connect \r0__data_o \reg_0_r0__data_o - connect \r0__ren \reg_0_r0__ren - connect \src10__data_o \reg_0_src10__data_o - connect \src10__ren \reg_0_src10__ren - connect \src20__data_o \reg_0_src20__data_o - connect \src20__ren \reg_0_src20__ren - connect \src30__data_o \reg_0_src30__data_o - connect \src30__ren \reg_0_src30__ren - connect \w0__data_i \reg_0_w0__data_i - connect \w0__wen \reg_0_w0__wen + attribute \src "libresoc.v:48911.3-48935.6" + process $proc$libresoc.v:48911$1599 + assign { } { } + assign { } { } + assign { } { } + assign $0\pc_changed$next[0:0]$1600 $3\pc_changed$next[0:0]$1603 + attribute \src "libresoc.v:48912.5-48912.29" + switch \initial + attribute \src "libresoc.v:48912.9-48912.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\pc_changed$next[0:0]$1601 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\pc_changed$next[0:0]$1601 $2\pc_changed$next[0:0]$1602 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + switch \$35 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\pc_changed$next[0:0]$1602 1'1 + case + assign $2\pc_changed$next[0:0]$1602 \pc_changed + end + case + assign $1\pc_changed$next[0:0]$1601 \pc_changed + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\pc_changed$next[0:0]$1603 1'0 + case + assign $3\pc_changed$next[0:0]$1603 $1\pc_changed$next[0:0]$1601 + end + sync always + update \pc_changed$next $0\pc_changed$next[0:0]$1600 end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:180818.15-180837.4" - cell \reg_1$130 \reg_1 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dest11__data_i \reg_1_dest11__data_i - connect \dest11__wen \reg_1_dest11__wen - connect \dest21__data_i \reg_1_dest21__data_i - connect \dest21__wen \reg_1_dest21__wen - connect \dest31__data_i \reg_1_dest31__data_i - connect \dest31__wen \reg_1_dest31__wen - connect \r1__data_o \reg_1_r1__data_o - connect \r1__ren \reg_1_r1__ren - connect \src11__data_o \reg_1_src11__data_o - connect \src11__ren \reg_1_src11__ren - connect \src21__data_o \reg_1_src21__data_o - connect \src21__ren \reg_1_src21__ren - connect \src31__data_o \reg_1_src31__data_o - connect \src31__ren \reg_1_src31__ren - connect \w1__data_i \reg_1_w1__data_i - connect \w1__wen \reg_1_w1__wen + attribute \src "libresoc.v:48936.3-49042.6" + process $proc$libresoc.v:48936$1604 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_asmcode$next[7:0]$1605 $1\core_asmcode$next[7:0]$1656 + assign $0\core_core_cia$next[63:0]$1606 $1\core_core_cia$next[63:0]$1657 + assign $0\core_core_cr_rd$next[7:0]$1607 $1\core_core_cr_rd$next[7:0]$1658 + assign { } { } + assign $0\core_core_cr_wr$next[7:0]$1609 $1\core_core_cr_wr$next[7:0]$1660 + assign { } { } + assign $0\core_core_fn_unit$next[11:0]$1611 $1\core_core_fn_unit$next[11:0]$1662 + assign $0\core_core_input_carry$next[1:0]$1612 $1\core_core_input_carry$next[1:0]$1663 + assign $0\core_core_insn$next[31:0]$1613 $1\core_core_insn$next[31:0]$1664 + assign $0\core_core_insn_type$next[6:0]$1614 $1\core_core_insn_type$next[6:0]$1665 + assign $0\core_core_is_32bit$next[0:0]$1615 $1\core_core_is_32bit$next[0:0]$1666 + assign $0\core_core_lk$next[0:0]$1616 $1\core_core_lk$next[0:0]$1667 + assign $0\core_core_msr$next[63:0]$1617 $1\core_core_msr$next[63:0]$1668 + assign $0\core_core_oe$next[0:0]$1618 $1\core_core_oe$next[0:0]$1669 + assign { } { } + assign $0\core_core_rc$next[0:0]$1620 $1\core_core_rc$next[0:0]$1671 + assign { } { } + assign $0\core_core_trapaddr$next[12:0]$1622 $1\core_core_trapaddr$next[12:0]$1673 + assign $0\core_core_traptype$next[6:0]$1623 $1\core_core_traptype$next[6:0]$1674 + assign $0\core_cr_in1$next[2:0]$1624 $1\core_cr_in1$next[2:0]$1675 + assign { } { } + assign $0\core_cr_in2$39$next[2:0]$1626 $1\core_cr_in2$39$next[2:0]$1677 + assign $0\core_cr_in2$next[2:0]$1627 $1\core_cr_in2$next[2:0]$1678 + assign { } { } + assign { } { } + assign $0\core_cr_out$next[2:0]$1630 $1\core_cr_out$next[2:0]$1681 + assign { } { } + assign $0\core_ea$next[4:0]$1632 $1\core_ea$next[4:0]$1683 + assign { } { } + assign $0\core_fast1$next[2:0]$1634 $1\core_fast1$next[2:0]$1685 + assign { } { } + assign $0\core_fast2$next[2:0]$1636 $1\core_fast2$next[2:0]$1687 + assign { } { } + assign $0\core_fasto1$next[2:0]$1638 $1\core_fasto1$next[2:0]$1689 + assign { } { } + assign $0\core_fasto2$next[2:0]$1640 $1\core_fasto2$next[2:0]$1691 + assign { } { } + assign $0\core_reg1$next[4:0]$1642 $1\core_reg1$next[4:0]$1693 + assign { } { } + assign $0\core_reg2$next[4:0]$1644 $1\core_reg2$next[4:0]$1695 + assign { } { } + assign $0\core_reg3$next[4:0]$1646 $1\core_reg3$next[4:0]$1697 + assign { } { } + assign $0\core_rego$next[4:0]$1648 $1\core_rego$next[4:0]$1699 + assign { } { } + assign $0\core_spr1$next[9:0]$1650 $1\core_spr1$next[9:0]$1701 + assign { } { } + assign $0\core_spro$next[9:0]$1652 $1\core_spro$next[9:0]$1703 + assign { } { } + assign $0\core_xer_in$next[2:0]$1654 $1\core_xer_in$next[2:0]$1705 + assign $0\core_xer_out$next[0:0]$1655 $1\core_xer_out$next[0:0]$1706 + assign $0\core_core_cr_rd_ok$next[0:0]$1608 $4\core_core_cr_rd_ok$next[0:0]$1809 + assign $0\core_core_cr_wr_ok$next[0:0]$1610 $4\core_core_cr_wr_ok$next[0:0]$1810 + assign $0\core_core_oe_ok$next[0:0]$1619 $4\core_core_oe_ok$next[0:0]$1811 + assign $0\core_core_rc_ok$next[0:0]$1621 $4\core_core_rc_ok$next[0:0]$1812 + assign $0\core_cr_in1_ok$next[0:0]$1625 $4\core_cr_in1_ok$next[0:0]$1813 + assign $0\core_cr_in2_ok$40$next[0:0]$1628 $4\core_cr_in2_ok$40$next[0:0]$1814 + assign $0\core_cr_in2_ok$next[0:0]$1629 $4\core_cr_in2_ok$next[0:0]$1815 + assign $0\core_cr_out_ok$next[0:0]$1631 $4\core_cr_out_ok$next[0:0]$1816 + assign $0\core_ea_ok$next[0:0]$1633 $4\core_ea_ok$next[0:0]$1817 + assign $0\core_fast1_ok$next[0:0]$1635 $4\core_fast1_ok$next[0:0]$1818 + assign $0\core_fast2_ok$next[0:0]$1637 $4\core_fast2_ok$next[0:0]$1819 + assign $0\core_fasto1_ok$next[0:0]$1639 $4\core_fasto1_ok$next[0:0]$1820 + assign $0\core_fasto2_ok$next[0:0]$1641 $4\core_fasto2_ok$next[0:0]$1821 + assign $0\core_reg1_ok$next[0:0]$1643 $4\core_reg1_ok$next[0:0]$1822 + assign $0\core_reg2_ok$next[0:0]$1645 $4\core_reg2_ok$next[0:0]$1823 + assign $0\core_reg3_ok$next[0:0]$1647 $4\core_reg3_ok$next[0:0]$1824 + assign $0\core_rego_ok$next[0:0]$1649 $4\core_rego_ok$next[0:0]$1825 + assign $0\core_spr1_ok$next[0:0]$1651 $4\core_spr1_ok$next[0:0]$1826 + assign $0\core_spro_ok$next[0:0]$1653 $4\core_spro_ok$next[0:0]$1827 + attribute \src "libresoc.v:48937.5-48937.29" + switch \initial + attribute \src "libresoc.v:48937.9-48937.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\core_core_is_32bit$next[0:0]$1666 $1\core_core_cr_wr_ok$next[0:0]$1661 $1\core_core_cr_wr$next[7:0]$1660 $1\core_core_cr_rd_ok$next[0:0]$1659 $1\core_core_cr_rd$next[7:0]$1658 $1\core_core_trapaddr$next[12:0]$1673 $1\core_core_traptype$next[6:0]$1674 $1\core_core_input_carry$next[1:0]$1663 $1\core_core_oe_ok$next[0:0]$1670 $1\core_core_oe$next[0:0]$1669 $1\core_core_rc_ok$next[0:0]$1672 $1\core_core_rc$next[0:0]$1671 $1\core_core_lk$next[0:0]$1667 $1\core_core_fn_unit$next[11:0]$1662 $1\core_core_insn_type$next[6:0]$1665 $1\core_core_insn$next[31:0]$1664 $1\core_core_cia$next[63:0]$1657 $1\core_core_msr$next[63:0]$1668 $1\core_cr_out_ok$next[0:0]$1682 $1\core_cr_out$next[2:0]$1681 $1\core_cr_in2_ok$40$next[0:0]$1679 $1\core_cr_in2$39$next[2:0]$1677 $1\core_cr_in2_ok$next[0:0]$1680 $1\core_cr_in2$next[2:0]$1678 $1\core_cr_in1_ok$next[0:0]$1676 $1\core_cr_in1$next[2:0]$1675 $1\core_fasto2_ok$next[0:0]$1692 $1\core_fasto2$next[2:0]$1691 $1\core_fasto1_ok$next[0:0]$1690 $1\core_fasto1$next[2:0]$1689 $1\core_fast2_ok$next[0:0]$1688 $1\core_fast2$next[2:0]$1687 $1\core_fast1_ok$next[0:0]$1686 $1\core_fast1$next[2:0]$1685 $1\core_xer_out$next[0:0]$1706 $1\core_xer_in$next[2:0]$1705 $1\core_spr1_ok$next[0:0]$1702 $1\core_spr1$next[9:0]$1701 $1\core_spro_ok$next[0:0]$1704 $1\core_spro$next[9:0]$1703 $1\core_reg3_ok$next[0:0]$1698 $1\core_reg3$next[4:0]$1697 $1\core_reg2_ok$next[0:0]$1696 $1\core_reg2$next[4:0]$1695 $1\core_reg1_ok$next[0:0]$1694 $1\core_reg1$next[4:0]$1693 $1\core_ea_ok$next[0:0]$1684 $1\core_ea$next[4:0]$1683 $1\core_rego_ok$next[0:0]$1700 $1\core_rego$next[4:0]$1699 $1\core_asmcode$next[7:0]$1656 } 321'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_asmcode$next[7:0]$1656 $2\core_asmcode$next[7:0]$1707 + assign $1\core_core_cia$next[63:0]$1657 $2\core_core_cia$next[63:0]$1708 + assign $1\core_core_cr_rd$next[7:0]$1658 $2\core_core_cr_rd$next[7:0]$1709 + assign $1\core_core_cr_rd_ok$next[0:0]$1659 $2\core_core_cr_rd_ok$next[0:0]$1710 + assign $1\core_core_cr_wr$next[7:0]$1660 $2\core_core_cr_wr$next[7:0]$1711 + assign $1\core_core_cr_wr_ok$next[0:0]$1661 $2\core_core_cr_wr_ok$next[0:0]$1712 + assign $1\core_core_fn_unit$next[11:0]$1662 $2\core_core_fn_unit$next[11:0]$1713 + assign $1\core_core_input_carry$next[1:0]$1663 $2\core_core_input_carry$next[1:0]$1714 + assign $1\core_core_insn$next[31:0]$1664 $2\core_core_insn$next[31:0]$1715 + assign $1\core_core_insn_type$next[6:0]$1665 $2\core_core_insn_type$next[6:0]$1716 + assign $1\core_core_is_32bit$next[0:0]$1666 $2\core_core_is_32bit$next[0:0]$1717 + assign $1\core_core_lk$next[0:0]$1667 $2\core_core_lk$next[0:0]$1718 + assign $1\core_core_msr$next[63:0]$1668 $2\core_core_msr$next[63:0]$1719 + assign $1\core_core_oe$next[0:0]$1669 $2\core_core_oe$next[0:0]$1720 + assign $1\core_core_oe_ok$next[0:0]$1670 $2\core_core_oe_ok$next[0:0]$1721 + assign $1\core_core_rc$next[0:0]$1671 $2\core_core_rc$next[0:0]$1722 + assign $1\core_core_rc_ok$next[0:0]$1672 $2\core_core_rc_ok$next[0:0]$1723 + assign $1\core_core_trapaddr$next[12:0]$1673 $2\core_core_trapaddr$next[12:0]$1724 + assign $1\core_core_traptype$next[6:0]$1674 $2\core_core_traptype$next[6:0]$1725 + assign $1\core_cr_in1$next[2:0]$1675 $2\core_cr_in1$next[2:0]$1726 + assign $1\core_cr_in1_ok$next[0:0]$1676 $2\core_cr_in1_ok$next[0:0]$1727 + assign $1\core_cr_in2$39$next[2:0]$1677 $2\core_cr_in2$39$next[2:0]$1728 + assign $1\core_cr_in2$next[2:0]$1678 $2\core_cr_in2$next[2:0]$1729 + assign $1\core_cr_in2_ok$40$next[0:0]$1679 $2\core_cr_in2_ok$40$next[0:0]$1730 + assign $1\core_cr_in2_ok$next[0:0]$1680 $2\core_cr_in2_ok$next[0:0]$1731 + assign $1\core_cr_out$next[2:0]$1681 $2\core_cr_out$next[2:0]$1732 + assign $1\core_cr_out_ok$next[0:0]$1682 $2\core_cr_out_ok$next[0:0]$1733 + assign $1\core_ea$next[4:0]$1683 $2\core_ea$next[4:0]$1734 + assign $1\core_ea_ok$next[0:0]$1684 $2\core_ea_ok$next[0:0]$1735 + assign $1\core_fast1$next[2:0]$1685 $2\core_fast1$next[2:0]$1736 + assign $1\core_fast1_ok$next[0:0]$1686 $2\core_fast1_ok$next[0:0]$1737 + assign $1\core_fast2$next[2:0]$1687 $2\core_fast2$next[2:0]$1738 + assign $1\core_fast2_ok$next[0:0]$1688 $2\core_fast2_ok$next[0:0]$1739 + assign $1\core_fasto1$next[2:0]$1689 $2\core_fasto1$next[2:0]$1740 + assign $1\core_fasto1_ok$next[0:0]$1690 $2\core_fasto1_ok$next[0:0]$1741 + assign $1\core_fasto2$next[2:0]$1691 $2\core_fasto2$next[2:0]$1742 + assign $1\core_fasto2_ok$next[0:0]$1692 $2\core_fasto2_ok$next[0:0]$1743 + assign $1\core_reg1$next[4:0]$1693 $2\core_reg1$next[4:0]$1744 + assign $1\core_reg1_ok$next[0:0]$1694 $2\core_reg1_ok$next[0:0]$1745 + assign $1\core_reg2$next[4:0]$1695 $2\core_reg2$next[4:0]$1746 + assign $1\core_reg2_ok$next[0:0]$1696 $2\core_reg2_ok$next[0:0]$1747 + assign $1\core_reg3$next[4:0]$1697 $2\core_reg3$next[4:0]$1748 + assign $1\core_reg3_ok$next[0:0]$1698 $2\core_reg3_ok$next[0:0]$1749 + assign $1\core_rego$next[4:0]$1699 $2\core_rego$next[4:0]$1750 + assign $1\core_rego_ok$next[0:0]$1700 $2\core_rego_ok$next[0:0]$1751 + assign $1\core_spr1$next[9:0]$1701 $2\core_spr1$next[9:0]$1752 + assign $1\core_spr1_ok$next[0:0]$1702 $2\core_spr1_ok$next[0:0]$1753 + assign $1\core_spro$next[9:0]$1703 $2\core_spro$next[9:0]$1754 + assign $1\core_spro_ok$next[0:0]$1704 $2\core_spro_ok$next[0:0]$1755 + assign $1\core_xer_in$next[2:0]$1705 $2\core_xer_in$next[2:0]$1756 + assign $1\core_xer_out$next[0:0]$1706 $2\core_xer_out$next[0:0]$1757 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_asmcode$next[7:0]$1707 \core_asmcode + assign $2\core_core_cia$next[63:0]$1708 \core_core_cia + assign $2\core_core_cr_rd$next[7:0]$1709 \core_core_cr_rd + assign $2\core_core_cr_rd_ok$next[0:0]$1710 \core_core_cr_rd_ok + assign $2\core_core_cr_wr$next[7:0]$1711 \core_core_cr_wr + assign $2\core_core_cr_wr_ok$next[0:0]$1712 \core_core_cr_wr_ok + assign $2\core_core_fn_unit$next[11:0]$1713 \core_core_fn_unit + assign $2\core_core_input_carry$next[1:0]$1714 \core_core_input_carry + assign $2\core_core_insn$next[31:0]$1715 \core_core_insn + assign $2\core_core_insn_type$next[6:0]$1716 \core_core_insn_type + assign $2\core_core_is_32bit$next[0:0]$1717 \core_core_is_32bit + assign $2\core_core_lk$next[0:0]$1718 \core_core_lk + assign $2\core_core_msr$next[63:0]$1719 \core_core_msr + assign $2\core_core_oe$next[0:0]$1720 \core_core_oe + assign $2\core_core_oe_ok$next[0:0]$1721 \core_core_oe_ok + assign $2\core_core_rc$next[0:0]$1722 \core_core_rc + assign $2\core_core_rc_ok$next[0:0]$1723 \core_core_rc_ok + assign $2\core_core_trapaddr$next[12:0]$1724 \core_core_trapaddr + assign $2\core_core_traptype$next[6:0]$1725 \core_core_traptype + assign $2\core_cr_in1$next[2:0]$1726 \core_cr_in1 + assign $2\core_cr_in1_ok$next[0:0]$1727 \core_cr_in1_ok + assign $2\core_cr_in2$39$next[2:0]$1728 \core_cr_in2$39 + assign $2\core_cr_in2$next[2:0]$1729 \core_cr_in2 + assign $2\core_cr_in2_ok$40$next[0:0]$1730 \core_cr_in2_ok$40 + assign $2\core_cr_in2_ok$next[0:0]$1731 \core_cr_in2_ok + assign $2\core_cr_out$next[2:0]$1732 \core_cr_out + assign $2\core_cr_out_ok$next[0:0]$1733 \core_cr_out_ok + assign $2\core_ea$next[4:0]$1734 \core_ea + assign $2\core_ea_ok$next[0:0]$1735 \core_ea_ok + assign $2\core_fast1$next[2:0]$1736 \core_fast1 + assign $2\core_fast1_ok$next[0:0]$1737 \core_fast1_ok + assign $2\core_fast2$next[2:0]$1738 \core_fast2 + assign $2\core_fast2_ok$next[0:0]$1739 \core_fast2_ok + assign $2\core_fasto1$next[2:0]$1740 \core_fasto1 + assign $2\core_fasto1_ok$next[0:0]$1741 \core_fasto1_ok + assign $2\core_fasto2$next[2:0]$1742 \core_fasto2 + assign $2\core_fasto2_ok$next[0:0]$1743 \core_fasto2_ok + assign $2\core_reg1$next[4:0]$1744 \core_reg1 + assign $2\core_reg1_ok$next[0:0]$1745 \core_reg1_ok + assign $2\core_reg2$next[4:0]$1746 \core_reg2 + assign $2\core_reg2_ok$next[0:0]$1747 \core_reg2_ok + assign $2\core_reg3$next[4:0]$1748 \core_reg3 + assign $2\core_reg3_ok$next[0:0]$1749 \core_reg3_ok + assign $2\core_rego$next[4:0]$1750 \core_rego + assign $2\core_rego_ok$next[0:0]$1751 \core_rego_ok + assign $2\core_spr1$next[9:0]$1752 \core_spr1 + assign $2\core_spr1_ok$next[0:0]$1753 \core_spr1_ok + assign $2\core_spro$next[9:0]$1754 \core_spro + assign $2\core_spro_ok$next[0:0]$1755 \core_spro_ok + assign $2\core_xer_in$next[2:0]$1756 \core_xer_in + assign $2\core_xer_out$next[0:0]$1757 \core_xer_out + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\core_core_is_32bit$next[0:0]$1717 $2\core_core_cr_wr_ok$next[0:0]$1712 $2\core_core_cr_wr$next[7:0]$1711 $2\core_core_cr_rd_ok$next[0:0]$1710 $2\core_core_cr_rd$next[7:0]$1709 $2\core_core_trapaddr$next[12:0]$1724 $2\core_core_traptype$next[6:0]$1725 $2\core_core_input_carry$next[1:0]$1714 $2\core_core_oe_ok$next[0:0]$1721 $2\core_core_oe$next[0:0]$1720 $2\core_core_rc_ok$next[0:0]$1723 $2\core_core_rc$next[0:0]$1722 $2\core_core_lk$next[0:0]$1718 $2\core_core_fn_unit$next[11:0]$1713 $2\core_core_insn_type$next[6:0]$1716 $2\core_core_insn$next[31:0]$1715 $2\core_core_cia$next[63:0]$1708 $2\core_core_msr$next[63:0]$1719 $2\core_cr_out_ok$next[0:0]$1733 $2\core_cr_out$next[2:0]$1732 $2\core_cr_in2_ok$40$next[0:0]$1730 $2\core_cr_in2$39$next[2:0]$1728 $2\core_cr_in2_ok$next[0:0]$1731 $2\core_cr_in2$next[2:0]$1729 $2\core_cr_in1_ok$next[0:0]$1727 $2\core_cr_in1$next[2:0]$1726 $2\core_fasto2_ok$next[0:0]$1743 $2\core_fasto2$next[2:0]$1742 $2\core_fasto1_ok$next[0:0]$1741 $2\core_fasto1$next[2:0]$1740 $2\core_fast2_ok$next[0:0]$1739 $2\core_fast2$next[2:0]$1738 $2\core_fast1_ok$next[0:0]$1737 $2\core_fast1$next[2:0]$1736 $2\core_xer_out$next[0:0]$1757 $2\core_xer_in$next[2:0]$1756 $2\core_spr1_ok$next[0:0]$1753 $2\core_spr1$next[9:0]$1752 $2\core_spro_ok$next[0:0]$1755 $2\core_spro$next[9:0]$1754 $2\core_reg3_ok$next[0:0]$1749 $2\core_reg3$next[4:0]$1748 $2\core_reg2_ok$next[0:0]$1747 $2\core_reg2$next[4:0]$1746 $2\core_reg1_ok$next[0:0]$1745 $2\core_reg1$next[4:0]$1744 $2\core_ea_ok$next[0:0]$1735 $2\core_ea$next[4:0]$1734 $2\core_rego_ok$next[0:0]$1751 $2\core_rego$next[4:0]$1750 $2\core_asmcode$next[7:0]$1707 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$2 \dec2_cr_in2$1 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_asmcode$next[7:0]$1656 $3\core_asmcode$next[7:0]$1758 + assign $1\core_core_cia$next[63:0]$1657 $3\core_core_cia$next[63:0]$1759 + assign $1\core_core_cr_rd$next[7:0]$1658 $3\core_core_cr_rd$next[7:0]$1760 + assign $1\core_core_cr_rd_ok$next[0:0]$1659 $3\core_core_cr_rd_ok$next[0:0]$1761 + assign $1\core_core_cr_wr$next[7:0]$1660 $3\core_core_cr_wr$next[7:0]$1762 + assign $1\core_core_cr_wr_ok$next[0:0]$1661 $3\core_core_cr_wr_ok$next[0:0]$1763 + assign $1\core_core_fn_unit$next[11:0]$1662 $3\core_core_fn_unit$next[11:0]$1764 + assign $1\core_core_input_carry$next[1:0]$1663 $3\core_core_input_carry$next[1:0]$1765 + assign $1\core_core_insn$next[31:0]$1664 $3\core_core_insn$next[31:0]$1766 + assign $1\core_core_insn_type$next[6:0]$1665 $3\core_core_insn_type$next[6:0]$1767 + assign $1\core_core_is_32bit$next[0:0]$1666 $3\core_core_is_32bit$next[0:0]$1768 + assign $1\core_core_lk$next[0:0]$1667 $3\core_core_lk$next[0:0]$1769 + assign $1\core_core_msr$next[63:0]$1668 $3\core_core_msr$next[63:0]$1770 + assign $1\core_core_oe$next[0:0]$1669 $3\core_core_oe$next[0:0]$1771 + assign $1\core_core_oe_ok$next[0:0]$1670 $3\core_core_oe_ok$next[0:0]$1772 + assign $1\core_core_rc$next[0:0]$1671 $3\core_core_rc$next[0:0]$1773 + assign $1\core_core_rc_ok$next[0:0]$1672 $3\core_core_rc_ok$next[0:0]$1774 + assign $1\core_core_trapaddr$next[12:0]$1673 $3\core_core_trapaddr$next[12:0]$1775 + assign $1\core_core_traptype$next[6:0]$1674 $3\core_core_traptype$next[6:0]$1776 + assign $1\core_cr_in1$next[2:0]$1675 $3\core_cr_in1$next[2:0]$1777 + assign $1\core_cr_in1_ok$next[0:0]$1676 $3\core_cr_in1_ok$next[0:0]$1778 + assign $1\core_cr_in2$39$next[2:0]$1677 $3\core_cr_in2$39$next[2:0]$1779 + assign $1\core_cr_in2$next[2:0]$1678 $3\core_cr_in2$next[2:0]$1780 + assign $1\core_cr_in2_ok$40$next[0:0]$1679 $3\core_cr_in2_ok$40$next[0:0]$1781 + assign $1\core_cr_in2_ok$next[0:0]$1680 $3\core_cr_in2_ok$next[0:0]$1782 + assign $1\core_cr_out$next[2:0]$1681 $3\core_cr_out$next[2:0]$1783 + assign $1\core_cr_out_ok$next[0:0]$1682 $3\core_cr_out_ok$next[0:0]$1784 + assign $1\core_ea$next[4:0]$1683 $3\core_ea$next[4:0]$1785 + assign $1\core_ea_ok$next[0:0]$1684 $3\core_ea_ok$next[0:0]$1786 + assign $1\core_fast1$next[2:0]$1685 $3\core_fast1$next[2:0]$1787 + assign $1\core_fast1_ok$next[0:0]$1686 $3\core_fast1_ok$next[0:0]$1788 + assign $1\core_fast2$next[2:0]$1687 $3\core_fast2$next[2:0]$1789 + assign $1\core_fast2_ok$next[0:0]$1688 $3\core_fast2_ok$next[0:0]$1790 + assign $1\core_fasto1$next[2:0]$1689 $3\core_fasto1$next[2:0]$1791 + assign $1\core_fasto1_ok$next[0:0]$1690 $3\core_fasto1_ok$next[0:0]$1792 + assign $1\core_fasto2$next[2:0]$1691 $3\core_fasto2$next[2:0]$1793 + assign $1\core_fasto2_ok$next[0:0]$1692 $3\core_fasto2_ok$next[0:0]$1794 + assign $1\core_reg1$next[4:0]$1693 $3\core_reg1$next[4:0]$1795 + assign $1\core_reg1_ok$next[0:0]$1694 $3\core_reg1_ok$next[0:0]$1796 + assign $1\core_reg2$next[4:0]$1695 $3\core_reg2$next[4:0]$1797 + assign $1\core_reg2_ok$next[0:0]$1696 $3\core_reg2_ok$next[0:0]$1798 + assign $1\core_reg3$next[4:0]$1697 $3\core_reg3$next[4:0]$1799 + assign $1\core_reg3_ok$next[0:0]$1698 $3\core_reg3_ok$next[0:0]$1800 + assign $1\core_rego$next[4:0]$1699 $3\core_rego$next[4:0]$1801 + assign $1\core_rego_ok$next[0:0]$1700 $3\core_rego_ok$next[0:0]$1802 + assign $1\core_spr1$next[9:0]$1701 $3\core_spr1$next[9:0]$1803 + assign $1\core_spr1_ok$next[0:0]$1702 $3\core_spr1_ok$next[0:0]$1804 + assign $1\core_spro$next[9:0]$1703 $3\core_spro$next[9:0]$1805 + assign $1\core_spro_ok$next[0:0]$1704 $3\core_spro_ok$next[0:0]$1806 + assign $1\core_xer_in$next[2:0]$1705 $3\core_xer_in$next[2:0]$1807 + assign $1\core_xer_out$next[0:0]$1706 $3\core_xer_out$next[0:0]$1808 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + switch \$41 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\core_core_is_32bit$next[0:0]$1768 $3\core_core_cr_wr_ok$next[0:0]$1763 $3\core_core_cr_wr$next[7:0]$1762 $3\core_core_cr_rd_ok$next[0:0]$1761 $3\core_core_cr_rd$next[7:0]$1760 $3\core_core_trapaddr$next[12:0]$1775 $3\core_core_traptype$next[6:0]$1776 $3\core_core_input_carry$next[1:0]$1765 $3\core_core_oe_ok$next[0:0]$1772 $3\core_core_oe$next[0:0]$1771 $3\core_core_rc_ok$next[0:0]$1774 $3\core_core_rc$next[0:0]$1773 $3\core_core_lk$next[0:0]$1769 $3\core_core_fn_unit$next[11:0]$1764 $3\core_core_insn_type$next[6:0]$1767 $3\core_core_insn$next[31:0]$1766 $3\core_core_cia$next[63:0]$1759 $3\core_core_msr$next[63:0]$1770 $3\core_cr_out_ok$next[0:0]$1784 $3\core_cr_out$next[2:0]$1783 $3\core_cr_in2_ok$40$next[0:0]$1781 $3\core_cr_in2$39$next[2:0]$1779 $3\core_cr_in2_ok$next[0:0]$1782 $3\core_cr_in2$next[2:0]$1780 $3\core_cr_in1_ok$next[0:0]$1778 $3\core_cr_in1$next[2:0]$1777 $3\core_fasto2_ok$next[0:0]$1794 $3\core_fasto2$next[2:0]$1793 $3\core_fasto1_ok$next[0:0]$1792 $3\core_fasto1$next[2:0]$1791 $3\core_fast2_ok$next[0:0]$1790 $3\core_fast2$next[2:0]$1789 $3\core_fast1_ok$next[0:0]$1788 $3\core_fast1$next[2:0]$1787 $3\core_xer_out$next[0:0]$1808 $3\core_xer_in$next[2:0]$1807 $3\core_spr1_ok$next[0:0]$1804 $3\core_spr1$next[9:0]$1803 $3\core_spro_ok$next[0:0]$1806 $3\core_spro$next[9:0]$1805 $3\core_reg3_ok$next[0:0]$1800 $3\core_reg3$next[4:0]$1799 $3\core_reg2_ok$next[0:0]$1798 $3\core_reg2$next[4:0]$1797 $3\core_reg1_ok$next[0:0]$1796 $3\core_reg1$next[4:0]$1795 $3\core_ea_ok$next[0:0]$1786 $3\core_ea$next[4:0]$1785 $3\core_rego_ok$next[0:0]$1802 $3\core_rego$next[4:0]$1801 $3\core_asmcode$next[7:0]$1758 } 321'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\core_asmcode$next[7:0]$1758 \core_asmcode + assign $3\core_core_cia$next[63:0]$1759 \core_core_cia + assign $3\core_core_cr_rd$next[7:0]$1760 \core_core_cr_rd + assign $3\core_core_cr_rd_ok$next[0:0]$1761 \core_core_cr_rd_ok + assign $3\core_core_cr_wr$next[7:0]$1762 \core_core_cr_wr + assign $3\core_core_cr_wr_ok$next[0:0]$1763 \core_core_cr_wr_ok + assign $3\core_core_fn_unit$next[11:0]$1764 \core_core_fn_unit + assign $3\core_core_input_carry$next[1:0]$1765 \core_core_input_carry + assign $3\core_core_insn$next[31:0]$1766 \core_core_insn + assign $3\core_core_insn_type$next[6:0]$1767 \core_core_insn_type + assign $3\core_core_is_32bit$next[0:0]$1768 \core_core_is_32bit + assign $3\core_core_lk$next[0:0]$1769 \core_core_lk + assign $3\core_core_msr$next[63:0]$1770 \core_core_msr + assign $3\core_core_oe$next[0:0]$1771 \core_core_oe + assign $3\core_core_oe_ok$next[0:0]$1772 \core_core_oe_ok + assign $3\core_core_rc$next[0:0]$1773 \core_core_rc + assign $3\core_core_rc_ok$next[0:0]$1774 \core_core_rc_ok + assign $3\core_core_trapaddr$next[12:0]$1775 \core_core_trapaddr + assign $3\core_core_traptype$next[6:0]$1776 \core_core_traptype + assign $3\core_cr_in1$next[2:0]$1777 \core_cr_in1 + assign $3\core_cr_in1_ok$next[0:0]$1778 \core_cr_in1_ok + assign $3\core_cr_in2$39$next[2:0]$1779 \core_cr_in2$39 + assign $3\core_cr_in2$next[2:0]$1780 \core_cr_in2 + assign $3\core_cr_in2_ok$40$next[0:0]$1781 \core_cr_in2_ok$40 + assign $3\core_cr_in2_ok$next[0:0]$1782 \core_cr_in2_ok + assign $3\core_cr_out$next[2:0]$1783 \core_cr_out + assign $3\core_cr_out_ok$next[0:0]$1784 \core_cr_out_ok + assign $3\core_ea$next[4:0]$1785 \core_ea + assign $3\core_ea_ok$next[0:0]$1786 \core_ea_ok + assign $3\core_fast1$next[2:0]$1787 \core_fast1 + assign $3\core_fast1_ok$next[0:0]$1788 \core_fast1_ok + assign $3\core_fast2$next[2:0]$1789 \core_fast2 + assign $3\core_fast2_ok$next[0:0]$1790 \core_fast2_ok + assign $3\core_fasto1$next[2:0]$1791 \core_fasto1 + assign $3\core_fasto1_ok$next[0:0]$1792 \core_fasto1_ok + assign $3\core_fasto2$next[2:0]$1793 \core_fasto2 + assign $3\core_fasto2_ok$next[0:0]$1794 \core_fasto2_ok + assign $3\core_reg1$next[4:0]$1795 \core_reg1 + assign $3\core_reg1_ok$next[0:0]$1796 \core_reg1_ok + assign $3\core_reg2$next[4:0]$1797 \core_reg2 + assign $3\core_reg2_ok$next[0:0]$1798 \core_reg2_ok + assign $3\core_reg3$next[4:0]$1799 \core_reg3 + assign $3\core_reg3_ok$next[0:0]$1800 \core_reg3_ok + assign $3\core_rego$next[4:0]$1801 \core_rego + assign $3\core_rego_ok$next[0:0]$1802 \core_rego_ok + assign $3\core_spr1$next[9:0]$1803 \core_spr1 + assign $3\core_spr1_ok$next[0:0]$1804 \core_spr1_ok + assign $3\core_spro$next[9:0]$1805 \core_spro + assign $3\core_spro_ok$next[0:0]$1806 \core_spro_ok + assign $3\core_xer_in$next[2:0]$1807 \core_xer_in + assign $3\core_xer_out$next[0:0]$1808 \core_xer_out + end + case + assign $1\core_asmcode$next[7:0]$1656 \core_asmcode + assign $1\core_core_cia$next[63:0]$1657 \core_core_cia + assign $1\core_core_cr_rd$next[7:0]$1658 \core_core_cr_rd + assign $1\core_core_cr_rd_ok$next[0:0]$1659 \core_core_cr_rd_ok + assign $1\core_core_cr_wr$next[7:0]$1660 \core_core_cr_wr + assign $1\core_core_cr_wr_ok$next[0:0]$1661 \core_core_cr_wr_ok + assign $1\core_core_fn_unit$next[11:0]$1662 \core_core_fn_unit + assign $1\core_core_input_carry$next[1:0]$1663 \core_core_input_carry + assign $1\core_core_insn$next[31:0]$1664 \core_core_insn + assign $1\core_core_insn_type$next[6:0]$1665 \core_core_insn_type + assign $1\core_core_is_32bit$next[0:0]$1666 \core_core_is_32bit + assign $1\core_core_lk$next[0:0]$1667 \core_core_lk + assign $1\core_core_msr$next[63:0]$1668 \core_core_msr + assign $1\core_core_oe$next[0:0]$1669 \core_core_oe + assign $1\core_core_oe_ok$next[0:0]$1670 \core_core_oe_ok + assign $1\core_core_rc$next[0:0]$1671 \core_core_rc + assign $1\core_core_rc_ok$next[0:0]$1672 \core_core_rc_ok + assign $1\core_core_trapaddr$next[12:0]$1673 \core_core_trapaddr + assign $1\core_core_traptype$next[6:0]$1674 \core_core_traptype + assign $1\core_cr_in1$next[2:0]$1675 \core_cr_in1 + assign $1\core_cr_in1_ok$next[0:0]$1676 \core_cr_in1_ok + assign $1\core_cr_in2$39$next[2:0]$1677 \core_cr_in2$39 + assign $1\core_cr_in2$next[2:0]$1678 \core_cr_in2 + assign $1\core_cr_in2_ok$40$next[0:0]$1679 \core_cr_in2_ok$40 + assign $1\core_cr_in2_ok$next[0:0]$1680 \core_cr_in2_ok + assign $1\core_cr_out$next[2:0]$1681 \core_cr_out + assign $1\core_cr_out_ok$next[0:0]$1682 \core_cr_out_ok + assign $1\core_ea$next[4:0]$1683 \core_ea + assign $1\core_ea_ok$next[0:0]$1684 \core_ea_ok + assign $1\core_fast1$next[2:0]$1685 \core_fast1 + assign $1\core_fast1_ok$next[0:0]$1686 \core_fast1_ok + assign $1\core_fast2$next[2:0]$1687 \core_fast2 + assign $1\core_fast2_ok$next[0:0]$1688 \core_fast2_ok + assign $1\core_fasto1$next[2:0]$1689 \core_fasto1 + assign $1\core_fasto1_ok$next[0:0]$1690 \core_fasto1_ok + assign $1\core_fasto2$next[2:0]$1691 \core_fasto2 + assign $1\core_fasto2_ok$next[0:0]$1692 \core_fasto2_ok + assign $1\core_reg1$next[4:0]$1693 \core_reg1 + assign $1\core_reg1_ok$next[0:0]$1694 \core_reg1_ok + assign $1\core_reg2$next[4:0]$1695 \core_reg2 + assign $1\core_reg2_ok$next[0:0]$1696 \core_reg2_ok + assign $1\core_reg3$next[4:0]$1697 \core_reg3 + assign $1\core_reg3_ok$next[0:0]$1698 \core_reg3_ok + assign $1\core_rego$next[4:0]$1699 \core_rego + assign $1\core_rego_ok$next[0:0]$1700 \core_rego_ok + assign $1\core_spr1$next[9:0]$1701 \core_spr1 + assign $1\core_spr1_ok$next[0:0]$1702 \core_spr1_ok + assign $1\core_spro$next[9:0]$1703 \core_spro + assign $1\core_spro_ok$next[0:0]$1704 \core_spro_ok + assign $1\core_xer_in$next[2:0]$1705 \core_xer_in + assign $1\core_xer_out$next[0:0]$1706 \core_xer_out + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $4\core_rego_ok$next[0:0]$1825 1'0 + assign $4\core_ea_ok$next[0:0]$1817 1'0 + assign $4\core_reg1_ok$next[0:0]$1822 1'0 + assign $4\core_reg2_ok$next[0:0]$1823 1'0 + assign $4\core_reg3_ok$next[0:0]$1824 1'0 + assign $4\core_spro_ok$next[0:0]$1827 1'0 + assign $4\core_spr1_ok$next[0:0]$1826 1'0 + assign $4\core_fast1_ok$next[0:0]$1818 1'0 + assign $4\core_fast2_ok$next[0:0]$1819 1'0 + assign $4\core_fasto1_ok$next[0:0]$1820 1'0 + assign $4\core_fasto2_ok$next[0:0]$1821 1'0 + assign $4\core_cr_in1_ok$next[0:0]$1813 1'0 + assign $4\core_cr_in2_ok$next[0:0]$1815 1'0 + assign $4\core_cr_in2_ok$40$next[0:0]$1814 1'0 + assign $4\core_cr_out_ok$next[0:0]$1816 1'0 + assign $4\core_core_rc_ok$next[0:0]$1812 1'0 + assign $4\core_core_oe_ok$next[0:0]$1811 1'0 + assign $4\core_core_cr_rd_ok$next[0:0]$1809 1'0 + assign $4\core_core_cr_wr_ok$next[0:0]$1810 1'0 + case + assign $4\core_core_cr_rd_ok$next[0:0]$1809 $1\core_core_cr_rd_ok$next[0:0]$1659 + assign $4\core_core_cr_wr_ok$next[0:0]$1810 $1\core_core_cr_wr_ok$next[0:0]$1661 + assign $4\core_core_oe_ok$next[0:0]$1811 $1\core_core_oe_ok$next[0:0]$1670 + assign $4\core_core_rc_ok$next[0:0]$1812 $1\core_core_rc_ok$next[0:0]$1672 + assign $4\core_cr_in1_ok$next[0:0]$1813 $1\core_cr_in1_ok$next[0:0]$1676 + assign $4\core_cr_in2_ok$40$next[0:0]$1814 $1\core_cr_in2_ok$40$next[0:0]$1679 + assign $4\core_cr_in2_ok$next[0:0]$1815 $1\core_cr_in2_ok$next[0:0]$1680 + assign $4\core_cr_out_ok$next[0:0]$1816 $1\core_cr_out_ok$next[0:0]$1682 + assign $4\core_ea_ok$next[0:0]$1817 $1\core_ea_ok$next[0:0]$1684 + assign $4\core_fast1_ok$next[0:0]$1818 $1\core_fast1_ok$next[0:0]$1686 + assign $4\core_fast2_ok$next[0:0]$1819 $1\core_fast2_ok$next[0:0]$1688 + assign $4\core_fasto1_ok$next[0:0]$1820 $1\core_fasto1_ok$next[0:0]$1690 + assign $4\core_fasto2_ok$next[0:0]$1821 $1\core_fasto2_ok$next[0:0]$1692 + assign $4\core_reg1_ok$next[0:0]$1822 $1\core_reg1_ok$next[0:0]$1694 + assign $4\core_reg2_ok$next[0:0]$1823 $1\core_reg2_ok$next[0:0]$1696 + assign $4\core_reg3_ok$next[0:0]$1824 $1\core_reg3_ok$next[0:0]$1698 + assign $4\core_rego_ok$next[0:0]$1825 $1\core_rego_ok$next[0:0]$1700 + assign $4\core_spr1_ok$next[0:0]$1826 $1\core_spr1_ok$next[0:0]$1702 + assign $4\core_spro_ok$next[0:0]$1827 $1\core_spro_ok$next[0:0]$1704 + end + sync always + update \core_asmcode$next $0\core_asmcode$next[7:0]$1605 + update \core_core_cia$next $0\core_core_cia$next[63:0]$1606 + update \core_core_cr_rd$next $0\core_core_cr_rd$next[7:0]$1607 + update \core_core_cr_rd_ok$next $0\core_core_cr_rd_ok$next[0:0]$1608 + update \core_core_cr_wr$next $0\core_core_cr_wr$next[7:0]$1609 + update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$1610 + update \core_core_fn_unit$next $0\core_core_fn_unit$next[11:0]$1611 + update \core_core_input_carry$next $0\core_core_input_carry$next[1:0]$1612 + update \core_core_insn$next $0\core_core_insn$next[31:0]$1613 + update \core_core_insn_type$next $0\core_core_insn_type$next[6:0]$1614 + update \core_core_is_32bit$next $0\core_core_is_32bit$next[0:0]$1615 + update \core_core_lk$next $0\core_core_lk$next[0:0]$1616 + update \core_core_msr$next $0\core_core_msr$next[63:0]$1617 + update \core_core_oe$next $0\core_core_oe$next[0:0]$1618 + update \core_core_oe_ok$next $0\core_core_oe_ok$next[0:0]$1619 + update \core_core_rc$next $0\core_core_rc$next[0:0]$1620 + update \core_core_rc_ok$next $0\core_core_rc_ok$next[0:0]$1621 + update \core_core_trapaddr$next $0\core_core_trapaddr$next[12:0]$1622 + update \core_core_traptype$next $0\core_core_traptype$next[6:0]$1623 + update \core_cr_in1$next $0\core_cr_in1$next[2:0]$1624 + update \core_cr_in1_ok$next $0\core_cr_in1_ok$next[0:0]$1625 + update \core_cr_in2$39$next $0\core_cr_in2$39$next[2:0]$1626 + update \core_cr_in2$next $0\core_cr_in2$next[2:0]$1627 + update \core_cr_in2_ok$40$next $0\core_cr_in2_ok$40$next[0:0]$1628 + update \core_cr_in2_ok$next $0\core_cr_in2_ok$next[0:0]$1629 + update \core_cr_out$next $0\core_cr_out$next[2:0]$1630 + update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$1631 + update \core_ea$next $0\core_ea$next[4:0]$1632 + update \core_ea_ok$next $0\core_ea_ok$next[0:0]$1633 + update \core_fast1$next $0\core_fast1$next[2:0]$1634 + update \core_fast1_ok$next $0\core_fast1_ok$next[0:0]$1635 + update \core_fast2$next $0\core_fast2$next[2:0]$1636 + update \core_fast2_ok$next $0\core_fast2_ok$next[0:0]$1637 + update \core_fasto1$next $0\core_fasto1$next[2:0]$1638 + update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$1639 + update \core_fasto2$next $0\core_fasto2$next[2:0]$1640 + update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$1641 + update \core_reg1$next $0\core_reg1$next[4:0]$1642 + update \core_reg1_ok$next $0\core_reg1_ok$next[0:0]$1643 + update \core_reg2$next $0\core_reg2$next[4:0]$1644 + update \core_reg2_ok$next $0\core_reg2_ok$next[0:0]$1645 + update \core_reg3$next $0\core_reg3$next[4:0]$1646 + update \core_reg3_ok$next $0\core_reg3_ok$next[0:0]$1647 + update \core_rego$next $0\core_rego$next[4:0]$1648 + update \core_rego_ok$next $0\core_rego_ok$next[0:0]$1649 + update \core_spr1$next $0\core_spr1$next[9:0]$1650 + update \core_spr1_ok$next $0\core_spr1_ok$next[0:0]$1651 + update \core_spro$next $0\core_spro$next[9:0]$1652 + update \core_spro_ok$next $0\core_spro_ok$next[0:0]$1653 + update \core_xer_in$next $0\core_xer_in$next[2:0]$1654 + update \core_xer_out$next $0\core_xer_out$next[0:0]$1655 + end + attribute \src "libresoc.v:49043.3-49051.6" + process $proc$libresoc.v:49043$1828 + assign { } { } + assign { } { } + assign $0\jtag_dmi0_ack_o$next[0:0]$1829 $1\jtag_dmi0_ack_o$next[0:0]$1830 + attribute \src "libresoc.v:49044.5-49044.29" + switch \initial + attribute \src "libresoc.v:49044.9-49044.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_dmi0_ack_o$next[0:0]$1830 1'0 + case + assign $1\jtag_dmi0_ack_o$next[0:0]$1830 \dbg_dmi_ack_o + end + sync always + update \jtag_dmi0_ack_o$next $0\jtag_dmi0_ack_o$next[0:0]$1829 end - attribute \module_not_derived 1 - attribute \src "issuer_ls180.v:180838.15-180857.4" - cell \reg_2$131 \reg_2 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dest12__data_i \reg_2_dest12__data_i - connect \dest12__wen \reg_2_dest12__wen - connect \dest22__data_i \reg_2_dest22__data_i - connect \dest22__wen \reg_2_dest22__wen - connect \dest32__data_i \reg_2_dest32__data_i - connect \dest32__wen \reg_2_dest32__wen - connect \r2__data_o \reg_2_r2__data_o - connect \r2__ren \reg_2_r2__ren - connect \src12__data_o \reg_2_src12__data_o - connect \src12__ren \reg_2_src12__ren - connect \src22__data_o \reg_2_src22__data_o - connect \src22__ren \reg_2_src22__ren - connect \src32__data_o \reg_2_src32__data_o - connect \src32__ren \reg_2_src32__ren - connect \w2__data_i \reg_2_w2__data_i - connect \w2__wen \reg_2_w2__wen - end - attribute \src "issuer_ls180.v:180617.7-180617.20" - process $proc$issuer_ls180.v:180617$13386 + attribute \src "libresoc.v:49052.3-49060.6" + process $proc$libresoc.v:49052$1831 assign { } { } - assign $0\initial[0:0] 1'0 + assign { } { } + assign $0\jtag_dmi0_dout$next[63:0]$1832 $1\jtag_dmi0_dout$next[63:0]$1833 + attribute \src "libresoc.v:49053.5-49053.29" + switch \initial + attribute \src "libresoc.v:49053.9-49053.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_dmi0_dout$next[63:0]$1833 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\jtag_dmi0_dout$next[63:0]$1833 \dbg_dmi_dout + end sync always - update \initial $0\initial[0:0] - sync init + update \jtag_dmi0_dout$next $0\jtag_dmi0_dout$next[63:0]$1832 end - attribute \src "issuer_ls180.v:180751.13-180751.29" - process $proc$issuer_ls180.v:180751$13387 + attribute \src "libresoc.v:49061.3-49069.6" + process $proc$libresoc.v:49061$1834 assign { } { } - assign $1\ren_delay[2:0] 3'000 + assign { } { } + assign $0\dec2_cur_eint$next[0:0]$1835 $1\dec2_cur_eint$next[0:0]$1836 + attribute \src "libresoc.v:49062.5-49062.29" + switch \initial + attribute \src "libresoc.v:49062.9-49062.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dec2_cur_eint$next[0:0]$1836 1'0 + case + assign $1\dec2_cur_eint$next[0:0]$1836 \xics_icp_core_irq_o + end sync always - sync init - update \ren_delay $1\ren_delay[2:0] + update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$1835 + end + attribute \src "libresoc.v:49070.3-49106.6" + process $proc$libresoc.v:49070$1837 + assign { } { } + assign { } { } + assign { } { } + assign $0\raw_insn_i$next[31:0]$1838 $4\raw_insn_i$next[31:0]$1842 + attribute \src "libresoc.v:49071.5-49071.29" + switch \initial + attribute \src "libresoc.v:49071.9-49071.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\raw_insn_i$next[31:0]$1839 0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\raw_insn_i$next[31:0]$1839 $2\raw_insn_i$next[31:0]$1840 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\raw_insn_i$next[31:0]$1840 \raw_insn_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\raw_insn_i$next[31:0]$1840 \dec2_raw_opcode_in + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\raw_insn_i$next[31:0]$1839 $3\raw_insn_i$next[31:0]$1841 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + switch \$43 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\raw_insn_i$next[31:0]$1841 0 + case + assign $3\raw_insn_i$next[31:0]$1841 \raw_insn_i + end + case + assign $1\raw_insn_i$next[31:0]$1839 \raw_insn_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\raw_insn_i$next[31:0]$1842 0 + case + assign $4\raw_insn_i$next[31:0]$1842 $1\raw_insn_i$next[31:0]$1839 + end + sync always + update \raw_insn_i$next $0\raw_insn_i$next[31:0]$1838 end - attribute \src "issuer_ls180.v:180753.13-180753.34" - process $proc$issuer_ls180.v:180753$13388 + attribute \src "libresoc.v:49107.3-49143.6" + process $proc$libresoc.v:49107$1843 + assign { } { } + assign { } { } assign { } { } - assign $0\ren_delay$11[2:0]$13389 3'000 + assign $0\bigendian_i$next[0:0]$1844 $4\bigendian_i$next[0:0]$1848 + attribute \src "libresoc.v:49108.5-49108.29" + switch \initial + attribute \src "libresoc.v:49108.9-49108.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\bigendian_i$next[0:0]$1845 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\bigendian_i$next[0:0]$1845 $2\bigendian_i$next[0:0]$1846 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\bigendian_i$next[0:0]$1846 \bigendian_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\bigendian_i$next[0:0]$1846 \core_bigendian_i + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\bigendian_i$next[0:0]$1845 $3\bigendian_i$next[0:0]$1847 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + switch \$45 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\bigendian_i$next[0:0]$1847 1'0 + case + assign $3\bigendian_i$next[0:0]$1847 \bigendian_i + end + case + assign $1\bigendian_i$next[0:0]$1845 \bigendian_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\bigendian_i$next[0:0]$1848 1'0 + case + assign $4\bigendian_i$next[0:0]$1848 $1\bigendian_i$next[0:0]$1845 + end sync always - sync init - update \ren_delay$11 $0\ren_delay$11[2:0]$13389 + update \bigendian_i$next $0\bigendian_i$next[0:0]$1844 + end + attribute \src "libresoc.v:49144.3-49159.6" + process $proc$libresoc.v:49144$1849 + assign { } { } + assign { } { } + assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] + attribute \src "libresoc.v:49145.5-49145.29" + switch \initial + attribute \src "libresoc.v:49145.9-49145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + switch \$51 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_a_pc_i[47:0] \pc [47:0] + case + assign $2\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + case + assign $1\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + sync always + update \imem_a_pc_i $0\imem_a_pc_i[47:0] end - attribute \src "issuer_ls180.v:180757.13-180757.34" - process $proc$issuer_ls180.v:180757$13390 + attribute \src "libresoc.v:49160.3-49184.6" + process $proc$libresoc.v:49160$1850 assign { } { } - assign $0\ren_delay$18[2:0]$13391 3'000 + assign { } { } + assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] + attribute \src "libresoc.v:49161.5-49161.29" + switch \initial + attribute \src "libresoc.v:49161.9-49161.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + switch \$57 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_a_valid_i[0:0] 1'1 + case + assign $2\imem_a_valid_i[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\imem_a_valid_i[0:0] 1'1 + case + assign $3\imem_a_valid_i[0:0] 1'0 + end + case + assign $1\imem_a_valid_i[0:0] 1'0 + end sync always - sync init - update \ren_delay$18 $0\ren_delay$18[2:0]$13391 + update \imem_a_valid_i $0\imem_a_valid_i[0:0] end - attribute \src "issuer_ls180.v:180792.3-180793.43" - process $proc$issuer_ls180.v:180792$13369 + attribute \src "libresoc.v:49185.3-49209.6" + process $proc$libresoc.v:49185$1851 assign { } { } - assign $0\ren_delay$18[2:0]$13370 \ren_delay$18$next - sync posedge \coresync_clk - update \ren_delay$18 $0\ren_delay$18[2:0]$13370 + assign { } { } + assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] + attribute \src "libresoc.v:49186.5-49186.29" + switch \initial + attribute \src "libresoc.v:49186.9-49186.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + switch \$63 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_f_valid_i[0:0] 1'1 + case + assign $2\imem_f_valid_i[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\imem_f_valid_i[0:0] 1'1 + case + assign $3\imem_f_valid_i[0:0] 1'0 + end + case + assign $1\imem_f_valid_i[0:0] 1'0 + end + sync always + update \imem_f_valid_i $0\imem_f_valid_i[0:0] end - attribute \src "issuer_ls180.v:180794.3-180795.43" - process $proc$issuer_ls180.v:180794$13371 + attribute \src "libresoc.v:49210.3-49230.6" + process $proc$libresoc.v:49210$1852 + assign { } { } + assign { } { } assign { } { } - assign $0\ren_delay$11[2:0]$13372 \ren_delay$11$next - sync posedge \coresync_clk - update \ren_delay$11 $0\ren_delay$11[2:0]$13372 + assign $0\dec2_cur_pc$next[63:0]$1853 $3\dec2_cur_pc$next[63:0]$1856 + attribute \src "libresoc.v:49211.5-49211.29" + switch \initial + attribute \src "libresoc.v:49211.9-49211.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec2_cur_pc$next[63:0]$1854 $2\dec2_cur_pc$next[63:0]$1855 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + switch \$69 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_pc$next[63:0]$1855 \pc + case + assign $2\dec2_cur_pc$next[63:0]$1855 \dec2_cur_pc + end + case + assign $1\dec2_cur_pc$next[63:0]$1854 \dec2_cur_pc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dec2_cur_pc$next[63:0]$1856 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dec2_cur_pc$next[63:0]$1856 $1\dec2_cur_pc$next[63:0]$1854 + end + sync always + update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$1853 end - attribute \src "issuer_ls180.v:180796.3-180797.35" - process $proc$issuer_ls180.v:180796$13373 + attribute \src "libresoc.v:49231.3-49260.6" + process $proc$libresoc.v:49231$1857 + assign { } { } assign { } { } - assign $0\ren_delay[2:0] \ren_delay$next - sync posedge \coresync_clk - update \ren_delay $0\ren_delay[2:0] + assign { } { } + assign $0\msr_read$next[0:0]$1858 $4\msr_read$next[0:0]$1862 + attribute \src "libresoc.v:49232.5-49232.29" + switch \initial + attribute \src "libresoc.v:49232.9-49232.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\msr_read$next[0:0]$1859 $2\msr_read$next[0:0]$1860 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + switch \$75 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr_read$next[0:0]$1860 1'0 + case + assign $2\msr_read$next[0:0]$1860 \msr_read + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\msr_read$next[0:0]$1859 $3\msr_read$next[0:0]$1861 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:255" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr_read$next[0:0]$1861 1'1 + case + assign $3\msr_read$next[0:0]$1861 \msr_read + end + case + assign $1\msr_read$next[0:0]$1859 \msr_read + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr_read$next[0:0]$1862 1'1 + case + assign $4\msr_read$next[0:0]$1862 $1\msr_read$next[0:0]$1859 + end + sync always + update \msr_read$next $0\msr_read$next[0:0]$1858 end - attribute \src "issuer_ls180.v:180858.3-180866.6" - process $proc$issuer_ls180.v:180858$13374 + attribute \src "libresoc.v:49261.3-49306.6" + process $proc$libresoc.v:49261$1863 + assign { } { } assign { } { } assign { } { } - assign $0\ren_delay$18$next[2:0]$13375 $1\ren_delay$18$next[2:0]$13376 - attribute \src "issuer_ls180.v:180859.5-180859.29" + assign $0\fsm_state$next[1:0]$1864 $5\fsm_state$next[1:0]$1869 + attribute \src "libresoc.v:49262.5-49262.29" switch \initial - attribute \src "issuer_ls180.v:180859.9-180859.17" + attribute \src "libresoc.v:49262.9-49262.17" case 1'1 case end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fsm_state$next[1:0]$1865 $2\fsm_state$next[1:0]$1866 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + switch \$83 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$next[1:0]$1866 2'01 + case + assign $2\fsm_state$next[1:0]$1866 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fsm_state$next[1:0]$1865 $3\fsm_state$next[1:0]$1867 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\fsm_state$next[1:0]$1867 \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\fsm_state$next[1:0]$1867 2'10 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fsm_state$next[1:0]$1865 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\fsm_state$next[1:0]$1865 $4\fsm_state$next[1:0]$1868 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[1:0]$1868 2'00 + case + assign $4\fsm_state$next[1:0]$1868 \fsm_state + end + case + assign $1\fsm_state$next[1:0]$1865 \fsm_state + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$18$next[2:0]$13376 3'000 + assign $5\fsm_state$next[1:0]$1869 2'00 case - assign $1\ren_delay$18$next[2:0]$13376 \src3__ren + assign $5\fsm_state$next[1:0]$1869 $1\fsm_state$next[1:0]$1865 end sync always - update \ren_delay$18$next $0\ren_delay$18$next[2:0]$13375 + update \fsm_state$next $0\fsm_state$next[1:0]$1864 end - attribute \src "issuer_ls180.v:180867.3-180876.6" - process $proc$issuer_ls180.v:180867$13377 + attribute \src "libresoc.v:49307.3-49316.6" + process $proc$libresoc.v:49307$1870 assign { } { } assign { } { } - assign $0\src3__data_o[1:0] $1\src3__data_o[1:0] - attribute \src "issuer_ls180.v:180868.5-180868.29" + assign $0\delay$next[1:0]$1871 $1\delay$next[1:0]$1872 + attribute \src "libresoc.v:49308.5-49308.29" switch \initial - attribute \src "issuer_ls180.v:180868.9-180868.17" + attribute \src "libresoc.v:49308.9-49308.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch \$19 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:156" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\delay$next[1:0]$1872 \$5 [1:0] + case + assign $1\delay$next[1:0]$1872 \delay + end + sync always + update \delay$next $0\delay$next[1:0]$1871 + end + attribute \src "libresoc.v:49317.3-49335.6" + process $proc$libresoc.v:49317$1873 + assign { } { } + assign { } { } + assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] + attribute \src "libresoc.v:49318.5-49318.29" + switch \initial + attribute \src "libresoc.v:49318.9-49318.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + switch \$91 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\core_stopped_i[0:0] 1'1 + end + case + assign $1\core_stopped_i[0:0] 1'0 + end + sync always + update \core_stopped_i $0\core_stopped_i[0:0] + end + attribute \src "libresoc.v:49336.3-49354.6" + process $proc$libresoc.v:49336$1874 + assign { } { } + assign { } { } + assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:49337.5-49337.29" + switch \initial + attribute \src "libresoc.v:49337.9-49337.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 assign { } { } - assign $1\src3__data_o[1:0] \$23 + assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + switch \$97 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\dbg_core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbg_core_stopped_i[0:0] 1'1 + end case - assign $1\src3__data_o[1:0] 2'00 + assign $1\dbg_core_stopped_i[0:0] 1'0 end sync always - update \src3__data_o $0\src3__data_o[1:0] + update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] end - attribute \src "issuer_ls180.v:180877.3-180885.6" - process $proc$issuer_ls180.v:180877$13378 + attribute \src "libresoc.v:49355.3-49375.6" + process $proc$libresoc.v:49355$1875 assign { } { } assign { } { } - assign $0\ren_delay$next[2:0]$13379 $1\ren_delay$next[2:0]$13380 - attribute \src "issuer_ls180.v:180878.5-180878.29" + assign { } { } + assign $0\dec2_cur_msr$next[63:0]$1876 $3\dec2_cur_msr$next[63:0]$1879 + attribute \src "libresoc.v:49356.5-49356.29" switch \initial - attribute \src "issuer_ls180.v:180878.9-180878.17" + attribute \src "libresoc.v:49356.9-49356.17" case 1'1 case end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_cur_msr$next[63:0]$1877 $2\dec2_cur_msr$next[63:0]$1878 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:255" + switch \$99 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_msr$next[63:0]$1878 \msr__data_o + case + assign $2\dec2_cur_msr$next[63:0]$1878 \dec2_cur_msr + end + case + assign $1\dec2_cur_msr$next[63:0]$1877 \dec2_cur_msr + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[2:0]$13380 3'000 + assign $3\dec2_cur_msr$next[63:0]$1879 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\ren_delay$next[2:0]$13380 \src1__ren + assign $3\dec2_cur_msr$next[63:0]$1879 $1\dec2_cur_msr$next[63:0]$1877 end sync always - update \ren_delay$next $0\ren_delay$next[2:0]$13379 + update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$1876 end - attribute \src "issuer_ls180.v:180886.3-180895.6" - process $proc$issuer_ls180.v:180886$13381 + attribute \src "libresoc.v:49376.3-49394.6" + process $proc$libresoc.v:49376$1880 assign { } { } assign { } { } - assign $0\src1__data_o[1:0] $1\src1__data_o[1:0] - attribute \src "issuer_ls180.v:180887.5-180887.29" + assign $0\dec2_raw_opcode_in[31:0] $1\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:49377.5-49377.29" switch \initial - attribute \src "issuer_ls180.v:180887.9-180887.17" + attribute \src "libresoc.v:49377.9-49377.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch \$5 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_raw_opcode_in[31:0] $2\dec2_raw_opcode_in[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\dec2_raw_opcode_in[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dec2_raw_opcode_in[31:0] \$101 + end + case + assign $1\dec2_raw_opcode_in[31:0] 0 + end + sync always + update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] + end + attribute \src "libresoc.v:49395.3-49426.6" + process $proc$libresoc.v:49395$1881 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_dec$next[63:0]$1882 $3\core_dec$next[63:0]$1894 + assign $0\core_eint$next[0:0]$1883 $3\core_eint$next[0:0]$1895 + assign $0\core_msr$next[63:0]$1884 $3\core_msr$next[63:0]$1896 + assign $0\core_pc$next[63:0]$1885 $3\core_pc$next[63:0]$1897 + attribute \src "libresoc.v:49396.5-49396.29" + switch \initial + attribute \src "libresoc.v:49396.9-49396.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_dec$next[63:0]$1886 $2\core_dec$next[63:0]$1890 + assign $1\core_eint$next[0:0]$1887 $2\core_eint$next[0:0]$1891 + assign $1\core_msr$next[63:0]$1888 $2\core_msr$next[63:0]$1892 + assign $1\core_pc$next[63:0]$1889 $2\core_pc$next[63:0]$1893 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_dec$next[63:0]$1890 \core_dec + assign $2\core_eint$next[0:0]$1891 \core_eint + assign $2\core_msr$next[63:0]$1892 \core_msr + assign $2\core_pc$next[63:0]$1893 \core_pc + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\core_dec$next[63:0]$1890 $2\core_eint$next[0:0]$1891 $2\core_msr$next[63:0]$1892 $2\core_pc$next[63:0]$1893 } { \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + end + case + assign $1\core_dec$next[63:0]$1886 \core_dec + assign $1\core_eint$next[0:0]$1887 \core_eint + assign $1\core_msr$next[63:0]$1888 \core_msr + assign $1\core_pc$next[63:0]$1889 \core_pc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src1__data_o[1:0] \$9 + assign { } { } + assign { } { } + assign { } { } + assign $3\core_pc$next[63:0]$1897 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_msr$next[63:0]$1896 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_eint$next[0:0]$1895 1'0 + assign $3\core_dec$next[63:0]$1894 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\src1__data_o[1:0] 2'00 + assign $3\core_dec$next[63:0]$1894 $1\core_dec$next[63:0]$1886 + assign $3\core_eint$next[0:0]$1895 $1\core_eint$next[0:0]$1887 + assign $3\core_msr$next[63:0]$1896 $1\core_msr$next[63:0]$1888 + assign $3\core_pc$next[63:0]$1897 $1\core_pc$next[63:0]$1889 end sync always - update \src1__data_o $0\src1__data_o[1:0] + update \core_dec$next $0\core_dec$next[63:0]$1882 + update \core_eint$next $0\core_eint$next[0:0]$1883 + update \core_msr$next $0\core_msr$next[63:0]$1884 + update \core_pc$next $0\core_pc$next[63:0]$1885 end - attribute \src "issuer_ls180.v:180896.3-180904.6" - process $proc$issuer_ls180.v:180896$13382 + attribute \src "libresoc.v:49427.3-49450.6" + process $proc$libresoc.v:49427$1898 + assign { } { } assign { } { } assign { } { } - assign $0\ren_delay$11$next[2:0]$13383 $1\ren_delay$11$next[2:0]$13384 - attribute \src "issuer_ls180.v:180897.5-180897.29" + assign $0\ilatch$next[31:0]$1899 $3\ilatch$next[31:0]$1902 + attribute \src "libresoc.v:49428.5-49428.29" switch \initial - attribute \src "issuer_ls180.v:180897.9-180897.17" + attribute \src "libresoc.v:49428.9-49428.17" case 1'1 case end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\ilatch$next[31:0]$1900 $2\ilatch$next[31:0]$1901 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\ilatch$next[31:0]$1901 \ilatch + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\ilatch$next[31:0]$1901 \$105 + end + case + assign $1\ilatch$next[31:0]$1900 \ilatch + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "issuer_ls180.v:0.0-0.0" + switch \rst + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$11$next[2:0]$13384 3'000 + assign $3\ilatch$next[31:0]$1902 0 case - assign $1\ren_delay$11$next[2:0]$13384 \src2__ren + assign $3\ilatch$next[31:0]$1902 $1\ilatch$next[31:0]$1900 end sync always - update \ren_delay$11$next $0\ren_delay$11$next[2:0]$13383 + update \ilatch$next $0\ilatch$next[31:0]$1899 end - attribute \src "issuer_ls180.v:180905.3-180914.6" - process $proc$issuer_ls180.v:180905$13385 + attribute \src "libresoc.v:49451.3-49470.6" + process $proc$libresoc.v:49451$1903 assign { } { } assign { } { } - assign $0\src2__data_o[1:0] $1\src2__data_o[1:0] - attribute \src "issuer_ls180.v:180906.5-180906.29" + assign $0\ivalid_i[0:0] $1\ivalid_i[0:0] + attribute \src "libresoc.v:49452.5-49452.29" switch \initial - attribute \src "issuer_ls180.v:180906.9-180906.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch \$12 - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src2__data_o[1:0] \$16 - case - assign $1\src2__data_o[1:0] 2'00 - end - sync always - update \src2__data_o $0\src2__data_o[1:0] - end - connect \$9 $or$issuer_ls180.v:180783$13360_Y - connect \$12 $reduce_or$issuer_ls180.v:180784$13361_Y - connect \$14 $or$issuer_ls180.v:180785$13362_Y - connect \$16 $or$issuer_ls180.v:180786$13363_Y - connect \$19 $reduce_or$issuer_ls180.v:180787$13364_Y - connect \$21 $or$issuer_ls180.v:180788$13365_Y - connect \$23 $or$issuer_ls180.v:180789$13366_Y - connect \$5 $reduce_or$issuer_ls180.v:180790$13367_Y - connect \$7 $or$issuer_ls180.v:180791$13368_Y - connect \full_wr__data_i 6'000000 - connect \full_wr__wen 3'000 - connect { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } 3'000 - connect { \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } 6'000000 - connect { \reg_2_r2__ren \reg_1_r1__ren \reg_0_r0__ren } \full_rd__ren - connect \full_rd__data_o { \reg_2_r2__data_o \reg_1_r1__data_o \reg_0_r0__data_o } - connect \reg_2_dest32__data_i \data_i$1 - connect \reg_1_dest31__data_i \data_i$1 - connect \reg_0_dest30__data_i \data_i$1 - connect { \reg_2_dest32__wen \reg_1_dest31__wen \reg_0_dest30__wen } \wen$2 - connect \reg_2_dest22__data_i \data_i - connect \reg_1_dest21__data_i \data_i - connect \reg_0_dest20__data_i \data_i - connect { \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } \wen - connect \reg_2_dest12__data_i \data_i$3 - connect \reg_1_dest11__data_i \data_i$3 - connect \reg_0_dest10__data_i \data_i$3 - connect { \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen$4 - connect { \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren - connect { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren - connect { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren + attribute \src "libresoc.v:49452.9-49452.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\ivalid_i[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\ivalid_i[0:0] $2\ivalid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \$109 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ivalid_i[0:0] 1'1 + case + assign $2\ivalid_i[0:0] 1'0 + end + case + assign $1\ivalid_i[0:0] 1'0 + end + sync always + update \ivalid_i $0\ivalid_i[0:0] + end + connect \$99 $not$libresoc.v:48036$1403_Y + connect \$102 $mul$libresoc.v:48037$1404_Y + connect \$101 $shr$libresoc.v:48038$1405_Y [31:0] + connect \$106 $mul$libresoc.v:48039$1406_Y + connect \$105 $shr$libresoc.v:48040$1407_Y [31:0] + connect \$10 $ne$libresoc.v:48041$1408_Y + connect \$109 $ne$libresoc.v:48042$1409_Y + connect \$111 $pos$libresoc.v:48043$1411_Y + connect \$113 $pos$libresoc.v:48044$1413_Y + connect \$117 $sub$libresoc.v:48045$1414_Y + connect \$121 $add$libresoc.v:48046$1415_Y + connect \$12 $not$libresoc.v:48047$1416_Y + connect \$14 $and$libresoc.v:48048$1417_Y + connect \$17 $add$libresoc.v:48049$1418_Y + connect \$19 $not$libresoc.v:48050$1419_Y + connect \$21 $not$libresoc.v:48051$1420_Y + connect \$23 $not$libresoc.v:48052$1421_Y + connect \$25 $not$libresoc.v:48053$1422_Y + connect \$27 $not$libresoc.v:48054$1423_Y + connect \$29 $not$libresoc.v:48055$1424_Y + connect \$31 $not$libresoc.v:48056$1425_Y + connect \$33 $and$libresoc.v:48057$1426_Y + connect \$36 $and$libresoc.v:48058$1427_Y + connect \$35 $reduce_or$libresoc.v:48059$1428_Y + connect \$3 $ne$libresoc.v:48060$1429_Y + connect \$41 $not$libresoc.v:48061$1430_Y + connect \$43 $not$libresoc.v:48062$1431_Y + connect \$45 $not$libresoc.v:48063$1432_Y + connect \$47 $not$libresoc.v:48064$1433_Y + connect \$49 $not$libresoc.v:48065$1434_Y + connect \$51 $and$libresoc.v:48066$1435_Y + connect \$53 $not$libresoc.v:48067$1436_Y + connect \$55 $not$libresoc.v:48068$1437_Y + connect \$57 $and$libresoc.v:48069$1438_Y + connect \$59 $not$libresoc.v:48070$1439_Y + connect \$61 $not$libresoc.v:48071$1440_Y + connect \$63 $and$libresoc.v:48072$1441_Y + connect \$65 $not$libresoc.v:48073$1442_Y + connect \$67 $not$libresoc.v:48074$1443_Y + connect \$6 $sub$libresoc.v:48075$1444_Y + connect \$69 $and$libresoc.v:48076$1445_Y + connect \$71 $not$libresoc.v:48077$1446_Y + connect \$73 $not$libresoc.v:48078$1447_Y + connect \$75 $and$libresoc.v:48079$1448_Y + connect \$77 $not$libresoc.v:48080$1449_Y + connect \$79 $not$libresoc.v:48081$1450_Y + connect \$81 $not$libresoc.v:48082$1451_Y + connect \$83 $and$libresoc.v:48083$1452_Y + connect \$85 $not$libresoc.v:48084$1453_Y + connect \$87 $not$libresoc.v:48085$1454_Y + connect \$8 $or$libresoc.v:48086$1455_Y + connect \$89 $not$libresoc.v:48087$1456_Y + connect \$91 $and$libresoc.v:48088$1457_Y + connect \$93 $not$libresoc.v:48089$1458_Y + connect \$95 $not$libresoc.v:48090$1459_Y + connect \$97 $and$libresoc.v:48091$1460_Y + connect \$5 \$6 + connect \$16 \$17 + connect \$116 \$117 + connect \$120 \$121 + connect \corebusy_o 1'0 + connect \cu_st__rel_o 1'0 + connect \cu_ad__rel_o 1'0 + connect \cia__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \core_terminate_o 1'0 + connect \state_nia_wen 4'0000 + connect \msr__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \dmi__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \full_rd2__data_o 0 + connect \full_rd__data_o 6'000000 + connect \issue__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \dbg_core_dbg_msr \dec2_cur_msr + connect \dbg_core_dbg_pc \pc + connect \dbg_terminate_i 1'0 + connect \nia \$17 [63:0] + connect \pc_o \dec2_cur_pc + connect \cu_st__go_i \cu_st__rel_o_rise + connect \cu_ad__go_i 1'0 + connect \cu_st__rel_o_rise \$14 + connect \cu_st__rel_o_dly$next 1'0 + connect \dec2_bigendian \core_bigendian_i + connect \busy_o 1'0 + connect \core_reset_i \$10 + connect \coresync_clk \clk + connect \por_clk \clk + connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src } end -attribute \src "issuer_ls180.v:180940.1-181254.10" +attribute \src "libresoc.v:49505.1-49819.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.xics_icp" attribute \generator "nMigen" module \xics_icp - attribute \src "issuer_ls180.v:181118.3-181146.6" + attribute \src "libresoc.v:49683.3-49711.6" wire width 32 $0\be_out[31:0] - attribute \src "issuer_ls180.v:181169.3-181177.6" - wire $0\core_irq_o$next[0:0]$13427 - attribute \src "issuer_ls180.v:181062.3-181063.37" + attribute \src "libresoc.v:49734.3-49742.6" + wire $0\core_irq_o$next[0:0]$2021 + attribute \src "libresoc.v:49625.3-49626.37" wire $0\core_irq_o[0:0] - attribute \src "issuer_ls180.v:181188.3-181250.6" - wire width 8 $0\cppr$10[7:0]$13431 - attribute \src "issuer_ls180.v:181074.3-181089.6" - wire width 8 $0\cppr$next[7:0]$13410 - attribute \src "issuer_ls180.v:181066.3-181067.25" + attribute \src "libresoc.v:49753.3-49815.6" + wire width 8 $0\cppr$10[7:0]$2025 + attribute \src "libresoc.v:49639.3-49654.6" + wire width 8 $0\cppr$next[7:0]$2004 + attribute \src "libresoc.v:49629.3-49630.25" wire width 8 $0\cppr[7:0] - attribute \src "issuer_ls180.v:181178.3-181187.6" + attribute \src "libresoc.v:49743.3-49752.6" wire width 32 $0\icp_wb__dat_r[31:0] - attribute \src "issuer_ls180.v:180941.7-180941.20" + attribute \src "libresoc.v:49506.7-49506.20" wire $0\initial[0:0] - attribute \src "issuer_ls180.v:181188.3-181250.6" - wire $0\irq$12[0:0]$13432 - attribute \src "issuer_ls180.v:181074.3-181089.6" - wire $0\irq$next[0:0]$13411 - attribute \src "issuer_ls180.v:181070.3-181071.23" + attribute \src "libresoc.v:49753.3-49815.6" + wire $0\irq$12[0:0]$2026 + attribute \src "libresoc.v:49639.3-49654.6" + wire $0\irq$next[0:0]$2005 + attribute \src "libresoc.v:49633.3-49634.23" wire $0\irq[0:0] - attribute \src "issuer_ls180.v:181188.3-181250.6" - wire width 8 $0\mfrr$11[7:0]$13433 - attribute \src "issuer_ls180.v:181074.3-181089.6" - wire width 8 $0\mfrr$next[7:0]$13412 - attribute \src "issuer_ls180.v:181068.3-181069.25" + attribute \src "libresoc.v:49753.3-49815.6" + wire width 8 $0\mfrr$11[7:0]$2027 + attribute \src "libresoc.v:49639.3-49654.6" + wire width 8 $0\mfrr$next[7:0]$2006 + attribute \src "libresoc.v:49631.3-49632.25" wire width 8 $0\mfrr[7:0] - attribute \src "issuer_ls180.v:181157.3-181168.6" + attribute \src "libresoc.v:49722.3-49733.6" wire width 8 $0\min_pri[7:0] - attribute \src "issuer_ls180.v:181147.3-181156.6" + attribute \src "libresoc.v:49712.3-49721.6" wire width 8 $0\pending_priority[7:0] - attribute \src "issuer_ls180.v:181188.3-181250.6" - wire $0\wb_ack$14[0:0]$13434 - attribute \src "issuer_ls180.v:181074.3-181089.6" - wire $0\wb_ack$next[0:0]$13413 - attribute \src "issuer_ls180.v:181060.3-181061.29" + attribute \src "libresoc.v:49753.3-49815.6" + wire $0\wb_ack$14[0:0]$2028 + attribute \src "libresoc.v:49639.3-49654.6" + wire $0\wb_ack$next[0:0]$2007 + attribute \src "libresoc.v:49637.3-49638.29" wire $0\wb_ack[0:0] - attribute \src "issuer_ls180.v:181188.3-181250.6" - wire width 32 $0\wb_rd_data$13[31:0]$13435 - attribute \src "issuer_ls180.v:181074.3-181089.6" - wire width 32 $0\wb_rd_data$next[31:0]$13414 - attribute \src "issuer_ls180.v:181072.3-181073.37" + attribute \src "libresoc.v:49753.3-49815.6" + wire width 32 $0\wb_rd_data$13[31:0]$2029 + attribute \src "libresoc.v:49639.3-49654.6" + wire width 32 $0\wb_rd_data$next[31:0]$2008 + attribute \src "libresoc.v:49635.3-49636.37" wire width 32 $0\wb_rd_data[31:0] - attribute \src "issuer_ls180.v:181090.3-181117.6" + attribute \src "libresoc.v:49655.3-49682.6" wire $0\xirr_accept_rd[0:0] - attribute \src "issuer_ls180.v:181188.3-181250.6" - wire width 24 $0\xisr$9[23:0]$13436 - attribute \src "issuer_ls180.v:181074.3-181089.6" - wire width 24 $0\xisr$next[23:0]$13415 - attribute \src "issuer_ls180.v:181064.3-181065.25" + attribute \src "libresoc.v:49753.3-49815.6" + wire width 24 $0\xisr$9[23:0]$2030 + attribute \src "libresoc.v:49639.3-49654.6" + wire width 24 $0\xisr$next[23:0]$2009 + attribute \src "libresoc.v:49627.3-49628.25" wire width 24 $0\xisr[23:0] - attribute \src "issuer_ls180.v:181118.3-181146.6" + attribute \src "libresoc.v:49683.3-49711.6" wire width 32 $1\be_out[31:0] - attribute \src "issuer_ls180.v:181169.3-181177.6" - wire $1\core_irq_o$next[0:0]$13428 - attribute \src "issuer_ls180.v:180970.7-180970.24" + attribute \src "libresoc.v:49734.3-49742.6" + wire $1\core_irq_o$next[0:0]$2022 + attribute \src "libresoc.v:49535.7-49535.24" wire $1\core_irq_o[0:0] - attribute \src "issuer_ls180.v:181188.3-181250.6" - wire width 8 $1\cppr$10[7:0]$13437 - attribute \src "issuer_ls180.v:181074.3-181089.6" - wire width 8 $1\cppr$next[7:0]$13416 - attribute \src "issuer_ls180.v:180974.13-180974.25" + attribute \src "libresoc.v:49753.3-49815.6" + wire width 8 $1\cppr$10[7:0]$2031 + attribute \src "libresoc.v:49639.3-49654.6" + wire width 8 $1\cppr$next[7:0]$2010 + attribute \src "libresoc.v:49539.13-49539.25" wire width 8 $1\cppr[7:0] - attribute \src "issuer_ls180.v:181178.3-181187.6" + attribute \src "libresoc.v:49743.3-49752.6" wire width 32 $1\icp_wb__dat_r[31:0] - attribute \src "issuer_ls180.v:181188.3-181250.6" - wire $1\irq$12[0:0]$13447 - attribute \src "issuer_ls180.v:181074.3-181089.6" - wire $1\irq$next[0:0]$13417 - attribute \src "issuer_ls180.v:181003.7-181003.17" + attribute \src "libresoc.v:49753.3-49815.6" + wire $1\irq$12[0:0]$2041 + attribute \src "libresoc.v:49639.3-49654.6" + wire $1\irq$next[0:0]$2011 + attribute \src "libresoc.v:49568.7-49568.17" wire $1\irq[0:0] - attribute \src "issuer_ls180.v:181188.3-181250.6" - wire width 8 $1\mfrr$11[7:0]$13438 - attribute \src "issuer_ls180.v:181074.3-181089.6" - wire width 8 $1\mfrr$next[7:0]$13418 - attribute \src "issuer_ls180.v:181011.13-181011.25" + attribute \src "libresoc.v:49753.3-49815.6" + wire width 8 $1\mfrr$11[7:0]$2032 + attribute \src "libresoc.v:49639.3-49654.6" + wire width 8 $1\mfrr$next[7:0]$2012 + attribute \src "libresoc.v:49576.13-49576.25" wire width 8 $1\mfrr[7:0] - attribute \src "issuer_ls180.v:181157.3-181168.6" + attribute \src "libresoc.v:49722.3-49733.6" wire width 8 $1\min_pri[7:0] - attribute \src "issuer_ls180.v:181147.3-181156.6" + attribute \src "libresoc.v:49712.3-49721.6" wire width 8 $1\pending_priority[7:0] - attribute \src "issuer_ls180.v:181188.3-181250.6" - wire $1\wb_ack$14[0:0]$13439 - attribute \src "issuer_ls180.v:181074.3-181089.6" - wire $1\wb_ack$next[0:0]$13419 - attribute \src "issuer_ls180.v:181025.7-181025.20" + attribute \src "libresoc.v:49753.3-49815.6" + wire $1\wb_ack$14[0:0]$2033 + attribute \src "libresoc.v:49639.3-49654.6" + wire $1\wb_ack$next[0:0]$2013 + attribute \src "libresoc.v:49590.7-49590.20" wire $1\wb_ack[0:0] - attribute \src "issuer_ls180.v:181074.3-181089.6" - wire width 32 $1\wb_rd_data$next[31:0]$13420 - attribute \src "issuer_ls180.v:181033.14-181033.32" + attribute \src "libresoc.v:49639.3-49654.6" + wire width 32 $1\wb_rd_data$next[31:0]$2014 + attribute \src "libresoc.v:49598.14-49598.32" wire width 32 $1\wb_rd_data[31:0] - attribute \src "issuer_ls180.v:181090.3-181117.6" + attribute \src "libresoc.v:49655.3-49682.6" wire $1\xirr_accept_rd[0:0] - attribute \src "issuer_ls180.v:181188.3-181250.6" - wire width 24 $1\xisr$9[23:0]$13444 - attribute \src "issuer_ls180.v:181074.3-181089.6" - wire width 24 $1\xisr$next[23:0]$13421 - attribute \src "issuer_ls180.v:181043.14-181043.31" + attribute \src "libresoc.v:49753.3-49815.6" + wire width 24 $1\xisr$9[23:0]$2038 + attribute \src "libresoc.v:49639.3-49654.6" + wire width 24 $1\xisr$next[23:0]$2015 + attribute \src "libresoc.v:49608.14-49608.31" wire width 24 $1\xisr[23:0] - attribute \src "issuer_ls180.v:181118.3-181146.6" + attribute \src "libresoc.v:49683.3-49711.6" wire width 32 $2\be_out[31:0] - attribute \src "issuer_ls180.v:181188.3-181250.6" - wire width 8 $2\cppr$10[7:0]$13440 - attribute \src "issuer_ls180.v:181188.3-181250.6" - wire width 8 $2\mfrr$11[7:0]$13441 - attribute \src "issuer_ls180.v:181090.3-181117.6" + attribute \src "libresoc.v:49753.3-49815.6" + wire width 8 $2\cppr$10[7:0]$2034 + attribute \src "libresoc.v:49753.3-49815.6" + wire width 8 $2\mfrr$11[7:0]$2035 + attribute \src "libresoc.v:49655.3-49682.6" wire $2\xirr_accept_rd[0:0] - attribute \src "issuer_ls180.v:181188.3-181250.6" - wire width 24 $2\xisr$9[23:0]$13445 - attribute \src "issuer_ls180.v:181118.3-181146.6" + attribute \src "libresoc.v:49753.3-49815.6" + wire width 24 $2\xisr$9[23:0]$2039 + attribute \src "libresoc.v:49683.3-49711.6" wire width 32 $3\be_out[31:0] - attribute \src "issuer_ls180.v:181188.3-181250.6" - wire width 8 $3\cppr$10[7:0]$13442 - attribute \src "issuer_ls180.v:181188.3-181250.6" - wire width 8 $3\mfrr$11[7:0]$13443 - attribute \src "issuer_ls180.v:181090.3-181117.6" + attribute \src "libresoc.v:49753.3-49815.6" + wire width 8 $3\cppr$10[7:0]$2036 + attribute \src "libresoc.v:49753.3-49815.6" + wire width 8 $3\mfrr$11[7:0]$2037 + attribute \src "libresoc.v:49655.3-49682.6" wire $3\xirr_accept_rd[0:0] - attribute \src "issuer_ls180.v:181188.3-181250.6" - wire width 8 $4\cppr$10[7:0]$13446 - attribute \src "issuer_ls180.v:181090.3-181117.6" + attribute \src "libresoc.v:49753.3-49815.6" + wire width 8 $4\cppr$10[7:0]$2040 + attribute \src "libresoc.v:49655.3-49682.6" wire $4\xirr_accept_rd[0:0] - attribute \src "issuer_ls180.v:181050.18-181050.116" - wire $and$issuer_ls180.v:181050$13392_Y - attribute \src "issuer_ls180.v:181054.18-181054.116" - wire $and$issuer_ls180.v:181054$13396_Y - attribute \src "issuer_ls180.v:181056.18-181056.116" - wire $and$issuer_ls180.v:181056$13398_Y - attribute \src "issuer_ls180.v:181059.17-181059.109" - wire $and$issuer_ls180.v:181059$13401_Y - attribute \src "issuer_ls180.v:181055.18-181055.110" - wire $eq$issuer_ls180.v:181055$13397_Y - attribute \src "issuer_ls180.v:181052.18-181052.114" - wire $lt$issuer_ls180.v:181052$13394_Y - attribute \src "issuer_ls180.v:181053.18-181053.109" - wire $lt$issuer_ls180.v:181053$13395_Y - attribute \src "issuer_ls180.v:181058.18-181058.114" - wire $lt$issuer_ls180.v:181058$13400_Y - attribute \src "issuer_ls180.v:181051.18-181051.109" - wire $ne$issuer_ls180.v:181051$13393_Y - attribute \src "issuer_ls180.v:181057.18-181057.109" - wire $ne$issuer_ls180.v:181057$13399_Y + attribute \src "libresoc.v:49615.18-49615.116" + wire $and$libresoc.v:49615$1986_Y + attribute \src "libresoc.v:49619.18-49619.116" + wire $and$libresoc.v:49619$1990_Y + attribute \src "libresoc.v:49621.18-49621.116" + wire $and$libresoc.v:49621$1992_Y + attribute \src "libresoc.v:49624.17-49624.109" + wire $and$libresoc.v:49624$1995_Y + attribute \src "libresoc.v:49620.18-49620.110" + wire $eq$libresoc.v:49620$1991_Y + attribute \src "libresoc.v:49617.18-49617.114" + wire $lt$libresoc.v:49617$1988_Y + attribute \src "libresoc.v:49618.18-49618.109" + wire $lt$libresoc.v:49618$1989_Y + attribute \src "libresoc.v:49623.18-49623.114" + wire $lt$libresoc.v:49623$1994_Y + attribute \src "libresoc.v:49616.18-49616.109" + wire $ne$libresoc.v:49616$1987_Y + attribute \src "libresoc.v:49622.18-49622.109" + wire $ne$libresoc.v:49622$1993_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" wire \$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" @@ -376701,7 +140353,7 @@ module \xics_icp wire width 32 \be_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" wire width 32 \be_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" wire input 3 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" wire output 2 \core_irq_o @@ -376735,7 +140387,7 @@ module \xics_icp wire width 8 input 1 \ics_i_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 input 13 \ics_i_src - attribute \src "issuer_ls180.v:180941.7-180941.15" + attribute \src "libresoc.v:49506.7-49506.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" wire \irq @@ -376757,7 +140409,7 @@ module \xics_icp wire width 8 \min_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" wire width 8 \pending_priority - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" wire input 4 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" wire \wb_ack @@ -376786,7 +140438,7 @@ module \xics_icp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" wire width 24 \xisr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$issuer_ls180.v:181050$13392 + cell $and $and$libresoc.v:49615$1986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376794,10 +140446,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$issuer_ls180.v:181050$13392_Y + connect \Y $and$libresoc.v:49615$1986_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$issuer_ls180.v:181054$13396 + cell $and $and$libresoc.v:49619$1990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376805,10 +140457,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$issuer_ls180.v:181054$13396_Y + connect \Y $and$libresoc.v:49619$1990_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$issuer_ls180.v:181056$13398 + cell $and $and$libresoc.v:49621$1992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376816,10 +140468,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$issuer_ls180.v:181056$13398_Y + connect \Y $and$libresoc.v:49621$1992_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" - cell $and $and$issuer_ls180.v:181059$13401 + cell $and $and$libresoc.v:49624$1995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376827,10 +140479,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \wb_ack connect \B \icp_wb__cyc - connect \Y $and$issuer_ls180.v:181059$13401_Y + connect \Y $and$libresoc.v:49624$1995_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" - cell $eq $eq$issuer_ls180.v:181055$13397 + cell $eq $eq$libresoc.v:49620$1991 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -376838,10 +140490,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__sel connect \B 4'1111 - connect \Y $eq$issuer_ls180.v:181055$13397_Y + connect \Y $eq$libresoc.v:49620$1991_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$issuer_ls180.v:181052$13394 + cell $lt $lt$libresoc.v:49617$1988 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -376849,10 +140501,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$issuer_ls180.v:181052$13394_Y + connect \Y $lt$libresoc.v:49617$1988_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" - cell $lt $lt$issuer_ls180.v:181053$13395 + cell $lt $lt$libresoc.v:49618$1989 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -376860,10 +140512,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \min_pri connect \B \cppr$10 - connect \Y $lt$issuer_ls180.v:181053$13395_Y + connect \Y $lt$libresoc.v:49618$1989_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$issuer_ls180.v:181058$13400 + cell $lt $lt$libresoc.v:49623$1994 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -376871,10 +140523,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$issuer_ls180.v:181058$13400_Y + connect \Y $lt$libresoc.v:49623$1994_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$issuer_ls180.v:181051$13393 + cell $ne $ne$libresoc.v:49616$1987 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -376882,10 +140534,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$issuer_ls180.v:181051$13393_Y + connect \Y $ne$libresoc.v:49616$1987_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$issuer_ls180.v:181057$13399 + cell $ne $ne$libresoc.v:49622$1993 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -376893,123 +140545,123 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$issuer_ls180.v:181057$13399_Y + connect \Y $ne$libresoc.v:49622$1993_Y end - attribute \src "issuer_ls180.v:180941.7-180941.20" - process $proc$issuer_ls180.v:180941$13448 + attribute \src "libresoc.v:49506.7-49506.20" + process $proc$libresoc.v:49506$2042 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "issuer_ls180.v:180970.7-180970.24" - process $proc$issuer_ls180.v:180970$13449 + attribute \src "libresoc.v:49535.7-49535.24" + process $proc$libresoc.v:49535$2043 assign { } { } assign $1\core_irq_o[0:0] 1'0 sync always sync init update \core_irq_o $1\core_irq_o[0:0] end - attribute \src "issuer_ls180.v:180974.13-180974.25" - process $proc$issuer_ls180.v:180974$13450 + attribute \src "libresoc.v:49539.13-49539.25" + process $proc$libresoc.v:49539$2044 assign { } { } assign $1\cppr[7:0] 8'00000000 sync always sync init update \cppr $1\cppr[7:0] end - attribute \src "issuer_ls180.v:181003.7-181003.17" - process $proc$issuer_ls180.v:181003$13451 + attribute \src "libresoc.v:49568.7-49568.17" + process $proc$libresoc.v:49568$2045 assign { } { } assign $1\irq[0:0] 1'0 sync always sync init update \irq $1\irq[0:0] end - attribute \src "issuer_ls180.v:181011.13-181011.25" - process $proc$issuer_ls180.v:181011$13452 + attribute \src "libresoc.v:49576.13-49576.25" + process $proc$libresoc.v:49576$2046 assign { } { } assign $1\mfrr[7:0] 8'11111111 sync always sync init update \mfrr $1\mfrr[7:0] end - attribute \src "issuer_ls180.v:181025.7-181025.20" - process $proc$issuer_ls180.v:181025$13453 + attribute \src "libresoc.v:49590.7-49590.20" + process $proc$libresoc.v:49590$2047 assign { } { } assign $1\wb_ack[0:0] 1'0 sync always sync init update \wb_ack $1\wb_ack[0:0] end - attribute \src "issuer_ls180.v:181033.14-181033.32" - process $proc$issuer_ls180.v:181033$13454 + attribute \src "libresoc.v:49598.14-49598.32" + process $proc$libresoc.v:49598$2048 assign { } { } assign $1\wb_rd_data[31:0] 0 sync always sync init update \wb_rd_data $1\wb_rd_data[31:0] end - attribute \src "issuer_ls180.v:181043.14-181043.31" - process $proc$issuer_ls180.v:181043$13455 + attribute \src "libresoc.v:49608.14-49608.31" + process $proc$libresoc.v:49608$2049 assign { } { } assign $1\xisr[23:0] 24'000000000000000000000000 sync always sync init update \xisr $1\xisr[23:0] end - attribute \src "issuer_ls180.v:181060.3-181061.29" - process $proc$issuer_ls180.v:181060$13402 - assign { } { } - assign $0\wb_ack[0:0] \wb_ack$next - sync posedge \clk - update \wb_ack $0\wb_ack[0:0] - end - attribute \src "issuer_ls180.v:181062.3-181063.37" - process $proc$issuer_ls180.v:181062$13403 + attribute \src "libresoc.v:49625.3-49626.37" + process $proc$libresoc.v:49625$1996 assign { } { } assign $0\core_irq_o[0:0] \core_irq_o$next sync posedge \clk update \core_irq_o $0\core_irq_o[0:0] end - attribute \src "issuer_ls180.v:181064.3-181065.25" - process $proc$issuer_ls180.v:181064$13404 + attribute \src "libresoc.v:49627.3-49628.25" + process $proc$libresoc.v:49627$1997 assign { } { } assign $0\xisr[23:0] \xisr$next sync posedge \clk update \xisr $0\xisr[23:0] end - attribute \src "issuer_ls180.v:181066.3-181067.25" - process $proc$issuer_ls180.v:181066$13405 + attribute \src "libresoc.v:49629.3-49630.25" + process $proc$libresoc.v:49629$1998 assign { } { } assign $0\cppr[7:0] \cppr$next sync posedge \clk update \cppr $0\cppr[7:0] end - attribute \src "issuer_ls180.v:181068.3-181069.25" - process $proc$issuer_ls180.v:181068$13406 + attribute \src "libresoc.v:49631.3-49632.25" + process $proc$libresoc.v:49631$1999 assign { } { } assign $0\mfrr[7:0] \mfrr$next sync posedge \clk update \mfrr $0\mfrr[7:0] end - attribute \src "issuer_ls180.v:181070.3-181071.23" - process $proc$issuer_ls180.v:181070$13407 + attribute \src "libresoc.v:49633.3-49634.23" + process $proc$libresoc.v:49633$2000 assign { } { } assign $0\irq[0:0] \irq$next sync posedge \clk update \irq $0\irq[0:0] end - attribute \src "issuer_ls180.v:181072.3-181073.37" - process $proc$issuer_ls180.v:181072$13408 + attribute \src "libresoc.v:49635.3-49636.37" + process $proc$libresoc.v:49635$2001 assign { } { } assign $0\wb_rd_data[31:0] \wb_rd_data$next sync posedge \clk update \wb_rd_data $0\wb_rd_data[31:0] end - attribute \src "issuer_ls180.v:181074.3-181089.6" - process $proc$issuer_ls180.v:181074$13409 + attribute \src "libresoc.v:49637.3-49638.29" + process $proc$libresoc.v:49637$2002 + assign { } { } + assign $0\wb_ack[0:0] \wb_ack$next + sync posedge \clk + update \wb_ack $0\wb_ack[0:0] + end + attribute \src "libresoc.v:49639.3-49654.6" + process $proc$libresoc.v:49639$2003 assign { } { } assign { } { } assign { } { } @@ -377017,21 +140669,21 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\cppr$next[7:0]$13410 $1\cppr$next[7:0]$13416 - assign $0\irq$next[0:0]$13411 $1\irq$next[0:0]$13417 - assign $0\mfrr$next[7:0]$13412 $1\mfrr$next[7:0]$13418 - assign $0\wb_ack$next[0:0]$13413 $1\wb_ack$next[0:0]$13419 - assign $0\wb_rd_data$next[31:0]$13414 $1\wb_rd_data$next[31:0]$13420 - assign $0\xisr$next[23:0]$13415 $1\xisr$next[23:0]$13421 - attribute \src "issuer_ls180.v:181075.5-181075.29" + assign $0\cppr$next[7:0]$2004 $1\cppr$next[7:0]$2010 + assign $0\irq$next[0:0]$2005 $1\irq$next[0:0]$2011 + assign $0\mfrr$next[7:0]$2006 $1\mfrr$next[7:0]$2012 + assign $0\wb_ack$next[0:0]$2007 $1\wb_ack$next[0:0]$2013 + assign $0\wb_rd_data$next[31:0]$2008 $1\wb_rd_data$next[31:0]$2014 + assign $0\xisr$next[23:0]$2009 $1\xisr$next[23:0]$2015 + attribute \src "libresoc.v:49640.5-49640.29" switch \initial - attribute \src "issuer_ls180.v:181075.9-181075.17" + attribute \src "libresoc.v:49640.9-49640.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } @@ -377039,63 +140691,63 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\xisr$next[23:0]$13421 24'000000000000000000000000 - assign $1\cppr$next[7:0]$13416 8'00000000 - assign $1\mfrr$next[7:0]$13418 8'11111111 - assign $1\irq$next[0:0]$13417 1'0 - assign $1\wb_rd_data$next[31:0]$13420 0 - assign $1\wb_ack$next[0:0]$13419 1'0 + assign $1\xisr$next[23:0]$2015 24'000000000000000000000000 + assign $1\cppr$next[7:0]$2010 8'00000000 + assign $1\mfrr$next[7:0]$2012 8'11111111 + assign $1\irq$next[0:0]$2011 1'0 + assign $1\wb_rd_data$next[31:0]$2014 0 + assign $1\wb_ack$next[0:0]$2013 1'0 case - assign $1\cppr$next[7:0]$13416 \cppr$2 - assign $1\irq$next[0:0]$13417 \irq$4 - assign $1\mfrr$next[7:0]$13418 \mfrr$3 - assign $1\wb_ack$next[0:0]$13419 \wb_ack$6 - assign $1\wb_rd_data$next[31:0]$13420 \wb_rd_data$5 - assign $1\xisr$next[23:0]$13421 \xisr$1 + assign $1\cppr$next[7:0]$2010 \cppr$2 + assign $1\irq$next[0:0]$2011 \irq$4 + assign $1\mfrr$next[7:0]$2012 \mfrr$3 + assign $1\wb_ack$next[0:0]$2013 \wb_ack$6 + assign $1\wb_rd_data$next[31:0]$2014 \wb_rd_data$5 + assign $1\xisr$next[23:0]$2015 \xisr$1 end sync always - update \cppr$next $0\cppr$next[7:0]$13410 - update \irq$next $0\irq$next[0:0]$13411 - update \mfrr$next $0\mfrr$next[7:0]$13412 - update \wb_ack$next $0\wb_ack$next[0:0]$13413 - update \wb_rd_data$next $0\wb_rd_data$next[31:0]$13414 - update \xisr$next $0\xisr$next[23:0]$13415 + update \cppr$next $0\cppr$next[7:0]$2004 + update \irq$next $0\irq$next[0:0]$2005 + update \mfrr$next $0\mfrr$next[7:0]$2006 + update \wb_ack$next $0\wb_ack$next[0:0]$2007 + update \wb_rd_data$next $0\wb_rd_data$next[31:0]$2008 + update \xisr$next $0\xisr$next[23:0]$2009 end - attribute \src "issuer_ls180.v:181090.3-181117.6" - process $proc$issuer_ls180.v:181090$13422 + attribute \src "libresoc.v:49655.3-49682.6" + process $proc$libresoc.v:49655$2016 assign { } { } assign { } { } assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0] - attribute \src "issuer_ls180.v:181091.5-181091.29" + attribute \src "libresoc.v:49656.5-49656.29" switch \initial - attribute \src "issuer_ls180.v:181091.9-181091.17" + attribute \src "libresoc.v:49656.9-49656.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" switch \$23 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\xirr_accept_rd[0:0] $2\xirr_accept_rd[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" switch \icp_wb__we - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\xirr_accept_rd[0:0] 1'0 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\xirr_accept_rd[0:0] $3\xirr_accept_rd[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155" switch \icp_wb__adr [5:0] - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 6'000001 assign { } { } assign $3\xirr_accept_rd[0:0] $4\xirr_accept_rd[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" switch \$25 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\xirr_accept_rd[0:0] 1'1 @@ -377112,43 +140764,43 @@ module \xics_icp sync always update \xirr_accept_rd $0\xirr_accept_rd[0:0] end - attribute \src "issuer_ls180.v:181118.3-181146.6" - process $proc$issuer_ls180.v:181118$13423 + attribute \src "libresoc.v:49683.3-49711.6" + process $proc$libresoc.v:49683$2017 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "issuer_ls180.v:181119.5-181119.29" + attribute \src "libresoc.v:49684.5-49684.29" switch \initial - attribute \src "issuer_ls180.v:181119.9-181119.17" + attribute \src "libresoc.v:49684.9-49684.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" switch \$27 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\be_out[31:0] $2\be_out[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" switch \icp_wb__we - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\be_out[31:0] 0 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\be_out[31:0] $3\be_out[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155" switch \icp_wb__adr [5:0] - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 6'000000 assign { } { } assign $3\be_out[31:0] { \cppr \xisr } - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 6'000001 assign { } { } assign $3\be_out[31:0] { \cppr \xisr } - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign $3\be_out[31:0] [23:0] 24'000000000000000000000000 assign $3\be_out[31:0] [31:24] \mfrr @@ -377162,20 +140814,20 @@ module \xics_icp sync always update \be_out $0\be_out[31:0] end - attribute \src "issuer_ls180.v:181147.3-181156.6" - process $proc$issuer_ls180.v:181147$13424 + attribute \src "libresoc.v:49712.3-49721.6" + process $proc$libresoc.v:49712$2018 assign { } { } assign { } { } assign $0\pending_priority[7:0] $1\pending_priority[7:0] - attribute \src "issuer_ls180.v:181148.5-181148.29" + attribute \src "libresoc.v:49713.5-49713.29" switch \initial - attribute \src "issuer_ls180.v:181148.9-181148.17" + attribute \src "libresoc.v:49713.9-49713.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" switch \$29 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\pending_priority[7:0] \ics_i_pri @@ -377185,23 +140837,23 @@ module \xics_icp sync always update \pending_priority $0\pending_priority[7:0] end - attribute \src "issuer_ls180.v:181157.3-181168.6" - process $proc$issuer_ls180.v:181157$13425 + attribute \src "libresoc.v:49722.3-49733.6" + process $proc$libresoc.v:49722$2019 assign { } { } assign $0\min_pri[7:0] $1\min_pri[7:0] - attribute \src "issuer_ls180.v:181158.5-181158.29" + attribute \src "libresoc.v:49723.5-49723.29" switch \initial - attribute \src "issuer_ls180.v:181158.9-181158.17" + attribute \src "libresoc.v:49723.9-49723.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" switch \$31 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\min_pri[7:0] \mfrr - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\min_pri[7:0] \pending_priority @@ -377209,43 +140861,43 @@ module \xics_icp sync always update \min_pri $0\min_pri[7:0] end - attribute \src "issuer_ls180.v:181169.3-181177.6" - process $proc$issuer_ls180.v:181169$13426 + attribute \src "libresoc.v:49734.3-49742.6" + process $proc$libresoc.v:49734$2020 assign { } { } assign { } { } - assign $0\core_irq_o$next[0:0]$13427 $1\core_irq_o$next[0:0]$13428 - attribute \src "issuer_ls180.v:181170.5-181170.29" + assign $0\core_irq_o$next[0:0]$2021 $1\core_irq_o$next[0:0]$2022 + attribute \src "libresoc.v:49735.5-49735.29" switch \initial - attribute \src "issuer_ls180.v:181170.9-181170.17" + attribute \src "libresoc.v:49735.9-49735.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_irq_o$next[0:0]$13428 1'0 + assign $1\core_irq_o$next[0:0]$2022 1'0 case - assign $1\core_irq_o$next[0:0]$13428 \irq + assign $1\core_irq_o$next[0:0]$2022 \irq end sync always - update \core_irq_o$next $0\core_irq_o$next[0:0]$13427 + update \core_irq_o$next $0\core_irq_o$next[0:0]$2021 end - attribute \src "issuer_ls180.v:181178.3-181187.6" - process $proc$issuer_ls180.v:181178$13429 + attribute \src "libresoc.v:49743.3-49752.6" + process $proc$libresoc.v:49743$2023 assign { } { } assign { } { } assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0] - attribute \src "issuer_ls180.v:181179.5-181179.29" + attribute \src "libresoc.v:49744.5-49744.29" switch \initial - attribute \src "issuer_ls180.v:181179.9-181179.17" + attribute \src "libresoc.v:49744.9-49744.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:97" switch \icp_wb__ack - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\icp_wb__dat_r[31:0] \wb_rd_data @@ -377255,8 +140907,8 @@ module \xics_icp sync always update \icp_wb__dat_r $0\icp_wb__dat_r[31:0] end - attribute \src "issuer_ls180.v:181188.3-181250.6" - process $proc$issuer_ls180.v:181188$13430 + attribute \src "libresoc.v:49753.3-49815.6" + process $proc$libresoc.v:49753$2024 assign { } { } assign { } { } assign { } { } @@ -377266,734 +140918,734 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\mfrr$11[7:0]$13433 $1\mfrr$11[7:0]$13438 - assign $0\wb_ack$14[0:0]$13434 $1\wb_ack$14[0:0]$13439 + assign $0\mfrr$11[7:0]$2027 $1\mfrr$11[7:0]$2032 + assign $0\wb_ack$14[0:0]$2028 $1\wb_ack$14[0:0]$2033 assign { } { } assign { } { } assign { } { } - assign $0\xisr$9[23:0]$13436 $2\xisr$9[23:0]$13445 - assign $0\cppr$10[7:0]$13431 $4\cppr$10[7:0]$13446 - assign $0\wb_rd_data$13[31:0]$13435 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } - assign $0\irq$12[0:0]$13432 $1\irq$12[0:0]$13447 - attribute \src "issuer_ls180.v:181189.5-181189.29" + assign $0\xisr$9[23:0]$2030 $2\xisr$9[23:0]$2039 + assign $0\cppr$10[7:0]$2025 $4\cppr$10[7:0]$2040 + assign $0\wb_rd_data$13[31:0]$2029 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $0\irq$12[0:0]$2026 $1\irq$12[0:0]$2041 + attribute \src "libresoc.v:49754.5-49754.29" switch \initial - attribute \src "issuer_ls180.v:181189.9-181189.17" + attribute \src "libresoc.v:49754.9-49754.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" switch \$15 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } - assign $1\wb_ack$14[0:0]$13439 1'1 - assign $1\cppr$10[7:0]$13437 $2\cppr$10[7:0]$13440 - assign $1\mfrr$11[7:0]$13438 $2\mfrr$11[7:0]$13441 + assign $1\wb_ack$14[0:0]$2033 1'1 + assign $1\cppr$10[7:0]$2031 $2\cppr$10[7:0]$2034 + assign $1\mfrr$11[7:0]$2032 $2\mfrr$11[7:0]$2035 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" switch \icp_wb__we - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign $2\cppr$10[7:0]$13440 $3\cppr$10[7:0]$13442 - assign $2\mfrr$11[7:0]$13441 $3\mfrr$11[7:0]$13443 + assign $2\cppr$10[7:0]$2034 $3\cppr$10[7:0]$2036 + assign $2\mfrr$11[7:0]$2035 $3\mfrr$11[7:0]$2037 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121" switch \icp_wb__adr [5:0] - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 6'000000 assign { } { } - assign $3\mfrr$11[7:0]$13443 \mfrr - assign $3\cppr$10[7:0]$13442 \be_in [31:24] - attribute \src "issuer_ls180.v:0.0-0.0" + assign $3\mfrr$11[7:0]$2037 \mfrr + assign $3\cppr$10[7:0]$2036 \be_in [31:24] + attribute \src "libresoc.v:0.0-0.0" case 6'000001 assign { } { } - assign $3\mfrr$11[7:0]$13443 \mfrr - assign $3\cppr$10[7:0]$13442 \be_in [31:24] - attribute \src "issuer_ls180.v:0.0-0.0" + assign $3\mfrr$11[7:0]$2037 \mfrr + assign $3\cppr$10[7:0]$2036 \be_in [31:24] + attribute \src "libresoc.v:0.0-0.0" case 6'000011 - assign $3\cppr$10[7:0]$13442 \cppr + assign $3\cppr$10[7:0]$2036 \cppr assign { } { } - assign $3\mfrr$11[7:0]$13443 \be_in [31:24] + assign $3\mfrr$11[7:0]$2037 \be_in [31:24] case - assign $3\cppr$10[7:0]$13442 \cppr - assign $3\mfrr$11[7:0]$13443 \mfrr + assign $3\cppr$10[7:0]$2036 \cppr + assign $3\mfrr$11[7:0]$2037 \mfrr end case - assign $2\cppr$10[7:0]$13440 \cppr - assign $2\mfrr$11[7:0]$13441 \mfrr + assign $2\cppr$10[7:0]$2034 \cppr + assign $2\mfrr$11[7:0]$2035 \mfrr end case - assign $1\cppr$10[7:0]$13437 \cppr - assign $1\mfrr$11[7:0]$13438 \mfrr - assign $1\wb_ack$14[0:0]$13439 1'0 + assign $1\cppr$10[7:0]$2031 \cppr + assign $1\mfrr$11[7:0]$2032 \mfrr + assign $1\wb_ack$14[0:0]$2033 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" switch \$17 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xisr$9[23:0]$13444 { 20'00000000000000000001 \ics_i_src } + assign $1\xisr$9[23:0]$2038 { 20'00000000000000000001 \ics_i_src } case - assign $1\xisr$9[23:0]$13444 24'000000000000000000000000 + assign $1\xisr$9[23:0]$2038 24'000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" switch \$19 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xisr$9[23:0]$13445 24'000000000000000000000010 + assign $2\xisr$9[23:0]$2039 24'000000000000000000000010 case - assign $2\xisr$9[23:0]$13445 $1\xisr$9[23:0]$13444 + assign $2\xisr$9[23:0]$2039 $1\xisr$9[23:0]$2038 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185" switch \xirr_accept_rd - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cppr$10[7:0]$13446 \min_pri + assign $4\cppr$10[7:0]$2040 \min_pri case - assign $4\cppr$10[7:0]$13446 $1\cppr$10[7:0]$13437 + assign $4\cppr$10[7:0]$2040 $1\cppr$10[7:0]$2031 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" switch { \irq \$21 } - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\irq$12[0:0]$13447 1'1 + assign $1\irq$12[0:0]$2041 1'1 case - assign $1\irq$12[0:0]$13447 1'0 + assign $1\irq$12[0:0]$2041 1'0 end sync always - update \cppr$10 $0\cppr$10[7:0]$13431 - update \irq$12 $0\irq$12[0:0]$13432 - update \mfrr$11 $0\mfrr$11[7:0]$13433 - update \wb_ack$14 $0\wb_ack$14[0:0]$13434 - update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$13435 - update \xisr$9 $0\xisr$9[23:0]$13436 + update \cppr$10 $0\cppr$10[7:0]$2025 + update \irq$12 $0\irq$12[0:0]$2026 + update \mfrr$11 $0\mfrr$11[7:0]$2027 + update \wb_ack$14 $0\wb_ack$14[0:0]$2028 + update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$2029 + update \xisr$9 $0\xisr$9[23:0]$2030 end - connect \$15 $and$issuer_ls180.v:181050$13392_Y - connect \$17 $ne$issuer_ls180.v:181051$13393_Y - connect \$19 $lt$issuer_ls180.v:181052$13394_Y - connect \$21 $lt$issuer_ls180.v:181053$13395_Y - connect \$23 $and$issuer_ls180.v:181054$13396_Y - connect \$25 $eq$issuer_ls180.v:181055$13397_Y - connect \$27 $and$issuer_ls180.v:181056$13398_Y - connect \$29 $ne$issuer_ls180.v:181057$13399_Y - connect \$31 $lt$issuer_ls180.v:181058$13400_Y - connect \$7 $and$issuer_ls180.v:181059$13401_Y + connect \$15 $and$libresoc.v:49615$1986_Y + connect \$17 $ne$libresoc.v:49616$1987_Y + connect \$19 $lt$libresoc.v:49617$1988_Y + connect \$21 $lt$libresoc.v:49618$1989_Y + connect \$23 $and$libresoc.v:49619$1990_Y + connect \$25 $eq$libresoc.v:49620$1991_Y + connect \$27 $and$libresoc.v:49621$1992_Y + connect \$29 $ne$libresoc.v:49622$1993_Y + connect \$31 $lt$libresoc.v:49623$1994_Y + connect \$7 $and$libresoc.v:49624$1995_Y connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 } connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] } connect \icp_wb__ack \$7 end -attribute \src "issuer_ls180.v:181258.1-182307.10" +attribute \src "libresoc.v:49823.1-50872.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.xics_ics" attribute \generator "nMigen" module \xics_ics - attribute \src "issuer_ls180.v:182188.3-182237.6" + attribute \src "libresoc.v:50753.3-50802.6" wire width 32 $0\be_out[31:0] - attribute \src "issuer_ls180.v:181899.3-181908.6" + attribute \src "libresoc.v:50464.3-50473.6" wire width 4 $0\cur_idx0[3:0] - attribute \src "issuer_ls180.v:182108.3-182117.6" + attribute \src "libresoc.v:50673.3-50682.6" wire width 4 $0\cur_idx10[3:0] - attribute \src "issuer_ls180.v:182128.3-182137.6" + attribute \src "libresoc.v:50693.3-50702.6" wire width 4 $0\cur_idx11[3:0] - attribute \src "issuer_ls180.v:182148.3-182157.6" + attribute \src "libresoc.v:50713.3-50722.6" wire width 4 $0\cur_idx12[3:0] - attribute \src "issuer_ls180.v:182168.3-182177.6" + attribute \src "libresoc.v:50733.3-50742.6" wire width 4 $0\cur_idx13[3:0] - attribute \src "issuer_ls180.v:182238.3-182247.6" + attribute \src "libresoc.v:50803.3-50812.6" wire width 4 $0\cur_idx14[3:0] - attribute \src "issuer_ls180.v:182258.3-182267.6" + attribute \src "libresoc.v:50823.3-50832.6" wire width 4 $0\cur_idx15[3:0] - attribute \src "issuer_ls180.v:181919.3-181928.6" + attribute \src "libresoc.v:50484.3-50493.6" wire width 4 $0\cur_idx1[3:0] - attribute \src "issuer_ls180.v:181939.3-181948.6" + attribute \src "libresoc.v:50504.3-50513.6" wire width 4 $0\cur_idx2[3:0] - attribute \src "issuer_ls180.v:181959.3-181968.6" + attribute \src "libresoc.v:50524.3-50533.6" wire width 4 $0\cur_idx3[3:0] - attribute \src "issuer_ls180.v:181988.3-181997.6" + attribute \src "libresoc.v:50553.3-50562.6" wire width 4 $0\cur_idx4[3:0] - attribute \src "issuer_ls180.v:182008.3-182017.6" + attribute \src "libresoc.v:50573.3-50582.6" wire width 4 $0\cur_idx5[3:0] - attribute \src "issuer_ls180.v:182028.3-182037.6" + attribute \src "libresoc.v:50593.3-50602.6" wire width 4 $0\cur_idx6[3:0] - attribute \src "issuer_ls180.v:182048.3-182057.6" + attribute \src "libresoc.v:50613.3-50622.6" wire width 4 $0\cur_idx7[3:0] - attribute \src "issuer_ls180.v:182068.3-182077.6" + attribute \src "libresoc.v:50633.3-50642.6" wire width 4 $0\cur_idx8[3:0] - attribute \src "issuer_ls180.v:182088.3-182097.6" + attribute \src "libresoc.v:50653.3-50662.6" wire width 4 $0\cur_idx9[3:0] - attribute \src "issuer_ls180.v:181889.3-181898.6" + attribute \src "libresoc.v:50454.3-50463.6" wire width 8 $0\cur_pri0[7:0] - attribute \src "issuer_ls180.v:182098.3-182107.6" + attribute \src "libresoc.v:50663.3-50672.6" wire width 8 $0\cur_pri10[7:0] - attribute \src "issuer_ls180.v:182118.3-182127.6" + attribute \src "libresoc.v:50683.3-50692.6" wire width 8 $0\cur_pri11[7:0] - attribute \src "issuer_ls180.v:182138.3-182147.6" + attribute \src "libresoc.v:50703.3-50712.6" wire width 8 $0\cur_pri12[7:0] - attribute \src "issuer_ls180.v:182158.3-182167.6" + attribute \src "libresoc.v:50723.3-50732.6" wire width 8 $0\cur_pri13[7:0] - attribute \src "issuer_ls180.v:182178.3-182187.6" + attribute \src "libresoc.v:50743.3-50752.6" wire width 8 $0\cur_pri14[7:0] - attribute \src "issuer_ls180.v:182248.3-182257.6" + attribute \src "libresoc.v:50813.3-50822.6" wire width 8 $0\cur_pri15[7:0] - attribute \src "issuer_ls180.v:181909.3-181918.6" + attribute \src "libresoc.v:50474.3-50483.6" wire width 8 $0\cur_pri1[7:0] - attribute \src "issuer_ls180.v:181929.3-181938.6" + attribute \src "libresoc.v:50494.3-50503.6" wire width 8 $0\cur_pri2[7:0] - attribute \src "issuer_ls180.v:181949.3-181958.6" + attribute \src "libresoc.v:50514.3-50523.6" wire width 8 $0\cur_pri3[7:0] - attribute \src "issuer_ls180.v:181969.3-181978.6" + attribute \src "libresoc.v:50534.3-50543.6" wire width 8 $0\cur_pri4[7:0] - attribute \src "issuer_ls180.v:181998.3-182007.6" + attribute \src "libresoc.v:50563.3-50572.6" wire width 8 $0\cur_pri5[7:0] - attribute \src "issuer_ls180.v:182018.3-182027.6" + attribute \src "libresoc.v:50583.3-50592.6" wire width 8 $0\cur_pri6[7:0] - attribute \src "issuer_ls180.v:182038.3-182047.6" + attribute \src "libresoc.v:50603.3-50612.6" wire width 8 $0\cur_pri7[7:0] - attribute \src "issuer_ls180.v:182058.3-182067.6" + attribute \src "libresoc.v:50623.3-50632.6" wire width 8 $0\cur_pri8[7:0] - attribute \src "issuer_ls180.v:182078.3-182087.6" + attribute \src "libresoc.v:50643.3-50652.6" wire width 8 $0\cur_pri9[7:0] - attribute \src "issuer_ls180.v:182268.3-182277.6" + attribute \src "libresoc.v:50833.3-50842.6" wire $0\ibit[0:0] - attribute \src "issuer_ls180.v:181763.3-181764.25" + attribute \src "libresoc.v:50328.3-50329.25" wire width 8 $0\icp_o_pri[7:0] - attribute \src "issuer_ls180.v:181761.3-181762.28" + attribute \src "libresoc.v:50326.3-50327.28" wire width 4 $0\icp_o_src[3:0] - attribute \src "issuer_ls180.v:182287.3-182295.6" - wire $0\ics_wb__ack$next[0:0]$13702 - attribute \src "issuer_ls180.v:181797.3-181798.39" + attribute \src "libresoc.v:50852.3-50860.6" + wire $0\ics_wb__ack$next[0:0]$2296 + attribute \src "libresoc.v:50362.3-50363.39" wire $0\ics_wb__ack[0:0] - attribute \src "issuer_ls180.v:182278.3-182286.6" - wire width 32 $0\ics_wb__dat_r$next[31:0]$13699 - attribute \src "issuer_ls180.v:181799.3-181800.43" + attribute \src "libresoc.v:50843.3-50851.6" + wire width 32 $0\ics_wb__dat_r$next[31:0]$2293 + attribute \src "libresoc.v:50364.3-50365.43" wire width 32 $0\ics_wb__dat_r[31:0] - attribute \src "issuer_ls180.v:181259.7-181259.20" + attribute \src "libresoc.v:49824.7-49824.20" wire $0\initial[0:0] - attribute \src "issuer_ls180.v:181979.3-181987.6" - wire width 16 $0\int_level_l$next[15:0]$13671 - attribute \src "issuer_ls180.v:181801.3-181802.39" + attribute \src "libresoc.v:50544.3-50552.6" + wire width 16 $0\int_level_l$next[15:0]$2265 + attribute \src "libresoc.v:50366.3-50367.39" wire width 16 $0\int_level_l[15:0] - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $0\xive0_pri$next[7:0]$13581 - attribute \src "issuer_ls180.v:181765.3-181766.35" + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $0\xive0_pri$next[7:0]$2175 + attribute \src "libresoc.v:50330.3-50331.35" wire width 8 $0\xive0_pri[7:0] - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $0\xive10_pri$next[7:0]$13582 - attribute \src "issuer_ls180.v:181785.3-181786.37" + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $0\xive10_pri$next[7:0]$2176 + attribute \src "libresoc.v:50350.3-50351.37" wire width 8 $0\xive10_pri[7:0] - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $0\xive11_pri$next[7:0]$13583 - attribute \src "issuer_ls180.v:181787.3-181788.37" + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $0\xive11_pri$next[7:0]$2177 + attribute \src "libresoc.v:50352.3-50353.37" wire width 8 $0\xive11_pri[7:0] - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $0\xive12_pri$next[7:0]$13584 - attribute \src "issuer_ls180.v:181789.3-181790.37" + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $0\xive12_pri$next[7:0]$2178 + attribute \src "libresoc.v:50354.3-50355.37" wire width 8 $0\xive12_pri[7:0] - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $0\xive13_pri$next[7:0]$13585 - attribute \src "issuer_ls180.v:181791.3-181792.37" + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $0\xive13_pri$next[7:0]$2179 + attribute \src "libresoc.v:50356.3-50357.37" wire width 8 $0\xive13_pri[7:0] - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $0\xive14_pri$next[7:0]$13586 - attribute \src "issuer_ls180.v:181793.3-181794.37" + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $0\xive14_pri$next[7:0]$2180 + attribute \src "libresoc.v:50358.3-50359.37" wire width 8 $0\xive14_pri[7:0] - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $0\xive15_pri$next[7:0]$13587 - attribute \src "issuer_ls180.v:181795.3-181796.37" + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $0\xive15_pri$next[7:0]$2181 + attribute \src "libresoc.v:50360.3-50361.37" wire width 8 $0\xive15_pri[7:0] - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $0\xive1_pri$next[7:0]$13588 - attribute \src "issuer_ls180.v:181767.3-181768.35" + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $0\xive1_pri$next[7:0]$2182 + attribute \src "libresoc.v:50332.3-50333.35" wire width 8 $0\xive1_pri[7:0] - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $0\xive2_pri$next[7:0]$13589 - attribute \src "issuer_ls180.v:181769.3-181770.35" + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $0\xive2_pri$next[7:0]$2183 + attribute \src "libresoc.v:50334.3-50335.35" wire width 8 $0\xive2_pri[7:0] - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $0\xive3_pri$next[7:0]$13590 - attribute \src "issuer_ls180.v:181771.3-181772.35" + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $0\xive3_pri$next[7:0]$2184 + attribute \src "libresoc.v:50336.3-50337.35" wire width 8 $0\xive3_pri[7:0] - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $0\xive4_pri$next[7:0]$13591 - attribute \src "issuer_ls180.v:181773.3-181774.35" + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $0\xive4_pri$next[7:0]$2185 + attribute \src "libresoc.v:50338.3-50339.35" wire width 8 $0\xive4_pri[7:0] - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $0\xive5_pri$next[7:0]$13592 - attribute \src "issuer_ls180.v:181775.3-181776.35" + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $0\xive5_pri$next[7:0]$2186 + attribute \src "libresoc.v:50340.3-50341.35" wire width 8 $0\xive5_pri[7:0] - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $0\xive6_pri$next[7:0]$13593 - attribute \src "issuer_ls180.v:181777.3-181778.35" + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $0\xive6_pri$next[7:0]$2187 + attribute \src "libresoc.v:50342.3-50343.35" wire width 8 $0\xive6_pri[7:0] - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $0\xive7_pri$next[7:0]$13594 - attribute \src "issuer_ls180.v:181779.3-181780.35" + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $0\xive7_pri$next[7:0]$2188 + attribute \src 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$4\xive11_pri$next[7:0]$13647 - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $4\xive12_pri$next[7:0]$13648 - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $4\xive13_pri$next[7:0]$13649 - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $4\xive14_pri$next[7:0]$13650 - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $4\xive15_pri$next[7:0]$13651 - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $4\xive1_pri$next[7:0]$13652 - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $4\xive2_pri$next[7:0]$13653 - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $4\xive3_pri$next[7:0]$13654 - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $4\xive4_pri$next[7:0]$13655 - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $4\xive5_pri$next[7:0]$13656 - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $4\xive6_pri$next[7:0]$13657 - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $4\xive7_pri$next[7:0]$13658 - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $4\xive8_pri$next[7:0]$13659 - attribute \src "issuer_ls180.v:181803.3-181888.6" - wire width 8 $4\xive9_pri$next[7:0]$13660 - attribute \src "issuer_ls180.v:181660.19-181660.113" - wire $and$issuer_ls180.v:181660$13458_Y - attribute \src "issuer_ls180.v:181662.19-181662.114" - wire $and$issuer_ls180.v:181662$13460_Y - attribute \src "issuer_ls180.v:181664.19-181664.114" - wire $and$issuer_ls180.v:181664$13462_Y - attribute \src "issuer_ls180.v:181666.19-181666.114" - wire $and$issuer_ls180.v:181666$13464_Y - attribute \src "issuer_ls180.v:181668.19-181668.114" - wire $and$issuer_ls180.v:181668$13466_Y - attribute \src "issuer_ls180.v:181670.19-181670.114" - wire $and$issuer_ls180.v:181670$13468_Y - attribute \src "issuer_ls180.v:181672.19-181672.114" - wire $and$issuer_ls180.v:181672$13470_Y - attribute \src "issuer_ls180.v:181675.19-181675.114" - wire $and$issuer_ls180.v:181675$13473_Y - attribute \src "issuer_ls180.v:181677.19-181677.114" - wire $and$issuer_ls180.v:181677$13475_Y - attribute \src "issuer_ls180.v:181679.19-181679.114" - wire $and$issuer_ls180.v:181679$13477_Y - attribute \src "issuer_ls180.v:181682.19-181682.114" - wire $and$issuer_ls180.v:181682$13480_Y - attribute \src "issuer_ls180.v:181684.19-181684.114" - wire $and$issuer_ls180.v:181684$13482_Y - attribute \src "issuer_ls180.v:181686.19-181686.114" - wire $and$issuer_ls180.v:181686$13484_Y - attribute \src "issuer_ls180.v:181688.19-181688.114" - wire $and$issuer_ls180.v:181688$13486_Y - attribute \src "issuer_ls180.v:181690.19-181690.115" - wire $and$issuer_ls180.v:181690$13488_Y - attribute \src "issuer_ls180.v:181692.19-181692.115" - wire $and$issuer_ls180.v:181692$13490_Y - attribute \src "issuer_ls180.v:181694.19-181694.115" - wire $and$issuer_ls180.v:181694$13492_Y - attribute \src "issuer_ls180.v:181697.19-181697.115" - wire $and$issuer_ls180.v:181697$13495_Y - attribute \src "issuer_ls180.v:181699.19-181699.115" - wire $and$issuer_ls180.v:181699$13497_Y - attribute \src "issuer_ls180.v:181701.19-181701.115" - wire $and$issuer_ls180.v:181701$13499_Y - attribute \src "issuer_ls180.v:181704.19-181704.115" - wire $and$issuer_ls180.v:181704$13502_Y - attribute \src "issuer_ls180.v:181706.19-181706.115" - wire $and$issuer_ls180.v:181706$13504_Y - attribute \src "issuer_ls180.v:181708.19-181708.115" - wire $and$issuer_ls180.v:181708$13506_Y - attribute \src "issuer_ls180.v:181710.19-181710.115" - wire $and$issuer_ls180.v:181710$13508_Y - attribute \src "issuer_ls180.v:181712.19-181712.115" - wire $and$issuer_ls180.v:181712$13510_Y - attribute \src "issuer_ls180.v:181715.19-181715.115" - wire $and$issuer_ls180.v:181715$13513_Y - attribute \src "issuer_ls180.v:181739.17-181739.115" - wire $and$issuer_ls180.v:181739$13537_Y - attribute \src "issuer_ls180.v:181747.18-181747.112" - wire $and$issuer_ls180.v:181747$13545_Y - attribute \src "issuer_ls180.v:181749.18-181749.112" - wire $and$issuer_ls180.v:181749$13547_Y - attribute \src "issuer_ls180.v:181751.18-181751.112" - wire $and$issuer_ls180.v:181751$13549_Y - attribute \src "issuer_ls180.v:181753.18-181753.112" - wire $and$issuer_ls180.v:181753$13551_Y - attribute \src "issuer_ls180.v:181756.18-181756.112" - wire $and$issuer_ls180.v:181756$13554_Y - attribute \src "issuer_ls180.v:181758.18-181758.112" - wire $and$issuer_ls180.v:181758$13556_Y - attribute \src "issuer_ls180.v:181760.18-181760.112" - wire $and$issuer_ls180.v:181760$13558_Y - attribute \src "issuer_ls180.v:181674.18-181674.109" - wire $eq$issuer_ls180.v:181674$13472_Y - attribute \src "issuer_ls180.v:181696.18-181696.109" - wire $eq$issuer_ls180.v:181696$13494_Y - attribute \src "issuer_ls180.v:181713.17-181713.114" - wire $eq$issuer_ls180.v:181713$13511_Y - attribute \src "issuer_ls180.v:181716.19-181716.110" - wire $eq$issuer_ls180.v:181716$13514_Y - attribute \src "issuer_ls180.v:181718.18-181718.109" - wire $eq$issuer_ls180.v:181718$13516_Y - attribute \src "issuer_ls180.v:181720.18-181720.109" - wire $eq$issuer_ls180.v:181720$13518_Y - attribute \src "issuer_ls180.v:181722.18-181722.109" - wire $eq$issuer_ls180.v:181722$13520_Y - attribute \src "issuer_ls180.v:181724.18-181724.109" - wire $eq$issuer_ls180.v:181724$13522_Y - attribute \src "issuer_ls180.v:181726.18-181726.109" - wire $eq$issuer_ls180.v:181726$13524_Y - attribute \src "issuer_ls180.v:181728.17-181728.114" - wire $eq$issuer_ls180.v:181728$13526_Y - attribute \src "issuer_ls180.v:181729.18-181729.109" - wire $eq$issuer_ls180.v:181729$13527_Y - attribute \src "issuer_ls180.v:181731.18-181731.109" - wire $eq$issuer_ls180.v:181731$13529_Y - attribute \src "issuer_ls180.v:181733.18-181733.110" - wire $eq$issuer_ls180.v:181733$13531_Y - attribute \src "issuer_ls180.v:181735.18-181735.110" - wire $eq$issuer_ls180.v:181735$13533_Y - attribute \src "issuer_ls180.v:181737.18-181737.110" - wire $eq$issuer_ls180.v:181737$13535_Y - attribute \src "issuer_ls180.v:181740.18-181740.110" - wire $eq$issuer_ls180.v:181740$13538_Y - attribute \src "issuer_ls180.v:181742.18-181742.110" - wire $eq$issuer_ls180.v:181742$13540_Y - attribute \src "issuer_ls180.v:181744.18-181744.110" - wire $eq$issuer_ls180.v:181744$13542_Y - attribute \src "issuer_ls180.v:181755.17-181755.108" - wire $eq$issuer_ls180.v:181755$13553_Y - attribute \src "issuer_ls180.v:181659.18-181659.111" - wire $lt$issuer_ls180.v:181659$13457_Y - attribute \src "issuer_ls180.v:181661.19-181661.112" - wire $lt$issuer_ls180.v:181661$13459_Y - attribute \src "issuer_ls180.v:181663.19-181663.112" - wire $lt$issuer_ls180.v:181663$13461_Y - attribute \src "issuer_ls180.v:181665.19-181665.112" - wire $lt$issuer_ls180.v:181665$13463_Y - attribute \src "issuer_ls180.v:181667.19-181667.112" - wire $lt$issuer_ls180.v:181667$13465_Y - attribute \src "issuer_ls180.v:181669.19-181669.112" - wire $lt$issuer_ls180.v:181669$13467_Y - attribute \src "issuer_ls180.v:181671.19-181671.112" - wire $lt$issuer_ls180.v:181671$13469_Y - attribute \src "issuer_ls180.v:181673.19-181673.112" - wire $lt$issuer_ls180.v:181673$13471_Y - attribute \src "issuer_ls180.v:181676.19-181676.112" - wire $lt$issuer_ls180.v:181676$13474_Y - attribute \src "issuer_ls180.v:181678.19-181678.112" - wire $lt$issuer_ls180.v:181678$13476_Y - attribute \src "issuer_ls180.v:181681.19-181681.112" - wire $lt$issuer_ls180.v:181681$13479_Y - attribute \src "issuer_ls180.v:181683.19-181683.112" - wire $lt$issuer_ls180.v:181683$13481_Y - attribute \src "issuer_ls180.v:181685.19-181685.112" - wire $lt$issuer_ls180.v:181685$13483_Y - attribute \src "issuer_ls180.v:181687.19-181687.112" - wire $lt$issuer_ls180.v:181687$13485_Y - attribute \src "issuer_ls180.v:181689.19-181689.113" - wire $lt$issuer_ls180.v:181689$13487_Y - attribute \src "issuer_ls180.v:181691.19-181691.113" - wire $lt$issuer_ls180.v:181691$13489_Y - attribute \src "issuer_ls180.v:181693.19-181693.114" - wire $lt$issuer_ls180.v:181693$13491_Y - attribute \src "issuer_ls180.v:181695.19-181695.114" - wire $lt$issuer_ls180.v:181695$13493_Y - attribute \src "issuer_ls180.v:181698.19-181698.114" - wire $lt$issuer_ls180.v:181698$13496_Y - attribute \src "issuer_ls180.v:181700.19-181700.114" - wire $lt$issuer_ls180.v:181700$13498_Y - attribute \src "issuer_ls180.v:181703.19-181703.114" - wire $lt$issuer_ls180.v:181703$13501_Y - attribute \src "issuer_ls180.v:181705.19-181705.114" - wire $lt$issuer_ls180.v:181705$13503_Y - attribute \src "issuer_ls180.v:181707.19-181707.114" - wire $lt$issuer_ls180.v:181707$13505_Y - attribute \src "issuer_ls180.v:181709.19-181709.114" - wire $lt$issuer_ls180.v:181709$13507_Y - attribute \src "issuer_ls180.v:181711.19-181711.114" - wire $lt$issuer_ls180.v:181711$13509_Y - attribute \src "issuer_ls180.v:181714.19-181714.114" - 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width 8 $ternary$issuer_ls180.v:181702$13500_Y - attribute \src "issuer_ls180.v:181717.19-181717.118" - wire width 8 $ternary$issuer_ls180.v:181717$13515_Y - attribute \src "issuer_ls180.v:181719.18-181719.116" - wire width 8 $ternary$issuer_ls180.v:181719$13517_Y - attribute \src "issuer_ls180.v:181721.18-181721.116" - wire width 8 $ternary$issuer_ls180.v:181721$13519_Y - attribute \src "issuer_ls180.v:181723.18-181723.116" - wire width 8 $ternary$issuer_ls180.v:181723$13521_Y - attribute \src "issuer_ls180.v:181725.18-181725.116" - wire width 8 $ternary$issuer_ls180.v:181725$13523_Y - attribute \src "issuer_ls180.v:181727.18-181727.116" - wire width 8 $ternary$issuer_ls180.v:181727$13525_Y - attribute \src "issuer_ls180.v:181730.18-181730.116" - wire width 8 $ternary$issuer_ls180.v:181730$13528_Y - attribute \src "issuer_ls180.v:181732.18-181732.116" - wire width 8 $ternary$issuer_ls180.v:181732$13530_Y - attribute \src "issuer_ls180.v:181734.18-181734.117" - wire width 8 $ternary$issuer_ls180.v:181734$13532_Y - attribute \src "issuer_ls180.v:181736.18-181736.117" - wire width 8 $ternary$issuer_ls180.v:181736$13534_Y - attribute \src "issuer_ls180.v:181738.18-181738.117" - wire width 8 $ternary$issuer_ls180.v:181738$13536_Y - attribute \src "issuer_ls180.v:181741.18-181741.117" - wire width 8 $ternary$issuer_ls180.v:181741$13539_Y - attribute \src "issuer_ls180.v:181743.18-181743.117" - wire width 8 $ternary$issuer_ls180.v:181743$13541_Y - attribute \src "issuer_ls180.v:181745.18-181745.117" - wire width 8 $ternary$issuer_ls180.v:181745$13543_Y + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $2\xive0_pri$next[7:0]$2207 + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $2\xive10_pri$next[7:0]$2208 + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $2\xive11_pri$next[7:0]$2209 + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $2\xive12_pri$next[7:0]$2210 + attribute \src "libresoc.v:50368.3-50453.6" + wire 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$2\xive9_pri$next[7:0]$2222 + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $3\xive0_pri$next[7:0]$2223 + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $3\xive10_pri$next[7:0]$2224 + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $3\xive11_pri$next[7:0]$2225 + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $3\xive12_pri$next[7:0]$2226 + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $3\xive13_pri$next[7:0]$2227 + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $3\xive14_pri$next[7:0]$2228 + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $3\xive15_pri$next[7:0]$2229 + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $3\xive1_pri$next[7:0]$2230 + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $3\xive2_pri$next[7:0]$2231 + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 $3\xive3_pri$next[7:0]$2232 + attribute \src "libresoc.v:50368.3-50453.6" + wire width 8 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$ternary$libresoc.v:50288$2115_Y + attribute \src "libresoc.v:50290.18-50290.116" + wire width 8 $ternary$libresoc.v:50290$2117_Y + attribute \src "libresoc.v:50292.18-50292.116" + wire width 8 $ternary$libresoc.v:50292$2119_Y + attribute \src "libresoc.v:50295.18-50295.116" + wire width 8 $ternary$libresoc.v:50295$2122_Y + attribute \src "libresoc.v:50297.18-50297.116" + wire width 8 $ternary$libresoc.v:50297$2124_Y + attribute \src "libresoc.v:50299.18-50299.117" + wire width 8 $ternary$libresoc.v:50299$2126_Y + attribute \src "libresoc.v:50301.18-50301.117" + wire width 8 $ternary$libresoc.v:50301$2128_Y + attribute \src "libresoc.v:50303.18-50303.117" + wire width 8 $ternary$libresoc.v:50303$2130_Y + attribute \src "libresoc.v:50306.18-50306.117" + wire width 8 $ternary$libresoc.v:50306$2133_Y + attribute \src "libresoc.v:50308.18-50308.117" + wire width 8 $ternary$libresoc.v:50308$2135_Y + attribute \src "libresoc.v:50310.18-50310.117" + wire width 8 $ternary$libresoc.v:50310$2137_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" @@ -378204,7 +141856,7 @@ module \xics_ics wire width 32 \be_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308" wire width 32 \be_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" wire input 2 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx0 @@ -378302,7 +141954,7 @@ module \xics_ics wire input 7 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire input 11 \ics_wb__we - attribute \src "issuer_ls180.v:181259.7-181259.15" + attribute \src "libresoc.v:49824.7-49824.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" wire width 16 input 5 \int_level_i @@ -378322,7 +141974,7 @@ module \xics_ics wire \reg_is_debug attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286" wire \reg_is_xive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" wire input 3 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260" wire \wb_valid @@ -378391,7 +142043,7 @@ module \xics_ics attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive9_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181660$13458 + cell $and $and$libresoc.v:50225$2052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378399,10 +142051,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$99 - connect \Y $and$issuer_ls180.v:181660$13458_Y + connect \Y $and$libresoc.v:50225$2052_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181662$13460 + cell $and $and$libresoc.v:50227$2054 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378410,10 +142062,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$103 - connect \Y $and$issuer_ls180.v:181662$13460_Y + connect \Y $and$libresoc.v:50227$2054_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181664$13462 + cell $and $and$libresoc.v:50229$2056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378421,10 +142073,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$107 - connect \Y $and$issuer_ls180.v:181664$13462_Y + connect \Y $and$libresoc.v:50229$2056_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181666$13464 + cell $and $and$libresoc.v:50231$2058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378432,10 +142084,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$111 - connect \Y $and$issuer_ls180.v:181666$13464_Y + connect \Y $and$libresoc.v:50231$2058_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181668$13466 + cell $and $and$libresoc.v:50233$2060 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378443,10 +142095,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$115 - connect \Y $and$issuer_ls180.v:181668$13466_Y + connect \Y $and$libresoc.v:50233$2060_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181670$13468 + cell $and $and$libresoc.v:50235$2062 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378454,10 +142106,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$119 - connect \Y $and$issuer_ls180.v:181670$13468_Y + connect \Y $and$libresoc.v:50235$2062_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181672$13470 + cell $and $and$libresoc.v:50237$2064 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378465,10 +142117,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$123 - connect \Y $and$issuer_ls180.v:181672$13470_Y + connect \Y $and$libresoc.v:50237$2064_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181675$13473 + cell $and $and$libresoc.v:50240$2067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378476,10 +142128,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$127 - connect \Y $and$issuer_ls180.v:181675$13473_Y + connect \Y $and$libresoc.v:50240$2067_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181677$13475 + cell $and $and$libresoc.v:50242$2069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378487,10 +142139,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$131 - connect \Y $and$issuer_ls180.v:181677$13475_Y + connect \Y $and$libresoc.v:50242$2069_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181679$13477 + cell $and $and$libresoc.v:50244$2071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378498,10 +142150,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$135 - connect \Y $and$issuer_ls180.v:181679$13477_Y + connect \Y $and$libresoc.v:50244$2071_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181682$13480 + cell $and $and$libresoc.v:50247$2074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378509,10 +142161,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$139 - connect \Y $and$issuer_ls180.v:181682$13480_Y + connect \Y $and$libresoc.v:50247$2074_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181684$13482 + cell $and $and$libresoc.v:50249$2076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378520,10 +142172,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$143 - connect \Y $and$issuer_ls180.v:181684$13482_Y + connect \Y $and$libresoc.v:50249$2076_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181686$13484 + cell $and $and$libresoc.v:50251$2078 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378531,10 +142183,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$147 - connect \Y $and$issuer_ls180.v:181686$13484_Y + connect \Y $and$libresoc.v:50251$2078_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181688$13486 + cell $and $and$libresoc.v:50253$2080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378542,10 +142194,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$151 - connect \Y $and$issuer_ls180.v:181688$13486_Y + connect \Y $and$libresoc.v:50253$2080_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181690$13488 + cell $and $and$libresoc.v:50255$2082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378553,10 +142205,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$155 - connect \Y $and$issuer_ls180.v:181690$13488_Y + connect \Y $and$libresoc.v:50255$2082_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181692$13490 + cell $and $and$libresoc.v:50257$2084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378564,10 +142216,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$159 - connect \Y $and$issuer_ls180.v:181692$13490_Y + connect \Y $and$libresoc.v:50257$2084_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181694$13492 + cell $and $and$libresoc.v:50259$2086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378575,10 +142227,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$163 - connect \Y $and$issuer_ls180.v:181694$13492_Y + connect \Y $and$libresoc.v:50259$2086_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181697$13495 + cell $and $and$libresoc.v:50262$2089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378586,10 +142238,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$167 - connect \Y $and$issuer_ls180.v:181697$13495_Y + connect \Y $and$libresoc.v:50262$2089_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181699$13497 + cell $and $and$libresoc.v:50264$2091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378597,10 +142249,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$171 - connect \Y $and$issuer_ls180.v:181699$13497_Y + connect \Y $and$libresoc.v:50264$2091_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181701$13499 + cell $and $and$libresoc.v:50266$2093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378608,10 +142260,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$175 - connect \Y $and$issuer_ls180.v:181701$13499_Y + connect \Y $and$libresoc.v:50266$2093_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181704$13502 + cell $and $and$libresoc.v:50269$2096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378619,10 +142271,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$179 - connect \Y $and$issuer_ls180.v:181704$13502_Y + connect \Y $and$libresoc.v:50269$2096_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181706$13504 + cell $and $and$libresoc.v:50271$2098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378630,10 +142282,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$183 - connect \Y $and$issuer_ls180.v:181706$13504_Y + connect \Y $and$libresoc.v:50271$2098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181708$13506 + cell $and $and$libresoc.v:50273$2100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378641,10 +142293,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$187 - connect \Y $and$issuer_ls180.v:181708$13506_Y + connect \Y $and$libresoc.v:50273$2100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181710$13508 + cell $and $and$libresoc.v:50275$2102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378652,10 +142304,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$191 - connect \Y $and$issuer_ls180.v:181710$13508_Y + connect \Y $and$libresoc.v:50275$2102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181712$13510 + cell $and $and$libresoc.v:50277$2104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378663,10 +142315,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$195 - connect \Y $and$issuer_ls180.v:181712$13510_Y + connect \Y $and$libresoc.v:50277$2104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181715$13513 + cell $and $and$libresoc.v:50280$2107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378674,10 +142326,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$199 - connect \Y $and$issuer_ls180.v:181715$13513_Y + connect \Y $and$libresoc.v:50280$2107_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" - cell $and $and$issuer_ls180.v:181739$13537 + cell $and $and$libresoc.v:50304$2131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378685,10 +142337,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__cyc connect \B \ics_wb__stb - connect \Y $and$issuer_ls180.v:181739$13537_Y + connect \Y $and$libresoc.v:50304$2131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" - cell $and $and$issuer_ls180.v:181747$13545 + cell $and $and$libresoc.v:50312$2139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378696,10 +142348,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \wb_valid connect \B \ics_wb__we - connect \Y $and$issuer_ls180.v:181747$13545_Y + connect \Y $and$libresoc.v:50312$2139_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181749$13547 + cell $and $and$libresoc.v:50314$2141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378707,10 +142359,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$75 - connect \Y $and$issuer_ls180.v:181749$13547_Y + connect \Y $and$libresoc.v:50314$2141_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181751$13549 + cell $and $and$libresoc.v:50316$2143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378718,10 +142370,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$79 - connect \Y $and$issuer_ls180.v:181751$13549_Y + connect \Y $and$libresoc.v:50316$2143_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181753$13551 + cell $and $and$libresoc.v:50318$2145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378729,10 +142381,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$83 - connect \Y $and$issuer_ls180.v:181753$13551_Y + connect \Y $and$libresoc.v:50318$2145_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181756$13554 + cell $and $and$libresoc.v:50321$2148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378740,10 +142392,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$87 - connect \Y $and$issuer_ls180.v:181756$13554_Y + connect \Y $and$libresoc.v:50321$2148_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181758$13556 + cell $and $and$libresoc.v:50323$2150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378751,10 +142403,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$91 - connect \Y $and$issuer_ls180.v:181758$13556_Y + connect \Y $and$libresoc.v:50323$2150_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$issuer_ls180.v:181760$13558 + cell $and $and$libresoc.v:50325$2152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -378762,10 +142414,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$95 - connect \Y $and$issuer_ls180.v:181760$13558_Y + connect \Y $and$libresoc.v:50325$2152_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$issuer_ls180.v:181674$13472 + cell $eq $eq$libresoc.v:50239$2066 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -378773,10 +142425,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B 8'11111111 - connect \Y $eq$issuer_ls180.v:181674$13472_Y + connect \Y $eq$libresoc.v:50239$2066_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$issuer_ls180.v:181696$13494 + cell $eq $eq$libresoc.v:50261$2088 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -378784,10 +142436,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B 8'11111111 - connect \Y $eq$issuer_ls180.v:181696$13494_Y + connect \Y $eq$libresoc.v:50261$2088_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" - cell $eq $eq$issuer_ls180.v:181713$13511 + cell $eq $eq$libresoc.v:50278$2105 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -378795,10 +142447,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 1'0 - connect \Y $eq$issuer_ls180.v:181713$13511_Y + connect \Y $eq$libresoc.v:50278$2105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$issuer_ls180.v:181716$13514 + cell $eq $eq$libresoc.v:50281$2108 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -378806,10 +142458,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \cur_pri15 connect \B 8'11111111 - connect \Y $eq$issuer_ls180.v:181716$13514_Y + connect \Y $eq$libresoc.v:50281$2108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$issuer_ls180.v:181718$13516 + cell $eq $eq$libresoc.v:50283$2110 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -378817,10 +142469,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B 8'11111111 - connect \Y $eq$issuer_ls180.v:181718$13516_Y + connect \Y $eq$libresoc.v:50283$2110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$issuer_ls180.v:181720$13518 + cell $eq $eq$libresoc.v:50285$2112 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -378828,10 +142480,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B 8'11111111 - connect \Y $eq$issuer_ls180.v:181720$13518_Y + connect \Y $eq$libresoc.v:50285$2112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$issuer_ls180.v:181722$13520 + cell $eq $eq$libresoc.v:50287$2114 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -378839,10 +142491,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B 8'11111111 - connect \Y $eq$issuer_ls180.v:181722$13520_Y + connect \Y $eq$libresoc.v:50287$2114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$issuer_ls180.v:181724$13522 + cell $eq $eq$libresoc.v:50289$2116 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -378850,10 +142502,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B 8'11111111 - connect \Y $eq$issuer_ls180.v:181724$13522_Y + connect \Y $eq$libresoc.v:50289$2116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$issuer_ls180.v:181726$13524 + cell $eq $eq$libresoc.v:50291$2118 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -378861,10 +142513,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B 8'11111111 - connect \Y $eq$issuer_ls180.v:181726$13524_Y + connect \Y $eq$libresoc.v:50291$2118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" - cell $eq $eq$issuer_ls180.v:181728$13526 + cell $eq $eq$libresoc.v:50293$2120 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -378872,10 +142524,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 3'100 - connect \Y $eq$issuer_ls180.v:181728$13526_Y + connect \Y $eq$libresoc.v:50293$2120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$issuer_ls180.v:181729$13527 + cell $eq $eq$libresoc.v:50294$2121 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -378883,10 +142535,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B 8'11111111 - connect \Y $eq$issuer_ls180.v:181729$13527_Y + connect \Y $eq$libresoc.v:50294$2121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$issuer_ls180.v:181731$13529 + cell $eq $eq$libresoc.v:50296$2123 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -378894,10 +142546,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B 8'11111111 - connect \Y $eq$issuer_ls180.v:181731$13529_Y + connect \Y $eq$libresoc.v:50296$2123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$issuer_ls180.v:181733$13531 + cell $eq $eq$libresoc.v:50298$2125 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -378905,10 +142557,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B 8'11111111 - connect \Y $eq$issuer_ls180.v:181733$13531_Y + connect \Y $eq$libresoc.v:50298$2125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$issuer_ls180.v:181735$13533 + cell $eq $eq$libresoc.v:50300$2127 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -378916,10 +142568,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B 8'11111111 - connect \Y $eq$issuer_ls180.v:181735$13533_Y + connect \Y $eq$libresoc.v:50300$2127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$issuer_ls180.v:181737$13535 + cell $eq $eq$libresoc.v:50302$2129 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -378927,10 +142579,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B 8'11111111 - connect \Y $eq$issuer_ls180.v:181737$13535_Y + connect \Y $eq$libresoc.v:50302$2129_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$issuer_ls180.v:181740$13538 + cell $eq $eq$libresoc.v:50305$2132 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -378938,10 +142590,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B 8'11111111 - connect \Y $eq$issuer_ls180.v:181740$13538_Y + connect \Y $eq$libresoc.v:50305$2132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$issuer_ls180.v:181742$13540 + cell $eq $eq$libresoc.v:50307$2134 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -378949,10 +142601,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B 8'11111111 - connect \Y $eq$issuer_ls180.v:181742$13540_Y + connect \Y $eq$libresoc.v:50307$2134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$issuer_ls180.v:181744$13542 + cell $eq $eq$libresoc.v:50309$2136 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -378960,10 +142612,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B 8'11111111 - connect \Y $eq$issuer_ls180.v:181744$13542_Y + connect \Y $eq$libresoc.v:50309$2136_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$issuer_ls180.v:181755$13553 + cell $eq $eq$libresoc.v:50320$2147 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -378971,10 +142623,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B 8'11111111 - connect \Y $eq$issuer_ls180.v:181755$13553_Y + connect \Y $eq$libresoc.v:50320$2147_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181659$13457 + cell $lt $lt$libresoc.v:50224$2051 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -378982,10 +142634,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$issuer_ls180.v:181659$13457_Y + connect \Y $lt$libresoc.v:50224$2051_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181661$13459 + cell $lt $lt$libresoc.v:50226$2053 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -378993,10 +142645,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$issuer_ls180.v:181661$13459_Y + connect \Y $lt$libresoc.v:50226$2053_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181663$13461 + cell $lt $lt$libresoc.v:50228$2055 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379004,10 +142656,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$issuer_ls180.v:181663$13461_Y + connect \Y $lt$libresoc.v:50228$2055_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181665$13463 + cell $lt $lt$libresoc.v:50230$2057 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379015,10 +142667,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$issuer_ls180.v:181665$13463_Y + connect \Y $lt$libresoc.v:50230$2057_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181667$13465 + cell $lt $lt$libresoc.v:50232$2059 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379026,10 +142678,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$issuer_ls180.v:181667$13465_Y + connect \Y $lt$libresoc.v:50232$2059_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181669$13467 + cell $lt $lt$libresoc.v:50234$2061 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379037,10 +142689,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$issuer_ls180.v:181669$13467_Y + connect \Y $lt$libresoc.v:50234$2061_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181671$13469 + cell $lt $lt$libresoc.v:50236$2063 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379048,10 +142700,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$issuer_ls180.v:181671$13469_Y + connect \Y $lt$libresoc.v:50236$2063_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181673$13471 + cell $lt $lt$libresoc.v:50238$2065 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379059,10 +142711,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$issuer_ls180.v:181673$13471_Y + connect \Y $lt$libresoc.v:50238$2065_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181676$13474 + cell $lt $lt$libresoc.v:50241$2068 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379070,10 +142722,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$issuer_ls180.v:181676$13474_Y + connect \Y $lt$libresoc.v:50241$2068_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181678$13476 + cell $lt $lt$libresoc.v:50243$2070 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379081,10 +142733,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$issuer_ls180.v:181678$13476_Y + connect \Y $lt$libresoc.v:50243$2070_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181681$13479 + cell $lt $lt$libresoc.v:50246$2073 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379092,10 +142744,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$issuer_ls180.v:181681$13479_Y + connect \Y $lt$libresoc.v:50246$2073_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181683$13481 + cell $lt $lt$libresoc.v:50248$2075 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379103,10 +142755,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$issuer_ls180.v:181683$13481_Y + connect \Y $lt$libresoc.v:50248$2075_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181685$13483 + cell $lt $lt$libresoc.v:50250$2077 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379114,10 +142766,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$issuer_ls180.v:181685$13483_Y + connect \Y $lt$libresoc.v:50250$2077_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181687$13485 + cell $lt $lt$libresoc.v:50252$2079 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379125,10 +142777,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$issuer_ls180.v:181687$13485_Y + connect \Y $lt$libresoc.v:50252$2079_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181689$13487 + cell $lt $lt$libresoc.v:50254$2081 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379136,10 +142788,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$issuer_ls180.v:181689$13487_Y + connect \Y $lt$libresoc.v:50254$2081_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181691$13489 + cell $lt $lt$libresoc.v:50256$2083 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379147,10 +142799,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$issuer_ls180.v:181691$13489_Y + connect \Y $lt$libresoc.v:50256$2083_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181693$13491 + cell $lt $lt$libresoc.v:50258$2085 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379158,10 +142810,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$issuer_ls180.v:181693$13491_Y + connect \Y $lt$libresoc.v:50258$2085_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181695$13493 + cell $lt $lt$libresoc.v:50260$2087 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379169,10 +142821,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$issuer_ls180.v:181695$13493_Y + connect \Y $lt$libresoc.v:50260$2087_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181698$13496 + cell $lt $lt$libresoc.v:50263$2090 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379180,10 +142832,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$issuer_ls180.v:181698$13496_Y + connect \Y $lt$libresoc.v:50263$2090_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181700$13498 + cell $lt $lt$libresoc.v:50265$2092 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379191,10 +142843,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$issuer_ls180.v:181700$13498_Y + connect \Y $lt$libresoc.v:50265$2092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181703$13501 + cell $lt $lt$libresoc.v:50268$2095 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379202,10 +142854,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$issuer_ls180.v:181703$13501_Y + connect \Y $lt$libresoc.v:50268$2095_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181705$13503 + cell $lt $lt$libresoc.v:50270$2097 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379213,10 +142865,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$issuer_ls180.v:181705$13503_Y + connect \Y $lt$libresoc.v:50270$2097_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181707$13505 + cell $lt $lt$libresoc.v:50272$2099 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379224,10 +142876,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$issuer_ls180.v:181707$13505_Y + connect \Y $lt$libresoc.v:50272$2099_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181709$13507 + cell $lt $lt$libresoc.v:50274$2101 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379235,10 +142887,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$issuer_ls180.v:181709$13507_Y + connect \Y $lt$libresoc.v:50274$2101_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181711$13509 + cell $lt $lt$libresoc.v:50276$2103 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379246,10 +142898,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$issuer_ls180.v:181711$13509_Y + connect \Y $lt$libresoc.v:50276$2103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181714$13512 + cell $lt $lt$libresoc.v:50279$2106 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379257,10 +142909,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$issuer_ls180.v:181714$13512_Y + connect \Y $lt$libresoc.v:50279$2106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181748$13546 + cell $lt $lt$libresoc.v:50313$2140 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379268,10 +142920,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$issuer_ls180.v:181748$13546_Y + connect \Y $lt$libresoc.v:50313$2140_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181750$13548 + cell $lt $lt$libresoc.v:50315$2142 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379279,10 +142931,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$issuer_ls180.v:181750$13548_Y + connect \Y $lt$libresoc.v:50315$2142_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181752$13550 + cell $lt $lt$libresoc.v:50317$2144 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379290,10 +142942,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$issuer_ls180.v:181752$13550_Y + connect \Y $lt$libresoc.v:50317$2144_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181754$13552 + cell $lt $lt$libresoc.v:50319$2146 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379301,10 +142953,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$issuer_ls180.v:181754$13552_Y + connect \Y $lt$libresoc.v:50319$2146_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181757$13555 + cell $lt $lt$libresoc.v:50322$2149 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379312,10 +142964,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$issuer_ls180.v:181757$13555_Y + connect \Y $lt$libresoc.v:50322$2149_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$issuer_ls180.v:181759$13557 + cell $lt $lt$libresoc.v:50324$2151 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -379323,10 +142975,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$issuer_ls180.v:181759$13557_Y + connect \Y $lt$libresoc.v:50324$2151_Y end - attribute \src "issuer_ls180.v:181746.18-181746.40" - cell $shr $shr$issuer_ls180.v:181746$13544 + attribute \src "libresoc.v:50311.18-50311.40" + cell $shr $shr$libresoc.v:50311$2138 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -379334,469 +142986,469 @@ module \xics_ics parameter \Y_WIDTH 16 connect \A \int_level_l connect \B \reg_idx - connect \Y $shr$issuer_ls180.v:181746$13544_Y + connect \Y $shr$libresoc.v:50311$2138_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$issuer_ls180.v:181658$13456 + cell $mux $ternary$libresoc.v:50223$2050 parameter \WIDTH 8 connect \A \xive0_pri connect \B 8'11111111 connect \S \$8 - connect \Y $ternary$issuer_ls180.v:181658$13456_Y + connect \Y $ternary$libresoc.v:50223$2050_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$issuer_ls180.v:181680$13478 + cell $mux $ternary$libresoc.v:50245$2072 parameter \WIDTH 8 connect \A \xive1_pri connect \B 8'11111111 connect \S \$12 - connect \Y $ternary$issuer_ls180.v:181680$13478_Y + connect \Y $ternary$libresoc.v:50245$2072_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$issuer_ls180.v:181702$13500 + cell $mux $ternary$libresoc.v:50267$2094 parameter \WIDTH 8 connect \A \xive2_pri connect \B 8'11111111 connect \S \$16 - connect \Y $ternary$issuer_ls180.v:181702$13500_Y + connect \Y $ternary$libresoc.v:50267$2094_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$issuer_ls180.v:181717$13515 + cell $mux $ternary$libresoc.v:50282$2109 parameter \WIDTH 8 connect \A \cur_pri15 connect \B 8'11111111 connect \S \$204 - connect \Y $ternary$issuer_ls180.v:181717$13515_Y + connect \Y $ternary$libresoc.v:50282$2109_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$issuer_ls180.v:181719$13517 + cell $mux $ternary$libresoc.v:50284$2111 parameter \WIDTH 8 connect \A \xive3_pri connect \B 8'11111111 connect \S \$20 - connect \Y $ternary$issuer_ls180.v:181719$13517_Y + connect \Y $ternary$libresoc.v:50284$2111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$issuer_ls180.v:181721$13519 + cell $mux $ternary$libresoc.v:50286$2113 parameter \WIDTH 8 connect \A \xive4_pri connect \B 8'11111111 connect \S \$24 - connect \Y $ternary$issuer_ls180.v:181721$13519_Y + connect \Y $ternary$libresoc.v:50286$2113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$issuer_ls180.v:181723$13521 + cell $mux $ternary$libresoc.v:50288$2115 parameter \WIDTH 8 connect \A \xive5_pri connect \B 8'11111111 connect \S \$28 - connect \Y $ternary$issuer_ls180.v:181723$13521_Y + connect \Y $ternary$libresoc.v:50288$2115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$issuer_ls180.v:181725$13523 + cell $mux $ternary$libresoc.v:50290$2117 parameter \WIDTH 8 connect \A \xive6_pri connect \B 8'11111111 connect \S \$32 - connect \Y $ternary$issuer_ls180.v:181725$13523_Y + connect \Y $ternary$libresoc.v:50290$2117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$issuer_ls180.v:181727$13525 + cell $mux $ternary$libresoc.v:50292$2119 parameter \WIDTH 8 connect \A \xive7_pri connect \B 8'11111111 connect \S \$36 - connect \Y $ternary$issuer_ls180.v:181727$13525_Y + connect \Y $ternary$libresoc.v:50292$2119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$issuer_ls180.v:181730$13528 + cell $mux $ternary$libresoc.v:50295$2122 parameter \WIDTH 8 connect \A \xive8_pri connect \B 8'11111111 connect \S \$40 - connect \Y $ternary$issuer_ls180.v:181730$13528_Y + connect \Y $ternary$libresoc.v:50295$2122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$issuer_ls180.v:181732$13530 + cell $mux $ternary$libresoc.v:50297$2124 parameter \WIDTH 8 connect \A \xive9_pri connect \B 8'11111111 connect \S \$44 - connect \Y $ternary$issuer_ls180.v:181732$13530_Y + connect \Y $ternary$libresoc.v:50297$2124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$issuer_ls180.v:181734$13532 + cell $mux $ternary$libresoc.v:50299$2126 parameter \WIDTH 8 connect \A \xive10_pri connect \B 8'11111111 connect \S \$48 - connect \Y $ternary$issuer_ls180.v:181734$13532_Y + connect \Y $ternary$libresoc.v:50299$2126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$issuer_ls180.v:181736$13534 + cell $mux $ternary$libresoc.v:50301$2128 parameter \WIDTH 8 connect \A \xive11_pri connect \B 8'11111111 connect \S \$52 - connect \Y $ternary$issuer_ls180.v:181736$13534_Y + connect \Y $ternary$libresoc.v:50301$2128_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$issuer_ls180.v:181738$13536 + cell $mux $ternary$libresoc.v:50303$2130 parameter \WIDTH 8 connect \A \xive12_pri connect \B 8'11111111 connect \S \$56 - connect \Y $ternary$issuer_ls180.v:181738$13536_Y + connect \Y $ternary$libresoc.v:50303$2130_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$issuer_ls180.v:181741$13539 + cell $mux $ternary$libresoc.v:50306$2133 parameter \WIDTH 8 connect \A \xive13_pri connect \B 8'11111111 connect \S \$60 - connect \Y $ternary$issuer_ls180.v:181741$13539_Y + connect \Y $ternary$libresoc.v:50306$2133_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$issuer_ls180.v:181743$13541 + cell $mux $ternary$libresoc.v:50308$2135 parameter \WIDTH 8 connect \A \xive14_pri connect \B 8'11111111 connect \S \$64 - connect \Y $ternary$issuer_ls180.v:181743$13541_Y + connect \Y $ternary$libresoc.v:50308$2135_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$issuer_ls180.v:181745$13543 + cell $mux $ternary$libresoc.v:50310$2137 parameter \WIDTH 8 connect \A \xive15_pri connect \B 8'11111111 connect \S \$68 - connect \Y $ternary$issuer_ls180.v:181745$13543_Y + connect \Y $ternary$libresoc.v:50310$2137_Y end - attribute \src "issuer_ls180.v:181259.7-181259.20" - process $proc$issuer_ls180.v:181259$13704 + attribute \src "libresoc.v:49824.7-49824.20" + process $proc$libresoc.v:49824$2298 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "issuer_ls180.v:181540.13-181540.30" - process $proc$issuer_ls180.v:181540$13705 + attribute \src "libresoc.v:50105.13-50105.30" + process $proc$libresoc.v:50105$2299 assign { } { } assign $1\icp_o_pri[7:0] 8'00000000 sync always sync init update \icp_o_pri $1\icp_o_pri[7:0] end - attribute \src "issuer_ls180.v:181545.13-181545.29" - process $proc$issuer_ls180.v:181545$13706 + attribute \src "libresoc.v:50110.13-50110.29" + process $proc$libresoc.v:50110$2300 assign { } { } assign $1\icp_o_src[3:0] 4'0000 sync always sync init update \icp_o_src $1\icp_o_src[3:0] end - attribute \src "issuer_ls180.v:181554.7-181554.25" - process $proc$issuer_ls180.v:181554$13707 + attribute \src "libresoc.v:50119.7-50119.25" + process $proc$libresoc.v:50119$2301 assign { } { } assign $1\ics_wb__ack[0:0] 1'0 sync always sync init update \ics_wb__ack $1\ics_wb__ack[0:0] end - attribute \src "issuer_ls180.v:181563.14-181563.35" - process $proc$issuer_ls180.v:181563$13708 + attribute \src "libresoc.v:50128.14-50128.35" + process $proc$libresoc.v:50128$2302 assign { } { } assign $1\ics_wb__dat_r[31:0] 0 sync always sync init update \ics_wb__dat_r $1\ics_wb__dat_r[31:0] end - attribute \src "issuer_ls180.v:181575.14-181575.36" - process $proc$issuer_ls180.v:181575$13709 + attribute \src "libresoc.v:50140.14-50140.36" + process $proc$libresoc.v:50140$2303 assign { } { } assign $1\int_level_l[15:0] 16'0000000000000000 sync always sync init update \int_level_l $1\int_level_l[15:0] end - attribute \src "issuer_ls180.v:181595.13-181595.30" - process $proc$issuer_ls180.v:181595$13710 + attribute \src "libresoc.v:50160.13-50160.30" + process $proc$libresoc.v:50160$2304 assign { } { } assign $1\xive0_pri[7:0] 8'11111111 sync always sync init update \xive0_pri $1\xive0_pri[7:0] end - attribute \src "issuer_ls180.v:181599.13-181599.31" - process $proc$issuer_ls180.v:181599$13711 + attribute \src "libresoc.v:50164.13-50164.31" + process $proc$libresoc.v:50164$2305 assign { } { } assign $1\xive10_pri[7:0] 8'11111111 sync always sync init update \xive10_pri $1\xive10_pri[7:0] end - attribute \src "issuer_ls180.v:181603.13-181603.31" - process $proc$issuer_ls180.v:181603$13712 + attribute \src "libresoc.v:50168.13-50168.31" + process $proc$libresoc.v:50168$2306 assign { } { } assign $1\xive11_pri[7:0] 8'11111111 sync always sync init update \xive11_pri $1\xive11_pri[7:0] end - attribute \src "issuer_ls180.v:181607.13-181607.31" - process $proc$issuer_ls180.v:181607$13713 + attribute \src "libresoc.v:50172.13-50172.31" + process $proc$libresoc.v:50172$2307 assign { } { } assign $1\xive12_pri[7:0] 8'11111111 sync always sync init update \xive12_pri $1\xive12_pri[7:0] end - attribute \src "issuer_ls180.v:181611.13-181611.31" - process $proc$issuer_ls180.v:181611$13714 + attribute \src "libresoc.v:50176.13-50176.31" + process $proc$libresoc.v:50176$2308 assign { } { } assign $1\xive13_pri[7:0] 8'11111111 sync always sync init update \xive13_pri $1\xive13_pri[7:0] end - attribute \src "issuer_ls180.v:181615.13-181615.31" - process $proc$issuer_ls180.v:181615$13715 + attribute \src "libresoc.v:50180.13-50180.31" + process $proc$libresoc.v:50180$2309 assign { } { } assign $1\xive14_pri[7:0] 8'11111111 sync always sync init update \xive14_pri $1\xive14_pri[7:0] end - attribute \src "issuer_ls180.v:181619.13-181619.31" - process $proc$issuer_ls180.v:181619$13716 + attribute \src "libresoc.v:50184.13-50184.31" + process $proc$libresoc.v:50184$2310 assign { } { } assign $1\xive15_pri[7:0] 8'11111111 sync always sync init update \xive15_pri $1\xive15_pri[7:0] end - attribute \src "issuer_ls180.v:181623.13-181623.30" - process $proc$issuer_ls180.v:181623$13717 + attribute \src "libresoc.v:50188.13-50188.30" + process $proc$libresoc.v:50188$2311 assign { } { } assign $1\xive1_pri[7:0] 8'11111111 sync always sync init update \xive1_pri $1\xive1_pri[7:0] end - attribute \src "issuer_ls180.v:181627.13-181627.30" - process $proc$issuer_ls180.v:181627$13718 + attribute \src "libresoc.v:50192.13-50192.30" + process $proc$libresoc.v:50192$2312 assign { } { } assign $1\xive2_pri[7:0] 8'11111111 sync always sync init update \xive2_pri $1\xive2_pri[7:0] end - attribute \src "issuer_ls180.v:181631.13-181631.30" - process $proc$issuer_ls180.v:181631$13719 + attribute \src "libresoc.v:50196.13-50196.30" + process $proc$libresoc.v:50196$2313 assign { } { } assign $1\xive3_pri[7:0] 8'11111111 sync always sync init update \xive3_pri $1\xive3_pri[7:0] end - attribute \src "issuer_ls180.v:181635.13-181635.30" - process $proc$issuer_ls180.v:181635$13720 + attribute \src "libresoc.v:50200.13-50200.30" + process $proc$libresoc.v:50200$2314 assign { } { } assign $1\xive4_pri[7:0] 8'11111111 sync always sync init update \xive4_pri $1\xive4_pri[7:0] end - attribute \src "issuer_ls180.v:181639.13-181639.30" - process $proc$issuer_ls180.v:181639$13721 + attribute \src "libresoc.v:50204.13-50204.30" + process $proc$libresoc.v:50204$2315 assign { } { } assign $1\xive5_pri[7:0] 8'11111111 sync always sync init update \xive5_pri $1\xive5_pri[7:0] end - attribute \src "issuer_ls180.v:181643.13-181643.30" - process $proc$issuer_ls180.v:181643$13722 + attribute \src "libresoc.v:50208.13-50208.30" + process $proc$libresoc.v:50208$2316 assign { } { } assign $1\xive6_pri[7:0] 8'11111111 sync always sync init update \xive6_pri $1\xive6_pri[7:0] end - attribute \src "issuer_ls180.v:181647.13-181647.30" - process $proc$issuer_ls180.v:181647$13723 + attribute \src "libresoc.v:50212.13-50212.30" + process $proc$libresoc.v:50212$2317 assign { } { } assign $1\xive7_pri[7:0] 8'11111111 sync always sync init update \xive7_pri $1\xive7_pri[7:0] end - attribute \src "issuer_ls180.v:181651.13-181651.30" - process $proc$issuer_ls180.v:181651$13724 + attribute \src "libresoc.v:50216.13-50216.30" + process $proc$libresoc.v:50216$2318 assign { } { } assign $1\xive8_pri[7:0] 8'11111111 sync always sync init update \xive8_pri $1\xive8_pri[7:0] end - attribute \src "issuer_ls180.v:181655.13-181655.30" - process $proc$issuer_ls180.v:181655$13725 + attribute \src "libresoc.v:50220.13-50220.30" + process $proc$libresoc.v:50220$2319 assign { } { } assign $1\xive9_pri[7:0] 8'11111111 sync always sync init update \xive9_pri $1\xive9_pri[7:0] end - attribute \src "issuer_ls180.v:181761.3-181762.28" - process $proc$issuer_ls180.v:181761$13559 + attribute \src "libresoc.v:50326.3-50327.28" + process $proc$libresoc.v:50326$2153 assign { } { } assign $0\icp_o_src[3:0] \cur_idx15 sync posedge \clk update \icp_o_src $0\icp_o_src[3:0] end - attribute \src "issuer_ls180.v:181763.3-181764.25" - process $proc$issuer_ls180.v:181763$13560 + attribute \src "libresoc.v:50328.3-50329.25" + process $proc$libresoc.v:50328$2154 assign { } { } assign $0\icp_o_pri[7:0] \$203 sync posedge \clk update \icp_o_pri $0\icp_o_pri[7:0] end - attribute \src "issuer_ls180.v:181765.3-181766.35" - process $proc$issuer_ls180.v:181765$13561 + attribute \src "libresoc.v:50330.3-50331.35" + process $proc$libresoc.v:50330$2155 assign { } { } assign $0\xive0_pri[7:0] \xive0_pri$next sync posedge \clk update \xive0_pri $0\xive0_pri[7:0] end - attribute \src "issuer_ls180.v:181767.3-181768.35" - process $proc$issuer_ls180.v:181767$13562 + attribute \src "libresoc.v:50332.3-50333.35" + process $proc$libresoc.v:50332$2156 assign { } { } assign $0\xive1_pri[7:0] \xive1_pri$next sync posedge \clk update \xive1_pri $0\xive1_pri[7:0] end - attribute \src "issuer_ls180.v:181769.3-181770.35" - process $proc$issuer_ls180.v:181769$13563 + attribute \src "libresoc.v:50334.3-50335.35" + process $proc$libresoc.v:50334$2157 assign { } { } assign $0\xive2_pri[7:0] \xive2_pri$next sync posedge \clk update \xive2_pri $0\xive2_pri[7:0] end - attribute \src "issuer_ls180.v:181771.3-181772.35" - process $proc$issuer_ls180.v:181771$13564 + attribute \src "libresoc.v:50336.3-50337.35" + process $proc$libresoc.v:50336$2158 assign { } { } assign $0\xive3_pri[7:0] \xive3_pri$next sync posedge \clk update \xive3_pri $0\xive3_pri[7:0] end - attribute \src "issuer_ls180.v:181773.3-181774.35" - process $proc$issuer_ls180.v:181773$13565 + attribute \src "libresoc.v:50338.3-50339.35" + process $proc$libresoc.v:50338$2159 assign { } { } assign $0\xive4_pri[7:0] \xive4_pri$next sync posedge \clk update \xive4_pri $0\xive4_pri[7:0] end - attribute \src "issuer_ls180.v:181775.3-181776.35" - process $proc$issuer_ls180.v:181775$13566 + attribute \src "libresoc.v:50340.3-50341.35" + process $proc$libresoc.v:50340$2160 assign { } { } assign $0\xive5_pri[7:0] \xive5_pri$next sync posedge \clk update \xive5_pri $0\xive5_pri[7:0] end - attribute \src "issuer_ls180.v:181777.3-181778.35" - process $proc$issuer_ls180.v:181777$13567 + attribute \src "libresoc.v:50342.3-50343.35" + process $proc$libresoc.v:50342$2161 assign { } { } assign $0\xive6_pri[7:0] \xive6_pri$next sync posedge \clk update \xive6_pri $0\xive6_pri[7:0] end - attribute \src "issuer_ls180.v:181779.3-181780.35" - process $proc$issuer_ls180.v:181779$13568 + attribute \src "libresoc.v:50344.3-50345.35" + process $proc$libresoc.v:50344$2162 assign { } { } assign $0\xive7_pri[7:0] \xive7_pri$next sync posedge \clk update \xive7_pri $0\xive7_pri[7:0] end - attribute \src "issuer_ls180.v:181781.3-181782.35" - process $proc$issuer_ls180.v:181781$13569 + attribute \src "libresoc.v:50346.3-50347.35" + process $proc$libresoc.v:50346$2163 assign { } { } assign $0\xive8_pri[7:0] \xive8_pri$next sync posedge \clk update \xive8_pri $0\xive8_pri[7:0] end - attribute \src "issuer_ls180.v:181783.3-181784.35" - process $proc$issuer_ls180.v:181783$13570 + attribute \src "libresoc.v:50348.3-50349.35" + process $proc$libresoc.v:50348$2164 assign { } { } assign $0\xive9_pri[7:0] \xive9_pri$next sync posedge \clk update \xive9_pri $0\xive9_pri[7:0] end - attribute \src "issuer_ls180.v:181785.3-181786.37" - process $proc$issuer_ls180.v:181785$13571 + attribute \src "libresoc.v:50350.3-50351.37" + process $proc$libresoc.v:50350$2165 assign { } { } assign $0\xive10_pri[7:0] \xive10_pri$next sync posedge \clk update \xive10_pri $0\xive10_pri[7:0] end - attribute \src "issuer_ls180.v:181787.3-181788.37" - process $proc$issuer_ls180.v:181787$13572 + attribute \src "libresoc.v:50352.3-50353.37" + process $proc$libresoc.v:50352$2166 assign { } { } assign $0\xive11_pri[7:0] \xive11_pri$next sync posedge \clk update \xive11_pri $0\xive11_pri[7:0] end - attribute \src "issuer_ls180.v:181789.3-181790.37" - process $proc$issuer_ls180.v:181789$13573 + attribute \src "libresoc.v:50354.3-50355.37" + process $proc$libresoc.v:50354$2167 assign { } { } assign $0\xive12_pri[7:0] \xive12_pri$next sync posedge \clk update \xive12_pri $0\xive12_pri[7:0] end - attribute \src "issuer_ls180.v:181791.3-181792.37" - process $proc$issuer_ls180.v:181791$13574 + attribute \src "libresoc.v:50356.3-50357.37" + process $proc$libresoc.v:50356$2168 assign { } { } assign $0\xive13_pri[7:0] \xive13_pri$next sync posedge \clk update \xive13_pri $0\xive13_pri[7:0] end - attribute \src "issuer_ls180.v:181793.3-181794.37" - process $proc$issuer_ls180.v:181793$13575 + attribute \src "libresoc.v:50358.3-50359.37" + process $proc$libresoc.v:50358$2169 assign { } { } assign $0\xive14_pri[7:0] \xive14_pri$next sync posedge \clk update \xive14_pri $0\xive14_pri[7:0] end - attribute \src "issuer_ls180.v:181795.3-181796.37" - process $proc$issuer_ls180.v:181795$13576 + attribute \src "libresoc.v:50360.3-50361.37" + process $proc$libresoc.v:50360$2170 assign { } { } assign $0\xive15_pri[7:0] \xive15_pri$next sync posedge \clk update \xive15_pri $0\xive15_pri[7:0] end - attribute \src "issuer_ls180.v:181797.3-181798.39" - process $proc$issuer_ls180.v:181797$13577 + attribute \src "libresoc.v:50362.3-50363.39" + process $proc$libresoc.v:50362$2171 assign { } { } assign $0\ics_wb__ack[0:0] \ics_wb__ack$next sync posedge \clk update \ics_wb__ack $0\ics_wb__ack[0:0] end - attribute \src "issuer_ls180.v:181799.3-181800.43" - process $proc$issuer_ls180.v:181799$13578 + attribute \src "libresoc.v:50364.3-50365.43" + process $proc$libresoc.v:50364$2172 assign { } { } assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next sync posedge \clk update \ics_wb__dat_r $0\ics_wb__dat_r[31:0] end - attribute \src "issuer_ls180.v:181801.3-181802.39" - process $proc$issuer_ls180.v:181801$13579 + attribute \src "libresoc.v:50366.3-50367.39" + process $proc$libresoc.v:50366$2173 assign { } { } assign $0\int_level_l[15:0] \int_level_l$next sync posedge \clk update \int_level_l $0\int_level_l[15:0] end - attribute \src "issuer_ls180.v:181803.3-181888.6" - process $proc$issuer_ls180.v:181803$13580 + attribute \src "libresoc.v:50368.3-50453.6" + process $proc$libresoc.v:50368$2174 assign { } { } assign { } { } assign { } { } @@ -379845,31 +143497,31 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $0\xive0_pri$next[7:0]$13581 $4\xive0_pri$next[7:0]$13645 - assign $0\xive10_pri$next[7:0]$13582 $4\xive10_pri$next[7:0]$13646 - assign $0\xive11_pri$next[7:0]$13583 $4\xive11_pri$next[7:0]$13647 - assign $0\xive12_pri$next[7:0]$13584 $4\xive12_pri$next[7:0]$13648 - assign $0\xive13_pri$next[7:0]$13585 $4\xive13_pri$next[7:0]$13649 - assign $0\xive14_pri$next[7:0]$13586 $4\xive14_pri$next[7:0]$13650 - assign $0\xive15_pri$next[7:0]$13587 $4\xive15_pri$next[7:0]$13651 - assign $0\xive1_pri$next[7:0]$13588 $4\xive1_pri$next[7:0]$13652 - assign $0\xive2_pri$next[7:0]$13589 $4\xive2_pri$next[7:0]$13653 - assign $0\xive3_pri$next[7:0]$13590 $4\xive3_pri$next[7:0]$13654 - assign $0\xive4_pri$next[7:0]$13591 $4\xive4_pri$next[7:0]$13655 - assign $0\xive5_pri$next[7:0]$13592 $4\xive5_pri$next[7:0]$13656 - assign $0\xive6_pri$next[7:0]$13593 $4\xive6_pri$next[7:0]$13657 - assign $0\xive7_pri$next[7:0]$13594 $4\xive7_pri$next[7:0]$13658 - assign $0\xive8_pri$next[7:0]$13595 $4\xive8_pri$next[7:0]$13659 - assign $0\xive9_pri$next[7:0]$13596 $4\xive9_pri$next[7:0]$13660 - attribute \src "issuer_ls180.v:181804.5-181804.29" + assign $0\xive0_pri$next[7:0]$2175 $4\xive0_pri$next[7:0]$2239 + assign $0\xive10_pri$next[7:0]$2176 $4\xive10_pri$next[7:0]$2240 + assign $0\xive11_pri$next[7:0]$2177 $4\xive11_pri$next[7:0]$2241 + assign $0\xive12_pri$next[7:0]$2178 $4\xive12_pri$next[7:0]$2242 + assign $0\xive13_pri$next[7:0]$2179 $4\xive13_pri$next[7:0]$2243 + assign $0\xive14_pri$next[7:0]$2180 $4\xive14_pri$next[7:0]$2244 + assign $0\xive15_pri$next[7:0]$2181 $4\xive15_pri$next[7:0]$2245 + assign $0\xive1_pri$next[7:0]$2182 $4\xive1_pri$next[7:0]$2246 + assign $0\xive2_pri$next[7:0]$2183 $4\xive2_pri$next[7:0]$2247 + assign $0\xive3_pri$next[7:0]$2184 $4\xive3_pri$next[7:0]$2248 + assign $0\xive4_pri$next[7:0]$2185 $4\xive4_pri$next[7:0]$2249 + assign $0\xive5_pri$next[7:0]$2186 $4\xive5_pri$next[7:0]$2250 + assign $0\xive6_pri$next[7:0]$2187 $4\xive6_pri$next[7:0]$2251 + assign $0\xive7_pri$next[7:0]$2188 $4\xive7_pri$next[7:0]$2252 + assign $0\xive8_pri$next[7:0]$2189 $4\xive8_pri$next[7:0]$2253 + assign $0\xive9_pri$next[7:0]$2190 $4\xive9_pri$next[7:0]$2254 + attribute \src "libresoc.v:50369.5-50369.29" switch \initial - attribute \src "issuer_ls180.v:181804.9-181804.17" + attribute \src "libresoc.v:50369.9-50369.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" switch \$73 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } @@ -379887,25 +143539,25 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $1\xive0_pri$next[7:0]$13597 $2\xive0_pri$next[7:0]$13613 - assign $1\xive10_pri$next[7:0]$13598 $2\xive10_pri$next[7:0]$13614 - assign $1\xive11_pri$next[7:0]$13599 $2\xive11_pri$next[7:0]$13615 - assign $1\xive12_pri$next[7:0]$13600 $2\xive12_pri$next[7:0]$13616 - assign $1\xive13_pri$next[7:0]$13601 $2\xive13_pri$next[7:0]$13617 - assign $1\xive14_pri$next[7:0]$13602 $2\xive14_pri$next[7:0]$13618 - assign $1\xive15_pri$next[7:0]$13603 $2\xive15_pri$next[7:0]$13619 - assign $1\xive1_pri$next[7:0]$13604 $2\xive1_pri$next[7:0]$13620 - assign $1\xive2_pri$next[7:0]$13605 $2\xive2_pri$next[7:0]$13621 - assign $1\xive3_pri$next[7:0]$13606 $2\xive3_pri$next[7:0]$13622 - assign $1\xive4_pri$next[7:0]$13607 $2\xive4_pri$next[7:0]$13623 - assign $1\xive5_pri$next[7:0]$13608 $2\xive5_pri$next[7:0]$13624 - assign $1\xive6_pri$next[7:0]$13609 $2\xive6_pri$next[7:0]$13625 - assign $1\xive7_pri$next[7:0]$13610 $2\xive7_pri$next[7:0]$13626 - assign $1\xive8_pri$next[7:0]$13611 $2\xive8_pri$next[7:0]$13627 - assign $1\xive9_pri$next[7:0]$13612 $2\xive9_pri$next[7:0]$13628 + assign $1\xive0_pri$next[7:0]$2191 $2\xive0_pri$next[7:0]$2207 + assign $1\xive10_pri$next[7:0]$2192 $2\xive10_pri$next[7:0]$2208 + assign $1\xive11_pri$next[7:0]$2193 $2\xive11_pri$next[7:0]$2209 + assign $1\xive12_pri$next[7:0]$2194 $2\xive12_pri$next[7:0]$2210 + assign $1\xive13_pri$next[7:0]$2195 $2\xive13_pri$next[7:0]$2211 + assign $1\xive14_pri$next[7:0]$2196 $2\xive14_pri$next[7:0]$2212 + assign $1\xive15_pri$next[7:0]$2197 $2\xive15_pri$next[7:0]$2213 + assign $1\xive1_pri$next[7:0]$2198 $2\xive1_pri$next[7:0]$2214 + assign $1\xive2_pri$next[7:0]$2199 $2\xive2_pri$next[7:0]$2215 + assign $1\xive3_pri$next[7:0]$2200 $2\xive3_pri$next[7:0]$2216 + assign $1\xive4_pri$next[7:0]$2201 $2\xive4_pri$next[7:0]$2217 + assign $1\xive5_pri$next[7:0]$2202 $2\xive5_pri$next[7:0]$2218 + assign $1\xive6_pri$next[7:0]$2203 $2\xive6_pri$next[7:0]$2219 + assign $1\xive7_pri$next[7:0]$2204 $2\xive7_pri$next[7:0]$2220 + assign $1\xive8_pri$next[7:0]$2205 $2\xive8_pri$next[7:0]$2221 + assign $1\xive9_pri$next[7:0]$2206 $2\xive9_pri$next[7:0]$2222 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" switch \reg_is_xive - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } @@ -379923,385 +143575,385 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $2\xive0_pri$next[7:0]$13613 $3\xive0_pri$next[7:0]$13629 - assign $2\xive10_pri$next[7:0]$13614 $3\xive10_pri$next[7:0]$13630 - assign $2\xive11_pri$next[7:0]$13615 $3\xive11_pri$next[7:0]$13631 - assign $2\xive12_pri$next[7:0]$13616 $3\xive12_pri$next[7:0]$13632 - assign $2\xive13_pri$next[7:0]$13617 $3\xive13_pri$next[7:0]$13633 - assign $2\xive14_pri$next[7:0]$13618 $3\xive14_pri$next[7:0]$13634 - assign $2\xive15_pri$next[7:0]$13619 $3\xive15_pri$next[7:0]$13635 - assign $2\xive1_pri$next[7:0]$13620 $3\xive1_pri$next[7:0]$13636 - assign $2\xive2_pri$next[7:0]$13621 $3\xive2_pri$next[7:0]$13637 - assign $2\xive3_pri$next[7:0]$13622 $3\xive3_pri$next[7:0]$13638 - assign $2\xive4_pri$next[7:0]$13623 $3\xive4_pri$next[7:0]$13639 - assign $2\xive5_pri$next[7:0]$13624 $3\xive5_pri$next[7:0]$13640 - assign $2\xive6_pri$next[7:0]$13625 $3\xive6_pri$next[7:0]$13641 - assign $2\xive7_pri$next[7:0]$13626 $3\xive7_pri$next[7:0]$13642 - assign $2\xive8_pri$next[7:0]$13627 $3\xive8_pri$next[7:0]$13643 - assign $2\xive9_pri$next[7:0]$13628 $3\xive9_pri$next[7:0]$13644 + assign $2\xive0_pri$next[7:0]$2207 $3\xive0_pri$next[7:0]$2223 + assign $2\xive10_pri$next[7:0]$2208 $3\xive10_pri$next[7:0]$2224 + assign $2\xive11_pri$next[7:0]$2209 $3\xive11_pri$next[7:0]$2225 + assign $2\xive12_pri$next[7:0]$2210 $3\xive12_pri$next[7:0]$2226 + assign $2\xive13_pri$next[7:0]$2211 $3\xive13_pri$next[7:0]$2227 + assign $2\xive14_pri$next[7:0]$2212 $3\xive14_pri$next[7:0]$2228 + assign $2\xive15_pri$next[7:0]$2213 $3\xive15_pri$next[7:0]$2229 + assign $2\xive1_pri$next[7:0]$2214 $3\xive1_pri$next[7:0]$2230 + assign $2\xive2_pri$next[7:0]$2215 $3\xive2_pri$next[7:0]$2231 + assign $2\xive3_pri$next[7:0]$2216 $3\xive3_pri$next[7:0]$2232 + assign $2\xive4_pri$next[7:0]$2217 $3\xive4_pri$next[7:0]$2233 + assign $2\xive5_pri$next[7:0]$2218 $3\xive5_pri$next[7:0]$2234 + assign $2\xive6_pri$next[7:0]$2219 $3\xive6_pri$next[7:0]$2235 + assign $2\xive7_pri$next[7:0]$2220 $3\xive7_pri$next[7:0]$2236 + assign $2\xive8_pri$next[7:0]$2221 $3\xive8_pri$next[7:0]$2237 + assign $2\xive9_pri$next[7:0]$2222 $3\xive9_pri$next[7:0]$2238 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345" switch \reg_idx - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $3\xive10_pri$next[7:0]$13630 \xive10_pri - assign $3\xive11_pri$next[7:0]$13631 \xive11_pri - assign $3\xive12_pri$next[7:0]$13632 \xive12_pri - assign $3\xive13_pri$next[7:0]$13633 \xive13_pri - assign $3\xive14_pri$next[7:0]$13634 \xive14_pri - assign $3\xive15_pri$next[7:0]$13635 \xive15_pri - assign $3\xive1_pri$next[7:0]$13636 \xive1_pri - assign $3\xive2_pri$next[7:0]$13637 \xive2_pri - assign $3\xive3_pri$next[7:0]$13638 \xive3_pri - assign $3\xive4_pri$next[7:0]$13639 \xive4_pri - assign $3\xive5_pri$next[7:0]$13640 \xive5_pri - assign $3\xive6_pri$next[7:0]$13641 \xive6_pri - assign $3\xive7_pri$next[7:0]$13642 \xive7_pri - assign $3\xive8_pri$next[7:0]$13643 \xive8_pri - assign $3\xive9_pri$next[7:0]$13644 \xive9_pri - assign $3\xive0_pri$next[7:0]$13629 \be_in [7:0] - attribute \src "issuer_ls180.v:0.0-0.0" + assign $3\xive10_pri$next[7:0]$2224 \xive10_pri + assign $3\xive11_pri$next[7:0]$2225 \xive11_pri + assign $3\xive12_pri$next[7:0]$2226 \xive12_pri + assign $3\xive13_pri$next[7:0]$2227 \xive13_pri + assign $3\xive14_pri$next[7:0]$2228 \xive14_pri + assign $3\xive15_pri$next[7:0]$2229 \xive15_pri + assign $3\xive1_pri$next[7:0]$2230 \xive1_pri + assign $3\xive2_pri$next[7:0]$2231 \xive2_pri + assign $3\xive3_pri$next[7:0]$2232 \xive3_pri + assign $3\xive4_pri$next[7:0]$2233 \xive4_pri + assign $3\xive5_pri$next[7:0]$2234 \xive5_pri + assign $3\xive6_pri$next[7:0]$2235 \xive6_pri + assign $3\xive7_pri$next[7:0]$2236 \xive7_pri + assign $3\xive8_pri$next[7:0]$2237 \xive8_pri + assign $3\xive9_pri$next[7:0]$2238 \xive9_pri + assign $3\xive0_pri$next[7:0]$2223 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" case 4'0001 - assign $3\xive0_pri$next[7:0]$13629 \xive0_pri - assign $3\xive10_pri$next[7:0]$13630 \xive10_pri - assign $3\xive11_pri$next[7:0]$13631 \xive11_pri - assign $3\xive12_pri$next[7:0]$13632 \xive12_pri - assign $3\xive13_pri$next[7:0]$13633 \xive13_pri - assign $3\xive14_pri$next[7:0]$13634 \xive14_pri - assign $3\xive15_pri$next[7:0]$13635 \xive15_pri + assign $3\xive0_pri$next[7:0]$2223 \xive0_pri + assign $3\xive10_pri$next[7:0]$2224 \xive10_pri + assign $3\xive11_pri$next[7:0]$2225 \xive11_pri + assign $3\xive12_pri$next[7:0]$2226 \xive12_pri + assign $3\xive13_pri$next[7:0]$2227 \xive13_pri + assign $3\xive14_pri$next[7:0]$2228 \xive14_pri + assign $3\xive15_pri$next[7:0]$2229 \xive15_pri assign { } { } - assign $3\xive2_pri$next[7:0]$13637 \xive2_pri - assign $3\xive3_pri$next[7:0]$13638 \xive3_pri - assign $3\xive4_pri$next[7:0]$13639 \xive4_pri - assign $3\xive5_pri$next[7:0]$13640 \xive5_pri - assign $3\xive6_pri$next[7:0]$13641 \xive6_pri - assign $3\xive7_pri$next[7:0]$13642 \xive7_pri - assign $3\xive8_pri$next[7:0]$13643 \xive8_pri - assign $3\xive9_pri$next[7:0]$13644 \xive9_pri - assign $3\xive1_pri$next[7:0]$13636 \be_in [7:0] - attribute \src "issuer_ls180.v:0.0-0.0" + assign $3\xive2_pri$next[7:0]$2231 \xive2_pri + assign $3\xive3_pri$next[7:0]$2232 \xive3_pri + assign $3\xive4_pri$next[7:0]$2233 \xive4_pri + assign $3\xive5_pri$next[7:0]$2234 \xive5_pri + assign $3\xive6_pri$next[7:0]$2235 \xive6_pri + assign $3\xive7_pri$next[7:0]$2236 \xive7_pri + assign $3\xive8_pri$next[7:0]$2237 \xive8_pri + assign $3\xive9_pri$next[7:0]$2238 \xive9_pri + assign $3\xive1_pri$next[7:0]$2230 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" case 4'0010 - assign $3\xive0_pri$next[7:0]$13629 \xive0_pri - assign $3\xive10_pri$next[7:0]$13630 \xive10_pri - assign $3\xive11_pri$next[7:0]$13631 \xive11_pri - assign $3\xive12_pri$next[7:0]$13632 \xive12_pri - assign $3\xive13_pri$next[7:0]$13633 \xive13_pri - assign $3\xive14_pri$next[7:0]$13634 \xive14_pri - assign $3\xive15_pri$next[7:0]$13635 \xive15_pri - assign $3\xive1_pri$next[7:0]$13636 \xive1_pri + assign $3\xive0_pri$next[7:0]$2223 \xive0_pri + assign $3\xive10_pri$next[7:0]$2224 \xive10_pri + assign $3\xive11_pri$next[7:0]$2225 \xive11_pri + assign $3\xive12_pri$next[7:0]$2226 \xive12_pri + assign $3\xive13_pri$next[7:0]$2227 \xive13_pri + assign $3\xive14_pri$next[7:0]$2228 \xive14_pri + assign $3\xive15_pri$next[7:0]$2229 \xive15_pri + assign $3\xive1_pri$next[7:0]$2230 \xive1_pri assign { } { } - assign $3\xive3_pri$next[7:0]$13638 \xive3_pri - assign $3\xive4_pri$next[7:0]$13639 \xive4_pri - assign $3\xive5_pri$next[7:0]$13640 \xive5_pri - assign $3\xive6_pri$next[7:0]$13641 \xive6_pri - assign $3\xive7_pri$next[7:0]$13642 \xive7_pri - assign $3\xive8_pri$next[7:0]$13643 \xive8_pri - assign $3\xive9_pri$next[7:0]$13644 \xive9_pri - assign $3\xive2_pri$next[7:0]$13637 \be_in [7:0] - attribute \src "issuer_ls180.v:0.0-0.0" + assign $3\xive3_pri$next[7:0]$2232 \xive3_pri + assign $3\xive4_pri$next[7:0]$2233 \xive4_pri + assign $3\xive5_pri$next[7:0]$2234 \xive5_pri + assign $3\xive6_pri$next[7:0]$2235 \xive6_pri + assign $3\xive7_pri$next[7:0]$2236 \xive7_pri + assign $3\xive8_pri$next[7:0]$2237 \xive8_pri + assign $3\xive9_pri$next[7:0]$2238 \xive9_pri + assign $3\xive2_pri$next[7:0]$2231 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" case 4'0011 - assign $3\xive0_pri$next[7:0]$13629 \xive0_pri - assign $3\xive10_pri$next[7:0]$13630 \xive10_pri - assign $3\xive11_pri$next[7:0]$13631 \xive11_pri - assign $3\xive12_pri$next[7:0]$13632 \xive12_pri - assign $3\xive13_pri$next[7:0]$13633 \xive13_pri - assign $3\xive14_pri$next[7:0]$13634 \xive14_pri - assign $3\xive15_pri$next[7:0]$13635 \xive15_pri - assign $3\xive1_pri$next[7:0]$13636 \xive1_pri - assign $3\xive2_pri$next[7:0]$13637 \xive2_pri + assign $3\xive0_pri$next[7:0]$2223 \xive0_pri + assign $3\xive10_pri$next[7:0]$2224 \xive10_pri + assign $3\xive11_pri$next[7:0]$2225 \xive11_pri + assign $3\xive12_pri$next[7:0]$2226 \xive12_pri + assign $3\xive13_pri$next[7:0]$2227 \xive13_pri + assign $3\xive14_pri$next[7:0]$2228 \xive14_pri + assign $3\xive15_pri$next[7:0]$2229 \xive15_pri + assign $3\xive1_pri$next[7:0]$2230 \xive1_pri + assign $3\xive2_pri$next[7:0]$2231 \xive2_pri assign { } { } - assign $3\xive4_pri$next[7:0]$13639 \xive4_pri - assign $3\xive5_pri$next[7:0]$13640 \xive5_pri - assign $3\xive6_pri$next[7:0]$13641 \xive6_pri - assign $3\xive7_pri$next[7:0]$13642 \xive7_pri - assign $3\xive8_pri$next[7:0]$13643 \xive8_pri - assign $3\xive9_pri$next[7:0]$13644 \xive9_pri - assign $3\xive3_pri$next[7:0]$13638 \be_in [7:0] - attribute \src "issuer_ls180.v:0.0-0.0" + assign $3\xive4_pri$next[7:0]$2233 \xive4_pri + assign $3\xive5_pri$next[7:0]$2234 \xive5_pri + assign $3\xive6_pri$next[7:0]$2235 \xive6_pri + assign $3\xive7_pri$next[7:0]$2236 \xive7_pri + assign $3\xive8_pri$next[7:0]$2237 \xive8_pri + assign $3\xive9_pri$next[7:0]$2238 \xive9_pri + assign $3\xive3_pri$next[7:0]$2232 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" case 4'0100 - assign $3\xive0_pri$next[7:0]$13629 \xive0_pri - assign $3\xive10_pri$next[7:0]$13630 \xive10_pri - assign $3\xive11_pri$next[7:0]$13631 \xive11_pri - assign $3\xive12_pri$next[7:0]$13632 \xive12_pri - assign $3\xive13_pri$next[7:0]$13633 \xive13_pri - assign $3\xive14_pri$next[7:0]$13634 \xive14_pri - assign $3\xive15_pri$next[7:0]$13635 \xive15_pri - assign $3\xive1_pri$next[7:0]$13636 \xive1_pri - assign $3\xive2_pri$next[7:0]$13637 \xive2_pri - assign $3\xive3_pri$next[7:0]$13638 \xive3_pri + assign $3\xive0_pri$next[7:0]$2223 \xive0_pri + assign $3\xive10_pri$next[7:0]$2224 \xive10_pri + assign $3\xive11_pri$next[7:0]$2225 \xive11_pri + assign $3\xive12_pri$next[7:0]$2226 \xive12_pri + assign $3\xive13_pri$next[7:0]$2227 \xive13_pri + assign $3\xive14_pri$next[7:0]$2228 \xive14_pri + assign $3\xive15_pri$next[7:0]$2229 \xive15_pri + assign $3\xive1_pri$next[7:0]$2230 \xive1_pri + assign $3\xive2_pri$next[7:0]$2231 \xive2_pri + assign $3\xive3_pri$next[7:0]$2232 \xive3_pri assign { } { } - assign $3\xive5_pri$next[7:0]$13640 \xive5_pri - assign $3\xive6_pri$next[7:0]$13641 \xive6_pri - assign $3\xive7_pri$next[7:0]$13642 \xive7_pri - assign $3\xive8_pri$next[7:0]$13643 \xive8_pri - assign $3\xive9_pri$next[7:0]$13644 \xive9_pri - assign $3\xive4_pri$next[7:0]$13639 \be_in [7:0] - attribute \src "issuer_ls180.v:0.0-0.0" + assign $3\xive5_pri$next[7:0]$2234 \xive5_pri + assign $3\xive6_pri$next[7:0]$2235 \xive6_pri + assign $3\xive7_pri$next[7:0]$2236 \xive7_pri + assign $3\xive8_pri$next[7:0]$2237 \xive8_pri + assign $3\xive9_pri$next[7:0]$2238 \xive9_pri + assign $3\xive4_pri$next[7:0]$2233 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" case 4'0101 - assign $3\xive0_pri$next[7:0]$13629 \xive0_pri - assign $3\xive10_pri$next[7:0]$13630 \xive10_pri - assign $3\xive11_pri$next[7:0]$13631 \xive11_pri - assign $3\xive12_pri$next[7:0]$13632 \xive12_pri - assign $3\xive13_pri$next[7:0]$13633 \xive13_pri - assign $3\xive14_pri$next[7:0]$13634 \xive14_pri - assign $3\xive15_pri$next[7:0]$13635 \xive15_pri - assign $3\xive1_pri$next[7:0]$13636 \xive1_pri - assign $3\xive2_pri$next[7:0]$13637 \xive2_pri - assign $3\xive3_pri$next[7:0]$13638 \xive3_pri - assign $3\xive4_pri$next[7:0]$13639 \xive4_pri + assign $3\xive0_pri$next[7:0]$2223 \xive0_pri + assign $3\xive10_pri$next[7:0]$2224 \xive10_pri + assign $3\xive11_pri$next[7:0]$2225 \xive11_pri + assign $3\xive12_pri$next[7:0]$2226 \xive12_pri + assign $3\xive13_pri$next[7:0]$2227 \xive13_pri + assign $3\xive14_pri$next[7:0]$2228 \xive14_pri + assign $3\xive15_pri$next[7:0]$2229 \xive15_pri + assign $3\xive1_pri$next[7:0]$2230 \xive1_pri + assign $3\xive2_pri$next[7:0]$2231 \xive2_pri + assign $3\xive3_pri$next[7:0]$2232 \xive3_pri + assign $3\xive4_pri$next[7:0]$2233 \xive4_pri assign { } { } - assign $3\xive6_pri$next[7:0]$13641 \xive6_pri - assign $3\xive7_pri$next[7:0]$13642 \xive7_pri - assign $3\xive8_pri$next[7:0]$13643 \xive8_pri - assign $3\xive9_pri$next[7:0]$13644 \xive9_pri - assign $3\xive5_pri$next[7:0]$13640 \be_in [7:0] - attribute \src "issuer_ls180.v:0.0-0.0" + assign $3\xive6_pri$next[7:0]$2235 \xive6_pri + assign $3\xive7_pri$next[7:0]$2236 \xive7_pri + assign $3\xive8_pri$next[7:0]$2237 \xive8_pri + assign $3\xive9_pri$next[7:0]$2238 \xive9_pri + assign $3\xive5_pri$next[7:0]$2234 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" case 4'0110 - assign $3\xive0_pri$next[7:0]$13629 \xive0_pri - assign $3\xive10_pri$next[7:0]$13630 \xive10_pri - assign $3\xive11_pri$next[7:0]$13631 \xive11_pri - assign $3\xive12_pri$next[7:0]$13632 \xive12_pri - assign $3\xive13_pri$next[7:0]$13633 \xive13_pri - assign $3\xive14_pri$next[7:0]$13634 \xive14_pri - assign $3\xive15_pri$next[7:0]$13635 \xive15_pri - assign $3\xive1_pri$next[7:0]$13636 \xive1_pri - assign $3\xive2_pri$next[7:0]$13637 \xive2_pri - assign $3\xive3_pri$next[7:0]$13638 \xive3_pri - assign $3\xive4_pri$next[7:0]$13639 \xive4_pri - assign $3\xive5_pri$next[7:0]$13640 \xive5_pri + assign $3\xive0_pri$next[7:0]$2223 \xive0_pri + assign $3\xive10_pri$next[7:0]$2224 \xive10_pri + assign $3\xive11_pri$next[7:0]$2225 \xive11_pri + assign $3\xive12_pri$next[7:0]$2226 \xive12_pri + assign $3\xive13_pri$next[7:0]$2227 \xive13_pri + assign $3\xive14_pri$next[7:0]$2228 \xive14_pri + assign $3\xive15_pri$next[7:0]$2229 \xive15_pri + assign $3\xive1_pri$next[7:0]$2230 \xive1_pri + assign $3\xive2_pri$next[7:0]$2231 \xive2_pri + assign $3\xive3_pri$next[7:0]$2232 \xive3_pri + assign $3\xive4_pri$next[7:0]$2233 \xive4_pri + assign $3\xive5_pri$next[7:0]$2234 \xive5_pri assign { } { } - assign $3\xive7_pri$next[7:0]$13642 \xive7_pri - assign $3\xive8_pri$next[7:0]$13643 \xive8_pri - assign $3\xive9_pri$next[7:0]$13644 \xive9_pri - assign $3\xive6_pri$next[7:0]$13641 \be_in [7:0] - attribute \src "issuer_ls180.v:0.0-0.0" + assign $3\xive7_pri$next[7:0]$2236 \xive7_pri + assign $3\xive8_pri$next[7:0]$2237 \xive8_pri + assign $3\xive9_pri$next[7:0]$2238 \xive9_pri + assign $3\xive6_pri$next[7:0]$2235 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" case 4'0111 - assign $3\xive0_pri$next[7:0]$13629 \xive0_pri - assign $3\xive10_pri$next[7:0]$13630 \xive10_pri - assign $3\xive11_pri$next[7:0]$13631 \xive11_pri - assign $3\xive12_pri$next[7:0]$13632 \xive12_pri - assign $3\xive13_pri$next[7:0]$13633 \xive13_pri - assign $3\xive14_pri$next[7:0]$13634 \xive14_pri - assign $3\xive15_pri$next[7:0]$13635 \xive15_pri - assign $3\xive1_pri$next[7:0]$13636 \xive1_pri - assign $3\xive2_pri$next[7:0]$13637 \xive2_pri - assign $3\xive3_pri$next[7:0]$13638 \xive3_pri - assign $3\xive4_pri$next[7:0]$13639 \xive4_pri - assign $3\xive5_pri$next[7:0]$13640 \xive5_pri - assign $3\xive6_pri$next[7:0]$13641 \xive6_pri + assign $3\xive0_pri$next[7:0]$2223 \xive0_pri + assign $3\xive10_pri$next[7:0]$2224 \xive10_pri + assign $3\xive11_pri$next[7:0]$2225 \xive11_pri + assign $3\xive12_pri$next[7:0]$2226 \xive12_pri + assign $3\xive13_pri$next[7:0]$2227 \xive13_pri + assign $3\xive14_pri$next[7:0]$2228 \xive14_pri + assign $3\xive15_pri$next[7:0]$2229 \xive15_pri + assign $3\xive1_pri$next[7:0]$2230 \xive1_pri + assign $3\xive2_pri$next[7:0]$2231 \xive2_pri + assign $3\xive3_pri$next[7:0]$2232 \xive3_pri + assign $3\xive4_pri$next[7:0]$2233 \xive4_pri + assign $3\xive5_pri$next[7:0]$2234 \xive5_pri + assign $3\xive6_pri$next[7:0]$2235 \xive6_pri assign { } { } - assign $3\xive8_pri$next[7:0]$13643 \xive8_pri - assign $3\xive9_pri$next[7:0]$13644 \xive9_pri - assign $3\xive7_pri$next[7:0]$13642 \be_in [7:0] - attribute \src "issuer_ls180.v:0.0-0.0" + assign $3\xive8_pri$next[7:0]$2237 \xive8_pri + assign $3\xive9_pri$next[7:0]$2238 \xive9_pri + assign $3\xive7_pri$next[7:0]$2236 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" case 4'1000 - assign $3\xive0_pri$next[7:0]$13629 \xive0_pri - assign $3\xive10_pri$next[7:0]$13630 \xive10_pri - assign $3\xive11_pri$next[7:0]$13631 \xive11_pri - assign $3\xive12_pri$next[7:0]$13632 \xive12_pri - assign $3\xive13_pri$next[7:0]$13633 \xive13_pri - assign $3\xive14_pri$next[7:0]$13634 \xive14_pri - assign $3\xive15_pri$next[7:0]$13635 \xive15_pri - assign $3\xive1_pri$next[7:0]$13636 \xive1_pri - assign $3\xive2_pri$next[7:0]$13637 \xive2_pri - assign $3\xive3_pri$next[7:0]$13638 \xive3_pri - assign $3\xive4_pri$next[7:0]$13639 \xive4_pri - assign $3\xive5_pri$next[7:0]$13640 \xive5_pri - assign $3\xive6_pri$next[7:0]$13641 \xive6_pri - assign $3\xive7_pri$next[7:0]$13642 \xive7_pri + assign $3\xive0_pri$next[7:0]$2223 \xive0_pri + assign $3\xive10_pri$next[7:0]$2224 \xive10_pri + assign $3\xive11_pri$next[7:0]$2225 \xive11_pri + assign $3\xive12_pri$next[7:0]$2226 \xive12_pri + assign $3\xive13_pri$next[7:0]$2227 \xive13_pri + assign $3\xive14_pri$next[7:0]$2228 \xive14_pri + assign $3\xive15_pri$next[7:0]$2229 \xive15_pri + assign $3\xive1_pri$next[7:0]$2230 \xive1_pri + assign $3\xive2_pri$next[7:0]$2231 \xive2_pri + assign $3\xive3_pri$next[7:0]$2232 \xive3_pri + assign $3\xive4_pri$next[7:0]$2233 \xive4_pri + assign $3\xive5_pri$next[7:0]$2234 \xive5_pri + assign $3\xive6_pri$next[7:0]$2235 \xive6_pri + assign $3\xive7_pri$next[7:0]$2236 \xive7_pri assign { } { } - assign $3\xive9_pri$next[7:0]$13644 \xive9_pri - assign $3\xive8_pri$next[7:0]$13643 \be_in [7:0] - attribute \src "issuer_ls180.v:0.0-0.0" + assign $3\xive9_pri$next[7:0]$2238 \xive9_pri + assign $3\xive8_pri$next[7:0]$2237 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" case 4'1001 - assign $3\xive0_pri$next[7:0]$13629 \xive0_pri - assign $3\xive10_pri$next[7:0]$13630 \xive10_pri - assign $3\xive11_pri$next[7:0]$13631 \xive11_pri - assign $3\xive12_pri$next[7:0]$13632 \xive12_pri - assign $3\xive13_pri$next[7:0]$13633 \xive13_pri - assign $3\xive14_pri$next[7:0]$13634 \xive14_pri - assign $3\xive15_pri$next[7:0]$13635 \xive15_pri - assign $3\xive1_pri$next[7:0]$13636 \xive1_pri - assign $3\xive2_pri$next[7:0]$13637 \xive2_pri - assign $3\xive3_pri$next[7:0]$13638 \xive3_pri - assign $3\xive4_pri$next[7:0]$13639 \xive4_pri - assign $3\xive5_pri$next[7:0]$13640 \xive5_pri - assign $3\xive6_pri$next[7:0]$13641 \xive6_pri - assign $3\xive7_pri$next[7:0]$13642 \xive7_pri - assign $3\xive8_pri$next[7:0]$13643 \xive8_pri + assign $3\xive0_pri$next[7:0]$2223 \xive0_pri + assign $3\xive10_pri$next[7:0]$2224 \xive10_pri + assign $3\xive11_pri$next[7:0]$2225 \xive11_pri + assign $3\xive12_pri$next[7:0]$2226 \xive12_pri + assign $3\xive13_pri$next[7:0]$2227 \xive13_pri + assign $3\xive14_pri$next[7:0]$2228 \xive14_pri + assign $3\xive15_pri$next[7:0]$2229 \xive15_pri + assign $3\xive1_pri$next[7:0]$2230 \xive1_pri + assign $3\xive2_pri$next[7:0]$2231 \xive2_pri + assign $3\xive3_pri$next[7:0]$2232 \xive3_pri + assign $3\xive4_pri$next[7:0]$2233 \xive4_pri + assign $3\xive5_pri$next[7:0]$2234 \xive5_pri + assign $3\xive6_pri$next[7:0]$2235 \xive6_pri + assign $3\xive7_pri$next[7:0]$2236 \xive7_pri + assign $3\xive8_pri$next[7:0]$2237 \xive8_pri assign { } { } - assign $3\xive9_pri$next[7:0]$13644 \be_in [7:0] - attribute \src "issuer_ls180.v:0.0-0.0" + assign $3\xive9_pri$next[7:0]$2238 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" case 4'1010 - assign $3\xive0_pri$next[7:0]$13629 \xive0_pri + assign $3\xive0_pri$next[7:0]$2223 \xive0_pri assign { } { } - assign $3\xive11_pri$next[7:0]$13631 \xive11_pri - assign $3\xive12_pri$next[7:0]$13632 \xive12_pri - assign $3\xive13_pri$next[7:0]$13633 \xive13_pri - assign $3\xive14_pri$next[7:0]$13634 \xive14_pri - assign $3\xive15_pri$next[7:0]$13635 \xive15_pri - assign $3\xive1_pri$next[7:0]$13636 \xive1_pri - assign $3\xive2_pri$next[7:0]$13637 \xive2_pri - assign $3\xive3_pri$next[7:0]$13638 \xive3_pri - assign $3\xive4_pri$next[7:0]$13639 \xive4_pri - assign $3\xive5_pri$next[7:0]$13640 \xive5_pri - assign $3\xive6_pri$next[7:0]$13641 \xive6_pri - assign $3\xive7_pri$next[7:0]$13642 \xive7_pri - assign $3\xive8_pri$next[7:0]$13643 \xive8_pri - assign $3\xive9_pri$next[7:0]$13644 \xive9_pri - assign $3\xive10_pri$next[7:0]$13630 \be_in [7:0] - attribute \src "issuer_ls180.v:0.0-0.0" + assign $3\xive11_pri$next[7:0]$2225 \xive11_pri + assign $3\xive12_pri$next[7:0]$2226 \xive12_pri + assign $3\xive13_pri$next[7:0]$2227 \xive13_pri + assign $3\xive14_pri$next[7:0]$2228 \xive14_pri + assign $3\xive15_pri$next[7:0]$2229 \xive15_pri + assign $3\xive1_pri$next[7:0]$2230 \xive1_pri + assign $3\xive2_pri$next[7:0]$2231 \xive2_pri + assign $3\xive3_pri$next[7:0]$2232 \xive3_pri + assign $3\xive4_pri$next[7:0]$2233 \xive4_pri + assign $3\xive5_pri$next[7:0]$2234 \xive5_pri + assign $3\xive6_pri$next[7:0]$2235 \xive6_pri + assign $3\xive7_pri$next[7:0]$2236 \xive7_pri + assign $3\xive8_pri$next[7:0]$2237 \xive8_pri + assign $3\xive9_pri$next[7:0]$2238 \xive9_pri + assign $3\xive10_pri$next[7:0]$2224 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" case 4'1011 - assign $3\xive0_pri$next[7:0]$13629 \xive0_pri - assign $3\xive10_pri$next[7:0]$13630 \xive10_pri + assign $3\xive0_pri$next[7:0]$2223 \xive0_pri + assign $3\xive10_pri$next[7:0]$2224 \xive10_pri assign { } { } - assign $3\xive12_pri$next[7:0]$13632 \xive12_pri - assign $3\xive13_pri$next[7:0]$13633 \xive13_pri - assign $3\xive14_pri$next[7:0]$13634 \xive14_pri - assign $3\xive15_pri$next[7:0]$13635 \xive15_pri - assign $3\xive1_pri$next[7:0]$13636 \xive1_pri - assign $3\xive2_pri$next[7:0]$13637 \xive2_pri - assign $3\xive3_pri$next[7:0]$13638 \xive3_pri - assign $3\xive4_pri$next[7:0]$13639 \xive4_pri - assign $3\xive5_pri$next[7:0]$13640 \xive5_pri - assign $3\xive6_pri$next[7:0]$13641 \xive6_pri - assign $3\xive7_pri$next[7:0]$13642 \xive7_pri - assign $3\xive8_pri$next[7:0]$13643 \xive8_pri - assign $3\xive9_pri$next[7:0]$13644 \xive9_pri - assign $3\xive11_pri$next[7:0]$13631 \be_in [7:0] - attribute \src "issuer_ls180.v:0.0-0.0" + assign $3\xive12_pri$next[7:0]$2226 \xive12_pri + assign $3\xive13_pri$next[7:0]$2227 \xive13_pri + assign $3\xive14_pri$next[7:0]$2228 \xive14_pri + assign $3\xive15_pri$next[7:0]$2229 \xive15_pri + assign $3\xive1_pri$next[7:0]$2230 \xive1_pri + assign $3\xive2_pri$next[7:0]$2231 \xive2_pri + assign $3\xive3_pri$next[7:0]$2232 \xive3_pri + assign $3\xive4_pri$next[7:0]$2233 \xive4_pri + assign $3\xive5_pri$next[7:0]$2234 \xive5_pri + assign $3\xive6_pri$next[7:0]$2235 \xive6_pri + assign $3\xive7_pri$next[7:0]$2236 \xive7_pri + assign $3\xive8_pri$next[7:0]$2237 \xive8_pri + assign $3\xive9_pri$next[7:0]$2238 \xive9_pri + assign $3\xive11_pri$next[7:0]$2225 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" case 4'1100 - assign $3\xive0_pri$next[7:0]$13629 \xive0_pri - assign $3\xive10_pri$next[7:0]$13630 \xive10_pri - assign $3\xive11_pri$next[7:0]$13631 \xive11_pri + assign $3\xive0_pri$next[7:0]$2223 \xive0_pri + assign $3\xive10_pri$next[7:0]$2224 \xive10_pri + assign $3\xive11_pri$next[7:0]$2225 \xive11_pri assign { } { } - assign $3\xive13_pri$next[7:0]$13633 \xive13_pri - assign $3\xive14_pri$next[7:0]$13634 \xive14_pri - assign $3\xive15_pri$next[7:0]$13635 \xive15_pri - assign $3\xive1_pri$next[7:0]$13636 \xive1_pri - assign $3\xive2_pri$next[7:0]$13637 \xive2_pri - assign $3\xive3_pri$next[7:0]$13638 \xive3_pri - assign $3\xive4_pri$next[7:0]$13639 \xive4_pri - assign $3\xive5_pri$next[7:0]$13640 \xive5_pri - assign $3\xive6_pri$next[7:0]$13641 \xive6_pri - assign $3\xive7_pri$next[7:0]$13642 \xive7_pri - assign $3\xive8_pri$next[7:0]$13643 \xive8_pri - assign $3\xive9_pri$next[7:0]$13644 \xive9_pri - assign $3\xive12_pri$next[7:0]$13632 \be_in [7:0] - attribute \src "issuer_ls180.v:0.0-0.0" + assign $3\xive13_pri$next[7:0]$2227 \xive13_pri + assign $3\xive14_pri$next[7:0]$2228 \xive14_pri + assign $3\xive15_pri$next[7:0]$2229 \xive15_pri + assign $3\xive1_pri$next[7:0]$2230 \xive1_pri + assign $3\xive2_pri$next[7:0]$2231 \xive2_pri + assign $3\xive3_pri$next[7:0]$2232 \xive3_pri + assign $3\xive4_pri$next[7:0]$2233 \xive4_pri + assign $3\xive5_pri$next[7:0]$2234 \xive5_pri + assign $3\xive6_pri$next[7:0]$2235 \xive6_pri + assign $3\xive7_pri$next[7:0]$2236 \xive7_pri + assign $3\xive8_pri$next[7:0]$2237 \xive8_pri + assign $3\xive9_pri$next[7:0]$2238 \xive9_pri + assign $3\xive12_pri$next[7:0]$2226 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" case 4'1101 - assign $3\xive0_pri$next[7:0]$13629 \xive0_pri - assign $3\xive10_pri$next[7:0]$13630 \xive10_pri - assign $3\xive11_pri$next[7:0]$13631 \xive11_pri - assign $3\xive12_pri$next[7:0]$13632 \xive12_pri + assign $3\xive0_pri$next[7:0]$2223 \xive0_pri + assign $3\xive10_pri$next[7:0]$2224 \xive10_pri + assign $3\xive11_pri$next[7:0]$2225 \xive11_pri + assign $3\xive12_pri$next[7:0]$2226 \xive12_pri assign { } { } - assign $3\xive14_pri$next[7:0]$13634 \xive14_pri - assign $3\xive15_pri$next[7:0]$13635 \xive15_pri - assign $3\xive1_pri$next[7:0]$13636 \xive1_pri - assign $3\xive2_pri$next[7:0]$13637 \xive2_pri - assign $3\xive3_pri$next[7:0]$13638 \xive3_pri - assign $3\xive4_pri$next[7:0]$13639 \xive4_pri - assign $3\xive5_pri$next[7:0]$13640 \xive5_pri - assign $3\xive6_pri$next[7:0]$13641 \xive6_pri - assign $3\xive7_pri$next[7:0]$13642 \xive7_pri - assign $3\xive8_pri$next[7:0]$13643 \xive8_pri - assign $3\xive9_pri$next[7:0]$13644 \xive9_pri - assign $3\xive13_pri$next[7:0]$13633 \be_in [7:0] - attribute \src "issuer_ls180.v:0.0-0.0" + assign $3\xive14_pri$next[7:0]$2228 \xive14_pri + assign $3\xive15_pri$next[7:0]$2229 \xive15_pri + assign $3\xive1_pri$next[7:0]$2230 \xive1_pri + assign $3\xive2_pri$next[7:0]$2231 \xive2_pri + assign $3\xive3_pri$next[7:0]$2232 \xive3_pri + assign $3\xive4_pri$next[7:0]$2233 \xive4_pri + assign $3\xive5_pri$next[7:0]$2234 \xive5_pri + assign $3\xive6_pri$next[7:0]$2235 \xive6_pri + assign $3\xive7_pri$next[7:0]$2236 \xive7_pri + assign $3\xive8_pri$next[7:0]$2237 \xive8_pri + assign $3\xive9_pri$next[7:0]$2238 \xive9_pri + assign $3\xive13_pri$next[7:0]$2227 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" case 4'1110 - assign $3\xive0_pri$next[7:0]$13629 \xive0_pri - assign $3\xive10_pri$next[7:0]$13630 \xive10_pri - assign $3\xive11_pri$next[7:0]$13631 \xive11_pri - assign $3\xive12_pri$next[7:0]$13632 \xive12_pri - assign $3\xive13_pri$next[7:0]$13633 \xive13_pri + assign $3\xive0_pri$next[7:0]$2223 \xive0_pri + assign $3\xive10_pri$next[7:0]$2224 \xive10_pri + assign $3\xive11_pri$next[7:0]$2225 \xive11_pri + assign $3\xive12_pri$next[7:0]$2226 \xive12_pri + assign $3\xive13_pri$next[7:0]$2227 \xive13_pri assign { } { } - assign $3\xive15_pri$next[7:0]$13635 \xive15_pri - assign $3\xive1_pri$next[7:0]$13636 \xive1_pri - assign $3\xive2_pri$next[7:0]$13637 \xive2_pri - assign $3\xive3_pri$next[7:0]$13638 \xive3_pri - assign $3\xive4_pri$next[7:0]$13639 \xive4_pri - assign $3\xive5_pri$next[7:0]$13640 \xive5_pri - assign $3\xive6_pri$next[7:0]$13641 \xive6_pri - assign $3\xive7_pri$next[7:0]$13642 \xive7_pri - assign $3\xive8_pri$next[7:0]$13643 \xive8_pri - assign $3\xive9_pri$next[7:0]$13644 \xive9_pri - assign $3\xive14_pri$next[7:0]$13634 \be_in [7:0] - attribute \src "issuer_ls180.v:0.0-0.0" + assign $3\xive15_pri$next[7:0]$2229 \xive15_pri + assign $3\xive1_pri$next[7:0]$2230 \xive1_pri + assign $3\xive2_pri$next[7:0]$2231 \xive2_pri + assign $3\xive3_pri$next[7:0]$2232 \xive3_pri + assign $3\xive4_pri$next[7:0]$2233 \xive4_pri + assign $3\xive5_pri$next[7:0]$2234 \xive5_pri + assign $3\xive6_pri$next[7:0]$2235 \xive6_pri + assign $3\xive7_pri$next[7:0]$2236 \xive7_pri + assign $3\xive8_pri$next[7:0]$2237 \xive8_pri + assign $3\xive9_pri$next[7:0]$2238 \xive9_pri + assign $3\xive14_pri$next[7:0]$2228 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" case 4'---- - assign $3\xive0_pri$next[7:0]$13629 \xive0_pri - assign $3\xive10_pri$next[7:0]$13630 \xive10_pri - assign $3\xive11_pri$next[7:0]$13631 \xive11_pri - assign $3\xive12_pri$next[7:0]$13632 \xive12_pri - assign $3\xive13_pri$next[7:0]$13633 \xive13_pri - assign $3\xive14_pri$next[7:0]$13634 \xive14_pri + assign $3\xive0_pri$next[7:0]$2223 \xive0_pri + assign $3\xive10_pri$next[7:0]$2224 \xive10_pri + assign $3\xive11_pri$next[7:0]$2225 \xive11_pri + assign $3\xive12_pri$next[7:0]$2226 \xive12_pri + assign $3\xive13_pri$next[7:0]$2227 \xive13_pri + assign $3\xive14_pri$next[7:0]$2228 \xive14_pri assign { } { } - assign $3\xive1_pri$next[7:0]$13636 \xive1_pri - assign $3\xive2_pri$next[7:0]$13637 \xive2_pri - assign $3\xive3_pri$next[7:0]$13638 \xive3_pri - assign $3\xive4_pri$next[7:0]$13639 \xive4_pri - assign $3\xive5_pri$next[7:0]$13640 \xive5_pri - assign $3\xive6_pri$next[7:0]$13641 \xive6_pri - assign $3\xive7_pri$next[7:0]$13642 \xive7_pri - assign $3\xive8_pri$next[7:0]$13643 \xive8_pri - assign $3\xive9_pri$next[7:0]$13644 \xive9_pri - assign $3\xive15_pri$next[7:0]$13635 \be_in [7:0] + assign $3\xive1_pri$next[7:0]$2230 \xive1_pri + assign $3\xive2_pri$next[7:0]$2231 \xive2_pri + assign $3\xive3_pri$next[7:0]$2232 \xive3_pri + assign $3\xive4_pri$next[7:0]$2233 \xive4_pri + assign $3\xive5_pri$next[7:0]$2234 \xive5_pri + assign $3\xive6_pri$next[7:0]$2235 \xive6_pri + assign $3\xive7_pri$next[7:0]$2236 \xive7_pri + assign $3\xive8_pri$next[7:0]$2237 \xive8_pri + assign $3\xive9_pri$next[7:0]$2238 \xive9_pri + assign $3\xive15_pri$next[7:0]$2229 \be_in [7:0] case - assign $3\xive0_pri$next[7:0]$13629 \xive0_pri - assign $3\xive10_pri$next[7:0]$13630 \xive10_pri - assign $3\xive11_pri$next[7:0]$13631 \xive11_pri - assign $3\xive12_pri$next[7:0]$13632 \xive12_pri - assign $3\xive13_pri$next[7:0]$13633 \xive13_pri - assign $3\xive14_pri$next[7:0]$13634 \xive14_pri - assign $3\xive15_pri$next[7:0]$13635 \xive15_pri - assign $3\xive1_pri$next[7:0]$13636 \xive1_pri - assign $3\xive2_pri$next[7:0]$13637 \xive2_pri - assign $3\xive3_pri$next[7:0]$13638 \xive3_pri - assign $3\xive4_pri$next[7:0]$13639 \xive4_pri - assign $3\xive5_pri$next[7:0]$13640 \xive5_pri - assign $3\xive6_pri$next[7:0]$13641 \xive6_pri - assign $3\xive7_pri$next[7:0]$13642 \xive7_pri - assign $3\xive8_pri$next[7:0]$13643 \xive8_pri - assign $3\xive9_pri$next[7:0]$13644 \xive9_pri + assign $3\xive0_pri$next[7:0]$2223 \xive0_pri + assign $3\xive10_pri$next[7:0]$2224 \xive10_pri + assign $3\xive11_pri$next[7:0]$2225 \xive11_pri + assign $3\xive12_pri$next[7:0]$2226 \xive12_pri + assign $3\xive13_pri$next[7:0]$2227 \xive13_pri + assign $3\xive14_pri$next[7:0]$2228 \xive14_pri + assign $3\xive15_pri$next[7:0]$2229 \xive15_pri + assign $3\xive1_pri$next[7:0]$2230 \xive1_pri + assign $3\xive2_pri$next[7:0]$2231 \xive2_pri + assign $3\xive3_pri$next[7:0]$2232 \xive3_pri + assign $3\xive4_pri$next[7:0]$2233 \xive4_pri + assign $3\xive5_pri$next[7:0]$2234 \xive5_pri + assign $3\xive6_pri$next[7:0]$2235 \xive6_pri + assign $3\xive7_pri$next[7:0]$2236 \xive7_pri + assign $3\xive8_pri$next[7:0]$2237 \xive8_pri + assign $3\xive9_pri$next[7:0]$2238 \xive9_pri end case - assign $2\xive0_pri$next[7:0]$13613 \xive0_pri - assign $2\xive10_pri$next[7:0]$13614 \xive10_pri - assign $2\xive11_pri$next[7:0]$13615 \xive11_pri - assign $2\xive12_pri$next[7:0]$13616 \xive12_pri - assign $2\xive13_pri$next[7:0]$13617 \xive13_pri - assign $2\xive14_pri$next[7:0]$13618 \xive14_pri - assign $2\xive15_pri$next[7:0]$13619 \xive15_pri - assign $2\xive1_pri$next[7:0]$13620 \xive1_pri - assign $2\xive2_pri$next[7:0]$13621 \xive2_pri - assign $2\xive3_pri$next[7:0]$13622 \xive3_pri - assign $2\xive4_pri$next[7:0]$13623 \xive4_pri - assign $2\xive5_pri$next[7:0]$13624 \xive5_pri - assign $2\xive6_pri$next[7:0]$13625 \xive6_pri - assign $2\xive7_pri$next[7:0]$13626 \xive7_pri - assign $2\xive8_pri$next[7:0]$13627 \xive8_pri - assign $2\xive9_pri$next[7:0]$13628 \xive9_pri - end - case - assign $1\xive0_pri$next[7:0]$13597 \xive0_pri - assign $1\xive10_pri$next[7:0]$13598 \xive10_pri - assign $1\xive11_pri$next[7:0]$13599 \xive11_pri - assign $1\xive12_pri$next[7:0]$13600 \xive12_pri - assign $1\xive13_pri$next[7:0]$13601 \xive13_pri - assign $1\xive14_pri$next[7:0]$13602 \xive14_pri - assign $1\xive15_pri$next[7:0]$13603 \xive15_pri - assign $1\xive1_pri$next[7:0]$13604 \xive1_pri - assign $1\xive2_pri$next[7:0]$13605 \xive2_pri - assign $1\xive3_pri$next[7:0]$13606 \xive3_pri - assign $1\xive4_pri$next[7:0]$13607 \xive4_pri - assign $1\xive5_pri$next[7:0]$13608 \xive5_pri - assign $1\xive6_pri$next[7:0]$13609 \xive6_pri - assign $1\xive7_pri$next[7:0]$13610 \xive7_pri - assign $1\xive8_pri$next[7:0]$13611 \xive8_pri - assign $1\xive9_pri$next[7:0]$13612 \xive9_pri + assign $2\xive0_pri$next[7:0]$2207 \xive0_pri + assign $2\xive10_pri$next[7:0]$2208 \xive10_pri + assign $2\xive11_pri$next[7:0]$2209 \xive11_pri + assign $2\xive12_pri$next[7:0]$2210 \xive12_pri + assign $2\xive13_pri$next[7:0]$2211 \xive13_pri + assign $2\xive14_pri$next[7:0]$2212 \xive14_pri + assign $2\xive15_pri$next[7:0]$2213 \xive15_pri + assign $2\xive1_pri$next[7:0]$2214 \xive1_pri + assign $2\xive2_pri$next[7:0]$2215 \xive2_pri + assign $2\xive3_pri$next[7:0]$2216 \xive3_pri + assign $2\xive4_pri$next[7:0]$2217 \xive4_pri + assign $2\xive5_pri$next[7:0]$2218 \xive5_pri + assign $2\xive6_pri$next[7:0]$2219 \xive6_pri + assign $2\xive7_pri$next[7:0]$2220 \xive7_pri + assign $2\xive8_pri$next[7:0]$2221 \xive8_pri + assign $2\xive9_pri$next[7:0]$2222 \xive9_pri + end + case + assign $1\xive0_pri$next[7:0]$2191 \xive0_pri + assign $1\xive10_pri$next[7:0]$2192 \xive10_pri + assign $1\xive11_pri$next[7:0]$2193 \xive11_pri + assign $1\xive12_pri$next[7:0]$2194 \xive12_pri + assign $1\xive13_pri$next[7:0]$2195 \xive13_pri + assign $1\xive14_pri$next[7:0]$2196 \xive14_pri + assign $1\xive15_pri$next[7:0]$2197 \xive15_pri + assign $1\xive1_pri$next[7:0]$2198 \xive1_pri + assign $1\xive2_pri$next[7:0]$2199 \xive2_pri + assign $1\xive3_pri$next[7:0]$2200 \xive3_pri + assign $1\xive4_pri$next[7:0]$2201 \xive4_pri + assign $1\xive5_pri$next[7:0]$2202 \xive5_pri + assign $1\xive6_pri$next[7:0]$2203 \xive6_pri + assign $1\xive7_pri$next[7:0]$2204 \xive7_pri + assign $1\xive8_pri$next[7:0]$2205 \xive8_pri + assign $1\xive9_pri$next[7:0]$2206 \xive9_pri end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } @@ -380319,72 +143971,72 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $4\xive0_pri$next[7:0]$13645 8'11111111 - assign $4\xive1_pri$next[7:0]$13652 8'11111111 - assign $4\xive2_pri$next[7:0]$13653 8'11111111 - assign $4\xive3_pri$next[7:0]$13654 8'11111111 - assign $4\xive4_pri$next[7:0]$13655 8'11111111 - assign $4\xive5_pri$next[7:0]$13656 8'11111111 - assign $4\xive6_pri$next[7:0]$13657 8'11111111 - assign $4\xive7_pri$next[7:0]$13658 8'11111111 - assign $4\xive8_pri$next[7:0]$13659 8'11111111 - assign $4\xive9_pri$next[7:0]$13660 8'11111111 - assign $4\xive10_pri$next[7:0]$13646 8'11111111 - assign $4\xive11_pri$next[7:0]$13647 8'11111111 - assign $4\xive12_pri$next[7:0]$13648 8'11111111 - assign $4\xive13_pri$next[7:0]$13649 8'11111111 - assign $4\xive14_pri$next[7:0]$13650 8'11111111 - assign $4\xive15_pri$next[7:0]$13651 8'11111111 + assign $4\xive0_pri$next[7:0]$2239 8'11111111 + assign $4\xive1_pri$next[7:0]$2246 8'11111111 + assign $4\xive2_pri$next[7:0]$2247 8'11111111 + assign $4\xive3_pri$next[7:0]$2248 8'11111111 + assign $4\xive4_pri$next[7:0]$2249 8'11111111 + assign $4\xive5_pri$next[7:0]$2250 8'11111111 + assign $4\xive6_pri$next[7:0]$2251 8'11111111 + assign $4\xive7_pri$next[7:0]$2252 8'11111111 + assign $4\xive8_pri$next[7:0]$2253 8'11111111 + assign $4\xive9_pri$next[7:0]$2254 8'11111111 + assign $4\xive10_pri$next[7:0]$2240 8'11111111 + assign $4\xive11_pri$next[7:0]$2241 8'11111111 + assign $4\xive12_pri$next[7:0]$2242 8'11111111 + assign $4\xive13_pri$next[7:0]$2243 8'11111111 + assign $4\xive14_pri$next[7:0]$2244 8'11111111 + assign $4\xive15_pri$next[7:0]$2245 8'11111111 case - assign $4\xive0_pri$next[7:0]$13645 $1\xive0_pri$next[7:0]$13597 - assign $4\xive10_pri$next[7:0]$13646 $1\xive10_pri$next[7:0]$13598 - assign $4\xive11_pri$next[7:0]$13647 $1\xive11_pri$next[7:0]$13599 - assign $4\xive12_pri$next[7:0]$13648 $1\xive12_pri$next[7:0]$13600 - assign $4\xive13_pri$next[7:0]$13649 $1\xive13_pri$next[7:0]$13601 - assign $4\xive14_pri$next[7:0]$13650 $1\xive14_pri$next[7:0]$13602 - assign $4\xive15_pri$next[7:0]$13651 $1\xive15_pri$next[7:0]$13603 - assign $4\xive1_pri$next[7:0]$13652 $1\xive1_pri$next[7:0]$13604 - assign $4\xive2_pri$next[7:0]$13653 $1\xive2_pri$next[7:0]$13605 - assign $4\xive3_pri$next[7:0]$13654 $1\xive3_pri$next[7:0]$13606 - assign $4\xive4_pri$next[7:0]$13655 $1\xive4_pri$next[7:0]$13607 - assign $4\xive5_pri$next[7:0]$13656 $1\xive5_pri$next[7:0]$13608 - assign $4\xive6_pri$next[7:0]$13657 $1\xive6_pri$next[7:0]$13609 - assign $4\xive7_pri$next[7:0]$13658 $1\xive7_pri$next[7:0]$13610 - assign $4\xive8_pri$next[7:0]$13659 $1\xive8_pri$next[7:0]$13611 - assign $4\xive9_pri$next[7:0]$13660 $1\xive9_pri$next[7:0]$13612 + assign $4\xive0_pri$next[7:0]$2239 $1\xive0_pri$next[7:0]$2191 + assign $4\xive10_pri$next[7:0]$2240 $1\xive10_pri$next[7:0]$2192 + assign $4\xive11_pri$next[7:0]$2241 $1\xive11_pri$next[7:0]$2193 + assign $4\xive12_pri$next[7:0]$2242 $1\xive12_pri$next[7:0]$2194 + assign $4\xive13_pri$next[7:0]$2243 $1\xive13_pri$next[7:0]$2195 + assign $4\xive14_pri$next[7:0]$2244 $1\xive14_pri$next[7:0]$2196 + assign $4\xive15_pri$next[7:0]$2245 $1\xive15_pri$next[7:0]$2197 + assign $4\xive1_pri$next[7:0]$2246 $1\xive1_pri$next[7:0]$2198 + assign $4\xive2_pri$next[7:0]$2247 $1\xive2_pri$next[7:0]$2199 + assign $4\xive3_pri$next[7:0]$2248 $1\xive3_pri$next[7:0]$2200 + assign $4\xive4_pri$next[7:0]$2249 $1\xive4_pri$next[7:0]$2201 + assign $4\xive5_pri$next[7:0]$2250 $1\xive5_pri$next[7:0]$2202 + assign $4\xive6_pri$next[7:0]$2251 $1\xive6_pri$next[7:0]$2203 + assign $4\xive7_pri$next[7:0]$2252 $1\xive7_pri$next[7:0]$2204 + assign $4\xive8_pri$next[7:0]$2253 $1\xive8_pri$next[7:0]$2205 + assign $4\xive9_pri$next[7:0]$2254 $1\xive9_pri$next[7:0]$2206 end sync always - update \xive0_pri$next $0\xive0_pri$next[7:0]$13581 - update \xive10_pri$next $0\xive10_pri$next[7:0]$13582 - update \xive11_pri$next $0\xive11_pri$next[7:0]$13583 - update \xive12_pri$next $0\xive12_pri$next[7:0]$13584 - update \xive13_pri$next $0\xive13_pri$next[7:0]$13585 - update \xive14_pri$next $0\xive14_pri$next[7:0]$13586 - update \xive15_pri$next $0\xive15_pri$next[7:0]$13587 - update \xive1_pri$next $0\xive1_pri$next[7:0]$13588 - update \xive2_pri$next $0\xive2_pri$next[7:0]$13589 - update \xive3_pri$next $0\xive3_pri$next[7:0]$13590 - update \xive4_pri$next $0\xive4_pri$next[7:0]$13591 - update \xive5_pri$next $0\xive5_pri$next[7:0]$13592 - update \xive6_pri$next $0\xive6_pri$next[7:0]$13593 - update \xive7_pri$next $0\xive7_pri$next[7:0]$13594 - update \xive8_pri$next $0\xive8_pri$next[7:0]$13595 - update \xive9_pri$next $0\xive9_pri$next[7:0]$13596 + update \xive0_pri$next $0\xive0_pri$next[7:0]$2175 + update \xive10_pri$next $0\xive10_pri$next[7:0]$2176 + update \xive11_pri$next $0\xive11_pri$next[7:0]$2177 + update \xive12_pri$next $0\xive12_pri$next[7:0]$2178 + update \xive13_pri$next $0\xive13_pri$next[7:0]$2179 + update \xive14_pri$next $0\xive14_pri$next[7:0]$2180 + update \xive15_pri$next $0\xive15_pri$next[7:0]$2181 + update \xive1_pri$next $0\xive1_pri$next[7:0]$2182 + update \xive2_pri$next $0\xive2_pri$next[7:0]$2183 + update \xive3_pri$next $0\xive3_pri$next[7:0]$2184 + update \xive4_pri$next $0\xive4_pri$next[7:0]$2185 + update \xive5_pri$next $0\xive5_pri$next[7:0]$2186 + update \xive6_pri$next $0\xive6_pri$next[7:0]$2187 + update \xive7_pri$next $0\xive7_pri$next[7:0]$2188 + update \xive8_pri$next $0\xive8_pri$next[7:0]$2189 + update \xive9_pri$next $0\xive9_pri$next[7:0]$2190 end - attribute \src "issuer_ls180.v:181889.3-181898.6" - process $proc$issuer_ls180.v:181889$13661 + attribute \src "libresoc.v:50454.3-50463.6" + process $proc$libresoc.v:50454$2255 assign { } { } assign { } { } assign $0\cur_pri0[7:0] $1\cur_pri0[7:0] - attribute \src "issuer_ls180.v:181890.5-181890.29" + attribute \src "libresoc.v:50455.5-50455.29" switch \initial - attribute \src "issuer_ls180.v:181890.9-181890.17" + attribute \src "libresoc.v:50455.9-50455.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$77 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri0[7:0] \xive0_pri @@ -380394,20 +144046,20 @@ module \xics_ics sync always update \cur_pri0 $0\cur_pri0[7:0] end - attribute \src "issuer_ls180.v:181899.3-181908.6" - process $proc$issuer_ls180.v:181899$13662 + attribute \src "libresoc.v:50464.3-50473.6" + process $proc$libresoc.v:50464$2256 assign { } { } assign { } { } assign $0\cur_idx0[3:0] $1\cur_idx0[3:0] - attribute \src "issuer_ls180.v:181900.5-181900.29" + attribute \src "libresoc.v:50465.5-50465.29" switch \initial - attribute \src "issuer_ls180.v:181900.9-181900.17" + attribute \src "libresoc.v:50465.9-50465.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$81 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx0[3:0] 4'0000 @@ -380417,20 +144069,20 @@ module \xics_ics sync always update \cur_idx0 $0\cur_idx0[3:0] end - attribute \src "issuer_ls180.v:181909.3-181918.6" - process $proc$issuer_ls180.v:181909$13663 + attribute \src "libresoc.v:50474.3-50483.6" + process $proc$libresoc.v:50474$2257 assign { } { } assign { } { } assign $0\cur_pri1[7:0] $1\cur_pri1[7:0] - attribute \src "issuer_ls180.v:181910.5-181910.29" + attribute \src "libresoc.v:50475.5-50475.29" switch \initial - attribute \src "issuer_ls180.v:181910.9-181910.17" + attribute \src "libresoc.v:50475.9-50475.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$85 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri1[7:0] \xive1_pri @@ -380440,20 +144092,20 @@ module \xics_ics sync always update \cur_pri1 $0\cur_pri1[7:0] end - attribute \src "issuer_ls180.v:181919.3-181928.6" - process $proc$issuer_ls180.v:181919$13664 + attribute \src "libresoc.v:50484.3-50493.6" + process $proc$libresoc.v:50484$2258 assign { } { } assign { } { } assign $0\cur_idx1[3:0] $1\cur_idx1[3:0] - attribute \src "issuer_ls180.v:181920.5-181920.29" + attribute \src "libresoc.v:50485.5-50485.29" switch \initial - attribute \src "issuer_ls180.v:181920.9-181920.17" + attribute \src "libresoc.v:50485.9-50485.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$89 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx1[3:0] 4'0001 @@ -380463,20 +144115,20 @@ module \xics_ics sync always update \cur_idx1 $0\cur_idx1[3:0] end - attribute \src "issuer_ls180.v:181929.3-181938.6" - process $proc$issuer_ls180.v:181929$13665 + attribute \src "libresoc.v:50494.3-50503.6" + process $proc$libresoc.v:50494$2259 assign { } { } assign { } { } assign $0\cur_pri2[7:0] $1\cur_pri2[7:0] - attribute \src "issuer_ls180.v:181930.5-181930.29" + attribute \src "libresoc.v:50495.5-50495.29" switch \initial - attribute \src "issuer_ls180.v:181930.9-181930.17" + attribute \src "libresoc.v:50495.9-50495.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$93 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri2[7:0] \xive2_pri @@ -380486,20 +144138,20 @@ module \xics_ics sync always update \cur_pri2 $0\cur_pri2[7:0] end - attribute \src "issuer_ls180.v:181939.3-181948.6" - process $proc$issuer_ls180.v:181939$13666 + attribute \src "libresoc.v:50504.3-50513.6" + process $proc$libresoc.v:50504$2260 assign { } { } assign { } { } assign $0\cur_idx2[3:0] $1\cur_idx2[3:0] - attribute \src "issuer_ls180.v:181940.5-181940.29" + attribute \src "libresoc.v:50505.5-50505.29" switch \initial - attribute \src "issuer_ls180.v:181940.9-181940.17" + attribute \src "libresoc.v:50505.9-50505.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$97 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx2[3:0] 4'0010 @@ -380509,20 +144161,20 @@ module \xics_ics sync always update \cur_idx2 $0\cur_idx2[3:0] end - attribute \src "issuer_ls180.v:181949.3-181958.6" - process $proc$issuer_ls180.v:181949$13667 + attribute \src "libresoc.v:50514.3-50523.6" + process $proc$libresoc.v:50514$2261 assign { } { } assign { } { } assign $0\cur_pri3[7:0] $1\cur_pri3[7:0] - attribute \src "issuer_ls180.v:181950.5-181950.29" + attribute \src "libresoc.v:50515.5-50515.29" switch \initial - attribute \src "issuer_ls180.v:181950.9-181950.17" + attribute \src "libresoc.v:50515.9-50515.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$101 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri3[7:0] \xive3_pri @@ -380532,20 +144184,20 @@ module \xics_ics sync always update \cur_pri3 $0\cur_pri3[7:0] end - attribute \src "issuer_ls180.v:181959.3-181968.6" - process $proc$issuer_ls180.v:181959$13668 + attribute \src "libresoc.v:50524.3-50533.6" + process $proc$libresoc.v:50524$2262 assign { } { } assign { } { } assign $0\cur_idx3[3:0] $1\cur_idx3[3:0] - attribute \src "issuer_ls180.v:181960.5-181960.29" + attribute \src "libresoc.v:50525.5-50525.29" switch \initial - attribute \src "issuer_ls180.v:181960.9-181960.17" + attribute \src "libresoc.v:50525.9-50525.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$105 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx3[3:0] 4'0011 @@ -380555,20 +144207,20 @@ module \xics_ics sync always update \cur_idx3 $0\cur_idx3[3:0] end - attribute \src "issuer_ls180.v:181969.3-181978.6" - process $proc$issuer_ls180.v:181969$13669 + attribute \src "libresoc.v:50534.3-50543.6" + process $proc$libresoc.v:50534$2263 assign { } { } assign { } { } assign $0\cur_pri4[7:0] $1\cur_pri4[7:0] - attribute \src "issuer_ls180.v:181970.5-181970.29" + attribute \src "libresoc.v:50535.5-50535.29" switch \initial - attribute \src "issuer_ls180.v:181970.9-181970.17" + attribute \src "libresoc.v:50535.9-50535.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$109 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri4[7:0] \xive4_pri @@ -380578,43 +144230,43 @@ module \xics_ics sync always update \cur_pri4 $0\cur_pri4[7:0] end - attribute \src "issuer_ls180.v:181979.3-181987.6" - process $proc$issuer_ls180.v:181979$13670 + attribute \src "libresoc.v:50544.3-50552.6" + process $proc$libresoc.v:50544$2264 assign { } { } assign { } { } - assign $0\int_level_l$next[15:0]$13671 $1\int_level_l$next[15:0]$13672 - attribute \src "issuer_ls180.v:181980.5-181980.29" + assign $0\int_level_l$next[15:0]$2265 $1\int_level_l$next[15:0]$2266 + attribute \src "libresoc.v:50545.5-50545.29" switch \initial - attribute \src "issuer_ls180.v:181980.9-181980.17" + attribute \src "libresoc.v:50545.9-50545.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\int_level_l$next[15:0]$13672 16'0000000000000000 + assign $1\int_level_l$next[15:0]$2266 16'0000000000000000 case - assign $1\int_level_l$next[15:0]$13672 \int_level_i + assign $1\int_level_l$next[15:0]$2266 \int_level_i end sync always - update \int_level_l$next $0\int_level_l$next[15:0]$13671 + update \int_level_l$next $0\int_level_l$next[15:0]$2265 end - attribute \src "issuer_ls180.v:181988.3-181997.6" - process $proc$issuer_ls180.v:181988$13673 + attribute \src "libresoc.v:50553.3-50562.6" + process $proc$libresoc.v:50553$2267 assign { } { } assign { } { } assign $0\cur_idx4[3:0] $1\cur_idx4[3:0] - attribute \src "issuer_ls180.v:181989.5-181989.29" + attribute \src "libresoc.v:50554.5-50554.29" switch \initial - attribute \src "issuer_ls180.v:181989.9-181989.17" + attribute \src "libresoc.v:50554.9-50554.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$113 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx4[3:0] 4'0100 @@ -380624,20 +144276,20 @@ module \xics_ics sync always update \cur_idx4 $0\cur_idx4[3:0] end - attribute \src "issuer_ls180.v:181998.3-182007.6" - process $proc$issuer_ls180.v:181998$13674 + attribute \src "libresoc.v:50563.3-50572.6" + process $proc$libresoc.v:50563$2268 assign { } { } assign { } { } assign $0\cur_pri5[7:0] $1\cur_pri5[7:0] - attribute \src "issuer_ls180.v:181999.5-181999.29" + attribute \src "libresoc.v:50564.5-50564.29" switch \initial - attribute \src "issuer_ls180.v:181999.9-181999.17" + attribute \src "libresoc.v:50564.9-50564.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$117 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri5[7:0] \xive5_pri @@ -380647,20 +144299,20 @@ module \xics_ics sync always update \cur_pri5 $0\cur_pri5[7:0] end - attribute \src "issuer_ls180.v:182008.3-182017.6" - process $proc$issuer_ls180.v:182008$13675 + attribute \src "libresoc.v:50573.3-50582.6" + process $proc$libresoc.v:50573$2269 assign { } { } assign { } { } assign $0\cur_idx5[3:0] $1\cur_idx5[3:0] - attribute \src "issuer_ls180.v:182009.5-182009.29" + attribute \src "libresoc.v:50574.5-50574.29" switch \initial - attribute \src "issuer_ls180.v:182009.9-182009.17" + attribute \src "libresoc.v:50574.9-50574.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$121 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx5[3:0] 4'0101 @@ -380670,20 +144322,20 @@ module \xics_ics sync always update \cur_idx5 $0\cur_idx5[3:0] end - attribute \src "issuer_ls180.v:182018.3-182027.6" - process $proc$issuer_ls180.v:182018$13676 + attribute \src "libresoc.v:50583.3-50592.6" + process $proc$libresoc.v:50583$2270 assign { } { } assign { } { } assign $0\cur_pri6[7:0] $1\cur_pri6[7:0] - attribute \src "issuer_ls180.v:182019.5-182019.29" + attribute \src "libresoc.v:50584.5-50584.29" switch \initial - attribute \src "issuer_ls180.v:182019.9-182019.17" + attribute \src "libresoc.v:50584.9-50584.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$125 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri6[7:0] \xive6_pri @@ -380693,20 +144345,20 @@ module \xics_ics sync always update \cur_pri6 $0\cur_pri6[7:0] end - attribute \src "issuer_ls180.v:182028.3-182037.6" - process $proc$issuer_ls180.v:182028$13677 + attribute \src "libresoc.v:50593.3-50602.6" + process $proc$libresoc.v:50593$2271 assign { } { } assign { } { } assign $0\cur_idx6[3:0] $1\cur_idx6[3:0] - attribute \src "issuer_ls180.v:182029.5-182029.29" + attribute \src "libresoc.v:50594.5-50594.29" switch \initial - attribute \src "issuer_ls180.v:182029.9-182029.17" + attribute \src "libresoc.v:50594.9-50594.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$129 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx6[3:0] 4'0110 @@ -380716,20 +144368,20 @@ module \xics_ics sync always update \cur_idx6 $0\cur_idx6[3:0] end - attribute \src "issuer_ls180.v:182038.3-182047.6" - process $proc$issuer_ls180.v:182038$13678 + attribute \src "libresoc.v:50603.3-50612.6" + process $proc$libresoc.v:50603$2272 assign { } { } assign { } { } assign $0\cur_pri7[7:0] $1\cur_pri7[7:0] - attribute \src "issuer_ls180.v:182039.5-182039.29" + attribute \src "libresoc.v:50604.5-50604.29" switch \initial - attribute \src "issuer_ls180.v:182039.9-182039.17" + attribute \src "libresoc.v:50604.9-50604.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$133 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri7[7:0] \xive7_pri @@ -380739,20 +144391,20 @@ module \xics_ics sync always update \cur_pri7 $0\cur_pri7[7:0] end - attribute \src "issuer_ls180.v:182048.3-182057.6" - process $proc$issuer_ls180.v:182048$13679 + attribute \src "libresoc.v:50613.3-50622.6" + process $proc$libresoc.v:50613$2273 assign { } { } assign { } { } assign $0\cur_idx7[3:0] $1\cur_idx7[3:0] - attribute \src "issuer_ls180.v:182049.5-182049.29" + attribute \src "libresoc.v:50614.5-50614.29" switch \initial - attribute \src "issuer_ls180.v:182049.9-182049.17" + attribute \src "libresoc.v:50614.9-50614.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$137 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx7[3:0] 4'0111 @@ -380762,20 +144414,20 @@ module \xics_ics sync always update \cur_idx7 $0\cur_idx7[3:0] end - attribute \src "issuer_ls180.v:182058.3-182067.6" - process $proc$issuer_ls180.v:182058$13680 + attribute \src "libresoc.v:50623.3-50632.6" + process $proc$libresoc.v:50623$2274 assign { } { } assign { } { } assign $0\cur_pri8[7:0] $1\cur_pri8[7:0] - attribute \src "issuer_ls180.v:182059.5-182059.29" + attribute \src "libresoc.v:50624.5-50624.29" switch \initial - attribute \src "issuer_ls180.v:182059.9-182059.17" + attribute \src "libresoc.v:50624.9-50624.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$141 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri8[7:0] \xive8_pri @@ -380785,20 +144437,20 @@ module \xics_ics sync always update \cur_pri8 $0\cur_pri8[7:0] end - attribute \src "issuer_ls180.v:182068.3-182077.6" - process $proc$issuer_ls180.v:182068$13681 + attribute \src "libresoc.v:50633.3-50642.6" + process $proc$libresoc.v:50633$2275 assign { } { } assign { } { } assign $0\cur_idx8[3:0] $1\cur_idx8[3:0] - attribute \src "issuer_ls180.v:182069.5-182069.29" + attribute \src "libresoc.v:50634.5-50634.29" switch \initial - attribute \src "issuer_ls180.v:182069.9-182069.17" + attribute \src "libresoc.v:50634.9-50634.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$145 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx8[3:0] 4'1000 @@ -380808,20 +144460,20 @@ module \xics_ics sync always update \cur_idx8 $0\cur_idx8[3:0] end - attribute \src "issuer_ls180.v:182078.3-182087.6" - process $proc$issuer_ls180.v:182078$13682 + attribute \src "libresoc.v:50643.3-50652.6" + process $proc$libresoc.v:50643$2276 assign { } { } assign { } { } assign $0\cur_pri9[7:0] $1\cur_pri9[7:0] - attribute \src "issuer_ls180.v:182079.5-182079.29" + attribute \src "libresoc.v:50644.5-50644.29" switch \initial - attribute \src "issuer_ls180.v:182079.9-182079.17" + attribute \src "libresoc.v:50644.9-50644.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$149 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri9[7:0] \xive9_pri @@ -380831,20 +144483,20 @@ module \xics_ics sync always update \cur_pri9 $0\cur_pri9[7:0] end - attribute \src "issuer_ls180.v:182088.3-182097.6" - process $proc$issuer_ls180.v:182088$13683 + attribute \src "libresoc.v:50653.3-50662.6" + process $proc$libresoc.v:50653$2277 assign { } { } assign { } { } assign $0\cur_idx9[3:0] $1\cur_idx9[3:0] - attribute \src "issuer_ls180.v:182089.5-182089.29" + attribute \src "libresoc.v:50654.5-50654.29" switch \initial - attribute \src "issuer_ls180.v:182089.9-182089.17" + attribute \src "libresoc.v:50654.9-50654.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$153 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx9[3:0] 4'1001 @@ -380854,20 +144506,20 @@ module \xics_ics sync always update \cur_idx9 $0\cur_idx9[3:0] end - attribute \src "issuer_ls180.v:182098.3-182107.6" - process $proc$issuer_ls180.v:182098$13684 + attribute \src "libresoc.v:50663.3-50672.6" + process $proc$libresoc.v:50663$2278 assign { } { } assign { } { } assign $0\cur_pri10[7:0] $1\cur_pri10[7:0] - attribute \src "issuer_ls180.v:182099.5-182099.29" + attribute \src "libresoc.v:50664.5-50664.29" switch \initial - attribute \src "issuer_ls180.v:182099.9-182099.17" + attribute \src "libresoc.v:50664.9-50664.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$157 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri10[7:0] \xive10_pri @@ -380877,20 +144529,20 @@ module \xics_ics sync always update \cur_pri10 $0\cur_pri10[7:0] end - attribute \src "issuer_ls180.v:182108.3-182117.6" - process $proc$issuer_ls180.v:182108$13685 + attribute \src "libresoc.v:50673.3-50682.6" + process $proc$libresoc.v:50673$2279 assign { } { } assign { } { } assign $0\cur_idx10[3:0] $1\cur_idx10[3:0] - attribute \src "issuer_ls180.v:182109.5-182109.29" + attribute \src "libresoc.v:50674.5-50674.29" switch \initial - attribute \src "issuer_ls180.v:182109.9-182109.17" + attribute \src "libresoc.v:50674.9-50674.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$161 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx10[3:0] 4'1010 @@ -380900,20 +144552,20 @@ module \xics_ics sync always update \cur_idx10 $0\cur_idx10[3:0] end - attribute \src "issuer_ls180.v:182118.3-182127.6" - process $proc$issuer_ls180.v:182118$13686 + attribute \src "libresoc.v:50683.3-50692.6" + process $proc$libresoc.v:50683$2280 assign { } { } assign { } { } assign $0\cur_pri11[7:0] $1\cur_pri11[7:0] - attribute \src "issuer_ls180.v:182119.5-182119.29" + attribute \src "libresoc.v:50684.5-50684.29" switch \initial - attribute \src "issuer_ls180.v:182119.9-182119.17" + attribute \src "libresoc.v:50684.9-50684.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$165 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri11[7:0] \xive11_pri @@ -380923,20 +144575,20 @@ module \xics_ics sync always update \cur_pri11 $0\cur_pri11[7:0] end - attribute \src "issuer_ls180.v:182128.3-182137.6" - process $proc$issuer_ls180.v:182128$13687 + attribute \src "libresoc.v:50693.3-50702.6" + process $proc$libresoc.v:50693$2281 assign { } { } assign { } { } assign $0\cur_idx11[3:0] $1\cur_idx11[3:0] - attribute \src "issuer_ls180.v:182129.5-182129.29" + attribute \src "libresoc.v:50694.5-50694.29" switch \initial - attribute \src "issuer_ls180.v:182129.9-182129.17" + attribute \src "libresoc.v:50694.9-50694.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$169 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx11[3:0] 4'1011 @@ -380946,20 +144598,20 @@ module \xics_ics sync always update \cur_idx11 $0\cur_idx11[3:0] end - attribute \src "issuer_ls180.v:182138.3-182147.6" - process $proc$issuer_ls180.v:182138$13688 + attribute \src "libresoc.v:50703.3-50712.6" + process $proc$libresoc.v:50703$2282 assign { } { } assign { } { } assign $0\cur_pri12[7:0] $1\cur_pri12[7:0] - attribute \src "issuer_ls180.v:182139.5-182139.29" + attribute \src "libresoc.v:50704.5-50704.29" switch \initial - attribute \src "issuer_ls180.v:182139.9-182139.17" + attribute \src "libresoc.v:50704.9-50704.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$173 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri12[7:0] \xive12_pri @@ -380969,20 +144621,20 @@ module \xics_ics sync always update \cur_pri12 $0\cur_pri12[7:0] end - attribute \src "issuer_ls180.v:182148.3-182157.6" - process $proc$issuer_ls180.v:182148$13689 + attribute \src "libresoc.v:50713.3-50722.6" + process $proc$libresoc.v:50713$2283 assign { } { } assign { } { } assign $0\cur_idx12[3:0] $1\cur_idx12[3:0] - attribute \src "issuer_ls180.v:182149.5-182149.29" + attribute \src "libresoc.v:50714.5-50714.29" switch \initial - attribute \src "issuer_ls180.v:182149.9-182149.17" + attribute \src "libresoc.v:50714.9-50714.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$177 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx12[3:0] 4'1100 @@ -380992,20 +144644,20 @@ module \xics_ics sync always update \cur_idx12 $0\cur_idx12[3:0] end - attribute \src "issuer_ls180.v:182158.3-182167.6" - process $proc$issuer_ls180.v:182158$13690 + attribute \src "libresoc.v:50723.3-50732.6" + process $proc$libresoc.v:50723$2284 assign { } { } assign { } { } assign $0\cur_pri13[7:0] $1\cur_pri13[7:0] - attribute \src "issuer_ls180.v:182159.5-182159.29" + attribute \src "libresoc.v:50724.5-50724.29" switch \initial - attribute \src "issuer_ls180.v:182159.9-182159.17" + attribute \src "libresoc.v:50724.9-50724.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$181 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri13[7:0] \xive13_pri @@ -381015,20 +144667,20 @@ module \xics_ics sync always update \cur_pri13 $0\cur_pri13[7:0] end - attribute \src "issuer_ls180.v:182168.3-182177.6" - process $proc$issuer_ls180.v:182168$13691 + attribute \src "libresoc.v:50733.3-50742.6" + process $proc$libresoc.v:50733$2285 assign { } { } assign { } { } assign $0\cur_idx13[3:0] $1\cur_idx13[3:0] - attribute \src "issuer_ls180.v:182169.5-182169.29" + attribute \src "libresoc.v:50734.5-50734.29" switch \initial - attribute \src "issuer_ls180.v:182169.9-182169.17" + attribute \src "libresoc.v:50734.9-50734.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$185 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx13[3:0] 4'1101 @@ -381038,20 +144690,20 @@ module \xics_ics sync always update \cur_idx13 $0\cur_idx13[3:0] end - attribute \src "issuer_ls180.v:182178.3-182187.6" - process $proc$issuer_ls180.v:182178$13692 + attribute \src "libresoc.v:50743.3-50752.6" + process $proc$libresoc.v:50743$2286 assign { } { } assign { } { } assign $0\cur_pri14[7:0] $1\cur_pri14[7:0] - attribute \src "issuer_ls180.v:182179.5-182179.29" + attribute \src "libresoc.v:50744.5-50744.29" switch \initial - attribute \src "issuer_ls180.v:182179.9-182179.17" + attribute \src "libresoc.v:50744.9-50744.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$189 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri14[7:0] \xive14_pri @@ -381061,97 +144713,97 @@ module \xics_ics sync always update \cur_pri14 $0\cur_pri14[7:0] end - attribute \src "issuer_ls180.v:182188.3-182237.6" - process $proc$issuer_ls180.v:182188$13693 + attribute \src "libresoc.v:50753.3-50802.6" + process $proc$libresoc.v:50753$2287 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "issuer_ls180.v:182189.5-182189.29" + attribute \src "libresoc.v:50754.5-50754.29" switch \initial - attribute \src "issuer_ls180.v:182189.9-182189.17" + attribute \src "libresoc.v:50754.9-50754.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" switch { \reg_is_debug \reg_is_config \reg_is_xive } - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign $1\be_out[31:0] $2\be_out[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" switch \reg_idx - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$7 } - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$11 } - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$15 } - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$19 } - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$23 } - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$27 } - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$31 } - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$35 } - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$39 } - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$43 } - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 4'1010 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$47 } - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 4'1011 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$51 } - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 4'1100 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$55 } - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 4'1101 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$59 } - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 4'1110 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$63 } - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 4'---- assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$67 } case assign $2\be_out[31:0] 0 end - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } assign $1\be_out[31:0] 134217744 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } assign $1\be_out[31:0] { \icp_r_src 20'00000000000000000000 \icp_r_pri } @@ -381161,20 +144813,20 @@ module \xics_ics sync always update \be_out $0\be_out[31:0] end - attribute \src "issuer_ls180.v:182238.3-182247.6" - process $proc$issuer_ls180.v:182238$13694 + attribute \src "libresoc.v:50803.3-50812.6" + process $proc$libresoc.v:50803$2288 assign { } { } assign { } { } assign $0\cur_idx14[3:0] $1\cur_idx14[3:0] - attribute \src "issuer_ls180.v:182239.5-182239.29" + attribute \src "libresoc.v:50804.5-50804.29" switch \initial - attribute \src "issuer_ls180.v:182239.9-182239.17" + attribute \src "libresoc.v:50804.9-50804.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$193 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx14[3:0] 4'1110 @@ -381184,20 +144836,20 @@ module \xics_ics sync always update \cur_idx14 $0\cur_idx14[3:0] end - attribute \src "issuer_ls180.v:182248.3-182257.6" - process $proc$issuer_ls180.v:182248$13695 + attribute \src "libresoc.v:50813.3-50822.6" + process $proc$libresoc.v:50813$2289 assign { } { } assign { } { } assign $0\cur_pri15[7:0] $1\cur_pri15[7:0] - attribute \src "issuer_ls180.v:182249.5-182249.29" + attribute \src "libresoc.v:50814.5-50814.29" switch \initial - attribute \src "issuer_ls180.v:182249.9-182249.17" + attribute \src "libresoc.v:50814.9-50814.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$197 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri15[7:0] \xive15_pri @@ -381207,20 +144859,20 @@ module \xics_ics sync always update \cur_pri15 $0\cur_pri15[7:0] end - attribute \src "issuer_ls180.v:182258.3-182267.6" - process $proc$issuer_ls180.v:182258$13696 + attribute \src "libresoc.v:50823.3-50832.6" + process $proc$libresoc.v:50823$2290 assign { } { } assign { } { } assign $0\cur_idx15[3:0] $1\cur_idx15[3:0] - attribute \src "issuer_ls180.v:182259.5-182259.29" + attribute \src "libresoc.v:50824.5-50824.29" switch \initial - attribute \src "issuer_ls180.v:182259.9-182259.17" + attribute \src "libresoc.v:50824.9-50824.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$201 - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx15[3:0] 4'1111 @@ -381230,20 +144882,20 @@ module \xics_ics sync always update \cur_idx15 $0\cur_idx15[3:0] end - attribute \src "issuer_ls180.v:182268.3-182277.6" - process $proc$issuer_ls180.v:182268$13697 + attribute \src "libresoc.v:50833.3-50842.6" + process $proc$libresoc.v:50833$2291 assign { } { } assign { } { } assign $0\ibit[0:0] $1\ibit[0:0] - attribute \src "issuer_ls180.v:182269.5-182269.29" + attribute \src "libresoc.v:50834.5-50834.29" switch \initial - attribute \src "issuer_ls180.v:182269.9-182269.17" + attribute \src "libresoc.v:50834.9-50834.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" switch { \reg_is_debug \reg_is_config \reg_is_xive } - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign $1\ibit[0:0] \$71 @@ -381253,155 +144905,155 @@ module \xics_ics sync always update \ibit $0\ibit[0:0] end - attribute \src "issuer_ls180.v:182278.3-182286.6" - process $proc$issuer_ls180.v:182278$13698 + attribute \src "libresoc.v:50843.3-50851.6" + process $proc$libresoc.v:50843$2292 assign { } { } assign { } { } - assign $0\ics_wb__dat_r$next[31:0]$13699 $1\ics_wb__dat_r$next[31:0]$13700 - attribute \src "issuer_ls180.v:182279.5-182279.29" + assign $0\ics_wb__dat_r$next[31:0]$2293 $1\ics_wb__dat_r$next[31:0]$2294 + attribute \src "libresoc.v:50844.5-50844.29" switch \initial - attribute \src "issuer_ls180.v:182279.9-182279.17" + attribute \src "libresoc.v:50844.9-50844.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__dat_r$next[31:0]$13700 0 + assign $1\ics_wb__dat_r$next[31:0]$2294 0 case - assign $1\ics_wb__dat_r$next[31:0]$13700 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $1\ics_wb__dat_r$next[31:0]$2294 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } end sync always - update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$13699 + update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$2293 end - attribute \src "issuer_ls180.v:182287.3-182295.6" - process $proc$issuer_ls180.v:182287$13701 + attribute \src "libresoc.v:50852.3-50860.6" + process $proc$libresoc.v:50852$2295 assign { } { } assign { } { } - assign $0\ics_wb__ack$next[0:0]$13702 $1\ics_wb__ack$next[0:0]$13703 - attribute \src "issuer_ls180.v:182288.5-182288.29" + assign $0\ics_wb__ack$next[0:0]$2296 $1\ics_wb__ack$next[0:0]$2297 + attribute \src "libresoc.v:50853.5-50853.29" switch \initial - attribute \src "issuer_ls180.v:182288.9-182288.17" + attribute \src "libresoc.v:50853.9-50853.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst - attribute \src "issuer_ls180.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ics_wb__ack$next[0:0]$13703 1'0 - case - assign $1\ics_wb__ack$next[0:0]$13703 \wb_valid - end - sync always - update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$13702 - end - connect \$7 $ternary$issuer_ls180.v:181658$13456_Y - connect \$99 $lt$issuer_ls180.v:181659$13457_Y - connect \$101 $and$issuer_ls180.v:181660$13458_Y - connect \$103 $lt$issuer_ls180.v:181661$13459_Y - connect \$105 $and$issuer_ls180.v:181662$13460_Y - connect \$107 $lt$issuer_ls180.v:181663$13461_Y - connect \$109 $and$issuer_ls180.v:181664$13462_Y - connect \$111 $lt$issuer_ls180.v:181665$13463_Y - connect \$113 $and$issuer_ls180.v:181666$13464_Y - connect \$115 $lt$issuer_ls180.v:181667$13465_Y - connect \$117 $and$issuer_ls180.v:181668$13466_Y - connect \$119 $lt$issuer_ls180.v:181669$13467_Y - connect \$121 $and$issuer_ls180.v:181670$13468_Y - connect \$123 $lt$issuer_ls180.v:181671$13469_Y - connect \$125 $and$issuer_ls180.v:181672$13470_Y - connect \$127 $lt$issuer_ls180.v:181673$13471_Y - connect \$12 $eq$issuer_ls180.v:181674$13472_Y - connect \$129 $and$issuer_ls180.v:181675$13473_Y - connect \$131 $lt$issuer_ls180.v:181676$13474_Y - connect \$133 $and$issuer_ls180.v:181677$13475_Y - connect \$135 $lt$issuer_ls180.v:181678$13476_Y - connect \$137 $and$issuer_ls180.v:181679$13477_Y - connect \$11 $ternary$issuer_ls180.v:181680$13478_Y - connect \$139 $lt$issuer_ls180.v:181681$13479_Y - connect \$141 $and$issuer_ls180.v:181682$13480_Y - connect \$143 $lt$issuer_ls180.v:181683$13481_Y - connect \$145 $and$issuer_ls180.v:181684$13482_Y - connect \$147 $lt$issuer_ls180.v:181685$13483_Y - connect \$149 $and$issuer_ls180.v:181686$13484_Y - connect \$151 $lt$issuer_ls180.v:181687$13485_Y - connect \$153 $and$issuer_ls180.v:181688$13486_Y - connect \$155 $lt$issuer_ls180.v:181689$13487_Y - connect \$157 $and$issuer_ls180.v:181690$13488_Y - connect \$159 $lt$issuer_ls180.v:181691$13489_Y - connect \$161 $and$issuer_ls180.v:181692$13490_Y - connect \$163 $lt$issuer_ls180.v:181693$13491_Y - connect \$165 $and$issuer_ls180.v:181694$13492_Y - connect \$167 $lt$issuer_ls180.v:181695$13493_Y - connect \$16 $eq$issuer_ls180.v:181696$13494_Y - connect \$169 $and$issuer_ls180.v:181697$13495_Y - connect \$171 $lt$issuer_ls180.v:181698$13496_Y - connect \$173 $and$issuer_ls180.v:181699$13497_Y - connect \$175 $lt$issuer_ls180.v:181700$13498_Y - connect \$177 $and$issuer_ls180.v:181701$13499_Y - connect \$15 $ternary$issuer_ls180.v:181702$13500_Y - connect \$179 $lt$issuer_ls180.v:181703$13501_Y - connect \$181 $and$issuer_ls180.v:181704$13502_Y - connect \$183 $lt$issuer_ls180.v:181705$13503_Y - connect \$185 $and$issuer_ls180.v:181706$13504_Y - connect \$187 $lt$issuer_ls180.v:181707$13505_Y - connect \$189 $and$issuer_ls180.v:181708$13506_Y - connect \$191 $lt$issuer_ls180.v:181709$13507_Y - connect \$193 $and$issuer_ls180.v:181710$13508_Y - connect \$195 $lt$issuer_ls180.v:181711$13509_Y - connect \$197 $and$issuer_ls180.v:181712$13510_Y - connect \$1 $eq$issuer_ls180.v:181713$13511_Y - connect \$199 $lt$issuer_ls180.v:181714$13512_Y - connect \$201 $and$issuer_ls180.v:181715$13513_Y - connect \$204 $eq$issuer_ls180.v:181716$13514_Y - connect \$203 $ternary$issuer_ls180.v:181717$13515_Y - connect \$20 $eq$issuer_ls180.v:181718$13516_Y - connect \$19 $ternary$issuer_ls180.v:181719$13517_Y - connect \$24 $eq$issuer_ls180.v:181720$13518_Y - connect \$23 $ternary$issuer_ls180.v:181721$13519_Y - connect \$28 $eq$issuer_ls180.v:181722$13520_Y - connect \$27 $ternary$issuer_ls180.v:181723$13521_Y - connect \$32 $eq$issuer_ls180.v:181724$13522_Y - connect \$31 $ternary$issuer_ls180.v:181725$13523_Y - connect \$36 $eq$issuer_ls180.v:181726$13524_Y - connect \$35 $ternary$issuer_ls180.v:181727$13525_Y - connect \$3 $eq$issuer_ls180.v:181728$13526_Y - connect \$40 $eq$issuer_ls180.v:181729$13527_Y - connect \$39 $ternary$issuer_ls180.v:181730$13528_Y - connect \$44 $eq$issuer_ls180.v:181731$13529_Y - connect \$43 $ternary$issuer_ls180.v:181732$13530_Y - connect \$48 $eq$issuer_ls180.v:181733$13531_Y - connect \$47 $ternary$issuer_ls180.v:181734$13532_Y - connect \$52 $eq$issuer_ls180.v:181735$13533_Y - connect \$51 $ternary$issuer_ls180.v:181736$13534_Y - connect \$56 $eq$issuer_ls180.v:181737$13535_Y - connect \$55 $ternary$issuer_ls180.v:181738$13536_Y - connect \$5 $and$issuer_ls180.v:181739$13537_Y - connect \$60 $eq$issuer_ls180.v:181740$13538_Y - connect \$59 $ternary$issuer_ls180.v:181741$13539_Y - connect \$64 $eq$issuer_ls180.v:181742$13540_Y - connect \$63 $ternary$issuer_ls180.v:181743$13541_Y - connect \$68 $eq$issuer_ls180.v:181744$13542_Y - connect \$67 $ternary$issuer_ls180.v:181745$13543_Y - connect \$71 $shr$issuer_ls180.v:181746$13544_Y [0] - connect \$73 $and$issuer_ls180.v:181747$13545_Y - connect \$75 $lt$issuer_ls180.v:181748$13546_Y - connect \$77 $and$issuer_ls180.v:181749$13547_Y - connect \$79 $lt$issuer_ls180.v:181750$13548_Y - connect \$81 $and$issuer_ls180.v:181751$13549_Y - connect \$83 $lt$issuer_ls180.v:181752$13550_Y - connect \$85 $and$issuer_ls180.v:181753$13551_Y - connect \$87 $lt$issuer_ls180.v:181754$13552_Y - connect \$8 $eq$issuer_ls180.v:181755$13553_Y - connect \$89 $and$issuer_ls180.v:181756$13554_Y - connect \$91 $lt$issuer_ls180.v:181757$13555_Y - connect \$93 $and$issuer_ls180.v:181758$13556_Y - connect \$95 $lt$issuer_ls180.v:181759$13557_Y - connect \$97 $and$issuer_ls180.v:181760$13558_Y + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ics_wb__ack$next[0:0]$2297 1'0 + case + assign $1\ics_wb__ack$next[0:0]$2297 \wb_valid + end + sync always + update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$2296 + end + connect \$7 $ternary$libresoc.v:50223$2050_Y + connect \$99 $lt$libresoc.v:50224$2051_Y + connect \$101 $and$libresoc.v:50225$2052_Y + connect \$103 $lt$libresoc.v:50226$2053_Y + connect \$105 $and$libresoc.v:50227$2054_Y + connect \$107 $lt$libresoc.v:50228$2055_Y + connect \$109 $and$libresoc.v:50229$2056_Y + connect \$111 $lt$libresoc.v:50230$2057_Y + connect \$113 $and$libresoc.v:50231$2058_Y + connect \$115 $lt$libresoc.v:50232$2059_Y + connect \$117 $and$libresoc.v:50233$2060_Y + connect \$119 $lt$libresoc.v:50234$2061_Y + connect \$121 $and$libresoc.v:50235$2062_Y + connect \$123 $lt$libresoc.v:50236$2063_Y + connect \$125 $and$libresoc.v:50237$2064_Y + connect \$127 $lt$libresoc.v:50238$2065_Y + connect \$12 $eq$libresoc.v:50239$2066_Y + connect \$129 $and$libresoc.v:50240$2067_Y + connect \$131 $lt$libresoc.v:50241$2068_Y + connect \$133 $and$libresoc.v:50242$2069_Y + connect \$135 $lt$libresoc.v:50243$2070_Y + connect \$137 $and$libresoc.v:50244$2071_Y + connect \$11 $ternary$libresoc.v:50245$2072_Y + connect \$139 $lt$libresoc.v:50246$2073_Y + connect \$141 $and$libresoc.v:50247$2074_Y + connect \$143 $lt$libresoc.v:50248$2075_Y + connect \$145 $and$libresoc.v:50249$2076_Y + connect \$147 $lt$libresoc.v:50250$2077_Y + connect \$149 $and$libresoc.v:50251$2078_Y + connect \$151 $lt$libresoc.v:50252$2079_Y + connect \$153 $and$libresoc.v:50253$2080_Y + connect \$155 $lt$libresoc.v:50254$2081_Y + connect \$157 $and$libresoc.v:50255$2082_Y + connect \$159 $lt$libresoc.v:50256$2083_Y + connect \$161 $and$libresoc.v:50257$2084_Y + connect \$163 $lt$libresoc.v:50258$2085_Y + connect \$165 $and$libresoc.v:50259$2086_Y + connect \$167 $lt$libresoc.v:50260$2087_Y + connect \$16 $eq$libresoc.v:50261$2088_Y + connect \$169 $and$libresoc.v:50262$2089_Y + connect \$171 $lt$libresoc.v:50263$2090_Y + connect \$173 $and$libresoc.v:50264$2091_Y + connect \$175 $lt$libresoc.v:50265$2092_Y + connect \$177 $and$libresoc.v:50266$2093_Y + connect \$15 $ternary$libresoc.v:50267$2094_Y + connect \$179 $lt$libresoc.v:50268$2095_Y + connect \$181 $and$libresoc.v:50269$2096_Y + connect \$183 $lt$libresoc.v:50270$2097_Y + connect \$185 $and$libresoc.v:50271$2098_Y + connect \$187 $lt$libresoc.v:50272$2099_Y + connect \$189 $and$libresoc.v:50273$2100_Y + connect \$191 $lt$libresoc.v:50274$2101_Y + connect \$193 $and$libresoc.v:50275$2102_Y + connect \$195 $lt$libresoc.v:50276$2103_Y + connect \$197 $and$libresoc.v:50277$2104_Y + connect \$1 $eq$libresoc.v:50278$2105_Y + connect \$199 $lt$libresoc.v:50279$2106_Y + connect \$201 $and$libresoc.v:50280$2107_Y + connect \$204 $eq$libresoc.v:50281$2108_Y + connect \$203 $ternary$libresoc.v:50282$2109_Y + connect \$20 $eq$libresoc.v:50283$2110_Y + connect \$19 $ternary$libresoc.v:50284$2111_Y + connect \$24 $eq$libresoc.v:50285$2112_Y + connect \$23 $ternary$libresoc.v:50286$2113_Y + connect \$28 $eq$libresoc.v:50287$2114_Y + connect \$27 $ternary$libresoc.v:50288$2115_Y + connect \$32 $eq$libresoc.v:50289$2116_Y + connect \$31 $ternary$libresoc.v:50290$2117_Y + connect \$36 $eq$libresoc.v:50291$2118_Y + connect \$35 $ternary$libresoc.v:50292$2119_Y + connect \$3 $eq$libresoc.v:50293$2120_Y + connect \$40 $eq$libresoc.v:50294$2121_Y + connect \$39 $ternary$libresoc.v:50295$2122_Y + connect \$44 $eq$libresoc.v:50296$2123_Y + connect \$43 $ternary$libresoc.v:50297$2124_Y + connect \$48 $eq$libresoc.v:50298$2125_Y + connect \$47 $ternary$libresoc.v:50299$2126_Y + connect \$52 $eq$libresoc.v:50300$2127_Y + connect \$51 $ternary$libresoc.v:50301$2128_Y + connect \$56 $eq$libresoc.v:50302$2129_Y + connect \$55 $ternary$libresoc.v:50303$2130_Y + connect \$5 $and$libresoc.v:50304$2131_Y + connect \$60 $eq$libresoc.v:50305$2132_Y + connect \$59 $ternary$libresoc.v:50306$2133_Y + connect \$64 $eq$libresoc.v:50307$2134_Y + connect \$63 $ternary$libresoc.v:50308$2135_Y + connect \$68 $eq$libresoc.v:50309$2136_Y + connect \$67 $ternary$libresoc.v:50310$2137_Y + connect \$71 $shr$libresoc.v:50311$2138_Y [0] + connect \$73 $and$libresoc.v:50312$2139_Y + connect \$75 $lt$libresoc.v:50313$2140_Y + connect \$77 $and$libresoc.v:50314$2141_Y + connect \$79 $lt$libresoc.v:50315$2142_Y + connect \$81 $and$libresoc.v:50316$2143_Y + connect \$83 $lt$libresoc.v:50317$2144_Y + connect \$85 $and$libresoc.v:50318$2145_Y + connect \$87 $lt$libresoc.v:50319$2146_Y + connect \$8 $eq$libresoc.v:50320$2147_Y + connect \$89 $and$libresoc.v:50321$2148_Y + connect \$91 $lt$libresoc.v:50322$2149_Y + connect \$93 $and$libresoc.v:50323$2150_Y + connect \$95 $lt$libresoc.v:50324$2151_Y + connect \$97 $and$libresoc.v:50325$2152_Y connect \icp_r_pri \$203 connect \icp_r_src \cur_idx15 connect \max_idx 4'0000 -- 2.30.2